./Ultimate.py --spec ../../sv-benchmarks/c/properties/termination.prp --file ../../sv-benchmarks/c/systemc/token_ring.05_false-unreach-call_false-termination.cil.c --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for termination Using default analysis Version aa418289 Calling Ultimate with: java -Dosgi.configuration.area=/tmp/vcloud-vcloud-master/worker/working_dir_dc28e54a-25be-4fa6-93e3-2eb7786d5d84/bin-2019/uautomizer/data/config -Xmx12G -Xms1G -jar /tmp/vcloud-vcloud-master/worker/working_dir_dc28e54a-25be-4fa6-93e3-2eb7786d5d84/bin-2019/uautomizer/plugins/org.eclipse.equinox.launcher_1.3.100.v20150511-1540.jar -data @noDefault -ultimatedata /tmp/vcloud-vcloud-master/worker/working_dir_dc28e54a-25be-4fa6-93e3-2eb7786d5d84/bin-2019/uautomizer/data -tc /tmp/vcloud-vcloud-master/worker/working_dir_dc28e54a-25be-4fa6-93e3-2eb7786d5d84/bin-2019/uautomizer/config/AutomizerTermination.xml -i ../../sv-benchmarks/c/systemc/token_ring.05_false-unreach-call_false-termination.cil.c -s /tmp/vcloud-vcloud-master/worker/working_dir_dc28e54a-25be-4fa6-93e3-2eb7786d5d84/bin-2019/uautomizer/config/svcomp-Termination-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud-vcloud-master/worker/working_dir_dc28e54a-25be-4fa6-93e3-2eb7786d5d84/bin-2019/uautomizer --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash 27d160802d278384ef6d8db395ef2d19702d5645 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Execution finished normally Writing output log to file Ultimate.log Writing human readable error path to file UltimateCounterExample.errorpath Result: FALSE(TERM) --- Real Ultimate output --- This is Ultimate 0.1.23-aa41828 [2018-11-23 00:23:52,562 INFO L170 SettingsManager]: Resetting all preferences to default values... [2018-11-23 00:23:52,564 INFO L174 SettingsManager]: Resetting UltimateCore preferences to default values [2018-11-23 00:23:52,572 INFO L177 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2018-11-23 00:23:52,573 INFO L174 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2018-11-23 00:23:52,573 INFO L174 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2018-11-23 00:23:52,574 INFO L174 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2018-11-23 00:23:52,575 INFO L174 SettingsManager]: Resetting LassoRanker preferences to default values [2018-11-23 00:23:52,577 INFO L174 SettingsManager]: Resetting Reaching Definitions preferences to default values [2018-11-23 00:23:52,577 INFO L174 SettingsManager]: Resetting SyntaxChecker preferences to default values [2018-11-23 00:23:52,578 INFO L177 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2018-11-23 00:23:52,578 INFO L174 SettingsManager]: Resetting LTL2Aut preferences to default values [2018-11-23 00:23:52,579 INFO L174 SettingsManager]: Resetting PEA to Boogie preferences to default values [2018-11-23 00:23:52,579 INFO L174 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2018-11-23 00:23:52,580 INFO L174 SettingsManager]: Resetting ChcToBoogie preferences to default values [2018-11-23 00:23:52,581 INFO L174 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2018-11-23 00:23:52,581 INFO L174 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2018-11-23 00:23:52,583 INFO L174 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2018-11-23 00:23:52,584 INFO L174 SettingsManager]: Resetting CodeCheck preferences to default values [2018-11-23 00:23:52,586 INFO L174 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2018-11-23 00:23:52,586 INFO L174 SettingsManager]: Resetting RCFGBuilder preferences to default values [2018-11-23 00:23:52,587 INFO L174 SettingsManager]: Resetting TraceAbstraction preferences to default values [2018-11-23 00:23:52,589 INFO L177 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2018-11-23 00:23:52,589 INFO L177 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2018-11-23 00:23:52,589 INFO L174 SettingsManager]: Resetting TreeAutomizer preferences to default values [2018-11-23 00:23:52,590 INFO L174 SettingsManager]: Resetting IcfgTransformer preferences to default values [2018-11-23 00:23:52,591 INFO L174 SettingsManager]: Resetting Boogie Printer preferences to default values [2018-11-23 00:23:52,591 INFO L174 SettingsManager]: Resetting ReqPrinter preferences to default values [2018-11-23 00:23:52,592 INFO L174 SettingsManager]: Resetting Witness Printer preferences to default values [2018-11-23 00:23:52,593 INFO L177 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2018-11-23 00:23:52,593 INFO L174 SettingsManager]: Resetting CDTParser preferences to default values [2018-11-23 00:23:52,593 INFO L177 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2018-11-23 00:23:52,594 INFO L177 SettingsManager]: ReqParser provides no preferences, ignoring... [2018-11-23 00:23:52,594 INFO L174 SettingsManager]: Resetting SmtParser preferences to default values [2018-11-23 00:23:52,594 INFO L174 SettingsManager]: Resetting Witness Parser preferences to default values [2018-11-23 00:23:52,595 INFO L181 SettingsManager]: Finished resetting all preferences to default values... [2018-11-23 00:23:52,595 INFO L98 SettingsManager]: Beginning loading settings from /tmp/vcloud-vcloud-master/worker/working_dir_dc28e54a-25be-4fa6-93e3-2eb7786d5d84/bin-2019/uautomizer/config/svcomp-Termination-32bit-Automizer_Default.epf [2018-11-23 00:23:52,606 INFO L110 SettingsManager]: Loading preferences was successful [2018-11-23 00:23:52,606 INFO L112 SettingsManager]: Preferences different from defaults after loading the file: [2018-11-23 00:23:52,607 INFO L131 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2018-11-23 00:23:52,608 INFO L133 SettingsManager]: * Create parallel compositions if possible=false [2018-11-23 00:23:52,608 INFO L133 SettingsManager]: * Use SBE=true [2018-11-23 00:23:52,608 INFO L131 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: [2018-11-23 00:23:52,608 INFO L133 SettingsManager]: * NCSB implementation=INTSET_LAZY3 [2018-11-23 00:23:52,608 INFO L133 SettingsManager]: * Use old map elimination=false [2018-11-23 00:23:52,608 INFO L133 SettingsManager]: * Use external solver (rank synthesis)=false [2018-11-23 00:23:52,608 INFO L133 SettingsManager]: * Use only trivial implications for array writes=true [2018-11-23 00:23:52,609 INFO L133 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES [2018-11-23 00:23:52,609 INFO L131 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2018-11-23 00:23:52,609 INFO L133 SettingsManager]: * sizeof long=4 [2018-11-23 00:23:52,609 INFO L133 SettingsManager]: * Check unreachability of error function in SV-COMP mode=false [2018-11-23 00:23:52,609 INFO L133 SettingsManager]: * Overapproximate operations on floating types=true [2018-11-23 00:23:52,609 INFO L133 SettingsManager]: * sizeof POINTER=4 [2018-11-23 00:23:52,609 INFO L133 SettingsManager]: * Check division by zero=IGNORE [2018-11-23 00:23:52,610 INFO L133 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME [2018-11-23 00:23:52,610 INFO L133 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME [2018-11-23 00:23:52,610 INFO L133 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME [2018-11-23 00:23:52,610 INFO L133 SettingsManager]: * sizeof long double=12 [2018-11-23 00:23:52,610 INFO L133 SettingsManager]: * Check if freed pointer was valid=false [2018-11-23 00:23:52,610 INFO L133 SettingsManager]: * Assume nondeterminstic values are in range=false [2018-11-23 00:23:52,610 INFO L133 SettingsManager]: * Use constant arrays=true [2018-11-23 00:23:52,611 INFO L133 SettingsManager]: * Pointer base address is valid at dereference=ASSUME [2018-11-23 00:23:52,611 INFO L131 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2018-11-23 00:23:52,611 INFO L133 SettingsManager]: * Size of a code block=SequenceOfStatements [2018-11-23 00:23:52,611 INFO L133 SettingsManager]: * To the following directory=/home/matthias/ultimate/dump [2018-11-23 00:23:52,611 INFO L131 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2018-11-23 00:23:52,611 INFO L133 SettingsManager]: * Trace refinement strategy=CAMEL [2018-11-23 00:23:52,612 INFO L133 SettingsManager]: * Dump automata to the following directory=/home/matthias/ultimate/dump/auto [2018-11-23 00:23:52,612 INFO L131 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2018-11-23 00:23:52,612 INFO L133 SettingsManager]: * TransformationType=MODULO_NEIGHBOR Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud-vcloud-master/worker/working_dir_dc28e54a-25be-4fa6-93e3-2eb7786d5d84/bin-2019/uautomizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> 27d160802d278384ef6d8db395ef2d19702d5645 [2018-11-23 00:23:52,636 INFO L81 nceAwareModelManager]: Repository-Root is: /tmp [2018-11-23 00:23:52,645 INFO L258 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2018-11-23 00:23:52,648 INFO L214 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2018-11-23 00:23:52,649 INFO L271 PluginConnector]: Initializing CDTParser... [2018-11-23 00:23:52,649 INFO L276 PluginConnector]: CDTParser initialized [2018-11-23 00:23:52,650 INFO L418 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud-vcloud-master/worker/working_dir_dc28e54a-25be-4fa6-93e3-2eb7786d5d84/bin-2019/uautomizer/../../sv-benchmarks/c/systemc/token_ring.05_false-unreach-call_false-termination.cil.c [2018-11-23 00:23:52,694 INFO L221 CDTParser]: Created temporary CDT project at /tmp/vcloud-vcloud-master/worker/working_dir_dc28e54a-25be-4fa6-93e3-2eb7786d5d84/bin-2019/uautomizer/data/0d4277a9e/d22925a154d1480aa0c50c3e817a5bf7/FLAG008be4198 [2018-11-23 00:23:53,056 INFO L307 CDTParser]: Found 1 translation units. [2018-11-23 00:23:53,057 INFO L161 CDTParser]: Scanning /tmp/vcloud-vcloud-master/worker/working_dir_dc28e54a-25be-4fa6-93e3-2eb7786d5d84/sv-benchmarks/c/systemc/token_ring.05_false-unreach-call_false-termination.cil.c [2018-11-23 00:23:53,066 INFO L355 CDTParser]: About to delete temporary CDT project at /tmp/vcloud-vcloud-master/worker/working_dir_dc28e54a-25be-4fa6-93e3-2eb7786d5d84/bin-2019/uautomizer/data/0d4277a9e/d22925a154d1480aa0c50c3e817a5bf7/FLAG008be4198 [2018-11-23 00:23:53,452 INFO L363 CDTParser]: Successfully deleted /tmp/vcloud-vcloud-master/worker/working_dir_dc28e54a-25be-4fa6-93e3-2eb7786d5d84/bin-2019/uautomizer/data/0d4277a9e/d22925a154d1480aa0c50c3e817a5bf7 [2018-11-23 00:23:53,454 INFO L296 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2018-11-23 00:23:53,455 INFO L131 ToolchainWalker]: Walking toolchain with 6 elements. [2018-11-23 00:23:53,456 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2018-11-23 00:23:53,456 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2018-11-23 00:23:53,459 INFO L276 PluginConnector]: CACSL2BoogieTranslator initialized [2018-11-23 00:23:53,459 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 23.11 12:23:53" (1/1) ... [2018-11-23 00:23:53,461 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@1538edb and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 12:23:53, skipping insertion in model container [2018-11-23 00:23:53,462 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 23.11 12:23:53" (1/1) ... [2018-11-23 00:23:53,468 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2018-11-23 00:23:53,498 INFO L176 MainTranslator]: Built tables and reachable declarations [2018-11-23 00:23:53,670 INFO L201 PostProcessor]: Analyzing one entry point: main [2018-11-23 00:23:53,674 INFO L191 MainTranslator]: Completed pre-run [2018-11-23 00:23:53,718 INFO L201 PostProcessor]: Analyzing one entry point: main [2018-11-23 00:23:53,731 INFO L195 MainTranslator]: Completed translation [2018-11-23 00:23:53,731 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 12:23:53 WrapperNode [2018-11-23 00:23:53,731 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2018-11-23 00:23:53,732 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2018-11-23 00:23:53,732 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2018-11-23 00:23:53,732 INFO L276 PluginConnector]: Boogie Procedure Inliner initialized [2018-11-23 00:23:53,737 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 12:23:53" (1/1) ... [2018-11-23 00:23:53,742 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 12:23:53" (1/1) ... [2018-11-23 00:23:53,821 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2018-11-23 00:23:53,821 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2018-11-23 00:23:53,821 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2018-11-23 00:23:53,821 INFO L276 PluginConnector]: Boogie Preprocessor initialized [2018-11-23 00:23:53,830 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 12:23:53" (1/1) ... [2018-11-23 00:23:53,830 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 12:23:53" (1/1) ... [2018-11-23 00:23:53,833 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 12:23:53" (1/1) ... [2018-11-23 00:23:53,833 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 12:23:53" (1/1) ... [2018-11-23 00:23:53,845 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 12:23:53" (1/1) ... [2018-11-23 00:23:53,859 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 12:23:53" (1/1) ... [2018-11-23 00:23:53,862 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 12:23:53" (1/1) ... [2018-11-23 00:23:53,866 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2018-11-23 00:23:53,867 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2018-11-23 00:23:53,867 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2018-11-23 00:23:53,867 INFO L276 PluginConnector]: RCFGBuilder initialized [2018-11-23 00:23:53,868 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 12:23:53" (1/1) ... No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_dc28e54a-25be-4fa6-93e3-2eb7786d5d84/bin-2019/uautomizer/z3 Starting monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2018-11-23 00:23:53,914 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2018-11-23 00:23:53,914 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2018-11-23 00:23:54,799 INFO L275 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2018-11-23 00:23:54,799 INFO L280 CfgBuilder]: Removed 198 assue(true) statements. [2018-11-23 00:23:54,799 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 23.11 12:23:54 BoogieIcfgContainer [2018-11-23 00:23:54,800 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2018-11-23 00:23:54,800 INFO L113 PluginConnector]: ------------------------BuchiAutomizer---------------------------- [2018-11-23 00:23:54,800 INFO L271 PluginConnector]: Initializing BuchiAutomizer... [2018-11-23 00:23:54,803 INFO L276 PluginConnector]: BuchiAutomizer initialized [2018-11-23 00:23:54,804 INFO L102 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2018-11-23 00:23:54,804 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 23.11 12:23:53" (1/3) ... [2018-11-23 00:23:54,805 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@2f13babe and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 23.11 12:23:54, skipping insertion in model container [2018-11-23 00:23:54,805 INFO L102 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2018-11-23 00:23:54,805 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 12:23:53" (2/3) ... [2018-11-23 00:23:54,806 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@2f13babe and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 23.11 12:23:54, skipping insertion in model container [2018-11-23 00:23:54,806 INFO L102 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2018-11-23 00:23:54,806 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 23.11 12:23:54" (3/3) ... [2018-11-23 00:23:54,808 INFO L375 chiAutomizerObserver]: Analyzing ICFG token_ring.05_false-unreach-call_false-termination.cil.c [2018-11-23 00:23:54,841 INFO L133 ementStrategyFactory]: Using default assertion order modulation [2018-11-23 00:23:54,841 INFO L374 BuchiCegarLoop]: Interprodecural is true [2018-11-23 00:23:54,842 INFO L375 BuchiCegarLoop]: Hoare is false [2018-11-23 00:23:54,842 INFO L376 BuchiCegarLoop]: Compute interpolants for ForwardPredicates [2018-11-23 00:23:54,842 INFO L377 BuchiCegarLoop]: Backedges is STRAIGHT_LINE [2018-11-23 00:23:54,842 INFO L378 BuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2018-11-23 00:23:54,842 INFO L379 BuchiCegarLoop]: Difference is false [2018-11-23 00:23:54,842 INFO L380 BuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2018-11-23 00:23:54,842 INFO L383 BuchiCegarLoop]: ======== Iteration 0==of CEGAR loop == BuchiCegarLoop======== [2018-11-23 00:23:54,859 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 538 states. [2018-11-23 00:23:54,887 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 459 [2018-11-23 00:23:54,888 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-23 00:23:54,888 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-23 00:23:54,895 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 00:23:54,895 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 00:23:54,896 INFO L442 BuchiCegarLoop]: ======== Iteration 1============ [2018-11-23 00:23:54,896 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 538 states. [2018-11-23 00:23:54,905 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 459 [2018-11-23 00:23:54,906 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-23 00:23:54,906 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-23 00:23:54,908 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 00:23:54,908 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 00:23:54,916 INFO L794 eck$LassoCheckResult]: Stem: 341#ULTIMATE.startENTRYtrue ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 279#L-1true havoc main_#res;havoc main_~__retres1~7;havoc main_~__retres1~7;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 187#L893true havoc start_simulation_#t~ret16, start_simulation_#t~ret17, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 160#L409true assume !(1 == ~m_i~0);~m_st~0 := 2; 454#L416-1true assume 1 == ~t1_i~0;~t1_st~0 := 0; 212#L421-1true assume !(1 == ~t2_i~0);~t2_st~0 := 2; 497#L426-1true assume !(1 == ~t3_i~0);~t3_st~0 := 2; 161#L431-1true assume !(1 == ~t4_i~0);~t4_st~0 := 2; 409#L436-1true assume !(1 == ~t5_i~0);~t5_st~0 := 2; 191#L441-1true assume !(0 == ~M_E~0); 427#L601-1true assume !(0 == ~T1_E~0); 194#L606-1true assume !(0 == ~T2_E~0); 90#L611-1true assume 0 == ~T3_E~0;~T3_E~0 := 1; 361#L616-1true assume !(0 == ~T4_E~0); 8#L621-1true assume !(0 == ~T5_E~0); 305#L626-1true assume !(0 == ~E_M~0); 65#L631-1true assume !(0 == ~E_1~0); 460#L636-1true assume !(0 == ~E_2~0); 236#L641-1true assume !(0 == ~E_3~0); 538#L646-1true assume !(0 == ~E_4~0); 185#L651-1true assume 0 == ~E_5~0;~E_5~0 := 1; 438#L656-1true havoc activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 484#L294true assume 1 == ~m_pc~0; 317#L295true assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 509#L305true is_master_triggered_#res := is_master_triggered_~__retres1~0; 323#L306true activate_threads_#t~ret9 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 531#L745true assume !(0 != activate_threads_~tmp~1); 534#L745-2true havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 125#L313true assume !(1 == ~t1_pc~0); 134#L313-2true is_transmit1_triggered_~__retres1~1 := 0; 123#L324true is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 85#L325true activate_threads_#t~ret10 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 16#L753true assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 19#L753-2true havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 166#L332true assume 1 == ~t2_pc~0; 215#L333true assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 165#L343true is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 214#L344true activate_threads_#t~ret11 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 181#L761true assume !(0 != activate_threads_~tmp___1~0); 182#L761-2true havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 300#L351true assume !(1 == ~t3_pc~0); 284#L351-2true is_transmit3_triggered_~__retres1~3 := 0; 299#L362true is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 355#L363true activate_threads_#t~ret12 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 309#L769true assume !(0 != activate_threads_~tmp___2~0); 310#L769-2true havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 415#L370true assume 1 == ~t4_pc~0; 500#L371true assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 412#L381true is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 498#L382true activate_threads_#t~ret13 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 434#L777true assume !(0 != activate_threads_~tmp___3~0); 435#L777-2true havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 58#L389true assume !(1 == ~t5_pc~0); 38#L389-2true is_transmit5_triggered_~__retres1~5 := 0; 56#L400true is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 151#L401true activate_threads_#t~ret14 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 69#L785true assume !(0 != activate_threads_~tmp___4~0); 71#L785-2true assume !(1 == ~M_E~0); 457#L669-1true assume !(1 == ~T1_E~0); 235#L674-1true assume !(1 == ~T2_E~0); 535#L679-1true assume !(1 == ~T3_E~0); 184#L684-1true assume !(1 == ~T4_E~0); 437#L689-1true assume 1 == ~T5_E~0;~T5_E~0 := 2; 331#L694-1true assume !(1 == ~E_M~0); 102#L699-1true assume !(1 == ~E_1~0); 372#L704-1true assume !(1 == ~E_2~0); 3#L709-1true assume !(1 == ~E_3~0); 301#L714-1true assume !(1 == ~E_4~0); 61#L719-1true assume !(1 == ~E_5~0); 107#L930-1true [2018-11-23 00:23:54,917 INFO L796 eck$LassoCheckResult]: Loop: 107#L930-1true assume !false; 439#L931true start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret2, eval_#t~nondet3, eval_~tmp_ndt_1~0, eval_#t~nondet4, eval_~tmp_ndt_2~0, eval_#t~nondet5, eval_~tmp_ndt_3~0, eval_#t~nondet6, eval_~tmp_ndt_4~0, eval_#t~nondet7, eval_~tmp_ndt_5~0, eval_#t~nondet8, eval_~tmp_ndt_6~0, eval_~tmp~0;havoc eval_~tmp~0; 67#L576true assume !true; 540#L591true start_simulation_~kernel_st~0 := 2; 163#L409-1true start_simulation_~kernel_st~0 := 3; 429#L601-2true assume 0 == ~M_E~0;~M_E~0 := 1; 432#L601-4true assume !(0 == ~T1_E~0); 197#L606-3true assume 0 == ~T2_E~0;~T2_E~0 := 1; 95#L611-3true assume 0 == ~T3_E~0;~T3_E~0 := 1; 363#L616-3true assume 0 == ~T4_E~0;~T4_E~0 := 1; 12#L621-3true assume 0 == ~T5_E~0;~T5_E~0 := 1; 307#L626-3true assume 0 == ~E_M~0;~E_M~0 := 1; 50#L631-3true assume 0 == ~E_1~0;~E_1~0 := 1; 451#L636-3true assume 0 == ~E_2~0;~E_2~0 := 1; 224#L641-3true assume !(0 == ~E_3~0); 524#L646-3true assume 0 == ~E_4~0;~E_4~0 := 1; 175#L651-3true assume 0 == ~E_5~0;~E_5~0 := 1; 428#L656-3true havoc activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 452#L294-21true assume !(1 == ~m_pc~0); 449#L294-23true is_master_triggered_~__retres1~0 := 0; 495#L305-7true is_master_triggered_#res := is_master_triggered_~__retres1~0; 319#L306-7true activate_threads_#t~ret9 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 469#L745-21true assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 472#L745-23true havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 88#L313-21true assume !(1 == ~t1_pc~0); 91#L313-23true is_transmit1_triggered_~__retres1~1 := 0; 116#L324-7true is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 444#L325-7true activate_threads_#t~ret10 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 118#L753-21true assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 122#L753-23true havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 234#L332-21true assume 1 == ~t2_pc~0; 209#L333-7true assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 266#L343-7true is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 208#L344-7true activate_threads_#t~ret11 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 246#L761-21true assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 248#L761-23true havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 371#L351-21true assume !(1 == ~t3_pc~0); 359#L351-23true is_transmit3_triggered_~__retres1~3 := 0; 272#L362-7true is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 333#L363-7true activate_threads_#t~ret12 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 276#L769-21true assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 278#L769-23true havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 533#L370-21true assume !(1 == ~t4_pc~0); 537#L370-23true is_transmit4_triggered_~__retres1~4 := 0; 401#L381-7true is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 488#L382-7true activate_threads_#t~ret13 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 387#L777-21true assume !(0 != activate_threads_~tmp___3~0); 389#L777-23true havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 18#L389-21true assume 1 == ~t5_pc~0; 146#L390-7true assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 29#L400-7true is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 143#L401-7true activate_threads_#t~ret14 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 34#L785-21true assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 36#L785-23true assume 1 == ~M_E~0;~M_E~0 := 2; 463#L669-3true assume 1 == ~T1_E~0;~T1_E~0 := 2; 238#L674-3true assume 1 == ~T2_E~0;~T2_E~0 := 2; 523#L679-3true assume !(1 == ~T3_E~0); 173#L684-3true assume 1 == ~T4_E~0;~T4_E~0 := 2; 424#L689-3true assume 1 == ~T5_E~0;~T5_E~0 := 2; 193#L694-3true assume 1 == ~E_M~0;~E_M~0 := 2; 89#L699-3true assume 1 == ~E_1~0;~E_1~0 := 2; 360#L704-3true assume 1 == ~E_2~0;~E_2~0 := 2; 7#L709-3true assume 1 == ~E_3~0;~E_3~0 := 2; 303#L714-3true assume 1 == ~E_4~0;~E_4~0 := 2; 64#L719-3true assume !(1 == ~E_5~0); 459#L724-3true havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 231#L454-1true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 180#L486-1true exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 230#L487-1true start_simulation_#t~ret16 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret16;havoc start_simulation_#t~ret16; 255#L949true assume !(0 == start_simulation_~tmp~3); 239#L949-1true havoc stop_simulation_#res;havoc stop_simulation_#t~ret15, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 213#L454-2true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 159#L486-2true exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 232#L487-2true stop_simulation_#t~ret15 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret15;havoc stop_simulation_#t~ret15; 186#L904true assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 476#L911true stop_simulation_#res := stop_simulation_~__retres2~0; 311#L912true start_simulation_#t~ret17 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret17;havoc start_simulation_#t~ret17; 23#L962true assume !(0 != start_simulation_~tmp___0~1); 107#L930-1true [2018-11-23 00:23:54,921 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 00:23:54,921 INFO L82 PathProgramCache]: Analyzing trace with hash -81461004, now seen corresponding path program 1 times [2018-11-23 00:23:54,922 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 00:23:54,923 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 00:23:54,959 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 00:23:54,959 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 00:23:54,959 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 00:23:54,987 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 00:23:55,030 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 00:23:55,032 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 00:23:55,032 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-23 00:23:55,035 INFO L799 eck$LassoCheckResult]: stem already infeasible [2018-11-23 00:23:55,035 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 00:23:55,035 INFO L82 PathProgramCache]: Analyzing trace with hash 821686751, now seen corresponding path program 1 times [2018-11-23 00:23:55,036 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 00:23:55,036 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 00:23:55,036 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 00:23:55,037 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 00:23:55,037 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 00:23:55,040 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 00:23:55,054 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 00:23:55,055 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 00:23:55,055 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2018-11-23 00:23:55,057 INFO L811 eck$LassoCheckResult]: loop already infeasible [2018-11-23 00:23:55,071 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-23 00:23:55,071 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-23 00:23:55,073 INFO L87 Difference]: Start difference. First operand 538 states. Second operand 3 states. [2018-11-23 00:23:55,110 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 00:23:55,110 INFO L93 Difference]: Finished difference Result 538 states and 814 transitions. [2018-11-23 00:23:55,111 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-23 00:23:55,113 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 538 states and 814 transitions. [2018-11-23 00:23:55,118 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 457 [2018-11-23 00:23:55,126 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 538 states to 532 states and 808 transitions. [2018-11-23 00:23:55,127 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 532 [2018-11-23 00:23:55,128 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 532 [2018-11-23 00:23:55,129 INFO L73 IsDeterministic]: Start isDeterministic. Operand 532 states and 808 transitions. [2018-11-23 00:23:55,131 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-23 00:23:55,132 INFO L705 BuchiCegarLoop]: Abstraction has 532 states and 808 transitions. [2018-11-23 00:23:55,149 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 532 states and 808 transitions. [2018-11-23 00:23:55,173 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 532 to 532. [2018-11-23 00:23:55,174 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 532 states. [2018-11-23 00:23:55,175 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 532 states to 532 states and 808 transitions. [2018-11-23 00:23:55,177 INFO L728 BuchiCegarLoop]: Abstraction has 532 states and 808 transitions. [2018-11-23 00:23:55,177 INFO L608 BuchiCegarLoop]: Abstraction has 532 states and 808 transitions. [2018-11-23 00:23:55,177 INFO L442 BuchiCegarLoop]: ======== Iteration 2============ [2018-11-23 00:23:55,177 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 532 states and 808 transitions. [2018-11-23 00:23:55,180 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 457 [2018-11-23 00:23:55,180 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-23 00:23:55,180 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-23 00:23:55,182 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 00:23:55,182 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 00:23:55,185 INFO L794 eck$LassoCheckResult]: Stem: 1530#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 1436#L-1 havoc main_#res;havoc main_~__retres1~7;havoc main_~__retres1~7;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 1339#L893 havoc start_simulation_#t~ret16, start_simulation_#t~ret17, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 1295#L409 assume 1 == ~m_i~0;~m_st~0 := 0; 1296#L416-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1382#L421-1 assume !(1 == ~t2_i~0);~t2_st~0 := 2; 1383#L426-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 1297#L431-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 1298#L436-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 1346#L441-1 assume !(0 == ~M_E~0); 1347#L601-1 assume !(0 == ~T1_E~0); 1349#L606-1 assume !(0 == ~T2_E~0); 1243#L611-1 assume 0 == ~T3_E~0;~T3_E~0 := 1; 1244#L616-1 assume !(0 == ~T4_E~0); 1096#L621-1 assume !(0 == ~T5_E~0); 1097#L626-1 assume !(0 == ~E_M~0); 1192#L631-1 assume !(0 == ~E_1~0); 1193#L636-1 assume !(0 == ~E_2~0); 1404#L641-1 assume !(0 == ~E_3~0); 1405#L646-1 assume !(0 == ~E_4~0); 1335#L651-1 assume 0 == ~E_5~0;~E_5~0 := 1; 1336#L656-1 havoc activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 1602#L294 assume 1 == ~m_pc~0; 1487#L295 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 1488#L305 is_master_triggered_#res := is_master_triggered_~__retres1~0; 1502#L306 activate_threads_#t~ret9 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 1503#L745 assume !(0 != activate_threads_~tmp~1); 1616#L745-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 1282#L313 assume !(1 == ~t1_pc~0); 1237#L313-2 is_transmit1_triggered_~__retres1~1 := 0; 1236#L324 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 1233#L325 activate_threads_#t~ret10 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 1111#L753 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 1112#L753-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 1116#L332 assume 1 == ~t2_pc~0; 1307#L333 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 1305#L343 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 1306#L344 activate_threads_#t~ret11 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 1329#L761 assume !(0 != activate_threads_~tmp___1~0); 1330#L761-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 1331#L351 assume !(1 == ~t3_pc~0); 1442#L351-2 is_transmit3_triggered_~__retres1~3 := 0; 1443#L362 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 1465#L363 activate_threads_#t~ret12 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 1471#L769 assume !(0 != activate_threads_~tmp___2~0); 1472#L769-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 1473#L370 assume 1 == ~t4_pc~0; 1586#L371 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 1581#L381 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 1582#L382 activate_threads_#t~ret13 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 1599#L777 assume !(0 != activate_threads_~tmp___3~0); 1600#L777-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 1182#L389 assume !(1 == ~t5_pc~0); 1148#L389-2 is_transmit5_triggered_~__retres1~5 := 0; 1149#L400 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 1181#L401 activate_threads_#t~ret14 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 1201#L785 assume !(0 != activate_threads_~tmp___4~0); 1202#L785-2 assume !(1 == ~M_E~0); 1203#L669-1 assume !(1 == ~T1_E~0); 1402#L674-1 assume !(1 == ~T2_E~0); 1403#L679-1 assume !(1 == ~T3_E~0); 1333#L684-1 assume !(1 == ~T4_E~0); 1334#L689-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 1522#L694-1 assume !(1 == ~E_M~0); 1265#L699-1 assume !(1 == ~E_1~0); 1266#L704-1 assume !(1 == ~E_2~0); 1085#L709-1 assume !(1 == ~E_3~0); 1086#L714-1 assume !(1 == ~E_4~0); 1186#L719-1 assume !(1 == ~E_5~0); 1125#L930-1 [2018-11-23 00:23:55,186 INFO L796 eck$LassoCheckResult]: Loop: 1125#L930-1 assume !false; 1271#L931 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret2, eval_#t~nondet3, eval_~tmp_ndt_1~0, eval_#t~nondet4, eval_~tmp_ndt_2~0, eval_#t~nondet5, eval_~tmp_ndt_3~0, eval_#t~nondet6, eval_~tmp_ndt_4~0, eval_#t~nondet7, eval_~tmp_ndt_5~0, eval_#t~nondet8, eval_~tmp_ndt_6~0, eval_~tmp~0;havoc eval_~tmp~0; 1195#L576 assume !false; 1196#L497 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 1324#L454 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 1173#L486 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 1326#L487 eval_#t~ret2 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret2;havoc eval_#t~ret2; 1256#L501 assume !(0 != eval_~tmp~0); 1257#L591 start_simulation_~kernel_st~0 := 2; 1301#L409-1 start_simulation_~kernel_st~0 := 3; 1302#L601-2 assume 0 == ~M_E~0;~M_E~0 := 1; 1597#L601-4 assume !(0 == ~T1_E~0); 1352#L606-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 1254#L611-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 1255#L616-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 1102#L621-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 1103#L626-3 assume 0 == ~E_M~0;~E_M~0 := 1; 1166#L631-3 assume 0 == ~E_1~0;~E_1~0 := 1; 1167#L636-3 assume 0 == ~E_2~0;~E_2~0 := 1; 1395#L641-3 assume !(0 == ~E_3~0); 1396#L646-3 assume 0 == ~E_4~0;~E_4~0 := 1; 1322#L651-3 assume 0 == ~E_5~0;~E_5~0 := 1; 1323#L656-3 havoc activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 1596#L294-21 assume 1 == ~m_pc~0; 1499#L295-7 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 1500#L305-7 is_master_triggered_#res := is_master_triggered_~__retres1~0; 1492#L306-7 activate_threads_#t~ret9 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 1493#L745-21 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 1603#L745-23 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 1238#L313-21 assume !(1 == ~t1_pc~0); 1239#L313-23 is_transmit1_triggered_~__retres1~1 := 0; 1245#L324-7 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 1276#L325-7 activate_threads_#t~ret10 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 1278#L753-21 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 1279#L753-23 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 1281#L332-21 assume !(1 == ~t2_pc~0); 1376#L332-23 is_transmit2_triggered_~__retres1~2 := 0; 1375#L343-7 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 1372#L344-7 activate_threads_#t~ret11 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 1373#L761-21 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 1411#L761-23 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 1412#L351-21 assume 1 == ~t3_pc~0; 1525#L352-7 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 1424#L362-7 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 1425#L363-7 activate_threads_#t~ret12 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 1431#L769-21 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 1432#L769-23 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 1435#L370-21 assume 1 == ~t4_pc~0; 1607#L371-7 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 1572#L381-7 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 1573#L382-7 activate_threads_#t~ret13 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 1553#L777-21 assume !(0 != activate_threads_~tmp___3~0); 1554#L777-23 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 1114#L389-21 assume !(1 == ~t5_pc~0); 1089#L389-23 is_transmit5_triggered_~__retres1~5 := 0; 1090#L400-7 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 1134#L401-7 activate_threads_#t~ret14 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 1143#L785-21 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 1144#L785-23 assume 1 == ~M_E~0;~M_E~0 := 2; 1146#L669-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 1406#L674-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 1407#L679-3 assume !(1 == ~T3_E~0); 1318#L684-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 1319#L689-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 1348#L694-3 assume 1 == ~E_M~0;~E_M~0 := 2; 1241#L699-3 assume 1 == ~E_1~0;~E_1~0 := 2; 1242#L704-3 assume 1 == ~E_2~0;~E_2~0 := 2; 1094#L709-3 assume 1 == ~E_3~0;~E_3~0 := 2; 1095#L714-3 assume 1 == ~E_4~0;~E_4~0 := 2; 1190#L719-3 assume !(1 == ~E_5~0); 1191#L724-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 1400#L454-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 1175#L486-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 1328#L487-1 start_simulation_#t~ret16 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret16;havoc start_simulation_#t~ret16; 1399#L949 assume !(0 == start_simulation_~tmp~3); 1408#L949-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret15, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 1384#L454-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 1179#L486-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 1294#L487-2 stop_simulation_#t~ret15 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret15;havoc stop_simulation_#t~ret15; 1337#L904 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 1338#L911 stop_simulation_#res := stop_simulation_~__retres2~0; 1474#L912 start_simulation_#t~ret17 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret17;havoc start_simulation_#t~ret17; 1124#L962 assume !(0 != start_simulation_~tmp___0~1); 1125#L930-1 [2018-11-23 00:23:55,186 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 00:23:55,186 INFO L82 PathProgramCache]: Analyzing trace with hash 650506422, now seen corresponding path program 1 times [2018-11-23 00:23:55,186 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 00:23:55,186 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 00:23:55,187 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 00:23:55,187 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 00:23:55,187 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 00:23:55,195 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 00:23:55,233 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 00:23:55,233 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 00:23:55,233 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-23 00:23:55,233 INFO L799 eck$LassoCheckResult]: stem already infeasible [2018-11-23 00:23:55,233 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 00:23:55,234 INFO L82 PathProgramCache]: Analyzing trace with hash 1943078903, now seen corresponding path program 1 times [2018-11-23 00:23:55,234 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 00:23:55,234 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 00:23:55,234 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 00:23:55,235 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 00:23:55,235 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 00:23:55,248 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 00:23:55,285 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 00:23:55,285 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 00:23:55,285 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-23 00:23:55,286 INFO L811 eck$LassoCheckResult]: loop already infeasible [2018-11-23 00:23:55,286 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-23 00:23:55,286 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-23 00:23:55,286 INFO L87 Difference]: Start difference. First operand 532 states and 808 transitions. cyclomatic complexity: 277 Second operand 3 states. [2018-11-23 00:23:55,298 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 00:23:55,298 INFO L93 Difference]: Finished difference Result 532 states and 807 transitions. [2018-11-23 00:23:55,299 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-23 00:23:55,300 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 532 states and 807 transitions. [2018-11-23 00:23:55,304 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 457 [2018-11-23 00:23:55,307 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 532 states to 532 states and 807 transitions. [2018-11-23 00:23:55,307 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 532 [2018-11-23 00:23:55,308 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 532 [2018-11-23 00:23:55,308 INFO L73 IsDeterministic]: Start isDeterministic. Operand 532 states and 807 transitions. [2018-11-23 00:23:55,309 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-23 00:23:55,310 INFO L705 BuchiCegarLoop]: Abstraction has 532 states and 807 transitions. [2018-11-23 00:23:55,310 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 532 states and 807 transitions. [2018-11-23 00:23:55,320 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 532 to 532. [2018-11-23 00:23:55,321 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 532 states. [2018-11-23 00:23:55,322 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 532 states to 532 states and 807 transitions. [2018-11-23 00:23:55,323 INFO L728 BuchiCegarLoop]: Abstraction has 532 states and 807 transitions. [2018-11-23 00:23:55,323 INFO L608 BuchiCegarLoop]: Abstraction has 532 states and 807 transitions. [2018-11-23 00:23:55,323 INFO L442 BuchiCegarLoop]: ======== Iteration 3============ [2018-11-23 00:23:55,323 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 532 states and 807 transitions. [2018-11-23 00:23:55,326 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 457 [2018-11-23 00:23:55,326 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-23 00:23:55,326 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-23 00:23:55,327 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 00:23:55,328 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 00:23:55,328 INFO L794 eck$LassoCheckResult]: Stem: 2601#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 2507#L-1 havoc main_#res;havoc main_~__retres1~7;havoc main_~__retres1~7;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 2410#L893 havoc start_simulation_#t~ret16, start_simulation_#t~ret17, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 2366#L409 assume 1 == ~m_i~0;~m_st~0 := 0; 2367#L416-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 2455#L421-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 2456#L426-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 2368#L431-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 2369#L436-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 2417#L441-1 assume !(0 == ~M_E~0); 2418#L601-1 assume !(0 == ~T1_E~0); 2420#L606-1 assume !(0 == ~T2_E~0); 2314#L611-1 assume 0 == ~T3_E~0;~T3_E~0 := 1; 2315#L616-1 assume !(0 == ~T4_E~0); 2167#L621-1 assume !(0 == ~T5_E~0); 2168#L626-1 assume !(0 == ~E_M~0); 2263#L631-1 assume !(0 == ~E_1~0); 2264#L636-1 assume !(0 == ~E_2~0); 2475#L641-1 assume !(0 == ~E_3~0); 2476#L646-1 assume !(0 == ~E_4~0); 2406#L651-1 assume 0 == ~E_5~0;~E_5~0 := 1; 2407#L656-1 havoc activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 2673#L294 assume 1 == ~m_pc~0; 2558#L295 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 2559#L305 is_master_triggered_#res := is_master_triggered_~__retres1~0; 2573#L306 activate_threads_#t~ret9 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 2574#L745 assume !(0 != activate_threads_~tmp~1); 2687#L745-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 2353#L313 assume !(1 == ~t1_pc~0); 2308#L313-2 is_transmit1_triggered_~__retres1~1 := 0; 2307#L324 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 2304#L325 activate_threads_#t~ret10 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 2182#L753 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 2183#L753-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 2187#L332 assume 1 == ~t2_pc~0; 2378#L333 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 2376#L343 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 2377#L344 activate_threads_#t~ret11 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 2400#L761 assume !(0 != activate_threads_~tmp___1~0); 2401#L761-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 2402#L351 assume !(1 == ~t3_pc~0); 2513#L351-2 is_transmit3_triggered_~__retres1~3 := 0; 2514#L362 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 2536#L363 activate_threads_#t~ret12 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 2542#L769 assume !(0 != activate_threads_~tmp___2~0); 2543#L769-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 2544#L370 assume 1 == ~t4_pc~0; 2657#L371 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 2652#L381 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 2653#L382 activate_threads_#t~ret13 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 2670#L777 assume !(0 != activate_threads_~tmp___3~0); 2671#L777-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 2254#L389 assume !(1 == ~t5_pc~0); 2221#L389-2 is_transmit5_triggered_~__retres1~5 := 0; 2222#L400 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 2252#L401 activate_threads_#t~ret14 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 2272#L785 assume !(0 != activate_threads_~tmp___4~0); 2273#L785-2 assume !(1 == ~M_E~0); 2274#L669-1 assume !(1 == ~T1_E~0); 2473#L674-1 assume !(1 == ~T2_E~0); 2474#L679-1 assume !(1 == ~T3_E~0); 2404#L684-1 assume !(1 == ~T4_E~0); 2405#L689-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 2593#L694-1 assume !(1 == ~E_M~0); 2336#L699-1 assume !(1 == ~E_1~0); 2337#L704-1 assume !(1 == ~E_2~0); 2156#L709-1 assume !(1 == ~E_3~0); 2157#L714-1 assume !(1 == ~E_4~0); 2257#L719-1 assume !(1 == ~E_5~0); 2196#L930-1 [2018-11-23 00:23:55,328 INFO L796 eck$LassoCheckResult]: Loop: 2196#L930-1 assume !false; 2342#L931 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret2, eval_#t~nondet3, eval_~tmp_ndt_1~0, eval_#t~nondet4, eval_~tmp_ndt_2~0, eval_#t~nondet5, eval_~tmp_ndt_3~0, eval_#t~nondet6, eval_~tmp_ndt_4~0, eval_#t~nondet7, eval_~tmp_ndt_5~0, eval_#t~nondet8, eval_~tmp_ndt_6~0, eval_~tmp~0;havoc eval_~tmp~0; 2266#L576 assume !false; 2267#L497 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 2395#L454 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 2244#L486 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 2397#L487 eval_#t~ret2 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret2;havoc eval_#t~ret2; 2327#L501 assume !(0 != eval_~tmp~0); 2328#L591 start_simulation_~kernel_st~0 := 2; 2372#L409-1 start_simulation_~kernel_st~0 := 3; 2373#L601-2 assume 0 == ~M_E~0;~M_E~0 := 1; 2668#L601-4 assume !(0 == ~T1_E~0); 2423#L606-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 2325#L611-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 2326#L616-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 2173#L621-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 2174#L626-3 assume 0 == ~E_M~0;~E_M~0 := 1; 2237#L631-3 assume 0 == ~E_1~0;~E_1~0 := 1; 2238#L636-3 assume 0 == ~E_2~0;~E_2~0 := 1; 2466#L641-3 assume !(0 == ~E_3~0); 2467#L646-3 assume 0 == ~E_4~0;~E_4~0 := 1; 2393#L651-3 assume 0 == ~E_5~0;~E_5~0 := 1; 2394#L656-3 havoc activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 2667#L294-21 assume 1 == ~m_pc~0; 2570#L295-7 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 2571#L305-7 is_master_triggered_#res := is_master_triggered_~__retres1~0; 2563#L306-7 activate_threads_#t~ret9 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 2564#L745-21 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 2674#L745-23 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 2309#L313-21 assume !(1 == ~t1_pc~0); 2310#L313-23 is_transmit1_triggered_~__retres1~1 := 0; 2316#L324-7 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 2347#L325-7 activate_threads_#t~ret10 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 2349#L753-21 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 2350#L753-23 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 2352#L332-21 assume 1 == ~t2_pc~0; 2445#L333-7 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 2446#L343-7 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 2443#L344-7 activate_threads_#t~ret11 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 2444#L761-21 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 2482#L761-23 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 2483#L351-21 assume 1 == ~t3_pc~0; 2596#L352-7 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 2495#L362-7 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 2496#L363-7 activate_threads_#t~ret12 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 2502#L769-21 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 2503#L769-23 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 2506#L370-21 assume 1 == ~t4_pc~0; 2678#L371-7 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 2643#L381-7 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 2644#L382-7 activate_threads_#t~ret13 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 2624#L777-21 assume !(0 != activate_threads_~tmp___3~0); 2625#L777-23 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 2185#L389-21 assume 1 == ~t5_pc~0; 2186#L390-7 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 2159#L400-7 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 2205#L401-7 activate_threads_#t~ret14 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 2211#L785-21 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 2212#L785-23 assume 1 == ~M_E~0;~M_E~0 := 2; 2216#L669-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 2477#L674-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 2478#L679-3 assume !(1 == ~T3_E~0); 2389#L684-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 2390#L689-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 2419#L694-3 assume 1 == ~E_M~0;~E_M~0 := 2; 2312#L699-3 assume 1 == ~E_1~0;~E_1~0 := 2; 2313#L704-3 assume 1 == ~E_2~0;~E_2~0 := 2; 2165#L709-3 assume 1 == ~E_3~0;~E_3~0 := 2; 2166#L714-3 assume 1 == ~E_4~0;~E_4~0 := 2; 2260#L719-3 assume !(1 == ~E_5~0); 2261#L724-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 2471#L454-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 2246#L486-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 2399#L487-1 start_simulation_#t~ret16 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret16;havoc start_simulation_#t~ret16; 2469#L949 assume !(0 == start_simulation_~tmp~3); 2479#L949-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret15, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 2453#L454-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 2250#L486-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 2365#L487-2 stop_simulation_#t~ret15 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret15;havoc stop_simulation_#t~ret15; 2408#L904 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 2409#L911 stop_simulation_#res := stop_simulation_~__retres2~0; 2545#L912 start_simulation_#t~ret17 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret17;havoc start_simulation_#t~ret17; 2195#L962 assume !(0 != start_simulation_~tmp___0~1); 2196#L930-1 [2018-11-23 00:23:55,328 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 00:23:55,329 INFO L82 PathProgramCache]: Analyzing trace with hash 704899320, now seen corresponding path program 1 times [2018-11-23 00:23:55,329 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 00:23:55,329 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 00:23:55,330 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 00:23:55,330 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 00:23:55,330 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 00:23:55,336 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 00:23:55,348 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 00:23:55,349 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 00:23:55,349 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-23 00:23:55,349 INFO L799 eck$LassoCheckResult]: stem already infeasible [2018-11-23 00:23:55,349 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 00:23:55,349 INFO L82 PathProgramCache]: Analyzing trace with hash 567388409, now seen corresponding path program 1 times [2018-11-23 00:23:55,349 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 00:23:55,349 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 00:23:55,350 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 00:23:55,350 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 00:23:55,350 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 00:23:55,357 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 00:23:55,395 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 00:23:55,395 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 00:23:55,395 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-23 00:23:55,395 INFO L811 eck$LassoCheckResult]: loop already infeasible [2018-11-23 00:23:55,396 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-23 00:23:55,396 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-23 00:23:55,396 INFO L87 Difference]: Start difference. First operand 532 states and 807 transitions. cyclomatic complexity: 276 Second operand 3 states. [2018-11-23 00:23:55,419 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 00:23:55,419 INFO L93 Difference]: Finished difference Result 532 states and 806 transitions. [2018-11-23 00:23:55,420 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-23 00:23:55,420 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 532 states and 806 transitions. [2018-11-23 00:23:55,423 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 457 [2018-11-23 00:23:55,426 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 532 states to 532 states and 806 transitions. [2018-11-23 00:23:55,426 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 532 [2018-11-23 00:23:55,427 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 532 [2018-11-23 00:23:55,427 INFO L73 IsDeterministic]: Start isDeterministic. Operand 532 states and 806 transitions. [2018-11-23 00:23:55,428 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-23 00:23:55,428 INFO L705 BuchiCegarLoop]: Abstraction has 532 states and 806 transitions. [2018-11-23 00:23:55,429 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 532 states and 806 transitions. [2018-11-23 00:23:55,436 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 532 to 532. [2018-11-23 00:23:55,436 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 532 states. [2018-11-23 00:23:55,437 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 532 states to 532 states and 806 transitions. [2018-11-23 00:23:55,438 INFO L728 BuchiCegarLoop]: Abstraction has 532 states and 806 transitions. [2018-11-23 00:23:55,438 INFO L608 BuchiCegarLoop]: Abstraction has 532 states and 806 transitions. [2018-11-23 00:23:55,438 INFO L442 BuchiCegarLoop]: ======== Iteration 4============ [2018-11-23 00:23:55,438 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 532 states and 806 transitions. [2018-11-23 00:23:55,440 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 457 [2018-11-23 00:23:55,441 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-23 00:23:55,441 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-23 00:23:55,442 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 00:23:55,442 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 00:23:55,442 INFO L794 eck$LassoCheckResult]: Stem: 3672#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 3578#L-1 havoc main_#res;havoc main_~__retres1~7;havoc main_~__retres1~7;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 3481#L893 havoc start_simulation_#t~ret16, start_simulation_#t~ret17, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 3437#L409 assume 1 == ~m_i~0;~m_st~0 := 0; 3438#L416-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 3526#L421-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 3527#L426-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 3439#L431-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 3440#L436-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 3488#L441-1 assume !(0 == ~M_E~0); 3489#L601-1 assume !(0 == ~T1_E~0); 3491#L606-1 assume !(0 == ~T2_E~0); 3385#L611-1 assume 0 == ~T3_E~0;~T3_E~0 := 1; 3386#L616-1 assume !(0 == ~T4_E~0); 3238#L621-1 assume !(0 == ~T5_E~0); 3239#L626-1 assume !(0 == ~E_M~0); 3334#L631-1 assume !(0 == ~E_1~0); 3335#L636-1 assume !(0 == ~E_2~0); 3546#L641-1 assume !(0 == ~E_3~0); 3547#L646-1 assume !(0 == ~E_4~0); 3477#L651-1 assume 0 == ~E_5~0;~E_5~0 := 1; 3478#L656-1 havoc activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 3744#L294 assume 1 == ~m_pc~0; 3629#L295 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 3630#L305 is_master_triggered_#res := is_master_triggered_~__retres1~0; 3644#L306 activate_threads_#t~ret9 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 3645#L745 assume !(0 != activate_threads_~tmp~1); 3758#L745-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 3424#L313 assume !(1 == ~t1_pc~0); 3379#L313-2 is_transmit1_triggered_~__retres1~1 := 0; 3378#L324 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 3375#L325 activate_threads_#t~ret10 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 3254#L753 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 3255#L753-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 3258#L332 assume 1 == ~t2_pc~0; 3449#L333 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 3447#L343 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 3448#L344 activate_threads_#t~ret11 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 3471#L761 assume !(0 != activate_threads_~tmp___1~0); 3472#L761-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 3473#L351 assume !(1 == ~t3_pc~0); 3584#L351-2 is_transmit3_triggered_~__retres1~3 := 0; 3585#L362 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 3607#L363 activate_threads_#t~ret12 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 3613#L769 assume !(0 != activate_threads_~tmp___2~0); 3614#L769-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 3615#L370 assume 1 == ~t4_pc~0; 3728#L371 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 3725#L381 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 3726#L382 activate_threads_#t~ret13 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 3741#L777 assume !(0 != activate_threads_~tmp___3~0); 3742#L777-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 3325#L389 assume !(1 == ~t5_pc~0); 3292#L389-2 is_transmit5_triggered_~__retres1~5 := 0; 3293#L400 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 3323#L401 activate_threads_#t~ret14 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 3343#L785 assume !(0 != activate_threads_~tmp___4~0); 3344#L785-2 assume !(1 == ~M_E~0); 3345#L669-1 assume !(1 == ~T1_E~0); 3544#L674-1 assume !(1 == ~T2_E~0); 3545#L679-1 assume !(1 == ~T3_E~0); 3475#L684-1 assume !(1 == ~T4_E~0); 3476#L689-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 3664#L694-1 assume !(1 == ~E_M~0); 3407#L699-1 assume !(1 == ~E_1~0); 3408#L704-1 assume !(1 == ~E_2~0); 3227#L709-1 assume !(1 == ~E_3~0); 3228#L714-1 assume !(1 == ~E_4~0); 3330#L719-1 assume !(1 == ~E_5~0); 3267#L930-1 [2018-11-23 00:23:55,443 INFO L796 eck$LassoCheckResult]: Loop: 3267#L930-1 assume !false; 3413#L931 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret2, eval_#t~nondet3, eval_~tmp_ndt_1~0, eval_#t~nondet4, eval_~tmp_ndt_2~0, eval_#t~nondet5, eval_~tmp_ndt_3~0, eval_#t~nondet6, eval_~tmp_ndt_4~0, eval_#t~nondet7, eval_~tmp_ndt_5~0, eval_#t~nondet8, eval_~tmp_ndt_6~0, eval_~tmp~0;havoc eval_~tmp~0; 3337#L576 assume !false; 3338#L497 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 3466#L454 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 3315#L486 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 3468#L487 eval_#t~ret2 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret2;havoc eval_#t~ret2; 3398#L501 assume !(0 != eval_~tmp~0); 3399#L591 start_simulation_~kernel_st~0 := 2; 3443#L409-1 start_simulation_~kernel_st~0 := 3; 3444#L601-2 assume 0 == ~M_E~0;~M_E~0 := 1; 3739#L601-4 assume !(0 == ~T1_E~0); 3494#L606-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 3396#L611-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 3397#L616-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 3244#L621-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 3245#L626-3 assume 0 == ~E_M~0;~E_M~0 := 1; 3308#L631-3 assume 0 == ~E_1~0;~E_1~0 := 1; 3309#L636-3 assume 0 == ~E_2~0;~E_2~0 := 1; 3537#L641-3 assume !(0 == ~E_3~0); 3538#L646-3 assume 0 == ~E_4~0;~E_4~0 := 1; 3464#L651-3 assume 0 == ~E_5~0;~E_5~0 := 1; 3465#L656-3 havoc activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 3738#L294-21 assume 1 == ~m_pc~0; 3641#L295-7 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 3642#L305-7 is_master_triggered_#res := is_master_triggered_~__retres1~0; 3634#L306-7 activate_threads_#t~ret9 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 3635#L745-21 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 3745#L745-23 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 3380#L313-21 assume !(1 == ~t1_pc~0); 3381#L313-23 is_transmit1_triggered_~__retres1~1 := 0; 3387#L324-7 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 3418#L325-7 activate_threads_#t~ret10 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 3420#L753-21 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 3421#L753-23 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 3423#L332-21 assume 1 == ~t2_pc~0; 3516#L333-7 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 3517#L343-7 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 3514#L344-7 activate_threads_#t~ret11 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 3515#L761-21 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 3553#L761-23 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 3554#L351-21 assume 1 == ~t3_pc~0; 3667#L352-7 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 3566#L362-7 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 3567#L363-7 activate_threads_#t~ret12 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 3573#L769-21 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 3574#L769-23 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 3577#L370-21 assume 1 == ~t4_pc~0; 3749#L371-7 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 3714#L381-7 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 3715#L382-7 activate_threads_#t~ret13 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 3695#L777-21 assume !(0 != activate_threads_~tmp___3~0); 3696#L777-23 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 3256#L389-21 assume 1 == ~t5_pc~0; 3257#L390-7 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 3230#L400-7 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 3276#L401-7 activate_threads_#t~ret14 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 3285#L785-21 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 3286#L785-23 assume 1 == ~M_E~0;~M_E~0 := 2; 3288#L669-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 3548#L674-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 3549#L679-3 assume !(1 == ~T3_E~0); 3460#L684-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 3461#L689-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 3490#L694-3 assume 1 == ~E_M~0;~E_M~0 := 2; 3383#L699-3 assume 1 == ~E_1~0;~E_1~0 := 2; 3384#L704-3 assume 1 == ~E_2~0;~E_2~0 := 2; 3236#L709-3 assume 1 == ~E_3~0;~E_3~0 := 2; 3237#L714-3 assume 1 == ~E_4~0;~E_4~0 := 2; 3332#L719-3 assume !(1 == ~E_5~0); 3333#L724-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 3542#L454-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 3317#L486-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 3470#L487-1 start_simulation_#t~ret16 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret16;havoc start_simulation_#t~ret16; 3540#L949 assume !(0 == start_simulation_~tmp~3); 3550#L949-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret15, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 3524#L454-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 3321#L486-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 3436#L487-2 stop_simulation_#t~ret15 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret15;havoc stop_simulation_#t~ret15; 3479#L904 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 3480#L911 stop_simulation_#res := stop_simulation_~__retres2~0; 3616#L912 start_simulation_#t~ret17 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret17;havoc start_simulation_#t~ret17; 3266#L962 assume !(0 != start_simulation_~tmp___0~1); 3267#L930-1 [2018-11-23 00:23:55,443 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 00:23:55,443 INFO L82 PathProgramCache]: Analyzing trace with hash 1122295926, now seen corresponding path program 1 times [2018-11-23 00:23:55,443 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 00:23:55,443 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 00:23:55,444 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 00:23:55,444 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 00:23:55,444 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 00:23:55,450 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 00:23:55,487 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 00:23:55,487 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 00:23:55,487 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-23 00:23:55,488 INFO L799 eck$LassoCheckResult]: stem already infeasible [2018-11-23 00:23:55,488 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 00:23:55,488 INFO L82 PathProgramCache]: Analyzing trace with hash 567388409, now seen corresponding path program 2 times [2018-11-23 00:23:55,488 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 00:23:55,488 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 00:23:55,489 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 00:23:55,489 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 00:23:55,489 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 00:23:55,495 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 00:23:55,546 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 00:23:55,547 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 00:23:55,547 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-23 00:23:55,547 INFO L811 eck$LassoCheckResult]: loop already infeasible [2018-11-23 00:23:55,547 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-23 00:23:55,547 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-23 00:23:55,547 INFO L87 Difference]: Start difference. First operand 532 states and 806 transitions. cyclomatic complexity: 275 Second operand 3 states. [2018-11-23 00:23:55,557 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 00:23:55,558 INFO L93 Difference]: Finished difference Result 532 states and 805 transitions. [2018-11-23 00:23:55,559 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-23 00:23:55,559 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 532 states and 805 transitions. [2018-11-23 00:23:55,561 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 457 [2018-11-23 00:23:55,563 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 532 states to 532 states and 805 transitions. [2018-11-23 00:23:55,564 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 532 [2018-11-23 00:23:55,564 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 532 [2018-11-23 00:23:55,564 INFO L73 IsDeterministic]: Start isDeterministic. Operand 532 states and 805 transitions. [2018-11-23 00:23:55,565 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-23 00:23:55,565 INFO L705 BuchiCegarLoop]: Abstraction has 532 states and 805 transitions. [2018-11-23 00:23:55,566 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 532 states and 805 transitions. [2018-11-23 00:23:55,572 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 532 to 532. [2018-11-23 00:23:55,572 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 532 states. [2018-11-23 00:23:55,574 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 532 states to 532 states and 805 transitions. [2018-11-23 00:23:55,574 INFO L728 BuchiCegarLoop]: Abstraction has 532 states and 805 transitions. [2018-11-23 00:23:55,574 INFO L608 BuchiCegarLoop]: Abstraction has 532 states and 805 transitions. [2018-11-23 00:23:55,574 INFO L442 BuchiCegarLoop]: ======== Iteration 5============ [2018-11-23 00:23:55,574 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 532 states and 805 transitions. [2018-11-23 00:23:55,577 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 457 [2018-11-23 00:23:55,577 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-23 00:23:55,577 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-23 00:23:55,578 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 00:23:55,578 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 00:23:55,579 INFO L794 eck$LassoCheckResult]: Stem: 4743#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 4649#L-1 havoc main_#res;havoc main_~__retres1~7;havoc main_~__retres1~7;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 4552#L893 havoc start_simulation_#t~ret16, start_simulation_#t~ret17, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 4508#L409 assume 1 == ~m_i~0;~m_st~0 := 0; 4509#L416-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 4597#L421-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 4598#L426-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 4510#L431-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 4511#L436-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 4559#L441-1 assume !(0 == ~M_E~0); 4560#L601-1 assume !(0 == ~T1_E~0); 4562#L606-1 assume !(0 == ~T2_E~0); 4456#L611-1 assume 0 == ~T3_E~0;~T3_E~0 := 1; 4457#L616-1 assume !(0 == ~T4_E~0); 4309#L621-1 assume !(0 == ~T5_E~0); 4310#L626-1 assume !(0 == ~E_M~0); 4405#L631-1 assume !(0 == ~E_1~0); 4406#L636-1 assume !(0 == ~E_2~0); 4617#L641-1 assume !(0 == ~E_3~0); 4618#L646-1 assume !(0 == ~E_4~0); 4548#L651-1 assume 0 == ~E_5~0;~E_5~0 := 1; 4549#L656-1 havoc activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 4815#L294 assume 1 == ~m_pc~0; 4700#L295 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 4701#L305 is_master_triggered_#res := is_master_triggered_~__retres1~0; 4715#L306 activate_threads_#t~ret9 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 4716#L745 assume !(0 != activate_threads_~tmp~1); 4829#L745-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 4495#L313 assume !(1 == ~t1_pc~0); 4450#L313-2 is_transmit1_triggered_~__retres1~1 := 0; 4449#L324 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 4446#L325 activate_threads_#t~ret10 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 4325#L753 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 4326#L753-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 4329#L332 assume 1 == ~t2_pc~0; 4520#L333 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 4518#L343 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 4519#L344 activate_threads_#t~ret11 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 4542#L761 assume !(0 != activate_threads_~tmp___1~0); 4543#L761-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 4544#L351 assume !(1 == ~t3_pc~0); 4655#L351-2 is_transmit3_triggered_~__retres1~3 := 0; 4656#L362 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 4678#L363 activate_threads_#t~ret12 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 4684#L769 assume !(0 != activate_threads_~tmp___2~0); 4685#L769-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 4686#L370 assume 1 == ~t4_pc~0; 4799#L371 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 4796#L381 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 4797#L382 activate_threads_#t~ret13 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 4812#L777 assume !(0 != activate_threads_~tmp___3~0); 4813#L777-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 4396#L389 assume !(1 == ~t5_pc~0); 4363#L389-2 is_transmit5_triggered_~__retres1~5 := 0; 4364#L400 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 4394#L401 activate_threads_#t~ret14 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 4414#L785 assume !(0 != activate_threads_~tmp___4~0); 4415#L785-2 assume !(1 == ~M_E~0); 4416#L669-1 assume !(1 == ~T1_E~0); 4615#L674-1 assume !(1 == ~T2_E~0); 4616#L679-1 assume !(1 == ~T3_E~0); 4546#L684-1 assume !(1 == ~T4_E~0); 4547#L689-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 4735#L694-1 assume !(1 == ~E_M~0); 4478#L699-1 assume !(1 == ~E_1~0); 4479#L704-1 assume !(1 == ~E_2~0); 4298#L709-1 assume !(1 == ~E_3~0); 4299#L714-1 assume !(1 == ~E_4~0); 4401#L719-1 assume !(1 == ~E_5~0); 4338#L930-1 [2018-11-23 00:23:55,579 INFO L796 eck$LassoCheckResult]: Loop: 4338#L930-1 assume !false; 4484#L931 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret2, eval_#t~nondet3, eval_~tmp_ndt_1~0, eval_#t~nondet4, eval_~tmp_ndt_2~0, eval_#t~nondet5, eval_~tmp_ndt_3~0, eval_#t~nondet6, eval_~tmp_ndt_4~0, eval_#t~nondet7, eval_~tmp_ndt_5~0, eval_#t~nondet8, eval_~tmp_ndt_6~0, eval_~tmp~0;havoc eval_~tmp~0; 4408#L576 assume !false; 4409#L497 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 4537#L454 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 4386#L486 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 4539#L487 eval_#t~ret2 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret2;havoc eval_#t~ret2; 4469#L501 assume !(0 != eval_~tmp~0); 4470#L591 start_simulation_~kernel_st~0 := 2; 4514#L409-1 start_simulation_~kernel_st~0 := 3; 4515#L601-2 assume 0 == ~M_E~0;~M_E~0 := 1; 4810#L601-4 assume !(0 == ~T1_E~0); 4565#L606-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 4467#L611-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 4468#L616-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 4315#L621-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 4316#L626-3 assume 0 == ~E_M~0;~E_M~0 := 1; 4379#L631-3 assume 0 == ~E_1~0;~E_1~0 := 1; 4380#L636-3 assume 0 == ~E_2~0;~E_2~0 := 1; 4608#L641-3 assume !(0 == ~E_3~0); 4609#L646-3 assume 0 == ~E_4~0;~E_4~0 := 1; 4535#L651-3 assume 0 == ~E_5~0;~E_5~0 := 1; 4536#L656-3 havoc activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 4809#L294-21 assume 1 == ~m_pc~0; 4712#L295-7 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 4713#L305-7 is_master_triggered_#res := is_master_triggered_~__retres1~0; 4705#L306-7 activate_threads_#t~ret9 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 4706#L745-21 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 4816#L745-23 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 4451#L313-21 assume !(1 == ~t1_pc~0); 4452#L313-23 is_transmit1_triggered_~__retres1~1 := 0; 4458#L324-7 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 4489#L325-7 activate_threads_#t~ret10 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 4491#L753-21 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 4492#L753-23 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 4494#L332-21 assume 1 == ~t2_pc~0; 4587#L333-7 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 4588#L343-7 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 4585#L344-7 activate_threads_#t~ret11 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 4586#L761-21 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 4624#L761-23 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 4625#L351-21 assume 1 == ~t3_pc~0; 4737#L352-7 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 4637#L362-7 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 4638#L363-7 activate_threads_#t~ret12 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 4644#L769-21 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 4645#L769-23 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 4648#L370-21 assume 1 == ~t4_pc~0; 4820#L371-7 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 4785#L381-7 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 4786#L382-7 activate_threads_#t~ret13 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 4766#L777-21 assume !(0 != activate_threads_~tmp___3~0); 4767#L777-23 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 4327#L389-21 assume 1 == ~t5_pc~0; 4328#L390-7 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 4301#L400-7 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 4347#L401-7 activate_threads_#t~ret14 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 4356#L785-21 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 4357#L785-23 assume 1 == ~M_E~0;~M_E~0 := 2; 4359#L669-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 4619#L674-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 4620#L679-3 assume !(1 == ~T3_E~0); 4531#L684-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 4532#L689-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 4561#L694-3 assume 1 == ~E_M~0;~E_M~0 := 2; 4454#L699-3 assume 1 == ~E_1~0;~E_1~0 := 2; 4455#L704-3 assume 1 == ~E_2~0;~E_2~0 := 2; 4307#L709-3 assume 1 == ~E_3~0;~E_3~0 := 2; 4308#L714-3 assume 1 == ~E_4~0;~E_4~0 := 2; 4403#L719-3 assume !(1 == ~E_5~0); 4404#L724-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 4613#L454-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 4388#L486-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 4541#L487-1 start_simulation_#t~ret16 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret16;havoc start_simulation_#t~ret16; 4611#L949 assume !(0 == start_simulation_~tmp~3); 4621#L949-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret15, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 4595#L454-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 4392#L486-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 4507#L487-2 stop_simulation_#t~ret15 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret15;havoc stop_simulation_#t~ret15; 4550#L904 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 4551#L911 stop_simulation_#res := stop_simulation_~__retres2~0; 4687#L912 start_simulation_#t~ret17 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret17;havoc start_simulation_#t~ret17; 4337#L962 assume !(0 != start_simulation_~tmp___0~1); 4338#L930-1 [2018-11-23 00:23:55,579 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 00:23:55,579 INFO L82 PathProgramCache]: Analyzing trace with hash 443023672, now seen corresponding path program 1 times [2018-11-23 00:23:55,579 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 00:23:55,579 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 00:23:55,580 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 00:23:55,580 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-23 00:23:55,580 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 00:23:55,584 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 00:23:55,601 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 00:23:55,601 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 00:23:55,601 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-23 00:23:55,601 INFO L799 eck$LassoCheckResult]: stem already infeasible [2018-11-23 00:23:55,602 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 00:23:55,602 INFO L82 PathProgramCache]: Analyzing trace with hash 567388409, now seen corresponding path program 3 times [2018-11-23 00:23:55,602 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 00:23:55,602 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 00:23:55,603 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 00:23:55,603 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 00:23:55,603 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 00:23:55,609 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 00:23:55,631 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 00:23:55,631 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 00:23:55,631 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-23 00:23:55,631 INFO L811 eck$LassoCheckResult]: loop already infeasible [2018-11-23 00:23:55,632 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-23 00:23:55,632 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-23 00:23:55,632 INFO L87 Difference]: Start difference. First operand 532 states and 805 transitions. cyclomatic complexity: 274 Second operand 3 states. [2018-11-23 00:23:55,641 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 00:23:55,641 INFO L93 Difference]: Finished difference Result 532 states and 804 transitions. [2018-11-23 00:23:55,642 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-23 00:23:55,642 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 532 states and 804 transitions. [2018-11-23 00:23:55,645 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 457 [2018-11-23 00:23:55,647 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 532 states to 532 states and 804 transitions. [2018-11-23 00:23:55,647 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 532 [2018-11-23 00:23:55,648 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 532 [2018-11-23 00:23:55,648 INFO L73 IsDeterministic]: Start isDeterministic. Operand 532 states and 804 transitions. [2018-11-23 00:23:55,649 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-23 00:23:55,649 INFO L705 BuchiCegarLoop]: Abstraction has 532 states and 804 transitions. [2018-11-23 00:23:55,650 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 532 states and 804 transitions. [2018-11-23 00:23:55,656 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 532 to 532. [2018-11-23 00:23:55,656 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 532 states. [2018-11-23 00:23:55,658 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 532 states to 532 states and 804 transitions. [2018-11-23 00:23:55,658 INFO L728 BuchiCegarLoop]: Abstraction has 532 states and 804 transitions. [2018-11-23 00:23:55,658 INFO L608 BuchiCegarLoop]: Abstraction has 532 states and 804 transitions. [2018-11-23 00:23:55,658 INFO L442 BuchiCegarLoop]: ======== Iteration 6============ [2018-11-23 00:23:55,658 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 532 states and 804 transitions. [2018-11-23 00:23:55,660 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 457 [2018-11-23 00:23:55,661 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-23 00:23:55,661 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-23 00:23:55,662 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 00:23:55,662 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 00:23:55,662 INFO L794 eck$LassoCheckResult]: Stem: 5814#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 5720#L-1 havoc main_#res;havoc main_~__retres1~7;havoc main_~__retres1~7;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 5623#L893 havoc start_simulation_#t~ret16, start_simulation_#t~ret17, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 5579#L409 assume 1 == ~m_i~0;~m_st~0 := 0; 5580#L416-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 5668#L421-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 5669#L426-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 5583#L431-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 5584#L436-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 5630#L441-1 assume !(0 == ~M_E~0); 5631#L601-1 assume !(0 == ~T1_E~0); 5633#L606-1 assume !(0 == ~T2_E~0); 5527#L611-1 assume 0 == ~T3_E~0;~T3_E~0 := 1; 5528#L616-1 assume !(0 == ~T4_E~0); 5380#L621-1 assume !(0 == ~T5_E~0); 5381#L626-1 assume !(0 == ~E_M~0); 5476#L631-1 assume !(0 == ~E_1~0); 5477#L636-1 assume !(0 == ~E_2~0); 5688#L641-1 assume !(0 == ~E_3~0); 5689#L646-1 assume !(0 == ~E_4~0); 5619#L651-1 assume 0 == ~E_5~0;~E_5~0 := 1; 5620#L656-1 havoc activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 5886#L294 assume 1 == ~m_pc~0; 5771#L295 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 5772#L305 is_master_triggered_#res := is_master_triggered_~__retres1~0; 5786#L306 activate_threads_#t~ret9 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 5787#L745 assume !(0 != activate_threads_~tmp~1); 5900#L745-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 5566#L313 assume !(1 == ~t1_pc~0); 5521#L313-2 is_transmit1_triggered_~__retres1~1 := 0; 5520#L324 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 5517#L325 activate_threads_#t~ret10 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 5396#L753 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 5397#L753-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 5400#L332 assume 1 == ~t2_pc~0; 5591#L333 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 5589#L343 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 5590#L344 activate_threads_#t~ret11 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 5613#L761 assume !(0 != activate_threads_~tmp___1~0); 5614#L761-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 5615#L351 assume !(1 == ~t3_pc~0); 5726#L351-2 is_transmit3_triggered_~__retres1~3 := 0; 5727#L362 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 5749#L363 activate_threads_#t~ret12 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 5755#L769 assume !(0 != activate_threads_~tmp___2~0); 5756#L769-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 5757#L370 assume 1 == ~t4_pc~0; 5870#L371 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 5867#L381 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 5868#L382 activate_threads_#t~ret13 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 5883#L777 assume !(0 != activate_threads_~tmp___3~0); 5884#L777-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 5467#L389 assume !(1 == ~t5_pc~0); 5434#L389-2 is_transmit5_triggered_~__retres1~5 := 0; 5435#L400 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 5465#L401 activate_threads_#t~ret14 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 5485#L785 assume !(0 != activate_threads_~tmp___4~0); 5486#L785-2 assume !(1 == ~M_E~0); 5487#L669-1 assume !(1 == ~T1_E~0); 5686#L674-1 assume !(1 == ~T2_E~0); 5687#L679-1 assume !(1 == ~T3_E~0); 5617#L684-1 assume !(1 == ~T4_E~0); 5618#L689-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 5806#L694-1 assume !(1 == ~E_M~0); 5549#L699-1 assume !(1 == ~E_1~0); 5550#L704-1 assume !(1 == ~E_2~0); 5369#L709-1 assume !(1 == ~E_3~0); 5370#L714-1 assume !(1 == ~E_4~0); 5472#L719-1 assume !(1 == ~E_5~0); 5409#L930-1 [2018-11-23 00:23:55,663 INFO L796 eck$LassoCheckResult]: Loop: 5409#L930-1 assume !false; 5555#L931 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret2, eval_#t~nondet3, eval_~tmp_ndt_1~0, eval_#t~nondet4, eval_~tmp_ndt_2~0, eval_#t~nondet5, eval_~tmp_ndt_3~0, eval_#t~nondet6, eval_~tmp_ndt_4~0, eval_#t~nondet7, eval_~tmp_ndt_5~0, eval_#t~nondet8, eval_~tmp_ndt_6~0, eval_~tmp~0;havoc eval_~tmp~0; 5479#L576 assume !false; 5480#L497 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 5608#L454 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 5457#L486 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 5610#L487 eval_#t~ret2 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret2;havoc eval_#t~ret2; 5540#L501 assume !(0 != eval_~tmp~0); 5541#L591 start_simulation_~kernel_st~0 := 2; 5585#L409-1 start_simulation_~kernel_st~0 := 3; 5586#L601-2 assume 0 == ~M_E~0;~M_E~0 := 1; 5881#L601-4 assume !(0 == ~T1_E~0); 5636#L606-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 5538#L611-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 5539#L616-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 5386#L621-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 5387#L626-3 assume 0 == ~E_M~0;~E_M~0 := 1; 5450#L631-3 assume 0 == ~E_1~0;~E_1~0 := 1; 5451#L636-3 assume 0 == ~E_2~0;~E_2~0 := 1; 5679#L641-3 assume !(0 == ~E_3~0); 5680#L646-3 assume 0 == ~E_4~0;~E_4~0 := 1; 5606#L651-3 assume 0 == ~E_5~0;~E_5~0 := 1; 5607#L656-3 havoc activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 5880#L294-21 assume 1 == ~m_pc~0; 5783#L295-7 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 5784#L305-7 is_master_triggered_#res := is_master_triggered_~__retres1~0; 5776#L306-7 activate_threads_#t~ret9 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 5777#L745-21 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 5887#L745-23 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 5522#L313-21 assume !(1 == ~t1_pc~0); 5523#L313-23 is_transmit1_triggered_~__retres1~1 := 0; 5529#L324-7 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 5560#L325-7 activate_threads_#t~ret10 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 5561#L753-21 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 5562#L753-23 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 5565#L332-21 assume 1 == ~t2_pc~0; 5658#L333-7 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 5659#L343-7 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 5656#L344-7 activate_threads_#t~ret11 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 5657#L761-21 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 5695#L761-23 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 5696#L351-21 assume 1 == ~t3_pc~0; 5808#L352-7 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 5708#L362-7 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 5709#L363-7 activate_threads_#t~ret12 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 5715#L769-21 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 5716#L769-23 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 5719#L370-21 assume 1 == ~t4_pc~0; 5891#L371-7 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 5856#L381-7 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 5857#L382-7 activate_threads_#t~ret13 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 5837#L777-21 assume !(0 != activate_threads_~tmp___3~0); 5838#L777-23 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 5398#L389-21 assume 1 == ~t5_pc~0; 5399#L390-7 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 5372#L400-7 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 5418#L401-7 activate_threads_#t~ret14 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 5427#L785-21 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 5428#L785-23 assume 1 == ~M_E~0;~M_E~0 := 2; 5430#L669-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 5690#L674-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 5691#L679-3 assume !(1 == ~T3_E~0); 5602#L684-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 5603#L689-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 5632#L694-3 assume 1 == ~E_M~0;~E_M~0 := 2; 5525#L699-3 assume 1 == ~E_1~0;~E_1~0 := 2; 5526#L704-3 assume 1 == ~E_2~0;~E_2~0 := 2; 5378#L709-3 assume 1 == ~E_3~0;~E_3~0 := 2; 5379#L714-3 assume 1 == ~E_4~0;~E_4~0 := 2; 5474#L719-3 assume !(1 == ~E_5~0); 5475#L724-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 5684#L454-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 5459#L486-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 5612#L487-1 start_simulation_#t~ret16 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret16;havoc start_simulation_#t~ret16; 5682#L949 assume !(0 == start_simulation_~tmp~3); 5692#L949-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret15, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 5666#L454-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 5463#L486-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 5578#L487-2 stop_simulation_#t~ret15 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret15;havoc stop_simulation_#t~ret15; 5621#L904 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 5622#L911 stop_simulation_#res := stop_simulation_~__retres2~0; 5758#L912 start_simulation_#t~ret17 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret17;havoc start_simulation_#t~ret17; 5408#L962 assume !(0 != start_simulation_~tmp___0~1); 5409#L930-1 [2018-11-23 00:23:55,663 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 00:23:55,678 INFO L82 PathProgramCache]: Analyzing trace with hash -1518550986, now seen corresponding path program 1 times [2018-11-23 00:23:55,678 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 00:23:55,678 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 00:23:55,679 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 00:23:55,679 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-23 00:23:55,679 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 00:23:55,684 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 00:23:55,717 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 00:23:55,717 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 00:23:55,718 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2018-11-23 00:23:55,718 INFO L799 eck$LassoCheckResult]: stem already infeasible [2018-11-23 00:23:55,718 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 00:23:55,718 INFO L82 PathProgramCache]: Analyzing trace with hash 567388409, now seen corresponding path program 4 times [2018-11-23 00:23:55,718 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 00:23:55,718 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 00:23:55,719 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 00:23:55,719 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 00:23:55,719 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 00:23:55,725 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 00:23:55,752 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 00:23:55,753 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 00:23:55,753 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-23 00:23:55,753 INFO L811 eck$LassoCheckResult]: loop already infeasible [2018-11-23 00:23:55,753 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-23 00:23:55,753 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-23 00:23:55,753 INFO L87 Difference]: Start difference. First operand 532 states and 804 transitions. cyclomatic complexity: 273 Second operand 3 states. [2018-11-23 00:23:55,787 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 00:23:55,787 INFO L93 Difference]: Finished difference Result 532 states and 799 transitions. [2018-11-23 00:23:55,788 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-23 00:23:55,788 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 532 states and 799 transitions. [2018-11-23 00:23:55,790 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 457 [2018-11-23 00:23:55,792 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 532 states to 532 states and 799 transitions. [2018-11-23 00:23:55,792 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 532 [2018-11-23 00:23:55,793 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 532 [2018-11-23 00:23:55,793 INFO L73 IsDeterministic]: Start isDeterministic. Operand 532 states and 799 transitions. [2018-11-23 00:23:55,794 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-23 00:23:55,794 INFO L705 BuchiCegarLoop]: Abstraction has 532 states and 799 transitions. [2018-11-23 00:23:55,795 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 532 states and 799 transitions. [2018-11-23 00:23:55,799 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 532 to 532. [2018-11-23 00:23:55,800 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 532 states. [2018-11-23 00:23:55,801 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 532 states to 532 states and 799 transitions. [2018-11-23 00:23:55,801 INFO L728 BuchiCegarLoop]: Abstraction has 532 states and 799 transitions. [2018-11-23 00:23:55,801 INFO L608 BuchiCegarLoop]: Abstraction has 532 states and 799 transitions. [2018-11-23 00:23:55,801 INFO L442 BuchiCegarLoop]: ======== Iteration 7============ [2018-11-23 00:23:55,801 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 532 states and 799 transitions. [2018-11-23 00:23:55,803 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 457 [2018-11-23 00:23:55,803 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-23 00:23:55,803 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-23 00:23:55,804 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 00:23:55,804 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 00:23:55,804 INFO L794 eck$LassoCheckResult]: Stem: 6885#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 6791#L-1 havoc main_#res;havoc main_~__retres1~7;havoc main_~__retres1~7;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 6694#L893 havoc start_simulation_#t~ret16, start_simulation_#t~ret17, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 6650#L409 assume 1 == ~m_i~0;~m_st~0 := 0; 6651#L416-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 6739#L421-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 6740#L426-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 6654#L431-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 6655#L436-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 6701#L441-1 assume !(0 == ~M_E~0); 6702#L601-1 assume !(0 == ~T1_E~0); 6704#L606-1 assume !(0 == ~T2_E~0); 6599#L611-1 assume !(0 == ~T3_E~0); 6600#L616-1 assume !(0 == ~T4_E~0); 6451#L621-1 assume !(0 == ~T5_E~0); 6452#L626-1 assume !(0 == ~E_M~0); 6547#L631-1 assume !(0 == ~E_1~0); 6548#L636-1 assume !(0 == ~E_2~0); 6759#L641-1 assume !(0 == ~E_3~0); 6760#L646-1 assume !(0 == ~E_4~0); 6690#L651-1 assume 0 == ~E_5~0;~E_5~0 := 1; 6691#L656-1 havoc activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 6957#L294 assume 1 == ~m_pc~0; 6842#L295 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 6843#L305 is_master_triggered_#res := is_master_triggered_~__retres1~0; 6857#L306 activate_threads_#t~ret9 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 6858#L745 assume !(0 != activate_threads_~tmp~1); 6971#L745-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 6637#L313 assume !(1 == ~t1_pc~0); 6592#L313-2 is_transmit1_triggered_~__retres1~1 := 0; 6591#L324 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 6588#L325 activate_threads_#t~ret10 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 6467#L753 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 6468#L753-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 6471#L332 assume 1 == ~t2_pc~0; 6662#L333 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 6660#L343 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 6661#L344 activate_threads_#t~ret11 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 6684#L761 assume !(0 != activate_threads_~tmp___1~0); 6685#L761-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 6686#L351 assume !(1 == ~t3_pc~0); 6797#L351-2 is_transmit3_triggered_~__retres1~3 := 0; 6798#L362 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 6820#L363 activate_threads_#t~ret12 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 6826#L769 assume !(0 != activate_threads_~tmp___2~0); 6827#L769-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 6828#L370 assume 1 == ~t4_pc~0; 6941#L371 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 6938#L381 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 6939#L382 activate_threads_#t~ret13 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 6954#L777 assume !(0 != activate_threads_~tmp___3~0); 6955#L777-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 6538#L389 assume !(1 == ~t5_pc~0); 6505#L389-2 is_transmit5_triggered_~__retres1~5 := 0; 6506#L400 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 6536#L401 activate_threads_#t~ret14 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 6556#L785 assume !(0 != activate_threads_~tmp___4~0); 6557#L785-2 assume !(1 == ~M_E~0); 6558#L669-1 assume !(1 == ~T1_E~0); 6757#L674-1 assume !(1 == ~T2_E~0); 6758#L679-1 assume !(1 == ~T3_E~0); 6688#L684-1 assume !(1 == ~T4_E~0); 6689#L689-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 6877#L694-1 assume !(1 == ~E_M~0); 6620#L699-1 assume !(1 == ~E_1~0); 6621#L704-1 assume !(1 == ~E_2~0); 6440#L709-1 assume !(1 == ~E_3~0); 6441#L714-1 assume !(1 == ~E_4~0); 6543#L719-1 assume !(1 == ~E_5~0); 6480#L930-1 [2018-11-23 00:23:55,805 INFO L796 eck$LassoCheckResult]: Loop: 6480#L930-1 assume !false; 6626#L931 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret2, eval_#t~nondet3, eval_~tmp_ndt_1~0, eval_#t~nondet4, eval_~tmp_ndt_2~0, eval_#t~nondet5, eval_~tmp_ndt_3~0, eval_#t~nondet6, eval_~tmp_ndt_4~0, eval_#t~nondet7, eval_~tmp_ndt_5~0, eval_#t~nondet8, eval_~tmp_ndt_6~0, eval_~tmp~0;havoc eval_~tmp~0; 6550#L576 assume !false; 6551#L497 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 6680#L454 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 6528#L486 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 6681#L487 eval_#t~ret2 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret2;havoc eval_#t~ret2; 6611#L501 assume !(0 != eval_~tmp~0); 6612#L591 start_simulation_~kernel_st~0 := 2; 6656#L409-1 start_simulation_~kernel_st~0 := 3; 6657#L601-2 assume 0 == ~M_E~0;~M_E~0 := 1; 6952#L601-4 assume !(0 == ~T1_E~0); 6707#L606-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 6609#L611-3 assume !(0 == ~T3_E~0); 6610#L616-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 6457#L621-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 6458#L626-3 assume 0 == ~E_M~0;~E_M~0 := 1; 6521#L631-3 assume 0 == ~E_1~0;~E_1~0 := 1; 6522#L636-3 assume 0 == ~E_2~0;~E_2~0 := 1; 6750#L641-3 assume !(0 == ~E_3~0); 6751#L646-3 assume 0 == ~E_4~0;~E_4~0 := 1; 6677#L651-3 assume 0 == ~E_5~0;~E_5~0 := 1; 6678#L656-3 havoc activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 6951#L294-21 assume 1 == ~m_pc~0; 6854#L295-7 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 6855#L305-7 is_master_triggered_#res := is_master_triggered_~__retres1~0; 6847#L306-7 activate_threads_#t~ret9 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 6848#L745-21 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 6958#L745-23 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 6593#L313-21 assume !(1 == ~t1_pc~0); 6594#L313-23 is_transmit1_triggered_~__retres1~1 := 0; 6598#L324-7 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 6631#L325-7 activate_threads_#t~ret10 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 6632#L753-21 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 6633#L753-23 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 6636#L332-21 assume 1 == ~t2_pc~0; 6729#L333-7 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 6730#L343-7 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 6727#L344-7 activate_threads_#t~ret11 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 6728#L761-21 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 6766#L761-23 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 6767#L351-21 assume !(1 == ~t3_pc~0); 6880#L351-23 is_transmit3_triggered_~__retres1~3 := 0; 6779#L362-7 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 6780#L363-7 activate_threads_#t~ret12 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 6786#L769-21 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 6787#L769-23 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 6790#L370-21 assume 1 == ~t4_pc~0; 6962#L371-7 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 6927#L381-7 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 6928#L382-7 activate_threads_#t~ret13 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 6908#L777-21 assume !(0 != activate_threads_~tmp___3~0); 6909#L777-23 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 6469#L389-21 assume 1 == ~t5_pc~0; 6470#L390-7 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 6443#L400-7 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 6489#L401-7 activate_threads_#t~ret14 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 6498#L785-21 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 6499#L785-23 assume 1 == ~M_E~0;~M_E~0 := 2; 6501#L669-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 6761#L674-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 6762#L679-3 assume !(1 == ~T3_E~0); 6673#L684-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 6674#L689-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 6703#L694-3 assume 1 == ~E_M~0;~E_M~0 := 2; 6596#L699-3 assume 1 == ~E_1~0;~E_1~0 := 2; 6597#L704-3 assume 1 == ~E_2~0;~E_2~0 := 2; 6449#L709-3 assume 1 == ~E_3~0;~E_3~0 := 2; 6450#L714-3 assume 1 == ~E_4~0;~E_4~0 := 2; 6545#L719-3 assume !(1 == ~E_5~0); 6546#L724-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 6755#L454-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 6530#L486-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 6683#L487-1 start_simulation_#t~ret16 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret16;havoc start_simulation_#t~ret16; 6753#L949 assume !(0 == start_simulation_~tmp~3); 6763#L949-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret15, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 6737#L454-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 6534#L486-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 6649#L487-2 stop_simulation_#t~ret15 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret15;havoc stop_simulation_#t~ret15; 6692#L904 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 6693#L911 stop_simulation_#res := stop_simulation_~__retres2~0; 6829#L912 start_simulation_#t~ret17 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret17;havoc start_simulation_#t~ret17; 6479#L962 assume !(0 != start_simulation_~tmp___0~1); 6480#L930-1 [2018-11-23 00:23:55,805 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 00:23:55,805 INFO L82 PathProgramCache]: Analyzing trace with hash -257633736, now seen corresponding path program 1 times [2018-11-23 00:23:55,805 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 00:23:55,805 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 00:23:55,806 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 00:23:55,806 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-23 00:23:55,807 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 00:23:55,810 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 00:23:55,845 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 00:23:55,845 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 00:23:55,845 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2018-11-23 00:23:55,845 INFO L799 eck$LassoCheckResult]: stem already infeasible [2018-11-23 00:23:55,845 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 00:23:55,846 INFO L82 PathProgramCache]: Analyzing trace with hash 320331798, now seen corresponding path program 1 times [2018-11-23 00:23:55,846 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 00:23:55,846 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 00:23:55,846 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 00:23:55,846 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 00:23:55,847 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 00:23:55,852 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 00:23:55,886 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 00:23:55,886 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 00:23:55,887 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-23 00:23:55,887 INFO L811 eck$LassoCheckResult]: loop already infeasible [2018-11-23 00:23:55,887 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-23 00:23:55,887 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-23 00:23:55,887 INFO L87 Difference]: Start difference. First operand 532 states and 799 transitions. cyclomatic complexity: 268 Second operand 3 states. [2018-11-23 00:23:55,945 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 00:23:55,945 INFO L93 Difference]: Finished difference Result 532 states and 786 transitions. [2018-11-23 00:23:55,945 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-23 00:23:55,946 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 532 states and 786 transitions. [2018-11-23 00:23:55,948 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 457 [2018-11-23 00:23:55,950 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 532 states to 532 states and 786 transitions. [2018-11-23 00:23:55,950 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 532 [2018-11-23 00:23:55,950 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 532 [2018-11-23 00:23:55,951 INFO L73 IsDeterministic]: Start isDeterministic. Operand 532 states and 786 transitions. [2018-11-23 00:23:55,951 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-23 00:23:55,951 INFO L705 BuchiCegarLoop]: Abstraction has 532 states and 786 transitions. [2018-11-23 00:23:55,952 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 532 states and 786 transitions. [2018-11-23 00:23:55,959 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 532 to 532. [2018-11-23 00:23:55,959 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 532 states. [2018-11-23 00:23:55,960 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 532 states to 532 states and 786 transitions. [2018-11-23 00:23:55,960 INFO L728 BuchiCegarLoop]: Abstraction has 532 states and 786 transitions. [2018-11-23 00:23:55,960 INFO L608 BuchiCegarLoop]: Abstraction has 532 states and 786 transitions. [2018-11-23 00:23:55,960 INFO L442 BuchiCegarLoop]: ======== Iteration 8============ [2018-11-23 00:23:55,960 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 532 states and 786 transitions. [2018-11-23 00:23:55,962 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 457 [2018-11-23 00:23:55,962 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-23 00:23:55,962 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-23 00:23:55,963 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 00:23:55,963 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 00:23:55,963 INFO L794 eck$LassoCheckResult]: Stem: 7956#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 7862#L-1 havoc main_#res;havoc main_~__retres1~7;havoc main_~__retres1~7;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 7765#L893 havoc start_simulation_#t~ret16, start_simulation_#t~ret17, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 7721#L409 assume 1 == ~m_i~0;~m_st~0 := 0; 7722#L416-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 7810#L421-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 7811#L426-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 7725#L431-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 7726#L436-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 7772#L441-1 assume !(0 == ~M_E~0); 7773#L601-1 assume !(0 == ~T1_E~0); 7775#L606-1 assume !(0 == ~T2_E~0); 7670#L611-1 assume !(0 == ~T3_E~0); 7671#L616-1 assume !(0 == ~T4_E~0); 7523#L621-1 assume !(0 == ~T5_E~0); 7524#L626-1 assume !(0 == ~E_M~0); 7618#L631-1 assume !(0 == ~E_1~0); 7619#L636-1 assume !(0 == ~E_2~0); 7830#L641-1 assume !(0 == ~E_3~0); 7831#L646-1 assume !(0 == ~E_4~0); 7761#L651-1 assume !(0 == ~E_5~0); 7762#L656-1 havoc activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 8028#L294 assume 1 == ~m_pc~0; 7915#L295 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 7916#L305 is_master_triggered_#res := is_master_triggered_~__retres1~0; 7928#L306 activate_threads_#t~ret9 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 7929#L745 assume !(0 != activate_threads_~tmp~1); 8042#L745-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 7708#L313 assume !(1 == ~t1_pc~0); 7663#L313-2 is_transmit1_triggered_~__retres1~1 := 0; 7662#L324 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 7659#L325 activate_threads_#t~ret10 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 7538#L753 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 7539#L753-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 7542#L332 assume 1 == ~t2_pc~0; 7733#L333 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 7731#L343 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 7732#L344 activate_threads_#t~ret11 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 7755#L761 assume !(0 != activate_threads_~tmp___1~0); 7756#L761-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 7757#L351 assume !(1 == ~t3_pc~0); 7868#L351-2 is_transmit3_triggered_~__retres1~3 := 0; 7869#L362 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 7891#L363 activate_threads_#t~ret12 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 7897#L769 assume !(0 != activate_threads_~tmp___2~0); 7898#L769-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 7899#L370 assume 1 == ~t4_pc~0; 8012#L371 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 8009#L381 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 8010#L382 activate_threads_#t~ret13 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 8025#L777 assume !(0 != activate_threads_~tmp___3~0); 8026#L777-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 7609#L389 assume !(1 == ~t5_pc~0); 7576#L389-2 is_transmit5_triggered_~__retres1~5 := 0; 7577#L400 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 7607#L401 activate_threads_#t~ret14 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 7627#L785 assume !(0 != activate_threads_~tmp___4~0); 7628#L785-2 assume !(1 == ~M_E~0); 7629#L669-1 assume !(1 == ~T1_E~0); 7828#L674-1 assume !(1 == ~T2_E~0); 7829#L679-1 assume !(1 == ~T3_E~0); 7759#L684-1 assume !(1 == ~T4_E~0); 7760#L689-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 7948#L694-1 assume !(1 == ~E_M~0); 7691#L699-1 assume !(1 == ~E_1~0); 7692#L704-1 assume !(1 == ~E_2~0); 7511#L709-1 assume !(1 == ~E_3~0); 7512#L714-1 assume !(1 == ~E_4~0); 7614#L719-1 assume !(1 == ~E_5~0); 7551#L930-1 [2018-11-23 00:23:55,964 INFO L796 eck$LassoCheckResult]: Loop: 7551#L930-1 assume !false; 7697#L931 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret2, eval_#t~nondet3, eval_~tmp_ndt_1~0, eval_#t~nondet4, eval_~tmp_ndt_2~0, eval_#t~nondet5, eval_~tmp_ndt_3~0, eval_#t~nondet6, eval_~tmp_ndt_4~0, eval_#t~nondet7, eval_~tmp_ndt_5~0, eval_#t~nondet8, eval_~tmp_ndt_6~0, eval_~tmp~0;havoc eval_~tmp~0; 7621#L576 assume !false; 7622#L497 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 7751#L454 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 7599#L486 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 7752#L487 eval_#t~ret2 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret2;havoc eval_#t~ret2; 7682#L501 assume !(0 != eval_~tmp~0); 7683#L591 start_simulation_~kernel_st~0 := 2; 7727#L409-1 start_simulation_~kernel_st~0 := 3; 7728#L601-2 assume 0 == ~M_E~0;~M_E~0 := 1; 8023#L601-4 assume !(0 == ~T1_E~0); 7778#L606-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 7680#L611-3 assume !(0 == ~T3_E~0); 7681#L616-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 7528#L621-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 7529#L626-3 assume 0 == ~E_M~0;~E_M~0 := 1; 7592#L631-3 assume 0 == ~E_1~0;~E_1~0 := 1; 7593#L636-3 assume 0 == ~E_2~0;~E_2~0 := 1; 7821#L641-3 assume !(0 == ~E_3~0); 7822#L646-3 assume 0 == ~E_4~0;~E_4~0 := 1; 7748#L651-3 assume !(0 == ~E_5~0); 7749#L656-3 havoc activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 8022#L294-21 assume 1 == ~m_pc~0; 7925#L295-7 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 7926#L305-7 is_master_triggered_#res := is_master_triggered_~__retres1~0; 7918#L306-7 activate_threads_#t~ret9 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 7919#L745-21 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 8029#L745-23 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 7664#L313-21 assume !(1 == ~t1_pc~0); 7665#L313-23 is_transmit1_triggered_~__retres1~1 := 0; 7669#L324-7 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 7702#L325-7 activate_threads_#t~ret10 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 7703#L753-21 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 7704#L753-23 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 7707#L332-21 assume 1 == ~t2_pc~0; 7800#L333-7 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 7801#L343-7 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 7798#L344-7 activate_threads_#t~ret11 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 7799#L761-21 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 7837#L761-23 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 7838#L351-21 assume 1 == ~t3_pc~0; 7950#L352-7 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 7850#L362-7 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 7851#L363-7 activate_threads_#t~ret12 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 7857#L769-21 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 7858#L769-23 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 7861#L370-21 assume 1 == ~t4_pc~0; 8033#L371-7 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 7998#L381-7 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 7999#L382-7 activate_threads_#t~ret13 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 7979#L777-21 assume !(0 != activate_threads_~tmp___3~0); 7980#L777-23 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 7540#L389-21 assume !(1 == ~t5_pc~0); 7515#L389-23 is_transmit5_triggered_~__retres1~5 := 0; 7516#L400-7 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 7560#L401-7 activate_threads_#t~ret14 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 7569#L785-21 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 7570#L785-23 assume 1 == ~M_E~0;~M_E~0 := 2; 7572#L669-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 7832#L674-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 7833#L679-3 assume !(1 == ~T3_E~0); 7744#L684-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 7745#L689-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 7774#L694-3 assume 1 == ~E_M~0;~E_M~0 := 2; 7667#L699-3 assume 1 == ~E_1~0;~E_1~0 := 2; 7668#L704-3 assume 1 == ~E_2~0;~E_2~0 := 2; 7520#L709-3 assume 1 == ~E_3~0;~E_3~0 := 2; 7521#L714-3 assume 1 == ~E_4~0;~E_4~0 := 2; 7616#L719-3 assume !(1 == ~E_5~0); 7617#L724-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 7826#L454-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 7601#L486-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 7754#L487-1 start_simulation_#t~ret16 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret16;havoc start_simulation_#t~ret16; 7824#L949 assume !(0 == start_simulation_~tmp~3); 7834#L949-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret15, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 7808#L454-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 7605#L486-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 7720#L487-2 stop_simulation_#t~ret15 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret15;havoc stop_simulation_#t~ret15; 7763#L904 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 7764#L911 stop_simulation_#res := stop_simulation_~__retres2~0; 7900#L912 start_simulation_#t~ret17 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret17;havoc start_simulation_#t~ret17; 7550#L962 assume !(0 != start_simulation_~tmp___0~1); 7551#L930-1 [2018-11-23 00:23:55,964 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 00:23:55,964 INFO L82 PathProgramCache]: Analyzing trace with hash -273152454, now seen corresponding path program 1 times [2018-11-23 00:23:55,964 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 00:23:55,964 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 00:23:55,965 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 00:23:55,965 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 00:23:55,965 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 00:23:55,968 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 00:23:55,982 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 00:23:55,982 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 00:23:55,982 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2018-11-23 00:23:55,982 INFO L799 eck$LassoCheckResult]: stem already infeasible [2018-11-23 00:23:55,983 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 00:23:55,983 INFO L82 PathProgramCache]: Analyzing trace with hash -1196993068, now seen corresponding path program 1 times [2018-11-23 00:23:55,983 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 00:23:55,983 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 00:23:55,984 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 00:23:55,984 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 00:23:55,984 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 00:23:55,989 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 00:23:56,031 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 00:23:56,031 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 00:23:56,031 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-11-23 00:23:56,032 INFO L811 eck$LassoCheckResult]: loop already infeasible [2018-11-23 00:23:56,032 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-23 00:23:56,032 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-23 00:23:56,032 INFO L87 Difference]: Start difference. First operand 532 states and 786 transitions. cyclomatic complexity: 255 Second operand 3 states. [2018-11-23 00:23:56,116 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 00:23:56,116 INFO L93 Difference]: Finished difference Result 974 states and 1421 transitions. [2018-11-23 00:23:56,117 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-23 00:23:56,118 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 974 states and 1421 transitions. [2018-11-23 00:23:56,122 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 898 [2018-11-23 00:23:56,126 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 974 states to 974 states and 1421 transitions. [2018-11-23 00:23:56,126 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 974 [2018-11-23 00:23:56,128 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 974 [2018-11-23 00:23:56,128 INFO L73 IsDeterministic]: Start isDeterministic. Operand 974 states and 1421 transitions. [2018-11-23 00:23:56,129 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-23 00:23:56,130 INFO L705 BuchiCegarLoop]: Abstraction has 974 states and 1421 transitions. [2018-11-23 00:23:56,131 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 974 states and 1421 transitions. [2018-11-23 00:23:56,144 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 974 to 934. [2018-11-23 00:23:56,144 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 934 states. [2018-11-23 00:23:56,147 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 934 states to 934 states and 1366 transitions. [2018-11-23 00:23:56,147 INFO L728 BuchiCegarLoop]: Abstraction has 934 states and 1366 transitions. [2018-11-23 00:23:56,147 INFO L608 BuchiCegarLoop]: Abstraction has 934 states and 1366 transitions. [2018-11-23 00:23:56,147 INFO L442 BuchiCegarLoop]: ======== Iteration 9============ [2018-11-23 00:23:56,147 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 934 states and 1366 transitions. [2018-11-23 00:23:56,152 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 858 [2018-11-23 00:23:56,153 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-23 00:23:56,153 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-23 00:23:56,153 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 00:23:56,153 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 00:23:56,155 INFO L794 eck$LassoCheckResult]: Stem: 9472#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 9380#L-1 havoc main_#res;havoc main_~__retres1~7;havoc main_~__retres1~7;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 9282#L893 havoc start_simulation_#t~ret16, start_simulation_#t~ret17, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 9238#L409 assume 1 == ~m_i~0;~m_st~0 := 0; 9239#L416-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 9327#L421-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 9328#L426-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 9242#L431-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 9243#L436-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 9289#L441-1 assume !(0 == ~M_E~0); 9290#L601-1 assume !(0 == ~T1_E~0); 9292#L606-1 assume !(0 == ~T2_E~0); 9186#L611-1 assume !(0 == ~T3_E~0); 9187#L616-1 assume !(0 == ~T4_E~0); 9038#L621-1 assume !(0 == ~T5_E~0); 9039#L626-1 assume !(0 == ~E_M~0); 9133#L631-1 assume !(0 == ~E_1~0); 9134#L636-1 assume !(0 == ~E_2~0); 9347#L641-1 assume !(0 == ~E_3~0); 9348#L646-1 assume !(0 == ~E_4~0); 9278#L651-1 assume !(0 == ~E_5~0); 9279#L656-1 havoc activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 9549#L294 assume !(1 == ~m_pc~0); 9565#L294-2 is_master_triggered_~__retres1~0 := 0; 9577#L305 is_master_triggered_#res := is_master_triggered_~__retres1~0; 9446#L306 activate_threads_#t~ret9 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 9447#L745 assume !(0 != activate_threads_~tmp~1); 9581#L745-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 9224#L313 assume !(1 == ~t1_pc~0); 9179#L313-2 is_transmit1_triggered_~__retres1~1 := 0; 9178#L324 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 9176#L325 activate_threads_#t~ret10 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 9053#L753 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 9054#L753-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 9057#L332 assume 1 == ~t2_pc~0; 9250#L333 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 9248#L343 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 9249#L344 activate_threads_#t~ret11 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 9272#L761 assume !(0 != activate_threads_~tmp___1~0); 9273#L761-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 9274#L351 assume !(1 == ~t3_pc~0); 9386#L351-2 is_transmit3_triggered_~__retres1~3 := 0; 9387#L362 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 9409#L363 activate_threads_#t~ret12 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 9415#L769 assume !(0 != activate_threads_~tmp___2~0); 9416#L769-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 9417#L370 assume 1 == ~t4_pc~0; 9533#L371 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 9531#L381 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 9532#L382 activate_threads_#t~ret13 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 9546#L777 assume !(0 != activate_threads_~tmp___3~0); 9547#L777-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 9124#L389 assume !(1 == ~t5_pc~0); 9091#L389-2 is_transmit5_triggered_~__retres1~5 := 0; 9092#L400 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 9122#L401 activate_threads_#t~ret14 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 9142#L785 assume !(0 != activate_threads_~tmp___4~0); 9143#L785-2 assume !(1 == ~M_E~0); 9144#L669-1 assume !(1 == ~T1_E~0); 9345#L674-1 assume !(1 == ~T2_E~0); 9346#L679-1 assume !(1 == ~T3_E~0); 9276#L684-1 assume !(1 == ~T4_E~0); 9277#L689-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 9463#L694-1 assume !(1 == ~E_M~0); 9207#L699-1 assume !(1 == ~E_1~0); 9208#L704-1 assume !(1 == ~E_2~0); 9026#L709-1 assume !(1 == ~E_3~0); 9027#L714-1 assume !(1 == ~E_4~0); 9129#L719-1 assume !(1 == ~E_5~0); 9066#L930-1 [2018-11-23 00:23:56,156 INFO L796 eck$LassoCheckResult]: Loop: 9066#L930-1 assume !false; 9213#L931 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret2, eval_#t~nondet3, eval_~tmp_ndt_1~0, eval_#t~nondet4, eval_~tmp_ndt_2~0, eval_#t~nondet5, eval_~tmp_ndt_3~0, eval_#t~nondet6, eval_~tmp_ndt_4~0, eval_#t~nondet7, eval_~tmp_ndt_5~0, eval_#t~nondet8, eval_~tmp_ndt_6~0, eval_~tmp~0;havoc eval_~tmp~0; 9136#L576 assume !false; 9137#L497 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 9268#L454 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 9114#L486 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 9269#L487 eval_#t~ret2 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret2;havoc eval_#t~ret2; 9198#L501 assume !(0 != eval_~tmp~0); 9199#L591 start_simulation_~kernel_st~0 := 2; 9244#L409-1 start_simulation_~kernel_st~0 := 3; 9245#L601-2 assume 0 == ~M_E~0;~M_E~0 := 1; 9544#L601-4 assume !(0 == ~T1_E~0); 9295#L606-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 9196#L611-3 assume !(0 == ~T3_E~0); 9197#L616-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 9043#L621-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 9044#L626-3 assume 0 == ~E_M~0;~E_M~0 := 1; 9107#L631-3 assume 0 == ~E_1~0;~E_1~0 := 1; 9108#L636-3 assume 0 == ~E_2~0;~E_2~0 := 1; 9338#L641-3 assume !(0 == ~E_3~0); 9339#L646-3 assume 0 == ~E_4~0;~E_4~0 := 1; 9265#L651-3 assume !(0 == ~E_5~0); 9266#L656-3 havoc activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 9543#L294-21 assume !(1 == ~m_pc~0); 9551#L294-23 is_master_triggered_~__retres1~0 := 0; 9552#L305-7 is_master_triggered_#res := is_master_triggered_~__retres1~0; 9433#L306-7 activate_threads_#t~ret9 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 9434#L745-21 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 9559#L745-23 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 9180#L313-21 assume !(1 == ~t1_pc~0); 9181#L313-23 is_transmit1_triggered_~__retres1~1 := 0; 9185#L324-7 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 9218#L325-7 activate_threads_#t~ret10 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 9219#L753-21 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 9220#L753-23 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 9223#L332-21 assume 1 == ~t2_pc~0; 9317#L333-7 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 9318#L343-7 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 9315#L344-7 activate_threads_#t~ret11 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 9316#L761-21 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 9354#L761-23 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 9355#L351-21 assume 1 == ~t3_pc~0; 9465#L352-7 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 9368#L362-7 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 9369#L363-7 activate_threads_#t~ret12 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 9375#L769-21 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 9376#L769-23 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 9379#L370-21 assume !(1 == ~t4_pc~0); 9582#L370-23 is_transmit4_triggered_~__retres1~4 := 0; 9920#L381-7 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 9919#L382-7 activate_threads_#t~ret13 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 9918#L777-21 assume !(0 != activate_threads_~tmp___3~0); 9917#L777-23 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 9916#L389-21 assume !(1 == ~t5_pc~0); 9914#L389-23 is_transmit5_triggered_~__retres1~5 := 0; 9913#L400-7 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 9911#L401-7 activate_threads_#t~ret14 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 9910#L785-21 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 9909#L785-23 assume 1 == ~M_E~0;~M_E~0 := 2; 9908#L669-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 9907#L674-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 9906#L679-3 assume !(1 == ~T3_E~0); 9905#L684-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 9904#L689-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 9903#L694-3 assume 1 == ~E_M~0;~E_M~0 := 2; 9902#L699-3 assume 1 == ~E_1~0;~E_1~0 := 2; 9485#L704-3 assume 1 == ~E_2~0;~E_2~0 := 2; 9035#L709-3 assume 1 == ~E_3~0;~E_3~0 := 2; 9036#L714-3 assume 1 == ~E_4~0;~E_4~0 := 2; 9131#L719-3 assume !(1 == ~E_5~0); 9132#L724-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 9343#L454-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 9116#L486-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 9271#L487-1 start_simulation_#t~ret16 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret16;havoc start_simulation_#t~ret16; 9342#L949 assume !(0 == start_simulation_~tmp~3); 9351#L949-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret15, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 9325#L454-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 9120#L486-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 9237#L487-2 stop_simulation_#t~ret15 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret15;havoc stop_simulation_#t~ret15; 9280#L904 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 9281#L911 stop_simulation_#res := stop_simulation_~__retres2~0; 9418#L912 start_simulation_#t~ret17 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret17;havoc start_simulation_#t~ret17; 9065#L962 assume !(0 != start_simulation_~tmp___0~1); 9066#L930-1 [2018-11-23 00:23:56,156 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 00:23:56,156 INFO L82 PathProgramCache]: Analyzing trace with hash 2128372667, now seen corresponding path program 1 times [2018-11-23 00:23:56,156 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 00:23:56,156 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 00:23:56,157 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 00:23:56,157 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 00:23:56,157 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 00:23:56,161 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 00:23:56,189 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 00:23:56,189 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 00:23:56,189 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2018-11-23 00:23:56,189 INFO L799 eck$LassoCheckResult]: stem already infeasible [2018-11-23 00:23:56,189 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 00:23:56,189 INFO L82 PathProgramCache]: Analyzing trace with hash -573326574, now seen corresponding path program 1 times [2018-11-23 00:23:56,190 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 00:23:56,190 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 00:23:56,190 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 00:23:56,190 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 00:23:56,190 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 00:23:56,195 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 00:23:56,231 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 00:23:56,232 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 00:23:56,232 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-11-23 00:23:56,232 INFO L811 eck$LassoCheckResult]: loop already infeasible [2018-11-23 00:23:56,232 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-23 00:23:56,232 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-23 00:23:56,232 INFO L87 Difference]: Start difference. First operand 934 states and 1366 transitions. cyclomatic complexity: 434 Second operand 3 states. [2018-11-23 00:23:56,311 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 00:23:56,312 INFO L93 Difference]: Finished difference Result 1695 states and 2461 transitions. [2018-11-23 00:23:56,312 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-23 00:23:56,312 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1695 states and 2461 transitions. [2018-11-23 00:23:56,318 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 1614 [2018-11-23 00:23:56,324 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1695 states to 1695 states and 2461 transitions. [2018-11-23 00:23:56,324 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1695 [2018-11-23 00:23:56,326 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1695 [2018-11-23 00:23:56,326 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1695 states and 2461 transitions. [2018-11-23 00:23:56,328 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-23 00:23:56,328 INFO L705 BuchiCegarLoop]: Abstraction has 1695 states and 2461 transitions. [2018-11-23 00:23:56,329 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1695 states and 2461 transitions. [2018-11-23 00:23:56,345 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1695 to 1691. [2018-11-23 00:23:56,345 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1691 states. [2018-11-23 00:23:56,349 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1691 states to 1691 states and 2457 transitions. [2018-11-23 00:23:56,349 INFO L728 BuchiCegarLoop]: Abstraction has 1691 states and 2457 transitions. [2018-11-23 00:23:56,349 INFO L608 BuchiCegarLoop]: Abstraction has 1691 states and 2457 transitions. [2018-11-23 00:23:56,349 INFO L442 BuchiCegarLoop]: ======== Iteration 10============ [2018-11-23 00:23:56,349 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1691 states and 2457 transitions. [2018-11-23 00:23:56,354 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 1610 [2018-11-23 00:23:56,354 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-23 00:23:56,355 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-23 00:23:56,355 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 00:23:56,356 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 00:23:56,356 INFO L794 eck$LassoCheckResult]: Stem: 12117#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 12026#L-1 havoc main_#res;havoc main_~__retres1~7;havoc main_~__retres1~7;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 11920#L893 havoc start_simulation_#t~ret16, start_simulation_#t~ret17, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 11877#L409 assume 1 == ~m_i~0;~m_st~0 := 0; 11878#L416-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 11963#L421-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 11964#L426-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 11879#L431-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 11880#L436-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 11926#L441-1 assume !(0 == ~M_E~0); 11927#L601-1 assume !(0 == ~T1_E~0); 11930#L606-1 assume !(0 == ~T2_E~0); 11824#L611-1 assume !(0 == ~T3_E~0); 11825#L616-1 assume !(0 == ~T4_E~0); 11675#L621-1 assume !(0 == ~T5_E~0); 11676#L626-1 assume !(0 == ~E_M~0); 11773#L631-1 assume !(0 == ~E_1~0); 11774#L636-1 assume !(0 == ~E_2~0); 11991#L641-1 assume !(0 == ~E_3~0); 11992#L646-1 assume !(0 == ~E_4~0); 11916#L651-1 assume !(0 == ~E_5~0); 11917#L656-1 havoc activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 12192#L294 assume !(1 == ~m_pc~0); 12211#L294-2 is_master_triggered_~__retres1~0 := 0; 12222#L305 is_master_triggered_#res := is_master_triggered_~__retres1~0; 12088#L306 activate_threads_#t~ret9 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 12089#L745 assume !(0 != activate_threads_~tmp~1); 12225#L745-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 11863#L313 assume !(1 == ~t1_pc~0); 11818#L313-2 is_transmit1_triggered_~__retres1~1 := 0; 11817#L324 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 11814#L325 activate_threads_#t~ret10 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 11690#L753 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 11691#L753-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 11695#L332 assume !(1 == ~t2_pc~0); 11889#L332-2 is_transmit2_triggered_~__retres1~2 := 0; 11887#L343 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 11888#L344 activate_threads_#t~ret11 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 11910#L761 assume !(0 != activate_threads_~tmp___1~0); 11911#L761-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 11912#L351 assume !(1 == ~t3_pc~0); 12032#L351-2 is_transmit3_triggered_~__retres1~3 := 0; 12033#L362 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 12054#L363 activate_threads_#t~ret12 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 12060#L769 assume !(0 != activate_threads_~tmp___2~0); 12061#L769-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 12062#L370 assume 1 == ~t4_pc~0; 12176#L371 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 12171#L381 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 12172#L382 activate_threads_#t~ret13 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 12189#L777 assume !(0 != activate_threads_~tmp___3~0); 12190#L777-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 11762#L389 assume !(1 == ~t5_pc~0); 11727#L389-2 is_transmit5_triggered_~__retres1~5 := 0; 11728#L400 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 11758#L401 activate_threads_#t~ret14 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 11781#L785 assume !(0 != activate_threads_~tmp___4~0); 11782#L785-2 assume !(1 == ~M_E~0); 11784#L669-1 assume !(1 == ~T1_E~0); 11989#L674-1 assume !(1 == ~T2_E~0); 11990#L679-1 assume !(1 == ~T3_E~0); 11914#L684-1 assume !(1 == ~T4_E~0); 11915#L689-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 12108#L694-1 assume !(1 == ~E_M~0); 11846#L699-1 assume !(1 == ~E_1~0); 11847#L704-1 assume !(1 == ~E_2~0); 11664#L709-1 assume !(1 == ~E_3~0); 11665#L714-1 assume !(1 == ~E_4~0); 11766#L719-1 assume !(1 == ~E_5~0); 11767#L930-1 [2018-11-23 00:23:56,356 INFO L796 eck$LassoCheckResult]: Loop: 11767#L930-1 assume !false; 12478#L931 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret2, eval_#t~nondet3, eval_~tmp_ndt_1~0, eval_#t~nondet4, eval_~tmp_ndt_2~0, eval_#t~nondet5, eval_~tmp_ndt_3~0, eval_#t~nondet6, eval_~tmp_ndt_4~0, eval_#t~nondet7, eval_~tmp_ndt_5~0, eval_#t~nondet8, eval_~tmp_ndt_6~0, eval_~tmp~0;havoc eval_~tmp~0; 12476#L576 assume !false; 12474#L497 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 12462#L454 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 12460#L486 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 12374#L487 eval_#t~ret2 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret2;havoc eval_#t~ret2; 12345#L501 assume !(0 != eval_~tmp~0); 12227#L591 start_simulation_~kernel_st~0 := 2; 11883#L409-1 start_simulation_~kernel_st~0 := 3; 11884#L601-2 assume 0 == ~M_E~0;~M_E~0 := 1; 12187#L601-4 assume !(0 == ~T1_E~0); 11933#L606-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 11835#L611-3 assume !(0 == ~T3_E~0); 11836#L616-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 11681#L621-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 11682#L626-3 assume 0 == ~E_M~0;~E_M~0 := 1; 11746#L631-3 assume 0 == ~E_1~0;~E_1~0 := 1; 11747#L636-3 assume 0 == ~E_2~0;~E_2~0 := 1; 11978#L641-3 assume !(0 == ~E_3~0); 11979#L646-3 assume 0 == ~E_4~0;~E_4~0 := 1; 11903#L651-3 assume !(0 == ~E_5~0); 11904#L656-3 havoc activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 12186#L294-21 assume !(1 == ~m_pc~0); 12193#L294-23 is_master_triggered_~__retres1~0 := 0; 12194#L305-7 is_master_triggered_#res := is_master_triggered_~__retres1~0; 12078#L306-7 activate_threads_#t~ret9 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 12079#L745-21 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 12204#L745-23 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 11819#L313-21 assume !(1 == ~t1_pc~0); 11820#L313-23 is_transmit1_triggered_~__retres1~1 := 0; 11826#L324-7 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 11857#L325-7 activate_threads_#t~ret10 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 11858#L753-21 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 11859#L753-23 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 11862#L332-21 assume !(1 == ~t2_pc~0); 11988#L332-23 is_transmit2_triggered_~__retres1~2 := 0; 11993#L343-7 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 11953#L344-7 activate_threads_#t~ret11 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 11954#L761-21 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 11999#L761-23 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 12000#L351-21 assume 1 == ~t3_pc~0; 12112#L352-7 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 12014#L362-7 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 12015#L363-7 activate_threads_#t~ret12 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 12021#L769-21 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 12022#L769-23 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 12025#L370-21 assume 1 == ~t4_pc~0; 12213#L371-7 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 12162#L381-7 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 12163#L382-7 activate_threads_#t~ret13 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 12143#L777-21 assume !(0 != activate_threads_~tmp___3~0); 12144#L777-23 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 11693#L389-21 assume !(1 == ~t5_pc~0); 11668#L389-23 is_transmit5_triggered_~__retres1~5 := 0; 11669#L400-7 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 11713#L401-7 activate_threads_#t~ret14 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 11719#L785-21 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 11720#L785-23 assume 1 == ~M_E~0;~M_E~0 := 2; 11724#L669-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 11994#L674-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 11995#L679-3 assume !(1 == ~T3_E~0); 11899#L684-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 11900#L689-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 11929#L694-3 assume 1 == ~E_M~0;~E_M~0 := 2; 11822#L699-3 assume 1 == ~E_1~0;~E_1~0 := 2; 11823#L704-3 assume 1 == ~E_2~0;~E_2~0 := 2; 11673#L709-3 assume 1 == ~E_3~0;~E_3~0 := 2; 11674#L714-3 assume 1 == ~E_4~0;~E_4~0 := 2; 11771#L719-3 assume !(1 == ~E_5~0); 11772#L724-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 11985#L454-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 11755#L486-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 11909#L487-1 start_simulation_#t~ret16 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret16;havoc start_simulation_#t~ret16; 11984#L949 assume !(0 == start_simulation_~tmp~3); 11996#L949-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret15, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 11965#L454-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 11760#L486-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 11876#L487-2 stop_simulation_#t~ret15 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret15;havoc stop_simulation_#t~ret15; 12590#L904 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 12589#L911 stop_simulation_#res := stop_simulation_~__retres2~0; 12588#L912 start_simulation_#t~ret17 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret17;havoc start_simulation_#t~ret17; 12587#L962 assume !(0 != start_simulation_~tmp___0~1); 11767#L930-1 [2018-11-23 00:23:56,356 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 00:23:56,356 INFO L82 PathProgramCache]: Analyzing trace with hash -1115145540, now seen corresponding path program 1 times [2018-11-23 00:23:56,356 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 00:23:56,356 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 00:23:56,357 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 00:23:56,357 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 00:23:56,357 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 00:23:56,361 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 00:23:56,381 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 00:23:56,382 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 00:23:56,382 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2018-11-23 00:23:56,382 INFO L799 eck$LassoCheckResult]: stem already infeasible [2018-11-23 00:23:56,382 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 00:23:56,382 INFO L82 PathProgramCache]: Analyzing trace with hash -1670642542, now seen corresponding path program 1 times [2018-11-23 00:23:56,382 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 00:23:56,382 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 00:23:56,383 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 00:23:56,383 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 00:23:56,383 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 00:23:56,388 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 00:23:56,419 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 00:23:56,420 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 00:23:56,420 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-11-23 00:23:56,420 INFO L811 eck$LassoCheckResult]: loop already infeasible [2018-11-23 00:23:56,420 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-23 00:23:56,420 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-23 00:23:56,421 INFO L87 Difference]: Start difference. First operand 1691 states and 2457 transitions. cyclomatic complexity: 770 Second operand 3 states. [2018-11-23 00:23:56,491 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 00:23:56,491 INFO L93 Difference]: Finished difference Result 3116 states and 4496 transitions. [2018-11-23 00:23:56,492 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-23 00:23:56,492 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 3116 states and 4496 transitions. [2018-11-23 00:23:56,504 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 3020 [2018-11-23 00:23:56,515 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 3116 states to 3116 states and 4496 transitions. [2018-11-23 00:23:56,515 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 3116 [2018-11-23 00:23:56,518 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 3116 [2018-11-23 00:23:56,518 INFO L73 IsDeterministic]: Start isDeterministic. Operand 3116 states and 4496 transitions. [2018-11-23 00:23:56,522 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-23 00:23:56,522 INFO L705 BuchiCegarLoop]: Abstraction has 3116 states and 4496 transitions. [2018-11-23 00:23:56,524 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3116 states and 4496 transitions. [2018-11-23 00:23:56,555 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3116 to 3108. [2018-11-23 00:23:56,555 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3108 states. [2018-11-23 00:23:56,561 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3108 states to 3108 states and 4488 transitions. [2018-11-23 00:23:56,561 INFO L728 BuchiCegarLoop]: Abstraction has 3108 states and 4488 transitions. [2018-11-23 00:23:56,561 INFO L608 BuchiCegarLoop]: Abstraction has 3108 states and 4488 transitions. [2018-11-23 00:23:56,561 INFO L442 BuchiCegarLoop]: ======== Iteration 11============ [2018-11-23 00:23:56,561 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 3108 states and 4488 transitions. [2018-11-23 00:23:56,570 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 3012 [2018-11-23 00:23:56,570 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-23 00:23:56,570 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-23 00:23:56,571 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 00:23:56,571 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 00:23:56,571 INFO L794 eck$LassoCheckResult]: Stem: 16955#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 16864#L-1 havoc main_#res;havoc main_~__retres1~7;havoc main_~__retres1~7;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 16748#L893 havoc start_simulation_#t~ret16, start_simulation_#t~ret17, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 16704#L409 assume 1 == ~m_i~0;~m_st~0 := 0; 16705#L416-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 16791#L421-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 16792#L426-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 16706#L431-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 16707#L436-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 16754#L441-1 assume !(0 == ~M_E~0); 16755#L601-1 assume !(0 == ~T1_E~0); 16758#L606-1 assume !(0 == ~T2_E~0); 16642#L611-1 assume !(0 == ~T3_E~0); 16643#L616-1 assume !(0 == ~T4_E~0); 16491#L621-1 assume !(0 == ~T5_E~0); 16492#L626-1 assume !(0 == ~E_M~0); 16590#L631-1 assume !(0 == ~E_1~0); 16591#L636-1 assume !(0 == ~E_2~0); 16820#L641-1 assume !(0 == ~E_3~0); 16821#L646-1 assume !(0 == ~E_4~0); 16744#L651-1 assume !(0 == ~E_5~0); 16745#L656-1 havoc activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 17028#L294 assume !(1 == ~m_pc~0); 17044#L294-2 is_master_triggered_~__retres1~0 := 0; 17061#L305 is_master_triggered_#res := is_master_triggered_~__retres1~0; 16926#L306 activate_threads_#t~ret9 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 16927#L745 assume !(0 != activate_threads_~tmp~1); 17067#L745-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 16684#L313 assume !(1 == ~t1_pc~0); 16636#L313-2 is_transmit1_triggered_~__retres1~1 := 0; 16635#L324 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 16632#L325 activate_threads_#t~ret10 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 16507#L753 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 16508#L753-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 16512#L332 assume !(1 == ~t2_pc~0); 16716#L332-2 is_transmit2_triggered_~__retres1~2 := 0; 16714#L343 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 16715#L344 activate_threads_#t~ret11 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 16738#L761 assume !(0 != activate_threads_~tmp___1~0); 16739#L761-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 16740#L351 assume !(1 == ~t3_pc~0); 16870#L351-2 is_transmit3_triggered_~__retres1~3 := 0; 16871#L362 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 16892#L363 activate_threads_#t~ret12 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 16898#L769 assume !(0 != activate_threads_~tmp___2~0); 16899#L769-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 16900#L370 assume !(1 == ~t4_pc~0); 17013#L370-2 is_transmit4_triggered_~__retres1~4 := 0; 17008#L381 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 17009#L382 activate_threads_#t~ret13 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 17025#L777 assume !(0 != activate_threads_~tmp___3~0); 17026#L777-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 16579#L389 assume !(1 == ~t5_pc~0); 16544#L389-2 is_transmit5_triggered_~__retres1~5 := 0; 16545#L400 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 16575#L401 activate_threads_#t~ret14 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 16599#L785 assume !(0 != activate_threads_~tmp___4~0); 16600#L785-2 assume !(1 == ~M_E~0); 16601#L669-1 assume !(1 == ~T1_E~0); 16818#L674-1 assume !(1 == ~T2_E~0); 16819#L679-1 assume !(1 == ~T3_E~0); 16742#L684-1 assume !(1 == ~T4_E~0); 16743#L689-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 16946#L694-1 assume !(1 == ~E_M~0); 16664#L699-1 assume !(1 == ~E_1~0); 16665#L704-1 assume !(1 == ~E_2~0); 16480#L709-1 assume !(1 == ~E_3~0); 16481#L714-1 assume !(1 == ~E_4~0); 16583#L719-1 assume !(1 == ~E_5~0); 16584#L930-1 [2018-11-23 00:23:56,571 INFO L796 eck$LassoCheckResult]: Loop: 16584#L930-1 assume !false; 18605#L931 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret2, eval_#t~nondet3, eval_~tmp_ndt_1~0, eval_#t~nondet4, eval_~tmp_ndt_2~0, eval_#t~nondet5, eval_~tmp_ndt_3~0, eval_#t~nondet6, eval_~tmp_ndt_4~0, eval_#t~nondet7, eval_~tmp_ndt_5~0, eval_#t~nondet8, eval_~tmp_ndt_6~0, eval_~tmp~0;havoc eval_~tmp~0; 18603#L576 assume !false; 18601#L497 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 18587#L454 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 18585#L486 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 18583#L487 eval_#t~ret2 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret2;havoc eval_#t~ret2; 18580#L501 assume !(0 != eval_~tmp~0); 18581#L591 start_simulation_~kernel_st~0 := 2; 19049#L409-1 start_simulation_~kernel_st~0 := 3; 19042#L601-2 assume 0 == ~M_E~0;~M_E~0 := 1; 19037#L601-4 assume !(0 == ~T1_E~0); 19032#L606-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 19027#L611-3 assume !(0 == ~T3_E~0); 19023#L616-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 19018#L621-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 19017#L626-3 assume 0 == ~E_M~0;~E_M~0 := 1; 19016#L631-3 assume 0 == ~E_1~0;~E_1~0 := 1; 19015#L636-3 assume 0 == ~E_2~0;~E_2~0 := 1; 19014#L641-3 assume !(0 == ~E_3~0); 19013#L646-3 assume 0 == ~E_4~0;~E_4~0 := 1; 19012#L651-3 assume !(0 == ~E_5~0); 19011#L656-3 havoc activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 19010#L294-21 assume !(1 == ~m_pc~0); 19009#L294-23 is_master_triggered_~__retres1~0 := 0; 19008#L305-7 is_master_triggered_#res := is_master_triggered_~__retres1~0; 19007#L306-7 activate_threads_#t~ret9 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 19006#L745-21 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 19005#L745-23 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 19004#L313-21 assume !(1 == ~t1_pc~0); 19002#L313-23 is_transmit1_triggered_~__retres1~1 := 0; 19000#L324-7 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 18998#L325-7 activate_threads_#t~ret10 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 18996#L753-21 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 18994#L753-23 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 18992#L332-21 assume !(1 == ~t2_pc~0); 18990#L332-23 is_transmit2_triggered_~__retres1~2 := 0; 18988#L343-7 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 18985#L344-7 activate_threads_#t~ret11 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 18983#L761-21 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 18981#L761-23 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 18979#L351-21 assume !(1 == ~t3_pc~0); 18976#L351-23 is_transmit3_triggered_~__retres1~3 := 0; 18974#L362-7 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 18972#L363-7 activate_threads_#t~ret12 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 18970#L769-21 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 18968#L769-23 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 18966#L370-21 assume !(1 == ~t4_pc~0); 18964#L370-23 is_transmit4_triggered_~__retres1~4 := 0; 18962#L381-7 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 18959#L382-7 activate_threads_#t~ret13 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 18957#L777-21 assume !(0 != activate_threads_~tmp___3~0); 18955#L777-23 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 18953#L389-21 assume !(1 == ~t5_pc~0); 18950#L389-23 is_transmit5_triggered_~__retres1~5 := 0; 18948#L400-7 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 18946#L401-7 activate_threads_#t~ret14 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 18944#L785-21 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 18942#L785-23 assume 1 == ~M_E~0;~M_E~0 := 2; 18940#L669-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 18938#L674-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 18935#L679-3 assume !(1 == ~T3_E~0); 18933#L684-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 18931#L689-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 18929#L694-3 assume 1 == ~E_M~0;~E_M~0 := 2; 18927#L699-3 assume 1 == ~E_1~0;~E_1~0 := 2; 18925#L704-3 assume 1 == ~E_2~0;~E_2~0 := 2; 18923#L709-3 assume 1 == ~E_3~0;~E_3~0 := 2; 18921#L714-3 assume 1 == ~E_4~0;~E_4~0 := 2; 18919#L719-3 assume !(1 == ~E_5~0); 18917#L724-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 18912#L454-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 18906#L486-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 18904#L487-1 start_simulation_#t~ret16 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret16;havoc start_simulation_#t~ret16; 18900#L949 assume !(0 == start_simulation_~tmp~3); 18899#L949-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret15, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 18892#L454-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 18887#L486-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 18885#L487-2 stop_simulation_#t~ret15 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret15;havoc stop_simulation_#t~ret15; 18884#L904 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 18882#L911 stop_simulation_#res := stop_simulation_~__retres2~0; 18881#L912 start_simulation_#t~ret17 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret17;havoc start_simulation_#t~ret17; 18880#L962 assume !(0 != start_simulation_~tmp___0~1); 16584#L930-1 [2018-11-23 00:23:56,571 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 00:23:56,572 INFO L82 PathProgramCache]: Analyzing trace with hash -335164611, now seen corresponding path program 1 times [2018-11-23 00:23:56,572 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 00:23:56,572 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 00:23:56,572 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 00:23:56,572 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 00:23:56,572 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 00:23:56,576 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 00:23:56,594 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 00:23:56,594 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 00:23:56,595 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2018-11-23 00:23:56,595 INFO L799 eck$LassoCheckResult]: stem already infeasible [2018-11-23 00:23:56,595 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 00:23:56,595 INFO L82 PathProgramCache]: Analyzing trace with hash -1296006256, now seen corresponding path program 1 times [2018-11-23 00:23:56,595 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 00:23:56,595 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 00:23:56,596 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 00:23:56,596 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 00:23:56,596 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 00:23:56,600 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 00:23:56,615 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 00:23:56,615 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 00:23:56,615 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-11-23 00:23:56,615 INFO L811 eck$LassoCheckResult]: loop already infeasible [2018-11-23 00:23:56,616 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-23 00:23:56,616 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-23 00:23:56,616 INFO L87 Difference]: Start difference. First operand 3108 states and 4488 transitions. cyclomatic complexity: 1388 Second operand 3 states. [2018-11-23 00:23:56,661 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 00:23:56,662 INFO L93 Difference]: Finished difference Result 3108 states and 4462 transitions. [2018-11-23 00:23:56,662 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-23 00:23:56,663 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 3108 states and 4462 transitions. [2018-11-23 00:23:56,673 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 3012 [2018-11-23 00:23:56,685 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 3108 states to 3108 states and 4462 transitions. [2018-11-23 00:23:56,685 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 3108 [2018-11-23 00:23:56,688 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 3108 [2018-11-23 00:23:56,688 INFO L73 IsDeterministic]: Start isDeterministic. Operand 3108 states and 4462 transitions. [2018-11-23 00:23:56,691 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-23 00:23:56,692 INFO L705 BuchiCegarLoop]: Abstraction has 3108 states and 4462 transitions. [2018-11-23 00:23:56,694 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3108 states and 4462 transitions. [2018-11-23 00:23:56,723 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3108 to 3108. [2018-11-23 00:23:56,724 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3108 states. [2018-11-23 00:23:56,730 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3108 states to 3108 states and 4462 transitions. [2018-11-23 00:23:56,730 INFO L728 BuchiCegarLoop]: Abstraction has 3108 states and 4462 transitions. [2018-11-23 00:23:56,730 INFO L608 BuchiCegarLoop]: Abstraction has 3108 states and 4462 transitions. [2018-11-23 00:23:56,730 INFO L442 BuchiCegarLoop]: ======== Iteration 12============ [2018-11-23 00:23:56,730 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 3108 states and 4462 transitions. [2018-11-23 00:23:56,738 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 3012 [2018-11-23 00:23:56,738 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-23 00:23:56,739 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-23 00:23:56,739 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 00:23:56,739 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 00:23:56,740 INFO L794 eck$LassoCheckResult]: Stem: 23174#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 23082#L-1 havoc main_#res;havoc main_~__retres1~7;havoc main_~__retres1~7;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 22965#L893 havoc start_simulation_#t~ret16, start_simulation_#t~ret17, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 22922#L409 assume 1 == ~m_i~0;~m_st~0 := 0; 22923#L416-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 23008#L421-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 23009#L426-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 22924#L431-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 22925#L436-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 22971#L441-1 assume !(0 == ~M_E~0); 22972#L601-1 assume !(0 == ~T1_E~0); 22975#L606-1 assume !(0 == ~T2_E~0); 22868#L611-1 assume !(0 == ~T3_E~0); 22869#L616-1 assume !(0 == ~T4_E~0); 22716#L621-1 assume !(0 == ~T5_E~0); 22717#L626-1 assume !(0 == ~E_M~0); 22816#L631-1 assume !(0 == ~E_1~0); 22817#L636-1 assume !(0 == ~E_2~0); 23040#L641-1 assume !(0 == ~E_3~0); 23041#L646-1 assume !(0 == ~E_4~0); 22961#L651-1 assume !(0 == ~E_5~0); 22962#L656-1 havoc activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 23247#L294 assume !(1 == ~m_pc~0); 23270#L294-2 is_master_triggered_~__retres1~0 := 0; 23287#L305 is_master_triggered_#res := is_master_triggered_~__retres1~0; 23144#L306 activate_threads_#t~ret9 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 23145#L745 assume !(0 != activate_threads_~tmp~1); 23301#L745-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 22909#L313 assume !(1 == ~t1_pc~0); 22862#L313-2 is_transmit1_triggered_~__retres1~1 := 0; 22861#L324 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 22858#L325 activate_threads_#t~ret10 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 22732#L753 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 22733#L753-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 22737#L332 assume !(1 == ~t2_pc~0); 22934#L332-2 is_transmit2_triggered_~__retres1~2 := 0; 22932#L343 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 22933#L344 activate_threads_#t~ret11 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 22955#L761 assume !(0 != activate_threads_~tmp___1~0); 22956#L761-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 22957#L351 assume !(1 == ~t3_pc~0); 23088#L351-2 is_transmit3_triggered_~__retres1~3 := 0; 23089#L362 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 23110#L363 activate_threads_#t~ret12 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 23116#L769 assume !(0 != activate_threads_~tmp___2~0); 23117#L769-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 23118#L370 assume !(1 == ~t4_pc~0); 23231#L370-2 is_transmit4_triggered_~__retres1~4 := 0; 23226#L381 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 23227#L382 activate_threads_#t~ret13 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 23244#L777 assume !(0 != activate_threads_~tmp___3~0); 23245#L777-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 22805#L389 assume !(1 == ~t5_pc~0); 22771#L389-2 is_transmit5_triggered_~__retres1~5 := 0; 22772#L400 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 22801#L401 activate_threads_#t~ret14 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 22824#L785 assume !(0 != activate_threads_~tmp___4~0); 22825#L785-2 assume !(1 == ~M_E~0); 22827#L669-1 assume !(1 == ~T1_E~0); 23038#L674-1 assume !(1 == ~T2_E~0); 23039#L679-1 assume !(1 == ~T3_E~0); 22959#L684-1 assume !(1 == ~T4_E~0); 22960#L689-1 assume !(1 == ~T5_E~0); 23164#L694-1 assume !(1 == ~E_M~0); 22891#L699-1 assume !(1 == ~E_1~0); 22892#L704-1 assume !(1 == ~E_2~0); 22705#L709-1 assume !(1 == ~E_3~0); 22706#L714-1 assume !(1 == ~E_4~0); 22809#L719-1 assume !(1 == ~E_5~0); 22746#L930-1 [2018-11-23 00:23:56,740 INFO L796 eck$LassoCheckResult]: Loop: 22746#L930-1 assume !false; 22897#L931 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret2, eval_#t~nondet3, eval_~tmp_ndt_1~0, eval_#t~nondet4, eval_~tmp_ndt_2~0, eval_#t~nondet5, eval_~tmp_ndt_3~0, eval_#t~nondet6, eval_~tmp_ndt_4~0, eval_#t~nondet7, eval_~tmp_ndt_5~0, eval_#t~nondet8, eval_~tmp_ndt_6~0, eval_~tmp~0;havoc eval_~tmp~0; 22819#L576 assume !false; 22820#L497 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 22950#L454 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 22796#L486 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 22952#L487 eval_#t~ret2 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret2;havoc eval_#t~ret2; 22882#L501 assume !(0 != eval_~tmp~0); 22883#L591 start_simulation_~kernel_st~0 := 2; 25685#L409-1 start_simulation_~kernel_st~0 := 3; 25684#L601-2 assume 0 == ~M_E~0;~M_E~0 := 1; 25683#L601-4 assume !(0 == ~T1_E~0); 25682#L606-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 25681#L611-3 assume !(0 == ~T3_E~0); 25679#L616-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 25677#L621-3 assume !(0 == ~T5_E~0); 25675#L626-3 assume 0 == ~E_M~0;~E_M~0 := 1; 25673#L631-3 assume 0 == ~E_1~0;~E_1~0 := 1; 25671#L636-3 assume 0 == ~E_2~0;~E_2~0 := 1; 25669#L641-3 assume !(0 == ~E_3~0); 25667#L646-3 assume 0 == ~E_4~0;~E_4~0 := 1; 25665#L651-3 assume !(0 == ~E_5~0); 25663#L656-3 havoc activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 25661#L294-21 assume !(1 == ~m_pc~0); 25659#L294-23 is_master_triggered_~__retres1~0 := 0; 25657#L305-7 is_master_triggered_#res := is_master_triggered_~__retres1~0; 25655#L306-7 activate_threads_#t~ret9 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 25653#L745-21 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 25651#L745-23 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 25650#L313-21 assume !(1 == ~t1_pc~0); 25648#L313-23 is_transmit1_triggered_~__retres1~1 := 0; 25646#L324-7 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 25644#L325-7 activate_threads_#t~ret10 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 25642#L753-21 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 25640#L753-23 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 25637#L332-21 assume !(1 == ~t2_pc~0); 25635#L332-23 is_transmit2_triggered_~__retres1~2 := 0; 25632#L343-7 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 25630#L344-7 activate_threads_#t~ret11 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 25628#L761-21 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 25626#L761-23 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 25624#L351-21 assume !(1 == ~t3_pc~0); 25621#L351-23 is_transmit3_triggered_~__retres1~3 := 0; 25620#L362-7 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 25619#L363-7 activate_threads_#t~ret12 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 25617#L769-21 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 25615#L769-23 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 25613#L370-21 assume !(1 == ~t4_pc~0); 25611#L370-23 is_transmit4_triggered_~__retres1~4 := 0; 25608#L381-7 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 25606#L382-7 activate_threads_#t~ret13 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 25604#L777-21 assume !(0 != activate_threads_~tmp___3~0); 25602#L777-23 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 25600#L389-21 assume !(1 == ~t5_pc~0); 25597#L389-23 is_transmit5_triggered_~__retres1~5 := 0; 25595#L400-7 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 25593#L401-7 activate_threads_#t~ret14 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 25591#L785-21 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 25589#L785-23 assume 1 == ~M_E~0;~M_E~0 := 2; 25587#L669-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 25584#L674-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 25582#L679-3 assume !(1 == ~T3_E~0); 25580#L684-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 25578#L689-3 assume !(1 == ~T5_E~0); 25576#L694-3 assume 1 == ~E_M~0;~E_M~0 := 2; 25574#L699-3 assume 1 == ~E_1~0;~E_1~0 := 2; 25572#L704-3 assume 1 == ~E_2~0;~E_2~0 := 2; 25570#L709-3 assume 1 == ~E_3~0;~E_3~0 := 2; 25568#L714-3 assume 1 == ~E_4~0;~E_4~0 := 2; 25566#L719-3 assume !(1 == ~E_5~0); 25564#L724-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 25559#L454-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 25552#L486-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 23032#L487-1 start_simulation_#t~ret16 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret16;havoc start_simulation_#t~ret16; 23033#L949 assume !(0 == start_simulation_~tmp~3); 23044#L949-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret15, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 23010#L454-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 22803#L486-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 22921#L487-2 stop_simulation_#t~ret15 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret15;havoc stop_simulation_#t~ret15; 22963#L904 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 22964#L911 stop_simulation_#res := stop_simulation_~__retres2~0; 23119#L912 start_simulation_#t~ret17 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret17;havoc start_simulation_#t~ret17; 22745#L962 assume !(0 != start_simulation_~tmp___0~1); 22746#L930-1 [2018-11-23 00:23:56,740 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 00:23:56,740 INFO L82 PathProgramCache]: Analyzing trace with hash 1439842751, now seen corresponding path program 1 times [2018-11-23 00:23:56,740 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 00:23:56,740 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 00:23:56,741 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 00:23:56,741 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 00:23:56,741 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 00:23:56,746 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 00:23:56,813 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 00:23:56,813 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 00:23:56,813 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-11-23 00:23:56,813 INFO L799 eck$LassoCheckResult]: stem already infeasible [2018-11-23 00:23:56,813 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 00:23:56,813 INFO L82 PathProgramCache]: Analyzing trace with hash -1159714548, now seen corresponding path program 1 times [2018-11-23 00:23:56,814 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 00:23:56,814 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 00:23:56,814 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 00:23:56,814 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 00:23:56,814 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 00:23:56,819 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 00:23:56,835 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 00:23:56,835 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 00:23:56,835 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-11-23 00:23:56,836 INFO L811 eck$LassoCheckResult]: loop already infeasible [2018-11-23 00:23:56,836 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-11-23 00:23:56,836 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-11-23 00:23:56,836 INFO L87 Difference]: Start difference. First operand 3108 states and 4462 transitions. cyclomatic complexity: 1362 Second operand 5 states. [2018-11-23 00:23:57,084 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 00:23:57,085 INFO L93 Difference]: Finished difference Result 8447 states and 12061 transitions. [2018-11-23 00:23:57,086 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2018-11-23 00:23:57,086 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 8447 states and 12061 transitions. [2018-11-23 00:23:57,121 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 8224 [2018-11-23 00:23:57,154 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 8447 states to 8447 states and 12061 transitions. [2018-11-23 00:23:57,155 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 8447 [2018-11-23 00:23:57,161 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 8447 [2018-11-23 00:23:57,162 INFO L73 IsDeterministic]: Start isDeterministic. Operand 8447 states and 12061 transitions. [2018-11-23 00:23:57,173 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-23 00:23:57,173 INFO L705 BuchiCegarLoop]: Abstraction has 8447 states and 12061 transitions. [2018-11-23 00:23:57,178 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 8447 states and 12061 transitions. [2018-11-23 00:23:57,251 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 8447 to 3267. [2018-11-23 00:23:57,252 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3267 states. [2018-11-23 00:23:57,255 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3267 states to 3267 states and 4621 transitions. [2018-11-23 00:23:57,256 INFO L728 BuchiCegarLoop]: Abstraction has 3267 states and 4621 transitions. [2018-11-23 00:23:57,256 INFO L608 BuchiCegarLoop]: Abstraction has 3267 states and 4621 transitions. [2018-11-23 00:23:57,256 INFO L442 BuchiCegarLoop]: ======== Iteration 13============ [2018-11-23 00:23:57,256 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 3267 states and 4621 transitions. [2018-11-23 00:23:57,262 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 3168 [2018-11-23 00:23:57,262 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-23 00:23:57,262 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-23 00:23:57,263 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 00:23:57,263 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 00:23:57,263 INFO L794 eck$LassoCheckResult]: Stem: 34764#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 34669#L-1 havoc main_#res;havoc main_~__retres1~7;havoc main_~__retres1~7;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 34556#L893 havoc start_simulation_#t~ret16, start_simulation_#t~ret17, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 34512#L409 assume 1 == ~m_i~0;~m_st~0 := 0; 34513#L416-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 34602#L421-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 34603#L426-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 34514#L431-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 34515#L436-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 34563#L441-1 assume !(0 == ~M_E~0); 34564#L601-1 assume !(0 == ~T1_E~0); 34566#L606-1 assume !(0 == ~T2_E~0); 34438#L611-1 assume !(0 == ~T3_E~0); 34439#L616-1 assume !(0 == ~T4_E~0); 34286#L621-1 assume !(0 == ~T5_E~0); 34287#L626-1 assume !(0 == ~E_M~0); 34384#L631-1 assume !(0 == ~E_1~0); 34385#L636-1 assume !(0 == ~E_2~0); 34628#L641-1 assume !(0 == ~E_3~0); 34629#L646-1 assume !(0 == ~E_4~0); 34552#L651-1 assume !(0 == ~E_5~0); 34553#L656-1 havoc activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 34838#L294 assume !(1 == ~m_pc~0); 34863#L294-2 is_master_triggered_~__retres1~0 := 0; 34880#L305 is_master_triggered_#res := is_master_triggered_~__retres1~0; 34732#L306 activate_threads_#t~ret9 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 34733#L745 assume !(0 != activate_threads_~tmp~1); 34892#L745-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 34493#L313 assume !(1 == ~t1_pc~0); 34432#L313-2 is_transmit1_triggered_~__retres1~1 := 0; 34491#L324 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 34492#L325 activate_threads_#t~ret10 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 34301#L753 assume !(0 != activate_threads_~tmp___0~0); 34302#L753-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 34306#L332 assume !(1 == ~t2_pc~0); 34524#L332-2 is_transmit2_triggered_~__retres1~2 := 0; 34522#L343 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 34523#L344 activate_threads_#t~ret11 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 34546#L761 assume !(0 != activate_threads_~tmp___1~0); 34547#L761-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 34548#L351 assume !(1 == ~t3_pc~0); 34676#L351-2 is_transmit3_triggered_~__retres1~3 := 0; 34677#L362 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 34698#L363 activate_threads_#t~ret12 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 34704#L769 assume !(0 != activate_threads_~tmp___2~0); 34705#L769-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 34706#L370 assume !(1 == ~t4_pc~0); 34823#L370-2 is_transmit4_triggered_~__retres1~4 := 0; 34818#L381 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 34819#L382 activate_threads_#t~ret13 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 34835#L777 assume !(0 != activate_threads_~tmp___3~0); 34836#L777-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 34374#L389 assume !(1 == ~t5_pc~0); 34340#L389-2 is_transmit5_triggered_~__retres1~5 := 0; 34341#L400 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 34372#L401 activate_threads_#t~ret14 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 34394#L785 assume !(0 != activate_threads_~tmp___4~0); 34395#L785-2 assume !(1 == ~M_E~0); 34396#L669-1 assume !(1 == ~T1_E~0); 34626#L674-1 assume !(1 == ~T2_E~0); 34627#L679-1 assume !(1 == ~T3_E~0); 34550#L684-1 assume !(1 == ~T4_E~0); 34551#L689-1 assume !(1 == ~T5_E~0); 34752#L694-1 assume !(1 == ~E_M~0); 34464#L699-1 assume !(1 == ~E_1~0); 34465#L704-1 assume !(1 == ~E_2~0); 34275#L709-1 assume !(1 == ~E_3~0); 34276#L714-1 assume !(1 == ~E_4~0); 34377#L719-1 assume !(1 == ~E_5~0); 34378#L930-1 [2018-11-23 00:23:57,263 INFO L796 eck$LassoCheckResult]: Loop: 34378#L930-1 assume !false; 35376#L931 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret2, eval_#t~nondet3, eval_~tmp_ndt_1~0, eval_#t~nondet4, eval_~tmp_ndt_2~0, eval_#t~nondet5, eval_~tmp_ndt_3~0, eval_#t~nondet6, eval_~tmp_ndt_4~0, eval_#t~nondet7, eval_~tmp_ndt_5~0, eval_#t~nondet8, eval_~tmp_ndt_6~0, eval_~tmp~0;havoc eval_~tmp~0; 35374#L576 assume !false; 35372#L497 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 35355#L454 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 35354#L486 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 35353#L487 eval_#t~ret2 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret2;havoc eval_#t~ret2; 35351#L501 assume !(0 != eval_~tmp~0); 35352#L591 start_simulation_~kernel_st~0 := 2; 35611#L409-1 start_simulation_~kernel_st~0 := 3; 35609#L601-2 assume 0 == ~M_E~0;~M_E~0 := 1; 35607#L601-4 assume !(0 == ~T1_E~0); 35605#L606-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 35603#L611-3 assume !(0 == ~T3_E~0); 35601#L616-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 35599#L621-3 assume !(0 == ~T5_E~0); 35597#L626-3 assume 0 == ~E_M~0;~E_M~0 := 1; 35593#L631-3 assume 0 == ~E_1~0;~E_1~0 := 1; 35591#L636-3 assume 0 == ~E_2~0;~E_2~0 := 1; 35590#L641-3 assume !(0 == ~E_3~0); 35589#L646-3 assume 0 == ~E_4~0;~E_4~0 := 1; 35588#L651-3 assume !(0 == ~E_5~0); 35587#L656-3 havoc activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 35586#L294-21 assume !(1 == ~m_pc~0); 35585#L294-23 is_master_triggered_~__retres1~0 := 0; 35584#L305-7 is_master_triggered_#res := is_master_triggered_~__retres1~0; 35583#L306-7 activate_threads_#t~ret9 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 35582#L745-21 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 35581#L745-23 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 35580#L313-21 assume 1 == ~t1_pc~0; 35578#L314-7 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 35576#L324-7 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 35574#L325-7 activate_threads_#t~ret10 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 35572#L753-21 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 35571#L753-23 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 35570#L332-21 assume !(1 == ~t2_pc~0); 35569#L332-23 is_transmit2_triggered_~__retres1~2 := 0; 35568#L343-7 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 35567#L344-7 activate_threads_#t~ret11 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 35566#L761-21 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 35565#L761-23 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 35549#L351-21 assume !(1 == ~t3_pc~0); 35546#L351-23 is_transmit3_triggered_~__retres1~3 := 0; 35544#L362-7 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 35542#L363-7 activate_threads_#t~ret12 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 35540#L769-21 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 35538#L769-23 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 35536#L370-21 assume !(1 == ~t4_pc~0); 35534#L370-23 is_transmit4_triggered_~__retres1~4 := 0; 35532#L381-7 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 35529#L382-7 activate_threads_#t~ret13 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 35527#L777-21 assume !(0 != activate_threads_~tmp___3~0); 35525#L777-23 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 35523#L389-21 assume !(1 == ~t5_pc~0); 35520#L389-23 is_transmit5_triggered_~__retres1~5 := 0; 35518#L400-7 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 35516#L401-7 activate_threads_#t~ret14 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 35514#L785-21 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 35512#L785-23 assume 1 == ~M_E~0;~M_E~0 := 2; 35510#L669-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 35508#L674-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 35505#L679-3 assume !(1 == ~T3_E~0); 35503#L684-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 35501#L689-3 assume !(1 == ~T5_E~0); 35499#L694-3 assume 1 == ~E_M~0;~E_M~0 := 2; 35497#L699-3 assume 1 == ~E_1~0;~E_1~0 := 2; 35495#L704-3 assume 1 == ~E_2~0;~E_2~0 := 2; 35493#L709-3 assume 1 == ~E_3~0;~E_3~0 := 2; 35491#L714-3 assume 1 == ~E_4~0;~E_4~0 := 2; 35489#L719-3 assume !(1 == ~E_5~0); 35487#L724-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 35482#L454-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 35476#L486-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 35474#L487-1 start_simulation_#t~ret16 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret16;havoc start_simulation_#t~ret16; 35470#L949 assume !(0 == start_simulation_~tmp~3); 35469#L949-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret15, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 35450#L454-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 35445#L486-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 35443#L487-2 stop_simulation_#t~ret15 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret15;havoc stop_simulation_#t~ret15; 35441#L904 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 35439#L911 stop_simulation_#res := stop_simulation_~__retres2~0; 35437#L912 start_simulation_#t~ret17 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret17;havoc start_simulation_#t~ret17; 35435#L962 assume !(0 != start_simulation_~tmp___0~1); 34378#L930-1 [2018-11-23 00:23:57,264 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 00:23:57,264 INFO L82 PathProgramCache]: Analyzing trace with hash 2099374273, now seen corresponding path program 1 times [2018-11-23 00:23:57,264 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 00:23:57,264 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 00:23:57,264 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 00:23:57,265 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 00:23:57,265 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 00:23:57,269 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-23 00:23:57,273 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-23 00:23:57,295 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 00:23:57,295 INFO L82 PathProgramCache]: Analyzing trace with hash -1262515795, now seen corresponding path program 1 times [2018-11-23 00:23:57,295 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 00:23:57,295 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 00:23:57,296 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 00:23:57,296 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 00:23:57,296 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 00:23:57,300 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 00:23:57,323 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 00:23:57,323 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 00:23:57,324 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-11-23 00:23:57,324 INFO L811 eck$LassoCheckResult]: loop already infeasible [2018-11-23 00:23:57,324 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-11-23 00:23:57,324 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-11-23 00:23:57,324 INFO L87 Difference]: Start difference. First operand 3267 states and 4621 transitions. cyclomatic complexity: 1362 Second operand 5 states. [2018-11-23 00:23:57,420 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 00:23:57,420 INFO L93 Difference]: Finished difference Result 5847 states and 8165 transitions. [2018-11-23 00:23:57,421 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2018-11-23 00:23:57,421 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 5847 states and 8165 transitions. [2018-11-23 00:23:57,433 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 5724 [2018-11-23 00:23:57,446 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 5847 states to 5847 states and 8165 transitions. [2018-11-23 00:23:57,446 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 5847 [2018-11-23 00:23:57,448 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 5847 [2018-11-23 00:23:57,448 INFO L73 IsDeterministic]: Start isDeterministic. Operand 5847 states and 8165 transitions. [2018-11-23 00:23:57,453 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-23 00:23:57,453 INFO L705 BuchiCegarLoop]: Abstraction has 5847 states and 8165 transitions. [2018-11-23 00:23:57,457 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 5847 states and 8165 transitions. [2018-11-23 00:23:57,483 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 5847 to 3291. [2018-11-23 00:23:57,484 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3291 states. [2018-11-23 00:23:57,487 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3291 states to 3291 states and 4645 transitions. [2018-11-23 00:23:57,487 INFO L728 BuchiCegarLoop]: Abstraction has 3291 states and 4645 transitions. [2018-11-23 00:23:57,488 INFO L608 BuchiCegarLoop]: Abstraction has 3291 states and 4645 transitions. [2018-11-23 00:23:57,488 INFO L442 BuchiCegarLoop]: ======== Iteration 14============ [2018-11-23 00:23:57,488 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 3291 states and 4645 transitions. [2018-11-23 00:23:57,494 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 3192 [2018-11-23 00:23:57,494 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-23 00:23:57,494 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-23 00:23:57,495 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 00:23:57,495 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 00:23:57,495 INFO L794 eck$LassoCheckResult]: Stem: 43883#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 43791#L-1 havoc main_#res;havoc main_~__retres1~7;havoc main_~__retres1~7;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 43672#L893 havoc start_simulation_#t~ret16, start_simulation_#t~ret17, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 43628#L409 assume 1 == ~m_i~0;~m_st~0 := 0; 43629#L416-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 43717#L421-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 43718#L426-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 43632#L431-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 43633#L436-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 43679#L441-1 assume !(0 == ~M_E~0); 43680#L601-1 assume !(0 == ~T1_E~0); 43682#L606-1 assume !(0 == ~T2_E~0); 43568#L611-1 assume !(0 == ~T3_E~0); 43569#L616-1 assume !(0 == ~T4_E~0); 43416#L621-1 assume !(0 == ~T5_E~0); 43417#L626-1 assume !(0 == ~E_M~0); 43514#L631-1 assume !(0 == ~E_1~0); 43515#L636-1 assume !(0 == ~E_2~0); 43747#L641-1 assume !(0 == ~E_3~0); 43748#L646-1 assume !(0 == ~E_4~0); 43668#L651-1 assume !(0 == ~E_5~0); 43669#L656-1 havoc activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 43957#L294 assume !(1 == ~m_pc~0); 43984#L294-2 is_master_triggered_~__retres1~0 := 0; 44000#L305 is_master_triggered_#res := is_master_triggered_~__retres1~0; 43854#L306 activate_threads_#t~ret9 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 43855#L745 assume !(0 != activate_threads_~tmp~1); 44010#L745-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 43613#L313 assume !(1 == ~t1_pc~0); 43561#L313-2 is_transmit1_triggered_~__retres1~1 := 0; 43612#L324 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 43557#L325 activate_threads_#t~ret10 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 43432#L753 assume !(0 != activate_threads_~tmp___0~0); 43433#L753-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 43436#L332 assume !(1 == ~t2_pc~0); 43640#L332-2 is_transmit2_triggered_~__retres1~2 := 0; 43638#L343 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 43639#L344 activate_threads_#t~ret11 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 43662#L761 assume !(0 != activate_threads_~tmp___1~0); 43663#L761-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 43664#L351 assume !(1 == ~t3_pc~0); 43797#L351-2 is_transmit3_triggered_~__retres1~3 := 0; 43798#L362 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 43819#L363 activate_threads_#t~ret12 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 43826#L769 assume !(0 != activate_threads_~tmp___2~0); 43827#L769-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 43828#L370 assume !(1 == ~t4_pc~0); 43941#L370-2 is_transmit4_triggered_~__retres1~4 := 0; 43938#L381 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 43939#L382 activate_threads_#t~ret13 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 43954#L777 assume !(0 != activate_threads_~tmp___3~0); 43955#L777-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 43504#L389 assume !(1 == ~t5_pc~0); 43471#L389-2 is_transmit5_triggered_~__retres1~5 := 0; 43472#L400 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 43502#L401 activate_threads_#t~ret14 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 43524#L785 assume !(0 != activate_threads_~tmp___4~0); 43525#L785-2 assume !(1 == ~M_E~0); 43526#L669-1 assume !(1 == ~T1_E~0); 43745#L674-1 assume !(1 == ~T2_E~0); 43746#L679-1 assume !(1 == ~T3_E~0); 43666#L684-1 assume !(1 == ~T4_E~0); 43667#L689-1 assume !(1 == ~T5_E~0); 43874#L694-1 assume !(1 == ~E_M~0); 43589#L699-1 assume !(1 == ~E_1~0); 43590#L704-1 assume !(1 == ~E_2~0); 43405#L709-1 assume !(1 == ~E_3~0); 43406#L714-1 assume !(1 == ~E_4~0); 43507#L719-1 assume !(1 == ~E_5~0); 43508#L930-1 [2018-11-23 00:23:57,495 INFO L796 eck$LassoCheckResult]: Loop: 43508#L930-1 assume !false; 43958#L931 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret2, eval_#t~nondet3, eval_~tmp_ndt_1~0, eval_#t~nondet4, eval_~tmp_ndt_2~0, eval_#t~nondet5, eval_~tmp_ndt_3~0, eval_#t~nondet6, eval_~tmp_ndt_4~0, eval_#t~nondet7, eval_~tmp_ndt_5~0, eval_#t~nondet8, eval_~tmp_ndt_6~0, eval_~tmp~0;havoc eval_~tmp~0; 43517#L576 assume !false; 43518#L497 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 43657#L454 assume !(0 == ~m_st~0); 43738#L458 assume !(0 == ~t1_st~0); 43893#L462 assume !(0 == ~t2_st~0); 43492#L466 assume !(0 == ~t3_st~0); 43493#L470 assume !(0 == ~t4_st~0); 43686#L474 assume !(0 == ~t5_st~0);exists_runnable_thread_~__retres1~6 := 0; 43658#L486 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 43659#L487 eval_#t~ret2 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret2;havoc eval_#t~ret2; 45089#L501 assume !(0 != eval_~tmp~0); 44012#L591 start_simulation_~kernel_st~0 := 2; 43634#L409-1 start_simulation_~kernel_st~0 := 3; 43635#L601-2 assume 0 == ~M_E~0;~M_E~0 := 1; 43952#L601-4 assume !(0 == ~T1_E~0); 43685#L606-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 43578#L611-3 assume !(0 == ~T3_E~0); 43579#L616-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 43422#L621-3 assume !(0 == ~T5_E~0); 43423#L626-3 assume 0 == ~E_M~0;~E_M~0 := 1; 43487#L631-3 assume 0 == ~E_1~0;~E_1~0 := 1; 43488#L636-3 assume 0 == ~E_2~0;~E_2~0 := 1; 43730#L641-3 assume !(0 == ~E_3~0); 43731#L646-3 assume 0 == ~E_4~0;~E_4~0 := 1; 43654#L651-3 assume !(0 == ~E_5~0); 43655#L656-3 havoc activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 43951#L294-21 assume !(1 == ~m_pc~0); 43964#L294-23 is_master_triggered_~__retres1~0 := 0; 43965#L305-7 is_master_triggered_#res := is_master_triggered_~__retres1~0; 44978#L306-7 activate_threads_#t~ret9 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 44977#L745-21 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 44976#L745-23 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 44975#L313-21 assume 1 == ~t1_pc~0; 44973#L314-7 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 44382#L324-7 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 44383#L325-7 activate_threads_#t~ret10 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 44378#L753-21 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 43607#L753-23 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 44128#L332-21 assume !(1 == ~t2_pc~0); 43749#L332-23 is_transmit2_triggered_~__retres1~2 := 0; 43750#L343-7 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 43705#L344-7 activate_threads_#t~ret11 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 43706#L761-21 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 43763#L761-23 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 43764#L351-21 assume 1 == ~t3_pc~0; 43876#L352-7 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 43779#L362-7 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 43780#L363-7 activate_threads_#t~ret12 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 43786#L769-21 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 43787#L769-23 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 43790#L370-21 assume !(1 == ~t4_pc~0); 44011#L370-23 is_transmit4_triggered_~__retres1~4 := 0; 46582#L381-7 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 46581#L382-7 activate_threads_#t~ret13 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 46580#L777-21 assume !(0 != activate_threads_~tmp___3~0); 46579#L777-23 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 46578#L389-21 assume !(1 == ~t5_pc~0); 46576#L389-23 is_transmit5_triggered_~__retres1~5 := 0; 46575#L400-7 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 46574#L401-7 activate_threads_#t~ret14 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 46573#L785-21 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 46572#L785-23 assume 1 == ~M_E~0;~M_E~0 := 2; 46571#L669-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 46570#L674-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 46569#L679-3 assume !(1 == ~T3_E~0); 46568#L684-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 46567#L689-3 assume !(1 == ~T5_E~0); 46566#L694-3 assume 1 == ~E_M~0;~E_M~0 := 2; 46565#L699-3 assume 1 == ~E_1~0;~E_1~0 := 2; 46564#L704-3 assume 1 == ~E_2~0;~E_2~0 := 2; 46563#L709-3 assume 1 == ~E_3~0;~E_3~0 := 2; 46562#L714-3 assume 1 == ~E_4~0;~E_4~0 := 2; 46561#L719-3 assume !(1 == ~E_5~0); 46504#L724-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 46505#L454-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 46555#L486-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 46553#L487-1 start_simulation_#t~ret16 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret16;havoc start_simulation_#t~ret16; 46549#L949 assume !(0 == start_simulation_~tmp~3); 43753#L949-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret15, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 43754#L454-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 46542#L486-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 46541#L487-2 stop_simulation_#t~ret15 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret15;havoc stop_simulation_#t~ret15; 46540#L904 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 46539#L911 stop_simulation_#res := stop_simulation_~__retres2~0; 46538#L912 start_simulation_#t~ret17 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret17;havoc start_simulation_#t~ret17; 46537#L962 assume !(0 != start_simulation_~tmp___0~1); 43508#L930-1 [2018-11-23 00:23:57,495 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 00:23:57,496 INFO L82 PathProgramCache]: Analyzing trace with hash 2099374273, now seen corresponding path program 2 times [2018-11-23 00:23:57,496 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 00:23:57,496 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 00:23:57,496 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 00:23:57,496 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 00:23:57,497 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 00:23:57,500 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-23 00:23:57,504 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-23 00:23:57,516 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 00:23:57,516 INFO L82 PathProgramCache]: Analyzing trace with hash 215214055, now seen corresponding path program 1 times [2018-11-23 00:23:57,516 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 00:23:57,516 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 00:23:57,517 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 00:23:57,517 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-23 00:23:57,517 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 00:23:57,522 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 00:23:57,573 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 00:23:57,573 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 00:23:57,574 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-11-23 00:23:57,574 INFO L811 eck$LassoCheckResult]: loop already infeasible [2018-11-23 00:23:57,574 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-11-23 00:23:57,574 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-11-23 00:23:57,574 INFO L87 Difference]: Start difference. First operand 3291 states and 4645 transitions. cyclomatic complexity: 1362 Second operand 5 states. [2018-11-23 00:23:57,694 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 00:23:57,695 INFO L93 Difference]: Finished difference Result 6491 states and 9104 transitions. [2018-11-23 00:23:57,696 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2018-11-23 00:23:57,696 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 6491 states and 9104 transitions. [2018-11-23 00:23:57,710 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 6376 [2018-11-23 00:23:57,722 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 6491 states to 6491 states and 9104 transitions. [2018-11-23 00:23:57,723 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 6491 [2018-11-23 00:23:57,725 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 6491 [2018-11-23 00:23:57,725 INFO L73 IsDeterministic]: Start isDeterministic. Operand 6491 states and 9104 transitions. [2018-11-23 00:23:57,731 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-23 00:23:57,731 INFO L705 BuchiCegarLoop]: Abstraction has 6491 states and 9104 transitions. [2018-11-23 00:23:57,735 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 6491 states and 9104 transitions. [2018-11-23 00:23:57,760 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 6491 to 3375. [2018-11-23 00:23:57,760 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3375 states. [2018-11-23 00:23:57,764 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3375 states to 3375 states and 4704 transitions. [2018-11-23 00:23:57,764 INFO L728 BuchiCegarLoop]: Abstraction has 3375 states and 4704 transitions. [2018-11-23 00:23:57,764 INFO L608 BuchiCegarLoop]: Abstraction has 3375 states and 4704 transitions. [2018-11-23 00:23:57,764 INFO L442 BuchiCegarLoop]: ======== Iteration 15============ [2018-11-23 00:23:57,765 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 3375 states and 4704 transitions. [2018-11-23 00:23:57,771 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 3276 [2018-11-23 00:23:57,771 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-23 00:23:57,771 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-23 00:23:57,772 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 00:23:57,772 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 00:23:57,772 INFO L794 eck$LassoCheckResult]: Stem: 53688#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 53595#L-1 havoc main_#res;havoc main_~__retres1~7;havoc main_~__retres1~7;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 53476#L893 havoc start_simulation_#t~ret16, start_simulation_#t~ret17, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 53430#L409 assume 1 == ~m_i~0;~m_st~0 := 0; 53431#L416-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 53523#L421-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 53524#L426-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 53434#L431-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 53435#L436-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 53483#L441-1 assume !(0 == ~M_E~0); 53484#L601-1 assume !(0 == ~T1_E~0); 53486#L606-1 assume !(0 == ~T2_E~0); 53363#L611-1 assume !(0 == ~T3_E~0); 53364#L616-1 assume !(0 == ~T4_E~0); 53212#L621-1 assume !(0 == ~T5_E~0); 53213#L626-1 assume !(0 == ~E_M~0); 53310#L631-1 assume !(0 == ~E_1~0); 53311#L636-1 assume !(0 == ~E_2~0); 53550#L641-1 assume !(0 == ~E_3~0); 53551#L646-1 assume !(0 == ~E_4~0); 53472#L651-1 assume !(0 == ~E_5~0); 53473#L656-1 havoc activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 53779#L294 assume !(1 == ~m_pc~0); 53814#L294-2 is_master_triggered_~__retres1~0 := 0; 53839#L305 is_master_triggered_#res := is_master_triggered_~__retres1~0; 53658#L306 activate_threads_#t~ret9 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 53659#L745 assume !(0 != activate_threads_~tmp~1); 53852#L745-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 53411#L313 assume !(1 == ~t1_pc~0); 53355#L313-2 is_transmit1_triggered_~__retres1~1 := 0; 53410#L324 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 53352#L325 activate_threads_#t~ret10 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 53227#L753 assume !(0 != activate_threads_~tmp___0~0); 53228#L753-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 53231#L332 assume !(1 == ~t2_pc~0); 53442#L332-2 is_transmit2_triggered_~__retres1~2 := 0; 53440#L343 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 53441#L344 activate_threads_#t~ret11 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 53466#L761 assume !(0 != activate_threads_~tmp___1~0); 53467#L761-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 53468#L351 assume !(1 == ~t3_pc~0); 53601#L351-2 is_transmit3_triggered_~__retres1~3 := 0; 53602#L362 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 53624#L363 activate_threads_#t~ret12 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 53630#L769 assume !(0 != activate_threads_~tmp___2~0); 53631#L769-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 53632#L370 assume !(1 == ~t4_pc~0); 53760#L370-2 is_transmit4_triggered_~__retres1~4 := 0; 53758#L381 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 53759#L382 activate_threads_#t~ret13 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 53776#L777 assume !(0 != activate_threads_~tmp___3~0); 53777#L777-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 53300#L389 assume !(1 == ~t5_pc~0); 53266#L389-2 is_transmit5_triggered_~__retres1~5 := 0; 53267#L400 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 53298#L401 activate_threads_#t~ret14 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 53319#L785 assume !(0 != activate_threads_~tmp___4~0); 53320#L785-2 assume !(1 == ~M_E~0); 53321#L669-1 assume !(1 == ~T1_E~0); 53548#L674-1 assume !(1 == ~T2_E~0); 53549#L679-1 assume !(1 == ~T3_E~0); 53470#L684-1 assume !(1 == ~T4_E~0); 53471#L689-1 assume !(1 == ~T5_E~0); 53678#L694-1 assume !(1 == ~E_M~0); 53384#L699-1 assume !(1 == ~E_1~0); 53385#L704-1 assume !(1 == ~E_2~0); 53200#L709-1 assume !(1 == ~E_3~0); 53201#L714-1 assume !(1 == ~E_4~0); 53305#L719-1 assume !(1 == ~E_5~0); 53306#L930-1 [2018-11-23 00:23:57,772 INFO L796 eck$LassoCheckResult]: Loop: 53306#L930-1 assume !false; 55222#L931 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret2, eval_#t~nondet3, eval_~tmp_ndt_1~0, eval_#t~nondet4, eval_~tmp_ndt_2~0, eval_#t~nondet5, eval_~tmp_ndt_3~0, eval_#t~nondet6, eval_~tmp_ndt_4~0, eval_#t~nondet7, eval_~tmp_ndt_5~0, eval_#t~nondet8, eval_~tmp_ndt_6~0, eval_~tmp~0;havoc eval_~tmp~0; 55221#L576 assume !false; 55220#L497 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 55213#L454 assume !(0 == ~m_st~0); 55214#L458 assume !(0 == ~t1_st~0); 55217#L462 assume !(0 == ~t2_st~0); 55219#L466 assume !(0 == ~t3_st~0); 55215#L470 assume !(0 == ~t4_st~0); 55216#L474 assume !(0 == ~t5_st~0);exists_runnable_thread_~__retres1~6 := 0; 55218#L486 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 55209#L487 eval_#t~ret2 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret2;havoc eval_#t~ret2; 55210#L501 assume !(0 != eval_~tmp~0); 55375#L591 start_simulation_~kernel_st~0 := 2; 55374#L409-1 start_simulation_~kernel_st~0 := 3; 55373#L601-2 assume 0 == ~M_E~0;~M_E~0 := 1; 55372#L601-4 assume !(0 == ~T1_E~0); 55371#L606-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 55370#L611-3 assume !(0 == ~T3_E~0); 55369#L616-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 55368#L621-3 assume !(0 == ~T5_E~0); 55367#L626-3 assume 0 == ~E_M~0;~E_M~0 := 1; 55366#L631-3 assume 0 == ~E_1~0;~E_1~0 := 1; 55365#L636-3 assume 0 == ~E_2~0;~E_2~0 := 1; 55364#L641-3 assume !(0 == ~E_3~0); 55363#L646-3 assume 0 == ~E_4~0;~E_4~0 := 1; 55362#L651-3 assume !(0 == ~E_5~0); 53770#L656-3 havoc activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 53771#L294-21 assume !(1 == ~m_pc~0); 53788#L294-23 is_master_triggered_~__retres1~0 := 0; 55208#L305-7 is_master_triggered_#res := is_master_triggered_~__retres1~0; 55207#L306-7 activate_threads_#t~ret9 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 55206#L745-21 assume !(0 != activate_threads_~tmp~1); 55205#L745-23 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 55204#L313-21 assume 1 == ~t1_pc~0; 55202#L314-7 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 55200#L324-7 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 55198#L325-7 activate_threads_#t~ret10 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 55196#L753-21 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 55195#L753-23 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 55194#L332-21 assume !(1 == ~t2_pc~0); 55193#L332-23 is_transmit2_triggered_~__retres1~2 := 0; 55192#L343-7 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 55191#L344-7 activate_threads_#t~ret11 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 55190#L761-21 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 55189#L761-23 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 55188#L351-21 assume !(1 == ~t3_pc~0); 55186#L351-23 is_transmit3_triggered_~__retres1~3 := 0; 55185#L362-7 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 55184#L363-7 activate_threads_#t~ret12 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 55183#L769-21 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 55182#L769-23 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 55181#L370-21 assume !(1 == ~t4_pc~0); 55180#L370-23 is_transmit4_triggered_~__retres1~4 := 0; 55179#L381-7 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 55178#L382-7 activate_threads_#t~ret13 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 55177#L777-21 assume !(0 != activate_threads_~tmp___3~0); 55176#L777-23 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 55175#L389-21 assume !(1 == ~t5_pc~0); 55173#L389-23 is_transmit5_triggered_~__retres1~5 := 0; 55172#L400-7 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 55171#L401-7 activate_threads_#t~ret14 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 55169#L785-21 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 55167#L785-23 assume 1 == ~M_E~0;~M_E~0 := 2; 55165#L669-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 55163#L674-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 55161#L679-3 assume !(1 == ~T3_E~0); 55159#L684-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 55157#L689-3 assume !(1 == ~T5_E~0); 55155#L694-3 assume 1 == ~E_M~0;~E_M~0 := 2; 55153#L699-3 assume 1 == ~E_1~0;~E_1~0 := 2; 55151#L704-3 assume 1 == ~E_2~0;~E_2~0 := 2; 55149#L709-3 assume 1 == ~E_3~0;~E_3~0 := 2; 55147#L714-3 assume 1 == ~E_4~0;~E_4~0 := 2; 55145#L719-3 assume !(1 == ~E_5~0); 55143#L724-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 55140#L454-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 55134#L486-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 55132#L487-1 start_simulation_#t~ret16 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret16;havoc start_simulation_#t~ret16; 55129#L949 assume !(0 == start_simulation_~tmp~3); 55130#L949-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret15, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 55244#L454-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 55238#L486-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 55236#L487-2 stop_simulation_#t~ret15 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret15;havoc stop_simulation_#t~ret15; 55234#L904 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 55232#L911 stop_simulation_#res := stop_simulation_~__retres2~0; 55230#L912 start_simulation_#t~ret17 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret17;havoc start_simulation_#t~ret17; 55227#L962 assume !(0 != start_simulation_~tmp___0~1); 53306#L930-1 [2018-11-23 00:23:57,772 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 00:23:57,772 INFO L82 PathProgramCache]: Analyzing trace with hash 2099374273, now seen corresponding path program 3 times [2018-11-23 00:23:57,772 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 00:23:57,773 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 00:23:57,773 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 00:23:57,773 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 00:23:57,773 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 00:23:57,778 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-23 00:23:57,783 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-23 00:23:57,793 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 00:23:57,793 INFO L82 PathProgramCache]: Analyzing trace with hash -1899625596, now seen corresponding path program 1 times [2018-11-23 00:23:57,793 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 00:23:57,793 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 00:23:57,794 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 00:23:57,794 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-23 00:23:57,794 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 00:23:57,798 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 00:23:57,822 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 00:23:57,822 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 00:23:57,822 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-23 00:23:57,822 INFO L811 eck$LassoCheckResult]: loop already infeasible [2018-11-23 00:23:57,823 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-23 00:23:57,823 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-23 00:23:57,823 INFO L87 Difference]: Start difference. First operand 3375 states and 4704 transitions. cyclomatic complexity: 1337 Second operand 3 states. [2018-11-23 00:23:57,867 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 00:23:57,868 INFO L93 Difference]: Finished difference Result 5777 states and 7930 transitions. [2018-11-23 00:23:57,869 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-23 00:23:57,869 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 5777 states and 7930 transitions. [2018-11-23 00:23:57,882 INFO L131 ngComponentsAnalysis]: Automaton has 12 accepting balls. 5660 [2018-11-23 00:23:57,890 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 5777 states to 5777 states and 7930 transitions. [2018-11-23 00:23:57,890 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 5777 [2018-11-23 00:23:57,893 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 5777 [2018-11-23 00:23:57,893 INFO L73 IsDeterministic]: Start isDeterministic. Operand 5777 states and 7930 transitions. [2018-11-23 00:23:57,896 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-23 00:23:57,896 INFO L705 BuchiCegarLoop]: Abstraction has 5777 states and 7930 transitions. [2018-11-23 00:23:57,899 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 5777 states and 7930 transitions. [2018-11-23 00:23:57,930 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 5777 to 5625. [2018-11-23 00:23:57,930 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 5625 states. [2018-11-23 00:23:57,936 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 5625 states to 5625 states and 7730 transitions. [2018-11-23 00:23:57,936 INFO L728 BuchiCegarLoop]: Abstraction has 5625 states and 7730 transitions. [2018-11-23 00:23:57,936 INFO L608 BuchiCegarLoop]: Abstraction has 5625 states and 7730 transitions. [2018-11-23 00:23:57,936 INFO L442 BuchiCegarLoop]: ======== Iteration 16============ [2018-11-23 00:23:57,936 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 5625 states and 7730 transitions. [2018-11-23 00:23:57,946 INFO L131 ngComponentsAnalysis]: Automaton has 12 accepting balls. 5508 [2018-11-23 00:23:57,946 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-23 00:23:57,946 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-23 00:23:57,947 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 00:23:57,947 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 00:23:57,947 INFO L794 eck$LassoCheckResult]: Stem: 62844#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 62750#L-1 havoc main_#res;havoc main_~__retres1~7;havoc main_~__retres1~7;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 62630#L893 havoc start_simulation_#t~ret16, start_simulation_#t~ret17, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 62586#L409 assume 1 == ~m_i~0;~m_st~0 := 0; 62587#L416-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 62677#L421-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 62678#L426-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 62590#L431-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 62591#L436-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 62637#L441-1 assume !(0 == ~M_E~0); 62638#L601-1 assume !(0 == ~T1_E~0); 62640#L606-1 assume !(0 == ~T2_E~0); 62519#L611-1 assume !(0 == ~T3_E~0); 62520#L616-1 assume !(0 == ~T4_E~0); 62370#L621-1 assume !(0 == ~T5_E~0); 62371#L626-1 assume !(0 == ~E_M~0); 62466#L631-1 assume !(0 == ~E_1~0); 62467#L636-1 assume !(0 == ~E_2~0); 62708#L641-1 assume !(0 == ~E_3~0); 62709#L646-1 assume !(0 == ~E_4~0); 62626#L651-1 assume !(0 == ~E_5~0); 62627#L656-1 havoc activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 62918#L294 assume !(1 == ~m_pc~0); 62949#L294-2 is_master_triggered_~__retres1~0 := 0; 62965#L305 is_master_triggered_#res := is_master_triggered_~__retres1~0; 62817#L306 activate_threads_#t~ret9 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 62818#L745 assume !(0 != activate_threads_~tmp~1); 62970#L745-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 62564#L313 assume !(1 == ~t1_pc~0); 62512#L313-2 is_transmit1_triggered_~__retres1~1 := 0; 62563#L324 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 62509#L325 activate_threads_#t~ret10 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 62385#L753 assume !(0 != activate_threads_~tmp___0~0); 62386#L753-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 62389#L332 assume !(1 == ~t2_pc~0); 62598#L332-2 is_transmit2_triggered_~__retres1~2 := 0; 62596#L343 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 62597#L344 activate_threads_#t~ret11 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 62620#L761 assume !(0 != activate_threads_~tmp___1~0); 62621#L761-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 62622#L351 assume !(1 == ~t3_pc~0); 62756#L351-2 is_transmit3_triggered_~__retres1~3 := 0; 62757#L362 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 62778#L363 activate_threads_#t~ret12 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 62786#L769 assume !(0 != activate_threads_~tmp___2~0); 62787#L769-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 62788#L370 assume !(1 == ~t4_pc~0); 62903#L370-2 is_transmit4_triggered_~__retres1~4 := 0; 62901#L381 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 62902#L382 activate_threads_#t~ret13 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 62915#L777 assume !(0 != activate_threads_~tmp___3~0); 62916#L777-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 62456#L389 assume !(1 == ~t5_pc~0); 62423#L389-2 is_transmit5_triggered_~__retres1~5 := 0; 62424#L400 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 62454#L401 activate_threads_#t~ret14 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 62475#L785 assume !(0 != activate_threads_~tmp___4~0); 62476#L785-2 assume !(1 == ~M_E~0); 62477#L669-1 assume !(1 == ~T1_E~0); 62706#L674-1 assume !(1 == ~T2_E~0); 62707#L679-1 assume !(1 == ~T3_E~0); 62624#L684-1 assume !(1 == ~T4_E~0); 62625#L689-1 assume !(1 == ~T5_E~0); 62834#L694-1 assume !(1 == ~E_M~0); 62542#L699-1 assume !(1 == ~E_1~0); 62543#L704-1 assume !(1 == ~E_2~0); 62358#L709-1 assume !(1 == ~E_3~0); 62359#L714-1 assume !(1 == ~E_4~0); 62461#L719-1 assume !(1 == ~E_5~0); 62462#L930-1 assume !false; 66754#L931 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret2, eval_#t~nondet3, eval_~tmp_ndt_1~0, eval_#t~nondet4, eval_~tmp_ndt_2~0, eval_#t~nondet5, eval_~tmp_ndt_3~0, eval_#t~nondet6, eval_~tmp_ndt_4~0, eval_#t~nondet7, eval_~tmp_ndt_5~0, eval_#t~nondet8, eval_~tmp_ndt_6~0, eval_~tmp~0;havoc eval_~tmp~0; 66751#L576 [2018-11-23 00:23:57,947 INFO L796 eck$LassoCheckResult]: Loop: 66751#L576 assume !false; 66747#L497 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 66743#L454 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 66740#L486 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 66737#L487 eval_#t~ret2 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret2;havoc eval_#t~ret2; 66733#L501 assume 0 != eval_~tmp~0; 66731#L501-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0;eval_~tmp_ndt_1~0 := eval_#t~nondet3;havoc eval_#t~nondet3; 66727#L509 assume !(0 != eval_~tmp_ndt_1~0); 66728#L506 assume !(0 == ~t1_st~0); 66789#L520 assume !(0 == ~t2_st~0); 66786#L534 assume !(0 == ~t3_st~0); 66767#L548 assume !(0 == ~t4_st~0); 66758#L562 assume !(0 == ~t5_st~0); 66751#L576 [2018-11-23 00:23:57,947 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 00:23:57,947 INFO L82 PathProgramCache]: Analyzing trace with hash -1135942013, now seen corresponding path program 1 times [2018-11-23 00:23:57,947 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 00:23:57,948 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 00:23:57,948 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 00:23:57,948 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 00:23:57,948 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 00:23:57,952 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-23 00:23:57,957 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-23 00:23:57,967 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 00:23:57,967 INFO L82 PathProgramCache]: Analyzing trace with hash -1634271327, now seen corresponding path program 1 times [2018-11-23 00:23:57,967 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 00:23:57,967 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 00:23:57,968 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 00:23:57,968 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 00:23:57,968 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 00:23:57,969 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-23 00:23:57,971 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-23 00:23:57,973 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 00:23:57,973 INFO L82 PathProgramCache]: Analyzing trace with hash -1605223329, now seen corresponding path program 1 times [2018-11-23 00:23:57,973 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 00:23:57,973 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 00:23:57,974 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 00:23:57,974 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 00:23:57,974 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 00:23:57,979 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 00:23:58,001 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 00:23:58,001 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 00:23:58,001 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-23 00:23:58,058 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-23 00:23:58,058 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-23 00:23:58,058 INFO L87 Difference]: Start difference. First operand 5625 states and 7730 transitions. cyclomatic complexity: 2117 Second operand 3 states. [2018-11-23 00:23:58,182 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 00:23:58,182 INFO L93 Difference]: Finished difference Result 10493 states and 14318 transitions. [2018-11-23 00:23:58,182 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-23 00:23:58,182 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 10493 states and 14318 transitions. [2018-11-23 00:23:58,206 INFO L131 ngComponentsAnalysis]: Automaton has 12 accepting balls. 10264 [2018-11-23 00:23:58,231 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 10493 states to 10493 states and 14318 transitions. [2018-11-23 00:23:58,231 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 10493 [2018-11-23 00:23:58,237 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 10493 [2018-11-23 00:23:58,237 INFO L73 IsDeterministic]: Start isDeterministic. Operand 10493 states and 14318 transitions. [2018-11-23 00:23:58,244 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-23 00:23:58,244 INFO L705 BuchiCegarLoop]: Abstraction has 10493 states and 14318 transitions. [2018-11-23 00:23:58,251 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 10493 states and 14318 transitions. [2018-11-23 00:23:58,332 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 10493 to 10013. [2018-11-23 00:23:58,332 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 10013 states. [2018-11-23 00:23:58,350 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 10013 states to 10013 states and 13694 transitions. [2018-11-23 00:23:58,350 INFO L728 BuchiCegarLoop]: Abstraction has 10013 states and 13694 transitions. [2018-11-23 00:23:58,351 INFO L608 BuchiCegarLoop]: Abstraction has 10013 states and 13694 transitions. [2018-11-23 00:23:58,351 INFO L442 BuchiCegarLoop]: ======== Iteration 17============ [2018-11-23 00:23:58,351 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 10013 states and 13694 transitions. [2018-11-23 00:23:58,376 INFO L131 ngComponentsAnalysis]: Automaton has 12 accepting balls. 9784 [2018-11-23 00:23:58,376 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-23 00:23:58,376 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-23 00:23:58,377 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 00:23:58,377 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 00:23:58,378 INFO L794 eck$LassoCheckResult]: Stem: 78979#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 78886#L-1 havoc main_#res;havoc main_~__retres1~7;havoc main_~__retres1~7;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 78765#L893 havoc start_simulation_#t~ret16, start_simulation_#t~ret17, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 78720#L409 assume 1 == ~m_i~0;~m_st~0 := 0; 78721#L416-1 assume !(1 == ~t1_i~0);~t1_st~0 := 2; 78810#L421-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 78811#L426-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 78722#L431-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 78723#L436-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 78771#L441-1 assume !(0 == ~M_E~0); 78772#L601-1 assume !(0 == ~T1_E~0); 78775#L606-1 assume !(0 == ~T2_E~0); 78648#L611-1 assume !(0 == ~T3_E~0); 78649#L616-1 assume !(0 == ~T4_E~0); 78495#L621-1 assume !(0 == ~T5_E~0); 78496#L626-1 assume !(0 == ~E_M~0); 78595#L631-1 assume !(0 == ~E_1~0); 78596#L636-1 assume !(0 == ~E_2~0); 78841#L641-1 assume !(0 == ~E_3~0); 78842#L646-1 assume !(0 == ~E_4~0); 78761#L651-1 assume !(0 == ~E_5~0); 78762#L656-1 havoc activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 79065#L294 assume !(1 == ~m_pc~0); 79094#L294-2 is_master_triggered_~__retres1~0 := 0; 79112#L305 is_master_triggered_#res := is_master_triggered_~__retres1~0; 78950#L306 activate_threads_#t~ret9 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 78951#L745 assume !(0 != activate_threads_~tmp~1); 79124#L745-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 78698#L313 assume !(1 == ~t1_pc~0); 78642#L313-2 is_transmit1_triggered_~__retres1~1 := 0; 78696#L324 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 78697#L325 activate_threads_#t~ret10 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 78511#L753 assume !(0 != activate_threads_~tmp___0~0); 78512#L753-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 78516#L332 assume !(1 == ~t2_pc~0); 78732#L332-2 is_transmit2_triggered_~__retres1~2 := 0; 78730#L343 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 78731#L344 activate_threads_#t~ret11 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 78755#L761 assume !(0 != activate_threads_~tmp___1~0); 78756#L761-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 78757#L351 assume !(1 == ~t3_pc~0); 78892#L351-2 is_transmit3_triggered_~__retres1~3 := 0; 78893#L362 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 78914#L363 activate_threads_#t~ret12 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 78922#L769 assume !(0 != activate_threads_~tmp___2~0); 78923#L769-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 78924#L370 assume !(1 == ~t4_pc~0); 79044#L370-2 is_transmit4_triggered_~__retres1~4 := 0; 79038#L381 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 79039#L382 activate_threads_#t~ret13 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 79062#L777 assume !(0 != activate_threads_~tmp___3~0); 79063#L777-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 78583#L389 assume !(1 == ~t5_pc~0); 78548#L389-2 is_transmit5_triggered_~__retres1~5 := 0; 78549#L400 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 78579#L401 activate_threads_#t~ret14 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 78603#L785 assume !(0 != activate_threads_~tmp___4~0); 78604#L785-2 assume !(1 == ~M_E~0); 78606#L669-1 assume !(1 == ~T1_E~0); 78839#L674-1 assume !(1 == ~T2_E~0); 78840#L679-1 assume !(1 == ~T3_E~0); 78759#L684-1 assume !(1 == ~T4_E~0); 78760#L689-1 assume !(1 == ~T5_E~0); 78970#L694-1 assume !(1 == ~E_M~0); 78670#L699-1 assume !(1 == ~E_1~0); 78671#L704-1 assume !(1 == ~E_2~0); 78484#L709-1 assume !(1 == ~E_3~0); 78485#L714-1 assume !(1 == ~E_4~0); 78916#L719-1 assume !(1 == ~E_5~0); 79800#L930-1 assume !false; 79796#L931 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret2, eval_#t~nondet3, eval_~tmp_ndt_1~0, eval_#t~nondet4, eval_~tmp_ndt_2~0, eval_#t~nondet5, eval_~tmp_ndt_3~0, eval_#t~nondet6, eval_~tmp_ndt_4~0, eval_#t~nondet7, eval_~tmp_ndt_5~0, eval_#t~nondet8, eval_~tmp_ndt_6~0, eval_~tmp~0;havoc eval_~tmp~0; 79756#L576 [2018-11-23 00:23:58,378 INFO L796 eck$LassoCheckResult]: Loop: 79756#L576 assume !false; 79757#L497 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 79748#L454 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 79749#L486 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 79741#L487 eval_#t~ret2 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret2;havoc eval_#t~ret2; 79742#L501 assume 0 != eval_~tmp~0; 79384#L501-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0;eval_~tmp_ndt_1~0 := eval_#t~nondet3;havoc eval_#t~nondet3; 79385#L509 assume !(0 != eval_~tmp_ndt_1~0); 79788#L506 assume !(0 == ~t1_st~0); 79782#L520 assume !(0 == ~t2_st~0); 79780#L534 assume !(0 == ~t3_st~0); 79769#L548 assume !(0 == ~t4_st~0); 79767#L562 assume !(0 == ~t5_st~0); 79756#L576 [2018-11-23 00:23:58,378 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 00:23:58,378 INFO L82 PathProgramCache]: Analyzing trace with hash 1942871557, now seen corresponding path program 1 times [2018-11-23 00:23:58,378 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 00:23:58,378 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 00:23:58,379 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 00:23:58,379 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 00:23:58,379 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 00:23:58,382 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 00:23:58,400 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 00:23:58,400 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 00:23:58,400 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-23 00:23:58,400 INFO L799 eck$LassoCheckResult]: stem already infeasible [2018-11-23 00:23:58,400 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 00:23:58,401 INFO L82 PathProgramCache]: Analyzing trace with hash -1634271327, now seen corresponding path program 2 times [2018-11-23 00:23:58,401 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 00:23:58,401 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 00:23:58,401 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 00:23:58,402 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 00:23:58,402 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 00:23:58,403 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-23 00:23:58,405 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-23 00:23:58,501 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-23 00:23:58,501 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-23 00:23:58,501 INFO L87 Difference]: Start difference. First operand 10013 states and 13694 transitions. cyclomatic complexity: 3693 Second operand 3 states. [2018-11-23 00:23:58,523 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 00:23:58,523 INFO L93 Difference]: Finished difference Result 9941 states and 13593 transitions. [2018-11-23 00:23:58,523 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-23 00:23:58,523 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 9941 states and 13593 transitions. [2018-11-23 00:23:58,545 INFO L131 ngComponentsAnalysis]: Automaton has 12 accepting balls. 9784 [2018-11-23 00:23:58,597 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 9941 states to 9941 states and 13593 transitions. [2018-11-23 00:23:58,597 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 9941 [2018-11-23 00:23:58,602 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 9941 [2018-11-23 00:23:58,602 INFO L73 IsDeterministic]: Start isDeterministic. Operand 9941 states and 13593 transitions. [2018-11-23 00:23:58,607 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-23 00:23:58,607 INFO L705 BuchiCegarLoop]: Abstraction has 9941 states and 13593 transitions. [2018-11-23 00:23:58,612 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 9941 states and 13593 transitions. [2018-11-23 00:23:58,673 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 9941 to 9941. [2018-11-23 00:23:58,673 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 9941 states. [2018-11-23 00:23:58,686 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 9941 states to 9941 states and 13593 transitions. [2018-11-23 00:23:58,686 INFO L728 BuchiCegarLoop]: Abstraction has 9941 states and 13593 transitions. [2018-11-23 00:23:58,686 INFO L608 BuchiCegarLoop]: Abstraction has 9941 states and 13593 transitions. [2018-11-23 00:23:58,686 INFO L442 BuchiCegarLoop]: ======== Iteration 18============ [2018-11-23 00:23:58,686 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 9941 states and 13593 transitions. [2018-11-23 00:23:58,709 INFO L131 ngComponentsAnalysis]: Automaton has 12 accepting balls. 9784 [2018-11-23 00:23:58,709 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-23 00:23:58,709 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-23 00:23:58,710 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 00:23:58,710 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 00:23:58,710 INFO L794 eck$LassoCheckResult]: Stem: 98946#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 98852#L-1 havoc main_#res;havoc main_~__retres1~7;havoc main_~__retres1~7;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 98729#L893 havoc start_simulation_#t~ret16, start_simulation_#t~ret17, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 98682#L409 assume 1 == ~m_i~0;~m_st~0 := 0; 98683#L416-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 98775#L421-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 98776#L426-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 98684#L431-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 98685#L436-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 98735#L441-1 assume !(0 == ~M_E~0); 98736#L601-1 assume !(0 == ~T1_E~0); 98739#L606-1 assume !(0 == ~T2_E~0); 98607#L611-1 assume !(0 == ~T3_E~0); 98608#L616-1 assume !(0 == ~T4_E~0); 98455#L621-1 assume !(0 == ~T5_E~0); 98456#L626-1 assume !(0 == ~E_M~0); 98556#L631-1 assume !(0 == ~E_1~0); 98557#L636-1 assume !(0 == ~E_2~0); 98809#L641-1 assume !(0 == ~E_3~0); 98810#L646-1 assume !(0 == ~E_4~0); 98725#L651-1 assume !(0 == ~E_5~0); 98726#L656-1 havoc activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 99026#L294 assume !(1 == ~m_pc~0); 99053#L294-2 is_master_triggered_~__retres1~0 := 0; 99070#L305 is_master_triggered_#res := is_master_triggered_~__retres1~0; 98915#L306 activate_threads_#t~ret9 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 98916#L745 assume !(0 != activate_threads_~tmp~1); 99085#L745-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 98658#L313 assume !(1 == ~t1_pc~0); 98601#L313-2 is_transmit1_triggered_~__retres1~1 := 0; 98657#L324 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 98597#L325 activate_threads_#t~ret10 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 98471#L753 assume !(0 != activate_threads_~tmp___0~0); 98472#L753-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 98476#L332 assume !(1 == ~t2_pc~0); 98694#L332-2 is_transmit2_triggered_~__retres1~2 := 0; 98692#L343 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 98693#L344 activate_threads_#t~ret11 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 98719#L761 assume !(0 != activate_threads_~tmp___1~0); 98720#L761-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 98721#L351 assume !(1 == ~t3_pc~0); 98858#L351-2 is_transmit3_triggered_~__retres1~3 := 0; 98859#L362 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 98880#L363 activate_threads_#t~ret12 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 98887#L769 assume !(0 != activate_threads_~tmp___2~0); 98888#L769-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 98889#L370 assume !(1 == ~t4_pc~0); 99004#L370-2 is_transmit4_triggered_~__retres1~4 := 0; 98999#L381 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 99000#L382 activate_threads_#t~ret13 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 99023#L777 assume !(0 != activate_threads_~tmp___3~0); 99024#L777-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 98545#L389 assume !(1 == ~t5_pc~0); 98510#L389-2 is_transmit5_triggered_~__retres1~5 := 0; 98511#L400 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 98541#L401 activate_threads_#t~ret14 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 98565#L785 assume !(0 != activate_threads_~tmp___4~0); 98566#L785-2 assume !(1 == ~M_E~0); 98567#L669-1 assume !(1 == ~T1_E~0); 98807#L674-1 assume !(1 == ~T2_E~0); 98808#L679-1 assume !(1 == ~T3_E~0); 98723#L684-1 assume !(1 == ~T4_E~0); 98724#L689-1 assume !(1 == ~T5_E~0); 98935#L694-1 assume !(1 == ~E_M~0); 98631#L699-1 assume !(1 == ~E_1~0); 98632#L704-1 assume !(1 == ~E_2~0); 98444#L709-1 assume !(1 == ~E_3~0); 98445#L714-1 assume !(1 == ~E_4~0); 98549#L719-1 assume !(1 == ~E_5~0); 98550#L930-1 assume !false; 101375#L931 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret2, eval_#t~nondet3, eval_~tmp_ndt_1~0, eval_#t~nondet4, eval_~tmp_ndt_2~0, eval_#t~nondet5, eval_~tmp_ndt_3~0, eval_#t~nondet6, eval_~tmp_ndt_4~0, eval_#t~nondet7, eval_~tmp_ndt_5~0, eval_#t~nondet8, eval_~tmp_ndt_6~0, eval_~tmp~0;havoc eval_~tmp~0; 101370#L576 [2018-11-23 00:23:58,710 INFO L796 eck$LassoCheckResult]: Loop: 101370#L576 assume !false; 101365#L497 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 101357#L454 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 101351#L486 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 101343#L487 eval_#t~ret2 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret2;havoc eval_#t~ret2; 101337#L501 assume 0 != eval_~tmp~0; 101332#L501-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0;eval_~tmp_ndt_1~0 := eval_#t~nondet3;havoc eval_#t~nondet3; 101324#L509 assume !(0 != eval_~tmp_ndt_1~0); 101318#L506 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0;eval_~tmp_ndt_2~0 := eval_#t~nondet4;havoc eval_#t~nondet4; 101298#L523 assume !(0 != eval_~tmp_ndt_2~0); 101288#L520 assume !(0 == ~t2_st~0); 101278#L534 assume !(0 == ~t3_st~0); 101269#L548 assume !(0 == ~t4_st~0); 101262#L562 assume !(0 == ~t5_st~0); 101370#L576 [2018-11-23 00:23:58,710 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 00:23:58,710 INFO L82 PathProgramCache]: Analyzing trace with hash -1135942013, now seen corresponding path program 2 times [2018-11-23 00:23:58,710 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 00:23:58,711 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 00:23:58,711 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 00:23:58,711 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-23 00:23:58,711 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 00:23:58,716 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-23 00:23:58,721 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-23 00:23:58,729 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 00:23:58,729 INFO L82 PathProgramCache]: Analyzing trace with hash -11527191, now seen corresponding path program 1 times [2018-11-23 00:23:58,729 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 00:23:58,729 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 00:23:58,729 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 00:23:58,730 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-23 00:23:58,730 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 00:23:58,731 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-23 00:23:58,733 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-23 00:23:58,734 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 00:23:58,734 INFO L82 PathProgramCache]: Analyzing trace with hash 888960747, now seen corresponding path program 1 times [2018-11-23 00:23:58,734 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 00:23:58,734 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 00:23:58,735 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 00:23:58,735 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 00:23:58,735 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 00:23:58,740 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 00:23:58,768 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 00:23:58,768 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 00:23:58,768 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-23 00:23:58,861 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-23 00:23:58,861 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-23 00:23:58,861 INFO L87 Difference]: Start difference. First operand 9941 states and 13593 transitions. cyclomatic complexity: 3664 Second operand 3 states. [2018-11-23 00:23:58,918 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 00:23:58,918 INFO L93 Difference]: Finished difference Result 13023 states and 17719 transitions. [2018-11-23 00:23:58,918 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-23 00:23:58,919 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 13023 states and 17719 transitions. [2018-11-23 00:23:58,957 INFO L131 ngComponentsAnalysis]: Automaton has 12 accepting balls. 12842 [2018-11-23 00:23:58,974 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 13023 states to 13023 states and 17719 transitions. [2018-11-23 00:23:58,974 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 13023 [2018-11-23 00:23:58,980 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 13023 [2018-11-23 00:23:58,981 INFO L73 IsDeterministic]: Start isDeterministic. Operand 13023 states and 17719 transitions. [2018-11-23 00:23:58,988 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-23 00:23:58,988 INFO L705 BuchiCegarLoop]: Abstraction has 13023 states and 17719 transitions. [2018-11-23 00:23:58,994 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 13023 states and 17719 transitions. [2018-11-23 00:23:59,074 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 13023 to 12647. [2018-11-23 00:23:59,074 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 12647 states. [2018-11-23 00:23:59,090 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 12647 states to 12647 states and 17231 transitions. [2018-11-23 00:23:59,090 INFO L728 BuchiCegarLoop]: Abstraction has 12647 states and 17231 transitions. [2018-11-23 00:23:59,091 INFO L608 BuchiCegarLoop]: Abstraction has 12647 states and 17231 transitions. [2018-11-23 00:23:59,091 INFO L442 BuchiCegarLoop]: ======== Iteration 19============ [2018-11-23 00:23:59,091 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 12647 states and 17231 transitions. [2018-11-23 00:23:59,118 INFO L131 ngComponentsAnalysis]: Automaton has 12 accepting balls. 12466 [2018-11-23 00:23:59,118 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-23 00:23:59,118 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-23 00:23:59,119 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 00:23:59,119 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 00:23:59,119 INFO L794 eck$LassoCheckResult]: Stem: 121916#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 121822#L-1 havoc main_#res;havoc main_~__retres1~7;havoc main_~__retres1~7;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 121699#L893 havoc start_simulation_#t~ret16, start_simulation_#t~ret17, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 121654#L409 assume 1 == ~m_i~0;~m_st~0 := 0; 121655#L416-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 121747#L421-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 121748#L426-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 121656#L431-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 121657#L436-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 121705#L441-1 assume !(0 == ~M_E~0); 121706#L601-1 assume !(0 == ~T1_E~0); 121709#L606-1 assume !(0 == ~T2_E~0); 121579#L611-1 assume !(0 == ~T3_E~0); 121580#L616-1 assume !(0 == ~T4_E~0); 121427#L621-1 assume !(0 == ~T5_E~0); 121428#L626-1 assume !(0 == ~E_M~0); 121528#L631-1 assume !(0 == ~E_1~0); 121529#L636-1 assume !(0 == ~E_2~0); 121777#L641-1 assume !(0 == ~E_3~0); 121778#L646-1 assume !(0 == ~E_4~0); 121695#L651-1 assume !(0 == ~E_5~0); 121696#L656-1 havoc activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 122000#L294 assume !(1 == ~m_pc~0); 122027#L294-2 is_master_triggered_~__retres1~0 := 0; 122042#L305 is_master_triggered_#res := is_master_triggered_~__retres1~0; 121886#L306 activate_threads_#t~ret9 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 121887#L745 assume !(0 != activate_threads_~tmp~1); 122057#L745-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 121633#L313 assume !(1 == ~t1_pc~0); 121573#L313-2 is_transmit1_triggered_~__retres1~1 := 0; 121632#L324 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 121569#L325 activate_threads_#t~ret10 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 121443#L753 assume !(0 != activate_threads_~tmp___0~0); 121444#L753-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 121448#L332 assume !(1 == ~t2_pc~0); 121666#L332-2 is_transmit2_triggered_~__retres1~2 := 0; 121664#L343 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 121665#L344 activate_threads_#t~ret11 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 121689#L761 assume !(0 != activate_threads_~tmp___1~0); 121690#L761-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 121691#L351 assume !(1 == ~t3_pc~0); 121828#L351-2 is_transmit3_triggered_~__retres1~3 := 0; 121829#L362 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 121850#L363 activate_threads_#t~ret12 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 121858#L769 assume !(0 != activate_threads_~tmp___2~0); 121859#L769-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 121860#L370 assume !(1 == ~t4_pc~0); 121978#L370-2 is_transmit4_triggered_~__retres1~4 := 0; 121973#L381 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 121974#L382 activate_threads_#t~ret13 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 121997#L777 assume !(0 != activate_threads_~tmp___3~0); 121998#L777-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 121517#L389 assume !(1 == ~t5_pc~0); 121481#L389-2 is_transmit5_triggered_~__retres1~5 := 0; 121482#L400 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 121513#L401 activate_threads_#t~ret14 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 121536#L785 assume !(0 != activate_threads_~tmp___4~0); 121537#L785-2 assume !(1 == ~M_E~0); 121539#L669-1 assume !(1 == ~T1_E~0); 121775#L674-1 assume !(1 == ~T2_E~0); 121776#L679-1 assume !(1 == ~T3_E~0); 121693#L684-1 assume !(1 == ~T4_E~0); 121694#L689-1 assume !(1 == ~T5_E~0); 121906#L694-1 assume !(1 == ~E_M~0); 121603#L699-1 assume !(1 == ~E_1~0); 121604#L704-1 assume !(1 == ~E_2~0); 121416#L709-1 assume !(1 == ~E_3~0); 121417#L714-1 assume !(1 == ~E_4~0); 121521#L719-1 assume !(1 == ~E_5~0); 121522#L930-1 assume !false; 126193#L931 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret2, eval_#t~nondet3, eval_~tmp_ndt_1~0, eval_#t~nondet4, eval_~tmp_ndt_2~0, eval_#t~nondet5, eval_~tmp_ndt_3~0, eval_#t~nondet6, eval_~tmp_ndt_4~0, eval_#t~nondet7, eval_~tmp_ndt_5~0, eval_#t~nondet8, eval_~tmp_ndt_6~0, eval_~tmp~0;havoc eval_~tmp~0; 126192#L576 [2018-11-23 00:23:59,119 INFO L796 eck$LassoCheckResult]: Loop: 126192#L576 assume !false; 126188#L497 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 126149#L454 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 126146#L486 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 126147#L487 eval_#t~ret2 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret2;havoc eval_#t~ret2; 126140#L501 assume 0 != eval_~tmp~0; 126141#L501-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0;eval_~tmp_ndt_1~0 := eval_#t~nondet3;havoc eval_#t~nondet3; 126558#L509 assume !(0 != eval_~tmp_ndt_1~0); 124107#L506 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0;eval_~tmp_ndt_2~0 := eval_#t~nondet4;havoc eval_#t~nondet4; 124097#L523 assume !(0 != eval_~tmp_ndt_2~0); 124087#L520 assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0;eval_~tmp_ndt_3~0 := eval_#t~nondet5;havoc eval_#t~nondet5; 124076#L537 assume !(0 != eval_~tmp_ndt_3~0); 124077#L534 assume !(0 == ~t3_st~0); 124799#L548 assume !(0 == ~t4_st~0); 124790#L562 assume !(0 == ~t5_st~0); 126192#L576 [2018-11-23 00:23:59,120 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 00:23:59,120 INFO L82 PathProgramCache]: Analyzing trace with hash -1135942013, now seen corresponding path program 3 times [2018-11-23 00:23:59,120 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 00:23:59,120 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 00:23:59,120 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 00:23:59,120 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 00:23:59,121 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 00:23:59,124 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-23 00:23:59,129 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-23 00:23:59,138 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 00:23:59,138 INFO L82 PathProgramCache]: Analyzing trace with hash -524557124, now seen corresponding path program 1 times [2018-11-23 00:23:59,138 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 00:23:59,138 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 00:23:59,139 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 00:23:59,139 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-23 00:23:59,139 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 00:23:59,141 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-23 00:23:59,142 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-23 00:23:59,144 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 00:23:59,144 INFO L82 PathProgramCache]: Analyzing trace with hash 1620765178, now seen corresponding path program 1 times [2018-11-23 00:23:59,144 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 00:23:59,144 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 00:23:59,145 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 00:23:59,145 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 00:23:59,145 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 00:23:59,149 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 00:23:59,200 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 00:23:59,200 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 00:23:59,200 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-23 00:23:59,277 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-23 00:23:59,277 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-23 00:23:59,278 INFO L87 Difference]: Start difference. First operand 12647 states and 17231 transitions. cyclomatic complexity: 4596 Second operand 3 states. [2018-11-23 00:23:59,351 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 00:23:59,351 INFO L93 Difference]: Finished difference Result 23117 states and 31385 transitions. [2018-11-23 00:23:59,351 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-23 00:23:59,351 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 23117 states and 31385 transitions. [2018-11-23 00:23:59,416 INFO L131 ngComponentsAnalysis]: Automaton has 12 accepting balls. 22832 [2018-11-23 00:23:59,452 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 23117 states to 23117 states and 31385 transitions. [2018-11-23 00:23:59,452 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 23117 [2018-11-23 00:23:59,461 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 23117 [2018-11-23 00:23:59,461 INFO L73 IsDeterministic]: Start isDeterministic. Operand 23117 states and 31385 transitions. [2018-11-23 00:23:59,474 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-23 00:23:59,474 INFO L705 BuchiCegarLoop]: Abstraction has 23117 states and 31385 transitions. [2018-11-23 00:23:59,484 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 23117 states and 31385 transitions. [2018-11-23 00:23:59,589 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 23117 to 22325. [2018-11-23 00:23:59,589 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 22325 states. [2018-11-23 00:23:59,607 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 22325 states to 22325 states and 30401 transitions. [2018-11-23 00:23:59,607 INFO L728 BuchiCegarLoop]: Abstraction has 22325 states and 30401 transitions. [2018-11-23 00:23:59,607 INFO L608 BuchiCegarLoop]: Abstraction has 22325 states and 30401 transitions. [2018-11-23 00:23:59,607 INFO L442 BuchiCegarLoop]: ======== Iteration 20============ [2018-11-23 00:23:59,608 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 22325 states and 30401 transitions. [2018-11-23 00:23:59,679 INFO L131 ngComponentsAnalysis]: Automaton has 12 accepting balls. 22040 [2018-11-23 00:23:59,679 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-23 00:23:59,679 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-23 00:23:59,679 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 00:23:59,679 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 00:23:59,680 INFO L794 eck$LassoCheckResult]: Stem: 157689#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 157593#L-1 havoc main_#res;havoc main_~__retres1~7;havoc main_~__retres1~7;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 157466#L893 havoc start_simulation_#t~ret16, start_simulation_#t~ret17, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 157420#L409 assume 1 == ~m_i~0;~m_st~0 := 0; 157421#L416-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 157516#L421-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 157517#L426-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 157422#L431-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 157423#L436-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 157473#L441-1 assume !(0 == ~M_E~0); 157474#L601-1 assume !(0 == ~T1_E~0); 157477#L606-1 assume !(0 == ~T2_E~0); 157347#L611-1 assume !(0 == ~T3_E~0); 157348#L616-1 assume !(0 == ~T4_E~0); 157199#L621-1 assume !(0 == ~T5_E~0); 157200#L626-1 assume !(0 == ~E_M~0); 157294#L631-1 assume !(0 == ~E_1~0); 157295#L636-1 assume !(0 == ~E_2~0); 157548#L641-1 assume !(0 == ~E_3~0); 157549#L646-1 assume !(0 == ~E_4~0); 157462#L651-1 assume !(0 == ~E_5~0); 157463#L656-1 havoc activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 157778#L294 assume !(1 == ~m_pc~0); 157813#L294-2 is_master_triggered_~__retres1~0 := 0; 157834#L305 is_master_triggered_#res := is_master_triggered_~__retres1~0; 157658#L306 activate_threads_#t~ret9 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 157659#L745 assume !(0 != activate_threads_~tmp~1); 157851#L745-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 157402#L313 assume !(1 == ~t1_pc~0); 157341#L313-2 is_transmit1_triggered_~__retres1~1 := 0; 157401#L324 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 157337#L325 activate_threads_#t~ret10 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 157214#L753 assume !(0 != activate_threads_~tmp___0~0); 157215#L753-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 157220#L332 assume !(1 == ~t2_pc~0); 157432#L332-2 is_transmit2_triggered_~__retres1~2 := 0; 157430#L343 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 157431#L344 activate_threads_#t~ret11 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 157456#L761 assume !(0 != activate_threads_~tmp___1~0); 157457#L761-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 157458#L351 assume !(1 == ~t3_pc~0); 157599#L351-2 is_transmit3_triggered_~__retres1~3 := 0; 157600#L362 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 157621#L363 activate_threads_#t~ret12 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 157629#L769 assume !(0 != activate_threads_~tmp___2~0); 157630#L769-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 157631#L370 assume !(1 == ~t4_pc~0); 157758#L370-2 is_transmit4_triggered_~__retres1~4 := 0; 157753#L381 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 157754#L382 activate_threads_#t~ret13 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 157775#L777 assume !(0 != activate_threads_~tmp___3~0); 157776#L777-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 157283#L389 assume !(1 == ~t5_pc~0); 157252#L389-2 is_transmit5_triggered_~__retres1~5 := 0; 157253#L400 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 157280#L401 activate_threads_#t~ret14 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 157302#L785 assume !(0 != activate_threads_~tmp___4~0); 157303#L785-2 assume !(1 == ~M_E~0); 157305#L669-1 assume !(1 == ~T1_E~0); 157546#L674-1 assume !(1 == ~T2_E~0); 157547#L679-1 assume !(1 == ~T3_E~0); 157460#L684-1 assume !(1 == ~T4_E~0); 157461#L689-1 assume !(1 == ~T5_E~0); 157678#L694-1 assume !(1 == ~E_M~0); 157371#L699-1 assume !(1 == ~E_1~0); 157372#L704-1 assume !(1 == ~E_2~0); 157188#L709-1 assume !(1 == ~E_3~0); 157189#L714-1 assume !(1 == ~E_4~0); 157287#L719-1 assume !(1 == ~E_5~0); 157288#L930-1 assume !false; 161305#L931 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret2, eval_#t~nondet3, eval_~tmp_ndt_1~0, eval_#t~nondet4, eval_~tmp_ndt_2~0, eval_#t~nondet5, eval_~tmp_ndt_3~0, eval_#t~nondet6, eval_~tmp_ndt_4~0, eval_#t~nondet7, eval_~tmp_ndt_5~0, eval_#t~nondet8, eval_~tmp_ndt_6~0, eval_~tmp~0;havoc eval_~tmp~0; 161299#L576 [2018-11-23 00:23:59,680 INFO L796 eck$LassoCheckResult]: Loop: 161299#L576 assume !false; 161294#L497 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 161288#L454 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 161283#L486 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 161279#L487 eval_#t~ret2 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret2;havoc eval_#t~ret2; 161269#L501 assume 0 != eval_~tmp~0; 161258#L501-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0;eval_~tmp_ndt_1~0 := eval_#t~nondet3;havoc eval_#t~nondet3; 161249#L509 assume !(0 != eval_~tmp_ndt_1~0); 160648#L506 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0;eval_~tmp_ndt_2~0 := eval_#t~nondet4;havoc eval_#t~nondet4; 160646#L523 assume !(0 != eval_~tmp_ndt_2~0); 160644#L520 assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0;eval_~tmp_ndt_3~0 := eval_#t~nondet5;havoc eval_#t~nondet5; 160641#L537 assume !(0 != eval_~tmp_ndt_3~0); 160642#L534 assume 0 == ~t3_st~0;havoc eval_~tmp_ndt_4~0;eval_~tmp_ndt_4~0 := eval_#t~nondet6;havoc eval_#t~nondet6; 161323#L551 assume !(0 != eval_~tmp_ndt_4~0); 161316#L548 assume !(0 == ~t4_st~0); 161309#L562 assume !(0 == ~t5_st~0); 161299#L576 [2018-11-23 00:23:59,680 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 00:23:59,680 INFO L82 PathProgramCache]: Analyzing trace with hash -1135942013, now seen corresponding path program 4 times [2018-11-23 00:23:59,680 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 00:23:59,680 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 00:23:59,681 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 00:23:59,681 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 00:23:59,681 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 00:23:59,685 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-23 00:23:59,690 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-23 00:23:59,699 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 00:23:59,699 INFO L82 PathProgramCache]: Analyzing trace with hash 913205966, now seen corresponding path program 1 times [2018-11-23 00:23:59,699 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 00:23:59,699 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 00:23:59,700 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 00:23:59,700 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-23 00:23:59,700 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 00:23:59,702 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-23 00:23:59,703 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-23 00:23:59,705 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 00:23:59,705 INFO L82 PathProgramCache]: Analyzing trace with hash -1301279408, now seen corresponding path program 1 times [2018-11-23 00:23:59,705 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 00:23:59,705 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 00:23:59,706 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 00:23:59,706 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 00:23:59,706 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 00:23:59,710 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 00:23:59,736 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 00:23:59,736 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 00:23:59,736 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-23 00:23:59,842 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-23 00:23:59,842 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-23 00:23:59,843 INFO L87 Difference]: Start difference. First operand 22325 states and 30401 transitions. cyclomatic complexity: 8088 Second operand 3 states. [2018-11-23 00:23:59,947 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 00:23:59,947 INFO L93 Difference]: Finished difference Result 29707 states and 40327 transitions. [2018-11-23 00:23:59,948 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-23 00:23:59,949 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 29707 states and 40327 transitions. [2018-11-23 00:24:00,038 INFO L131 ngComponentsAnalysis]: Automaton has 12 accepting balls. 29366 [2018-11-23 00:24:00,096 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 29707 states to 29707 states and 40327 transitions. [2018-11-23 00:24:00,097 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 29707 [2018-11-23 00:24:00,110 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 29707 [2018-11-23 00:24:00,110 INFO L73 IsDeterministic]: Start isDeterministic. Operand 29707 states and 40327 transitions. [2018-11-23 00:24:00,121 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-23 00:24:00,122 INFO L705 BuchiCegarLoop]: Abstraction has 29707 states and 40327 transitions. [2018-11-23 00:24:00,134 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 29707 states and 40327 transitions. [2018-11-23 00:24:00,295 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 29707 to 29227. [2018-11-23 00:24:00,295 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 29227 states. [2018-11-23 00:24:00,333 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 29227 states to 29227 states and 39703 transitions. [2018-11-23 00:24:00,333 INFO L728 BuchiCegarLoop]: Abstraction has 29227 states and 39703 transitions. [2018-11-23 00:24:00,333 INFO L608 BuchiCegarLoop]: Abstraction has 29227 states and 39703 transitions. [2018-11-23 00:24:00,334 INFO L442 BuchiCegarLoop]: ======== Iteration 21============ [2018-11-23 00:24:00,334 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 29227 states and 39703 transitions. [2018-11-23 00:24:00,386 INFO L131 ngComponentsAnalysis]: Automaton has 12 accepting balls. 28886 [2018-11-23 00:24:00,387 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-23 00:24:00,387 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-23 00:24:00,387 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 00:24:00,387 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 00:24:00,388 INFO L794 eck$LassoCheckResult]: Stem: 209761#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 209660#L-1 havoc main_#res;havoc main_~__retres1~7;havoc main_~__retres1~7;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 209523#L893 havoc start_simulation_#t~ret16, start_simulation_#t~ret17, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 209477#L409 assume 1 == ~m_i~0;~m_st~0 := 0; 209478#L416-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 209576#L421-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 209577#L426-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 209481#L431-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 209482#L436-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 209532#L441-1 assume !(0 == ~M_E~0); 209533#L601-1 assume !(0 == ~T1_E~0); 209535#L606-1 assume !(0 == ~T2_E~0); 209396#L611-1 assume !(0 == ~T3_E~0); 209397#L616-1 assume !(0 == ~T4_E~0); 209239#L621-1 assume !(0 == ~T5_E~0); 209240#L626-1 assume !(0 == ~E_M~0); 209340#L631-1 assume !(0 == ~E_1~0); 209341#L636-1 assume !(0 == ~E_2~0); 209603#L641-1 assume !(0 == ~E_3~0); 209604#L646-1 assume !(0 == ~E_4~0); 209519#L651-1 assume !(0 == ~E_5~0); 209520#L656-1 havoc activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 209860#L294 assume !(1 == ~m_pc~0); 209895#L294-2 is_master_triggered_~__retres1~0 := 0; 209916#L305 is_master_triggered_#res := is_master_triggered_~__retres1~0; 209733#L306 activate_threads_#t~ret9 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 209734#L745 assume !(0 != activate_threads_~tmp~1); 209927#L745-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 209450#L313 assume !(1 == ~t1_pc~0); 209388#L313-2 is_transmit1_triggered_~__retres1~1 := 0; 209449#L324 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 209385#L325 activate_threads_#t~ret10 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 209256#L753 assume !(0 != activate_threads_~tmp___0~0); 209257#L753-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 209260#L332 assume !(1 == ~t2_pc~0); 209489#L332-2 is_transmit2_triggered_~__retres1~2 := 0; 209487#L343 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 209488#L344 activate_threads_#t~ret11 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 209513#L761 assume !(0 != activate_threads_~tmp___1~0); 209514#L761-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 209515#L351 assume !(1 == ~t3_pc~0); 209667#L351-2 is_transmit3_triggered_~__retres1~3 := 0; 209668#L362 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 209692#L363 activate_threads_#t~ret12 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 209702#L769 assume !(0 != activate_threads_~tmp___2~0); 209703#L769-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 209704#L370 assume !(1 == ~t4_pc~0); 209838#L370-2 is_transmit4_triggered_~__retres1~4 := 0; 209836#L381 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 209837#L382 activate_threads_#t~ret13 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 209857#L777 assume !(0 != activate_threads_~tmp___3~0); 209858#L777-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 209330#L389 assume !(1 == ~t5_pc~0); 209297#L389-2 is_transmit5_triggered_~__retres1~5 := 0; 209298#L400 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 209327#L401 activate_threads_#t~ret14 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 209350#L785 assume !(0 != activate_threads_~tmp___4~0); 209351#L785-2 assume !(1 == ~M_E~0); 209352#L669-1 assume !(1 == ~T1_E~0); 209601#L674-1 assume !(1 == ~T2_E~0); 209602#L679-1 assume !(1 == ~T3_E~0); 209517#L684-1 assume !(1 == ~T4_E~0); 209518#L689-1 assume !(1 == ~T5_E~0); 209750#L694-1 assume !(1 == ~E_M~0); 209421#L699-1 assume !(1 == ~E_1~0); 209422#L704-1 assume !(1 == ~E_2~0); 209228#L709-1 assume !(1 == ~E_3~0); 209229#L714-1 assume !(1 == ~E_4~0); 209333#L719-1 assume !(1 == ~E_5~0); 209334#L930-1 assume !false; 226022#L931 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret2, eval_#t~nondet3, eval_~tmp_ndt_1~0, eval_#t~nondet4, eval_~tmp_ndt_2~0, eval_#t~nondet5, eval_~tmp_ndt_3~0, eval_#t~nondet6, eval_~tmp_ndt_4~0, eval_#t~nondet7, eval_~tmp_ndt_5~0, eval_#t~nondet8, eval_~tmp_ndt_6~0, eval_~tmp~0;havoc eval_~tmp~0; 226021#L576 [2018-11-23 00:24:00,388 INFO L796 eck$LassoCheckResult]: Loop: 226021#L576 assume !false; 226020#L497 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 226017#L454 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 226015#L486 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 226013#L487 eval_#t~ret2 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret2;havoc eval_#t~ret2; 226011#L501 assume 0 != eval_~tmp~0; 226008#L501-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0;eval_~tmp_ndt_1~0 := eval_#t~nondet3;havoc eval_#t~nondet3; 226005#L509 assume !(0 != eval_~tmp_ndt_1~0); 226001#L506 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0;eval_~tmp_ndt_2~0 := eval_#t~nondet4;havoc eval_#t~nondet4; 225998#L523 assume !(0 != eval_~tmp_ndt_2~0); 225996#L520 assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0;eval_~tmp_ndt_3~0 := eval_#t~nondet5;havoc eval_#t~nondet5; 225994#L537 assume !(0 != eval_~tmp_ndt_3~0); 225989#L534 assume 0 == ~t3_st~0;havoc eval_~tmp_ndt_4~0;eval_~tmp_ndt_4~0 := eval_#t~nondet6;havoc eval_#t~nondet6; 225932#L551 assume !(0 != eval_~tmp_ndt_4~0); 225987#L548 assume 0 == ~t4_st~0;havoc eval_~tmp_ndt_5~0;eval_~tmp_ndt_5~0 := eval_#t~nondet7;havoc eval_#t~nondet7; 226027#L565 assume !(0 != eval_~tmp_ndt_5~0); 226026#L562 assume !(0 == ~t5_st~0); 226021#L576 [2018-11-23 00:24:00,388 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 00:24:00,388 INFO L82 PathProgramCache]: Analyzing trace with hash -1135942013, now seen corresponding path program 5 times [2018-11-23 00:24:00,388 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 00:24:00,388 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 00:24:00,389 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 00:24:00,389 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 00:24:00,390 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 00:24:00,394 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-23 00:24:00,398 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-23 00:24:00,408 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 00:24:00,408 INFO L82 PathProgramCache]: Analyzing trace with hash -1755558441, now seen corresponding path program 1 times [2018-11-23 00:24:00,408 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 00:24:00,408 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 00:24:00,409 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 00:24:00,409 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-23 00:24:00,409 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 00:24:00,410 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-23 00:24:00,412 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-23 00:24:00,413 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 00:24:00,414 INFO L82 PathProgramCache]: Analyzing trace with hash -1685128299, now seen corresponding path program 1 times [2018-11-23 00:24:00,414 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 00:24:00,414 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 00:24:00,414 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 00:24:00,414 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 00:24:00,415 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 00:24:00,419 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 00:24:00,455 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 00:24:00,456 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 00:24:00,456 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2018-11-23 00:24:00,596 WARN L180 SmtUtils]: Spent 138.00 ms on a formula simplification. DAG size of input: 44 DAG size of output: 42 [2018-11-23 00:24:00,662 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-23 00:24:00,662 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-23 00:24:00,662 INFO L87 Difference]: Start difference. First operand 29227 states and 39703 transitions. cyclomatic complexity: 10488 Second operand 3 states. [2018-11-23 00:24:00,777 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 00:24:00,777 INFO L93 Difference]: Finished difference Result 50701 states and 68749 transitions. [2018-11-23 00:24:00,777 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-23 00:24:00,778 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 50701 states and 68749 transitions. [2018-11-23 00:24:00,892 INFO L131 ngComponentsAnalysis]: Automaton has 12 accepting balls. 50096 [2018-11-23 00:24:00,968 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 50701 states to 50701 states and 68749 transitions. [2018-11-23 00:24:00,969 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 50701 [2018-11-23 00:24:00,994 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 50701 [2018-11-23 00:24:00,994 INFO L73 IsDeterministic]: Start isDeterministic. Operand 50701 states and 68749 transitions. [2018-11-23 00:24:01,014 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-23 00:24:01,014 INFO L705 BuchiCegarLoop]: Abstraction has 50701 states and 68749 transitions. [2018-11-23 00:24:01,031 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 50701 states and 68749 transitions. [2018-11-23 00:24:01,359 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 50701 to 50269. [2018-11-23 00:24:01,359 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 50269 states. [2018-11-23 00:24:01,405 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 50269 states to 50269 states and 68317 transitions. [2018-11-23 00:24:01,405 INFO L728 BuchiCegarLoop]: Abstraction has 50269 states and 68317 transitions. [2018-11-23 00:24:01,405 INFO L608 BuchiCegarLoop]: Abstraction has 50269 states and 68317 transitions. [2018-11-23 00:24:01,405 INFO L442 BuchiCegarLoop]: ======== Iteration 22============ [2018-11-23 00:24:01,405 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 50269 states and 68317 transitions. [2018-11-23 00:24:01,495 INFO L131 ngComponentsAnalysis]: Automaton has 12 accepting balls. 49664 [2018-11-23 00:24:01,495 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-23 00:24:01,496 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-23 00:24:01,496 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 00:24:01,496 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 00:24:01,497 INFO L794 eck$LassoCheckResult]: Stem: 289683#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 289584#L-1 havoc main_#res;havoc main_~__retres1~7;havoc main_~__retres1~7;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 289455#L893 havoc start_simulation_#t~ret16, start_simulation_#t~ret17, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 289409#L409 assume 1 == ~m_i~0;~m_st~0 := 0; 289410#L416-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 289506#L421-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 289507#L426-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 289413#L431-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 289414#L436-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 289464#L441-1 assume !(0 == ~M_E~0); 289465#L601-1 assume !(0 == ~T1_E~0); 289467#L606-1 assume !(0 == ~T2_E~0); 289331#L611-1 assume !(0 == ~T3_E~0); 289332#L616-1 assume !(0 == ~T4_E~0); 289175#L621-1 assume !(0 == ~T5_E~0); 289176#L626-1 assume !(0 == ~E_M~0); 289278#L631-1 assume !(0 == ~E_1~0); 289279#L636-1 assume !(0 == ~E_2~0); 289535#L641-1 assume !(0 == ~E_3~0); 289536#L646-1 assume !(0 == ~E_4~0); 289451#L651-1 assume !(0 == ~E_5~0); 289452#L656-1 havoc activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 289780#L294 assume !(1 == ~m_pc~0); 289820#L294-2 is_master_triggered_~__retres1~0 := 0; 289840#L305 is_master_triggered_#res := is_master_triggered_~__retres1~0; 289656#L306 activate_threads_#t~ret9 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 289657#L745 assume !(0 != activate_threads_~tmp~1); 289855#L745-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 289385#L313 assume !(1 == ~t1_pc~0); 289323#L313-2 is_transmit1_triggered_~__retres1~1 := 0; 289384#L324 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 289320#L325 activate_threads_#t~ret10 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 289192#L753 assume !(0 != activate_threads_~tmp___0~0); 289193#L753-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 289196#L332 assume !(1 == ~t2_pc~0); 289421#L332-2 is_transmit2_triggered_~__retres1~2 := 0; 289419#L343 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 289420#L344 activate_threads_#t~ret11 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 289444#L761 assume !(0 != activate_threads_~tmp___1~0); 289445#L761-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 289446#L351 assume !(1 == ~t3_pc~0); 289590#L351-2 is_transmit3_triggered_~__retres1~3 := 0; 289591#L362 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 289615#L363 activate_threads_#t~ret12 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 289624#L769 assume !(0 != activate_threads_~tmp___2~0); 289625#L769-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 289626#L370 assume !(1 == ~t4_pc~0); 289755#L370-2 is_transmit4_triggered_~__retres1~4 := 0; 289753#L381 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 289754#L382 activate_threads_#t~ret13 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 289777#L777 assume !(0 != activate_threads_~tmp___3~0); 289778#L777-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 289266#L389 assume !(1 == ~t5_pc~0); 289234#L389-2 is_transmit5_triggered_~__retres1~5 := 0; 289235#L400 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 289263#L401 activate_threads_#t~ret14 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 289287#L785 assume !(0 != activate_threads_~tmp___4~0); 289288#L785-2 assume !(1 == ~M_E~0); 289289#L669-1 assume !(1 == ~T1_E~0); 289533#L674-1 assume !(1 == ~T2_E~0); 289534#L679-1 assume !(1 == ~T3_E~0); 289449#L684-1 assume !(1 == ~T4_E~0); 289450#L689-1 assume !(1 == ~T5_E~0); 289673#L694-1 assume !(1 == ~E_M~0); 289356#L699-1 assume !(1 == ~E_1~0); 289357#L704-1 assume !(1 == ~E_2~0); 289164#L709-1 assume !(1 == ~E_3~0); 289165#L714-1 assume !(1 == ~E_4~0); 289270#L719-1 assume !(1 == ~E_5~0); 289271#L930-1 assume !false; 305020#L931 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret2, eval_#t~nondet3, eval_~tmp_ndt_1~0, eval_#t~nondet4, eval_~tmp_ndt_2~0, eval_#t~nondet5, eval_~tmp_ndt_3~0, eval_#t~nondet6, eval_~tmp_ndt_4~0, eval_#t~nondet7, eval_~tmp_ndt_5~0, eval_#t~nondet8, eval_~tmp_ndt_6~0, eval_~tmp~0;havoc eval_~tmp~0; 305018#L576 [2018-11-23 00:24:01,497 INFO L796 eck$LassoCheckResult]: Loop: 305018#L576 assume !false; 305015#L497 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 305012#L454 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 305010#L486 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 305008#L487 eval_#t~ret2 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret2;havoc eval_#t~ret2; 305006#L501 assume 0 != eval_~tmp~0; 305003#L501-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0;eval_~tmp_ndt_1~0 := eval_#t~nondet3;havoc eval_#t~nondet3; 305000#L509 assume !(0 != eval_~tmp_ndt_1~0); 304998#L506 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0;eval_~tmp_ndt_2~0 := eval_#t~nondet4;havoc eval_#t~nondet4; 304664#L523 assume !(0 != eval_~tmp_ndt_2~0); 304995#L520 assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0;eval_~tmp_ndt_3~0 := eval_#t~nondet5;havoc eval_#t~nondet5; 304993#L537 assume !(0 != eval_~tmp_ndt_3~0); 304992#L534 assume 0 == ~t3_st~0;havoc eval_~tmp_ndt_4~0;eval_~tmp_ndt_4~0 := eval_#t~nondet6;havoc eval_#t~nondet6; 304978#L551 assume !(0 != eval_~tmp_ndt_4~0); 304989#L548 assume 0 == ~t4_st~0;havoc eval_~tmp_ndt_5~0;eval_~tmp_ndt_5~0 := eval_#t~nondet7;havoc eval_#t~nondet7; 306490#L565 assume !(0 != eval_~tmp_ndt_5~0); 305024#L562 assume 0 == ~t5_st~0;havoc eval_~tmp_ndt_6~0;eval_~tmp_ndt_6~0 := eval_#t~nondet8;havoc eval_#t~nondet8; 305021#L579 assume !(0 != eval_~tmp_ndt_6~0); 305018#L576 [2018-11-23 00:24:01,497 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 00:24:01,497 INFO L82 PathProgramCache]: Analyzing trace with hash -1135942013, now seen corresponding path program 6 times [2018-11-23 00:24:01,497 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 00:24:01,497 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 00:24:01,498 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 00:24:01,498 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 00:24:01,498 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 00:24:01,501 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-23 00:24:01,512 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-23 00:24:01,517 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 00:24:01,518 INFO L82 PathProgramCache]: Analyzing trace with hash 1412259251, now seen corresponding path program 1 times [2018-11-23 00:24:01,518 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 00:24:01,518 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 00:24:01,518 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 00:24:01,518 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-23 00:24:01,519 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 00:24:01,520 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-23 00:24:01,521 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-23 00:24:01,523 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 00:24:01,523 INFO L82 PathProgramCache]: Analyzing trace with hash -699373643, now seen corresponding path program 1 times [2018-11-23 00:24:01,523 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 00:24:01,523 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 00:24:01,524 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 00:24:01,524 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 00:24:01,524 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 00:24:01,528 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-23 00:24:01,533 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-23 00:24:01,960 WARN L180 SmtUtils]: Spent 316.00 ms on a formula simplification. DAG size of input: 198 DAG size of output: 132 ----- class de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder.RCFGBacktranslator [?] ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; [?] havoc main_#res;havoc main_~__retres1~7;havoc main_~__retres1~7;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; [?] havoc start_simulation_#t~ret16, start_simulation_#t~ret17, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; [?] assume 1 == ~m_i~0;~m_st~0 := 0; [?] assume 1 == ~t1_i~0;~t1_st~0 := 0; [?] assume 1 == ~t2_i~0;~t2_st~0 := 0; [?] assume 1 == ~t3_i~0;~t3_st~0 := 0; [?] assume 1 == ~t4_i~0;~t4_st~0 := 0; [?] assume 1 == ~t5_i~0;~t5_st~0 := 0; [?] assume !(0 == ~M_E~0); [?] assume !(0 == ~T1_E~0); [?] assume !(0 == ~T2_E~0); [?] assume !(0 == ~T3_E~0); [?] assume !(0 == ~T4_E~0); [?] assume !(0 == ~T5_E~0); [?] assume !(0 == ~E_M~0); [?] assume !(0 == ~E_1~0); [?] assume !(0 == ~E_2~0); [?] assume !(0 == ~E_3~0); [?] assume !(0 == ~E_4~0); [?] assume !(0 == ~E_5~0); [?] havoc activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; [?] assume !(1 == ~m_pc~0); [?] is_master_triggered_~__retres1~0 := 0; [?] is_master_triggered_#res := is_master_triggered_~__retres1~0; [?] activate_threads_#t~ret9 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; [?] assume !(0 != activate_threads_~tmp~1); [?] havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; [?] assume !(1 == ~t1_pc~0); [?] is_transmit1_triggered_~__retres1~1 := 0; [?] is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; [?] activate_threads_#t~ret10 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; [?] assume !(0 != activate_threads_~tmp___0~0); [?] havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; [?] assume !(1 == ~t2_pc~0); [?] is_transmit2_triggered_~__retres1~2 := 0; [?] is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; [?] activate_threads_#t~ret11 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; [?] assume !(0 != activate_threads_~tmp___1~0); [?] havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; [?] assume !(1 == ~t3_pc~0); [?] is_transmit3_triggered_~__retres1~3 := 0; [?] is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; [?] activate_threads_#t~ret12 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; [?] assume !(0 != activate_threads_~tmp___2~0); [?] havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; [?] assume !(1 == ~t4_pc~0); [?] is_transmit4_triggered_~__retres1~4 := 0; [?] is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; [?] activate_threads_#t~ret13 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; [?] assume !(0 != activate_threads_~tmp___3~0); [?] havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; [?] assume !(1 == ~t5_pc~0); [?] is_transmit5_triggered_~__retres1~5 := 0; [?] is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; [?] activate_threads_#t~ret14 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; [?] assume !(0 != activate_threads_~tmp___4~0); [?] assume !(1 == ~M_E~0); [?] assume !(1 == ~T1_E~0); [?] assume !(1 == ~T2_E~0); [?] assume !(1 == ~T3_E~0); [?] assume !(1 == ~T4_E~0); [?] assume !(1 == ~T5_E~0); [?] assume !(1 == ~E_M~0); [?] assume !(1 == ~E_1~0); [?] assume !(1 == ~E_2~0); [?] assume !(1 == ~E_3~0); [?] assume !(1 == ~E_4~0); [?] assume !(1 == ~E_5~0); [?] assume !false; [?] start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret2, eval_#t~nondet3, eval_~tmp_ndt_1~0, eval_#t~nondet4, eval_~tmp_ndt_2~0, eval_#t~nondet5, eval_~tmp_ndt_3~0, eval_#t~nondet6, eval_~tmp_ndt_4~0, eval_#t~nondet7, eval_~tmp_ndt_5~0, eval_#t~nondet8, eval_~tmp_ndt_6~0, eval_~tmp~0;havoc eval_~tmp~0; [L14] ~m_pc~0 := 0; [L15] ~t1_pc~0 := 0; [L16] ~t2_pc~0 := 0; [L17] ~t3_pc~0 := 0; [L18] ~t4_pc~0 := 0; [L19] ~t5_pc~0 := 0; [L20] ~m_st~0 := 0; [L21] ~t1_st~0 := 0; [L22] ~t2_st~0 := 0; [L23] ~t3_st~0 := 0; [L24] ~t4_st~0 := 0; [L25] ~t5_st~0 := 0; [L26] ~m_i~0 := 0; [L27] ~t1_i~0 := 0; [L28] ~t2_i~0 := 0; [L29] ~t3_i~0 := 0; [L30] ~t4_i~0 := 0; [L31] ~t5_i~0 := 0; [L32] ~M_E~0 := 2; [L33] ~T1_E~0 := 2; [L34] ~T2_E~0 := 2; [L35] ~T3_E~0 := 2; [L36] ~T4_E~0 := 2; [L37] ~T5_E~0 := 2; [L38] ~E_M~0 := 2; [L39] ~E_1~0 := 2; [L40] ~E_2~0 := 2; [L41] ~E_3~0 := 2; [L42] ~E_4~0 := 2; [L43] ~E_5~0 := 2; [L51] ~token~0 := 0; [L53] ~local~0 := 0; [?] havoc main_#res; [?] havoc main_~__retres1~7; [L975] havoc main_~__retres1~7; [L886] ~m_i~0 := 1; [L887] ~t1_i~0 := 1; [L888] ~t2_i~0 := 1; [L889] ~t3_i~0 := 1; [L890] ~t4_i~0 := 1; [L891] ~t5_i~0 := 1; [L980] havoc start_simulation_#t~ret16, start_simulation_#t~ret17, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1; [L916] havoc start_simulation_~kernel_st~0; [L917] havoc start_simulation_~tmp~3; [L918] havoc start_simulation_~tmp___0~1; [L922] start_simulation_~kernel_st~0 := 0; [L416-L420] assume 1 == ~m_i~0; [L417] ~m_st~0 := 0; [L421-L425] assume 1 == ~t1_i~0; [L422] ~t1_st~0 := 0; [L426-L430] assume 1 == ~t2_i~0; [L427] ~t2_st~0 := 0; [L431-L435] assume 1 == ~t3_i~0; [L432] ~t3_st~0 := 0; [L436-L440] assume 1 == ~t4_i~0; [L437] ~t4_st~0 := 0; [L441-L445] assume 1 == ~t5_i~0; [L442] ~t5_st~0 := 0; [L601-L605] assume !(0 == ~M_E~0); [L606-L610] assume !(0 == ~T1_E~0); [L611-L615] assume !(0 == ~T2_E~0); [L616-L620] assume !(0 == ~T3_E~0); [L621-L625] assume !(0 == ~T4_E~0); [L626-L630] assume !(0 == ~T5_E~0); [L631-L635] assume !(0 == ~E_M~0); [L636-L640] assume !(0 == ~E_1~0); [L641-L645] assume !(0 == ~E_2~0); [L646-L650] assume !(0 == ~E_3~0); [L651-L655] assume !(0 == ~E_4~0); [L656-L660] assume !(0 == ~E_5~0); [L926] havoc activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0; [L734] havoc activate_threads_~tmp~1; [L735] havoc activate_threads_~tmp___0~0; [L736] havoc activate_threads_~tmp___1~0; [L737] havoc activate_threads_~tmp___2~0; [L738] havoc activate_threads_~tmp___3~0; [L739] havoc activate_threads_~tmp___4~0; [L743] havoc is_master_triggered_#res; [L743] havoc is_master_triggered_~__retres1~0; [L291] havoc is_master_triggered_~__retres1~0; [L294-L303] assume !(1 == ~m_pc~0); [L304] is_master_triggered_~__retres1~0 := 0; [L306] is_master_triggered_#res := is_master_triggered_~__retres1~0; [L743] activate_threads_#t~ret9 := is_master_triggered_#res; [L743] activate_threads_~tmp~1 := activate_threads_#t~ret9; [L743] havoc activate_threads_#t~ret9; [L745-L749] assume !(0 != activate_threads_~tmp~1); [L751] havoc is_transmit1_triggered_#res; [L751] havoc is_transmit1_triggered_~__retres1~1; [L310] havoc is_transmit1_triggered_~__retres1~1; [L313-L322] assume !(1 == ~t1_pc~0); [L323] is_transmit1_triggered_~__retres1~1 := 0; [L325] is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; [L751] activate_threads_#t~ret10 := is_transmit1_triggered_#res; [L751] activate_threads_~tmp___0~0 := activate_threads_#t~ret10; [L751] havoc activate_threads_#t~ret10; [L753-L757] assume !(0 != activate_threads_~tmp___0~0); [L759] havoc is_transmit2_triggered_#res; [L759] havoc is_transmit2_triggered_~__retres1~2; [L329] havoc is_transmit2_triggered_~__retres1~2; [L332-L341] assume !(1 == ~t2_pc~0); [L342] is_transmit2_triggered_~__retres1~2 := 0; [L344] is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; [L759] activate_threads_#t~ret11 := is_transmit2_triggered_#res; [L759] activate_threads_~tmp___1~0 := activate_threads_#t~ret11; [L759] havoc activate_threads_#t~ret11; [L761-L765] assume !(0 != activate_threads_~tmp___1~0); [L767] havoc is_transmit3_triggered_#res; [L767] havoc is_transmit3_triggered_~__retres1~3; [L348] havoc is_transmit3_triggered_~__retres1~3; [L351-L360] assume !(1 == ~t3_pc~0); [L361] is_transmit3_triggered_~__retres1~3 := 0; [L363] is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; [L767] activate_threads_#t~ret12 := is_transmit3_triggered_#res; [L767] activate_threads_~tmp___2~0 := activate_threads_#t~ret12; [L767] havoc activate_threads_#t~ret12; [L769-L773] assume !(0 != activate_threads_~tmp___2~0); [L775] havoc is_transmit4_triggered_#res; [L775] havoc is_transmit4_triggered_~__retres1~4; [L367] havoc is_transmit4_triggered_~__retres1~4; [L370-L379] assume !(1 == ~t4_pc~0); [L380] is_transmit4_triggered_~__retres1~4 := 0; [L382] is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; [L775] activate_threads_#t~ret13 := is_transmit4_triggered_#res; [L775] activate_threads_~tmp___3~0 := activate_threads_#t~ret13; [L775] havoc activate_threads_#t~ret13; [L777-L781] assume !(0 != activate_threads_~tmp___3~0); [L783] havoc is_transmit5_triggered_#res; [L783] havoc is_transmit5_triggered_~__retres1~5; [L386] havoc is_transmit5_triggered_~__retres1~5; [L389-L398] assume !(1 == ~t5_pc~0); [L399] is_transmit5_triggered_~__retres1~5 := 0; [L401] is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; [L783] activate_threads_#t~ret14 := is_transmit5_triggered_#res; [L783] activate_threads_~tmp___4~0 := activate_threads_#t~ret14; [L783] havoc activate_threads_#t~ret14; [L785-L789] assume !(0 != activate_threads_~tmp___4~0); [L669-L673] assume !(1 == ~M_E~0); [L674-L678] assume !(1 == ~T1_E~0); [L679-L683] assume !(1 == ~T2_E~0); [L684-L688] assume !(1 == ~T3_E~0); [L689-L693] assume !(1 == ~T4_E~0); [L694-L698] assume !(1 == ~T5_E~0); [L699-L703] assume !(1 == ~E_M~0); [L704-L708] assume !(1 == ~E_1~0); [L709-L713] assume !(1 == ~E_2~0); [L714-L718] assume !(1 == ~E_3~0); [L719-L723] assume !(1 == ~E_4~0); [L724-L728] assume !(1 == ~E_5~0); [L930-L967] assume !false; [L933] start_simulation_~kernel_st~0 := 1; [L934] havoc eval_#t~ret2, eval_#t~nondet3, eval_~tmp_ndt_1~0, eval_#t~nondet4, eval_~tmp_ndt_2~0, eval_#t~nondet5, eval_~tmp_ndt_3~0, eval_#t~nondet6, eval_~tmp_ndt_4~0, eval_#t~nondet7, eval_~tmp_ndt_5~0, eval_#t~nondet8, eval_~tmp_ndt_6~0, eval_~tmp~0; [L492] havoc eval_~tmp~0; ----- ----- class de.uni_freiburg.informatik.ultimate.boogie.preprocessor.BoogiePreprocessorBacktranslator [L14] ~m_pc~0 := 0; [L15] ~t1_pc~0 := 0; [L16] ~t2_pc~0 := 0; [L17] ~t3_pc~0 := 0; [L18] ~t4_pc~0 := 0; [L19] ~t5_pc~0 := 0; [L20] ~m_st~0 := 0; [L21] ~t1_st~0 := 0; [L22] ~t2_st~0 := 0; [L23] ~t3_st~0 := 0; [L24] ~t4_st~0 := 0; [L25] ~t5_st~0 := 0; [L26] ~m_i~0 := 0; [L27] ~t1_i~0 := 0; [L28] ~t2_i~0 := 0; [L29] ~t3_i~0 := 0; [L30] ~t4_i~0 := 0; [L31] ~t5_i~0 := 0; [L32] ~M_E~0 := 2; [L33] ~T1_E~0 := 2; [L34] ~T2_E~0 := 2; [L35] ~T3_E~0 := 2; [L36] ~T4_E~0 := 2; [L37] ~T5_E~0 := 2; [L38] ~E_M~0 := 2; [L39] ~E_1~0 := 2; [L40] ~E_2~0 := 2; [L41] ~E_3~0 := 2; [L42] ~E_4~0 := 2; [L43] ~E_5~0 := 2; [L51] ~token~0 := 0; [L53] ~local~0 := 0; [?] havoc main_#res; [?] havoc main_~__retres1~7; [L975] havoc main_~__retres1~7; [L886] ~m_i~0 := 1; [L887] ~t1_i~0 := 1; [L888] ~t2_i~0 := 1; [L889] ~t3_i~0 := 1; [L890] ~t4_i~0 := 1; [L891] ~t5_i~0 := 1; [L980] havoc start_simulation_#t~ret16, start_simulation_#t~ret17, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1; [L916] havoc start_simulation_~kernel_st~0; [L917] havoc start_simulation_~tmp~3; [L918] havoc start_simulation_~tmp___0~1; [L922] start_simulation_~kernel_st~0 := 0; [L416-L420] assume 1 == ~m_i~0; [L417] ~m_st~0 := 0; [L421-L425] assume 1 == ~t1_i~0; [L422] ~t1_st~0 := 0; [L426-L430] assume 1 == ~t2_i~0; [L427] ~t2_st~0 := 0; [L431-L435] assume 1 == ~t3_i~0; [L432] ~t3_st~0 := 0; [L436-L440] assume 1 == ~t4_i~0; [L437] ~t4_st~0 := 0; [L441-L445] assume 1 == ~t5_i~0; [L442] ~t5_st~0 := 0; [L601-L605] assume !(0 == ~M_E~0); [L606-L610] assume !(0 == ~T1_E~0); [L611-L615] assume !(0 == ~T2_E~0); [L616-L620] assume !(0 == ~T3_E~0); [L621-L625] assume !(0 == ~T4_E~0); [L626-L630] assume !(0 == ~T5_E~0); [L631-L635] assume !(0 == ~E_M~0); [L636-L640] assume !(0 == ~E_1~0); [L641-L645] assume !(0 == ~E_2~0); [L646-L650] assume !(0 == ~E_3~0); [L651-L655] assume !(0 == ~E_4~0); [L656-L660] assume !(0 == ~E_5~0); [L926] havoc activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0; [L734] havoc activate_threads_~tmp~1; [L735] havoc activate_threads_~tmp___0~0; [L736] havoc activate_threads_~tmp___1~0; [L737] havoc activate_threads_~tmp___2~0; [L738] havoc activate_threads_~tmp___3~0; [L739] havoc activate_threads_~tmp___4~0; [L743] havoc is_master_triggered_#res; [L743] havoc is_master_triggered_~__retres1~0; [L291] havoc is_master_triggered_~__retres1~0; [L294-L303] assume !(1 == ~m_pc~0); [L304] is_master_triggered_~__retres1~0 := 0; [L306] is_master_triggered_#res := is_master_triggered_~__retres1~0; [L743] activate_threads_#t~ret9 := is_master_triggered_#res; [L743] activate_threads_~tmp~1 := activate_threads_#t~ret9; [L743] havoc activate_threads_#t~ret9; [L745-L749] assume !(0 != activate_threads_~tmp~1); [L751] havoc is_transmit1_triggered_#res; [L751] havoc is_transmit1_triggered_~__retres1~1; [L310] havoc is_transmit1_triggered_~__retres1~1; [L313-L322] assume !(1 == ~t1_pc~0); [L323] is_transmit1_triggered_~__retres1~1 := 0; [L325] is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; [L751] activate_threads_#t~ret10 := is_transmit1_triggered_#res; [L751] activate_threads_~tmp___0~0 := activate_threads_#t~ret10; [L751] havoc activate_threads_#t~ret10; [L753-L757] assume !(0 != activate_threads_~tmp___0~0); [L759] havoc is_transmit2_triggered_#res; [L759] havoc is_transmit2_triggered_~__retres1~2; [L329] havoc is_transmit2_triggered_~__retres1~2; [L332-L341] assume !(1 == ~t2_pc~0); [L342] is_transmit2_triggered_~__retres1~2 := 0; [L344] is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; [L759] activate_threads_#t~ret11 := is_transmit2_triggered_#res; [L759] activate_threads_~tmp___1~0 := activate_threads_#t~ret11; [L759] havoc activate_threads_#t~ret11; [L761-L765] assume !(0 != activate_threads_~tmp___1~0); [L767] havoc is_transmit3_triggered_#res; [L767] havoc is_transmit3_triggered_~__retres1~3; [L348] havoc is_transmit3_triggered_~__retres1~3; [L351-L360] assume !(1 == ~t3_pc~0); [L361] is_transmit3_triggered_~__retres1~3 := 0; [L363] is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; [L767] activate_threads_#t~ret12 := is_transmit3_triggered_#res; [L767] activate_threads_~tmp___2~0 := activate_threads_#t~ret12; [L767] havoc activate_threads_#t~ret12; [L769-L773] assume !(0 != activate_threads_~tmp___2~0); [L775] havoc is_transmit4_triggered_#res; [L775] havoc is_transmit4_triggered_~__retres1~4; [L367] havoc is_transmit4_triggered_~__retres1~4; [L370-L379] assume !(1 == ~t4_pc~0); [L380] is_transmit4_triggered_~__retres1~4 := 0; [L382] is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; [L775] activate_threads_#t~ret13 := is_transmit4_triggered_#res; [L775] activate_threads_~tmp___3~0 := activate_threads_#t~ret13; [L775] havoc activate_threads_#t~ret13; [L777-L781] assume !(0 != activate_threads_~tmp___3~0); [L783] havoc is_transmit5_triggered_#res; [L783] havoc is_transmit5_triggered_~__retres1~5; [L386] havoc is_transmit5_triggered_~__retres1~5; [L389-L398] assume !(1 == ~t5_pc~0); [L399] is_transmit5_triggered_~__retres1~5 := 0; [L401] is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; [L783] activate_threads_#t~ret14 := is_transmit5_triggered_#res; [L783] activate_threads_~tmp___4~0 := activate_threads_#t~ret14; [L783] havoc activate_threads_#t~ret14; [L785-L789] assume !(0 != activate_threads_~tmp___4~0); [L669-L673] assume !(1 == ~M_E~0); [L674-L678] assume !(1 == ~T1_E~0); [L679-L683] assume !(1 == ~T2_E~0); [L684-L688] assume !(1 == ~T3_E~0); [L689-L693] assume !(1 == ~T4_E~0); [L694-L698] assume !(1 == ~T5_E~0); [L699-L703] assume !(1 == ~E_M~0); [L704-L708] assume !(1 == ~E_1~0); [L709-L713] assume !(1 == ~E_2~0); [L714-L718] assume !(1 == ~E_3~0); [L719-L723] assume !(1 == ~E_4~0); [L724-L728] assume !(1 == ~E_5~0); [L930-L967] assume !false; [L933] start_simulation_~kernel_st~0 := 1; [L934] havoc eval_#t~ret2, eval_#t~nondet3, eval_~tmp_ndt_1~0, eval_#t~nondet4, eval_~tmp_ndt_2~0, eval_#t~nondet5, eval_~tmp_ndt_3~0, eval_#t~nondet6, eval_~tmp_ndt_4~0, eval_#t~nondet7, eval_~tmp_ndt_5~0, eval_#t~nondet8, eval_~tmp_ndt_6~0, eval_~tmp~0; [L492] havoc eval_~tmp~0; [L14] ~m_pc~0 := 0; [L15] ~t1_pc~0 := 0; [L16] ~t2_pc~0 := 0; [L17] ~t3_pc~0 := 0; [L18] ~t4_pc~0 := 0; [L19] ~t5_pc~0 := 0; [L20] ~m_st~0 := 0; [L21] ~t1_st~0 := 0; [L22] ~t2_st~0 := 0; [L23] ~t3_st~0 := 0; [L24] ~t4_st~0 := 0; [L25] ~t5_st~0 := 0; [L26] ~m_i~0 := 0; [L27] ~t1_i~0 := 0; [L28] ~t2_i~0 := 0; [L29] ~t3_i~0 := 0; [L30] ~t4_i~0 := 0; [L31] ~t5_i~0 := 0; [L32] ~M_E~0 := 2; [L33] ~T1_E~0 := 2; [L34] ~T2_E~0 := 2; [L35] ~T3_E~0 := 2; [L36] ~T4_E~0 := 2; [L37] ~T5_E~0 := 2; [L38] ~E_M~0 := 2; [L39] ~E_1~0 := 2; [L40] ~E_2~0 := 2; [L41] ~E_3~0 := 2; [L42] ~E_4~0 := 2; [L43] ~E_5~0 := 2; [L51] ~token~0 := 0; [L53] ~local~0 := 0; [?] havoc main_#res; [?] havoc main_~__retres1~7; [L975] havoc main_~__retres1~7; [L886] ~m_i~0 := 1; [L887] ~t1_i~0 := 1; [L888] ~t2_i~0 := 1; [L889] ~t3_i~0 := 1; [L890] ~t4_i~0 := 1; [L891] ~t5_i~0 := 1; [L980] havoc start_simulation_#t~ret16, start_simulation_#t~ret17, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1; [L916] havoc start_simulation_~kernel_st~0; [L917] havoc start_simulation_~tmp~3; [L918] havoc start_simulation_~tmp___0~1; [L922] start_simulation_~kernel_st~0 := 0; [L416] COND TRUE 1 == ~m_i~0 [L417] ~m_st~0 := 0; [L421] COND TRUE 1 == ~t1_i~0 [L422] ~t1_st~0 := 0; [L426] COND TRUE 1 == ~t2_i~0 [L427] ~t2_st~0 := 0; [L431] COND TRUE 1 == ~t3_i~0 [L432] ~t3_st~0 := 0; [L436] COND TRUE 1 == ~t4_i~0 [L437] ~t4_st~0 := 0; [L441] COND TRUE 1 == ~t5_i~0 [L442] ~t5_st~0 := 0; [L601] COND FALSE !(0 == ~M_E~0) [L606] COND FALSE !(0 == ~T1_E~0) [L611] COND FALSE !(0 == ~T2_E~0) [L616] COND FALSE !(0 == ~T3_E~0) [L621] COND FALSE !(0 == ~T4_E~0) [L626] COND FALSE !(0 == ~T5_E~0) [L631] COND FALSE !(0 == ~E_M~0) [L636] COND FALSE !(0 == ~E_1~0) [L641] COND FALSE !(0 == ~E_2~0) [L646] COND FALSE !(0 == ~E_3~0) [L651] COND FALSE !(0 == ~E_4~0) [L656] COND FALSE !(0 == ~E_5~0) [L926] havoc activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0; [L734] havoc activate_threads_~tmp~1; [L735] havoc activate_threads_~tmp___0~0; [L736] havoc activate_threads_~tmp___1~0; [L737] havoc activate_threads_~tmp___2~0; [L738] havoc activate_threads_~tmp___3~0; [L739] havoc activate_threads_~tmp___4~0; [L743] havoc is_master_triggered_#res; [L743] havoc is_master_triggered_~__retres1~0; [L291] havoc is_master_triggered_~__retres1~0; [L294] COND FALSE !(1 == ~m_pc~0) [L304] is_master_triggered_~__retres1~0 := 0; [L306] is_master_triggered_#res := is_master_triggered_~__retres1~0; [L743] activate_threads_#t~ret9 := is_master_triggered_#res; [L743] activate_threads_~tmp~1 := activate_threads_#t~ret9; [L743] havoc activate_threads_#t~ret9; [L745-L749] COND FALSE !(0 != activate_threads_~tmp~1) [L751] havoc is_transmit1_triggered_#res; [L751] havoc is_transmit1_triggered_~__retres1~1; [L310] havoc is_transmit1_triggered_~__retres1~1; [L313] COND FALSE !(1 == ~t1_pc~0) [L323] is_transmit1_triggered_~__retres1~1 := 0; [L325] is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; [L751] activate_threads_#t~ret10 := is_transmit1_triggered_#res; [L751] activate_threads_~tmp___0~0 := activate_threads_#t~ret10; [L751] havoc activate_threads_#t~ret10; [L753-L757] COND FALSE !(0 != activate_threads_~tmp___0~0) [L759] havoc is_transmit2_triggered_#res; [L759] havoc is_transmit2_triggered_~__retres1~2; [L329] havoc is_transmit2_triggered_~__retres1~2; [L332] COND FALSE !(1 == ~t2_pc~0) [L342] is_transmit2_triggered_~__retres1~2 := 0; [L344] is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; [L759] activate_threads_#t~ret11 := is_transmit2_triggered_#res; [L759] activate_threads_~tmp___1~0 := activate_threads_#t~ret11; [L759] havoc activate_threads_#t~ret11; [L761-L765] COND FALSE !(0 != activate_threads_~tmp___1~0) [L767] havoc is_transmit3_triggered_#res; [L767] havoc is_transmit3_triggered_~__retres1~3; [L348] havoc is_transmit3_triggered_~__retres1~3; [L351] COND FALSE !(1 == ~t3_pc~0) [L361] is_transmit3_triggered_~__retres1~3 := 0; [L363] is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; [L767] activate_threads_#t~ret12 := is_transmit3_triggered_#res; [L767] activate_threads_~tmp___2~0 := activate_threads_#t~ret12; [L767] havoc activate_threads_#t~ret12; [L769-L773] COND FALSE !(0 != activate_threads_~tmp___2~0) [L775] havoc is_transmit4_triggered_#res; [L775] havoc is_transmit4_triggered_~__retres1~4; [L367] havoc is_transmit4_triggered_~__retres1~4; [L370] COND FALSE !(1 == ~t4_pc~0) [L380] is_transmit4_triggered_~__retres1~4 := 0; [L382] is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; [L775] activate_threads_#t~ret13 := is_transmit4_triggered_#res; [L775] activate_threads_~tmp___3~0 := activate_threads_#t~ret13; [L775] havoc activate_threads_#t~ret13; [L777-L781] COND FALSE !(0 != activate_threads_~tmp___3~0) [L783] havoc is_transmit5_triggered_#res; [L783] havoc is_transmit5_triggered_~__retres1~5; [L386] havoc is_transmit5_triggered_~__retres1~5; [L389] COND FALSE !(1 == ~t5_pc~0) [L399] is_transmit5_triggered_~__retres1~5 := 0; [L401] is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; [L783] activate_threads_#t~ret14 := is_transmit5_triggered_#res; [L783] activate_threads_~tmp___4~0 := activate_threads_#t~ret14; [L783] havoc activate_threads_#t~ret14; [L785-L789] COND FALSE !(0 != activate_threads_~tmp___4~0) [L669] COND FALSE !(1 == ~M_E~0) [L674] COND FALSE !(1 == ~T1_E~0) [L679] COND FALSE !(1 == ~T2_E~0) [L684] COND FALSE !(1 == ~T3_E~0) [L689] COND FALSE !(1 == ~T4_E~0) [L694] COND FALSE !(1 == ~T5_E~0) [L699] COND FALSE !(1 == ~E_M~0) [L704] COND FALSE !(1 == ~E_1~0) [L709] COND FALSE !(1 == ~E_2~0) [L714] COND FALSE !(1 == ~E_3~0) [L719] COND FALSE !(1 == ~E_4~0) [L724] COND FALSE !(1 == ~E_5~0) [L930-L967] COND FALSE !(false) [L933] start_simulation_~kernel_st~0 := 1; [L934] havoc eval_#t~ret2, eval_#t~nondet3, eval_~tmp_ndt_1~0, eval_#t~nondet4, eval_~tmp_ndt_2~0, eval_#t~nondet5, eval_~tmp_ndt_3~0, eval_#t~nondet6, eval_~tmp_ndt_4~0, eval_#t~nondet7, eval_~tmp_ndt_5~0, eval_#t~nondet8, eval_~tmp_ndt_6~0, eval_~tmp~0; [L492] havoc eval_~tmp~0; ----- ----- class de.uni_freiburg.informatik.ultimate.boogie.procedureinliner.backtranslation.InlinerBacktranslator [L14] ~m_pc~0 := 0; [L15] ~t1_pc~0 := 0; [L16] ~t2_pc~0 := 0; [L17] ~t3_pc~0 := 0; [L18] ~t4_pc~0 := 0; [L19] ~t5_pc~0 := 0; [L20] ~m_st~0 := 0; [L21] ~t1_st~0 := 0; [L22] ~t2_st~0 := 0; [L23] ~t3_st~0 := 0; [L24] ~t4_st~0 := 0; [L25] ~t5_st~0 := 0; [L26] ~m_i~0 := 0; [L27] ~t1_i~0 := 0; [L28] ~t2_i~0 := 0; [L29] ~t3_i~0 := 0; [L30] ~t4_i~0 := 0; [L31] ~t5_i~0 := 0; [L32] ~M_E~0 := 2; [L33] ~T1_E~0 := 2; [L34] ~T2_E~0 := 2; [L35] ~T3_E~0 := 2; [L36] ~T4_E~0 := 2; [L37] ~T5_E~0 := 2; [L38] ~E_M~0 := 2; [L39] ~E_1~0 := 2; [L40] ~E_2~0 := 2; [L41] ~E_3~0 := 2; [L42] ~E_4~0 := 2; [L43] ~E_5~0 := 2; [L51] ~token~0 := 0; [L53] ~local~0 := 0; [?] havoc main_#res; [?] havoc main_~__retres1~7; [L975] havoc main_~__retres1~7; [L886] ~m_i~0 := 1; [L887] ~t1_i~0 := 1; [L888] ~t2_i~0 := 1; [L889] ~t3_i~0 := 1; [L890] ~t4_i~0 := 1; [L891] ~t5_i~0 := 1; [L980] havoc start_simulation_#t~ret16, start_simulation_#t~ret17, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1; [L916] havoc start_simulation_~kernel_st~0; [L917] havoc start_simulation_~tmp~3; [L918] havoc start_simulation_~tmp___0~1; [L922] start_simulation_~kernel_st~0 := 0; [L416] COND TRUE 1 == ~m_i~0 [L417] ~m_st~0 := 0; [L421] COND TRUE 1 == ~t1_i~0 [L422] ~t1_st~0 := 0; [L426] COND TRUE 1 == ~t2_i~0 [L427] ~t2_st~0 := 0; [L431] COND TRUE 1 == ~t3_i~0 [L432] ~t3_st~0 := 0; [L436] COND TRUE 1 == ~t4_i~0 [L437] ~t4_st~0 := 0; [L441] COND TRUE 1 == ~t5_i~0 [L442] ~t5_st~0 := 0; [L601] COND FALSE !(0 == ~M_E~0) [L606] COND FALSE !(0 == ~T1_E~0) [L611] COND FALSE !(0 == ~T2_E~0) [L616] COND FALSE !(0 == ~T3_E~0) [L621] COND FALSE !(0 == ~T4_E~0) [L626] COND FALSE !(0 == ~T5_E~0) [L631] COND FALSE !(0 == ~E_M~0) [L636] COND FALSE !(0 == ~E_1~0) [L641] COND FALSE !(0 == ~E_2~0) [L646] COND FALSE !(0 == ~E_3~0) [L651] COND FALSE !(0 == ~E_4~0) [L656] COND FALSE !(0 == ~E_5~0) [L926] havoc activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0; [L734] havoc activate_threads_~tmp~1; [L735] havoc activate_threads_~tmp___0~0; [L736] havoc activate_threads_~tmp___1~0; [L737] havoc activate_threads_~tmp___2~0; [L738] havoc activate_threads_~tmp___3~0; [L739] havoc activate_threads_~tmp___4~0; [L743] havoc is_master_triggered_#res; [L743] havoc is_master_triggered_~__retres1~0; [L291] havoc is_master_triggered_~__retres1~0; [L294] COND FALSE !(1 == ~m_pc~0) [L304] is_master_triggered_~__retres1~0 := 0; [L306] is_master_triggered_#res := is_master_triggered_~__retres1~0; [L743] activate_threads_#t~ret9 := is_master_triggered_#res; [L743] activate_threads_~tmp~1 := activate_threads_#t~ret9; [L743] havoc activate_threads_#t~ret9; [L745-L749] COND FALSE !(0 != activate_threads_~tmp~1) [L751] havoc is_transmit1_triggered_#res; [L751] havoc is_transmit1_triggered_~__retres1~1; [L310] havoc is_transmit1_triggered_~__retres1~1; [L313] COND FALSE !(1 == ~t1_pc~0) [L323] is_transmit1_triggered_~__retres1~1 := 0; [L325] is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; [L751] activate_threads_#t~ret10 := is_transmit1_triggered_#res; [L751] activate_threads_~tmp___0~0 := activate_threads_#t~ret10; [L751] havoc activate_threads_#t~ret10; [L753-L757] COND FALSE !(0 != activate_threads_~tmp___0~0) [L759] havoc is_transmit2_triggered_#res; [L759] havoc is_transmit2_triggered_~__retres1~2; [L329] havoc is_transmit2_triggered_~__retres1~2; [L332] COND FALSE !(1 == ~t2_pc~0) [L342] is_transmit2_triggered_~__retres1~2 := 0; [L344] is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; [L759] activate_threads_#t~ret11 := is_transmit2_triggered_#res; [L759] activate_threads_~tmp___1~0 := activate_threads_#t~ret11; [L759] havoc activate_threads_#t~ret11; [L761-L765] COND FALSE !(0 != activate_threads_~tmp___1~0) [L767] havoc is_transmit3_triggered_#res; [L767] havoc is_transmit3_triggered_~__retres1~3; [L348] havoc is_transmit3_triggered_~__retres1~3; [L351] COND FALSE !(1 == ~t3_pc~0) [L361] is_transmit3_triggered_~__retres1~3 := 0; [L363] is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; [L767] activate_threads_#t~ret12 := is_transmit3_triggered_#res; [L767] activate_threads_~tmp___2~0 := activate_threads_#t~ret12; [L767] havoc activate_threads_#t~ret12; [L769-L773] COND FALSE !(0 != activate_threads_~tmp___2~0) [L775] havoc is_transmit4_triggered_#res; [L775] havoc is_transmit4_triggered_~__retres1~4; [L367] havoc is_transmit4_triggered_~__retres1~4; [L370] COND FALSE !(1 == ~t4_pc~0) [L380] is_transmit4_triggered_~__retres1~4 := 0; [L382] is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; [L775] activate_threads_#t~ret13 := is_transmit4_triggered_#res; [L775] activate_threads_~tmp___3~0 := activate_threads_#t~ret13; [L775] havoc activate_threads_#t~ret13; [L777-L781] COND FALSE !(0 != activate_threads_~tmp___3~0) [L783] havoc is_transmit5_triggered_#res; [L783] havoc is_transmit5_triggered_~__retres1~5; [L386] havoc is_transmit5_triggered_~__retres1~5; [L389] COND FALSE !(1 == ~t5_pc~0) [L399] is_transmit5_triggered_~__retres1~5 := 0; [L401] is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; [L783] activate_threads_#t~ret14 := is_transmit5_triggered_#res; [L783] activate_threads_~tmp___4~0 := activate_threads_#t~ret14; [L783] havoc activate_threads_#t~ret14; [L785-L789] COND FALSE !(0 != activate_threads_~tmp___4~0) [L669] COND FALSE !(1 == ~M_E~0) [L674] COND FALSE !(1 == ~T1_E~0) [L679] COND FALSE !(1 == ~T2_E~0) [L684] COND FALSE !(1 == ~T3_E~0) [L689] COND FALSE !(1 == ~T4_E~0) [L694] COND FALSE !(1 == ~T5_E~0) [L699] COND FALSE !(1 == ~E_M~0) [L704] COND FALSE !(1 == ~E_1~0) [L709] COND FALSE !(1 == ~E_2~0) [L714] COND FALSE !(1 == ~E_3~0) [L719] COND FALSE !(1 == ~E_4~0) [L724] COND FALSE !(1 == ~E_5~0) [L930-L967] COND FALSE !(false) [L933] start_simulation_~kernel_st~0 := 1; [L934] havoc eval_#t~ret2, eval_#t~nondet3, eval_~tmp_ndt_1~0, eval_#t~nondet4, eval_~tmp_ndt_2~0, eval_#t~nondet5, eval_~tmp_ndt_3~0, eval_#t~nondet6, eval_~tmp_ndt_4~0, eval_#t~nondet7, eval_~tmp_ndt_5~0, eval_#t~nondet8, eval_~tmp_ndt_6~0, eval_~tmp~0; [L492] havoc eval_~tmp~0; [L14] ~m_pc~0 := 0; [L15] ~t1_pc~0 := 0; [L16] ~t2_pc~0 := 0; [L17] ~t3_pc~0 := 0; [L18] ~t4_pc~0 := 0; [L19] ~t5_pc~0 := 0; [L20] ~m_st~0 := 0; [L21] ~t1_st~0 := 0; [L22] ~t2_st~0 := 0; [L23] ~t3_st~0 := 0; [L24] ~t4_st~0 := 0; [L25] ~t5_st~0 := 0; [L26] ~m_i~0 := 0; [L27] ~t1_i~0 := 0; [L28] ~t2_i~0 := 0; [L29] ~t3_i~0 := 0; [L30] ~t4_i~0 := 0; [L31] ~t5_i~0 := 0; [L32] ~M_E~0 := 2; [L33] ~T1_E~0 := 2; [L34] ~T2_E~0 := 2; [L35] ~T3_E~0 := 2; [L36] ~T4_E~0 := 2; [L37] ~T5_E~0 := 2; [L38] ~E_M~0 := 2; [L39] ~E_1~0 := 2; [L40] ~E_2~0 := 2; [L41] ~E_3~0 := 2; [L42] ~E_4~0 := 2; [L43] ~E_5~0 := 2; [L51] ~token~0 := 0; [L53] ~local~0 := 0; [L975] havoc ~__retres1~7; [L886] ~m_i~0 := 1; [L887] ~t1_i~0 := 1; [L888] ~t2_i~0 := 1; [L889] ~t3_i~0 := 1; [L890] ~t4_i~0 := 1; [L891] ~t5_i~0 := 1; [L916] havoc ~kernel_st~0; [L917] havoc ~tmp~3; [L918] havoc ~tmp___0~1; [L922] ~kernel_st~0 := 0; [L416] COND TRUE 1 == ~m_i~0 [L417] ~m_st~0 := 0; [L421] COND TRUE 1 == ~t1_i~0 [L422] ~t1_st~0 := 0; [L426] COND TRUE 1 == ~t2_i~0 [L427] ~t2_st~0 := 0; [L431] COND TRUE 1 == ~t3_i~0 [L432] ~t3_st~0 := 0; [L436] COND TRUE 1 == ~t4_i~0 [L437] ~t4_st~0 := 0; [L441] COND TRUE 1 == ~t5_i~0 [L442] ~t5_st~0 := 0; [L601] COND FALSE !(0 == ~M_E~0) [L606] COND FALSE !(0 == ~T1_E~0) [L611] COND FALSE !(0 == ~T2_E~0) [L616] COND FALSE !(0 == ~T3_E~0) [L621] COND FALSE !(0 == ~T4_E~0) [L626] COND FALSE !(0 == ~T5_E~0) [L631] COND FALSE !(0 == ~E_M~0) [L636] COND FALSE !(0 == ~E_1~0) [L641] COND FALSE !(0 == ~E_2~0) [L646] COND FALSE !(0 == ~E_3~0) [L651] COND FALSE !(0 == ~E_4~0) [L656] COND FALSE !(0 == ~E_5~0) [L734] havoc ~tmp~1; [L735] havoc ~tmp___0~0; [L736] havoc ~tmp___1~0; [L737] havoc ~tmp___2~0; [L738] havoc ~tmp___3~0; [L739] havoc ~tmp___4~0; [L291] havoc ~__retres1~0; [L294] COND FALSE !(1 == ~m_pc~0) [L304] ~__retres1~0 := 0; [L306] #res := ~__retres1~0; [L743] ~tmp~1 := #t~ret9; [L743] havoc #t~ret9; [L745-L749] COND FALSE !(0 != ~tmp~1) [L310] havoc ~__retres1~1; [L313] COND FALSE !(1 == ~t1_pc~0) [L323] ~__retres1~1 := 0; [L325] #res := ~__retres1~1; [L751] ~tmp___0~0 := #t~ret10; [L751] havoc #t~ret10; [L753-L757] COND FALSE !(0 != ~tmp___0~0) [L329] havoc ~__retres1~2; [L332] COND FALSE !(1 == ~t2_pc~0) [L342] ~__retres1~2 := 0; [L344] #res := ~__retres1~2; [L759] ~tmp___1~0 := #t~ret11; [L759] havoc #t~ret11; [L761-L765] COND FALSE !(0 != ~tmp___1~0) [L348] havoc ~__retres1~3; [L351] COND FALSE !(1 == ~t3_pc~0) [L361] ~__retres1~3 := 0; [L363] #res := ~__retres1~3; [L767] ~tmp___2~0 := #t~ret12; [L767] havoc #t~ret12; [L769-L773] COND FALSE !(0 != ~tmp___2~0) [L367] havoc ~__retres1~4; [L370] COND FALSE !(1 == ~t4_pc~0) [L380] ~__retres1~4 := 0; [L382] #res := ~__retres1~4; [L775] ~tmp___3~0 := #t~ret13; [L775] havoc #t~ret13; [L777-L781] COND FALSE !(0 != ~tmp___3~0) [L386] havoc ~__retres1~5; [L389] COND FALSE !(1 == ~t5_pc~0) [L399] ~__retres1~5 := 0; [L401] #res := ~__retres1~5; [L783] ~tmp___4~0 := #t~ret14; [L783] havoc #t~ret14; [L785-L789] COND FALSE !(0 != ~tmp___4~0) [L669] COND FALSE !(1 == ~M_E~0) [L674] COND FALSE !(1 == ~T1_E~0) [L679] COND FALSE !(1 == ~T2_E~0) [L684] COND FALSE !(1 == ~T3_E~0) [L689] COND FALSE !(1 == ~T4_E~0) [L694] COND FALSE !(1 == ~T5_E~0) [L699] COND FALSE !(1 == ~E_M~0) [L704] COND FALSE !(1 == ~E_1~0) [L709] COND FALSE !(1 == ~E_2~0) [L714] COND FALSE !(1 == ~E_3~0) [L719] COND FALSE !(1 == ~E_4~0) [L724] COND FALSE !(1 == ~E_5~0) [L930-L967] COND FALSE !(false) [L933] ~kernel_st~0 := 1; [L492] havoc ~tmp~0; ----- ----- class de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.CACSL2BoogieBacktranslator [L14] ~m_pc~0 := 0; [L15] ~t1_pc~0 := 0; [L16] ~t2_pc~0 := 0; [L17] ~t3_pc~0 := 0; [L18] ~t4_pc~0 := 0; [L19] ~t5_pc~0 := 0; [L20] ~m_st~0 := 0; [L21] ~t1_st~0 := 0; [L22] ~t2_st~0 := 0; [L23] ~t3_st~0 := 0; [L24] ~t4_st~0 := 0; [L25] ~t5_st~0 := 0; [L26] ~m_i~0 := 0; [L27] ~t1_i~0 := 0; [L28] ~t2_i~0 := 0; [L29] ~t3_i~0 := 0; [L30] ~t4_i~0 := 0; [L31] ~t5_i~0 := 0; [L32] ~M_E~0 := 2; [L33] ~T1_E~0 := 2; [L34] ~T2_E~0 := 2; [L35] ~T3_E~0 := 2; [L36] ~T4_E~0 := 2; [L37] ~T5_E~0 := 2; [L38] ~E_M~0 := 2; [L39] ~E_1~0 := 2; [L40] ~E_2~0 := 2; [L41] ~E_3~0 := 2; [L42] ~E_4~0 := 2; [L43] ~E_5~0 := 2; [L51] ~token~0 := 0; [L53] ~local~0 := 0; [L975] havoc ~__retres1~7; [L886] ~m_i~0 := 1; [L887] ~t1_i~0 := 1; [L888] ~t2_i~0 := 1; [L889] ~t3_i~0 := 1; [L890] ~t4_i~0 := 1; [L891] ~t5_i~0 := 1; [L916] havoc ~kernel_st~0; [L917] havoc ~tmp~3; [L918] havoc ~tmp___0~1; [L922] ~kernel_st~0 := 0; [L416] COND TRUE 1 == ~m_i~0 [L417] ~m_st~0 := 0; [L421] COND TRUE 1 == ~t1_i~0 [L422] ~t1_st~0 := 0; [L426] COND TRUE 1 == ~t2_i~0 [L427] ~t2_st~0 := 0; [L431] COND TRUE 1 == ~t3_i~0 [L432] ~t3_st~0 := 0; [L436] COND TRUE 1 == ~t4_i~0 [L437] ~t4_st~0 := 0; [L441] COND TRUE 1 == ~t5_i~0 [L442] ~t5_st~0 := 0; [L601] COND FALSE !(0 == ~M_E~0) [L606] COND FALSE !(0 == ~T1_E~0) [L611] COND FALSE !(0 == ~T2_E~0) [L616] COND FALSE !(0 == ~T3_E~0) [L621] COND FALSE !(0 == ~T4_E~0) [L626] COND FALSE !(0 == ~T5_E~0) [L631] COND FALSE !(0 == ~E_M~0) [L636] COND FALSE !(0 == ~E_1~0) [L641] COND FALSE !(0 == ~E_2~0) [L646] COND FALSE !(0 == ~E_3~0) [L651] COND FALSE !(0 == ~E_4~0) [L656] COND FALSE !(0 == ~E_5~0) [L734] havoc ~tmp~1; [L735] havoc ~tmp___0~0; [L736] havoc ~tmp___1~0; [L737] havoc ~tmp___2~0; [L738] havoc ~tmp___3~0; [L739] havoc ~tmp___4~0; [L291] havoc ~__retres1~0; [L294] COND FALSE !(1 == ~m_pc~0) [L304] ~__retres1~0 := 0; [L306] #res := ~__retres1~0; [L743] ~tmp~1 := #t~ret9; [L743] havoc #t~ret9; [L745-L749] COND FALSE !(0 != ~tmp~1) [L310] havoc ~__retres1~1; [L313] COND FALSE !(1 == ~t1_pc~0) [L323] ~__retres1~1 := 0; [L325] #res := ~__retres1~1; [L751] ~tmp___0~0 := #t~ret10; [L751] havoc #t~ret10; [L753-L757] COND FALSE !(0 != ~tmp___0~0) [L329] havoc ~__retres1~2; [L332] COND FALSE !(1 == ~t2_pc~0) [L342] ~__retres1~2 := 0; [L344] #res := ~__retres1~2; [L759] ~tmp___1~0 := #t~ret11; [L759] havoc #t~ret11; [L761-L765] COND FALSE !(0 != ~tmp___1~0) [L348] havoc ~__retres1~3; [L351] COND FALSE !(1 == ~t3_pc~0) [L361] ~__retres1~3 := 0; [L363] #res := ~__retres1~3; [L767] ~tmp___2~0 := #t~ret12; [L767] havoc #t~ret12; [L769-L773] COND FALSE !(0 != ~tmp___2~0) [L367] havoc ~__retres1~4; [L370] COND FALSE !(1 == ~t4_pc~0) [L380] ~__retres1~4 := 0; [L382] #res := ~__retres1~4; [L775] ~tmp___3~0 := #t~ret13; [L775] havoc #t~ret13; [L777-L781] COND FALSE !(0 != ~tmp___3~0) [L386] havoc ~__retres1~5; [L389] COND FALSE !(1 == ~t5_pc~0) [L399] ~__retres1~5 := 0; [L401] #res := ~__retres1~5; [L783] ~tmp___4~0 := #t~ret14; [L783] havoc #t~ret14; [L785-L789] COND FALSE !(0 != ~tmp___4~0) [L669] COND FALSE !(1 == ~M_E~0) [L674] COND FALSE !(1 == ~T1_E~0) [L679] COND FALSE !(1 == ~T2_E~0) [L684] COND FALSE !(1 == ~T3_E~0) [L689] COND FALSE !(1 == ~T4_E~0) [L694] COND FALSE !(1 == ~T5_E~0) [L699] COND FALSE !(1 == ~E_M~0) [L704] COND FALSE !(1 == ~E_1~0) [L709] COND FALSE !(1 == ~E_2~0) [L714] COND FALSE !(1 == ~E_3~0) [L719] COND FALSE !(1 == ~E_4~0) [L724] COND FALSE !(1 == ~E_5~0) [L930-L967] COND FALSE !(false) [L933] ~kernel_st~0 := 1; [L492] havoc ~tmp~0; [L14] int m_pc = 0; [L15] int t1_pc = 0; [L16] int t2_pc = 0; [L17] int t3_pc = 0; [L18] int t4_pc = 0; [L19] int t5_pc = 0; [L20] int m_st ; [L21] int t1_st ; [L22] int t2_st ; [L23] int t3_st ; [L24] int t4_st ; [L25] int t5_st ; [L26] int m_i ; [L27] int t1_i ; [L28] int t2_i ; [L29] int t3_i ; [L30] int t4_i ; [L31] int t5_i ; [L32] int M_E = 2; [L33] int T1_E = 2; [L34] int T2_E = 2; [L35] int T3_E = 2; [L36] int T4_E = 2; [L37] int T5_E = 2; [L38] int E_M = 2; [L39] int E_1 = 2; [L40] int E_2 = 2; [L41] int E_3 = 2; [L42] int E_4 = 2; [L43] int E_5 = 2; [L51] int token ; [L53] int local ; [L975] int __retres1 ; [L886] m_i = 1 [L887] t1_i = 1 [L888] t2_i = 1 [L889] t3_i = 1 [L890] t4_i = 1 [L891] t5_i = 1 [L916] int kernel_st ; [L917] int tmp ; [L918] int tmp___0 ; [L922] kernel_st = 0 [L416] COND TRUE m_i == 1 [L417] m_st = 0 [L421] COND TRUE t1_i == 1 [L422] t1_st = 0 [L426] COND TRUE t2_i == 1 [L427] t2_st = 0 [L431] COND TRUE t3_i == 1 [L432] t3_st = 0 [L436] COND TRUE t4_i == 1 [L437] t4_st = 0 [L441] COND TRUE t5_i == 1 [L442] t5_st = 0 [L601] COND FALSE !(M_E == 0) [L606] COND FALSE !(T1_E == 0) [L611] COND FALSE !(T2_E == 0) [L616] COND FALSE !(T3_E == 0) [L621] COND FALSE !(T4_E == 0) [L626] COND FALSE !(T5_E == 0) [L631] COND FALSE !(E_M == 0) [L636] COND FALSE !(E_1 == 0) [L641] COND FALSE !(E_2 == 0) [L646] COND FALSE !(E_3 == 0) [L651] COND FALSE !(E_4 == 0) [L656] COND FALSE !(E_5 == 0) [L734] int tmp ; [L735] int tmp___0 ; [L736] int tmp___1 ; [L737] int tmp___2 ; [L738] int tmp___3 ; [L739] int tmp___4 ; [L291] int __retres1 ; [L294] COND FALSE !(m_pc == 1) [L304] __retres1 = 0 [L306] return (__retres1); [L743] tmp = is_master_triggered() [L745] COND FALSE !(\read(tmp)) [L310] int __retres1 ; [L313] COND FALSE !(t1_pc == 1) [L323] __retres1 = 0 [L325] return (__retres1); [L751] tmp___0 = is_transmit1_triggered() [L753] COND FALSE !(\read(tmp___0)) [L329] int __retres1 ; [L332] COND FALSE !(t2_pc == 1) [L342] __retres1 = 0 [L344] return (__retres1); [L759] tmp___1 = is_transmit2_triggered() [L761] COND FALSE !(\read(tmp___1)) [L348] int __retres1 ; [L351] COND FALSE !(t3_pc == 1) [L361] __retres1 = 0 [L363] return (__retres1); [L767] tmp___2 = is_transmit3_triggered() [L769] COND FALSE !(\read(tmp___2)) [L367] int __retres1 ; [L370] COND FALSE !(t4_pc == 1) [L380] __retres1 = 0 [L382] return (__retres1); [L775] tmp___3 = is_transmit4_triggered() [L777] COND FALSE !(\read(tmp___3)) [L386] int __retres1 ; [L389] COND FALSE !(t5_pc == 1) [L399] __retres1 = 0 [L401] return (__retres1); [L783] tmp___4 = is_transmit5_triggered() [L785] COND FALSE !(\read(tmp___4)) [L669] COND FALSE !(M_E == 1) [L674] COND FALSE !(T1_E == 1) [L679] COND FALSE !(T2_E == 1) [L684] COND FALSE !(T3_E == 1) [L689] COND FALSE !(T4_E == 1) [L694] COND FALSE !(T5_E == 1) [L699] COND FALSE !(E_M == 1) [L704] COND FALSE !(E_1 == 1) [L709] COND FALSE !(E_2 == 1) [L714] COND FALSE !(E_3 == 1) [L719] COND FALSE !(E_4 == 1) [L724] COND FALSE !(E_5 == 1) [L930] COND TRUE 1 [L933] kernel_st = 1 [L492] int tmp ; ----- ----- class de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder.RCFGBacktranslator [?] assume !false; [?] havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; [?] assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; [?] exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; [?] eval_#t~ret2 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret2;havoc eval_#t~ret2; [?] assume 0 != eval_~tmp~0; [?] assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0;eval_~tmp_ndt_1~0 := eval_#t~nondet3;havoc eval_#t~nondet3; [?] assume !(0 != eval_~tmp_ndt_1~0); [?] assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0;eval_~tmp_ndt_2~0 := eval_#t~nondet4;havoc eval_#t~nondet4; [?] assume !(0 != eval_~tmp_ndt_2~0); [?] assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0;eval_~tmp_ndt_3~0 := eval_#t~nondet5;havoc eval_#t~nondet5; [?] assume !(0 != eval_~tmp_ndt_3~0); [?] assume 0 == ~t3_st~0;havoc eval_~tmp_ndt_4~0;eval_~tmp_ndt_4~0 := eval_#t~nondet6;havoc eval_#t~nondet6; [?] assume !(0 != eval_~tmp_ndt_4~0); [?] assume 0 == ~t4_st~0;havoc eval_~tmp_ndt_5~0;eval_~tmp_ndt_5~0 := eval_#t~nondet7;havoc eval_#t~nondet7; [?] assume !(0 != eval_~tmp_ndt_5~0); [?] assume 0 == ~t5_st~0;havoc eval_~tmp_ndt_6~0;eval_~tmp_ndt_6~0 := eval_#t~nondet8;havoc eval_#t~nondet8; [?] assume !(0 != eval_~tmp_ndt_6~0); [L496-L590] assume !false; [L499] havoc exists_runnable_thread_#res; [L499] havoc exists_runnable_thread_~__retres1~6; [L451] havoc exists_runnable_thread_~__retres1~6; [L454-L484] assume 0 == ~m_st~0; [L455] exists_runnable_thread_~__retres1~6 := 1; [L487] exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; [L499] eval_#t~ret2 := exists_runnable_thread_#res; [L499] eval_~tmp~0 := eval_#t~ret2; [L499] havoc eval_#t~ret2; [L501-L505] assume 0 != eval_~tmp~0; [L506-L519] assume 0 == ~m_st~0; [L507] havoc eval_~tmp_ndt_1~0; [L508] eval_~tmp_ndt_1~0 := eval_#t~nondet3; [L508] havoc eval_#t~nondet3; [L509-L516] assume !(0 != eval_~tmp_ndt_1~0); [L520-L533] assume 0 == ~t1_st~0; [L521] havoc eval_~tmp_ndt_2~0; [L522] eval_~tmp_ndt_2~0 := eval_#t~nondet4; [L522] havoc eval_#t~nondet4; [L523-L530] assume !(0 != eval_~tmp_ndt_2~0); [L534-L547] assume 0 == ~t2_st~0; [L535] havoc eval_~tmp_ndt_3~0; [L536] eval_~tmp_ndt_3~0 := eval_#t~nondet5; [L536] havoc eval_#t~nondet5; [L537-L544] assume !(0 != eval_~tmp_ndt_3~0); [L548-L561] assume 0 == ~t3_st~0; [L549] havoc eval_~tmp_ndt_4~0; [L550] eval_~tmp_ndt_4~0 := eval_#t~nondet6; [L550] havoc eval_#t~nondet6; [L551-L558] assume !(0 != eval_~tmp_ndt_4~0); [L562-L575] assume 0 == ~t4_st~0; [L563] havoc eval_~tmp_ndt_5~0; [L564] eval_~tmp_ndt_5~0 := eval_#t~nondet7; [L564] havoc eval_#t~nondet7; [L565-L572] assume !(0 != eval_~tmp_ndt_5~0); [L576-L589] assume 0 == ~t5_st~0; [L577] havoc eval_~tmp_ndt_6~0; [L578] eval_~tmp_ndt_6~0 := eval_#t~nondet8; [L578] havoc eval_#t~nondet8; [L579-L586] assume !(0 != eval_~tmp_ndt_6~0); ----- ----- class de.uni_freiburg.informatik.ultimate.boogie.preprocessor.BoogiePreprocessorBacktranslator [L496-L590] assume !false; [L499] havoc exists_runnable_thread_#res; [L499] havoc exists_runnable_thread_~__retres1~6; [L451] havoc exists_runnable_thread_~__retres1~6; [L454-L484] assume 0 == ~m_st~0; [L455] exists_runnable_thread_~__retres1~6 := 1; [L487] exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; [L499] eval_#t~ret2 := exists_runnable_thread_#res; [L499] eval_~tmp~0 := eval_#t~ret2; [L499] havoc eval_#t~ret2; [L501-L505] assume 0 != eval_~tmp~0; [L506-L519] assume 0 == ~m_st~0; [L507] havoc eval_~tmp_ndt_1~0; [L508] eval_~tmp_ndt_1~0 := eval_#t~nondet3; [L508] havoc eval_#t~nondet3; [L509-L516] assume !(0 != eval_~tmp_ndt_1~0); [L520-L533] assume 0 == ~t1_st~0; [L521] havoc eval_~tmp_ndt_2~0; [L522] eval_~tmp_ndt_2~0 := eval_#t~nondet4; [L522] havoc eval_#t~nondet4; [L523-L530] assume !(0 != eval_~tmp_ndt_2~0); [L534-L547] assume 0 == ~t2_st~0; [L535] havoc eval_~tmp_ndt_3~0; [L536] eval_~tmp_ndt_3~0 := eval_#t~nondet5; [L536] havoc eval_#t~nondet5; [L537-L544] assume !(0 != eval_~tmp_ndt_3~0); [L548-L561] assume 0 == ~t3_st~0; [L549] havoc eval_~tmp_ndt_4~0; [L550] eval_~tmp_ndt_4~0 := eval_#t~nondet6; [L550] havoc eval_#t~nondet6; [L551-L558] assume !(0 != eval_~tmp_ndt_4~0); [L562-L575] assume 0 == ~t4_st~0; [L563] havoc eval_~tmp_ndt_5~0; [L564] eval_~tmp_ndt_5~0 := eval_#t~nondet7; [L564] havoc eval_#t~nondet7; [L565-L572] assume !(0 != eval_~tmp_ndt_5~0); [L576-L589] assume 0 == ~t5_st~0; [L577] havoc eval_~tmp_ndt_6~0; [L578] eval_~tmp_ndt_6~0 := eval_#t~nondet8; [L578] havoc eval_#t~nondet8; [L579-L586] assume !(0 != eval_~tmp_ndt_6~0); [L496-L590] COND FALSE !(false) [L499] havoc exists_runnable_thread_#res; [L499] havoc exists_runnable_thread_~__retres1~6; [L451] havoc exists_runnable_thread_~__retres1~6; [L454] COND TRUE 0 == ~m_st~0 [L455] exists_runnable_thread_~__retres1~6 := 1; [L487] exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; [L499] eval_#t~ret2 := exists_runnable_thread_#res; [L499] eval_~tmp~0 := eval_#t~ret2; [L499] havoc eval_#t~ret2; [L501-L505] COND TRUE 0 != eval_~tmp~0 [L506] COND TRUE 0 == ~m_st~0 [L507] havoc eval_~tmp_ndt_1~0; [L508] eval_~tmp_ndt_1~0 := eval_#t~nondet3; [L508] havoc eval_#t~nondet3; [L509-L516] COND FALSE !(0 != eval_~tmp_ndt_1~0) [L520] COND TRUE 0 == ~t1_st~0 [L521] havoc eval_~tmp_ndt_2~0; [L522] eval_~tmp_ndt_2~0 := eval_#t~nondet4; [L522] havoc eval_#t~nondet4; [L523-L530] COND FALSE !(0 != eval_~tmp_ndt_2~0) [L534] COND TRUE 0 == ~t2_st~0 [L535] havoc eval_~tmp_ndt_3~0; [L536] eval_~tmp_ndt_3~0 := eval_#t~nondet5; [L536] havoc eval_#t~nondet5; [L537-L544] COND FALSE !(0 != eval_~tmp_ndt_3~0) [L548] COND TRUE 0 == ~t3_st~0 [L549] havoc eval_~tmp_ndt_4~0; [L550] eval_~tmp_ndt_4~0 := eval_#t~nondet6; [L550] havoc eval_#t~nondet6; [L551-L558] COND FALSE !(0 != eval_~tmp_ndt_4~0) [L562] COND TRUE 0 == ~t4_st~0 [L563] havoc eval_~tmp_ndt_5~0; [L564] eval_~tmp_ndt_5~0 := eval_#t~nondet7; [L564] havoc eval_#t~nondet7; [L565-L572] COND FALSE !(0 != eval_~tmp_ndt_5~0) [L576] COND TRUE 0 == ~t5_st~0 [L577] havoc eval_~tmp_ndt_6~0; [L578] eval_~tmp_ndt_6~0 := eval_#t~nondet8; [L578] havoc eval_#t~nondet8; [L579-L586] COND FALSE !(0 != eval_~tmp_ndt_6~0) ----- ----- class de.uni_freiburg.informatik.ultimate.boogie.procedureinliner.backtranslation.InlinerBacktranslator [L496-L590] COND FALSE !(false) [L499] havoc exists_runnable_thread_#res; [L499] havoc exists_runnable_thread_~__retres1~6; [L451] havoc exists_runnable_thread_~__retres1~6; [L454] COND TRUE 0 == ~m_st~0 [L455] exists_runnable_thread_~__retres1~6 := 1; [L487] exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; [L499] eval_#t~ret2 := exists_runnable_thread_#res; [L499] eval_~tmp~0 := eval_#t~ret2; [L499] havoc eval_#t~ret2; [L501-L505] COND TRUE 0 != eval_~tmp~0 [L506] COND TRUE 0 == ~m_st~0 [L507] havoc eval_~tmp_ndt_1~0; [L508] eval_~tmp_ndt_1~0 := eval_#t~nondet3; [L508] havoc eval_#t~nondet3; [L509-L516] COND FALSE !(0 != eval_~tmp_ndt_1~0) [L520] COND TRUE 0 == ~t1_st~0 [L521] havoc eval_~tmp_ndt_2~0; [L522] eval_~tmp_ndt_2~0 := eval_#t~nondet4; [L522] havoc eval_#t~nondet4; [L523-L530] COND FALSE !(0 != eval_~tmp_ndt_2~0) [L534] COND TRUE 0 == ~t2_st~0 [L535] havoc eval_~tmp_ndt_3~0; [L536] eval_~tmp_ndt_3~0 := eval_#t~nondet5; [L536] havoc eval_#t~nondet5; [L537-L544] COND FALSE !(0 != eval_~tmp_ndt_3~0) [L548] COND TRUE 0 == ~t3_st~0 [L549] havoc eval_~tmp_ndt_4~0; [L550] eval_~tmp_ndt_4~0 := eval_#t~nondet6; [L550] havoc eval_#t~nondet6; [L551-L558] COND FALSE !(0 != eval_~tmp_ndt_4~0) [L562] COND TRUE 0 == ~t4_st~0 [L563] havoc eval_~tmp_ndt_5~0; [L564] eval_~tmp_ndt_5~0 := eval_#t~nondet7; [L564] havoc eval_#t~nondet7; [L565-L572] COND FALSE !(0 != eval_~tmp_ndt_5~0) [L576] COND TRUE 0 == ~t5_st~0 [L577] havoc eval_~tmp_ndt_6~0; [L578] eval_~tmp_ndt_6~0 := eval_#t~nondet8; [L578] havoc eval_#t~nondet8; [L579-L586] COND FALSE !(0 != eval_~tmp_ndt_6~0) [L496-L590] COND FALSE !(false) [L451] havoc ~__retres1~6; [L454] COND TRUE 0 == ~m_st~0 [L455] ~__retres1~6 := 1; [L487] #res := ~__retres1~6; [L499] ~tmp~0 := #t~ret2; [L499] havoc #t~ret2; [L501-L505] COND TRUE 0 != ~tmp~0 [L506] COND TRUE 0 == ~m_st~0 [L507] havoc ~tmp_ndt_1~0; [L508] ~tmp_ndt_1~0 := #t~nondet3; [L508] havoc #t~nondet3; [L509-L516] COND FALSE !(0 != ~tmp_ndt_1~0) [L520] COND TRUE 0 == ~t1_st~0 [L521] havoc ~tmp_ndt_2~0; [L522] ~tmp_ndt_2~0 := #t~nondet4; [L522] havoc #t~nondet4; [L523-L530] COND FALSE !(0 != ~tmp_ndt_2~0) [L534] COND TRUE 0 == ~t2_st~0 [L535] havoc ~tmp_ndt_3~0; [L536] ~tmp_ndt_3~0 := #t~nondet5; [L536] havoc #t~nondet5; [L537-L544] COND FALSE !(0 != ~tmp_ndt_3~0) [L548] COND TRUE 0 == ~t3_st~0 [L549] havoc ~tmp_ndt_4~0; [L550] ~tmp_ndt_4~0 := #t~nondet6; [L550] havoc #t~nondet6; [L551-L558] COND FALSE !(0 != ~tmp_ndt_4~0) [L562] COND TRUE 0 == ~t4_st~0 [L563] havoc ~tmp_ndt_5~0; [L564] ~tmp_ndt_5~0 := #t~nondet7; [L564] havoc #t~nondet7; [L565-L572] COND FALSE !(0 != ~tmp_ndt_5~0) [L576] COND TRUE 0 == ~t5_st~0 [L577] havoc ~tmp_ndt_6~0; [L578] ~tmp_ndt_6~0 := #t~nondet8; [L578] havoc #t~nondet8; [L579-L586] COND FALSE !(0 != ~tmp_ndt_6~0) ----- ----- class de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.CACSL2BoogieBacktranslator [L496-L590] COND FALSE !(false) [L451] havoc ~__retres1~6; [L454] COND TRUE 0 == ~m_st~0 [L455] ~__retres1~6 := 1; [L487] #res := ~__retres1~6; [L499] ~tmp~0 := #t~ret2; [L499] havoc #t~ret2; [L501-L505] COND TRUE 0 != ~tmp~0 [L506] COND TRUE 0 == ~m_st~0 [L507] havoc ~tmp_ndt_1~0; [L508] ~tmp_ndt_1~0 := #t~nondet3; [L508] havoc #t~nondet3; [L509-L516] COND FALSE !(0 != ~tmp_ndt_1~0) [L520] COND TRUE 0 == ~t1_st~0 [L521] havoc ~tmp_ndt_2~0; [L522] ~tmp_ndt_2~0 := #t~nondet4; [L522] havoc #t~nondet4; [L523-L530] COND FALSE !(0 != ~tmp_ndt_2~0) [L534] COND TRUE 0 == ~t2_st~0 [L535] havoc ~tmp_ndt_3~0; [L536] ~tmp_ndt_3~0 := #t~nondet5; [L536] havoc #t~nondet5; [L537-L544] COND FALSE !(0 != ~tmp_ndt_3~0) [L548] COND TRUE 0 == ~t3_st~0 [L549] havoc ~tmp_ndt_4~0; [L550] ~tmp_ndt_4~0 := #t~nondet6; [L550] havoc #t~nondet6; [L551-L558] COND FALSE !(0 != ~tmp_ndt_4~0) [L562] COND TRUE 0 == ~t4_st~0 [L563] havoc ~tmp_ndt_5~0; [L564] ~tmp_ndt_5~0 := #t~nondet7; [L564] havoc #t~nondet7; [L565-L572] COND FALSE !(0 != ~tmp_ndt_5~0) [L576] COND TRUE 0 == ~t5_st~0 [L577] havoc ~tmp_ndt_6~0; [L578] ~tmp_ndt_6~0 := #t~nondet8; [L578] havoc #t~nondet8; [L579-L586] COND FALSE !(0 != ~tmp_ndt_6~0) [L496] COND TRUE 1 [L451] int __retres1 ; [L454] COND TRUE m_st == 0 [L455] __retres1 = 1 [L487] return (__retres1); [L499] tmp = exists_runnable_thread() [L501] COND TRUE \read(tmp) [L506] COND TRUE m_st == 0 [L507] int tmp_ndt_1; [L508] tmp_ndt_1 = __VERIFIER_nondet_int() [L509] COND FALSE !(\read(tmp_ndt_1)) [L520] COND TRUE t1_st == 0 [L521] int tmp_ndt_2; [L522] tmp_ndt_2 = __VERIFIER_nondet_int() [L523] COND FALSE !(\read(tmp_ndt_2)) [L534] COND TRUE t2_st == 0 [L535] int tmp_ndt_3; [L536] tmp_ndt_3 = __VERIFIER_nondet_int() [L537] COND FALSE !(\read(tmp_ndt_3)) [L548] COND TRUE t3_st == 0 [L549] int tmp_ndt_4; [L550] tmp_ndt_4 = __VERIFIER_nondet_int() [L551] COND FALSE !(\read(tmp_ndt_4)) [L562] COND TRUE t4_st == 0 [L563] int tmp_ndt_5; [L564] tmp_ndt_5 = __VERIFIER_nondet_int() [L565] COND FALSE !(\read(tmp_ndt_5)) [L576] COND TRUE t5_st == 0 [L577] int tmp_ndt_6; [L578] tmp_ndt_6 = __VERIFIER_nondet_int() [L579] COND FALSE !(\read(tmp_ndt_6)) ----- [2018-11-23 00:24:02,251 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer CFG 23.11 12:24:02 BoogieIcfgContainer [2018-11-23 00:24:02,251 INFO L132 PluginConnector]: ------------------------ END BuchiAutomizer---------------------------- [2018-11-23 00:24:02,251 INFO L113 PluginConnector]: ------------------------Witness Printer---------------------------- [2018-11-23 00:24:02,251 INFO L271 PluginConnector]: Initializing Witness Printer... [2018-11-23 00:24:02,251 INFO L276 PluginConnector]: Witness Printer initialized [2018-11-23 00:24:02,252 INFO L185 PluginConnector]: Executing the observer RCFGCatcher from plugin Witness Printer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 23.11 12:23:54" (3/4) ... [2018-11-23 00:24:02,254 INFO L141 WitnessPrinter]: Generating witness for non-termination counterexample ----- class de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder.RCFGBacktranslator [?] ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; [?] havoc main_#res;havoc main_~__retres1~7;havoc main_~__retres1~7;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; [?] havoc start_simulation_#t~ret16, start_simulation_#t~ret17, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; [?] assume 1 == ~m_i~0;~m_st~0 := 0; [?] assume 1 == ~t1_i~0;~t1_st~0 := 0; [?] assume 1 == ~t2_i~0;~t2_st~0 := 0; [?] assume 1 == ~t3_i~0;~t3_st~0 := 0; [?] assume 1 == ~t4_i~0;~t4_st~0 := 0; [?] assume 1 == ~t5_i~0;~t5_st~0 := 0; [?] assume !(0 == ~M_E~0); [?] assume !(0 == ~T1_E~0); [?] assume !(0 == ~T2_E~0); [?] assume !(0 == ~T3_E~0); [?] assume !(0 == ~T4_E~0); [?] assume !(0 == ~T5_E~0); [?] assume !(0 == ~E_M~0); [?] assume !(0 == ~E_1~0); [?] assume !(0 == ~E_2~0); [?] assume !(0 == ~E_3~0); [?] assume !(0 == ~E_4~0); [?] assume !(0 == ~E_5~0); [?] havoc activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; [?] assume !(1 == ~m_pc~0); [?] is_master_triggered_~__retres1~0 := 0; [?] is_master_triggered_#res := is_master_triggered_~__retres1~0; [?] activate_threads_#t~ret9 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; [?] assume !(0 != activate_threads_~tmp~1); [?] havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; [?] assume !(1 == ~t1_pc~0); [?] is_transmit1_triggered_~__retres1~1 := 0; [?] is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; [?] activate_threads_#t~ret10 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; [?] assume !(0 != activate_threads_~tmp___0~0); [?] havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; [?] assume !(1 == ~t2_pc~0); [?] is_transmit2_triggered_~__retres1~2 := 0; [?] is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; [?] activate_threads_#t~ret11 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; [?] assume !(0 != activate_threads_~tmp___1~0); [?] havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; [?] assume !(1 == ~t3_pc~0); [?] is_transmit3_triggered_~__retres1~3 := 0; [?] is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; [?] activate_threads_#t~ret12 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; [?] assume !(0 != activate_threads_~tmp___2~0); [?] havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; [?] assume !(1 == ~t4_pc~0); [?] is_transmit4_triggered_~__retres1~4 := 0; [?] is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; [?] activate_threads_#t~ret13 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; [?] assume !(0 != activate_threads_~tmp___3~0); [?] havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; [?] assume !(1 == ~t5_pc~0); [?] is_transmit5_triggered_~__retres1~5 := 0; [?] is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; [?] activate_threads_#t~ret14 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; [?] assume !(0 != activate_threads_~tmp___4~0); [?] assume !(1 == ~M_E~0); [?] assume !(1 == ~T1_E~0); [?] assume !(1 == ~T2_E~0); [?] assume !(1 == ~T3_E~0); [?] assume !(1 == ~T4_E~0); [?] assume !(1 == ~T5_E~0); [?] assume !(1 == ~E_M~0); [?] assume !(1 == ~E_1~0); [?] assume !(1 == ~E_2~0); [?] assume !(1 == ~E_3~0); [?] assume !(1 == ~E_4~0); [?] assume !(1 == ~E_5~0); [?] assume !false; [?] start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret2, eval_#t~nondet3, eval_~tmp_ndt_1~0, eval_#t~nondet4, eval_~tmp_ndt_2~0, eval_#t~nondet5, eval_~tmp_ndt_3~0, eval_#t~nondet6, eval_~tmp_ndt_4~0, eval_#t~nondet7, eval_~tmp_ndt_5~0, eval_#t~nondet8, eval_~tmp_ndt_6~0, eval_~tmp~0;havoc eval_~tmp~0; [L14] ~m_pc~0 := 0; [L15] ~t1_pc~0 := 0; [L16] ~t2_pc~0 := 0; [L17] ~t3_pc~0 := 0; [L18] ~t4_pc~0 := 0; [L19] ~t5_pc~0 := 0; [L20] ~m_st~0 := 0; [L21] ~t1_st~0 := 0; [L22] ~t2_st~0 := 0; [L23] ~t3_st~0 := 0; [L24] ~t4_st~0 := 0; [L25] ~t5_st~0 := 0; [L26] ~m_i~0 := 0; [L27] ~t1_i~0 := 0; [L28] ~t2_i~0 := 0; [L29] ~t3_i~0 := 0; [L30] ~t4_i~0 := 0; [L31] ~t5_i~0 := 0; [L32] ~M_E~0 := 2; [L33] ~T1_E~0 := 2; [L34] ~T2_E~0 := 2; [L35] ~T3_E~0 := 2; [L36] ~T4_E~0 := 2; [L37] ~T5_E~0 := 2; [L38] ~E_M~0 := 2; [L39] ~E_1~0 := 2; [L40] ~E_2~0 := 2; [L41] ~E_3~0 := 2; [L42] ~E_4~0 := 2; [L43] ~E_5~0 := 2; [L51] ~token~0 := 0; [L53] ~local~0 := 0; [?] havoc main_#res; [?] havoc main_~__retres1~7; [L975] havoc main_~__retres1~7; [L886] ~m_i~0 := 1; [L887] ~t1_i~0 := 1; [L888] ~t2_i~0 := 1; [L889] ~t3_i~0 := 1; [L890] ~t4_i~0 := 1; [L891] ~t5_i~0 := 1; [L980] havoc start_simulation_#t~ret16, start_simulation_#t~ret17, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1; [L916] havoc start_simulation_~kernel_st~0; [L917] havoc start_simulation_~tmp~3; [L918] havoc start_simulation_~tmp___0~1; [L922] start_simulation_~kernel_st~0 := 0; [L416-L420] assume 1 == ~m_i~0; [L417] ~m_st~0 := 0; [L421-L425] assume 1 == ~t1_i~0; [L422] ~t1_st~0 := 0; [L426-L430] assume 1 == ~t2_i~0; [L427] ~t2_st~0 := 0; [L431-L435] assume 1 == ~t3_i~0; [L432] ~t3_st~0 := 0; [L436-L440] assume 1 == ~t4_i~0; [L437] ~t4_st~0 := 0; [L441-L445] assume 1 == ~t5_i~0; [L442] ~t5_st~0 := 0; [L601-L605] assume !(0 == ~M_E~0); [L606-L610] assume !(0 == ~T1_E~0); [L611-L615] assume !(0 == ~T2_E~0); [L616-L620] assume !(0 == ~T3_E~0); [L621-L625] assume !(0 == ~T4_E~0); [L626-L630] assume !(0 == ~T5_E~0); [L631-L635] assume !(0 == ~E_M~0); [L636-L640] assume !(0 == ~E_1~0); [L641-L645] assume !(0 == ~E_2~0); [L646-L650] assume !(0 == ~E_3~0); [L651-L655] assume !(0 == ~E_4~0); [L656-L660] assume !(0 == ~E_5~0); [L926] havoc activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0; [L734] havoc activate_threads_~tmp~1; [L735] havoc activate_threads_~tmp___0~0; [L736] havoc activate_threads_~tmp___1~0; [L737] havoc activate_threads_~tmp___2~0; [L738] havoc activate_threads_~tmp___3~0; [L739] havoc activate_threads_~tmp___4~0; [L743] havoc is_master_triggered_#res; [L743] havoc is_master_triggered_~__retres1~0; [L291] havoc is_master_triggered_~__retres1~0; [L294-L303] assume !(1 == ~m_pc~0); [L304] is_master_triggered_~__retres1~0 := 0; [L306] is_master_triggered_#res := is_master_triggered_~__retres1~0; [L743] activate_threads_#t~ret9 := is_master_triggered_#res; [L743] activate_threads_~tmp~1 := activate_threads_#t~ret9; [L743] havoc activate_threads_#t~ret9; [L745-L749] assume !(0 != activate_threads_~tmp~1); [L751] havoc is_transmit1_triggered_#res; [L751] havoc is_transmit1_triggered_~__retres1~1; [L310] havoc is_transmit1_triggered_~__retres1~1; [L313-L322] assume !(1 == ~t1_pc~0); [L323] is_transmit1_triggered_~__retres1~1 := 0; [L325] is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; [L751] activate_threads_#t~ret10 := is_transmit1_triggered_#res; [L751] activate_threads_~tmp___0~0 := activate_threads_#t~ret10; [L751] havoc activate_threads_#t~ret10; [L753-L757] assume !(0 != activate_threads_~tmp___0~0); [L759] havoc is_transmit2_triggered_#res; [L759] havoc is_transmit2_triggered_~__retres1~2; [L329] havoc is_transmit2_triggered_~__retres1~2; [L332-L341] assume !(1 == ~t2_pc~0); [L342] is_transmit2_triggered_~__retres1~2 := 0; [L344] is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; [L759] activate_threads_#t~ret11 := is_transmit2_triggered_#res; [L759] activate_threads_~tmp___1~0 := activate_threads_#t~ret11; [L759] havoc activate_threads_#t~ret11; [L761-L765] assume !(0 != activate_threads_~tmp___1~0); [L767] havoc is_transmit3_triggered_#res; [L767] havoc is_transmit3_triggered_~__retres1~3; [L348] havoc is_transmit3_triggered_~__retres1~3; [L351-L360] assume !(1 == ~t3_pc~0); [L361] is_transmit3_triggered_~__retres1~3 := 0; [L363] is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; [L767] activate_threads_#t~ret12 := is_transmit3_triggered_#res; [L767] activate_threads_~tmp___2~0 := activate_threads_#t~ret12; [L767] havoc activate_threads_#t~ret12; [L769-L773] assume !(0 != activate_threads_~tmp___2~0); [L775] havoc is_transmit4_triggered_#res; [L775] havoc is_transmit4_triggered_~__retres1~4; [L367] havoc is_transmit4_triggered_~__retres1~4; [L370-L379] assume !(1 == ~t4_pc~0); [L380] is_transmit4_triggered_~__retres1~4 := 0; [L382] is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; [L775] activate_threads_#t~ret13 := is_transmit4_triggered_#res; [L775] activate_threads_~tmp___3~0 := activate_threads_#t~ret13; [L775] havoc activate_threads_#t~ret13; [L777-L781] assume !(0 != activate_threads_~tmp___3~0); [L783] havoc is_transmit5_triggered_#res; [L783] havoc is_transmit5_triggered_~__retres1~5; [L386] havoc is_transmit5_triggered_~__retres1~5; [L389-L398] assume !(1 == ~t5_pc~0); [L399] is_transmit5_triggered_~__retres1~5 := 0; [L401] is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; [L783] activate_threads_#t~ret14 := is_transmit5_triggered_#res; [L783] activate_threads_~tmp___4~0 := activate_threads_#t~ret14; [L783] havoc activate_threads_#t~ret14; [L785-L789] assume !(0 != activate_threads_~tmp___4~0); [L669-L673] assume !(1 == ~M_E~0); [L674-L678] assume !(1 == ~T1_E~0); [L679-L683] assume !(1 == ~T2_E~0); [L684-L688] assume !(1 == ~T3_E~0); [L689-L693] assume !(1 == ~T4_E~0); [L694-L698] assume !(1 == ~T5_E~0); [L699-L703] assume !(1 == ~E_M~0); [L704-L708] assume !(1 == ~E_1~0); [L709-L713] assume !(1 == ~E_2~0); [L714-L718] assume !(1 == ~E_3~0); [L719-L723] assume !(1 == ~E_4~0); [L724-L728] assume !(1 == ~E_5~0); [L930-L967] assume !false; [L933] start_simulation_~kernel_st~0 := 1; [L934] havoc eval_#t~ret2, eval_#t~nondet3, eval_~tmp_ndt_1~0, eval_#t~nondet4, eval_~tmp_ndt_2~0, eval_#t~nondet5, eval_~tmp_ndt_3~0, eval_#t~nondet6, eval_~tmp_ndt_4~0, eval_#t~nondet7, eval_~tmp_ndt_5~0, eval_#t~nondet8, eval_~tmp_ndt_6~0, eval_~tmp~0; [L492] havoc eval_~tmp~0; ----- ----- class de.uni_freiburg.informatik.ultimate.boogie.preprocessor.BoogiePreprocessorBacktranslator [L14] ~m_pc~0 := 0; [L15] ~t1_pc~0 := 0; [L16] ~t2_pc~0 := 0; [L17] ~t3_pc~0 := 0; [L18] ~t4_pc~0 := 0; [L19] ~t5_pc~0 := 0; [L20] ~m_st~0 := 0; [L21] ~t1_st~0 := 0; [L22] ~t2_st~0 := 0; [L23] ~t3_st~0 := 0; [L24] ~t4_st~0 := 0; [L25] ~t5_st~0 := 0; [L26] ~m_i~0 := 0; [L27] ~t1_i~0 := 0; [L28] ~t2_i~0 := 0; [L29] ~t3_i~0 := 0; [L30] ~t4_i~0 := 0; [L31] ~t5_i~0 := 0; [L32] ~M_E~0 := 2; [L33] ~T1_E~0 := 2; [L34] ~T2_E~0 := 2; [L35] ~T3_E~0 := 2; [L36] ~T4_E~0 := 2; [L37] ~T5_E~0 := 2; [L38] ~E_M~0 := 2; [L39] ~E_1~0 := 2; [L40] ~E_2~0 := 2; [L41] ~E_3~0 := 2; [L42] ~E_4~0 := 2; [L43] ~E_5~0 := 2; [L51] ~token~0 := 0; [L53] ~local~0 := 0; [?] havoc main_#res; [?] havoc main_~__retres1~7; [L975] havoc main_~__retres1~7; [L886] ~m_i~0 := 1; [L887] ~t1_i~0 := 1; [L888] ~t2_i~0 := 1; [L889] ~t3_i~0 := 1; [L890] ~t4_i~0 := 1; [L891] ~t5_i~0 := 1; [L980] havoc start_simulation_#t~ret16, start_simulation_#t~ret17, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1; [L916] havoc start_simulation_~kernel_st~0; [L917] havoc start_simulation_~tmp~3; [L918] havoc start_simulation_~tmp___0~1; [L922] start_simulation_~kernel_st~0 := 0; [L416-L420] assume 1 == ~m_i~0; [L417] ~m_st~0 := 0; [L421-L425] assume 1 == ~t1_i~0; [L422] ~t1_st~0 := 0; [L426-L430] assume 1 == ~t2_i~0; [L427] ~t2_st~0 := 0; [L431-L435] assume 1 == ~t3_i~0; [L432] ~t3_st~0 := 0; [L436-L440] assume 1 == ~t4_i~0; [L437] ~t4_st~0 := 0; [L441-L445] assume 1 == ~t5_i~0; [L442] ~t5_st~0 := 0; [L601-L605] assume !(0 == ~M_E~0); [L606-L610] assume !(0 == ~T1_E~0); [L611-L615] assume !(0 == ~T2_E~0); [L616-L620] assume !(0 == ~T3_E~0); [L621-L625] assume !(0 == ~T4_E~0); [L626-L630] assume !(0 == ~T5_E~0); [L631-L635] assume !(0 == ~E_M~0); [L636-L640] assume !(0 == ~E_1~0); [L641-L645] assume !(0 == ~E_2~0); [L646-L650] assume !(0 == ~E_3~0); [L651-L655] assume !(0 == ~E_4~0); [L656-L660] assume !(0 == ~E_5~0); [L926] havoc activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0; [L734] havoc activate_threads_~tmp~1; [L735] havoc activate_threads_~tmp___0~0; [L736] havoc activate_threads_~tmp___1~0; [L737] havoc activate_threads_~tmp___2~0; [L738] havoc activate_threads_~tmp___3~0; [L739] havoc activate_threads_~tmp___4~0; [L743] havoc is_master_triggered_#res; [L743] havoc is_master_triggered_~__retres1~0; [L291] havoc is_master_triggered_~__retres1~0; [L294-L303] assume !(1 == ~m_pc~0); [L304] is_master_triggered_~__retres1~0 := 0; [L306] is_master_triggered_#res := is_master_triggered_~__retres1~0; [L743] activate_threads_#t~ret9 := is_master_triggered_#res; [L743] activate_threads_~tmp~1 := activate_threads_#t~ret9; [L743] havoc activate_threads_#t~ret9; [L745-L749] assume !(0 != activate_threads_~tmp~1); [L751] havoc is_transmit1_triggered_#res; [L751] havoc is_transmit1_triggered_~__retres1~1; [L310] havoc is_transmit1_triggered_~__retres1~1; [L313-L322] assume !(1 == ~t1_pc~0); [L323] is_transmit1_triggered_~__retres1~1 := 0; [L325] is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; [L751] activate_threads_#t~ret10 := is_transmit1_triggered_#res; [L751] activate_threads_~tmp___0~0 := activate_threads_#t~ret10; [L751] havoc activate_threads_#t~ret10; [L753-L757] assume !(0 != activate_threads_~tmp___0~0); [L759] havoc is_transmit2_triggered_#res; [L759] havoc is_transmit2_triggered_~__retres1~2; [L329] havoc is_transmit2_triggered_~__retres1~2; [L332-L341] assume !(1 == ~t2_pc~0); [L342] is_transmit2_triggered_~__retres1~2 := 0; [L344] is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; [L759] activate_threads_#t~ret11 := is_transmit2_triggered_#res; [L759] activate_threads_~tmp___1~0 := activate_threads_#t~ret11; [L759] havoc activate_threads_#t~ret11; [L761-L765] assume !(0 != activate_threads_~tmp___1~0); [L767] havoc is_transmit3_triggered_#res; [L767] havoc is_transmit3_triggered_~__retres1~3; [L348] havoc is_transmit3_triggered_~__retres1~3; [L351-L360] assume !(1 == ~t3_pc~0); [L361] is_transmit3_triggered_~__retres1~3 := 0; [L363] is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; [L767] activate_threads_#t~ret12 := is_transmit3_triggered_#res; [L767] activate_threads_~tmp___2~0 := activate_threads_#t~ret12; [L767] havoc activate_threads_#t~ret12; [L769-L773] assume !(0 != activate_threads_~tmp___2~0); [L775] havoc is_transmit4_triggered_#res; [L775] havoc is_transmit4_triggered_~__retres1~4; [L367] havoc is_transmit4_triggered_~__retres1~4; [L370-L379] assume !(1 == ~t4_pc~0); [L380] is_transmit4_triggered_~__retres1~4 := 0; [L382] is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; [L775] activate_threads_#t~ret13 := is_transmit4_triggered_#res; [L775] activate_threads_~tmp___3~0 := activate_threads_#t~ret13; [L775] havoc activate_threads_#t~ret13; [L777-L781] assume !(0 != activate_threads_~tmp___3~0); [L783] havoc is_transmit5_triggered_#res; [L783] havoc is_transmit5_triggered_~__retres1~5; [L386] havoc is_transmit5_triggered_~__retres1~5; [L389-L398] assume !(1 == ~t5_pc~0); [L399] is_transmit5_triggered_~__retres1~5 := 0; [L401] is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; [L783] activate_threads_#t~ret14 := is_transmit5_triggered_#res; [L783] activate_threads_~tmp___4~0 := activate_threads_#t~ret14; [L783] havoc activate_threads_#t~ret14; [L785-L789] assume !(0 != activate_threads_~tmp___4~0); [L669-L673] assume !(1 == ~M_E~0); [L674-L678] assume !(1 == ~T1_E~0); [L679-L683] assume !(1 == ~T2_E~0); [L684-L688] assume !(1 == ~T3_E~0); [L689-L693] assume !(1 == ~T4_E~0); [L694-L698] assume !(1 == ~T5_E~0); [L699-L703] assume !(1 == ~E_M~0); [L704-L708] assume !(1 == ~E_1~0); [L709-L713] assume !(1 == ~E_2~0); [L714-L718] assume !(1 == ~E_3~0); [L719-L723] assume !(1 == ~E_4~0); [L724-L728] assume !(1 == ~E_5~0); [L930-L967] assume !false; [L933] start_simulation_~kernel_st~0 := 1; [L934] havoc eval_#t~ret2, eval_#t~nondet3, eval_~tmp_ndt_1~0, eval_#t~nondet4, eval_~tmp_ndt_2~0, eval_#t~nondet5, eval_~tmp_ndt_3~0, eval_#t~nondet6, eval_~tmp_ndt_4~0, eval_#t~nondet7, eval_~tmp_ndt_5~0, eval_#t~nondet8, eval_~tmp_ndt_6~0, eval_~tmp~0; [L492] havoc eval_~tmp~0; [L14] ~m_pc~0 := 0; [L15] ~t1_pc~0 := 0; [L16] ~t2_pc~0 := 0; [L17] ~t3_pc~0 := 0; [L18] ~t4_pc~0 := 0; [L19] ~t5_pc~0 := 0; [L20] ~m_st~0 := 0; [L21] ~t1_st~0 := 0; [L22] ~t2_st~0 := 0; [L23] ~t3_st~0 := 0; [L24] ~t4_st~0 := 0; [L25] ~t5_st~0 := 0; [L26] ~m_i~0 := 0; [L27] ~t1_i~0 := 0; [L28] ~t2_i~0 := 0; [L29] ~t3_i~0 := 0; [L30] ~t4_i~0 := 0; [L31] ~t5_i~0 := 0; [L32] ~M_E~0 := 2; [L33] ~T1_E~0 := 2; [L34] ~T2_E~0 := 2; [L35] ~T3_E~0 := 2; [L36] ~T4_E~0 := 2; [L37] ~T5_E~0 := 2; [L38] ~E_M~0 := 2; [L39] ~E_1~0 := 2; [L40] ~E_2~0 := 2; [L41] ~E_3~0 := 2; [L42] ~E_4~0 := 2; [L43] ~E_5~0 := 2; [L51] ~token~0 := 0; [L53] ~local~0 := 0; [?] havoc main_#res; [?] havoc main_~__retres1~7; [L975] havoc main_~__retres1~7; [L886] ~m_i~0 := 1; [L887] ~t1_i~0 := 1; [L888] ~t2_i~0 := 1; [L889] ~t3_i~0 := 1; [L890] ~t4_i~0 := 1; [L891] ~t5_i~0 := 1; [L980] havoc start_simulation_#t~ret16, start_simulation_#t~ret17, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1; [L916] havoc start_simulation_~kernel_st~0; [L917] havoc start_simulation_~tmp~3; [L918] havoc start_simulation_~tmp___0~1; [L922] start_simulation_~kernel_st~0 := 0; [L416] COND TRUE 1 == ~m_i~0 [L417] ~m_st~0 := 0; [L421] COND TRUE 1 == ~t1_i~0 [L422] ~t1_st~0 := 0; [L426] COND TRUE 1 == ~t2_i~0 [L427] ~t2_st~0 := 0; [L431] COND TRUE 1 == ~t3_i~0 [L432] ~t3_st~0 := 0; [L436] COND TRUE 1 == ~t4_i~0 [L437] ~t4_st~0 := 0; [L441] COND TRUE 1 == ~t5_i~0 [L442] ~t5_st~0 := 0; [L601] COND FALSE !(0 == ~M_E~0) [L606] COND FALSE !(0 == ~T1_E~0) [L611] COND FALSE !(0 == ~T2_E~0) [L616] COND FALSE !(0 == ~T3_E~0) [L621] COND FALSE !(0 == ~T4_E~0) [L626] COND FALSE !(0 == ~T5_E~0) [L631] COND FALSE !(0 == ~E_M~0) [L636] COND FALSE !(0 == ~E_1~0) [L641] COND FALSE !(0 == ~E_2~0) [L646] COND FALSE !(0 == ~E_3~0) [L651] COND FALSE !(0 == ~E_4~0) [L656] COND FALSE !(0 == ~E_5~0) [L926] havoc activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0; [L734] havoc activate_threads_~tmp~1; [L735] havoc activate_threads_~tmp___0~0; [L736] havoc activate_threads_~tmp___1~0; [L737] havoc activate_threads_~tmp___2~0; [L738] havoc activate_threads_~tmp___3~0; [L739] havoc activate_threads_~tmp___4~0; [L743] havoc is_master_triggered_#res; [L743] havoc is_master_triggered_~__retres1~0; [L291] havoc is_master_triggered_~__retres1~0; [L294] COND FALSE !(1 == ~m_pc~0) [L304] is_master_triggered_~__retres1~0 := 0; [L306] is_master_triggered_#res := is_master_triggered_~__retres1~0; [L743] activate_threads_#t~ret9 := is_master_triggered_#res; [L743] activate_threads_~tmp~1 := activate_threads_#t~ret9; [L743] havoc activate_threads_#t~ret9; [L745-L749] COND FALSE !(0 != activate_threads_~tmp~1) [L751] havoc is_transmit1_triggered_#res; [L751] havoc is_transmit1_triggered_~__retres1~1; [L310] havoc is_transmit1_triggered_~__retres1~1; [L313] COND FALSE !(1 == ~t1_pc~0) [L323] is_transmit1_triggered_~__retres1~1 := 0; [L325] is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; [L751] activate_threads_#t~ret10 := is_transmit1_triggered_#res; [L751] activate_threads_~tmp___0~0 := activate_threads_#t~ret10; [L751] havoc activate_threads_#t~ret10; [L753-L757] COND FALSE !(0 != activate_threads_~tmp___0~0) [L759] havoc is_transmit2_triggered_#res; [L759] havoc is_transmit2_triggered_~__retres1~2; [L329] havoc is_transmit2_triggered_~__retres1~2; [L332] COND FALSE !(1 == ~t2_pc~0) [L342] is_transmit2_triggered_~__retres1~2 := 0; [L344] is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; [L759] activate_threads_#t~ret11 := is_transmit2_triggered_#res; [L759] activate_threads_~tmp___1~0 := activate_threads_#t~ret11; [L759] havoc activate_threads_#t~ret11; [L761-L765] COND FALSE !(0 != activate_threads_~tmp___1~0) [L767] havoc is_transmit3_triggered_#res; [L767] havoc is_transmit3_triggered_~__retres1~3; [L348] havoc is_transmit3_triggered_~__retres1~3; [L351] COND FALSE !(1 == ~t3_pc~0) [L361] is_transmit3_triggered_~__retres1~3 := 0; [L363] is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; [L767] activate_threads_#t~ret12 := is_transmit3_triggered_#res; [L767] activate_threads_~tmp___2~0 := activate_threads_#t~ret12; [L767] havoc activate_threads_#t~ret12; [L769-L773] COND FALSE !(0 != activate_threads_~tmp___2~0) [L775] havoc is_transmit4_triggered_#res; [L775] havoc is_transmit4_triggered_~__retres1~4; [L367] havoc is_transmit4_triggered_~__retres1~4; [L370] COND FALSE !(1 == ~t4_pc~0) [L380] is_transmit4_triggered_~__retres1~4 := 0; [L382] is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; [L775] activate_threads_#t~ret13 := is_transmit4_triggered_#res; [L775] activate_threads_~tmp___3~0 := activate_threads_#t~ret13; [L775] havoc activate_threads_#t~ret13; [L777-L781] COND FALSE !(0 != activate_threads_~tmp___3~0) [L783] havoc is_transmit5_triggered_#res; [L783] havoc is_transmit5_triggered_~__retres1~5; [L386] havoc is_transmit5_triggered_~__retres1~5; [L389] COND FALSE !(1 == ~t5_pc~0) [L399] is_transmit5_triggered_~__retres1~5 := 0; [L401] is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; [L783] activate_threads_#t~ret14 := is_transmit5_triggered_#res; [L783] activate_threads_~tmp___4~0 := activate_threads_#t~ret14; [L783] havoc activate_threads_#t~ret14; [L785-L789] COND FALSE !(0 != activate_threads_~tmp___4~0) [L669] COND FALSE !(1 == ~M_E~0) [L674] COND FALSE !(1 == ~T1_E~0) [L679] COND FALSE !(1 == ~T2_E~0) [L684] COND FALSE !(1 == ~T3_E~0) [L689] COND FALSE !(1 == ~T4_E~0) [L694] COND FALSE !(1 == ~T5_E~0) [L699] COND FALSE !(1 == ~E_M~0) [L704] COND FALSE !(1 == ~E_1~0) [L709] COND FALSE !(1 == ~E_2~0) [L714] COND FALSE !(1 == ~E_3~0) [L719] COND FALSE !(1 == ~E_4~0) [L724] COND FALSE !(1 == ~E_5~0) [L930-L967] COND FALSE !(false) [L933] start_simulation_~kernel_st~0 := 1; [L934] havoc eval_#t~ret2, eval_#t~nondet3, eval_~tmp_ndt_1~0, eval_#t~nondet4, eval_~tmp_ndt_2~0, eval_#t~nondet5, eval_~tmp_ndt_3~0, eval_#t~nondet6, eval_~tmp_ndt_4~0, eval_#t~nondet7, eval_~tmp_ndt_5~0, eval_#t~nondet8, eval_~tmp_ndt_6~0, eval_~tmp~0; [L492] havoc eval_~tmp~0; ----- ----- class de.uni_freiburg.informatik.ultimate.boogie.procedureinliner.backtranslation.InlinerBacktranslator [L14] ~m_pc~0 := 0; [L15] ~t1_pc~0 := 0; [L16] ~t2_pc~0 := 0; [L17] ~t3_pc~0 := 0; [L18] ~t4_pc~0 := 0; [L19] ~t5_pc~0 := 0; [L20] ~m_st~0 := 0; [L21] ~t1_st~0 := 0; [L22] ~t2_st~0 := 0; [L23] ~t3_st~0 := 0; [L24] ~t4_st~0 := 0; [L25] ~t5_st~0 := 0; [L26] ~m_i~0 := 0; [L27] ~t1_i~0 := 0; [L28] ~t2_i~0 := 0; [L29] ~t3_i~0 := 0; [L30] ~t4_i~0 := 0; [L31] ~t5_i~0 := 0; [L32] ~M_E~0 := 2; [L33] ~T1_E~0 := 2; [L34] ~T2_E~0 := 2; [L35] ~T3_E~0 := 2; [L36] ~T4_E~0 := 2; [L37] ~T5_E~0 := 2; [L38] ~E_M~0 := 2; [L39] ~E_1~0 := 2; [L40] ~E_2~0 := 2; [L41] ~E_3~0 := 2; [L42] ~E_4~0 := 2; [L43] ~E_5~0 := 2; [L51] ~token~0 := 0; [L53] ~local~0 := 0; [?] havoc main_#res; [?] havoc main_~__retres1~7; [L975] havoc main_~__retres1~7; [L886] ~m_i~0 := 1; [L887] ~t1_i~0 := 1; [L888] ~t2_i~0 := 1; [L889] ~t3_i~0 := 1; [L890] ~t4_i~0 := 1; [L891] ~t5_i~0 := 1; [L980] havoc start_simulation_#t~ret16, start_simulation_#t~ret17, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1; [L916] havoc start_simulation_~kernel_st~0; [L917] havoc start_simulation_~tmp~3; [L918] havoc start_simulation_~tmp___0~1; [L922] start_simulation_~kernel_st~0 := 0; [L416] COND TRUE 1 == ~m_i~0 [L417] ~m_st~0 := 0; [L421] COND TRUE 1 == ~t1_i~0 [L422] ~t1_st~0 := 0; [L426] COND TRUE 1 == ~t2_i~0 [L427] ~t2_st~0 := 0; [L431] COND TRUE 1 == ~t3_i~0 [L432] ~t3_st~0 := 0; [L436] COND TRUE 1 == ~t4_i~0 [L437] ~t4_st~0 := 0; [L441] COND TRUE 1 == ~t5_i~0 [L442] ~t5_st~0 := 0; [L601] COND FALSE !(0 == ~M_E~0) [L606] COND FALSE !(0 == ~T1_E~0) [L611] COND FALSE !(0 == ~T2_E~0) [L616] COND FALSE !(0 == ~T3_E~0) [L621] COND FALSE !(0 == ~T4_E~0) [L626] COND FALSE !(0 == ~T5_E~0) [L631] COND FALSE !(0 == ~E_M~0) [L636] COND FALSE !(0 == ~E_1~0) [L641] COND FALSE !(0 == ~E_2~0) [L646] COND FALSE !(0 == ~E_3~0) [L651] COND FALSE !(0 == ~E_4~0) [L656] COND FALSE !(0 == ~E_5~0) [L926] havoc activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0; [L734] havoc activate_threads_~tmp~1; [L735] havoc activate_threads_~tmp___0~0; [L736] havoc activate_threads_~tmp___1~0; [L737] havoc activate_threads_~tmp___2~0; [L738] havoc activate_threads_~tmp___3~0; [L739] havoc activate_threads_~tmp___4~0; [L743] havoc is_master_triggered_#res; [L743] havoc is_master_triggered_~__retres1~0; [L291] havoc is_master_triggered_~__retres1~0; [L294] COND FALSE !(1 == ~m_pc~0) [L304] is_master_triggered_~__retres1~0 := 0; [L306] is_master_triggered_#res := is_master_triggered_~__retres1~0; [L743] activate_threads_#t~ret9 := is_master_triggered_#res; [L743] activate_threads_~tmp~1 := activate_threads_#t~ret9; [L743] havoc activate_threads_#t~ret9; [L745-L749] COND FALSE !(0 != activate_threads_~tmp~1) [L751] havoc is_transmit1_triggered_#res; [L751] havoc is_transmit1_triggered_~__retres1~1; [L310] havoc is_transmit1_triggered_~__retres1~1; [L313] COND FALSE !(1 == ~t1_pc~0) [L323] is_transmit1_triggered_~__retres1~1 := 0; [L325] is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; [L751] activate_threads_#t~ret10 := is_transmit1_triggered_#res; [L751] activate_threads_~tmp___0~0 := activate_threads_#t~ret10; [L751] havoc activate_threads_#t~ret10; [L753-L757] COND FALSE !(0 != activate_threads_~tmp___0~0) [L759] havoc is_transmit2_triggered_#res; [L759] havoc is_transmit2_triggered_~__retres1~2; [L329] havoc is_transmit2_triggered_~__retres1~2; [L332] COND FALSE !(1 == ~t2_pc~0) [L342] is_transmit2_triggered_~__retres1~2 := 0; [L344] is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; [L759] activate_threads_#t~ret11 := is_transmit2_triggered_#res; [L759] activate_threads_~tmp___1~0 := activate_threads_#t~ret11; [L759] havoc activate_threads_#t~ret11; [L761-L765] COND FALSE !(0 != activate_threads_~tmp___1~0) [L767] havoc is_transmit3_triggered_#res; [L767] havoc is_transmit3_triggered_~__retres1~3; [L348] havoc is_transmit3_triggered_~__retres1~3; [L351] COND FALSE !(1 == ~t3_pc~0) [L361] is_transmit3_triggered_~__retres1~3 := 0; [L363] is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; [L767] activate_threads_#t~ret12 := is_transmit3_triggered_#res; [L767] activate_threads_~tmp___2~0 := activate_threads_#t~ret12; [L767] havoc activate_threads_#t~ret12; [L769-L773] COND FALSE !(0 != activate_threads_~tmp___2~0) [L775] havoc is_transmit4_triggered_#res; [L775] havoc is_transmit4_triggered_~__retres1~4; [L367] havoc is_transmit4_triggered_~__retres1~4; [L370] COND FALSE !(1 == ~t4_pc~0) [L380] is_transmit4_triggered_~__retres1~4 := 0; [L382] is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; [L775] activate_threads_#t~ret13 := is_transmit4_triggered_#res; [L775] activate_threads_~tmp___3~0 := activate_threads_#t~ret13; [L775] havoc activate_threads_#t~ret13; [L777-L781] COND FALSE !(0 != activate_threads_~tmp___3~0) [L783] havoc is_transmit5_triggered_#res; [L783] havoc is_transmit5_triggered_~__retres1~5; [L386] havoc is_transmit5_triggered_~__retres1~5; [L389] COND FALSE !(1 == ~t5_pc~0) [L399] is_transmit5_triggered_~__retres1~5 := 0; [L401] is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; [L783] activate_threads_#t~ret14 := is_transmit5_triggered_#res; [L783] activate_threads_~tmp___4~0 := activate_threads_#t~ret14; [L783] havoc activate_threads_#t~ret14; [L785-L789] COND FALSE !(0 != activate_threads_~tmp___4~0) [L669] COND FALSE !(1 == ~M_E~0) [L674] COND FALSE !(1 == ~T1_E~0) [L679] COND FALSE !(1 == ~T2_E~0) [L684] COND FALSE !(1 == ~T3_E~0) [L689] COND FALSE !(1 == ~T4_E~0) [L694] COND FALSE !(1 == ~T5_E~0) [L699] COND FALSE !(1 == ~E_M~0) [L704] COND FALSE !(1 == ~E_1~0) [L709] COND FALSE !(1 == ~E_2~0) [L714] COND FALSE !(1 == ~E_3~0) [L719] COND FALSE !(1 == ~E_4~0) [L724] COND FALSE !(1 == ~E_5~0) [L930-L967] COND FALSE !(false) [L933] start_simulation_~kernel_st~0 := 1; [L934] havoc eval_#t~ret2, eval_#t~nondet3, eval_~tmp_ndt_1~0, eval_#t~nondet4, eval_~tmp_ndt_2~0, eval_#t~nondet5, eval_~tmp_ndt_3~0, eval_#t~nondet6, eval_~tmp_ndt_4~0, eval_#t~nondet7, eval_~tmp_ndt_5~0, eval_#t~nondet8, eval_~tmp_ndt_6~0, eval_~tmp~0; [L492] havoc eval_~tmp~0; [L14] ~m_pc~0 := 0; [L15] ~t1_pc~0 := 0; [L16] ~t2_pc~0 := 0; [L17] ~t3_pc~0 := 0; [L18] ~t4_pc~0 := 0; [L19] ~t5_pc~0 := 0; [L20] ~m_st~0 := 0; [L21] ~t1_st~0 := 0; [L22] ~t2_st~0 := 0; [L23] ~t3_st~0 := 0; [L24] ~t4_st~0 := 0; [L25] ~t5_st~0 := 0; [L26] ~m_i~0 := 0; [L27] ~t1_i~0 := 0; [L28] ~t2_i~0 := 0; [L29] ~t3_i~0 := 0; [L30] ~t4_i~0 := 0; [L31] ~t5_i~0 := 0; [L32] ~M_E~0 := 2; [L33] ~T1_E~0 := 2; [L34] ~T2_E~0 := 2; [L35] ~T3_E~0 := 2; [L36] ~T4_E~0 := 2; [L37] ~T5_E~0 := 2; [L38] ~E_M~0 := 2; [L39] ~E_1~0 := 2; [L40] ~E_2~0 := 2; [L41] ~E_3~0 := 2; [L42] ~E_4~0 := 2; [L43] ~E_5~0 := 2; [L51] ~token~0 := 0; [L53] ~local~0 := 0; [L975] havoc ~__retres1~7; [L886] ~m_i~0 := 1; [L887] ~t1_i~0 := 1; [L888] ~t2_i~0 := 1; [L889] ~t3_i~0 := 1; [L890] ~t4_i~0 := 1; [L891] ~t5_i~0 := 1; [L916] havoc ~kernel_st~0; [L917] havoc ~tmp~3; [L918] havoc ~tmp___0~1; [L922] ~kernel_st~0 := 0; [L416] COND TRUE 1 == ~m_i~0 [L417] ~m_st~0 := 0; [L421] COND TRUE 1 == ~t1_i~0 [L422] ~t1_st~0 := 0; [L426] COND TRUE 1 == ~t2_i~0 [L427] ~t2_st~0 := 0; [L431] COND TRUE 1 == ~t3_i~0 [L432] ~t3_st~0 := 0; [L436] COND TRUE 1 == ~t4_i~0 [L437] ~t4_st~0 := 0; [L441] COND TRUE 1 == ~t5_i~0 [L442] ~t5_st~0 := 0; [L601] COND FALSE !(0 == ~M_E~0) [L606] COND FALSE !(0 == ~T1_E~0) [L611] COND FALSE !(0 == ~T2_E~0) [L616] COND FALSE !(0 == ~T3_E~0) [L621] COND FALSE !(0 == ~T4_E~0) [L626] COND FALSE !(0 == ~T5_E~0) [L631] COND FALSE !(0 == ~E_M~0) [L636] COND FALSE !(0 == ~E_1~0) [L641] COND FALSE !(0 == ~E_2~0) [L646] COND FALSE !(0 == ~E_3~0) [L651] COND FALSE !(0 == ~E_4~0) [L656] COND FALSE !(0 == ~E_5~0) [L734] havoc ~tmp~1; [L735] havoc ~tmp___0~0; [L736] havoc ~tmp___1~0; [L737] havoc ~tmp___2~0; [L738] havoc ~tmp___3~0; [L739] havoc ~tmp___4~0; [L291] havoc ~__retres1~0; [L294] COND FALSE !(1 == ~m_pc~0) [L304] ~__retres1~0 := 0; [L306] #res := ~__retres1~0; [L743] ~tmp~1 := #t~ret9; [L743] havoc #t~ret9; [L745-L749] COND FALSE !(0 != ~tmp~1) [L310] havoc ~__retres1~1; [L313] COND FALSE !(1 == ~t1_pc~0) [L323] ~__retres1~1 := 0; [L325] #res := ~__retres1~1; [L751] ~tmp___0~0 := #t~ret10; [L751] havoc #t~ret10; [L753-L757] COND FALSE !(0 != ~tmp___0~0) [L329] havoc ~__retres1~2; [L332] COND FALSE !(1 == ~t2_pc~0) [L342] ~__retres1~2 := 0; [L344] #res := ~__retres1~2; [L759] ~tmp___1~0 := #t~ret11; [L759] havoc #t~ret11; [L761-L765] COND FALSE !(0 != ~tmp___1~0) [L348] havoc ~__retres1~3; [L351] COND FALSE !(1 == ~t3_pc~0) [L361] ~__retres1~3 := 0; [L363] #res := ~__retres1~3; [L767] ~tmp___2~0 := #t~ret12; [L767] havoc #t~ret12; [L769-L773] COND FALSE !(0 != ~tmp___2~0) [L367] havoc ~__retres1~4; [L370] COND FALSE !(1 == ~t4_pc~0) [L380] ~__retres1~4 := 0; [L382] #res := ~__retres1~4; [L775] ~tmp___3~0 := #t~ret13; [L775] havoc #t~ret13; [L777-L781] COND FALSE !(0 != ~tmp___3~0) [L386] havoc ~__retres1~5; [L389] COND FALSE !(1 == ~t5_pc~0) [L399] ~__retres1~5 := 0; [L401] #res := ~__retres1~5; [L783] ~tmp___4~0 := #t~ret14; [L783] havoc #t~ret14; [L785-L789] COND FALSE !(0 != ~tmp___4~0) [L669] COND FALSE !(1 == ~M_E~0) [L674] COND FALSE !(1 == ~T1_E~0) [L679] COND FALSE !(1 == ~T2_E~0) [L684] COND FALSE !(1 == ~T3_E~0) [L689] COND FALSE !(1 == ~T4_E~0) [L694] COND FALSE !(1 == ~T5_E~0) [L699] COND FALSE !(1 == ~E_M~0) [L704] COND FALSE !(1 == ~E_1~0) [L709] COND FALSE !(1 == ~E_2~0) [L714] COND FALSE !(1 == ~E_3~0) [L719] COND FALSE !(1 == ~E_4~0) [L724] COND FALSE !(1 == ~E_5~0) [L930-L967] COND FALSE !(false) [L933] ~kernel_st~0 := 1; [L492] havoc ~tmp~0; ----- ----- class de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.CACSL2BoogieBacktranslator [L14] ~m_pc~0 := 0; [L15] ~t1_pc~0 := 0; [L16] ~t2_pc~0 := 0; [L17] ~t3_pc~0 := 0; [L18] ~t4_pc~0 := 0; [L19] ~t5_pc~0 := 0; [L20] ~m_st~0 := 0; [L21] ~t1_st~0 := 0; [L22] ~t2_st~0 := 0; [L23] ~t3_st~0 := 0; [L24] ~t4_st~0 := 0; [L25] ~t5_st~0 := 0; [L26] ~m_i~0 := 0; [L27] ~t1_i~0 := 0; [L28] ~t2_i~0 := 0; [L29] ~t3_i~0 := 0; [L30] ~t4_i~0 := 0; [L31] ~t5_i~0 := 0; [L32] ~M_E~0 := 2; [L33] ~T1_E~0 := 2; [L34] ~T2_E~0 := 2; [L35] ~T3_E~0 := 2; [L36] ~T4_E~0 := 2; [L37] ~T5_E~0 := 2; [L38] ~E_M~0 := 2; [L39] ~E_1~0 := 2; [L40] ~E_2~0 := 2; [L41] ~E_3~0 := 2; [L42] ~E_4~0 := 2; [L43] ~E_5~0 := 2; [L51] ~token~0 := 0; [L53] ~local~0 := 0; [L975] havoc ~__retres1~7; [L886] ~m_i~0 := 1; [L887] ~t1_i~0 := 1; [L888] ~t2_i~0 := 1; [L889] ~t3_i~0 := 1; [L890] ~t4_i~0 := 1; [L891] ~t5_i~0 := 1; [L916] havoc ~kernel_st~0; [L917] havoc ~tmp~3; [L918] havoc ~tmp___0~1; [L922] ~kernel_st~0 := 0; [L416] COND TRUE 1 == ~m_i~0 [L417] ~m_st~0 := 0; [L421] COND TRUE 1 == ~t1_i~0 [L422] ~t1_st~0 := 0; [L426] COND TRUE 1 == ~t2_i~0 [L427] ~t2_st~0 := 0; [L431] COND TRUE 1 == ~t3_i~0 [L432] ~t3_st~0 := 0; [L436] COND TRUE 1 == ~t4_i~0 [L437] ~t4_st~0 := 0; [L441] COND TRUE 1 == ~t5_i~0 [L442] ~t5_st~0 := 0; [L601] COND FALSE !(0 == ~M_E~0) [L606] COND FALSE !(0 == ~T1_E~0) [L611] COND FALSE !(0 == ~T2_E~0) [L616] COND FALSE !(0 == ~T3_E~0) [L621] COND FALSE !(0 == ~T4_E~0) [L626] COND FALSE !(0 == ~T5_E~0) [L631] COND FALSE !(0 == ~E_M~0) [L636] COND FALSE !(0 == ~E_1~0) [L641] COND FALSE !(0 == ~E_2~0) [L646] COND FALSE !(0 == ~E_3~0) [L651] COND FALSE !(0 == ~E_4~0) [L656] COND FALSE !(0 == ~E_5~0) [L734] havoc ~tmp~1; [L735] havoc ~tmp___0~0; [L736] havoc ~tmp___1~0; [L737] havoc ~tmp___2~0; [L738] havoc ~tmp___3~0; [L739] havoc ~tmp___4~0; [L291] havoc ~__retres1~0; [L294] COND FALSE !(1 == ~m_pc~0) [L304] ~__retres1~0 := 0; [L306] #res := ~__retres1~0; [L743] ~tmp~1 := #t~ret9; [L743] havoc #t~ret9; [L745-L749] COND FALSE !(0 != ~tmp~1) [L310] havoc ~__retres1~1; [L313] COND FALSE !(1 == ~t1_pc~0) [L323] ~__retres1~1 := 0; [L325] #res := ~__retres1~1; [L751] ~tmp___0~0 := #t~ret10; [L751] havoc #t~ret10; [L753-L757] COND FALSE !(0 != ~tmp___0~0) [L329] havoc ~__retres1~2; [L332] COND FALSE !(1 == ~t2_pc~0) [L342] ~__retres1~2 := 0; [L344] #res := ~__retres1~2; [L759] ~tmp___1~0 := #t~ret11; [L759] havoc #t~ret11; [L761-L765] COND FALSE !(0 != ~tmp___1~0) [L348] havoc ~__retres1~3; [L351] COND FALSE !(1 == ~t3_pc~0) [L361] ~__retres1~3 := 0; [L363] #res := ~__retres1~3; [L767] ~tmp___2~0 := #t~ret12; [L767] havoc #t~ret12; [L769-L773] COND FALSE !(0 != ~tmp___2~0) [L367] havoc ~__retres1~4; [L370] COND FALSE !(1 == ~t4_pc~0) [L380] ~__retres1~4 := 0; [L382] #res := ~__retres1~4; [L775] ~tmp___3~0 := #t~ret13; [L775] havoc #t~ret13; [L777-L781] COND FALSE !(0 != ~tmp___3~0) [L386] havoc ~__retres1~5; [L389] COND FALSE !(1 == ~t5_pc~0) [L399] ~__retres1~5 := 0; [L401] #res := ~__retres1~5; [L783] ~tmp___4~0 := #t~ret14; [L783] havoc #t~ret14; [L785-L789] COND FALSE !(0 != ~tmp___4~0) [L669] COND FALSE !(1 == ~M_E~0) [L674] COND FALSE !(1 == ~T1_E~0) [L679] COND FALSE !(1 == ~T2_E~0) [L684] COND FALSE !(1 == ~T3_E~0) [L689] COND FALSE !(1 == ~T4_E~0) [L694] COND FALSE !(1 == ~T5_E~0) [L699] COND FALSE !(1 == ~E_M~0) [L704] COND FALSE !(1 == ~E_1~0) [L709] COND FALSE !(1 == ~E_2~0) [L714] COND FALSE !(1 == ~E_3~0) [L719] COND FALSE !(1 == ~E_4~0) [L724] COND FALSE !(1 == ~E_5~0) [L930-L967] COND FALSE !(false) [L933] ~kernel_st~0 := 1; [L492] havoc ~tmp~0; [L14] int m_pc = 0; [L15] int t1_pc = 0; [L16] int t2_pc = 0; [L17] int t3_pc = 0; [L18] int t4_pc = 0; [L19] int t5_pc = 0; [L20] int m_st ; [L21] int t1_st ; [L22] int t2_st ; [L23] int t3_st ; [L24] int t4_st ; [L25] int t5_st ; [L26] int m_i ; [L27] int t1_i ; [L28] int t2_i ; [L29] int t3_i ; [L30] int t4_i ; [L31] int t5_i ; [L32] int M_E = 2; [L33] int T1_E = 2; [L34] int T2_E = 2; [L35] int T3_E = 2; [L36] int T4_E = 2; [L37] int T5_E = 2; [L38] int E_M = 2; [L39] int E_1 = 2; [L40] int E_2 = 2; [L41] int E_3 = 2; [L42] int E_4 = 2; [L43] int E_5 = 2; [L51] int token ; [L53] int local ; [L975] int __retres1 ; [L886] m_i = 1 [L887] t1_i = 1 [L888] t2_i = 1 [L889] t3_i = 1 [L890] t4_i = 1 [L891] t5_i = 1 [L916] int kernel_st ; [L917] int tmp ; [L918] int tmp___0 ; [L922] kernel_st = 0 [L416] COND TRUE m_i == 1 [L417] m_st = 0 [L421] COND TRUE t1_i == 1 [L422] t1_st = 0 [L426] COND TRUE t2_i == 1 [L427] t2_st = 0 [L431] COND TRUE t3_i == 1 [L432] t3_st = 0 [L436] COND TRUE t4_i == 1 [L437] t4_st = 0 [L441] COND TRUE t5_i == 1 [L442] t5_st = 0 [L601] COND FALSE !(M_E == 0) [L606] COND FALSE !(T1_E == 0) [L611] COND FALSE !(T2_E == 0) [L616] COND FALSE !(T3_E == 0) [L621] COND FALSE !(T4_E == 0) [L626] COND FALSE !(T5_E == 0) [L631] COND FALSE !(E_M == 0) [L636] COND FALSE !(E_1 == 0) [L641] COND FALSE !(E_2 == 0) [L646] COND FALSE !(E_3 == 0) [L651] COND FALSE !(E_4 == 0) [L656] COND FALSE !(E_5 == 0) [L734] int tmp ; [L735] int tmp___0 ; [L736] int tmp___1 ; [L737] int tmp___2 ; [L738] int tmp___3 ; [L739] int tmp___4 ; [L291] int __retres1 ; [L294] COND FALSE !(m_pc == 1) [L304] __retres1 = 0 [L306] return (__retres1); [L743] tmp = is_master_triggered() [L745] COND FALSE !(\read(tmp)) [L310] int __retres1 ; [L313] COND FALSE !(t1_pc == 1) [L323] __retres1 = 0 [L325] return (__retres1); [L751] tmp___0 = is_transmit1_triggered() [L753] COND FALSE !(\read(tmp___0)) [L329] int __retres1 ; [L332] COND FALSE !(t2_pc == 1) [L342] __retres1 = 0 [L344] return (__retres1); [L759] tmp___1 = is_transmit2_triggered() [L761] COND FALSE !(\read(tmp___1)) [L348] int __retres1 ; [L351] COND FALSE !(t3_pc == 1) [L361] __retres1 = 0 [L363] return (__retres1); [L767] tmp___2 = is_transmit3_triggered() [L769] COND FALSE !(\read(tmp___2)) [L367] int __retres1 ; [L370] COND FALSE !(t4_pc == 1) [L380] __retres1 = 0 [L382] return (__retres1); [L775] tmp___3 = is_transmit4_triggered() [L777] COND FALSE !(\read(tmp___3)) [L386] int __retres1 ; [L389] COND FALSE !(t5_pc == 1) [L399] __retres1 = 0 [L401] return (__retres1); [L783] tmp___4 = is_transmit5_triggered() [L785] COND FALSE !(\read(tmp___4)) [L669] COND FALSE !(M_E == 1) [L674] COND FALSE !(T1_E == 1) [L679] COND FALSE !(T2_E == 1) [L684] COND FALSE !(T3_E == 1) [L689] COND FALSE !(T4_E == 1) [L694] COND FALSE !(T5_E == 1) [L699] COND FALSE !(E_M == 1) [L704] COND FALSE !(E_1 == 1) [L709] COND FALSE !(E_2 == 1) [L714] COND FALSE !(E_3 == 1) [L719] COND FALSE !(E_4 == 1) [L724] COND FALSE !(E_5 == 1) [L930] COND TRUE 1 [L933] kernel_st = 1 [L492] int tmp ; ----- ----- class de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder.RCFGBacktranslator [?] assume !false; [?] havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; [?] assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; [?] exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; [?] eval_#t~ret2 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret2;havoc eval_#t~ret2; [?] assume 0 != eval_~tmp~0; [?] assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0;eval_~tmp_ndt_1~0 := eval_#t~nondet3;havoc eval_#t~nondet3; [?] assume !(0 != eval_~tmp_ndt_1~0); [?] assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0;eval_~tmp_ndt_2~0 := eval_#t~nondet4;havoc eval_#t~nondet4; [?] assume !(0 != eval_~tmp_ndt_2~0); [?] assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0;eval_~tmp_ndt_3~0 := eval_#t~nondet5;havoc eval_#t~nondet5; [?] assume !(0 != eval_~tmp_ndt_3~0); [?] assume 0 == ~t3_st~0;havoc eval_~tmp_ndt_4~0;eval_~tmp_ndt_4~0 := eval_#t~nondet6;havoc eval_#t~nondet6; [?] assume !(0 != eval_~tmp_ndt_4~0); [?] assume 0 == ~t4_st~0;havoc eval_~tmp_ndt_5~0;eval_~tmp_ndt_5~0 := eval_#t~nondet7;havoc eval_#t~nondet7; [?] assume !(0 != eval_~tmp_ndt_5~0); [?] assume 0 == ~t5_st~0;havoc eval_~tmp_ndt_6~0;eval_~tmp_ndt_6~0 := eval_#t~nondet8;havoc eval_#t~nondet8; [?] assume !(0 != eval_~tmp_ndt_6~0); [L496-L590] assume !false; [L499] havoc exists_runnable_thread_#res; [L499] havoc exists_runnable_thread_~__retres1~6; [L451] havoc exists_runnable_thread_~__retres1~6; [L454-L484] assume 0 == ~m_st~0; [L455] exists_runnable_thread_~__retres1~6 := 1; [L487] exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; [L499] eval_#t~ret2 := exists_runnable_thread_#res; [L499] eval_~tmp~0 := eval_#t~ret2; [L499] havoc eval_#t~ret2; [L501-L505] assume 0 != eval_~tmp~0; [L506-L519] assume 0 == ~m_st~0; [L507] havoc eval_~tmp_ndt_1~0; [L508] eval_~tmp_ndt_1~0 := eval_#t~nondet3; [L508] havoc eval_#t~nondet3; [L509-L516] assume !(0 != eval_~tmp_ndt_1~0); [L520-L533] assume 0 == ~t1_st~0; [L521] havoc eval_~tmp_ndt_2~0; [L522] eval_~tmp_ndt_2~0 := eval_#t~nondet4; [L522] havoc eval_#t~nondet4; [L523-L530] assume !(0 != eval_~tmp_ndt_2~0); [L534-L547] assume 0 == ~t2_st~0; [L535] havoc eval_~tmp_ndt_3~0; [L536] eval_~tmp_ndt_3~0 := eval_#t~nondet5; [L536] havoc eval_#t~nondet5; [L537-L544] assume !(0 != eval_~tmp_ndt_3~0); [L548-L561] assume 0 == ~t3_st~0; [L549] havoc eval_~tmp_ndt_4~0; [L550] eval_~tmp_ndt_4~0 := eval_#t~nondet6; [L550] havoc eval_#t~nondet6; [L551-L558] assume !(0 != eval_~tmp_ndt_4~0); [L562-L575] assume 0 == ~t4_st~0; [L563] havoc eval_~tmp_ndt_5~0; [L564] eval_~tmp_ndt_5~0 := eval_#t~nondet7; [L564] havoc eval_#t~nondet7; [L565-L572] assume !(0 != eval_~tmp_ndt_5~0); [L576-L589] assume 0 == ~t5_st~0; [L577] havoc eval_~tmp_ndt_6~0; [L578] eval_~tmp_ndt_6~0 := eval_#t~nondet8; [L578] havoc eval_#t~nondet8; [L579-L586] assume !(0 != eval_~tmp_ndt_6~0); ----- ----- class de.uni_freiburg.informatik.ultimate.boogie.preprocessor.BoogiePreprocessorBacktranslator [L496-L590] assume !false; [L499] havoc exists_runnable_thread_#res; [L499] havoc exists_runnable_thread_~__retres1~6; [L451] havoc exists_runnable_thread_~__retres1~6; [L454-L484] assume 0 == ~m_st~0; [L455] exists_runnable_thread_~__retres1~6 := 1; [L487] exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; [L499] eval_#t~ret2 := exists_runnable_thread_#res; [L499] eval_~tmp~0 := eval_#t~ret2; [L499] havoc eval_#t~ret2; [L501-L505] assume 0 != eval_~tmp~0; [L506-L519] assume 0 == ~m_st~0; [L507] havoc eval_~tmp_ndt_1~0; [L508] eval_~tmp_ndt_1~0 := eval_#t~nondet3; [L508] havoc eval_#t~nondet3; [L509-L516] assume !(0 != eval_~tmp_ndt_1~0); [L520-L533] assume 0 == ~t1_st~0; [L521] havoc eval_~tmp_ndt_2~0; [L522] eval_~tmp_ndt_2~0 := eval_#t~nondet4; [L522] havoc eval_#t~nondet4; [L523-L530] assume !(0 != eval_~tmp_ndt_2~0); [L534-L547] assume 0 == ~t2_st~0; [L535] havoc eval_~tmp_ndt_3~0; [L536] eval_~tmp_ndt_3~0 := eval_#t~nondet5; [L536] havoc eval_#t~nondet5; [L537-L544] assume !(0 != eval_~tmp_ndt_3~0); [L548-L561] assume 0 == ~t3_st~0; [L549] havoc eval_~tmp_ndt_4~0; [L550] eval_~tmp_ndt_4~0 := eval_#t~nondet6; [L550] havoc eval_#t~nondet6; [L551-L558] assume !(0 != eval_~tmp_ndt_4~0); [L562-L575] assume 0 == ~t4_st~0; [L563] havoc eval_~tmp_ndt_5~0; [L564] eval_~tmp_ndt_5~0 := eval_#t~nondet7; [L564] havoc eval_#t~nondet7; [L565-L572] assume !(0 != eval_~tmp_ndt_5~0); [L576-L589] assume 0 == ~t5_st~0; [L577] havoc eval_~tmp_ndt_6~0; [L578] eval_~tmp_ndt_6~0 := eval_#t~nondet8; [L578] havoc eval_#t~nondet8; [L579-L586] assume !(0 != eval_~tmp_ndt_6~0); [L496-L590] COND FALSE !(false) [L499] havoc exists_runnable_thread_#res; [L499] havoc exists_runnable_thread_~__retres1~6; [L451] havoc exists_runnable_thread_~__retres1~6; [L454] COND TRUE 0 == ~m_st~0 [L455] exists_runnable_thread_~__retres1~6 := 1; [L487] exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; [L499] eval_#t~ret2 := exists_runnable_thread_#res; [L499] eval_~tmp~0 := eval_#t~ret2; [L499] havoc eval_#t~ret2; [L501-L505] COND TRUE 0 != eval_~tmp~0 [L506] COND TRUE 0 == ~m_st~0 [L507] havoc eval_~tmp_ndt_1~0; [L508] eval_~tmp_ndt_1~0 := eval_#t~nondet3; [L508] havoc eval_#t~nondet3; [L509-L516] COND FALSE !(0 != eval_~tmp_ndt_1~0) [L520] COND TRUE 0 == ~t1_st~0 [L521] havoc eval_~tmp_ndt_2~0; [L522] eval_~tmp_ndt_2~0 := eval_#t~nondet4; [L522] havoc eval_#t~nondet4; [L523-L530] COND FALSE !(0 != eval_~tmp_ndt_2~0) [L534] COND TRUE 0 == ~t2_st~0 [L535] havoc eval_~tmp_ndt_3~0; [L536] eval_~tmp_ndt_3~0 := eval_#t~nondet5; [L536] havoc eval_#t~nondet5; [L537-L544] COND FALSE !(0 != eval_~tmp_ndt_3~0) [L548] COND TRUE 0 == ~t3_st~0 [L549] havoc eval_~tmp_ndt_4~0; [L550] eval_~tmp_ndt_4~0 := eval_#t~nondet6; [L550] havoc eval_#t~nondet6; [L551-L558] COND FALSE !(0 != eval_~tmp_ndt_4~0) [L562] COND TRUE 0 == ~t4_st~0 [L563] havoc eval_~tmp_ndt_5~0; [L564] eval_~tmp_ndt_5~0 := eval_#t~nondet7; [L564] havoc eval_#t~nondet7; [L565-L572] COND FALSE !(0 != eval_~tmp_ndt_5~0) [L576] COND TRUE 0 == ~t5_st~0 [L577] havoc eval_~tmp_ndt_6~0; [L578] eval_~tmp_ndt_6~0 := eval_#t~nondet8; [L578] havoc eval_#t~nondet8; [L579-L586] COND FALSE !(0 != eval_~tmp_ndt_6~0) ----- ----- class de.uni_freiburg.informatik.ultimate.boogie.procedureinliner.backtranslation.InlinerBacktranslator [L496-L590] COND FALSE !(false) [L499] havoc exists_runnable_thread_#res; [L499] havoc exists_runnable_thread_~__retres1~6; [L451] havoc exists_runnable_thread_~__retres1~6; [L454] COND TRUE 0 == ~m_st~0 [L455] exists_runnable_thread_~__retres1~6 := 1; [L487] exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; [L499] eval_#t~ret2 := exists_runnable_thread_#res; [L499] eval_~tmp~0 := eval_#t~ret2; [L499] havoc eval_#t~ret2; [L501-L505] COND TRUE 0 != eval_~tmp~0 [L506] COND TRUE 0 == ~m_st~0 [L507] havoc eval_~tmp_ndt_1~0; [L508] eval_~tmp_ndt_1~0 := eval_#t~nondet3; [L508] havoc eval_#t~nondet3; [L509-L516] COND FALSE !(0 != eval_~tmp_ndt_1~0) [L520] COND TRUE 0 == ~t1_st~0 [L521] havoc eval_~tmp_ndt_2~0; [L522] eval_~tmp_ndt_2~0 := eval_#t~nondet4; [L522] havoc eval_#t~nondet4; [L523-L530] COND FALSE !(0 != eval_~tmp_ndt_2~0) [L534] COND TRUE 0 == ~t2_st~0 [L535] havoc eval_~tmp_ndt_3~0; [L536] eval_~tmp_ndt_3~0 := eval_#t~nondet5; [L536] havoc eval_#t~nondet5; [L537-L544] COND FALSE !(0 != eval_~tmp_ndt_3~0) [L548] COND TRUE 0 == ~t3_st~0 [L549] havoc eval_~tmp_ndt_4~0; [L550] eval_~tmp_ndt_4~0 := eval_#t~nondet6; [L550] havoc eval_#t~nondet6; [L551-L558] COND FALSE !(0 != eval_~tmp_ndt_4~0) [L562] COND TRUE 0 == ~t4_st~0 [L563] havoc eval_~tmp_ndt_5~0; [L564] eval_~tmp_ndt_5~0 := eval_#t~nondet7; [L564] havoc eval_#t~nondet7; [L565-L572] COND FALSE !(0 != eval_~tmp_ndt_5~0) [L576] COND TRUE 0 == ~t5_st~0 [L577] havoc eval_~tmp_ndt_6~0; [L578] eval_~tmp_ndt_6~0 := eval_#t~nondet8; [L578] havoc eval_#t~nondet8; [L579-L586] COND FALSE !(0 != eval_~tmp_ndt_6~0) [L496-L590] COND FALSE !(false) [L451] havoc ~__retres1~6; [L454] COND TRUE 0 == ~m_st~0 [L455] ~__retres1~6 := 1; [L487] #res := ~__retres1~6; [L499] ~tmp~0 := #t~ret2; [L499] havoc #t~ret2; [L501-L505] COND TRUE 0 != ~tmp~0 [L506] COND TRUE 0 == ~m_st~0 [L507] havoc ~tmp_ndt_1~0; [L508] ~tmp_ndt_1~0 := #t~nondet3; [L508] havoc #t~nondet3; [L509-L516] COND FALSE !(0 != ~tmp_ndt_1~0) [L520] COND TRUE 0 == ~t1_st~0 [L521] havoc ~tmp_ndt_2~0; [L522] ~tmp_ndt_2~0 := #t~nondet4; [L522] havoc #t~nondet4; [L523-L530] COND FALSE !(0 != ~tmp_ndt_2~0) [L534] COND TRUE 0 == ~t2_st~0 [L535] havoc ~tmp_ndt_3~0; [L536] ~tmp_ndt_3~0 := #t~nondet5; [L536] havoc #t~nondet5; [L537-L544] COND FALSE !(0 != ~tmp_ndt_3~0) [L548] COND TRUE 0 == ~t3_st~0 [L549] havoc ~tmp_ndt_4~0; [L550] ~tmp_ndt_4~0 := #t~nondet6; [L550] havoc #t~nondet6; [L551-L558] COND FALSE !(0 != ~tmp_ndt_4~0) [L562] COND TRUE 0 == ~t4_st~0 [L563] havoc ~tmp_ndt_5~0; [L564] ~tmp_ndt_5~0 := #t~nondet7; [L564] havoc #t~nondet7; [L565-L572] COND FALSE !(0 != ~tmp_ndt_5~0) [L576] COND TRUE 0 == ~t5_st~0 [L577] havoc ~tmp_ndt_6~0; [L578] ~tmp_ndt_6~0 := #t~nondet8; [L578] havoc #t~nondet8; [L579-L586] COND FALSE !(0 != ~tmp_ndt_6~0) ----- ----- class de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.CACSL2BoogieBacktranslator [L496-L590] COND FALSE !(false) [L451] havoc ~__retres1~6; [L454] COND TRUE 0 == ~m_st~0 [L455] ~__retres1~6 := 1; [L487] #res := ~__retres1~6; [L499] ~tmp~0 := #t~ret2; [L499] havoc #t~ret2; [L501-L505] COND TRUE 0 != ~tmp~0 [L506] COND TRUE 0 == ~m_st~0 [L507] havoc ~tmp_ndt_1~0; [L508] ~tmp_ndt_1~0 := #t~nondet3; [L508] havoc #t~nondet3; [L509-L516] COND FALSE !(0 != ~tmp_ndt_1~0) [L520] COND TRUE 0 == ~t1_st~0 [L521] havoc ~tmp_ndt_2~0; [L522] ~tmp_ndt_2~0 := #t~nondet4; [L522] havoc #t~nondet4; [L523-L530] COND FALSE !(0 != ~tmp_ndt_2~0) [L534] COND TRUE 0 == ~t2_st~0 [L535] havoc ~tmp_ndt_3~0; [L536] ~tmp_ndt_3~0 := #t~nondet5; [L536] havoc #t~nondet5; [L537-L544] COND FALSE !(0 != ~tmp_ndt_3~0) [L548] COND TRUE 0 == ~t3_st~0 [L549] havoc ~tmp_ndt_4~0; [L550] ~tmp_ndt_4~0 := #t~nondet6; [L550] havoc #t~nondet6; [L551-L558] COND FALSE !(0 != ~tmp_ndt_4~0) [L562] COND TRUE 0 == ~t4_st~0 [L563] havoc ~tmp_ndt_5~0; [L564] ~tmp_ndt_5~0 := #t~nondet7; [L564] havoc #t~nondet7; [L565-L572] COND FALSE !(0 != ~tmp_ndt_5~0) [L576] COND TRUE 0 == ~t5_st~0 [L577] havoc ~tmp_ndt_6~0; [L578] ~tmp_ndt_6~0 := #t~nondet8; [L578] havoc #t~nondet8; [L579-L586] COND FALSE !(0 != ~tmp_ndt_6~0) [L496] COND TRUE 1 [L451] int __retres1 ; [L454] COND TRUE m_st == 0 [L455] __retres1 = 1 [L487] return (__retres1); [L499] tmp = exists_runnable_thread() [L501] COND TRUE \read(tmp) [L506] COND TRUE m_st == 0 [L507] int tmp_ndt_1; [L508] tmp_ndt_1 = __VERIFIER_nondet_int() [L509] COND FALSE !(\read(tmp_ndt_1)) [L520] COND TRUE t1_st == 0 [L521] int tmp_ndt_2; [L522] tmp_ndt_2 = __VERIFIER_nondet_int() [L523] COND FALSE !(\read(tmp_ndt_2)) [L534] COND TRUE t2_st == 0 [L535] int tmp_ndt_3; [L536] tmp_ndt_3 = __VERIFIER_nondet_int() [L537] COND FALSE !(\read(tmp_ndt_3)) [L548] COND TRUE t3_st == 0 [L549] int tmp_ndt_4; [L550] tmp_ndt_4 = __VERIFIER_nondet_int() [L551] COND FALSE !(\read(tmp_ndt_4)) [L562] COND TRUE t4_st == 0 [L563] int tmp_ndt_5; [L564] tmp_ndt_5 = __VERIFIER_nondet_int() [L565] COND FALSE !(\read(tmp_ndt_5)) [L576] COND TRUE t5_st == 0 [L577] int tmp_ndt_6; [L578] tmp_ndt_6 = __VERIFIER_nondet_int() [L579] COND FALSE !(\read(tmp_ndt_6)) ----- [2018-11-23 00:24:02,988 INFO L145 WitnessManager]: Wrote witness to /tmp/vcloud-vcloud-master/worker/working_dir_dc28e54a-25be-4fa6-93e3-2eb7786d5d84/bin-2019/uautomizer/witness.graphml [2018-11-23 00:24:02,988 INFO L132 PluginConnector]: ------------------------ END Witness Printer---------------------------- [2018-11-23 00:24:02,988 INFO L168 Benchmark]: Toolchain (without parser) took 9533.52 ms. Allocated memory was 1.0 GB in the beginning and 1.5 GB in the end (delta: 470.8 MB). Free memory was 959.1 MB in the beginning and 798.1 MB in the end (delta: 161.1 MB). Peak memory consumption was 631.9 MB. Max. memory is 11.5 GB. [2018-11-23 00:24:02,989 INFO L168 Benchmark]: CDTParser took 0.17 ms. Allocated memory is still 1.0 GB. Free memory is still 985.4 MB. There was no memory consumed. Max. memory is 11.5 GB. [2018-11-23 00:24:02,989 INFO L168 Benchmark]: CACSL2BoogieTranslator took 275.54 ms. Allocated memory is still 1.0 GB. Free memory was 959.1 MB in the beginning and 937.6 MB in the end (delta: 21.5 MB). Peak memory consumption was 21.5 MB. Max. memory is 11.5 GB. [2018-11-23 00:24:02,989 INFO L168 Benchmark]: Boogie Procedure Inliner took 89.38 ms. Allocated memory was 1.0 GB in the beginning and 1.1 GB in the end (delta: 118.0 MB). Free memory was 937.6 MB in the beginning and 1.1 GB in the end (delta: -172.1 MB). Peak memory consumption was 14.8 MB. Max. memory is 11.5 GB. [2018-11-23 00:24:02,992 INFO L168 Benchmark]: Boogie Preprocessor took 45.44 ms. Allocated memory is still 1.1 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 9.8 MB). Peak memory consumption was 9.8 MB. Max. memory is 11.5 GB. [2018-11-23 00:24:02,993 INFO L168 Benchmark]: RCFGBuilder took 932.79 ms. Allocated memory is still 1.1 GB. Free memory was 1.1 GB in the beginning and 980.4 MB in the end (delta: 119.5 MB). Peak memory consumption was 119.5 MB. Max. memory is 11.5 GB. [2018-11-23 00:24:02,993 INFO L168 Benchmark]: BuchiAutomizer took 7450.79 ms. Allocated memory was 1.1 GB in the beginning and 1.5 GB in the end (delta: 352.8 MB). Free memory was 980.4 MB in the beginning and 798.1 MB in the end (delta: 182.4 MB). Peak memory consumption was 535.2 MB. Max. memory is 11.5 GB. [2018-11-23 00:24:02,993 INFO L168 Benchmark]: Witness Printer took 736.55 ms. Allocated memory is still 1.5 GB. Free memory was 798.1 MB in the beginning and 798.1 MB in the end (delta: 48 B). Peak memory consumption was 48 B. Max. memory is 11.5 GB. [2018-11-23 00:24:02,994 INFO L336 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.17 ms. Allocated memory is still 1.0 GB. Free memory is still 985.4 MB. There was no memory consumed. Max. memory is 11.5 GB. * CACSL2BoogieTranslator took 275.54 ms. Allocated memory is still 1.0 GB. Free memory was 959.1 MB in the beginning and 937.6 MB in the end (delta: 21.5 MB). Peak memory consumption was 21.5 MB. Max. memory is 11.5 GB. * Boogie Procedure Inliner took 89.38 ms. Allocated memory was 1.0 GB in the beginning and 1.1 GB in the end (delta: 118.0 MB). Free memory was 937.6 MB in the beginning and 1.1 GB in the end (delta: -172.1 MB). Peak memory consumption was 14.8 MB. Max. memory is 11.5 GB. * Boogie Preprocessor took 45.44 ms. Allocated memory is still 1.1 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 9.8 MB). Peak memory consumption was 9.8 MB. Max. memory is 11.5 GB. * RCFGBuilder took 932.79 ms. Allocated memory is still 1.1 GB. Free memory was 1.1 GB in the beginning and 980.4 MB in the end (delta: 119.5 MB). Peak memory consumption was 119.5 MB. Max. memory is 11.5 GB. * BuchiAutomizer took 7450.79 ms. Allocated memory was 1.1 GB in the beginning and 1.5 GB in the end (delta: 352.8 MB). Free memory was 980.4 MB in the beginning and 798.1 MB in the end (delta: 182.4 MB). Peak memory consumption was 535.2 MB. Max. memory is 11.5 GB. * Witness Printer took 736.55 ms. Allocated memory is still 1.5 GB. Free memory was 798.1 MB in the beginning and 798.1 MB in the end (delta: 48 B). Peak memory consumption was 48 B. Max. memory is 11.5 GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - StatisticsResult: Constructed decomposition of program Your program was decomposed into 21 terminating modules (21 trivial, 0 deterministic, 0 nondeterministic) and one nonterminating remainder module.21 modules have a trivial ranking function, the largest among these consists of 5 locations. The remainder module has 50269 locations. - StatisticsResult: Timing statistics BüchiAutomizer plugin needed 7.2s and 22 iterations. TraceHistogramMax:1. Analysis of lassos took 2.7s. Construction of modules took 0.7s. Büchi inclusion checks took 0.7s. Highest rank in rank-based complementation 0. Minimization of det autom 21. Minimization of nondet autom 0. Automata minimization 1.4s AutomataMinimizationTime, 21 MinimizatonAttempts, 13616 StatesRemovedByMinimization, 12 NontrivialMinimizations. Non-live state removal took 0.8s Buchi closure took 0.0s. Biggest automaton had 50269 states and ocurred in iteration 21. Nontrivial modules had stage [0, 0, 0, 0, 0]. InterpolantCoveringCapabilityFinite: 0/0 InterpolantCoveringCapabilityBuchi: 0/0 HoareTripleCheckerStatistics: 17284 SDtfs, 18776 SDslu, 14402 SDs, 0 SdLazy, 479 SolverSat, 267 SolverUnsat, 0 SolverUnknown, 0 SolverNotchecked, 0.7s Time LassoAnalysisResults: nont1 unkn0 SFLI3 SFLT0 conc5 concLT0 SILN1 SILU0 SILI12 SILT0 lasso0 LassoPreprocessingBenchmarks: LassoTerminationAnalysisBenchmarks: not availableLassoTerminationAnalysisBenchmarks: LassoNonterminationAnalysisSatFixpoint: 0 LassoNonterminationAnalysisSatUnbounded: 0 LassoNonterminationAnalysisUnsat: 0 LassoNonterminationAnalysisUnknown: 0 LassoNonterminationAnalysisTime: 0.0s - TerminationAnalysisResult: Nontermination possible Buchi Automizer proved that your program is nonterminating for some inputs - FixpointNonTerminationResult [Line: 496]: Nontermination argument in form of an infinite program execution. Nontermination argument in form of an infinite execution State at position 0 is {} State at position 1 is {__retres1=0, t3_st=0, token=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@4984f3d5=0, tmp=1, t5_i=1, __retres1=0, kernel_st=1, t2_st=0, t4_i=1, E_3=2, t4_pc=0, E_5=2, \result=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@4594db1d=0, E_1=2, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@683b0c1b=0, tmp_ndt_2=0, \result=0, __retres1=0, \result=0, tmp_ndt_4=0, tmp_ndt_6=0, m_st=0, tmp___2=0, tmp___0=0, t3_pc=0, tmp=0, \result=0, __retres1=0, m_pc=0, tmp___4=0, \result=0, __retres1=0, \result=0, __retres1=0, \result=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@7cb8f26b=0, T2_E=2, tmp___0=0, t1_pc=0, t5_st=0, __retres1=1, E_2=2, E_4=2, T1_E=2, tmp_ndt_1=0, M_E=2, tmp=0, tmp_ndt_3=0, __retres1=0, T5_E=2, t2_i=1, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@2a7d1a6e=0, T4_E=2, t3_i=1, t4_st=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@3680e9cc=0, m_i=1, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@18abdc4b=0, t1_st=0, tmp_ndt_5=0, t5_pc=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@5b736995=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@6a0c2391=0, local=0, t2_pc=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@2c03ebde=0, tmp___3=0, E_M=2, tmp___1=0, T3_E=2, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@5d372538=0, t1_i=1, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@1f56aa13=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@1babdd43=0, \result=1, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@e2dac23=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@433b5a15=0} - StatisticsResult: NonterminationArgumentStatistics Fixpoint - NonterminatingLassoResult [Line: 496]: Nonterminating execution ----- class de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder.RCFGBacktranslator [?] ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; [?] havoc main_#res;havoc main_~__retres1~7;havoc main_~__retres1~7;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; [?] havoc start_simulation_#t~ret16, start_simulation_#t~ret17, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; [?] assume 1 == ~m_i~0;~m_st~0 := 0; [?] assume 1 == ~t1_i~0;~t1_st~0 := 0; [?] assume 1 == ~t2_i~0;~t2_st~0 := 0; [?] assume 1 == ~t3_i~0;~t3_st~0 := 0; [?] assume 1 == ~t4_i~0;~t4_st~0 := 0; [?] assume 1 == ~t5_i~0;~t5_st~0 := 0; [?] assume !(0 == ~M_E~0); [?] assume !(0 == ~T1_E~0); [?] assume !(0 == ~T2_E~0); [?] assume !(0 == ~T3_E~0); [?] assume !(0 == ~T4_E~0); [?] assume !(0 == ~T5_E~0); [?] assume !(0 == ~E_M~0); [?] assume !(0 == ~E_1~0); [?] assume !(0 == ~E_2~0); [?] assume !(0 == ~E_3~0); [?] assume !(0 == ~E_4~0); [?] assume !(0 == ~E_5~0); [?] havoc activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; [?] assume !(1 == ~m_pc~0); [?] is_master_triggered_~__retres1~0 := 0; [?] is_master_triggered_#res := is_master_triggered_~__retres1~0; [?] activate_threads_#t~ret9 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; [?] assume !(0 != activate_threads_~tmp~1); [?] havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; [?] assume !(1 == ~t1_pc~0); [?] is_transmit1_triggered_~__retres1~1 := 0; [?] is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; [?] activate_threads_#t~ret10 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; [?] assume !(0 != activate_threads_~tmp___0~0); [?] havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; [?] assume !(1 == ~t2_pc~0); [?] is_transmit2_triggered_~__retres1~2 := 0; [?] is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; [?] activate_threads_#t~ret11 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; [?] assume !(0 != activate_threads_~tmp___1~0); [?] havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; [?] assume !(1 == ~t3_pc~0); [?] is_transmit3_triggered_~__retres1~3 := 0; [?] is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; [?] activate_threads_#t~ret12 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; [?] assume !(0 != activate_threads_~tmp___2~0); [?] havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; [?] assume !(1 == ~t4_pc~0); [?] is_transmit4_triggered_~__retres1~4 := 0; [?] is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; [?] activate_threads_#t~ret13 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; [?] assume !(0 != activate_threads_~tmp___3~0); [?] havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; [?] assume !(1 == ~t5_pc~0); [?] is_transmit5_triggered_~__retres1~5 := 0; [?] is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; [?] activate_threads_#t~ret14 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; [?] assume !(0 != activate_threads_~tmp___4~0); [?] assume !(1 == ~M_E~0); [?] assume !(1 == ~T1_E~0); [?] assume !(1 == ~T2_E~0); [?] assume !(1 == ~T3_E~0); [?] assume !(1 == ~T4_E~0); [?] assume !(1 == ~T5_E~0); [?] assume !(1 == ~E_M~0); [?] assume !(1 == ~E_1~0); [?] assume !(1 == ~E_2~0); [?] assume !(1 == ~E_3~0); [?] assume !(1 == ~E_4~0); [?] assume !(1 == ~E_5~0); [?] assume !false; [?] start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret2, eval_#t~nondet3, eval_~tmp_ndt_1~0, eval_#t~nondet4, eval_~tmp_ndt_2~0, eval_#t~nondet5, eval_~tmp_ndt_3~0, eval_#t~nondet6, eval_~tmp_ndt_4~0, eval_#t~nondet7, eval_~tmp_ndt_5~0, eval_#t~nondet8, eval_~tmp_ndt_6~0, eval_~tmp~0;havoc eval_~tmp~0; [L14] ~m_pc~0 := 0; [L15] ~t1_pc~0 := 0; [L16] ~t2_pc~0 := 0; [L17] ~t3_pc~0 := 0; [L18] ~t4_pc~0 := 0; [L19] ~t5_pc~0 := 0; [L20] ~m_st~0 := 0; [L21] ~t1_st~0 := 0; [L22] ~t2_st~0 := 0; [L23] ~t3_st~0 := 0; [L24] ~t4_st~0 := 0; [L25] ~t5_st~0 := 0; [L26] ~m_i~0 := 0; [L27] ~t1_i~0 := 0; [L28] ~t2_i~0 := 0; [L29] ~t3_i~0 := 0; [L30] ~t4_i~0 := 0; [L31] ~t5_i~0 := 0; [L32] ~M_E~0 := 2; [L33] ~T1_E~0 := 2; [L34] ~T2_E~0 := 2; [L35] ~T3_E~0 := 2; [L36] ~T4_E~0 := 2; [L37] ~T5_E~0 := 2; [L38] ~E_M~0 := 2; [L39] ~E_1~0 := 2; [L40] ~E_2~0 := 2; [L41] ~E_3~0 := 2; [L42] ~E_4~0 := 2; [L43] ~E_5~0 := 2; [L51] ~token~0 := 0; [L53] ~local~0 := 0; [?] havoc main_#res; [?] havoc main_~__retres1~7; [L975] havoc main_~__retres1~7; [L886] ~m_i~0 := 1; [L887] ~t1_i~0 := 1; [L888] ~t2_i~0 := 1; [L889] ~t3_i~0 := 1; [L890] ~t4_i~0 := 1; [L891] ~t5_i~0 := 1; [L980] havoc start_simulation_#t~ret16, start_simulation_#t~ret17, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1; [L916] havoc start_simulation_~kernel_st~0; [L917] havoc start_simulation_~tmp~3; [L918] havoc start_simulation_~tmp___0~1; [L922] start_simulation_~kernel_st~0 := 0; [L416-L420] assume 1 == ~m_i~0; [L417] ~m_st~0 := 0; [L421-L425] assume 1 == ~t1_i~0; [L422] ~t1_st~0 := 0; [L426-L430] assume 1 == ~t2_i~0; [L427] ~t2_st~0 := 0; [L431-L435] assume 1 == ~t3_i~0; [L432] ~t3_st~0 := 0; [L436-L440] assume 1 == ~t4_i~0; [L437] ~t4_st~0 := 0; [L441-L445] assume 1 == ~t5_i~0; [L442] ~t5_st~0 := 0; [L601-L605] assume !(0 == ~M_E~0); [L606-L610] assume !(0 == ~T1_E~0); [L611-L615] assume !(0 == ~T2_E~0); [L616-L620] assume !(0 == ~T3_E~0); [L621-L625] assume !(0 == ~T4_E~0); [L626-L630] assume !(0 == ~T5_E~0); [L631-L635] assume !(0 == ~E_M~0); [L636-L640] assume !(0 == ~E_1~0); [L641-L645] assume !(0 == ~E_2~0); [L646-L650] assume !(0 == ~E_3~0); [L651-L655] assume !(0 == ~E_4~0); [L656-L660] assume !(0 == ~E_5~0); [L926] havoc activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0; [L734] havoc activate_threads_~tmp~1; [L735] havoc activate_threads_~tmp___0~0; [L736] havoc activate_threads_~tmp___1~0; [L737] havoc activate_threads_~tmp___2~0; [L738] havoc activate_threads_~tmp___3~0; [L739] havoc activate_threads_~tmp___4~0; [L743] havoc is_master_triggered_#res; [L743] havoc is_master_triggered_~__retres1~0; [L291] havoc is_master_triggered_~__retres1~0; [L294-L303] assume !(1 == ~m_pc~0); [L304] is_master_triggered_~__retres1~0 := 0; [L306] is_master_triggered_#res := is_master_triggered_~__retres1~0; [L743] activate_threads_#t~ret9 := is_master_triggered_#res; [L743] activate_threads_~tmp~1 := activate_threads_#t~ret9; [L743] havoc activate_threads_#t~ret9; [L745-L749] assume !(0 != activate_threads_~tmp~1); [L751] havoc is_transmit1_triggered_#res; [L751] havoc is_transmit1_triggered_~__retres1~1; [L310] havoc is_transmit1_triggered_~__retres1~1; [L313-L322] assume !(1 == ~t1_pc~0); [L323] is_transmit1_triggered_~__retres1~1 := 0; [L325] is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; [L751] activate_threads_#t~ret10 := is_transmit1_triggered_#res; [L751] activate_threads_~tmp___0~0 := activate_threads_#t~ret10; [L751] havoc activate_threads_#t~ret10; [L753-L757] assume !(0 != activate_threads_~tmp___0~0); [L759] havoc is_transmit2_triggered_#res; [L759] havoc is_transmit2_triggered_~__retres1~2; [L329] havoc is_transmit2_triggered_~__retres1~2; [L332-L341] assume !(1 == ~t2_pc~0); [L342] is_transmit2_triggered_~__retres1~2 := 0; [L344] is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; [L759] activate_threads_#t~ret11 := is_transmit2_triggered_#res; [L759] activate_threads_~tmp___1~0 := activate_threads_#t~ret11; [L759] havoc activate_threads_#t~ret11; [L761-L765] assume !(0 != activate_threads_~tmp___1~0); [L767] havoc is_transmit3_triggered_#res; [L767] havoc is_transmit3_triggered_~__retres1~3; [L348] havoc is_transmit3_triggered_~__retres1~3; [L351-L360] assume !(1 == ~t3_pc~0); [L361] is_transmit3_triggered_~__retres1~3 := 0; [L363] is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; [L767] activate_threads_#t~ret12 := is_transmit3_triggered_#res; [L767] activate_threads_~tmp___2~0 := activate_threads_#t~ret12; [L767] havoc activate_threads_#t~ret12; [L769-L773] assume !(0 != activate_threads_~tmp___2~0); [L775] havoc is_transmit4_triggered_#res; [L775] havoc is_transmit4_triggered_~__retres1~4; [L367] havoc is_transmit4_triggered_~__retres1~4; [L370-L379] assume !(1 == ~t4_pc~0); [L380] is_transmit4_triggered_~__retres1~4 := 0; [L382] is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; [L775] activate_threads_#t~ret13 := is_transmit4_triggered_#res; [L775] activate_threads_~tmp___3~0 := activate_threads_#t~ret13; [L775] havoc activate_threads_#t~ret13; [L777-L781] assume !(0 != activate_threads_~tmp___3~0); [L783] havoc is_transmit5_triggered_#res; [L783] havoc is_transmit5_triggered_~__retres1~5; [L386] havoc is_transmit5_triggered_~__retres1~5; [L389-L398] assume !(1 == ~t5_pc~0); [L399] is_transmit5_triggered_~__retres1~5 := 0; [L401] is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; [L783] activate_threads_#t~ret14 := is_transmit5_triggered_#res; [L783] activate_threads_~tmp___4~0 := activate_threads_#t~ret14; [L783] havoc activate_threads_#t~ret14; [L785-L789] assume !(0 != activate_threads_~tmp___4~0); [L669-L673] assume !(1 == ~M_E~0); [L674-L678] assume !(1 == ~T1_E~0); [L679-L683] assume !(1 == ~T2_E~0); [L684-L688] assume !(1 == ~T3_E~0); [L689-L693] assume !(1 == ~T4_E~0); [L694-L698] assume !(1 == ~T5_E~0); [L699-L703] assume !(1 == ~E_M~0); [L704-L708] assume !(1 == ~E_1~0); [L709-L713] assume !(1 == ~E_2~0); [L714-L718] assume !(1 == ~E_3~0); [L719-L723] assume !(1 == ~E_4~0); [L724-L728] assume !(1 == ~E_5~0); [L930-L967] assume !false; [L933] start_simulation_~kernel_st~0 := 1; [L934] havoc eval_#t~ret2, eval_#t~nondet3, eval_~tmp_ndt_1~0, eval_#t~nondet4, eval_~tmp_ndt_2~0, eval_#t~nondet5, eval_~tmp_ndt_3~0, eval_#t~nondet6, eval_~tmp_ndt_4~0, eval_#t~nondet7, eval_~tmp_ndt_5~0, eval_#t~nondet8, eval_~tmp_ndt_6~0, eval_~tmp~0; [L492] havoc eval_~tmp~0; ----- ----- class de.uni_freiburg.informatik.ultimate.boogie.preprocessor.BoogiePreprocessorBacktranslator [L14] ~m_pc~0 := 0; [L15] ~t1_pc~0 := 0; [L16] ~t2_pc~0 := 0; [L17] ~t3_pc~0 := 0; [L18] ~t4_pc~0 := 0; [L19] ~t5_pc~0 := 0; [L20] ~m_st~0 := 0; [L21] ~t1_st~0 := 0; [L22] ~t2_st~0 := 0; [L23] ~t3_st~0 := 0; [L24] ~t4_st~0 := 0; [L25] ~t5_st~0 := 0; [L26] ~m_i~0 := 0; [L27] ~t1_i~0 := 0; [L28] ~t2_i~0 := 0; [L29] ~t3_i~0 := 0; [L30] ~t4_i~0 := 0; [L31] ~t5_i~0 := 0; [L32] ~M_E~0 := 2; [L33] ~T1_E~0 := 2; [L34] ~T2_E~0 := 2; [L35] ~T3_E~0 := 2; [L36] ~T4_E~0 := 2; [L37] ~T5_E~0 := 2; [L38] ~E_M~0 := 2; [L39] ~E_1~0 := 2; [L40] ~E_2~0 := 2; [L41] ~E_3~0 := 2; [L42] ~E_4~0 := 2; [L43] ~E_5~0 := 2; [L51] ~token~0 := 0; [L53] ~local~0 := 0; [?] havoc main_#res; [?] havoc main_~__retres1~7; [L975] havoc main_~__retres1~7; [L886] ~m_i~0 := 1; [L887] ~t1_i~0 := 1; [L888] ~t2_i~0 := 1; [L889] ~t3_i~0 := 1; [L890] ~t4_i~0 := 1; [L891] ~t5_i~0 := 1; [L980] havoc start_simulation_#t~ret16, start_simulation_#t~ret17, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1; [L916] havoc start_simulation_~kernel_st~0; [L917] havoc start_simulation_~tmp~3; [L918] havoc start_simulation_~tmp___0~1; [L922] start_simulation_~kernel_st~0 := 0; [L416-L420] assume 1 == ~m_i~0; [L417] ~m_st~0 := 0; [L421-L425] assume 1 == ~t1_i~0; [L422] ~t1_st~0 := 0; [L426-L430] assume 1 == ~t2_i~0; [L427] ~t2_st~0 := 0; [L431-L435] assume 1 == ~t3_i~0; [L432] ~t3_st~0 := 0; [L436-L440] assume 1 == ~t4_i~0; [L437] ~t4_st~0 := 0; [L441-L445] assume 1 == ~t5_i~0; [L442] ~t5_st~0 := 0; [L601-L605] assume !(0 == ~M_E~0); [L606-L610] assume !(0 == ~T1_E~0); [L611-L615] assume !(0 == ~T2_E~0); [L616-L620] assume !(0 == ~T3_E~0); [L621-L625] assume !(0 == ~T4_E~0); [L626-L630] assume !(0 == ~T5_E~0); [L631-L635] assume !(0 == ~E_M~0); [L636-L640] assume !(0 == ~E_1~0); [L641-L645] assume !(0 == ~E_2~0); [L646-L650] assume !(0 == ~E_3~0); [L651-L655] assume !(0 == ~E_4~0); [L656-L660] assume !(0 == ~E_5~0); [L926] havoc activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0; [L734] havoc activate_threads_~tmp~1; [L735] havoc activate_threads_~tmp___0~0; [L736] havoc activate_threads_~tmp___1~0; [L737] havoc activate_threads_~tmp___2~0; [L738] havoc activate_threads_~tmp___3~0; [L739] havoc activate_threads_~tmp___4~0; [L743] havoc is_master_triggered_#res; [L743] havoc is_master_triggered_~__retres1~0; [L291] havoc is_master_triggered_~__retres1~0; [L294-L303] assume !(1 == ~m_pc~0); [L304] is_master_triggered_~__retres1~0 := 0; [L306] is_master_triggered_#res := is_master_triggered_~__retres1~0; [L743] activate_threads_#t~ret9 := is_master_triggered_#res; [L743] activate_threads_~tmp~1 := activate_threads_#t~ret9; [L743] havoc activate_threads_#t~ret9; [L745-L749] assume !(0 != activate_threads_~tmp~1); [L751] havoc is_transmit1_triggered_#res; [L751] havoc is_transmit1_triggered_~__retres1~1; [L310] havoc is_transmit1_triggered_~__retres1~1; [L313-L322] assume !(1 == ~t1_pc~0); [L323] is_transmit1_triggered_~__retres1~1 := 0; [L325] is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; [L751] activate_threads_#t~ret10 := is_transmit1_triggered_#res; [L751] activate_threads_~tmp___0~0 := activate_threads_#t~ret10; [L751] havoc activate_threads_#t~ret10; [L753-L757] assume !(0 != activate_threads_~tmp___0~0); [L759] havoc is_transmit2_triggered_#res; [L759] havoc is_transmit2_triggered_~__retres1~2; [L329] havoc is_transmit2_triggered_~__retres1~2; [L332-L341] assume !(1 == ~t2_pc~0); [L342] is_transmit2_triggered_~__retres1~2 := 0; [L344] is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; [L759] activate_threads_#t~ret11 := is_transmit2_triggered_#res; [L759] activate_threads_~tmp___1~0 := activate_threads_#t~ret11; [L759] havoc activate_threads_#t~ret11; [L761-L765] assume !(0 != activate_threads_~tmp___1~0); [L767] havoc is_transmit3_triggered_#res; [L767] havoc is_transmit3_triggered_~__retres1~3; [L348] havoc is_transmit3_triggered_~__retres1~3; [L351-L360] assume !(1 == ~t3_pc~0); [L361] is_transmit3_triggered_~__retres1~3 := 0; [L363] is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; [L767] activate_threads_#t~ret12 := is_transmit3_triggered_#res; [L767] activate_threads_~tmp___2~0 := activate_threads_#t~ret12; [L767] havoc activate_threads_#t~ret12; [L769-L773] assume !(0 != activate_threads_~tmp___2~0); [L775] havoc is_transmit4_triggered_#res; [L775] havoc is_transmit4_triggered_~__retres1~4; [L367] havoc is_transmit4_triggered_~__retres1~4; [L370-L379] assume !(1 == ~t4_pc~0); [L380] is_transmit4_triggered_~__retres1~4 := 0; [L382] is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; [L775] activate_threads_#t~ret13 := is_transmit4_triggered_#res; [L775] activate_threads_~tmp___3~0 := activate_threads_#t~ret13; [L775] havoc activate_threads_#t~ret13; [L777-L781] assume !(0 != activate_threads_~tmp___3~0); [L783] havoc is_transmit5_triggered_#res; [L783] havoc is_transmit5_triggered_~__retres1~5; [L386] havoc is_transmit5_triggered_~__retres1~5; [L389-L398] assume !(1 == ~t5_pc~0); [L399] is_transmit5_triggered_~__retres1~5 := 0; [L401] is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; [L783] activate_threads_#t~ret14 := is_transmit5_triggered_#res; [L783] activate_threads_~tmp___4~0 := activate_threads_#t~ret14; [L783] havoc activate_threads_#t~ret14; [L785-L789] assume !(0 != activate_threads_~tmp___4~0); [L669-L673] assume !(1 == ~M_E~0); [L674-L678] assume !(1 == ~T1_E~0); [L679-L683] assume !(1 == ~T2_E~0); [L684-L688] assume !(1 == ~T3_E~0); [L689-L693] assume !(1 == ~T4_E~0); [L694-L698] assume !(1 == ~T5_E~0); [L699-L703] assume !(1 == ~E_M~0); [L704-L708] assume !(1 == ~E_1~0); [L709-L713] assume !(1 == ~E_2~0); [L714-L718] assume !(1 == ~E_3~0); [L719-L723] assume !(1 == ~E_4~0); [L724-L728] assume !(1 == ~E_5~0); [L930-L967] assume !false; [L933] start_simulation_~kernel_st~0 := 1; [L934] havoc eval_#t~ret2, eval_#t~nondet3, eval_~tmp_ndt_1~0, eval_#t~nondet4, eval_~tmp_ndt_2~0, eval_#t~nondet5, eval_~tmp_ndt_3~0, eval_#t~nondet6, eval_~tmp_ndt_4~0, eval_#t~nondet7, eval_~tmp_ndt_5~0, eval_#t~nondet8, eval_~tmp_ndt_6~0, eval_~tmp~0; [L492] havoc eval_~tmp~0; [L14] ~m_pc~0 := 0; [L15] ~t1_pc~0 := 0; [L16] ~t2_pc~0 := 0; [L17] ~t3_pc~0 := 0; [L18] ~t4_pc~0 := 0; [L19] ~t5_pc~0 := 0; [L20] ~m_st~0 := 0; [L21] ~t1_st~0 := 0; [L22] ~t2_st~0 := 0; [L23] ~t3_st~0 := 0; [L24] ~t4_st~0 := 0; [L25] ~t5_st~0 := 0; [L26] ~m_i~0 := 0; [L27] ~t1_i~0 := 0; [L28] ~t2_i~0 := 0; [L29] ~t3_i~0 := 0; [L30] ~t4_i~0 := 0; [L31] ~t5_i~0 := 0; [L32] ~M_E~0 := 2; [L33] ~T1_E~0 := 2; [L34] ~T2_E~0 := 2; [L35] ~T3_E~0 := 2; [L36] ~T4_E~0 := 2; [L37] ~T5_E~0 := 2; [L38] ~E_M~0 := 2; [L39] ~E_1~0 := 2; [L40] ~E_2~0 := 2; [L41] ~E_3~0 := 2; [L42] ~E_4~0 := 2; [L43] ~E_5~0 := 2; [L51] ~token~0 := 0; [L53] ~local~0 := 0; [?] havoc main_#res; [?] havoc main_~__retres1~7; [L975] havoc main_~__retres1~7; [L886] ~m_i~0 := 1; [L887] ~t1_i~0 := 1; [L888] ~t2_i~0 := 1; [L889] ~t3_i~0 := 1; [L890] ~t4_i~0 := 1; [L891] ~t5_i~0 := 1; [L980] havoc start_simulation_#t~ret16, start_simulation_#t~ret17, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1; [L916] havoc start_simulation_~kernel_st~0; [L917] havoc start_simulation_~tmp~3; [L918] havoc start_simulation_~tmp___0~1; [L922] start_simulation_~kernel_st~0 := 0; [L416] COND TRUE 1 == ~m_i~0 [L417] ~m_st~0 := 0; [L421] COND TRUE 1 == ~t1_i~0 [L422] ~t1_st~0 := 0; [L426] COND TRUE 1 == ~t2_i~0 [L427] ~t2_st~0 := 0; [L431] COND TRUE 1 == ~t3_i~0 [L432] ~t3_st~0 := 0; [L436] COND TRUE 1 == ~t4_i~0 [L437] ~t4_st~0 := 0; [L441] COND TRUE 1 == ~t5_i~0 [L442] ~t5_st~0 := 0; [L601] COND FALSE !(0 == ~M_E~0) [L606] COND FALSE !(0 == ~T1_E~0) [L611] COND FALSE !(0 == ~T2_E~0) [L616] COND FALSE !(0 == ~T3_E~0) [L621] COND FALSE !(0 == ~T4_E~0) [L626] COND FALSE !(0 == ~T5_E~0) [L631] COND FALSE !(0 == ~E_M~0) [L636] COND FALSE !(0 == ~E_1~0) [L641] COND FALSE !(0 == ~E_2~0) [L646] COND FALSE !(0 == ~E_3~0) [L651] COND FALSE !(0 == ~E_4~0) [L656] COND FALSE !(0 == ~E_5~0) [L926] havoc activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0; [L734] havoc activate_threads_~tmp~1; [L735] havoc activate_threads_~tmp___0~0; [L736] havoc activate_threads_~tmp___1~0; [L737] havoc activate_threads_~tmp___2~0; [L738] havoc activate_threads_~tmp___3~0; [L739] havoc activate_threads_~tmp___4~0; [L743] havoc is_master_triggered_#res; [L743] havoc is_master_triggered_~__retres1~0; [L291] havoc is_master_triggered_~__retres1~0; [L294] COND FALSE !(1 == ~m_pc~0) [L304] is_master_triggered_~__retres1~0 := 0; [L306] is_master_triggered_#res := is_master_triggered_~__retres1~0; [L743] activate_threads_#t~ret9 := is_master_triggered_#res; [L743] activate_threads_~tmp~1 := activate_threads_#t~ret9; [L743] havoc activate_threads_#t~ret9; [L745-L749] COND FALSE !(0 != activate_threads_~tmp~1) [L751] havoc is_transmit1_triggered_#res; [L751] havoc is_transmit1_triggered_~__retres1~1; [L310] havoc is_transmit1_triggered_~__retres1~1; [L313] COND FALSE !(1 == ~t1_pc~0) [L323] is_transmit1_triggered_~__retres1~1 := 0; [L325] is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; [L751] activate_threads_#t~ret10 := is_transmit1_triggered_#res; [L751] activate_threads_~tmp___0~0 := activate_threads_#t~ret10; [L751] havoc activate_threads_#t~ret10; [L753-L757] COND FALSE !(0 != activate_threads_~tmp___0~0) [L759] havoc is_transmit2_triggered_#res; [L759] havoc is_transmit2_triggered_~__retres1~2; [L329] havoc is_transmit2_triggered_~__retres1~2; [L332] COND FALSE !(1 == ~t2_pc~0) [L342] is_transmit2_triggered_~__retres1~2 := 0; [L344] is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; [L759] activate_threads_#t~ret11 := is_transmit2_triggered_#res; [L759] activate_threads_~tmp___1~0 := activate_threads_#t~ret11; [L759] havoc activate_threads_#t~ret11; [L761-L765] COND FALSE !(0 != activate_threads_~tmp___1~0) [L767] havoc is_transmit3_triggered_#res; [L767] havoc is_transmit3_triggered_~__retres1~3; [L348] havoc is_transmit3_triggered_~__retres1~3; [L351] COND FALSE !(1 == ~t3_pc~0) [L361] is_transmit3_triggered_~__retres1~3 := 0; [L363] is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; [L767] activate_threads_#t~ret12 := is_transmit3_triggered_#res; [L767] activate_threads_~tmp___2~0 := activate_threads_#t~ret12; [L767] havoc activate_threads_#t~ret12; [L769-L773] COND FALSE !(0 != activate_threads_~tmp___2~0) [L775] havoc is_transmit4_triggered_#res; [L775] havoc is_transmit4_triggered_~__retres1~4; [L367] havoc is_transmit4_triggered_~__retres1~4; [L370] COND FALSE !(1 == ~t4_pc~0) [L380] is_transmit4_triggered_~__retres1~4 := 0; [L382] is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; [L775] activate_threads_#t~ret13 := is_transmit4_triggered_#res; [L775] activate_threads_~tmp___3~0 := activate_threads_#t~ret13; [L775] havoc activate_threads_#t~ret13; [L777-L781] COND FALSE !(0 != activate_threads_~tmp___3~0) [L783] havoc is_transmit5_triggered_#res; [L783] havoc is_transmit5_triggered_~__retres1~5; [L386] havoc is_transmit5_triggered_~__retres1~5; [L389] COND FALSE !(1 == ~t5_pc~0) [L399] is_transmit5_triggered_~__retres1~5 := 0; [L401] is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; [L783] activate_threads_#t~ret14 := is_transmit5_triggered_#res; [L783] activate_threads_~tmp___4~0 := activate_threads_#t~ret14; [L783] havoc activate_threads_#t~ret14; [L785-L789] COND FALSE !(0 != activate_threads_~tmp___4~0) [L669] COND FALSE !(1 == ~M_E~0) [L674] COND FALSE !(1 == ~T1_E~0) [L679] COND FALSE !(1 == ~T2_E~0) [L684] COND FALSE !(1 == ~T3_E~0) [L689] COND FALSE !(1 == ~T4_E~0) [L694] COND FALSE !(1 == ~T5_E~0) [L699] COND FALSE !(1 == ~E_M~0) [L704] COND FALSE !(1 == ~E_1~0) [L709] COND FALSE !(1 == ~E_2~0) [L714] COND FALSE !(1 == ~E_3~0) [L719] COND FALSE !(1 == ~E_4~0) [L724] COND FALSE !(1 == ~E_5~0) [L930-L967] COND FALSE !(false) [L933] start_simulation_~kernel_st~0 := 1; [L934] havoc eval_#t~ret2, eval_#t~nondet3, eval_~tmp_ndt_1~0, eval_#t~nondet4, eval_~tmp_ndt_2~0, eval_#t~nondet5, eval_~tmp_ndt_3~0, eval_#t~nondet6, eval_~tmp_ndt_4~0, eval_#t~nondet7, eval_~tmp_ndt_5~0, eval_#t~nondet8, eval_~tmp_ndt_6~0, eval_~tmp~0; [L492] havoc eval_~tmp~0; ----- ----- class de.uni_freiburg.informatik.ultimate.boogie.procedureinliner.backtranslation.InlinerBacktranslator [L14] ~m_pc~0 := 0; [L15] ~t1_pc~0 := 0; [L16] ~t2_pc~0 := 0; [L17] ~t3_pc~0 := 0; [L18] ~t4_pc~0 := 0; [L19] ~t5_pc~0 := 0; [L20] ~m_st~0 := 0; [L21] ~t1_st~0 := 0; [L22] ~t2_st~0 := 0; [L23] ~t3_st~0 := 0; [L24] ~t4_st~0 := 0; [L25] ~t5_st~0 := 0; [L26] ~m_i~0 := 0; [L27] ~t1_i~0 := 0; [L28] ~t2_i~0 := 0; [L29] ~t3_i~0 := 0; [L30] ~t4_i~0 := 0; [L31] ~t5_i~0 := 0; [L32] ~M_E~0 := 2; [L33] ~T1_E~0 := 2; [L34] ~T2_E~0 := 2; [L35] ~T3_E~0 := 2; [L36] ~T4_E~0 := 2; [L37] ~T5_E~0 := 2; [L38] ~E_M~0 := 2; [L39] ~E_1~0 := 2; [L40] ~E_2~0 := 2; [L41] ~E_3~0 := 2; [L42] ~E_4~0 := 2; [L43] ~E_5~0 := 2; [L51] ~token~0 := 0; [L53] ~local~0 := 0; [?] havoc main_#res; [?] havoc main_~__retres1~7; [L975] havoc main_~__retres1~7; [L886] ~m_i~0 := 1; [L887] ~t1_i~0 := 1; [L888] ~t2_i~0 := 1; [L889] ~t3_i~0 := 1; [L890] ~t4_i~0 := 1; [L891] ~t5_i~0 := 1; [L980] havoc start_simulation_#t~ret16, start_simulation_#t~ret17, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1; [L916] havoc start_simulation_~kernel_st~0; [L917] havoc start_simulation_~tmp~3; [L918] havoc start_simulation_~tmp___0~1; [L922] start_simulation_~kernel_st~0 := 0; [L416] COND TRUE 1 == ~m_i~0 [L417] ~m_st~0 := 0; [L421] COND TRUE 1 == ~t1_i~0 [L422] ~t1_st~0 := 0; [L426] COND TRUE 1 == ~t2_i~0 [L427] ~t2_st~0 := 0; [L431] COND TRUE 1 == ~t3_i~0 [L432] ~t3_st~0 := 0; [L436] COND TRUE 1 == ~t4_i~0 [L437] ~t4_st~0 := 0; [L441] COND TRUE 1 == ~t5_i~0 [L442] ~t5_st~0 := 0; [L601] COND FALSE !(0 == ~M_E~0) [L606] COND FALSE !(0 == ~T1_E~0) [L611] COND FALSE !(0 == ~T2_E~0) [L616] COND FALSE !(0 == ~T3_E~0) [L621] COND FALSE !(0 == ~T4_E~0) [L626] COND FALSE !(0 == ~T5_E~0) [L631] COND FALSE !(0 == ~E_M~0) [L636] COND FALSE !(0 == ~E_1~0) [L641] COND FALSE !(0 == ~E_2~0) [L646] COND FALSE !(0 == ~E_3~0) [L651] COND FALSE !(0 == ~E_4~0) [L656] COND FALSE !(0 == ~E_5~0) [L926] havoc activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0; [L734] havoc activate_threads_~tmp~1; [L735] havoc activate_threads_~tmp___0~0; [L736] havoc activate_threads_~tmp___1~0; [L737] havoc activate_threads_~tmp___2~0; [L738] havoc activate_threads_~tmp___3~0; [L739] havoc activate_threads_~tmp___4~0; [L743] havoc is_master_triggered_#res; [L743] havoc is_master_triggered_~__retres1~0; [L291] havoc is_master_triggered_~__retres1~0; [L294] COND FALSE !(1 == ~m_pc~0) [L304] is_master_triggered_~__retres1~0 := 0; [L306] is_master_triggered_#res := is_master_triggered_~__retres1~0; [L743] activate_threads_#t~ret9 := is_master_triggered_#res; [L743] activate_threads_~tmp~1 := activate_threads_#t~ret9; [L743] havoc activate_threads_#t~ret9; [L745-L749] COND FALSE !(0 != activate_threads_~tmp~1) [L751] havoc is_transmit1_triggered_#res; [L751] havoc is_transmit1_triggered_~__retres1~1; [L310] havoc is_transmit1_triggered_~__retres1~1; [L313] COND FALSE !(1 == ~t1_pc~0) [L323] is_transmit1_triggered_~__retres1~1 := 0; [L325] is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; [L751] activate_threads_#t~ret10 := is_transmit1_triggered_#res; [L751] activate_threads_~tmp___0~0 := activate_threads_#t~ret10; [L751] havoc activate_threads_#t~ret10; [L753-L757] COND FALSE !(0 != activate_threads_~tmp___0~0) [L759] havoc is_transmit2_triggered_#res; [L759] havoc is_transmit2_triggered_~__retres1~2; [L329] havoc is_transmit2_triggered_~__retres1~2; [L332] COND FALSE !(1 == ~t2_pc~0) [L342] is_transmit2_triggered_~__retres1~2 := 0; [L344] is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; [L759] activate_threads_#t~ret11 := is_transmit2_triggered_#res; [L759] activate_threads_~tmp___1~0 := activate_threads_#t~ret11; [L759] havoc activate_threads_#t~ret11; [L761-L765] COND FALSE !(0 != activate_threads_~tmp___1~0) [L767] havoc is_transmit3_triggered_#res; [L767] havoc is_transmit3_triggered_~__retres1~3; [L348] havoc is_transmit3_triggered_~__retres1~3; [L351] COND FALSE !(1 == ~t3_pc~0) [L361] is_transmit3_triggered_~__retres1~3 := 0; [L363] is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; [L767] activate_threads_#t~ret12 := is_transmit3_triggered_#res; [L767] activate_threads_~tmp___2~0 := activate_threads_#t~ret12; [L767] havoc activate_threads_#t~ret12; [L769-L773] COND FALSE !(0 != activate_threads_~tmp___2~0) [L775] havoc is_transmit4_triggered_#res; [L775] havoc is_transmit4_triggered_~__retres1~4; [L367] havoc is_transmit4_triggered_~__retres1~4; [L370] COND FALSE !(1 == ~t4_pc~0) [L380] is_transmit4_triggered_~__retres1~4 := 0; [L382] is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; [L775] activate_threads_#t~ret13 := is_transmit4_triggered_#res; [L775] activate_threads_~tmp___3~0 := activate_threads_#t~ret13; [L775] havoc activate_threads_#t~ret13; [L777-L781] COND FALSE !(0 != activate_threads_~tmp___3~0) [L783] havoc is_transmit5_triggered_#res; [L783] havoc is_transmit5_triggered_~__retres1~5; [L386] havoc is_transmit5_triggered_~__retres1~5; [L389] COND FALSE !(1 == ~t5_pc~0) [L399] is_transmit5_triggered_~__retres1~5 := 0; [L401] is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; [L783] activate_threads_#t~ret14 := is_transmit5_triggered_#res; [L783] activate_threads_~tmp___4~0 := activate_threads_#t~ret14; [L783] havoc activate_threads_#t~ret14; [L785-L789] COND FALSE !(0 != activate_threads_~tmp___4~0) [L669] COND FALSE !(1 == ~M_E~0) [L674] COND FALSE !(1 == ~T1_E~0) [L679] COND FALSE !(1 == ~T2_E~0) [L684] COND FALSE !(1 == ~T3_E~0) [L689] COND FALSE !(1 == ~T4_E~0) [L694] COND FALSE !(1 == ~T5_E~0) [L699] COND FALSE !(1 == ~E_M~0) [L704] COND FALSE !(1 == ~E_1~0) [L709] COND FALSE !(1 == ~E_2~0) [L714] COND FALSE !(1 == ~E_3~0) [L719] COND FALSE !(1 == ~E_4~0) [L724] COND FALSE !(1 == ~E_5~0) [L930-L967] COND FALSE !(false) [L933] start_simulation_~kernel_st~0 := 1; [L934] havoc eval_#t~ret2, eval_#t~nondet3, eval_~tmp_ndt_1~0, eval_#t~nondet4, eval_~tmp_ndt_2~0, eval_#t~nondet5, eval_~tmp_ndt_3~0, eval_#t~nondet6, eval_~tmp_ndt_4~0, eval_#t~nondet7, eval_~tmp_ndt_5~0, eval_#t~nondet8, eval_~tmp_ndt_6~0, eval_~tmp~0; [L492] havoc eval_~tmp~0; [L14] ~m_pc~0 := 0; [L15] ~t1_pc~0 := 0; [L16] ~t2_pc~0 := 0; [L17] ~t3_pc~0 := 0; [L18] ~t4_pc~0 := 0; [L19] ~t5_pc~0 := 0; [L20] ~m_st~0 := 0; [L21] ~t1_st~0 := 0; [L22] ~t2_st~0 := 0; [L23] ~t3_st~0 := 0; [L24] ~t4_st~0 := 0; [L25] ~t5_st~0 := 0; [L26] ~m_i~0 := 0; [L27] ~t1_i~0 := 0; [L28] ~t2_i~0 := 0; [L29] ~t3_i~0 := 0; [L30] ~t4_i~0 := 0; [L31] ~t5_i~0 := 0; [L32] ~M_E~0 := 2; [L33] ~T1_E~0 := 2; [L34] ~T2_E~0 := 2; [L35] ~T3_E~0 := 2; [L36] ~T4_E~0 := 2; [L37] ~T5_E~0 := 2; [L38] ~E_M~0 := 2; [L39] ~E_1~0 := 2; [L40] ~E_2~0 := 2; [L41] ~E_3~0 := 2; [L42] ~E_4~0 := 2; [L43] ~E_5~0 := 2; [L51] ~token~0 := 0; [L53] ~local~0 := 0; [L975] havoc ~__retres1~7; [L886] ~m_i~0 := 1; [L887] ~t1_i~0 := 1; [L888] ~t2_i~0 := 1; [L889] ~t3_i~0 := 1; [L890] ~t4_i~0 := 1; [L891] ~t5_i~0 := 1; [L916] havoc ~kernel_st~0; [L917] havoc ~tmp~3; [L918] havoc ~tmp___0~1; [L922] ~kernel_st~0 := 0; [L416] COND TRUE 1 == ~m_i~0 [L417] ~m_st~0 := 0; [L421] COND TRUE 1 == ~t1_i~0 [L422] ~t1_st~0 := 0; [L426] COND TRUE 1 == ~t2_i~0 [L427] ~t2_st~0 := 0; [L431] COND TRUE 1 == ~t3_i~0 [L432] ~t3_st~0 := 0; [L436] COND TRUE 1 == ~t4_i~0 [L437] ~t4_st~0 := 0; [L441] COND TRUE 1 == ~t5_i~0 [L442] ~t5_st~0 := 0; [L601] COND FALSE !(0 == ~M_E~0) [L606] COND FALSE !(0 == ~T1_E~0) [L611] COND FALSE !(0 == ~T2_E~0) [L616] COND FALSE !(0 == ~T3_E~0) [L621] COND FALSE !(0 == ~T4_E~0) [L626] COND FALSE !(0 == ~T5_E~0) [L631] COND FALSE !(0 == ~E_M~0) [L636] COND FALSE !(0 == ~E_1~0) [L641] COND FALSE !(0 == ~E_2~0) [L646] COND FALSE !(0 == ~E_3~0) [L651] COND FALSE !(0 == ~E_4~0) [L656] COND FALSE !(0 == ~E_5~0) [L734] havoc ~tmp~1; [L735] havoc ~tmp___0~0; [L736] havoc ~tmp___1~0; [L737] havoc ~tmp___2~0; [L738] havoc ~tmp___3~0; [L739] havoc ~tmp___4~0; [L291] havoc ~__retres1~0; [L294] COND FALSE !(1 == ~m_pc~0) [L304] ~__retres1~0 := 0; [L306] #res := ~__retres1~0; [L743] ~tmp~1 := #t~ret9; [L743] havoc #t~ret9; [L745-L749] COND FALSE !(0 != ~tmp~1) [L310] havoc ~__retres1~1; [L313] COND FALSE !(1 == ~t1_pc~0) [L323] ~__retres1~1 := 0; [L325] #res := ~__retres1~1; [L751] ~tmp___0~0 := #t~ret10; [L751] havoc #t~ret10; [L753-L757] COND FALSE !(0 != ~tmp___0~0) [L329] havoc ~__retres1~2; [L332] COND FALSE !(1 == ~t2_pc~0) [L342] ~__retres1~2 := 0; [L344] #res := ~__retres1~2; [L759] ~tmp___1~0 := #t~ret11; [L759] havoc #t~ret11; [L761-L765] COND FALSE !(0 != ~tmp___1~0) [L348] havoc ~__retres1~3; [L351] COND FALSE !(1 == ~t3_pc~0) [L361] ~__retres1~3 := 0; [L363] #res := ~__retres1~3; [L767] ~tmp___2~0 := #t~ret12; [L767] havoc #t~ret12; [L769-L773] COND FALSE !(0 != ~tmp___2~0) [L367] havoc ~__retres1~4; [L370] COND FALSE !(1 == ~t4_pc~0) [L380] ~__retres1~4 := 0; [L382] #res := ~__retres1~4; [L775] ~tmp___3~0 := #t~ret13; [L775] havoc #t~ret13; [L777-L781] COND FALSE !(0 != ~tmp___3~0) [L386] havoc ~__retres1~5; [L389] COND FALSE !(1 == ~t5_pc~0) [L399] ~__retres1~5 := 0; [L401] #res := ~__retres1~5; [L783] ~tmp___4~0 := #t~ret14; [L783] havoc #t~ret14; [L785-L789] COND FALSE !(0 != ~tmp___4~0) [L669] COND FALSE !(1 == ~M_E~0) [L674] COND FALSE !(1 == ~T1_E~0) [L679] COND FALSE !(1 == ~T2_E~0) [L684] COND FALSE !(1 == ~T3_E~0) [L689] COND FALSE !(1 == ~T4_E~0) [L694] COND FALSE !(1 == ~T5_E~0) [L699] COND FALSE !(1 == ~E_M~0) [L704] COND FALSE !(1 == ~E_1~0) [L709] COND FALSE !(1 == ~E_2~0) [L714] COND FALSE !(1 == ~E_3~0) [L719] COND FALSE !(1 == ~E_4~0) [L724] COND FALSE !(1 == ~E_5~0) [L930-L967] COND FALSE !(false) [L933] ~kernel_st~0 := 1; [L492] havoc ~tmp~0; ----- ----- class de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.CACSL2BoogieBacktranslator [L14] ~m_pc~0 := 0; [L15] ~t1_pc~0 := 0; [L16] ~t2_pc~0 := 0; [L17] ~t3_pc~0 := 0; [L18] ~t4_pc~0 := 0; [L19] ~t5_pc~0 := 0; [L20] ~m_st~0 := 0; [L21] ~t1_st~0 := 0; [L22] ~t2_st~0 := 0; [L23] ~t3_st~0 := 0; [L24] ~t4_st~0 := 0; [L25] ~t5_st~0 := 0; [L26] ~m_i~0 := 0; [L27] ~t1_i~0 := 0; [L28] ~t2_i~0 := 0; [L29] ~t3_i~0 := 0; [L30] ~t4_i~0 := 0; [L31] ~t5_i~0 := 0; [L32] ~M_E~0 := 2; [L33] ~T1_E~0 := 2; [L34] ~T2_E~0 := 2; [L35] ~T3_E~0 := 2; [L36] ~T4_E~0 := 2; [L37] ~T5_E~0 := 2; [L38] ~E_M~0 := 2; [L39] ~E_1~0 := 2; [L40] ~E_2~0 := 2; [L41] ~E_3~0 := 2; [L42] ~E_4~0 := 2; [L43] ~E_5~0 := 2; [L51] ~token~0 := 0; [L53] ~local~0 := 0; [L975] havoc ~__retres1~7; [L886] ~m_i~0 := 1; [L887] ~t1_i~0 := 1; [L888] ~t2_i~0 := 1; [L889] ~t3_i~0 := 1; [L890] ~t4_i~0 := 1; [L891] ~t5_i~0 := 1; [L916] havoc ~kernel_st~0; [L917] havoc ~tmp~3; [L918] havoc ~tmp___0~1; [L922] ~kernel_st~0 := 0; [L416] COND TRUE 1 == ~m_i~0 [L417] ~m_st~0 := 0; [L421] COND TRUE 1 == ~t1_i~0 [L422] ~t1_st~0 := 0; [L426] COND TRUE 1 == ~t2_i~0 [L427] ~t2_st~0 := 0; [L431] COND TRUE 1 == ~t3_i~0 [L432] ~t3_st~0 := 0; [L436] COND TRUE 1 == ~t4_i~0 [L437] ~t4_st~0 := 0; [L441] COND TRUE 1 == ~t5_i~0 [L442] ~t5_st~0 := 0; [L601] COND FALSE !(0 == ~M_E~0) [L606] COND FALSE !(0 == ~T1_E~0) [L611] COND FALSE !(0 == ~T2_E~0) [L616] COND FALSE !(0 == ~T3_E~0) [L621] COND FALSE !(0 == ~T4_E~0) [L626] COND FALSE !(0 == ~T5_E~0) [L631] COND FALSE !(0 == ~E_M~0) [L636] COND FALSE !(0 == ~E_1~0) [L641] COND FALSE !(0 == ~E_2~0) [L646] COND FALSE !(0 == ~E_3~0) [L651] COND FALSE !(0 == ~E_4~0) [L656] COND FALSE !(0 == ~E_5~0) [L734] havoc ~tmp~1; [L735] havoc ~tmp___0~0; [L736] havoc ~tmp___1~0; [L737] havoc ~tmp___2~0; [L738] havoc ~tmp___3~0; [L739] havoc ~tmp___4~0; [L291] havoc ~__retres1~0; [L294] COND FALSE !(1 == ~m_pc~0) [L304] ~__retres1~0 := 0; [L306] #res := ~__retres1~0; [L743] ~tmp~1 := #t~ret9; [L743] havoc #t~ret9; [L745-L749] COND FALSE !(0 != ~tmp~1) [L310] havoc ~__retres1~1; [L313] COND FALSE !(1 == ~t1_pc~0) [L323] ~__retres1~1 := 0; [L325] #res := ~__retres1~1; [L751] ~tmp___0~0 := #t~ret10; [L751] havoc #t~ret10; [L753-L757] COND FALSE !(0 != ~tmp___0~0) [L329] havoc ~__retres1~2; [L332] COND FALSE !(1 == ~t2_pc~0) [L342] ~__retres1~2 := 0; [L344] #res := ~__retres1~2; [L759] ~tmp___1~0 := #t~ret11; [L759] havoc #t~ret11; [L761-L765] COND FALSE !(0 != ~tmp___1~0) [L348] havoc ~__retres1~3; [L351] COND FALSE !(1 == ~t3_pc~0) [L361] ~__retres1~3 := 0; [L363] #res := ~__retres1~3; [L767] ~tmp___2~0 := #t~ret12; [L767] havoc #t~ret12; [L769-L773] COND FALSE !(0 != ~tmp___2~0) [L367] havoc ~__retres1~4; [L370] COND FALSE !(1 == ~t4_pc~0) [L380] ~__retres1~4 := 0; [L382] #res := ~__retres1~4; [L775] ~tmp___3~0 := #t~ret13; [L775] havoc #t~ret13; [L777-L781] COND FALSE !(0 != ~tmp___3~0) [L386] havoc ~__retres1~5; [L389] COND FALSE !(1 == ~t5_pc~0) [L399] ~__retres1~5 := 0; [L401] #res := ~__retres1~5; [L783] ~tmp___4~0 := #t~ret14; [L783] havoc #t~ret14; [L785-L789] COND FALSE !(0 != ~tmp___4~0) [L669] COND FALSE !(1 == ~M_E~0) [L674] COND FALSE !(1 == ~T1_E~0) [L679] COND FALSE !(1 == ~T2_E~0) [L684] COND FALSE !(1 == ~T3_E~0) [L689] COND FALSE !(1 == ~T4_E~0) [L694] COND FALSE !(1 == ~T5_E~0) [L699] COND FALSE !(1 == ~E_M~0) [L704] COND FALSE !(1 == ~E_1~0) [L709] COND FALSE !(1 == ~E_2~0) [L714] COND FALSE !(1 == ~E_3~0) [L719] COND FALSE !(1 == ~E_4~0) [L724] COND FALSE !(1 == ~E_5~0) [L930-L967] COND FALSE !(false) [L933] ~kernel_st~0 := 1; [L492] havoc ~tmp~0; [L14] int m_pc = 0; [L15] int t1_pc = 0; [L16] int t2_pc = 0; [L17] int t3_pc = 0; [L18] int t4_pc = 0; [L19] int t5_pc = 0; [L20] int m_st ; [L21] int t1_st ; [L22] int t2_st ; [L23] int t3_st ; [L24] int t4_st ; [L25] int t5_st ; [L26] int m_i ; [L27] int t1_i ; [L28] int t2_i ; [L29] int t3_i ; [L30] int t4_i ; [L31] int t5_i ; [L32] int M_E = 2; [L33] int T1_E = 2; [L34] int T2_E = 2; [L35] int T3_E = 2; [L36] int T4_E = 2; [L37] int T5_E = 2; [L38] int E_M = 2; [L39] int E_1 = 2; [L40] int E_2 = 2; [L41] int E_3 = 2; [L42] int E_4 = 2; [L43] int E_5 = 2; [L51] int token ; [L53] int local ; [L975] int __retres1 ; [L886] m_i = 1 [L887] t1_i = 1 [L888] t2_i = 1 [L889] t3_i = 1 [L890] t4_i = 1 [L891] t5_i = 1 [L916] int kernel_st ; [L917] int tmp ; [L918] int tmp___0 ; [L922] kernel_st = 0 [L416] COND TRUE m_i == 1 [L417] m_st = 0 [L421] COND TRUE t1_i == 1 [L422] t1_st = 0 [L426] COND TRUE t2_i == 1 [L427] t2_st = 0 [L431] COND TRUE t3_i == 1 [L432] t3_st = 0 [L436] COND TRUE t4_i == 1 [L437] t4_st = 0 [L441] COND TRUE t5_i == 1 [L442] t5_st = 0 [L601] COND FALSE !(M_E == 0) [L606] COND FALSE !(T1_E == 0) [L611] COND FALSE !(T2_E == 0) [L616] COND FALSE !(T3_E == 0) [L621] COND FALSE !(T4_E == 0) [L626] COND FALSE !(T5_E == 0) [L631] COND FALSE !(E_M == 0) [L636] COND FALSE !(E_1 == 0) [L641] COND FALSE !(E_2 == 0) [L646] COND FALSE !(E_3 == 0) [L651] COND FALSE !(E_4 == 0) [L656] COND FALSE !(E_5 == 0) [L734] int tmp ; [L735] int tmp___0 ; [L736] int tmp___1 ; [L737] int tmp___2 ; [L738] int tmp___3 ; [L739] int tmp___4 ; [L291] int __retres1 ; [L294] COND FALSE !(m_pc == 1) [L304] __retres1 = 0 [L306] return (__retres1); [L743] tmp = is_master_triggered() [L745] COND FALSE !(\read(tmp)) [L310] int __retres1 ; [L313] COND FALSE !(t1_pc == 1) [L323] __retres1 = 0 [L325] return (__retres1); [L751] tmp___0 = is_transmit1_triggered() [L753] COND FALSE !(\read(tmp___0)) [L329] int __retres1 ; [L332] COND FALSE !(t2_pc == 1) [L342] __retres1 = 0 [L344] return (__retres1); [L759] tmp___1 = is_transmit2_triggered() [L761] COND FALSE !(\read(tmp___1)) [L348] int __retres1 ; [L351] COND FALSE !(t3_pc == 1) [L361] __retres1 = 0 [L363] return (__retres1); [L767] tmp___2 = is_transmit3_triggered() [L769] COND FALSE !(\read(tmp___2)) [L367] int __retres1 ; [L370] COND FALSE !(t4_pc == 1) [L380] __retres1 = 0 [L382] return (__retres1); [L775] tmp___3 = is_transmit4_triggered() [L777] COND FALSE !(\read(tmp___3)) [L386] int __retres1 ; [L389] COND FALSE !(t5_pc == 1) [L399] __retres1 = 0 [L401] return (__retres1); [L783] tmp___4 = is_transmit5_triggered() [L785] COND FALSE !(\read(tmp___4)) [L669] COND FALSE !(M_E == 1) [L674] COND FALSE !(T1_E == 1) [L679] COND FALSE !(T2_E == 1) [L684] COND FALSE !(T3_E == 1) [L689] COND FALSE !(T4_E == 1) [L694] COND FALSE !(T5_E == 1) [L699] COND FALSE !(E_M == 1) [L704] COND FALSE !(E_1 == 1) [L709] COND FALSE !(E_2 == 1) [L714] COND FALSE !(E_3 == 1) [L719] COND FALSE !(E_4 == 1) [L724] COND FALSE !(E_5 == 1) [L930] COND TRUE 1 [L933] kernel_st = 1 [L492] int tmp ; ----- ----- class de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder.RCFGBacktranslator [?] assume !false; [?] havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; [?] assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; [?] exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; [?] eval_#t~ret2 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret2;havoc eval_#t~ret2; [?] assume 0 != eval_~tmp~0; [?] assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0;eval_~tmp_ndt_1~0 := eval_#t~nondet3;havoc eval_#t~nondet3; [?] assume !(0 != eval_~tmp_ndt_1~0); [?] assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0;eval_~tmp_ndt_2~0 := eval_#t~nondet4;havoc eval_#t~nondet4; [?] assume !(0 != eval_~tmp_ndt_2~0); [?] assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0;eval_~tmp_ndt_3~0 := eval_#t~nondet5;havoc eval_#t~nondet5; [?] assume !(0 != eval_~tmp_ndt_3~0); [?] assume 0 == ~t3_st~0;havoc eval_~tmp_ndt_4~0;eval_~tmp_ndt_4~0 := eval_#t~nondet6;havoc eval_#t~nondet6; [?] assume !(0 != eval_~tmp_ndt_4~0); [?] assume 0 == ~t4_st~0;havoc eval_~tmp_ndt_5~0;eval_~tmp_ndt_5~0 := eval_#t~nondet7;havoc eval_#t~nondet7; [?] assume !(0 != eval_~tmp_ndt_5~0); [?] assume 0 == ~t5_st~0;havoc eval_~tmp_ndt_6~0;eval_~tmp_ndt_6~0 := eval_#t~nondet8;havoc eval_#t~nondet8; [?] assume !(0 != eval_~tmp_ndt_6~0); [L496-L590] assume !false; [L499] havoc exists_runnable_thread_#res; [L499] havoc exists_runnable_thread_~__retres1~6; [L451] havoc exists_runnable_thread_~__retres1~6; [L454-L484] assume 0 == ~m_st~0; [L455] exists_runnable_thread_~__retres1~6 := 1; [L487] exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; [L499] eval_#t~ret2 := exists_runnable_thread_#res; [L499] eval_~tmp~0 := eval_#t~ret2; [L499] havoc eval_#t~ret2; [L501-L505] assume 0 != eval_~tmp~0; [L506-L519] assume 0 == ~m_st~0; [L507] havoc eval_~tmp_ndt_1~0; [L508] eval_~tmp_ndt_1~0 := eval_#t~nondet3; [L508] havoc eval_#t~nondet3; [L509-L516] assume !(0 != eval_~tmp_ndt_1~0); [L520-L533] assume 0 == ~t1_st~0; [L521] havoc eval_~tmp_ndt_2~0; [L522] eval_~tmp_ndt_2~0 := eval_#t~nondet4; [L522] havoc eval_#t~nondet4; [L523-L530] assume !(0 != eval_~tmp_ndt_2~0); [L534-L547] assume 0 == ~t2_st~0; [L535] havoc eval_~tmp_ndt_3~0; [L536] eval_~tmp_ndt_3~0 := eval_#t~nondet5; [L536] havoc eval_#t~nondet5; [L537-L544] assume !(0 != eval_~tmp_ndt_3~0); [L548-L561] assume 0 == ~t3_st~0; [L549] havoc eval_~tmp_ndt_4~0; [L550] eval_~tmp_ndt_4~0 := eval_#t~nondet6; [L550] havoc eval_#t~nondet6; [L551-L558] assume !(0 != eval_~tmp_ndt_4~0); [L562-L575] assume 0 == ~t4_st~0; [L563] havoc eval_~tmp_ndt_5~0; [L564] eval_~tmp_ndt_5~0 := eval_#t~nondet7; [L564] havoc eval_#t~nondet7; [L565-L572] assume !(0 != eval_~tmp_ndt_5~0); [L576-L589] assume 0 == ~t5_st~0; [L577] havoc eval_~tmp_ndt_6~0; [L578] eval_~tmp_ndt_6~0 := eval_#t~nondet8; [L578] havoc eval_#t~nondet8; [L579-L586] assume !(0 != eval_~tmp_ndt_6~0); ----- ----- class de.uni_freiburg.informatik.ultimate.boogie.preprocessor.BoogiePreprocessorBacktranslator [L496-L590] assume !false; [L499] havoc exists_runnable_thread_#res; [L499] havoc exists_runnable_thread_~__retres1~6; [L451] havoc exists_runnable_thread_~__retres1~6; [L454-L484] assume 0 == ~m_st~0; [L455] exists_runnable_thread_~__retres1~6 := 1; [L487] exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; [L499] eval_#t~ret2 := exists_runnable_thread_#res; [L499] eval_~tmp~0 := eval_#t~ret2; [L499] havoc eval_#t~ret2; [L501-L505] assume 0 != eval_~tmp~0; [L506-L519] assume 0 == ~m_st~0; [L507] havoc eval_~tmp_ndt_1~0; [L508] eval_~tmp_ndt_1~0 := eval_#t~nondet3; [L508] havoc eval_#t~nondet3; [L509-L516] assume !(0 != eval_~tmp_ndt_1~0); [L520-L533] assume 0 == ~t1_st~0; [L521] havoc eval_~tmp_ndt_2~0; [L522] eval_~tmp_ndt_2~0 := eval_#t~nondet4; [L522] havoc eval_#t~nondet4; [L523-L530] assume !(0 != eval_~tmp_ndt_2~0); [L534-L547] assume 0 == ~t2_st~0; [L535] havoc eval_~tmp_ndt_3~0; [L536] eval_~tmp_ndt_3~0 := eval_#t~nondet5; [L536] havoc eval_#t~nondet5; [L537-L544] assume !(0 != eval_~tmp_ndt_3~0); [L548-L561] assume 0 == ~t3_st~0; [L549] havoc eval_~tmp_ndt_4~0; [L550] eval_~tmp_ndt_4~0 := eval_#t~nondet6; [L550] havoc eval_#t~nondet6; [L551-L558] assume !(0 != eval_~tmp_ndt_4~0); [L562-L575] assume 0 == ~t4_st~0; [L563] havoc eval_~tmp_ndt_5~0; [L564] eval_~tmp_ndt_5~0 := eval_#t~nondet7; [L564] havoc eval_#t~nondet7; [L565-L572] assume !(0 != eval_~tmp_ndt_5~0); [L576-L589] assume 0 == ~t5_st~0; [L577] havoc eval_~tmp_ndt_6~0; [L578] eval_~tmp_ndt_6~0 := eval_#t~nondet8; [L578] havoc eval_#t~nondet8; [L579-L586] assume !(0 != eval_~tmp_ndt_6~0); [L496-L590] COND FALSE !(false) [L499] havoc exists_runnable_thread_#res; [L499] havoc exists_runnable_thread_~__retres1~6; [L451] havoc exists_runnable_thread_~__retres1~6; [L454] COND TRUE 0 == ~m_st~0 [L455] exists_runnable_thread_~__retres1~6 := 1; [L487] exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; [L499] eval_#t~ret2 := exists_runnable_thread_#res; [L499] eval_~tmp~0 := eval_#t~ret2; [L499] havoc eval_#t~ret2; [L501-L505] COND TRUE 0 != eval_~tmp~0 [L506] COND TRUE 0 == ~m_st~0 [L507] havoc eval_~tmp_ndt_1~0; [L508] eval_~tmp_ndt_1~0 := eval_#t~nondet3; [L508] havoc eval_#t~nondet3; [L509-L516] COND FALSE !(0 != eval_~tmp_ndt_1~0) [L520] COND TRUE 0 == ~t1_st~0 [L521] havoc eval_~tmp_ndt_2~0; [L522] eval_~tmp_ndt_2~0 := eval_#t~nondet4; [L522] havoc eval_#t~nondet4; [L523-L530] COND FALSE !(0 != eval_~tmp_ndt_2~0) [L534] COND TRUE 0 == ~t2_st~0 [L535] havoc eval_~tmp_ndt_3~0; [L536] eval_~tmp_ndt_3~0 := eval_#t~nondet5; [L536] havoc eval_#t~nondet5; [L537-L544] COND FALSE !(0 != eval_~tmp_ndt_3~0) [L548] COND TRUE 0 == ~t3_st~0 [L549] havoc eval_~tmp_ndt_4~0; [L550] eval_~tmp_ndt_4~0 := eval_#t~nondet6; [L550] havoc eval_#t~nondet6; [L551-L558] COND FALSE !(0 != eval_~tmp_ndt_4~0) [L562] COND TRUE 0 == ~t4_st~0 [L563] havoc eval_~tmp_ndt_5~0; [L564] eval_~tmp_ndt_5~0 := eval_#t~nondet7; [L564] havoc eval_#t~nondet7; [L565-L572] COND FALSE !(0 != eval_~tmp_ndt_5~0) [L576] COND TRUE 0 == ~t5_st~0 [L577] havoc eval_~tmp_ndt_6~0; [L578] eval_~tmp_ndt_6~0 := eval_#t~nondet8; [L578] havoc eval_#t~nondet8; [L579-L586] COND FALSE !(0 != eval_~tmp_ndt_6~0) ----- ----- class de.uni_freiburg.informatik.ultimate.boogie.procedureinliner.backtranslation.InlinerBacktranslator [L496-L590] COND FALSE !(false) [L499] havoc exists_runnable_thread_#res; [L499] havoc exists_runnable_thread_~__retres1~6; [L451] havoc exists_runnable_thread_~__retres1~6; [L454] COND TRUE 0 == ~m_st~0 [L455] exists_runnable_thread_~__retres1~6 := 1; [L487] exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; [L499] eval_#t~ret2 := exists_runnable_thread_#res; [L499] eval_~tmp~0 := eval_#t~ret2; [L499] havoc eval_#t~ret2; [L501-L505] COND TRUE 0 != eval_~tmp~0 [L506] COND TRUE 0 == ~m_st~0 [L507] havoc eval_~tmp_ndt_1~0; [L508] eval_~tmp_ndt_1~0 := eval_#t~nondet3; [L508] havoc eval_#t~nondet3; [L509-L516] COND FALSE !(0 != eval_~tmp_ndt_1~0) [L520] COND TRUE 0 == ~t1_st~0 [L521] havoc eval_~tmp_ndt_2~0; [L522] eval_~tmp_ndt_2~0 := eval_#t~nondet4; [L522] havoc eval_#t~nondet4; [L523-L530] COND FALSE !(0 != eval_~tmp_ndt_2~0) [L534] COND TRUE 0 == ~t2_st~0 [L535] havoc eval_~tmp_ndt_3~0; [L536] eval_~tmp_ndt_3~0 := eval_#t~nondet5; [L536] havoc eval_#t~nondet5; [L537-L544] COND FALSE !(0 != eval_~tmp_ndt_3~0) [L548] COND TRUE 0 == ~t3_st~0 [L549] havoc eval_~tmp_ndt_4~0; [L550] eval_~tmp_ndt_4~0 := eval_#t~nondet6; [L550] havoc eval_#t~nondet6; [L551-L558] COND FALSE !(0 != eval_~tmp_ndt_4~0) [L562] COND TRUE 0 == ~t4_st~0 [L563] havoc eval_~tmp_ndt_5~0; [L564] eval_~tmp_ndt_5~0 := eval_#t~nondet7; [L564] havoc eval_#t~nondet7; [L565-L572] COND FALSE !(0 != eval_~tmp_ndt_5~0) [L576] COND TRUE 0 == ~t5_st~0 [L577] havoc eval_~tmp_ndt_6~0; [L578] eval_~tmp_ndt_6~0 := eval_#t~nondet8; [L578] havoc eval_#t~nondet8; [L579-L586] COND FALSE !(0 != eval_~tmp_ndt_6~0) [L496-L590] COND FALSE !(false) [L451] havoc ~__retres1~6; [L454] COND TRUE 0 == ~m_st~0 [L455] ~__retres1~6 := 1; [L487] #res := ~__retres1~6; [L499] ~tmp~0 := #t~ret2; [L499] havoc #t~ret2; [L501-L505] COND TRUE 0 != ~tmp~0 [L506] COND TRUE 0 == ~m_st~0 [L507] havoc ~tmp_ndt_1~0; [L508] ~tmp_ndt_1~0 := #t~nondet3; [L508] havoc #t~nondet3; [L509-L516] COND FALSE !(0 != ~tmp_ndt_1~0) [L520] COND TRUE 0 == ~t1_st~0 [L521] havoc ~tmp_ndt_2~0; [L522] ~tmp_ndt_2~0 := #t~nondet4; [L522] havoc #t~nondet4; [L523-L530] COND FALSE !(0 != ~tmp_ndt_2~0) [L534] COND TRUE 0 == ~t2_st~0 [L535] havoc ~tmp_ndt_3~0; [L536] ~tmp_ndt_3~0 := #t~nondet5; [L536] havoc #t~nondet5; [L537-L544] COND FALSE !(0 != ~tmp_ndt_3~0) [L548] COND TRUE 0 == ~t3_st~0 [L549] havoc ~tmp_ndt_4~0; [L550] ~tmp_ndt_4~0 := #t~nondet6; [L550] havoc #t~nondet6; [L551-L558] COND FALSE !(0 != ~tmp_ndt_4~0) [L562] COND TRUE 0 == ~t4_st~0 [L563] havoc ~tmp_ndt_5~0; [L564] ~tmp_ndt_5~0 := #t~nondet7; [L564] havoc #t~nondet7; [L565-L572] COND FALSE !(0 != ~tmp_ndt_5~0) [L576] COND TRUE 0 == ~t5_st~0 [L577] havoc ~tmp_ndt_6~0; [L578] ~tmp_ndt_6~0 := #t~nondet8; [L578] havoc #t~nondet8; [L579-L586] COND FALSE !(0 != ~tmp_ndt_6~0) ----- ----- class de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.CACSL2BoogieBacktranslator [L496-L590] COND FALSE !(false) [L451] havoc ~__retres1~6; [L454] COND TRUE 0 == ~m_st~0 [L455] ~__retres1~6 := 1; [L487] #res := ~__retres1~6; [L499] ~tmp~0 := #t~ret2; [L499] havoc #t~ret2; [L501-L505] COND TRUE 0 != ~tmp~0 [L506] COND TRUE 0 == ~m_st~0 [L507] havoc ~tmp_ndt_1~0; [L508] ~tmp_ndt_1~0 := #t~nondet3; [L508] havoc #t~nondet3; [L509-L516] COND FALSE !(0 != ~tmp_ndt_1~0) [L520] COND TRUE 0 == ~t1_st~0 [L521] havoc ~tmp_ndt_2~0; [L522] ~tmp_ndt_2~0 := #t~nondet4; [L522] havoc #t~nondet4; [L523-L530] COND FALSE !(0 != ~tmp_ndt_2~0) [L534] COND TRUE 0 == ~t2_st~0 [L535] havoc ~tmp_ndt_3~0; [L536] ~tmp_ndt_3~0 := #t~nondet5; [L536] havoc #t~nondet5; [L537-L544] COND FALSE !(0 != ~tmp_ndt_3~0) [L548] COND TRUE 0 == ~t3_st~0 [L549] havoc ~tmp_ndt_4~0; [L550] ~tmp_ndt_4~0 := #t~nondet6; [L550] havoc #t~nondet6; [L551-L558] COND FALSE !(0 != ~tmp_ndt_4~0) [L562] COND TRUE 0 == ~t4_st~0 [L563] havoc ~tmp_ndt_5~0; [L564] ~tmp_ndt_5~0 := #t~nondet7; [L564] havoc #t~nondet7; [L565-L572] COND FALSE !(0 != ~tmp_ndt_5~0) [L576] COND TRUE 0 == ~t5_st~0 [L577] havoc ~tmp_ndt_6~0; [L578] ~tmp_ndt_6~0 := #t~nondet8; [L578] havoc #t~nondet8; [L579-L586] COND FALSE !(0 != ~tmp_ndt_6~0) [L496] COND TRUE 1 [L451] int __retres1 ; [L454] COND TRUE m_st == 0 [L455] __retres1 = 1 [L487] return (__retres1); [L499] tmp = exists_runnable_thread() [L501] COND TRUE \read(tmp) [L506] COND TRUE m_st == 0 [L507] int tmp_ndt_1; [L508] tmp_ndt_1 = __VERIFIER_nondet_int() [L509] COND FALSE !(\read(tmp_ndt_1)) [L520] COND TRUE t1_st == 0 [L521] int tmp_ndt_2; [L522] tmp_ndt_2 = __VERIFIER_nondet_int() [L523] COND FALSE !(\read(tmp_ndt_2)) [L534] COND TRUE t2_st == 0 [L535] int tmp_ndt_3; [L536] tmp_ndt_3 = __VERIFIER_nondet_int() [L537] COND FALSE !(\read(tmp_ndt_3)) [L548] COND TRUE t3_st == 0 [L549] int tmp_ndt_4; [L550] tmp_ndt_4 = __VERIFIER_nondet_int() [L551] COND FALSE !(\read(tmp_ndt_4)) [L562] COND TRUE t4_st == 0 [L563] int tmp_ndt_5; [L564] tmp_ndt_5 = __VERIFIER_nondet_int() [L565] COND FALSE !(\read(tmp_ndt_5)) [L576] COND TRUE t5_st == 0 [L577] int tmp_ndt_6; [L578] tmp_ndt_6 = __VERIFIER_nondet_int() [L579] COND FALSE !(\read(tmp_ndt_6)) ----- ----- class de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder.RCFGBacktranslator [?] ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; [?] havoc main_#res;havoc main_~__retres1~7;havoc main_~__retres1~7;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; [?] havoc start_simulation_#t~ret16, start_simulation_#t~ret17, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; [?] assume 1 == ~m_i~0;~m_st~0 := 0; [?] assume 1 == ~t1_i~0;~t1_st~0 := 0; [?] assume 1 == ~t2_i~0;~t2_st~0 := 0; [?] assume 1 == ~t3_i~0;~t3_st~0 := 0; [?] assume 1 == ~t4_i~0;~t4_st~0 := 0; [?] assume 1 == ~t5_i~0;~t5_st~0 := 0; [?] assume !(0 == ~M_E~0); [?] assume !(0 == ~T1_E~0); [?] assume !(0 == ~T2_E~0); [?] assume !(0 == ~T3_E~0); [?] assume !(0 == ~T4_E~0); [?] assume !(0 == ~T5_E~0); [?] assume !(0 == ~E_M~0); [?] assume !(0 == ~E_1~0); [?] assume !(0 == ~E_2~0); [?] assume !(0 == ~E_3~0); [?] assume !(0 == ~E_4~0); [?] assume !(0 == ~E_5~0); [?] havoc activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; [?] assume !(1 == ~m_pc~0); [?] is_master_triggered_~__retres1~0 := 0; [?] is_master_triggered_#res := is_master_triggered_~__retres1~0; [?] activate_threads_#t~ret9 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; [?] assume !(0 != activate_threads_~tmp~1); [?] havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; [?] assume !(1 == ~t1_pc~0); [?] is_transmit1_triggered_~__retres1~1 := 0; [?] is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; [?] activate_threads_#t~ret10 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; [?] assume !(0 != activate_threads_~tmp___0~0); [?] havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; [?] assume !(1 == ~t2_pc~0); [?] is_transmit2_triggered_~__retres1~2 := 0; [?] is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; [?] activate_threads_#t~ret11 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; [?] assume !(0 != activate_threads_~tmp___1~0); [?] havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; [?] assume !(1 == ~t3_pc~0); [?] is_transmit3_triggered_~__retres1~3 := 0; [?] is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; [?] activate_threads_#t~ret12 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; [?] assume !(0 != activate_threads_~tmp___2~0); [?] havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; [?] assume !(1 == ~t4_pc~0); [?] is_transmit4_triggered_~__retres1~4 := 0; [?] is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; [?] activate_threads_#t~ret13 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; [?] assume !(0 != activate_threads_~tmp___3~0); [?] havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; [?] assume !(1 == ~t5_pc~0); [?] is_transmit5_triggered_~__retres1~5 := 0; [?] is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; [?] activate_threads_#t~ret14 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; [?] assume !(0 != activate_threads_~tmp___4~0); [?] assume !(1 == ~M_E~0); [?] assume !(1 == ~T1_E~0); [?] assume !(1 == ~T2_E~0); [?] assume !(1 == ~T3_E~0); [?] assume !(1 == ~T4_E~0); [?] assume !(1 == ~T5_E~0); [?] assume !(1 == ~E_M~0); [?] assume !(1 == ~E_1~0); [?] assume !(1 == ~E_2~0); [?] assume !(1 == ~E_3~0); [?] assume !(1 == ~E_4~0); [?] assume !(1 == ~E_5~0); [?] assume !false; [?] start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret2, eval_#t~nondet3, eval_~tmp_ndt_1~0, eval_#t~nondet4, eval_~tmp_ndt_2~0, eval_#t~nondet5, eval_~tmp_ndt_3~0, eval_#t~nondet6, eval_~tmp_ndt_4~0, eval_#t~nondet7, eval_~tmp_ndt_5~0, eval_#t~nondet8, eval_~tmp_ndt_6~0, eval_~tmp~0;havoc eval_~tmp~0; [L14] ~m_pc~0 := 0; [L15] ~t1_pc~0 := 0; [L16] ~t2_pc~0 := 0; [L17] ~t3_pc~0 := 0; [L18] ~t4_pc~0 := 0; [L19] ~t5_pc~0 := 0; [L20] ~m_st~0 := 0; [L21] ~t1_st~0 := 0; [L22] ~t2_st~0 := 0; [L23] ~t3_st~0 := 0; [L24] ~t4_st~0 := 0; [L25] ~t5_st~0 := 0; [L26] ~m_i~0 := 0; [L27] ~t1_i~0 := 0; [L28] ~t2_i~0 := 0; [L29] ~t3_i~0 := 0; [L30] ~t4_i~0 := 0; [L31] ~t5_i~0 := 0; [L32] ~M_E~0 := 2; [L33] ~T1_E~0 := 2; [L34] ~T2_E~0 := 2; [L35] ~T3_E~0 := 2; [L36] ~T4_E~0 := 2; [L37] ~T5_E~0 := 2; [L38] ~E_M~0 := 2; [L39] ~E_1~0 := 2; [L40] ~E_2~0 := 2; [L41] ~E_3~0 := 2; [L42] ~E_4~0 := 2; [L43] ~E_5~0 := 2; [L51] ~token~0 := 0; [L53] ~local~0 := 0; [?] havoc main_#res; [?] havoc main_~__retres1~7; [L975] havoc main_~__retres1~7; [L886] ~m_i~0 := 1; [L887] ~t1_i~0 := 1; [L888] ~t2_i~0 := 1; [L889] ~t3_i~0 := 1; [L890] ~t4_i~0 := 1; [L891] ~t5_i~0 := 1; [L980] havoc start_simulation_#t~ret16, start_simulation_#t~ret17, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1; [L916] havoc start_simulation_~kernel_st~0; [L917] havoc start_simulation_~tmp~3; [L918] havoc start_simulation_~tmp___0~1; [L922] start_simulation_~kernel_st~0 := 0; [L416-L420] assume 1 == ~m_i~0; [L417] ~m_st~0 := 0; [L421-L425] assume 1 == ~t1_i~0; [L422] ~t1_st~0 := 0; [L426-L430] assume 1 == ~t2_i~0; [L427] ~t2_st~0 := 0; [L431-L435] assume 1 == ~t3_i~0; [L432] ~t3_st~0 := 0; [L436-L440] assume 1 == ~t4_i~0; [L437] ~t4_st~0 := 0; [L441-L445] assume 1 == ~t5_i~0; [L442] ~t5_st~0 := 0; [L601-L605] assume !(0 == ~M_E~0); [L606-L610] assume !(0 == ~T1_E~0); [L611-L615] assume !(0 == ~T2_E~0); [L616-L620] assume !(0 == ~T3_E~0); [L621-L625] assume !(0 == ~T4_E~0); [L626-L630] assume !(0 == ~T5_E~0); [L631-L635] assume !(0 == ~E_M~0); [L636-L640] assume !(0 == ~E_1~0); [L641-L645] assume !(0 == ~E_2~0); [L646-L650] assume !(0 == ~E_3~0); [L651-L655] assume !(0 == ~E_4~0); [L656-L660] assume !(0 == ~E_5~0); [L926] havoc activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0; [L734] havoc activate_threads_~tmp~1; [L735] havoc activate_threads_~tmp___0~0; [L736] havoc activate_threads_~tmp___1~0; [L737] havoc activate_threads_~tmp___2~0; [L738] havoc activate_threads_~tmp___3~0; [L739] havoc activate_threads_~tmp___4~0; [L743] havoc is_master_triggered_#res; [L743] havoc is_master_triggered_~__retres1~0; [L291] havoc is_master_triggered_~__retres1~0; [L294-L303] assume !(1 == ~m_pc~0); [L304] is_master_triggered_~__retres1~0 := 0; [L306] is_master_triggered_#res := is_master_triggered_~__retres1~0; [L743] activate_threads_#t~ret9 := is_master_triggered_#res; [L743] activate_threads_~tmp~1 := activate_threads_#t~ret9; [L743] havoc activate_threads_#t~ret9; [L745-L749] assume !(0 != activate_threads_~tmp~1); [L751] havoc is_transmit1_triggered_#res; [L751] havoc is_transmit1_triggered_~__retres1~1; [L310] havoc is_transmit1_triggered_~__retres1~1; [L313-L322] assume !(1 == ~t1_pc~0); [L323] is_transmit1_triggered_~__retres1~1 := 0; [L325] is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; [L751] activate_threads_#t~ret10 := is_transmit1_triggered_#res; [L751] activate_threads_~tmp___0~0 := activate_threads_#t~ret10; [L751] havoc activate_threads_#t~ret10; [L753-L757] assume !(0 != activate_threads_~tmp___0~0); [L759] havoc is_transmit2_triggered_#res; [L759] havoc is_transmit2_triggered_~__retres1~2; [L329] havoc is_transmit2_triggered_~__retres1~2; [L332-L341] assume !(1 == ~t2_pc~0); [L342] is_transmit2_triggered_~__retres1~2 := 0; [L344] is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; [L759] activate_threads_#t~ret11 := is_transmit2_triggered_#res; [L759] activate_threads_~tmp___1~0 := activate_threads_#t~ret11; [L759] havoc activate_threads_#t~ret11; [L761-L765] assume !(0 != activate_threads_~tmp___1~0); [L767] havoc is_transmit3_triggered_#res; [L767] havoc is_transmit3_triggered_~__retres1~3; [L348] havoc is_transmit3_triggered_~__retres1~3; [L351-L360] assume !(1 == ~t3_pc~0); [L361] is_transmit3_triggered_~__retres1~3 := 0; [L363] is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; [L767] activate_threads_#t~ret12 := is_transmit3_triggered_#res; [L767] activate_threads_~tmp___2~0 := activate_threads_#t~ret12; [L767] havoc activate_threads_#t~ret12; [L769-L773] assume !(0 != activate_threads_~tmp___2~0); [L775] havoc is_transmit4_triggered_#res; [L775] havoc is_transmit4_triggered_~__retres1~4; [L367] havoc is_transmit4_triggered_~__retres1~4; [L370-L379] assume !(1 == ~t4_pc~0); [L380] is_transmit4_triggered_~__retres1~4 := 0; [L382] is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; [L775] activate_threads_#t~ret13 := is_transmit4_triggered_#res; [L775] activate_threads_~tmp___3~0 := activate_threads_#t~ret13; [L775] havoc activate_threads_#t~ret13; [L777-L781] assume !(0 != activate_threads_~tmp___3~0); [L783] havoc is_transmit5_triggered_#res; [L783] havoc is_transmit5_triggered_~__retres1~5; [L386] havoc is_transmit5_triggered_~__retres1~5; [L389-L398] assume !(1 == ~t5_pc~0); [L399] is_transmit5_triggered_~__retres1~5 := 0; [L401] is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; [L783] activate_threads_#t~ret14 := is_transmit5_triggered_#res; [L783] activate_threads_~tmp___4~0 := activate_threads_#t~ret14; [L783] havoc activate_threads_#t~ret14; [L785-L789] assume !(0 != activate_threads_~tmp___4~0); [L669-L673] assume !(1 == ~M_E~0); [L674-L678] assume !(1 == ~T1_E~0); [L679-L683] assume !(1 == ~T2_E~0); [L684-L688] assume !(1 == ~T3_E~0); [L689-L693] assume !(1 == ~T4_E~0); [L694-L698] assume !(1 == ~T5_E~0); [L699-L703] assume !(1 == ~E_M~0); [L704-L708] assume !(1 == ~E_1~0); [L709-L713] assume !(1 == ~E_2~0); [L714-L718] assume !(1 == ~E_3~0); [L719-L723] assume !(1 == ~E_4~0); [L724-L728] assume !(1 == ~E_5~0); [L930-L967] assume !false; [L933] start_simulation_~kernel_st~0 := 1; [L934] havoc eval_#t~ret2, eval_#t~nondet3, eval_~tmp_ndt_1~0, eval_#t~nondet4, eval_~tmp_ndt_2~0, eval_#t~nondet5, eval_~tmp_ndt_3~0, eval_#t~nondet6, eval_~tmp_ndt_4~0, eval_#t~nondet7, eval_~tmp_ndt_5~0, eval_#t~nondet8, eval_~tmp_ndt_6~0, eval_~tmp~0; [L492] havoc eval_~tmp~0; ----- ----- class de.uni_freiburg.informatik.ultimate.boogie.preprocessor.BoogiePreprocessorBacktranslator [L14] ~m_pc~0 := 0; [L15] ~t1_pc~0 := 0; [L16] ~t2_pc~0 := 0; [L17] ~t3_pc~0 := 0; [L18] ~t4_pc~0 := 0; [L19] ~t5_pc~0 := 0; [L20] ~m_st~0 := 0; [L21] ~t1_st~0 := 0; [L22] ~t2_st~0 := 0; [L23] ~t3_st~0 := 0; [L24] ~t4_st~0 := 0; [L25] ~t5_st~0 := 0; [L26] ~m_i~0 := 0; [L27] ~t1_i~0 := 0; [L28] ~t2_i~0 := 0; [L29] ~t3_i~0 := 0; [L30] ~t4_i~0 := 0; [L31] ~t5_i~0 := 0; [L32] ~M_E~0 := 2; [L33] ~T1_E~0 := 2; [L34] ~T2_E~0 := 2; [L35] ~T3_E~0 := 2; [L36] ~T4_E~0 := 2; [L37] ~T5_E~0 := 2; [L38] ~E_M~0 := 2; [L39] ~E_1~0 := 2; [L40] ~E_2~0 := 2; [L41] ~E_3~0 := 2; [L42] ~E_4~0 := 2; [L43] ~E_5~0 := 2; [L51] ~token~0 := 0; [L53] ~local~0 := 0; [?] havoc main_#res; [?] havoc main_~__retres1~7; [L975] havoc main_~__retres1~7; [L886] ~m_i~0 := 1; [L887] ~t1_i~0 := 1; [L888] ~t2_i~0 := 1; [L889] ~t3_i~0 := 1; [L890] ~t4_i~0 := 1; [L891] ~t5_i~0 := 1; [L980] havoc start_simulation_#t~ret16, start_simulation_#t~ret17, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1; [L916] havoc start_simulation_~kernel_st~0; [L917] havoc start_simulation_~tmp~3; [L918] havoc start_simulation_~tmp___0~1; [L922] start_simulation_~kernel_st~0 := 0; [L416-L420] assume 1 == ~m_i~0; [L417] ~m_st~0 := 0; [L421-L425] assume 1 == ~t1_i~0; [L422] ~t1_st~0 := 0; [L426-L430] assume 1 == ~t2_i~0; [L427] ~t2_st~0 := 0; [L431-L435] assume 1 == ~t3_i~0; [L432] ~t3_st~0 := 0; [L436-L440] assume 1 == ~t4_i~0; [L437] ~t4_st~0 := 0; [L441-L445] assume 1 == ~t5_i~0; [L442] ~t5_st~0 := 0; [L601-L605] assume !(0 == ~M_E~0); [L606-L610] assume !(0 == ~T1_E~0); [L611-L615] assume !(0 == ~T2_E~0); [L616-L620] assume !(0 == ~T3_E~0); [L621-L625] assume !(0 == ~T4_E~0); [L626-L630] assume !(0 == ~T5_E~0); [L631-L635] assume !(0 == ~E_M~0); [L636-L640] assume !(0 == ~E_1~0); [L641-L645] assume !(0 == ~E_2~0); [L646-L650] assume !(0 == ~E_3~0); [L651-L655] assume !(0 == ~E_4~0); [L656-L660] assume !(0 == ~E_5~0); [L926] havoc activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0; [L734] havoc activate_threads_~tmp~1; [L735] havoc activate_threads_~tmp___0~0; [L736] havoc activate_threads_~tmp___1~0; [L737] havoc activate_threads_~tmp___2~0; [L738] havoc activate_threads_~tmp___3~0; [L739] havoc activate_threads_~tmp___4~0; [L743] havoc is_master_triggered_#res; [L743] havoc is_master_triggered_~__retres1~0; [L291] havoc is_master_triggered_~__retres1~0; [L294-L303] assume !(1 == ~m_pc~0); [L304] is_master_triggered_~__retres1~0 := 0; [L306] is_master_triggered_#res := is_master_triggered_~__retres1~0; [L743] activate_threads_#t~ret9 := is_master_triggered_#res; [L743] activate_threads_~tmp~1 := activate_threads_#t~ret9; [L743] havoc activate_threads_#t~ret9; [L745-L749] assume !(0 != activate_threads_~tmp~1); [L751] havoc is_transmit1_triggered_#res; [L751] havoc is_transmit1_triggered_~__retres1~1; [L310] havoc is_transmit1_triggered_~__retres1~1; [L313-L322] assume !(1 == ~t1_pc~0); [L323] is_transmit1_triggered_~__retres1~1 := 0; [L325] is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; [L751] activate_threads_#t~ret10 := is_transmit1_triggered_#res; [L751] activate_threads_~tmp___0~0 := activate_threads_#t~ret10; [L751] havoc activate_threads_#t~ret10; [L753-L757] assume !(0 != activate_threads_~tmp___0~0); [L759] havoc is_transmit2_triggered_#res; [L759] havoc is_transmit2_triggered_~__retres1~2; [L329] havoc is_transmit2_triggered_~__retres1~2; [L332-L341] assume !(1 == ~t2_pc~0); [L342] is_transmit2_triggered_~__retres1~2 := 0; [L344] is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; [L759] activate_threads_#t~ret11 := is_transmit2_triggered_#res; [L759] activate_threads_~tmp___1~0 := activate_threads_#t~ret11; [L759] havoc activate_threads_#t~ret11; [L761-L765] assume !(0 != activate_threads_~tmp___1~0); [L767] havoc is_transmit3_triggered_#res; [L767] havoc is_transmit3_triggered_~__retres1~3; [L348] havoc is_transmit3_triggered_~__retres1~3; [L351-L360] assume !(1 == ~t3_pc~0); [L361] is_transmit3_triggered_~__retres1~3 := 0; [L363] is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; [L767] activate_threads_#t~ret12 := is_transmit3_triggered_#res; [L767] activate_threads_~tmp___2~0 := activate_threads_#t~ret12; [L767] havoc activate_threads_#t~ret12; [L769-L773] assume !(0 != activate_threads_~tmp___2~0); [L775] havoc is_transmit4_triggered_#res; [L775] havoc is_transmit4_triggered_~__retres1~4; [L367] havoc is_transmit4_triggered_~__retres1~4; [L370-L379] assume !(1 == ~t4_pc~0); [L380] is_transmit4_triggered_~__retres1~4 := 0; [L382] is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; [L775] activate_threads_#t~ret13 := is_transmit4_triggered_#res; [L775] activate_threads_~tmp___3~0 := activate_threads_#t~ret13; [L775] havoc activate_threads_#t~ret13; [L777-L781] assume !(0 != activate_threads_~tmp___3~0); [L783] havoc is_transmit5_triggered_#res; [L783] havoc is_transmit5_triggered_~__retres1~5; [L386] havoc is_transmit5_triggered_~__retres1~5; [L389-L398] assume !(1 == ~t5_pc~0); [L399] is_transmit5_triggered_~__retres1~5 := 0; [L401] is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; [L783] activate_threads_#t~ret14 := is_transmit5_triggered_#res; [L783] activate_threads_~tmp___4~0 := activate_threads_#t~ret14; [L783] havoc activate_threads_#t~ret14; [L785-L789] assume !(0 != activate_threads_~tmp___4~0); [L669-L673] assume !(1 == ~M_E~0); [L674-L678] assume !(1 == ~T1_E~0); [L679-L683] assume !(1 == ~T2_E~0); [L684-L688] assume !(1 == ~T3_E~0); [L689-L693] assume !(1 == ~T4_E~0); [L694-L698] assume !(1 == ~T5_E~0); [L699-L703] assume !(1 == ~E_M~0); [L704-L708] assume !(1 == ~E_1~0); [L709-L713] assume !(1 == ~E_2~0); [L714-L718] assume !(1 == ~E_3~0); [L719-L723] assume !(1 == ~E_4~0); [L724-L728] assume !(1 == ~E_5~0); [L930-L967] assume !false; [L933] start_simulation_~kernel_st~0 := 1; [L934] havoc eval_#t~ret2, eval_#t~nondet3, eval_~tmp_ndt_1~0, eval_#t~nondet4, eval_~tmp_ndt_2~0, eval_#t~nondet5, eval_~tmp_ndt_3~0, eval_#t~nondet6, eval_~tmp_ndt_4~0, eval_#t~nondet7, eval_~tmp_ndt_5~0, eval_#t~nondet8, eval_~tmp_ndt_6~0, eval_~tmp~0; [L492] havoc eval_~tmp~0; [L14] ~m_pc~0 := 0; [L15] ~t1_pc~0 := 0; [L16] ~t2_pc~0 := 0; [L17] ~t3_pc~0 := 0; [L18] ~t4_pc~0 := 0; [L19] ~t5_pc~0 := 0; [L20] ~m_st~0 := 0; [L21] ~t1_st~0 := 0; [L22] ~t2_st~0 := 0; [L23] ~t3_st~0 := 0; [L24] ~t4_st~0 := 0; [L25] ~t5_st~0 := 0; [L26] ~m_i~0 := 0; [L27] ~t1_i~0 := 0; [L28] ~t2_i~0 := 0; [L29] ~t3_i~0 := 0; [L30] ~t4_i~0 := 0; [L31] ~t5_i~0 := 0; [L32] ~M_E~0 := 2; [L33] ~T1_E~0 := 2; [L34] ~T2_E~0 := 2; [L35] ~T3_E~0 := 2; [L36] ~T4_E~0 := 2; [L37] ~T5_E~0 := 2; [L38] ~E_M~0 := 2; [L39] ~E_1~0 := 2; [L40] ~E_2~0 := 2; [L41] ~E_3~0 := 2; [L42] ~E_4~0 := 2; [L43] ~E_5~0 := 2; [L51] ~token~0 := 0; [L53] ~local~0 := 0; [?] havoc main_#res; [?] havoc main_~__retres1~7; [L975] havoc main_~__retres1~7; [L886] ~m_i~0 := 1; [L887] ~t1_i~0 := 1; [L888] ~t2_i~0 := 1; [L889] ~t3_i~0 := 1; [L890] ~t4_i~0 := 1; [L891] ~t5_i~0 := 1; [L980] havoc start_simulation_#t~ret16, start_simulation_#t~ret17, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1; [L916] havoc start_simulation_~kernel_st~0; [L917] havoc start_simulation_~tmp~3; [L918] havoc start_simulation_~tmp___0~1; [L922] start_simulation_~kernel_st~0 := 0; [L416] COND TRUE 1 == ~m_i~0 [L417] ~m_st~0 := 0; [L421] COND TRUE 1 == ~t1_i~0 [L422] ~t1_st~0 := 0; [L426] COND TRUE 1 == ~t2_i~0 [L427] ~t2_st~0 := 0; [L431] COND TRUE 1 == ~t3_i~0 [L432] ~t3_st~0 := 0; [L436] COND TRUE 1 == ~t4_i~0 [L437] ~t4_st~0 := 0; [L441] COND TRUE 1 == ~t5_i~0 [L442] ~t5_st~0 := 0; [L601] COND FALSE !(0 == ~M_E~0) [L606] COND FALSE !(0 == ~T1_E~0) [L611] COND FALSE !(0 == ~T2_E~0) [L616] COND FALSE !(0 == ~T3_E~0) [L621] COND FALSE !(0 == ~T4_E~0) [L626] COND FALSE !(0 == ~T5_E~0) [L631] COND FALSE !(0 == ~E_M~0) [L636] COND FALSE !(0 == ~E_1~0) [L641] COND FALSE !(0 == ~E_2~0) [L646] COND FALSE !(0 == ~E_3~0) [L651] COND FALSE !(0 == ~E_4~0) [L656] COND FALSE !(0 == ~E_5~0) [L926] havoc activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0; [L734] havoc activate_threads_~tmp~1; [L735] havoc activate_threads_~tmp___0~0; [L736] havoc activate_threads_~tmp___1~0; [L737] havoc activate_threads_~tmp___2~0; [L738] havoc activate_threads_~tmp___3~0; [L739] havoc activate_threads_~tmp___4~0; [L743] havoc is_master_triggered_#res; [L743] havoc is_master_triggered_~__retres1~0; [L291] havoc is_master_triggered_~__retres1~0; [L294] COND FALSE !(1 == ~m_pc~0) [L304] is_master_triggered_~__retres1~0 := 0; [L306] is_master_triggered_#res := is_master_triggered_~__retres1~0; [L743] activate_threads_#t~ret9 := is_master_triggered_#res; [L743] activate_threads_~tmp~1 := activate_threads_#t~ret9; [L743] havoc activate_threads_#t~ret9; [L745-L749] COND FALSE !(0 != activate_threads_~tmp~1) [L751] havoc is_transmit1_triggered_#res; [L751] havoc is_transmit1_triggered_~__retres1~1; [L310] havoc is_transmit1_triggered_~__retres1~1; [L313] COND FALSE !(1 == ~t1_pc~0) [L323] is_transmit1_triggered_~__retres1~1 := 0; [L325] is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; [L751] activate_threads_#t~ret10 := is_transmit1_triggered_#res; [L751] activate_threads_~tmp___0~0 := activate_threads_#t~ret10; [L751] havoc activate_threads_#t~ret10; [L753-L757] COND FALSE !(0 != activate_threads_~tmp___0~0) [L759] havoc is_transmit2_triggered_#res; [L759] havoc is_transmit2_triggered_~__retres1~2; [L329] havoc is_transmit2_triggered_~__retres1~2; [L332] COND FALSE !(1 == ~t2_pc~0) [L342] is_transmit2_triggered_~__retres1~2 := 0; [L344] is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; [L759] activate_threads_#t~ret11 := is_transmit2_triggered_#res; [L759] activate_threads_~tmp___1~0 := activate_threads_#t~ret11; [L759] havoc activate_threads_#t~ret11; [L761-L765] COND FALSE !(0 != activate_threads_~tmp___1~0) [L767] havoc is_transmit3_triggered_#res; [L767] havoc is_transmit3_triggered_~__retres1~3; [L348] havoc is_transmit3_triggered_~__retres1~3; [L351] COND FALSE !(1 == ~t3_pc~0) [L361] is_transmit3_triggered_~__retres1~3 := 0; [L363] is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; [L767] activate_threads_#t~ret12 := is_transmit3_triggered_#res; [L767] activate_threads_~tmp___2~0 := activate_threads_#t~ret12; [L767] havoc activate_threads_#t~ret12; [L769-L773] COND FALSE !(0 != activate_threads_~tmp___2~0) [L775] havoc is_transmit4_triggered_#res; [L775] havoc is_transmit4_triggered_~__retres1~4; [L367] havoc is_transmit4_triggered_~__retres1~4; [L370] COND FALSE !(1 == ~t4_pc~0) [L380] is_transmit4_triggered_~__retres1~4 := 0; [L382] is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; [L775] activate_threads_#t~ret13 := is_transmit4_triggered_#res; [L775] activate_threads_~tmp___3~0 := activate_threads_#t~ret13; [L775] havoc activate_threads_#t~ret13; [L777-L781] COND FALSE !(0 != activate_threads_~tmp___3~0) [L783] havoc is_transmit5_triggered_#res; [L783] havoc is_transmit5_triggered_~__retres1~5; [L386] havoc is_transmit5_triggered_~__retres1~5; [L389] COND FALSE !(1 == ~t5_pc~0) [L399] is_transmit5_triggered_~__retres1~5 := 0; [L401] is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; [L783] activate_threads_#t~ret14 := is_transmit5_triggered_#res; [L783] activate_threads_~tmp___4~0 := activate_threads_#t~ret14; [L783] havoc activate_threads_#t~ret14; [L785-L789] COND FALSE !(0 != activate_threads_~tmp___4~0) [L669] COND FALSE !(1 == ~M_E~0) [L674] COND FALSE !(1 == ~T1_E~0) [L679] COND FALSE !(1 == ~T2_E~0) [L684] COND FALSE !(1 == ~T3_E~0) [L689] COND FALSE !(1 == ~T4_E~0) [L694] COND FALSE !(1 == ~T5_E~0) [L699] COND FALSE !(1 == ~E_M~0) [L704] COND FALSE !(1 == ~E_1~0) [L709] COND FALSE !(1 == ~E_2~0) [L714] COND FALSE !(1 == ~E_3~0) [L719] COND FALSE !(1 == ~E_4~0) [L724] COND FALSE !(1 == ~E_5~0) [L930-L967] COND FALSE !(false) [L933] start_simulation_~kernel_st~0 := 1; [L934] havoc eval_#t~ret2, eval_#t~nondet3, eval_~tmp_ndt_1~0, eval_#t~nondet4, eval_~tmp_ndt_2~0, eval_#t~nondet5, eval_~tmp_ndt_3~0, eval_#t~nondet6, eval_~tmp_ndt_4~0, eval_#t~nondet7, eval_~tmp_ndt_5~0, eval_#t~nondet8, eval_~tmp_ndt_6~0, eval_~tmp~0; [L492] havoc eval_~tmp~0; ----- ----- class de.uni_freiburg.informatik.ultimate.boogie.procedureinliner.backtranslation.InlinerBacktranslator [L14] ~m_pc~0 := 0; [L15] ~t1_pc~0 := 0; [L16] ~t2_pc~0 := 0; [L17] ~t3_pc~0 := 0; [L18] ~t4_pc~0 := 0; [L19] ~t5_pc~0 := 0; [L20] ~m_st~0 := 0; [L21] ~t1_st~0 := 0; [L22] ~t2_st~0 := 0; [L23] ~t3_st~0 := 0; [L24] ~t4_st~0 := 0; [L25] ~t5_st~0 := 0; [L26] ~m_i~0 := 0; [L27] ~t1_i~0 := 0; [L28] ~t2_i~0 := 0; [L29] ~t3_i~0 := 0; [L30] ~t4_i~0 := 0; [L31] ~t5_i~0 := 0; [L32] ~M_E~0 := 2; [L33] ~T1_E~0 := 2; [L34] ~T2_E~0 := 2; [L35] ~T3_E~0 := 2; [L36] ~T4_E~0 := 2; [L37] ~T5_E~0 := 2; [L38] ~E_M~0 := 2; [L39] ~E_1~0 := 2; [L40] ~E_2~0 := 2; [L41] ~E_3~0 := 2; [L42] ~E_4~0 := 2; [L43] ~E_5~0 := 2; [L51] ~token~0 := 0; [L53] ~local~0 := 0; [?] havoc main_#res; [?] havoc main_~__retres1~7; [L975] havoc main_~__retres1~7; [L886] ~m_i~0 := 1; [L887] ~t1_i~0 := 1; [L888] ~t2_i~0 := 1; [L889] ~t3_i~0 := 1; [L890] ~t4_i~0 := 1; [L891] ~t5_i~0 := 1; [L980] havoc start_simulation_#t~ret16, start_simulation_#t~ret17, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1; [L916] havoc start_simulation_~kernel_st~0; [L917] havoc start_simulation_~tmp~3; [L918] havoc start_simulation_~tmp___0~1; [L922] start_simulation_~kernel_st~0 := 0; [L416] COND TRUE 1 == ~m_i~0 [L417] ~m_st~0 := 0; [L421] COND TRUE 1 == ~t1_i~0 [L422] ~t1_st~0 := 0; [L426] COND TRUE 1 == ~t2_i~0 [L427] ~t2_st~0 := 0; [L431] COND TRUE 1 == ~t3_i~0 [L432] ~t3_st~0 := 0; [L436] COND TRUE 1 == ~t4_i~0 [L437] ~t4_st~0 := 0; [L441] COND TRUE 1 == ~t5_i~0 [L442] ~t5_st~0 := 0; [L601] COND FALSE !(0 == ~M_E~0) [L606] COND FALSE !(0 == ~T1_E~0) [L611] COND FALSE !(0 == ~T2_E~0) [L616] COND FALSE !(0 == ~T3_E~0) [L621] COND FALSE !(0 == ~T4_E~0) [L626] COND FALSE !(0 == ~T5_E~0) [L631] COND FALSE !(0 == ~E_M~0) [L636] COND FALSE !(0 == ~E_1~0) [L641] COND FALSE !(0 == ~E_2~0) [L646] COND FALSE !(0 == ~E_3~0) [L651] COND FALSE !(0 == ~E_4~0) [L656] COND FALSE !(0 == ~E_5~0) [L926] havoc activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0; [L734] havoc activate_threads_~tmp~1; [L735] havoc activate_threads_~tmp___0~0; [L736] havoc activate_threads_~tmp___1~0; [L737] havoc activate_threads_~tmp___2~0; [L738] havoc activate_threads_~tmp___3~0; [L739] havoc activate_threads_~tmp___4~0; [L743] havoc is_master_triggered_#res; [L743] havoc is_master_triggered_~__retres1~0; [L291] havoc is_master_triggered_~__retres1~0; [L294] COND FALSE !(1 == ~m_pc~0) [L304] is_master_triggered_~__retres1~0 := 0; [L306] is_master_triggered_#res := is_master_triggered_~__retres1~0; [L743] activate_threads_#t~ret9 := is_master_triggered_#res; [L743] activate_threads_~tmp~1 := activate_threads_#t~ret9; [L743] havoc activate_threads_#t~ret9; [L745-L749] COND FALSE !(0 != activate_threads_~tmp~1) [L751] havoc is_transmit1_triggered_#res; [L751] havoc is_transmit1_triggered_~__retres1~1; [L310] havoc is_transmit1_triggered_~__retres1~1; [L313] COND FALSE !(1 == ~t1_pc~0) [L323] is_transmit1_triggered_~__retres1~1 := 0; [L325] is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; [L751] activate_threads_#t~ret10 := is_transmit1_triggered_#res; [L751] activate_threads_~tmp___0~0 := activate_threads_#t~ret10; [L751] havoc activate_threads_#t~ret10; [L753-L757] COND FALSE !(0 != activate_threads_~tmp___0~0) [L759] havoc is_transmit2_triggered_#res; [L759] havoc is_transmit2_triggered_~__retres1~2; [L329] havoc is_transmit2_triggered_~__retres1~2; [L332] COND FALSE !(1 == ~t2_pc~0) [L342] is_transmit2_triggered_~__retres1~2 := 0; [L344] is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; [L759] activate_threads_#t~ret11 := is_transmit2_triggered_#res; [L759] activate_threads_~tmp___1~0 := activate_threads_#t~ret11; [L759] havoc activate_threads_#t~ret11; [L761-L765] COND FALSE !(0 != activate_threads_~tmp___1~0) [L767] havoc is_transmit3_triggered_#res; [L767] havoc is_transmit3_triggered_~__retres1~3; [L348] havoc is_transmit3_triggered_~__retres1~3; [L351] COND FALSE !(1 == ~t3_pc~0) [L361] is_transmit3_triggered_~__retres1~3 := 0; [L363] is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; [L767] activate_threads_#t~ret12 := is_transmit3_triggered_#res; [L767] activate_threads_~tmp___2~0 := activate_threads_#t~ret12; [L767] havoc activate_threads_#t~ret12; [L769-L773] COND FALSE !(0 != activate_threads_~tmp___2~0) [L775] havoc is_transmit4_triggered_#res; [L775] havoc is_transmit4_triggered_~__retres1~4; [L367] havoc is_transmit4_triggered_~__retres1~4; [L370] COND FALSE !(1 == ~t4_pc~0) [L380] is_transmit4_triggered_~__retres1~4 := 0; [L382] is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; [L775] activate_threads_#t~ret13 := is_transmit4_triggered_#res; [L775] activate_threads_~tmp___3~0 := activate_threads_#t~ret13; [L775] havoc activate_threads_#t~ret13; [L777-L781] COND FALSE !(0 != activate_threads_~tmp___3~0) [L783] havoc is_transmit5_triggered_#res; [L783] havoc is_transmit5_triggered_~__retres1~5; [L386] havoc is_transmit5_triggered_~__retres1~5; [L389] COND FALSE !(1 == ~t5_pc~0) [L399] is_transmit5_triggered_~__retres1~5 := 0; [L401] is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; [L783] activate_threads_#t~ret14 := is_transmit5_triggered_#res; [L783] activate_threads_~tmp___4~0 := activate_threads_#t~ret14; [L783] havoc activate_threads_#t~ret14; [L785-L789] COND FALSE !(0 != activate_threads_~tmp___4~0) [L669] COND FALSE !(1 == ~M_E~0) [L674] COND FALSE !(1 == ~T1_E~0) [L679] COND FALSE !(1 == ~T2_E~0) [L684] COND FALSE !(1 == ~T3_E~0) [L689] COND FALSE !(1 == ~T4_E~0) [L694] COND FALSE !(1 == ~T5_E~0) [L699] COND FALSE !(1 == ~E_M~0) [L704] COND FALSE !(1 == ~E_1~0) [L709] COND FALSE !(1 == ~E_2~0) [L714] COND FALSE !(1 == ~E_3~0) [L719] COND FALSE !(1 == ~E_4~0) [L724] COND FALSE !(1 == ~E_5~0) [L930-L967] COND FALSE !(false) [L933] start_simulation_~kernel_st~0 := 1; [L934] havoc eval_#t~ret2, eval_#t~nondet3, eval_~tmp_ndt_1~0, eval_#t~nondet4, eval_~tmp_ndt_2~0, eval_#t~nondet5, eval_~tmp_ndt_3~0, eval_#t~nondet6, eval_~tmp_ndt_4~0, eval_#t~nondet7, eval_~tmp_ndt_5~0, eval_#t~nondet8, eval_~tmp_ndt_6~0, eval_~tmp~0; [L492] havoc eval_~tmp~0; [L14] ~m_pc~0 := 0; [L15] ~t1_pc~0 := 0; [L16] ~t2_pc~0 := 0; [L17] ~t3_pc~0 := 0; [L18] ~t4_pc~0 := 0; [L19] ~t5_pc~0 := 0; [L20] ~m_st~0 := 0; [L21] ~t1_st~0 := 0; [L22] ~t2_st~0 := 0; [L23] ~t3_st~0 := 0; [L24] ~t4_st~0 := 0; [L25] ~t5_st~0 := 0; [L26] ~m_i~0 := 0; [L27] ~t1_i~0 := 0; [L28] ~t2_i~0 := 0; [L29] ~t3_i~0 := 0; [L30] ~t4_i~0 := 0; [L31] ~t5_i~0 := 0; [L32] ~M_E~0 := 2; [L33] ~T1_E~0 := 2; [L34] ~T2_E~0 := 2; [L35] ~T3_E~0 := 2; [L36] ~T4_E~0 := 2; [L37] ~T5_E~0 := 2; [L38] ~E_M~0 := 2; [L39] ~E_1~0 := 2; [L40] ~E_2~0 := 2; [L41] ~E_3~0 := 2; [L42] ~E_4~0 := 2; [L43] ~E_5~0 := 2; [L51] ~token~0 := 0; [L53] ~local~0 := 0; [L975] havoc ~__retres1~7; [L886] ~m_i~0 := 1; [L887] ~t1_i~0 := 1; [L888] ~t2_i~0 := 1; [L889] ~t3_i~0 := 1; [L890] ~t4_i~0 := 1; [L891] ~t5_i~0 := 1; [L916] havoc ~kernel_st~0; [L917] havoc ~tmp~3; [L918] havoc ~tmp___0~1; [L922] ~kernel_st~0 := 0; [L416] COND TRUE 1 == ~m_i~0 [L417] ~m_st~0 := 0; [L421] COND TRUE 1 == ~t1_i~0 [L422] ~t1_st~0 := 0; [L426] COND TRUE 1 == ~t2_i~0 [L427] ~t2_st~0 := 0; [L431] COND TRUE 1 == ~t3_i~0 [L432] ~t3_st~0 := 0; [L436] COND TRUE 1 == ~t4_i~0 [L437] ~t4_st~0 := 0; [L441] COND TRUE 1 == ~t5_i~0 [L442] ~t5_st~0 := 0; [L601] COND FALSE !(0 == ~M_E~0) [L606] COND FALSE !(0 == ~T1_E~0) [L611] COND FALSE !(0 == ~T2_E~0) [L616] COND FALSE !(0 == ~T3_E~0) [L621] COND FALSE !(0 == ~T4_E~0) [L626] COND FALSE !(0 == ~T5_E~0) [L631] COND FALSE !(0 == ~E_M~0) [L636] COND FALSE !(0 == ~E_1~0) [L641] COND FALSE !(0 == ~E_2~0) [L646] COND FALSE !(0 == ~E_3~0) [L651] COND FALSE !(0 == ~E_4~0) [L656] COND FALSE !(0 == ~E_5~0) [L734] havoc ~tmp~1; [L735] havoc ~tmp___0~0; [L736] havoc ~tmp___1~0; [L737] havoc ~tmp___2~0; [L738] havoc ~tmp___3~0; [L739] havoc ~tmp___4~0; [L291] havoc ~__retres1~0; [L294] COND FALSE !(1 == ~m_pc~0) [L304] ~__retres1~0 := 0; [L306] #res := ~__retres1~0; [L743] ~tmp~1 := #t~ret9; [L743] havoc #t~ret9; [L745-L749] COND FALSE !(0 != ~tmp~1) [L310] havoc ~__retres1~1; [L313] COND FALSE !(1 == ~t1_pc~0) [L323] ~__retres1~1 := 0; [L325] #res := ~__retres1~1; [L751] ~tmp___0~0 := #t~ret10; [L751] havoc #t~ret10; [L753-L757] COND FALSE !(0 != ~tmp___0~0) [L329] havoc ~__retres1~2; [L332] COND FALSE !(1 == ~t2_pc~0) [L342] ~__retres1~2 := 0; [L344] #res := ~__retres1~2; [L759] ~tmp___1~0 := #t~ret11; [L759] havoc #t~ret11; [L761-L765] COND FALSE !(0 != ~tmp___1~0) [L348] havoc ~__retres1~3; [L351] COND FALSE !(1 == ~t3_pc~0) [L361] ~__retres1~3 := 0; [L363] #res := ~__retres1~3; [L767] ~tmp___2~0 := #t~ret12; [L767] havoc #t~ret12; [L769-L773] COND FALSE !(0 != ~tmp___2~0) [L367] havoc ~__retres1~4; [L370] COND FALSE !(1 == ~t4_pc~0) [L380] ~__retres1~4 := 0; [L382] #res := ~__retres1~4; [L775] ~tmp___3~0 := #t~ret13; [L775] havoc #t~ret13; [L777-L781] COND FALSE !(0 != ~tmp___3~0) [L386] havoc ~__retres1~5; [L389] COND FALSE !(1 == ~t5_pc~0) [L399] ~__retres1~5 := 0; [L401] #res := ~__retres1~5; [L783] ~tmp___4~0 := #t~ret14; [L783] havoc #t~ret14; [L785-L789] COND FALSE !(0 != ~tmp___4~0) [L669] COND FALSE !(1 == ~M_E~0) [L674] COND FALSE !(1 == ~T1_E~0) [L679] COND FALSE !(1 == ~T2_E~0) [L684] COND FALSE !(1 == ~T3_E~0) [L689] COND FALSE !(1 == ~T4_E~0) [L694] COND FALSE !(1 == ~T5_E~0) [L699] COND FALSE !(1 == ~E_M~0) [L704] COND FALSE !(1 == ~E_1~0) [L709] COND FALSE !(1 == ~E_2~0) [L714] COND FALSE !(1 == ~E_3~0) [L719] COND FALSE !(1 == ~E_4~0) [L724] COND FALSE !(1 == ~E_5~0) [L930-L967] COND FALSE !(false) [L933] ~kernel_st~0 := 1; [L492] havoc ~tmp~0; ----- ----- class de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.CACSL2BoogieBacktranslator [L14] ~m_pc~0 := 0; [L15] ~t1_pc~0 := 0; [L16] ~t2_pc~0 := 0; [L17] ~t3_pc~0 := 0; [L18] ~t4_pc~0 := 0; [L19] ~t5_pc~0 := 0; [L20] ~m_st~0 := 0; [L21] ~t1_st~0 := 0; [L22] ~t2_st~0 := 0; [L23] ~t3_st~0 := 0; [L24] ~t4_st~0 := 0; [L25] ~t5_st~0 := 0; [L26] ~m_i~0 := 0; [L27] ~t1_i~0 := 0; [L28] ~t2_i~0 := 0; [L29] ~t3_i~0 := 0; [L30] ~t4_i~0 := 0; [L31] ~t5_i~0 := 0; [L32] ~M_E~0 := 2; [L33] ~T1_E~0 := 2; [L34] ~T2_E~0 := 2; [L35] ~T3_E~0 := 2; [L36] ~T4_E~0 := 2; [L37] ~T5_E~0 := 2; [L38] ~E_M~0 := 2; [L39] ~E_1~0 := 2; [L40] ~E_2~0 := 2; [L41] ~E_3~0 := 2; [L42] ~E_4~0 := 2; [L43] ~E_5~0 := 2; [L51] ~token~0 := 0; [L53] ~local~0 := 0; [L975] havoc ~__retres1~7; [L886] ~m_i~0 := 1; [L887] ~t1_i~0 := 1; [L888] ~t2_i~0 := 1; [L889] ~t3_i~0 := 1; [L890] ~t4_i~0 := 1; [L891] ~t5_i~0 := 1; [L916] havoc ~kernel_st~0; [L917] havoc ~tmp~3; [L918] havoc ~tmp___0~1; [L922] ~kernel_st~0 := 0; [L416] COND TRUE 1 == ~m_i~0 [L417] ~m_st~0 := 0; [L421] COND TRUE 1 == ~t1_i~0 [L422] ~t1_st~0 := 0; [L426] COND TRUE 1 == ~t2_i~0 [L427] ~t2_st~0 := 0; [L431] COND TRUE 1 == ~t3_i~0 [L432] ~t3_st~0 := 0; [L436] COND TRUE 1 == ~t4_i~0 [L437] ~t4_st~0 := 0; [L441] COND TRUE 1 == ~t5_i~0 [L442] ~t5_st~0 := 0; [L601] COND FALSE !(0 == ~M_E~0) [L606] COND FALSE !(0 == ~T1_E~0) [L611] COND FALSE !(0 == ~T2_E~0) [L616] COND FALSE !(0 == ~T3_E~0) [L621] COND FALSE !(0 == ~T4_E~0) [L626] COND FALSE !(0 == ~T5_E~0) [L631] COND FALSE !(0 == ~E_M~0) [L636] COND FALSE !(0 == ~E_1~0) [L641] COND FALSE !(0 == ~E_2~0) [L646] COND FALSE !(0 == ~E_3~0) [L651] COND FALSE !(0 == ~E_4~0) [L656] COND FALSE !(0 == ~E_5~0) [L734] havoc ~tmp~1; [L735] havoc ~tmp___0~0; [L736] havoc ~tmp___1~0; [L737] havoc ~tmp___2~0; [L738] havoc ~tmp___3~0; [L739] havoc ~tmp___4~0; [L291] havoc ~__retres1~0; [L294] COND FALSE !(1 == ~m_pc~0) [L304] ~__retres1~0 := 0; [L306] #res := ~__retres1~0; [L743] ~tmp~1 := #t~ret9; [L743] havoc #t~ret9; [L745-L749] COND FALSE !(0 != ~tmp~1) [L310] havoc ~__retres1~1; [L313] COND FALSE !(1 == ~t1_pc~0) [L323] ~__retres1~1 := 0; [L325] #res := ~__retres1~1; [L751] ~tmp___0~0 := #t~ret10; [L751] havoc #t~ret10; [L753-L757] COND FALSE !(0 != ~tmp___0~0) [L329] havoc ~__retres1~2; [L332] COND FALSE !(1 == ~t2_pc~0) [L342] ~__retres1~2 := 0; [L344] #res := ~__retres1~2; [L759] ~tmp___1~0 := #t~ret11; [L759] havoc #t~ret11; [L761-L765] COND FALSE !(0 != ~tmp___1~0) [L348] havoc ~__retres1~3; [L351] COND FALSE !(1 == ~t3_pc~0) [L361] ~__retres1~3 := 0; [L363] #res := ~__retres1~3; [L767] ~tmp___2~0 := #t~ret12; [L767] havoc #t~ret12; [L769-L773] COND FALSE !(0 != ~tmp___2~0) [L367] havoc ~__retres1~4; [L370] COND FALSE !(1 == ~t4_pc~0) [L380] ~__retres1~4 := 0; [L382] #res := ~__retres1~4; [L775] ~tmp___3~0 := #t~ret13; [L775] havoc #t~ret13; [L777-L781] COND FALSE !(0 != ~tmp___3~0) [L386] havoc ~__retres1~5; [L389] COND FALSE !(1 == ~t5_pc~0) [L399] ~__retres1~5 := 0; [L401] #res := ~__retres1~5; [L783] ~tmp___4~0 := #t~ret14; [L783] havoc #t~ret14; [L785-L789] COND FALSE !(0 != ~tmp___4~0) [L669] COND FALSE !(1 == ~M_E~0) [L674] COND FALSE !(1 == ~T1_E~0) [L679] COND FALSE !(1 == ~T2_E~0) [L684] COND FALSE !(1 == ~T3_E~0) [L689] COND FALSE !(1 == ~T4_E~0) [L694] COND FALSE !(1 == ~T5_E~0) [L699] COND FALSE !(1 == ~E_M~0) [L704] COND FALSE !(1 == ~E_1~0) [L709] COND FALSE !(1 == ~E_2~0) [L714] COND FALSE !(1 == ~E_3~0) [L719] COND FALSE !(1 == ~E_4~0) [L724] COND FALSE !(1 == ~E_5~0) [L930-L967] COND FALSE !(false) [L933] ~kernel_st~0 := 1; [L492] havoc ~tmp~0; [L14] int m_pc = 0; [L15] int t1_pc = 0; [L16] int t2_pc = 0; [L17] int t3_pc = 0; [L18] int t4_pc = 0; [L19] int t5_pc = 0; [L20] int m_st ; [L21] int t1_st ; [L22] int t2_st ; [L23] int t3_st ; [L24] int t4_st ; [L25] int t5_st ; [L26] int m_i ; [L27] int t1_i ; [L28] int t2_i ; [L29] int t3_i ; [L30] int t4_i ; [L31] int t5_i ; [L32] int M_E = 2; [L33] int T1_E = 2; [L34] int T2_E = 2; [L35] int T3_E = 2; [L36] int T4_E = 2; [L37] int T5_E = 2; [L38] int E_M = 2; [L39] int E_1 = 2; [L40] int E_2 = 2; [L41] int E_3 = 2; [L42] int E_4 = 2; [L43] int E_5 = 2; [L51] int token ; [L53] int local ; [L975] int __retres1 ; [L886] m_i = 1 [L887] t1_i = 1 [L888] t2_i = 1 [L889] t3_i = 1 [L890] t4_i = 1 [L891] t5_i = 1 [L916] int kernel_st ; [L917] int tmp ; [L918] int tmp___0 ; [L922] kernel_st = 0 [L416] COND TRUE m_i == 1 [L417] m_st = 0 [L421] COND TRUE t1_i == 1 [L422] t1_st = 0 [L426] COND TRUE t2_i == 1 [L427] t2_st = 0 [L431] COND TRUE t3_i == 1 [L432] t3_st = 0 [L436] COND TRUE t4_i == 1 [L437] t4_st = 0 [L441] COND TRUE t5_i == 1 [L442] t5_st = 0 [L601] COND FALSE !(M_E == 0) [L606] COND FALSE !(T1_E == 0) [L611] COND FALSE !(T2_E == 0) [L616] COND FALSE !(T3_E == 0) [L621] COND FALSE !(T4_E == 0) [L626] COND FALSE !(T5_E == 0) [L631] COND FALSE !(E_M == 0) [L636] COND FALSE !(E_1 == 0) [L641] COND FALSE !(E_2 == 0) [L646] COND FALSE !(E_3 == 0) [L651] COND FALSE !(E_4 == 0) [L656] COND FALSE !(E_5 == 0) [L734] int tmp ; [L735] int tmp___0 ; [L736] int tmp___1 ; [L737] int tmp___2 ; [L738] int tmp___3 ; [L739] int tmp___4 ; [L291] int __retres1 ; [L294] COND FALSE !(m_pc == 1) [L304] __retres1 = 0 [L306] return (__retres1); [L743] tmp = is_master_triggered() [L745] COND FALSE !(\read(tmp)) [L310] int __retres1 ; [L313] COND FALSE !(t1_pc == 1) [L323] __retres1 = 0 [L325] return (__retres1); [L751] tmp___0 = is_transmit1_triggered() [L753] COND FALSE !(\read(tmp___0)) [L329] int __retres1 ; [L332] COND FALSE !(t2_pc == 1) [L342] __retres1 = 0 [L344] return (__retres1); [L759] tmp___1 = is_transmit2_triggered() [L761] COND FALSE !(\read(tmp___1)) [L348] int __retres1 ; [L351] COND FALSE !(t3_pc == 1) [L361] __retres1 = 0 [L363] return (__retres1); [L767] tmp___2 = is_transmit3_triggered() [L769] COND FALSE !(\read(tmp___2)) [L367] int __retres1 ; [L370] COND FALSE !(t4_pc == 1) [L380] __retres1 = 0 [L382] return (__retres1); [L775] tmp___3 = is_transmit4_triggered() [L777] COND FALSE !(\read(tmp___3)) [L386] int __retres1 ; [L389] COND FALSE !(t5_pc == 1) [L399] __retres1 = 0 [L401] return (__retres1); [L783] tmp___4 = is_transmit5_triggered() [L785] COND FALSE !(\read(tmp___4)) [L669] COND FALSE !(M_E == 1) [L674] COND FALSE !(T1_E == 1) [L679] COND FALSE !(T2_E == 1) [L684] COND FALSE !(T3_E == 1) [L689] COND FALSE !(T4_E == 1) [L694] COND FALSE !(T5_E == 1) [L699] COND FALSE !(E_M == 1) [L704] COND FALSE !(E_1 == 1) [L709] COND FALSE !(E_2 == 1) [L714] COND FALSE !(E_3 == 1) [L719] COND FALSE !(E_4 == 1) [L724] COND FALSE !(E_5 == 1) [L930] COND TRUE 1 [L933] kernel_st = 1 [L492] int tmp ; ----- ----- class de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder.RCFGBacktranslator [?] assume !false; [?] havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; [?] assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; [?] exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; [?] eval_#t~ret2 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret2;havoc eval_#t~ret2; [?] assume 0 != eval_~tmp~0; [?] assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0;eval_~tmp_ndt_1~0 := eval_#t~nondet3;havoc eval_#t~nondet3; [?] assume !(0 != eval_~tmp_ndt_1~0); [?] assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0;eval_~tmp_ndt_2~0 := eval_#t~nondet4;havoc eval_#t~nondet4; [?] assume !(0 != eval_~tmp_ndt_2~0); [?] assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0;eval_~tmp_ndt_3~0 := eval_#t~nondet5;havoc eval_#t~nondet5; [?] assume !(0 != eval_~tmp_ndt_3~0); [?] assume 0 == ~t3_st~0;havoc eval_~tmp_ndt_4~0;eval_~tmp_ndt_4~0 := eval_#t~nondet6;havoc eval_#t~nondet6; [?] assume !(0 != eval_~tmp_ndt_4~0); [?] assume 0 == ~t4_st~0;havoc eval_~tmp_ndt_5~0;eval_~tmp_ndt_5~0 := eval_#t~nondet7;havoc eval_#t~nondet7; [?] assume !(0 != eval_~tmp_ndt_5~0); [?] assume 0 == ~t5_st~0;havoc eval_~tmp_ndt_6~0;eval_~tmp_ndt_6~0 := eval_#t~nondet8;havoc eval_#t~nondet8; [?] assume !(0 != eval_~tmp_ndt_6~0); [L496-L590] assume !false; [L499] havoc exists_runnable_thread_#res; [L499] havoc exists_runnable_thread_~__retres1~6; [L451] havoc exists_runnable_thread_~__retres1~6; [L454-L484] assume 0 == ~m_st~0; [L455] exists_runnable_thread_~__retres1~6 := 1; [L487] exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; [L499] eval_#t~ret2 := exists_runnable_thread_#res; [L499] eval_~tmp~0 := eval_#t~ret2; [L499] havoc eval_#t~ret2; [L501-L505] assume 0 != eval_~tmp~0; [L506-L519] assume 0 == ~m_st~0; [L507] havoc eval_~tmp_ndt_1~0; [L508] eval_~tmp_ndt_1~0 := eval_#t~nondet3; [L508] havoc eval_#t~nondet3; [L509-L516] assume !(0 != eval_~tmp_ndt_1~0); [L520-L533] assume 0 == ~t1_st~0; [L521] havoc eval_~tmp_ndt_2~0; [L522] eval_~tmp_ndt_2~0 := eval_#t~nondet4; [L522] havoc eval_#t~nondet4; [L523-L530] assume !(0 != eval_~tmp_ndt_2~0); [L534-L547] assume 0 == ~t2_st~0; [L535] havoc eval_~tmp_ndt_3~0; [L536] eval_~tmp_ndt_3~0 := eval_#t~nondet5; [L536] havoc eval_#t~nondet5; [L537-L544] assume !(0 != eval_~tmp_ndt_3~0); [L548-L561] assume 0 == ~t3_st~0; [L549] havoc eval_~tmp_ndt_4~0; [L550] eval_~tmp_ndt_4~0 := eval_#t~nondet6; [L550] havoc eval_#t~nondet6; [L551-L558] assume !(0 != eval_~tmp_ndt_4~0); [L562-L575] assume 0 == ~t4_st~0; [L563] havoc eval_~tmp_ndt_5~0; [L564] eval_~tmp_ndt_5~0 := eval_#t~nondet7; [L564] havoc eval_#t~nondet7; [L565-L572] assume !(0 != eval_~tmp_ndt_5~0); [L576-L589] assume 0 == ~t5_st~0; [L577] havoc eval_~tmp_ndt_6~0; [L578] eval_~tmp_ndt_6~0 := eval_#t~nondet8; [L578] havoc eval_#t~nondet8; [L579-L586] assume !(0 != eval_~tmp_ndt_6~0); ----- ----- class de.uni_freiburg.informatik.ultimate.boogie.preprocessor.BoogiePreprocessorBacktranslator [L496-L590] assume !false; [L499] havoc exists_runnable_thread_#res; [L499] havoc exists_runnable_thread_~__retres1~6; [L451] havoc exists_runnable_thread_~__retres1~6; [L454-L484] assume 0 == ~m_st~0; [L455] exists_runnable_thread_~__retres1~6 := 1; [L487] exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; [L499] eval_#t~ret2 := exists_runnable_thread_#res; [L499] eval_~tmp~0 := eval_#t~ret2; [L499] havoc eval_#t~ret2; [L501-L505] assume 0 != eval_~tmp~0; [L506-L519] assume 0 == ~m_st~0; [L507] havoc eval_~tmp_ndt_1~0; [L508] eval_~tmp_ndt_1~0 := eval_#t~nondet3; [L508] havoc eval_#t~nondet3; [L509-L516] assume !(0 != eval_~tmp_ndt_1~0); [L520-L533] assume 0 == ~t1_st~0; [L521] havoc eval_~tmp_ndt_2~0; [L522] eval_~tmp_ndt_2~0 := eval_#t~nondet4; [L522] havoc eval_#t~nondet4; [L523-L530] assume !(0 != eval_~tmp_ndt_2~0); [L534-L547] assume 0 == ~t2_st~0; [L535] havoc eval_~tmp_ndt_3~0; [L536] eval_~tmp_ndt_3~0 := eval_#t~nondet5; [L536] havoc eval_#t~nondet5; [L537-L544] assume !(0 != eval_~tmp_ndt_3~0); [L548-L561] assume 0 == ~t3_st~0; [L549] havoc eval_~tmp_ndt_4~0; [L550] eval_~tmp_ndt_4~0 := eval_#t~nondet6; [L550] havoc eval_#t~nondet6; [L551-L558] assume !(0 != eval_~tmp_ndt_4~0); [L562-L575] assume 0 == ~t4_st~0; [L563] havoc eval_~tmp_ndt_5~0; [L564] eval_~tmp_ndt_5~0 := eval_#t~nondet7; [L564] havoc eval_#t~nondet7; [L565-L572] assume !(0 != eval_~tmp_ndt_5~0); [L576-L589] assume 0 == ~t5_st~0; [L577] havoc eval_~tmp_ndt_6~0; [L578] eval_~tmp_ndt_6~0 := eval_#t~nondet8; [L578] havoc eval_#t~nondet8; [L579-L586] assume !(0 != eval_~tmp_ndt_6~0); [L496-L590] COND FALSE !(false) [L499] havoc exists_runnable_thread_#res; [L499] havoc exists_runnable_thread_~__retres1~6; [L451] havoc exists_runnable_thread_~__retres1~6; [L454] COND TRUE 0 == ~m_st~0 [L455] exists_runnable_thread_~__retres1~6 := 1; [L487] exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; [L499] eval_#t~ret2 := exists_runnable_thread_#res; [L499] eval_~tmp~0 := eval_#t~ret2; [L499] havoc eval_#t~ret2; [L501-L505] COND TRUE 0 != eval_~tmp~0 [L506] COND TRUE 0 == ~m_st~0 [L507] havoc eval_~tmp_ndt_1~0; [L508] eval_~tmp_ndt_1~0 := eval_#t~nondet3; [L508] havoc eval_#t~nondet3; [L509-L516] COND FALSE !(0 != eval_~tmp_ndt_1~0) [L520] COND TRUE 0 == ~t1_st~0 [L521] havoc eval_~tmp_ndt_2~0; [L522] eval_~tmp_ndt_2~0 := eval_#t~nondet4; [L522] havoc eval_#t~nondet4; [L523-L530] COND FALSE !(0 != eval_~tmp_ndt_2~0) [L534] COND TRUE 0 == ~t2_st~0 [L535] havoc eval_~tmp_ndt_3~0; [L536] eval_~tmp_ndt_3~0 := eval_#t~nondet5; [L536] havoc eval_#t~nondet5; [L537-L544] COND FALSE !(0 != eval_~tmp_ndt_3~0) [L548] COND TRUE 0 == ~t3_st~0 [L549] havoc eval_~tmp_ndt_4~0; [L550] eval_~tmp_ndt_4~0 := eval_#t~nondet6; [L550] havoc eval_#t~nondet6; [L551-L558] COND FALSE !(0 != eval_~tmp_ndt_4~0) [L562] COND TRUE 0 == ~t4_st~0 [L563] havoc eval_~tmp_ndt_5~0; [L564] eval_~tmp_ndt_5~0 := eval_#t~nondet7; [L564] havoc eval_#t~nondet7; [L565-L572] COND FALSE !(0 != eval_~tmp_ndt_5~0) [L576] COND TRUE 0 == ~t5_st~0 [L577] havoc eval_~tmp_ndt_6~0; [L578] eval_~tmp_ndt_6~0 := eval_#t~nondet8; [L578] havoc eval_#t~nondet8; [L579-L586] COND FALSE !(0 != eval_~tmp_ndt_6~0) ----- ----- class de.uni_freiburg.informatik.ultimate.boogie.procedureinliner.backtranslation.InlinerBacktranslator [L496-L590] COND FALSE !(false) [L499] havoc exists_runnable_thread_#res; [L499] havoc exists_runnable_thread_~__retres1~6; [L451] havoc exists_runnable_thread_~__retres1~6; [L454] COND TRUE 0 == ~m_st~0 [L455] exists_runnable_thread_~__retres1~6 := 1; [L487] exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; [L499] eval_#t~ret2 := exists_runnable_thread_#res; [L499] eval_~tmp~0 := eval_#t~ret2; [L499] havoc eval_#t~ret2; [L501-L505] COND TRUE 0 != eval_~tmp~0 [L506] COND TRUE 0 == ~m_st~0 [L507] havoc eval_~tmp_ndt_1~0; [L508] eval_~tmp_ndt_1~0 := eval_#t~nondet3; [L508] havoc eval_#t~nondet3; [L509-L516] COND FALSE !(0 != eval_~tmp_ndt_1~0) [L520] COND TRUE 0 == ~t1_st~0 [L521] havoc eval_~tmp_ndt_2~0; [L522] eval_~tmp_ndt_2~0 := eval_#t~nondet4; [L522] havoc eval_#t~nondet4; [L523-L530] COND FALSE !(0 != eval_~tmp_ndt_2~0) [L534] COND TRUE 0 == ~t2_st~0 [L535] havoc eval_~tmp_ndt_3~0; [L536] eval_~tmp_ndt_3~0 := eval_#t~nondet5; [L536] havoc eval_#t~nondet5; [L537-L544] COND FALSE !(0 != eval_~tmp_ndt_3~0) [L548] COND TRUE 0 == ~t3_st~0 [L549] havoc eval_~tmp_ndt_4~0; [L550] eval_~tmp_ndt_4~0 := eval_#t~nondet6; [L550] havoc eval_#t~nondet6; [L551-L558] COND FALSE !(0 != eval_~tmp_ndt_4~0) [L562] COND TRUE 0 == ~t4_st~0 [L563] havoc eval_~tmp_ndt_5~0; [L564] eval_~tmp_ndt_5~0 := eval_#t~nondet7; [L564] havoc eval_#t~nondet7; [L565-L572] COND FALSE !(0 != eval_~tmp_ndt_5~0) [L576] COND TRUE 0 == ~t5_st~0 [L577] havoc eval_~tmp_ndt_6~0; [L578] eval_~tmp_ndt_6~0 := eval_#t~nondet8; [L578] havoc eval_#t~nondet8; [L579-L586] COND FALSE !(0 != eval_~tmp_ndt_6~0) [L496-L590] COND FALSE !(false) [L451] havoc ~__retres1~6; [L454] COND TRUE 0 == ~m_st~0 [L455] ~__retres1~6 := 1; [L487] #res := ~__retres1~6; [L499] ~tmp~0 := #t~ret2; [L499] havoc #t~ret2; [L501-L505] COND TRUE 0 != ~tmp~0 [L506] COND TRUE 0 == ~m_st~0 [L507] havoc ~tmp_ndt_1~0; [L508] ~tmp_ndt_1~0 := #t~nondet3; [L508] havoc #t~nondet3; [L509-L516] COND FALSE !(0 != ~tmp_ndt_1~0) [L520] COND TRUE 0 == ~t1_st~0 [L521] havoc ~tmp_ndt_2~0; [L522] ~tmp_ndt_2~0 := #t~nondet4; [L522] havoc #t~nondet4; [L523-L530] COND FALSE !(0 != ~tmp_ndt_2~0) [L534] COND TRUE 0 == ~t2_st~0 [L535] havoc ~tmp_ndt_3~0; [L536] ~tmp_ndt_3~0 := #t~nondet5; [L536] havoc #t~nondet5; [L537-L544] COND FALSE !(0 != ~tmp_ndt_3~0) [L548] COND TRUE 0 == ~t3_st~0 [L549] havoc ~tmp_ndt_4~0; [L550] ~tmp_ndt_4~0 := #t~nondet6; [L550] havoc #t~nondet6; [L551-L558] COND FALSE !(0 != ~tmp_ndt_4~0) [L562] COND TRUE 0 == ~t4_st~0 [L563] havoc ~tmp_ndt_5~0; [L564] ~tmp_ndt_5~0 := #t~nondet7; [L564] havoc #t~nondet7; [L565-L572] COND FALSE !(0 != ~tmp_ndt_5~0) [L576] COND TRUE 0 == ~t5_st~0 [L577] havoc ~tmp_ndt_6~0; [L578] ~tmp_ndt_6~0 := #t~nondet8; [L578] havoc #t~nondet8; [L579-L586] COND FALSE !(0 != ~tmp_ndt_6~0) ----- ----- class de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.CACSL2BoogieBacktranslator [L496-L590] COND FALSE !(false) [L451] havoc ~__retres1~6; [L454] COND TRUE 0 == ~m_st~0 [L455] ~__retres1~6 := 1; [L487] #res := ~__retres1~6; [L499] ~tmp~0 := #t~ret2; [L499] havoc #t~ret2; [L501-L505] COND TRUE 0 != ~tmp~0 [L506] COND TRUE 0 == ~m_st~0 [L507] havoc ~tmp_ndt_1~0; [L508] ~tmp_ndt_1~0 := #t~nondet3; [L508] havoc #t~nondet3; [L509-L516] COND FALSE !(0 != ~tmp_ndt_1~0) [L520] COND TRUE 0 == ~t1_st~0 [L521] havoc ~tmp_ndt_2~0; [L522] ~tmp_ndt_2~0 := #t~nondet4; [L522] havoc #t~nondet4; [L523-L530] COND FALSE !(0 != ~tmp_ndt_2~0) [L534] COND TRUE 0 == ~t2_st~0 [L535] havoc ~tmp_ndt_3~0; [L536] ~tmp_ndt_3~0 := #t~nondet5; [L536] havoc #t~nondet5; [L537-L544] COND FALSE !(0 != ~tmp_ndt_3~0) [L548] COND TRUE 0 == ~t3_st~0 [L549] havoc ~tmp_ndt_4~0; [L550] ~tmp_ndt_4~0 := #t~nondet6; [L550] havoc #t~nondet6; [L551-L558] COND FALSE !(0 != ~tmp_ndt_4~0) [L562] COND TRUE 0 == ~t4_st~0 [L563] havoc ~tmp_ndt_5~0; [L564] ~tmp_ndt_5~0 := #t~nondet7; [L564] havoc #t~nondet7; [L565-L572] COND FALSE !(0 != ~tmp_ndt_5~0) [L576] COND TRUE 0 == ~t5_st~0 [L577] havoc ~tmp_ndt_6~0; [L578] ~tmp_ndt_6~0 := #t~nondet8; [L578] havoc #t~nondet8; [L579-L586] COND FALSE !(0 != ~tmp_ndt_6~0) [L496] COND TRUE 1 [L451] int __retres1 ; [L454] COND TRUE m_st == 0 [L455] __retres1 = 1 [L487] return (__retres1); [L499] tmp = exists_runnable_thread() [L501] COND TRUE \read(tmp) [L506] COND TRUE m_st == 0 [L507] int tmp_ndt_1; [L508] tmp_ndt_1 = __VERIFIER_nondet_int() [L509] COND FALSE !(\read(tmp_ndt_1)) [L520] COND TRUE t1_st == 0 [L521] int tmp_ndt_2; [L522] tmp_ndt_2 = __VERIFIER_nondet_int() [L523] COND FALSE !(\read(tmp_ndt_2)) [L534] COND TRUE t2_st == 0 [L535] int tmp_ndt_3; [L536] tmp_ndt_3 = __VERIFIER_nondet_int() [L537] COND FALSE !(\read(tmp_ndt_3)) [L548] COND TRUE t3_st == 0 [L549] int tmp_ndt_4; [L550] tmp_ndt_4 = __VERIFIER_nondet_int() [L551] COND FALSE !(\read(tmp_ndt_4)) [L562] COND TRUE t4_st == 0 [L563] int tmp_ndt_5; [L564] tmp_ndt_5 = __VERIFIER_nondet_int() [L565] COND FALSE !(\read(tmp_ndt_5)) [L576] COND TRUE t5_st == 0 [L577] int tmp_ndt_6; [L578] tmp_ndt_6 = __VERIFIER_nondet_int() [L579] COND FALSE !(\read(tmp_ndt_6)) ----- Found a nonterminating execution for the following lasso shaped sequence of statements. Stem: [L14] int m_pc = 0; [L15] int t1_pc = 0; [L16] int t2_pc = 0; [L17] int t3_pc = 0; [L18] int t4_pc = 0; [L19] int t5_pc = 0; [L20] int m_st ; [L21] int t1_st ; [L22] int t2_st ; [L23] int t3_st ; [L24] int t4_st ; [L25] int t5_st ; [L26] int m_i ; [L27] int t1_i ; [L28] int t2_i ; [L29] int t3_i ; [L30] int t4_i ; [L31] int t5_i ; [L32] int M_E = 2; [L33] int T1_E = 2; [L34] int T2_E = 2; [L35] int T3_E = 2; [L36] int T4_E = 2; [L37] int T5_E = 2; [L38] int E_M = 2; [L39] int E_1 = 2; [L40] int E_2 = 2; [L41] int E_3 = 2; [L42] int E_4 = 2; [L43] int E_5 = 2; [L51] int token ; [L53] int local ; [L975] int __retres1 ; [L886] m_i = 1 [L887] t1_i = 1 [L888] t2_i = 1 [L889] t3_i = 1 [L890] t4_i = 1 [L891] t5_i = 1 [L916] int kernel_st ; [L917] int tmp ; [L918] int tmp___0 ; [L922] kernel_st = 0 [L416] COND TRUE m_i == 1 [L417] m_st = 0 [L421] COND TRUE t1_i == 1 [L422] t1_st = 0 [L426] COND TRUE t2_i == 1 [L427] t2_st = 0 [L431] COND TRUE t3_i == 1 [L432] t3_st = 0 [L436] COND TRUE t4_i == 1 [L437] t4_st = 0 [L441] COND TRUE t5_i == 1 [L442] t5_st = 0 [L601] COND FALSE !(M_E == 0) [L606] COND FALSE !(T1_E == 0) [L611] COND FALSE !(T2_E == 0) [L616] COND FALSE !(T3_E == 0) [L621] COND FALSE !(T4_E == 0) [L626] COND FALSE !(T5_E == 0) [L631] COND FALSE !(E_M == 0) [L636] COND FALSE !(E_1 == 0) [L641] COND FALSE !(E_2 == 0) [L646] COND FALSE !(E_3 == 0) [L651] COND FALSE !(E_4 == 0) [L656] COND FALSE !(E_5 == 0) [L734] int tmp ; [L735] int tmp___0 ; [L736] int tmp___1 ; [L737] int tmp___2 ; [L738] int tmp___3 ; [L739] int tmp___4 ; [L291] int __retres1 ; [L294] COND FALSE !(m_pc == 1) [L304] __retres1 = 0 [L306] return (__retres1); [L743] tmp = is_master_triggered() [L745] COND FALSE !(\read(tmp)) [L310] int __retres1 ; [L313] COND FALSE !(t1_pc == 1) [L323] __retres1 = 0 [L325] return (__retres1); [L751] tmp___0 = is_transmit1_triggered() [L753] COND FALSE !(\read(tmp___0)) [L329] int __retres1 ; [L332] COND FALSE !(t2_pc == 1) [L342] __retres1 = 0 [L344] return (__retres1); [L759] tmp___1 = is_transmit2_triggered() [L761] COND FALSE !(\read(tmp___1)) [L348] int __retres1 ; [L351] COND FALSE !(t3_pc == 1) [L361] __retres1 = 0 [L363] return (__retres1); [L767] tmp___2 = is_transmit3_triggered() [L769] COND FALSE !(\read(tmp___2)) [L367] int __retres1 ; [L370] COND FALSE !(t4_pc == 1) [L380] __retres1 = 0 [L382] return (__retres1); [L775] tmp___3 = is_transmit4_triggered() [L777] COND FALSE !(\read(tmp___3)) [L386] int __retres1 ; [L389] COND FALSE !(t5_pc == 1) [L399] __retres1 = 0 [L401] return (__retres1); [L783] tmp___4 = is_transmit5_triggered() [L785] COND FALSE !(\read(tmp___4)) [L669] COND FALSE !(M_E == 1) [L674] COND FALSE !(T1_E == 1) [L679] COND FALSE !(T2_E == 1) [L684] COND FALSE !(T3_E == 1) [L689] COND FALSE !(T4_E == 1) [L694] COND FALSE !(T5_E == 1) [L699] COND FALSE !(E_M == 1) [L704] COND FALSE !(E_1 == 1) [L709] COND FALSE !(E_2 == 1) [L714] COND FALSE !(E_3 == 1) [L719] COND FALSE !(E_4 == 1) [L724] COND FALSE !(E_5 == 1) [L930] COND TRUE 1 [L933] kernel_st = 1 [L492] int tmp ; Loop: [L496] COND TRUE 1 [L451] int __retres1 ; [L454] COND TRUE m_st == 0 [L455] __retres1 = 1 [L487] return (__retres1); [L499] tmp = exists_runnable_thread() [L501] COND TRUE \read(tmp) [L506] COND TRUE m_st == 0 [L507] int tmp_ndt_1; [L508] tmp_ndt_1 = __VERIFIER_nondet_int() [L509] COND FALSE !(\read(tmp_ndt_1)) [L520] COND TRUE t1_st == 0 [L521] int tmp_ndt_2; [L522] tmp_ndt_2 = __VERIFIER_nondet_int() [L523] COND FALSE !(\read(tmp_ndt_2)) [L534] COND TRUE t2_st == 0 [L535] int tmp_ndt_3; [L536] tmp_ndt_3 = __VERIFIER_nondet_int() [L537] COND FALSE !(\read(tmp_ndt_3)) [L548] COND TRUE t3_st == 0 [L549] int tmp_ndt_4; [L550] tmp_ndt_4 = __VERIFIER_nondet_int() [L551] COND FALSE !(\read(tmp_ndt_4)) [L562] COND TRUE t4_st == 0 [L563] int tmp_ndt_5; [L564] tmp_ndt_5 = __VERIFIER_nondet_int() [L565] COND FALSE !(\read(tmp_ndt_5)) [L576] COND TRUE t5_st == 0 [L577] int tmp_ndt_6; [L578] tmp_ndt_6 = __VERIFIER_nondet_int() [L579] COND FALSE !(\read(tmp_ndt_6)) End of lasso representation. RESULT: Ultimate proved your program to be incorrect! Received shutdown request...