./Ultimate.py --spec ../../sv-benchmarks/c/properties/termination.prp --file ../../sv-benchmarks/c/systemc/token_ring.05_true-unreach-call_false-termination.cil.c --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for termination Using default analysis Version aa418289 Calling Ultimate with: java -Dosgi.configuration.area=/tmp/vcloud-vcloud-master/worker/working_dir_fb5f2687-a2ab-446f-b368-1667316ddbd5/bin-2019/uautomizer/data/config -Xmx12G -Xms1G -jar /tmp/vcloud-vcloud-master/worker/working_dir_fb5f2687-a2ab-446f-b368-1667316ddbd5/bin-2019/uautomizer/plugins/org.eclipse.equinox.launcher_1.3.100.v20150511-1540.jar -data @noDefault -ultimatedata /tmp/vcloud-vcloud-master/worker/working_dir_fb5f2687-a2ab-446f-b368-1667316ddbd5/bin-2019/uautomizer/data -tc /tmp/vcloud-vcloud-master/worker/working_dir_fb5f2687-a2ab-446f-b368-1667316ddbd5/bin-2019/uautomizer/config/AutomizerTermination.xml -i ../../sv-benchmarks/c/systemc/token_ring.05_true-unreach-call_false-termination.cil.c -s /tmp/vcloud-vcloud-master/worker/working_dir_fb5f2687-a2ab-446f-b368-1667316ddbd5/bin-2019/uautomizer/config/svcomp-Termination-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud-vcloud-master/worker/working_dir_fb5f2687-a2ab-446f-b368-1667316ddbd5/bin-2019/uautomizer --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash 75ee388caeaa04bad2057d2e7044ba2f86479f59 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Execution finished normally Writing output log to file Ultimate.log Writing human readable error path to file UltimateCounterExample.errorpath Result: FALSE(TERM) --- Real Ultimate output --- This is Ultimate 0.1.23-aa41828 [2018-11-23 13:21:47,331 INFO L170 SettingsManager]: Resetting all preferences to default values... [2018-11-23 13:21:47,332 INFO L174 SettingsManager]: Resetting UltimateCore preferences to default values [2018-11-23 13:21:47,342 INFO L177 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2018-11-23 13:21:47,343 INFO L174 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2018-11-23 13:21:47,343 INFO L174 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2018-11-23 13:21:47,344 INFO L174 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2018-11-23 13:21:47,346 INFO L174 SettingsManager]: Resetting LassoRanker preferences to default values [2018-11-23 13:21:47,348 INFO L174 SettingsManager]: Resetting Reaching Definitions preferences to default values [2018-11-23 13:21:47,348 INFO L174 SettingsManager]: Resetting SyntaxChecker preferences to default values [2018-11-23 13:21:47,349 INFO L177 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2018-11-23 13:21:47,349 INFO L174 SettingsManager]: Resetting LTL2Aut preferences to default values [2018-11-23 13:21:47,350 INFO L174 SettingsManager]: Resetting PEA to Boogie preferences to default values [2018-11-23 13:21:47,351 INFO L174 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2018-11-23 13:21:47,352 INFO L174 SettingsManager]: Resetting ChcToBoogie preferences to default values [2018-11-23 13:21:47,353 INFO L174 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2018-11-23 13:21:47,353 INFO L174 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2018-11-23 13:21:47,355 INFO L174 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2018-11-23 13:21:47,356 INFO L174 SettingsManager]: Resetting CodeCheck preferences to default values [2018-11-23 13:21:47,358 INFO L174 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2018-11-23 13:21:47,358 INFO L174 SettingsManager]: Resetting RCFGBuilder preferences to default values [2018-11-23 13:21:47,359 INFO L174 SettingsManager]: Resetting TraceAbstraction preferences to default values [2018-11-23 13:21:47,361 INFO L177 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2018-11-23 13:21:47,361 INFO L177 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2018-11-23 13:21:47,362 INFO L174 SettingsManager]: Resetting TreeAutomizer preferences to default values [2018-11-23 13:21:47,362 INFO L174 SettingsManager]: Resetting IcfgTransformer preferences to default values [2018-11-23 13:21:47,363 INFO L174 SettingsManager]: Resetting Boogie Printer preferences to default values [2018-11-23 13:21:47,364 INFO L174 SettingsManager]: Resetting ReqPrinter preferences to default values [2018-11-23 13:21:47,364 INFO L174 SettingsManager]: Resetting Witness Printer preferences to default values [2018-11-23 13:21:47,365 INFO L177 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2018-11-23 13:21:47,365 INFO L174 SettingsManager]: Resetting CDTParser preferences to default values [2018-11-23 13:21:47,366 INFO L177 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2018-11-23 13:21:47,366 INFO L177 SettingsManager]: ReqParser provides no preferences, ignoring... [2018-11-23 13:21:47,366 INFO L174 SettingsManager]: Resetting SmtParser preferences to default values [2018-11-23 13:21:47,367 INFO L174 SettingsManager]: Resetting Witness Parser preferences to default values [2018-11-23 13:21:47,367 INFO L181 SettingsManager]: Finished resetting all preferences to default values... [2018-11-23 13:21:47,368 INFO L98 SettingsManager]: Beginning loading settings from /tmp/vcloud-vcloud-master/worker/working_dir_fb5f2687-a2ab-446f-b368-1667316ddbd5/bin-2019/uautomizer/config/svcomp-Termination-32bit-Automizer_Default.epf [2018-11-23 13:21:47,380 INFO L110 SettingsManager]: Loading preferences was successful [2018-11-23 13:21:47,380 INFO L112 SettingsManager]: Preferences different from defaults after loading the file: [2018-11-23 13:21:47,381 INFO L131 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2018-11-23 13:21:47,381 INFO L133 SettingsManager]: * Create parallel compositions if possible=false [2018-11-23 13:21:47,381 INFO L133 SettingsManager]: * Use SBE=true [2018-11-23 13:21:47,382 INFO L131 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: [2018-11-23 13:21:47,382 INFO L133 SettingsManager]: * NCSB implementation=INTSET_LAZY3 [2018-11-23 13:21:47,382 INFO L133 SettingsManager]: * Use old map elimination=false [2018-11-23 13:21:47,382 INFO L133 SettingsManager]: * Use external solver (rank synthesis)=false [2018-11-23 13:21:47,382 INFO L133 SettingsManager]: * Use only trivial implications for array writes=true [2018-11-23 13:21:47,382 INFO L133 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES [2018-11-23 13:21:47,383 INFO L131 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2018-11-23 13:21:47,383 INFO L133 SettingsManager]: * sizeof long=4 [2018-11-23 13:21:47,383 INFO L133 SettingsManager]: * Check unreachability of error function in SV-COMP mode=false [2018-11-23 13:21:47,383 INFO L133 SettingsManager]: * Overapproximate operations on floating types=true [2018-11-23 13:21:47,383 INFO L133 SettingsManager]: * sizeof POINTER=4 [2018-11-23 13:21:47,383 INFO L133 SettingsManager]: * Check division by zero=IGNORE [2018-11-23 13:21:47,383 INFO L133 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME [2018-11-23 13:21:47,383 INFO L133 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME [2018-11-23 13:21:47,384 INFO L133 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME [2018-11-23 13:21:47,384 INFO L133 SettingsManager]: * sizeof long double=12 [2018-11-23 13:21:47,384 INFO L133 SettingsManager]: * Check if freed pointer was valid=false [2018-11-23 13:21:47,384 INFO L133 SettingsManager]: * Assume nondeterminstic values are in range=false [2018-11-23 13:21:47,384 INFO L133 SettingsManager]: * Use constant arrays=true [2018-11-23 13:21:47,384 INFO L133 SettingsManager]: * Pointer base address is valid at dereference=ASSUME [2018-11-23 13:21:47,384 INFO L131 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2018-11-23 13:21:47,385 INFO L133 SettingsManager]: * Size of a code block=SequenceOfStatements [2018-11-23 13:21:47,385 INFO L133 SettingsManager]: * To the following directory=/home/matthias/ultimate/dump [2018-11-23 13:21:47,385 INFO L131 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2018-11-23 13:21:47,385 INFO L133 SettingsManager]: * Trace refinement strategy=CAMEL [2018-11-23 13:21:47,385 INFO L133 SettingsManager]: * Dump automata to the following directory=/home/matthias/ultimate/dump/auto [2018-11-23 13:21:47,386 INFO L131 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2018-11-23 13:21:47,386 INFO L133 SettingsManager]: * TransformationType=MODULO_NEIGHBOR Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud-vcloud-master/worker/working_dir_fb5f2687-a2ab-446f-b368-1667316ddbd5/bin-2019/uautomizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> 75ee388caeaa04bad2057d2e7044ba2f86479f59 [2018-11-23 13:21:47,409 INFO L81 nceAwareModelManager]: Repository-Root is: /tmp [2018-11-23 13:21:47,419 INFO L258 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2018-11-23 13:21:47,422 INFO L214 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2018-11-23 13:21:47,423 INFO L271 PluginConnector]: Initializing CDTParser... [2018-11-23 13:21:47,423 INFO L276 PluginConnector]: CDTParser initialized [2018-11-23 13:21:47,423 INFO L418 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud-vcloud-master/worker/working_dir_fb5f2687-a2ab-446f-b368-1667316ddbd5/bin-2019/uautomizer/../../sv-benchmarks/c/systemc/token_ring.05_true-unreach-call_false-termination.cil.c [2018-11-23 13:21:47,469 INFO L221 CDTParser]: Created temporary CDT project at /tmp/vcloud-vcloud-master/worker/working_dir_fb5f2687-a2ab-446f-b368-1667316ddbd5/bin-2019/uautomizer/data/5e865b368/136f42a841784357b6d7f0be14e37996/FLAGda63a6426 [2018-11-23 13:21:47,828 INFO L307 CDTParser]: Found 1 translation units. [2018-11-23 13:21:47,828 INFO L161 CDTParser]: Scanning /tmp/vcloud-vcloud-master/worker/working_dir_fb5f2687-a2ab-446f-b368-1667316ddbd5/sv-benchmarks/c/systemc/token_ring.05_true-unreach-call_false-termination.cil.c [2018-11-23 13:21:47,837 INFO L355 CDTParser]: About to delete temporary CDT project at /tmp/vcloud-vcloud-master/worker/working_dir_fb5f2687-a2ab-446f-b368-1667316ddbd5/bin-2019/uautomizer/data/5e865b368/136f42a841784357b6d7f0be14e37996/FLAGda63a6426 [2018-11-23 13:21:48,228 INFO L363 CDTParser]: Successfully deleted /tmp/vcloud-vcloud-master/worker/working_dir_fb5f2687-a2ab-446f-b368-1667316ddbd5/bin-2019/uautomizer/data/5e865b368/136f42a841784357b6d7f0be14e37996 [2018-11-23 13:21:48,230 INFO L296 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2018-11-23 13:21:48,231 INFO L131 ToolchainWalker]: Walking toolchain with 6 elements. [2018-11-23 13:21:48,232 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2018-11-23 13:21:48,232 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2018-11-23 13:21:48,234 INFO L276 PluginConnector]: CACSL2BoogieTranslator initialized [2018-11-23 13:21:48,235 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 23.11 01:21:48" (1/1) ... [2018-11-23 13:21:48,237 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@6f51b539 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 01:21:48, skipping insertion in model container [2018-11-23 13:21:48,237 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 23.11 01:21:48" (1/1) ... [2018-11-23 13:21:48,243 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2018-11-23 13:21:48,270 INFO L176 MainTranslator]: Built tables and reachable declarations [2018-11-23 13:21:48,421 INFO L201 PostProcessor]: Analyzing one entry point: main [2018-11-23 13:21:48,426 INFO L191 MainTranslator]: Completed pre-run [2018-11-23 13:21:48,458 INFO L201 PostProcessor]: Analyzing one entry point: main [2018-11-23 13:21:48,472 INFO L195 MainTranslator]: Completed translation [2018-11-23 13:21:48,472 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 01:21:48 WrapperNode [2018-11-23 13:21:48,472 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2018-11-23 13:21:48,473 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2018-11-23 13:21:48,473 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2018-11-23 13:21:48,473 INFO L276 PluginConnector]: Boogie Procedure Inliner initialized [2018-11-23 13:21:48,478 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 01:21:48" (1/1) ... [2018-11-23 13:21:48,483 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 01:21:48" (1/1) ... [2018-11-23 13:21:48,561 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2018-11-23 13:21:48,562 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2018-11-23 13:21:48,562 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2018-11-23 13:21:48,562 INFO L276 PluginConnector]: Boogie Preprocessor initialized [2018-11-23 13:21:48,570 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 01:21:48" (1/1) ... [2018-11-23 13:21:48,570 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 01:21:48" (1/1) ... [2018-11-23 13:21:48,575 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 01:21:48" (1/1) ... [2018-11-23 13:21:48,575 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 01:21:48" (1/1) ... [2018-11-23 13:21:48,587 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 01:21:48" (1/1) ... [2018-11-23 13:21:48,600 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 01:21:48" (1/1) ... [2018-11-23 13:21:48,603 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 01:21:48" (1/1) ... [2018-11-23 13:21:48,609 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2018-11-23 13:21:48,609 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2018-11-23 13:21:48,609 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2018-11-23 13:21:48,609 INFO L276 PluginConnector]: RCFGBuilder initialized [2018-11-23 13:21:48,610 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 01:21:48" (1/1) ... No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_fb5f2687-a2ab-446f-b368-1667316ddbd5/bin-2019/uautomizer/z3 Starting monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2018-11-23 13:21:48,667 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2018-11-23 13:21:48,668 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2018-11-23 13:21:49,614 INFO L275 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2018-11-23 13:21:49,615 INFO L280 CfgBuilder]: Removed 196 assue(true) statements. [2018-11-23 13:21:49,615 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 23.11 01:21:49 BoogieIcfgContainer [2018-11-23 13:21:49,615 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2018-11-23 13:21:49,616 INFO L113 PluginConnector]: ------------------------BuchiAutomizer---------------------------- [2018-11-23 13:21:49,616 INFO L271 PluginConnector]: Initializing BuchiAutomizer... [2018-11-23 13:21:49,618 INFO L276 PluginConnector]: BuchiAutomizer initialized [2018-11-23 13:21:49,619 INFO L102 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2018-11-23 13:21:49,619 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 23.11 01:21:48" (1/3) ... [2018-11-23 13:21:49,620 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@74592fe4 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 23.11 01:21:49, skipping insertion in model container [2018-11-23 13:21:49,620 INFO L102 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2018-11-23 13:21:49,620 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 01:21:48" (2/3) ... [2018-11-23 13:21:49,620 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@74592fe4 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 23.11 01:21:49, skipping insertion in model container [2018-11-23 13:21:49,620 INFO L102 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2018-11-23 13:21:49,620 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 23.11 01:21:49" (3/3) ... [2018-11-23 13:21:49,622 INFO L375 chiAutomizerObserver]: Analyzing ICFG token_ring.05_true-unreach-call_false-termination.cil.c [2018-11-23 13:21:49,662 INFO L133 ementStrategyFactory]: Using default assertion order modulation [2018-11-23 13:21:49,663 INFO L374 BuchiCegarLoop]: Interprodecural is true [2018-11-23 13:21:49,663 INFO L375 BuchiCegarLoop]: Hoare is false [2018-11-23 13:21:49,663 INFO L376 BuchiCegarLoop]: Compute interpolants for ForwardPredicates [2018-11-23 13:21:49,663 INFO L377 BuchiCegarLoop]: Backedges is STRAIGHT_LINE [2018-11-23 13:21:49,663 INFO L378 BuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2018-11-23 13:21:49,663 INFO L379 BuchiCegarLoop]: Difference is false [2018-11-23 13:21:49,663 INFO L380 BuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2018-11-23 13:21:49,663 INFO L383 BuchiCegarLoop]: ======== Iteration 0==of CEGAR loop == BuchiCegarLoop======== [2018-11-23 13:21:49,684 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 532 states. [2018-11-23 13:21:49,719 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 453 [2018-11-23 13:21:49,719 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-23 13:21:49,719 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-23 13:21:49,727 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 13:21:49,727 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 13:21:49,728 INFO L442 BuchiCegarLoop]: ======== Iteration 1============ [2018-11-23 13:21:49,728 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 532 states. [2018-11-23 13:21:49,737 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 453 [2018-11-23 13:21:49,737 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-23 13:21:49,738 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-23 13:21:49,740 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 13:21:49,740 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 13:21:49,747 INFO L794 eck$LassoCheckResult]: Stem: 377#ULTIMATE.startENTRYtrue ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 305#L-1true havoc main_#res;havoc main_~__retres1~7;havoc main_~__retres1~7;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 376#L881true havoc start_simulation_#t~ret15, start_simulation_#t~ret16, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 214#L397true assume !(1 == ~m_i~0);~m_st~0 := 2; 511#L404-1true assume 1 == ~t1_i~0;~t1_st~0 := 0; 156#L409-1true assume !(1 == ~t2_i~0);~t2_st~0 := 2; 429#L414-1true assume !(1 == ~t3_i~0);~t3_st~0 := 2; 215#L419-1true assume !(1 == ~t4_i~0);~t4_st~0 := 2; 107#L424-1true assume !(1 == ~t5_i~0);~t5_st~0 := 2; 380#L429-1true assume !(0 == ~M_E~0); 121#L589-1true assume !(0 == ~T1_E~0); 384#L594-1true assume !(0 == ~T2_E~0); 7#L599-1true assume 0 == ~T3_E~0;~T3_E~0 := 1; 330#L604-1true assume !(0 == ~T4_E~0); 80#L609-1true assume !(0 == ~T5_E~0); 496#L614-1true assume !(0 == ~E_M~0); 279#L619-1true assume !(0 == ~E_1~0); 534#L624-1true assume !(0 == ~E_2~0); 164#L629-1true assume !(0 == ~E_3~0); 448#L634-1true assume !(0 == ~E_4~0); 223#L639-1true assume 0 == ~E_5~0;~E_5~0 := 1; 116#L644-1true havoc activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 407#L282true assume 1 == ~m_pc~0; 507#L283true assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 408#L293true is_master_triggered_#res := is_master_triggered_~__retres1~0; 508#L294true activate_threads_#t~ret8 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 460#L733true assume !(0 != activate_threads_~tmp~1); 463#L733-2true havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 69#L301true assume !(1 == ~t1_pc~0); 65#L301-2true is_transmit1_triggered_~__retres1~1 := 0; 47#L312true is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 138#L313true activate_threads_#t~ret9 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 87#L741true assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 74#L741-2true havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 220#L320true assume 1 == ~t2_pc~0; 159#L321true assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 219#L331true is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 158#L332true activate_threads_#t~ret10 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 371#L749true assume !(0 != activate_threads_~tmp___1~0); 372#L749-2true havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 358#L339true assume !(1 == ~t3_pc~0); 362#L339-2true is_transmit3_triggered_~__retres1~3 := 0; 357#L350true is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 325#L351true activate_threads_#t~ret11 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 501#L757true assume !(0 != activate_threads_~tmp___2~0); 489#L757-2true havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 111#L358true assume 1 == ~t4_pc~0; 434#L359true assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 109#L369true is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 431#L370true activate_threads_#t~ret12 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 126#L765true assume !(0 != activate_threads_~tmp___3~0); 127#L765-2true havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 255#L377true assume !(1 == ~t5_pc~0); 259#L377-2true is_transmit5_triggered_~__retres1~5 := 0; 253#L388true is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 70#L389true activate_threads_#t~ret13 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 281#L773true assume !(0 != activate_threads_~tmp___4~0); 274#L773-2true assume !(1 == ~M_E~0); 531#L657-1true assume !(1 == ~T1_E~0); 178#L662-1true assume !(1 == ~T2_E~0); 464#L667-1true assume !(1 == ~T3_E~0); 374#L672-1true assume !(1 == ~T4_E~0); 115#L677-1true assume 1 == ~T5_E~0;~T5_E~0 := 2; 382#L682-1true assume !(1 == ~E_M~0); 3#L687-1true assume !(1 == ~E_1~0); 327#L692-1true assume !(1 == ~E_2~0); 75#L697-1true assume !(1 == ~E_3~0); 490#L702-1true assume !(1 == ~E_4~0); 275#L707-1true assume !(1 == ~E_5~0); 24#L918-1true [2018-11-23 13:21:49,748 INFO L796 eck$LassoCheckResult]: Loop: 24#L918-1true assume !false; 130#L919true start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret1, eval_#t~nondet2, eval_~tmp_ndt_1~0, eval_#t~nondet3, eval_~tmp_ndt_2~0, eval_#t~nondet4, eval_~tmp_ndt_3~0, eval_#t~nondet5, eval_~tmp_ndt_4~0, eval_#t~nondet6, eval_~tmp_ndt_5~0, eval_#t~nondet7, eval_~tmp_ndt_6~0, eval_~tmp~0;havoc eval_~tmp~0; 266#L564true assume !true; 450#L579true start_simulation_~kernel_st~0 := 2; 217#L397-1true start_simulation_~kernel_st~0 := 3; 123#L589-2true assume 0 == ~M_E~0;~M_E~0 := 1; 102#L589-4true assume !(0 == ~T1_E~0); 387#L594-3true assume 0 == ~T2_E~0;~T2_E~0 := 1; 144#L599-3true assume 0 == ~T3_E~0;~T3_E~0 := 1; 319#L604-3true assume 0 == ~T4_E~0;~T4_E~0 := 1; 62#L609-3true assume 0 == ~T5_E~0;~T5_E~0 := 1; 485#L614-3true assume 0 == ~E_M~0;~E_M~0 := 1; 268#L619-3true assume 0 == ~E_1~0;~E_1~0 := 1; 525#L624-3true assume 0 == ~E_2~0;~E_2~0 := 1; 168#L629-3true assume !(0 == ~E_3~0); 453#L634-3true assume 0 == ~E_4~0;~E_4~0 := 1; 227#L639-3true assume 0 == ~E_5~0;~E_5~0 := 1; 122#L644-3true havoc activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 521#L282-21true assume !(1 == ~m_pc~0); 532#L282-23true is_master_triggered_~__retres1~0 := 0; 396#L293-7true is_master_triggered_#res := is_master_triggered_~__retres1~0; 509#L294-7true activate_threads_#t~ret8 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 401#L733-21true assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 403#L733-23true havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 14#L301-21true assume 1 == ~t1_pc~0; 131#L302-7true assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 38#L312-7true is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 136#L313-7true activate_threads_#t~ret9 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 40#L741-21true assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 17#L741-23true havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 177#L320-21true assume !(1 == ~t2_pc~0); 165#L320-23true is_transmit2_triggered_~__retres1~2 := 0; 187#L331-7true is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 296#L332-7true activate_threads_#t~ret10 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 191#L749-21true assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 196#L749-23true havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 326#L339-21true assume !(1 == ~t3_pc~0); 328#L339-23true is_transmit3_triggered_~__retres1~3 := 0; 350#L350-7true is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 301#L351-7true activate_threads_#t~ret11 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 354#L757-21true assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 337#L757-23true havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 462#L358-21true assume !(1 == ~t4_pc~0); 466#L358-23true is_transmit4_triggered_~__retres1~4 := 0; 100#L369-7true is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 418#L370-7true activate_threads_#t~ret12 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 479#L765-21true assume !(0 != activate_threads_~tmp___3~0); 481#L765-23true havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 73#L377-21true assume 1 == ~t5_pc~0; 32#L378-7true assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 247#L388-7true is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 29#L389-7true activate_threads_#t~ret13 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 252#L773-21true assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 233#L773-23true assume 1 == ~M_E~0;~M_E~0 := 2; 522#L657-3true assume 1 == ~T1_E~0;~T1_E~0 := 2; 166#L662-3true assume 1 == ~T2_E~0;~T2_E~0 := 2; 452#L667-3true assume !(1 == ~T3_E~0); 225#L672-3true assume 1 == ~T4_E~0;~T4_E~0 := 2; 118#L677-3true assume 1 == ~T5_E~0;~T5_E~0 := 2; 383#L682-3true assume 1 == ~E_M~0;~E_M~0 := 2; 6#L687-3true assume 1 == ~E_1~0;~E_1~0 := 2; 329#L692-3true assume 1 == ~E_2~0;~E_2~0 := 2; 79#L697-3true assume 1 == ~E_3~0;~E_3~0 := 2; 493#L702-3true assume 1 == ~E_4~0;~E_4~0 := 2; 278#L707-3true assume !(1 == ~E_5~0); 533#L712-3true havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 154#L442-1true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 212#L474-1true exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 174#L475-1true start_simulation_#t~ret15 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret15;havoc start_simulation_#t~ret15; 180#L937true assume !(0 == start_simulation_~tmp~3); 182#L937-1true havoc stop_simulation_#res;havoc stop_simulation_#t~ret14, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 157#L442-2true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 213#L474-2true exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 155#L475-2true stop_simulation_#t~ret14 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret14;havoc stop_simulation_#t~ret14; 375#L892true assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 390#L899true stop_simulation_#res := stop_simulation_~__retres2~0; 498#L900true start_simulation_#t~ret16 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret16;havoc start_simulation_#t~ret16; 238#L950true assume !(0 != start_simulation_~tmp___0~1); 24#L918-1true [2018-11-23 13:21:49,754 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 13:21:49,754 INFO L82 PathProgramCache]: Analyzing trace with hash -81461004, now seen corresponding path program 1 times [2018-11-23 13:21:49,756 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 13:21:49,756 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 13:21:49,788 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 13:21:49,789 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 13:21:49,789 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 13:21:49,816 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 13:21:49,883 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 13:21:49,885 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 13:21:49,886 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-23 13:21:49,890 INFO L799 eck$LassoCheckResult]: stem already infeasible [2018-11-23 13:21:49,890 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 13:21:49,890 INFO L82 PathProgramCache]: Analyzing trace with hash 705629471, now seen corresponding path program 1 times [2018-11-23 13:21:49,891 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 13:21:49,891 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 13:21:49,892 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 13:21:49,892 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 13:21:49,892 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 13:21:49,897 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 13:21:49,912 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 13:21:49,912 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 13:21:49,912 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2018-11-23 13:21:49,914 INFO L811 eck$LassoCheckResult]: loop already infeasible [2018-11-23 13:21:49,928 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-23 13:21:49,929 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-23 13:21:49,930 INFO L87 Difference]: Start difference. First operand 532 states. Second operand 3 states. [2018-11-23 13:21:49,980 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 13:21:49,980 INFO L93 Difference]: Finished difference Result 532 states and 804 transitions. [2018-11-23 13:21:49,981 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-23 13:21:49,982 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 532 states and 804 transitions. [2018-11-23 13:21:49,986 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 452 [2018-11-23 13:21:49,993 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 532 states to 527 states and 799 transitions. [2018-11-23 13:21:49,994 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 527 [2018-11-23 13:21:49,995 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 527 [2018-11-23 13:21:49,996 INFO L73 IsDeterministic]: Start isDeterministic. Operand 527 states and 799 transitions. [2018-11-23 13:21:49,998 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-23 13:21:49,999 INFO L705 BuchiCegarLoop]: Abstraction has 527 states and 799 transitions. [2018-11-23 13:21:50,011 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 527 states and 799 transitions. [2018-11-23 13:21:50,035 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 527 to 527. [2018-11-23 13:21:50,036 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 527 states. [2018-11-23 13:21:50,038 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 527 states to 527 states and 799 transitions. [2018-11-23 13:21:50,039 INFO L728 BuchiCegarLoop]: Abstraction has 527 states and 799 transitions. [2018-11-23 13:21:50,039 INFO L608 BuchiCegarLoop]: Abstraction has 527 states and 799 transitions. [2018-11-23 13:21:50,041 INFO L442 BuchiCegarLoop]: ======== Iteration 2============ [2018-11-23 13:21:50,041 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 527 states and 799 transitions. [2018-11-23 13:21:50,044 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 452 [2018-11-23 13:21:50,044 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-23 13:21:50,044 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-23 13:21:50,046 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 13:21:50,047 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 13:21:50,047 INFO L794 eck$LassoCheckResult]: Stem: 1511#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 1461#L-1 havoc main_#res;havoc main_~__retres1~7;havoc main_~__retres1~7;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 1462#L881 havoc start_simulation_#t~ret15, start_simulation_#t~ret16, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 1395#L397 assume 1 == ~m_i~0;~m_st~0 := 0; 1396#L404-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1316#L409-1 assume !(1 == ~t2_i~0);~t2_st~0 := 2; 1317#L414-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 1397#L419-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 1267#L424-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 1268#L429-1 assume !(0 == ~M_E~0); 1293#L589-1 assume !(0 == ~T1_E~0); 1294#L594-1 assume !(0 == ~T2_E~0); 1082#L599-1 assume 0 == ~T3_E~0;~T3_E~0 := 1; 1083#L604-1 assume !(0 == ~T4_E~0); 1221#L609-1 assume !(0 == ~T5_E~0); 1222#L614-1 assume !(0 == ~E_M~0); 1441#L619-1 assume !(0 == ~E_1~0); 1442#L624-1 assume !(0 == ~E_2~0); 1334#L629-1 assume !(0 == ~E_3~0); 1335#L634-1 assume !(0 == ~E_4~0); 1403#L639-1 assume 0 == ~E_5~0;~E_5~0 := 1; 1283#L644-1 havoc activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 1284#L282 assume 1 == ~m_pc~0; 1540#L283 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 1542#L293 is_master_triggered_#res := is_master_triggered_~__retres1~0; 1543#L294 activate_threads_#t~ret8 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 1582#L733 assume !(0 != activate_threads_~tmp~1); 1583#L733-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 1203#L301 assume !(1 == ~t1_pc~0); 1196#L301-2 is_transmit1_triggered_~__retres1~1 := 0; 1160#L312 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 1161#L313 activate_threads_#t~ret9 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 1228#L741 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 1212#L741-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 1213#L320 assume 1 == ~t2_pc~0; 1321#L321 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 1322#L331 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 1319#L332 activate_threads_#t~ret10 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 1320#L749 assume !(0 != activate_threads_~tmp___1~0); 1508#L749-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 1504#L339 assume !(1 == ~t3_pc~0); 1464#L339-2 is_transmit3_triggered_~__retres1~3 := 0; 1465#L350 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 1493#L351 activate_threads_#t~ret11 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 1494#L757 assume !(0 != activate_threads_~tmp___2~0); 1591#L757-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 1275#L358 assume 1 == ~t4_pc~0; 1276#L359 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 1230#L369 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 1272#L370 activate_threads_#t~ret12 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 1301#L765 assume !(0 != activate_threads_~tmp___3~0); 1302#L765-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 1303#L377 assume !(1 == ~t5_pc~0); 1209#L377-2 is_transmit5_triggered_~__retres1~5 := 0; 1208#L388 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 1205#L389 activate_threads_#t~ret13 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 1206#L773 assume !(0 != activate_threads_~tmp___4~0); 1435#L773-2 assume !(1 == ~M_E~0); 1436#L657-1 assume !(1 == ~T1_E~0); 1355#L662-1 assume !(1 == ~T2_E~0); 1356#L667-1 assume !(1 == ~T3_E~0); 1509#L672-1 assume !(1 == ~T4_E~0); 1281#L677-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 1282#L682-1 assume !(1 == ~E_M~0); 1073#L687-1 assume !(1 == ~E_1~0); 1074#L692-1 assume !(1 == ~E_2~0); 1214#L697-1 assume !(1 == ~E_3~0); 1215#L702-1 assume !(1 == ~E_4~0); 1437#L707-1 assume !(1 == ~E_5~0); 1116#L918-1 [2018-11-23 13:21:50,048 INFO L796 eck$LassoCheckResult]: Loop: 1116#L918-1 assume !false; 1117#L919 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret1, eval_#t~nondet2, eval_~tmp_ndt_1~0, eval_#t~nondet3, eval_~tmp_ndt_2~0, eval_#t~nondet4, eval_~tmp_ndt_3~0, eval_#t~nondet5, eval_~tmp_ndt_4~0, eval_#t~nondet6, eval_~tmp_ndt_5~0, eval_#t~nondet7, eval_~tmp_ndt_6~0, eval_~tmp~0;havoc eval_~tmp~0; 1290#L564 assume !false; 1409#L485 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 1348#L442 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 1261#L474 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 1347#L475 eval_#t~ret1 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret1;havoc eval_#t~ret1; 1307#L489 assume !(0 != eval_~tmp~0); 1309#L579 start_simulation_~kernel_st~0 := 2; 1399#L397-1 start_simulation_~kernel_st~0 := 3; 1297#L589-2 assume 0 == ~M_E~0;~M_E~0 := 1; 1255#L589-4 assume !(0 == ~T1_E~0); 1256#L594-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 1305#L599-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 1306#L604-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 1192#L609-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 1193#L614-3 assume 0 == ~E_M~0;~E_M~0 := 1; 1427#L619-3 assume 0 == ~E_1~0;~E_1~0 := 1; 1428#L624-3 assume 0 == ~E_2~0;~E_2~0 := 1; 1342#L629-3 assume !(0 == ~E_3~0); 1343#L634-3 assume 0 == ~E_4~0;~E_4~0 := 1; 1408#L639-3 assume 0 == ~E_5~0;~E_5~0 := 1; 1295#L644-3 havoc activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 1296#L282-21 assume 1 == ~m_pc~0; 1595#L283-7 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 1525#L293-7 is_master_triggered_#res := is_master_triggered_~__retres1~0; 1526#L294-7 activate_threads_#t~ret8 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 1532#L733-21 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 1533#L733-23 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 1099#L301-21 assume !(1 == ~t1_pc~0); 1097#L301-23 is_transmit1_triggered_~__retres1~1 := 0; 1098#L312-7 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 1145#L313-7 activate_threads_#t~ret9 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 1148#L741-21 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 1104#L741-23 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 1105#L320-21 assume !(1 == ~t2_pc~0); 1336#L320-23 is_transmit2_triggered_~__retres1~2 := 0; 1337#L331-7 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 1369#L332-7 activate_threads_#t~ret10 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 1373#L749-21 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 1374#L749-23 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 1382#L339-21 assume 1 == ~t3_pc~0; 1453#L340-7 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 1454#L350-7 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 1451#L351-7 activate_threads_#t~ret11 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 1452#L757-21 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 1495#L757-23 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 1496#L358-21 assume 1 == ~t4_pc~0; 1554#L359-7 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 1251#L369-7 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 1252#L370-7 activate_threads_#t~ret12 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 1553#L765-21 assume !(0 != activate_threads_~tmp___3~0); 1587#L765-23 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 1211#L377-21 assume 1 == ~t5_pc~0; 1131#L378-7 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 1132#L388-7 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 1126#L389-7 activate_threads_#t~ret13 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 1127#L773-21 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 1413#L773-23 assume 1 == ~M_E~0;~M_E~0 := 2; 1414#L657-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 1338#L662-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 1339#L667-3 assume !(1 == ~T3_E~0); 1406#L672-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 1287#L677-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 1288#L682-3 assume 1 == ~E_M~0;~E_M~0 := 2; 1080#L687-3 assume 1 == ~E_1~0;~E_1~0 := 2; 1081#L692-3 assume 1 == ~E_2~0;~E_2~0 := 2; 1219#L697-3 assume 1 == ~E_3~0;~E_3~0 := 2; 1220#L702-3 assume 1 == ~E_4~0;~E_4~0 := 2; 1439#L707-3 assume !(1 == ~E_5~0); 1440#L712-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 1313#L442-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 1264#L474-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 1349#L475-1 start_simulation_#t~ret15 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret15;havoc start_simulation_#t~ret15; 1350#L937 assume !(0 == start_simulation_~tmp~3); 1359#L937-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret14, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 1318#L442-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 1270#L474-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 1314#L475-2 stop_simulation_#t~ret14 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret14;havoc stop_simulation_#t~ret14; 1315#L892 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 1510#L899 stop_simulation_#res := stop_simulation_~__retres2~0; 1517#L900 start_simulation_#t~ret16 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret16;havoc start_simulation_#t~ret16; 1418#L950 assume !(0 != start_simulation_~tmp___0~1); 1116#L918-1 [2018-11-23 13:21:50,048 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 13:21:50,048 INFO L82 PathProgramCache]: Analyzing trace with hash 650506422, now seen corresponding path program 1 times [2018-11-23 13:21:50,048 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 13:21:50,048 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 13:21:50,049 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 13:21:50,049 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 13:21:50,049 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 13:21:50,058 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 13:21:50,082 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 13:21:50,082 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 13:21:50,082 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-23 13:21:50,082 INFO L799 eck$LassoCheckResult]: stem already infeasible [2018-11-23 13:21:50,083 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 13:21:50,083 INFO L82 PathProgramCache]: Analyzing trace with hash 1676480376, now seen corresponding path program 1 times [2018-11-23 13:21:50,083 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 13:21:50,083 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 13:21:50,084 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 13:21:50,084 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 13:21:50,084 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 13:21:50,100 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 13:21:50,142 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 13:21:50,143 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 13:21:50,143 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-23 13:21:50,143 INFO L811 eck$LassoCheckResult]: loop already infeasible [2018-11-23 13:21:50,143 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-23 13:21:50,144 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-23 13:21:50,144 INFO L87 Difference]: Start difference. First operand 527 states and 799 transitions. cyclomatic complexity: 273 Second operand 3 states. [2018-11-23 13:21:50,155 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 13:21:50,155 INFO L93 Difference]: Finished difference Result 527 states and 798 transitions. [2018-11-23 13:21:50,155 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-23 13:21:50,156 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 527 states and 798 transitions. [2018-11-23 13:21:50,160 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 452 [2018-11-23 13:21:50,163 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 527 states to 527 states and 798 transitions. [2018-11-23 13:21:50,164 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 527 [2018-11-23 13:21:50,164 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 527 [2018-11-23 13:21:50,164 INFO L73 IsDeterministic]: Start isDeterministic. Operand 527 states and 798 transitions. [2018-11-23 13:21:50,166 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-23 13:21:50,166 INFO L705 BuchiCegarLoop]: Abstraction has 527 states and 798 transitions. [2018-11-23 13:21:50,167 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 527 states and 798 transitions. [2018-11-23 13:21:50,176 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 527 to 527. [2018-11-23 13:21:50,176 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 527 states. [2018-11-23 13:21:50,178 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 527 states to 527 states and 798 transitions. [2018-11-23 13:21:50,179 INFO L728 BuchiCegarLoop]: Abstraction has 527 states and 798 transitions. [2018-11-23 13:21:50,179 INFO L608 BuchiCegarLoop]: Abstraction has 527 states and 798 transitions. [2018-11-23 13:21:50,179 INFO L442 BuchiCegarLoop]: ======== Iteration 3============ [2018-11-23 13:21:50,179 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 527 states and 798 transitions. [2018-11-23 13:21:50,182 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 452 [2018-11-23 13:21:50,182 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-23 13:21:50,182 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-23 13:21:50,184 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 13:21:50,184 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 13:21:50,184 INFO L794 eck$LassoCheckResult]: Stem: 2572#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 2522#L-1 havoc main_#res;havoc main_~__retres1~7;havoc main_~__retres1~7;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 2523#L881 havoc start_simulation_#t~ret15, start_simulation_#t~ret16, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 2456#L397 assume 1 == ~m_i~0;~m_st~0 := 0; 2457#L404-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 2378#L409-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 2379#L414-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 2458#L419-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 2328#L424-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 2329#L429-1 assume !(0 == ~M_E~0); 2354#L589-1 assume !(0 == ~T1_E~0); 2355#L594-1 assume !(0 == ~T2_E~0); 2143#L599-1 assume 0 == ~T3_E~0;~T3_E~0 := 1; 2144#L604-1 assume !(0 == ~T4_E~0); 2282#L609-1 assume !(0 == ~T5_E~0); 2283#L614-1 assume !(0 == ~E_M~0); 2502#L619-1 assume !(0 == ~E_1~0); 2503#L624-1 assume !(0 == ~E_2~0); 2395#L629-1 assume !(0 == ~E_3~0); 2396#L634-1 assume !(0 == ~E_4~0); 2464#L639-1 assume 0 == ~E_5~0;~E_5~0 := 1; 2344#L644-1 havoc activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 2345#L282 assume 1 == ~m_pc~0; 2601#L283 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 2603#L293 is_master_triggered_#res := is_master_triggered_~__retres1~0; 2604#L294 activate_threads_#t~ret8 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 2643#L733 assume !(0 != activate_threads_~tmp~1); 2644#L733-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 2264#L301 assume !(1 == ~t1_pc~0); 2257#L301-2 is_transmit1_triggered_~__retres1~1 := 0; 2221#L312 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 2222#L313 activate_threads_#t~ret9 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 2289#L741 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 2273#L741-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 2274#L320 assume 1 == ~t2_pc~0; 2382#L321 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 2383#L331 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 2380#L332 activate_threads_#t~ret10 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 2381#L749 assume !(0 != activate_threads_~tmp___1~0); 2569#L749-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 2565#L339 assume !(1 == ~t3_pc~0); 2525#L339-2 is_transmit3_triggered_~__retres1~3 := 0; 2526#L350 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 2554#L351 activate_threads_#t~ret11 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 2555#L757 assume !(0 != activate_threads_~tmp___2~0); 2652#L757-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 2336#L358 assume 1 == ~t4_pc~0; 2337#L359 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 2291#L369 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 2333#L370 activate_threads_#t~ret12 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 2362#L765 assume !(0 != activate_threads_~tmp___3~0); 2363#L765-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 2364#L377 assume !(1 == ~t5_pc~0); 2270#L377-2 is_transmit5_triggered_~__retres1~5 := 0; 2269#L388 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 2266#L389 activate_threads_#t~ret13 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 2267#L773 assume !(0 != activate_threads_~tmp___4~0); 2496#L773-2 assume !(1 == ~M_E~0); 2497#L657-1 assume !(1 == ~T1_E~0); 2416#L662-1 assume !(1 == ~T2_E~0); 2417#L667-1 assume !(1 == ~T3_E~0); 2570#L672-1 assume !(1 == ~T4_E~0); 2342#L677-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 2343#L682-1 assume !(1 == ~E_M~0); 2134#L687-1 assume !(1 == ~E_1~0); 2135#L692-1 assume !(1 == ~E_2~0); 2275#L697-1 assume !(1 == ~E_3~0); 2276#L702-1 assume !(1 == ~E_4~0); 2498#L707-1 assume !(1 == ~E_5~0); 2177#L918-1 [2018-11-23 13:21:50,185 INFO L796 eck$LassoCheckResult]: Loop: 2177#L918-1 assume !false; 2178#L919 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret1, eval_#t~nondet2, eval_~tmp_ndt_1~0, eval_#t~nondet3, eval_~tmp_ndt_2~0, eval_#t~nondet4, eval_~tmp_ndt_3~0, eval_#t~nondet5, eval_~tmp_ndt_4~0, eval_#t~nondet6, eval_~tmp_ndt_5~0, eval_#t~nondet7, eval_~tmp_ndt_6~0, eval_~tmp~0;havoc eval_~tmp~0; 2351#L564 assume !false; 2470#L485 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 2411#L442 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 2322#L474 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 2408#L475 eval_#t~ret1 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret1;havoc eval_#t~ret1; 2368#L489 assume !(0 != eval_~tmp~0); 2370#L579 start_simulation_~kernel_st~0 := 2; 2460#L397-1 start_simulation_~kernel_st~0 := 3; 2358#L589-2 assume 0 == ~M_E~0;~M_E~0 := 1; 2316#L589-4 assume !(0 == ~T1_E~0); 2317#L594-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 2366#L599-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 2367#L604-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 2253#L609-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 2254#L614-3 assume 0 == ~E_M~0;~E_M~0 := 1; 2488#L619-3 assume 0 == ~E_1~0;~E_1~0 := 1; 2489#L624-3 assume 0 == ~E_2~0;~E_2~0 := 1; 2403#L629-3 assume !(0 == ~E_3~0); 2404#L634-3 assume 0 == ~E_4~0;~E_4~0 := 1; 2469#L639-3 assume 0 == ~E_5~0;~E_5~0 := 1; 2356#L644-3 havoc activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 2357#L282-21 assume 1 == ~m_pc~0; 2656#L283-7 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 2586#L293-7 is_master_triggered_#res := is_master_triggered_~__retres1~0; 2587#L294-7 activate_threads_#t~ret8 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 2593#L733-21 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 2594#L733-23 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 2160#L301-21 assume 1 == ~t1_pc~0; 2161#L302-7 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 2159#L312-7 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 2206#L313-7 activate_threads_#t~ret9 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 2209#L741-21 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 2165#L741-23 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 2166#L320-21 assume !(1 == ~t2_pc~0); 2397#L320-23 is_transmit2_triggered_~__retres1~2 := 0; 2398#L331-7 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 2430#L332-7 activate_threads_#t~ret10 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 2434#L749-21 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 2435#L749-23 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 2443#L339-21 assume 1 == ~t3_pc~0; 2514#L340-7 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 2515#L350-7 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 2512#L351-7 activate_threads_#t~ret11 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 2513#L757-21 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 2556#L757-23 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 2557#L358-21 assume 1 == ~t4_pc~0; 2615#L359-7 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 2312#L369-7 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 2313#L370-7 activate_threads_#t~ret12 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 2614#L765-21 assume !(0 != activate_threads_~tmp___3~0); 2648#L765-23 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 2272#L377-21 assume 1 == ~t5_pc~0; 2192#L378-7 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 2193#L388-7 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 2187#L389-7 activate_threads_#t~ret13 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 2188#L773-21 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 2474#L773-23 assume 1 == ~M_E~0;~M_E~0 := 2; 2475#L657-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 2399#L662-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 2400#L667-3 assume !(1 == ~T3_E~0); 2467#L672-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 2348#L677-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 2349#L682-3 assume 1 == ~E_M~0;~E_M~0 := 2; 2141#L687-3 assume 1 == ~E_1~0;~E_1~0 := 2; 2142#L692-3 assume 1 == ~E_2~0;~E_2~0 := 2; 2280#L697-3 assume 1 == ~E_3~0;~E_3~0 := 2; 2281#L702-3 assume 1 == ~E_4~0;~E_4~0 := 2; 2500#L707-3 assume !(1 == ~E_5~0); 2501#L712-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 2374#L442-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 2325#L474-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 2409#L475-1 start_simulation_#t~ret15 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret15;havoc start_simulation_#t~ret15; 2410#L937 assume !(0 == start_simulation_~tmp~3); 2420#L937-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret14, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 2377#L442-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 2331#L474-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 2375#L475-2 stop_simulation_#t~ret14 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret14;havoc stop_simulation_#t~ret14; 2376#L892 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 2571#L899 stop_simulation_#res := stop_simulation_~__retres2~0; 2578#L900 start_simulation_#t~ret16 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret16;havoc start_simulation_#t~ret16; 2479#L950 assume !(0 != start_simulation_~tmp___0~1); 2177#L918-1 [2018-11-23 13:21:50,185 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 13:21:50,185 INFO L82 PathProgramCache]: Analyzing trace with hash 704899320, now seen corresponding path program 1 times [2018-11-23 13:21:50,185 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 13:21:50,185 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 13:21:50,186 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 13:21:50,186 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 13:21:50,187 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 13:21:50,193 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 13:21:50,216 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 13:21:50,216 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 13:21:50,217 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-23 13:21:50,217 INFO L799 eck$LassoCheckResult]: stem already infeasible [2018-11-23 13:21:50,217 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 13:21:50,217 INFO L82 PathProgramCache]: Analyzing trace with hash 1573679129, now seen corresponding path program 1 times [2018-11-23 13:21:50,217 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 13:21:50,217 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 13:21:50,218 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 13:21:50,218 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 13:21:50,218 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 13:21:50,227 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 13:21:50,272 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 13:21:50,272 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 13:21:50,272 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-23 13:21:50,272 INFO L811 eck$LassoCheckResult]: loop already infeasible [2018-11-23 13:21:50,273 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-23 13:21:50,273 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-23 13:21:50,273 INFO L87 Difference]: Start difference. First operand 527 states and 798 transitions. cyclomatic complexity: 272 Second operand 3 states. [2018-11-23 13:21:50,285 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 13:21:50,285 INFO L93 Difference]: Finished difference Result 527 states and 797 transitions. [2018-11-23 13:21:50,286 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-23 13:21:50,286 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 527 states and 797 transitions. [2018-11-23 13:21:50,290 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 452 [2018-11-23 13:21:50,292 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 527 states to 527 states and 797 transitions. [2018-11-23 13:21:50,293 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 527 [2018-11-23 13:21:50,293 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 527 [2018-11-23 13:21:50,293 INFO L73 IsDeterministic]: Start isDeterministic. Operand 527 states and 797 transitions. [2018-11-23 13:21:50,294 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-23 13:21:50,294 INFO L705 BuchiCegarLoop]: Abstraction has 527 states and 797 transitions. [2018-11-23 13:21:50,295 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 527 states and 797 transitions. [2018-11-23 13:21:50,301 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 527 to 527. [2018-11-23 13:21:50,302 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 527 states. [2018-11-23 13:21:50,303 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 527 states to 527 states and 797 transitions. [2018-11-23 13:21:50,304 INFO L728 BuchiCegarLoop]: Abstraction has 527 states and 797 transitions. [2018-11-23 13:21:50,304 INFO L608 BuchiCegarLoop]: Abstraction has 527 states and 797 transitions. [2018-11-23 13:21:50,304 INFO L442 BuchiCegarLoop]: ======== Iteration 4============ [2018-11-23 13:21:50,304 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 527 states and 797 transitions. [2018-11-23 13:21:50,306 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 452 [2018-11-23 13:21:50,306 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-23 13:21:50,306 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-23 13:21:50,308 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 13:21:50,308 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 13:21:50,308 INFO L794 eck$LassoCheckResult]: Stem: 3633#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 3583#L-1 havoc main_#res;havoc main_~__retres1~7;havoc main_~__retres1~7;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 3584#L881 havoc start_simulation_#t~ret15, start_simulation_#t~ret16, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 3517#L397 assume 1 == ~m_i~0;~m_st~0 := 0; 3518#L404-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 3439#L409-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 3440#L414-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 3519#L419-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 3389#L424-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 3390#L429-1 assume !(0 == ~M_E~0); 3415#L589-1 assume !(0 == ~T1_E~0); 3416#L594-1 assume !(0 == ~T2_E~0); 3204#L599-1 assume 0 == ~T3_E~0;~T3_E~0 := 1; 3205#L604-1 assume !(0 == ~T4_E~0); 3343#L609-1 assume !(0 == ~T5_E~0); 3344#L614-1 assume !(0 == ~E_M~0); 3563#L619-1 assume !(0 == ~E_1~0); 3564#L624-1 assume !(0 == ~E_2~0); 3456#L629-1 assume !(0 == ~E_3~0); 3457#L634-1 assume !(0 == ~E_4~0); 3525#L639-1 assume 0 == ~E_5~0;~E_5~0 := 1; 3405#L644-1 havoc activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 3406#L282 assume 1 == ~m_pc~0; 3662#L283 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 3664#L293 is_master_triggered_#res := is_master_triggered_~__retres1~0; 3665#L294 activate_threads_#t~ret8 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 3704#L733 assume !(0 != activate_threads_~tmp~1); 3705#L733-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 3325#L301 assume !(1 == ~t1_pc~0); 3318#L301-2 is_transmit1_triggered_~__retres1~1 := 0; 3282#L312 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 3283#L313 activate_threads_#t~ret9 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 3350#L741 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 3334#L741-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 3335#L320 assume 1 == ~t2_pc~0; 3443#L321 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 3444#L331 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 3441#L332 activate_threads_#t~ret10 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 3442#L749 assume !(0 != activate_threads_~tmp___1~0); 3630#L749-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 3626#L339 assume !(1 == ~t3_pc~0); 3586#L339-2 is_transmit3_triggered_~__retres1~3 := 0; 3587#L350 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 3615#L351 activate_threads_#t~ret11 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 3616#L757 assume !(0 != activate_threads_~tmp___2~0); 3713#L757-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 3397#L358 assume 1 == ~t4_pc~0; 3398#L359 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 3352#L369 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 3394#L370 activate_threads_#t~ret12 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 3423#L765 assume !(0 != activate_threads_~tmp___3~0); 3424#L765-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 3425#L377 assume !(1 == ~t5_pc~0); 3331#L377-2 is_transmit5_triggered_~__retres1~5 := 0; 3330#L388 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 3327#L389 activate_threads_#t~ret13 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 3328#L773 assume !(0 != activate_threads_~tmp___4~0); 3557#L773-2 assume !(1 == ~M_E~0); 3558#L657-1 assume !(1 == ~T1_E~0); 3477#L662-1 assume !(1 == ~T2_E~0); 3478#L667-1 assume !(1 == ~T3_E~0); 3631#L672-1 assume !(1 == ~T4_E~0); 3403#L677-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 3404#L682-1 assume !(1 == ~E_M~0); 3195#L687-1 assume !(1 == ~E_1~0); 3196#L692-1 assume !(1 == ~E_2~0); 3336#L697-1 assume !(1 == ~E_3~0); 3337#L702-1 assume !(1 == ~E_4~0); 3559#L707-1 assume !(1 == ~E_5~0); 3238#L918-1 [2018-11-23 13:21:50,308 INFO L796 eck$LassoCheckResult]: Loop: 3238#L918-1 assume !false; 3239#L919 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret1, eval_#t~nondet2, eval_~tmp_ndt_1~0, eval_#t~nondet3, eval_~tmp_ndt_2~0, eval_#t~nondet4, eval_~tmp_ndt_3~0, eval_#t~nondet5, eval_~tmp_ndt_4~0, eval_#t~nondet6, eval_~tmp_ndt_5~0, eval_#t~nondet7, eval_~tmp_ndt_6~0, eval_~tmp~0;havoc eval_~tmp~0; 3412#L564 assume !false; 3531#L485 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 3472#L442 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 3383#L474 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 3469#L475 eval_#t~ret1 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret1;havoc eval_#t~ret1; 3429#L489 assume !(0 != eval_~tmp~0); 3431#L579 start_simulation_~kernel_st~0 := 2; 3521#L397-1 start_simulation_~kernel_st~0 := 3; 3419#L589-2 assume 0 == ~M_E~0;~M_E~0 := 1; 3377#L589-4 assume !(0 == ~T1_E~0); 3378#L594-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 3427#L599-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 3428#L604-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 3314#L609-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 3315#L614-3 assume 0 == ~E_M~0;~E_M~0 := 1; 3549#L619-3 assume 0 == ~E_1~0;~E_1~0 := 1; 3550#L624-3 assume 0 == ~E_2~0;~E_2~0 := 1; 3464#L629-3 assume !(0 == ~E_3~0); 3465#L634-3 assume 0 == ~E_4~0;~E_4~0 := 1; 3530#L639-3 assume 0 == ~E_5~0;~E_5~0 := 1; 3417#L644-3 havoc activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 3418#L282-21 assume 1 == ~m_pc~0; 3717#L283-7 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 3647#L293-7 is_master_triggered_#res := is_master_triggered_~__retres1~0; 3648#L294-7 activate_threads_#t~ret8 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 3654#L733-21 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 3655#L733-23 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 3221#L301-21 assume !(1 == ~t1_pc~0); 3219#L301-23 is_transmit1_triggered_~__retres1~1 := 0; 3220#L312-7 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 3267#L313-7 activate_threads_#t~ret9 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 3270#L741-21 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 3226#L741-23 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 3227#L320-21 assume !(1 == ~t2_pc~0); 3458#L320-23 is_transmit2_triggered_~__retres1~2 := 0; 3459#L331-7 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 3491#L332-7 activate_threads_#t~ret10 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 3495#L749-21 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 3496#L749-23 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 3504#L339-21 assume 1 == ~t3_pc~0; 3575#L340-7 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 3576#L350-7 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 3573#L351-7 activate_threads_#t~ret11 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 3574#L757-21 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 3617#L757-23 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 3618#L358-21 assume 1 == ~t4_pc~0; 3676#L359-7 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 3373#L369-7 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 3374#L370-7 activate_threads_#t~ret12 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 3674#L765-21 assume !(0 != activate_threads_~tmp___3~0); 3709#L765-23 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 3333#L377-21 assume 1 == ~t5_pc~0; 3250#L378-7 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 3251#L388-7 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 3248#L389-7 activate_threads_#t~ret13 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 3249#L773-21 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 3535#L773-23 assume 1 == ~M_E~0;~M_E~0 := 2; 3536#L657-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 3460#L662-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 3461#L667-3 assume !(1 == ~T3_E~0); 3528#L672-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 3409#L677-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 3410#L682-3 assume 1 == ~E_M~0;~E_M~0 := 2; 3202#L687-3 assume 1 == ~E_1~0;~E_1~0 := 2; 3203#L692-3 assume 1 == ~E_2~0;~E_2~0 := 2; 3341#L697-3 assume 1 == ~E_3~0;~E_3~0 := 2; 3342#L702-3 assume 1 == ~E_4~0;~E_4~0 := 2; 3561#L707-3 assume !(1 == ~E_5~0); 3562#L712-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 3435#L442-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 3386#L474-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 3470#L475-1 start_simulation_#t~ret15 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret15;havoc start_simulation_#t~ret15; 3471#L937 assume !(0 == start_simulation_~tmp~3); 3481#L937-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret14, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 3438#L442-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 3392#L474-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 3436#L475-2 stop_simulation_#t~ret14 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret14;havoc stop_simulation_#t~ret14; 3437#L892 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 3632#L899 stop_simulation_#res := stop_simulation_~__retres2~0; 3639#L900 start_simulation_#t~ret16 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret16;havoc start_simulation_#t~ret16; 3540#L950 assume !(0 != start_simulation_~tmp___0~1); 3238#L918-1 [2018-11-23 13:21:50,309 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 13:21:50,309 INFO L82 PathProgramCache]: Analyzing trace with hash 1122295926, now seen corresponding path program 1 times [2018-11-23 13:21:50,309 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 13:21:50,309 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 13:21:50,310 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 13:21:50,310 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 13:21:50,310 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 13:21:50,316 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 13:21:50,348 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 13:21:50,349 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 13:21:50,349 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-23 13:21:50,349 INFO L799 eck$LassoCheckResult]: stem already infeasible [2018-11-23 13:21:50,349 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 13:21:50,350 INFO L82 PathProgramCache]: Analyzing trace with hash 1676480376, now seen corresponding path program 2 times [2018-11-23 13:21:50,350 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 13:21:50,350 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 13:21:50,350 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 13:21:50,351 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 13:21:50,351 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 13:21:50,358 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 13:21:50,392 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 13:21:50,393 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 13:21:50,393 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-23 13:21:50,393 INFO L811 eck$LassoCheckResult]: loop already infeasible [2018-11-23 13:21:50,393 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-23 13:21:50,393 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-23 13:21:50,393 INFO L87 Difference]: Start difference. First operand 527 states and 797 transitions. cyclomatic complexity: 271 Second operand 3 states. [2018-11-23 13:21:50,407 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 13:21:50,407 INFO L93 Difference]: Finished difference Result 527 states and 796 transitions. [2018-11-23 13:21:50,408 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-23 13:21:50,408 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 527 states and 796 transitions. [2018-11-23 13:21:50,411 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 452 [2018-11-23 13:21:50,413 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 527 states to 527 states and 796 transitions. [2018-11-23 13:21:50,413 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 527 [2018-11-23 13:21:50,414 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 527 [2018-11-23 13:21:50,414 INFO L73 IsDeterministic]: Start isDeterministic. Operand 527 states and 796 transitions. [2018-11-23 13:21:50,415 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-23 13:21:50,415 INFO L705 BuchiCegarLoop]: Abstraction has 527 states and 796 transitions. [2018-11-23 13:21:50,415 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 527 states and 796 transitions. [2018-11-23 13:21:50,421 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 527 to 527. [2018-11-23 13:21:50,421 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 527 states. [2018-11-23 13:21:50,422 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 527 states to 527 states and 796 transitions. [2018-11-23 13:21:50,422 INFO L728 BuchiCegarLoop]: Abstraction has 527 states and 796 transitions. [2018-11-23 13:21:50,422 INFO L608 BuchiCegarLoop]: Abstraction has 527 states and 796 transitions. [2018-11-23 13:21:50,422 INFO L442 BuchiCegarLoop]: ======== Iteration 5============ [2018-11-23 13:21:50,423 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 527 states and 796 transitions. [2018-11-23 13:21:50,424 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 452 [2018-11-23 13:21:50,425 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-23 13:21:50,425 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-23 13:21:50,426 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 13:21:50,426 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 13:21:50,426 INFO L794 eck$LassoCheckResult]: Stem: 4694#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 4644#L-1 havoc main_#res;havoc main_~__retres1~7;havoc main_~__retres1~7;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 4645#L881 havoc start_simulation_#t~ret15, start_simulation_#t~ret16, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 4578#L397 assume 1 == ~m_i~0;~m_st~0 := 0; 4579#L404-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 4500#L409-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 4501#L414-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 4580#L419-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 4450#L424-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 4451#L429-1 assume !(0 == ~M_E~0); 4476#L589-1 assume !(0 == ~T1_E~0); 4477#L594-1 assume !(0 == ~T2_E~0); 4265#L599-1 assume 0 == ~T3_E~0;~T3_E~0 := 1; 4266#L604-1 assume !(0 == ~T4_E~0); 4404#L609-1 assume !(0 == ~T5_E~0); 4405#L614-1 assume !(0 == ~E_M~0); 4624#L619-1 assume !(0 == ~E_1~0); 4625#L624-1 assume !(0 == ~E_2~0); 4517#L629-1 assume !(0 == ~E_3~0); 4518#L634-1 assume !(0 == ~E_4~0); 4586#L639-1 assume 0 == ~E_5~0;~E_5~0 := 1; 4466#L644-1 havoc activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 4467#L282 assume 1 == ~m_pc~0; 4723#L283 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 4725#L293 is_master_triggered_#res := is_master_triggered_~__retres1~0; 4726#L294 activate_threads_#t~ret8 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 4765#L733 assume !(0 != activate_threads_~tmp~1); 4766#L733-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 4386#L301 assume !(1 == ~t1_pc~0); 4379#L301-2 is_transmit1_triggered_~__retres1~1 := 0; 4346#L312 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 4347#L313 activate_threads_#t~ret9 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 4411#L741 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 4395#L741-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 4396#L320 assume 1 == ~t2_pc~0; 4504#L321 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 4505#L331 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 4502#L332 activate_threads_#t~ret10 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 4503#L749 assume !(0 != activate_threads_~tmp___1~0); 4691#L749-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 4687#L339 assume !(1 == ~t3_pc~0); 4647#L339-2 is_transmit3_triggered_~__retres1~3 := 0; 4648#L350 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 4676#L351 activate_threads_#t~ret11 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 4677#L757 assume !(0 != activate_threads_~tmp___2~0); 4774#L757-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 4458#L358 assume 1 == ~t4_pc~0; 4459#L359 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 4413#L369 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 4457#L370 activate_threads_#t~ret12 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 4484#L765 assume !(0 != activate_threads_~tmp___3~0); 4485#L765-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 4486#L377 assume !(1 == ~t5_pc~0); 4392#L377-2 is_transmit5_triggered_~__retres1~5 := 0; 4391#L388 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 4388#L389 activate_threads_#t~ret13 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 4389#L773 assume !(0 != activate_threads_~tmp___4~0); 4618#L773-2 assume !(1 == ~M_E~0); 4619#L657-1 assume !(1 == ~T1_E~0); 4538#L662-1 assume !(1 == ~T2_E~0); 4539#L667-1 assume !(1 == ~T3_E~0); 4692#L672-1 assume !(1 == ~T4_E~0); 4464#L677-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 4465#L682-1 assume !(1 == ~E_M~0); 4256#L687-1 assume !(1 == ~E_1~0); 4257#L692-1 assume !(1 == ~E_2~0); 4397#L697-1 assume !(1 == ~E_3~0); 4398#L702-1 assume !(1 == ~E_4~0); 4621#L707-1 assume !(1 == ~E_5~0); 4299#L918-1 [2018-11-23 13:21:50,426 INFO L796 eck$LassoCheckResult]: Loop: 4299#L918-1 assume !false; 4300#L919 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret1, eval_#t~nondet2, eval_~tmp_ndt_1~0, eval_#t~nondet3, eval_~tmp_ndt_2~0, eval_#t~nondet4, eval_~tmp_ndt_3~0, eval_#t~nondet5, eval_~tmp_ndt_4~0, eval_#t~nondet6, eval_~tmp_ndt_5~0, eval_#t~nondet7, eval_~tmp_ndt_6~0, eval_~tmp~0;havoc eval_~tmp~0; 4473#L564 assume !false; 4592#L485 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 4533#L442 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 4444#L474 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 4530#L475 eval_#t~ret1 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret1;havoc eval_#t~ret1; 4490#L489 assume !(0 != eval_~tmp~0); 4492#L579 start_simulation_~kernel_st~0 := 2; 4582#L397-1 start_simulation_~kernel_st~0 := 3; 4480#L589-2 assume 0 == ~M_E~0;~M_E~0 := 1; 4438#L589-4 assume !(0 == ~T1_E~0); 4439#L594-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 4488#L599-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 4489#L604-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 4375#L609-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 4376#L614-3 assume 0 == ~E_M~0;~E_M~0 := 1; 4610#L619-3 assume 0 == ~E_1~0;~E_1~0 := 1; 4611#L624-3 assume 0 == ~E_2~0;~E_2~0 := 1; 4525#L629-3 assume !(0 == ~E_3~0); 4526#L634-3 assume 0 == ~E_4~0;~E_4~0 := 1; 4591#L639-3 assume 0 == ~E_5~0;~E_5~0 := 1; 4478#L644-3 havoc activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 4479#L282-21 assume 1 == ~m_pc~0; 4778#L283-7 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 4708#L293-7 is_master_triggered_#res := is_master_triggered_~__retres1~0; 4709#L294-7 activate_threads_#t~ret8 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 4715#L733-21 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 4716#L733-23 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 4282#L301-21 assume !(1 == ~t1_pc~0); 4280#L301-23 is_transmit1_triggered_~__retres1~1 := 0; 4281#L312-7 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 4328#L313-7 activate_threads_#t~ret9 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 4331#L741-21 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 4287#L741-23 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 4288#L320-21 assume !(1 == ~t2_pc~0); 4519#L320-23 is_transmit2_triggered_~__retres1~2 := 0; 4520#L331-7 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 4552#L332-7 activate_threads_#t~ret10 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 4556#L749-21 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 4557#L749-23 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 4565#L339-21 assume 1 == ~t3_pc~0; 4636#L340-7 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 4637#L350-7 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 4634#L351-7 activate_threads_#t~ret11 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 4635#L757-21 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 4678#L757-23 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 4679#L358-21 assume 1 == ~t4_pc~0; 4737#L359-7 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 4434#L369-7 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 4435#L370-7 activate_threads_#t~ret12 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 4735#L765-21 assume !(0 != activate_threads_~tmp___3~0); 4770#L765-23 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 4394#L377-21 assume 1 == ~t5_pc~0; 4311#L378-7 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 4312#L388-7 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 4309#L389-7 activate_threads_#t~ret13 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 4310#L773-21 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 4596#L773-23 assume 1 == ~M_E~0;~M_E~0 := 2; 4597#L657-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 4521#L662-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 4522#L667-3 assume !(1 == ~T3_E~0); 4589#L672-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 4470#L677-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 4471#L682-3 assume 1 == ~E_M~0;~E_M~0 := 2; 4263#L687-3 assume 1 == ~E_1~0;~E_1~0 := 2; 4264#L692-3 assume 1 == ~E_2~0;~E_2~0 := 2; 4402#L697-3 assume 1 == ~E_3~0;~E_3~0 := 2; 4403#L702-3 assume 1 == ~E_4~0;~E_4~0 := 2; 4622#L707-3 assume !(1 == ~E_5~0); 4623#L712-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 4496#L442-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 4447#L474-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 4531#L475-1 start_simulation_#t~ret15 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret15;havoc start_simulation_#t~ret15; 4532#L937 assume !(0 == start_simulation_~tmp~3); 4542#L937-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret14, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 4499#L442-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 4453#L474-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 4497#L475-2 stop_simulation_#t~ret14 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret14;havoc stop_simulation_#t~ret14; 4498#L892 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 4693#L899 stop_simulation_#res := stop_simulation_~__retres2~0; 4700#L900 start_simulation_#t~ret16 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret16;havoc start_simulation_#t~ret16; 4601#L950 assume !(0 != start_simulation_~tmp___0~1); 4299#L918-1 [2018-11-23 13:21:50,426 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 13:21:50,427 INFO L82 PathProgramCache]: Analyzing trace with hash 443023672, now seen corresponding path program 1 times [2018-11-23 13:21:50,427 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 13:21:50,427 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 13:21:50,427 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 13:21:50,427 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-23 13:21:50,428 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 13:21:50,435 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 13:21:50,456 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 13:21:50,457 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 13:21:50,457 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-23 13:21:50,457 INFO L799 eck$LassoCheckResult]: stem already infeasible [2018-11-23 13:21:50,457 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 13:21:50,458 INFO L82 PathProgramCache]: Analyzing trace with hash 1676480376, now seen corresponding path program 3 times [2018-11-23 13:21:50,458 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 13:21:50,458 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 13:21:50,458 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 13:21:50,459 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 13:21:50,459 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 13:21:50,464 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 13:21:50,490 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 13:21:50,490 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 13:21:50,490 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-23 13:21:50,491 INFO L811 eck$LassoCheckResult]: loop already infeasible [2018-11-23 13:21:50,491 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-23 13:21:50,491 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-23 13:21:50,491 INFO L87 Difference]: Start difference. First operand 527 states and 796 transitions. cyclomatic complexity: 270 Second operand 3 states. [2018-11-23 13:21:50,503 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 13:21:50,503 INFO L93 Difference]: Finished difference Result 527 states and 795 transitions. [2018-11-23 13:21:50,504 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-23 13:21:50,504 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 527 states and 795 transitions. [2018-11-23 13:21:50,507 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 452 [2018-11-23 13:21:50,509 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 527 states to 527 states and 795 transitions. [2018-11-23 13:21:50,509 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 527 [2018-11-23 13:21:50,510 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 527 [2018-11-23 13:21:50,510 INFO L73 IsDeterministic]: Start isDeterministic. Operand 527 states and 795 transitions. [2018-11-23 13:21:50,511 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-23 13:21:50,511 INFO L705 BuchiCegarLoop]: Abstraction has 527 states and 795 transitions. [2018-11-23 13:21:50,512 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 527 states and 795 transitions. [2018-11-23 13:21:50,518 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 527 to 527. [2018-11-23 13:21:50,519 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 527 states. [2018-11-23 13:21:50,520 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 527 states to 527 states and 795 transitions. [2018-11-23 13:21:50,520 INFO L728 BuchiCegarLoop]: Abstraction has 527 states and 795 transitions. [2018-11-23 13:21:50,520 INFO L608 BuchiCegarLoop]: Abstraction has 527 states and 795 transitions. [2018-11-23 13:21:50,520 INFO L442 BuchiCegarLoop]: ======== Iteration 6============ [2018-11-23 13:21:50,521 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 527 states and 795 transitions. [2018-11-23 13:21:50,523 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 452 [2018-11-23 13:21:50,523 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-23 13:21:50,523 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-23 13:21:50,524 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 13:21:50,524 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 13:21:50,525 INFO L794 eck$LassoCheckResult]: Stem: 5755#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 5705#L-1 havoc main_#res;havoc main_~__retres1~7;havoc main_~__retres1~7;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 5706#L881 havoc start_simulation_#t~ret15, start_simulation_#t~ret16, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 5639#L397 assume 1 == ~m_i~0;~m_st~0 := 0; 5640#L404-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 5561#L409-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 5562#L414-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 5641#L419-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 5511#L424-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 5512#L429-1 assume !(0 == ~M_E~0); 5537#L589-1 assume !(0 == ~T1_E~0); 5538#L594-1 assume !(0 == ~T2_E~0); 5326#L599-1 assume 0 == ~T3_E~0;~T3_E~0 := 1; 5327#L604-1 assume !(0 == ~T4_E~0); 5465#L609-1 assume !(0 == ~T5_E~0); 5466#L614-1 assume !(0 == ~E_M~0); 5685#L619-1 assume !(0 == ~E_1~0); 5686#L624-1 assume !(0 == ~E_2~0); 5578#L629-1 assume !(0 == ~E_3~0); 5579#L634-1 assume !(0 == ~E_4~0); 5647#L639-1 assume 0 == ~E_5~0;~E_5~0 := 1; 5527#L644-1 havoc activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 5528#L282 assume 1 == ~m_pc~0; 5784#L283 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 5786#L293 is_master_triggered_#res := is_master_triggered_~__retres1~0; 5787#L294 activate_threads_#t~ret8 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 5826#L733 assume !(0 != activate_threads_~tmp~1); 5827#L733-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 5447#L301 assume !(1 == ~t1_pc~0); 5440#L301-2 is_transmit1_triggered_~__retres1~1 := 0; 5407#L312 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 5408#L313 activate_threads_#t~ret9 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 5472#L741 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 5456#L741-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 5457#L320 assume 1 == ~t2_pc~0; 5565#L321 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 5566#L331 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 5563#L332 activate_threads_#t~ret10 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 5564#L749 assume !(0 != activate_threads_~tmp___1~0); 5752#L749-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 5748#L339 assume !(1 == ~t3_pc~0); 5708#L339-2 is_transmit3_triggered_~__retres1~3 := 0; 5709#L350 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 5737#L351 activate_threads_#t~ret11 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 5738#L757 assume !(0 != activate_threads_~tmp___2~0); 5835#L757-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 5519#L358 assume 1 == ~t4_pc~0; 5520#L359 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 5474#L369 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 5518#L370 activate_threads_#t~ret12 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 5545#L765 assume !(0 != activate_threads_~tmp___3~0); 5546#L765-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 5547#L377 assume !(1 == ~t5_pc~0); 5453#L377-2 is_transmit5_triggered_~__retres1~5 := 0; 5452#L388 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 5449#L389 activate_threads_#t~ret13 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 5450#L773 assume !(0 != activate_threads_~tmp___4~0); 5679#L773-2 assume !(1 == ~M_E~0); 5680#L657-1 assume !(1 == ~T1_E~0); 5599#L662-1 assume !(1 == ~T2_E~0); 5600#L667-1 assume !(1 == ~T3_E~0); 5753#L672-1 assume !(1 == ~T4_E~0); 5525#L677-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 5526#L682-1 assume !(1 == ~E_M~0); 5317#L687-1 assume !(1 == ~E_1~0); 5318#L692-1 assume !(1 == ~E_2~0); 5458#L697-1 assume !(1 == ~E_3~0); 5459#L702-1 assume !(1 == ~E_4~0); 5682#L707-1 assume !(1 == ~E_5~0); 5360#L918-1 [2018-11-23 13:21:50,525 INFO L796 eck$LassoCheckResult]: Loop: 5360#L918-1 assume !false; 5361#L919 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret1, eval_#t~nondet2, eval_~tmp_ndt_1~0, eval_#t~nondet3, eval_~tmp_ndt_2~0, eval_#t~nondet4, eval_~tmp_ndt_3~0, eval_#t~nondet5, eval_~tmp_ndt_4~0, eval_#t~nondet6, eval_~tmp_ndt_5~0, eval_#t~nondet7, eval_~tmp_ndt_6~0, eval_~tmp~0;havoc eval_~tmp~0; 5536#L564 assume !false; 5653#L485 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 5594#L442 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 5505#L474 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 5591#L475 eval_#t~ret1 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret1;havoc eval_#t~ret1; 5551#L489 assume !(0 != eval_~tmp~0); 5553#L579 start_simulation_~kernel_st~0 := 2; 5643#L397-1 start_simulation_~kernel_st~0 := 3; 5541#L589-2 assume 0 == ~M_E~0;~M_E~0 := 1; 5499#L589-4 assume !(0 == ~T1_E~0); 5500#L594-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 5549#L599-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 5550#L604-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 5436#L609-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 5437#L614-3 assume 0 == ~E_M~0;~E_M~0 := 1; 5671#L619-3 assume 0 == ~E_1~0;~E_1~0 := 1; 5672#L624-3 assume 0 == ~E_2~0;~E_2~0 := 1; 5586#L629-3 assume !(0 == ~E_3~0); 5587#L634-3 assume 0 == ~E_4~0;~E_4~0 := 1; 5652#L639-3 assume 0 == ~E_5~0;~E_5~0 := 1; 5539#L644-3 havoc activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 5540#L282-21 assume !(1 == ~m_pc~0); 5840#L282-23 is_master_triggered_~__retres1~0 := 0; 5769#L293-7 is_master_triggered_#res := is_master_triggered_~__retres1~0; 5770#L294-7 activate_threads_#t~ret8 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 5776#L733-21 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 5777#L733-23 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 5343#L301-21 assume 1 == ~t1_pc~0; 5344#L302-7 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 5342#L312-7 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 5389#L313-7 activate_threads_#t~ret9 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 5392#L741-21 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 5348#L741-23 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 5349#L320-21 assume !(1 == ~t2_pc~0); 5580#L320-23 is_transmit2_triggered_~__retres1~2 := 0; 5581#L331-7 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 5613#L332-7 activate_threads_#t~ret10 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 5617#L749-21 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 5618#L749-23 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 5626#L339-21 assume 1 == ~t3_pc~0; 5697#L340-7 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 5698#L350-7 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 5695#L351-7 activate_threads_#t~ret11 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 5696#L757-21 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 5739#L757-23 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 5740#L358-21 assume 1 == ~t4_pc~0; 5798#L359-7 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 5495#L369-7 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 5496#L370-7 activate_threads_#t~ret12 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 5796#L765-21 assume !(0 != activate_threads_~tmp___3~0); 5831#L765-23 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 5455#L377-21 assume 1 == ~t5_pc~0; 5372#L378-7 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 5373#L388-7 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 5370#L389-7 activate_threads_#t~ret13 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 5371#L773-21 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 5657#L773-23 assume 1 == ~M_E~0;~M_E~0 := 2; 5658#L657-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 5582#L662-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 5583#L667-3 assume !(1 == ~T3_E~0); 5650#L672-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 5531#L677-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 5532#L682-3 assume 1 == ~E_M~0;~E_M~0 := 2; 5324#L687-3 assume 1 == ~E_1~0;~E_1~0 := 2; 5325#L692-3 assume 1 == ~E_2~0;~E_2~0 := 2; 5463#L697-3 assume 1 == ~E_3~0;~E_3~0 := 2; 5464#L702-3 assume 1 == ~E_4~0;~E_4~0 := 2; 5683#L707-3 assume !(1 == ~E_5~0); 5684#L712-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 5557#L442-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 5508#L474-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 5592#L475-1 start_simulation_#t~ret15 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret15;havoc start_simulation_#t~ret15; 5593#L937 assume !(0 == start_simulation_~tmp~3); 5603#L937-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret14, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 5560#L442-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 5514#L474-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 5558#L475-2 stop_simulation_#t~ret14 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret14;havoc stop_simulation_#t~ret14; 5559#L892 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 5754#L899 stop_simulation_#res := stop_simulation_~__retres2~0; 5761#L900 start_simulation_#t~ret16 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret16;havoc start_simulation_#t~ret16; 5662#L950 assume !(0 != start_simulation_~tmp___0~1); 5360#L918-1 [2018-11-23 13:21:50,525 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 13:21:50,525 INFO L82 PathProgramCache]: Analyzing trace with hash -1518550986, now seen corresponding path program 1 times [2018-11-23 13:21:50,526 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 13:21:50,526 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 13:21:50,526 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 13:21:50,527 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-23 13:21:50,527 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 13:21:50,532 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 13:21:50,559 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 13:21:50,559 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 13:21:50,559 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2018-11-23 13:21:50,559 INFO L799 eck$LassoCheckResult]: stem already infeasible [2018-11-23 13:21:50,560 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 13:21:50,560 INFO L82 PathProgramCache]: Analyzing trace with hash -332805064, now seen corresponding path program 1 times [2018-11-23 13:21:50,560 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 13:21:50,560 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 13:21:50,561 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 13:21:50,561 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 13:21:50,561 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 13:21:50,588 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 13:21:50,613 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 13:21:50,613 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 13:21:50,614 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-23 13:21:50,614 INFO L811 eck$LassoCheckResult]: loop already infeasible [2018-11-23 13:21:50,614 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-23 13:21:50,614 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-23 13:21:50,614 INFO L87 Difference]: Start difference. First operand 527 states and 795 transitions. cyclomatic complexity: 269 Second operand 3 states. [2018-11-23 13:21:50,634 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 13:21:50,634 INFO L93 Difference]: Finished difference Result 527 states and 790 transitions. [2018-11-23 13:21:50,635 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-23 13:21:50,635 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 527 states and 790 transitions. [2018-11-23 13:21:50,637 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 452 [2018-11-23 13:21:50,639 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 527 states to 527 states and 790 transitions. [2018-11-23 13:21:50,639 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 527 [2018-11-23 13:21:50,640 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 527 [2018-11-23 13:21:50,640 INFO L73 IsDeterministic]: Start isDeterministic. Operand 527 states and 790 transitions. [2018-11-23 13:21:50,641 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-23 13:21:50,641 INFO L705 BuchiCegarLoop]: Abstraction has 527 states and 790 transitions. [2018-11-23 13:21:50,641 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 527 states and 790 transitions. [2018-11-23 13:21:50,646 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 527 to 527. [2018-11-23 13:21:50,646 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 527 states. [2018-11-23 13:21:50,647 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 527 states to 527 states and 790 transitions. [2018-11-23 13:21:50,648 INFO L728 BuchiCegarLoop]: Abstraction has 527 states and 790 transitions. [2018-11-23 13:21:50,648 INFO L608 BuchiCegarLoop]: Abstraction has 527 states and 790 transitions. [2018-11-23 13:21:50,648 INFO L442 BuchiCegarLoop]: ======== Iteration 7============ [2018-11-23 13:21:50,648 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 527 states and 790 transitions. [2018-11-23 13:21:50,650 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 452 [2018-11-23 13:21:50,650 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-23 13:21:50,650 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-23 13:21:50,651 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 13:21:50,651 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 13:21:50,651 INFO L794 eck$LassoCheckResult]: Stem: 6816#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 6766#L-1 havoc main_#res;havoc main_~__retres1~7;havoc main_~__retres1~7;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 6767#L881 havoc start_simulation_#t~ret15, start_simulation_#t~ret16, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 6700#L397 assume 1 == ~m_i~0;~m_st~0 := 0; 6701#L404-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 6622#L409-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 6623#L414-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 6702#L419-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 6572#L424-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 6573#L429-1 assume !(0 == ~M_E~0); 6598#L589-1 assume !(0 == ~T1_E~0); 6599#L594-1 assume !(0 == ~T2_E~0); 6387#L599-1 assume !(0 == ~T3_E~0); 6388#L604-1 assume !(0 == ~T4_E~0); 6526#L609-1 assume !(0 == ~T5_E~0); 6527#L614-1 assume !(0 == ~E_M~0); 6746#L619-1 assume !(0 == ~E_1~0); 6747#L624-1 assume !(0 == ~E_2~0); 6639#L629-1 assume !(0 == ~E_3~0); 6640#L634-1 assume !(0 == ~E_4~0); 6708#L639-1 assume 0 == ~E_5~0;~E_5~0 := 1; 6588#L644-1 havoc activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 6589#L282 assume 1 == ~m_pc~0; 6845#L283 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 6847#L293 is_master_triggered_#res := is_master_triggered_~__retres1~0; 6848#L294 activate_threads_#t~ret8 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 6887#L733 assume !(0 != activate_threads_~tmp~1); 6888#L733-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 6508#L301 assume !(1 == ~t1_pc~0); 6501#L301-2 is_transmit1_triggered_~__retres1~1 := 0; 6468#L312 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 6469#L313 activate_threads_#t~ret9 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 6533#L741 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 6517#L741-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 6518#L320 assume 1 == ~t2_pc~0; 6626#L321 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 6627#L331 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 6624#L332 activate_threads_#t~ret10 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 6625#L749 assume !(0 != activate_threads_~tmp___1~0); 6813#L749-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 6809#L339 assume !(1 == ~t3_pc~0); 6769#L339-2 is_transmit3_triggered_~__retres1~3 := 0; 6770#L350 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 6798#L351 activate_threads_#t~ret11 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 6799#L757 assume !(0 != activate_threads_~tmp___2~0); 6896#L757-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 6580#L358 assume 1 == ~t4_pc~0; 6581#L359 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 6535#L369 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 6579#L370 activate_threads_#t~ret12 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 6606#L765 assume !(0 != activate_threads_~tmp___3~0); 6607#L765-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 6608#L377 assume !(1 == ~t5_pc~0); 6514#L377-2 is_transmit5_triggered_~__retres1~5 := 0; 6513#L388 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 6510#L389 activate_threads_#t~ret13 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 6511#L773 assume !(0 != activate_threads_~tmp___4~0); 6740#L773-2 assume !(1 == ~M_E~0); 6741#L657-1 assume !(1 == ~T1_E~0); 6660#L662-1 assume !(1 == ~T2_E~0); 6661#L667-1 assume !(1 == ~T3_E~0); 6814#L672-1 assume !(1 == ~T4_E~0); 6586#L677-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 6587#L682-1 assume !(1 == ~E_M~0); 6378#L687-1 assume !(1 == ~E_1~0); 6379#L692-1 assume !(1 == ~E_2~0); 6519#L697-1 assume !(1 == ~E_3~0); 6520#L702-1 assume !(1 == ~E_4~0); 6743#L707-1 assume !(1 == ~E_5~0); 6421#L918-1 [2018-11-23 13:21:50,651 INFO L796 eck$LassoCheckResult]: Loop: 6421#L918-1 assume !false; 6422#L919 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret1, eval_#t~nondet2, eval_~tmp_ndt_1~0, eval_#t~nondet3, eval_~tmp_ndt_2~0, eval_#t~nondet4, eval_~tmp_ndt_3~0, eval_#t~nondet5, eval_~tmp_ndt_4~0, eval_#t~nondet6, eval_~tmp_ndt_5~0, eval_#t~nondet7, eval_~tmp_ndt_6~0, eval_~tmp~0;havoc eval_~tmp~0; 6597#L564 assume !false; 6714#L485 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 6655#L442 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 6566#L474 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 6652#L475 eval_#t~ret1 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret1;havoc eval_#t~ret1; 6612#L489 assume !(0 != eval_~tmp~0); 6614#L579 start_simulation_~kernel_st~0 := 2; 6704#L397-1 start_simulation_~kernel_st~0 := 3; 6602#L589-2 assume 0 == ~M_E~0;~M_E~0 := 1; 6560#L589-4 assume !(0 == ~T1_E~0); 6561#L594-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 6610#L599-3 assume !(0 == ~T3_E~0); 6611#L604-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 6497#L609-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 6498#L614-3 assume 0 == ~E_M~0;~E_M~0 := 1; 6732#L619-3 assume 0 == ~E_1~0;~E_1~0 := 1; 6733#L624-3 assume 0 == ~E_2~0;~E_2~0 := 1; 6647#L629-3 assume !(0 == ~E_3~0); 6648#L634-3 assume 0 == ~E_4~0;~E_4~0 := 1; 6713#L639-3 assume 0 == ~E_5~0;~E_5~0 := 1; 6600#L644-3 havoc activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 6601#L282-21 assume 1 == ~m_pc~0; 6900#L283-7 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 6830#L293-7 is_master_triggered_#res := is_master_triggered_~__retres1~0; 6831#L294-7 activate_threads_#t~ret8 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 6837#L733-21 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 6838#L733-23 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 6404#L301-21 assume !(1 == ~t1_pc~0); 6402#L301-23 is_transmit1_triggered_~__retres1~1 := 0; 6403#L312-7 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 6450#L313-7 activate_threads_#t~ret9 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 6453#L741-21 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 6407#L741-23 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 6408#L320-21 assume !(1 == ~t2_pc~0); 6641#L320-23 is_transmit2_triggered_~__retres1~2 := 0; 6642#L331-7 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 6674#L332-7 activate_threads_#t~ret10 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 6678#L749-21 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 6679#L749-23 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 6687#L339-21 assume 1 == ~t3_pc~0; 6758#L340-7 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 6759#L350-7 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 6756#L351-7 activate_threads_#t~ret11 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 6757#L757-21 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 6800#L757-23 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 6801#L358-21 assume 1 == ~t4_pc~0; 6859#L359-7 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 6556#L369-7 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 6557#L370-7 activate_threads_#t~ret12 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 6857#L765-21 assume !(0 != activate_threads_~tmp___3~0); 6892#L765-23 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 6516#L377-21 assume 1 == ~t5_pc~0; 6433#L378-7 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 6434#L388-7 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 6431#L389-7 activate_threads_#t~ret13 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 6432#L773-21 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 6718#L773-23 assume 1 == ~M_E~0;~M_E~0 := 2; 6719#L657-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 6643#L662-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 6644#L667-3 assume !(1 == ~T3_E~0); 6711#L672-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 6592#L677-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 6593#L682-3 assume 1 == ~E_M~0;~E_M~0 := 2; 6385#L687-3 assume 1 == ~E_1~0;~E_1~0 := 2; 6386#L692-3 assume 1 == ~E_2~0;~E_2~0 := 2; 6524#L697-3 assume 1 == ~E_3~0;~E_3~0 := 2; 6525#L702-3 assume 1 == ~E_4~0;~E_4~0 := 2; 6744#L707-3 assume !(1 == ~E_5~0); 6745#L712-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 6618#L442-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 6569#L474-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 6653#L475-1 start_simulation_#t~ret15 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret15;havoc start_simulation_#t~ret15; 6654#L937 assume !(0 == start_simulation_~tmp~3); 6664#L937-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret14, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 6621#L442-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 6575#L474-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 6619#L475-2 stop_simulation_#t~ret14 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret14;havoc stop_simulation_#t~ret14; 6620#L892 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 6815#L899 stop_simulation_#res := stop_simulation_~__retres2~0; 6822#L900 start_simulation_#t~ret16 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret16;havoc start_simulation_#t~ret16; 6723#L950 assume !(0 != start_simulation_~tmp___0~1); 6421#L918-1 [2018-11-23 13:21:50,651 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 13:21:50,652 INFO L82 PathProgramCache]: Analyzing trace with hash -257633736, now seen corresponding path program 1 times [2018-11-23 13:21:50,652 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 13:21:50,652 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 13:21:50,652 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 13:21:50,653 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 13:21:50,653 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 13:21:50,659 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 13:21:50,685 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 13:21:50,686 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 13:21:50,686 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2018-11-23 13:21:50,686 INFO L799 eck$LassoCheckResult]: stem already infeasible [2018-11-23 13:21:50,686 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 13:21:50,686 INFO L82 PathProgramCache]: Analyzing trace with hash -710029130, now seen corresponding path program 1 times [2018-11-23 13:21:50,687 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 13:21:50,687 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 13:21:50,687 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 13:21:50,687 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 13:21:50,687 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 13:21:50,693 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 13:21:50,729 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 13:21:50,729 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 13:21:50,730 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-23 13:21:50,730 INFO L811 eck$LassoCheckResult]: loop already infeasible [2018-11-23 13:21:50,730 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-23 13:21:50,730 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-23 13:21:50,730 INFO L87 Difference]: Start difference. First operand 527 states and 790 transitions. cyclomatic complexity: 264 Second operand 3 states. [2018-11-23 13:21:50,783 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 13:21:50,783 INFO L93 Difference]: Finished difference Result 527 states and 777 transitions. [2018-11-23 13:21:50,784 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-23 13:21:50,784 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 527 states and 777 transitions. [2018-11-23 13:21:50,786 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 452 [2018-11-23 13:21:50,787 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 527 states to 527 states and 777 transitions. [2018-11-23 13:21:50,787 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 527 [2018-11-23 13:21:50,788 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 527 [2018-11-23 13:21:50,788 INFO L73 IsDeterministic]: Start isDeterministic. Operand 527 states and 777 transitions. [2018-11-23 13:21:50,789 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-23 13:21:50,789 INFO L705 BuchiCegarLoop]: Abstraction has 527 states and 777 transitions. [2018-11-23 13:21:50,790 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 527 states and 777 transitions. [2018-11-23 13:21:50,793 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 527 to 527. [2018-11-23 13:21:50,794 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 527 states. [2018-11-23 13:21:50,795 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 527 states to 527 states and 777 transitions. [2018-11-23 13:21:50,795 INFO L728 BuchiCegarLoop]: Abstraction has 527 states and 777 transitions. [2018-11-23 13:21:50,795 INFO L608 BuchiCegarLoop]: Abstraction has 527 states and 777 transitions. [2018-11-23 13:21:50,795 INFO L442 BuchiCegarLoop]: ======== Iteration 8============ [2018-11-23 13:21:50,795 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 527 states and 777 transitions. [2018-11-23 13:21:50,797 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 452 [2018-11-23 13:21:50,797 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-23 13:21:50,797 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-23 13:21:50,798 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 13:21:50,798 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 13:21:50,798 INFO L794 eck$LassoCheckResult]: Stem: 7877#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 7827#L-1 havoc main_#res;havoc main_~__retres1~7;havoc main_~__retres1~7;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 7828#L881 havoc start_simulation_#t~ret15, start_simulation_#t~ret16, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 7756#L397 assume 1 == ~m_i~0;~m_st~0 := 0; 7757#L404-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 7678#L409-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 7679#L414-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 7759#L419-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 7628#L424-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 7629#L429-1 assume !(0 == ~M_E~0); 7654#L589-1 assume !(0 == ~T1_E~0); 7655#L594-1 assume !(0 == ~T2_E~0); 7448#L599-1 assume !(0 == ~T3_E~0); 7449#L604-1 assume !(0 == ~T4_E~0); 7580#L609-1 assume !(0 == ~T5_E~0); 7581#L614-1 assume !(0 == ~E_M~0); 7807#L619-1 assume !(0 == ~E_1~0); 7808#L624-1 assume !(0 == ~E_2~0); 7695#L629-1 assume !(0 == ~E_3~0); 7696#L634-1 assume !(0 == ~E_4~0); 7764#L639-1 assume !(0 == ~E_5~0); 7644#L644-1 havoc activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 7645#L282 assume 1 == ~m_pc~0; 7906#L283 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 7908#L293 is_master_triggered_#res := is_master_triggered_~__retres1~0; 7909#L294 activate_threads_#t~ret8 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 7948#L733 assume !(0 != activate_threads_~tmp~1); 7949#L733-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 7562#L301 assume !(1 == ~t1_pc~0); 7555#L301-2 is_transmit1_triggered_~__retres1~1 := 0; 7524#L312 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 7525#L313 activate_threads_#t~ret9 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 7589#L741 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 7570#L741-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 7571#L320 assume 1 == ~t2_pc~0; 7682#L321 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 7683#L331 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 7680#L332 activate_threads_#t~ret10 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 7681#L749 assume !(0 != activate_threads_~tmp___1~0); 7874#L749-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 7870#L339 assume !(1 == ~t3_pc~0); 7830#L339-2 is_transmit3_triggered_~__retres1~3 := 0; 7831#L350 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 7859#L351 activate_threads_#t~ret11 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 7860#L757 assume !(0 != activate_threads_~tmp___2~0); 7957#L757-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 7636#L358 assume 1 == ~t4_pc~0; 7637#L359 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 7591#L369 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 7635#L370 activate_threads_#t~ret12 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 7662#L765 assume !(0 != activate_threads_~tmp___3~0); 7663#L765-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 7664#L377 assume !(1 == ~t5_pc~0); 7567#L377-2 is_transmit5_triggered_~__retres1~5 := 0; 7789#L388 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 7564#L389 activate_threads_#t~ret13 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 7565#L773 assume !(0 != activate_threads_~tmp___4~0); 7801#L773-2 assume !(1 == ~M_E~0); 7802#L657-1 assume !(1 == ~T1_E~0); 7716#L662-1 assume !(1 == ~T2_E~0); 7717#L667-1 assume !(1 == ~T3_E~0); 7875#L672-1 assume !(1 == ~T4_E~0); 7642#L677-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 7643#L682-1 assume !(1 == ~E_M~0); 7439#L687-1 assume !(1 == ~E_1~0); 7440#L692-1 assume !(1 == ~E_2~0); 7572#L697-1 assume !(1 == ~E_3~0); 7573#L702-1 assume !(1 == ~E_4~0); 7804#L707-1 assume !(1 == ~E_5~0); 7482#L918-1 [2018-11-23 13:21:50,798 INFO L796 eck$LassoCheckResult]: Loop: 7482#L918-1 assume !false; 7483#L919 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret1, eval_#t~nondet2, eval_~tmp_ndt_1~0, eval_#t~nondet3, eval_~tmp_ndt_2~0, eval_#t~nondet4, eval_~tmp_ndt_3~0, eval_#t~nondet5, eval_~tmp_ndt_4~0, eval_#t~nondet6, eval_~tmp_ndt_5~0, eval_#t~nondet7, eval_~tmp_ndt_6~0, eval_~tmp~0;havoc eval_~tmp~0; 7653#L564 assume !false; 7771#L485 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 7711#L442 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 7622#L474 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 7708#L475 eval_#t~ret1 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret1;havoc eval_#t~ret1; 7668#L489 assume !(0 != eval_~tmp~0); 7670#L579 start_simulation_~kernel_st~0 := 2; 7760#L397-1 start_simulation_~kernel_st~0 := 3; 7658#L589-2 assume 0 == ~M_E~0;~M_E~0 := 1; 7616#L589-4 assume !(0 == ~T1_E~0); 7617#L594-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 7666#L599-3 assume !(0 == ~T3_E~0); 7667#L604-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 7551#L609-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 7552#L614-3 assume 0 == ~E_M~0;~E_M~0 := 1; 7793#L619-3 assume 0 == ~E_1~0;~E_1~0 := 1; 7794#L624-3 assume 0 == ~E_2~0;~E_2~0 := 1; 7703#L629-3 assume !(0 == ~E_3~0); 7704#L634-3 assume 0 == ~E_4~0;~E_4~0 := 1; 7769#L639-3 assume !(0 == ~E_5~0); 7656#L644-3 havoc activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 7657#L282-21 assume 1 == ~m_pc~0; 7961#L283-7 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 7891#L293-7 is_master_triggered_#res := is_master_triggered_~__retres1~0; 7892#L294-7 activate_threads_#t~ret8 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 7898#L733-21 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 7899#L733-23 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 7465#L301-21 assume !(1 == ~t1_pc~0); 7463#L301-23 is_transmit1_triggered_~__retres1~1 := 0; 7464#L312-7 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 7505#L313-7 activate_threads_#t~ret9 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 7509#L741-21 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 7468#L741-23 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 7469#L320-21 assume !(1 == ~t2_pc~0); 7697#L320-23 is_transmit2_triggered_~__retres1~2 := 0; 7698#L331-7 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 7730#L332-7 activate_threads_#t~ret10 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 7734#L749-21 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 7735#L749-23 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 7743#L339-21 assume 1 == ~t3_pc~0; 7819#L340-7 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 7820#L350-7 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 7817#L351-7 activate_threads_#t~ret11 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 7818#L757-21 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 7861#L757-23 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 7862#L358-21 assume 1 == ~t4_pc~0; 7920#L359-7 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 7612#L369-7 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 7613#L370-7 activate_threads_#t~ret12 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 7918#L765-21 assume !(0 != activate_threads_~tmp___3~0); 7953#L765-23 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 7569#L377-21 assume !(1 == ~t5_pc~0); 7494#L377-23 is_transmit5_triggered_~__retres1~5 := 0; 7574#L388-7 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 7491#L389-7 activate_threads_#t~ret13 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 7492#L773-21 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 7775#L773-23 assume 1 == ~M_E~0;~M_E~0 := 2; 7776#L657-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 7699#L662-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 7700#L667-3 assume !(1 == ~T3_E~0); 7767#L672-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 7648#L677-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 7649#L682-3 assume 1 == ~E_M~0;~E_M~0 := 2; 7446#L687-3 assume 1 == ~E_1~0;~E_1~0 := 2; 7447#L692-3 assume 1 == ~E_2~0;~E_2~0 := 2; 7578#L697-3 assume 1 == ~E_3~0;~E_3~0 := 2; 7579#L702-3 assume 1 == ~E_4~0;~E_4~0 := 2; 7805#L707-3 assume !(1 == ~E_5~0); 7806#L712-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 7674#L442-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 7625#L474-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 7709#L475-1 start_simulation_#t~ret15 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret15;havoc start_simulation_#t~ret15; 7710#L937 assume !(0 == start_simulation_~tmp~3); 7720#L937-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret14, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 7677#L442-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 7631#L474-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 7675#L475-2 stop_simulation_#t~ret14 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret14;havoc stop_simulation_#t~ret14; 7676#L892 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 7876#L899 stop_simulation_#res := stop_simulation_~__retres2~0; 7883#L900 start_simulation_#t~ret16 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret16;havoc start_simulation_#t~ret16; 7780#L950 assume !(0 != start_simulation_~tmp___0~1); 7482#L918-1 [2018-11-23 13:21:50,799 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 13:21:50,799 INFO L82 PathProgramCache]: Analyzing trace with hash -273152454, now seen corresponding path program 1 times [2018-11-23 13:21:50,799 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 13:21:50,799 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 13:21:50,800 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 13:21:50,800 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 13:21:50,800 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 13:21:50,803 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 13:21:50,823 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 13:21:50,824 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 13:21:50,824 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2018-11-23 13:21:50,824 INFO L799 eck$LassoCheckResult]: stem already infeasible [2018-11-23 13:21:50,824 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 13:21:50,824 INFO L82 PathProgramCache]: Analyzing trace with hash -87901101, now seen corresponding path program 1 times [2018-11-23 13:21:50,824 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 13:21:50,824 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 13:21:50,825 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 13:21:50,825 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 13:21:50,825 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 13:21:50,830 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 13:21:50,858 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 13:21:50,858 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 13:21:50,859 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-11-23 13:21:50,859 INFO L811 eck$LassoCheckResult]: loop already infeasible [2018-11-23 13:21:50,859 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-23 13:21:50,859 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-23 13:21:50,859 INFO L87 Difference]: Start difference. First operand 527 states and 777 transitions. cyclomatic complexity: 251 Second operand 3 states. [2018-11-23 13:21:50,907 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 13:21:50,907 INFO L93 Difference]: Finished difference Result 969 states and 1412 transitions. [2018-11-23 13:21:50,908 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-23 13:21:50,908 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 969 states and 1412 transitions. [2018-11-23 13:21:50,911 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 893 [2018-11-23 13:21:50,913 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 969 states to 969 states and 1412 transitions. [2018-11-23 13:21:50,913 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 969 [2018-11-23 13:21:50,914 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 969 [2018-11-23 13:21:50,914 INFO L73 IsDeterministic]: Start isDeterministic. Operand 969 states and 1412 transitions. [2018-11-23 13:21:50,915 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-23 13:21:50,915 INFO L705 BuchiCegarLoop]: Abstraction has 969 states and 1412 transitions. [2018-11-23 13:21:50,916 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 969 states and 1412 transitions. [2018-11-23 13:21:50,925 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 969 to 929. [2018-11-23 13:21:50,925 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 929 states. [2018-11-23 13:21:50,927 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 929 states to 929 states and 1357 transitions. [2018-11-23 13:21:50,927 INFO L728 BuchiCegarLoop]: Abstraction has 929 states and 1357 transitions. [2018-11-23 13:21:50,927 INFO L608 BuchiCegarLoop]: Abstraction has 929 states and 1357 transitions. [2018-11-23 13:21:50,927 INFO L442 BuchiCegarLoop]: ======== Iteration 9============ [2018-11-23 13:21:50,927 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 929 states and 1357 transitions. [2018-11-23 13:21:50,930 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 853 [2018-11-23 13:21:50,930 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-23 13:21:50,930 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-23 13:21:50,931 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 13:21:50,931 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 13:21:50,931 INFO L794 eck$LassoCheckResult]: Stem: 9416#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 9351#L-1 havoc main_#res;havoc main_~__retres1~7;havoc main_~__retres1~7;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 9352#L881 havoc start_simulation_#t~ret15, start_simulation_#t~ret16, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 9269#L397 assume 1 == ~m_i~0;~m_st~0 := 0; 9270#L404-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 9186#L409-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 9187#L414-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 9272#L419-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 9135#L424-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 9136#L429-1 assume !(0 == ~M_E~0); 9161#L589-1 assume !(0 == ~T1_E~0); 9162#L594-1 assume !(0 == ~T2_E~0); 8953#L599-1 assume !(0 == ~T3_E~0); 8954#L604-1 assume !(0 == ~T4_E~0); 9088#L609-1 assume !(0 == ~T5_E~0); 9089#L614-1 assume !(0 == ~E_M~0); 9330#L619-1 assume !(0 == ~E_1~0); 9331#L624-1 assume !(0 == ~E_2~0); 9203#L629-1 assume !(0 == ~E_3~0); 9204#L634-1 assume !(0 == ~E_4~0); 9277#L639-1 assume !(0 == ~E_5~0); 9151#L644-1 havoc activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 9152#L282 assume !(1 == ~m_pc~0); 9448#L282-2 is_master_triggered_~__retres1~0 := 0; 9451#L293 is_master_triggered_#res := is_master_triggered_~__retres1~0; 9452#L294 activate_threads_#t~ret8 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 9495#L733 assume !(0 != activate_threads_~tmp~1); 9496#L733-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 9069#L301 assume !(1 == ~t1_pc~0); 9061#L301-2 is_transmit1_triggered_~__retres1~1 := 0; 9029#L312 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 9030#L313 activate_threads_#t~ret9 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 9096#L741 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 9077#L741-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 9078#L320 assume 1 == ~t2_pc~0; 9190#L321 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 9191#L331 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 9188#L332 activate_threads_#t~ret10 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 9189#L749 assume !(0 != activate_threads_~tmp___1~0); 9413#L749-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 9407#L339 assume !(1 == ~t3_pc~0); 9354#L339-2 is_transmit3_triggered_~__retres1~3 := 0; 9355#L350 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 9385#L351 activate_threads_#t~ret11 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 9386#L757 assume !(0 != activate_threads_~tmp___2~0); 9509#L757-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 9143#L358 assume 1 == ~t4_pc~0; 9144#L359 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 9098#L369 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 9142#L370 activate_threads_#t~ret12 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 9169#L765 assume !(0 != activate_threads_~tmp___3~0); 9170#L765-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 9171#L377 assume !(1 == ~t5_pc~0); 9075#L377-2 is_transmit5_triggered_~__retres1~5 := 0; 9310#L388 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 9071#L389 activate_threads_#t~ret13 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 9072#L773 assume !(0 != activate_threads_~tmp___4~0); 9324#L773-2 assume !(1 == ~M_E~0); 9325#L657-1 assume !(1 == ~T1_E~0); 9224#L662-1 assume !(1 == ~T2_E~0); 9225#L667-1 assume !(1 == ~T3_E~0); 9414#L672-1 assume !(1 == ~T4_E~0); 9149#L677-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 9150#L682-1 assume !(1 == ~E_M~0); 8944#L687-1 assume !(1 == ~E_1~0); 8945#L692-1 assume !(1 == ~E_2~0); 9079#L697-1 assume !(1 == ~E_3~0); 9080#L702-1 assume !(1 == ~E_4~0); 9327#L707-1 assume !(1 == ~E_5~0); 8987#L918-1 [2018-11-23 13:21:50,931 INFO L796 eck$LassoCheckResult]: Loop: 8987#L918-1 assume !false; 8988#L919 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret1, eval_#t~nondet2, eval_~tmp_ndt_1~0, eval_#t~nondet3, eval_~tmp_ndt_2~0, eval_#t~nondet4, eval_~tmp_ndt_3~0, eval_#t~nondet5, eval_~tmp_ndt_4~0, eval_#t~nondet6, eval_~tmp_ndt_5~0, eval_#t~nondet7, eval_~tmp_ndt_6~0, eval_~tmp~0;havoc eval_~tmp~0; 9173#L564 assume !false; 9313#L485 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 9217#L442 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 9129#L474 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 9539#L475 eval_#t~ret1 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret1;havoc eval_#t~ret1; 9536#L489 assume !(0 != eval_~tmp~0); 9537#L579 start_simulation_~kernel_st~0 := 2; 9633#L397-1 start_simulation_~kernel_st~0 := 3; 9632#L589-2 assume 0 == ~M_E~0;~M_E~0 := 1; 9631#L589-4 assume !(0 == ~T1_E~0); 9421#L594-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 9174#L599-3 assume !(0 == ~T3_E~0); 9175#L604-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 9629#L609-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 9628#L614-3 assume 0 == ~E_M~0;~E_M~0 := 1; 9316#L619-3 assume 0 == ~E_1~0;~E_1~0 := 1; 9317#L624-3 assume 0 == ~E_2~0;~E_2~0 := 1; 9211#L629-3 assume !(0 == ~E_3~0); 9212#L634-3 assume 0 == ~E_4~0;~E_4~0 := 1; 9625#L639-3 assume !(0 == ~E_5~0); 9163#L644-3 havoc activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 9164#L282-21 assume !(1 == ~m_pc~0); 9529#L282-23 is_master_triggered_~__retres1~0 := 0; 9770#L293-7 is_master_triggered_#res := is_master_triggered_~__retres1~0; 9769#L294-7 activate_threads_#t~ret8 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 9768#L733-21 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 9767#L733-23 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 9766#L301-21 assume !(1 == ~t1_pc~0); 9764#L301-23 is_transmit1_triggered_~__retres1~1 := 0; 9763#L312-7 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 9762#L313-7 activate_threads_#t~ret9 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 9761#L741-21 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 9760#L741-23 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 9759#L320-21 assume 1 == ~t2_pc~0; 9757#L321-7 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 9756#L331-7 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 9755#L332-7 activate_threads_#t~ret10 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 9754#L749-21 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 9753#L749-23 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 9387#L339-21 assume 1 == ~t3_pc~0; 9388#L340-7 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 9401#L350-7 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 9402#L351-7 activate_threads_#t~ret11 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 9404#L757-21 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 9405#L757-23 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 9752#L358-21 assume 1 == ~t4_pc~0; 9462#L359-7 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 9119#L369-7 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 9120#L370-7 activate_threads_#t~ret12 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 9750#L765-21 assume !(0 != activate_threads_~tmp___3~0); 9749#L765-23 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 9748#L377-21 assume !(1 == ~t5_pc~0); 9746#L377-23 is_transmit5_triggered_~__retres1~5 := 0; 9304#L388-7 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 9305#L389-7 activate_threads_#t~ret13 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 9745#L773-21 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 9293#L773-23 assume 1 == ~M_E~0;~M_E~0 := 2; 9294#L657-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 9207#L662-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 9208#L667-3 assume !(1 == ~T3_E~0); 9280#L672-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 9281#L677-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 9420#L682-3 assume 1 == ~E_M~0;~E_M~0 := 2; 8951#L687-3 assume 1 == ~E_1~0;~E_1~0 := 2; 8952#L692-3 assume 1 == ~E_2~0;~E_2~0 := 2; 9741#L697-3 assume 1 == ~E_3~0;~E_3~0 := 2; 9740#L702-3 assume 1 == ~E_4~0;~E_4~0 := 2; 9328#L707-3 assume !(1 == ~E_5~0); 9329#L712-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 9182#L442-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 9132#L474-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 9218#L475-1 start_simulation_#t~ret15 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret15;havoc start_simulation_#t~ret15; 9219#L937 assume !(0 == start_simulation_~tmp~3); 9228#L937-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret14, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 9798#L442-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 9793#L474-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 9791#L475-2 stop_simulation_#t~ret14 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret14;havoc stop_simulation_#t~ret14; 9789#L892 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 9424#L899 stop_simulation_#res := stop_simulation_~__retres2~0; 9425#L900 start_simulation_#t~ret16 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret16;havoc start_simulation_#t~ret16; 9298#L950 assume !(0 != start_simulation_~tmp___0~1); 8987#L918-1 [2018-11-23 13:21:50,932 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 13:21:50,932 INFO L82 PathProgramCache]: Analyzing trace with hash 2128372667, now seen corresponding path program 1 times [2018-11-23 13:21:50,932 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 13:21:50,932 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 13:21:50,932 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 13:21:50,933 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 13:21:50,933 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 13:21:50,937 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 13:21:50,962 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 13:21:50,963 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 13:21:50,963 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2018-11-23 13:21:50,963 INFO L799 eck$LassoCheckResult]: stem already infeasible [2018-11-23 13:21:50,963 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 13:21:50,963 INFO L82 PathProgramCache]: Analyzing trace with hash 867747283, now seen corresponding path program 1 times [2018-11-23 13:21:50,963 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 13:21:50,963 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 13:21:50,964 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 13:21:50,964 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 13:21:50,964 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 13:21:50,969 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 13:21:50,996 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 13:21:50,996 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 13:21:50,996 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-11-23 13:21:50,996 INFO L811 eck$LassoCheckResult]: loop already infeasible [2018-11-23 13:21:50,996 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-23 13:21:50,996 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-23 13:21:50,997 INFO L87 Difference]: Start difference. First operand 929 states and 1357 transitions. cyclomatic complexity: 430 Second operand 3 states. [2018-11-23 13:21:51,036 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 13:21:51,036 INFO L93 Difference]: Finished difference Result 1685 states and 2443 transitions. [2018-11-23 13:21:51,037 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-23 13:21:51,037 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1685 states and 2443 transitions. [2018-11-23 13:21:51,041 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 1604 [2018-11-23 13:21:51,045 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1685 states to 1685 states and 2443 transitions. [2018-11-23 13:21:51,046 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1685 [2018-11-23 13:21:51,047 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1685 [2018-11-23 13:21:51,047 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1685 states and 2443 transitions. [2018-11-23 13:21:51,049 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-23 13:21:51,049 INFO L705 BuchiCegarLoop]: Abstraction has 1685 states and 2443 transitions. [2018-11-23 13:21:51,050 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1685 states and 2443 transitions. [2018-11-23 13:21:51,062 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1685 to 1681. [2018-11-23 13:21:51,062 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1681 states. [2018-11-23 13:21:51,065 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1681 states to 1681 states and 2439 transitions. [2018-11-23 13:21:51,065 INFO L728 BuchiCegarLoop]: Abstraction has 1681 states and 2439 transitions. [2018-11-23 13:21:51,065 INFO L608 BuchiCegarLoop]: Abstraction has 1681 states and 2439 transitions. [2018-11-23 13:21:51,065 INFO L442 BuchiCegarLoop]: ======== Iteration 10============ [2018-11-23 13:21:51,065 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1681 states and 2439 transitions. [2018-11-23 13:21:51,069 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 1600 [2018-11-23 13:21:51,070 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-23 13:21:51,070 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-23 13:21:51,071 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 13:21:51,071 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 13:21:51,071 INFO L794 eck$LassoCheckResult]: Stem: 12032#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 11982#L-1 havoc main_#res;havoc main_~__retres1~7;havoc main_~__retres1~7;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 11983#L881 havoc start_simulation_#t~ret15, start_simulation_#t~ret16, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 11890#L397 assume 1 == ~m_i~0;~m_st~0 := 0; 11891#L404-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 11809#L409-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 11810#L414-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 11892#L419-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 11759#L424-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 11760#L429-1 assume !(0 == ~M_E~0); 11785#L589-1 assume !(0 == ~T1_E~0); 11786#L594-1 assume !(0 == ~T2_E~0); 11576#L599-1 assume !(0 == ~T3_E~0); 11577#L604-1 assume !(0 == ~T4_E~0); 11711#L609-1 assume !(0 == ~T5_E~0); 11712#L614-1 assume !(0 == ~E_M~0); 11949#L619-1 assume !(0 == ~E_1~0); 11950#L624-1 assume !(0 == ~E_2~0); 11824#L629-1 assume !(0 == ~E_3~0); 11825#L634-1 assume !(0 == ~E_4~0); 11898#L639-1 assume !(0 == ~E_5~0); 11775#L644-1 havoc activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 11776#L282 assume !(1 == ~m_pc~0); 12060#L282-2 is_master_triggered_~__retres1~0 := 0; 12061#L293 is_master_triggered_#res := is_master_triggered_~__retres1~0; 12062#L294 activate_threads_#t~ret8 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 12104#L733 assume !(0 != activate_threads_~tmp~1); 12105#L733-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 11692#L301 assume !(1 == ~t1_pc~0); 11685#L301-2 is_transmit1_triggered_~__retres1~1 := 0; 11651#L312 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 11652#L313 activate_threads_#t~ret9 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 11719#L741 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 11701#L741-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 11702#L320 assume !(1 == ~t2_pc~0); 11874#L320-2 is_transmit2_triggered_~__retres1~2 := 0; 11875#L331 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 11812#L332 activate_threads_#t~ret10 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 11813#L749 assume !(0 != activate_threads_~tmp___1~0); 12029#L749-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 12025#L339 assume !(1 == ~t3_pc~0); 11985#L339-2 is_transmit3_triggered_~__retres1~3 := 0; 11986#L350 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 12014#L351 activate_threads_#t~ret11 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 12015#L757 assume !(0 != activate_threads_~tmp___2~0); 12117#L757-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 11767#L358 assume 1 == ~t4_pc~0; 11768#L359 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 11722#L369 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 11764#L370 activate_threads_#t~ret12 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 11793#L765 assume !(0 != activate_threads_~tmp___3~0); 11794#L765-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 11795#L377 assume !(1 == ~t5_pc~0); 11697#L377-2 is_transmit5_triggered_~__retres1~5 := 0; 11923#L388 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 11694#L389 activate_threads_#t~ret13 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 11695#L773 assume !(0 != activate_threads_~tmp___4~0); 11940#L773-2 assume !(1 == ~M_E~0); 11941#L657-1 assume !(1 == ~T1_E~0); 11843#L662-1 assume !(1 == ~T2_E~0); 11844#L667-1 assume !(1 == ~T3_E~0); 12030#L672-1 assume !(1 == ~T4_E~0); 11773#L677-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 11774#L682-1 assume !(1 == ~E_M~0); 11567#L687-1 assume !(1 == ~E_1~0); 11568#L692-1 assume !(1 == ~E_2~0); 11703#L697-1 assume !(1 == ~E_3~0); 11704#L702-1 assume !(1 == ~E_4~0); 11942#L707-1 assume !(1 == ~E_5~0); 11610#L918-1 [2018-11-23 13:21:51,071 INFO L796 eck$LassoCheckResult]: Loop: 11610#L918-1 assume !false; 11611#L919 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret1, eval_#t~nondet2, eval_~tmp_ndt_1~0, eval_#t~nondet3, eval_~tmp_ndt_2~0, eval_#t~nondet4, eval_~tmp_ndt_3~0, eval_#t~nondet5, eval_~tmp_ndt_4~0, eval_#t~nondet6, eval_~tmp_ndt_5~0, eval_#t~nondet7, eval_~tmp_ndt_6~0, eval_~tmp~0;havoc eval_~tmp~0; 11782#L564 assume !false; 11904#L485 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 11837#L442 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 11753#L474 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 11836#L475 eval_#t~ret1 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret1;havoc eval_#t~ret1; 11799#L489 assume !(0 != eval_~tmp~0); 11801#L579 start_simulation_~kernel_st~0 := 2; 13238#L397-1 start_simulation_~kernel_st~0 := 3; 13237#L589-2 assume 0 == ~M_E~0;~M_E~0 := 1; 13236#L589-4 assume !(0 == ~T1_E~0); 13235#L594-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 13234#L599-3 assume !(0 == ~T3_E~0); 13233#L604-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 13232#L609-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 13231#L614-3 assume 0 == ~E_M~0;~E_M~0 := 1; 13230#L619-3 assume 0 == ~E_1~0;~E_1~0 := 1; 12138#L624-3 assume 0 == ~E_2~0;~E_2~0 := 1; 11831#L629-3 assume !(0 == ~E_3~0); 11832#L634-3 assume 0 == ~E_4~0;~E_4~0 := 1; 11903#L639-3 assume !(0 == ~E_5~0); 11787#L644-3 havoc activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 11788#L282-21 assume !(1 == ~m_pc~0); 12137#L282-23 is_master_triggered_~__retres1~0 := 0; 13247#L293-7 is_master_triggered_#res := is_master_triggered_~__retres1~0; 12127#L294-7 activate_threads_#t~ret8 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 12052#L733-21 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 12053#L733-23 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 11593#L301-21 assume !(1 == ~t1_pc~0); 11591#L301-23 is_transmit1_triggered_~__retres1~1 := 0; 11592#L312-7 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 11634#L313-7 activate_threads_#t~ret9 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 11637#L741-21 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 11598#L741-23 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 11599#L320-21 assume !(1 == ~t2_pc~0); 11842#L320-23 is_transmit2_triggered_~__retres1~2 := 0; 13224#L331-7 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 13223#L332-7 activate_threads_#t~ret10 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 13222#L749-21 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 13148#L749-23 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 13146#L339-21 assume !(1 == ~t3_pc~0); 13143#L339-23 is_transmit3_triggered_~__retres1~3 := 0; 13141#L350-7 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 13139#L351-7 activate_threads_#t~ret11 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 13137#L757-21 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 13135#L757-23 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 13133#L358-21 assume 1 == ~t4_pc~0; 13130#L359-7 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 13128#L369-7 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 13126#L370-7 activate_threads_#t~ret12 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 13124#L765-21 assume !(0 != activate_threads_~tmp___3~0); 13079#L765-23 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 13077#L377-21 assume !(1 == ~t5_pc~0); 13074#L377-23 is_transmit5_triggered_~__retres1~5 := 0; 13072#L388-7 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 13070#L389-7 activate_threads_#t~ret13 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 13068#L773-21 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 13066#L773-23 assume 1 == ~M_E~0;~M_E~0 := 2; 13049#L657-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 13046#L662-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 13044#L667-3 assume !(1 == ~T3_E~0); 13042#L672-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 13040#L677-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 13038#L682-3 assume 1 == ~E_M~0;~E_M~0 := 2; 13035#L687-3 assume 1 == ~E_1~0;~E_1~0 := 2; 13033#L692-3 assume 1 == ~E_2~0;~E_2~0 := 2; 13031#L697-3 assume 1 == ~E_3~0;~E_3~0 := 2; 13029#L702-3 assume 1 == ~E_4~0;~E_4~0 := 2; 13025#L707-3 assume !(1 == ~E_5~0); 13023#L712-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 12937#L442-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 12931#L474-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 12929#L475-1 start_simulation_#t~ret15 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret15;havoc start_simulation_#t~ret15; 12925#L937 assume !(0 == start_simulation_~tmp~3); 12924#L937-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret14, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 12919#L442-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 11889#L474-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 11807#L475-2 stop_simulation_#t~ret14 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret14;havoc stop_simulation_#t~ret14; 11808#L892 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 12031#L899 stop_simulation_#res := stop_simulation_~__retres2~0; 12038#L900 start_simulation_#t~ret16 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret16;havoc start_simulation_#t~ret16; 11915#L950 assume !(0 != start_simulation_~tmp___0~1); 11610#L918-1 [2018-11-23 13:21:51,071 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 13:21:51,071 INFO L82 PathProgramCache]: Analyzing trace with hash -1115145540, now seen corresponding path program 1 times [2018-11-23 13:21:51,072 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 13:21:51,072 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 13:21:51,072 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 13:21:51,072 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 13:21:51,073 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 13:21:51,077 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 13:21:51,099 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 13:21:51,099 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 13:21:51,099 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2018-11-23 13:21:51,099 INFO L799 eck$LassoCheckResult]: stem already infeasible [2018-11-23 13:21:51,099 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 13:21:51,100 INFO L82 PathProgramCache]: Analyzing trace with hash 145067601, now seen corresponding path program 1 times [2018-11-23 13:21:51,100 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 13:21:51,100 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 13:21:51,100 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 13:21:51,100 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 13:21:51,101 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 13:21:51,106 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 13:21:51,132 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 13:21:51,132 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 13:21:51,132 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-11-23 13:21:51,133 INFO L811 eck$LassoCheckResult]: loop already infeasible [2018-11-23 13:21:51,133 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-23 13:21:51,133 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-23 13:21:51,133 INFO L87 Difference]: Start difference. First operand 1681 states and 2439 transitions. cyclomatic complexity: 762 Second operand 3 states. [2018-11-23 13:21:51,176 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 13:21:51,176 INFO L93 Difference]: Finished difference Result 3096 states and 4460 transitions. [2018-11-23 13:21:51,177 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-23 13:21:51,178 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 3096 states and 4460 transitions. [2018-11-23 13:21:51,186 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 3000 [2018-11-23 13:21:51,194 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 3096 states to 3096 states and 4460 transitions. [2018-11-23 13:21:51,194 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 3096 [2018-11-23 13:21:51,196 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 3096 [2018-11-23 13:21:51,196 INFO L73 IsDeterministic]: Start isDeterministic. Operand 3096 states and 4460 transitions. [2018-11-23 13:21:51,199 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-23 13:21:51,200 INFO L705 BuchiCegarLoop]: Abstraction has 3096 states and 4460 transitions. [2018-11-23 13:21:51,202 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3096 states and 4460 transitions. [2018-11-23 13:21:51,223 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3096 to 3088. [2018-11-23 13:21:51,223 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3088 states. [2018-11-23 13:21:51,228 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3088 states to 3088 states and 4452 transitions. [2018-11-23 13:21:51,228 INFO L728 BuchiCegarLoop]: Abstraction has 3088 states and 4452 transitions. [2018-11-23 13:21:51,228 INFO L608 BuchiCegarLoop]: Abstraction has 3088 states and 4452 transitions. [2018-11-23 13:21:51,229 INFO L442 BuchiCegarLoop]: ======== Iteration 11============ [2018-11-23 13:21:51,229 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 3088 states and 4452 transitions. [2018-11-23 13:21:51,238 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 2992 [2018-11-23 13:21:51,238 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-23 13:21:51,238 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-23 13:21:51,239 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 13:21:51,239 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 13:21:51,239 INFO L794 eck$LassoCheckResult]: Stem: 16817#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 16760#L-1 havoc main_#res;havoc main_~__retres1~7;havoc main_~__retres1~7;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 16761#L881 havoc start_simulation_#t~ret15, start_simulation_#t~ret16, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 16674#L397 assume 1 == ~m_i~0;~m_st~0 := 0; 16675#L404-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 16593#L409-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 16594#L414-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 16676#L419-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 16541#L424-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 16542#L429-1 assume !(0 == ~M_E~0); 16566#L589-1 assume !(0 == ~T1_E~0); 16567#L594-1 assume !(0 == ~T2_E~0); 16362#L599-1 assume !(0 == ~T3_E~0); 16363#L604-1 assume !(0 == ~T4_E~0); 16495#L609-1 assume !(0 == ~T5_E~0); 16496#L614-1 assume !(0 == ~E_M~0); 16728#L619-1 assume !(0 == ~E_1~0); 16729#L624-1 assume !(0 == ~E_2~0); 16608#L629-1 assume !(0 == ~E_3~0); 16609#L634-1 assume !(0 == ~E_4~0); 16682#L639-1 assume !(0 == ~E_5~0); 16556#L644-1 havoc activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 16557#L282 assume !(1 == ~m_pc~0); 16846#L282-2 is_master_triggered_~__retres1~0 := 0; 16847#L293 is_master_triggered_#res := is_master_triggered_~__retres1~0; 16848#L294 activate_threads_#t~ret8 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 16900#L733 assume !(0 != activate_threads_~tmp~1); 16901#L733-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 16477#L301 assume !(1 == ~t1_pc~0); 16470#L301-2 is_transmit1_triggered_~__retres1~1 := 0; 16437#L312 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 16438#L313 activate_threads_#t~ret9 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 16503#L741 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 16485#L741-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 16486#L320 assume !(1 == ~t2_pc~0); 16659#L320-2 is_transmit2_triggered_~__retres1~2 := 0; 16660#L331 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 16596#L332 activate_threads_#t~ret10 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 16597#L749 assume !(0 != activate_threads_~tmp___1~0); 16814#L749-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 16808#L339 assume !(1 == ~t3_pc~0); 16763#L339-2 is_transmit3_triggered_~__retres1~3 := 0; 16764#L350 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 16792#L351 activate_threads_#t~ret11 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 16793#L757 assume !(0 != activate_threads_~tmp___2~0); 16914#L757-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 16549#L358 assume !(1 == ~t4_pc~0); 16505#L358-2 is_transmit4_triggered_~__retres1~4 := 0; 16506#L369 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 16546#L370 activate_threads_#t~ret12 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 16575#L765 assume !(0 != activate_threads_~tmp___3~0); 16576#L765-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 16577#L377 assume !(1 == ~t5_pc~0); 16482#L377-2 is_transmit5_triggered_~__retres1~5 := 0; 16706#L388 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 16479#L389 activate_threads_#t~ret13 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 16480#L773 assume !(0 != activate_threads_~tmp___4~0); 16721#L773-2 assume !(1 == ~M_E~0); 16722#L657-1 assume !(1 == ~T1_E~0); 16627#L662-1 assume !(1 == ~T2_E~0); 16628#L667-1 assume !(1 == ~T3_E~0); 16815#L672-1 assume !(1 == ~T4_E~0); 16554#L677-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 16555#L682-1 assume !(1 == ~E_M~0); 16353#L687-1 assume !(1 == ~E_1~0); 16354#L692-1 assume !(1 == ~E_2~0); 16487#L697-1 assume !(1 == ~E_3~0); 16488#L702-1 assume !(1 == ~E_4~0); 16723#L707-1 assume !(1 == ~E_5~0); 16397#L918-1 [2018-11-23 13:21:51,239 INFO L796 eck$LassoCheckResult]: Loop: 16397#L918-1 assume !false; 16398#L919 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret1, eval_#t~nondet2, eval_~tmp_ndt_1~0, eval_#t~nondet3, eval_~tmp_ndt_2~0, eval_#t~nondet4, eval_~tmp_ndt_3~0, eval_#t~nondet5, eval_~tmp_ndt_4~0, eval_#t~nondet6, eval_~tmp_ndt_5~0, eval_#t~nondet7, eval_~tmp_ndt_6~0, eval_~tmp~0;havoc eval_~tmp~0; 16563#L564 assume !false; 16688#L485 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 16622#L442 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 16535#L474 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 16621#L475 eval_#t~ret1 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret1;havoc eval_#t~ret1; 16583#L489 assume !(0 != eval_~tmp~0); 16585#L579 start_simulation_~kernel_st~0 := 2; 19170#L397-1 start_simulation_~kernel_st~0 := 3; 19168#L589-2 assume 0 == ~M_E~0;~M_E~0 := 1; 16529#L589-4 assume !(0 == ~T1_E~0); 16530#L594-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 16581#L599-3 assume !(0 == ~T3_E~0); 16582#L604-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 16466#L609-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 16467#L614-3 assume 0 == ~E_M~0;~E_M~0 := 1; 16713#L619-3 assume 0 == ~E_1~0;~E_1~0 := 1; 16714#L624-3 assume 0 == ~E_2~0;~E_2~0 := 1; 16616#L629-3 assume !(0 == ~E_3~0); 16617#L634-3 assume 0 == ~E_4~0;~E_4~0 := 1; 16687#L639-3 assume !(0 == ~E_5~0); 16568#L644-3 havoc activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 16569#L282-21 assume !(1 == ~m_pc~0); 16941#L282-23 is_master_triggered_~__retres1~0 := 0; 16829#L293-7 is_master_triggered_#res := is_master_triggered_~__retres1~0; 16830#L294-7 activate_threads_#t~ret8 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 16836#L733-21 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 16837#L733-23 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 16380#L301-21 assume !(1 == ~t1_pc~0); 16378#L301-23 is_transmit1_triggered_~__retres1~1 := 0; 16379#L312-7 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 16421#L313-7 activate_threads_#t~ret9 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 16424#L741-21 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 16385#L741-23 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 16386#L320-21 assume !(1 == ~t2_pc~0); 16610#L320-23 is_transmit2_triggered_~__retres1~2 := 0; 16611#L331-7 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 16641#L332-7 activate_threads_#t~ret10 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 16646#L749-21 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 16647#L749-23 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 16655#L339-21 assume 1 == ~t3_pc~0; 16752#L340-7 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 16753#L350-7 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 16750#L351-7 activate_threads_#t~ret11 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 16751#L757-21 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 16798#L757-23 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 16799#L358-21 assume !(1 == ~t4_pc~0); 16902#L358-23 is_transmit4_triggered_~__retres1~4 := 0; 16904#L369-7 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 19214#L370-7 activate_threads_#t~ret12 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 19211#L765-21 assume !(0 != activate_threads_~tmp___3~0); 19208#L765-23 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 19207#L377-21 assume !(1 == ~t5_pc~0); 19205#L377-23 is_transmit5_triggered_~__retres1~5 := 0; 19204#L388-7 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 19203#L389-7 activate_threads_#t~ret13 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 19202#L773-21 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 19200#L773-23 assume 1 == ~M_E~0;~M_E~0 := 2; 19198#L657-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 19196#L662-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 19194#L667-3 assume !(1 == ~T3_E~0); 19192#L672-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 19190#L677-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 19189#L682-3 assume 1 == ~E_M~0;~E_M~0 := 2; 19188#L687-3 assume 1 == ~E_1~0;~E_1~0 := 2; 19187#L692-3 assume 1 == ~E_2~0;~E_2~0 := 2; 19186#L697-3 assume 1 == ~E_3~0;~E_3~0 := 2; 16916#L702-3 assume 1 == ~E_4~0;~E_4~0 := 2; 16726#L707-3 assume !(1 == ~E_5~0); 16727#L712-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 16590#L442-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 16538#L474-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 16623#L475-1 start_simulation_#t~ret15 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret15;havoc start_simulation_#t~ret15; 16624#L937 assume !(0 == start_simulation_~tmp~3); 16630#L937-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret14, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 16595#L442-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 16544#L474-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 16591#L475-2 stop_simulation_#t~ret14 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret14;havoc stop_simulation_#t~ret14; 16592#L892 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 16816#L899 stop_simulation_#res := stop_simulation_~__retres2~0; 16823#L900 start_simulation_#t~ret16 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret16;havoc start_simulation_#t~ret16; 16699#L950 assume !(0 != start_simulation_~tmp___0~1); 16397#L918-1 [2018-11-23 13:21:51,240 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 13:21:51,240 INFO L82 PathProgramCache]: Analyzing trace with hash -335164611, now seen corresponding path program 1 times [2018-11-23 13:21:51,240 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 13:21:51,240 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 13:21:51,241 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 13:21:51,241 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 13:21:51,241 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 13:21:51,245 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 13:21:51,263 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 13:21:51,264 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 13:21:51,264 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2018-11-23 13:21:51,264 INFO L799 eck$LassoCheckResult]: stem already infeasible [2018-11-23 13:21:51,264 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 13:21:51,264 INFO L82 PathProgramCache]: Analyzing trace with hash 535765393, now seen corresponding path program 1 times [2018-11-23 13:21:51,264 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 13:21:51,265 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 13:21:51,265 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 13:21:51,265 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 13:21:51,265 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 13:21:51,271 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 13:21:51,303 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 13:21:51,303 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 13:21:51,303 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-11-23 13:21:51,303 INFO L811 eck$LassoCheckResult]: loop already infeasible [2018-11-23 13:21:51,304 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-23 13:21:51,304 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-23 13:21:51,304 INFO L87 Difference]: Start difference. First operand 3088 states and 4452 transitions. cyclomatic complexity: 1372 Second operand 3 states. [2018-11-23 13:21:51,324 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 13:21:51,325 INFO L93 Difference]: Finished difference Result 3088 states and 4426 transitions. [2018-11-23 13:21:51,326 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-23 13:21:51,326 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 3088 states and 4426 transitions. [2018-11-23 13:21:51,334 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 2992 [2018-11-23 13:21:51,343 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 3088 states to 3088 states and 4426 transitions. [2018-11-23 13:21:51,343 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 3088 [2018-11-23 13:21:51,345 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 3088 [2018-11-23 13:21:51,346 INFO L73 IsDeterministic]: Start isDeterministic. Operand 3088 states and 4426 transitions. [2018-11-23 13:21:51,349 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-23 13:21:51,349 INFO L705 BuchiCegarLoop]: Abstraction has 3088 states and 4426 transitions. [2018-11-23 13:21:51,351 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3088 states and 4426 transitions. [2018-11-23 13:21:51,375 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3088 to 3088. [2018-11-23 13:21:51,375 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3088 states. [2018-11-23 13:21:51,380 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3088 states to 3088 states and 4426 transitions. [2018-11-23 13:21:51,380 INFO L728 BuchiCegarLoop]: Abstraction has 3088 states and 4426 transitions. [2018-11-23 13:21:51,380 INFO L608 BuchiCegarLoop]: Abstraction has 3088 states and 4426 transitions. [2018-11-23 13:21:51,380 INFO L442 BuchiCegarLoop]: ======== Iteration 12============ [2018-11-23 13:21:51,380 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 3088 states and 4426 transitions. [2018-11-23 13:21:51,388 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 2992 [2018-11-23 13:21:51,388 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-23 13:21:51,388 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-23 13:21:51,389 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 13:21:51,389 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 13:21:51,389 INFO L794 eck$LassoCheckResult]: Stem: 22998#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 22947#L-1 havoc main_#res;havoc main_~__retres1~7;havoc main_~__retres1~7;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 22948#L881 havoc start_simulation_#t~ret15, start_simulation_#t~ret16, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 22858#L397 assume 1 == ~m_i~0;~m_st~0 := 0; 22859#L404-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 22778#L409-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 22779#L414-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 22860#L419-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 22727#L424-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 22728#L429-1 assume !(0 == ~M_E~0); 22752#L589-1 assume !(0 == ~T1_E~0); 22753#L594-1 assume !(0 == ~T2_E~0); 22547#L599-1 assume !(0 == ~T3_E~0); 22548#L604-1 assume !(0 == ~T4_E~0); 22680#L609-1 assume !(0 == ~T5_E~0); 22681#L614-1 assume !(0 == ~E_M~0); 22913#L619-1 assume !(0 == ~E_1~0); 22914#L624-1 assume !(0 == ~E_2~0); 22793#L629-1 assume !(0 == ~E_3~0); 22794#L634-1 assume !(0 == ~E_4~0); 22866#L639-1 assume !(0 == ~E_5~0); 22742#L644-1 havoc activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 22743#L282 assume !(1 == ~m_pc~0); 23026#L282-2 is_master_triggered_~__retres1~0 := 0; 23027#L293 is_master_triggered_#res := is_master_triggered_~__retres1~0; 23028#L294 activate_threads_#t~ret8 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 23079#L733 assume !(0 != activate_threads_~tmp~1); 23080#L733-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 22662#L301 assume !(1 == ~t1_pc~0); 22655#L301-2 is_transmit1_triggered_~__retres1~1 := 0; 22622#L312 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 22623#L313 activate_threads_#t~ret9 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 22688#L741 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 22670#L741-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 22671#L320 assume !(1 == ~t2_pc~0); 22843#L320-2 is_transmit2_triggered_~__retres1~2 := 0; 22844#L331 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 22781#L332 activate_threads_#t~ret10 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 22782#L749 assume !(0 != activate_threads_~tmp___1~0); 22995#L749-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 22991#L339 assume !(1 == ~t3_pc~0); 22950#L339-2 is_transmit3_triggered_~__retres1~3 := 0; 22951#L350 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 22979#L351 activate_threads_#t~ret11 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 22980#L757 assume !(0 != activate_threads_~tmp___2~0); 23092#L757-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 22735#L358 assume !(1 == ~t4_pc~0); 22690#L358-2 is_transmit4_triggered_~__retres1~4 := 0; 22691#L369 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 22732#L370 activate_threads_#t~ret12 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 22760#L765 assume !(0 != activate_threads_~tmp___3~0); 22761#L765-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 22762#L377 assume !(1 == ~t5_pc~0); 22667#L377-2 is_transmit5_triggered_~__retres1~5 := 0; 22890#L388 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 22664#L389 activate_threads_#t~ret13 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 22665#L773 assume !(0 != activate_threads_~tmp___4~0); 22906#L773-2 assume !(1 == ~M_E~0); 22907#L657-1 assume !(1 == ~T1_E~0); 22811#L662-1 assume !(1 == ~T2_E~0); 22812#L667-1 assume !(1 == ~T3_E~0); 22996#L672-1 assume !(1 == ~T4_E~0); 22740#L677-1 assume !(1 == ~T5_E~0); 22741#L682-1 assume !(1 == ~E_M~0); 22538#L687-1 assume !(1 == ~E_1~0); 22539#L692-1 assume !(1 == ~E_2~0); 22672#L697-1 assume !(1 == ~E_3~0); 22673#L702-1 assume !(1 == ~E_4~0); 22908#L707-1 assume !(1 == ~E_5~0); 22582#L918-1 [2018-11-23 13:21:51,390 INFO L796 eck$LassoCheckResult]: Loop: 22582#L918-1 assume !false; 22583#L919 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret1, eval_#t~nondet2, eval_~tmp_ndt_1~0, eval_#t~nondet3, eval_~tmp_ndt_2~0, eval_#t~nondet4, eval_~tmp_ndt_3~0, eval_#t~nondet5, eval_~tmp_ndt_4~0, eval_#t~nondet6, eval_~tmp_ndt_5~0, eval_#t~nondet7, eval_~tmp_ndt_6~0, eval_~tmp~0;havoc eval_~tmp~0; 22749#L564 assume !false; 22872#L485 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 22806#L442 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 22721#L474 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 22805#L475 eval_#t~ret1 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret1;havoc eval_#t~ret1; 22768#L489 assume !(0 != eval_~tmp~0); 22770#L579 start_simulation_~kernel_st~0 := 2; 22862#L397-1 start_simulation_~kernel_st~0 := 3; 22756#L589-2 assume 0 == ~M_E~0;~M_E~0 := 1; 22715#L589-4 assume !(0 == ~T1_E~0); 22716#L594-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 22766#L599-3 assume !(0 == ~T3_E~0); 22767#L604-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 22651#L609-3 assume !(0 == ~T5_E~0); 22652#L614-3 assume 0 == ~E_M~0;~E_M~0 := 1; 22898#L619-3 assume 0 == ~E_1~0;~E_1~0 := 1; 22899#L624-3 assume 0 == ~E_2~0;~E_2~0 := 1; 22800#L629-3 assume !(0 == ~E_3~0); 22801#L634-3 assume 0 == ~E_4~0;~E_4~0 := 1; 22871#L639-3 assume !(0 == ~E_5~0); 22754#L644-3 havoc activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 22755#L282-21 assume !(1 == ~m_pc~0); 23114#L282-23 is_master_triggered_~__retres1~0 := 0; 23011#L293-7 is_master_triggered_#res := is_master_triggered_~__retres1~0; 23012#L294-7 activate_threads_#t~ret8 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 23018#L733-21 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 23019#L733-23 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 22565#L301-21 assume !(1 == ~t1_pc~0); 22563#L301-23 is_transmit1_triggered_~__retres1~1 := 0; 22564#L312-7 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 22606#L313-7 activate_threads_#t~ret9 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 22609#L741-21 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 22570#L741-23 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 22571#L320-21 assume !(1 == ~t2_pc~0); 22795#L320-23 is_transmit2_triggered_~__retres1~2 := 0; 22796#L331-7 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 22825#L332-7 activate_threads_#t~ret10 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 22831#L749-21 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 22832#L749-23 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 22840#L339-21 assume 1 == ~t3_pc~0; 22939#L340-7 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 22940#L350-7 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 22937#L351-7 activate_threads_#t~ret11 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 22938#L757-21 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 22981#L757-23 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 22982#L358-21 assume !(1 == ~t4_pc~0); 23081#L358-23 is_transmit4_triggered_~__retres1~4 := 0; 22711#L369-7 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 22712#L370-7 activate_threads_#t~ret12 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 23040#L765-21 assume !(0 != activate_threads_~tmp___3~0); 23087#L765-23 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 22669#L377-21 assume !(1 == ~t5_pc~0); 22597#L377-23 is_transmit5_triggered_~__retres1~5 := 0; 22676#L388-7 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 22591#L389-7 activate_threads_#t~ret13 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 22592#L773-21 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 22877#L773-23 assume 1 == ~M_E~0;~M_E~0 := 2; 22878#L657-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 22797#L662-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 22798#L667-3 assume !(1 == ~T3_E~0); 22869#L672-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 22746#L677-3 assume !(1 == ~T5_E~0); 22747#L682-3 assume 1 == ~E_M~0;~E_M~0 := 2; 22545#L687-3 assume 1 == ~E_1~0;~E_1~0 := 2; 22546#L692-3 assume 1 == ~E_2~0;~E_2~0 := 2; 22678#L697-3 assume 1 == ~E_3~0;~E_3~0 := 2; 22679#L702-3 assume 1 == ~E_4~0;~E_4~0 := 2; 22911#L707-3 assume !(1 == ~E_5~0); 22912#L712-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 22775#L442-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 22724#L474-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 22807#L475-1 start_simulation_#t~ret15 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret15;havoc start_simulation_#t~ret15; 22808#L937 assume !(0 == start_simulation_~tmp~3); 22815#L937-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret14, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 22780#L442-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 22730#L474-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 22776#L475-2 stop_simulation_#t~ret14 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret14;havoc stop_simulation_#t~ret14; 22777#L892 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 22997#L899 stop_simulation_#res := stop_simulation_~__retres2~0; 23004#L900 start_simulation_#t~ret16 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret16;havoc start_simulation_#t~ret16; 22883#L950 assume !(0 != start_simulation_~tmp___0~1); 22582#L918-1 [2018-11-23 13:21:51,390 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 13:21:51,390 INFO L82 PathProgramCache]: Analyzing trace with hash 1439842751, now seen corresponding path program 1 times [2018-11-23 13:21:51,390 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 13:21:51,390 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 13:21:51,391 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 13:21:51,391 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 13:21:51,391 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 13:21:51,397 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 13:21:51,456 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 13:21:51,456 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 13:21:51,456 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-11-23 13:21:51,456 INFO L799 eck$LassoCheckResult]: stem already infeasible [2018-11-23 13:21:51,456 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 13:21:51,457 INFO L82 PathProgramCache]: Analyzing trace with hash 672057101, now seen corresponding path program 1 times [2018-11-23 13:21:51,457 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 13:21:51,457 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 13:21:51,457 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 13:21:51,457 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 13:21:51,458 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 13:21:51,463 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 13:21:51,493 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 13:21:51,493 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 13:21:51,493 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-11-23 13:21:51,493 INFO L811 eck$LassoCheckResult]: loop already infeasible [2018-11-23 13:21:51,494 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-11-23 13:21:51,494 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-11-23 13:21:51,494 INFO L87 Difference]: Start difference. First operand 3088 states and 4426 transitions. cyclomatic complexity: 1346 Second operand 5 states. [2018-11-23 13:21:51,666 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 13:21:51,666 INFO L93 Difference]: Finished difference Result 8387 states and 11953 transitions. [2018-11-23 13:21:51,667 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2018-11-23 13:21:51,668 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 8387 states and 11953 transitions. [2018-11-23 13:21:51,696 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 8164 [2018-11-23 13:21:51,722 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 8387 states to 8387 states and 11953 transitions. [2018-11-23 13:21:51,723 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 8387 [2018-11-23 13:21:51,728 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 8387 [2018-11-23 13:21:51,729 INFO L73 IsDeterministic]: Start isDeterministic. Operand 8387 states and 11953 transitions. [2018-11-23 13:21:51,737 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-23 13:21:51,737 INFO L705 BuchiCegarLoop]: Abstraction has 8387 states and 11953 transitions. [2018-11-23 13:21:51,742 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 8387 states and 11953 transitions. [2018-11-23 13:21:51,831 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 8387 to 3247. [2018-11-23 13:21:51,831 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3247 states. [2018-11-23 13:21:51,837 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3247 states to 3247 states and 4585 transitions. [2018-11-23 13:21:51,837 INFO L728 BuchiCegarLoop]: Abstraction has 3247 states and 4585 transitions. [2018-11-23 13:21:51,837 INFO L608 BuchiCegarLoop]: Abstraction has 3247 states and 4585 transitions. [2018-11-23 13:21:51,837 INFO L442 BuchiCegarLoop]: ======== Iteration 13============ [2018-11-23 13:21:51,837 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 3247 states and 4585 transitions. [2018-11-23 13:21:51,844 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 3148 [2018-11-23 13:21:51,844 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-23 13:21:51,844 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-23 13:21:51,845 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 13:21:51,845 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 13:21:51,846 INFO L794 eck$LassoCheckResult]: Stem: 34531#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 34478#L-1 havoc main_#res;havoc main_~__retres1~7;havoc main_~__retres1~7;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 34479#L881 havoc start_simulation_#t~ret15, start_simulation_#t~ret16, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 34389#L397 assume 1 == ~m_i~0;~m_st~0 := 0; 34390#L404-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 34308#L409-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 34309#L414-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 34391#L419-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 34224#L424-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 34225#L429-1 assume !(0 == ~M_E~0); 34249#L589-1 assume !(0 == ~T1_E~0); 34250#L594-1 assume !(0 == ~T2_E~0); 34037#L599-1 assume !(0 == ~T3_E~0); 34038#L604-1 assume !(0 == ~T4_E~0); 34178#L609-1 assume !(0 == ~T5_E~0); 34179#L614-1 assume !(0 == ~E_M~0); 34450#L619-1 assume !(0 == ~E_1~0); 34451#L624-1 assume !(0 == ~E_2~0); 34322#L629-1 assume !(0 == ~E_3~0); 34323#L634-1 assume !(0 == ~E_4~0); 34397#L639-1 assume !(0 == ~E_5~0); 34239#L644-1 havoc activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 34240#L282 assume !(1 == ~m_pc~0); 34562#L282-2 is_master_triggered_~__retres1~0 := 0; 34563#L293 is_master_triggered_#res := is_master_triggered_~__retres1~0; 34564#L294 activate_threads_#t~ret8 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 34618#L733 assume !(0 != activate_threads_~tmp~1); 34619#L733-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 34159#L301 assume !(1 == ~t1_pc~0); 34152#L301-2 is_transmit1_triggered_~__retres1~1 := 0; 34118#L312 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 34119#L313 activate_threads_#t~ret9 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 34186#L741 assume !(0 != activate_threads_~tmp___0~0); 34167#L741-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 34168#L320 assume !(1 == ~t2_pc~0); 34376#L320-2 is_transmit2_triggered_~__retres1~2 := 0; 34377#L331 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 34310#L332 activate_threads_#t~ret10 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 34311#L749 assume !(0 != activate_threads_~tmp___1~0); 34528#L749-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 34524#L339 assume !(1 == ~t3_pc~0); 34481#L339-2 is_transmit3_triggered_~__retres1~3 := 0; 34482#L350 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 34511#L351 activate_threads_#t~ret11 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 34512#L757 assume !(0 != activate_threads_~tmp___2~0); 34630#L757-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 34232#L358 assume !(1 == ~t4_pc~0); 34188#L358-2 is_transmit4_triggered_~__retres1~4 := 0; 34189#L369 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 34229#L370 activate_threads_#t~ret12 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 34258#L765 assume !(0 != activate_threads_~tmp___3~0); 34259#L765-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 34260#L377 assume !(1 == ~t5_pc~0); 34164#L377-2 is_transmit5_triggered_~__retres1~5 := 0; 34428#L388 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 34161#L389 activate_threads_#t~ret13 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 34162#L773 assume !(0 != activate_threads_~tmp___4~0); 34442#L773-2 assume !(1 == ~M_E~0); 34443#L657-1 assume !(1 == ~T1_E~0); 34343#L662-1 assume !(1 == ~T2_E~0); 34344#L667-1 assume !(1 == ~T3_E~0); 34529#L672-1 assume !(1 == ~T4_E~0); 34237#L677-1 assume !(1 == ~T5_E~0); 34238#L682-1 assume !(1 == ~E_M~0); 34028#L687-1 assume !(1 == ~E_1~0); 34029#L692-1 assume !(1 == ~E_2~0); 34169#L697-1 assume !(1 == ~E_3~0); 34170#L702-1 assume !(1 == ~E_4~0); 34444#L707-1 assume !(1 == ~E_5~0); 34445#L918-1 [2018-11-23 13:21:51,846 INFO L796 eck$LassoCheckResult]: Loop: 34445#L918-1 assume !false; 35325#L919 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret1, eval_#t~nondet2, eval_~tmp_ndt_1~0, eval_#t~nondet3, eval_~tmp_ndt_2~0, eval_#t~nondet4, eval_~tmp_ndt_3~0, eval_#t~nondet5, eval_~tmp_ndt_4~0, eval_#t~nondet6, eval_~tmp_ndt_5~0, eval_#t~nondet7, eval_~tmp_ndt_6~0, eval_~tmp~0;havoc eval_~tmp~0; 35323#L564 assume !false; 35321#L485 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 35307#L442 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 35305#L474 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 35303#L475 eval_#t~ret1 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret1;havoc eval_#t~ret1; 35300#L489 assume !(0 != eval_~tmp~0); 35301#L579 start_simulation_~kernel_st~0 := 2; 35605#L397-1 start_simulation_~kernel_st~0 := 3; 35603#L589-2 assume 0 == ~M_E~0;~M_E~0 := 1; 35601#L589-4 assume !(0 == ~T1_E~0); 35599#L594-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 35597#L599-3 assume !(0 == ~T3_E~0); 35594#L604-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 35592#L609-3 assume !(0 == ~T5_E~0); 35590#L614-3 assume 0 == ~E_M~0;~E_M~0 := 1; 35588#L619-3 assume 0 == ~E_1~0;~E_1~0 := 1; 35586#L624-3 assume 0 == ~E_2~0;~E_2~0 := 1; 35585#L629-3 assume !(0 == ~E_3~0); 35581#L634-3 assume 0 == ~E_4~0;~E_4~0 := 1; 35579#L639-3 assume !(0 == ~E_5~0); 35578#L644-3 havoc activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 35577#L282-21 assume !(1 == ~m_pc~0); 35576#L282-23 is_master_triggered_~__retres1~0 := 0; 35575#L293-7 is_master_triggered_#res := is_master_triggered_~__retres1~0; 35574#L294-7 activate_threads_#t~ret8 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 35573#L733-21 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 35572#L733-23 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 35571#L301-21 assume 1 == ~t1_pc~0; 35569#L302-7 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 35567#L312-7 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 35565#L313-7 activate_threads_#t~ret9 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 35563#L741-21 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 35562#L741-23 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 35561#L320-21 assume !(1 == ~t2_pc~0); 35560#L320-23 is_transmit2_triggered_~__retres1~2 := 0; 35559#L331-7 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 35558#L332-7 activate_threads_#t~ret10 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 35557#L749-21 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 35556#L749-23 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 35555#L339-21 assume !(1 == ~t3_pc~0); 35553#L339-23 is_transmit3_triggered_~__retres1~3 := 0; 35552#L350-7 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 35551#L351-7 activate_threads_#t~ret11 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 35550#L757-21 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 35549#L757-23 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 35548#L358-21 assume !(1 == ~t4_pc~0); 35532#L358-23 is_transmit4_triggered_~__retres1~4 := 0; 35530#L369-7 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 35528#L370-7 activate_threads_#t~ret12 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 35525#L765-21 assume !(0 != activate_threads_~tmp___3~0); 35523#L765-23 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 35521#L377-21 assume !(1 == ~t5_pc~0); 35518#L377-23 is_transmit5_triggered_~__retres1~5 := 0; 35516#L388-7 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 35514#L389-7 activate_threads_#t~ret13 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 35511#L773-21 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 35509#L773-23 assume 1 == ~M_E~0;~M_E~0 := 2; 35507#L657-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 35505#L662-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 35503#L667-3 assume !(1 == ~T3_E~0); 35501#L672-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 35498#L677-3 assume !(1 == ~T5_E~0); 35496#L682-3 assume 1 == ~E_M~0;~E_M~0 := 2; 35494#L687-3 assume 1 == ~E_1~0;~E_1~0 := 2; 35492#L692-3 assume 1 == ~E_2~0;~E_2~0 := 2; 35490#L697-3 assume 1 == ~E_3~0;~E_3~0 := 2; 35489#L702-3 assume 1 == ~E_4~0;~E_4~0 := 2; 35488#L707-3 assume !(1 == ~E_5~0); 35487#L712-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 35483#L442-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 35477#L474-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 35475#L475-1 start_simulation_#t~ret15 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret15;havoc start_simulation_#t~ret15; 35471#L937 assume !(0 == start_simulation_~tmp~3); 35468#L937-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret14, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 35461#L442-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 35454#L474-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 35452#L475-2 stop_simulation_#t~ret14 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret14;havoc stop_simulation_#t~ret14; 35451#L892 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 35450#L899 stop_simulation_#res := stop_simulation_~__retres2~0; 35434#L900 start_simulation_#t~ret16 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret16;havoc start_simulation_#t~ret16; 35432#L950 assume !(0 != start_simulation_~tmp___0~1); 34445#L918-1 [2018-11-23 13:21:51,846 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 13:21:51,846 INFO L82 PathProgramCache]: Analyzing trace with hash 2099374273, now seen corresponding path program 1 times [2018-11-23 13:21:51,846 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 13:21:51,846 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 13:21:51,847 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 13:21:51,847 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 13:21:51,847 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 13:21:51,852 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-23 13:21:51,857 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-23 13:21:51,882 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 13:21:51,882 INFO L82 PathProgramCache]: Analyzing trace with hash -1586258547, now seen corresponding path program 1 times [2018-11-23 13:21:51,882 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 13:21:51,882 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 13:21:51,883 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 13:21:51,883 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 13:21:51,883 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 13:21:51,888 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 13:21:51,914 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 13:21:51,915 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 13:21:51,915 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-11-23 13:21:51,915 INFO L811 eck$LassoCheckResult]: loop already infeasible [2018-11-23 13:21:51,915 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-11-23 13:21:51,915 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-11-23 13:21:51,915 INFO L87 Difference]: Start difference. First operand 3247 states and 4585 transitions. cyclomatic complexity: 1346 Second operand 5 states. [2018-11-23 13:21:51,999 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 13:21:51,999 INFO L93 Difference]: Finished difference Result 5807 states and 8093 transitions. [2018-11-23 13:21:52,000 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2018-11-23 13:21:52,000 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 5807 states and 8093 transitions. [2018-11-23 13:21:52,015 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 5684 [2018-11-23 13:21:52,034 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 5807 states to 5807 states and 8093 transitions. [2018-11-23 13:21:52,034 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 5807 [2018-11-23 13:21:52,037 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 5807 [2018-11-23 13:21:52,037 INFO L73 IsDeterministic]: Start isDeterministic. Operand 5807 states and 8093 transitions. [2018-11-23 13:21:52,042 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-23 13:21:52,042 INFO L705 BuchiCegarLoop]: Abstraction has 5807 states and 8093 transitions. [2018-11-23 13:21:52,046 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 5807 states and 8093 transitions. [2018-11-23 13:21:52,078 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 5807 to 3271. [2018-11-23 13:21:52,078 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3271 states. [2018-11-23 13:21:52,082 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3271 states to 3271 states and 4609 transitions. [2018-11-23 13:21:52,083 INFO L728 BuchiCegarLoop]: Abstraction has 3271 states and 4609 transitions. [2018-11-23 13:21:52,083 INFO L608 BuchiCegarLoop]: Abstraction has 3271 states and 4609 transitions. [2018-11-23 13:21:52,083 INFO L442 BuchiCegarLoop]: ======== Iteration 14============ [2018-11-23 13:21:52,083 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 3271 states and 4609 transitions. [2018-11-23 13:21:52,090 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 3172 [2018-11-23 13:21:52,090 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-23 13:21:52,091 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-23 13:21:52,092 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 13:21:52,092 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 13:21:52,092 INFO L794 eck$LassoCheckResult]: Stem: 43577#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 43525#L-1 havoc main_#res;havoc main_~__retres1~7;havoc main_~__retres1~7;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 43526#L881 havoc start_simulation_#t~ret15, start_simulation_#t~ret16, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 43430#L397 assume 1 == ~m_i~0;~m_st~0 := 0; 43431#L404-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 43350#L409-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 43351#L414-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 43434#L419-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 43291#L424-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 43292#L429-1 assume !(0 == ~M_E~0); 43316#L589-1 assume !(0 == ~T1_E~0); 43317#L594-1 assume !(0 == ~T2_E~0); 43107#L599-1 assume !(0 == ~T3_E~0); 43108#L604-1 assume !(0 == ~T4_E~0); 43245#L609-1 assume !(0 == ~T5_E~0); 43246#L614-1 assume !(0 == ~E_M~0); 43495#L619-1 assume !(0 == ~E_1~0); 43496#L624-1 assume !(0 == ~E_2~0); 43364#L629-1 assume !(0 == ~E_3~0); 43365#L634-1 assume !(0 == ~E_4~0); 43440#L639-1 assume !(0 == ~E_5~0); 43306#L644-1 havoc activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 43307#L282 assume !(1 == ~m_pc~0); 43611#L282-2 is_master_triggered_~__retres1~0 := 0; 43614#L293 is_master_triggered_#res := is_master_triggered_~__retres1~0; 43615#L294 activate_threads_#t~ret8 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 43666#L733 assume !(0 != activate_threads_~tmp~1); 43667#L733-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 43226#L301 assume !(1 == ~t1_pc~0); 43218#L301-2 is_transmit1_triggered_~__retres1~1 := 0; 43219#L312 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 43333#L313 activate_threads_#t~ret9 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 43254#L741 assume !(0 != activate_threads_~tmp___0~0); 43234#L741-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 43235#L320 assume !(1 == ~t2_pc~0); 43419#L320-2 is_transmit2_triggered_~__retres1~2 := 0; 43420#L331 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 43352#L332 activate_threads_#t~ret10 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 43353#L749 assume !(0 != activate_threads_~tmp___1~0); 43574#L749-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 43569#L339 assume !(1 == ~t3_pc~0); 43528#L339-2 is_transmit3_triggered_~__retres1~3 := 0; 43529#L350 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 43558#L351 activate_threads_#t~ret11 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 43559#L757 assume !(0 != activate_threads_~tmp___2~0); 43686#L757-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 43299#L358 assume !(1 == ~t4_pc~0); 43255#L358-2 is_transmit4_triggered_~__retres1~4 := 0; 43256#L369 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 43298#L370 activate_threads_#t~ret12 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 43324#L765 assume !(0 != activate_threads_~tmp___3~0); 43325#L765-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 43326#L377 assume !(1 == ~t5_pc~0); 43232#L377-2 is_transmit5_triggered_~__retres1~5 := 0; 43476#L388 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 43228#L389 activate_threads_#t~ret13 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 43229#L773 assume !(0 != activate_threads_~tmp___4~0); 43488#L773-2 assume !(1 == ~M_E~0); 43489#L657-1 assume !(1 == ~T1_E~0); 43384#L662-1 assume !(1 == ~T2_E~0); 43385#L667-1 assume !(1 == ~T3_E~0); 43575#L672-1 assume !(1 == ~T4_E~0); 43304#L677-1 assume !(1 == ~T5_E~0); 43305#L682-1 assume !(1 == ~E_M~0); 43098#L687-1 assume !(1 == ~E_1~0); 43099#L692-1 assume !(1 == ~E_2~0); 43236#L697-1 assume !(1 == ~E_3~0); 43237#L702-1 assume !(1 == ~E_4~0); 43490#L707-1 assume !(1 == ~E_5~0); 43491#L918-1 [2018-11-23 13:21:52,092 INFO L796 eck$LassoCheckResult]: Loop: 43491#L918-1 assume !false; 45931#L919 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret1, eval_#t~nondet2, eval_~tmp_ndt_1~0, eval_#t~nondet3, eval_~tmp_ndt_2~0, eval_#t~nondet4, eval_~tmp_ndt_3~0, eval_#t~nondet5, eval_~tmp_ndt_4~0, eval_#t~nondet6, eval_~tmp_ndt_5~0, eval_#t~nondet7, eval_~tmp_ndt_6~0, eval_~tmp~0;havoc eval_~tmp~0; 45441#L564 assume !false; 44888#L485 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 44877#L442 assume !(0 == ~m_st~0); 44878#L446 assume !(0 == ~t1_st~0); 44881#L450 assume !(0 == ~t2_st~0); 44882#L454 assume !(0 == ~t3_st~0); 44879#L458 assume !(0 == ~t4_st~0); 44880#L462 assume !(0 == ~t5_st~0);exists_runnable_thread_~__retres1~6 := 0; 43450#L474 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 43451#L475 eval_#t~ret1 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret1;havoc eval_#t~ret1; 44428#L489 assume !(0 != eval_~tmp~0); 44832#L579 start_simulation_~kernel_st~0 := 2; 44831#L397-1 start_simulation_~kernel_st~0 := 3; 44830#L589-2 assume 0 == ~M_E~0;~M_E~0 := 1; 44829#L589-4 assume !(0 == ~T1_E~0); 44828#L594-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 44827#L599-3 assume !(0 == ~T3_E~0); 44826#L604-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 44825#L609-3 assume !(0 == ~T5_E~0); 44824#L614-3 assume 0 == ~E_M~0;~E_M~0 := 1; 44823#L619-3 assume 0 == ~E_1~0;~E_1~0 := 1; 44822#L624-3 assume 0 == ~E_2~0;~E_2~0 := 1; 44821#L629-3 assume !(0 == ~E_3~0); 44820#L634-3 assume 0 == ~E_4~0;~E_4~0 := 1; 44819#L639-3 assume !(0 == ~E_5~0); 43318#L644-3 havoc activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 43319#L282-21 assume !(1 == ~m_pc~0); 43706#L282-23 is_master_triggered_~__retres1~0 := 0; 45798#L293-7 is_master_triggered_#res := is_master_triggered_~__retres1~0; 45797#L294-7 activate_threads_#t~ret8 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 45796#L733-21 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 45795#L733-23 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 43124#L301-21 assume !(1 == ~t1_pc~0); 43125#L301-23 is_transmit1_triggered_~__retres1~1 := 0; 46091#L312-7 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 46092#L313-7 activate_threads_#t~ret9 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 43173#L741-21 assume !(0 != activate_threads_~tmp___0~0); 43130#L741-23 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 43131#L320-21 assume !(1 == ~t2_pc~0); 43383#L320-23 is_transmit2_triggered_~__retres1~2 := 0; 46014#L331-7 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 46013#L332-7 activate_threads_#t~ret10 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 46012#L749-21 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 43413#L749-23 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 43414#L339-21 assume 1 == ~t3_pc~0; 43517#L340-7 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 43518#L350-7 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 43515#L351-7 activate_threads_#t~ret11 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 43516#L757-21 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 43560#L757-23 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 43561#L358-21 assume !(1 == ~t4_pc~0); 46004#L358-23 is_transmit4_triggered_~__retres1~4 := 0; 46003#L369-7 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 46002#L370-7 activate_threads_#t~ret12 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 46001#L765-21 assume !(0 != activate_threads_~tmp___3~0); 46000#L765-23 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 45999#L377-21 assume !(1 == ~t5_pc~0); 45997#L377-23 is_transmit5_triggered_~__retres1~5 := 0; 45996#L388-7 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 45995#L389-7 activate_threads_#t~ret13 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 45994#L773-21 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 45993#L773-23 assume 1 == ~M_E~0;~M_E~0 := 2; 45992#L657-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 45991#L662-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 45990#L667-3 assume !(1 == ~T3_E~0); 45989#L672-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 45988#L677-3 assume !(1 == ~T5_E~0); 45987#L682-3 assume 1 == ~E_M~0;~E_M~0 := 2; 45986#L687-3 assume 1 == ~E_1~0;~E_1~0 := 2; 45985#L692-3 assume 1 == ~E_2~0;~E_2~0 := 2; 45984#L697-3 assume 1 == ~E_3~0;~E_3~0 := 2; 45983#L702-3 assume 1 == ~E_4~0;~E_4~0 := 2; 45982#L707-3 assume !(1 == ~E_5~0); 45981#L712-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 45979#L442-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 45970#L474-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 45965#L475-1 start_simulation_#t~ret15 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret15;havoc start_simulation_#t~ret15; 45962#L937 assume !(0 == start_simulation_~tmp~3); 45960#L937-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret14, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 45957#L442-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 45952#L474-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 45950#L475-2 stop_simulation_#t~ret14 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret14;havoc stop_simulation_#t~ret14; 45948#L892 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 45946#L899 stop_simulation_#res := stop_simulation_~__retres2~0; 45945#L900 start_simulation_#t~ret16 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret16;havoc start_simulation_#t~ret16; 45939#L950 assume !(0 != start_simulation_~tmp___0~1); 43491#L918-1 [2018-11-23 13:21:52,092 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 13:21:52,092 INFO L82 PathProgramCache]: Analyzing trace with hash 2099374273, now seen corresponding path program 2 times [2018-11-23 13:21:52,093 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 13:21:52,093 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 13:21:52,093 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 13:21:52,093 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 13:21:52,094 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 13:21:52,098 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-23 13:21:52,104 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-23 13:21:52,119 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 13:21:52,119 INFO L82 PathProgramCache]: Analyzing trace with hash -486807708, now seen corresponding path program 1 times [2018-11-23 13:21:52,119 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 13:21:52,119 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 13:21:52,120 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 13:21:52,120 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-23 13:21:52,120 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 13:21:52,126 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 13:21:52,198 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 13:21:52,198 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 13:21:52,198 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-11-23 13:21:52,199 INFO L811 eck$LassoCheckResult]: loop already infeasible [2018-11-23 13:21:52,199 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-11-23 13:21:52,199 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-11-23 13:21:52,199 INFO L87 Difference]: Start difference. First operand 3271 states and 4609 transitions. cyclomatic complexity: 1346 Second operand 5 states. [2018-11-23 13:21:52,348 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 13:21:52,348 INFO L93 Difference]: Finished difference Result 6431 states and 8996 transitions. [2018-11-23 13:21:52,349 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2018-11-23 13:21:52,349 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 6431 states and 8996 transitions. [2018-11-23 13:21:52,367 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 6316 [2018-11-23 13:21:52,386 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 6431 states to 6431 states and 8996 transitions. [2018-11-23 13:21:52,386 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 6431 [2018-11-23 13:21:52,389 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 6431 [2018-11-23 13:21:52,389 INFO L73 IsDeterministic]: Start isDeterministic. Operand 6431 states and 8996 transitions. [2018-11-23 13:21:52,396 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-23 13:21:52,396 INFO L705 BuchiCegarLoop]: Abstraction has 6431 states and 8996 transitions. [2018-11-23 13:21:52,400 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 6431 states and 8996 transitions. [2018-11-23 13:21:52,430 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 6431 to 3355. [2018-11-23 13:21:52,431 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3355 states. [2018-11-23 13:21:52,435 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3355 states to 3355 states and 4668 transitions. [2018-11-23 13:21:52,435 INFO L728 BuchiCegarLoop]: Abstraction has 3355 states and 4668 transitions. [2018-11-23 13:21:52,435 INFO L608 BuchiCegarLoop]: Abstraction has 3355 states and 4668 transitions. [2018-11-23 13:21:52,435 INFO L442 BuchiCegarLoop]: ======== Iteration 15============ [2018-11-23 13:21:52,436 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 3355 states and 4668 transitions. [2018-11-23 13:21:52,442 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 3256 [2018-11-23 13:21:52,442 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-23 13:21:52,442 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-23 13:21:52,443 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 13:21:52,443 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 13:21:52,444 INFO L794 eck$LassoCheckResult]: Stem: 53316#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 53251#L-1 havoc main_#res;havoc main_~__retres1~7;havoc main_~__retres1~7;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 53252#L881 havoc start_simulation_#t~ret15, start_simulation_#t~ret16, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 53160#L397 assume 1 == ~m_i~0;~m_st~0 := 0; 53161#L404-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 53071#L409-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 53072#L414-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 53163#L419-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 53006#L424-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 53007#L429-1 assume !(0 == ~M_E~0); 53031#L589-1 assume !(0 == ~T1_E~0); 53032#L594-1 assume !(0 == ~T2_E~0); 52822#L599-1 assume !(0 == ~T3_E~0); 52823#L604-1 assume !(0 == ~T4_E~0); 52961#L609-1 assume !(0 == ~T5_E~0); 52962#L614-1 assume !(0 == ~E_M~0); 53220#L619-1 assume !(0 == ~E_1~0); 53221#L624-1 assume !(0 == ~E_2~0); 53085#L629-1 assume !(0 == ~E_3~0); 53086#L634-1 assume !(0 == ~E_4~0); 53168#L639-1 assume !(0 == ~E_5~0); 53021#L644-1 havoc activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 53022#L282 assume !(1 == ~m_pc~0); 53353#L282-2 is_master_triggered_~__retres1~0 := 0; 53354#L293 is_master_triggered_#res := is_master_triggered_~__retres1~0; 53355#L294 activate_threads_#t~ret8 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 53414#L733 assume !(0 != activate_threads_~tmp~1); 53415#L733-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 52942#L301 assume !(1 == ~t1_pc~0); 52933#L301-2 is_transmit1_triggered_~__retres1~1 := 0; 52934#L312 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 53051#L313 activate_threads_#t~ret9 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 52969#L741 assume !(0 != activate_threads_~tmp___0~0); 52950#L741-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 52951#L320 assume !(1 == ~t2_pc~0); 53147#L320-2 is_transmit2_triggered_~__retres1~2 := 0; 53148#L331 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 53073#L332 activate_threads_#t~ret10 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 53074#L749 assume !(0 != activate_threads_~tmp___1~0); 53313#L749-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 53303#L339 assume !(1 == ~t3_pc~0); 53254#L339-2 is_transmit3_triggered_~__retres1~3 := 0; 53255#L350 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 53283#L351 activate_threads_#t~ret11 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 53284#L757 assume !(0 != activate_threads_~tmp___2~0); 53432#L757-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 53014#L358 assume !(1 == ~t4_pc~0); 52970#L358-2 is_transmit4_triggered_~__retres1~4 := 0; 52971#L369 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 53013#L370 activate_threads_#t~ret12 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 53040#L765 assume !(0 != activate_threads_~tmp___3~0); 53041#L765-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 53042#L377 assume !(1 == ~t5_pc~0); 52948#L377-2 is_transmit5_triggered_~__retres1~5 := 0; 53196#L388 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 52944#L389 activate_threads_#t~ret13 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 52945#L773 assume !(0 != activate_threads_~tmp___4~0); 53213#L773-2 assume !(1 == ~M_E~0); 53214#L657-1 assume !(1 == ~T1_E~0); 53110#L662-1 assume !(1 == ~T2_E~0); 53111#L667-1 assume !(1 == ~T3_E~0); 53314#L672-1 assume !(1 == ~T4_E~0); 53019#L677-1 assume !(1 == ~T5_E~0); 53020#L682-1 assume !(1 == ~E_M~0); 52813#L687-1 assume !(1 == ~E_1~0); 52814#L692-1 assume !(1 == ~E_2~0); 52952#L697-1 assume !(1 == ~E_3~0); 52953#L702-1 assume !(1 == ~E_4~0); 53216#L707-1 assume !(1 == ~E_5~0); 53217#L918-1 [2018-11-23 13:21:52,444 INFO L796 eck$LassoCheckResult]: Loop: 53217#L918-1 assume !false; 54771#L919 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret1, eval_#t~nondet2, eval_~tmp_ndt_1~0, eval_#t~nondet3, eval_~tmp_ndt_2~0, eval_#t~nondet4, eval_~tmp_ndt_3~0, eval_#t~nondet5, eval_~tmp_ndt_4~0, eval_#t~nondet6, eval_~tmp_ndt_5~0, eval_#t~nondet7, eval_~tmp_ndt_6~0, eval_~tmp~0;havoc eval_~tmp~0; 54770#L564 assume !false; 54769#L485 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 54762#L442 assume !(0 == ~m_st~0); 54763#L446 assume !(0 == ~t1_st~0); 54766#L450 assume !(0 == ~t2_st~0); 54768#L454 assume !(0 == ~t3_st~0); 54764#L458 assume !(0 == ~t4_st~0); 54765#L462 assume !(0 == ~t5_st~0);exists_runnable_thread_~__retres1~6 := 0; 54767#L474 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 54400#L475 eval_#t~ret1 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret1;havoc eval_#t~ret1; 54401#L489 assume !(0 != eval_~tmp~0); 54964#L579 start_simulation_~kernel_st~0 := 2; 54963#L397-1 start_simulation_~kernel_st~0 := 3; 54962#L589-2 assume 0 == ~M_E~0;~M_E~0 := 1; 54961#L589-4 assume !(0 == ~T1_E~0); 54960#L594-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 54959#L599-3 assume !(0 == ~T3_E~0); 54958#L604-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 54957#L609-3 assume !(0 == ~T5_E~0); 54956#L614-3 assume 0 == ~E_M~0;~E_M~0 := 1; 54955#L619-3 assume 0 == ~E_1~0;~E_1~0 := 1; 54954#L624-3 assume 0 == ~E_2~0;~E_2~0 := 1; 54953#L629-3 assume !(0 == ~E_3~0); 54952#L634-3 assume 0 == ~E_4~0;~E_4~0 := 1; 54951#L639-3 assume !(0 == ~E_5~0); 54950#L644-3 havoc activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 54949#L282-21 assume !(1 == ~m_pc~0); 54948#L282-23 is_master_triggered_~__retres1~0 := 0; 54947#L293-7 is_master_triggered_#res := is_master_triggered_~__retres1~0; 54946#L294-7 activate_threads_#t~ret8 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 54945#L733-21 assume !(0 != activate_threads_~tmp~1); 54943#L733-23 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 54941#L301-21 assume 1 == ~t1_pc~0; 54938#L302-7 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 54935#L312-7 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 54932#L313-7 activate_threads_#t~ret9 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 54929#L741-21 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 54927#L741-23 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 54924#L320-21 assume !(1 == ~t2_pc~0); 54921#L320-23 is_transmit2_triggered_~__retres1~2 := 0; 54918#L331-7 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 54915#L332-7 activate_threads_#t~ret10 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 54913#L749-21 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 54911#L749-23 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 54909#L339-21 assume !(1 == ~t3_pc~0); 54906#L339-23 is_transmit3_triggered_~__retres1~3 := 0; 54904#L350-7 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 54902#L351-7 activate_threads_#t~ret11 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 54900#L757-21 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 54898#L757-23 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 54894#L358-21 assume !(1 == ~t4_pc~0); 54891#L358-23 is_transmit4_triggered_~__retres1~4 := 0; 54888#L369-7 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 54885#L370-7 activate_threads_#t~ret12 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 54882#L765-21 assume !(0 != activate_threads_~tmp___3~0); 54879#L765-23 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 54876#L377-21 assume !(1 == ~t5_pc~0); 54871#L377-23 is_transmit5_triggered_~__retres1~5 := 0; 54867#L388-7 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 54863#L389-7 activate_threads_#t~ret13 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 54859#L773-21 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 54855#L773-23 assume 1 == ~M_E~0;~M_E~0 := 2; 54852#L657-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 54849#L662-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 54846#L667-3 assume !(1 == ~T3_E~0); 54843#L672-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 54840#L677-3 assume !(1 == ~T5_E~0); 54837#L682-3 assume 1 == ~E_M~0;~E_M~0 := 2; 54834#L687-3 assume 1 == ~E_1~0;~E_1~0 := 2; 54830#L692-3 assume 1 == ~E_2~0;~E_2~0 := 2; 54827#L697-3 assume 1 == ~E_3~0;~E_3~0 := 2; 54824#L702-3 assume 1 == ~E_4~0;~E_4~0 := 2; 54821#L707-3 assume !(1 == ~E_5~0); 54818#L712-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 54814#L442-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 54807#L474-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 54804#L475-1 start_simulation_#t~ret15 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret15;havoc start_simulation_#t~ret15; 54800#L937 assume !(0 == start_simulation_~tmp~3); 54798#L937-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret14, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 54794#L442-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 54788#L474-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 54786#L475-2 stop_simulation_#t~ret14 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret14;havoc stop_simulation_#t~ret14; 54784#L892 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 54782#L899 stop_simulation_#res := stop_simulation_~__retres2~0; 54780#L900 start_simulation_#t~ret16 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret16;havoc start_simulation_#t~ret16; 54776#L950 assume !(0 != start_simulation_~tmp___0~1); 53217#L918-1 [2018-11-23 13:21:52,444 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 13:21:52,444 INFO L82 PathProgramCache]: Analyzing trace with hash 2099374273, now seen corresponding path program 3 times [2018-11-23 13:21:52,444 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 13:21:52,444 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 13:21:52,445 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 13:21:52,445 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 13:21:52,445 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 13:21:52,449 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-23 13:21:52,454 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-23 13:21:52,466 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 13:21:52,466 INFO L82 PathProgramCache]: Analyzing trace with hash 2071598948, now seen corresponding path program 1 times [2018-11-23 13:21:52,466 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 13:21:52,466 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 13:21:52,467 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 13:21:52,467 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-23 13:21:52,467 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 13:21:52,471 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 13:21:52,489 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 13:21:52,490 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 13:21:52,490 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-23 13:21:52,490 INFO L811 eck$LassoCheckResult]: loop already infeasible [2018-11-23 13:21:52,490 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-23 13:21:52,490 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-23 13:21:52,490 INFO L87 Difference]: Start difference. First operand 3355 states and 4668 transitions. cyclomatic complexity: 1321 Second operand 3 states. [2018-11-23 13:21:52,548 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 13:21:52,548 INFO L93 Difference]: Finished difference Result 5757 states and 7894 transitions. [2018-11-23 13:21:52,549 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-23 13:21:52,550 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 5757 states and 7894 transitions. [2018-11-23 13:21:52,564 INFO L131 ngComponentsAnalysis]: Automaton has 12 accepting balls. 5640 [2018-11-23 13:21:52,575 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 5757 states to 5757 states and 7894 transitions. [2018-11-23 13:21:52,575 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 5757 [2018-11-23 13:21:52,578 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 5757 [2018-11-23 13:21:52,578 INFO L73 IsDeterministic]: Start isDeterministic. Operand 5757 states and 7894 transitions. [2018-11-23 13:21:52,583 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-23 13:21:52,583 INFO L705 BuchiCegarLoop]: Abstraction has 5757 states and 7894 transitions. [2018-11-23 13:21:52,587 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 5757 states and 7894 transitions. [2018-11-23 13:21:52,626 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 5757 to 5605. [2018-11-23 13:21:52,626 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 5605 states. [2018-11-23 13:21:52,633 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 5605 states to 5605 states and 7694 transitions. [2018-11-23 13:21:52,633 INFO L728 BuchiCegarLoop]: Abstraction has 5605 states and 7694 transitions. [2018-11-23 13:21:52,633 INFO L608 BuchiCegarLoop]: Abstraction has 5605 states and 7694 transitions. [2018-11-23 13:21:52,634 INFO L442 BuchiCegarLoop]: ======== Iteration 16============ [2018-11-23 13:21:52,634 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 5605 states and 7694 transitions. [2018-11-23 13:21:52,646 INFO L131 ngComponentsAnalysis]: Automaton has 12 accepting balls. 5488 [2018-11-23 13:21:52,646 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-23 13:21:52,646 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-23 13:21:52,647 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 13:21:52,647 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 13:21:52,647 INFO L794 eck$LassoCheckResult]: Stem: 62419#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 62364#L-1 havoc main_#res;havoc main_~__retres1~7;havoc main_~__retres1~7;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 62365#L881 havoc start_simulation_#t~ret15, start_simulation_#t~ret16, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 62269#L397 assume 1 == ~m_i~0;~m_st~0 := 0; 62270#L404-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 62186#L409-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 62187#L414-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 62272#L419-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 62124#L424-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 62125#L429-1 assume !(0 == ~M_E~0); 62149#L589-1 assume !(0 == ~T1_E~0); 62150#L594-1 assume !(0 == ~T2_E~0); 61940#L599-1 assume !(0 == ~T3_E~0); 61941#L604-1 assume !(0 == ~T4_E~0); 62077#L609-1 assume !(0 == ~T5_E~0); 62078#L614-1 assume !(0 == ~E_M~0); 62332#L619-1 assume !(0 == ~E_1~0); 62333#L624-1 assume !(0 == ~E_2~0); 62200#L629-1 assume !(0 == ~E_3~0); 62201#L634-1 assume !(0 == ~E_4~0); 62278#L639-1 assume !(0 == ~E_5~0); 62139#L644-1 havoc activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 62140#L282 assume !(1 == ~m_pc~0); 62452#L282-2 is_master_triggered_~__retres1~0 := 0; 62455#L293 is_master_triggered_#res := is_master_triggered_~__retres1~0; 62456#L294 activate_threads_#t~ret8 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 62502#L733 assume !(0 != activate_threads_~tmp~1); 62503#L733-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 62058#L301 assume !(1 == ~t1_pc~0); 62050#L301-2 is_transmit1_triggered_~__retres1~1 := 0; 62051#L312 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 62169#L313 activate_threads_#t~ret9 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 62085#L741 assume !(0 != activate_threads_~tmp___0~0); 62066#L741-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 62067#L320 assume !(1 == ~t2_pc~0); 62255#L320-2 is_transmit2_triggered_~__retres1~2 := 0; 62256#L331 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 62188#L332 activate_threads_#t~ret10 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 62189#L749 assume !(0 != activate_threads_~tmp___1~0); 62415#L749-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 62409#L339 assume !(1 == ~t3_pc~0); 62367#L339-2 is_transmit3_triggered_~__retres1~3 := 0; 62368#L350 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 62396#L351 activate_threads_#t~ret11 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 62397#L757 assume !(0 != activate_threads_~tmp___2~0); 62517#L757-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 62132#L358 assume !(1 == ~t4_pc~0); 62086#L358-2 is_transmit4_triggered_~__retres1~4 := 0; 62087#L369 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 62131#L370 activate_threads_#t~ret12 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 62157#L765 assume !(0 != activate_threads_~tmp___3~0); 62158#L765-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 62159#L377 assume !(1 == ~t5_pc~0); 62064#L377-2 is_transmit5_triggered_~__retres1~5 := 0; 62309#L388 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 62060#L389 activate_threads_#t~ret13 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 62061#L773 assume !(0 != activate_threads_~tmp___4~0); 62323#L773-2 assume !(1 == ~M_E~0); 62324#L657-1 assume !(1 == ~T1_E~0); 62222#L662-1 assume !(1 == ~T2_E~0); 62223#L667-1 assume !(1 == ~T3_E~0); 62416#L672-1 assume !(1 == ~T4_E~0); 62137#L677-1 assume !(1 == ~T5_E~0); 62138#L682-1 assume !(1 == ~E_M~0); 61931#L687-1 assume !(1 == ~E_1~0); 61932#L692-1 assume !(1 == ~E_2~0); 62068#L697-1 assume !(1 == ~E_3~0); 62069#L702-1 assume !(1 == ~E_4~0); 62326#L707-1 assume !(1 == ~E_5~0); 62327#L918-1 assume !false; 65391#L919 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret1, eval_#t~nondet2, eval_~tmp_ndt_1~0, eval_#t~nondet3, eval_~tmp_ndt_2~0, eval_#t~nondet4, eval_~tmp_ndt_3~0, eval_#t~nondet5, eval_~tmp_ndt_4~0, eval_#t~nondet6, eval_~tmp_ndt_5~0, eval_#t~nondet7, eval_~tmp_ndt_6~0, eval_~tmp~0;havoc eval_~tmp~0; 65389#L564 [2018-11-23 13:21:52,648 INFO L796 eck$LassoCheckResult]: Loop: 65389#L564 assume !false; 65387#L485 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 65385#L442 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 65383#L474 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 65381#L475 eval_#t~ret1 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret1;havoc eval_#t~ret1; 65379#L489 assume 0 != eval_~tmp~0; 65377#L489-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0;eval_~tmp_ndt_1~0 := eval_#t~nondet2;havoc eval_#t~nondet2; 65374#L497 assume !(0 != eval_~tmp_ndt_1~0); 65316#L494 assume !(0 == ~t1_st~0); 65296#L508 assume !(0 == ~t2_st~0); 65286#L522 assume !(0 == ~t3_st~0); 65281#L536 assume !(0 == ~t4_st~0); 65280#L550 assume !(0 == ~t5_st~0); 65389#L564 [2018-11-23 13:21:52,648 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 13:21:52,648 INFO L82 PathProgramCache]: Analyzing trace with hash -1135942013, now seen corresponding path program 1 times [2018-11-23 13:21:52,648 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 13:21:52,648 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 13:21:52,649 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 13:21:52,649 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 13:21:52,649 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 13:21:52,654 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-23 13:21:52,659 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-23 13:21:52,672 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 13:21:52,673 INFO L82 PathProgramCache]: Analyzing trace with hash 1714025377, now seen corresponding path program 1 times [2018-11-23 13:21:52,673 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 13:21:52,673 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 13:21:52,673 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 13:21:52,674 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 13:21:52,674 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 13:21:52,675 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-23 13:21:52,677 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-23 13:21:52,679 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 13:21:52,679 INFO L82 PathProgramCache]: Analyzing trace with hash 1743073375, now seen corresponding path program 1 times [2018-11-23 13:21:52,679 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 13:21:52,680 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 13:21:52,680 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 13:21:52,680 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 13:21:52,680 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 13:21:52,686 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 13:21:52,720 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 13:21:52,720 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 13:21:52,720 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-23 13:21:52,772 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-23 13:21:52,772 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-23 13:21:52,772 INFO L87 Difference]: Start difference. First operand 5605 states and 7694 transitions. cyclomatic complexity: 2101 Second operand 3 states. [2018-11-23 13:21:52,905 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 13:21:52,905 INFO L93 Difference]: Finished difference Result 10453 states and 14246 transitions. [2018-11-23 13:21:52,907 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-23 13:21:52,907 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 10453 states and 14246 transitions. [2018-11-23 13:21:52,934 INFO L131 ngComponentsAnalysis]: Automaton has 12 accepting balls. 10224 [2018-11-23 13:21:52,955 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 10453 states to 10453 states and 14246 transitions. [2018-11-23 13:21:52,955 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 10453 [2018-11-23 13:21:52,960 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 10453 [2018-11-23 13:21:52,960 INFO L73 IsDeterministic]: Start isDeterministic. Operand 10453 states and 14246 transitions. [2018-11-23 13:21:52,969 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-23 13:21:52,969 INFO L705 BuchiCegarLoop]: Abstraction has 10453 states and 14246 transitions. [2018-11-23 13:21:52,976 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 10453 states and 14246 transitions. [2018-11-23 13:21:53,049 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 10453 to 9973. [2018-11-23 13:21:53,049 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 9973 states. [2018-11-23 13:21:53,065 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 9973 states to 9973 states and 13622 transitions. [2018-11-23 13:21:53,065 INFO L728 BuchiCegarLoop]: Abstraction has 9973 states and 13622 transitions. [2018-11-23 13:21:53,065 INFO L608 BuchiCegarLoop]: Abstraction has 9973 states and 13622 transitions. [2018-11-23 13:21:53,065 INFO L442 BuchiCegarLoop]: ======== Iteration 17============ [2018-11-23 13:21:53,066 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 9973 states and 13622 transitions. [2018-11-23 13:21:53,090 INFO L131 ngComponentsAnalysis]: Automaton has 12 accepting balls. 9744 [2018-11-23 13:21:53,090 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-23 13:21:53,090 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-23 13:21:53,091 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 13:21:53,091 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 13:21:53,091 INFO L794 eck$LassoCheckResult]: Stem: 78520#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 78452#L-1 havoc main_#res;havoc main_~__retres1~7;havoc main_~__retres1~7;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 78453#L881 havoc start_simulation_#t~ret15, start_simulation_#t~ret16, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 78347#L397 assume 1 == ~m_i~0;~m_st~0 := 0; 78348#L404-1 assume !(1 == ~t1_i~0);~t1_st~0 := 2; 78265#L409-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 78266#L414-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 78349#L419-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 78350#L424-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 78524#L429-1 assume !(0 == ~M_E~0); 78525#L589-1 assume !(0 == ~T1_E~0); 78530#L594-1 assume !(0 == ~T2_E~0); 78531#L599-1 assume !(0 == ~T3_E~0); 78490#L604-1 assume !(0 == ~T4_E~0); 78491#L609-1 assume !(0 == ~T5_E~0); 78642#L614-1 assume !(0 == ~E_M~0); 78643#L619-1 assume !(0 == ~E_1~0); 78682#L624-1 assume !(0 == ~E_2~0); 78683#L629-1 assume !(0 == ~E_3~0); 78609#L634-1 assume !(0 == ~E_4~0); 78610#L639-1 assume !(0 == ~E_5~0); 78210#L644-1 havoc activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 78211#L282 assume !(1 == ~m_pc~0); 78601#L282-2 is_master_triggered_~__retres1~0 := 0; 78602#L293 is_master_triggered_#res := is_master_triggered_~__retres1~0; 78655#L294 activate_threads_#t~ret8 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 78656#L733 assume !(0 != activate_threads_~tmp~1); 78621#L733-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 78622#L301 assume !(1 == ~t1_pc~0); 78120#L301-2 is_transmit1_triggered_~__retres1~1 := 0; 78121#L312 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 78685#L313 activate_threads_#t~ret9 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 78686#L741 assume !(0 != activate_threads_~tmp___0~0); 78137#L741-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 78138#L320 assume !(1 == ~t2_pc~0); 78332#L320-2 is_transmit2_triggered_~__retres1~2 := 0; 78333#L331 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 78268#L332 activate_threads_#t~ret10 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 78269#L749 assume !(0 != activate_threads_~tmp___1~0); 78515#L749-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 78516#L339 assume !(1 == ~t3_pc~0); 78455#L339-2 is_transmit3_triggered_~__retres1~3 := 0; 78456#L350 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 78487#L351 activate_threads_#t~ret11 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 78488#L757 assume !(0 != activate_threads_~tmp___2~0); 78637#L757-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 78638#L358 assume !(1 == ~t4_pc~0); 78159#L358-2 is_transmit4_triggered_~__retres1~4 := 0; 78160#L369 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 78594#L370 activate_threads_#t~ret12 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 78595#L765 assume !(0 != activate_threads_~tmp___3~0); 78230#L765-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 78231#L377 assume !(1 == ~t5_pc~0); 78134#L377-2 is_transmit5_triggered_~__retres1~5 := 0; 78393#L388 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 78131#L389 activate_threads_#t~ret13 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 78132#L773 assume !(0 != activate_threads_~tmp___4~0); 81411#L773-2 assume !(1 == ~M_E~0); 78680#L657-1 assume !(1 == ~T1_E~0); 78300#L662-1 assume !(1 == ~T2_E~0); 78301#L667-1 assume !(1 == ~T3_E~0); 78517#L672-1 assume !(1 == ~T4_E~0); 78518#L677-1 assume !(1 == ~T5_E~0); 78527#L682-1 assume !(1 == ~E_M~0); 78528#L687-1 assume !(1 == ~E_1~0); 78489#L692-1 assume !(1 == ~E_2~0); 78139#L697-1 assume !(1 == ~E_3~0); 78140#L702-1 assume !(1 == ~E_4~0); 78639#L707-1 assume !(1 == ~E_5~0); 81310#L918-1 assume !false; 81220#L919 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret1, eval_#t~nondet2, eval_~tmp_ndt_1~0, eval_#t~nondet3, eval_~tmp_ndt_2~0, eval_#t~nondet4, eval_~tmp_ndt_3~0, eval_#t~nondet5, eval_~tmp_ndt_4~0, eval_#t~nondet6, eval_~tmp_ndt_5~0, eval_#t~nondet7, eval_~tmp_ndt_6~0, eval_~tmp~0;havoc eval_~tmp~0; 81219#L564 [2018-11-23 13:21:53,091 INFO L796 eck$LassoCheckResult]: Loop: 81219#L564 assume !false; 81218#L485 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 81215#L442 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 81213#L474 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 81211#L475 eval_#t~ret1 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret1;havoc eval_#t~ret1; 81209#L489 assume 0 != eval_~tmp~0; 81199#L489-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0;eval_~tmp_ndt_1~0 := eval_#t~nondet2;havoc eval_#t~nondet2; 81194#L497 assume !(0 != eval_~tmp_ndt_1~0); 81185#L494 assume !(0 == ~t1_st~0); 81180#L508 assume !(0 == ~t2_st~0); 81176#L522 assume !(0 == ~t3_st~0); 81171#L536 assume !(0 == ~t4_st~0); 81169#L550 assume !(0 == ~t5_st~0); 81219#L564 [2018-11-23 13:21:53,092 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 13:21:53,092 INFO L82 PathProgramCache]: Analyzing trace with hash 1942871557, now seen corresponding path program 1 times [2018-11-23 13:21:53,092 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 13:21:53,092 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 13:21:53,093 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 13:21:53,093 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 13:21:53,093 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 13:21:53,097 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 13:21:53,116 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 13:21:53,116 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 13:21:53,116 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-23 13:21:53,117 INFO L799 eck$LassoCheckResult]: stem already infeasible [2018-11-23 13:21:53,117 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 13:21:53,117 INFO L82 PathProgramCache]: Analyzing trace with hash 1714025377, now seen corresponding path program 2 times [2018-11-23 13:21:53,117 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 13:21:53,117 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 13:21:53,118 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 13:21:53,118 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 13:21:53,118 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 13:21:53,120 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-23 13:21:53,123 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-23 13:21:53,200 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-23 13:21:53,200 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-23 13:21:53,200 INFO L87 Difference]: Start difference. First operand 9973 states and 13622 transitions. cyclomatic complexity: 3661 Second operand 3 states. [2018-11-23 13:21:53,226 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 13:21:53,226 INFO L93 Difference]: Finished difference Result 9901 states and 13521 transitions. [2018-11-23 13:21:53,228 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-23 13:21:53,228 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 9901 states and 13521 transitions. [2018-11-23 13:21:53,303 INFO L131 ngComponentsAnalysis]: Automaton has 12 accepting balls. 9744 [2018-11-23 13:21:53,319 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 9901 states to 9901 states and 13521 transitions. [2018-11-23 13:21:53,319 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 9901 [2018-11-23 13:21:53,323 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 9901 [2018-11-23 13:21:53,324 INFO L73 IsDeterministic]: Start isDeterministic. Operand 9901 states and 13521 transitions. [2018-11-23 13:21:53,331 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-23 13:21:53,331 INFO L705 BuchiCegarLoop]: Abstraction has 9901 states and 13521 transitions. [2018-11-23 13:21:53,337 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 9901 states and 13521 transitions. [2018-11-23 13:21:53,393 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 9901 to 9901. [2018-11-23 13:21:53,394 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 9901 states. [2018-11-23 13:21:53,406 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 9901 states to 9901 states and 13521 transitions. [2018-11-23 13:21:53,407 INFO L728 BuchiCegarLoop]: Abstraction has 9901 states and 13521 transitions. [2018-11-23 13:21:53,407 INFO L608 BuchiCegarLoop]: Abstraction has 9901 states and 13521 transitions. [2018-11-23 13:21:53,407 INFO L442 BuchiCegarLoop]: ======== Iteration 18============ [2018-11-23 13:21:53,407 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 9901 states and 13521 transitions. [2018-11-23 13:21:53,427 INFO L131 ngComponentsAnalysis]: Automaton has 12 accepting balls. 9744 [2018-11-23 13:21:53,427 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-23 13:21:53,427 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-23 13:21:53,428 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 13:21:53,428 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 13:21:53,428 INFO L794 eck$LassoCheckResult]: Stem: 98377#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 98320#L-1 havoc main_#res;havoc main_~__retres1~7;havoc main_~__retres1~7;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 98321#L881 havoc start_simulation_#t~ret15, start_simulation_#t~ret16, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 98221#L397 assume 1 == ~m_i~0;~m_st~0 := 0; 98222#L404-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 98136#L409-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 98137#L414-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 98223#L419-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 98070#L424-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 98071#L429-1 assume !(0 == ~M_E~0); 98094#L589-1 assume !(0 == ~T1_E~0); 98095#L594-1 assume !(0 == ~T2_E~0); 97886#L599-1 assume !(0 == ~T3_E~0); 97887#L604-1 assume !(0 == ~T4_E~0); 98024#L609-1 assume !(0 == ~T5_E~0); 98025#L614-1 assume !(0 == ~E_M~0); 98285#L619-1 assume !(0 == ~E_1~0); 98286#L624-1 assume !(0 == ~E_2~0); 98151#L629-1 assume !(0 == ~E_3~0); 98152#L634-1 assume !(0 == ~E_4~0); 98229#L639-1 assume !(0 == ~E_5~0); 98084#L644-1 havoc activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 98085#L282 assume !(1 == ~m_pc~0); 98410#L282-2 is_master_triggered_~__retres1~0 := 0; 98411#L293 is_master_triggered_#res := is_master_triggered_~__retres1~0; 98412#L294 activate_threads_#t~ret8 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 98462#L733 assume !(0 != activate_threads_~tmp~1); 98463#L733-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 98005#L301 assume !(1 == ~t1_pc~0); 97996#L301-2 is_transmit1_triggered_~__retres1~1 := 0; 97997#L312 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 98117#L313 activate_threads_#t~ret9 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 98032#L741 assume !(0 != activate_threads_~tmp___0~0); 98014#L741-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 98015#L320 assume !(1 == ~t2_pc~0); 98206#L320-2 is_transmit2_triggered_~__retres1~2 := 0; 98207#L331 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 98139#L332 activate_threads_#t~ret10 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 98140#L749 assume !(0 != activate_threads_~tmp___1~0); 98374#L749-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 98369#L339 assume !(1 == ~t3_pc~0); 98323#L339-2 is_transmit3_triggered_~__retres1~3 := 0; 98324#L350 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 98356#L351 activate_threads_#t~ret11 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 98357#L757 assume !(0 != activate_threads_~tmp___2~0); 98477#L757-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 98077#L358 assume !(1 == ~t4_pc~0); 98035#L358-2 is_transmit4_triggered_~__retres1~4 := 0; 98036#L369 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 98074#L370 activate_threads_#t~ret12 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 98102#L765 assume !(0 != activate_threads_~tmp___3~0); 98103#L765-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 98104#L377 assume !(1 == ~t5_pc~0); 98010#L377-2 is_transmit5_triggered_~__retres1~5 := 0; 98258#L388 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 98007#L389 activate_threads_#t~ret13 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 98008#L773 assume !(0 != activate_threads_~tmp___4~0); 98276#L773-2 assume !(1 == ~M_E~0); 98277#L657-1 assume !(1 == ~T1_E~0); 98174#L662-1 assume !(1 == ~T2_E~0); 98175#L667-1 assume !(1 == ~T3_E~0); 98375#L672-1 assume !(1 == ~T4_E~0); 98082#L677-1 assume !(1 == ~T5_E~0); 98083#L682-1 assume !(1 == ~E_M~0); 97877#L687-1 assume !(1 == ~E_1~0); 97878#L692-1 assume !(1 == ~E_2~0); 98016#L697-1 assume !(1 == ~E_3~0); 98017#L702-1 assume !(1 == ~E_4~0); 98278#L707-1 assume !(1 == ~E_5~0); 98279#L918-1 assume !false; 101419#L919 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret1, eval_#t~nondet2, eval_~tmp_ndt_1~0, eval_#t~nondet3, eval_~tmp_ndt_2~0, eval_#t~nondet4, eval_~tmp_ndt_3~0, eval_#t~nondet5, eval_~tmp_ndt_4~0, eval_#t~nondet6, eval_~tmp_ndt_5~0, eval_#t~nondet7, eval_~tmp_ndt_6~0, eval_~tmp~0;havoc eval_~tmp~0; 101415#L564 [2018-11-23 13:21:53,428 INFO L796 eck$LassoCheckResult]: Loop: 101415#L564 assume !false; 101413#L485 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 101410#L442 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 101408#L474 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 101405#L475 eval_#t~ret1 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret1;havoc eval_#t~ret1; 101403#L489 assume 0 != eval_~tmp~0; 101400#L489-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0;eval_~tmp_ndt_1~0 := eval_#t~nondet2;havoc eval_#t~nondet2; 101397#L497 assume !(0 != eval_~tmp_ndt_1~0); 101395#L494 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0;eval_~tmp_ndt_2~0 := eval_#t~nondet3;havoc eval_#t~nondet3; 101349#L511 assume !(0 != eval_~tmp_ndt_2~0); 101393#L508 assume !(0 == ~t2_st~0); 101781#L522 assume !(0 == ~t3_st~0); 102029#L536 assume !(0 == ~t4_st~0); 101423#L550 assume !(0 == ~t5_st~0); 101415#L564 [2018-11-23 13:21:53,429 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 13:21:53,429 INFO L82 PathProgramCache]: Analyzing trace with hash -1135942013, now seen corresponding path program 2 times [2018-11-23 13:21:53,429 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 13:21:53,429 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 13:21:53,430 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 13:21:53,430 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-23 13:21:53,430 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 13:21:53,435 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-23 13:21:53,440 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-23 13:21:53,452 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 13:21:53,452 INFO L82 PathProgramCache]: Analyzing trace with hash 706455497, now seen corresponding path program 1 times [2018-11-23 13:21:53,452 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 13:21:53,452 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 13:21:53,453 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 13:21:53,453 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-23 13:21:53,453 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 13:21:53,454 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-23 13:21:53,456 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-23 13:21:53,458 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 13:21:53,458 INFO L82 PathProgramCache]: Analyzing trace with hash 1606943435, now seen corresponding path program 1 times [2018-11-23 13:21:53,458 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 13:21:53,458 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 13:21:53,459 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 13:21:53,459 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 13:21:53,459 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 13:21:53,464 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 13:21:53,484 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 13:21:53,484 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 13:21:53,484 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-23 13:21:53,561 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-23 13:21:53,562 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-23 13:21:53,562 INFO L87 Difference]: Start difference. First operand 9901 states and 13521 transitions. cyclomatic complexity: 3632 Second operand 3 states. [2018-11-23 13:21:53,616 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 13:21:53,616 INFO L93 Difference]: Finished difference Result 12963 states and 17611 transitions. [2018-11-23 13:21:53,617 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-23 13:21:53,618 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 12963 states and 17611 transitions. [2018-11-23 13:21:53,651 INFO L131 ngComponentsAnalysis]: Automaton has 12 accepting balls. 12782 [2018-11-23 13:21:53,679 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 12963 states to 12963 states and 17611 transitions. [2018-11-23 13:21:53,679 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 12963 [2018-11-23 13:21:53,687 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 12963 [2018-11-23 13:21:53,687 INFO L73 IsDeterministic]: Start isDeterministic. Operand 12963 states and 17611 transitions. [2018-11-23 13:21:53,695 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-23 13:21:53,695 INFO L705 BuchiCegarLoop]: Abstraction has 12963 states and 17611 transitions. [2018-11-23 13:21:53,703 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 12963 states and 17611 transitions. [2018-11-23 13:21:53,781 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 12963 to 12587. [2018-11-23 13:21:53,782 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 12587 states. [2018-11-23 13:21:53,798 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 12587 states to 12587 states and 17123 transitions. [2018-11-23 13:21:53,799 INFO L728 BuchiCegarLoop]: Abstraction has 12587 states and 17123 transitions. [2018-11-23 13:21:53,799 INFO L608 BuchiCegarLoop]: Abstraction has 12587 states and 17123 transitions. [2018-11-23 13:21:53,799 INFO L442 BuchiCegarLoop]: ======== Iteration 19============ [2018-11-23 13:21:53,799 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 12587 states and 17123 transitions. [2018-11-23 13:21:53,824 INFO L131 ngComponentsAnalysis]: Automaton has 12 accepting balls. 12406 [2018-11-23 13:21:53,824 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-23 13:21:53,825 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-23 13:21:53,825 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 13:21:53,825 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 13:21:53,826 INFO L794 eck$LassoCheckResult]: Stem: 121252#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 121192#L-1 havoc main_#res;havoc main_~__retres1~7;havoc main_~__retres1~7;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 121193#L881 havoc start_simulation_#t~ret15, start_simulation_#t~ret16, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 121102#L397 assume 1 == ~m_i~0;~m_st~0 := 0; 121103#L404-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 121012#L409-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 121013#L414-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 121104#L419-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 120948#L424-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 120949#L429-1 assume !(0 == ~M_E~0); 120973#L589-1 assume !(0 == ~T1_E~0); 120974#L594-1 assume !(0 == ~T2_E~0); 120758#L599-1 assume !(0 == ~T3_E~0); 120759#L604-1 assume !(0 == ~T4_E~0); 120902#L609-1 assume !(0 == ~T5_E~0); 120903#L614-1 assume !(0 == ~E_M~0); 121166#L619-1 assume !(0 == ~E_1~0); 121167#L624-1 assume !(0 == ~E_2~0); 121027#L629-1 assume !(0 == ~E_3~0); 121028#L634-1 assume !(0 == ~E_4~0); 121111#L639-1 assume !(0 == ~E_5~0); 120962#L644-1 havoc activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 120963#L282 assume !(1 == ~m_pc~0); 121289#L282-2 is_master_triggered_~__retres1~0 := 0; 121290#L293 is_master_triggered_#res := is_master_triggered_~__retres1~0; 121291#L294 activate_threads_#t~ret8 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 121340#L733 assume !(0 != activate_threads_~tmp~1); 121341#L733-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 120883#L301 assume !(1 == ~t1_pc~0); 120874#L301-2 is_transmit1_triggered_~__retres1~1 := 0; 120875#L312 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 120994#L313 activate_threads_#t~ret9 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 120910#L741 assume !(0 != activate_threads_~tmp___0~0); 120892#L741-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 120893#L320 assume !(1 == ~t2_pc~0); 121086#L320-2 is_transmit2_triggered_~__retres1~2 := 0; 121087#L331 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 121015#L332 activate_threads_#t~ret10 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 121016#L749 assume !(0 != activate_threads_~tmp___1~0); 121249#L749-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 121244#L339 assume !(1 == ~t3_pc~0); 121195#L339-2 is_transmit3_triggered_~__retres1~3 := 0; 121196#L350 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 121231#L351 activate_threads_#t~ret11 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 121232#L757 assume !(0 != activate_threads_~tmp___2~0); 121356#L757-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 120955#L358 assume !(1 == ~t4_pc~0); 120912#L358-2 is_transmit4_triggered_~__retres1~4 := 0; 120913#L369 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 120952#L370 activate_threads_#t~ret12 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 120982#L765 assume !(0 != activate_threads_~tmp___3~0); 120983#L765-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 120984#L377 assume !(1 == ~t5_pc~0); 120888#L377-2 is_transmit5_triggered_~__retres1~5 := 0; 121141#L388 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 120885#L389 activate_threads_#t~ret13 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 120886#L773 assume !(0 != activate_threads_~tmp___4~0); 121159#L773-2 assume !(1 == ~M_E~0); 121160#L657-1 assume !(1 == ~T1_E~0); 121051#L662-1 assume !(1 == ~T2_E~0); 121052#L667-1 assume !(1 == ~T3_E~0); 121250#L672-1 assume !(1 == ~T4_E~0); 120960#L677-1 assume !(1 == ~T5_E~0); 120961#L682-1 assume !(1 == ~E_M~0); 120749#L687-1 assume !(1 == ~E_1~0); 120750#L692-1 assume !(1 == ~E_2~0); 120894#L697-1 assume !(1 == ~E_3~0); 120895#L702-1 assume !(1 == ~E_4~0); 121161#L707-1 assume !(1 == ~E_5~0); 121162#L918-1 assume !false; 123783#L919 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret1, eval_#t~nondet2, eval_~tmp_ndt_1~0, eval_#t~nondet3, eval_~tmp_ndt_2~0, eval_#t~nondet4, eval_~tmp_ndt_3~0, eval_#t~nondet5, eval_~tmp_ndt_4~0, eval_#t~nondet6, eval_~tmp_ndt_5~0, eval_#t~nondet7, eval_~tmp_ndt_6~0, eval_~tmp~0;havoc eval_~tmp~0; 123781#L564 [2018-11-23 13:21:53,826 INFO L796 eck$LassoCheckResult]: Loop: 123781#L564 assume !false; 123779#L485 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 123775#L442 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 123773#L474 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 123771#L475 eval_#t~ret1 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret1;havoc eval_#t~ret1; 123769#L489 assume 0 != eval_~tmp~0; 123766#L489-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0;eval_~tmp_ndt_1~0 := eval_#t~nondet2;havoc eval_#t~nondet2; 123767#L497 assume !(0 != eval_~tmp_ndt_1~0); 122521#L494 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0;eval_~tmp_ndt_2~0 := eval_#t~nondet3;havoc eval_#t~nondet3; 122516#L511 assume !(0 != eval_~tmp_ndt_2~0); 122518#L508 assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0;eval_~tmp_ndt_3~0 := eval_#t~nondet4;havoc eval_#t~nondet4; 122511#L525 assume !(0 != eval_~tmp_ndt_3~0); 122512#L522 assume !(0 == ~t3_st~0); 123795#L536 assume !(0 == ~t4_st~0); 123787#L550 assume !(0 == ~t5_st~0); 123781#L564 [2018-11-23 13:21:53,826 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 13:21:53,826 INFO L82 PathProgramCache]: Analyzing trace with hash -1135942013, now seen corresponding path program 3 times [2018-11-23 13:21:53,826 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 13:21:53,826 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 13:21:53,827 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 13:21:53,827 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 13:21:53,827 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 13:21:53,832 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-23 13:21:53,837 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-23 13:21:53,849 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 13:21:53,849 INFO L82 PathProgramCache]: Analyzing trace with hash 258069692, now seen corresponding path program 1 times [2018-11-23 13:21:53,849 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 13:21:53,849 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 13:21:53,850 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 13:21:53,850 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-23 13:21:53,850 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 13:21:53,852 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-23 13:21:53,854 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-23 13:21:53,855 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 13:21:53,855 INFO L82 PathProgramCache]: Analyzing trace with hash -1891575302, now seen corresponding path program 1 times [2018-11-23 13:21:53,856 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 13:21:53,856 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 13:21:53,856 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 13:21:53,856 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 13:21:53,857 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 13:21:53,863 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 13:21:53,896 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 13:21:53,896 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 13:21:53,896 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-23 13:21:53,966 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-23 13:21:53,966 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-23 13:21:53,967 INFO L87 Difference]: Start difference. First operand 12587 states and 17123 transitions. cyclomatic complexity: 4548 Second operand 3 states. [2018-11-23 13:21:54,034 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 13:21:54,034 INFO L93 Difference]: Finished difference Result 22997 states and 31169 transitions. [2018-11-23 13:21:54,035 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-23 13:21:54,036 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 22997 states and 31169 transitions. [2018-11-23 13:21:54,092 INFO L131 ngComponentsAnalysis]: Automaton has 12 accepting balls. 22712 [2018-11-23 13:21:54,140 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 22997 states to 22997 states and 31169 transitions. [2018-11-23 13:21:54,141 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 22997 [2018-11-23 13:21:54,151 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 22997 [2018-11-23 13:21:54,151 INFO L73 IsDeterministic]: Start isDeterministic. Operand 22997 states and 31169 transitions. [2018-11-23 13:21:54,163 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-23 13:21:54,163 INFO L705 BuchiCegarLoop]: Abstraction has 22997 states and 31169 transitions. [2018-11-23 13:21:54,175 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 22997 states and 31169 transitions. [2018-11-23 13:21:54,294 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 22997 to 22205. [2018-11-23 13:21:54,294 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 22205 states. [2018-11-23 13:21:54,433 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 22205 states to 22205 states and 30185 transitions. [2018-11-23 13:21:54,434 INFO L728 BuchiCegarLoop]: Abstraction has 22205 states and 30185 transitions. [2018-11-23 13:21:54,434 INFO L608 BuchiCegarLoop]: Abstraction has 22205 states and 30185 transitions. [2018-11-23 13:21:54,434 INFO L442 BuchiCegarLoop]: ======== Iteration 20============ [2018-11-23 13:21:54,434 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 22205 states and 30185 transitions. [2018-11-23 13:21:54,484 INFO L131 ngComponentsAnalysis]: Automaton has 12 accepting balls. 21920 [2018-11-23 13:21:54,484 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-23 13:21:54,484 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-23 13:21:54,485 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 13:21:54,485 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 13:21:54,485 INFO L794 eck$LassoCheckResult]: Stem: 156857#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 156789#L-1 havoc main_#res;havoc main_~__retres1~7;havoc main_~__retres1~7;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 156790#L881 havoc start_simulation_#t~ret15, start_simulation_#t~ret16, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 156698#L397 assume 1 == ~m_i~0;~m_st~0 := 0; 156699#L404-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 156606#L409-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 156607#L414-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 156700#L419-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 156541#L424-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 156542#L429-1 assume !(0 == ~M_E~0); 156565#L589-1 assume !(0 == ~T1_E~0); 156566#L594-1 assume !(0 == ~T2_E~0); 156350#L599-1 assume !(0 == ~T3_E~0); 156351#L604-1 assume !(0 == ~T4_E~0); 156495#L609-1 assume !(0 == ~T5_E~0); 156496#L614-1 assume !(0 == ~E_M~0); 156762#L619-1 assume !(0 == ~E_1~0); 156763#L624-1 assume !(0 == ~E_2~0); 156621#L629-1 assume !(0 == ~E_3~0); 156622#L634-1 assume !(0 == ~E_4~0); 156708#L639-1 assume !(0 == ~E_5~0); 156555#L644-1 havoc activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 156556#L282 assume !(1 == ~m_pc~0); 156902#L282-2 is_master_triggered_~__retres1~0 := 0; 156903#L293 is_master_triggered_#res := is_master_triggered_~__retres1~0; 156904#L294 activate_threads_#t~ret8 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 156958#L733 assume !(0 != activate_threads_~tmp~1); 156959#L733-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 156477#L301 assume !(1 == ~t1_pc~0); 156468#L301-2 is_transmit1_triggered_~__retres1~1 := 0; 156469#L312 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 156586#L313 activate_threads_#t~ret9 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 156503#L741 assume !(0 != activate_threads_~tmp___0~0); 156485#L741-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 156486#L320 assume !(1 == ~t2_pc~0); 156680#L320-2 is_transmit2_triggered_~__retres1~2 := 0; 156681#L331 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 156609#L332 activate_threads_#t~ret10 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 156610#L749 assume !(0 != activate_threads_~tmp___1~0); 156854#L749-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 156848#L339 assume !(1 == ~t3_pc~0); 156792#L339-2 is_transmit3_triggered_~__retres1~3 := 0; 156793#L350 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 156829#L351 activate_threads_#t~ret11 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 156830#L757 assume !(0 != activate_threads_~tmp___2~0); 156974#L757-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 156548#L358 assume !(1 == ~t4_pc~0); 156505#L358-2 is_transmit4_triggered_~__retres1~4 := 0; 156506#L369 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 156545#L370 activate_threads_#t~ret12 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 156574#L765 assume !(0 != activate_threads_~tmp___3~0); 156575#L765-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 156576#L377 assume !(1 == ~t5_pc~0); 156482#L377-2 is_transmit5_triggered_~__retres1~5 := 0; 156739#L388 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 156479#L389 activate_threads_#t~ret13 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 156480#L773 assume !(0 != activate_threads_~tmp___4~0); 156755#L773-2 assume !(1 == ~M_E~0); 156756#L657-1 assume !(1 == ~T1_E~0); 156646#L662-1 assume !(1 == ~T2_E~0); 156647#L667-1 assume !(1 == ~T3_E~0); 156855#L672-1 assume !(1 == ~T4_E~0); 156553#L677-1 assume !(1 == ~T5_E~0); 156554#L682-1 assume !(1 == ~E_M~0); 156341#L687-1 assume !(1 == ~E_1~0); 156342#L692-1 assume !(1 == ~E_2~0); 156487#L697-1 assume !(1 == ~E_3~0); 156488#L702-1 assume !(1 == ~E_4~0); 156757#L707-1 assume !(1 == ~E_5~0); 156758#L918-1 assume !false; 161105#L919 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret1, eval_#t~nondet2, eval_~tmp_ndt_1~0, eval_#t~nondet3, eval_~tmp_ndt_2~0, eval_#t~nondet4, eval_~tmp_ndt_3~0, eval_#t~nondet5, eval_~tmp_ndt_4~0, eval_#t~nondet6, eval_~tmp_ndt_5~0, eval_#t~nondet7, eval_~tmp_ndt_6~0, eval_~tmp~0;havoc eval_~tmp~0; 161101#L564 [2018-11-23 13:21:54,486 INFO L796 eck$LassoCheckResult]: Loop: 161101#L564 assume !false; 161098#L485 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 161056#L442 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 161057#L474 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 164819#L475 eval_#t~ret1 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret1;havoc eval_#t~ret1; 164817#L489 assume 0 != eval_~tmp~0; 164814#L489-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0;eval_~tmp_ndt_1~0 := eval_#t~nondet2;havoc eval_#t~nondet2; 164811#L497 assume !(0 != eval_~tmp_ndt_1~0); 158966#L494 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0;eval_~tmp_ndt_2~0 := eval_#t~nondet3;havoc eval_#t~nondet3; 158959#L511 assume !(0 != eval_~tmp_ndt_2~0); 158951#L508 assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0;eval_~tmp_ndt_3~0 := eval_#t~nondet4;havoc eval_#t~nondet4; 158943#L525 assume !(0 != eval_~tmp_ndt_3~0); 158944#L522 assume 0 == ~t3_st~0;havoc eval_~tmp_ndt_4~0;eval_~tmp_ndt_4~0 := eval_#t~nondet5;havoc eval_#t~nondet5; 159082#L539 assume !(0 != eval_~tmp_ndt_4~0); 161032#L536 assume !(0 == ~t4_st~0); 161030#L550 assume !(0 == ~t5_st~0); 161101#L564 [2018-11-23 13:21:54,486 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 13:21:54,486 INFO L82 PathProgramCache]: Analyzing trace with hash -1135942013, now seen corresponding path program 4 times [2018-11-23 13:21:54,486 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 13:21:54,486 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 13:21:54,487 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 13:21:54,487 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 13:21:54,487 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 13:21:54,492 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-23 13:21:54,497 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-23 13:21:54,508 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 13:21:54,508 INFO L82 PathProgramCache]: Analyzing trace with hash -595166546, now seen corresponding path program 1 times [2018-11-23 13:21:54,508 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 13:21:54,508 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 13:21:54,509 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 13:21:54,509 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-23 13:21:54,509 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 13:21:54,510 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-23 13:21:54,512 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-23 13:21:54,514 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 13:21:54,514 INFO L82 PathProgramCache]: Analyzing trace with hash 1485315376, now seen corresponding path program 1 times [2018-11-23 13:21:54,514 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 13:21:54,514 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 13:21:54,515 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 13:21:54,515 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 13:21:54,515 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 13:21:54,524 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 13:21:54,562 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 13:21:54,563 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 13:21:54,563 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-23 13:21:54,671 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-23 13:21:54,671 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-23 13:21:54,671 INFO L87 Difference]: Start difference. First operand 22205 states and 30185 transitions. cyclomatic complexity: 7992 Second operand 3 states. [2018-11-23 13:21:54,794 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 13:21:54,794 INFO L93 Difference]: Finished difference Result 29527 states and 40003 transitions. [2018-11-23 13:21:54,797 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-23 13:21:54,797 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 29527 states and 40003 transitions. [2018-11-23 13:21:54,898 INFO L131 ngComponentsAnalysis]: Automaton has 12 accepting balls. 29186 [2018-11-23 13:21:54,975 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 29527 states to 29527 states and 40003 transitions. [2018-11-23 13:21:54,976 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 29527 [2018-11-23 13:21:54,991 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 29527 [2018-11-23 13:21:54,992 INFO L73 IsDeterministic]: Start isDeterministic. Operand 29527 states and 40003 transitions. [2018-11-23 13:21:55,008 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-23 13:21:55,009 INFO L705 BuchiCegarLoop]: Abstraction has 29527 states and 40003 transitions. [2018-11-23 13:21:55,023 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 29527 states and 40003 transitions. [2018-11-23 13:21:55,210 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 29527 to 29047. [2018-11-23 13:21:55,210 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 29047 states. [2018-11-23 13:21:55,248 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 29047 states to 29047 states and 39379 transitions. [2018-11-23 13:21:55,248 INFO L728 BuchiCegarLoop]: Abstraction has 29047 states and 39379 transitions. [2018-11-23 13:21:55,248 INFO L608 BuchiCegarLoop]: Abstraction has 29047 states and 39379 transitions. [2018-11-23 13:21:55,248 INFO L442 BuchiCegarLoop]: ======== Iteration 21============ [2018-11-23 13:21:55,248 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 29047 states and 39379 transitions. [2018-11-23 13:21:55,306 INFO L131 ngComponentsAnalysis]: Automaton has 12 accepting balls. 28706 [2018-11-23 13:21:55,307 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-23 13:21:55,307 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-23 13:21:55,307 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 13:21:55,307 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 13:21:55,307 INFO L794 eck$LassoCheckResult]: Stem: 208606#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 208535#L-1 havoc main_#res;havoc main_~__retres1~7;havoc main_~__retres1~7;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 208536#L881 havoc start_simulation_#t~ret15, start_simulation_#t~ret16, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 208439#L397 assume 1 == ~m_i~0;~m_st~0 := 0; 208440#L404-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 208350#L409-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 208351#L414-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 208442#L419-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 208278#L424-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 208279#L429-1 assume !(0 == ~M_E~0); 208303#L589-1 assume !(0 == ~T1_E~0); 208304#L594-1 assume !(0 == ~T2_E~0); 208090#L599-1 assume !(0 == ~T3_E~0); 208091#L604-1 assume !(0 == ~T4_E~0); 208231#L609-1 assume !(0 == ~T5_E~0); 208232#L614-1 assume !(0 == ~E_M~0); 208504#L619-1 assume !(0 == ~E_1~0); 208505#L624-1 assume !(0 == ~E_2~0); 208364#L629-1 assume !(0 == ~E_3~0); 208365#L634-1 assume !(0 == ~E_4~0); 208448#L639-1 assume !(0 == ~E_5~0); 208293#L644-1 havoc activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 208294#L282 assume !(1 == ~m_pc~0); 208649#L282-2 is_master_triggered_~__retres1~0 := 0; 208653#L293 is_master_triggered_#res := is_master_triggered_~__retres1~0; 208654#L294 activate_threads_#t~ret8 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 208712#L733 assume !(0 != activate_threads_~tmp~1); 208713#L733-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 208213#L301 assume !(1 == ~t1_pc~0); 208205#L301-2 is_transmit1_triggered_~__retres1~1 := 0; 208172#L312 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 208173#L313 activate_threads_#t~ret9 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 208241#L741 assume !(0 != activate_threads_~tmp___0~0); 208221#L741-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 208222#L320 assume !(1 == ~t2_pc~0); 208425#L320-2 is_transmit2_triggered_~__retres1~2 := 0; 208426#L331 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 208352#L332 activate_threads_#t~ret10 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 208353#L749 assume !(0 != activate_threads_~tmp___1~0); 208601#L749-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 208593#L339 assume !(1 == ~t3_pc~0); 208538#L339-2 is_transmit3_triggered_~__retres1~3 := 0; 208539#L350 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 208577#L351 activate_threads_#t~ret11 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 208578#L757 assume !(0 != activate_threads_~tmp___2~0); 208735#L757-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 208285#L358 assume !(1 == ~t4_pc~0); 208242#L358-2 is_transmit4_triggered_~__retres1~4 := 0; 208243#L369 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 208284#L370 activate_threads_#t~ret12 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 208313#L765 assume !(0 != activate_threads_~tmp___3~0); 208314#L765-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 208315#L377 assume !(1 == ~t5_pc~0); 208219#L377-2 is_transmit5_triggered_~__retres1~5 := 0; 208479#L388 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 208215#L389 activate_threads_#t~ret13 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 208216#L773 assume !(0 != activate_threads_~tmp___4~0); 208496#L773-2 assume !(1 == ~M_E~0); 208497#L657-1 assume !(1 == ~T1_E~0); 208388#L662-1 assume !(1 == ~T2_E~0); 208389#L667-1 assume !(1 == ~T3_E~0); 208603#L672-1 assume !(1 == ~T4_E~0); 208291#L677-1 assume !(1 == ~T5_E~0); 208292#L682-1 assume !(1 == ~E_M~0); 208081#L687-1 assume !(1 == ~E_1~0); 208082#L692-1 assume !(1 == ~E_2~0); 208223#L697-1 assume !(1 == ~E_3~0); 208224#L702-1 assume !(1 == ~E_4~0); 208498#L707-1 assume !(1 == ~E_5~0); 208499#L918-1 assume !false; 219423#L919 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret1, eval_#t~nondet2, eval_~tmp_ndt_1~0, eval_#t~nondet3, eval_~tmp_ndt_2~0, eval_#t~nondet4, eval_~tmp_ndt_3~0, eval_#t~nondet5, eval_~tmp_ndt_4~0, eval_#t~nondet6, eval_~tmp_ndt_5~0, eval_#t~nondet7, eval_~tmp_ndt_6~0, eval_~tmp~0;havoc eval_~tmp~0; 219422#L564 [2018-11-23 13:21:55,308 INFO L796 eck$LassoCheckResult]: Loop: 219422#L564 assume !false; 219420#L485 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 219417#L442 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 219415#L474 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 219413#L475 eval_#t~ret1 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret1;havoc eval_#t~ret1; 219411#L489 assume 0 != eval_~tmp~0; 219409#L489-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0;eval_~tmp_ndt_1~0 := eval_#t~nondet2;havoc eval_#t~nondet2; 219405#L497 assume !(0 != eval_~tmp_ndt_1~0); 217734#L494 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0;eval_~tmp_ndt_2~0 := eval_#t~nondet3;havoc eval_#t~nondet3; 217728#L511 assume !(0 != eval_~tmp_ndt_2~0); 217726#L508 assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0;eval_~tmp_ndt_3~0 := eval_#t~nondet4;havoc eval_#t~nondet4; 217724#L525 assume !(0 != eval_~tmp_ndt_3~0); 217721#L522 assume 0 == ~t3_st~0;havoc eval_~tmp_ndt_4~0;eval_~tmp_ndt_4~0 := eval_#t~nondet5;havoc eval_#t~nondet5; 217420#L539 assume !(0 != eval_~tmp_ndt_4~0); 217719#L536 assume 0 == ~t4_st~0;havoc eval_~tmp_ndt_5~0;eval_~tmp_ndt_5~0 := eval_#t~nondet6;havoc eval_#t~nondet6; 219428#L553 assume !(0 != eval_~tmp_ndt_5~0); 219427#L550 assume !(0 == ~t5_st~0); 219422#L564 [2018-11-23 13:21:55,308 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 13:21:55,308 INFO L82 PathProgramCache]: Analyzing trace with hash -1135942013, now seen corresponding path program 5 times [2018-11-23 13:21:55,308 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 13:21:55,308 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 13:21:55,308 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 13:21:55,308 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 13:21:55,308 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 13:21:55,312 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-23 13:21:55,317 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-23 13:21:55,328 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 13:21:55,328 INFO L82 PathProgramCache]: Analyzing trace with hash -1270466089, now seen corresponding path program 1 times [2018-11-23 13:21:55,328 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 13:21:55,328 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 13:21:55,329 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 13:21:55,329 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-23 13:21:55,329 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 13:21:55,331 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-23 13:21:55,333 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-23 13:21:55,334 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 13:21:55,335 INFO L82 PathProgramCache]: Analyzing trace with hash -1200035947, now seen corresponding path program 1 times [2018-11-23 13:21:55,335 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 13:21:55,335 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 13:21:55,335 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 13:21:55,336 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 13:21:55,336 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 13:21:55,341 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 13:21:55,390 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 13:21:55,391 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 13:21:55,391 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2018-11-23 13:21:55,474 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-23 13:21:55,475 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-23 13:21:55,475 INFO L87 Difference]: Start difference. First operand 29047 states and 39379 transitions. cyclomatic complexity: 10344 Second operand 3 states. [2018-11-23 13:21:55,605 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 13:21:55,605 INFO L93 Difference]: Finished difference Result 50341 states and 68101 transitions. [2018-11-23 13:21:55,607 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-23 13:21:55,608 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 50341 states and 68101 transitions. [2018-11-23 13:21:55,742 INFO L131 ngComponentsAnalysis]: Automaton has 12 accepting balls. 49736 [2018-11-23 13:21:55,846 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 50341 states to 50341 states and 68101 transitions. [2018-11-23 13:21:55,846 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 50341 [2018-11-23 13:21:55,871 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 50341 [2018-11-23 13:21:55,872 INFO L73 IsDeterministic]: Start isDeterministic. Operand 50341 states and 68101 transitions. [2018-11-23 13:21:55,896 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-23 13:21:55,896 INFO L705 BuchiCegarLoop]: Abstraction has 50341 states and 68101 transitions. [2018-11-23 13:21:55,919 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 50341 states and 68101 transitions. [2018-11-23 13:21:56,412 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 50341 to 49909. [2018-11-23 13:21:56,412 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 49909 states. [2018-11-23 13:21:56,466 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 49909 states to 49909 states and 67669 transitions. [2018-11-23 13:21:56,466 INFO L728 BuchiCegarLoop]: Abstraction has 49909 states and 67669 transitions. [2018-11-23 13:21:56,466 INFO L608 BuchiCegarLoop]: Abstraction has 49909 states and 67669 transitions. [2018-11-23 13:21:56,466 INFO L442 BuchiCegarLoop]: ======== Iteration 22============ [2018-11-23 13:21:56,466 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 49909 states and 67669 transitions. [2018-11-23 13:21:56,566 INFO L131 ngComponentsAnalysis]: Automaton has 12 accepting balls. 49304 [2018-11-23 13:21:56,566 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-23 13:21:56,566 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-23 13:21:56,567 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 13:21:56,567 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 13:21:56,568 INFO L794 eck$LassoCheckResult]: Stem: 288009#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 287934#L-1 havoc main_#res;havoc main_~__retres1~7;havoc main_~__retres1~7;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 287935#L881 havoc start_simulation_#t~ret15, start_simulation_#t~ret16, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 287826#L397 assume 1 == ~m_i~0;~m_st~0 := 0; 287827#L404-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 287737#L409-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 287738#L414-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 287829#L419-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 287668#L424-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 287669#L429-1 assume !(0 == ~M_E~0); 287693#L589-1 assume !(0 == ~T1_E~0); 287694#L594-1 assume !(0 == ~T2_E~0); 287486#L599-1 assume !(0 == ~T3_E~0); 287487#L604-1 assume !(0 == ~T4_E~0); 287622#L609-1 assume !(0 == ~T5_E~0); 287623#L614-1 assume !(0 == ~E_M~0); 287902#L619-1 assume !(0 == ~E_1~0); 287903#L624-1 assume !(0 == ~E_2~0); 287751#L629-1 assume !(0 == ~E_3~0); 287752#L634-1 assume !(0 == ~E_4~0); 287836#L639-1 assume !(0 == ~E_5~0); 287682#L644-1 havoc activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 287683#L282 assume !(1 == ~m_pc~0); 288057#L282-2 is_master_triggered_~__retres1~0 := 0; 288061#L293 is_master_triggered_#res := is_master_triggered_~__retres1~0; 288062#L294 activate_threads_#t~ret8 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 288121#L733 assume !(0 != activate_threads_~tmp~1); 288122#L733-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 287604#L301 assume !(1 == ~t1_pc~0); 287596#L301-2 is_transmit1_triggered_~__retres1~1 := 0; 287566#L312 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 287567#L313 activate_threads_#t~ret9 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 287631#L741 assume !(0 != activate_threads_~tmp___0~0); 287612#L741-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 287613#L320 assume !(1 == ~t2_pc~0); 287812#L320-2 is_transmit2_triggered_~__retres1~2 := 0; 287813#L331 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 287739#L332 activate_threads_#t~ret10 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 287740#L749 assume !(0 != activate_threads_~tmp___1~0); 288006#L749-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 287997#L339 assume !(1 == ~t3_pc~0); 287937#L339-2 is_transmit3_triggered_~__retres1~3 := 0; 287938#L350 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 287975#L351 activate_threads_#t~ret11 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 287976#L757 assume !(0 != activate_threads_~tmp___2~0); 288142#L757-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 287675#L358 assume !(1 == ~t4_pc~0); 287632#L358-2 is_transmit4_triggered_~__retres1~4 := 0; 287633#L369 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 287674#L370 activate_threads_#t~ret12 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 287702#L765 assume !(0 != activate_threads_~tmp___3~0); 287703#L765-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 287704#L377 assume !(1 == ~t5_pc~0); 287610#L377-2 is_transmit5_triggered_~__retres1~5 := 0; 287872#L388 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 287606#L389 activate_threads_#t~ret13 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 287607#L773 assume !(0 != activate_threads_~tmp___4~0); 287894#L773-2 assume !(1 == ~M_E~0); 287895#L657-1 assume !(1 == ~T1_E~0); 287776#L662-1 assume !(1 == ~T2_E~0); 287777#L667-1 assume !(1 == ~T3_E~0); 288007#L672-1 assume !(1 == ~T4_E~0); 287680#L677-1 assume !(1 == ~T5_E~0); 287681#L682-1 assume !(1 == ~E_M~0); 287477#L687-1 assume !(1 == ~E_1~0); 287478#L692-1 assume !(1 == ~E_2~0); 287614#L697-1 assume !(1 == ~E_3~0); 287615#L702-1 assume !(1 == ~E_4~0); 287896#L707-1 assume !(1 == ~E_5~0); 287897#L918-1 assume !false; 300788#L919 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret1, eval_#t~nondet2, eval_~tmp_ndt_1~0, eval_#t~nondet3, eval_~tmp_ndt_2~0, eval_#t~nondet4, eval_~tmp_ndt_3~0, eval_#t~nondet5, eval_~tmp_ndt_4~0, eval_#t~nondet6, eval_~tmp_ndt_5~0, eval_#t~nondet7, eval_~tmp_ndt_6~0, eval_~tmp~0;havoc eval_~tmp~0; 300785#L564 [2018-11-23 13:21:56,568 INFO L796 eck$LassoCheckResult]: Loop: 300785#L564 assume !false; 300786#L485 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 301199#L442 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 301197#L474 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 300772#L475 eval_#t~ret1 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret1;havoc eval_#t~ret1; 300770#L489 assume 0 != eval_~tmp~0; 300767#L489-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0;eval_~tmp_ndt_1~0 := eval_#t~nondet2;havoc eval_#t~nondet2; 300768#L497 assume !(0 != eval_~tmp_ndt_1~0); 296460#L494 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0;eval_~tmp_ndt_2~0 := eval_#t~nondet3;havoc eval_#t~nondet3; 296457#L511 assume !(0 != eval_~tmp_ndt_2~0); 296455#L508 assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0;eval_~tmp_ndt_3~0 := eval_#t~nondet4;havoc eval_#t~nondet4; 296453#L525 assume !(0 != eval_~tmp_ndt_3~0); 296454#L522 assume 0 == ~t3_st~0;havoc eval_~tmp_ndt_4~0;eval_~tmp_ndt_4~0 := eval_#t~nondet5;havoc eval_#t~nondet5; 306094#L539 assume !(0 != eval_~tmp_ndt_4~0); 306198#L536 assume 0 == ~t4_st~0;havoc eval_~tmp_ndt_5~0;eval_~tmp_ndt_5~0 := eval_#t~nondet6;havoc eval_#t~nondet6; 302839#L553 assume !(0 != eval_~tmp_ndt_5~0); 301230#L550 assume 0 == ~t5_st~0;havoc eval_~tmp_ndt_6~0;eval_~tmp_ndt_6~0 := eval_#t~nondet7;havoc eval_#t~nondet7; 300789#L567 assume !(0 != eval_~tmp_ndt_6~0); 300785#L564 [2018-11-23 13:21:56,568 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 13:21:56,568 INFO L82 PathProgramCache]: Analyzing trace with hash -1135942013, now seen corresponding path program 6 times [2018-11-23 13:21:56,568 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 13:21:56,568 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 13:21:56,569 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 13:21:56,569 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 13:21:56,569 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 13:21:56,574 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-23 13:21:56,580 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-23 13:21:56,588 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 13:21:56,588 INFO L82 PathProgramCache]: Analyzing trace with hash -729747053, now seen corresponding path program 1 times [2018-11-23 13:21:56,588 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 13:21:56,589 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 13:21:56,589 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 13:21:56,589 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-23 13:21:56,589 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 13:21:56,591 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-23 13:21:56,593 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-23 13:21:56,595 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 13:21:56,595 INFO L82 PathProgramCache]: Analyzing trace with hash 1453587349, now seen corresponding path program 1 times [2018-11-23 13:21:56,595 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 13:21:56,595 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 13:21:56,596 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 13:21:56,596 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 13:21:56,596 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 13:21:56,601 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-23 13:21:56,606 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-23 13:21:57,206 WARN L180 SmtUtils]: Spent 489.00 ms on a formula simplification. DAG size of input: 198 DAG size of output: 132 ----- class de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder.RCFGBacktranslator [?] ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; [?] havoc main_#res;havoc main_~__retres1~7;havoc main_~__retres1~7;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; [?] havoc start_simulation_#t~ret15, start_simulation_#t~ret16, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; [?] assume 1 == ~m_i~0;~m_st~0 := 0; [?] assume 1 == ~t1_i~0;~t1_st~0 := 0; [?] assume 1 == ~t2_i~0;~t2_st~0 := 0; [?] assume 1 == ~t3_i~0;~t3_st~0 := 0; [?] assume 1 == ~t4_i~0;~t4_st~0 := 0; [?] assume 1 == ~t5_i~0;~t5_st~0 := 0; [?] assume !(0 == ~M_E~0); [?] assume !(0 == ~T1_E~0); [?] assume !(0 == ~T2_E~0); [?] assume !(0 == ~T3_E~0); [?] assume !(0 == ~T4_E~0); [?] assume !(0 == ~T5_E~0); [?] assume !(0 == ~E_M~0); [?] assume !(0 == ~E_1~0); [?] assume !(0 == ~E_2~0); [?] assume !(0 == ~E_3~0); [?] assume !(0 == ~E_4~0); [?] assume !(0 == ~E_5~0); [?] havoc activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; [?] assume !(1 == ~m_pc~0); [?] is_master_triggered_~__retres1~0 := 0; [?] is_master_triggered_#res := is_master_triggered_~__retres1~0; [?] activate_threads_#t~ret8 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; [?] assume !(0 != activate_threads_~tmp~1); [?] havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; [?] assume !(1 == ~t1_pc~0); [?] is_transmit1_triggered_~__retres1~1 := 0; [?] is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; [?] activate_threads_#t~ret9 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; [?] assume !(0 != activate_threads_~tmp___0~0); [?] havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; [?] assume !(1 == ~t2_pc~0); [?] is_transmit2_triggered_~__retres1~2 := 0; [?] is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; [?] activate_threads_#t~ret10 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; [?] assume !(0 != activate_threads_~tmp___1~0); [?] havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; [?] assume !(1 == ~t3_pc~0); [?] is_transmit3_triggered_~__retres1~3 := 0; [?] is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; [?] activate_threads_#t~ret11 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; [?] assume !(0 != activate_threads_~tmp___2~0); [?] havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; [?] assume !(1 == ~t4_pc~0); [?] is_transmit4_triggered_~__retres1~4 := 0; [?] is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; [?] activate_threads_#t~ret12 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; [?] assume !(0 != activate_threads_~tmp___3~0); [?] havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; [?] assume !(1 == ~t5_pc~0); [?] is_transmit5_triggered_~__retres1~5 := 0; [?] is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; [?] activate_threads_#t~ret13 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; [?] assume !(0 != activate_threads_~tmp___4~0); [?] assume !(1 == ~M_E~0); [?] assume !(1 == ~T1_E~0); [?] assume !(1 == ~T2_E~0); [?] assume !(1 == ~T3_E~0); [?] assume !(1 == ~T4_E~0); [?] assume !(1 == ~T5_E~0); [?] assume !(1 == ~E_M~0); [?] assume !(1 == ~E_1~0); [?] assume !(1 == ~E_2~0); [?] assume !(1 == ~E_3~0); [?] assume !(1 == ~E_4~0); [?] assume !(1 == ~E_5~0); [?] assume !false; [?] start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret1, eval_#t~nondet2, eval_~tmp_ndt_1~0, eval_#t~nondet3, eval_~tmp_ndt_2~0, eval_#t~nondet4, eval_~tmp_ndt_3~0, eval_#t~nondet5, eval_~tmp_ndt_4~0, eval_#t~nondet6, eval_~tmp_ndt_5~0, eval_#t~nondet7, eval_~tmp_ndt_6~0, eval_~tmp~0;havoc eval_~tmp~0; [L14] ~m_pc~0 := 0; [L15] ~t1_pc~0 := 0; [L16] ~t2_pc~0 := 0; [L17] ~t3_pc~0 := 0; [L18] ~t4_pc~0 := 0; [L19] ~t5_pc~0 := 0; [L20] ~m_st~0 := 0; [L21] ~t1_st~0 := 0; [L22] ~t2_st~0 := 0; [L23] ~t3_st~0 := 0; [L24] ~t4_st~0 := 0; [L25] ~t5_st~0 := 0; [L26] ~m_i~0 := 0; [L27] ~t1_i~0 := 0; [L28] ~t2_i~0 := 0; [L29] ~t3_i~0 := 0; [L30] ~t4_i~0 := 0; [L31] ~t5_i~0 := 0; [L32] ~M_E~0 := 2; [L33] ~T1_E~0 := 2; [L34] ~T2_E~0 := 2; [L35] ~T3_E~0 := 2; [L36] ~T4_E~0 := 2; [L37] ~T5_E~0 := 2; [L38] ~E_M~0 := 2; [L39] ~E_1~0 := 2; [L40] ~E_2~0 := 2; [L41] ~E_3~0 := 2; [L42] ~E_4~0 := 2; [L43] ~E_5~0 := 2; [L51] ~token~0 := 0; [L53] ~local~0 := 0; [?] havoc main_#res; [?] havoc main_~__retres1~7; [L963] havoc main_~__retres1~7; [L874] ~m_i~0 := 1; [L875] ~t1_i~0 := 1; [L876] ~t2_i~0 := 1; [L877] ~t3_i~0 := 1; [L878] ~t4_i~0 := 1; [L879] ~t5_i~0 := 1; [L968] havoc start_simulation_#t~ret15, start_simulation_#t~ret16, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1; [L904] havoc start_simulation_~kernel_st~0; [L905] havoc start_simulation_~tmp~3; [L906] havoc start_simulation_~tmp___0~1; [L910] start_simulation_~kernel_st~0 := 0; [L404-L408] assume 1 == ~m_i~0; [L405] ~m_st~0 := 0; [L409-L413] assume 1 == ~t1_i~0; [L410] ~t1_st~0 := 0; [L414-L418] assume 1 == ~t2_i~0; [L415] ~t2_st~0 := 0; [L419-L423] assume 1 == ~t3_i~0; [L420] ~t3_st~0 := 0; [L424-L428] assume 1 == ~t4_i~0; [L425] ~t4_st~0 := 0; [L429-L433] assume 1 == ~t5_i~0; [L430] ~t5_st~0 := 0; [L589-L593] assume !(0 == ~M_E~0); [L594-L598] assume !(0 == ~T1_E~0); [L599-L603] assume !(0 == ~T2_E~0); [L604-L608] assume !(0 == ~T3_E~0); [L609-L613] assume !(0 == ~T4_E~0); [L614-L618] assume !(0 == ~T5_E~0); [L619-L623] assume !(0 == ~E_M~0); [L624-L628] assume !(0 == ~E_1~0); [L629-L633] assume !(0 == ~E_2~0); [L634-L638] assume !(0 == ~E_3~0); [L639-L643] assume !(0 == ~E_4~0); [L644-L648] assume !(0 == ~E_5~0); [L914] havoc activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0; [L722] havoc activate_threads_~tmp~1; [L723] havoc activate_threads_~tmp___0~0; [L724] havoc activate_threads_~tmp___1~0; [L725] havoc activate_threads_~tmp___2~0; [L726] havoc activate_threads_~tmp___3~0; [L727] havoc activate_threads_~tmp___4~0; [L731] havoc is_master_triggered_#res; [L731] havoc is_master_triggered_~__retres1~0; [L279] havoc is_master_triggered_~__retres1~0; [L282-L291] assume !(1 == ~m_pc~0); [L292] is_master_triggered_~__retres1~0 := 0; [L294] is_master_triggered_#res := is_master_triggered_~__retres1~0; [L731] activate_threads_#t~ret8 := is_master_triggered_#res; [L731] activate_threads_~tmp~1 := activate_threads_#t~ret8; [L731] havoc activate_threads_#t~ret8; [L733-L737] assume !(0 != activate_threads_~tmp~1); [L739] havoc is_transmit1_triggered_#res; [L739] havoc is_transmit1_triggered_~__retres1~1; [L298] havoc is_transmit1_triggered_~__retres1~1; [L301-L310] assume !(1 == ~t1_pc~0); [L311] is_transmit1_triggered_~__retres1~1 := 0; [L313] is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; [L739] activate_threads_#t~ret9 := is_transmit1_triggered_#res; [L739] activate_threads_~tmp___0~0 := activate_threads_#t~ret9; [L739] havoc activate_threads_#t~ret9; [L741-L745] assume !(0 != activate_threads_~tmp___0~0); [L747] havoc is_transmit2_triggered_#res; [L747] havoc is_transmit2_triggered_~__retres1~2; [L317] havoc is_transmit2_triggered_~__retres1~2; [L320-L329] assume !(1 == ~t2_pc~0); [L330] is_transmit2_triggered_~__retres1~2 := 0; [L332] is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; [L747] activate_threads_#t~ret10 := is_transmit2_triggered_#res; [L747] activate_threads_~tmp___1~0 := activate_threads_#t~ret10; [L747] havoc activate_threads_#t~ret10; [L749-L753] assume !(0 != activate_threads_~tmp___1~0); [L755] havoc is_transmit3_triggered_#res; [L755] havoc is_transmit3_triggered_~__retres1~3; [L336] havoc is_transmit3_triggered_~__retres1~3; [L339-L348] assume !(1 == ~t3_pc~0); [L349] is_transmit3_triggered_~__retres1~3 := 0; [L351] is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; [L755] activate_threads_#t~ret11 := is_transmit3_triggered_#res; [L755] activate_threads_~tmp___2~0 := activate_threads_#t~ret11; [L755] havoc activate_threads_#t~ret11; [L757-L761] assume !(0 != activate_threads_~tmp___2~0); [L763] havoc is_transmit4_triggered_#res; [L763] havoc is_transmit4_triggered_~__retres1~4; [L355] havoc is_transmit4_triggered_~__retres1~4; [L358-L367] assume !(1 == ~t4_pc~0); [L368] is_transmit4_triggered_~__retres1~4 := 0; [L370] is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; [L763] activate_threads_#t~ret12 := is_transmit4_triggered_#res; [L763] activate_threads_~tmp___3~0 := activate_threads_#t~ret12; [L763] havoc activate_threads_#t~ret12; [L765-L769] assume !(0 != activate_threads_~tmp___3~0); [L771] havoc is_transmit5_triggered_#res; [L771] havoc is_transmit5_triggered_~__retres1~5; [L374] havoc is_transmit5_triggered_~__retres1~5; [L377-L386] assume !(1 == ~t5_pc~0); [L387] is_transmit5_triggered_~__retres1~5 := 0; [L389] is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; [L771] activate_threads_#t~ret13 := is_transmit5_triggered_#res; [L771] activate_threads_~tmp___4~0 := activate_threads_#t~ret13; [L771] havoc activate_threads_#t~ret13; [L773-L777] assume !(0 != activate_threads_~tmp___4~0); [L657-L661] assume !(1 == ~M_E~0); [L662-L666] assume !(1 == ~T1_E~0); [L667-L671] assume !(1 == ~T2_E~0); [L672-L676] assume !(1 == ~T3_E~0); [L677-L681] assume !(1 == ~T4_E~0); [L682-L686] assume !(1 == ~T5_E~0); [L687-L691] assume !(1 == ~E_M~0); [L692-L696] assume !(1 == ~E_1~0); [L697-L701] assume !(1 == ~E_2~0); [L702-L706] assume !(1 == ~E_3~0); [L707-L711] assume !(1 == ~E_4~0); [L712-L716] assume !(1 == ~E_5~0); [L918-L955] assume !false; [L921] start_simulation_~kernel_st~0 := 1; [L922] havoc eval_#t~ret1, eval_#t~nondet2, eval_~tmp_ndt_1~0, eval_#t~nondet3, eval_~tmp_ndt_2~0, eval_#t~nondet4, eval_~tmp_ndt_3~0, eval_#t~nondet5, eval_~tmp_ndt_4~0, eval_#t~nondet6, eval_~tmp_ndt_5~0, eval_#t~nondet7, eval_~tmp_ndt_6~0, eval_~tmp~0; [L480] havoc eval_~tmp~0; ----- ----- class de.uni_freiburg.informatik.ultimate.boogie.preprocessor.BoogiePreprocessorBacktranslator [L14] ~m_pc~0 := 0; [L15] ~t1_pc~0 := 0; [L16] ~t2_pc~0 := 0; [L17] ~t3_pc~0 := 0; [L18] ~t4_pc~0 := 0; [L19] ~t5_pc~0 := 0; [L20] ~m_st~0 := 0; [L21] ~t1_st~0 := 0; [L22] ~t2_st~0 := 0; [L23] ~t3_st~0 := 0; [L24] ~t4_st~0 := 0; [L25] ~t5_st~0 := 0; [L26] ~m_i~0 := 0; [L27] ~t1_i~0 := 0; [L28] ~t2_i~0 := 0; [L29] ~t3_i~0 := 0; [L30] ~t4_i~0 := 0; [L31] ~t5_i~0 := 0; [L32] ~M_E~0 := 2; [L33] ~T1_E~0 := 2; [L34] ~T2_E~0 := 2; [L35] ~T3_E~0 := 2; [L36] ~T4_E~0 := 2; [L37] ~T5_E~0 := 2; [L38] ~E_M~0 := 2; [L39] ~E_1~0 := 2; [L40] ~E_2~0 := 2; [L41] ~E_3~0 := 2; [L42] ~E_4~0 := 2; [L43] ~E_5~0 := 2; [L51] ~token~0 := 0; [L53] ~local~0 := 0; [?] havoc main_#res; [?] havoc main_~__retres1~7; [L963] havoc main_~__retres1~7; [L874] ~m_i~0 := 1; [L875] ~t1_i~0 := 1; [L876] ~t2_i~0 := 1; [L877] ~t3_i~0 := 1; [L878] ~t4_i~0 := 1; [L879] ~t5_i~0 := 1; [L968] havoc start_simulation_#t~ret15, start_simulation_#t~ret16, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1; [L904] havoc start_simulation_~kernel_st~0; [L905] havoc start_simulation_~tmp~3; [L906] havoc start_simulation_~tmp___0~1; [L910] start_simulation_~kernel_st~0 := 0; [L404-L408] assume 1 == ~m_i~0; [L405] ~m_st~0 := 0; [L409-L413] assume 1 == ~t1_i~0; [L410] ~t1_st~0 := 0; [L414-L418] assume 1 == ~t2_i~0; [L415] ~t2_st~0 := 0; [L419-L423] assume 1 == ~t3_i~0; [L420] ~t3_st~0 := 0; [L424-L428] assume 1 == ~t4_i~0; [L425] ~t4_st~0 := 0; [L429-L433] assume 1 == ~t5_i~0; [L430] ~t5_st~0 := 0; [L589-L593] assume !(0 == ~M_E~0); [L594-L598] assume !(0 == ~T1_E~0); [L599-L603] assume !(0 == ~T2_E~0); [L604-L608] assume !(0 == ~T3_E~0); [L609-L613] assume !(0 == ~T4_E~0); [L614-L618] assume !(0 == ~T5_E~0); [L619-L623] assume !(0 == ~E_M~0); [L624-L628] assume !(0 == ~E_1~0); [L629-L633] assume !(0 == ~E_2~0); [L634-L638] assume !(0 == ~E_3~0); [L639-L643] assume !(0 == ~E_4~0); [L644-L648] assume !(0 == ~E_5~0); [L914] havoc activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0; [L722] havoc activate_threads_~tmp~1; [L723] havoc activate_threads_~tmp___0~0; [L724] havoc activate_threads_~tmp___1~0; [L725] havoc activate_threads_~tmp___2~0; [L726] havoc activate_threads_~tmp___3~0; [L727] havoc activate_threads_~tmp___4~0; [L731] havoc is_master_triggered_#res; [L731] havoc is_master_triggered_~__retres1~0; [L279] havoc is_master_triggered_~__retres1~0; [L282-L291] assume !(1 == ~m_pc~0); [L292] is_master_triggered_~__retres1~0 := 0; [L294] is_master_triggered_#res := is_master_triggered_~__retres1~0; [L731] activate_threads_#t~ret8 := is_master_triggered_#res; [L731] activate_threads_~tmp~1 := activate_threads_#t~ret8; [L731] havoc activate_threads_#t~ret8; [L733-L737] assume !(0 != activate_threads_~tmp~1); [L739] havoc is_transmit1_triggered_#res; [L739] havoc is_transmit1_triggered_~__retres1~1; [L298] havoc is_transmit1_triggered_~__retres1~1; [L301-L310] assume !(1 == ~t1_pc~0); [L311] is_transmit1_triggered_~__retres1~1 := 0; [L313] is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; [L739] activate_threads_#t~ret9 := is_transmit1_triggered_#res; [L739] activate_threads_~tmp___0~0 := activate_threads_#t~ret9; [L739] havoc activate_threads_#t~ret9; [L741-L745] assume !(0 != activate_threads_~tmp___0~0); [L747] havoc is_transmit2_triggered_#res; [L747] havoc is_transmit2_triggered_~__retres1~2; [L317] havoc is_transmit2_triggered_~__retres1~2; [L320-L329] assume !(1 == ~t2_pc~0); [L330] is_transmit2_triggered_~__retres1~2 := 0; [L332] is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; [L747] activate_threads_#t~ret10 := is_transmit2_triggered_#res; [L747] activate_threads_~tmp___1~0 := activate_threads_#t~ret10; [L747] havoc activate_threads_#t~ret10; [L749-L753] assume !(0 != activate_threads_~tmp___1~0); [L755] havoc is_transmit3_triggered_#res; [L755] havoc is_transmit3_triggered_~__retres1~3; [L336] havoc is_transmit3_triggered_~__retres1~3; [L339-L348] assume !(1 == ~t3_pc~0); [L349] is_transmit3_triggered_~__retres1~3 := 0; [L351] is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; [L755] activate_threads_#t~ret11 := is_transmit3_triggered_#res; [L755] activate_threads_~tmp___2~0 := activate_threads_#t~ret11; [L755] havoc activate_threads_#t~ret11; [L757-L761] assume !(0 != activate_threads_~tmp___2~0); [L763] havoc is_transmit4_triggered_#res; [L763] havoc is_transmit4_triggered_~__retres1~4; [L355] havoc is_transmit4_triggered_~__retres1~4; [L358-L367] assume !(1 == ~t4_pc~0); [L368] is_transmit4_triggered_~__retres1~4 := 0; [L370] is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; [L763] activate_threads_#t~ret12 := is_transmit4_triggered_#res; [L763] activate_threads_~tmp___3~0 := activate_threads_#t~ret12; [L763] havoc activate_threads_#t~ret12; [L765-L769] assume !(0 != activate_threads_~tmp___3~0); [L771] havoc is_transmit5_triggered_#res; [L771] havoc is_transmit5_triggered_~__retres1~5; [L374] havoc is_transmit5_triggered_~__retres1~5; [L377-L386] assume !(1 == ~t5_pc~0); [L387] is_transmit5_triggered_~__retres1~5 := 0; [L389] is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; [L771] activate_threads_#t~ret13 := is_transmit5_triggered_#res; [L771] activate_threads_~tmp___4~0 := activate_threads_#t~ret13; [L771] havoc activate_threads_#t~ret13; [L773-L777] assume !(0 != activate_threads_~tmp___4~0); [L657-L661] assume !(1 == ~M_E~0); [L662-L666] assume !(1 == ~T1_E~0); [L667-L671] assume !(1 == ~T2_E~0); [L672-L676] assume !(1 == ~T3_E~0); [L677-L681] assume !(1 == ~T4_E~0); [L682-L686] assume !(1 == ~T5_E~0); [L687-L691] assume !(1 == ~E_M~0); [L692-L696] assume !(1 == ~E_1~0); [L697-L701] assume !(1 == ~E_2~0); [L702-L706] assume !(1 == ~E_3~0); [L707-L711] assume !(1 == ~E_4~0); [L712-L716] assume !(1 == ~E_5~0); [L918-L955] assume !false; [L921] start_simulation_~kernel_st~0 := 1; [L922] havoc eval_#t~ret1, eval_#t~nondet2, eval_~tmp_ndt_1~0, eval_#t~nondet3, eval_~tmp_ndt_2~0, eval_#t~nondet4, eval_~tmp_ndt_3~0, eval_#t~nondet5, eval_~tmp_ndt_4~0, eval_#t~nondet6, eval_~tmp_ndt_5~0, eval_#t~nondet7, eval_~tmp_ndt_6~0, eval_~tmp~0; [L480] havoc eval_~tmp~0; [L14] ~m_pc~0 := 0; [L15] ~t1_pc~0 := 0; [L16] ~t2_pc~0 := 0; [L17] ~t3_pc~0 := 0; [L18] ~t4_pc~0 := 0; [L19] ~t5_pc~0 := 0; [L20] ~m_st~0 := 0; [L21] ~t1_st~0 := 0; [L22] ~t2_st~0 := 0; [L23] ~t3_st~0 := 0; [L24] ~t4_st~0 := 0; [L25] ~t5_st~0 := 0; [L26] ~m_i~0 := 0; [L27] ~t1_i~0 := 0; [L28] ~t2_i~0 := 0; [L29] ~t3_i~0 := 0; [L30] ~t4_i~0 := 0; [L31] ~t5_i~0 := 0; [L32] ~M_E~0 := 2; [L33] ~T1_E~0 := 2; [L34] ~T2_E~0 := 2; [L35] ~T3_E~0 := 2; [L36] ~T4_E~0 := 2; [L37] ~T5_E~0 := 2; [L38] ~E_M~0 := 2; [L39] ~E_1~0 := 2; [L40] ~E_2~0 := 2; [L41] ~E_3~0 := 2; [L42] ~E_4~0 := 2; [L43] ~E_5~0 := 2; [L51] ~token~0 := 0; [L53] ~local~0 := 0; [?] havoc main_#res; [?] havoc main_~__retres1~7; [L963] havoc main_~__retres1~7; [L874] ~m_i~0 := 1; [L875] ~t1_i~0 := 1; [L876] ~t2_i~0 := 1; [L877] ~t3_i~0 := 1; [L878] ~t4_i~0 := 1; [L879] ~t5_i~0 := 1; [L968] havoc start_simulation_#t~ret15, start_simulation_#t~ret16, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1; [L904] havoc start_simulation_~kernel_st~0; [L905] havoc start_simulation_~tmp~3; [L906] havoc start_simulation_~tmp___0~1; [L910] start_simulation_~kernel_st~0 := 0; [L404] COND TRUE 1 == ~m_i~0 [L405] ~m_st~0 := 0; [L409] COND TRUE 1 == ~t1_i~0 [L410] ~t1_st~0 := 0; [L414] COND TRUE 1 == ~t2_i~0 [L415] ~t2_st~0 := 0; [L419] COND TRUE 1 == ~t3_i~0 [L420] ~t3_st~0 := 0; [L424] COND TRUE 1 == ~t4_i~0 [L425] ~t4_st~0 := 0; [L429] COND TRUE 1 == ~t5_i~0 [L430] ~t5_st~0 := 0; [L589] COND FALSE !(0 == ~M_E~0) [L594] COND FALSE !(0 == ~T1_E~0) [L599] COND FALSE !(0 == ~T2_E~0) [L604] COND FALSE !(0 == ~T3_E~0) [L609] COND FALSE !(0 == ~T4_E~0) [L614] COND FALSE !(0 == ~T5_E~0) [L619] COND FALSE !(0 == ~E_M~0) [L624] COND FALSE !(0 == ~E_1~0) [L629] COND FALSE !(0 == ~E_2~0) [L634] COND FALSE !(0 == ~E_3~0) [L639] COND FALSE !(0 == ~E_4~0) [L644] COND FALSE !(0 == ~E_5~0) [L914] havoc activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0; [L722] havoc activate_threads_~tmp~1; [L723] havoc activate_threads_~tmp___0~0; [L724] havoc activate_threads_~tmp___1~0; [L725] havoc activate_threads_~tmp___2~0; [L726] havoc activate_threads_~tmp___3~0; [L727] havoc activate_threads_~tmp___4~0; [L731] havoc is_master_triggered_#res; [L731] havoc is_master_triggered_~__retres1~0; [L279] havoc is_master_triggered_~__retres1~0; [L282] COND FALSE !(1 == ~m_pc~0) [L292] is_master_triggered_~__retres1~0 := 0; [L294] is_master_triggered_#res := is_master_triggered_~__retres1~0; [L731] activate_threads_#t~ret8 := is_master_triggered_#res; [L731] activate_threads_~tmp~1 := activate_threads_#t~ret8; [L731] havoc activate_threads_#t~ret8; [L733-L737] COND FALSE !(0 != activate_threads_~tmp~1) [L739] havoc is_transmit1_triggered_#res; [L739] havoc is_transmit1_triggered_~__retres1~1; [L298] havoc is_transmit1_triggered_~__retres1~1; [L301] COND FALSE !(1 == ~t1_pc~0) [L311] is_transmit1_triggered_~__retres1~1 := 0; [L313] is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; [L739] activate_threads_#t~ret9 := is_transmit1_triggered_#res; [L739] activate_threads_~tmp___0~0 := activate_threads_#t~ret9; [L739] havoc activate_threads_#t~ret9; [L741-L745] COND FALSE !(0 != activate_threads_~tmp___0~0) [L747] havoc is_transmit2_triggered_#res; [L747] havoc is_transmit2_triggered_~__retres1~2; [L317] havoc is_transmit2_triggered_~__retres1~2; [L320] COND FALSE !(1 == ~t2_pc~0) [L330] is_transmit2_triggered_~__retres1~2 := 0; [L332] is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; [L747] activate_threads_#t~ret10 := is_transmit2_triggered_#res; [L747] activate_threads_~tmp___1~0 := activate_threads_#t~ret10; [L747] havoc activate_threads_#t~ret10; [L749-L753] COND FALSE !(0 != activate_threads_~tmp___1~0) [L755] havoc is_transmit3_triggered_#res; [L755] havoc is_transmit3_triggered_~__retres1~3; [L336] havoc is_transmit3_triggered_~__retres1~3; [L339] COND FALSE !(1 == ~t3_pc~0) [L349] is_transmit3_triggered_~__retres1~3 := 0; [L351] is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; [L755] activate_threads_#t~ret11 := is_transmit3_triggered_#res; [L755] activate_threads_~tmp___2~0 := activate_threads_#t~ret11; [L755] havoc activate_threads_#t~ret11; [L757-L761] COND FALSE !(0 != activate_threads_~tmp___2~0) [L763] havoc is_transmit4_triggered_#res; [L763] havoc is_transmit4_triggered_~__retres1~4; [L355] havoc is_transmit4_triggered_~__retres1~4; [L358] COND FALSE !(1 == ~t4_pc~0) [L368] is_transmit4_triggered_~__retres1~4 := 0; [L370] is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; [L763] activate_threads_#t~ret12 := is_transmit4_triggered_#res; [L763] activate_threads_~tmp___3~0 := activate_threads_#t~ret12; [L763] havoc activate_threads_#t~ret12; [L765-L769] COND FALSE !(0 != activate_threads_~tmp___3~0) [L771] havoc is_transmit5_triggered_#res; [L771] havoc is_transmit5_triggered_~__retres1~5; [L374] havoc is_transmit5_triggered_~__retres1~5; [L377] COND FALSE !(1 == ~t5_pc~0) [L387] is_transmit5_triggered_~__retres1~5 := 0; [L389] is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; [L771] activate_threads_#t~ret13 := is_transmit5_triggered_#res; [L771] activate_threads_~tmp___4~0 := activate_threads_#t~ret13; [L771] havoc activate_threads_#t~ret13; [L773-L777] COND FALSE !(0 != activate_threads_~tmp___4~0) [L657] COND FALSE !(1 == ~M_E~0) [L662] COND FALSE !(1 == ~T1_E~0) [L667] COND FALSE !(1 == ~T2_E~0) [L672] COND FALSE !(1 == ~T3_E~0) [L677] COND FALSE !(1 == ~T4_E~0) [L682] COND FALSE !(1 == ~T5_E~0) [L687] COND FALSE !(1 == ~E_M~0) [L692] COND FALSE !(1 == ~E_1~0) [L697] COND FALSE !(1 == ~E_2~0) [L702] COND FALSE !(1 == ~E_3~0) [L707] COND FALSE !(1 == ~E_4~0) [L712] COND FALSE !(1 == ~E_5~0) [L918-L955] COND FALSE !(false) [L921] start_simulation_~kernel_st~0 := 1; [L922] havoc eval_#t~ret1, eval_#t~nondet2, eval_~tmp_ndt_1~0, eval_#t~nondet3, eval_~tmp_ndt_2~0, eval_#t~nondet4, eval_~tmp_ndt_3~0, eval_#t~nondet5, eval_~tmp_ndt_4~0, eval_#t~nondet6, eval_~tmp_ndt_5~0, eval_#t~nondet7, eval_~tmp_ndt_6~0, eval_~tmp~0; [L480] havoc eval_~tmp~0; ----- ----- class de.uni_freiburg.informatik.ultimate.boogie.procedureinliner.backtranslation.InlinerBacktranslator [L14] ~m_pc~0 := 0; [L15] ~t1_pc~0 := 0; [L16] ~t2_pc~0 := 0; [L17] ~t3_pc~0 := 0; [L18] ~t4_pc~0 := 0; [L19] ~t5_pc~0 := 0; [L20] ~m_st~0 := 0; [L21] ~t1_st~0 := 0; [L22] ~t2_st~0 := 0; [L23] ~t3_st~0 := 0; [L24] ~t4_st~0 := 0; [L25] ~t5_st~0 := 0; [L26] ~m_i~0 := 0; [L27] ~t1_i~0 := 0; [L28] ~t2_i~0 := 0; [L29] ~t3_i~0 := 0; [L30] ~t4_i~0 := 0; [L31] ~t5_i~0 := 0; [L32] ~M_E~0 := 2; [L33] ~T1_E~0 := 2; [L34] ~T2_E~0 := 2; [L35] ~T3_E~0 := 2; [L36] ~T4_E~0 := 2; [L37] ~T5_E~0 := 2; [L38] ~E_M~0 := 2; [L39] ~E_1~0 := 2; [L40] ~E_2~0 := 2; [L41] ~E_3~0 := 2; [L42] ~E_4~0 := 2; [L43] ~E_5~0 := 2; [L51] ~token~0 := 0; [L53] ~local~0 := 0; [?] havoc main_#res; [?] havoc main_~__retres1~7; [L963] havoc main_~__retres1~7; [L874] ~m_i~0 := 1; [L875] ~t1_i~0 := 1; [L876] ~t2_i~0 := 1; [L877] ~t3_i~0 := 1; [L878] ~t4_i~0 := 1; [L879] ~t5_i~0 := 1; [L968] havoc start_simulation_#t~ret15, start_simulation_#t~ret16, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1; [L904] havoc start_simulation_~kernel_st~0; [L905] havoc start_simulation_~tmp~3; [L906] havoc start_simulation_~tmp___0~1; [L910] start_simulation_~kernel_st~0 := 0; [L404] COND TRUE 1 == ~m_i~0 [L405] ~m_st~0 := 0; [L409] COND TRUE 1 == ~t1_i~0 [L410] ~t1_st~0 := 0; [L414] COND TRUE 1 == ~t2_i~0 [L415] ~t2_st~0 := 0; [L419] COND TRUE 1 == ~t3_i~0 [L420] ~t3_st~0 := 0; [L424] COND TRUE 1 == ~t4_i~0 [L425] ~t4_st~0 := 0; [L429] COND TRUE 1 == ~t5_i~0 [L430] ~t5_st~0 := 0; [L589] COND FALSE !(0 == ~M_E~0) [L594] COND FALSE !(0 == ~T1_E~0) [L599] COND FALSE !(0 == ~T2_E~0) [L604] COND FALSE !(0 == ~T3_E~0) [L609] COND FALSE !(0 == ~T4_E~0) [L614] COND FALSE !(0 == ~T5_E~0) [L619] COND FALSE !(0 == ~E_M~0) [L624] COND FALSE !(0 == ~E_1~0) [L629] COND FALSE !(0 == ~E_2~0) [L634] COND FALSE !(0 == ~E_3~0) [L639] COND FALSE !(0 == ~E_4~0) [L644] COND FALSE !(0 == ~E_5~0) [L914] havoc activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0; [L722] havoc activate_threads_~tmp~1; [L723] havoc activate_threads_~tmp___0~0; [L724] havoc activate_threads_~tmp___1~0; [L725] havoc activate_threads_~tmp___2~0; [L726] havoc activate_threads_~tmp___3~0; [L727] havoc activate_threads_~tmp___4~0; [L731] havoc is_master_triggered_#res; [L731] havoc is_master_triggered_~__retres1~0; [L279] havoc is_master_triggered_~__retres1~0; [L282] COND FALSE !(1 == ~m_pc~0) [L292] is_master_triggered_~__retres1~0 := 0; [L294] is_master_triggered_#res := is_master_triggered_~__retres1~0; [L731] activate_threads_#t~ret8 := is_master_triggered_#res; [L731] activate_threads_~tmp~1 := activate_threads_#t~ret8; [L731] havoc activate_threads_#t~ret8; [L733-L737] COND FALSE !(0 != activate_threads_~tmp~1) [L739] havoc is_transmit1_triggered_#res; [L739] havoc is_transmit1_triggered_~__retres1~1; [L298] havoc is_transmit1_triggered_~__retres1~1; [L301] COND FALSE !(1 == ~t1_pc~0) [L311] is_transmit1_triggered_~__retres1~1 := 0; [L313] is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; [L739] activate_threads_#t~ret9 := is_transmit1_triggered_#res; [L739] activate_threads_~tmp___0~0 := activate_threads_#t~ret9; [L739] havoc activate_threads_#t~ret9; [L741-L745] COND FALSE !(0 != activate_threads_~tmp___0~0) [L747] havoc is_transmit2_triggered_#res; [L747] havoc is_transmit2_triggered_~__retres1~2; [L317] havoc is_transmit2_triggered_~__retres1~2; [L320] COND FALSE !(1 == ~t2_pc~0) [L330] is_transmit2_triggered_~__retres1~2 := 0; [L332] is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; [L747] activate_threads_#t~ret10 := is_transmit2_triggered_#res; [L747] activate_threads_~tmp___1~0 := activate_threads_#t~ret10; [L747] havoc activate_threads_#t~ret10; [L749-L753] COND FALSE !(0 != activate_threads_~tmp___1~0) [L755] havoc is_transmit3_triggered_#res; [L755] havoc is_transmit3_triggered_~__retres1~3; [L336] havoc is_transmit3_triggered_~__retres1~3; [L339] COND FALSE !(1 == ~t3_pc~0) [L349] is_transmit3_triggered_~__retres1~3 := 0; [L351] is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; [L755] activate_threads_#t~ret11 := is_transmit3_triggered_#res; [L755] activate_threads_~tmp___2~0 := activate_threads_#t~ret11; [L755] havoc activate_threads_#t~ret11; [L757-L761] COND FALSE !(0 != activate_threads_~tmp___2~0) [L763] havoc is_transmit4_triggered_#res; [L763] havoc is_transmit4_triggered_~__retres1~4; [L355] havoc is_transmit4_triggered_~__retres1~4; [L358] COND FALSE !(1 == ~t4_pc~0) [L368] is_transmit4_triggered_~__retres1~4 := 0; [L370] is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; [L763] activate_threads_#t~ret12 := is_transmit4_triggered_#res; [L763] activate_threads_~tmp___3~0 := activate_threads_#t~ret12; [L763] havoc activate_threads_#t~ret12; [L765-L769] COND FALSE !(0 != activate_threads_~tmp___3~0) [L771] havoc is_transmit5_triggered_#res; [L771] havoc is_transmit5_triggered_~__retres1~5; [L374] havoc is_transmit5_triggered_~__retres1~5; [L377] COND FALSE !(1 == ~t5_pc~0) [L387] is_transmit5_triggered_~__retres1~5 := 0; [L389] is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; [L771] activate_threads_#t~ret13 := is_transmit5_triggered_#res; [L771] activate_threads_~tmp___4~0 := activate_threads_#t~ret13; [L771] havoc activate_threads_#t~ret13; [L773-L777] COND FALSE !(0 != activate_threads_~tmp___4~0) [L657] COND FALSE !(1 == ~M_E~0) [L662] COND FALSE !(1 == ~T1_E~0) [L667] COND FALSE !(1 == ~T2_E~0) [L672] COND FALSE !(1 == ~T3_E~0) [L677] COND FALSE !(1 == ~T4_E~0) [L682] COND FALSE !(1 == ~T5_E~0) [L687] COND FALSE !(1 == ~E_M~0) [L692] COND FALSE !(1 == ~E_1~0) [L697] COND FALSE !(1 == ~E_2~0) [L702] COND FALSE !(1 == ~E_3~0) [L707] COND FALSE !(1 == ~E_4~0) [L712] COND FALSE !(1 == ~E_5~0) [L918-L955] COND FALSE !(false) [L921] start_simulation_~kernel_st~0 := 1; [L922] havoc eval_#t~ret1, eval_#t~nondet2, eval_~tmp_ndt_1~0, eval_#t~nondet3, eval_~tmp_ndt_2~0, eval_#t~nondet4, eval_~tmp_ndt_3~0, eval_#t~nondet5, eval_~tmp_ndt_4~0, eval_#t~nondet6, eval_~tmp_ndt_5~0, eval_#t~nondet7, eval_~tmp_ndt_6~0, eval_~tmp~0; [L480] havoc eval_~tmp~0; [L14] ~m_pc~0 := 0; [L15] ~t1_pc~0 := 0; [L16] ~t2_pc~0 := 0; [L17] ~t3_pc~0 := 0; [L18] ~t4_pc~0 := 0; [L19] ~t5_pc~0 := 0; [L20] ~m_st~0 := 0; [L21] ~t1_st~0 := 0; [L22] ~t2_st~0 := 0; [L23] ~t3_st~0 := 0; [L24] ~t4_st~0 := 0; [L25] ~t5_st~0 := 0; [L26] ~m_i~0 := 0; [L27] ~t1_i~0 := 0; [L28] ~t2_i~0 := 0; [L29] ~t3_i~0 := 0; [L30] ~t4_i~0 := 0; [L31] ~t5_i~0 := 0; [L32] ~M_E~0 := 2; [L33] ~T1_E~0 := 2; [L34] ~T2_E~0 := 2; [L35] ~T3_E~0 := 2; [L36] ~T4_E~0 := 2; [L37] ~T5_E~0 := 2; [L38] ~E_M~0 := 2; [L39] ~E_1~0 := 2; [L40] ~E_2~0 := 2; [L41] ~E_3~0 := 2; [L42] ~E_4~0 := 2; [L43] ~E_5~0 := 2; [L51] ~token~0 := 0; [L53] ~local~0 := 0; [L963] havoc ~__retres1~7; [L874] ~m_i~0 := 1; [L875] ~t1_i~0 := 1; [L876] ~t2_i~0 := 1; [L877] ~t3_i~0 := 1; [L878] ~t4_i~0 := 1; [L879] ~t5_i~0 := 1; [L904] havoc ~kernel_st~0; [L905] havoc ~tmp~3; [L906] havoc ~tmp___0~1; [L910] ~kernel_st~0 := 0; [L404] COND TRUE 1 == ~m_i~0 [L405] ~m_st~0 := 0; [L409] COND TRUE 1 == ~t1_i~0 [L410] ~t1_st~0 := 0; [L414] COND TRUE 1 == ~t2_i~0 [L415] ~t2_st~0 := 0; [L419] COND TRUE 1 == ~t3_i~0 [L420] ~t3_st~0 := 0; [L424] COND TRUE 1 == ~t4_i~0 [L425] ~t4_st~0 := 0; [L429] COND TRUE 1 == ~t5_i~0 [L430] ~t5_st~0 := 0; [L589] COND FALSE !(0 == ~M_E~0) [L594] COND FALSE !(0 == ~T1_E~0) [L599] COND FALSE !(0 == ~T2_E~0) [L604] COND FALSE !(0 == ~T3_E~0) [L609] COND FALSE !(0 == ~T4_E~0) [L614] COND FALSE !(0 == ~T5_E~0) [L619] COND FALSE !(0 == ~E_M~0) [L624] COND FALSE !(0 == ~E_1~0) [L629] COND FALSE !(0 == ~E_2~0) [L634] COND FALSE !(0 == ~E_3~0) [L639] COND FALSE !(0 == ~E_4~0) [L644] COND FALSE !(0 == ~E_5~0) [L722] havoc ~tmp~1; [L723] havoc ~tmp___0~0; [L724] havoc ~tmp___1~0; [L725] havoc ~tmp___2~0; [L726] havoc ~tmp___3~0; [L727] havoc ~tmp___4~0; [L279] havoc ~__retres1~0; [L282] COND FALSE !(1 == ~m_pc~0) [L292] ~__retres1~0 := 0; [L294] #res := ~__retres1~0; [L731] ~tmp~1 := #t~ret8; [L731] havoc #t~ret8; [L733-L737] COND FALSE !(0 != ~tmp~1) [L298] havoc ~__retres1~1; [L301] COND FALSE !(1 == ~t1_pc~0) [L311] ~__retres1~1 := 0; [L313] #res := ~__retres1~1; [L739] ~tmp___0~0 := #t~ret9; [L739] havoc #t~ret9; [L741-L745] COND FALSE !(0 != ~tmp___0~0) [L317] havoc ~__retres1~2; [L320] COND FALSE !(1 == ~t2_pc~0) [L330] ~__retres1~2 := 0; [L332] #res := ~__retres1~2; [L747] ~tmp___1~0 := #t~ret10; [L747] havoc #t~ret10; [L749-L753] COND FALSE !(0 != ~tmp___1~0) [L336] havoc ~__retres1~3; [L339] COND FALSE !(1 == ~t3_pc~0) [L349] ~__retres1~3 := 0; [L351] #res := ~__retres1~3; [L755] ~tmp___2~0 := #t~ret11; [L755] havoc #t~ret11; [L757-L761] COND FALSE !(0 != ~tmp___2~0) [L355] havoc ~__retres1~4; [L358] COND FALSE !(1 == ~t4_pc~0) [L368] ~__retres1~4 := 0; [L370] #res := ~__retres1~4; [L763] ~tmp___3~0 := #t~ret12; [L763] havoc #t~ret12; [L765-L769] COND FALSE !(0 != ~tmp___3~0) [L374] havoc ~__retres1~5; [L377] COND FALSE !(1 == ~t5_pc~0) [L387] ~__retres1~5 := 0; [L389] #res := ~__retres1~5; [L771] ~tmp___4~0 := #t~ret13; [L771] havoc #t~ret13; [L773-L777] COND FALSE !(0 != ~tmp___4~0) [L657] COND FALSE !(1 == ~M_E~0) [L662] COND FALSE !(1 == ~T1_E~0) [L667] COND FALSE !(1 == ~T2_E~0) [L672] COND FALSE !(1 == ~T3_E~0) [L677] COND FALSE !(1 == ~T4_E~0) [L682] COND FALSE !(1 == ~T5_E~0) [L687] COND FALSE !(1 == ~E_M~0) [L692] COND FALSE !(1 == ~E_1~0) [L697] COND FALSE !(1 == ~E_2~0) [L702] COND FALSE !(1 == ~E_3~0) [L707] COND FALSE !(1 == ~E_4~0) [L712] COND FALSE !(1 == ~E_5~0) [L918-L955] COND FALSE !(false) [L921] ~kernel_st~0 := 1; [L480] havoc ~tmp~0; ----- ----- class de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.CACSL2BoogieBacktranslator [L14] ~m_pc~0 := 0; [L15] ~t1_pc~0 := 0; [L16] ~t2_pc~0 := 0; [L17] ~t3_pc~0 := 0; [L18] ~t4_pc~0 := 0; [L19] ~t5_pc~0 := 0; [L20] ~m_st~0 := 0; [L21] ~t1_st~0 := 0; [L22] ~t2_st~0 := 0; [L23] ~t3_st~0 := 0; [L24] ~t4_st~0 := 0; [L25] ~t5_st~0 := 0; [L26] ~m_i~0 := 0; [L27] ~t1_i~0 := 0; [L28] ~t2_i~0 := 0; [L29] ~t3_i~0 := 0; [L30] ~t4_i~0 := 0; [L31] ~t5_i~0 := 0; [L32] ~M_E~0 := 2; [L33] ~T1_E~0 := 2; [L34] ~T2_E~0 := 2; [L35] ~T3_E~0 := 2; [L36] ~T4_E~0 := 2; [L37] ~T5_E~0 := 2; [L38] ~E_M~0 := 2; [L39] ~E_1~0 := 2; [L40] ~E_2~0 := 2; [L41] ~E_3~0 := 2; [L42] ~E_4~0 := 2; [L43] ~E_5~0 := 2; [L51] ~token~0 := 0; [L53] ~local~0 := 0; [L963] havoc ~__retres1~7; [L874] ~m_i~0 := 1; [L875] ~t1_i~0 := 1; [L876] ~t2_i~0 := 1; [L877] ~t3_i~0 := 1; [L878] ~t4_i~0 := 1; [L879] ~t5_i~0 := 1; [L904] havoc ~kernel_st~0; [L905] havoc ~tmp~3; [L906] havoc ~tmp___0~1; [L910] ~kernel_st~0 := 0; [L404] COND TRUE 1 == ~m_i~0 [L405] ~m_st~0 := 0; [L409] COND TRUE 1 == ~t1_i~0 [L410] ~t1_st~0 := 0; [L414] COND TRUE 1 == ~t2_i~0 [L415] ~t2_st~0 := 0; [L419] COND TRUE 1 == ~t3_i~0 [L420] ~t3_st~0 := 0; [L424] COND TRUE 1 == ~t4_i~0 [L425] ~t4_st~0 := 0; [L429] COND TRUE 1 == ~t5_i~0 [L430] ~t5_st~0 := 0; [L589] COND FALSE !(0 == ~M_E~0) [L594] COND FALSE !(0 == ~T1_E~0) [L599] COND FALSE !(0 == ~T2_E~0) [L604] COND FALSE !(0 == ~T3_E~0) [L609] COND FALSE !(0 == ~T4_E~0) [L614] COND FALSE !(0 == ~T5_E~0) [L619] COND FALSE !(0 == ~E_M~0) [L624] COND FALSE !(0 == ~E_1~0) [L629] COND FALSE !(0 == ~E_2~0) [L634] COND FALSE !(0 == ~E_3~0) [L639] COND FALSE !(0 == ~E_4~0) [L644] COND FALSE !(0 == ~E_5~0) [L722] havoc ~tmp~1; [L723] havoc ~tmp___0~0; [L724] havoc ~tmp___1~0; [L725] havoc ~tmp___2~0; [L726] havoc ~tmp___3~0; [L727] havoc ~tmp___4~0; [L279] havoc ~__retres1~0; [L282] COND FALSE !(1 == ~m_pc~0) [L292] ~__retres1~0 := 0; [L294] #res := ~__retres1~0; [L731] ~tmp~1 := #t~ret8; [L731] havoc #t~ret8; [L733-L737] COND FALSE !(0 != ~tmp~1) [L298] havoc ~__retres1~1; [L301] COND FALSE !(1 == ~t1_pc~0) [L311] ~__retres1~1 := 0; [L313] #res := ~__retres1~1; [L739] ~tmp___0~0 := #t~ret9; [L739] havoc #t~ret9; [L741-L745] COND FALSE !(0 != ~tmp___0~0) [L317] havoc ~__retres1~2; [L320] COND FALSE !(1 == ~t2_pc~0) [L330] ~__retres1~2 := 0; [L332] #res := ~__retres1~2; [L747] ~tmp___1~0 := #t~ret10; [L747] havoc #t~ret10; [L749-L753] COND FALSE !(0 != ~tmp___1~0) [L336] havoc ~__retres1~3; [L339] COND FALSE !(1 == ~t3_pc~0) [L349] ~__retres1~3 := 0; [L351] #res := ~__retres1~3; [L755] ~tmp___2~0 := #t~ret11; [L755] havoc #t~ret11; [L757-L761] COND FALSE !(0 != ~tmp___2~0) [L355] havoc ~__retres1~4; [L358] COND FALSE !(1 == ~t4_pc~0) [L368] ~__retres1~4 := 0; [L370] #res := ~__retres1~4; [L763] ~tmp___3~0 := #t~ret12; [L763] havoc #t~ret12; [L765-L769] COND FALSE !(0 != ~tmp___3~0) [L374] havoc ~__retres1~5; [L377] COND FALSE !(1 == ~t5_pc~0) [L387] ~__retres1~5 := 0; [L389] #res := ~__retres1~5; [L771] ~tmp___4~0 := #t~ret13; [L771] havoc #t~ret13; [L773-L777] COND FALSE !(0 != ~tmp___4~0) [L657] COND FALSE !(1 == ~M_E~0) [L662] COND FALSE !(1 == ~T1_E~0) [L667] COND FALSE !(1 == ~T2_E~0) [L672] COND FALSE !(1 == ~T3_E~0) [L677] COND FALSE !(1 == ~T4_E~0) [L682] COND FALSE !(1 == ~T5_E~0) [L687] COND FALSE !(1 == ~E_M~0) [L692] COND FALSE !(1 == ~E_1~0) [L697] COND FALSE !(1 == ~E_2~0) [L702] COND FALSE !(1 == ~E_3~0) [L707] COND FALSE !(1 == ~E_4~0) [L712] COND FALSE !(1 == ~E_5~0) [L918-L955] COND FALSE !(false) [L921] ~kernel_st~0 := 1; [L480] havoc ~tmp~0; [L14] int m_pc = 0; [L15] int t1_pc = 0; [L16] int t2_pc = 0; [L17] int t3_pc = 0; [L18] int t4_pc = 0; [L19] int t5_pc = 0; [L20] int m_st ; [L21] int t1_st ; [L22] int t2_st ; [L23] int t3_st ; [L24] int t4_st ; [L25] int t5_st ; [L26] int m_i ; [L27] int t1_i ; [L28] int t2_i ; [L29] int t3_i ; [L30] int t4_i ; [L31] int t5_i ; [L32] int M_E = 2; [L33] int T1_E = 2; [L34] int T2_E = 2; [L35] int T3_E = 2; [L36] int T4_E = 2; [L37] int T5_E = 2; [L38] int E_M = 2; [L39] int E_1 = 2; [L40] int E_2 = 2; [L41] int E_3 = 2; [L42] int E_4 = 2; [L43] int E_5 = 2; [L51] int token ; [L53] int local ; [L963] int __retres1 ; [L874] m_i = 1 [L875] t1_i = 1 [L876] t2_i = 1 [L877] t3_i = 1 [L878] t4_i = 1 [L879] t5_i = 1 [L904] int kernel_st ; [L905] int tmp ; [L906] int tmp___0 ; [L910] kernel_st = 0 [L404] COND TRUE m_i == 1 [L405] m_st = 0 [L409] COND TRUE t1_i == 1 [L410] t1_st = 0 [L414] COND TRUE t2_i == 1 [L415] t2_st = 0 [L419] COND TRUE t3_i == 1 [L420] t3_st = 0 [L424] COND TRUE t4_i == 1 [L425] t4_st = 0 [L429] COND TRUE t5_i == 1 [L430] t5_st = 0 [L589] COND FALSE !(M_E == 0) [L594] COND FALSE !(T1_E == 0) [L599] COND FALSE !(T2_E == 0) [L604] COND FALSE !(T3_E == 0) [L609] COND FALSE !(T4_E == 0) [L614] COND FALSE !(T5_E == 0) [L619] COND FALSE !(E_M == 0) [L624] COND FALSE !(E_1 == 0) [L629] COND FALSE !(E_2 == 0) [L634] COND FALSE !(E_3 == 0) [L639] COND FALSE !(E_4 == 0) [L644] COND FALSE !(E_5 == 0) [L722] int tmp ; [L723] int tmp___0 ; [L724] int tmp___1 ; [L725] int tmp___2 ; [L726] int tmp___3 ; [L727] int tmp___4 ; [L279] int __retres1 ; [L282] COND FALSE !(m_pc == 1) [L292] __retres1 = 0 [L294] return (__retres1); [L731] tmp = is_master_triggered() [L733] COND FALSE !(\read(tmp)) [L298] int __retres1 ; [L301] COND FALSE !(t1_pc == 1) [L311] __retres1 = 0 [L313] return (__retres1); [L739] tmp___0 = is_transmit1_triggered() [L741] COND FALSE !(\read(tmp___0)) [L317] int __retres1 ; [L320] COND FALSE !(t2_pc == 1) [L330] __retres1 = 0 [L332] return (__retres1); [L747] tmp___1 = is_transmit2_triggered() [L749] COND FALSE !(\read(tmp___1)) [L336] int __retres1 ; [L339] COND FALSE !(t3_pc == 1) [L349] __retres1 = 0 [L351] return (__retres1); [L755] tmp___2 = is_transmit3_triggered() [L757] COND FALSE !(\read(tmp___2)) [L355] int __retres1 ; [L358] COND FALSE !(t4_pc == 1) [L368] __retres1 = 0 [L370] return (__retres1); [L763] tmp___3 = is_transmit4_triggered() [L765] COND FALSE !(\read(tmp___3)) [L374] int __retres1 ; [L377] COND FALSE !(t5_pc == 1) [L387] __retres1 = 0 [L389] return (__retres1); [L771] tmp___4 = is_transmit5_triggered() [L773] COND FALSE !(\read(tmp___4)) [L657] COND FALSE !(M_E == 1) [L662] COND FALSE !(T1_E == 1) [L667] COND FALSE !(T2_E == 1) [L672] COND FALSE !(T3_E == 1) [L677] COND FALSE !(T4_E == 1) [L682] COND FALSE !(T5_E == 1) [L687] COND FALSE !(E_M == 1) [L692] COND FALSE !(E_1 == 1) [L697] COND FALSE !(E_2 == 1) [L702] COND FALSE !(E_3 == 1) [L707] COND FALSE !(E_4 == 1) [L712] COND FALSE !(E_5 == 1) [L918] COND TRUE 1 [L921] kernel_st = 1 [L480] int tmp ; ----- ----- class de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder.RCFGBacktranslator [?] assume !false; [?] havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; [?] assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; [?] exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; [?] eval_#t~ret1 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret1;havoc eval_#t~ret1; [?] assume 0 != eval_~tmp~0; [?] assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0;eval_~tmp_ndt_1~0 := eval_#t~nondet2;havoc eval_#t~nondet2; [?] assume !(0 != eval_~tmp_ndt_1~0); [?] assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0;eval_~tmp_ndt_2~0 := eval_#t~nondet3;havoc eval_#t~nondet3; [?] assume !(0 != eval_~tmp_ndt_2~0); [?] assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0;eval_~tmp_ndt_3~0 := eval_#t~nondet4;havoc eval_#t~nondet4; [?] assume !(0 != eval_~tmp_ndt_3~0); [?] assume 0 == ~t3_st~0;havoc eval_~tmp_ndt_4~0;eval_~tmp_ndt_4~0 := eval_#t~nondet5;havoc eval_#t~nondet5; [?] assume !(0 != eval_~tmp_ndt_4~0); [?] assume 0 == ~t4_st~0;havoc eval_~tmp_ndt_5~0;eval_~tmp_ndt_5~0 := eval_#t~nondet6;havoc eval_#t~nondet6; [?] assume !(0 != eval_~tmp_ndt_5~0); [?] assume 0 == ~t5_st~0;havoc eval_~tmp_ndt_6~0;eval_~tmp_ndt_6~0 := eval_#t~nondet7;havoc eval_#t~nondet7; [?] assume !(0 != eval_~tmp_ndt_6~0); [L484-L578] assume !false; [L487] havoc exists_runnable_thread_#res; [L487] havoc exists_runnable_thread_~__retres1~6; [L439] havoc exists_runnable_thread_~__retres1~6; [L442-L472] assume 0 == ~m_st~0; [L443] exists_runnable_thread_~__retres1~6 := 1; [L475] exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; [L487] eval_#t~ret1 := exists_runnable_thread_#res; [L487] eval_~tmp~0 := eval_#t~ret1; [L487] havoc eval_#t~ret1; [L489-L493] assume 0 != eval_~tmp~0; [L494-L507] assume 0 == ~m_st~0; [L495] havoc eval_~tmp_ndt_1~0; [L496] eval_~tmp_ndt_1~0 := eval_#t~nondet2; [L496] havoc eval_#t~nondet2; [L497-L504] assume !(0 != eval_~tmp_ndt_1~0); [L508-L521] assume 0 == ~t1_st~0; [L509] havoc eval_~tmp_ndt_2~0; [L510] eval_~tmp_ndt_2~0 := eval_#t~nondet3; [L510] havoc eval_#t~nondet3; [L511-L518] assume !(0 != eval_~tmp_ndt_2~0); [L522-L535] assume 0 == ~t2_st~0; [L523] havoc eval_~tmp_ndt_3~0; [L524] eval_~tmp_ndt_3~0 := eval_#t~nondet4; [L524] havoc eval_#t~nondet4; [L525-L532] assume !(0 != eval_~tmp_ndt_3~0); [L536-L549] assume 0 == ~t3_st~0; [L537] havoc eval_~tmp_ndt_4~0; [L538] eval_~tmp_ndt_4~0 := eval_#t~nondet5; [L538] havoc eval_#t~nondet5; [L539-L546] assume !(0 != eval_~tmp_ndt_4~0); [L550-L563] assume 0 == ~t4_st~0; [L551] havoc eval_~tmp_ndt_5~0; [L552] eval_~tmp_ndt_5~0 := eval_#t~nondet6; [L552] havoc eval_#t~nondet6; [L553-L560] assume !(0 != eval_~tmp_ndt_5~0); [L564-L577] assume 0 == ~t5_st~0; [L565] havoc eval_~tmp_ndt_6~0; [L566] eval_~tmp_ndt_6~0 := eval_#t~nondet7; [L566] havoc eval_#t~nondet7; [L567-L574] assume !(0 != eval_~tmp_ndt_6~0); ----- ----- class de.uni_freiburg.informatik.ultimate.boogie.preprocessor.BoogiePreprocessorBacktranslator [L484-L578] assume !false; [L487] havoc exists_runnable_thread_#res; [L487] havoc exists_runnable_thread_~__retres1~6; [L439] havoc exists_runnable_thread_~__retres1~6; [L442-L472] assume 0 == ~m_st~0; [L443] exists_runnable_thread_~__retres1~6 := 1; [L475] exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; [L487] eval_#t~ret1 := exists_runnable_thread_#res; [L487] eval_~tmp~0 := eval_#t~ret1; [L487] havoc eval_#t~ret1; [L489-L493] assume 0 != eval_~tmp~0; [L494-L507] assume 0 == ~m_st~0; [L495] havoc eval_~tmp_ndt_1~0; [L496] eval_~tmp_ndt_1~0 := eval_#t~nondet2; [L496] havoc eval_#t~nondet2; [L497-L504] assume !(0 != eval_~tmp_ndt_1~0); [L508-L521] assume 0 == ~t1_st~0; [L509] havoc eval_~tmp_ndt_2~0; [L510] eval_~tmp_ndt_2~0 := eval_#t~nondet3; [L510] havoc eval_#t~nondet3; [L511-L518] assume !(0 != eval_~tmp_ndt_2~0); [L522-L535] assume 0 == ~t2_st~0; [L523] havoc eval_~tmp_ndt_3~0; [L524] eval_~tmp_ndt_3~0 := eval_#t~nondet4; [L524] havoc eval_#t~nondet4; [L525-L532] assume !(0 != eval_~tmp_ndt_3~0); [L536-L549] assume 0 == ~t3_st~0; [L537] havoc eval_~tmp_ndt_4~0; [L538] eval_~tmp_ndt_4~0 := eval_#t~nondet5; [L538] havoc eval_#t~nondet5; [L539-L546] assume !(0 != eval_~tmp_ndt_4~0); [L550-L563] assume 0 == ~t4_st~0; [L551] havoc eval_~tmp_ndt_5~0; [L552] eval_~tmp_ndt_5~0 := eval_#t~nondet6; [L552] havoc eval_#t~nondet6; [L553-L560] assume !(0 != eval_~tmp_ndt_5~0); [L564-L577] assume 0 == ~t5_st~0; [L565] havoc eval_~tmp_ndt_6~0; [L566] eval_~tmp_ndt_6~0 := eval_#t~nondet7; [L566] havoc eval_#t~nondet7; [L567-L574] assume !(0 != eval_~tmp_ndt_6~0); [L484-L578] COND FALSE !(false) [L487] havoc exists_runnable_thread_#res; [L487] havoc exists_runnable_thread_~__retres1~6; [L439] havoc exists_runnable_thread_~__retres1~6; [L442] COND TRUE 0 == ~m_st~0 [L443] exists_runnable_thread_~__retres1~6 := 1; [L475] exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; [L487] eval_#t~ret1 := exists_runnable_thread_#res; [L487] eval_~tmp~0 := eval_#t~ret1; [L487] havoc eval_#t~ret1; [L489-L493] COND TRUE 0 != eval_~tmp~0 [L494] COND TRUE 0 == ~m_st~0 [L495] havoc eval_~tmp_ndt_1~0; [L496] eval_~tmp_ndt_1~0 := eval_#t~nondet2; [L496] havoc eval_#t~nondet2; [L497-L504] COND FALSE !(0 != eval_~tmp_ndt_1~0) [L508] COND TRUE 0 == ~t1_st~0 [L509] havoc eval_~tmp_ndt_2~0; [L510] eval_~tmp_ndt_2~0 := eval_#t~nondet3; [L510] havoc eval_#t~nondet3; [L511-L518] COND FALSE !(0 != eval_~tmp_ndt_2~0) [L522] COND TRUE 0 == ~t2_st~0 [L523] havoc eval_~tmp_ndt_3~0; [L524] eval_~tmp_ndt_3~0 := eval_#t~nondet4; [L524] havoc eval_#t~nondet4; [L525-L532] COND FALSE !(0 != eval_~tmp_ndt_3~0) [L536] COND TRUE 0 == ~t3_st~0 [L537] havoc eval_~tmp_ndt_4~0; [L538] eval_~tmp_ndt_4~0 := eval_#t~nondet5; [L538] havoc eval_#t~nondet5; [L539-L546] COND FALSE !(0 != eval_~tmp_ndt_4~0) [L550] COND TRUE 0 == ~t4_st~0 [L551] havoc eval_~tmp_ndt_5~0; [L552] eval_~tmp_ndt_5~0 := eval_#t~nondet6; [L552] havoc eval_#t~nondet6; [L553-L560] COND FALSE !(0 != eval_~tmp_ndt_5~0) [L564] COND TRUE 0 == ~t5_st~0 [L565] havoc eval_~tmp_ndt_6~0; [L566] eval_~tmp_ndt_6~0 := eval_#t~nondet7; [L566] havoc eval_#t~nondet7; [L567-L574] COND FALSE !(0 != eval_~tmp_ndt_6~0) ----- ----- class de.uni_freiburg.informatik.ultimate.boogie.procedureinliner.backtranslation.InlinerBacktranslator [L484-L578] COND FALSE !(false) [L487] havoc exists_runnable_thread_#res; [L487] havoc exists_runnable_thread_~__retres1~6; [L439] havoc exists_runnable_thread_~__retres1~6; [L442] COND TRUE 0 == ~m_st~0 [L443] exists_runnable_thread_~__retres1~6 := 1; [L475] exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; [L487] eval_#t~ret1 := exists_runnable_thread_#res; [L487] eval_~tmp~0 := eval_#t~ret1; [L487] havoc eval_#t~ret1; [L489-L493] COND TRUE 0 != eval_~tmp~0 [L494] COND TRUE 0 == ~m_st~0 [L495] havoc eval_~tmp_ndt_1~0; [L496] eval_~tmp_ndt_1~0 := eval_#t~nondet2; [L496] havoc eval_#t~nondet2; [L497-L504] COND FALSE !(0 != eval_~tmp_ndt_1~0) [L508] COND TRUE 0 == ~t1_st~0 [L509] havoc eval_~tmp_ndt_2~0; [L510] eval_~tmp_ndt_2~0 := eval_#t~nondet3; [L510] havoc eval_#t~nondet3; [L511-L518] COND FALSE !(0 != eval_~tmp_ndt_2~0) [L522] COND TRUE 0 == ~t2_st~0 [L523] havoc eval_~tmp_ndt_3~0; [L524] eval_~tmp_ndt_3~0 := eval_#t~nondet4; [L524] havoc eval_#t~nondet4; [L525-L532] COND FALSE !(0 != eval_~tmp_ndt_3~0) [L536] COND TRUE 0 == ~t3_st~0 [L537] havoc eval_~tmp_ndt_4~0; [L538] eval_~tmp_ndt_4~0 := eval_#t~nondet5; [L538] havoc eval_#t~nondet5; [L539-L546] COND FALSE !(0 != eval_~tmp_ndt_4~0) [L550] COND TRUE 0 == ~t4_st~0 [L551] havoc eval_~tmp_ndt_5~0; [L552] eval_~tmp_ndt_5~0 := eval_#t~nondet6; [L552] havoc eval_#t~nondet6; [L553-L560] COND FALSE !(0 != eval_~tmp_ndt_5~0) [L564] COND TRUE 0 == ~t5_st~0 [L565] havoc eval_~tmp_ndt_6~0; [L566] eval_~tmp_ndt_6~0 := eval_#t~nondet7; [L566] havoc eval_#t~nondet7; [L567-L574] COND FALSE !(0 != eval_~tmp_ndt_6~0) [L484-L578] COND FALSE !(false) [L439] havoc ~__retres1~6; [L442] COND TRUE 0 == ~m_st~0 [L443] ~__retres1~6 := 1; [L475] #res := ~__retres1~6; [L487] ~tmp~0 := #t~ret1; [L487] havoc #t~ret1; [L489-L493] COND TRUE 0 != ~tmp~0 [L494] COND TRUE 0 == ~m_st~0 [L495] havoc ~tmp_ndt_1~0; [L496] ~tmp_ndt_1~0 := #t~nondet2; [L496] havoc #t~nondet2; [L497-L504] COND FALSE !(0 != ~tmp_ndt_1~0) [L508] COND TRUE 0 == ~t1_st~0 [L509] havoc ~tmp_ndt_2~0; [L510] ~tmp_ndt_2~0 := #t~nondet3; [L510] havoc #t~nondet3; [L511-L518] COND FALSE !(0 != ~tmp_ndt_2~0) [L522] COND TRUE 0 == ~t2_st~0 [L523] havoc ~tmp_ndt_3~0; [L524] ~tmp_ndt_3~0 := #t~nondet4; [L524] havoc #t~nondet4; [L525-L532] COND FALSE !(0 != ~tmp_ndt_3~0) [L536] COND TRUE 0 == ~t3_st~0 [L537] havoc ~tmp_ndt_4~0; [L538] ~tmp_ndt_4~0 := #t~nondet5; [L538] havoc #t~nondet5; [L539-L546] COND FALSE !(0 != ~tmp_ndt_4~0) [L550] COND TRUE 0 == ~t4_st~0 [L551] havoc ~tmp_ndt_5~0; [L552] ~tmp_ndt_5~0 := #t~nondet6; [L552] havoc #t~nondet6; [L553-L560] COND FALSE !(0 != ~tmp_ndt_5~0) [L564] COND TRUE 0 == ~t5_st~0 [L565] havoc ~tmp_ndt_6~0; [L566] ~tmp_ndt_6~0 := #t~nondet7; [L566] havoc #t~nondet7; [L567-L574] COND FALSE !(0 != ~tmp_ndt_6~0) ----- ----- class de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.CACSL2BoogieBacktranslator [L484-L578] COND FALSE !(false) [L439] havoc ~__retres1~6; [L442] COND TRUE 0 == ~m_st~0 [L443] ~__retres1~6 := 1; [L475] #res := ~__retres1~6; [L487] ~tmp~0 := #t~ret1; [L487] havoc #t~ret1; [L489-L493] COND TRUE 0 != ~tmp~0 [L494] COND TRUE 0 == ~m_st~0 [L495] havoc ~tmp_ndt_1~0; [L496] ~tmp_ndt_1~0 := #t~nondet2; [L496] havoc #t~nondet2; [L497-L504] COND FALSE !(0 != ~tmp_ndt_1~0) [L508] COND TRUE 0 == ~t1_st~0 [L509] havoc ~tmp_ndt_2~0; [L510] ~tmp_ndt_2~0 := #t~nondet3; [L510] havoc #t~nondet3; [L511-L518] COND FALSE !(0 != ~tmp_ndt_2~0) [L522] COND TRUE 0 == ~t2_st~0 [L523] havoc ~tmp_ndt_3~0; [L524] ~tmp_ndt_3~0 := #t~nondet4; [L524] havoc #t~nondet4; [L525-L532] COND FALSE !(0 != ~tmp_ndt_3~0) [L536] COND TRUE 0 == ~t3_st~0 [L537] havoc ~tmp_ndt_4~0; [L538] ~tmp_ndt_4~0 := #t~nondet5; [L538] havoc #t~nondet5; [L539-L546] COND FALSE !(0 != ~tmp_ndt_4~0) [L550] COND TRUE 0 == ~t4_st~0 [L551] havoc ~tmp_ndt_5~0; [L552] ~tmp_ndt_5~0 := #t~nondet6; [L552] havoc #t~nondet6; [L553-L560] COND FALSE !(0 != ~tmp_ndt_5~0) [L564] COND TRUE 0 == ~t5_st~0 [L565] havoc ~tmp_ndt_6~0; [L566] ~tmp_ndt_6~0 := #t~nondet7; [L566] havoc #t~nondet7; [L567-L574] COND FALSE !(0 != ~tmp_ndt_6~0) [L484] COND TRUE 1 [L439] int __retres1 ; [L442] COND TRUE m_st == 0 [L443] __retres1 = 1 [L475] return (__retres1); [L487] tmp = exists_runnable_thread() [L489] COND TRUE \read(tmp) [L494] COND TRUE m_st == 0 [L495] int tmp_ndt_1; [L496] tmp_ndt_1 = __VERIFIER_nondet_int() [L497] COND FALSE !(\read(tmp_ndt_1)) [L508] COND TRUE t1_st == 0 [L509] int tmp_ndt_2; [L510] tmp_ndt_2 = __VERIFIER_nondet_int() [L511] COND FALSE !(\read(tmp_ndt_2)) [L522] COND TRUE t2_st == 0 [L523] int tmp_ndt_3; [L524] tmp_ndt_3 = __VERIFIER_nondet_int() [L525] COND FALSE !(\read(tmp_ndt_3)) [L536] COND TRUE t3_st == 0 [L537] int tmp_ndt_4; [L538] tmp_ndt_4 = __VERIFIER_nondet_int() [L539] COND FALSE !(\read(tmp_ndt_4)) [L550] COND TRUE t4_st == 0 [L551] int tmp_ndt_5; [L552] tmp_ndt_5 = __VERIFIER_nondet_int() [L553] COND FALSE !(\read(tmp_ndt_5)) [L564] COND TRUE t5_st == 0 [L565] int tmp_ndt_6; [L566] tmp_ndt_6 = __VERIFIER_nondet_int() [L567] COND FALSE !(\read(tmp_ndt_6)) ----- [2018-11-23 13:21:57,533 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer CFG 23.11 01:21:57 BoogieIcfgContainer [2018-11-23 13:21:57,533 INFO L132 PluginConnector]: ------------------------ END BuchiAutomizer---------------------------- [2018-11-23 13:21:57,534 INFO L113 PluginConnector]: ------------------------Witness Printer---------------------------- [2018-11-23 13:21:57,534 INFO L271 PluginConnector]: Initializing Witness Printer... [2018-11-23 13:21:57,534 INFO L276 PluginConnector]: Witness Printer initialized [2018-11-23 13:21:57,534 INFO L185 PluginConnector]: Executing the observer RCFGCatcher from plugin Witness Printer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 23.11 01:21:49" (3/4) ... [2018-11-23 13:21:57,537 INFO L141 WitnessPrinter]: Generating witness for non-termination counterexample ----- class de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder.RCFGBacktranslator [?] ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; [?] havoc main_#res;havoc main_~__retres1~7;havoc main_~__retres1~7;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; [?] havoc start_simulation_#t~ret15, start_simulation_#t~ret16, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; [?] assume 1 == ~m_i~0;~m_st~0 := 0; [?] assume 1 == ~t1_i~0;~t1_st~0 := 0; [?] assume 1 == ~t2_i~0;~t2_st~0 := 0; [?] assume 1 == ~t3_i~0;~t3_st~0 := 0; [?] assume 1 == ~t4_i~0;~t4_st~0 := 0; [?] assume 1 == ~t5_i~0;~t5_st~0 := 0; [?] assume !(0 == ~M_E~0); [?] assume !(0 == ~T1_E~0); [?] assume !(0 == ~T2_E~0); [?] assume !(0 == ~T3_E~0); [?] assume !(0 == ~T4_E~0); [?] assume !(0 == ~T5_E~0); [?] assume !(0 == ~E_M~0); [?] assume !(0 == ~E_1~0); [?] assume !(0 == ~E_2~0); [?] assume !(0 == ~E_3~0); [?] assume !(0 == ~E_4~0); [?] assume !(0 == ~E_5~0); [?] havoc activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; [?] assume !(1 == ~m_pc~0); [?] is_master_triggered_~__retres1~0 := 0; [?] is_master_triggered_#res := is_master_triggered_~__retres1~0; [?] activate_threads_#t~ret8 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; [?] assume !(0 != activate_threads_~tmp~1); [?] havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; [?] assume !(1 == ~t1_pc~0); [?] is_transmit1_triggered_~__retres1~1 := 0; [?] is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; [?] activate_threads_#t~ret9 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; [?] assume !(0 != activate_threads_~tmp___0~0); [?] havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; [?] assume !(1 == ~t2_pc~0); [?] is_transmit2_triggered_~__retres1~2 := 0; [?] is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; [?] activate_threads_#t~ret10 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; [?] assume !(0 != activate_threads_~tmp___1~0); [?] havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; [?] assume !(1 == ~t3_pc~0); [?] is_transmit3_triggered_~__retres1~3 := 0; [?] is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; [?] activate_threads_#t~ret11 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; [?] assume !(0 != activate_threads_~tmp___2~0); [?] havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; [?] assume !(1 == ~t4_pc~0); [?] is_transmit4_triggered_~__retres1~4 := 0; [?] is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; [?] activate_threads_#t~ret12 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; [?] assume !(0 != activate_threads_~tmp___3~0); [?] havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; [?] assume !(1 == ~t5_pc~0); [?] is_transmit5_triggered_~__retres1~5 := 0; [?] is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; [?] activate_threads_#t~ret13 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; [?] assume !(0 != activate_threads_~tmp___4~0); [?] assume !(1 == ~M_E~0); [?] assume !(1 == ~T1_E~0); [?] assume !(1 == ~T2_E~0); [?] assume !(1 == ~T3_E~0); [?] assume !(1 == ~T4_E~0); [?] assume !(1 == ~T5_E~0); [?] assume !(1 == ~E_M~0); [?] assume !(1 == ~E_1~0); [?] assume !(1 == ~E_2~0); [?] assume !(1 == ~E_3~0); [?] assume !(1 == ~E_4~0); [?] assume !(1 == ~E_5~0); [?] assume !false; [?] start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret1, eval_#t~nondet2, eval_~tmp_ndt_1~0, eval_#t~nondet3, eval_~tmp_ndt_2~0, eval_#t~nondet4, eval_~tmp_ndt_3~0, eval_#t~nondet5, eval_~tmp_ndt_4~0, eval_#t~nondet6, eval_~tmp_ndt_5~0, eval_#t~nondet7, eval_~tmp_ndt_6~0, eval_~tmp~0;havoc eval_~tmp~0; [L14] ~m_pc~0 := 0; [L15] ~t1_pc~0 := 0; [L16] ~t2_pc~0 := 0; [L17] ~t3_pc~0 := 0; [L18] ~t4_pc~0 := 0; [L19] ~t5_pc~0 := 0; [L20] ~m_st~0 := 0; [L21] ~t1_st~0 := 0; [L22] ~t2_st~0 := 0; [L23] ~t3_st~0 := 0; [L24] ~t4_st~0 := 0; [L25] ~t5_st~0 := 0; [L26] ~m_i~0 := 0; [L27] ~t1_i~0 := 0; [L28] ~t2_i~0 := 0; [L29] ~t3_i~0 := 0; [L30] ~t4_i~0 := 0; [L31] ~t5_i~0 := 0; [L32] ~M_E~0 := 2; [L33] ~T1_E~0 := 2; [L34] ~T2_E~0 := 2; [L35] ~T3_E~0 := 2; [L36] ~T4_E~0 := 2; [L37] ~T5_E~0 := 2; [L38] ~E_M~0 := 2; [L39] ~E_1~0 := 2; [L40] ~E_2~0 := 2; [L41] ~E_3~0 := 2; [L42] ~E_4~0 := 2; [L43] ~E_5~0 := 2; [L51] ~token~0 := 0; [L53] ~local~0 := 0; [?] havoc main_#res; [?] havoc main_~__retres1~7; [L963] havoc main_~__retres1~7; [L874] ~m_i~0 := 1; [L875] ~t1_i~0 := 1; [L876] ~t2_i~0 := 1; [L877] ~t3_i~0 := 1; [L878] ~t4_i~0 := 1; [L879] ~t5_i~0 := 1; [L968] havoc start_simulation_#t~ret15, start_simulation_#t~ret16, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1; [L904] havoc start_simulation_~kernel_st~0; [L905] havoc start_simulation_~tmp~3; [L906] havoc start_simulation_~tmp___0~1; [L910] start_simulation_~kernel_st~0 := 0; [L404-L408] assume 1 == ~m_i~0; [L405] ~m_st~0 := 0; [L409-L413] assume 1 == ~t1_i~0; [L410] ~t1_st~0 := 0; [L414-L418] assume 1 == ~t2_i~0; [L415] ~t2_st~0 := 0; [L419-L423] assume 1 == ~t3_i~0; [L420] ~t3_st~0 := 0; [L424-L428] assume 1 == ~t4_i~0; [L425] ~t4_st~0 := 0; [L429-L433] assume 1 == ~t5_i~0; [L430] ~t5_st~0 := 0; [L589-L593] assume !(0 == ~M_E~0); [L594-L598] assume !(0 == ~T1_E~0); [L599-L603] assume !(0 == ~T2_E~0); [L604-L608] assume !(0 == ~T3_E~0); [L609-L613] assume !(0 == ~T4_E~0); [L614-L618] assume !(0 == ~T5_E~0); [L619-L623] assume !(0 == ~E_M~0); [L624-L628] assume !(0 == ~E_1~0); [L629-L633] assume !(0 == ~E_2~0); [L634-L638] assume !(0 == ~E_3~0); [L639-L643] assume !(0 == ~E_4~0); [L644-L648] assume !(0 == ~E_5~0); [L914] havoc activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0; [L722] havoc activate_threads_~tmp~1; [L723] havoc activate_threads_~tmp___0~0; [L724] havoc activate_threads_~tmp___1~0; [L725] havoc activate_threads_~tmp___2~0; [L726] havoc activate_threads_~tmp___3~0; [L727] havoc activate_threads_~tmp___4~0; [L731] havoc is_master_triggered_#res; [L731] havoc is_master_triggered_~__retres1~0; [L279] havoc is_master_triggered_~__retres1~0; [L282-L291] assume !(1 == ~m_pc~0); [L292] is_master_triggered_~__retres1~0 := 0; [L294] is_master_triggered_#res := is_master_triggered_~__retres1~0; [L731] activate_threads_#t~ret8 := is_master_triggered_#res; [L731] activate_threads_~tmp~1 := activate_threads_#t~ret8; [L731] havoc activate_threads_#t~ret8; [L733-L737] assume !(0 != activate_threads_~tmp~1); [L739] havoc is_transmit1_triggered_#res; [L739] havoc is_transmit1_triggered_~__retres1~1; [L298] havoc is_transmit1_triggered_~__retres1~1; [L301-L310] assume !(1 == ~t1_pc~0); [L311] is_transmit1_triggered_~__retres1~1 := 0; [L313] is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; [L739] activate_threads_#t~ret9 := is_transmit1_triggered_#res; [L739] activate_threads_~tmp___0~0 := activate_threads_#t~ret9; [L739] havoc activate_threads_#t~ret9; [L741-L745] assume !(0 != activate_threads_~tmp___0~0); [L747] havoc is_transmit2_triggered_#res; [L747] havoc is_transmit2_triggered_~__retres1~2; [L317] havoc is_transmit2_triggered_~__retres1~2; [L320-L329] assume !(1 == ~t2_pc~0); [L330] is_transmit2_triggered_~__retres1~2 := 0; [L332] is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; [L747] activate_threads_#t~ret10 := is_transmit2_triggered_#res; [L747] activate_threads_~tmp___1~0 := activate_threads_#t~ret10; [L747] havoc activate_threads_#t~ret10; [L749-L753] assume !(0 != activate_threads_~tmp___1~0); [L755] havoc is_transmit3_triggered_#res; [L755] havoc is_transmit3_triggered_~__retres1~3; [L336] havoc is_transmit3_triggered_~__retres1~3; [L339-L348] assume !(1 == ~t3_pc~0); [L349] is_transmit3_triggered_~__retres1~3 := 0; [L351] is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; [L755] activate_threads_#t~ret11 := is_transmit3_triggered_#res; [L755] activate_threads_~tmp___2~0 := activate_threads_#t~ret11; [L755] havoc activate_threads_#t~ret11; [L757-L761] assume !(0 != activate_threads_~tmp___2~0); [L763] havoc is_transmit4_triggered_#res; [L763] havoc is_transmit4_triggered_~__retres1~4; [L355] havoc is_transmit4_triggered_~__retres1~4; [L358-L367] assume !(1 == ~t4_pc~0); [L368] is_transmit4_triggered_~__retres1~4 := 0; [L370] is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; [L763] activate_threads_#t~ret12 := is_transmit4_triggered_#res; [L763] activate_threads_~tmp___3~0 := activate_threads_#t~ret12; [L763] havoc activate_threads_#t~ret12; [L765-L769] assume !(0 != activate_threads_~tmp___3~0); [L771] havoc is_transmit5_triggered_#res; [L771] havoc is_transmit5_triggered_~__retres1~5; [L374] havoc is_transmit5_triggered_~__retres1~5; [L377-L386] assume !(1 == ~t5_pc~0); [L387] is_transmit5_triggered_~__retres1~5 := 0; [L389] is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; [L771] activate_threads_#t~ret13 := is_transmit5_triggered_#res; [L771] activate_threads_~tmp___4~0 := activate_threads_#t~ret13; [L771] havoc activate_threads_#t~ret13; [L773-L777] assume !(0 != activate_threads_~tmp___4~0); [L657-L661] assume !(1 == ~M_E~0); [L662-L666] assume !(1 == ~T1_E~0); [L667-L671] assume !(1 == ~T2_E~0); [L672-L676] assume !(1 == ~T3_E~0); [L677-L681] assume !(1 == ~T4_E~0); [L682-L686] assume !(1 == ~T5_E~0); [L687-L691] assume !(1 == ~E_M~0); [L692-L696] assume !(1 == ~E_1~0); [L697-L701] assume !(1 == ~E_2~0); [L702-L706] assume !(1 == ~E_3~0); [L707-L711] assume !(1 == ~E_4~0); [L712-L716] assume !(1 == ~E_5~0); [L918-L955] assume !false; [L921] start_simulation_~kernel_st~0 := 1; [L922] havoc eval_#t~ret1, eval_#t~nondet2, eval_~tmp_ndt_1~0, eval_#t~nondet3, eval_~tmp_ndt_2~0, eval_#t~nondet4, eval_~tmp_ndt_3~0, eval_#t~nondet5, eval_~tmp_ndt_4~0, eval_#t~nondet6, eval_~tmp_ndt_5~0, eval_#t~nondet7, eval_~tmp_ndt_6~0, eval_~tmp~0; [L480] havoc eval_~tmp~0; ----- ----- class de.uni_freiburg.informatik.ultimate.boogie.preprocessor.BoogiePreprocessorBacktranslator [L14] ~m_pc~0 := 0; [L15] ~t1_pc~0 := 0; [L16] ~t2_pc~0 := 0; [L17] ~t3_pc~0 := 0; [L18] ~t4_pc~0 := 0; [L19] ~t5_pc~0 := 0; [L20] ~m_st~0 := 0; [L21] ~t1_st~0 := 0; [L22] ~t2_st~0 := 0; [L23] ~t3_st~0 := 0; [L24] ~t4_st~0 := 0; [L25] ~t5_st~0 := 0; [L26] ~m_i~0 := 0; [L27] ~t1_i~0 := 0; [L28] ~t2_i~0 := 0; [L29] ~t3_i~0 := 0; [L30] ~t4_i~0 := 0; [L31] ~t5_i~0 := 0; [L32] ~M_E~0 := 2; [L33] ~T1_E~0 := 2; [L34] ~T2_E~0 := 2; [L35] ~T3_E~0 := 2; [L36] ~T4_E~0 := 2; [L37] ~T5_E~0 := 2; [L38] ~E_M~0 := 2; [L39] ~E_1~0 := 2; [L40] ~E_2~0 := 2; [L41] ~E_3~0 := 2; [L42] ~E_4~0 := 2; [L43] ~E_5~0 := 2; [L51] ~token~0 := 0; [L53] ~local~0 := 0; [?] havoc main_#res; [?] havoc main_~__retres1~7; [L963] havoc main_~__retres1~7; [L874] ~m_i~0 := 1; [L875] ~t1_i~0 := 1; [L876] ~t2_i~0 := 1; [L877] ~t3_i~0 := 1; [L878] ~t4_i~0 := 1; [L879] ~t5_i~0 := 1; [L968] havoc start_simulation_#t~ret15, start_simulation_#t~ret16, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1; [L904] havoc start_simulation_~kernel_st~0; [L905] havoc start_simulation_~tmp~3; [L906] havoc start_simulation_~tmp___0~1; [L910] start_simulation_~kernel_st~0 := 0; [L404-L408] assume 1 == ~m_i~0; [L405] ~m_st~0 := 0; [L409-L413] assume 1 == ~t1_i~0; [L410] ~t1_st~0 := 0; [L414-L418] assume 1 == ~t2_i~0; [L415] ~t2_st~0 := 0; [L419-L423] assume 1 == ~t3_i~0; [L420] ~t3_st~0 := 0; [L424-L428] assume 1 == ~t4_i~0; [L425] ~t4_st~0 := 0; [L429-L433] assume 1 == ~t5_i~0; [L430] ~t5_st~0 := 0; [L589-L593] assume !(0 == ~M_E~0); [L594-L598] assume !(0 == ~T1_E~0); [L599-L603] assume !(0 == ~T2_E~0); [L604-L608] assume !(0 == ~T3_E~0); [L609-L613] assume !(0 == ~T4_E~0); [L614-L618] assume !(0 == ~T5_E~0); [L619-L623] assume !(0 == ~E_M~0); [L624-L628] assume !(0 == ~E_1~0); [L629-L633] assume !(0 == ~E_2~0); [L634-L638] assume !(0 == ~E_3~0); [L639-L643] assume !(0 == ~E_4~0); [L644-L648] assume !(0 == ~E_5~0); [L914] havoc activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0; [L722] havoc activate_threads_~tmp~1; [L723] havoc activate_threads_~tmp___0~0; [L724] havoc activate_threads_~tmp___1~0; [L725] havoc activate_threads_~tmp___2~0; [L726] havoc activate_threads_~tmp___3~0; [L727] havoc activate_threads_~tmp___4~0; [L731] havoc is_master_triggered_#res; [L731] havoc is_master_triggered_~__retres1~0; [L279] havoc is_master_triggered_~__retres1~0; [L282-L291] assume !(1 == ~m_pc~0); [L292] is_master_triggered_~__retres1~0 := 0; [L294] is_master_triggered_#res := is_master_triggered_~__retres1~0; [L731] activate_threads_#t~ret8 := is_master_triggered_#res; [L731] activate_threads_~tmp~1 := activate_threads_#t~ret8; [L731] havoc activate_threads_#t~ret8; [L733-L737] assume !(0 != activate_threads_~tmp~1); [L739] havoc is_transmit1_triggered_#res; [L739] havoc is_transmit1_triggered_~__retres1~1; [L298] havoc is_transmit1_triggered_~__retres1~1; [L301-L310] assume !(1 == ~t1_pc~0); [L311] is_transmit1_triggered_~__retres1~1 := 0; [L313] is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; [L739] activate_threads_#t~ret9 := is_transmit1_triggered_#res; [L739] activate_threads_~tmp___0~0 := activate_threads_#t~ret9; [L739] havoc activate_threads_#t~ret9; [L741-L745] assume !(0 != activate_threads_~tmp___0~0); [L747] havoc is_transmit2_triggered_#res; [L747] havoc is_transmit2_triggered_~__retres1~2; [L317] havoc is_transmit2_triggered_~__retres1~2; [L320-L329] assume !(1 == ~t2_pc~0); [L330] is_transmit2_triggered_~__retres1~2 := 0; [L332] is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; [L747] activate_threads_#t~ret10 := is_transmit2_triggered_#res; [L747] activate_threads_~tmp___1~0 := activate_threads_#t~ret10; [L747] havoc activate_threads_#t~ret10; [L749-L753] assume !(0 != activate_threads_~tmp___1~0); [L755] havoc is_transmit3_triggered_#res; [L755] havoc is_transmit3_triggered_~__retres1~3; [L336] havoc is_transmit3_triggered_~__retres1~3; [L339-L348] assume !(1 == ~t3_pc~0); [L349] is_transmit3_triggered_~__retres1~3 := 0; [L351] is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; [L755] activate_threads_#t~ret11 := is_transmit3_triggered_#res; [L755] activate_threads_~tmp___2~0 := activate_threads_#t~ret11; [L755] havoc activate_threads_#t~ret11; [L757-L761] assume !(0 != activate_threads_~tmp___2~0); [L763] havoc is_transmit4_triggered_#res; [L763] havoc is_transmit4_triggered_~__retres1~4; [L355] havoc is_transmit4_triggered_~__retres1~4; [L358-L367] assume !(1 == ~t4_pc~0); [L368] is_transmit4_triggered_~__retres1~4 := 0; [L370] is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; [L763] activate_threads_#t~ret12 := is_transmit4_triggered_#res; [L763] activate_threads_~tmp___3~0 := activate_threads_#t~ret12; [L763] havoc activate_threads_#t~ret12; [L765-L769] assume !(0 != activate_threads_~tmp___3~0); [L771] havoc is_transmit5_triggered_#res; [L771] havoc is_transmit5_triggered_~__retres1~5; [L374] havoc is_transmit5_triggered_~__retres1~5; [L377-L386] assume !(1 == ~t5_pc~0); [L387] is_transmit5_triggered_~__retres1~5 := 0; [L389] is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; [L771] activate_threads_#t~ret13 := is_transmit5_triggered_#res; [L771] activate_threads_~tmp___4~0 := activate_threads_#t~ret13; [L771] havoc activate_threads_#t~ret13; [L773-L777] assume !(0 != activate_threads_~tmp___4~0); [L657-L661] assume !(1 == ~M_E~0); [L662-L666] assume !(1 == ~T1_E~0); [L667-L671] assume !(1 == ~T2_E~0); [L672-L676] assume !(1 == ~T3_E~0); [L677-L681] assume !(1 == ~T4_E~0); [L682-L686] assume !(1 == ~T5_E~0); [L687-L691] assume !(1 == ~E_M~0); [L692-L696] assume !(1 == ~E_1~0); [L697-L701] assume !(1 == ~E_2~0); [L702-L706] assume !(1 == ~E_3~0); [L707-L711] assume !(1 == ~E_4~0); [L712-L716] assume !(1 == ~E_5~0); [L918-L955] assume !false; [L921] start_simulation_~kernel_st~0 := 1; [L922] havoc eval_#t~ret1, eval_#t~nondet2, eval_~tmp_ndt_1~0, eval_#t~nondet3, eval_~tmp_ndt_2~0, eval_#t~nondet4, eval_~tmp_ndt_3~0, eval_#t~nondet5, eval_~tmp_ndt_4~0, eval_#t~nondet6, eval_~tmp_ndt_5~0, eval_#t~nondet7, eval_~tmp_ndt_6~0, eval_~tmp~0; [L480] havoc eval_~tmp~0; [L14] ~m_pc~0 := 0; [L15] ~t1_pc~0 := 0; [L16] ~t2_pc~0 := 0; [L17] ~t3_pc~0 := 0; [L18] ~t4_pc~0 := 0; [L19] ~t5_pc~0 := 0; [L20] ~m_st~0 := 0; [L21] ~t1_st~0 := 0; [L22] ~t2_st~0 := 0; [L23] ~t3_st~0 := 0; [L24] ~t4_st~0 := 0; [L25] ~t5_st~0 := 0; [L26] ~m_i~0 := 0; [L27] ~t1_i~0 := 0; [L28] ~t2_i~0 := 0; [L29] ~t3_i~0 := 0; [L30] ~t4_i~0 := 0; [L31] ~t5_i~0 := 0; [L32] ~M_E~0 := 2; [L33] ~T1_E~0 := 2; [L34] ~T2_E~0 := 2; [L35] ~T3_E~0 := 2; [L36] ~T4_E~0 := 2; [L37] ~T5_E~0 := 2; [L38] ~E_M~0 := 2; [L39] ~E_1~0 := 2; [L40] ~E_2~0 := 2; [L41] ~E_3~0 := 2; [L42] ~E_4~0 := 2; [L43] ~E_5~0 := 2; [L51] ~token~0 := 0; [L53] ~local~0 := 0; [?] havoc main_#res; [?] havoc main_~__retres1~7; [L963] havoc main_~__retres1~7; [L874] ~m_i~0 := 1; [L875] ~t1_i~0 := 1; [L876] ~t2_i~0 := 1; [L877] ~t3_i~0 := 1; [L878] ~t4_i~0 := 1; [L879] ~t5_i~0 := 1; [L968] havoc start_simulation_#t~ret15, start_simulation_#t~ret16, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1; [L904] havoc start_simulation_~kernel_st~0; [L905] havoc start_simulation_~tmp~3; [L906] havoc start_simulation_~tmp___0~1; [L910] start_simulation_~kernel_st~0 := 0; [L404] COND TRUE 1 == ~m_i~0 [L405] ~m_st~0 := 0; [L409] COND TRUE 1 == ~t1_i~0 [L410] ~t1_st~0 := 0; [L414] COND TRUE 1 == ~t2_i~0 [L415] ~t2_st~0 := 0; [L419] COND TRUE 1 == ~t3_i~0 [L420] ~t3_st~0 := 0; [L424] COND TRUE 1 == ~t4_i~0 [L425] ~t4_st~0 := 0; [L429] COND TRUE 1 == ~t5_i~0 [L430] ~t5_st~0 := 0; [L589] COND FALSE !(0 == ~M_E~0) [L594] COND FALSE !(0 == ~T1_E~0) [L599] COND FALSE !(0 == ~T2_E~0) [L604] COND FALSE !(0 == ~T3_E~0) [L609] COND FALSE !(0 == ~T4_E~0) [L614] COND FALSE !(0 == ~T5_E~0) [L619] COND FALSE !(0 == ~E_M~0) [L624] COND FALSE !(0 == ~E_1~0) [L629] COND FALSE !(0 == ~E_2~0) [L634] COND FALSE !(0 == ~E_3~0) [L639] COND FALSE !(0 == ~E_4~0) [L644] COND FALSE !(0 == ~E_5~0) [L914] havoc activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0; [L722] havoc activate_threads_~tmp~1; [L723] havoc activate_threads_~tmp___0~0; [L724] havoc activate_threads_~tmp___1~0; [L725] havoc activate_threads_~tmp___2~0; [L726] havoc activate_threads_~tmp___3~0; [L727] havoc activate_threads_~tmp___4~0; [L731] havoc is_master_triggered_#res; [L731] havoc is_master_triggered_~__retres1~0; [L279] havoc is_master_triggered_~__retres1~0; [L282] COND FALSE !(1 == ~m_pc~0) [L292] is_master_triggered_~__retres1~0 := 0; [L294] is_master_triggered_#res := is_master_triggered_~__retres1~0; [L731] activate_threads_#t~ret8 := is_master_triggered_#res; [L731] activate_threads_~tmp~1 := activate_threads_#t~ret8; [L731] havoc activate_threads_#t~ret8; [L733-L737] COND FALSE !(0 != activate_threads_~tmp~1) [L739] havoc is_transmit1_triggered_#res; [L739] havoc is_transmit1_triggered_~__retres1~1; [L298] havoc is_transmit1_triggered_~__retres1~1; [L301] COND FALSE !(1 == ~t1_pc~0) [L311] is_transmit1_triggered_~__retres1~1 := 0; [L313] is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; [L739] activate_threads_#t~ret9 := is_transmit1_triggered_#res; [L739] activate_threads_~tmp___0~0 := activate_threads_#t~ret9; [L739] havoc activate_threads_#t~ret9; [L741-L745] COND FALSE !(0 != activate_threads_~tmp___0~0) [L747] havoc is_transmit2_triggered_#res; [L747] havoc is_transmit2_triggered_~__retres1~2; [L317] havoc is_transmit2_triggered_~__retres1~2; [L320] COND FALSE !(1 == ~t2_pc~0) [L330] is_transmit2_triggered_~__retres1~2 := 0; [L332] is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; [L747] activate_threads_#t~ret10 := is_transmit2_triggered_#res; [L747] activate_threads_~tmp___1~0 := activate_threads_#t~ret10; [L747] havoc activate_threads_#t~ret10; [L749-L753] COND FALSE !(0 != activate_threads_~tmp___1~0) [L755] havoc is_transmit3_triggered_#res; [L755] havoc is_transmit3_triggered_~__retres1~3; [L336] havoc is_transmit3_triggered_~__retres1~3; [L339] COND FALSE !(1 == ~t3_pc~0) [L349] is_transmit3_triggered_~__retres1~3 := 0; [L351] is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; [L755] activate_threads_#t~ret11 := is_transmit3_triggered_#res; [L755] activate_threads_~tmp___2~0 := activate_threads_#t~ret11; [L755] havoc activate_threads_#t~ret11; [L757-L761] COND FALSE !(0 != activate_threads_~tmp___2~0) [L763] havoc is_transmit4_triggered_#res; [L763] havoc is_transmit4_triggered_~__retres1~4; [L355] havoc is_transmit4_triggered_~__retres1~4; [L358] COND FALSE !(1 == ~t4_pc~0) [L368] is_transmit4_triggered_~__retres1~4 := 0; [L370] is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; [L763] activate_threads_#t~ret12 := is_transmit4_triggered_#res; [L763] activate_threads_~tmp___3~0 := activate_threads_#t~ret12; [L763] havoc activate_threads_#t~ret12; [L765-L769] COND FALSE !(0 != activate_threads_~tmp___3~0) [L771] havoc is_transmit5_triggered_#res; [L771] havoc is_transmit5_triggered_~__retres1~5; [L374] havoc is_transmit5_triggered_~__retres1~5; [L377] COND FALSE !(1 == ~t5_pc~0) [L387] is_transmit5_triggered_~__retres1~5 := 0; [L389] is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; [L771] activate_threads_#t~ret13 := is_transmit5_triggered_#res; [L771] activate_threads_~tmp___4~0 := activate_threads_#t~ret13; [L771] havoc activate_threads_#t~ret13; [L773-L777] COND FALSE !(0 != activate_threads_~tmp___4~0) [L657] COND FALSE !(1 == ~M_E~0) [L662] COND FALSE !(1 == ~T1_E~0) [L667] COND FALSE !(1 == ~T2_E~0) [L672] COND FALSE !(1 == ~T3_E~0) [L677] COND FALSE !(1 == ~T4_E~0) [L682] COND FALSE !(1 == ~T5_E~0) [L687] COND FALSE !(1 == ~E_M~0) [L692] COND FALSE !(1 == ~E_1~0) [L697] COND FALSE !(1 == ~E_2~0) [L702] COND FALSE !(1 == ~E_3~0) [L707] COND FALSE !(1 == ~E_4~0) [L712] COND FALSE !(1 == ~E_5~0) [L918-L955] COND FALSE !(false) [L921] start_simulation_~kernel_st~0 := 1; [L922] havoc eval_#t~ret1, eval_#t~nondet2, eval_~tmp_ndt_1~0, eval_#t~nondet3, eval_~tmp_ndt_2~0, eval_#t~nondet4, eval_~tmp_ndt_3~0, eval_#t~nondet5, eval_~tmp_ndt_4~0, eval_#t~nondet6, eval_~tmp_ndt_5~0, eval_#t~nondet7, eval_~tmp_ndt_6~0, eval_~tmp~0; [L480] havoc eval_~tmp~0; ----- ----- class de.uni_freiburg.informatik.ultimate.boogie.procedureinliner.backtranslation.InlinerBacktranslator [L14] ~m_pc~0 := 0; [L15] ~t1_pc~0 := 0; [L16] ~t2_pc~0 := 0; [L17] ~t3_pc~0 := 0; [L18] ~t4_pc~0 := 0; [L19] ~t5_pc~0 := 0; [L20] ~m_st~0 := 0; [L21] ~t1_st~0 := 0; [L22] ~t2_st~0 := 0; [L23] ~t3_st~0 := 0; [L24] ~t4_st~0 := 0; [L25] ~t5_st~0 := 0; [L26] ~m_i~0 := 0; [L27] ~t1_i~0 := 0; [L28] ~t2_i~0 := 0; [L29] ~t3_i~0 := 0; [L30] ~t4_i~0 := 0; [L31] ~t5_i~0 := 0; [L32] ~M_E~0 := 2; [L33] ~T1_E~0 := 2; [L34] ~T2_E~0 := 2; [L35] ~T3_E~0 := 2; [L36] ~T4_E~0 := 2; [L37] ~T5_E~0 := 2; [L38] ~E_M~0 := 2; [L39] ~E_1~0 := 2; [L40] ~E_2~0 := 2; [L41] ~E_3~0 := 2; [L42] ~E_4~0 := 2; [L43] ~E_5~0 := 2; [L51] ~token~0 := 0; [L53] ~local~0 := 0; [?] havoc main_#res; [?] havoc main_~__retres1~7; [L963] havoc main_~__retres1~7; [L874] ~m_i~0 := 1; [L875] ~t1_i~0 := 1; [L876] ~t2_i~0 := 1; [L877] ~t3_i~0 := 1; [L878] ~t4_i~0 := 1; [L879] ~t5_i~0 := 1; [L968] havoc start_simulation_#t~ret15, start_simulation_#t~ret16, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1; [L904] havoc start_simulation_~kernel_st~0; [L905] havoc start_simulation_~tmp~3; [L906] havoc start_simulation_~tmp___0~1; [L910] start_simulation_~kernel_st~0 := 0; [L404] COND TRUE 1 == ~m_i~0 [L405] ~m_st~0 := 0; [L409] COND TRUE 1 == ~t1_i~0 [L410] ~t1_st~0 := 0; [L414] COND TRUE 1 == ~t2_i~0 [L415] ~t2_st~0 := 0; [L419] COND TRUE 1 == ~t3_i~0 [L420] ~t3_st~0 := 0; [L424] COND TRUE 1 == ~t4_i~0 [L425] ~t4_st~0 := 0; [L429] COND TRUE 1 == ~t5_i~0 [L430] ~t5_st~0 := 0; [L589] COND FALSE !(0 == ~M_E~0) [L594] COND FALSE !(0 == ~T1_E~0) [L599] COND FALSE !(0 == ~T2_E~0) [L604] COND FALSE !(0 == ~T3_E~0) [L609] COND FALSE !(0 == ~T4_E~0) [L614] COND FALSE !(0 == ~T5_E~0) [L619] COND FALSE !(0 == ~E_M~0) [L624] COND FALSE !(0 == ~E_1~0) [L629] COND FALSE !(0 == ~E_2~0) [L634] COND FALSE !(0 == ~E_3~0) [L639] COND FALSE !(0 == ~E_4~0) [L644] COND FALSE !(0 == ~E_5~0) [L914] havoc activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0; [L722] havoc activate_threads_~tmp~1; [L723] havoc activate_threads_~tmp___0~0; [L724] havoc activate_threads_~tmp___1~0; [L725] havoc activate_threads_~tmp___2~0; [L726] havoc activate_threads_~tmp___3~0; [L727] havoc activate_threads_~tmp___4~0; [L731] havoc is_master_triggered_#res; [L731] havoc is_master_triggered_~__retres1~0; [L279] havoc is_master_triggered_~__retres1~0; [L282] COND FALSE !(1 == ~m_pc~0) [L292] is_master_triggered_~__retres1~0 := 0; [L294] is_master_triggered_#res := is_master_triggered_~__retres1~0; [L731] activate_threads_#t~ret8 := is_master_triggered_#res; [L731] activate_threads_~tmp~1 := activate_threads_#t~ret8; [L731] havoc activate_threads_#t~ret8; [L733-L737] COND FALSE !(0 != activate_threads_~tmp~1) [L739] havoc is_transmit1_triggered_#res; [L739] havoc is_transmit1_triggered_~__retres1~1; [L298] havoc is_transmit1_triggered_~__retres1~1; [L301] COND FALSE !(1 == ~t1_pc~0) [L311] is_transmit1_triggered_~__retres1~1 := 0; [L313] is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; [L739] activate_threads_#t~ret9 := is_transmit1_triggered_#res; [L739] activate_threads_~tmp___0~0 := activate_threads_#t~ret9; [L739] havoc activate_threads_#t~ret9; [L741-L745] COND FALSE !(0 != activate_threads_~tmp___0~0) [L747] havoc is_transmit2_triggered_#res; [L747] havoc is_transmit2_triggered_~__retres1~2; [L317] havoc is_transmit2_triggered_~__retres1~2; [L320] COND FALSE !(1 == ~t2_pc~0) [L330] is_transmit2_triggered_~__retres1~2 := 0; [L332] is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; [L747] activate_threads_#t~ret10 := is_transmit2_triggered_#res; [L747] activate_threads_~tmp___1~0 := activate_threads_#t~ret10; [L747] havoc activate_threads_#t~ret10; [L749-L753] COND FALSE !(0 != activate_threads_~tmp___1~0) [L755] havoc is_transmit3_triggered_#res; [L755] havoc is_transmit3_triggered_~__retres1~3; [L336] havoc is_transmit3_triggered_~__retres1~3; [L339] COND FALSE !(1 == ~t3_pc~0) [L349] is_transmit3_triggered_~__retres1~3 := 0; [L351] is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; [L755] activate_threads_#t~ret11 := is_transmit3_triggered_#res; [L755] activate_threads_~tmp___2~0 := activate_threads_#t~ret11; [L755] havoc activate_threads_#t~ret11; [L757-L761] COND FALSE !(0 != activate_threads_~tmp___2~0) [L763] havoc is_transmit4_triggered_#res; [L763] havoc is_transmit4_triggered_~__retres1~4; [L355] havoc is_transmit4_triggered_~__retres1~4; [L358] COND FALSE !(1 == ~t4_pc~0) [L368] is_transmit4_triggered_~__retres1~4 := 0; [L370] is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; [L763] activate_threads_#t~ret12 := is_transmit4_triggered_#res; [L763] activate_threads_~tmp___3~0 := activate_threads_#t~ret12; [L763] havoc activate_threads_#t~ret12; [L765-L769] COND FALSE !(0 != activate_threads_~tmp___3~0) [L771] havoc is_transmit5_triggered_#res; [L771] havoc is_transmit5_triggered_~__retres1~5; [L374] havoc is_transmit5_triggered_~__retres1~5; [L377] COND FALSE !(1 == ~t5_pc~0) [L387] is_transmit5_triggered_~__retres1~5 := 0; [L389] is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; [L771] activate_threads_#t~ret13 := is_transmit5_triggered_#res; [L771] activate_threads_~tmp___4~0 := activate_threads_#t~ret13; [L771] havoc activate_threads_#t~ret13; [L773-L777] COND FALSE !(0 != activate_threads_~tmp___4~0) [L657] COND FALSE !(1 == ~M_E~0) [L662] COND FALSE !(1 == ~T1_E~0) [L667] COND FALSE !(1 == ~T2_E~0) [L672] COND FALSE !(1 == ~T3_E~0) [L677] COND FALSE !(1 == ~T4_E~0) [L682] COND FALSE !(1 == ~T5_E~0) [L687] COND FALSE !(1 == ~E_M~0) [L692] COND FALSE !(1 == ~E_1~0) [L697] COND FALSE !(1 == ~E_2~0) [L702] COND FALSE !(1 == ~E_3~0) [L707] COND FALSE !(1 == ~E_4~0) [L712] COND FALSE !(1 == ~E_5~0) [L918-L955] COND FALSE !(false) [L921] start_simulation_~kernel_st~0 := 1; [L922] havoc eval_#t~ret1, eval_#t~nondet2, eval_~tmp_ndt_1~0, eval_#t~nondet3, eval_~tmp_ndt_2~0, eval_#t~nondet4, eval_~tmp_ndt_3~0, eval_#t~nondet5, eval_~tmp_ndt_4~0, eval_#t~nondet6, eval_~tmp_ndt_5~0, eval_#t~nondet7, eval_~tmp_ndt_6~0, eval_~tmp~0; [L480] havoc eval_~tmp~0; [L14] ~m_pc~0 := 0; [L15] ~t1_pc~0 := 0; [L16] ~t2_pc~0 := 0; [L17] ~t3_pc~0 := 0; [L18] ~t4_pc~0 := 0; [L19] ~t5_pc~0 := 0; [L20] ~m_st~0 := 0; [L21] ~t1_st~0 := 0; [L22] ~t2_st~0 := 0; [L23] ~t3_st~0 := 0; [L24] ~t4_st~0 := 0; [L25] ~t5_st~0 := 0; [L26] ~m_i~0 := 0; [L27] ~t1_i~0 := 0; [L28] ~t2_i~0 := 0; [L29] ~t3_i~0 := 0; [L30] ~t4_i~0 := 0; [L31] ~t5_i~0 := 0; [L32] ~M_E~0 := 2; [L33] ~T1_E~0 := 2; [L34] ~T2_E~0 := 2; [L35] ~T3_E~0 := 2; [L36] ~T4_E~0 := 2; [L37] ~T5_E~0 := 2; [L38] ~E_M~0 := 2; [L39] ~E_1~0 := 2; [L40] ~E_2~0 := 2; [L41] ~E_3~0 := 2; [L42] ~E_4~0 := 2; [L43] ~E_5~0 := 2; [L51] ~token~0 := 0; [L53] ~local~0 := 0; [L963] havoc ~__retres1~7; [L874] ~m_i~0 := 1; [L875] ~t1_i~0 := 1; [L876] ~t2_i~0 := 1; [L877] ~t3_i~0 := 1; [L878] ~t4_i~0 := 1; [L879] ~t5_i~0 := 1; [L904] havoc ~kernel_st~0; [L905] havoc ~tmp~3; [L906] havoc ~tmp___0~1; [L910] ~kernel_st~0 := 0; [L404] COND TRUE 1 == ~m_i~0 [L405] ~m_st~0 := 0; [L409] COND TRUE 1 == ~t1_i~0 [L410] ~t1_st~0 := 0; [L414] COND TRUE 1 == ~t2_i~0 [L415] ~t2_st~0 := 0; [L419] COND TRUE 1 == ~t3_i~0 [L420] ~t3_st~0 := 0; [L424] COND TRUE 1 == ~t4_i~0 [L425] ~t4_st~0 := 0; [L429] COND TRUE 1 == ~t5_i~0 [L430] ~t5_st~0 := 0; [L589] COND FALSE !(0 == ~M_E~0) [L594] COND FALSE !(0 == ~T1_E~0) [L599] COND FALSE !(0 == ~T2_E~0) [L604] COND FALSE !(0 == ~T3_E~0) [L609] COND FALSE !(0 == ~T4_E~0) [L614] COND FALSE !(0 == ~T5_E~0) [L619] COND FALSE !(0 == ~E_M~0) [L624] COND FALSE !(0 == ~E_1~0) [L629] COND FALSE !(0 == ~E_2~0) [L634] COND FALSE !(0 == ~E_3~0) [L639] COND FALSE !(0 == ~E_4~0) [L644] COND FALSE !(0 == ~E_5~0) [L722] havoc ~tmp~1; [L723] havoc ~tmp___0~0; [L724] havoc ~tmp___1~0; [L725] havoc ~tmp___2~0; [L726] havoc ~tmp___3~0; [L727] havoc ~tmp___4~0; [L279] havoc ~__retres1~0; [L282] COND FALSE !(1 == ~m_pc~0) [L292] ~__retres1~0 := 0; [L294] #res := ~__retres1~0; [L731] ~tmp~1 := #t~ret8; [L731] havoc #t~ret8; [L733-L737] COND FALSE !(0 != ~tmp~1) [L298] havoc ~__retres1~1; [L301] COND FALSE !(1 == ~t1_pc~0) [L311] ~__retres1~1 := 0; [L313] #res := ~__retres1~1; [L739] ~tmp___0~0 := #t~ret9; [L739] havoc #t~ret9; [L741-L745] COND FALSE !(0 != ~tmp___0~0) [L317] havoc ~__retres1~2; [L320] COND FALSE !(1 == ~t2_pc~0) [L330] ~__retres1~2 := 0; [L332] #res := ~__retres1~2; [L747] ~tmp___1~0 := #t~ret10; [L747] havoc #t~ret10; [L749-L753] COND FALSE !(0 != ~tmp___1~0) [L336] havoc ~__retres1~3; [L339] COND FALSE !(1 == ~t3_pc~0) [L349] ~__retres1~3 := 0; [L351] #res := ~__retres1~3; [L755] ~tmp___2~0 := #t~ret11; [L755] havoc #t~ret11; [L757-L761] COND FALSE !(0 != ~tmp___2~0) [L355] havoc ~__retres1~4; [L358] COND FALSE !(1 == ~t4_pc~0) [L368] ~__retres1~4 := 0; [L370] #res := ~__retres1~4; [L763] ~tmp___3~0 := #t~ret12; [L763] havoc #t~ret12; [L765-L769] COND FALSE !(0 != ~tmp___3~0) [L374] havoc ~__retres1~5; [L377] COND FALSE !(1 == ~t5_pc~0) [L387] ~__retres1~5 := 0; [L389] #res := ~__retres1~5; [L771] ~tmp___4~0 := #t~ret13; [L771] havoc #t~ret13; [L773-L777] COND FALSE !(0 != ~tmp___4~0) [L657] COND FALSE !(1 == ~M_E~0) [L662] COND FALSE !(1 == ~T1_E~0) [L667] COND FALSE !(1 == ~T2_E~0) [L672] COND FALSE !(1 == ~T3_E~0) [L677] COND FALSE !(1 == ~T4_E~0) [L682] COND FALSE !(1 == ~T5_E~0) [L687] COND FALSE !(1 == ~E_M~0) [L692] COND FALSE !(1 == ~E_1~0) [L697] COND FALSE !(1 == ~E_2~0) [L702] COND FALSE !(1 == ~E_3~0) [L707] COND FALSE !(1 == ~E_4~0) [L712] COND FALSE !(1 == ~E_5~0) [L918-L955] COND FALSE !(false) [L921] ~kernel_st~0 := 1; [L480] havoc ~tmp~0; ----- ----- class de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.CACSL2BoogieBacktranslator [L14] ~m_pc~0 := 0; [L15] ~t1_pc~0 := 0; [L16] ~t2_pc~0 := 0; [L17] ~t3_pc~0 := 0; [L18] ~t4_pc~0 := 0; [L19] ~t5_pc~0 := 0; [L20] ~m_st~0 := 0; [L21] ~t1_st~0 := 0; [L22] ~t2_st~0 := 0; [L23] ~t3_st~0 := 0; [L24] ~t4_st~0 := 0; [L25] ~t5_st~0 := 0; [L26] ~m_i~0 := 0; [L27] ~t1_i~0 := 0; [L28] ~t2_i~0 := 0; [L29] ~t3_i~0 := 0; [L30] ~t4_i~0 := 0; [L31] ~t5_i~0 := 0; [L32] ~M_E~0 := 2; [L33] ~T1_E~0 := 2; [L34] ~T2_E~0 := 2; [L35] ~T3_E~0 := 2; [L36] ~T4_E~0 := 2; [L37] ~T5_E~0 := 2; [L38] ~E_M~0 := 2; [L39] ~E_1~0 := 2; [L40] ~E_2~0 := 2; [L41] ~E_3~0 := 2; [L42] ~E_4~0 := 2; [L43] ~E_5~0 := 2; [L51] ~token~0 := 0; [L53] ~local~0 := 0; [L963] havoc ~__retres1~7; [L874] ~m_i~0 := 1; [L875] ~t1_i~0 := 1; [L876] ~t2_i~0 := 1; [L877] ~t3_i~0 := 1; [L878] ~t4_i~0 := 1; [L879] ~t5_i~0 := 1; [L904] havoc ~kernel_st~0; [L905] havoc ~tmp~3; [L906] havoc ~tmp___0~1; [L910] ~kernel_st~0 := 0; [L404] COND TRUE 1 == ~m_i~0 [L405] ~m_st~0 := 0; [L409] COND TRUE 1 == ~t1_i~0 [L410] ~t1_st~0 := 0; [L414] COND TRUE 1 == ~t2_i~0 [L415] ~t2_st~0 := 0; [L419] COND TRUE 1 == ~t3_i~0 [L420] ~t3_st~0 := 0; [L424] COND TRUE 1 == ~t4_i~0 [L425] ~t4_st~0 := 0; [L429] COND TRUE 1 == ~t5_i~0 [L430] ~t5_st~0 := 0; [L589] COND FALSE !(0 == ~M_E~0) [L594] COND FALSE !(0 == ~T1_E~0) [L599] COND FALSE !(0 == ~T2_E~0) [L604] COND FALSE !(0 == ~T3_E~0) [L609] COND FALSE !(0 == ~T4_E~0) [L614] COND FALSE !(0 == ~T5_E~0) [L619] COND FALSE !(0 == ~E_M~0) [L624] COND FALSE !(0 == ~E_1~0) [L629] COND FALSE !(0 == ~E_2~0) [L634] COND FALSE !(0 == ~E_3~0) [L639] COND FALSE !(0 == ~E_4~0) [L644] COND FALSE !(0 == ~E_5~0) [L722] havoc ~tmp~1; [L723] havoc ~tmp___0~0; [L724] havoc ~tmp___1~0; [L725] havoc ~tmp___2~0; [L726] havoc ~tmp___3~0; [L727] havoc ~tmp___4~0; [L279] havoc ~__retres1~0; [L282] COND FALSE !(1 == ~m_pc~0) [L292] ~__retres1~0 := 0; [L294] #res := ~__retres1~0; [L731] ~tmp~1 := #t~ret8; [L731] havoc #t~ret8; [L733-L737] COND FALSE !(0 != ~tmp~1) [L298] havoc ~__retres1~1; [L301] COND FALSE !(1 == ~t1_pc~0) [L311] ~__retres1~1 := 0; [L313] #res := ~__retres1~1; [L739] ~tmp___0~0 := #t~ret9; [L739] havoc #t~ret9; [L741-L745] COND FALSE !(0 != ~tmp___0~0) [L317] havoc ~__retres1~2; [L320] COND FALSE !(1 == ~t2_pc~0) [L330] ~__retres1~2 := 0; [L332] #res := ~__retres1~2; [L747] ~tmp___1~0 := #t~ret10; [L747] havoc #t~ret10; [L749-L753] COND FALSE !(0 != ~tmp___1~0) [L336] havoc ~__retres1~3; [L339] COND FALSE !(1 == ~t3_pc~0) [L349] ~__retres1~3 := 0; [L351] #res := ~__retres1~3; [L755] ~tmp___2~0 := #t~ret11; [L755] havoc #t~ret11; [L757-L761] COND FALSE !(0 != ~tmp___2~0) [L355] havoc ~__retres1~4; [L358] COND FALSE !(1 == ~t4_pc~0) [L368] ~__retres1~4 := 0; [L370] #res := ~__retres1~4; [L763] ~tmp___3~0 := #t~ret12; [L763] havoc #t~ret12; [L765-L769] COND FALSE !(0 != ~tmp___3~0) [L374] havoc ~__retres1~5; [L377] COND FALSE !(1 == ~t5_pc~0) [L387] ~__retres1~5 := 0; [L389] #res := ~__retres1~5; [L771] ~tmp___4~0 := #t~ret13; [L771] havoc #t~ret13; [L773-L777] COND FALSE !(0 != ~tmp___4~0) [L657] COND FALSE !(1 == ~M_E~0) [L662] COND FALSE !(1 == ~T1_E~0) [L667] COND FALSE !(1 == ~T2_E~0) [L672] COND FALSE !(1 == ~T3_E~0) [L677] COND FALSE !(1 == ~T4_E~0) [L682] COND FALSE !(1 == ~T5_E~0) [L687] COND FALSE !(1 == ~E_M~0) [L692] COND FALSE !(1 == ~E_1~0) [L697] COND FALSE !(1 == ~E_2~0) [L702] COND FALSE !(1 == ~E_3~0) [L707] COND FALSE !(1 == ~E_4~0) [L712] COND FALSE !(1 == ~E_5~0) [L918-L955] COND FALSE !(false) [L921] ~kernel_st~0 := 1; [L480] havoc ~tmp~0; [L14] int m_pc = 0; [L15] int t1_pc = 0; [L16] int t2_pc = 0; [L17] int t3_pc = 0; [L18] int t4_pc = 0; [L19] int t5_pc = 0; [L20] int m_st ; [L21] int t1_st ; [L22] int t2_st ; [L23] int t3_st ; [L24] int t4_st ; [L25] int t5_st ; [L26] int m_i ; [L27] int t1_i ; [L28] int t2_i ; [L29] int t3_i ; [L30] int t4_i ; [L31] int t5_i ; [L32] int M_E = 2; [L33] int T1_E = 2; [L34] int T2_E = 2; [L35] int T3_E = 2; [L36] int T4_E = 2; [L37] int T5_E = 2; [L38] int E_M = 2; [L39] int E_1 = 2; [L40] int E_2 = 2; [L41] int E_3 = 2; [L42] int E_4 = 2; [L43] int E_5 = 2; [L51] int token ; [L53] int local ; [L963] int __retres1 ; [L874] m_i = 1 [L875] t1_i = 1 [L876] t2_i = 1 [L877] t3_i = 1 [L878] t4_i = 1 [L879] t5_i = 1 [L904] int kernel_st ; [L905] int tmp ; [L906] int tmp___0 ; [L910] kernel_st = 0 [L404] COND TRUE m_i == 1 [L405] m_st = 0 [L409] COND TRUE t1_i == 1 [L410] t1_st = 0 [L414] COND TRUE t2_i == 1 [L415] t2_st = 0 [L419] COND TRUE t3_i == 1 [L420] t3_st = 0 [L424] COND TRUE t4_i == 1 [L425] t4_st = 0 [L429] COND TRUE t5_i == 1 [L430] t5_st = 0 [L589] COND FALSE !(M_E == 0) [L594] COND FALSE !(T1_E == 0) [L599] COND FALSE !(T2_E == 0) [L604] COND FALSE !(T3_E == 0) [L609] COND FALSE !(T4_E == 0) [L614] COND FALSE !(T5_E == 0) [L619] COND FALSE !(E_M == 0) [L624] COND FALSE !(E_1 == 0) [L629] COND FALSE !(E_2 == 0) [L634] COND FALSE !(E_3 == 0) [L639] COND FALSE !(E_4 == 0) [L644] COND FALSE !(E_5 == 0) [L722] int tmp ; [L723] int tmp___0 ; [L724] int tmp___1 ; [L725] int tmp___2 ; [L726] int tmp___3 ; [L727] int tmp___4 ; [L279] int __retres1 ; [L282] COND FALSE !(m_pc == 1) [L292] __retres1 = 0 [L294] return (__retres1); [L731] tmp = is_master_triggered() [L733] COND FALSE !(\read(tmp)) [L298] int __retres1 ; [L301] COND FALSE !(t1_pc == 1) [L311] __retres1 = 0 [L313] return (__retres1); [L739] tmp___0 = is_transmit1_triggered() [L741] COND FALSE !(\read(tmp___0)) [L317] int __retres1 ; [L320] COND FALSE !(t2_pc == 1) [L330] __retres1 = 0 [L332] return (__retres1); [L747] tmp___1 = is_transmit2_triggered() [L749] COND FALSE !(\read(tmp___1)) [L336] int __retres1 ; [L339] COND FALSE !(t3_pc == 1) [L349] __retres1 = 0 [L351] return (__retres1); [L755] tmp___2 = is_transmit3_triggered() [L757] COND FALSE !(\read(tmp___2)) [L355] int __retres1 ; [L358] COND FALSE !(t4_pc == 1) [L368] __retres1 = 0 [L370] return (__retres1); [L763] tmp___3 = is_transmit4_triggered() [L765] COND FALSE !(\read(tmp___3)) [L374] int __retres1 ; [L377] COND FALSE !(t5_pc == 1) [L387] __retres1 = 0 [L389] return (__retres1); [L771] tmp___4 = is_transmit5_triggered() [L773] COND FALSE !(\read(tmp___4)) [L657] COND FALSE !(M_E == 1) [L662] COND FALSE !(T1_E == 1) [L667] COND FALSE !(T2_E == 1) [L672] COND FALSE !(T3_E == 1) [L677] COND FALSE !(T4_E == 1) [L682] COND FALSE !(T5_E == 1) [L687] COND FALSE !(E_M == 1) [L692] COND FALSE !(E_1 == 1) [L697] COND FALSE !(E_2 == 1) [L702] COND FALSE !(E_3 == 1) [L707] COND FALSE !(E_4 == 1) [L712] COND FALSE !(E_5 == 1) [L918] COND TRUE 1 [L921] kernel_st = 1 [L480] int tmp ; ----- ----- class de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder.RCFGBacktranslator [?] assume !false; [?] havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; [?] assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; [?] exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; [?] eval_#t~ret1 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret1;havoc eval_#t~ret1; [?] assume 0 != eval_~tmp~0; [?] assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0;eval_~tmp_ndt_1~0 := eval_#t~nondet2;havoc eval_#t~nondet2; [?] assume !(0 != eval_~tmp_ndt_1~0); [?] assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0;eval_~tmp_ndt_2~0 := eval_#t~nondet3;havoc eval_#t~nondet3; [?] assume !(0 != eval_~tmp_ndt_2~0); [?] assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0;eval_~tmp_ndt_3~0 := eval_#t~nondet4;havoc eval_#t~nondet4; [?] assume !(0 != eval_~tmp_ndt_3~0); [?] assume 0 == ~t3_st~0;havoc eval_~tmp_ndt_4~0;eval_~tmp_ndt_4~0 := eval_#t~nondet5;havoc eval_#t~nondet5; [?] assume !(0 != eval_~tmp_ndt_4~0); [?] assume 0 == ~t4_st~0;havoc eval_~tmp_ndt_5~0;eval_~tmp_ndt_5~0 := eval_#t~nondet6;havoc eval_#t~nondet6; [?] assume !(0 != eval_~tmp_ndt_5~0); [?] assume 0 == ~t5_st~0;havoc eval_~tmp_ndt_6~0;eval_~tmp_ndt_6~0 := eval_#t~nondet7;havoc eval_#t~nondet7; [?] assume !(0 != eval_~tmp_ndt_6~0); [L484-L578] assume !false; [L487] havoc exists_runnable_thread_#res; [L487] havoc exists_runnable_thread_~__retres1~6; [L439] havoc exists_runnable_thread_~__retres1~6; [L442-L472] assume 0 == ~m_st~0; [L443] exists_runnable_thread_~__retres1~6 := 1; [L475] exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; [L487] eval_#t~ret1 := exists_runnable_thread_#res; [L487] eval_~tmp~0 := eval_#t~ret1; [L487] havoc eval_#t~ret1; [L489-L493] assume 0 != eval_~tmp~0; [L494-L507] assume 0 == ~m_st~0; [L495] havoc eval_~tmp_ndt_1~0; [L496] eval_~tmp_ndt_1~0 := eval_#t~nondet2; [L496] havoc eval_#t~nondet2; [L497-L504] assume !(0 != eval_~tmp_ndt_1~0); [L508-L521] assume 0 == ~t1_st~0; [L509] havoc eval_~tmp_ndt_2~0; [L510] eval_~tmp_ndt_2~0 := eval_#t~nondet3; [L510] havoc eval_#t~nondet3; [L511-L518] assume !(0 != eval_~tmp_ndt_2~0); [L522-L535] assume 0 == ~t2_st~0; [L523] havoc eval_~tmp_ndt_3~0; [L524] eval_~tmp_ndt_3~0 := eval_#t~nondet4; [L524] havoc eval_#t~nondet4; [L525-L532] assume !(0 != eval_~tmp_ndt_3~0); [L536-L549] assume 0 == ~t3_st~0; [L537] havoc eval_~tmp_ndt_4~0; [L538] eval_~tmp_ndt_4~0 := eval_#t~nondet5; [L538] havoc eval_#t~nondet5; [L539-L546] assume !(0 != eval_~tmp_ndt_4~0); [L550-L563] assume 0 == ~t4_st~0; [L551] havoc eval_~tmp_ndt_5~0; [L552] eval_~tmp_ndt_5~0 := eval_#t~nondet6; [L552] havoc eval_#t~nondet6; [L553-L560] assume !(0 != eval_~tmp_ndt_5~0); [L564-L577] assume 0 == ~t5_st~0; [L565] havoc eval_~tmp_ndt_6~0; [L566] eval_~tmp_ndt_6~0 := eval_#t~nondet7; [L566] havoc eval_#t~nondet7; [L567-L574] assume !(0 != eval_~tmp_ndt_6~0); ----- ----- class de.uni_freiburg.informatik.ultimate.boogie.preprocessor.BoogiePreprocessorBacktranslator [L484-L578] assume !false; [L487] havoc exists_runnable_thread_#res; [L487] havoc exists_runnable_thread_~__retres1~6; [L439] havoc exists_runnable_thread_~__retres1~6; [L442-L472] assume 0 == ~m_st~0; [L443] exists_runnable_thread_~__retres1~6 := 1; [L475] exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; [L487] eval_#t~ret1 := exists_runnable_thread_#res; [L487] eval_~tmp~0 := eval_#t~ret1; [L487] havoc eval_#t~ret1; [L489-L493] assume 0 != eval_~tmp~0; [L494-L507] assume 0 == ~m_st~0; [L495] havoc eval_~tmp_ndt_1~0; [L496] eval_~tmp_ndt_1~0 := eval_#t~nondet2; [L496] havoc eval_#t~nondet2; [L497-L504] assume !(0 != eval_~tmp_ndt_1~0); [L508-L521] assume 0 == ~t1_st~0; [L509] havoc eval_~tmp_ndt_2~0; [L510] eval_~tmp_ndt_2~0 := eval_#t~nondet3; [L510] havoc eval_#t~nondet3; [L511-L518] assume !(0 != eval_~tmp_ndt_2~0); [L522-L535] assume 0 == ~t2_st~0; [L523] havoc eval_~tmp_ndt_3~0; [L524] eval_~tmp_ndt_3~0 := eval_#t~nondet4; [L524] havoc eval_#t~nondet4; [L525-L532] assume !(0 != eval_~tmp_ndt_3~0); [L536-L549] assume 0 == ~t3_st~0; [L537] havoc eval_~tmp_ndt_4~0; [L538] eval_~tmp_ndt_4~0 := eval_#t~nondet5; [L538] havoc eval_#t~nondet5; [L539-L546] assume !(0 != eval_~tmp_ndt_4~0); [L550-L563] assume 0 == ~t4_st~0; [L551] havoc eval_~tmp_ndt_5~0; [L552] eval_~tmp_ndt_5~0 := eval_#t~nondet6; [L552] havoc eval_#t~nondet6; [L553-L560] assume !(0 != eval_~tmp_ndt_5~0); [L564-L577] assume 0 == ~t5_st~0; [L565] havoc eval_~tmp_ndt_6~0; [L566] eval_~tmp_ndt_6~0 := eval_#t~nondet7; [L566] havoc eval_#t~nondet7; [L567-L574] assume !(0 != eval_~tmp_ndt_6~0); [L484-L578] COND FALSE !(false) [L487] havoc exists_runnable_thread_#res; [L487] havoc exists_runnable_thread_~__retres1~6; [L439] havoc exists_runnable_thread_~__retres1~6; [L442] COND TRUE 0 == ~m_st~0 [L443] exists_runnable_thread_~__retres1~6 := 1; [L475] exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; [L487] eval_#t~ret1 := exists_runnable_thread_#res; [L487] eval_~tmp~0 := eval_#t~ret1; [L487] havoc eval_#t~ret1; [L489-L493] COND TRUE 0 != eval_~tmp~0 [L494] COND TRUE 0 == ~m_st~0 [L495] havoc eval_~tmp_ndt_1~0; [L496] eval_~tmp_ndt_1~0 := eval_#t~nondet2; [L496] havoc eval_#t~nondet2; [L497-L504] COND FALSE !(0 != eval_~tmp_ndt_1~0) [L508] COND TRUE 0 == ~t1_st~0 [L509] havoc eval_~tmp_ndt_2~0; [L510] eval_~tmp_ndt_2~0 := eval_#t~nondet3; [L510] havoc eval_#t~nondet3; [L511-L518] COND FALSE !(0 != eval_~tmp_ndt_2~0) [L522] COND TRUE 0 == ~t2_st~0 [L523] havoc eval_~tmp_ndt_3~0; [L524] eval_~tmp_ndt_3~0 := eval_#t~nondet4; [L524] havoc eval_#t~nondet4; [L525-L532] COND FALSE !(0 != eval_~tmp_ndt_3~0) [L536] COND TRUE 0 == ~t3_st~0 [L537] havoc eval_~tmp_ndt_4~0; [L538] eval_~tmp_ndt_4~0 := eval_#t~nondet5; [L538] havoc eval_#t~nondet5; [L539-L546] COND FALSE !(0 != eval_~tmp_ndt_4~0) [L550] COND TRUE 0 == ~t4_st~0 [L551] havoc eval_~tmp_ndt_5~0; [L552] eval_~tmp_ndt_5~0 := eval_#t~nondet6; [L552] havoc eval_#t~nondet6; [L553-L560] COND FALSE !(0 != eval_~tmp_ndt_5~0) [L564] COND TRUE 0 == ~t5_st~0 [L565] havoc eval_~tmp_ndt_6~0; [L566] eval_~tmp_ndt_6~0 := eval_#t~nondet7; [L566] havoc eval_#t~nondet7; [L567-L574] COND FALSE !(0 != eval_~tmp_ndt_6~0) ----- ----- class de.uni_freiburg.informatik.ultimate.boogie.procedureinliner.backtranslation.InlinerBacktranslator [L484-L578] COND FALSE !(false) [L487] havoc exists_runnable_thread_#res; [L487] havoc exists_runnable_thread_~__retres1~6; [L439] havoc exists_runnable_thread_~__retres1~6; [L442] COND TRUE 0 == ~m_st~0 [L443] exists_runnable_thread_~__retres1~6 := 1; [L475] exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; [L487] eval_#t~ret1 := exists_runnable_thread_#res; [L487] eval_~tmp~0 := eval_#t~ret1; [L487] havoc eval_#t~ret1; [L489-L493] COND TRUE 0 != eval_~tmp~0 [L494] COND TRUE 0 == ~m_st~0 [L495] havoc eval_~tmp_ndt_1~0; [L496] eval_~tmp_ndt_1~0 := eval_#t~nondet2; [L496] havoc eval_#t~nondet2; [L497-L504] COND FALSE !(0 != eval_~tmp_ndt_1~0) [L508] COND TRUE 0 == ~t1_st~0 [L509] havoc eval_~tmp_ndt_2~0; [L510] eval_~tmp_ndt_2~0 := eval_#t~nondet3; [L510] havoc eval_#t~nondet3; [L511-L518] COND FALSE !(0 != eval_~tmp_ndt_2~0) [L522] COND TRUE 0 == ~t2_st~0 [L523] havoc eval_~tmp_ndt_3~0; [L524] eval_~tmp_ndt_3~0 := eval_#t~nondet4; [L524] havoc eval_#t~nondet4; [L525-L532] COND FALSE !(0 != eval_~tmp_ndt_3~0) [L536] COND TRUE 0 == ~t3_st~0 [L537] havoc eval_~tmp_ndt_4~0; [L538] eval_~tmp_ndt_4~0 := eval_#t~nondet5; [L538] havoc eval_#t~nondet5; [L539-L546] COND FALSE !(0 != eval_~tmp_ndt_4~0) [L550] COND TRUE 0 == ~t4_st~0 [L551] havoc eval_~tmp_ndt_5~0; [L552] eval_~tmp_ndt_5~0 := eval_#t~nondet6; [L552] havoc eval_#t~nondet6; [L553-L560] COND FALSE !(0 != eval_~tmp_ndt_5~0) [L564] COND TRUE 0 == ~t5_st~0 [L565] havoc eval_~tmp_ndt_6~0; [L566] eval_~tmp_ndt_6~0 := eval_#t~nondet7; [L566] havoc eval_#t~nondet7; [L567-L574] COND FALSE !(0 != eval_~tmp_ndt_6~0) [L484-L578] COND FALSE !(false) [L439] havoc ~__retres1~6; [L442] COND TRUE 0 == ~m_st~0 [L443] ~__retres1~6 := 1; [L475] #res := ~__retres1~6; [L487] ~tmp~0 := #t~ret1; [L487] havoc #t~ret1; [L489-L493] COND TRUE 0 != ~tmp~0 [L494] COND TRUE 0 == ~m_st~0 [L495] havoc ~tmp_ndt_1~0; [L496] ~tmp_ndt_1~0 := #t~nondet2; [L496] havoc #t~nondet2; [L497-L504] COND FALSE !(0 != ~tmp_ndt_1~0) [L508] COND TRUE 0 == ~t1_st~0 [L509] havoc ~tmp_ndt_2~0; [L510] ~tmp_ndt_2~0 := #t~nondet3; [L510] havoc #t~nondet3; [L511-L518] COND FALSE !(0 != ~tmp_ndt_2~0) [L522] COND TRUE 0 == ~t2_st~0 [L523] havoc ~tmp_ndt_3~0; [L524] ~tmp_ndt_3~0 := #t~nondet4; [L524] havoc #t~nondet4; [L525-L532] COND FALSE !(0 != ~tmp_ndt_3~0) [L536] COND TRUE 0 == ~t3_st~0 [L537] havoc ~tmp_ndt_4~0; [L538] ~tmp_ndt_4~0 := #t~nondet5; [L538] havoc #t~nondet5; [L539-L546] COND FALSE !(0 != ~tmp_ndt_4~0) [L550] COND TRUE 0 == ~t4_st~0 [L551] havoc ~tmp_ndt_5~0; [L552] ~tmp_ndt_5~0 := #t~nondet6; [L552] havoc #t~nondet6; [L553-L560] COND FALSE !(0 != ~tmp_ndt_5~0) [L564] COND TRUE 0 == ~t5_st~0 [L565] havoc ~tmp_ndt_6~0; [L566] ~tmp_ndt_6~0 := #t~nondet7; [L566] havoc #t~nondet7; [L567-L574] COND FALSE !(0 != ~tmp_ndt_6~0) ----- ----- class de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.CACSL2BoogieBacktranslator [L484-L578] COND FALSE !(false) [L439] havoc ~__retres1~6; [L442] COND TRUE 0 == ~m_st~0 [L443] ~__retres1~6 := 1; [L475] #res := ~__retres1~6; [L487] ~tmp~0 := #t~ret1; [L487] havoc #t~ret1; [L489-L493] COND TRUE 0 != ~tmp~0 [L494] COND TRUE 0 == ~m_st~0 [L495] havoc ~tmp_ndt_1~0; [L496] ~tmp_ndt_1~0 := #t~nondet2; [L496] havoc #t~nondet2; [L497-L504] COND FALSE !(0 != ~tmp_ndt_1~0) [L508] COND TRUE 0 == ~t1_st~0 [L509] havoc ~tmp_ndt_2~0; [L510] ~tmp_ndt_2~0 := #t~nondet3; [L510] havoc #t~nondet3; [L511-L518] COND FALSE !(0 != ~tmp_ndt_2~0) [L522] COND TRUE 0 == ~t2_st~0 [L523] havoc ~tmp_ndt_3~0; [L524] ~tmp_ndt_3~0 := #t~nondet4; [L524] havoc #t~nondet4; [L525-L532] COND FALSE !(0 != ~tmp_ndt_3~0) [L536] COND TRUE 0 == ~t3_st~0 [L537] havoc ~tmp_ndt_4~0; [L538] ~tmp_ndt_4~0 := #t~nondet5; [L538] havoc #t~nondet5; [L539-L546] COND FALSE !(0 != ~tmp_ndt_4~0) [L550] COND TRUE 0 == ~t4_st~0 [L551] havoc ~tmp_ndt_5~0; [L552] ~tmp_ndt_5~0 := #t~nondet6; [L552] havoc #t~nondet6; [L553-L560] COND FALSE !(0 != ~tmp_ndt_5~0) [L564] COND TRUE 0 == ~t5_st~0 [L565] havoc ~tmp_ndt_6~0; [L566] ~tmp_ndt_6~0 := #t~nondet7; [L566] havoc #t~nondet7; [L567-L574] COND FALSE !(0 != ~tmp_ndt_6~0) [L484] COND TRUE 1 [L439] int __retres1 ; [L442] COND TRUE m_st == 0 [L443] __retres1 = 1 [L475] return (__retres1); [L487] tmp = exists_runnable_thread() [L489] COND TRUE \read(tmp) [L494] COND TRUE m_st == 0 [L495] int tmp_ndt_1; [L496] tmp_ndt_1 = __VERIFIER_nondet_int() [L497] COND FALSE !(\read(tmp_ndt_1)) [L508] COND TRUE t1_st == 0 [L509] int tmp_ndt_2; [L510] tmp_ndt_2 = __VERIFIER_nondet_int() [L511] COND FALSE !(\read(tmp_ndt_2)) [L522] COND TRUE t2_st == 0 [L523] int tmp_ndt_3; [L524] tmp_ndt_3 = __VERIFIER_nondet_int() [L525] COND FALSE !(\read(tmp_ndt_3)) [L536] COND TRUE t3_st == 0 [L537] int tmp_ndt_4; [L538] tmp_ndt_4 = __VERIFIER_nondet_int() [L539] COND FALSE !(\read(tmp_ndt_4)) [L550] COND TRUE t4_st == 0 [L551] int tmp_ndt_5; [L552] tmp_ndt_5 = __VERIFIER_nondet_int() [L553] COND FALSE !(\read(tmp_ndt_5)) [L564] COND TRUE t5_st == 0 [L565] int tmp_ndt_6; [L566] tmp_ndt_6 = __VERIFIER_nondet_int() [L567] COND FALSE !(\read(tmp_ndt_6)) ----- [2018-11-23 13:21:58,327 INFO L145 WitnessManager]: Wrote witness to /tmp/vcloud-vcloud-master/worker/working_dir_fb5f2687-a2ab-446f-b368-1667316ddbd5/bin-2019/uautomizer/witness.graphml [2018-11-23 13:21:58,327 INFO L132 PluginConnector]: ------------------------ END Witness Printer---------------------------- [2018-11-23 13:21:58,328 INFO L168 Benchmark]: Toolchain (without parser) took 10097.37 ms. Allocated memory was 1.0 GB in the beginning and 1.6 GB in the end (delta: 552.1 MB). Free memory was 952.7 MB in the beginning and 747.5 MB in the end (delta: 205.2 MB). Peak memory consumption was 757.2 MB. Max. memory is 11.5 GB. [2018-11-23 13:21:58,328 INFO L168 Benchmark]: CDTParser took 0.12 ms. Allocated memory is still 1.0 GB. Free memory is still 980.1 MB. There was no memory consumed. Max. memory is 11.5 GB. [2018-11-23 13:21:58,329 INFO L168 Benchmark]: CACSL2BoogieTranslator took 240.58 ms. Allocated memory is still 1.0 GB. Free memory was 952.7 MB in the beginning and 931.2 MB in the end (delta: 21.5 MB). Peak memory consumption was 21.5 MB. Max. memory is 11.5 GB. [2018-11-23 13:21:58,329 INFO L168 Benchmark]: Boogie Procedure Inliner took 88.92 ms. Allocated memory was 1.0 GB in the beginning and 1.2 GB in the end (delta: 155.7 MB). Free memory was 931.2 MB in the beginning and 1.1 GB in the end (delta: -216.3 MB). Peak memory consumption was 14.7 MB. Max. memory is 11.5 GB. [2018-11-23 13:21:58,333 INFO L168 Benchmark]: Boogie Preprocessor took 47.15 ms. Allocated memory is still 1.2 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 3.2 MB). Peak memory consumption was 3.2 MB. Max. memory is 11.5 GB. [2018-11-23 13:21:58,333 INFO L168 Benchmark]: RCFGBuilder took 1006.06 ms. Allocated memory is still 1.2 GB. Free memory was 1.1 GB in the beginning and 1.0 GB in the end (delta: 115.8 MB). Peak memory consumption was 115.8 MB. Max. memory is 11.5 GB. [2018-11-23 13:21:58,334 INFO L168 Benchmark]: BuchiAutomizer took 7917.91 ms. Allocated memory was 1.2 GB in the beginning and 1.6 GB in the end (delta: 396.4 MB). Free memory was 1.0 GB in the beginning and 747.5 MB in the end (delta: 281.0 MB). Peak memory consumption was 677.4 MB. Max. memory is 11.5 GB. [2018-11-23 13:21:58,334 INFO L168 Benchmark]: Witness Printer took 793.74 ms. Allocated memory is still 1.6 GB. Free memory was 747.5 MB in the beginning and 747.5 MB in the end (delta: 48 B). Peak memory consumption was 48 B. Max. memory is 11.5 GB. [2018-11-23 13:21:58,336 INFO L336 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.12 ms. Allocated memory is still 1.0 GB. Free memory is still 980.1 MB. There was no memory consumed. Max. memory is 11.5 GB. * CACSL2BoogieTranslator took 240.58 ms. Allocated memory is still 1.0 GB. Free memory was 952.7 MB in the beginning and 931.2 MB in the end (delta: 21.5 MB). Peak memory consumption was 21.5 MB. Max. memory is 11.5 GB. * Boogie Procedure Inliner took 88.92 ms. Allocated memory was 1.0 GB in the beginning and 1.2 GB in the end (delta: 155.7 MB). Free memory was 931.2 MB in the beginning and 1.1 GB in the end (delta: -216.3 MB). Peak memory consumption was 14.7 MB. Max. memory is 11.5 GB. * Boogie Preprocessor took 47.15 ms. Allocated memory is still 1.2 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 3.2 MB). Peak memory consumption was 3.2 MB. Max. memory is 11.5 GB. * RCFGBuilder took 1006.06 ms. Allocated memory is still 1.2 GB. Free memory was 1.1 GB in the beginning and 1.0 GB in the end (delta: 115.8 MB). Peak memory consumption was 115.8 MB. Max. memory is 11.5 GB. * BuchiAutomizer took 7917.91 ms. Allocated memory was 1.2 GB in the beginning and 1.6 GB in the end (delta: 396.4 MB). Free memory was 1.0 GB in the beginning and 747.5 MB in the end (delta: 281.0 MB). Peak memory consumption was 677.4 MB. Max. memory is 11.5 GB. * Witness Printer took 793.74 ms. Allocated memory is still 1.6 GB. Free memory was 747.5 MB in the beginning and 747.5 MB in the end (delta: 48 B). Peak memory consumption was 48 B. Max. memory is 11.5 GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - StatisticsResult: Constructed decomposition of program Your program was decomposed into 21 terminating modules (21 trivial, 0 deterministic, 0 nondeterministic) and one nonterminating remainder module.21 modules have a trivial ranking function, the largest among these consists of 5 locations. The remainder module has 49909 locations. - StatisticsResult: Timing statistics BüchiAutomizer plugin needed 7.6s and 22 iterations. TraceHistogramMax:1. Analysis of lassos took 2.8s. Construction of modules took 0.6s. Büchi inclusion checks took 0.7s. Highest rank in rank-based complementation 0. Minimization of det autom 21. Minimization of nondet autom 0. Automata minimization 1.7s AutomataMinimizationTime, 21 MinimizatonAttempts, 13516 StatesRemovedByMinimization, 12 NontrivialMinimizations. Non-live state removal took 0.9s Buchi closure took 0.0s. Biggest automaton had 49909 states and ocurred in iteration 21. Nontrivial modules had stage [0, 0, 0, 0, 0]. InterpolantCoveringCapabilityFinite: 0/0 InterpolantCoveringCapabilityBuchi: 0/0 HoareTripleCheckerStatistics: 17094 SDtfs, 18523 SDslu, 14213 SDs, 0 SdLazy, 479 SolverSat, 267 SolverUnsat, 0 SolverUnknown, 0 SolverNotchecked, 0.6s Time LassoAnalysisResults: nont1 unkn0 SFLI3 SFLT0 conc5 concLT0 SILN1 SILU0 SILI12 SILT0 lasso0 LassoPreprocessingBenchmarks: LassoTerminationAnalysisBenchmarks: not availableLassoTerminationAnalysisBenchmarks: LassoNonterminationAnalysisSatFixpoint: 0 LassoNonterminationAnalysisSatUnbounded: 0 LassoNonterminationAnalysisUnsat: 0 LassoNonterminationAnalysisUnknown: 0 LassoNonterminationAnalysisTime: 0.0s - TerminationAnalysisResult: Nontermination possible Buchi Automizer proved that your program is nonterminating for some inputs - FixpointNonTerminationResult [Line: 484]: Nontermination argument in form of an infinite program execution. Nontermination argument in form of an infinite execution State at position 0 is {} State at position 1 is {__retres1=0, t3_st=0, token=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@5d87be3a=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@eb92d6=0, tmp=1, t5_i=1, __retres1=0, kernel_st=1, t2_st=0, t4_i=1, E_3=2, t4_pc=0, E_5=2, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@321a38e5=0, \result=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@4bda9710=0, E_1=2, tmp_ndt_2=0, \result=0, __retres1=0, \result=0, tmp_ndt_4=0, tmp_ndt_6=0, m_st=0, tmp___2=0, tmp___0=0, t3_pc=0, tmp=0, \result=0, __retres1=0, m_pc=0, tmp___4=0, \result=0, __retres1=0, \result=0, __retres1=0, \result=0, T2_E=2, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@1c032fa9=0, tmp___0=0, t1_pc=0, t5_st=0, __retres1=1, E_2=2, E_4=2, T1_E=2, tmp_ndt_1=0, M_E=2, tmp=0, tmp_ndt_3=0, __retres1=0, T5_E=2, t2_i=1, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@36f1051b=0, T4_E=2, t3_i=1, t4_st=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@56af0071=0, m_i=1, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@3c39f6df=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@2545228e=0, t1_st=0, tmp_ndt_5=0, t5_pc=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@49d0968d=0, local=0, t2_pc=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@3a2c0019=0, tmp___3=0, E_M=2, tmp___1=0, T3_E=2, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@21f080af=0, t1_i=1, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@6274c410=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@1948f877=0, \result=1, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@12ed183=0} - StatisticsResult: NonterminationArgumentStatistics Fixpoint - NonterminatingLassoResult [Line: 484]: Nonterminating execution ----- class de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder.RCFGBacktranslator [?] ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; [?] havoc main_#res;havoc main_~__retres1~7;havoc main_~__retres1~7;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; [?] havoc start_simulation_#t~ret15, start_simulation_#t~ret16, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; [?] assume 1 == ~m_i~0;~m_st~0 := 0; [?] assume 1 == ~t1_i~0;~t1_st~0 := 0; [?] assume 1 == ~t2_i~0;~t2_st~0 := 0; [?] assume 1 == ~t3_i~0;~t3_st~0 := 0; [?] assume 1 == ~t4_i~0;~t4_st~0 := 0; [?] assume 1 == ~t5_i~0;~t5_st~0 := 0; [?] assume !(0 == ~M_E~0); [?] assume !(0 == ~T1_E~0); [?] assume !(0 == ~T2_E~0); [?] assume !(0 == ~T3_E~0); [?] assume !(0 == ~T4_E~0); [?] assume !(0 == ~T5_E~0); [?] assume !(0 == ~E_M~0); [?] assume !(0 == ~E_1~0); [?] assume !(0 == ~E_2~0); [?] assume !(0 == ~E_3~0); [?] assume !(0 == ~E_4~0); [?] assume !(0 == ~E_5~0); [?] havoc activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; [?] assume !(1 == ~m_pc~0); [?] is_master_triggered_~__retres1~0 := 0; [?] is_master_triggered_#res := is_master_triggered_~__retres1~0; [?] activate_threads_#t~ret8 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; [?] assume !(0 != activate_threads_~tmp~1); [?] havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; [?] assume !(1 == ~t1_pc~0); [?] is_transmit1_triggered_~__retres1~1 := 0; [?] is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; [?] activate_threads_#t~ret9 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; [?] assume !(0 != activate_threads_~tmp___0~0); [?] havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; [?] assume !(1 == ~t2_pc~0); [?] is_transmit2_triggered_~__retres1~2 := 0; [?] is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; [?] activate_threads_#t~ret10 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; [?] assume !(0 != activate_threads_~tmp___1~0); [?] havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; [?] assume !(1 == ~t3_pc~0); [?] is_transmit3_triggered_~__retres1~3 := 0; [?] is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; [?] activate_threads_#t~ret11 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; [?] assume !(0 != activate_threads_~tmp___2~0); [?] havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; [?] assume !(1 == ~t4_pc~0); [?] is_transmit4_triggered_~__retres1~4 := 0; [?] is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; [?] activate_threads_#t~ret12 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; [?] assume !(0 != activate_threads_~tmp___3~0); [?] havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; [?] assume !(1 == ~t5_pc~0); [?] is_transmit5_triggered_~__retres1~5 := 0; [?] is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; [?] activate_threads_#t~ret13 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; [?] assume !(0 != activate_threads_~tmp___4~0); [?] assume !(1 == ~M_E~0); [?] assume !(1 == ~T1_E~0); [?] assume !(1 == ~T2_E~0); [?] assume !(1 == ~T3_E~0); [?] assume !(1 == ~T4_E~0); [?] assume !(1 == ~T5_E~0); [?] assume !(1 == ~E_M~0); [?] assume !(1 == ~E_1~0); [?] assume !(1 == ~E_2~0); [?] assume !(1 == ~E_3~0); [?] assume !(1 == ~E_4~0); [?] assume !(1 == ~E_5~0); [?] assume !false; [?] start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret1, eval_#t~nondet2, eval_~tmp_ndt_1~0, eval_#t~nondet3, eval_~tmp_ndt_2~0, eval_#t~nondet4, eval_~tmp_ndt_3~0, eval_#t~nondet5, eval_~tmp_ndt_4~0, eval_#t~nondet6, eval_~tmp_ndt_5~0, eval_#t~nondet7, eval_~tmp_ndt_6~0, eval_~tmp~0;havoc eval_~tmp~0; [L14] ~m_pc~0 := 0; [L15] ~t1_pc~0 := 0; [L16] ~t2_pc~0 := 0; [L17] ~t3_pc~0 := 0; [L18] ~t4_pc~0 := 0; [L19] ~t5_pc~0 := 0; [L20] ~m_st~0 := 0; [L21] ~t1_st~0 := 0; [L22] ~t2_st~0 := 0; [L23] ~t3_st~0 := 0; [L24] ~t4_st~0 := 0; [L25] ~t5_st~0 := 0; [L26] ~m_i~0 := 0; [L27] ~t1_i~0 := 0; [L28] ~t2_i~0 := 0; [L29] ~t3_i~0 := 0; [L30] ~t4_i~0 := 0; [L31] ~t5_i~0 := 0; [L32] ~M_E~0 := 2; [L33] ~T1_E~0 := 2; [L34] ~T2_E~0 := 2; [L35] ~T3_E~0 := 2; [L36] ~T4_E~0 := 2; [L37] ~T5_E~0 := 2; [L38] ~E_M~0 := 2; [L39] ~E_1~0 := 2; [L40] ~E_2~0 := 2; [L41] ~E_3~0 := 2; [L42] ~E_4~0 := 2; [L43] ~E_5~0 := 2; [L51] ~token~0 := 0; [L53] ~local~0 := 0; [?] havoc main_#res; [?] havoc main_~__retres1~7; [L963] havoc main_~__retres1~7; [L874] ~m_i~0 := 1; [L875] ~t1_i~0 := 1; [L876] ~t2_i~0 := 1; [L877] ~t3_i~0 := 1; [L878] ~t4_i~0 := 1; [L879] ~t5_i~0 := 1; [L968] havoc start_simulation_#t~ret15, start_simulation_#t~ret16, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1; [L904] havoc start_simulation_~kernel_st~0; [L905] havoc start_simulation_~tmp~3; [L906] havoc start_simulation_~tmp___0~1; [L910] start_simulation_~kernel_st~0 := 0; [L404-L408] assume 1 == ~m_i~0; [L405] ~m_st~0 := 0; [L409-L413] assume 1 == ~t1_i~0; [L410] ~t1_st~0 := 0; [L414-L418] assume 1 == ~t2_i~0; [L415] ~t2_st~0 := 0; [L419-L423] assume 1 == ~t3_i~0; [L420] ~t3_st~0 := 0; [L424-L428] assume 1 == ~t4_i~0; [L425] ~t4_st~0 := 0; [L429-L433] assume 1 == ~t5_i~0; [L430] ~t5_st~0 := 0; [L589-L593] assume !(0 == ~M_E~0); [L594-L598] assume !(0 == ~T1_E~0); [L599-L603] assume !(0 == ~T2_E~0); [L604-L608] assume !(0 == ~T3_E~0); [L609-L613] assume !(0 == ~T4_E~0); [L614-L618] assume !(0 == ~T5_E~0); [L619-L623] assume !(0 == ~E_M~0); [L624-L628] assume !(0 == ~E_1~0); [L629-L633] assume !(0 == ~E_2~0); [L634-L638] assume !(0 == ~E_3~0); [L639-L643] assume !(0 == ~E_4~0); [L644-L648] assume !(0 == ~E_5~0); [L914] havoc activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0; [L722] havoc activate_threads_~tmp~1; [L723] havoc activate_threads_~tmp___0~0; [L724] havoc activate_threads_~tmp___1~0; [L725] havoc activate_threads_~tmp___2~0; [L726] havoc activate_threads_~tmp___3~0; [L727] havoc activate_threads_~tmp___4~0; [L731] havoc is_master_triggered_#res; [L731] havoc is_master_triggered_~__retres1~0; [L279] havoc is_master_triggered_~__retres1~0; [L282-L291] assume !(1 == ~m_pc~0); [L292] is_master_triggered_~__retres1~0 := 0; [L294] is_master_triggered_#res := is_master_triggered_~__retres1~0; [L731] activate_threads_#t~ret8 := is_master_triggered_#res; [L731] activate_threads_~tmp~1 := activate_threads_#t~ret8; [L731] havoc activate_threads_#t~ret8; [L733-L737] assume !(0 != activate_threads_~tmp~1); [L739] havoc is_transmit1_triggered_#res; [L739] havoc is_transmit1_triggered_~__retres1~1; [L298] havoc is_transmit1_triggered_~__retres1~1; [L301-L310] assume !(1 == ~t1_pc~0); [L311] is_transmit1_triggered_~__retres1~1 := 0; [L313] is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; [L739] activate_threads_#t~ret9 := is_transmit1_triggered_#res; [L739] activate_threads_~tmp___0~0 := activate_threads_#t~ret9; [L739] havoc activate_threads_#t~ret9; [L741-L745] assume !(0 != activate_threads_~tmp___0~0); [L747] havoc is_transmit2_triggered_#res; [L747] havoc is_transmit2_triggered_~__retres1~2; [L317] havoc is_transmit2_triggered_~__retres1~2; [L320-L329] assume !(1 == ~t2_pc~0); [L330] is_transmit2_triggered_~__retres1~2 := 0; [L332] is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; [L747] activate_threads_#t~ret10 := is_transmit2_triggered_#res; [L747] activate_threads_~tmp___1~0 := activate_threads_#t~ret10; [L747] havoc activate_threads_#t~ret10; [L749-L753] assume !(0 != activate_threads_~tmp___1~0); [L755] havoc is_transmit3_triggered_#res; [L755] havoc is_transmit3_triggered_~__retres1~3; [L336] havoc is_transmit3_triggered_~__retres1~3; [L339-L348] assume !(1 == ~t3_pc~0); [L349] is_transmit3_triggered_~__retres1~3 := 0; [L351] is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; [L755] activate_threads_#t~ret11 := is_transmit3_triggered_#res; [L755] activate_threads_~tmp___2~0 := activate_threads_#t~ret11; [L755] havoc activate_threads_#t~ret11; [L757-L761] assume !(0 != activate_threads_~tmp___2~0); [L763] havoc is_transmit4_triggered_#res; [L763] havoc is_transmit4_triggered_~__retres1~4; [L355] havoc is_transmit4_triggered_~__retres1~4; [L358-L367] assume !(1 == ~t4_pc~0); [L368] is_transmit4_triggered_~__retres1~4 := 0; [L370] is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; [L763] activate_threads_#t~ret12 := is_transmit4_triggered_#res; [L763] activate_threads_~tmp___3~0 := activate_threads_#t~ret12; [L763] havoc activate_threads_#t~ret12; [L765-L769] assume !(0 != activate_threads_~tmp___3~0); [L771] havoc is_transmit5_triggered_#res; [L771] havoc is_transmit5_triggered_~__retres1~5; [L374] havoc is_transmit5_triggered_~__retres1~5; [L377-L386] assume !(1 == ~t5_pc~0); [L387] is_transmit5_triggered_~__retres1~5 := 0; [L389] is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; [L771] activate_threads_#t~ret13 := is_transmit5_triggered_#res; [L771] activate_threads_~tmp___4~0 := activate_threads_#t~ret13; [L771] havoc activate_threads_#t~ret13; [L773-L777] assume !(0 != activate_threads_~tmp___4~0); [L657-L661] assume !(1 == ~M_E~0); [L662-L666] assume !(1 == ~T1_E~0); [L667-L671] assume !(1 == ~T2_E~0); [L672-L676] assume !(1 == ~T3_E~0); [L677-L681] assume !(1 == ~T4_E~0); [L682-L686] assume !(1 == ~T5_E~0); [L687-L691] assume !(1 == ~E_M~0); [L692-L696] assume !(1 == ~E_1~0); [L697-L701] assume !(1 == ~E_2~0); [L702-L706] assume !(1 == ~E_3~0); [L707-L711] assume !(1 == ~E_4~0); [L712-L716] assume !(1 == ~E_5~0); [L918-L955] assume !false; [L921] start_simulation_~kernel_st~0 := 1; [L922] havoc eval_#t~ret1, eval_#t~nondet2, eval_~tmp_ndt_1~0, eval_#t~nondet3, eval_~tmp_ndt_2~0, eval_#t~nondet4, eval_~tmp_ndt_3~0, eval_#t~nondet5, eval_~tmp_ndt_4~0, eval_#t~nondet6, eval_~tmp_ndt_5~0, eval_#t~nondet7, eval_~tmp_ndt_6~0, eval_~tmp~0; [L480] havoc eval_~tmp~0; ----- ----- class de.uni_freiburg.informatik.ultimate.boogie.preprocessor.BoogiePreprocessorBacktranslator [L14] ~m_pc~0 := 0; [L15] ~t1_pc~0 := 0; [L16] ~t2_pc~0 := 0; [L17] ~t3_pc~0 := 0; [L18] ~t4_pc~0 := 0; [L19] ~t5_pc~0 := 0; [L20] ~m_st~0 := 0; [L21] ~t1_st~0 := 0; [L22] ~t2_st~0 := 0; [L23] ~t3_st~0 := 0; [L24] ~t4_st~0 := 0; [L25] ~t5_st~0 := 0; [L26] ~m_i~0 := 0; [L27] ~t1_i~0 := 0; [L28] ~t2_i~0 := 0; [L29] ~t3_i~0 := 0; [L30] ~t4_i~0 := 0; [L31] ~t5_i~0 := 0; [L32] ~M_E~0 := 2; [L33] ~T1_E~0 := 2; [L34] ~T2_E~0 := 2; [L35] ~T3_E~0 := 2; [L36] ~T4_E~0 := 2; [L37] ~T5_E~0 := 2; [L38] ~E_M~0 := 2; [L39] ~E_1~0 := 2; [L40] ~E_2~0 := 2; [L41] ~E_3~0 := 2; [L42] ~E_4~0 := 2; [L43] ~E_5~0 := 2; [L51] ~token~0 := 0; [L53] ~local~0 := 0; [?] havoc main_#res; [?] havoc main_~__retres1~7; [L963] havoc main_~__retres1~7; [L874] ~m_i~0 := 1; [L875] ~t1_i~0 := 1; [L876] ~t2_i~0 := 1; [L877] ~t3_i~0 := 1; [L878] ~t4_i~0 := 1; [L879] ~t5_i~0 := 1; [L968] havoc start_simulation_#t~ret15, start_simulation_#t~ret16, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1; [L904] havoc start_simulation_~kernel_st~0; [L905] havoc start_simulation_~tmp~3; [L906] havoc start_simulation_~tmp___0~1; [L910] start_simulation_~kernel_st~0 := 0; [L404-L408] assume 1 == ~m_i~0; [L405] ~m_st~0 := 0; [L409-L413] assume 1 == ~t1_i~0; [L410] ~t1_st~0 := 0; [L414-L418] assume 1 == ~t2_i~0; [L415] ~t2_st~0 := 0; [L419-L423] assume 1 == ~t3_i~0; [L420] ~t3_st~0 := 0; [L424-L428] assume 1 == ~t4_i~0; [L425] ~t4_st~0 := 0; [L429-L433] assume 1 == ~t5_i~0; [L430] ~t5_st~0 := 0; [L589-L593] assume !(0 == ~M_E~0); [L594-L598] assume !(0 == ~T1_E~0); [L599-L603] assume !(0 == ~T2_E~0); [L604-L608] assume !(0 == ~T3_E~0); [L609-L613] assume !(0 == ~T4_E~0); [L614-L618] assume !(0 == ~T5_E~0); [L619-L623] assume !(0 == ~E_M~0); [L624-L628] assume !(0 == ~E_1~0); [L629-L633] assume !(0 == ~E_2~0); [L634-L638] assume !(0 == ~E_3~0); [L639-L643] assume !(0 == ~E_4~0); [L644-L648] assume !(0 == ~E_5~0); [L914] havoc activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0; [L722] havoc activate_threads_~tmp~1; [L723] havoc activate_threads_~tmp___0~0; [L724] havoc activate_threads_~tmp___1~0; [L725] havoc activate_threads_~tmp___2~0; [L726] havoc activate_threads_~tmp___3~0; [L727] havoc activate_threads_~tmp___4~0; [L731] havoc is_master_triggered_#res; [L731] havoc is_master_triggered_~__retres1~0; [L279] havoc is_master_triggered_~__retres1~0; [L282-L291] assume !(1 == ~m_pc~0); [L292] is_master_triggered_~__retres1~0 := 0; [L294] is_master_triggered_#res := is_master_triggered_~__retres1~0; [L731] activate_threads_#t~ret8 := is_master_triggered_#res; [L731] activate_threads_~tmp~1 := activate_threads_#t~ret8; [L731] havoc activate_threads_#t~ret8; [L733-L737] assume !(0 != activate_threads_~tmp~1); [L739] havoc is_transmit1_triggered_#res; [L739] havoc is_transmit1_triggered_~__retres1~1; [L298] havoc is_transmit1_triggered_~__retres1~1; [L301-L310] assume !(1 == ~t1_pc~0); [L311] is_transmit1_triggered_~__retres1~1 := 0; [L313] is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; [L739] activate_threads_#t~ret9 := is_transmit1_triggered_#res; [L739] activate_threads_~tmp___0~0 := activate_threads_#t~ret9; [L739] havoc activate_threads_#t~ret9; [L741-L745] assume !(0 != activate_threads_~tmp___0~0); [L747] havoc is_transmit2_triggered_#res; [L747] havoc is_transmit2_triggered_~__retres1~2; [L317] havoc is_transmit2_triggered_~__retres1~2; [L320-L329] assume !(1 == ~t2_pc~0); [L330] is_transmit2_triggered_~__retres1~2 := 0; [L332] is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; [L747] activate_threads_#t~ret10 := is_transmit2_triggered_#res; [L747] activate_threads_~tmp___1~0 := activate_threads_#t~ret10; [L747] havoc activate_threads_#t~ret10; [L749-L753] assume !(0 != activate_threads_~tmp___1~0); [L755] havoc is_transmit3_triggered_#res; [L755] havoc is_transmit3_triggered_~__retres1~3; [L336] havoc is_transmit3_triggered_~__retres1~3; [L339-L348] assume !(1 == ~t3_pc~0); [L349] is_transmit3_triggered_~__retres1~3 := 0; [L351] is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; [L755] activate_threads_#t~ret11 := is_transmit3_triggered_#res; [L755] activate_threads_~tmp___2~0 := activate_threads_#t~ret11; [L755] havoc activate_threads_#t~ret11; [L757-L761] assume !(0 != activate_threads_~tmp___2~0); [L763] havoc is_transmit4_triggered_#res; [L763] havoc is_transmit4_triggered_~__retres1~4; [L355] havoc is_transmit4_triggered_~__retres1~4; [L358-L367] assume !(1 == ~t4_pc~0); [L368] is_transmit4_triggered_~__retres1~4 := 0; [L370] is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; [L763] activate_threads_#t~ret12 := is_transmit4_triggered_#res; [L763] activate_threads_~tmp___3~0 := activate_threads_#t~ret12; [L763] havoc activate_threads_#t~ret12; [L765-L769] assume !(0 != activate_threads_~tmp___3~0); [L771] havoc is_transmit5_triggered_#res; [L771] havoc is_transmit5_triggered_~__retres1~5; [L374] havoc is_transmit5_triggered_~__retres1~5; [L377-L386] assume !(1 == ~t5_pc~0); [L387] is_transmit5_triggered_~__retres1~5 := 0; [L389] is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; [L771] activate_threads_#t~ret13 := is_transmit5_triggered_#res; [L771] activate_threads_~tmp___4~0 := activate_threads_#t~ret13; [L771] havoc activate_threads_#t~ret13; [L773-L777] assume !(0 != activate_threads_~tmp___4~0); [L657-L661] assume !(1 == ~M_E~0); [L662-L666] assume !(1 == ~T1_E~0); [L667-L671] assume !(1 == ~T2_E~0); [L672-L676] assume !(1 == ~T3_E~0); [L677-L681] assume !(1 == ~T4_E~0); [L682-L686] assume !(1 == ~T5_E~0); [L687-L691] assume !(1 == ~E_M~0); [L692-L696] assume !(1 == ~E_1~0); [L697-L701] assume !(1 == ~E_2~0); [L702-L706] assume !(1 == ~E_3~0); [L707-L711] assume !(1 == ~E_4~0); [L712-L716] assume !(1 == ~E_5~0); [L918-L955] assume !false; [L921] start_simulation_~kernel_st~0 := 1; [L922] havoc eval_#t~ret1, eval_#t~nondet2, eval_~tmp_ndt_1~0, eval_#t~nondet3, eval_~tmp_ndt_2~0, eval_#t~nondet4, eval_~tmp_ndt_3~0, eval_#t~nondet5, eval_~tmp_ndt_4~0, eval_#t~nondet6, eval_~tmp_ndt_5~0, eval_#t~nondet7, eval_~tmp_ndt_6~0, eval_~tmp~0; [L480] havoc eval_~tmp~0; [L14] ~m_pc~0 := 0; [L15] ~t1_pc~0 := 0; [L16] ~t2_pc~0 := 0; [L17] ~t3_pc~0 := 0; [L18] ~t4_pc~0 := 0; [L19] ~t5_pc~0 := 0; [L20] ~m_st~0 := 0; [L21] ~t1_st~0 := 0; [L22] ~t2_st~0 := 0; [L23] ~t3_st~0 := 0; [L24] ~t4_st~0 := 0; [L25] ~t5_st~0 := 0; [L26] ~m_i~0 := 0; [L27] ~t1_i~0 := 0; [L28] ~t2_i~0 := 0; [L29] ~t3_i~0 := 0; [L30] ~t4_i~0 := 0; [L31] ~t5_i~0 := 0; [L32] ~M_E~0 := 2; [L33] ~T1_E~0 := 2; [L34] ~T2_E~0 := 2; [L35] ~T3_E~0 := 2; [L36] ~T4_E~0 := 2; [L37] ~T5_E~0 := 2; [L38] ~E_M~0 := 2; [L39] ~E_1~0 := 2; [L40] ~E_2~0 := 2; [L41] ~E_3~0 := 2; [L42] ~E_4~0 := 2; [L43] ~E_5~0 := 2; [L51] ~token~0 := 0; [L53] ~local~0 := 0; [?] havoc main_#res; [?] havoc main_~__retres1~7; [L963] havoc main_~__retres1~7; [L874] ~m_i~0 := 1; [L875] ~t1_i~0 := 1; [L876] ~t2_i~0 := 1; [L877] ~t3_i~0 := 1; [L878] ~t4_i~0 := 1; [L879] ~t5_i~0 := 1; [L968] havoc start_simulation_#t~ret15, start_simulation_#t~ret16, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1; [L904] havoc start_simulation_~kernel_st~0; [L905] havoc start_simulation_~tmp~3; [L906] havoc start_simulation_~tmp___0~1; [L910] start_simulation_~kernel_st~0 := 0; [L404] COND TRUE 1 == ~m_i~0 [L405] ~m_st~0 := 0; [L409] COND TRUE 1 == ~t1_i~0 [L410] ~t1_st~0 := 0; [L414] COND TRUE 1 == ~t2_i~0 [L415] ~t2_st~0 := 0; [L419] COND TRUE 1 == ~t3_i~0 [L420] ~t3_st~0 := 0; [L424] COND TRUE 1 == ~t4_i~0 [L425] ~t4_st~0 := 0; [L429] COND TRUE 1 == ~t5_i~0 [L430] ~t5_st~0 := 0; [L589] COND FALSE !(0 == ~M_E~0) [L594] COND FALSE !(0 == ~T1_E~0) [L599] COND FALSE !(0 == ~T2_E~0) [L604] COND FALSE !(0 == ~T3_E~0) [L609] COND FALSE !(0 == ~T4_E~0) [L614] COND FALSE !(0 == ~T5_E~0) [L619] COND FALSE !(0 == ~E_M~0) [L624] COND FALSE !(0 == ~E_1~0) [L629] COND FALSE !(0 == ~E_2~0) [L634] COND FALSE !(0 == ~E_3~0) [L639] COND FALSE !(0 == ~E_4~0) [L644] COND FALSE !(0 == ~E_5~0) [L914] havoc activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0; [L722] havoc activate_threads_~tmp~1; [L723] havoc activate_threads_~tmp___0~0; [L724] havoc activate_threads_~tmp___1~0; [L725] havoc activate_threads_~tmp___2~0; [L726] havoc activate_threads_~tmp___3~0; [L727] havoc activate_threads_~tmp___4~0; [L731] havoc is_master_triggered_#res; [L731] havoc is_master_triggered_~__retres1~0; [L279] havoc is_master_triggered_~__retres1~0; [L282] COND FALSE !(1 == ~m_pc~0) [L292] is_master_triggered_~__retres1~0 := 0; [L294] is_master_triggered_#res := is_master_triggered_~__retres1~0; [L731] activate_threads_#t~ret8 := is_master_triggered_#res; [L731] activate_threads_~tmp~1 := activate_threads_#t~ret8; [L731] havoc activate_threads_#t~ret8; [L733-L737] COND FALSE !(0 != activate_threads_~tmp~1) [L739] havoc is_transmit1_triggered_#res; [L739] havoc is_transmit1_triggered_~__retres1~1; [L298] havoc is_transmit1_triggered_~__retres1~1; [L301] COND FALSE !(1 == ~t1_pc~0) [L311] is_transmit1_triggered_~__retres1~1 := 0; [L313] is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; [L739] activate_threads_#t~ret9 := is_transmit1_triggered_#res; [L739] activate_threads_~tmp___0~0 := activate_threads_#t~ret9; [L739] havoc activate_threads_#t~ret9; [L741-L745] COND FALSE !(0 != activate_threads_~tmp___0~0) [L747] havoc is_transmit2_triggered_#res; [L747] havoc is_transmit2_triggered_~__retres1~2; [L317] havoc is_transmit2_triggered_~__retres1~2; [L320] COND FALSE !(1 == ~t2_pc~0) [L330] is_transmit2_triggered_~__retres1~2 := 0; [L332] is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; [L747] activate_threads_#t~ret10 := is_transmit2_triggered_#res; [L747] activate_threads_~tmp___1~0 := activate_threads_#t~ret10; [L747] havoc activate_threads_#t~ret10; [L749-L753] COND FALSE !(0 != activate_threads_~tmp___1~0) [L755] havoc is_transmit3_triggered_#res; [L755] havoc is_transmit3_triggered_~__retres1~3; [L336] havoc is_transmit3_triggered_~__retres1~3; [L339] COND FALSE !(1 == ~t3_pc~0) [L349] is_transmit3_triggered_~__retres1~3 := 0; [L351] is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; [L755] activate_threads_#t~ret11 := is_transmit3_triggered_#res; [L755] activate_threads_~tmp___2~0 := activate_threads_#t~ret11; [L755] havoc activate_threads_#t~ret11; [L757-L761] COND FALSE !(0 != activate_threads_~tmp___2~0) [L763] havoc is_transmit4_triggered_#res; [L763] havoc is_transmit4_triggered_~__retres1~4; [L355] havoc is_transmit4_triggered_~__retres1~4; [L358] COND FALSE !(1 == ~t4_pc~0) [L368] is_transmit4_triggered_~__retres1~4 := 0; [L370] is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; [L763] activate_threads_#t~ret12 := is_transmit4_triggered_#res; [L763] activate_threads_~tmp___3~0 := activate_threads_#t~ret12; [L763] havoc activate_threads_#t~ret12; [L765-L769] COND FALSE !(0 != activate_threads_~tmp___3~0) [L771] havoc is_transmit5_triggered_#res; [L771] havoc is_transmit5_triggered_~__retres1~5; [L374] havoc is_transmit5_triggered_~__retres1~5; [L377] COND FALSE !(1 == ~t5_pc~0) [L387] is_transmit5_triggered_~__retres1~5 := 0; [L389] is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; [L771] activate_threads_#t~ret13 := is_transmit5_triggered_#res; [L771] activate_threads_~tmp___4~0 := activate_threads_#t~ret13; [L771] havoc activate_threads_#t~ret13; [L773-L777] COND FALSE !(0 != activate_threads_~tmp___4~0) [L657] COND FALSE !(1 == ~M_E~0) [L662] COND FALSE !(1 == ~T1_E~0) [L667] COND FALSE !(1 == ~T2_E~0) [L672] COND FALSE !(1 == ~T3_E~0) [L677] COND FALSE !(1 == ~T4_E~0) [L682] COND FALSE !(1 == ~T5_E~0) [L687] COND FALSE !(1 == ~E_M~0) [L692] COND FALSE !(1 == ~E_1~0) [L697] COND FALSE !(1 == ~E_2~0) [L702] COND FALSE !(1 == ~E_3~0) [L707] COND FALSE !(1 == ~E_4~0) [L712] COND FALSE !(1 == ~E_5~0) [L918-L955] COND FALSE !(false) [L921] start_simulation_~kernel_st~0 := 1; [L922] havoc eval_#t~ret1, eval_#t~nondet2, eval_~tmp_ndt_1~0, eval_#t~nondet3, eval_~tmp_ndt_2~0, eval_#t~nondet4, eval_~tmp_ndt_3~0, eval_#t~nondet5, eval_~tmp_ndt_4~0, eval_#t~nondet6, eval_~tmp_ndt_5~0, eval_#t~nondet7, eval_~tmp_ndt_6~0, eval_~tmp~0; [L480] havoc eval_~tmp~0; ----- ----- class de.uni_freiburg.informatik.ultimate.boogie.procedureinliner.backtranslation.InlinerBacktranslator [L14] ~m_pc~0 := 0; [L15] ~t1_pc~0 := 0; [L16] ~t2_pc~0 := 0; [L17] ~t3_pc~0 := 0; [L18] ~t4_pc~0 := 0; [L19] ~t5_pc~0 := 0; [L20] ~m_st~0 := 0; [L21] ~t1_st~0 := 0; [L22] ~t2_st~0 := 0; [L23] ~t3_st~0 := 0; [L24] ~t4_st~0 := 0; [L25] ~t5_st~0 := 0; [L26] ~m_i~0 := 0; [L27] ~t1_i~0 := 0; [L28] ~t2_i~0 := 0; [L29] ~t3_i~0 := 0; [L30] ~t4_i~0 := 0; [L31] ~t5_i~0 := 0; [L32] ~M_E~0 := 2; [L33] ~T1_E~0 := 2; [L34] ~T2_E~0 := 2; [L35] ~T3_E~0 := 2; [L36] ~T4_E~0 := 2; [L37] ~T5_E~0 := 2; [L38] ~E_M~0 := 2; [L39] ~E_1~0 := 2; [L40] ~E_2~0 := 2; [L41] ~E_3~0 := 2; [L42] ~E_4~0 := 2; [L43] ~E_5~0 := 2; [L51] ~token~0 := 0; [L53] ~local~0 := 0; [?] havoc main_#res; [?] havoc main_~__retres1~7; [L963] havoc main_~__retres1~7; [L874] ~m_i~0 := 1; [L875] ~t1_i~0 := 1; [L876] ~t2_i~0 := 1; [L877] ~t3_i~0 := 1; [L878] ~t4_i~0 := 1; [L879] ~t5_i~0 := 1; [L968] havoc start_simulation_#t~ret15, start_simulation_#t~ret16, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1; [L904] havoc start_simulation_~kernel_st~0; [L905] havoc start_simulation_~tmp~3; [L906] havoc start_simulation_~tmp___0~1; [L910] start_simulation_~kernel_st~0 := 0; [L404] COND TRUE 1 == ~m_i~0 [L405] ~m_st~0 := 0; [L409] COND TRUE 1 == ~t1_i~0 [L410] ~t1_st~0 := 0; [L414] COND TRUE 1 == ~t2_i~0 [L415] ~t2_st~0 := 0; [L419] COND TRUE 1 == ~t3_i~0 [L420] ~t3_st~0 := 0; [L424] COND TRUE 1 == ~t4_i~0 [L425] ~t4_st~0 := 0; [L429] COND TRUE 1 == ~t5_i~0 [L430] ~t5_st~0 := 0; [L589] COND FALSE !(0 == ~M_E~0) [L594] COND FALSE !(0 == ~T1_E~0) [L599] COND FALSE !(0 == ~T2_E~0) [L604] COND FALSE !(0 == ~T3_E~0) [L609] COND FALSE !(0 == ~T4_E~0) [L614] COND FALSE !(0 == ~T5_E~0) [L619] COND FALSE !(0 == ~E_M~0) [L624] COND FALSE !(0 == ~E_1~0) [L629] COND FALSE !(0 == ~E_2~0) [L634] COND FALSE !(0 == ~E_3~0) [L639] COND FALSE !(0 == ~E_4~0) [L644] COND FALSE !(0 == ~E_5~0) [L914] havoc activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0; [L722] havoc activate_threads_~tmp~1; [L723] havoc activate_threads_~tmp___0~0; [L724] havoc activate_threads_~tmp___1~0; [L725] havoc activate_threads_~tmp___2~0; [L726] havoc activate_threads_~tmp___3~0; [L727] havoc activate_threads_~tmp___4~0; [L731] havoc is_master_triggered_#res; [L731] havoc is_master_triggered_~__retres1~0; [L279] havoc is_master_triggered_~__retres1~0; [L282] COND FALSE !(1 == ~m_pc~0) [L292] is_master_triggered_~__retres1~0 := 0; [L294] is_master_triggered_#res := is_master_triggered_~__retres1~0; [L731] activate_threads_#t~ret8 := is_master_triggered_#res; [L731] activate_threads_~tmp~1 := activate_threads_#t~ret8; [L731] havoc activate_threads_#t~ret8; [L733-L737] COND FALSE !(0 != activate_threads_~tmp~1) [L739] havoc is_transmit1_triggered_#res; [L739] havoc is_transmit1_triggered_~__retres1~1; [L298] havoc is_transmit1_triggered_~__retres1~1; [L301] COND FALSE !(1 == ~t1_pc~0) [L311] is_transmit1_triggered_~__retres1~1 := 0; [L313] is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; [L739] activate_threads_#t~ret9 := is_transmit1_triggered_#res; [L739] activate_threads_~tmp___0~0 := activate_threads_#t~ret9; [L739] havoc activate_threads_#t~ret9; [L741-L745] COND FALSE !(0 != activate_threads_~tmp___0~0) [L747] havoc is_transmit2_triggered_#res; [L747] havoc is_transmit2_triggered_~__retres1~2; [L317] havoc is_transmit2_triggered_~__retres1~2; [L320] COND FALSE !(1 == ~t2_pc~0) [L330] is_transmit2_triggered_~__retres1~2 := 0; [L332] is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; [L747] activate_threads_#t~ret10 := is_transmit2_triggered_#res; [L747] activate_threads_~tmp___1~0 := activate_threads_#t~ret10; [L747] havoc activate_threads_#t~ret10; [L749-L753] COND FALSE !(0 != activate_threads_~tmp___1~0) [L755] havoc is_transmit3_triggered_#res; [L755] havoc is_transmit3_triggered_~__retres1~3; [L336] havoc is_transmit3_triggered_~__retres1~3; [L339] COND FALSE !(1 == ~t3_pc~0) [L349] is_transmit3_triggered_~__retres1~3 := 0; [L351] is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; [L755] activate_threads_#t~ret11 := is_transmit3_triggered_#res; [L755] activate_threads_~tmp___2~0 := activate_threads_#t~ret11; [L755] havoc activate_threads_#t~ret11; [L757-L761] COND FALSE !(0 != activate_threads_~tmp___2~0) [L763] havoc is_transmit4_triggered_#res; [L763] havoc is_transmit4_triggered_~__retres1~4; [L355] havoc is_transmit4_triggered_~__retres1~4; [L358] COND FALSE !(1 == ~t4_pc~0) [L368] is_transmit4_triggered_~__retres1~4 := 0; [L370] is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; [L763] activate_threads_#t~ret12 := is_transmit4_triggered_#res; [L763] activate_threads_~tmp___3~0 := activate_threads_#t~ret12; [L763] havoc activate_threads_#t~ret12; [L765-L769] COND FALSE !(0 != activate_threads_~tmp___3~0) [L771] havoc is_transmit5_triggered_#res; [L771] havoc is_transmit5_triggered_~__retres1~5; [L374] havoc is_transmit5_triggered_~__retres1~5; [L377] COND FALSE !(1 == ~t5_pc~0) [L387] is_transmit5_triggered_~__retres1~5 := 0; [L389] is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; [L771] activate_threads_#t~ret13 := is_transmit5_triggered_#res; [L771] activate_threads_~tmp___4~0 := activate_threads_#t~ret13; [L771] havoc activate_threads_#t~ret13; [L773-L777] COND FALSE !(0 != activate_threads_~tmp___4~0) [L657] COND FALSE !(1 == ~M_E~0) [L662] COND FALSE !(1 == ~T1_E~0) [L667] COND FALSE !(1 == ~T2_E~0) [L672] COND FALSE !(1 == ~T3_E~0) [L677] COND FALSE !(1 == ~T4_E~0) [L682] COND FALSE !(1 == ~T5_E~0) [L687] COND FALSE !(1 == ~E_M~0) [L692] COND FALSE !(1 == ~E_1~0) [L697] COND FALSE !(1 == ~E_2~0) [L702] COND FALSE !(1 == ~E_3~0) [L707] COND FALSE !(1 == ~E_4~0) [L712] COND FALSE !(1 == ~E_5~0) [L918-L955] COND FALSE !(false) [L921] start_simulation_~kernel_st~0 := 1; [L922] havoc eval_#t~ret1, eval_#t~nondet2, eval_~tmp_ndt_1~0, eval_#t~nondet3, eval_~tmp_ndt_2~0, eval_#t~nondet4, eval_~tmp_ndt_3~0, eval_#t~nondet5, eval_~tmp_ndt_4~0, eval_#t~nondet6, eval_~tmp_ndt_5~0, eval_#t~nondet7, eval_~tmp_ndt_6~0, eval_~tmp~0; [L480] havoc eval_~tmp~0; [L14] ~m_pc~0 := 0; [L15] ~t1_pc~0 := 0; [L16] ~t2_pc~0 := 0; [L17] ~t3_pc~0 := 0; [L18] ~t4_pc~0 := 0; [L19] ~t5_pc~0 := 0; [L20] ~m_st~0 := 0; [L21] ~t1_st~0 := 0; [L22] ~t2_st~0 := 0; [L23] ~t3_st~0 := 0; [L24] ~t4_st~0 := 0; [L25] ~t5_st~0 := 0; [L26] ~m_i~0 := 0; [L27] ~t1_i~0 := 0; [L28] ~t2_i~0 := 0; [L29] ~t3_i~0 := 0; [L30] ~t4_i~0 := 0; [L31] ~t5_i~0 := 0; [L32] ~M_E~0 := 2; [L33] ~T1_E~0 := 2; [L34] ~T2_E~0 := 2; [L35] ~T3_E~0 := 2; [L36] ~T4_E~0 := 2; [L37] ~T5_E~0 := 2; [L38] ~E_M~0 := 2; [L39] ~E_1~0 := 2; [L40] ~E_2~0 := 2; [L41] ~E_3~0 := 2; [L42] ~E_4~0 := 2; [L43] ~E_5~0 := 2; [L51] ~token~0 := 0; [L53] ~local~0 := 0; [L963] havoc ~__retres1~7; [L874] ~m_i~0 := 1; [L875] ~t1_i~0 := 1; [L876] ~t2_i~0 := 1; [L877] ~t3_i~0 := 1; [L878] ~t4_i~0 := 1; [L879] ~t5_i~0 := 1; [L904] havoc ~kernel_st~0; [L905] havoc ~tmp~3; [L906] havoc ~tmp___0~1; [L910] ~kernel_st~0 := 0; [L404] COND TRUE 1 == ~m_i~0 [L405] ~m_st~0 := 0; [L409] COND TRUE 1 == ~t1_i~0 [L410] ~t1_st~0 := 0; [L414] COND TRUE 1 == ~t2_i~0 [L415] ~t2_st~0 := 0; [L419] COND TRUE 1 == ~t3_i~0 [L420] ~t3_st~0 := 0; [L424] COND TRUE 1 == ~t4_i~0 [L425] ~t4_st~0 := 0; [L429] COND TRUE 1 == ~t5_i~0 [L430] ~t5_st~0 := 0; [L589] COND FALSE !(0 == ~M_E~0) [L594] COND FALSE !(0 == ~T1_E~0) [L599] COND FALSE !(0 == ~T2_E~0) [L604] COND FALSE !(0 == ~T3_E~0) [L609] COND FALSE !(0 == ~T4_E~0) [L614] COND FALSE !(0 == ~T5_E~0) [L619] COND FALSE !(0 == ~E_M~0) [L624] COND FALSE !(0 == ~E_1~0) [L629] COND FALSE !(0 == ~E_2~0) [L634] COND FALSE !(0 == ~E_3~0) [L639] COND FALSE !(0 == ~E_4~0) [L644] COND FALSE !(0 == ~E_5~0) [L722] havoc ~tmp~1; [L723] havoc ~tmp___0~0; [L724] havoc ~tmp___1~0; [L725] havoc ~tmp___2~0; [L726] havoc ~tmp___3~0; [L727] havoc ~tmp___4~0; [L279] havoc ~__retres1~0; [L282] COND FALSE !(1 == ~m_pc~0) [L292] ~__retres1~0 := 0; [L294] #res := ~__retres1~0; [L731] ~tmp~1 := #t~ret8; [L731] havoc #t~ret8; [L733-L737] COND FALSE !(0 != ~tmp~1) [L298] havoc ~__retres1~1; [L301] COND FALSE !(1 == ~t1_pc~0) [L311] ~__retres1~1 := 0; [L313] #res := ~__retres1~1; [L739] ~tmp___0~0 := #t~ret9; [L739] havoc #t~ret9; [L741-L745] COND FALSE !(0 != ~tmp___0~0) [L317] havoc ~__retres1~2; [L320] COND FALSE !(1 == ~t2_pc~0) [L330] ~__retres1~2 := 0; [L332] #res := ~__retres1~2; [L747] ~tmp___1~0 := #t~ret10; [L747] havoc #t~ret10; [L749-L753] COND FALSE !(0 != ~tmp___1~0) [L336] havoc ~__retres1~3; [L339] COND FALSE !(1 == ~t3_pc~0) [L349] ~__retres1~3 := 0; [L351] #res := ~__retres1~3; [L755] ~tmp___2~0 := #t~ret11; [L755] havoc #t~ret11; [L757-L761] COND FALSE !(0 != ~tmp___2~0) [L355] havoc ~__retres1~4; [L358] COND FALSE !(1 == ~t4_pc~0) [L368] ~__retres1~4 := 0; [L370] #res := ~__retres1~4; [L763] ~tmp___3~0 := #t~ret12; [L763] havoc #t~ret12; [L765-L769] COND FALSE !(0 != ~tmp___3~0) [L374] havoc ~__retres1~5; [L377] COND FALSE !(1 == ~t5_pc~0) [L387] ~__retres1~5 := 0; [L389] #res := ~__retres1~5; [L771] ~tmp___4~0 := #t~ret13; [L771] havoc #t~ret13; [L773-L777] COND FALSE !(0 != ~tmp___4~0) [L657] COND FALSE !(1 == ~M_E~0) [L662] COND FALSE !(1 == ~T1_E~0) [L667] COND FALSE !(1 == ~T2_E~0) [L672] COND FALSE !(1 == ~T3_E~0) [L677] COND FALSE !(1 == ~T4_E~0) [L682] COND FALSE !(1 == ~T5_E~0) [L687] COND FALSE !(1 == ~E_M~0) [L692] COND FALSE !(1 == ~E_1~0) [L697] COND FALSE !(1 == ~E_2~0) [L702] COND FALSE !(1 == ~E_3~0) [L707] COND FALSE !(1 == ~E_4~0) [L712] COND FALSE !(1 == ~E_5~0) [L918-L955] COND FALSE !(false) [L921] ~kernel_st~0 := 1; [L480] havoc ~tmp~0; ----- ----- class de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.CACSL2BoogieBacktranslator [L14] ~m_pc~0 := 0; [L15] ~t1_pc~0 := 0; [L16] ~t2_pc~0 := 0; [L17] ~t3_pc~0 := 0; [L18] ~t4_pc~0 := 0; [L19] ~t5_pc~0 := 0; [L20] ~m_st~0 := 0; [L21] ~t1_st~0 := 0; [L22] ~t2_st~0 := 0; [L23] ~t3_st~0 := 0; [L24] ~t4_st~0 := 0; [L25] ~t5_st~0 := 0; [L26] ~m_i~0 := 0; [L27] ~t1_i~0 := 0; [L28] ~t2_i~0 := 0; [L29] ~t3_i~0 := 0; [L30] ~t4_i~0 := 0; [L31] ~t5_i~0 := 0; [L32] ~M_E~0 := 2; [L33] ~T1_E~0 := 2; [L34] ~T2_E~0 := 2; [L35] ~T3_E~0 := 2; [L36] ~T4_E~0 := 2; [L37] ~T5_E~0 := 2; [L38] ~E_M~0 := 2; [L39] ~E_1~0 := 2; [L40] ~E_2~0 := 2; [L41] ~E_3~0 := 2; [L42] ~E_4~0 := 2; [L43] ~E_5~0 := 2; [L51] ~token~0 := 0; [L53] ~local~0 := 0; [L963] havoc ~__retres1~7; [L874] ~m_i~0 := 1; [L875] ~t1_i~0 := 1; [L876] ~t2_i~0 := 1; [L877] ~t3_i~0 := 1; [L878] ~t4_i~0 := 1; [L879] ~t5_i~0 := 1; [L904] havoc ~kernel_st~0; [L905] havoc ~tmp~3; [L906] havoc ~tmp___0~1; [L910] ~kernel_st~0 := 0; [L404] COND TRUE 1 == ~m_i~0 [L405] ~m_st~0 := 0; [L409] COND TRUE 1 == ~t1_i~0 [L410] ~t1_st~0 := 0; [L414] COND TRUE 1 == ~t2_i~0 [L415] ~t2_st~0 := 0; [L419] COND TRUE 1 == ~t3_i~0 [L420] ~t3_st~0 := 0; [L424] COND TRUE 1 == ~t4_i~0 [L425] ~t4_st~0 := 0; [L429] COND TRUE 1 == ~t5_i~0 [L430] ~t5_st~0 := 0; [L589] COND FALSE !(0 == ~M_E~0) [L594] COND FALSE !(0 == ~T1_E~0) [L599] COND FALSE !(0 == ~T2_E~0) [L604] COND FALSE !(0 == ~T3_E~0) [L609] COND FALSE !(0 == ~T4_E~0) [L614] COND FALSE !(0 == ~T5_E~0) [L619] COND FALSE !(0 == ~E_M~0) [L624] COND FALSE !(0 == ~E_1~0) [L629] COND FALSE !(0 == ~E_2~0) [L634] COND FALSE !(0 == ~E_3~0) [L639] COND FALSE !(0 == ~E_4~0) [L644] COND FALSE !(0 == ~E_5~0) [L722] havoc ~tmp~1; [L723] havoc ~tmp___0~0; [L724] havoc ~tmp___1~0; [L725] havoc ~tmp___2~0; [L726] havoc ~tmp___3~0; [L727] havoc ~tmp___4~0; [L279] havoc ~__retres1~0; [L282] COND FALSE !(1 == ~m_pc~0) [L292] ~__retres1~0 := 0; [L294] #res := ~__retres1~0; [L731] ~tmp~1 := #t~ret8; [L731] havoc #t~ret8; [L733-L737] COND FALSE !(0 != ~tmp~1) [L298] havoc ~__retres1~1; [L301] COND FALSE !(1 == ~t1_pc~0) [L311] ~__retres1~1 := 0; [L313] #res := ~__retres1~1; [L739] ~tmp___0~0 := #t~ret9; [L739] havoc #t~ret9; [L741-L745] COND FALSE !(0 != ~tmp___0~0) [L317] havoc ~__retres1~2; [L320] COND FALSE !(1 == ~t2_pc~0) [L330] ~__retres1~2 := 0; [L332] #res := ~__retres1~2; [L747] ~tmp___1~0 := #t~ret10; [L747] havoc #t~ret10; [L749-L753] COND FALSE !(0 != ~tmp___1~0) [L336] havoc ~__retres1~3; [L339] COND FALSE !(1 == ~t3_pc~0) [L349] ~__retres1~3 := 0; [L351] #res := ~__retres1~3; [L755] ~tmp___2~0 := #t~ret11; [L755] havoc #t~ret11; [L757-L761] COND FALSE !(0 != ~tmp___2~0) [L355] havoc ~__retres1~4; [L358] COND FALSE !(1 == ~t4_pc~0) [L368] ~__retres1~4 := 0; [L370] #res := ~__retres1~4; [L763] ~tmp___3~0 := #t~ret12; [L763] havoc #t~ret12; [L765-L769] COND FALSE !(0 != ~tmp___3~0) [L374] havoc ~__retres1~5; [L377] COND FALSE !(1 == ~t5_pc~0) [L387] ~__retres1~5 := 0; [L389] #res := ~__retres1~5; [L771] ~tmp___4~0 := #t~ret13; [L771] havoc #t~ret13; [L773-L777] COND FALSE !(0 != ~tmp___4~0) [L657] COND FALSE !(1 == ~M_E~0) [L662] COND FALSE !(1 == ~T1_E~0) [L667] COND FALSE !(1 == ~T2_E~0) [L672] COND FALSE !(1 == ~T3_E~0) [L677] COND FALSE !(1 == ~T4_E~0) [L682] COND FALSE !(1 == ~T5_E~0) [L687] COND FALSE !(1 == ~E_M~0) [L692] COND FALSE !(1 == ~E_1~0) [L697] COND FALSE !(1 == ~E_2~0) [L702] COND FALSE !(1 == ~E_3~0) [L707] COND FALSE !(1 == ~E_4~0) [L712] COND FALSE !(1 == ~E_5~0) [L918-L955] COND FALSE !(false) [L921] ~kernel_st~0 := 1; [L480] havoc ~tmp~0; [L14] int m_pc = 0; [L15] int t1_pc = 0; [L16] int t2_pc = 0; [L17] int t3_pc = 0; [L18] int t4_pc = 0; [L19] int t5_pc = 0; [L20] int m_st ; [L21] int t1_st ; [L22] int t2_st ; [L23] int t3_st ; [L24] int t4_st ; [L25] int t5_st ; [L26] int m_i ; [L27] int t1_i ; [L28] int t2_i ; [L29] int t3_i ; [L30] int t4_i ; [L31] int t5_i ; [L32] int M_E = 2; [L33] int T1_E = 2; [L34] int T2_E = 2; [L35] int T3_E = 2; [L36] int T4_E = 2; [L37] int T5_E = 2; [L38] int E_M = 2; [L39] int E_1 = 2; [L40] int E_2 = 2; [L41] int E_3 = 2; [L42] int E_4 = 2; [L43] int E_5 = 2; [L51] int token ; [L53] int local ; [L963] int __retres1 ; [L874] m_i = 1 [L875] t1_i = 1 [L876] t2_i = 1 [L877] t3_i = 1 [L878] t4_i = 1 [L879] t5_i = 1 [L904] int kernel_st ; [L905] int tmp ; [L906] int tmp___0 ; [L910] kernel_st = 0 [L404] COND TRUE m_i == 1 [L405] m_st = 0 [L409] COND TRUE t1_i == 1 [L410] t1_st = 0 [L414] COND TRUE t2_i == 1 [L415] t2_st = 0 [L419] COND TRUE t3_i == 1 [L420] t3_st = 0 [L424] COND TRUE t4_i == 1 [L425] t4_st = 0 [L429] COND TRUE t5_i == 1 [L430] t5_st = 0 [L589] COND FALSE !(M_E == 0) [L594] COND FALSE !(T1_E == 0) [L599] COND FALSE !(T2_E == 0) [L604] COND FALSE !(T3_E == 0) [L609] COND FALSE !(T4_E == 0) [L614] COND FALSE !(T5_E == 0) [L619] COND FALSE !(E_M == 0) [L624] COND FALSE !(E_1 == 0) [L629] COND FALSE !(E_2 == 0) [L634] COND FALSE !(E_3 == 0) [L639] COND FALSE !(E_4 == 0) [L644] COND FALSE !(E_5 == 0) [L722] int tmp ; [L723] int tmp___0 ; [L724] int tmp___1 ; [L725] int tmp___2 ; [L726] int tmp___3 ; [L727] int tmp___4 ; [L279] int __retres1 ; [L282] COND FALSE !(m_pc == 1) [L292] __retres1 = 0 [L294] return (__retres1); [L731] tmp = is_master_triggered() [L733] COND FALSE !(\read(tmp)) [L298] int __retres1 ; [L301] COND FALSE !(t1_pc == 1) [L311] __retres1 = 0 [L313] return (__retres1); [L739] tmp___0 = is_transmit1_triggered() [L741] COND FALSE !(\read(tmp___0)) [L317] int __retres1 ; [L320] COND FALSE !(t2_pc == 1) [L330] __retres1 = 0 [L332] return (__retres1); [L747] tmp___1 = is_transmit2_triggered() [L749] COND FALSE !(\read(tmp___1)) [L336] int __retres1 ; [L339] COND FALSE !(t3_pc == 1) [L349] __retres1 = 0 [L351] return (__retres1); [L755] tmp___2 = is_transmit3_triggered() [L757] COND FALSE !(\read(tmp___2)) [L355] int __retres1 ; [L358] COND FALSE !(t4_pc == 1) [L368] __retres1 = 0 [L370] return (__retres1); [L763] tmp___3 = is_transmit4_triggered() [L765] COND FALSE !(\read(tmp___3)) [L374] int __retres1 ; [L377] COND FALSE !(t5_pc == 1) [L387] __retres1 = 0 [L389] return (__retres1); [L771] tmp___4 = is_transmit5_triggered() [L773] COND FALSE !(\read(tmp___4)) [L657] COND FALSE !(M_E == 1) [L662] COND FALSE !(T1_E == 1) [L667] COND FALSE !(T2_E == 1) [L672] COND FALSE !(T3_E == 1) [L677] COND FALSE !(T4_E == 1) [L682] COND FALSE !(T5_E == 1) [L687] COND FALSE !(E_M == 1) [L692] COND FALSE !(E_1 == 1) [L697] COND FALSE !(E_2 == 1) [L702] COND FALSE !(E_3 == 1) [L707] COND FALSE !(E_4 == 1) [L712] COND FALSE !(E_5 == 1) [L918] COND TRUE 1 [L921] kernel_st = 1 [L480] int tmp ; ----- ----- class de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder.RCFGBacktranslator [?] assume !false; [?] havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; [?] assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; [?] exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; [?] eval_#t~ret1 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret1;havoc eval_#t~ret1; [?] assume 0 != eval_~tmp~0; [?] assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0;eval_~tmp_ndt_1~0 := eval_#t~nondet2;havoc eval_#t~nondet2; [?] assume !(0 != eval_~tmp_ndt_1~0); [?] assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0;eval_~tmp_ndt_2~0 := eval_#t~nondet3;havoc eval_#t~nondet3; [?] assume !(0 != eval_~tmp_ndt_2~0); [?] assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0;eval_~tmp_ndt_3~0 := eval_#t~nondet4;havoc eval_#t~nondet4; [?] assume !(0 != eval_~tmp_ndt_3~0); [?] assume 0 == ~t3_st~0;havoc eval_~tmp_ndt_4~0;eval_~tmp_ndt_4~0 := eval_#t~nondet5;havoc eval_#t~nondet5; [?] assume !(0 != eval_~tmp_ndt_4~0); [?] assume 0 == ~t4_st~0;havoc eval_~tmp_ndt_5~0;eval_~tmp_ndt_5~0 := eval_#t~nondet6;havoc eval_#t~nondet6; [?] assume !(0 != eval_~tmp_ndt_5~0); [?] assume 0 == ~t5_st~0;havoc eval_~tmp_ndt_6~0;eval_~tmp_ndt_6~0 := eval_#t~nondet7;havoc eval_#t~nondet7; [?] assume !(0 != eval_~tmp_ndt_6~0); [L484-L578] assume !false; [L487] havoc exists_runnable_thread_#res; [L487] havoc exists_runnable_thread_~__retres1~6; [L439] havoc exists_runnable_thread_~__retres1~6; [L442-L472] assume 0 == ~m_st~0; [L443] exists_runnable_thread_~__retres1~6 := 1; [L475] exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; [L487] eval_#t~ret1 := exists_runnable_thread_#res; [L487] eval_~tmp~0 := eval_#t~ret1; [L487] havoc eval_#t~ret1; [L489-L493] assume 0 != eval_~tmp~0; [L494-L507] assume 0 == ~m_st~0; [L495] havoc eval_~tmp_ndt_1~0; [L496] eval_~tmp_ndt_1~0 := eval_#t~nondet2; [L496] havoc eval_#t~nondet2; [L497-L504] assume !(0 != eval_~tmp_ndt_1~0); [L508-L521] assume 0 == ~t1_st~0; [L509] havoc eval_~tmp_ndt_2~0; [L510] eval_~tmp_ndt_2~0 := eval_#t~nondet3; [L510] havoc eval_#t~nondet3; [L511-L518] assume !(0 != eval_~tmp_ndt_2~0); [L522-L535] assume 0 == ~t2_st~0; [L523] havoc eval_~tmp_ndt_3~0; [L524] eval_~tmp_ndt_3~0 := eval_#t~nondet4; [L524] havoc eval_#t~nondet4; [L525-L532] assume !(0 != eval_~tmp_ndt_3~0); [L536-L549] assume 0 == ~t3_st~0; [L537] havoc eval_~tmp_ndt_4~0; [L538] eval_~tmp_ndt_4~0 := eval_#t~nondet5; [L538] havoc eval_#t~nondet5; [L539-L546] assume !(0 != eval_~tmp_ndt_4~0); [L550-L563] assume 0 == ~t4_st~0; [L551] havoc eval_~tmp_ndt_5~0; [L552] eval_~tmp_ndt_5~0 := eval_#t~nondet6; [L552] havoc eval_#t~nondet6; [L553-L560] assume !(0 != eval_~tmp_ndt_5~0); [L564-L577] assume 0 == ~t5_st~0; [L565] havoc eval_~tmp_ndt_6~0; [L566] eval_~tmp_ndt_6~0 := eval_#t~nondet7; [L566] havoc eval_#t~nondet7; [L567-L574] assume !(0 != eval_~tmp_ndt_6~0); ----- ----- class de.uni_freiburg.informatik.ultimate.boogie.preprocessor.BoogiePreprocessorBacktranslator [L484-L578] assume !false; [L487] havoc exists_runnable_thread_#res; [L487] havoc exists_runnable_thread_~__retres1~6; [L439] havoc exists_runnable_thread_~__retres1~6; [L442-L472] assume 0 == ~m_st~0; [L443] exists_runnable_thread_~__retres1~6 := 1; [L475] exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; [L487] eval_#t~ret1 := exists_runnable_thread_#res; [L487] eval_~tmp~0 := eval_#t~ret1; [L487] havoc eval_#t~ret1; [L489-L493] assume 0 != eval_~tmp~0; [L494-L507] assume 0 == ~m_st~0; [L495] havoc eval_~tmp_ndt_1~0; [L496] eval_~tmp_ndt_1~0 := eval_#t~nondet2; [L496] havoc eval_#t~nondet2; [L497-L504] assume !(0 != eval_~tmp_ndt_1~0); [L508-L521] assume 0 == ~t1_st~0; [L509] havoc eval_~tmp_ndt_2~0; [L510] eval_~tmp_ndt_2~0 := eval_#t~nondet3; [L510] havoc eval_#t~nondet3; [L511-L518] assume !(0 != eval_~tmp_ndt_2~0); [L522-L535] assume 0 == ~t2_st~0; [L523] havoc eval_~tmp_ndt_3~0; [L524] eval_~tmp_ndt_3~0 := eval_#t~nondet4; [L524] havoc eval_#t~nondet4; [L525-L532] assume !(0 != eval_~tmp_ndt_3~0); [L536-L549] assume 0 == ~t3_st~0; [L537] havoc eval_~tmp_ndt_4~0; [L538] eval_~tmp_ndt_4~0 := eval_#t~nondet5; [L538] havoc eval_#t~nondet5; [L539-L546] assume !(0 != eval_~tmp_ndt_4~0); [L550-L563] assume 0 == ~t4_st~0; [L551] havoc eval_~tmp_ndt_5~0; [L552] eval_~tmp_ndt_5~0 := eval_#t~nondet6; [L552] havoc eval_#t~nondet6; [L553-L560] assume !(0 != eval_~tmp_ndt_5~0); [L564-L577] assume 0 == ~t5_st~0; [L565] havoc eval_~tmp_ndt_6~0; [L566] eval_~tmp_ndt_6~0 := eval_#t~nondet7; [L566] havoc eval_#t~nondet7; [L567-L574] assume !(0 != eval_~tmp_ndt_6~0); [L484-L578] COND FALSE !(false) [L487] havoc exists_runnable_thread_#res; [L487] havoc exists_runnable_thread_~__retres1~6; [L439] havoc exists_runnable_thread_~__retres1~6; [L442] COND TRUE 0 == ~m_st~0 [L443] exists_runnable_thread_~__retres1~6 := 1; [L475] exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; [L487] eval_#t~ret1 := exists_runnable_thread_#res; [L487] eval_~tmp~0 := eval_#t~ret1; [L487] havoc eval_#t~ret1; [L489-L493] COND TRUE 0 != eval_~tmp~0 [L494] COND TRUE 0 == ~m_st~0 [L495] havoc eval_~tmp_ndt_1~0; [L496] eval_~tmp_ndt_1~0 := eval_#t~nondet2; [L496] havoc eval_#t~nondet2; [L497-L504] COND FALSE !(0 != eval_~tmp_ndt_1~0) [L508] COND TRUE 0 == ~t1_st~0 [L509] havoc eval_~tmp_ndt_2~0; [L510] eval_~tmp_ndt_2~0 := eval_#t~nondet3; [L510] havoc eval_#t~nondet3; [L511-L518] COND FALSE !(0 != eval_~tmp_ndt_2~0) [L522] COND TRUE 0 == ~t2_st~0 [L523] havoc eval_~tmp_ndt_3~0; [L524] eval_~tmp_ndt_3~0 := eval_#t~nondet4; [L524] havoc eval_#t~nondet4; [L525-L532] COND FALSE !(0 != eval_~tmp_ndt_3~0) [L536] COND TRUE 0 == ~t3_st~0 [L537] havoc eval_~tmp_ndt_4~0; [L538] eval_~tmp_ndt_4~0 := eval_#t~nondet5; [L538] havoc eval_#t~nondet5; [L539-L546] COND FALSE !(0 != eval_~tmp_ndt_4~0) [L550] COND TRUE 0 == ~t4_st~0 [L551] havoc eval_~tmp_ndt_5~0; [L552] eval_~tmp_ndt_5~0 := eval_#t~nondet6; [L552] havoc eval_#t~nondet6; [L553-L560] COND FALSE !(0 != eval_~tmp_ndt_5~0) [L564] COND TRUE 0 == ~t5_st~0 [L565] havoc eval_~tmp_ndt_6~0; [L566] eval_~tmp_ndt_6~0 := eval_#t~nondet7; [L566] havoc eval_#t~nondet7; [L567-L574] COND FALSE !(0 != eval_~tmp_ndt_6~0) ----- ----- class de.uni_freiburg.informatik.ultimate.boogie.procedureinliner.backtranslation.InlinerBacktranslator [L484-L578] COND FALSE !(false) [L487] havoc exists_runnable_thread_#res; [L487] havoc exists_runnable_thread_~__retres1~6; [L439] havoc exists_runnable_thread_~__retres1~6; [L442] COND TRUE 0 == ~m_st~0 [L443] exists_runnable_thread_~__retres1~6 := 1; [L475] exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; [L487] eval_#t~ret1 := exists_runnable_thread_#res; [L487] eval_~tmp~0 := eval_#t~ret1; [L487] havoc eval_#t~ret1; [L489-L493] COND TRUE 0 != eval_~tmp~0 [L494] COND TRUE 0 == ~m_st~0 [L495] havoc eval_~tmp_ndt_1~0; [L496] eval_~tmp_ndt_1~0 := eval_#t~nondet2; [L496] havoc eval_#t~nondet2; [L497-L504] COND FALSE !(0 != eval_~tmp_ndt_1~0) [L508] COND TRUE 0 == ~t1_st~0 [L509] havoc eval_~tmp_ndt_2~0; [L510] eval_~tmp_ndt_2~0 := eval_#t~nondet3; [L510] havoc eval_#t~nondet3; [L511-L518] COND FALSE !(0 != eval_~tmp_ndt_2~0) [L522] COND TRUE 0 == ~t2_st~0 [L523] havoc eval_~tmp_ndt_3~0; [L524] eval_~tmp_ndt_3~0 := eval_#t~nondet4; [L524] havoc eval_#t~nondet4; [L525-L532] COND FALSE !(0 != eval_~tmp_ndt_3~0) [L536] COND TRUE 0 == ~t3_st~0 [L537] havoc eval_~tmp_ndt_4~0; [L538] eval_~tmp_ndt_4~0 := eval_#t~nondet5; [L538] havoc eval_#t~nondet5; [L539-L546] COND FALSE !(0 != eval_~tmp_ndt_4~0) [L550] COND TRUE 0 == ~t4_st~0 [L551] havoc eval_~tmp_ndt_5~0; [L552] eval_~tmp_ndt_5~0 := eval_#t~nondet6; [L552] havoc eval_#t~nondet6; [L553-L560] COND FALSE !(0 != eval_~tmp_ndt_5~0) [L564] COND TRUE 0 == ~t5_st~0 [L565] havoc eval_~tmp_ndt_6~0; [L566] eval_~tmp_ndt_6~0 := eval_#t~nondet7; [L566] havoc eval_#t~nondet7; [L567-L574] COND FALSE !(0 != eval_~tmp_ndt_6~0) [L484-L578] COND FALSE !(false) [L439] havoc ~__retres1~6; [L442] COND TRUE 0 == ~m_st~0 [L443] ~__retres1~6 := 1; [L475] #res := ~__retres1~6; [L487] ~tmp~0 := #t~ret1; [L487] havoc #t~ret1; [L489-L493] COND TRUE 0 != ~tmp~0 [L494] COND TRUE 0 == ~m_st~0 [L495] havoc ~tmp_ndt_1~0; [L496] ~tmp_ndt_1~0 := #t~nondet2; [L496] havoc #t~nondet2; [L497-L504] COND FALSE !(0 != ~tmp_ndt_1~0) [L508] COND TRUE 0 == ~t1_st~0 [L509] havoc ~tmp_ndt_2~0; [L510] ~tmp_ndt_2~0 := #t~nondet3; [L510] havoc #t~nondet3; [L511-L518] COND FALSE !(0 != ~tmp_ndt_2~0) [L522] COND TRUE 0 == ~t2_st~0 [L523] havoc ~tmp_ndt_3~0; [L524] ~tmp_ndt_3~0 := #t~nondet4; [L524] havoc #t~nondet4; [L525-L532] COND FALSE !(0 != ~tmp_ndt_3~0) [L536] COND TRUE 0 == ~t3_st~0 [L537] havoc ~tmp_ndt_4~0; [L538] ~tmp_ndt_4~0 := #t~nondet5; [L538] havoc #t~nondet5; [L539-L546] COND FALSE !(0 != ~tmp_ndt_4~0) [L550] COND TRUE 0 == ~t4_st~0 [L551] havoc ~tmp_ndt_5~0; [L552] ~tmp_ndt_5~0 := #t~nondet6; [L552] havoc #t~nondet6; [L553-L560] COND FALSE !(0 != ~tmp_ndt_5~0) [L564] COND TRUE 0 == ~t5_st~0 [L565] havoc ~tmp_ndt_6~0; [L566] ~tmp_ndt_6~0 := #t~nondet7; [L566] havoc #t~nondet7; [L567-L574] COND FALSE !(0 != ~tmp_ndt_6~0) ----- ----- class de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.CACSL2BoogieBacktranslator [L484-L578] COND FALSE !(false) [L439] havoc ~__retres1~6; [L442] COND TRUE 0 == ~m_st~0 [L443] ~__retres1~6 := 1; [L475] #res := ~__retres1~6; [L487] ~tmp~0 := #t~ret1; [L487] havoc #t~ret1; [L489-L493] COND TRUE 0 != ~tmp~0 [L494] COND TRUE 0 == ~m_st~0 [L495] havoc ~tmp_ndt_1~0; [L496] ~tmp_ndt_1~0 := #t~nondet2; [L496] havoc #t~nondet2; [L497-L504] COND FALSE !(0 != ~tmp_ndt_1~0) [L508] COND TRUE 0 == ~t1_st~0 [L509] havoc ~tmp_ndt_2~0; [L510] ~tmp_ndt_2~0 := #t~nondet3; [L510] havoc #t~nondet3; [L511-L518] COND FALSE !(0 != ~tmp_ndt_2~0) [L522] COND TRUE 0 == ~t2_st~0 [L523] havoc ~tmp_ndt_3~0; [L524] ~tmp_ndt_3~0 := #t~nondet4; [L524] havoc #t~nondet4; [L525-L532] COND FALSE !(0 != ~tmp_ndt_3~0) [L536] COND TRUE 0 == ~t3_st~0 [L537] havoc ~tmp_ndt_4~0; [L538] ~tmp_ndt_4~0 := #t~nondet5; [L538] havoc #t~nondet5; [L539-L546] COND FALSE !(0 != ~tmp_ndt_4~0) [L550] COND TRUE 0 == ~t4_st~0 [L551] havoc ~tmp_ndt_5~0; [L552] ~tmp_ndt_5~0 := #t~nondet6; [L552] havoc #t~nondet6; [L553-L560] COND FALSE !(0 != ~tmp_ndt_5~0) [L564] COND TRUE 0 == ~t5_st~0 [L565] havoc ~tmp_ndt_6~0; [L566] ~tmp_ndt_6~0 := #t~nondet7; [L566] havoc #t~nondet7; [L567-L574] COND FALSE !(0 != ~tmp_ndt_6~0) [L484] COND TRUE 1 [L439] int __retres1 ; [L442] COND TRUE m_st == 0 [L443] __retres1 = 1 [L475] return (__retres1); [L487] tmp = exists_runnable_thread() [L489] COND TRUE \read(tmp) [L494] COND TRUE m_st == 0 [L495] int tmp_ndt_1; [L496] tmp_ndt_1 = __VERIFIER_nondet_int() [L497] COND FALSE !(\read(tmp_ndt_1)) [L508] COND TRUE t1_st == 0 [L509] int tmp_ndt_2; [L510] tmp_ndt_2 = __VERIFIER_nondet_int() [L511] COND FALSE !(\read(tmp_ndt_2)) [L522] COND TRUE t2_st == 0 [L523] int tmp_ndt_3; [L524] tmp_ndt_3 = __VERIFIER_nondet_int() [L525] COND FALSE !(\read(tmp_ndt_3)) [L536] COND TRUE t3_st == 0 [L537] int tmp_ndt_4; [L538] tmp_ndt_4 = __VERIFIER_nondet_int() [L539] COND FALSE !(\read(tmp_ndt_4)) [L550] COND TRUE t4_st == 0 [L551] int tmp_ndt_5; [L552] tmp_ndt_5 = __VERIFIER_nondet_int() [L553] COND FALSE !(\read(tmp_ndt_5)) [L564] COND TRUE t5_st == 0 [L565] int tmp_ndt_6; [L566] tmp_ndt_6 = __VERIFIER_nondet_int() [L567] COND FALSE !(\read(tmp_ndt_6)) ----- ----- class de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder.RCFGBacktranslator [?] ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; [?] havoc main_#res;havoc main_~__retres1~7;havoc main_~__retres1~7;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; [?] havoc start_simulation_#t~ret15, start_simulation_#t~ret16, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; [?] assume 1 == ~m_i~0;~m_st~0 := 0; [?] assume 1 == ~t1_i~0;~t1_st~0 := 0; [?] assume 1 == ~t2_i~0;~t2_st~0 := 0; [?] assume 1 == ~t3_i~0;~t3_st~0 := 0; [?] assume 1 == ~t4_i~0;~t4_st~0 := 0; [?] assume 1 == ~t5_i~0;~t5_st~0 := 0; [?] assume !(0 == ~M_E~0); [?] assume !(0 == ~T1_E~0); [?] assume !(0 == ~T2_E~0); [?] assume !(0 == ~T3_E~0); [?] assume !(0 == ~T4_E~0); [?] assume !(0 == ~T5_E~0); [?] assume !(0 == ~E_M~0); [?] assume !(0 == ~E_1~0); [?] assume !(0 == ~E_2~0); [?] assume !(0 == ~E_3~0); [?] assume !(0 == ~E_4~0); [?] assume !(0 == ~E_5~0); [?] havoc activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; [?] assume !(1 == ~m_pc~0); [?] is_master_triggered_~__retres1~0 := 0; [?] is_master_triggered_#res := is_master_triggered_~__retres1~0; [?] activate_threads_#t~ret8 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; [?] assume !(0 != activate_threads_~tmp~1); [?] havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; [?] assume !(1 == ~t1_pc~0); [?] is_transmit1_triggered_~__retres1~1 := 0; [?] is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; [?] activate_threads_#t~ret9 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; [?] assume !(0 != activate_threads_~tmp___0~0); [?] havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; [?] assume !(1 == ~t2_pc~0); [?] is_transmit2_triggered_~__retres1~2 := 0; [?] is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; [?] activate_threads_#t~ret10 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; [?] assume !(0 != activate_threads_~tmp___1~0); [?] havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; [?] assume !(1 == ~t3_pc~0); [?] is_transmit3_triggered_~__retres1~3 := 0; [?] is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; [?] activate_threads_#t~ret11 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; [?] assume !(0 != activate_threads_~tmp___2~0); [?] havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; [?] assume !(1 == ~t4_pc~0); [?] is_transmit4_triggered_~__retres1~4 := 0; [?] is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; [?] activate_threads_#t~ret12 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; [?] assume !(0 != activate_threads_~tmp___3~0); [?] havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; [?] assume !(1 == ~t5_pc~0); [?] is_transmit5_triggered_~__retres1~5 := 0; [?] is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; [?] activate_threads_#t~ret13 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; [?] assume !(0 != activate_threads_~tmp___4~0); [?] assume !(1 == ~M_E~0); [?] assume !(1 == ~T1_E~0); [?] assume !(1 == ~T2_E~0); [?] assume !(1 == ~T3_E~0); [?] assume !(1 == ~T4_E~0); [?] assume !(1 == ~T5_E~0); [?] assume !(1 == ~E_M~0); [?] assume !(1 == ~E_1~0); [?] assume !(1 == ~E_2~0); [?] assume !(1 == ~E_3~0); [?] assume !(1 == ~E_4~0); [?] assume !(1 == ~E_5~0); [?] assume !false; [?] start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret1, eval_#t~nondet2, eval_~tmp_ndt_1~0, eval_#t~nondet3, eval_~tmp_ndt_2~0, eval_#t~nondet4, eval_~tmp_ndt_3~0, eval_#t~nondet5, eval_~tmp_ndt_4~0, eval_#t~nondet6, eval_~tmp_ndt_5~0, eval_#t~nondet7, eval_~tmp_ndt_6~0, eval_~tmp~0;havoc eval_~tmp~0; [L14] ~m_pc~0 := 0; [L15] ~t1_pc~0 := 0; [L16] ~t2_pc~0 := 0; [L17] ~t3_pc~0 := 0; [L18] ~t4_pc~0 := 0; [L19] ~t5_pc~0 := 0; [L20] ~m_st~0 := 0; [L21] ~t1_st~0 := 0; [L22] ~t2_st~0 := 0; [L23] ~t3_st~0 := 0; [L24] ~t4_st~0 := 0; [L25] ~t5_st~0 := 0; [L26] ~m_i~0 := 0; [L27] ~t1_i~0 := 0; [L28] ~t2_i~0 := 0; [L29] ~t3_i~0 := 0; [L30] ~t4_i~0 := 0; [L31] ~t5_i~0 := 0; [L32] ~M_E~0 := 2; [L33] ~T1_E~0 := 2; [L34] ~T2_E~0 := 2; [L35] ~T3_E~0 := 2; [L36] ~T4_E~0 := 2; [L37] ~T5_E~0 := 2; [L38] ~E_M~0 := 2; [L39] ~E_1~0 := 2; [L40] ~E_2~0 := 2; [L41] ~E_3~0 := 2; [L42] ~E_4~0 := 2; [L43] ~E_5~0 := 2; [L51] ~token~0 := 0; [L53] ~local~0 := 0; [?] havoc main_#res; [?] havoc main_~__retres1~7; [L963] havoc main_~__retres1~7; [L874] ~m_i~0 := 1; [L875] ~t1_i~0 := 1; [L876] ~t2_i~0 := 1; [L877] ~t3_i~0 := 1; [L878] ~t4_i~0 := 1; [L879] ~t5_i~0 := 1; [L968] havoc start_simulation_#t~ret15, start_simulation_#t~ret16, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1; [L904] havoc start_simulation_~kernel_st~0; [L905] havoc start_simulation_~tmp~3; [L906] havoc start_simulation_~tmp___0~1; [L910] start_simulation_~kernel_st~0 := 0; [L404-L408] assume 1 == ~m_i~0; [L405] ~m_st~0 := 0; [L409-L413] assume 1 == ~t1_i~0; [L410] ~t1_st~0 := 0; [L414-L418] assume 1 == ~t2_i~0; [L415] ~t2_st~0 := 0; [L419-L423] assume 1 == ~t3_i~0; [L420] ~t3_st~0 := 0; [L424-L428] assume 1 == ~t4_i~0; [L425] ~t4_st~0 := 0; [L429-L433] assume 1 == ~t5_i~0; [L430] ~t5_st~0 := 0; [L589-L593] assume !(0 == ~M_E~0); [L594-L598] assume !(0 == ~T1_E~0); [L599-L603] assume !(0 == ~T2_E~0); [L604-L608] assume !(0 == ~T3_E~0); [L609-L613] assume !(0 == ~T4_E~0); [L614-L618] assume !(0 == ~T5_E~0); [L619-L623] assume !(0 == ~E_M~0); [L624-L628] assume !(0 == ~E_1~0); [L629-L633] assume !(0 == ~E_2~0); [L634-L638] assume !(0 == ~E_3~0); [L639-L643] assume !(0 == ~E_4~0); [L644-L648] assume !(0 == ~E_5~0); [L914] havoc activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0; [L722] havoc activate_threads_~tmp~1; [L723] havoc activate_threads_~tmp___0~0; [L724] havoc activate_threads_~tmp___1~0; [L725] havoc activate_threads_~tmp___2~0; [L726] havoc activate_threads_~tmp___3~0; [L727] havoc activate_threads_~tmp___4~0; [L731] havoc is_master_triggered_#res; [L731] havoc is_master_triggered_~__retres1~0; [L279] havoc is_master_triggered_~__retres1~0; [L282-L291] assume !(1 == ~m_pc~0); [L292] is_master_triggered_~__retres1~0 := 0; [L294] is_master_triggered_#res := is_master_triggered_~__retres1~0; [L731] activate_threads_#t~ret8 := is_master_triggered_#res; [L731] activate_threads_~tmp~1 := activate_threads_#t~ret8; [L731] havoc activate_threads_#t~ret8; [L733-L737] assume !(0 != activate_threads_~tmp~1); [L739] havoc is_transmit1_triggered_#res; [L739] havoc is_transmit1_triggered_~__retres1~1; [L298] havoc is_transmit1_triggered_~__retres1~1; [L301-L310] assume !(1 == ~t1_pc~0); [L311] is_transmit1_triggered_~__retres1~1 := 0; [L313] is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; [L739] activate_threads_#t~ret9 := is_transmit1_triggered_#res; [L739] activate_threads_~tmp___0~0 := activate_threads_#t~ret9; [L739] havoc activate_threads_#t~ret9; [L741-L745] assume !(0 != activate_threads_~tmp___0~0); [L747] havoc is_transmit2_triggered_#res; [L747] havoc is_transmit2_triggered_~__retres1~2; [L317] havoc is_transmit2_triggered_~__retres1~2; [L320-L329] assume !(1 == ~t2_pc~0); [L330] is_transmit2_triggered_~__retres1~2 := 0; [L332] is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; [L747] activate_threads_#t~ret10 := is_transmit2_triggered_#res; [L747] activate_threads_~tmp___1~0 := activate_threads_#t~ret10; [L747] havoc activate_threads_#t~ret10; [L749-L753] assume !(0 != activate_threads_~tmp___1~0); [L755] havoc is_transmit3_triggered_#res; [L755] havoc is_transmit3_triggered_~__retres1~3; [L336] havoc is_transmit3_triggered_~__retres1~3; [L339-L348] assume !(1 == ~t3_pc~0); [L349] is_transmit3_triggered_~__retres1~3 := 0; [L351] is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; [L755] activate_threads_#t~ret11 := is_transmit3_triggered_#res; [L755] activate_threads_~tmp___2~0 := activate_threads_#t~ret11; [L755] havoc activate_threads_#t~ret11; [L757-L761] assume !(0 != activate_threads_~tmp___2~0); [L763] havoc is_transmit4_triggered_#res; [L763] havoc is_transmit4_triggered_~__retres1~4; [L355] havoc is_transmit4_triggered_~__retres1~4; [L358-L367] assume !(1 == ~t4_pc~0); [L368] is_transmit4_triggered_~__retres1~4 := 0; [L370] is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; [L763] activate_threads_#t~ret12 := is_transmit4_triggered_#res; [L763] activate_threads_~tmp___3~0 := activate_threads_#t~ret12; [L763] havoc activate_threads_#t~ret12; [L765-L769] assume !(0 != activate_threads_~tmp___3~0); [L771] havoc is_transmit5_triggered_#res; [L771] havoc is_transmit5_triggered_~__retres1~5; [L374] havoc is_transmit5_triggered_~__retres1~5; [L377-L386] assume !(1 == ~t5_pc~0); [L387] is_transmit5_triggered_~__retres1~5 := 0; [L389] is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; [L771] activate_threads_#t~ret13 := is_transmit5_triggered_#res; [L771] activate_threads_~tmp___4~0 := activate_threads_#t~ret13; [L771] havoc activate_threads_#t~ret13; [L773-L777] assume !(0 != activate_threads_~tmp___4~0); [L657-L661] assume !(1 == ~M_E~0); [L662-L666] assume !(1 == ~T1_E~0); [L667-L671] assume !(1 == ~T2_E~0); [L672-L676] assume !(1 == ~T3_E~0); [L677-L681] assume !(1 == ~T4_E~0); [L682-L686] assume !(1 == ~T5_E~0); [L687-L691] assume !(1 == ~E_M~0); [L692-L696] assume !(1 == ~E_1~0); [L697-L701] assume !(1 == ~E_2~0); [L702-L706] assume !(1 == ~E_3~0); [L707-L711] assume !(1 == ~E_4~0); [L712-L716] assume !(1 == ~E_5~0); [L918-L955] assume !false; [L921] start_simulation_~kernel_st~0 := 1; [L922] havoc eval_#t~ret1, eval_#t~nondet2, eval_~tmp_ndt_1~0, eval_#t~nondet3, eval_~tmp_ndt_2~0, eval_#t~nondet4, eval_~tmp_ndt_3~0, eval_#t~nondet5, eval_~tmp_ndt_4~0, eval_#t~nondet6, eval_~tmp_ndt_5~0, eval_#t~nondet7, eval_~tmp_ndt_6~0, eval_~tmp~0; [L480] havoc eval_~tmp~0; ----- ----- class de.uni_freiburg.informatik.ultimate.boogie.preprocessor.BoogiePreprocessorBacktranslator [L14] ~m_pc~0 := 0; [L15] ~t1_pc~0 := 0; [L16] ~t2_pc~0 := 0; [L17] ~t3_pc~0 := 0; [L18] ~t4_pc~0 := 0; [L19] ~t5_pc~0 := 0; [L20] ~m_st~0 := 0; [L21] ~t1_st~0 := 0; [L22] ~t2_st~0 := 0; [L23] ~t3_st~0 := 0; [L24] ~t4_st~0 := 0; [L25] ~t5_st~0 := 0; [L26] ~m_i~0 := 0; [L27] ~t1_i~0 := 0; [L28] ~t2_i~0 := 0; [L29] ~t3_i~0 := 0; [L30] ~t4_i~0 := 0; [L31] ~t5_i~0 := 0; [L32] ~M_E~0 := 2; [L33] ~T1_E~0 := 2; [L34] ~T2_E~0 := 2; [L35] ~T3_E~0 := 2; [L36] ~T4_E~0 := 2; [L37] ~T5_E~0 := 2; [L38] ~E_M~0 := 2; [L39] ~E_1~0 := 2; [L40] ~E_2~0 := 2; [L41] ~E_3~0 := 2; [L42] ~E_4~0 := 2; [L43] ~E_5~0 := 2; [L51] ~token~0 := 0; [L53] ~local~0 := 0; [?] havoc main_#res; [?] havoc main_~__retres1~7; [L963] havoc main_~__retres1~7; [L874] ~m_i~0 := 1; [L875] ~t1_i~0 := 1; [L876] ~t2_i~0 := 1; [L877] ~t3_i~0 := 1; [L878] ~t4_i~0 := 1; [L879] ~t5_i~0 := 1; [L968] havoc start_simulation_#t~ret15, start_simulation_#t~ret16, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1; [L904] havoc start_simulation_~kernel_st~0; [L905] havoc start_simulation_~tmp~3; [L906] havoc start_simulation_~tmp___0~1; [L910] start_simulation_~kernel_st~0 := 0; [L404-L408] assume 1 == ~m_i~0; [L405] ~m_st~0 := 0; [L409-L413] assume 1 == ~t1_i~0; [L410] ~t1_st~0 := 0; [L414-L418] assume 1 == ~t2_i~0; [L415] ~t2_st~0 := 0; [L419-L423] assume 1 == ~t3_i~0; [L420] ~t3_st~0 := 0; [L424-L428] assume 1 == ~t4_i~0; [L425] ~t4_st~0 := 0; [L429-L433] assume 1 == ~t5_i~0; [L430] ~t5_st~0 := 0; [L589-L593] assume !(0 == ~M_E~0); [L594-L598] assume !(0 == ~T1_E~0); [L599-L603] assume !(0 == ~T2_E~0); [L604-L608] assume !(0 == ~T3_E~0); [L609-L613] assume !(0 == ~T4_E~0); [L614-L618] assume !(0 == ~T5_E~0); [L619-L623] assume !(0 == ~E_M~0); [L624-L628] assume !(0 == ~E_1~0); [L629-L633] assume !(0 == ~E_2~0); [L634-L638] assume !(0 == ~E_3~0); [L639-L643] assume !(0 == ~E_4~0); [L644-L648] assume !(0 == ~E_5~0); [L914] havoc activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0; [L722] havoc activate_threads_~tmp~1; [L723] havoc activate_threads_~tmp___0~0; [L724] havoc activate_threads_~tmp___1~0; [L725] havoc activate_threads_~tmp___2~0; [L726] havoc activate_threads_~tmp___3~0; [L727] havoc activate_threads_~tmp___4~0; [L731] havoc is_master_triggered_#res; [L731] havoc is_master_triggered_~__retres1~0; [L279] havoc is_master_triggered_~__retres1~0; [L282-L291] assume !(1 == ~m_pc~0); [L292] is_master_triggered_~__retres1~0 := 0; [L294] is_master_triggered_#res := is_master_triggered_~__retres1~0; [L731] activate_threads_#t~ret8 := is_master_triggered_#res; [L731] activate_threads_~tmp~1 := activate_threads_#t~ret8; [L731] havoc activate_threads_#t~ret8; [L733-L737] assume !(0 != activate_threads_~tmp~1); [L739] havoc is_transmit1_triggered_#res; [L739] havoc is_transmit1_triggered_~__retres1~1; [L298] havoc is_transmit1_triggered_~__retres1~1; [L301-L310] assume !(1 == ~t1_pc~0); [L311] is_transmit1_triggered_~__retres1~1 := 0; [L313] is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; [L739] activate_threads_#t~ret9 := is_transmit1_triggered_#res; [L739] activate_threads_~tmp___0~0 := activate_threads_#t~ret9; [L739] havoc activate_threads_#t~ret9; [L741-L745] assume !(0 != activate_threads_~tmp___0~0); [L747] havoc is_transmit2_triggered_#res; [L747] havoc is_transmit2_triggered_~__retres1~2; [L317] havoc is_transmit2_triggered_~__retres1~2; [L320-L329] assume !(1 == ~t2_pc~0); [L330] is_transmit2_triggered_~__retres1~2 := 0; [L332] is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; [L747] activate_threads_#t~ret10 := is_transmit2_triggered_#res; [L747] activate_threads_~tmp___1~0 := activate_threads_#t~ret10; [L747] havoc activate_threads_#t~ret10; [L749-L753] assume !(0 != activate_threads_~tmp___1~0); [L755] havoc is_transmit3_triggered_#res; [L755] havoc is_transmit3_triggered_~__retres1~3; [L336] havoc is_transmit3_triggered_~__retres1~3; [L339-L348] assume !(1 == ~t3_pc~0); [L349] is_transmit3_triggered_~__retres1~3 := 0; [L351] is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; [L755] activate_threads_#t~ret11 := is_transmit3_triggered_#res; [L755] activate_threads_~tmp___2~0 := activate_threads_#t~ret11; [L755] havoc activate_threads_#t~ret11; [L757-L761] assume !(0 != activate_threads_~tmp___2~0); [L763] havoc is_transmit4_triggered_#res; [L763] havoc is_transmit4_triggered_~__retres1~4; [L355] havoc is_transmit4_triggered_~__retres1~4; [L358-L367] assume !(1 == ~t4_pc~0); [L368] is_transmit4_triggered_~__retres1~4 := 0; [L370] is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; [L763] activate_threads_#t~ret12 := is_transmit4_triggered_#res; [L763] activate_threads_~tmp___3~0 := activate_threads_#t~ret12; [L763] havoc activate_threads_#t~ret12; [L765-L769] assume !(0 != activate_threads_~tmp___3~0); [L771] havoc is_transmit5_triggered_#res; [L771] havoc is_transmit5_triggered_~__retres1~5; [L374] havoc is_transmit5_triggered_~__retres1~5; [L377-L386] assume !(1 == ~t5_pc~0); [L387] is_transmit5_triggered_~__retres1~5 := 0; [L389] is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; [L771] activate_threads_#t~ret13 := is_transmit5_triggered_#res; [L771] activate_threads_~tmp___4~0 := activate_threads_#t~ret13; [L771] havoc activate_threads_#t~ret13; [L773-L777] assume !(0 != activate_threads_~tmp___4~0); [L657-L661] assume !(1 == ~M_E~0); [L662-L666] assume !(1 == ~T1_E~0); [L667-L671] assume !(1 == ~T2_E~0); [L672-L676] assume !(1 == ~T3_E~0); [L677-L681] assume !(1 == ~T4_E~0); [L682-L686] assume !(1 == ~T5_E~0); [L687-L691] assume !(1 == ~E_M~0); [L692-L696] assume !(1 == ~E_1~0); [L697-L701] assume !(1 == ~E_2~0); [L702-L706] assume !(1 == ~E_3~0); [L707-L711] assume !(1 == ~E_4~0); [L712-L716] assume !(1 == ~E_5~0); [L918-L955] assume !false; [L921] start_simulation_~kernel_st~0 := 1; [L922] havoc eval_#t~ret1, eval_#t~nondet2, eval_~tmp_ndt_1~0, eval_#t~nondet3, eval_~tmp_ndt_2~0, eval_#t~nondet4, eval_~tmp_ndt_3~0, eval_#t~nondet5, eval_~tmp_ndt_4~0, eval_#t~nondet6, eval_~tmp_ndt_5~0, eval_#t~nondet7, eval_~tmp_ndt_6~0, eval_~tmp~0; [L480] havoc eval_~tmp~0; [L14] ~m_pc~0 := 0; [L15] ~t1_pc~0 := 0; [L16] ~t2_pc~0 := 0; [L17] ~t3_pc~0 := 0; [L18] ~t4_pc~0 := 0; [L19] ~t5_pc~0 := 0; [L20] ~m_st~0 := 0; [L21] ~t1_st~0 := 0; [L22] ~t2_st~0 := 0; [L23] ~t3_st~0 := 0; [L24] ~t4_st~0 := 0; [L25] ~t5_st~0 := 0; [L26] ~m_i~0 := 0; [L27] ~t1_i~0 := 0; [L28] ~t2_i~0 := 0; [L29] ~t3_i~0 := 0; [L30] ~t4_i~0 := 0; [L31] ~t5_i~0 := 0; [L32] ~M_E~0 := 2; [L33] ~T1_E~0 := 2; [L34] ~T2_E~0 := 2; [L35] ~T3_E~0 := 2; [L36] ~T4_E~0 := 2; [L37] ~T5_E~0 := 2; [L38] ~E_M~0 := 2; [L39] ~E_1~0 := 2; [L40] ~E_2~0 := 2; [L41] ~E_3~0 := 2; [L42] ~E_4~0 := 2; [L43] ~E_5~0 := 2; [L51] ~token~0 := 0; [L53] ~local~0 := 0; [?] havoc main_#res; [?] havoc main_~__retres1~7; [L963] havoc main_~__retres1~7; [L874] ~m_i~0 := 1; [L875] ~t1_i~0 := 1; [L876] ~t2_i~0 := 1; [L877] ~t3_i~0 := 1; [L878] ~t4_i~0 := 1; [L879] ~t5_i~0 := 1; [L968] havoc start_simulation_#t~ret15, start_simulation_#t~ret16, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1; [L904] havoc start_simulation_~kernel_st~0; [L905] havoc start_simulation_~tmp~3; [L906] havoc start_simulation_~tmp___0~1; [L910] start_simulation_~kernel_st~0 := 0; [L404] COND TRUE 1 == ~m_i~0 [L405] ~m_st~0 := 0; [L409] COND TRUE 1 == ~t1_i~0 [L410] ~t1_st~0 := 0; [L414] COND TRUE 1 == ~t2_i~0 [L415] ~t2_st~0 := 0; [L419] COND TRUE 1 == ~t3_i~0 [L420] ~t3_st~0 := 0; [L424] COND TRUE 1 == ~t4_i~0 [L425] ~t4_st~0 := 0; [L429] COND TRUE 1 == ~t5_i~0 [L430] ~t5_st~0 := 0; [L589] COND FALSE !(0 == ~M_E~0) [L594] COND FALSE !(0 == ~T1_E~0) [L599] COND FALSE !(0 == ~T2_E~0) [L604] COND FALSE !(0 == ~T3_E~0) [L609] COND FALSE !(0 == ~T4_E~0) [L614] COND FALSE !(0 == ~T5_E~0) [L619] COND FALSE !(0 == ~E_M~0) [L624] COND FALSE !(0 == ~E_1~0) [L629] COND FALSE !(0 == ~E_2~0) [L634] COND FALSE !(0 == ~E_3~0) [L639] COND FALSE !(0 == ~E_4~0) [L644] COND FALSE !(0 == ~E_5~0) [L914] havoc activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0; [L722] havoc activate_threads_~tmp~1; [L723] havoc activate_threads_~tmp___0~0; [L724] havoc activate_threads_~tmp___1~0; [L725] havoc activate_threads_~tmp___2~0; [L726] havoc activate_threads_~tmp___3~0; [L727] havoc activate_threads_~tmp___4~0; [L731] havoc is_master_triggered_#res; [L731] havoc is_master_triggered_~__retres1~0; [L279] havoc is_master_triggered_~__retres1~0; [L282] COND FALSE !(1 == ~m_pc~0) [L292] is_master_triggered_~__retres1~0 := 0; [L294] is_master_triggered_#res := is_master_triggered_~__retres1~0; [L731] activate_threads_#t~ret8 := is_master_triggered_#res; [L731] activate_threads_~tmp~1 := activate_threads_#t~ret8; [L731] havoc activate_threads_#t~ret8; [L733-L737] COND FALSE !(0 != activate_threads_~tmp~1) [L739] havoc is_transmit1_triggered_#res; [L739] havoc is_transmit1_triggered_~__retres1~1; [L298] havoc is_transmit1_triggered_~__retres1~1; [L301] COND FALSE !(1 == ~t1_pc~0) [L311] is_transmit1_triggered_~__retres1~1 := 0; [L313] is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; [L739] activate_threads_#t~ret9 := is_transmit1_triggered_#res; [L739] activate_threads_~tmp___0~0 := activate_threads_#t~ret9; [L739] havoc activate_threads_#t~ret9; [L741-L745] COND FALSE !(0 != activate_threads_~tmp___0~0) [L747] havoc is_transmit2_triggered_#res; [L747] havoc is_transmit2_triggered_~__retres1~2; [L317] havoc is_transmit2_triggered_~__retres1~2; [L320] COND FALSE !(1 == ~t2_pc~0) [L330] is_transmit2_triggered_~__retres1~2 := 0; [L332] is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; [L747] activate_threads_#t~ret10 := is_transmit2_triggered_#res; [L747] activate_threads_~tmp___1~0 := activate_threads_#t~ret10; [L747] havoc activate_threads_#t~ret10; [L749-L753] COND FALSE !(0 != activate_threads_~tmp___1~0) [L755] havoc is_transmit3_triggered_#res; [L755] havoc is_transmit3_triggered_~__retres1~3; [L336] havoc is_transmit3_triggered_~__retres1~3; [L339] COND FALSE !(1 == ~t3_pc~0) [L349] is_transmit3_triggered_~__retres1~3 := 0; [L351] is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; [L755] activate_threads_#t~ret11 := is_transmit3_triggered_#res; [L755] activate_threads_~tmp___2~0 := activate_threads_#t~ret11; [L755] havoc activate_threads_#t~ret11; [L757-L761] COND FALSE !(0 != activate_threads_~tmp___2~0) [L763] havoc is_transmit4_triggered_#res; [L763] havoc is_transmit4_triggered_~__retres1~4; [L355] havoc is_transmit4_triggered_~__retres1~4; [L358] COND FALSE !(1 == ~t4_pc~0) [L368] is_transmit4_triggered_~__retres1~4 := 0; [L370] is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; [L763] activate_threads_#t~ret12 := is_transmit4_triggered_#res; [L763] activate_threads_~tmp___3~0 := activate_threads_#t~ret12; [L763] havoc activate_threads_#t~ret12; [L765-L769] COND FALSE !(0 != activate_threads_~tmp___3~0) [L771] havoc is_transmit5_triggered_#res; [L771] havoc is_transmit5_triggered_~__retres1~5; [L374] havoc is_transmit5_triggered_~__retres1~5; [L377] COND FALSE !(1 == ~t5_pc~0) [L387] is_transmit5_triggered_~__retres1~5 := 0; [L389] is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; [L771] activate_threads_#t~ret13 := is_transmit5_triggered_#res; [L771] activate_threads_~tmp___4~0 := activate_threads_#t~ret13; [L771] havoc activate_threads_#t~ret13; [L773-L777] COND FALSE !(0 != activate_threads_~tmp___4~0) [L657] COND FALSE !(1 == ~M_E~0) [L662] COND FALSE !(1 == ~T1_E~0) [L667] COND FALSE !(1 == ~T2_E~0) [L672] COND FALSE !(1 == ~T3_E~0) [L677] COND FALSE !(1 == ~T4_E~0) [L682] COND FALSE !(1 == ~T5_E~0) [L687] COND FALSE !(1 == ~E_M~0) [L692] COND FALSE !(1 == ~E_1~0) [L697] COND FALSE !(1 == ~E_2~0) [L702] COND FALSE !(1 == ~E_3~0) [L707] COND FALSE !(1 == ~E_4~0) [L712] COND FALSE !(1 == ~E_5~0) [L918-L955] COND FALSE !(false) [L921] start_simulation_~kernel_st~0 := 1; [L922] havoc eval_#t~ret1, eval_#t~nondet2, eval_~tmp_ndt_1~0, eval_#t~nondet3, eval_~tmp_ndt_2~0, eval_#t~nondet4, eval_~tmp_ndt_3~0, eval_#t~nondet5, eval_~tmp_ndt_4~0, eval_#t~nondet6, eval_~tmp_ndt_5~0, eval_#t~nondet7, eval_~tmp_ndt_6~0, eval_~tmp~0; [L480] havoc eval_~tmp~0; ----- ----- class de.uni_freiburg.informatik.ultimate.boogie.procedureinliner.backtranslation.InlinerBacktranslator [L14] ~m_pc~0 := 0; [L15] ~t1_pc~0 := 0; [L16] ~t2_pc~0 := 0; [L17] ~t3_pc~0 := 0; [L18] ~t4_pc~0 := 0; [L19] ~t5_pc~0 := 0; [L20] ~m_st~0 := 0; [L21] ~t1_st~0 := 0; [L22] ~t2_st~0 := 0; [L23] ~t3_st~0 := 0; [L24] ~t4_st~0 := 0; [L25] ~t5_st~0 := 0; [L26] ~m_i~0 := 0; [L27] ~t1_i~0 := 0; [L28] ~t2_i~0 := 0; [L29] ~t3_i~0 := 0; [L30] ~t4_i~0 := 0; [L31] ~t5_i~0 := 0; [L32] ~M_E~0 := 2; [L33] ~T1_E~0 := 2; [L34] ~T2_E~0 := 2; [L35] ~T3_E~0 := 2; [L36] ~T4_E~0 := 2; [L37] ~T5_E~0 := 2; [L38] ~E_M~0 := 2; [L39] ~E_1~0 := 2; [L40] ~E_2~0 := 2; [L41] ~E_3~0 := 2; [L42] ~E_4~0 := 2; [L43] ~E_5~0 := 2; [L51] ~token~0 := 0; [L53] ~local~0 := 0; [?] havoc main_#res; [?] havoc main_~__retres1~7; [L963] havoc main_~__retres1~7; [L874] ~m_i~0 := 1; [L875] ~t1_i~0 := 1; [L876] ~t2_i~0 := 1; [L877] ~t3_i~0 := 1; [L878] ~t4_i~0 := 1; [L879] ~t5_i~0 := 1; [L968] havoc start_simulation_#t~ret15, start_simulation_#t~ret16, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1; [L904] havoc start_simulation_~kernel_st~0; [L905] havoc start_simulation_~tmp~3; [L906] havoc start_simulation_~tmp___0~1; [L910] start_simulation_~kernel_st~0 := 0; [L404] COND TRUE 1 == ~m_i~0 [L405] ~m_st~0 := 0; [L409] COND TRUE 1 == ~t1_i~0 [L410] ~t1_st~0 := 0; [L414] COND TRUE 1 == ~t2_i~0 [L415] ~t2_st~0 := 0; [L419] COND TRUE 1 == ~t3_i~0 [L420] ~t3_st~0 := 0; [L424] COND TRUE 1 == ~t4_i~0 [L425] ~t4_st~0 := 0; [L429] COND TRUE 1 == ~t5_i~0 [L430] ~t5_st~0 := 0; [L589] COND FALSE !(0 == ~M_E~0) [L594] COND FALSE !(0 == ~T1_E~0) [L599] COND FALSE !(0 == ~T2_E~0) [L604] COND FALSE !(0 == ~T3_E~0) [L609] COND FALSE !(0 == ~T4_E~0) [L614] COND FALSE !(0 == ~T5_E~0) [L619] COND FALSE !(0 == ~E_M~0) [L624] COND FALSE !(0 == ~E_1~0) [L629] COND FALSE !(0 == ~E_2~0) [L634] COND FALSE !(0 == ~E_3~0) [L639] COND FALSE !(0 == ~E_4~0) [L644] COND FALSE !(0 == ~E_5~0) [L914] havoc activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0; [L722] havoc activate_threads_~tmp~1; [L723] havoc activate_threads_~tmp___0~0; [L724] havoc activate_threads_~tmp___1~0; [L725] havoc activate_threads_~tmp___2~0; [L726] havoc activate_threads_~tmp___3~0; [L727] havoc activate_threads_~tmp___4~0; [L731] havoc is_master_triggered_#res; [L731] havoc is_master_triggered_~__retres1~0; [L279] havoc is_master_triggered_~__retres1~0; [L282] COND FALSE !(1 == ~m_pc~0) [L292] is_master_triggered_~__retres1~0 := 0; [L294] is_master_triggered_#res := is_master_triggered_~__retres1~0; [L731] activate_threads_#t~ret8 := is_master_triggered_#res; [L731] activate_threads_~tmp~1 := activate_threads_#t~ret8; [L731] havoc activate_threads_#t~ret8; [L733-L737] COND FALSE !(0 != activate_threads_~tmp~1) [L739] havoc is_transmit1_triggered_#res; [L739] havoc is_transmit1_triggered_~__retres1~1; [L298] havoc is_transmit1_triggered_~__retres1~1; [L301] COND FALSE !(1 == ~t1_pc~0) [L311] is_transmit1_triggered_~__retres1~1 := 0; [L313] is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; [L739] activate_threads_#t~ret9 := is_transmit1_triggered_#res; [L739] activate_threads_~tmp___0~0 := activate_threads_#t~ret9; [L739] havoc activate_threads_#t~ret9; [L741-L745] COND FALSE !(0 != activate_threads_~tmp___0~0) [L747] havoc is_transmit2_triggered_#res; [L747] havoc is_transmit2_triggered_~__retres1~2; [L317] havoc is_transmit2_triggered_~__retres1~2; [L320] COND FALSE !(1 == ~t2_pc~0) [L330] is_transmit2_triggered_~__retres1~2 := 0; [L332] is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; [L747] activate_threads_#t~ret10 := is_transmit2_triggered_#res; [L747] activate_threads_~tmp___1~0 := activate_threads_#t~ret10; [L747] havoc activate_threads_#t~ret10; [L749-L753] COND FALSE !(0 != activate_threads_~tmp___1~0) [L755] havoc is_transmit3_triggered_#res; [L755] havoc is_transmit3_triggered_~__retres1~3; [L336] havoc is_transmit3_triggered_~__retres1~3; [L339] COND FALSE !(1 == ~t3_pc~0) [L349] is_transmit3_triggered_~__retres1~3 := 0; [L351] is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; [L755] activate_threads_#t~ret11 := is_transmit3_triggered_#res; [L755] activate_threads_~tmp___2~0 := activate_threads_#t~ret11; [L755] havoc activate_threads_#t~ret11; [L757-L761] COND FALSE !(0 != activate_threads_~tmp___2~0) [L763] havoc is_transmit4_triggered_#res; [L763] havoc is_transmit4_triggered_~__retres1~4; [L355] havoc is_transmit4_triggered_~__retres1~4; [L358] COND FALSE !(1 == ~t4_pc~0) [L368] is_transmit4_triggered_~__retres1~4 := 0; [L370] is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; [L763] activate_threads_#t~ret12 := is_transmit4_triggered_#res; [L763] activate_threads_~tmp___3~0 := activate_threads_#t~ret12; [L763] havoc activate_threads_#t~ret12; [L765-L769] COND FALSE !(0 != activate_threads_~tmp___3~0) [L771] havoc is_transmit5_triggered_#res; [L771] havoc is_transmit5_triggered_~__retres1~5; [L374] havoc is_transmit5_triggered_~__retres1~5; [L377] COND FALSE !(1 == ~t5_pc~0) [L387] is_transmit5_triggered_~__retres1~5 := 0; [L389] is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; [L771] activate_threads_#t~ret13 := is_transmit5_triggered_#res; [L771] activate_threads_~tmp___4~0 := activate_threads_#t~ret13; [L771] havoc activate_threads_#t~ret13; [L773-L777] COND FALSE !(0 != activate_threads_~tmp___4~0) [L657] COND FALSE !(1 == ~M_E~0) [L662] COND FALSE !(1 == ~T1_E~0) [L667] COND FALSE !(1 == ~T2_E~0) [L672] COND FALSE !(1 == ~T3_E~0) [L677] COND FALSE !(1 == ~T4_E~0) [L682] COND FALSE !(1 == ~T5_E~0) [L687] COND FALSE !(1 == ~E_M~0) [L692] COND FALSE !(1 == ~E_1~0) [L697] COND FALSE !(1 == ~E_2~0) [L702] COND FALSE !(1 == ~E_3~0) [L707] COND FALSE !(1 == ~E_4~0) [L712] COND FALSE !(1 == ~E_5~0) [L918-L955] COND FALSE !(false) [L921] start_simulation_~kernel_st~0 := 1; [L922] havoc eval_#t~ret1, eval_#t~nondet2, eval_~tmp_ndt_1~0, eval_#t~nondet3, eval_~tmp_ndt_2~0, eval_#t~nondet4, eval_~tmp_ndt_3~0, eval_#t~nondet5, eval_~tmp_ndt_4~0, eval_#t~nondet6, eval_~tmp_ndt_5~0, eval_#t~nondet7, eval_~tmp_ndt_6~0, eval_~tmp~0; [L480] havoc eval_~tmp~0; [L14] ~m_pc~0 := 0; [L15] ~t1_pc~0 := 0; [L16] ~t2_pc~0 := 0; [L17] ~t3_pc~0 := 0; [L18] ~t4_pc~0 := 0; [L19] ~t5_pc~0 := 0; [L20] ~m_st~0 := 0; [L21] ~t1_st~0 := 0; [L22] ~t2_st~0 := 0; [L23] ~t3_st~0 := 0; [L24] ~t4_st~0 := 0; [L25] ~t5_st~0 := 0; [L26] ~m_i~0 := 0; [L27] ~t1_i~0 := 0; [L28] ~t2_i~0 := 0; [L29] ~t3_i~0 := 0; [L30] ~t4_i~0 := 0; [L31] ~t5_i~0 := 0; [L32] ~M_E~0 := 2; [L33] ~T1_E~0 := 2; [L34] ~T2_E~0 := 2; [L35] ~T3_E~0 := 2; [L36] ~T4_E~0 := 2; [L37] ~T5_E~0 := 2; [L38] ~E_M~0 := 2; [L39] ~E_1~0 := 2; [L40] ~E_2~0 := 2; [L41] ~E_3~0 := 2; [L42] ~E_4~0 := 2; [L43] ~E_5~0 := 2; [L51] ~token~0 := 0; [L53] ~local~0 := 0; [L963] havoc ~__retres1~7; [L874] ~m_i~0 := 1; [L875] ~t1_i~0 := 1; [L876] ~t2_i~0 := 1; [L877] ~t3_i~0 := 1; [L878] ~t4_i~0 := 1; [L879] ~t5_i~0 := 1; [L904] havoc ~kernel_st~0; [L905] havoc ~tmp~3; [L906] havoc ~tmp___0~1; [L910] ~kernel_st~0 := 0; [L404] COND TRUE 1 == ~m_i~0 [L405] ~m_st~0 := 0; [L409] COND TRUE 1 == ~t1_i~0 [L410] ~t1_st~0 := 0; [L414] COND TRUE 1 == ~t2_i~0 [L415] ~t2_st~0 := 0; [L419] COND TRUE 1 == ~t3_i~0 [L420] ~t3_st~0 := 0; [L424] COND TRUE 1 == ~t4_i~0 [L425] ~t4_st~0 := 0; [L429] COND TRUE 1 == ~t5_i~0 [L430] ~t5_st~0 := 0; [L589] COND FALSE !(0 == ~M_E~0) [L594] COND FALSE !(0 == ~T1_E~0) [L599] COND FALSE !(0 == ~T2_E~0) [L604] COND FALSE !(0 == ~T3_E~0) [L609] COND FALSE !(0 == ~T4_E~0) [L614] COND FALSE !(0 == ~T5_E~0) [L619] COND FALSE !(0 == ~E_M~0) [L624] COND FALSE !(0 == ~E_1~0) [L629] COND FALSE !(0 == ~E_2~0) [L634] COND FALSE !(0 == ~E_3~0) [L639] COND FALSE !(0 == ~E_4~0) [L644] COND FALSE !(0 == ~E_5~0) [L722] havoc ~tmp~1; [L723] havoc ~tmp___0~0; [L724] havoc ~tmp___1~0; [L725] havoc ~tmp___2~0; [L726] havoc ~tmp___3~0; [L727] havoc ~tmp___4~0; [L279] havoc ~__retres1~0; [L282] COND FALSE !(1 == ~m_pc~0) [L292] ~__retres1~0 := 0; [L294] #res := ~__retres1~0; [L731] ~tmp~1 := #t~ret8; [L731] havoc #t~ret8; [L733-L737] COND FALSE !(0 != ~tmp~1) [L298] havoc ~__retres1~1; [L301] COND FALSE !(1 == ~t1_pc~0) [L311] ~__retres1~1 := 0; [L313] #res := ~__retres1~1; [L739] ~tmp___0~0 := #t~ret9; [L739] havoc #t~ret9; [L741-L745] COND FALSE !(0 != ~tmp___0~0) [L317] havoc ~__retres1~2; [L320] COND FALSE !(1 == ~t2_pc~0) [L330] ~__retres1~2 := 0; [L332] #res := ~__retres1~2; [L747] ~tmp___1~0 := #t~ret10; [L747] havoc #t~ret10; [L749-L753] COND FALSE !(0 != ~tmp___1~0) [L336] havoc ~__retres1~3; [L339] COND FALSE !(1 == ~t3_pc~0) [L349] ~__retres1~3 := 0; [L351] #res := ~__retres1~3; [L755] ~tmp___2~0 := #t~ret11; [L755] havoc #t~ret11; [L757-L761] COND FALSE !(0 != ~tmp___2~0) [L355] havoc ~__retres1~4; [L358] COND FALSE !(1 == ~t4_pc~0) [L368] ~__retres1~4 := 0; [L370] #res := ~__retres1~4; [L763] ~tmp___3~0 := #t~ret12; [L763] havoc #t~ret12; [L765-L769] COND FALSE !(0 != ~tmp___3~0) [L374] havoc ~__retres1~5; [L377] COND FALSE !(1 == ~t5_pc~0) [L387] ~__retres1~5 := 0; [L389] #res := ~__retres1~5; [L771] ~tmp___4~0 := #t~ret13; [L771] havoc #t~ret13; [L773-L777] COND FALSE !(0 != ~tmp___4~0) [L657] COND FALSE !(1 == ~M_E~0) [L662] COND FALSE !(1 == ~T1_E~0) [L667] COND FALSE !(1 == ~T2_E~0) [L672] COND FALSE !(1 == ~T3_E~0) [L677] COND FALSE !(1 == ~T4_E~0) [L682] COND FALSE !(1 == ~T5_E~0) [L687] COND FALSE !(1 == ~E_M~0) [L692] COND FALSE !(1 == ~E_1~0) [L697] COND FALSE !(1 == ~E_2~0) [L702] COND FALSE !(1 == ~E_3~0) [L707] COND FALSE !(1 == ~E_4~0) [L712] COND FALSE !(1 == ~E_5~0) [L918-L955] COND FALSE !(false) [L921] ~kernel_st~0 := 1; [L480] havoc ~tmp~0; ----- ----- class de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.CACSL2BoogieBacktranslator [L14] ~m_pc~0 := 0; [L15] ~t1_pc~0 := 0; [L16] ~t2_pc~0 := 0; [L17] ~t3_pc~0 := 0; [L18] ~t4_pc~0 := 0; [L19] ~t5_pc~0 := 0; [L20] ~m_st~0 := 0; [L21] ~t1_st~0 := 0; [L22] ~t2_st~0 := 0; [L23] ~t3_st~0 := 0; [L24] ~t4_st~0 := 0; [L25] ~t5_st~0 := 0; [L26] ~m_i~0 := 0; [L27] ~t1_i~0 := 0; [L28] ~t2_i~0 := 0; [L29] ~t3_i~0 := 0; [L30] ~t4_i~0 := 0; [L31] ~t5_i~0 := 0; [L32] ~M_E~0 := 2; [L33] ~T1_E~0 := 2; [L34] ~T2_E~0 := 2; [L35] ~T3_E~0 := 2; [L36] ~T4_E~0 := 2; [L37] ~T5_E~0 := 2; [L38] ~E_M~0 := 2; [L39] ~E_1~0 := 2; [L40] ~E_2~0 := 2; [L41] ~E_3~0 := 2; [L42] ~E_4~0 := 2; [L43] ~E_5~0 := 2; [L51] ~token~0 := 0; [L53] ~local~0 := 0; [L963] havoc ~__retres1~7; [L874] ~m_i~0 := 1; [L875] ~t1_i~0 := 1; [L876] ~t2_i~0 := 1; [L877] ~t3_i~0 := 1; [L878] ~t4_i~0 := 1; [L879] ~t5_i~0 := 1; [L904] havoc ~kernel_st~0; [L905] havoc ~tmp~3; [L906] havoc ~tmp___0~1; [L910] ~kernel_st~0 := 0; [L404] COND TRUE 1 == ~m_i~0 [L405] ~m_st~0 := 0; [L409] COND TRUE 1 == ~t1_i~0 [L410] ~t1_st~0 := 0; [L414] COND TRUE 1 == ~t2_i~0 [L415] ~t2_st~0 := 0; [L419] COND TRUE 1 == ~t3_i~0 [L420] ~t3_st~0 := 0; [L424] COND TRUE 1 == ~t4_i~0 [L425] ~t4_st~0 := 0; [L429] COND TRUE 1 == ~t5_i~0 [L430] ~t5_st~0 := 0; [L589] COND FALSE !(0 == ~M_E~0) [L594] COND FALSE !(0 == ~T1_E~0) [L599] COND FALSE !(0 == ~T2_E~0) [L604] COND FALSE !(0 == ~T3_E~0) [L609] COND FALSE !(0 == ~T4_E~0) [L614] COND FALSE !(0 == ~T5_E~0) [L619] COND FALSE !(0 == ~E_M~0) [L624] COND FALSE !(0 == ~E_1~0) [L629] COND FALSE !(0 == ~E_2~0) [L634] COND FALSE !(0 == ~E_3~0) [L639] COND FALSE !(0 == ~E_4~0) [L644] COND FALSE !(0 == ~E_5~0) [L722] havoc ~tmp~1; [L723] havoc ~tmp___0~0; [L724] havoc ~tmp___1~0; [L725] havoc ~tmp___2~0; [L726] havoc ~tmp___3~0; [L727] havoc ~tmp___4~0; [L279] havoc ~__retres1~0; [L282] COND FALSE !(1 == ~m_pc~0) [L292] ~__retres1~0 := 0; [L294] #res := ~__retres1~0; [L731] ~tmp~1 := #t~ret8; [L731] havoc #t~ret8; [L733-L737] COND FALSE !(0 != ~tmp~1) [L298] havoc ~__retres1~1; [L301] COND FALSE !(1 == ~t1_pc~0) [L311] ~__retres1~1 := 0; [L313] #res := ~__retres1~1; [L739] ~tmp___0~0 := #t~ret9; [L739] havoc #t~ret9; [L741-L745] COND FALSE !(0 != ~tmp___0~0) [L317] havoc ~__retres1~2; [L320] COND FALSE !(1 == ~t2_pc~0) [L330] ~__retres1~2 := 0; [L332] #res := ~__retres1~2; [L747] ~tmp___1~0 := #t~ret10; [L747] havoc #t~ret10; [L749-L753] COND FALSE !(0 != ~tmp___1~0) [L336] havoc ~__retres1~3; [L339] COND FALSE !(1 == ~t3_pc~0) [L349] ~__retres1~3 := 0; [L351] #res := ~__retres1~3; [L755] ~tmp___2~0 := #t~ret11; [L755] havoc #t~ret11; [L757-L761] COND FALSE !(0 != ~tmp___2~0) [L355] havoc ~__retres1~4; [L358] COND FALSE !(1 == ~t4_pc~0) [L368] ~__retres1~4 := 0; [L370] #res := ~__retres1~4; [L763] ~tmp___3~0 := #t~ret12; [L763] havoc #t~ret12; [L765-L769] COND FALSE !(0 != ~tmp___3~0) [L374] havoc ~__retres1~5; [L377] COND FALSE !(1 == ~t5_pc~0) [L387] ~__retres1~5 := 0; [L389] #res := ~__retres1~5; [L771] ~tmp___4~0 := #t~ret13; [L771] havoc #t~ret13; [L773-L777] COND FALSE !(0 != ~tmp___4~0) [L657] COND FALSE !(1 == ~M_E~0) [L662] COND FALSE !(1 == ~T1_E~0) [L667] COND FALSE !(1 == ~T2_E~0) [L672] COND FALSE !(1 == ~T3_E~0) [L677] COND FALSE !(1 == ~T4_E~0) [L682] COND FALSE !(1 == ~T5_E~0) [L687] COND FALSE !(1 == ~E_M~0) [L692] COND FALSE !(1 == ~E_1~0) [L697] COND FALSE !(1 == ~E_2~0) [L702] COND FALSE !(1 == ~E_3~0) [L707] COND FALSE !(1 == ~E_4~0) [L712] COND FALSE !(1 == ~E_5~0) [L918-L955] COND FALSE !(false) [L921] ~kernel_st~0 := 1; [L480] havoc ~tmp~0; [L14] int m_pc = 0; [L15] int t1_pc = 0; [L16] int t2_pc = 0; [L17] int t3_pc = 0; [L18] int t4_pc = 0; [L19] int t5_pc = 0; [L20] int m_st ; [L21] int t1_st ; [L22] int t2_st ; [L23] int t3_st ; [L24] int t4_st ; [L25] int t5_st ; [L26] int m_i ; [L27] int t1_i ; [L28] int t2_i ; [L29] int t3_i ; [L30] int t4_i ; [L31] int t5_i ; [L32] int M_E = 2; [L33] int T1_E = 2; [L34] int T2_E = 2; [L35] int T3_E = 2; [L36] int T4_E = 2; [L37] int T5_E = 2; [L38] int E_M = 2; [L39] int E_1 = 2; [L40] int E_2 = 2; [L41] int E_3 = 2; [L42] int E_4 = 2; [L43] int E_5 = 2; [L51] int token ; [L53] int local ; [L963] int __retres1 ; [L874] m_i = 1 [L875] t1_i = 1 [L876] t2_i = 1 [L877] t3_i = 1 [L878] t4_i = 1 [L879] t5_i = 1 [L904] int kernel_st ; [L905] int tmp ; [L906] int tmp___0 ; [L910] kernel_st = 0 [L404] COND TRUE m_i == 1 [L405] m_st = 0 [L409] COND TRUE t1_i == 1 [L410] t1_st = 0 [L414] COND TRUE t2_i == 1 [L415] t2_st = 0 [L419] COND TRUE t3_i == 1 [L420] t3_st = 0 [L424] COND TRUE t4_i == 1 [L425] t4_st = 0 [L429] COND TRUE t5_i == 1 [L430] t5_st = 0 [L589] COND FALSE !(M_E == 0) [L594] COND FALSE !(T1_E == 0) [L599] COND FALSE !(T2_E == 0) [L604] COND FALSE !(T3_E == 0) [L609] COND FALSE !(T4_E == 0) [L614] COND FALSE !(T5_E == 0) [L619] COND FALSE !(E_M == 0) [L624] COND FALSE !(E_1 == 0) [L629] COND FALSE !(E_2 == 0) [L634] COND FALSE !(E_3 == 0) [L639] COND FALSE !(E_4 == 0) [L644] COND FALSE !(E_5 == 0) [L722] int tmp ; [L723] int tmp___0 ; [L724] int tmp___1 ; [L725] int tmp___2 ; [L726] int tmp___3 ; [L727] int tmp___4 ; [L279] int __retres1 ; [L282] COND FALSE !(m_pc == 1) [L292] __retres1 = 0 [L294] return (__retres1); [L731] tmp = is_master_triggered() [L733] COND FALSE !(\read(tmp)) [L298] int __retres1 ; [L301] COND FALSE !(t1_pc == 1) [L311] __retres1 = 0 [L313] return (__retres1); [L739] tmp___0 = is_transmit1_triggered() [L741] COND FALSE !(\read(tmp___0)) [L317] int __retres1 ; [L320] COND FALSE !(t2_pc == 1) [L330] __retres1 = 0 [L332] return (__retres1); [L747] tmp___1 = is_transmit2_triggered() [L749] COND FALSE !(\read(tmp___1)) [L336] int __retres1 ; [L339] COND FALSE !(t3_pc == 1) [L349] __retres1 = 0 [L351] return (__retres1); [L755] tmp___2 = is_transmit3_triggered() [L757] COND FALSE !(\read(tmp___2)) [L355] int __retres1 ; [L358] COND FALSE !(t4_pc == 1) [L368] __retres1 = 0 [L370] return (__retres1); [L763] tmp___3 = is_transmit4_triggered() [L765] COND FALSE !(\read(tmp___3)) [L374] int __retres1 ; [L377] COND FALSE !(t5_pc == 1) [L387] __retres1 = 0 [L389] return (__retres1); [L771] tmp___4 = is_transmit5_triggered() [L773] COND FALSE !(\read(tmp___4)) [L657] COND FALSE !(M_E == 1) [L662] COND FALSE !(T1_E == 1) [L667] COND FALSE !(T2_E == 1) [L672] COND FALSE !(T3_E == 1) [L677] COND FALSE !(T4_E == 1) [L682] COND FALSE !(T5_E == 1) [L687] COND FALSE !(E_M == 1) [L692] COND FALSE !(E_1 == 1) [L697] COND FALSE !(E_2 == 1) [L702] COND FALSE !(E_3 == 1) [L707] COND FALSE !(E_4 == 1) [L712] COND FALSE !(E_5 == 1) [L918] COND TRUE 1 [L921] kernel_st = 1 [L480] int tmp ; ----- ----- class de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder.RCFGBacktranslator [?] assume !false; [?] havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; [?] assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; [?] exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; [?] eval_#t~ret1 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret1;havoc eval_#t~ret1; [?] assume 0 != eval_~tmp~0; [?] assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0;eval_~tmp_ndt_1~0 := eval_#t~nondet2;havoc eval_#t~nondet2; [?] assume !(0 != eval_~tmp_ndt_1~0); [?] assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0;eval_~tmp_ndt_2~0 := eval_#t~nondet3;havoc eval_#t~nondet3; [?] assume !(0 != eval_~tmp_ndt_2~0); [?] assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0;eval_~tmp_ndt_3~0 := eval_#t~nondet4;havoc eval_#t~nondet4; [?] assume !(0 != eval_~tmp_ndt_3~0); [?] assume 0 == ~t3_st~0;havoc eval_~tmp_ndt_4~0;eval_~tmp_ndt_4~0 := eval_#t~nondet5;havoc eval_#t~nondet5; [?] assume !(0 != eval_~tmp_ndt_4~0); [?] assume 0 == ~t4_st~0;havoc eval_~tmp_ndt_5~0;eval_~tmp_ndt_5~0 := eval_#t~nondet6;havoc eval_#t~nondet6; [?] assume !(0 != eval_~tmp_ndt_5~0); [?] assume 0 == ~t5_st~0;havoc eval_~tmp_ndt_6~0;eval_~tmp_ndt_6~0 := eval_#t~nondet7;havoc eval_#t~nondet7; [?] assume !(0 != eval_~tmp_ndt_6~0); [L484-L578] assume !false; [L487] havoc exists_runnable_thread_#res; [L487] havoc exists_runnable_thread_~__retres1~6; [L439] havoc exists_runnable_thread_~__retres1~6; [L442-L472] assume 0 == ~m_st~0; [L443] exists_runnable_thread_~__retres1~6 := 1; [L475] exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; [L487] eval_#t~ret1 := exists_runnable_thread_#res; [L487] eval_~tmp~0 := eval_#t~ret1; [L487] havoc eval_#t~ret1; [L489-L493] assume 0 != eval_~tmp~0; [L494-L507] assume 0 == ~m_st~0; [L495] havoc eval_~tmp_ndt_1~0; [L496] eval_~tmp_ndt_1~0 := eval_#t~nondet2; [L496] havoc eval_#t~nondet2; [L497-L504] assume !(0 != eval_~tmp_ndt_1~0); [L508-L521] assume 0 == ~t1_st~0; [L509] havoc eval_~tmp_ndt_2~0; [L510] eval_~tmp_ndt_2~0 := eval_#t~nondet3; [L510] havoc eval_#t~nondet3; [L511-L518] assume !(0 != eval_~tmp_ndt_2~0); [L522-L535] assume 0 == ~t2_st~0; [L523] havoc eval_~tmp_ndt_3~0; [L524] eval_~tmp_ndt_3~0 := eval_#t~nondet4; [L524] havoc eval_#t~nondet4; [L525-L532] assume !(0 != eval_~tmp_ndt_3~0); [L536-L549] assume 0 == ~t3_st~0; [L537] havoc eval_~tmp_ndt_4~0; [L538] eval_~tmp_ndt_4~0 := eval_#t~nondet5; [L538] havoc eval_#t~nondet5; [L539-L546] assume !(0 != eval_~tmp_ndt_4~0); [L550-L563] assume 0 == ~t4_st~0; [L551] havoc eval_~tmp_ndt_5~0; [L552] eval_~tmp_ndt_5~0 := eval_#t~nondet6; [L552] havoc eval_#t~nondet6; [L553-L560] assume !(0 != eval_~tmp_ndt_5~0); [L564-L577] assume 0 == ~t5_st~0; [L565] havoc eval_~tmp_ndt_6~0; [L566] eval_~tmp_ndt_6~0 := eval_#t~nondet7; [L566] havoc eval_#t~nondet7; [L567-L574] assume !(0 != eval_~tmp_ndt_6~0); ----- ----- class de.uni_freiburg.informatik.ultimate.boogie.preprocessor.BoogiePreprocessorBacktranslator [L484-L578] assume !false; [L487] havoc exists_runnable_thread_#res; [L487] havoc exists_runnable_thread_~__retres1~6; [L439] havoc exists_runnable_thread_~__retres1~6; [L442-L472] assume 0 == ~m_st~0; [L443] exists_runnable_thread_~__retres1~6 := 1; [L475] exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; [L487] eval_#t~ret1 := exists_runnable_thread_#res; [L487] eval_~tmp~0 := eval_#t~ret1; [L487] havoc eval_#t~ret1; [L489-L493] assume 0 != eval_~tmp~0; [L494-L507] assume 0 == ~m_st~0; [L495] havoc eval_~tmp_ndt_1~0; [L496] eval_~tmp_ndt_1~0 := eval_#t~nondet2; [L496] havoc eval_#t~nondet2; [L497-L504] assume !(0 != eval_~tmp_ndt_1~0); [L508-L521] assume 0 == ~t1_st~0; [L509] havoc eval_~tmp_ndt_2~0; [L510] eval_~tmp_ndt_2~0 := eval_#t~nondet3; [L510] havoc eval_#t~nondet3; [L511-L518] assume !(0 != eval_~tmp_ndt_2~0); [L522-L535] assume 0 == ~t2_st~0; [L523] havoc eval_~tmp_ndt_3~0; [L524] eval_~tmp_ndt_3~0 := eval_#t~nondet4; [L524] havoc eval_#t~nondet4; [L525-L532] assume !(0 != eval_~tmp_ndt_3~0); [L536-L549] assume 0 == ~t3_st~0; [L537] havoc eval_~tmp_ndt_4~0; [L538] eval_~tmp_ndt_4~0 := eval_#t~nondet5; [L538] havoc eval_#t~nondet5; [L539-L546] assume !(0 != eval_~tmp_ndt_4~0); [L550-L563] assume 0 == ~t4_st~0; [L551] havoc eval_~tmp_ndt_5~0; [L552] eval_~tmp_ndt_5~0 := eval_#t~nondet6; [L552] havoc eval_#t~nondet6; [L553-L560] assume !(0 != eval_~tmp_ndt_5~0); [L564-L577] assume 0 == ~t5_st~0; [L565] havoc eval_~tmp_ndt_6~0; [L566] eval_~tmp_ndt_6~0 := eval_#t~nondet7; [L566] havoc eval_#t~nondet7; [L567-L574] assume !(0 != eval_~tmp_ndt_6~0); [L484-L578] COND FALSE !(false) [L487] havoc exists_runnable_thread_#res; [L487] havoc exists_runnable_thread_~__retres1~6; [L439] havoc exists_runnable_thread_~__retres1~6; [L442] COND TRUE 0 == ~m_st~0 [L443] exists_runnable_thread_~__retres1~6 := 1; [L475] exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; [L487] eval_#t~ret1 := exists_runnable_thread_#res; [L487] eval_~tmp~0 := eval_#t~ret1; [L487] havoc eval_#t~ret1; [L489-L493] COND TRUE 0 != eval_~tmp~0 [L494] COND TRUE 0 == ~m_st~0 [L495] havoc eval_~tmp_ndt_1~0; [L496] eval_~tmp_ndt_1~0 := eval_#t~nondet2; [L496] havoc eval_#t~nondet2; [L497-L504] COND FALSE !(0 != eval_~tmp_ndt_1~0) [L508] COND TRUE 0 == ~t1_st~0 [L509] havoc eval_~tmp_ndt_2~0; [L510] eval_~tmp_ndt_2~0 := eval_#t~nondet3; [L510] havoc eval_#t~nondet3; [L511-L518] COND FALSE !(0 != eval_~tmp_ndt_2~0) [L522] COND TRUE 0 == ~t2_st~0 [L523] havoc eval_~tmp_ndt_3~0; [L524] eval_~tmp_ndt_3~0 := eval_#t~nondet4; [L524] havoc eval_#t~nondet4; [L525-L532] COND FALSE !(0 != eval_~tmp_ndt_3~0) [L536] COND TRUE 0 == ~t3_st~0 [L537] havoc eval_~tmp_ndt_4~0; [L538] eval_~tmp_ndt_4~0 := eval_#t~nondet5; [L538] havoc eval_#t~nondet5; [L539-L546] COND FALSE !(0 != eval_~tmp_ndt_4~0) [L550] COND TRUE 0 == ~t4_st~0 [L551] havoc eval_~tmp_ndt_5~0; [L552] eval_~tmp_ndt_5~0 := eval_#t~nondet6; [L552] havoc eval_#t~nondet6; [L553-L560] COND FALSE !(0 != eval_~tmp_ndt_5~0) [L564] COND TRUE 0 == ~t5_st~0 [L565] havoc eval_~tmp_ndt_6~0; [L566] eval_~tmp_ndt_6~0 := eval_#t~nondet7; [L566] havoc eval_#t~nondet7; [L567-L574] COND FALSE !(0 != eval_~tmp_ndt_6~0) ----- ----- class de.uni_freiburg.informatik.ultimate.boogie.procedureinliner.backtranslation.InlinerBacktranslator [L484-L578] COND FALSE !(false) [L487] havoc exists_runnable_thread_#res; [L487] havoc exists_runnable_thread_~__retres1~6; [L439] havoc exists_runnable_thread_~__retres1~6; [L442] COND TRUE 0 == ~m_st~0 [L443] exists_runnable_thread_~__retres1~6 := 1; [L475] exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; [L487] eval_#t~ret1 := exists_runnable_thread_#res; [L487] eval_~tmp~0 := eval_#t~ret1; [L487] havoc eval_#t~ret1; [L489-L493] COND TRUE 0 != eval_~tmp~0 [L494] COND TRUE 0 == ~m_st~0 [L495] havoc eval_~tmp_ndt_1~0; [L496] eval_~tmp_ndt_1~0 := eval_#t~nondet2; [L496] havoc eval_#t~nondet2; [L497-L504] COND FALSE !(0 != eval_~tmp_ndt_1~0) [L508] COND TRUE 0 == ~t1_st~0 [L509] havoc eval_~tmp_ndt_2~0; [L510] eval_~tmp_ndt_2~0 := eval_#t~nondet3; [L510] havoc eval_#t~nondet3; [L511-L518] COND FALSE !(0 != eval_~tmp_ndt_2~0) [L522] COND TRUE 0 == ~t2_st~0 [L523] havoc eval_~tmp_ndt_3~0; [L524] eval_~tmp_ndt_3~0 := eval_#t~nondet4; [L524] havoc eval_#t~nondet4; [L525-L532] COND FALSE !(0 != eval_~tmp_ndt_3~0) [L536] COND TRUE 0 == ~t3_st~0 [L537] havoc eval_~tmp_ndt_4~0; [L538] eval_~tmp_ndt_4~0 := eval_#t~nondet5; [L538] havoc eval_#t~nondet5; [L539-L546] COND FALSE !(0 != eval_~tmp_ndt_4~0) [L550] COND TRUE 0 == ~t4_st~0 [L551] havoc eval_~tmp_ndt_5~0; [L552] eval_~tmp_ndt_5~0 := eval_#t~nondet6; [L552] havoc eval_#t~nondet6; [L553-L560] COND FALSE !(0 != eval_~tmp_ndt_5~0) [L564] COND TRUE 0 == ~t5_st~0 [L565] havoc eval_~tmp_ndt_6~0; [L566] eval_~tmp_ndt_6~0 := eval_#t~nondet7; [L566] havoc eval_#t~nondet7; [L567-L574] COND FALSE !(0 != eval_~tmp_ndt_6~0) [L484-L578] COND FALSE !(false) [L439] havoc ~__retres1~6; [L442] COND TRUE 0 == ~m_st~0 [L443] ~__retres1~6 := 1; [L475] #res := ~__retres1~6; [L487] ~tmp~0 := #t~ret1; [L487] havoc #t~ret1; [L489-L493] COND TRUE 0 != ~tmp~0 [L494] COND TRUE 0 == ~m_st~0 [L495] havoc ~tmp_ndt_1~0; [L496] ~tmp_ndt_1~0 := #t~nondet2; [L496] havoc #t~nondet2; [L497-L504] COND FALSE !(0 != ~tmp_ndt_1~0) [L508] COND TRUE 0 == ~t1_st~0 [L509] havoc ~tmp_ndt_2~0; [L510] ~tmp_ndt_2~0 := #t~nondet3; [L510] havoc #t~nondet3; [L511-L518] COND FALSE !(0 != ~tmp_ndt_2~0) [L522] COND TRUE 0 == ~t2_st~0 [L523] havoc ~tmp_ndt_3~0; [L524] ~tmp_ndt_3~0 := #t~nondet4; [L524] havoc #t~nondet4; [L525-L532] COND FALSE !(0 != ~tmp_ndt_3~0) [L536] COND TRUE 0 == ~t3_st~0 [L537] havoc ~tmp_ndt_4~0; [L538] ~tmp_ndt_4~0 := #t~nondet5; [L538] havoc #t~nondet5; [L539-L546] COND FALSE !(0 != ~tmp_ndt_4~0) [L550] COND TRUE 0 == ~t4_st~0 [L551] havoc ~tmp_ndt_5~0; [L552] ~tmp_ndt_5~0 := #t~nondet6; [L552] havoc #t~nondet6; [L553-L560] COND FALSE !(0 != ~tmp_ndt_5~0) [L564] COND TRUE 0 == ~t5_st~0 [L565] havoc ~tmp_ndt_6~0; [L566] ~tmp_ndt_6~0 := #t~nondet7; [L566] havoc #t~nondet7; [L567-L574] COND FALSE !(0 != ~tmp_ndt_6~0) ----- ----- class de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.CACSL2BoogieBacktranslator [L484-L578] COND FALSE !(false) [L439] havoc ~__retres1~6; [L442] COND TRUE 0 == ~m_st~0 [L443] ~__retres1~6 := 1; [L475] #res := ~__retres1~6; [L487] ~tmp~0 := #t~ret1; [L487] havoc #t~ret1; [L489-L493] COND TRUE 0 != ~tmp~0 [L494] COND TRUE 0 == ~m_st~0 [L495] havoc ~tmp_ndt_1~0; [L496] ~tmp_ndt_1~0 := #t~nondet2; [L496] havoc #t~nondet2; [L497-L504] COND FALSE !(0 != ~tmp_ndt_1~0) [L508] COND TRUE 0 == ~t1_st~0 [L509] havoc ~tmp_ndt_2~0; [L510] ~tmp_ndt_2~0 := #t~nondet3; [L510] havoc #t~nondet3; [L511-L518] COND FALSE !(0 != ~tmp_ndt_2~0) [L522] COND TRUE 0 == ~t2_st~0 [L523] havoc ~tmp_ndt_3~0; [L524] ~tmp_ndt_3~0 := #t~nondet4; [L524] havoc #t~nondet4; [L525-L532] COND FALSE !(0 != ~tmp_ndt_3~0) [L536] COND TRUE 0 == ~t3_st~0 [L537] havoc ~tmp_ndt_4~0; [L538] ~tmp_ndt_4~0 := #t~nondet5; [L538] havoc #t~nondet5; [L539-L546] COND FALSE !(0 != ~tmp_ndt_4~0) [L550] COND TRUE 0 == ~t4_st~0 [L551] havoc ~tmp_ndt_5~0; [L552] ~tmp_ndt_5~0 := #t~nondet6; [L552] havoc #t~nondet6; [L553-L560] COND FALSE !(0 != ~tmp_ndt_5~0) [L564] COND TRUE 0 == ~t5_st~0 [L565] havoc ~tmp_ndt_6~0; [L566] ~tmp_ndt_6~0 := #t~nondet7; [L566] havoc #t~nondet7; [L567-L574] COND FALSE !(0 != ~tmp_ndt_6~0) [L484] COND TRUE 1 [L439] int __retres1 ; [L442] COND TRUE m_st == 0 [L443] __retres1 = 1 [L475] return (__retres1); [L487] tmp = exists_runnable_thread() [L489] COND TRUE \read(tmp) [L494] COND TRUE m_st == 0 [L495] int tmp_ndt_1; [L496] tmp_ndt_1 = __VERIFIER_nondet_int() [L497] COND FALSE !(\read(tmp_ndt_1)) [L508] COND TRUE t1_st == 0 [L509] int tmp_ndt_2; [L510] tmp_ndt_2 = __VERIFIER_nondet_int() [L511] COND FALSE !(\read(tmp_ndt_2)) [L522] COND TRUE t2_st == 0 [L523] int tmp_ndt_3; [L524] tmp_ndt_3 = __VERIFIER_nondet_int() [L525] COND FALSE !(\read(tmp_ndt_3)) [L536] COND TRUE t3_st == 0 [L537] int tmp_ndt_4; [L538] tmp_ndt_4 = __VERIFIER_nondet_int() [L539] COND FALSE !(\read(tmp_ndt_4)) [L550] COND TRUE t4_st == 0 [L551] int tmp_ndt_5; [L552] tmp_ndt_5 = __VERIFIER_nondet_int() [L553] COND FALSE !(\read(tmp_ndt_5)) [L564] COND TRUE t5_st == 0 [L565] int tmp_ndt_6; [L566] tmp_ndt_6 = __VERIFIER_nondet_int() [L567] COND FALSE !(\read(tmp_ndt_6)) ----- Found a nonterminating execution for the following lasso shaped sequence of statements. Stem: [L14] int m_pc = 0; [L15] int t1_pc = 0; [L16] int t2_pc = 0; [L17] int t3_pc = 0; [L18] int t4_pc = 0; [L19] int t5_pc = 0; [L20] int m_st ; [L21] int t1_st ; [L22] int t2_st ; [L23] int t3_st ; [L24] int t4_st ; [L25] int t5_st ; [L26] int m_i ; [L27] int t1_i ; [L28] int t2_i ; [L29] int t3_i ; [L30] int t4_i ; [L31] int t5_i ; [L32] int M_E = 2; [L33] int T1_E = 2; [L34] int T2_E = 2; [L35] int T3_E = 2; [L36] int T4_E = 2; [L37] int T5_E = 2; [L38] int E_M = 2; [L39] int E_1 = 2; [L40] int E_2 = 2; [L41] int E_3 = 2; [L42] int E_4 = 2; [L43] int E_5 = 2; [L51] int token ; [L53] int local ; [L963] int __retres1 ; [L874] m_i = 1 [L875] t1_i = 1 [L876] t2_i = 1 [L877] t3_i = 1 [L878] t4_i = 1 [L879] t5_i = 1 [L904] int kernel_st ; [L905] int tmp ; [L906] int tmp___0 ; [L910] kernel_st = 0 [L404] COND TRUE m_i == 1 [L405] m_st = 0 [L409] COND TRUE t1_i == 1 [L410] t1_st = 0 [L414] COND TRUE t2_i == 1 [L415] t2_st = 0 [L419] COND TRUE t3_i == 1 [L420] t3_st = 0 [L424] COND TRUE t4_i == 1 [L425] t4_st = 0 [L429] COND TRUE t5_i == 1 [L430] t5_st = 0 [L589] COND FALSE !(M_E == 0) [L594] COND FALSE !(T1_E == 0) [L599] COND FALSE !(T2_E == 0) [L604] COND FALSE !(T3_E == 0) [L609] COND FALSE !(T4_E == 0) [L614] COND FALSE !(T5_E == 0) [L619] COND FALSE !(E_M == 0) [L624] COND FALSE !(E_1 == 0) [L629] COND FALSE !(E_2 == 0) [L634] COND FALSE !(E_3 == 0) [L639] COND FALSE !(E_4 == 0) [L644] COND FALSE !(E_5 == 0) [L722] int tmp ; [L723] int tmp___0 ; [L724] int tmp___1 ; [L725] int tmp___2 ; [L726] int tmp___3 ; [L727] int tmp___4 ; [L279] int __retres1 ; [L282] COND FALSE !(m_pc == 1) [L292] __retres1 = 0 [L294] return (__retres1); [L731] tmp = is_master_triggered() [L733] COND FALSE !(\read(tmp)) [L298] int __retres1 ; [L301] COND FALSE !(t1_pc == 1) [L311] __retres1 = 0 [L313] return (__retres1); [L739] tmp___0 = is_transmit1_triggered() [L741] COND FALSE !(\read(tmp___0)) [L317] int __retres1 ; [L320] COND FALSE !(t2_pc == 1) [L330] __retres1 = 0 [L332] return (__retres1); [L747] tmp___1 = is_transmit2_triggered() [L749] COND FALSE !(\read(tmp___1)) [L336] int __retres1 ; [L339] COND FALSE !(t3_pc == 1) [L349] __retres1 = 0 [L351] return (__retres1); [L755] tmp___2 = is_transmit3_triggered() [L757] COND FALSE !(\read(tmp___2)) [L355] int __retres1 ; [L358] COND FALSE !(t4_pc == 1) [L368] __retres1 = 0 [L370] return (__retres1); [L763] tmp___3 = is_transmit4_triggered() [L765] COND FALSE !(\read(tmp___3)) [L374] int __retres1 ; [L377] COND FALSE !(t5_pc == 1) [L387] __retres1 = 0 [L389] return (__retres1); [L771] tmp___4 = is_transmit5_triggered() [L773] COND FALSE !(\read(tmp___4)) [L657] COND FALSE !(M_E == 1) [L662] COND FALSE !(T1_E == 1) [L667] COND FALSE !(T2_E == 1) [L672] COND FALSE !(T3_E == 1) [L677] COND FALSE !(T4_E == 1) [L682] COND FALSE !(T5_E == 1) [L687] COND FALSE !(E_M == 1) [L692] COND FALSE !(E_1 == 1) [L697] COND FALSE !(E_2 == 1) [L702] COND FALSE !(E_3 == 1) [L707] COND FALSE !(E_4 == 1) [L712] COND FALSE !(E_5 == 1) [L918] COND TRUE 1 [L921] kernel_st = 1 [L480] int tmp ; Loop: [L484] COND TRUE 1 [L439] int __retres1 ; [L442] COND TRUE m_st == 0 [L443] __retres1 = 1 [L475] return (__retres1); [L487] tmp = exists_runnable_thread() [L489] COND TRUE \read(tmp) [L494] COND TRUE m_st == 0 [L495] int tmp_ndt_1; [L496] tmp_ndt_1 = __VERIFIER_nondet_int() [L497] COND FALSE !(\read(tmp_ndt_1)) [L508] COND TRUE t1_st == 0 [L509] int tmp_ndt_2; [L510] tmp_ndt_2 = __VERIFIER_nondet_int() [L511] COND FALSE !(\read(tmp_ndt_2)) [L522] COND TRUE t2_st == 0 [L523] int tmp_ndt_3; [L524] tmp_ndt_3 = __VERIFIER_nondet_int() [L525] COND FALSE !(\read(tmp_ndt_3)) [L536] COND TRUE t3_st == 0 [L537] int tmp_ndt_4; [L538] tmp_ndt_4 = __VERIFIER_nondet_int() [L539] COND FALSE !(\read(tmp_ndt_4)) [L550] COND TRUE t4_st == 0 [L551] int tmp_ndt_5; [L552] tmp_ndt_5 = __VERIFIER_nondet_int() [L553] COND FALSE !(\read(tmp_ndt_5)) [L564] COND TRUE t5_st == 0 [L565] int tmp_ndt_6; [L566] tmp_ndt_6 = __VERIFIER_nondet_int() [L567] COND FALSE !(\read(tmp_ndt_6)) End of lasso representation. RESULT: Ultimate proved your program to be incorrect! Received shutdown request...