./Ultimate.py --spec ../../sv-benchmarks/c/properties/termination.prp --file ../../sv-benchmarks/c/systemc/token_ring.06_false-unreach-call_false-termination.cil.c --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for termination Using default analysis Version aa418289 Calling Ultimate with: java -Dosgi.configuration.area=/tmp/vcloud-vcloud-master/worker/working_dir_3cb46500-1f11-408a-a24e-b9ac197b8b4e/bin-2019/uautomizer/data/config -Xmx12G -Xms1G -jar /tmp/vcloud-vcloud-master/worker/working_dir_3cb46500-1f11-408a-a24e-b9ac197b8b4e/bin-2019/uautomizer/plugins/org.eclipse.equinox.launcher_1.3.100.v20150511-1540.jar -data @noDefault -ultimatedata /tmp/vcloud-vcloud-master/worker/working_dir_3cb46500-1f11-408a-a24e-b9ac197b8b4e/bin-2019/uautomizer/data -tc /tmp/vcloud-vcloud-master/worker/working_dir_3cb46500-1f11-408a-a24e-b9ac197b8b4e/bin-2019/uautomizer/config/AutomizerTermination.xml -i ../../sv-benchmarks/c/systemc/token_ring.06_false-unreach-call_false-termination.cil.c -s /tmp/vcloud-vcloud-master/worker/working_dir_3cb46500-1f11-408a-a24e-b9ac197b8b4e/bin-2019/uautomizer/config/svcomp-Termination-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud-vcloud-master/worker/working_dir_3cb46500-1f11-408a-a24e-b9ac197b8b4e/bin-2019/uautomizer --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash 936bf61b77a625ec3ee8993291aaaab59d0dc18e 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Execution finished normally Writing output log to file Ultimate.log Writing human readable error path to file UltimateCounterExample.errorpath Result: FALSE(TERM) --- Real Ultimate output --- This is Ultimate 0.1.23-aa41828 [2018-11-23 01:26:42,875 INFO L170 SettingsManager]: Resetting all preferences to default values... [2018-11-23 01:26:42,876 INFO L174 SettingsManager]: Resetting UltimateCore preferences to default values [2018-11-23 01:26:42,883 INFO L177 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2018-11-23 01:26:42,883 INFO L174 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2018-11-23 01:26:42,884 INFO L174 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2018-11-23 01:26:42,885 INFO L174 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2018-11-23 01:26:42,886 INFO L174 SettingsManager]: Resetting LassoRanker preferences to default values [2018-11-23 01:26:42,887 INFO L174 SettingsManager]: Resetting Reaching Definitions preferences to default values [2018-11-23 01:26:42,887 INFO L174 SettingsManager]: Resetting SyntaxChecker preferences to default values [2018-11-23 01:26:42,888 INFO L177 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2018-11-23 01:26:42,888 INFO L174 SettingsManager]: Resetting LTL2Aut preferences to default values [2018-11-23 01:26:42,889 INFO L174 SettingsManager]: Resetting PEA to Boogie preferences to default values [2018-11-23 01:26:42,890 INFO L174 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2018-11-23 01:26:42,890 INFO L174 SettingsManager]: Resetting ChcToBoogie preferences to default values [2018-11-23 01:26:42,891 INFO L174 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2018-11-23 01:26:42,892 INFO L174 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2018-11-23 01:26:42,893 INFO L174 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2018-11-23 01:26:42,894 INFO L174 SettingsManager]: Resetting CodeCheck preferences to default values [2018-11-23 01:26:42,895 INFO L174 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2018-11-23 01:26:42,896 INFO L174 SettingsManager]: Resetting RCFGBuilder preferences to default values [2018-11-23 01:26:42,897 INFO L174 SettingsManager]: Resetting TraceAbstraction preferences to default values [2018-11-23 01:26:42,898 INFO L177 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2018-11-23 01:26:42,898 INFO L177 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2018-11-23 01:26:42,898 INFO L174 SettingsManager]: Resetting TreeAutomizer preferences to default values [2018-11-23 01:26:42,899 INFO L174 SettingsManager]: Resetting IcfgTransformer preferences to default values [2018-11-23 01:26:42,900 INFO L174 SettingsManager]: Resetting Boogie Printer preferences to default values [2018-11-23 01:26:42,900 INFO L174 SettingsManager]: Resetting ReqPrinter preferences to default values [2018-11-23 01:26:42,901 INFO L174 SettingsManager]: Resetting Witness Printer preferences to default values [2018-11-23 01:26:42,901 INFO L177 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2018-11-23 01:26:42,902 INFO L174 SettingsManager]: Resetting CDTParser preferences to default values [2018-11-23 01:26:42,902 INFO L177 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2018-11-23 01:26:42,902 INFO L177 SettingsManager]: ReqParser provides no preferences, ignoring... [2018-11-23 01:26:42,902 INFO L174 SettingsManager]: Resetting SmtParser preferences to default values [2018-11-23 01:26:42,903 INFO L174 SettingsManager]: Resetting Witness Parser preferences to default values [2018-11-23 01:26:42,904 INFO L181 SettingsManager]: Finished resetting all preferences to default values... [2018-11-23 01:26:42,904 INFO L98 SettingsManager]: Beginning loading settings from /tmp/vcloud-vcloud-master/worker/working_dir_3cb46500-1f11-408a-a24e-b9ac197b8b4e/bin-2019/uautomizer/config/svcomp-Termination-32bit-Automizer_Default.epf [2018-11-23 01:26:42,913 INFO L110 SettingsManager]: Loading preferences was successful [2018-11-23 01:26:42,914 INFO L112 SettingsManager]: Preferences different from defaults after loading the file: [2018-11-23 01:26:42,914 INFO L131 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2018-11-23 01:26:42,915 INFO L133 SettingsManager]: * Create parallel compositions if possible=false [2018-11-23 01:26:42,915 INFO L133 SettingsManager]: * Use SBE=true [2018-11-23 01:26:42,915 INFO L131 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: [2018-11-23 01:26:42,915 INFO L133 SettingsManager]: * NCSB implementation=INTSET_LAZY3 [2018-11-23 01:26:42,915 INFO L133 SettingsManager]: * Use old map elimination=false [2018-11-23 01:26:42,915 INFO L133 SettingsManager]: * Use external solver (rank synthesis)=false [2018-11-23 01:26:42,915 INFO L133 SettingsManager]: * Use only trivial implications for array writes=true [2018-11-23 01:26:42,916 INFO L133 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES [2018-11-23 01:26:42,916 INFO L131 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2018-11-23 01:26:42,916 INFO L133 SettingsManager]: * sizeof long=4 [2018-11-23 01:26:42,916 INFO L133 SettingsManager]: * Check unreachability of error function in SV-COMP mode=false [2018-11-23 01:26:42,916 INFO L133 SettingsManager]: * Overapproximate operations on floating types=true [2018-11-23 01:26:42,916 INFO L133 SettingsManager]: * sizeof POINTER=4 [2018-11-23 01:26:42,916 INFO L133 SettingsManager]: * Check division by zero=IGNORE [2018-11-23 01:26:42,916 INFO L133 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME [2018-11-23 01:26:42,917 INFO L133 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME [2018-11-23 01:26:42,917 INFO L133 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME [2018-11-23 01:26:42,917 INFO L133 SettingsManager]: * sizeof long double=12 [2018-11-23 01:26:42,917 INFO L133 SettingsManager]: * Check if freed pointer was valid=false [2018-11-23 01:26:42,917 INFO L133 SettingsManager]: * Assume nondeterminstic values are in range=false [2018-11-23 01:26:42,917 INFO L133 SettingsManager]: * Use constant arrays=true [2018-11-23 01:26:42,917 INFO L133 SettingsManager]: * Pointer base address is valid at dereference=ASSUME [2018-11-23 01:26:42,918 INFO L131 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2018-11-23 01:26:42,918 INFO L133 SettingsManager]: * Size of a code block=SequenceOfStatements [2018-11-23 01:26:42,918 INFO L133 SettingsManager]: * To the following directory=/home/matthias/ultimate/dump [2018-11-23 01:26:42,918 INFO L131 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2018-11-23 01:26:42,918 INFO L133 SettingsManager]: * Trace refinement strategy=CAMEL [2018-11-23 01:26:42,918 INFO L133 SettingsManager]: * Dump automata to the following directory=/home/matthias/ultimate/dump/auto [2018-11-23 01:26:42,919 INFO L131 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2018-11-23 01:26:42,919 INFO L133 SettingsManager]: * TransformationType=MODULO_NEIGHBOR Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud-vcloud-master/worker/working_dir_3cb46500-1f11-408a-a24e-b9ac197b8b4e/bin-2019/uautomizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> 936bf61b77a625ec3ee8993291aaaab59d0dc18e [2018-11-23 01:26:42,940 INFO L81 nceAwareModelManager]: Repository-Root is: /tmp [2018-11-23 01:26:42,949 INFO L258 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2018-11-23 01:26:42,951 INFO L214 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2018-11-23 01:26:42,952 INFO L271 PluginConnector]: Initializing CDTParser... [2018-11-23 01:26:42,953 INFO L276 PluginConnector]: CDTParser initialized [2018-11-23 01:26:42,953 INFO L418 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud-vcloud-master/worker/working_dir_3cb46500-1f11-408a-a24e-b9ac197b8b4e/bin-2019/uautomizer/../../sv-benchmarks/c/systemc/token_ring.06_false-unreach-call_false-termination.cil.c [2018-11-23 01:26:42,989 INFO L221 CDTParser]: Created temporary CDT project at /tmp/vcloud-vcloud-master/worker/working_dir_3cb46500-1f11-408a-a24e-b9ac197b8b4e/bin-2019/uautomizer/data/a79f20f7c/9a12deac8d5c4400af80739f3518d398/FLAG1411304c2 [2018-11-23 01:26:43,342 INFO L307 CDTParser]: Found 1 translation units. [2018-11-23 01:26:43,342 INFO L161 CDTParser]: Scanning /tmp/vcloud-vcloud-master/worker/working_dir_3cb46500-1f11-408a-a24e-b9ac197b8b4e/sv-benchmarks/c/systemc/token_ring.06_false-unreach-call_false-termination.cil.c [2018-11-23 01:26:43,349 INFO L355 CDTParser]: About to delete temporary CDT project at /tmp/vcloud-vcloud-master/worker/working_dir_3cb46500-1f11-408a-a24e-b9ac197b8b4e/bin-2019/uautomizer/data/a79f20f7c/9a12deac8d5c4400af80739f3518d398/FLAG1411304c2 [2018-11-23 01:26:43,751 INFO L363 CDTParser]: Successfully deleted /tmp/vcloud-vcloud-master/worker/working_dir_3cb46500-1f11-408a-a24e-b9ac197b8b4e/bin-2019/uautomizer/data/a79f20f7c/9a12deac8d5c4400af80739f3518d398 [2018-11-23 01:26:43,753 INFO L296 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2018-11-23 01:26:43,755 INFO L131 ToolchainWalker]: Walking toolchain with 6 elements. [2018-11-23 01:26:43,755 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2018-11-23 01:26:43,756 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2018-11-23 01:26:43,759 INFO L276 PluginConnector]: CACSL2BoogieTranslator initialized [2018-11-23 01:26:43,759 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 23.11 01:26:43" (1/1) ... [2018-11-23 01:26:43,761 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@1538edb and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 01:26:43, skipping insertion in model container [2018-11-23 01:26:43,761 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 23.11 01:26:43" (1/1) ... [2018-11-23 01:26:43,768 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2018-11-23 01:26:43,797 INFO L176 MainTranslator]: Built tables and reachable declarations [2018-11-23 01:26:43,967 INFO L201 PostProcessor]: Analyzing one entry point: main [2018-11-23 01:26:43,970 INFO L191 MainTranslator]: Completed pre-run [2018-11-23 01:26:44,004 INFO L201 PostProcessor]: Analyzing one entry point: main [2018-11-23 01:26:44,016 INFO L195 MainTranslator]: Completed translation [2018-11-23 01:26:44,017 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 01:26:44 WrapperNode [2018-11-23 01:26:44,017 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2018-11-23 01:26:44,017 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2018-11-23 01:26:44,017 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2018-11-23 01:26:44,018 INFO L276 PluginConnector]: Boogie Procedure Inliner initialized [2018-11-23 01:26:44,022 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 01:26:44" (1/1) ... [2018-11-23 01:26:44,028 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 01:26:44" (1/1) ... [2018-11-23 01:26:44,108 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2018-11-23 01:26:44,108 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2018-11-23 01:26:44,108 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2018-11-23 01:26:44,108 INFO L276 PluginConnector]: Boogie Preprocessor initialized [2018-11-23 01:26:44,115 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 01:26:44" (1/1) ... [2018-11-23 01:26:44,115 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 01:26:44" (1/1) ... [2018-11-23 01:26:44,119 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 01:26:44" (1/1) ... [2018-11-23 01:26:44,120 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 01:26:44" (1/1) ... [2018-11-23 01:26:44,133 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 01:26:44" (1/1) ... [2018-11-23 01:26:44,149 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 01:26:44" (1/1) ... [2018-11-23 01:26:44,152 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 01:26:44" (1/1) ... [2018-11-23 01:26:44,157 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2018-11-23 01:26:44,158 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2018-11-23 01:26:44,158 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2018-11-23 01:26:44,158 INFO L276 PluginConnector]: RCFGBuilder initialized [2018-11-23 01:26:44,159 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 01:26:44" (1/1) ... No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_3cb46500-1f11-408a-a24e-b9ac197b8b4e/bin-2019/uautomizer/z3 Starting monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2018-11-23 01:26:44,206 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2018-11-23 01:26:44,206 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2018-11-23 01:26:45,203 INFO L275 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2018-11-23 01:26:45,203 INFO L280 CfgBuilder]: Removed 237 assue(true) statements. [2018-11-23 01:26:45,203 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 23.11 01:26:45 BoogieIcfgContainer [2018-11-23 01:26:45,203 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2018-11-23 01:26:45,204 INFO L113 PluginConnector]: ------------------------BuchiAutomizer---------------------------- [2018-11-23 01:26:45,204 INFO L271 PluginConnector]: Initializing BuchiAutomizer... [2018-11-23 01:26:45,207 INFO L276 PluginConnector]: BuchiAutomizer initialized [2018-11-23 01:26:45,208 INFO L102 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2018-11-23 01:26:45,208 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 23.11 01:26:43" (1/3) ... [2018-11-23 01:26:45,209 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@123e4559 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 23.11 01:26:45, skipping insertion in model container [2018-11-23 01:26:45,209 INFO L102 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2018-11-23 01:26:45,209 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 01:26:44" (2/3) ... [2018-11-23 01:26:45,210 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@123e4559 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 23.11 01:26:45, skipping insertion in model container [2018-11-23 01:26:45,210 INFO L102 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2018-11-23 01:26:45,210 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 23.11 01:26:45" (3/3) ... [2018-11-23 01:26:45,211 INFO L375 chiAutomizerObserver]: Analyzing ICFG token_ring.06_false-unreach-call_false-termination.cil.c [2018-11-23 01:26:45,247 INFO L133 ementStrategyFactory]: Using default assertion order modulation [2018-11-23 01:26:45,248 INFO L374 BuchiCegarLoop]: Interprodecural is true [2018-11-23 01:26:45,248 INFO L375 BuchiCegarLoop]: Hoare is false [2018-11-23 01:26:45,248 INFO L376 BuchiCegarLoop]: Compute interpolants for ForwardPredicates [2018-11-23 01:26:45,248 INFO L377 BuchiCegarLoop]: Backedges is STRAIGHT_LINE [2018-11-23 01:26:45,248 INFO L378 BuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2018-11-23 01:26:45,248 INFO L379 BuchiCegarLoop]: Difference is false [2018-11-23 01:26:45,248 INFO L380 BuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2018-11-23 01:26:45,248 INFO L383 BuchiCegarLoop]: ======== Iteration 0==of CEGAR loop == BuchiCegarLoop======== [2018-11-23 01:26:45,272 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 671 states. [2018-11-23 01:26:45,302 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 580 [2018-11-23 01:26:45,302 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-23 01:26:45,302 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-23 01:26:45,311 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 01:26:45,311 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 01:26:45,311 INFO L442 BuchiCegarLoop]: ======== Iteration 1============ [2018-11-23 01:26:45,311 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 671 states. [2018-11-23 01:26:45,321 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 580 [2018-11-23 01:26:45,321 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-23 01:26:45,321 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-23 01:26:45,323 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 01:26:45,324 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 01:26:45,329 INFO L794 eck$LassoCheckResult]: Stem: 446#ULTIMATE.startENTRYtrue ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0; 349#L-1true havoc main_#res;havoc main_~__retres1~8;havoc main_~__retres1~8;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 152#L1018true havoc start_simulation_#t~ret18, start_simulation_#t~ret19, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 660#L470true assume !(1 == ~m_i~0);~m_st~0 := 2; 52#L477-1true assume 1 == ~t1_i~0;~t1_st~0 := 0; 588#L482-1true assume !(1 == ~t2_i~0);~t2_st~0 := 2; 297#L487-1true assume !(1 == ~t3_i~0);~t3_st~0 := 2; 662#L492-1true assume !(1 == ~t4_i~0);~t4_st~0 := 2; 179#L497-1true assume !(1 == ~t5_i~0);~t5_st~0 := 2; 554#L502-1true assume !(1 == ~t6_i~0);~t6_st~0 := 2; 234#L507-1true assume !(0 == ~M_E~0); 61#L686-1true assume !(0 == ~T1_E~0); 597#L691-1true assume 0 == ~T2_E~0;~T2_E~0 := 1; 309#L696-1true assume !(0 == ~T3_E~0); 669#L701-1true assume !(0 == ~T4_E~0); 184#L706-1true assume !(0 == ~T5_E~0); 561#L711-1true assume !(0 == ~T6_E~0); 416#L716-1true assume !(0 == ~E_M~0); 137#L721-1true assume !(0 == ~E_1~0); 505#L726-1true assume !(0 == ~E_2~0); 12#L731-1true assume 0 == ~E_3~0;~E_3~0 := 1; 374#L736-1true assume !(0 == ~E_4~0); 56#L741-1true assume !(0 == ~E_5~0); 593#L746-1true assume !(0 == ~E_6~0); 304#L751-1true havoc activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 114#L336true assume !(1 == ~m_pc~0); 84#L336-2true is_master_triggered_~__retres1~0 := 0; 112#L347true is_master_triggered_#res := is_master_triggered_~__retres1~0; 537#L348true activate_threads_#t~ret10 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 71#L851true assume !(0 != activate_threads_~tmp~1); 73#L851-2true havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 270#L355true assume 1 == ~t1_pc~0; 28#L356true assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 268#L366true is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 55#L367true activate_threads_#t~ret11 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 426#L859true assume !(0 != activate_threads_~tmp___0~0); 409#L859-2true havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 475#L374true assume 1 == ~t2_pc~0; 217#L375true assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 473#L385true is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 216#L386true activate_threads_#t~ret12 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 609#L867true assume !(0 != activate_threads_~tmp___1~0); 612#L867-2true havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 638#L393true assume !(1 == ~t3_pc~0); 642#L393-2true is_transmit3_triggered_~__retres1~3 := 0; 636#L404true is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 589#L405true activate_threads_#t~ret13 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 143#L875true assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 130#L875-2true havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 167#L412true assume 1 == ~t4_pc~0; 105#L413true assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 166#L423true is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 104#L424true activate_threads_#t~ret14 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 319#L883true assume !(0 != activate_threads_~tmp___3~0); 321#L883-2true havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 181#L431true assume !(1 == ~t5_pc~0); 173#L431-2true is_transmit5_triggered_~__retres1~5 := 0; 180#L442true is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 299#L443true activate_threads_#t~ret15 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 513#L891true assume !(0 != activate_threads_~tmp___4~0); 497#L891-2true havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 363#L450true assume 1 == ~t6_pc~0; 467#L451true assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6 := 1; 362#L461true is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 465#L462true activate_threads_#t~ret16 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 515#L899true assume !(0 != activate_threads_~tmp___5~0); 517#L899-2true assume !(1 == ~M_E~0); 10#L764-1true assume !(1 == ~T1_E~0); 372#L769-1true assume !(1 == ~T2_E~0); 76#L774-1true assume !(1 == ~T3_E~0); 615#L779-1true assume !(1 == ~T4_E~0); 325#L784-1true assume !(1 == ~T5_E~0); 665#L789-1true assume 1 == ~T6_E~0;~T6_E~0 := 2; 182#L794-1true assume !(1 == ~E_M~0); 557#L799-1true assume !(1 == ~E_1~0); 410#L804-1true assume !(1 == ~E_2~0); 131#L809-1true assume !(1 == ~E_3~0); 500#L814-1true assume !(1 == ~E_4~0); 9#L819-1true assume !(1 == ~E_5~0); 371#L824-1true assume !(1 == ~E_6~0); 376#L1055-1true [2018-11-23 01:26:45,331 INFO L796 eck$LassoCheckResult]: Loop: 376#L1055-1true assume !false; 348#L1056true start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret2, eval_#t~nondet3, eval_~tmp_ndt_1~0, eval_#t~nondet4, eval_~tmp_ndt_2~0, eval_#t~nondet5, eval_~tmp_ndt_3~0, eval_#t~nondet6, eval_~tmp_ndt_4~0, eval_#t~nondet7, eval_~tmp_ndt_5~0, eval_#t~nondet8, eval_~tmp_ndt_6~0, eval_#t~nondet9, eval_~tmp_ndt_7~0, eval_~tmp~0;havoc eval_~tmp~0; 417#L661true assume false; 3#L676true start_simulation_~kernel_st~0 := 2; 663#L470-1true start_simulation_~kernel_st~0 := 3; 64#L686-2true assume 0 == ~M_E~0;~M_E~0 := 1; 68#L686-4true assume 0 == ~T1_E~0;~T1_E~0 := 1; 606#L691-3true assume 0 == ~T2_E~0;~T2_E~0 := 1; 315#L696-3true assume 0 == ~T3_E~0;~T3_E~0 := 1; 671#L701-3true assume !(0 == ~T4_E~0); 185#L706-3true assume 0 == ~T5_E~0;~T5_E~0 := 1; 544#L711-3true assume 0 == ~T6_E~0;~T6_E~0 := 1; 225#L716-3true assume 0 == ~E_M~0;~E_M~0 := 1; 122#L721-3true assume 0 == ~E_1~0;~E_1~0 := 1; 483#L726-3true assume 0 == ~E_2~0;~E_2~0 := 1; 5#L731-3true assume 0 == ~E_3~0;~E_3~0 := 1; 370#L736-3true assume 0 == ~E_4~0;~E_4~0 := 1; 63#L741-3true assume !(0 == ~E_5~0); 600#L746-3true assume 0 == ~E_6~0;~E_6~0 := 1; 311#L751-3true havoc activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 547#L336-24true assume !(1 == ~m_pc~0); 551#L336-26true is_master_triggered_~__retres1~0 := 0; 574#L347-8true is_master_triggered_#res := is_master_triggered_~__retres1~0; 519#L348-8true activate_threads_#t~ret10 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 26#L851-24true assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 13#L851-26true havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 67#L355-24true assume 1 == ~t1_pc~0; 24#L356-8true assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 260#L366-8true is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 22#L367-8true activate_threads_#t~ret11 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 191#L859-24true assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 192#L859-26true havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 226#L374-24true assume 1 == ~t2_pc~0; 213#L375-8true assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 429#L385-8true is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 211#L386-8true activate_threads_#t~ret12 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 390#L867-24true assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 375#L867-26true havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 603#L393-24true assume !(1 == ~t3_pc~0); 608#L393-26true is_transmit3_triggered_~__retres1~3 := 0; 629#L404-8true is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 385#L405-8true activate_threads_#t~ret13 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 575#L875-24true assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 581#L875-26true havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 119#L412-24true assume 1 == ~t4_pc~0; 100#L413-8true assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 161#L423-8true is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 98#L424-8true activate_threads_#t~ret14 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 262#L883-24true assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 237#L883-26true havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 310#L431-24true assume !(1 == ~t5_pc~0); 316#L431-26true is_transmit5_triggered_~__retres1~5 := 0; 339#L442-8true is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 252#L443-8true activate_threads_#t~ret15 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 431#L891-24true assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 436#L891-26true havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 508#L450-24true assume !(1 == ~t6_pc~0); 485#L450-26true is_transmit6_triggered_~__retres1~6 := 0; 360#L461-8true is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 457#L462-8true activate_threads_#t~ret16 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 632#L899-24true assume 0 != activate_threads_~tmp___5~0;~t6_st~0 := 0; 616#L899-26true assume !(1 == ~M_E~0); 4#L764-3true assume 1 == ~T1_E~0;~T1_E~0 := 2; 369#L769-3true assume 1 == ~T2_E~0;~T2_E~0 := 2; 59#L774-3true assume 1 == ~T3_E~0;~T3_E~0 := 2; 595#L779-3true assume 1 == ~T4_E~0;~T4_E~0 := 2; 308#L784-3true assume 1 == ~T5_E~0;~T5_E~0 := 2; 668#L789-3true assume 1 == ~T6_E~0;~T6_E~0 := 2; 183#L794-3true assume 1 == ~E_M~0;~E_M~0 := 2; 560#L799-3true assume !(1 == ~E_1~0); 414#L804-3true assume 1 == ~E_2~0;~E_2~0 := 2; 136#L809-3true assume 1 == ~E_3~0;~E_3~0 := 2; 504#L814-3true assume 1 == ~E_4~0;~E_4~0 := 2; 11#L819-3true assume 1 == ~E_5~0;~E_5~0 := 2; 373#L824-3true assume 1 == ~E_6~0;~E_6~0 := 2; 77#L829-3true havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~7;havoc exists_runnable_thread_~__retres1~7; 296#L520-1true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7 := 1; 550#L557-1true exists_runnable_thread_#res := exists_runnable_thread_~__retres1~7; 656#L558-1true start_simulation_#t~ret18 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret18;havoc start_simulation_#t~ret18; 579#L1074true assume !(0 == start_simulation_~tmp~3); 580#L1074-1true havoc stop_simulation_#res;havoc stop_simulation_#t~ret17, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~7;havoc exists_runnable_thread_~__retres1~7; 298#L520-2true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7 := 1; 553#L557-2true exists_runnable_thread_#res := exists_runnable_thread_~__retres1~7; 659#L558-2true stop_simulation_#t~ret17 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret17;havoc stop_simulation_#t~ret17; 151#L1029true assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 193#L1036true stop_simulation_#res := stop_simulation_~__retres2~0; 330#L1037true start_simulation_#t~ret19 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret19;havoc start_simulation_#t~ret19; 635#L1087true assume !(0 != start_simulation_~tmp___0~1); 376#L1055-1true [2018-11-23 01:26:45,336 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 01:26:45,336 INFO L82 PathProgramCache]: Analyzing trace with hash 480768360, now seen corresponding path program 1 times [2018-11-23 01:26:45,337 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 01:26:45,338 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 01:26:45,367 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 01:26:45,367 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 01:26:45,367 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 01:26:45,395 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 01:26:45,458 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 01:26:45,459 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 01:26:45,460 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-23 01:26:45,463 INFO L799 eck$LassoCheckResult]: stem already infeasible [2018-11-23 01:26:45,463 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 01:26:45,463 INFO L82 PathProgramCache]: Analyzing trace with hash -883386385, now seen corresponding path program 1 times [2018-11-23 01:26:45,463 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 01:26:45,464 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 01:26:45,464 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 01:26:45,464 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 01:26:45,465 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 01:26:45,469 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 01:26:45,484 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 01:26:45,484 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 01:26:45,484 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2018-11-23 01:26:45,486 INFO L811 eck$LassoCheckResult]: loop already infeasible [2018-11-23 01:26:45,496 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-23 01:26:45,496 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-23 01:26:45,497 INFO L87 Difference]: Start difference. First operand 671 states. Second operand 3 states. [2018-11-23 01:26:45,537 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 01:26:45,537 INFO L93 Difference]: Finished difference Result 671 states and 1013 transitions. [2018-11-23 01:26:45,538 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-23 01:26:45,540 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 671 states and 1013 transitions. [2018-11-23 01:26:45,544 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 578 [2018-11-23 01:26:45,552 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 671 states to 665 states and 1007 transitions. [2018-11-23 01:26:45,553 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 665 [2018-11-23 01:26:45,554 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 665 [2018-11-23 01:26:45,555 INFO L73 IsDeterministic]: Start isDeterministic. Operand 665 states and 1007 transitions. [2018-11-23 01:26:45,558 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-23 01:26:45,558 INFO L705 BuchiCegarLoop]: Abstraction has 665 states and 1007 transitions. [2018-11-23 01:26:45,571 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 665 states and 1007 transitions. [2018-11-23 01:26:45,596 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 665 to 665. [2018-11-23 01:26:45,596 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 665 states. [2018-11-23 01:26:45,598 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 665 states to 665 states and 1007 transitions. [2018-11-23 01:26:45,599 INFO L728 BuchiCegarLoop]: Abstraction has 665 states and 1007 transitions. [2018-11-23 01:26:45,600 INFO L608 BuchiCegarLoop]: Abstraction has 665 states and 1007 transitions. [2018-11-23 01:26:45,600 INFO L442 BuchiCegarLoop]: ======== Iteration 2============ [2018-11-23 01:26:45,600 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 665 states and 1007 transitions. [2018-11-23 01:26:45,604 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 578 [2018-11-23 01:26:45,604 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-23 01:26:45,604 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-23 01:26:45,606 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 01:26:45,606 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 01:26:45,607 INFO L794 eck$LassoCheckResult]: Stem: 1929#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0; 1823#L-1 havoc main_#res;havoc main_~__retres1~8;havoc main_~__retres1~8;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 1607#L1018 havoc start_simulation_#t~ret18, start_simulation_#t~ret19, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 1608#L470 assume 1 == ~m_i~0;~m_st~0 := 0; 1452#L477-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1453#L482-1 assume !(1 == ~t2_i~0);~t2_st~0 := 2; 1783#L487-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 1784#L492-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 1629#L497-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 1630#L502-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 1724#L507-1 assume !(0 == ~M_E~0); 1465#L686-1 assume !(0 == ~T1_E~0); 1466#L691-1 assume 0 == ~T2_E~0;~T2_E~0 := 1; 1793#L696-1 assume !(0 == ~T3_E~0); 1794#L701-1 assume !(0 == ~T4_E~0); 1638#L706-1 assume !(0 == ~T5_E~0); 1639#L711-1 assume !(0 == ~T6_E~0); 1911#L716-1 assume !(0 == ~E_M~0); 1599#L721-1 assume !(0 == ~E_1~0); 1600#L726-1 assume !(0 == ~E_2~0); 1370#L731-1 assume 0 == ~E_3~0;~E_3~0 := 1; 1371#L736-1 assume !(0 == ~E_4~0); 1457#L741-1 assume !(0 == ~E_5~0); 1458#L746-1 assume !(0 == ~E_6~0); 1789#L751-1 havoc activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 1562#L336 assume !(1 == ~m_pc~0); 1496#L336-2 is_master_triggered_~__retres1~0 := 0; 1497#L347 is_master_triggered_#res := is_master_triggered_~__retres1~0; 1561#L348 activate_threads_#t~ret10 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 1476#L851 assume !(0 != activate_threads_~tmp~1); 1477#L851-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 1478#L355 assume 1 == ~t1_pc~0; 1403#L356 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 1404#L366 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 1455#L367 activate_threads_#t~ret11 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 1456#L859 assume !(0 != activate_threads_~tmp___0~0); 1905#L859-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 1906#L374 assume 1 == ~t2_pc~0; 1699#L375 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 1700#L385 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 1697#L386 activate_threads_#t~ret12 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 1698#L867 assume !(0 != activate_threads_~tmp___1~0); 2006#L867-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 2007#L393 assume !(1 == ~t3_pc~0); 2000#L393-2 is_transmit3_triggered_~__retres1~3 := 0; 1999#L404 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 1996#L405 activate_threads_#t~ret13 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 1604#L875 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 1589#L875-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 1590#L412 assume 1 == ~t4_pc~0; 1544#L413 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 1545#L423 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 1540#L424 activate_threads_#t~ret14 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 1541#L883 assume !(0 != activate_threads_~tmp___3~0); 1803#L883-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 1632#L431 assume !(1 == ~t5_pc~0); 1618#L431-2 is_transmit5_triggered_~__retres1~5 := 0; 1619#L442 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 1631#L443 activate_threads_#t~ret15 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 1785#L891 assume !(0 != activate_threads_~tmp___4~0); 1959#L891-2 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 1844#L450 assume 1 == ~t6_pc~0; 1845#L451 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6 := 1; 1842#L461 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 1843#L462 activate_threads_#t~ret16 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 1944#L899 assume !(0 != activate_threads_~tmp___5~0); 1962#L899-2 assume !(1 == ~M_E~0); 1366#L764-1 assume !(1 == ~T1_E~0); 1367#L769-1 assume !(1 == ~T2_E~0); 1480#L774-1 assume !(1 == ~T3_E~0); 1481#L779-1 assume !(1 == ~T4_E~0); 1804#L784-1 assume !(1 == ~T5_E~0); 1805#L789-1 assume 1 == ~T6_E~0;~T6_E~0 := 2; 1634#L794-1 assume !(1 == ~E_M~0); 1635#L799-1 assume !(1 == ~E_1~0); 1907#L804-1 assume !(1 == ~E_2~0); 1593#L809-1 assume !(1 == ~E_3~0); 1594#L814-1 assume !(1 == ~E_4~0); 1364#L819-1 assume !(1 == ~E_5~0); 1365#L824-1 assume !(1 == ~E_6~0); 1852#L1055-1 [2018-11-23 01:26:45,607 INFO L796 eck$LassoCheckResult]: Loop: 1852#L1055-1 assume !false; 1822#L1056 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret2, eval_#t~nondet3, eval_~tmp_ndt_1~0, eval_#t~nondet4, eval_~tmp_ndt_2~0, eval_#t~nondet5, eval_~tmp_ndt_3~0, eval_#t~nondet6, eval_~tmp_ndt_4~0, eval_#t~nondet7, eval_~tmp_ndt_5~0, eval_#t~nondet8, eval_~tmp_ndt_6~0, eval_#t~nondet9, eval_~tmp_ndt_7~0, eval_~tmp~0;havoc eval_~tmp~0; 1414#L661 assume !false; 1912#L568 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~7;havoc exists_runnable_thread_~__retres1~7; 1775#L520 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7 := 1; 1361#L557 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~7; 1987#L558 eval_#t~ret2 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret2;havoc eval_#t~ret2; 1954#L572 assume !(0 != eval_~tmp~0); 1351#L676 start_simulation_~kernel_st~0 := 2; 1352#L470-1 start_simulation_~kernel_st~0 := 3; 1471#L686-2 assume 0 == ~M_E~0;~M_E~0 := 1; 1472#L686-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 1474#L691-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 1801#L696-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 1802#L701-3 assume !(0 == ~T4_E~0); 1640#L706-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 1641#L711-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 1716#L716-3 assume 0 == ~E_M~0;~E_M~0 := 1; 1577#L721-3 assume 0 == ~E_1~0;~E_1~0 := 1; 1578#L726-3 assume 0 == ~E_2~0;~E_2~0 := 1; 1355#L731-3 assume 0 == ~E_3~0;~E_3~0 := 1; 1356#L736-3 assume 0 == ~E_4~0;~E_4~0 := 1; 1469#L741-3 assume !(0 == ~E_5~0); 1470#L746-3 assume 0 == ~E_6~0;~E_6~0 := 1; 1795#L751-3 havoc activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 1796#L336-24 assume 1 == ~m_pc~0; 1965#L337-8 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 1966#L347-8 is_master_triggered_#res := is_master_triggered_~__retres1~0; 1964#L348-8 activate_threads_#t~ret10 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 1402#L851-24 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 1372#L851-26 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 1373#L355-24 assume 1 == ~t1_pc~0; 1394#L356-8 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 1395#L366-8 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 1391#L367-8 activate_threads_#t~ret11 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 1392#L859-24 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 1653#L859-26 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 1654#L374-24 assume 1 == ~t2_pc~0; 1691#L375-8 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 1693#L385-8 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 1689#L386-8 activate_threads_#t~ret12 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 1690#L867-24 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 1853#L867-26 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 1854#L393-24 assume 1 == ~t3_pc~0; 1868#L394-8 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 1869#L404-8 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 1866#L405-8 activate_threads_#t~ret13 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 1867#L875-24 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 1991#L875-26 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 1571#L412-24 assume 1 == ~t4_pc~0; 1528#L413-8 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 1529#L423-8 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 1526#L424-8 activate_threads_#t~ret14 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 1527#L883-24 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 1725#L883-26 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 1726#L431-24 assume !(1 == ~t5_pc~0); 1745#L431-26 is_transmit5_triggered_~__retres1~5 := 0; 1744#L442-8 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 1741#L443-8 activate_threads_#t~ret15 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 1742#L891-24 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 1921#L891-26 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 1924#L450-24 assume 1 == ~t6_pc~0; 1938#L451-8 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6 := 1; 1839#L461-8 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 1840#L462-8 activate_threads_#t~ret16 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 1937#L899-24 assume 0 != activate_threads_~tmp___5~0;~t6_st~0 := 0; 2008#L899-26 assume !(1 == ~M_E~0); 1353#L764-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 1354#L769-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 1461#L774-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 1462#L779-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 1791#L784-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 1792#L789-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 1636#L794-3 assume 1 == ~E_M~0;~E_M~0 := 2; 1637#L799-3 assume !(1 == ~E_1~0); 1909#L804-3 assume 1 == ~E_2~0;~E_2~0 := 2; 1597#L809-3 assume 1 == ~E_3~0;~E_3~0 := 2; 1598#L814-3 assume 1 == ~E_4~0;~E_4~0 := 2; 1368#L819-3 assume 1 == ~E_5~0;~E_5~0 := 2; 1369#L824-3 assume 1 == ~E_6~0;~E_6~0 := 2; 1482#L829-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~7;havoc exists_runnable_thread_~__retres1~7; 1483#L520-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7 := 1; 1363#L557-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~7; 1988#L558-1 start_simulation_#t~ret18 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret18;havoc start_simulation_#t~ret18; 1992#L1074 assume !(0 == start_simulation_~tmp~3); 1659#L1074-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret17, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~7;havoc exists_runnable_thread_~__retres1~7; 1781#L520-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7 := 1; 1446#L557-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~7; 1989#L558-2 stop_simulation_#t~ret17 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret17;havoc stop_simulation_#t~ret17; 1605#L1029 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 1606#L1036 stop_simulation_#res := stop_simulation_~__retres2~0; 1655#L1037 start_simulation_#t~ret19 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret19;havoc start_simulation_#t~ret19; 1807#L1087 assume !(0 != start_simulation_~tmp___0~1); 1852#L1055-1 [2018-11-23 01:26:45,607 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 01:26:45,608 INFO L82 PathProgramCache]: Analyzing trace with hash 453702758, now seen corresponding path program 1 times [2018-11-23 01:26:45,608 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 01:26:45,608 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 01:26:45,609 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 01:26:45,609 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 01:26:45,609 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 01:26:45,619 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 01:26:45,651 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 01:26:45,651 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 01:26:45,652 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-23 01:26:45,652 INFO L799 eck$LassoCheckResult]: stem already infeasible [2018-11-23 01:26:45,652 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 01:26:45,653 INFO L82 PathProgramCache]: Analyzing trace with hash 613150449, now seen corresponding path program 1 times [2018-11-23 01:26:45,653 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 01:26:45,653 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 01:26:45,654 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 01:26:45,654 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 01:26:45,654 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 01:26:45,672 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 01:26:45,709 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 01:26:45,709 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 01:26:45,709 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-23 01:26:45,709 INFO L811 eck$LassoCheckResult]: loop already infeasible [2018-11-23 01:26:45,710 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-23 01:26:45,710 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-23 01:26:45,710 INFO L87 Difference]: Start difference. First operand 665 states and 1007 transitions. cyclomatic complexity: 343 Second operand 3 states. [2018-11-23 01:26:45,728 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 01:26:45,728 INFO L93 Difference]: Finished difference Result 665 states and 1006 transitions. [2018-11-23 01:26:45,729 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-23 01:26:45,730 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 665 states and 1006 transitions. [2018-11-23 01:26:45,734 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 578 [2018-11-23 01:26:45,737 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 665 states to 665 states and 1006 transitions. [2018-11-23 01:26:45,738 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 665 [2018-11-23 01:26:45,738 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 665 [2018-11-23 01:26:45,739 INFO L73 IsDeterministic]: Start isDeterministic. Operand 665 states and 1006 transitions. [2018-11-23 01:26:45,740 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-23 01:26:45,740 INFO L705 BuchiCegarLoop]: Abstraction has 665 states and 1006 transitions. [2018-11-23 01:26:45,741 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 665 states and 1006 transitions. [2018-11-23 01:26:45,752 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 665 to 665. [2018-11-23 01:26:45,752 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 665 states. [2018-11-23 01:26:45,754 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 665 states to 665 states and 1006 transitions. [2018-11-23 01:26:45,754 INFO L728 BuchiCegarLoop]: Abstraction has 665 states and 1006 transitions. [2018-11-23 01:26:45,755 INFO L608 BuchiCegarLoop]: Abstraction has 665 states and 1006 transitions. [2018-11-23 01:26:45,755 INFO L442 BuchiCegarLoop]: ======== Iteration 3============ [2018-11-23 01:26:45,755 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 665 states and 1006 transitions. [2018-11-23 01:26:45,758 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 578 [2018-11-23 01:26:45,758 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-23 01:26:45,758 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-23 01:26:45,760 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 01:26:45,760 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 01:26:45,761 INFO L794 eck$LassoCheckResult]: Stem: 3266#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0; 3160#L-1 havoc main_#res;havoc main_~__retres1~8;havoc main_~__retres1~8;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 2944#L1018 havoc start_simulation_#t~ret18, start_simulation_#t~ret19, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 2945#L470 assume 1 == ~m_i~0;~m_st~0 := 0; 2789#L477-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 2790#L482-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 3120#L487-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 3121#L492-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 2966#L497-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 2967#L502-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 3061#L507-1 assume !(0 == ~M_E~0); 2804#L686-1 assume !(0 == ~T1_E~0); 2805#L691-1 assume 0 == ~T2_E~0;~T2_E~0 := 1; 3130#L696-1 assume !(0 == ~T3_E~0); 3131#L701-1 assume !(0 == ~T4_E~0); 2975#L706-1 assume !(0 == ~T5_E~0); 2976#L711-1 assume !(0 == ~T6_E~0); 3248#L716-1 assume !(0 == ~E_M~0); 2936#L721-1 assume !(0 == ~E_1~0); 2937#L726-1 assume !(0 == ~E_2~0); 2707#L731-1 assume 0 == ~E_3~0;~E_3~0 := 1; 2708#L736-1 assume !(0 == ~E_4~0); 2794#L741-1 assume !(0 == ~E_5~0); 2795#L746-1 assume !(0 == ~E_6~0); 3126#L751-1 havoc activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 2899#L336 assume !(1 == ~m_pc~0); 2833#L336-2 is_master_triggered_~__retres1~0 := 0; 2834#L347 is_master_triggered_#res := is_master_triggered_~__retres1~0; 2895#L348 activate_threads_#t~ret10 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 2813#L851 assume !(0 != activate_threads_~tmp~1); 2814#L851-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 2815#L355 assume 1 == ~t1_pc~0; 2740#L356 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 2741#L366 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 2792#L367 activate_threads_#t~ret11 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 2793#L859 assume !(0 != activate_threads_~tmp___0~0); 3242#L859-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 3243#L374 assume 1 == ~t2_pc~0; 3036#L375 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 3037#L385 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 3034#L386 activate_threads_#t~ret12 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 3035#L867 assume !(0 != activate_threads_~tmp___1~0); 3343#L867-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 3344#L393 assume !(1 == ~t3_pc~0); 3337#L393-2 is_transmit3_triggered_~__retres1~3 := 0; 3336#L404 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 3333#L405 activate_threads_#t~ret13 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 2941#L875 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 2926#L875-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 2927#L412 assume 1 == ~t4_pc~0; 2879#L413 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 2880#L423 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 2877#L424 activate_threads_#t~ret14 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 2878#L883 assume !(0 != activate_threads_~tmp___3~0); 3140#L883-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 2969#L431 assume !(1 == ~t5_pc~0); 2955#L431-2 is_transmit5_triggered_~__retres1~5 := 0; 2956#L442 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 2968#L443 activate_threads_#t~ret15 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 3122#L891 assume !(0 != activate_threads_~tmp___4~0); 3296#L891-2 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 3181#L450 assume 1 == ~t6_pc~0; 3182#L451 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6 := 1; 3179#L461 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 3180#L462 activate_threads_#t~ret16 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 3280#L899 assume !(0 != activate_threads_~tmp___5~0); 3298#L899-2 assume !(1 == ~M_E~0); 2703#L764-1 assume !(1 == ~T1_E~0); 2704#L769-1 assume !(1 == ~T2_E~0); 2817#L774-1 assume !(1 == ~T3_E~0); 2818#L779-1 assume !(1 == ~T4_E~0); 3141#L784-1 assume !(1 == ~T5_E~0); 3142#L789-1 assume 1 == ~T6_E~0;~T6_E~0 := 2; 2971#L794-1 assume !(1 == ~E_M~0); 2972#L799-1 assume !(1 == ~E_1~0); 3244#L804-1 assume !(1 == ~E_2~0); 2928#L809-1 assume !(1 == ~E_3~0); 2929#L814-1 assume !(1 == ~E_4~0); 2701#L819-1 assume !(1 == ~E_5~0); 2702#L824-1 assume !(1 == ~E_6~0); 3189#L1055-1 [2018-11-23 01:26:45,761 INFO L796 eck$LassoCheckResult]: Loop: 3189#L1055-1 assume !false; 3159#L1056 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret2, eval_#t~nondet3, eval_~tmp_ndt_1~0, eval_#t~nondet4, eval_~tmp_ndt_2~0, eval_#t~nondet5, eval_~tmp_ndt_3~0, eval_#t~nondet6, eval_~tmp_ndt_4~0, eval_#t~nondet7, eval_~tmp_ndt_5~0, eval_#t~nondet8, eval_~tmp_ndt_6~0, eval_#t~nondet9, eval_~tmp_ndt_7~0, eval_~tmp~0;havoc eval_~tmp~0; 2751#L661 assume !false; 3249#L568 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~7;havoc exists_runnable_thread_~__retres1~7; 3110#L520 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7 := 1; 2698#L557 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~7; 3324#L558 eval_#t~ret2 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret2;havoc eval_#t~ret2; 3291#L572 assume !(0 != eval_~tmp~0); 2688#L676 start_simulation_~kernel_st~0 := 2; 2689#L470-1 start_simulation_~kernel_st~0 := 3; 2808#L686-2 assume 0 == ~M_E~0;~M_E~0 := 1; 2809#L686-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 2811#L691-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 3138#L696-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 3139#L701-3 assume !(0 == ~T4_E~0); 2977#L706-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 2978#L711-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 3053#L716-3 assume 0 == ~E_M~0;~E_M~0 := 1; 2914#L721-3 assume 0 == ~E_1~0;~E_1~0 := 1; 2915#L726-3 assume 0 == ~E_2~0;~E_2~0 := 1; 2692#L731-3 assume 0 == ~E_3~0;~E_3~0 := 1; 2693#L736-3 assume 0 == ~E_4~0;~E_4~0 := 1; 2806#L741-3 assume !(0 == ~E_5~0); 2807#L746-3 assume 0 == ~E_6~0;~E_6~0 := 1; 3132#L751-3 havoc activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 3133#L336-24 assume 1 == ~m_pc~0; 3302#L337-8 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 3303#L347-8 is_master_triggered_#res := is_master_triggered_~__retres1~0; 3301#L348-8 activate_threads_#t~ret10 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 2736#L851-24 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 2709#L851-26 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 2710#L355-24 assume 1 == ~t1_pc~0; 2731#L356-8 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 2732#L366-8 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 2728#L367-8 activate_threads_#t~ret11 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 2729#L859-24 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 2990#L859-26 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 2991#L374-24 assume 1 == ~t2_pc~0; 3029#L375-8 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 3031#L385-8 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 3026#L386-8 activate_threads_#t~ret12 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 3027#L867-24 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 3190#L867-26 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 3191#L393-24 assume 1 == ~t3_pc~0; 3205#L394-8 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 3206#L404-8 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 3203#L405-8 activate_threads_#t~ret13 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 3204#L875-24 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 3328#L875-26 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 2908#L412-24 assume 1 == ~t4_pc~0; 2867#L413-8 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 2868#L423-8 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 2863#L424-8 activate_threads_#t~ret14 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 2864#L883-24 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 3062#L883-26 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 3063#L431-24 assume 1 == ~t5_pc~0; 3080#L432-8 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 3081#L442-8 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 3078#L443-8 activate_threads_#t~ret15 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 3079#L891-24 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 3258#L891-26 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 3261#L450-24 assume 1 == ~t6_pc~0; 3275#L451-8 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6 := 1; 3176#L461-8 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 3177#L462-8 activate_threads_#t~ret16 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 3274#L899-24 assume 0 != activate_threads_~tmp___5~0;~t6_st~0 := 0; 3345#L899-26 assume !(1 == ~M_E~0); 2690#L764-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 2691#L769-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 2798#L774-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 2799#L779-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 3128#L784-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 3129#L789-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 2973#L794-3 assume 1 == ~E_M~0;~E_M~0 := 2; 2974#L799-3 assume !(1 == ~E_1~0); 3246#L804-3 assume 1 == ~E_2~0;~E_2~0 := 2; 2934#L809-3 assume 1 == ~E_3~0;~E_3~0 := 2; 2935#L814-3 assume 1 == ~E_4~0;~E_4~0 := 2; 2705#L819-3 assume 1 == ~E_5~0;~E_5~0 := 2; 2706#L824-3 assume 1 == ~E_6~0;~E_6~0 := 2; 2819#L829-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~7;havoc exists_runnable_thread_~__retres1~7; 2820#L520-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7 := 1; 2700#L557-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~7; 3325#L558-1 start_simulation_#t~ret18 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret18;havoc start_simulation_#t~ret18; 3329#L1074 assume !(0 == start_simulation_~tmp~3); 2997#L1074-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret17, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~7;havoc exists_runnable_thread_~__retres1~7; 3118#L520-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7 := 1; 2783#L557-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~7; 3326#L558-2 stop_simulation_#t~ret17 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret17;havoc stop_simulation_#t~ret17; 2942#L1029 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 2943#L1036 stop_simulation_#res := stop_simulation_~__retres2~0; 2992#L1037 start_simulation_#t~ret19 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret19;havoc start_simulation_#t~ret19; 3146#L1087 assume !(0 != start_simulation_~tmp___0~1); 3189#L1055-1 [2018-11-23 01:26:45,761 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 01:26:45,762 INFO L82 PathProgramCache]: Analyzing trace with hash -1280401692, now seen corresponding path program 1 times [2018-11-23 01:26:45,762 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 01:26:45,762 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 01:26:45,763 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 01:26:45,763 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 01:26:45,763 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 01:26:45,769 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 01:26:45,789 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 01:26:45,790 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 01:26:45,790 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-23 01:26:45,790 INFO L799 eck$LassoCheckResult]: stem already infeasible [2018-11-23 01:26:45,790 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 01:26:45,790 INFO L82 PathProgramCache]: Analyzing trace with hash 89829778, now seen corresponding path program 1 times [2018-11-23 01:26:45,791 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 01:26:45,791 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 01:26:45,791 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 01:26:45,791 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 01:26:45,792 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 01:26:45,807 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 01:26:45,841 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 01:26:45,842 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 01:26:45,842 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-23 01:26:45,842 INFO L811 eck$LassoCheckResult]: loop already infeasible [2018-11-23 01:26:45,842 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-23 01:26:45,842 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-23 01:26:45,842 INFO L87 Difference]: Start difference. First operand 665 states and 1006 transitions. cyclomatic complexity: 342 Second operand 3 states. [2018-11-23 01:26:45,851 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 01:26:45,851 INFO L93 Difference]: Finished difference Result 665 states and 1005 transitions. [2018-11-23 01:26:45,852 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-23 01:26:45,852 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 665 states and 1005 transitions. [2018-11-23 01:26:45,854 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 578 [2018-11-23 01:26:45,857 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 665 states to 665 states and 1005 transitions. [2018-11-23 01:26:45,857 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 665 [2018-11-23 01:26:45,857 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 665 [2018-11-23 01:26:45,857 INFO L73 IsDeterministic]: Start isDeterministic. Operand 665 states and 1005 transitions. [2018-11-23 01:26:45,858 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-23 01:26:45,858 INFO L705 BuchiCegarLoop]: Abstraction has 665 states and 1005 transitions. [2018-11-23 01:26:45,859 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 665 states and 1005 transitions. [2018-11-23 01:26:45,864 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 665 to 665. [2018-11-23 01:26:45,864 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 665 states. [2018-11-23 01:26:45,866 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 665 states to 665 states and 1005 transitions. [2018-11-23 01:26:45,866 INFO L728 BuchiCegarLoop]: Abstraction has 665 states and 1005 transitions. [2018-11-23 01:26:45,866 INFO L608 BuchiCegarLoop]: Abstraction has 665 states and 1005 transitions. [2018-11-23 01:26:45,866 INFO L442 BuchiCegarLoop]: ======== Iteration 4============ [2018-11-23 01:26:45,866 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 665 states and 1005 transitions. [2018-11-23 01:26:45,868 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 578 [2018-11-23 01:26:45,868 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-23 01:26:45,868 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-23 01:26:45,869 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 01:26:45,870 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 01:26:45,870 INFO L794 eck$LassoCheckResult]: Stem: 4603#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0; 4497#L-1 havoc main_#res;havoc main_~__retres1~8;havoc main_~__retres1~8;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 4281#L1018 havoc start_simulation_#t~ret18, start_simulation_#t~ret19, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 4282#L470 assume 1 == ~m_i~0;~m_st~0 := 0; 4126#L477-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 4127#L482-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 4455#L487-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 4456#L492-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 4303#L497-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 4304#L502-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 4397#L507-1 assume !(0 == ~M_E~0); 4139#L686-1 assume !(0 == ~T1_E~0); 4140#L691-1 assume 0 == ~T2_E~0;~T2_E~0 := 1; 4467#L696-1 assume !(0 == ~T3_E~0); 4468#L701-1 assume !(0 == ~T4_E~0); 4312#L706-1 assume !(0 == ~T5_E~0); 4313#L711-1 assume !(0 == ~T6_E~0); 4585#L716-1 assume !(0 == ~E_M~0); 4273#L721-1 assume !(0 == ~E_1~0); 4274#L726-1 assume !(0 == ~E_2~0); 4044#L731-1 assume 0 == ~E_3~0;~E_3~0 := 1; 4045#L736-1 assume !(0 == ~E_4~0); 4131#L741-1 assume !(0 == ~E_5~0); 4132#L746-1 assume !(0 == ~E_6~0); 4462#L751-1 havoc activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 4236#L336 assume !(1 == ~m_pc~0); 4170#L336-2 is_master_triggered_~__retres1~0 := 0; 4171#L347 is_master_triggered_#res := is_master_triggered_~__retres1~0; 4232#L348 activate_threads_#t~ret10 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 4150#L851 assume !(0 != activate_threads_~tmp~1); 4151#L851-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 4152#L355 assume 1 == ~t1_pc~0; 4077#L356 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 4078#L366 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 4129#L367 activate_threads_#t~ret11 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 4130#L859 assume !(0 != activate_threads_~tmp___0~0); 4579#L859-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 4580#L374 assume 1 == ~t2_pc~0; 4373#L375 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 4374#L385 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 4371#L386 activate_threads_#t~ret12 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 4372#L867 assume !(0 != activate_threads_~tmp___1~0); 4680#L867-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 4681#L393 assume !(1 == ~t3_pc~0); 4674#L393-2 is_transmit3_triggered_~__retres1~3 := 0; 4673#L404 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 4670#L405 activate_threads_#t~ret13 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 4278#L875 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 4263#L875-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 4264#L412 assume 1 == ~t4_pc~0; 4216#L413 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 4217#L423 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 4214#L424 activate_threads_#t~ret14 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 4215#L883 assume !(0 != activate_threads_~tmp___3~0); 4477#L883-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 4306#L431 assume !(1 == ~t5_pc~0); 4292#L431-2 is_transmit5_triggered_~__retres1~5 := 0; 4293#L442 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 4305#L443 activate_threads_#t~ret15 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 4459#L891 assume !(0 != activate_threads_~tmp___4~0); 4633#L891-2 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 4518#L450 assume 1 == ~t6_pc~0; 4519#L451 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6 := 1; 4516#L461 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 4517#L462 activate_threads_#t~ret16 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 4617#L899 assume !(0 != activate_threads_~tmp___5~0); 4635#L899-2 assume !(1 == ~M_E~0); 4040#L764-1 assume !(1 == ~T1_E~0); 4041#L769-1 assume !(1 == ~T2_E~0); 4154#L774-1 assume !(1 == ~T3_E~0); 4155#L779-1 assume !(1 == ~T4_E~0); 4478#L784-1 assume !(1 == ~T5_E~0); 4479#L789-1 assume 1 == ~T6_E~0;~T6_E~0 := 2; 4308#L794-1 assume !(1 == ~E_M~0); 4309#L799-1 assume !(1 == ~E_1~0); 4581#L804-1 assume !(1 == ~E_2~0); 4265#L809-1 assume !(1 == ~E_3~0); 4266#L814-1 assume !(1 == ~E_4~0); 4038#L819-1 assume !(1 == ~E_5~0); 4039#L824-1 assume !(1 == ~E_6~0); 4526#L1055-1 [2018-11-23 01:26:45,870 INFO L796 eck$LassoCheckResult]: Loop: 4526#L1055-1 assume !false; 4496#L1056 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret2, eval_#t~nondet3, eval_~tmp_ndt_1~0, eval_#t~nondet4, eval_~tmp_ndt_2~0, eval_#t~nondet5, eval_~tmp_ndt_3~0, eval_#t~nondet6, eval_~tmp_ndt_4~0, eval_#t~nondet7, eval_~tmp_ndt_5~0, eval_#t~nondet8, eval_~tmp_ndt_6~0, eval_#t~nondet9, eval_~tmp_ndt_7~0, eval_~tmp~0;havoc eval_~tmp~0; 4088#L661 assume !false; 4586#L568 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~7;havoc exists_runnable_thread_~__retres1~7; 4447#L520 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7 := 1; 4035#L557 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~7; 4661#L558 eval_#t~ret2 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret2;havoc eval_#t~ret2; 4628#L572 assume !(0 != eval_~tmp~0); 4025#L676 start_simulation_~kernel_st~0 := 2; 4026#L470-1 start_simulation_~kernel_st~0 := 3; 4145#L686-2 assume 0 == ~M_E~0;~M_E~0 := 1; 4146#L686-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 4148#L691-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 4475#L696-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 4476#L701-3 assume !(0 == ~T4_E~0); 4314#L706-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 4315#L711-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 4390#L716-3 assume 0 == ~E_M~0;~E_M~0 := 1; 4251#L721-3 assume 0 == ~E_1~0;~E_1~0 := 1; 4252#L726-3 assume 0 == ~E_2~0;~E_2~0 := 1; 4029#L731-3 assume 0 == ~E_3~0;~E_3~0 := 1; 4030#L736-3 assume 0 == ~E_4~0;~E_4~0 := 1; 4143#L741-3 assume !(0 == ~E_5~0); 4144#L746-3 assume 0 == ~E_6~0;~E_6~0 := 1; 4469#L751-3 havoc activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 4470#L336-24 assume !(1 == ~m_pc~0); 4641#L336-26 is_master_triggered_~__retres1~0 := 0; 4640#L347-8 is_master_triggered_#res := is_master_triggered_~__retres1~0; 4638#L348-8 activate_threads_#t~ret10 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 4073#L851-24 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 4046#L851-26 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 4047#L355-24 assume 1 == ~t1_pc~0; 4068#L356-8 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 4069#L366-8 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 4065#L367-8 activate_threads_#t~ret11 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 4066#L859-24 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 4327#L859-26 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 4328#L374-24 assume 1 == ~t2_pc~0; 4366#L375-8 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 4368#L385-8 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 4363#L386-8 activate_threads_#t~ret12 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 4364#L867-24 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 4527#L867-26 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 4528#L393-24 assume !(1 == ~t3_pc~0); 4544#L393-26 is_transmit3_triggered_~__retres1~3 := 0; 4543#L404-8 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 4540#L405-8 activate_threads_#t~ret13 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 4541#L875-24 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 4665#L875-26 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 4245#L412-24 assume 1 == ~t4_pc~0; 4204#L413-8 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 4205#L423-8 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 4200#L424-8 activate_threads_#t~ret14 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 4201#L883-24 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 4399#L883-26 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 4400#L431-24 assume 1 == ~t5_pc~0; 4417#L432-8 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 4418#L442-8 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 4415#L443-8 activate_threads_#t~ret15 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 4416#L891-24 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 4595#L891-26 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 4598#L450-24 assume 1 == ~t6_pc~0; 4612#L451-8 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6 := 1; 4513#L461-8 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 4514#L462-8 activate_threads_#t~ret16 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 4611#L899-24 assume 0 != activate_threads_~tmp___5~0;~t6_st~0 := 0; 4682#L899-26 assume !(1 == ~M_E~0); 4027#L764-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 4028#L769-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 4135#L774-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 4136#L779-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 4465#L784-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 4466#L789-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 4310#L794-3 assume 1 == ~E_M~0;~E_M~0 := 2; 4311#L799-3 assume !(1 == ~E_1~0); 4583#L804-3 assume 1 == ~E_2~0;~E_2~0 := 2; 4271#L809-3 assume 1 == ~E_3~0;~E_3~0 := 2; 4272#L814-3 assume 1 == ~E_4~0;~E_4~0 := 2; 4042#L819-3 assume 1 == ~E_5~0;~E_5~0 := 2; 4043#L824-3 assume 1 == ~E_6~0;~E_6~0 := 2; 4156#L829-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~7;havoc exists_runnable_thread_~__retres1~7; 4157#L520-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7 := 1; 4037#L557-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~7; 4662#L558-1 start_simulation_#t~ret18 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret18;havoc start_simulation_#t~ret18; 4666#L1074 assume !(0 == start_simulation_~tmp~3); 4334#L1074-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret17, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~7;havoc exists_runnable_thread_~__retres1~7; 4457#L520-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7 := 1; 4120#L557-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~7; 4663#L558-2 stop_simulation_#t~ret17 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret17;havoc stop_simulation_#t~ret17; 4279#L1029 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 4280#L1036 stop_simulation_#res := stop_simulation_~__retres2~0; 4329#L1037 start_simulation_#t~ret19 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret19;havoc start_simulation_#t~ret19; 4483#L1087 assume !(0 != start_simulation_~tmp___0~1); 4526#L1055-1 [2018-11-23 01:26:45,870 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 01:26:45,871 INFO L82 PathProgramCache]: Analyzing trace with hash 2127342758, now seen corresponding path program 1 times [2018-11-23 01:26:45,871 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 01:26:45,871 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 01:26:45,872 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 01:26:45,872 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 01:26:45,872 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 01:26:45,877 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 01:26:45,901 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 01:26:45,902 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 01:26:45,902 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-23 01:26:45,902 INFO L799 eck$LassoCheckResult]: stem already infeasible [2018-11-23 01:26:45,902 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 01:26:45,902 INFO L82 PathProgramCache]: Analyzing trace with hash 197305744, now seen corresponding path program 1 times [2018-11-23 01:26:45,903 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 01:26:45,903 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 01:26:45,903 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 01:26:45,903 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 01:26:45,904 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 01:26:45,912 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 01:26:45,974 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 01:26:45,974 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 01:26:45,975 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-23 01:26:45,975 INFO L811 eck$LassoCheckResult]: loop already infeasible [2018-11-23 01:26:45,975 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-23 01:26:45,975 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-23 01:26:45,975 INFO L87 Difference]: Start difference. First operand 665 states and 1005 transitions. cyclomatic complexity: 341 Second operand 3 states. [2018-11-23 01:26:45,983 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 01:26:45,984 INFO L93 Difference]: Finished difference Result 665 states and 1004 transitions. [2018-11-23 01:26:45,984 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-23 01:26:45,984 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 665 states and 1004 transitions. [2018-11-23 01:26:45,986 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 578 [2018-11-23 01:26:45,988 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 665 states to 665 states and 1004 transitions. [2018-11-23 01:26:45,988 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 665 [2018-11-23 01:26:45,989 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 665 [2018-11-23 01:26:45,989 INFO L73 IsDeterministic]: Start isDeterministic. Operand 665 states and 1004 transitions. [2018-11-23 01:26:45,989 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-23 01:26:45,989 INFO L705 BuchiCegarLoop]: Abstraction has 665 states and 1004 transitions. [2018-11-23 01:26:45,990 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 665 states and 1004 transitions. [2018-11-23 01:26:45,994 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 665 to 665. [2018-11-23 01:26:45,994 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 665 states. [2018-11-23 01:26:45,995 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 665 states to 665 states and 1004 transitions. [2018-11-23 01:26:45,996 INFO L728 BuchiCegarLoop]: Abstraction has 665 states and 1004 transitions. [2018-11-23 01:26:45,996 INFO L608 BuchiCegarLoop]: Abstraction has 665 states and 1004 transitions. [2018-11-23 01:26:45,996 INFO L442 BuchiCegarLoop]: ======== Iteration 5============ [2018-11-23 01:26:45,996 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 665 states and 1004 transitions. [2018-11-23 01:26:45,998 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 578 [2018-11-23 01:26:45,998 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-23 01:26:45,998 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-23 01:26:45,999 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 01:26:45,999 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 01:26:46,000 INFO L794 eck$LassoCheckResult]: Stem: 5940#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0; 5834#L-1 havoc main_#res;havoc main_~__retres1~8;havoc main_~__retres1~8;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 5618#L1018 havoc start_simulation_#t~ret18, start_simulation_#t~ret19, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 5619#L470 assume 1 == ~m_i~0;~m_st~0 := 0; 5463#L477-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 5464#L482-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 5794#L487-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 5795#L492-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 5640#L497-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 5641#L502-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 5735#L507-1 assume !(0 == ~M_E~0); 5476#L686-1 assume !(0 == ~T1_E~0); 5477#L691-1 assume 0 == ~T2_E~0;~T2_E~0 := 1; 5804#L696-1 assume !(0 == ~T3_E~0); 5805#L701-1 assume !(0 == ~T4_E~0); 5649#L706-1 assume !(0 == ~T5_E~0); 5650#L711-1 assume !(0 == ~T6_E~0); 5922#L716-1 assume !(0 == ~E_M~0); 5610#L721-1 assume !(0 == ~E_1~0); 5611#L726-1 assume !(0 == ~E_2~0); 5381#L731-1 assume 0 == ~E_3~0;~E_3~0 := 1; 5382#L736-1 assume !(0 == ~E_4~0); 5468#L741-1 assume !(0 == ~E_5~0); 5469#L746-1 assume !(0 == ~E_6~0); 5799#L751-1 havoc activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 5573#L336 assume !(1 == ~m_pc~0); 5507#L336-2 is_master_triggered_~__retres1~0 := 0; 5508#L347 is_master_triggered_#res := is_master_triggered_~__retres1~0; 5569#L348 activate_threads_#t~ret10 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 5487#L851 assume !(0 != activate_threads_~tmp~1); 5488#L851-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 5489#L355 assume 1 == ~t1_pc~0; 5414#L356 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 5415#L366 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 5466#L367 activate_threads_#t~ret11 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 5467#L859 assume !(0 != activate_threads_~tmp___0~0); 5916#L859-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 5917#L374 assume 1 == ~t2_pc~0; 5710#L375 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 5711#L385 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 5708#L386 activate_threads_#t~ret12 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 5709#L867 assume !(0 != activate_threads_~tmp___1~0); 6017#L867-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 6018#L393 assume !(1 == ~t3_pc~0); 6011#L393-2 is_transmit3_triggered_~__retres1~3 := 0; 6010#L404 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 6007#L405 activate_threads_#t~ret13 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 5615#L875 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 5600#L875-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 5601#L412 assume 1 == ~t4_pc~0; 5553#L413 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 5554#L423 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 5551#L424 activate_threads_#t~ret14 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 5552#L883 assume !(0 != activate_threads_~tmp___3~0); 5814#L883-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 5643#L431 assume !(1 == ~t5_pc~0); 5629#L431-2 is_transmit5_triggered_~__retres1~5 := 0; 5630#L442 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 5642#L443 activate_threads_#t~ret15 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 5796#L891 assume !(0 != activate_threads_~tmp___4~0); 5970#L891-2 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 5855#L450 assume 1 == ~t6_pc~0; 5856#L451 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6 := 1; 5853#L461 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 5854#L462 activate_threads_#t~ret16 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 5955#L899 assume !(0 != activate_threads_~tmp___5~0); 5973#L899-2 assume !(1 == ~M_E~0); 5377#L764-1 assume !(1 == ~T1_E~0); 5378#L769-1 assume !(1 == ~T2_E~0); 5491#L774-1 assume !(1 == ~T3_E~0); 5492#L779-1 assume !(1 == ~T4_E~0); 5815#L784-1 assume !(1 == ~T5_E~0); 5816#L789-1 assume 1 == ~T6_E~0;~T6_E~0 := 2; 5645#L794-1 assume !(1 == ~E_M~0); 5646#L799-1 assume !(1 == ~E_1~0); 5918#L804-1 assume !(1 == ~E_2~0); 5602#L809-1 assume !(1 == ~E_3~0); 5603#L814-1 assume !(1 == ~E_4~0); 5375#L819-1 assume !(1 == ~E_5~0); 5376#L824-1 assume !(1 == ~E_6~0); 5863#L1055-1 [2018-11-23 01:26:46,000 INFO L796 eck$LassoCheckResult]: Loop: 5863#L1055-1 assume !false; 5833#L1056 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret2, eval_#t~nondet3, eval_~tmp_ndt_1~0, eval_#t~nondet4, eval_~tmp_ndt_2~0, eval_#t~nondet5, eval_~tmp_ndt_3~0, eval_#t~nondet6, eval_~tmp_ndt_4~0, eval_#t~nondet7, eval_~tmp_ndt_5~0, eval_#t~nondet8, eval_~tmp_ndt_6~0, eval_#t~nondet9, eval_~tmp_ndt_7~0, eval_~tmp~0;havoc eval_~tmp~0; 5425#L661 assume !false; 5923#L568 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~7;havoc exists_runnable_thread_~__retres1~7; 5786#L520 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7 := 1; 5372#L557 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~7; 5998#L558 eval_#t~ret2 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret2;havoc eval_#t~ret2; 5965#L572 assume !(0 != eval_~tmp~0); 5362#L676 start_simulation_~kernel_st~0 := 2; 5363#L470-1 start_simulation_~kernel_st~0 := 3; 5482#L686-2 assume 0 == ~M_E~0;~M_E~0 := 1; 5483#L686-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 5485#L691-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 5812#L696-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 5813#L701-3 assume !(0 == ~T4_E~0); 5651#L706-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 5652#L711-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 5727#L716-3 assume 0 == ~E_M~0;~E_M~0 := 1; 5588#L721-3 assume 0 == ~E_1~0;~E_1~0 := 1; 5589#L726-3 assume 0 == ~E_2~0;~E_2~0 := 1; 5366#L731-3 assume 0 == ~E_3~0;~E_3~0 := 1; 5367#L736-3 assume 0 == ~E_4~0;~E_4~0 := 1; 5480#L741-3 assume !(0 == ~E_5~0); 5481#L746-3 assume 0 == ~E_6~0;~E_6~0 := 1; 5806#L751-3 havoc activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 5807#L336-24 assume 1 == ~m_pc~0; 5976#L337-8 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 5977#L347-8 is_master_triggered_#res := is_master_triggered_~__retres1~0; 5975#L348-8 activate_threads_#t~ret10 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 5413#L851-24 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 5383#L851-26 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 5384#L355-24 assume 1 == ~t1_pc~0; 5405#L356-8 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 5406#L366-8 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 5402#L367-8 activate_threads_#t~ret11 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 5403#L859-24 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 5664#L859-26 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 5666#L374-24 assume 1 == ~t2_pc~0; 5703#L375-8 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 5705#L385-8 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 5700#L386-8 activate_threads_#t~ret12 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 5701#L867-24 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 5864#L867-26 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 5865#L393-24 assume 1 == ~t3_pc~0; 5879#L394-8 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 5880#L404-8 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 5877#L405-8 activate_threads_#t~ret13 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 5878#L875-24 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 6002#L875-26 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 5582#L412-24 assume 1 == ~t4_pc~0; 5539#L413-8 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 5540#L423-8 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 5537#L424-8 activate_threads_#t~ret14 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 5538#L883-24 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 5736#L883-26 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 5737#L431-24 assume 1 == ~t5_pc~0; 5754#L432-8 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 5755#L442-8 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 5752#L443-8 activate_threads_#t~ret15 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 5753#L891-24 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 5932#L891-26 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 5935#L450-24 assume 1 == ~t6_pc~0; 5949#L451-8 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6 := 1; 5850#L461-8 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 5851#L462-8 activate_threads_#t~ret16 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 5948#L899-24 assume 0 != activate_threads_~tmp___5~0;~t6_st~0 := 0; 6019#L899-26 assume !(1 == ~M_E~0); 5364#L764-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 5365#L769-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 5472#L774-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 5473#L779-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 5801#L784-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 5802#L789-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 5647#L794-3 assume 1 == ~E_M~0;~E_M~0 := 2; 5648#L799-3 assume !(1 == ~E_1~0); 5920#L804-3 assume 1 == ~E_2~0;~E_2~0 := 2; 5607#L809-3 assume 1 == ~E_3~0;~E_3~0 := 2; 5608#L814-3 assume 1 == ~E_4~0;~E_4~0 := 2; 5379#L819-3 assume 1 == ~E_5~0;~E_5~0 := 2; 5380#L824-3 assume 1 == ~E_6~0;~E_6~0 := 2; 5493#L829-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~7;havoc exists_runnable_thread_~__retres1~7; 5494#L520-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7 := 1; 5374#L557-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~7; 5999#L558-1 start_simulation_#t~ret18 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret18;havoc start_simulation_#t~ret18; 6003#L1074 assume !(0 == start_simulation_~tmp~3); 5670#L1074-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret17, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~7;havoc exists_runnable_thread_~__retres1~7; 5792#L520-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7 := 1; 5457#L557-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~7; 6000#L558-2 stop_simulation_#t~ret17 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret17;havoc stop_simulation_#t~ret17; 5616#L1029 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 5617#L1036 stop_simulation_#res := stop_simulation_~__retres2~0; 5665#L1037 start_simulation_#t~ret19 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret19;havoc start_simulation_#t~ret19; 5818#L1087 assume !(0 != start_simulation_~tmp___0~1); 5863#L1055-1 [2018-11-23 01:26:46,000 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 01:26:46,000 INFO L82 PathProgramCache]: Analyzing trace with hash -256581980, now seen corresponding path program 1 times [2018-11-23 01:26:46,001 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 01:26:46,001 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 01:26:46,001 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 01:26:46,001 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 01:26:46,002 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 01:26:46,005 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 01:26:46,024 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 01:26:46,024 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 01:26:46,025 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-23 01:26:46,025 INFO L799 eck$LassoCheckResult]: stem already infeasible [2018-11-23 01:26:46,025 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 01:26:46,025 INFO L82 PathProgramCache]: Analyzing trace with hash 89829778, now seen corresponding path program 2 times [2018-11-23 01:26:46,025 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 01:26:46,025 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 01:26:46,026 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 01:26:46,026 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 01:26:46,026 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 01:26:46,031 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 01:26:46,061 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 01:26:46,061 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 01:26:46,061 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-23 01:26:46,061 INFO L811 eck$LassoCheckResult]: loop already infeasible [2018-11-23 01:26:46,062 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-23 01:26:46,062 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-23 01:26:46,062 INFO L87 Difference]: Start difference. First operand 665 states and 1004 transitions. cyclomatic complexity: 340 Second operand 3 states. [2018-11-23 01:26:46,074 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 01:26:46,074 INFO L93 Difference]: Finished difference Result 665 states and 1003 transitions. [2018-11-23 01:26:46,075 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-23 01:26:46,075 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 665 states and 1003 transitions. [2018-11-23 01:26:46,077 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 578 [2018-11-23 01:26:46,078 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 665 states to 665 states and 1003 transitions. [2018-11-23 01:26:46,079 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 665 [2018-11-23 01:26:46,079 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 665 [2018-11-23 01:26:46,079 INFO L73 IsDeterministic]: Start isDeterministic. Operand 665 states and 1003 transitions. [2018-11-23 01:26:46,080 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-23 01:26:46,080 INFO L705 BuchiCegarLoop]: Abstraction has 665 states and 1003 transitions. [2018-11-23 01:26:46,081 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 665 states and 1003 transitions. [2018-11-23 01:26:46,085 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 665 to 665. [2018-11-23 01:26:46,085 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 665 states. [2018-11-23 01:26:46,086 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 665 states to 665 states and 1003 transitions. [2018-11-23 01:26:46,086 INFO L728 BuchiCegarLoop]: Abstraction has 665 states and 1003 transitions. [2018-11-23 01:26:46,086 INFO L608 BuchiCegarLoop]: Abstraction has 665 states and 1003 transitions. [2018-11-23 01:26:46,086 INFO L442 BuchiCegarLoop]: ======== Iteration 6============ [2018-11-23 01:26:46,086 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 665 states and 1003 transitions. [2018-11-23 01:26:46,088 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 578 [2018-11-23 01:26:46,088 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-23 01:26:46,088 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-23 01:26:46,089 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 01:26:46,089 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 01:26:46,090 INFO L794 eck$LassoCheckResult]: Stem: 7277#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0; 7171#L-1 havoc main_#res;havoc main_~__retres1~8;havoc main_~__retres1~8;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 6955#L1018 havoc start_simulation_#t~ret18, start_simulation_#t~ret19, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 6956#L470 assume 1 == ~m_i~0;~m_st~0 := 0; 6800#L477-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 6801#L482-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 7131#L487-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 7132#L492-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 6977#L497-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 6978#L502-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 7072#L507-1 assume !(0 == ~M_E~0); 6815#L686-1 assume !(0 == ~T1_E~0); 6816#L691-1 assume 0 == ~T2_E~0;~T2_E~0 := 1; 7141#L696-1 assume !(0 == ~T3_E~0); 7142#L701-1 assume !(0 == ~T4_E~0); 6986#L706-1 assume !(0 == ~T5_E~0); 6987#L711-1 assume !(0 == ~T6_E~0); 7259#L716-1 assume !(0 == ~E_M~0); 6947#L721-1 assume !(0 == ~E_1~0); 6948#L726-1 assume !(0 == ~E_2~0); 6718#L731-1 assume 0 == ~E_3~0;~E_3~0 := 1; 6719#L736-1 assume !(0 == ~E_4~0); 6805#L741-1 assume !(0 == ~E_5~0); 6806#L746-1 assume !(0 == ~E_6~0); 7137#L751-1 havoc activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 6910#L336 assume !(1 == ~m_pc~0); 6844#L336-2 is_master_triggered_~__retres1~0 := 0; 6845#L347 is_master_triggered_#res := is_master_triggered_~__retres1~0; 6909#L348 activate_threads_#t~ret10 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 6824#L851 assume !(0 != activate_threads_~tmp~1); 6825#L851-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 6826#L355 assume 1 == ~t1_pc~0; 6753#L356 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 6754#L366 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 6803#L367 activate_threads_#t~ret11 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 6804#L859 assume !(0 != activate_threads_~tmp___0~0); 7253#L859-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 7254#L374 assume 1 == ~t2_pc~0; 7047#L375 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 7048#L385 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 7045#L386 activate_threads_#t~ret12 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 7046#L867 assume !(0 != activate_threads_~tmp___1~0); 7354#L867-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 7355#L393 assume !(1 == ~t3_pc~0); 7348#L393-2 is_transmit3_triggered_~__retres1~3 := 0; 7347#L404 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 7345#L405 activate_threads_#t~ret13 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 6952#L875 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 6937#L875-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 6938#L412 assume 1 == ~t4_pc~0; 6892#L413 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 6893#L423 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 6888#L424 activate_threads_#t~ret14 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 6889#L883 assume !(0 != activate_threads_~tmp___3~0); 7151#L883-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 6980#L431 assume !(1 == ~t5_pc~0); 6966#L431-2 is_transmit5_triggered_~__retres1~5 := 0; 6967#L442 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 6979#L443 activate_threads_#t~ret15 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 7133#L891 assume !(0 != activate_threads_~tmp___4~0); 7307#L891-2 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 7192#L450 assume 1 == ~t6_pc~0; 7193#L451 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6 := 1; 7190#L461 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 7191#L462 activate_threads_#t~ret16 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 7292#L899 assume !(0 != activate_threads_~tmp___5~0); 7310#L899-2 assume !(1 == ~M_E~0); 6714#L764-1 assume !(1 == ~T1_E~0); 6715#L769-1 assume !(1 == ~T2_E~0); 6828#L774-1 assume !(1 == ~T3_E~0); 6829#L779-1 assume !(1 == ~T4_E~0); 7152#L784-1 assume !(1 == ~T5_E~0); 7153#L789-1 assume 1 == ~T6_E~0;~T6_E~0 := 2; 6982#L794-1 assume !(1 == ~E_M~0); 6983#L799-1 assume !(1 == ~E_1~0); 7255#L804-1 assume !(1 == ~E_2~0); 6941#L809-1 assume !(1 == ~E_3~0); 6942#L814-1 assume !(1 == ~E_4~0); 6712#L819-1 assume !(1 == ~E_5~0); 6713#L824-1 assume !(1 == ~E_6~0); 7200#L1055-1 [2018-11-23 01:26:46,090 INFO L796 eck$LassoCheckResult]: Loop: 7200#L1055-1 assume !false; 7170#L1056 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret2, eval_#t~nondet3, eval_~tmp_ndt_1~0, eval_#t~nondet4, eval_~tmp_ndt_2~0, eval_#t~nondet5, eval_~tmp_ndt_3~0, eval_#t~nondet6, eval_~tmp_ndt_4~0, eval_#t~nondet7, eval_~tmp_ndt_5~0, eval_#t~nondet8, eval_~tmp_ndt_6~0, eval_#t~nondet9, eval_~tmp_ndt_7~0, eval_~tmp~0;havoc eval_~tmp~0; 6762#L661 assume !false; 7260#L568 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~7;havoc exists_runnable_thread_~__retres1~7; 7125#L520 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7 := 1; 6709#L557 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~7; 7335#L558 eval_#t~ret2 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret2;havoc eval_#t~ret2; 7302#L572 assume !(0 != eval_~tmp~0); 6699#L676 start_simulation_~kernel_st~0 := 2; 6700#L470-1 start_simulation_~kernel_st~0 := 3; 6819#L686-2 assume 0 == ~M_E~0;~M_E~0 := 1; 6820#L686-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 6822#L691-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 7149#L696-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 7150#L701-3 assume !(0 == ~T4_E~0); 6988#L706-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 6989#L711-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 7064#L716-3 assume 0 == ~E_M~0;~E_M~0 := 1; 6925#L721-3 assume 0 == ~E_1~0;~E_1~0 := 1; 6926#L726-3 assume 0 == ~E_2~0;~E_2~0 := 1; 6703#L731-3 assume 0 == ~E_3~0;~E_3~0 := 1; 6704#L736-3 assume 0 == ~E_4~0;~E_4~0 := 1; 6817#L741-3 assume !(0 == ~E_5~0); 6818#L746-3 assume 0 == ~E_6~0;~E_6~0 := 1; 7143#L751-3 havoc activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 7144#L336-24 assume 1 == ~m_pc~0; 7313#L337-8 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 7314#L347-8 is_master_triggered_#res := is_master_triggered_~__retres1~0; 7312#L348-8 activate_threads_#t~ret10 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 6747#L851-24 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 6720#L851-26 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 6721#L355-24 assume 1 == ~t1_pc~0; 6742#L356-8 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 6743#L366-8 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 6739#L367-8 activate_threads_#t~ret11 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 6740#L859-24 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 7001#L859-26 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 7002#L374-24 assume 1 == ~t2_pc~0; 7040#L375-8 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 7042#L385-8 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 7037#L386-8 activate_threads_#t~ret12 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 7038#L867-24 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 7201#L867-26 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 7202#L393-24 assume 1 == ~t3_pc~0; 7216#L394-8 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 7217#L404-8 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 7214#L405-8 activate_threads_#t~ret13 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 7215#L875-24 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 7339#L875-26 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 6919#L412-24 assume !(1 == ~t4_pc~0); 6880#L412-26 is_transmit4_triggered_~__retres1~4 := 0; 6879#L423-8 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 6874#L424-8 activate_threads_#t~ret14 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 6875#L883-24 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 7073#L883-26 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 7074#L431-24 assume 1 == ~t5_pc~0; 7091#L432-8 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 7092#L442-8 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 7089#L443-8 activate_threads_#t~ret15 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 7090#L891-24 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 7269#L891-26 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 7272#L450-24 assume 1 == ~t6_pc~0; 7286#L451-8 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6 := 1; 7187#L461-8 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 7188#L462-8 activate_threads_#t~ret16 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 7285#L899-24 assume 0 != activate_threads_~tmp___5~0;~t6_st~0 := 0; 7356#L899-26 assume !(1 == ~M_E~0); 6701#L764-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 6702#L769-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 6809#L774-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 6810#L779-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 7139#L784-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 7140#L789-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 6984#L794-3 assume 1 == ~E_M~0;~E_M~0 := 2; 6985#L799-3 assume !(1 == ~E_1~0); 7257#L804-3 assume 1 == ~E_2~0;~E_2~0 := 2; 6945#L809-3 assume 1 == ~E_3~0;~E_3~0 := 2; 6946#L814-3 assume 1 == ~E_4~0;~E_4~0 := 2; 6716#L819-3 assume 1 == ~E_5~0;~E_5~0 := 2; 6717#L824-3 assume 1 == ~E_6~0;~E_6~0 := 2; 6830#L829-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~7;havoc exists_runnable_thread_~__retres1~7; 6831#L520-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7 := 1; 6711#L557-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~7; 7336#L558-1 start_simulation_#t~ret18 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret18;havoc start_simulation_#t~ret18; 7340#L1074 assume !(0 == start_simulation_~tmp~3); 7008#L1074-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret17, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~7;havoc exists_runnable_thread_~__retres1~7; 7129#L520-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7 := 1; 6794#L557-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~7; 7337#L558-2 stop_simulation_#t~ret17 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret17;havoc stop_simulation_#t~ret17; 6953#L1029 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 6954#L1036 stop_simulation_#res := stop_simulation_~__retres2~0; 7003#L1037 start_simulation_#t~ret19 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret19;havoc start_simulation_#t~ret19; 7157#L1087 assume !(0 != start_simulation_~tmp___0~1); 7200#L1055-1 [2018-11-23 01:26:46,090 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 01:26:46,090 INFO L82 PathProgramCache]: Analyzing trace with hash -333482778, now seen corresponding path program 1 times [2018-11-23 01:26:46,090 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 01:26:46,090 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 01:26:46,091 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 01:26:46,091 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-23 01:26:46,091 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 01:26:46,095 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 01:26:46,107 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 01:26:46,107 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 01:26:46,107 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-23 01:26:46,108 INFO L799 eck$LassoCheckResult]: stem already infeasible [2018-11-23 01:26:46,108 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 01:26:46,108 INFO L82 PathProgramCache]: Analyzing trace with hash -1185272911, now seen corresponding path program 1 times [2018-11-23 01:26:46,108 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 01:26:46,108 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 01:26:46,109 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 01:26:46,109 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 01:26:46,109 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 01:26:46,114 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 01:26:46,147 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 01:26:46,148 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 01:26:46,148 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-23 01:26:46,148 INFO L811 eck$LassoCheckResult]: loop already infeasible [2018-11-23 01:26:46,148 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-23 01:26:46,148 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-23 01:26:46,148 INFO L87 Difference]: Start difference. First operand 665 states and 1003 transitions. cyclomatic complexity: 339 Second operand 3 states. [2018-11-23 01:26:46,161 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 01:26:46,161 INFO L93 Difference]: Finished difference Result 665 states and 1002 transitions. [2018-11-23 01:26:46,162 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-23 01:26:46,162 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 665 states and 1002 transitions. [2018-11-23 01:26:46,165 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 578 [2018-11-23 01:26:46,168 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 665 states to 665 states and 1002 transitions. [2018-11-23 01:26:46,168 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 665 [2018-11-23 01:26:46,168 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 665 [2018-11-23 01:26:46,169 INFO L73 IsDeterministic]: Start isDeterministic. Operand 665 states and 1002 transitions. [2018-11-23 01:26:46,170 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-23 01:26:46,170 INFO L705 BuchiCegarLoop]: Abstraction has 665 states and 1002 transitions. [2018-11-23 01:26:46,171 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 665 states and 1002 transitions. [2018-11-23 01:26:46,177 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 665 to 665. [2018-11-23 01:26:46,177 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 665 states. [2018-11-23 01:26:46,179 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 665 states to 665 states and 1002 transitions. [2018-11-23 01:26:46,179 INFO L728 BuchiCegarLoop]: Abstraction has 665 states and 1002 transitions. [2018-11-23 01:26:46,179 INFO L608 BuchiCegarLoop]: Abstraction has 665 states and 1002 transitions. [2018-11-23 01:26:46,179 INFO L442 BuchiCegarLoop]: ======== Iteration 7============ [2018-11-23 01:26:46,179 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 665 states and 1002 transitions. [2018-11-23 01:26:46,182 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 578 [2018-11-23 01:26:46,182 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-23 01:26:46,182 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-23 01:26:46,183 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 01:26:46,183 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 01:26:46,183 INFO L794 eck$LassoCheckResult]: Stem: 8614#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0; 8508#L-1 havoc main_#res;havoc main_~__retres1~8;havoc main_~__retres1~8;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 8292#L1018 havoc start_simulation_#t~ret18, start_simulation_#t~ret19, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 8293#L470 assume 1 == ~m_i~0;~m_st~0 := 0; 8137#L477-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 8138#L482-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 8466#L487-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 8467#L492-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 8314#L497-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 8315#L502-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 8408#L507-1 assume !(0 == ~M_E~0); 8150#L686-1 assume !(0 == ~T1_E~0); 8151#L691-1 assume 0 == ~T2_E~0;~T2_E~0 := 1; 8478#L696-1 assume !(0 == ~T3_E~0); 8479#L701-1 assume !(0 == ~T4_E~0); 8323#L706-1 assume !(0 == ~T5_E~0); 8324#L711-1 assume !(0 == ~T6_E~0); 8596#L716-1 assume !(0 == ~E_M~0); 8284#L721-1 assume !(0 == ~E_1~0); 8285#L726-1 assume !(0 == ~E_2~0); 8055#L731-1 assume 0 == ~E_3~0;~E_3~0 := 1; 8056#L736-1 assume !(0 == ~E_4~0); 8142#L741-1 assume !(0 == ~E_5~0); 8143#L746-1 assume !(0 == ~E_6~0); 8473#L751-1 havoc activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 8247#L336 assume !(1 == ~m_pc~0); 8181#L336-2 is_master_triggered_~__retres1~0 := 0; 8182#L347 is_master_triggered_#res := is_master_triggered_~__retres1~0; 8243#L348 activate_threads_#t~ret10 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 8161#L851 assume !(0 != activate_threads_~tmp~1); 8162#L851-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 8163#L355 assume 1 == ~t1_pc~0; 8088#L356 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 8089#L366 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 8140#L367 activate_threads_#t~ret11 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 8141#L859 assume !(0 != activate_threads_~tmp___0~0); 8590#L859-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 8591#L374 assume 1 == ~t2_pc~0; 8384#L375 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 8385#L385 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 8382#L386 activate_threads_#t~ret12 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 8383#L867 assume !(0 != activate_threads_~tmp___1~0); 8691#L867-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 8692#L393 assume !(1 == ~t3_pc~0); 8685#L393-2 is_transmit3_triggered_~__retres1~3 := 0; 8684#L404 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 8681#L405 activate_threads_#t~ret13 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 8289#L875 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 8274#L875-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 8275#L412 assume 1 == ~t4_pc~0; 8227#L413 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 8228#L423 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 8225#L424 activate_threads_#t~ret14 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 8226#L883 assume !(0 != activate_threads_~tmp___3~0); 8488#L883-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 8317#L431 assume !(1 == ~t5_pc~0); 8303#L431-2 is_transmit5_triggered_~__retres1~5 := 0; 8304#L442 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 8316#L443 activate_threads_#t~ret15 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 8470#L891 assume !(0 != activate_threads_~tmp___4~0); 8644#L891-2 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 8529#L450 assume 1 == ~t6_pc~0; 8530#L451 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6 := 1; 8527#L461 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 8528#L462 activate_threads_#t~ret16 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 8628#L899 assume !(0 != activate_threads_~tmp___5~0); 8646#L899-2 assume !(1 == ~M_E~0); 8051#L764-1 assume !(1 == ~T1_E~0); 8052#L769-1 assume !(1 == ~T2_E~0); 8165#L774-1 assume !(1 == ~T3_E~0); 8166#L779-1 assume !(1 == ~T4_E~0); 8489#L784-1 assume !(1 == ~T5_E~0); 8490#L789-1 assume 1 == ~T6_E~0;~T6_E~0 := 2; 8319#L794-1 assume !(1 == ~E_M~0); 8320#L799-1 assume !(1 == ~E_1~0); 8592#L804-1 assume !(1 == ~E_2~0); 8276#L809-1 assume !(1 == ~E_3~0); 8277#L814-1 assume !(1 == ~E_4~0); 8049#L819-1 assume !(1 == ~E_5~0); 8050#L824-1 assume !(1 == ~E_6~0); 8537#L1055-1 [2018-11-23 01:26:46,183 INFO L796 eck$LassoCheckResult]: Loop: 8537#L1055-1 assume !false; 8507#L1056 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret2, eval_#t~nondet3, eval_~tmp_ndt_1~0, eval_#t~nondet4, eval_~tmp_ndt_2~0, eval_#t~nondet5, eval_~tmp_ndt_3~0, eval_#t~nondet6, eval_~tmp_ndt_4~0, eval_#t~nondet7, eval_~tmp_ndt_5~0, eval_#t~nondet8, eval_~tmp_ndt_6~0, eval_#t~nondet9, eval_~tmp_ndt_7~0, eval_~tmp~0;havoc eval_~tmp~0; 8099#L661 assume !false; 8597#L568 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~7;havoc exists_runnable_thread_~__retres1~7; 8458#L520 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7 := 1; 8046#L557 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~7; 8672#L558 eval_#t~ret2 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret2;havoc eval_#t~ret2; 8639#L572 assume !(0 != eval_~tmp~0); 8036#L676 start_simulation_~kernel_st~0 := 2; 8037#L470-1 start_simulation_~kernel_st~0 := 3; 8156#L686-2 assume 0 == ~M_E~0;~M_E~0 := 1; 8157#L686-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 8159#L691-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 8486#L696-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 8487#L701-3 assume !(0 == ~T4_E~0); 8325#L706-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 8326#L711-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 8401#L716-3 assume 0 == ~E_M~0;~E_M~0 := 1; 8262#L721-3 assume 0 == ~E_1~0;~E_1~0 := 1; 8263#L726-3 assume 0 == ~E_2~0;~E_2~0 := 1; 8040#L731-3 assume 0 == ~E_3~0;~E_3~0 := 1; 8041#L736-3 assume 0 == ~E_4~0;~E_4~0 := 1; 8154#L741-3 assume !(0 == ~E_5~0); 8155#L746-3 assume 0 == ~E_6~0;~E_6~0 := 1; 8480#L751-3 havoc activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 8481#L336-24 assume 1 == ~m_pc~0; 8650#L337-8 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 8651#L347-8 is_master_triggered_#res := is_master_triggered_~__retres1~0; 8649#L348-8 activate_threads_#t~ret10 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 8084#L851-24 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 8057#L851-26 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 8058#L355-24 assume !(1 == ~t1_pc~0); 8081#L355-26 is_transmit1_triggered_~__retres1~1 := 0; 8080#L366-8 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 8076#L367-8 activate_threads_#t~ret11 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 8077#L859-24 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 8338#L859-26 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 8339#L374-24 assume 1 == ~t2_pc~0; 8377#L375-8 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 8379#L385-8 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 8374#L386-8 activate_threads_#t~ret12 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 8375#L867-24 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 8538#L867-26 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 8539#L393-24 assume 1 == ~t3_pc~0; 8553#L394-8 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 8554#L404-8 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 8551#L405-8 activate_threads_#t~ret13 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 8552#L875-24 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 8676#L875-26 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 8256#L412-24 assume 1 == ~t4_pc~0; 8215#L413-8 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 8216#L423-8 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 8211#L424-8 activate_threads_#t~ret14 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 8212#L883-24 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 8410#L883-26 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 8411#L431-24 assume 1 == ~t5_pc~0; 8428#L432-8 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 8429#L442-8 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 8426#L443-8 activate_threads_#t~ret15 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 8427#L891-24 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 8606#L891-26 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 8609#L450-24 assume !(1 == ~t6_pc~0); 8624#L450-26 is_transmit6_triggered_~__retres1~6 := 0; 8524#L461-8 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 8525#L462-8 activate_threads_#t~ret16 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 8622#L899-24 assume 0 != activate_threads_~tmp___5~0;~t6_st~0 := 0; 8693#L899-26 assume !(1 == ~M_E~0); 8038#L764-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 8039#L769-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 8146#L774-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 8147#L779-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 8476#L784-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 8477#L789-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 8321#L794-3 assume 1 == ~E_M~0;~E_M~0 := 2; 8322#L799-3 assume !(1 == ~E_1~0); 8594#L804-3 assume 1 == ~E_2~0;~E_2~0 := 2; 8282#L809-3 assume 1 == ~E_3~0;~E_3~0 := 2; 8283#L814-3 assume 1 == ~E_4~0;~E_4~0 := 2; 8053#L819-3 assume 1 == ~E_5~0;~E_5~0 := 2; 8054#L824-3 assume 1 == ~E_6~0;~E_6~0 := 2; 8167#L829-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~7;havoc exists_runnable_thread_~__retres1~7; 8168#L520-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7 := 1; 8048#L557-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~7; 8673#L558-1 start_simulation_#t~ret18 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret18;havoc start_simulation_#t~ret18; 8677#L1074 assume !(0 == start_simulation_~tmp~3); 8345#L1074-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret17, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~7;havoc exists_runnable_thread_~__retres1~7; 8468#L520-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7 := 1; 8131#L557-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~7; 8674#L558-2 stop_simulation_#t~ret17 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret17;havoc stop_simulation_#t~ret17; 8290#L1029 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 8291#L1036 stop_simulation_#res := stop_simulation_~__retres2~0; 8340#L1037 start_simulation_#t~ret19 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret19;havoc start_simulation_#t~ret19; 8494#L1087 assume !(0 != start_simulation_~tmp___0~1); 8537#L1055-1 [2018-11-23 01:26:46,184 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 01:26:46,184 INFO L82 PathProgramCache]: Analyzing trace with hash 633867876, now seen corresponding path program 1 times [2018-11-23 01:26:46,184 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 01:26:46,184 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 01:26:46,185 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 01:26:46,185 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 01:26:46,185 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 01:26:46,189 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 01:26:46,213 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 01:26:46,214 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 01:26:46,214 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2018-11-23 01:26:46,214 INFO L799 eck$LassoCheckResult]: stem already infeasible [2018-11-23 01:26:46,214 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 01:26:46,214 INFO L82 PathProgramCache]: Analyzing trace with hash -1466436976, now seen corresponding path program 1 times [2018-11-23 01:26:46,214 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 01:26:46,214 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 01:26:46,215 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 01:26:46,215 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 01:26:46,215 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 01:26:46,222 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 01:26:46,243 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 01:26:46,243 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 01:26:46,244 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-23 01:26:46,244 INFO L811 eck$LassoCheckResult]: loop already infeasible [2018-11-23 01:26:46,244 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-23 01:26:46,244 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-23 01:26:46,244 INFO L87 Difference]: Start difference. First operand 665 states and 1002 transitions. cyclomatic complexity: 338 Second operand 3 states. [2018-11-23 01:26:46,270 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 01:26:46,270 INFO L93 Difference]: Finished difference Result 665 states and 997 transitions. [2018-11-23 01:26:46,271 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-23 01:26:46,271 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 665 states and 997 transitions. [2018-11-23 01:26:46,274 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 578 [2018-11-23 01:26:46,276 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 665 states to 665 states and 997 transitions. [2018-11-23 01:26:46,277 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 665 [2018-11-23 01:26:46,277 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 665 [2018-11-23 01:26:46,277 INFO L73 IsDeterministic]: Start isDeterministic. Operand 665 states and 997 transitions. [2018-11-23 01:26:46,278 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-23 01:26:46,278 INFO L705 BuchiCegarLoop]: Abstraction has 665 states and 997 transitions. [2018-11-23 01:26:46,279 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 665 states and 997 transitions. [2018-11-23 01:26:46,286 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 665 to 665. [2018-11-23 01:26:46,286 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 665 states. [2018-11-23 01:26:46,288 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 665 states to 665 states and 997 transitions. [2018-11-23 01:26:46,288 INFO L728 BuchiCegarLoop]: Abstraction has 665 states and 997 transitions. [2018-11-23 01:26:46,288 INFO L608 BuchiCegarLoop]: Abstraction has 665 states and 997 transitions. [2018-11-23 01:26:46,288 INFO L442 BuchiCegarLoop]: ======== Iteration 8============ [2018-11-23 01:26:46,288 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 665 states and 997 transitions. [2018-11-23 01:26:46,291 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 578 [2018-11-23 01:26:46,291 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-23 01:26:46,291 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-23 01:26:46,292 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 01:26:46,292 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 01:26:46,292 INFO L794 eck$LassoCheckResult]: Stem: 9951#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0; 9845#L-1 havoc main_#res;havoc main_~__retres1~8;havoc main_~__retres1~8;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 9629#L1018 havoc start_simulation_#t~ret18, start_simulation_#t~ret19, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 9630#L470 assume 1 == ~m_i~0;~m_st~0 := 0; 9474#L477-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 9475#L482-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 9805#L487-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 9806#L492-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 9651#L497-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 9652#L502-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 9746#L507-1 assume !(0 == ~M_E~0); 9487#L686-1 assume !(0 == ~T1_E~0); 9488#L691-1 assume !(0 == ~T2_E~0); 9815#L696-1 assume !(0 == ~T3_E~0); 9816#L701-1 assume !(0 == ~T4_E~0); 9660#L706-1 assume !(0 == ~T5_E~0); 9661#L711-1 assume !(0 == ~T6_E~0); 9933#L716-1 assume !(0 == ~E_M~0); 9621#L721-1 assume !(0 == ~E_1~0); 9622#L726-1 assume !(0 == ~E_2~0); 9392#L731-1 assume 0 == ~E_3~0;~E_3~0 := 1; 9393#L736-1 assume !(0 == ~E_4~0); 9479#L741-1 assume !(0 == ~E_5~0); 9480#L746-1 assume !(0 == ~E_6~0); 9810#L751-1 havoc activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 9584#L336 assume !(1 == ~m_pc~0); 9518#L336-2 is_master_triggered_~__retres1~0 := 0; 9519#L347 is_master_triggered_#res := is_master_triggered_~__retres1~0; 9580#L348 activate_threads_#t~ret10 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 9498#L851 assume !(0 != activate_threads_~tmp~1); 9499#L851-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 9500#L355 assume 1 == ~t1_pc~0; 9425#L356 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 9426#L366 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 9477#L367 activate_threads_#t~ret11 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 9478#L859 assume !(0 != activate_threads_~tmp___0~0); 9927#L859-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 9928#L374 assume 1 == ~t2_pc~0; 9721#L375 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 9722#L385 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 9719#L386 activate_threads_#t~ret12 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 9720#L867 assume !(0 != activate_threads_~tmp___1~0); 10028#L867-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 10029#L393 assume !(1 == ~t3_pc~0); 10022#L393-2 is_transmit3_triggered_~__retres1~3 := 0; 10021#L404 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 10018#L405 activate_threads_#t~ret13 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 9626#L875 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 9611#L875-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 9612#L412 assume 1 == ~t4_pc~0; 9564#L413 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 9565#L423 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 9562#L424 activate_threads_#t~ret14 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 9563#L883 assume !(0 != activate_threads_~tmp___3~0); 9825#L883-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 9654#L431 assume !(1 == ~t5_pc~0); 9640#L431-2 is_transmit5_triggered_~__retres1~5 := 0; 9641#L442 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 9653#L443 activate_threads_#t~ret15 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 9807#L891 assume !(0 != activate_threads_~tmp___4~0); 9981#L891-2 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 9866#L450 assume 1 == ~t6_pc~0; 9867#L451 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6 := 1; 9864#L461 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 9865#L462 activate_threads_#t~ret16 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 9966#L899 assume !(0 != activate_threads_~tmp___5~0); 9984#L899-2 assume !(1 == ~M_E~0); 9388#L764-1 assume !(1 == ~T1_E~0); 9389#L769-1 assume !(1 == ~T2_E~0); 9502#L774-1 assume !(1 == ~T3_E~0); 9503#L779-1 assume !(1 == ~T4_E~0); 9826#L784-1 assume !(1 == ~T5_E~0); 9827#L789-1 assume 1 == ~T6_E~0;~T6_E~0 := 2; 9656#L794-1 assume !(1 == ~E_M~0); 9657#L799-1 assume !(1 == ~E_1~0); 9929#L804-1 assume !(1 == ~E_2~0); 9613#L809-1 assume !(1 == ~E_3~0); 9614#L814-1 assume !(1 == ~E_4~0); 9386#L819-1 assume !(1 == ~E_5~0); 9387#L824-1 assume !(1 == ~E_6~0); 9874#L1055-1 [2018-11-23 01:26:46,292 INFO L796 eck$LassoCheckResult]: Loop: 9874#L1055-1 assume !false; 9844#L1056 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret2, eval_#t~nondet3, eval_~tmp_ndt_1~0, eval_#t~nondet4, eval_~tmp_ndt_2~0, eval_#t~nondet5, eval_~tmp_ndt_3~0, eval_#t~nondet6, eval_~tmp_ndt_4~0, eval_#t~nondet7, eval_~tmp_ndt_5~0, eval_#t~nondet8, eval_~tmp_ndt_6~0, eval_#t~nondet9, eval_~tmp_ndt_7~0, eval_~tmp~0;havoc eval_~tmp~0; 9436#L661 assume !false; 9934#L568 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~7;havoc exists_runnable_thread_~__retres1~7; 9795#L520 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7 := 1; 9383#L557 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~7; 10009#L558 eval_#t~ret2 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret2;havoc eval_#t~ret2; 9976#L572 assume !(0 != eval_~tmp~0); 9373#L676 start_simulation_~kernel_st~0 := 2; 9374#L470-1 start_simulation_~kernel_st~0 := 3; 9493#L686-2 assume 0 == ~M_E~0;~M_E~0 := 1; 9494#L686-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 9496#L691-3 assume !(0 == ~T2_E~0); 9823#L696-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 9824#L701-3 assume !(0 == ~T4_E~0); 9662#L706-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 9663#L711-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 9738#L716-3 assume 0 == ~E_M~0;~E_M~0 := 1; 9599#L721-3 assume 0 == ~E_1~0;~E_1~0 := 1; 9600#L726-3 assume 0 == ~E_2~0;~E_2~0 := 1; 9377#L731-3 assume 0 == ~E_3~0;~E_3~0 := 1; 9378#L736-3 assume 0 == ~E_4~0;~E_4~0 := 1; 9491#L741-3 assume !(0 == ~E_5~0); 9492#L746-3 assume 0 == ~E_6~0;~E_6~0 := 1; 9817#L751-3 havoc activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 9818#L336-24 assume 1 == ~m_pc~0; 9987#L337-8 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 9988#L347-8 is_master_triggered_#res := is_master_triggered_~__retres1~0; 9986#L348-8 activate_threads_#t~ret10 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 9424#L851-24 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 9394#L851-26 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 9395#L355-24 assume 1 == ~t1_pc~0; 9416#L356-8 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 9417#L366-8 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 9413#L367-8 activate_threads_#t~ret11 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 9414#L859-24 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 9675#L859-26 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 9677#L374-24 assume 1 == ~t2_pc~0; 9714#L375-8 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 9716#L385-8 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 9711#L386-8 activate_threads_#t~ret12 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 9712#L867-24 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 9875#L867-26 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 9876#L393-24 assume 1 == ~t3_pc~0; 9890#L394-8 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 9891#L404-8 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 9888#L405-8 activate_threads_#t~ret13 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 9889#L875-24 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 10013#L875-26 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 9593#L412-24 assume 1 == ~t4_pc~0; 9552#L413-8 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 9553#L423-8 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 9548#L424-8 activate_threads_#t~ret14 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 9549#L883-24 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 9747#L883-26 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 9748#L431-24 assume 1 == ~t5_pc~0; 9765#L432-8 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 9766#L442-8 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 9763#L443-8 activate_threads_#t~ret15 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 9764#L891-24 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 9943#L891-26 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 9946#L450-24 assume 1 == ~t6_pc~0; 9960#L451-8 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6 := 1; 9861#L461-8 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 9862#L462-8 activate_threads_#t~ret16 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 9959#L899-24 assume 0 != activate_threads_~tmp___5~0;~t6_st~0 := 0; 10030#L899-26 assume !(1 == ~M_E~0); 9375#L764-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 9376#L769-3 assume !(1 == ~T2_E~0); 9483#L774-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 9484#L779-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 9812#L784-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 9813#L789-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 9658#L794-3 assume 1 == ~E_M~0;~E_M~0 := 2; 9659#L799-3 assume !(1 == ~E_1~0); 9931#L804-3 assume 1 == ~E_2~0;~E_2~0 := 2; 9618#L809-3 assume 1 == ~E_3~0;~E_3~0 := 2; 9619#L814-3 assume 1 == ~E_4~0;~E_4~0 := 2; 9390#L819-3 assume 1 == ~E_5~0;~E_5~0 := 2; 9391#L824-3 assume 1 == ~E_6~0;~E_6~0 := 2; 9504#L829-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~7;havoc exists_runnable_thread_~__retres1~7; 9505#L520-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7 := 1; 9385#L557-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~7; 10010#L558-1 start_simulation_#t~ret18 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret18;havoc start_simulation_#t~ret18; 10014#L1074 assume !(0 == start_simulation_~tmp~3); 9681#L1074-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret17, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~7;havoc exists_runnable_thread_~__retres1~7; 9803#L520-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7 := 1; 9468#L557-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~7; 10011#L558-2 stop_simulation_#t~ret17 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret17;havoc stop_simulation_#t~ret17; 9627#L1029 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 9628#L1036 stop_simulation_#res := stop_simulation_~__retres2~0; 9676#L1037 start_simulation_#t~ret19 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret19;havoc start_simulation_#t~ret19; 9829#L1087 assume !(0 != start_simulation_~tmp___0~1); 9874#L1055-1 [2018-11-23 01:26:46,293 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 01:26:46,293 INFO L82 PathProgramCache]: Analyzing trace with hash 1587808034, now seen corresponding path program 1 times [2018-11-23 01:26:46,293 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 01:26:46,293 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 01:26:46,294 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 01:26:46,294 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 01:26:46,294 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 01:26:46,297 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 01:26:46,322 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 01:26:46,322 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 01:26:46,322 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2018-11-23 01:26:46,323 INFO L799 eck$LassoCheckResult]: stem already infeasible [2018-11-23 01:26:46,323 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 01:26:46,323 INFO L82 PathProgramCache]: Analyzing trace with hash -827459690, now seen corresponding path program 1 times [2018-11-23 01:26:46,323 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 01:26:46,323 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 01:26:46,324 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 01:26:46,324 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 01:26:46,324 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 01:26:46,333 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 01:26:46,371 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 01:26:46,371 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 01:26:46,371 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-23 01:26:46,371 INFO L811 eck$LassoCheckResult]: loop already infeasible [2018-11-23 01:26:46,371 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-23 01:26:46,372 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-23 01:26:46,372 INFO L87 Difference]: Start difference. First operand 665 states and 997 transitions. cyclomatic complexity: 333 Second operand 3 states. [2018-11-23 01:26:46,435 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 01:26:46,436 INFO L93 Difference]: Finished difference Result 665 states and 983 transitions. [2018-11-23 01:26:46,437 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-23 01:26:46,437 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 665 states and 983 transitions. [2018-11-23 01:26:46,440 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 578 [2018-11-23 01:26:46,444 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 665 states to 665 states and 983 transitions. [2018-11-23 01:26:46,444 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 665 [2018-11-23 01:26:46,444 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 665 [2018-11-23 01:26:46,444 INFO L73 IsDeterministic]: Start isDeterministic. Operand 665 states and 983 transitions. [2018-11-23 01:26:46,445 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-23 01:26:46,445 INFO L705 BuchiCegarLoop]: Abstraction has 665 states and 983 transitions. [2018-11-23 01:26:46,446 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 665 states and 983 transitions. [2018-11-23 01:26:46,452 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 665 to 665. [2018-11-23 01:26:46,452 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 665 states. [2018-11-23 01:26:46,454 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 665 states to 665 states and 983 transitions. [2018-11-23 01:26:46,454 INFO L728 BuchiCegarLoop]: Abstraction has 665 states and 983 transitions. [2018-11-23 01:26:46,454 INFO L608 BuchiCegarLoop]: Abstraction has 665 states and 983 transitions. [2018-11-23 01:26:46,454 INFO L442 BuchiCegarLoop]: ======== Iteration 9============ [2018-11-23 01:26:46,454 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 665 states and 983 transitions. [2018-11-23 01:26:46,456 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 578 [2018-11-23 01:26:46,456 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-23 01:26:46,456 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-23 01:26:46,457 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 01:26:46,457 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 01:26:46,458 INFO L794 eck$LassoCheckResult]: Stem: 11280#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0; 11182#L-1 havoc main_#res;havoc main_~__retres1~8;havoc main_~__retres1~8;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 10966#L1018 havoc start_simulation_#t~ret18, start_simulation_#t~ret19, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 10967#L470 assume 1 == ~m_i~0;~m_st~0 := 0; 10811#L477-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 10812#L482-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 11142#L487-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 11143#L492-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 10988#L497-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 10989#L502-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 11083#L507-1 assume !(0 == ~M_E~0); 10824#L686-1 assume !(0 == ~T1_E~0); 10825#L691-1 assume !(0 == ~T2_E~0); 11152#L696-1 assume !(0 == ~T3_E~0); 11153#L701-1 assume !(0 == ~T4_E~0); 10997#L706-1 assume !(0 == ~T5_E~0); 10998#L711-1 assume !(0 == ~T6_E~0); 11262#L716-1 assume !(0 == ~E_M~0); 10958#L721-1 assume !(0 == ~E_1~0); 10959#L726-1 assume !(0 == ~E_2~0); 10729#L731-1 assume !(0 == ~E_3~0); 10730#L736-1 assume !(0 == ~E_4~0); 10816#L741-1 assume !(0 == ~E_5~0); 10817#L746-1 assume !(0 == ~E_6~0); 11148#L751-1 havoc activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 10921#L336 assume !(1 == ~m_pc~0); 10855#L336-2 is_master_triggered_~__retres1~0 := 0; 10856#L347 is_master_triggered_#res := is_master_triggered_~__retres1~0; 10920#L348 activate_threads_#t~ret10 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 10835#L851 assume !(0 != activate_threads_~tmp~1); 10836#L851-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 10837#L355 assume 1 == ~t1_pc~0; 10764#L356 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 10765#L366 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 10814#L367 activate_threads_#t~ret11 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 10815#L859 assume !(0 != activate_threads_~tmp___0~0); 11256#L859-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 11257#L374 assume 1 == ~t2_pc~0; 11058#L375 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 11059#L385 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 11056#L386 activate_threads_#t~ret12 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 11057#L867 assume !(0 != activate_threads_~tmp___1~0); 11359#L867-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 11361#L393 assume !(1 == ~t3_pc~0); 11351#L393-2 is_transmit3_triggered_~__retres1~3 := 0; 11370#L404 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 11349#L405 activate_threads_#t~ret13 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 10963#L875 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 10948#L875-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 10949#L412 assume 1 == ~t4_pc~0; 10903#L413 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 10904#L423 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 10899#L424 activate_threads_#t~ret14 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 10900#L883 assume !(0 != activate_threads_~tmp___3~0); 11162#L883-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 10991#L431 assume !(1 == ~t5_pc~0); 10977#L431-2 is_transmit5_triggered_~__retres1~5 := 0; 10978#L442 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 10990#L443 activate_threads_#t~ret15 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 11144#L891 assume !(0 != activate_threads_~tmp___4~0); 11310#L891-2 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 11203#L450 assume 1 == ~t6_pc~0; 11204#L451 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6 := 1; 11201#L461 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 11202#L462 activate_threads_#t~ret16 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 11295#L899 assume !(0 != activate_threads_~tmp___5~0); 11313#L899-2 assume !(1 == ~M_E~0); 10725#L764-1 assume !(1 == ~T1_E~0); 10726#L769-1 assume !(1 == ~T2_E~0); 10839#L774-1 assume !(1 == ~T3_E~0); 10840#L779-1 assume !(1 == ~T4_E~0); 11163#L784-1 assume !(1 == ~T5_E~0); 11164#L789-1 assume 1 == ~T6_E~0;~T6_E~0 := 2; 10993#L794-1 assume !(1 == ~E_M~0); 10994#L799-1 assume !(1 == ~E_1~0); 11258#L804-1 assume !(1 == ~E_2~0); 10952#L809-1 assume !(1 == ~E_3~0); 10953#L814-1 assume !(1 == ~E_4~0); 10723#L819-1 assume !(1 == ~E_5~0); 10724#L824-1 assume !(1 == ~E_6~0); 11211#L1055-1 [2018-11-23 01:26:46,458 INFO L796 eck$LassoCheckResult]: Loop: 11211#L1055-1 assume !false; 11181#L1056 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret2, eval_#t~nondet3, eval_~tmp_ndt_1~0, eval_#t~nondet4, eval_~tmp_ndt_2~0, eval_#t~nondet5, eval_~tmp_ndt_3~0, eval_#t~nondet6, eval_~tmp_ndt_4~0, eval_#t~nondet7, eval_~tmp_ndt_5~0, eval_#t~nondet8, eval_~tmp_ndt_6~0, eval_#t~nondet9, eval_~tmp_ndt_7~0, eval_~tmp~0;havoc eval_~tmp~0; 10773#L661 assume !false; 11263#L568 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~7;havoc exists_runnable_thread_~__retres1~7; 11134#L520 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7 := 1; 10720#L557 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~7; 11338#L558 eval_#t~ret2 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret2;havoc eval_#t~ret2; 11305#L572 assume !(0 != eval_~tmp~0); 10710#L676 start_simulation_~kernel_st~0 := 2; 10711#L470-1 start_simulation_~kernel_st~0 := 3; 10830#L686-2 assume 0 == ~M_E~0;~M_E~0 := 1; 10831#L686-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 10834#L691-3 assume !(0 == ~T2_E~0); 11160#L696-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 11161#L701-3 assume !(0 == ~T4_E~0); 10999#L706-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 11000#L711-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 11075#L716-3 assume 0 == ~E_M~0;~E_M~0 := 1; 10936#L721-3 assume 0 == ~E_1~0;~E_1~0 := 1; 10937#L726-3 assume 0 == ~E_2~0;~E_2~0 := 1; 10714#L731-3 assume !(0 == ~E_3~0); 10715#L736-3 assume 0 == ~E_4~0;~E_4~0 := 1; 10828#L741-3 assume !(0 == ~E_5~0); 10829#L746-3 assume 0 == ~E_6~0;~E_6~0 := 1; 11154#L751-3 havoc activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 11155#L336-24 assume 1 == ~m_pc~0; 11316#L337-8 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 11317#L347-8 is_master_triggered_#res := is_master_triggered_~__retres1~0; 11315#L348-8 activate_threads_#t~ret10 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 10758#L851-24 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 10731#L851-26 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 10732#L355-24 assume 1 == ~t1_pc~0; 10753#L356-8 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 10754#L366-8 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 10750#L367-8 activate_threads_#t~ret11 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 10751#L859-24 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 11012#L859-26 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 11013#L374-24 assume 1 == ~t2_pc~0; 11050#L375-8 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 11052#L385-8 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 11048#L386-8 activate_threads_#t~ret12 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 11049#L867-24 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 11212#L867-26 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 11213#L393-24 assume !(1 == ~t3_pc~0); 11226#L393-26 is_transmit3_triggered_~__retres1~3 := 0; 11358#L404-8 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 11223#L405-8 activate_threads_#t~ret13 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 11224#L875-24 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 11342#L875-26 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 10930#L412-24 assume 1 == ~t4_pc~0; 10889#L413-8 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 10890#L423-8 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 10885#L424-8 activate_threads_#t~ret14 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 10886#L883-24 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 11084#L883-26 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 11085#L431-24 assume !(1 == ~t5_pc~0); 11104#L431-26 is_transmit5_triggered_~__retres1~5 := 0; 11103#L442-8 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 11100#L443-8 activate_threads_#t~ret15 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 11101#L891-24 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 11272#L891-26 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 11275#L450-24 assume 1 == ~t6_pc~0; 11289#L451-8 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6 := 1; 11198#L461-8 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 11199#L462-8 activate_threads_#t~ret16 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 11288#L899-24 assume 0 != activate_threads_~tmp___5~0;~t6_st~0 := 0; 11363#L899-26 assume !(1 == ~M_E~0); 10712#L764-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 10713#L769-3 assume !(1 == ~T2_E~0); 10820#L774-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 10821#L779-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 11150#L784-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 11151#L789-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 10995#L794-3 assume 1 == ~E_M~0;~E_M~0 := 2; 10996#L799-3 assume !(1 == ~E_1~0); 11260#L804-3 assume 1 == ~E_2~0;~E_2~0 := 2; 10956#L809-3 assume !(1 == ~E_3~0); 10957#L814-3 assume 1 == ~E_4~0;~E_4~0 := 2; 10727#L819-3 assume 1 == ~E_5~0;~E_5~0 := 2; 10728#L824-3 assume 1 == ~E_6~0;~E_6~0 := 2; 10841#L829-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~7;havoc exists_runnable_thread_~__retres1~7; 10842#L520-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7 := 1; 10722#L557-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~7; 11339#L558-1 start_simulation_#t~ret18 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret18;havoc start_simulation_#t~ret18; 11343#L1074 assume !(0 == start_simulation_~tmp~3); 11018#L1074-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret17, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~7;havoc exists_runnable_thread_~__retres1~7; 11140#L520-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7 := 1; 10805#L557-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~7; 11340#L558-2 stop_simulation_#t~ret17 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret17;havoc stop_simulation_#t~ret17; 10964#L1029 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 10965#L1036 stop_simulation_#res := stop_simulation_~__retres2~0; 11014#L1037 start_simulation_#t~ret19 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret19;havoc start_simulation_#t~ret19; 11166#L1087 assume !(0 != start_simulation_~tmp___0~1); 11211#L1055-1 [2018-11-23 01:26:46,458 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 01:26:46,458 INFO L82 PathProgramCache]: Analyzing trace with hash 1789631968, now seen corresponding path program 1 times [2018-11-23 01:26:46,458 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 01:26:46,458 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 01:26:46,459 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 01:26:46,459 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 01:26:46,459 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 01:26:46,463 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 01:26:46,485 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 01:26:46,486 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 01:26:46,486 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2018-11-23 01:26:46,486 INFO L799 eck$LassoCheckResult]: stem already infeasible [2018-11-23 01:26:46,486 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 01:26:46,486 INFO L82 PathProgramCache]: Analyzing trace with hash -1238899240, now seen corresponding path program 1 times [2018-11-23 01:26:46,486 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 01:26:46,487 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 01:26:46,487 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 01:26:46,487 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 01:26:46,487 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 01:26:46,492 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 01:26:46,520 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 01:26:46,521 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 01:26:46,521 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-23 01:26:46,521 INFO L811 eck$LassoCheckResult]: loop already infeasible [2018-11-23 01:26:46,521 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-23 01:26:46,521 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-23 01:26:46,521 INFO L87 Difference]: Start difference. First operand 665 states and 983 transitions. cyclomatic complexity: 319 Second operand 3 states. [2018-11-23 01:26:46,596 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 01:26:46,597 INFO L93 Difference]: Finished difference Result 1184 states and 1736 transitions. [2018-11-23 01:26:46,597 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-23 01:26:46,597 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1184 states and 1736 transitions. [2018-11-23 01:26:46,602 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 1096 [2018-11-23 01:26:46,606 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1184 states to 1184 states and 1736 transitions. [2018-11-23 01:26:46,606 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1184 [2018-11-23 01:26:46,607 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1184 [2018-11-23 01:26:46,607 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1184 states and 1736 transitions. [2018-11-23 01:26:46,609 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-23 01:26:46,609 INFO L705 BuchiCegarLoop]: Abstraction has 1184 states and 1736 transitions. [2018-11-23 01:26:46,610 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1184 states and 1736 transitions. [2018-11-23 01:26:46,622 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1184 to 1182. [2018-11-23 01:26:46,622 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1182 states. [2018-11-23 01:26:46,624 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1182 states to 1182 states and 1734 transitions. [2018-11-23 01:26:46,625 INFO L728 BuchiCegarLoop]: Abstraction has 1182 states and 1734 transitions. [2018-11-23 01:26:46,625 INFO L608 BuchiCegarLoop]: Abstraction has 1182 states and 1734 transitions. [2018-11-23 01:26:46,625 INFO L442 BuchiCegarLoop]: ======== Iteration 10============ [2018-11-23 01:26:46,625 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1182 states and 1734 transitions. [2018-11-23 01:26:46,628 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 1094 [2018-11-23 01:26:46,629 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-23 01:26:46,629 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-23 01:26:46,629 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 01:26:46,630 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 01:26:46,630 INFO L794 eck$LassoCheckResult]: Stem: 13160#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0; 13060#L-1 havoc main_#res;havoc main_~__retres1~8;havoc main_~__retres1~8;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 12831#L1018 havoc start_simulation_#t~ret18, start_simulation_#t~ret19, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 12832#L470 assume 1 == ~m_i~0;~m_st~0 := 0; 12667#L477-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 12668#L482-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 13017#L487-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 13018#L492-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 12855#L497-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 12856#L502-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 12950#L507-1 assume !(0 == ~M_E~0); 12682#L686-1 assume !(0 == ~T1_E~0); 12683#L691-1 assume !(0 == ~T2_E~0); 13028#L696-1 assume !(0 == ~T3_E~0); 13029#L701-1 assume !(0 == ~T4_E~0); 12864#L706-1 assume !(0 == ~T5_E~0); 12865#L711-1 assume !(0 == ~T6_E~0); 13142#L716-1 assume !(0 == ~E_M~0); 12823#L721-1 assume !(0 == ~E_1~0); 12824#L726-1 assume !(0 == ~E_2~0); 12585#L731-1 assume !(0 == ~E_3~0); 12586#L736-1 assume !(0 == ~E_4~0); 12672#L741-1 assume !(0 == ~E_5~0); 12673#L746-1 assume !(0 == ~E_6~0); 13023#L751-1 havoc activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 12785#L336 assume !(1 == ~m_pc~0); 12719#L336-2 is_master_triggered_~__retres1~0 := 0; 12720#L347 is_master_triggered_#res := is_master_triggered_~__retres1~0; 12781#L348 activate_threads_#t~ret10 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 12696#L851 assume !(0 != activate_threads_~tmp~1); 12697#L851-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 12698#L355 assume !(1 == ~t1_pc~0); 12988#L355-2 is_transmit1_triggered_~__retres1~1 := 0; 12987#L366 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 12670#L367 activate_threads_#t~ret11 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 12671#L859 assume !(0 != activate_threads_~tmp___0~0); 13136#L859-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 13137#L374 assume 1 == ~t2_pc~0; 12925#L375 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 12926#L385 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 12923#L386 activate_threads_#t~ret12 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 12924#L867 assume !(0 != activate_threads_~tmp___1~0); 13242#L867-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 13245#L393 assume !(1 == ~t3_pc~0); 13234#L393-2 is_transmit3_triggered_~__retres1~3 := 0; 13255#L404 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 13231#L405 activate_threads_#t~ret13 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 12828#L875 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 12813#L875-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 12814#L412 assume 1 == ~t4_pc~0; 12765#L413 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 12766#L423 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 12763#L424 activate_threads_#t~ret14 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 12764#L883 assume !(0 != activate_threads_~tmp___3~0); 13038#L883-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 12858#L431 assume !(1 == ~t5_pc~0); 12844#L431-2 is_transmit5_triggered_~__retres1~5 := 0; 12845#L442 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 12857#L443 activate_threads_#t~ret15 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 13019#L891 assume !(0 != activate_threads_~tmp___4~0); 13193#L891-2 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 13081#L450 assume 1 == ~t6_pc~0; 13082#L451 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6 := 1; 13079#L461 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 13080#L462 activate_threads_#t~ret16 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 13176#L899 assume !(0 != activate_threads_~tmp___5~0); 13196#L899-2 assume !(1 == ~M_E~0); 12581#L764-1 assume !(1 == ~T1_E~0); 12582#L769-1 assume !(1 == ~T2_E~0); 12702#L774-1 assume !(1 == ~T3_E~0); 12703#L779-1 assume !(1 == ~T4_E~0); 13039#L784-1 assume !(1 == ~T5_E~0); 13040#L789-1 assume 1 == ~T6_E~0;~T6_E~0 := 2; 12860#L794-1 assume !(1 == ~E_M~0); 12861#L799-1 assume !(1 == ~E_1~0); 13138#L804-1 assume !(1 == ~E_2~0); 12815#L809-1 assume !(1 == ~E_3~0); 12816#L814-1 assume !(1 == ~E_4~0); 12579#L819-1 assume !(1 == ~E_5~0); 12580#L824-1 assume !(1 == ~E_6~0); 13089#L1055-1 [2018-11-23 01:26:46,630 INFO L796 eck$LassoCheckResult]: Loop: 13089#L1055-1 assume !false; 13536#L1056 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret2, eval_#t~nondet3, eval_~tmp_ndt_1~0, eval_#t~nondet4, eval_~tmp_ndt_2~0, eval_#t~nondet5, eval_~tmp_ndt_3~0, eval_#t~nondet6, eval_~tmp_ndt_4~0, eval_#t~nondet7, eval_~tmp_ndt_5~0, eval_#t~nondet8, eval_~tmp_ndt_6~0, eval_#t~nondet9, eval_~tmp_ndt_7~0, eval_~tmp~0;havoc eval_~tmp~0; 12681#L661 assume !false; 13535#L568 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~7;havoc exists_runnable_thread_~__retres1~7; 13531#L520 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7 := 1; 13489#L557 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~7; 13488#L558 eval_#t~ret2 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret2;havoc eval_#t~ret2; 13187#L572 assume !(0 != eval_~tmp~0); 13189#L676 start_simulation_~kernel_st~0 := 2; 13525#L470-1 start_simulation_~kernel_st~0 := 3; 13523#L686-2 assume 0 == ~M_E~0;~M_E~0 := 1; 13521#L686-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 13515#L691-3 assume !(0 == ~T2_E~0); 13514#L696-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 13513#L701-3 assume !(0 == ~T4_E~0); 13511#L706-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 13509#L711-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 13507#L716-3 assume 0 == ~E_M~0;~E_M~0 := 1; 13505#L721-3 assume 0 == ~E_1~0;~E_1~0 := 1; 13503#L726-3 assume 0 == ~E_2~0;~E_2~0 := 1; 12570#L731-3 assume !(0 == ~E_3~0); 12571#L736-3 assume 0 == ~E_4~0;~E_4~0 := 1; 12686#L741-3 assume !(0 == ~E_5~0); 12687#L746-3 assume 0 == ~E_6~0;~E_6~0 := 1; 13030#L751-3 havoc activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 13031#L336-24 assume !(1 == ~m_pc~0); 13201#L336-26 is_master_triggered_~__retres1~0 := 0; 13200#L347-8 is_master_triggered_#res := is_master_triggered_~__retres1~0; 13198#L348-8 activate_threads_#t~ret10 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 12617#L851-24 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 12587#L851-26 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 12588#L355-24 assume !(1 == ~t1_pc~0); 12690#L355-26 is_transmit1_triggered_~__retres1~1 := 0; 13747#L366-8 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 13746#L367-8 activate_threads_#t~ret11 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 13745#L859-24 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 13744#L859-26 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 13743#L374-24 assume !(1 == ~t2_pc~0); 13741#L374-26 is_transmit2_triggered_~__retres1~2 := 0; 13740#L385-8 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 13739#L386-8 activate_threads_#t~ret12 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 13738#L867-24 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 13737#L867-26 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 13736#L393-24 assume !(1 == ~t3_pc~0); 13734#L393-26 is_transmit3_triggered_~__retres1~3 := 0; 13733#L404-8 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 13732#L405-8 activate_threads_#t~ret13 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 13731#L875-24 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 13730#L875-26 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 13729#L412-24 assume 1 == ~t4_pc~0; 13728#L413-8 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 13726#L423-8 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 13711#L424-8 activate_threads_#t~ret14 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 13710#L883-24 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 13709#L883-26 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 13708#L431-24 assume 1 == ~t5_pc~0; 13706#L432-8 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 13047#L442-8 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 13048#L443-8 activate_threads_#t~ret15 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 13662#L891-24 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 13661#L891-26 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 13660#L450-24 assume !(1 == ~t6_pc~0); 13658#L450-26 is_transmit6_triggered_~__retres1~6 := 0; 13657#L461-8 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 13656#L462-8 activate_threads_#t~ret16 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 13655#L899-24 assume 0 != activate_threads_~tmp___5~0;~t6_st~0 := 0; 13654#L899-26 assume !(1 == ~M_E~0); 13653#L764-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 13652#L769-3 assume !(1 == ~T2_E~0); 13651#L774-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 13650#L779-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 13649#L784-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 13648#L789-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 13647#L794-3 assume 1 == ~E_M~0;~E_M~0 := 2; 13646#L799-3 assume !(1 == ~E_1~0); 13645#L804-3 assume 1 == ~E_2~0;~E_2~0 := 2; 13644#L809-3 assume !(1 == ~E_3~0); 13643#L814-3 assume 1 == ~E_4~0;~E_4~0 := 2; 13642#L819-3 assume 1 == ~E_5~0;~E_5~0 := 2; 13641#L824-3 assume 1 == ~E_6~0;~E_6~0 := 2; 13639#L829-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~7;havoc exists_runnable_thread_~__retres1~7; 13577#L520-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7 := 1; 13571#L557-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~7; 13567#L558-1 start_simulation_#t~ret18 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret18;havoc start_simulation_#t~ret18; 13563#L1074 assume !(0 == start_simulation_~tmp~3); 13560#L1074-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret17, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~7;havoc exists_runnable_thread_~__retres1~7; 13556#L520-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7 := 1; 13549#L557-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~7; 13546#L558-2 stop_simulation_#t~ret17 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret17;havoc stop_simulation_#t~ret17; 13544#L1029 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 13542#L1036 stop_simulation_#res := stop_simulation_~__retres2~0; 13540#L1037 start_simulation_#t~ret19 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret19;havoc start_simulation_#t~ret19; 13538#L1087 assume !(0 != start_simulation_~tmp___0~1); 13089#L1055-1 [2018-11-23 01:26:46,630 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 01:26:46,630 INFO L82 PathProgramCache]: Analyzing trace with hash -1037131999, now seen corresponding path program 1 times [2018-11-23 01:26:46,630 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 01:26:46,630 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 01:26:46,631 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 01:26:46,631 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 01:26:46,631 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 01:26:46,635 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 01:26:46,654 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 01:26:46,654 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 01:26:46,654 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2018-11-23 01:26:46,655 INFO L799 eck$LassoCheckResult]: stem already infeasible [2018-11-23 01:26:46,655 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 01:26:46,655 INFO L82 PathProgramCache]: Analyzing trace with hash -1472923083, now seen corresponding path program 1 times [2018-11-23 01:26:46,655 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 01:26:46,655 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 01:26:46,656 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 01:26:46,656 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 01:26:46,656 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 01:26:46,660 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 01:26:46,676 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 01:26:46,677 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 01:26:46,677 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-23 01:26:46,677 INFO L811 eck$LassoCheckResult]: loop already infeasible [2018-11-23 01:26:46,677 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-23 01:26:46,677 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-23 01:26:46,677 INFO L87 Difference]: Start difference. First operand 1182 states and 1734 transitions. cyclomatic complexity: 554 Second operand 3 states. [2018-11-23 01:26:46,765 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 01:26:46,765 INFO L93 Difference]: Finished difference Result 2163 states and 3150 transitions. [2018-11-23 01:26:46,770 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-23 01:26:46,770 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2163 states and 3150 transitions. [2018-11-23 01:26:46,778 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 2070 [2018-11-23 01:26:46,786 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2163 states to 2163 states and 3150 transitions. [2018-11-23 01:26:46,786 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2163 [2018-11-23 01:26:46,788 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2163 [2018-11-23 01:26:46,788 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2163 states and 3150 transitions. [2018-11-23 01:26:46,790 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-23 01:26:46,791 INFO L705 BuchiCegarLoop]: Abstraction has 2163 states and 3150 transitions. [2018-11-23 01:26:46,792 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2163 states and 3150 transitions. [2018-11-23 01:26:46,814 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2163 to 2159. [2018-11-23 01:26:46,814 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2159 states. [2018-11-23 01:26:46,818 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2159 states to 2159 states and 3146 transitions. [2018-11-23 01:26:46,818 INFO L728 BuchiCegarLoop]: Abstraction has 2159 states and 3146 transitions. [2018-11-23 01:26:46,818 INFO L608 BuchiCegarLoop]: Abstraction has 2159 states and 3146 transitions. [2018-11-23 01:26:46,819 INFO L442 BuchiCegarLoop]: ======== Iteration 11============ [2018-11-23 01:26:46,819 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2159 states and 3146 transitions. [2018-11-23 01:26:46,826 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 2066 [2018-11-23 01:26:46,826 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-23 01:26:46,826 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-23 01:26:46,827 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 01:26:46,827 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 01:26:46,827 INFO L794 eck$LassoCheckResult]: Stem: 16520#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0; 16412#L-1 havoc main_#res;havoc main_~__retres1~8;havoc main_~__retres1~8;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 16182#L1018 havoc start_simulation_#t~ret18, start_simulation_#t~ret19, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 16183#L470 assume 1 == ~m_i~0;~m_st~0 := 0; 16019#L477-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 16020#L482-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 16368#L487-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 16369#L492-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 16204#L497-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 16205#L502-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 16301#L507-1 assume !(0 == ~M_E~0); 16034#L686-1 assume !(0 == ~T1_E~0); 16035#L691-1 assume !(0 == ~T2_E~0); 16380#L696-1 assume !(0 == ~T3_E~0); 16381#L701-1 assume !(0 == ~T4_E~0); 16213#L706-1 assume !(0 == ~T5_E~0); 16214#L711-1 assume !(0 == ~T6_E~0); 16495#L716-1 assume !(0 == ~E_M~0); 16174#L721-1 assume !(0 == ~E_1~0); 16175#L726-1 assume !(0 == ~E_2~0); 15937#L731-1 assume !(0 == ~E_3~0); 15938#L736-1 assume !(0 == ~E_4~0); 16025#L741-1 assume !(0 == ~E_5~0); 16026#L746-1 assume !(0 == ~E_6~0); 16375#L751-1 havoc activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 16136#L336 assume !(1 == ~m_pc~0); 16070#L336-2 is_master_triggered_~__retres1~0 := 0; 16071#L347 is_master_triggered_#res := is_master_triggered_~__retres1~0; 16132#L348 activate_threads_#t~ret10 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 16047#L851 assume !(0 != activate_threads_~tmp~1); 16048#L851-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 16050#L355 assume !(1 == ~t1_pc~0); 16342#L355-2 is_transmit1_triggered_~__retres1~1 := 0; 16339#L366 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 16023#L367 activate_threads_#t~ret11 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 16024#L859 assume !(0 != activate_threads_~tmp___0~0); 16487#L859-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 16488#L374 assume !(1 == ~t2_pc~0); 16514#L374-2 is_transmit2_triggered_~__retres1~2 := 0; 16515#L385 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 16275#L386 activate_threads_#t~ret12 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 16276#L867 assume !(0 != activate_threads_~tmp___1~0); 16610#L867-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 16612#L393 assume !(1 == ~t3_pc~0); 16602#L393-2 is_transmit3_triggered_~__retres1~3 := 0; 16620#L404 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 16599#L405 activate_threads_#t~ret13 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 16179#L875 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 16164#L875-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 16165#L412 assume 1 == ~t4_pc~0; 16116#L413 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 16117#L423 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 16114#L424 activate_threads_#t~ret14 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 16115#L883 assume !(0 != activate_threads_~tmp___3~0); 16391#L883-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 16207#L431 assume !(1 == ~t5_pc~0); 16193#L431-2 is_transmit5_triggered_~__retres1~5 := 0; 16194#L442 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 16206#L443 activate_threads_#t~ret15 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 16372#L891 assume !(0 != activate_threads_~tmp___4~0); 16555#L891-2 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 16433#L450 assume 1 == ~t6_pc~0; 16434#L451 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6 := 1; 16431#L461 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 16432#L462 activate_threads_#t~ret16 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 16538#L899 assume !(0 != activate_threads_~tmp___5~0); 16557#L899-2 assume !(1 == ~M_E~0); 15933#L764-1 assume !(1 == ~T1_E~0); 15934#L769-1 assume !(1 == ~T2_E~0); 16053#L774-1 assume !(1 == ~T3_E~0); 16054#L779-1 assume !(1 == ~T4_E~0); 16392#L784-1 assume !(1 == ~T5_E~0); 16393#L789-1 assume 1 == ~T6_E~0;~T6_E~0 := 2; 16209#L794-1 assume !(1 == ~E_M~0); 16210#L799-1 assume !(1 == ~E_1~0); 16489#L804-1 assume !(1 == ~E_2~0); 16166#L809-1 assume !(1 == ~E_3~0); 16167#L814-1 assume !(1 == ~E_4~0); 15931#L819-1 assume !(1 == ~E_5~0); 15932#L824-1 assume !(1 == ~E_6~0); 16441#L1055-1 [2018-11-23 01:26:46,828 INFO L796 eck$LassoCheckResult]: Loop: 16441#L1055-1 assume !false; 16411#L1056 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret2, eval_#t~nondet3, eval_~tmp_ndt_1~0, eval_#t~nondet4, eval_~tmp_ndt_2~0, eval_#t~nondet5, eval_~tmp_ndt_3~0, eval_#t~nondet6, eval_~tmp_ndt_4~0, eval_#t~nondet7, eval_~tmp_ndt_5~0, eval_#t~nondet8, eval_~tmp_ndt_6~0, eval_#t~nondet9, eval_~tmp_ndt_7~0, eval_~tmp~0;havoc eval_~tmp~0; 15978#L661 assume !false; 16496#L568 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~7;havoc exists_runnable_thread_~__retres1~7; 16360#L520 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7 := 1; 15928#L557 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~7; 16588#L558 eval_#t~ret2 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret2;havoc eval_#t~ret2; 16549#L572 assume !(0 != eval_~tmp~0); 16551#L676 start_simulation_~kernel_st~0 := 2; 18032#L470-1 start_simulation_~kernel_st~0 := 3; 18031#L686-2 assume 0 == ~M_E~0;~M_E~0 := 1; 18030#L686-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 18029#L691-3 assume !(0 == ~T2_E~0); 18028#L696-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 18027#L701-3 assume !(0 == ~T4_E~0); 18026#L706-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 18025#L711-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 16291#L716-3 assume 0 == ~E_M~0;~E_M~0 := 1; 16152#L721-3 assume 0 == ~E_1~0;~E_1~0 := 1; 16153#L726-3 assume 0 == ~E_2~0;~E_2~0 := 1; 15922#L731-3 assume !(0 == ~E_3~0); 15923#L736-3 assume 0 == ~E_4~0;~E_4~0 := 1; 16038#L741-3 assume !(0 == ~E_5~0); 16039#L746-3 assume 0 == ~E_6~0;~E_6~0 := 1; 16382#L751-3 havoc activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 16383#L336-24 assume 1 == ~m_pc~0; 16561#L337-8 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 16562#L347-8 is_master_triggered_#res := is_master_triggered_~__retres1~0; 16560#L348-8 activate_threads_#t~ret10 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 15966#L851-24 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 15939#L851-26 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 15940#L355-24 assume !(1 == ~t1_pc~0); 16005#L355-26 is_transmit1_triggered_~__retres1~1 := 0; 16006#L366-8 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 15958#L367-8 activate_threads_#t~ret11 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 15959#L859-24 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 16228#L859-26 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 16292#L374-24 assume !(1 == ~t2_pc~0); 16293#L374-26 is_transmit2_triggered_~__retres1~2 := 0; 16298#L385-8 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 16265#L386-8 activate_threads_#t~ret12 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 16266#L867-24 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 16442#L867-26 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 16443#L393-24 assume !(1 == ~t3_pc~0); 16456#L393-26 is_transmit3_triggered_~__retres1~3 := 0; 16609#L404-8 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 16453#L405-8 activate_threads_#t~ret13 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 16454#L875-24 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 16593#L875-26 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 16146#L412-24 assume 1 == ~t4_pc~0; 16104#L413-8 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 16105#L423-8 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 16100#L424-8 activate_threads_#t~ret14 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 16101#L883-24 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 16303#L883-26 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 16304#L431-24 assume 1 == ~t5_pc~0; 16326#L432-8 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 16327#L442-8 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 16324#L443-8 activate_threads_#t~ret15 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 16325#L891-24 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 16510#L891-26 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 16513#L450-24 assume 1 == ~t6_pc~0; 16531#L451-8 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6 := 1; 16428#L461-8 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 16429#L462-8 activate_threads_#t~ret16 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 16530#L899-24 assume 0 != activate_threads_~tmp___5~0;~t6_st~0 := 0; 16614#L899-26 assume !(1 == ~M_E~0); 15920#L764-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 15921#L769-3 assume !(1 == ~T2_E~0); 16030#L774-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 16031#L779-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 16378#L784-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 16379#L789-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 16211#L794-3 assume 1 == ~E_M~0;~E_M~0 := 2; 16212#L799-3 assume !(1 == ~E_1~0); 16493#L804-3 assume 1 == ~E_2~0;~E_2~0 := 2; 16172#L809-3 assume !(1 == ~E_3~0); 16173#L814-3 assume 1 == ~E_4~0;~E_4~0 := 2; 15935#L819-3 assume 1 == ~E_5~0;~E_5~0 := 2; 15936#L824-3 assume 1 == ~E_6~0;~E_6~0 := 2; 16055#L829-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~7;havoc exists_runnable_thread_~__retres1~7; 16056#L520-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7 := 1; 15930#L557-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~7; 16589#L558-1 start_simulation_#t~ret18 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret18;havoc start_simulation_#t~ret18; 16594#L1074 assume !(0 == start_simulation_~tmp~3); 16236#L1074-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret17, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~7;havoc exists_runnable_thread_~__retres1~7; 16370#L520-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7 := 1; 16013#L557-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~7; 16590#L558-2 stop_simulation_#t~ret17 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret17;havoc stop_simulation_#t~ret17; 16180#L1029 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 16181#L1036 stop_simulation_#res := stop_simulation_~__retres2~0; 16231#L1037 start_simulation_#t~ret19 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret19;havoc start_simulation_#t~ret19; 16397#L1087 assume !(0 != start_simulation_~tmp___0~1); 16441#L1055-1 [2018-11-23 01:26:46,828 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 01:26:46,828 INFO L82 PathProgramCache]: Analyzing trace with hash 861398306, now seen corresponding path program 1 times [2018-11-23 01:26:46,828 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 01:26:46,828 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 01:26:46,829 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 01:26:46,829 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 01:26:46,829 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 01:26:46,833 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 01:26:46,871 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 01:26:46,872 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 01:26:46,872 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2018-11-23 01:26:46,872 INFO L799 eck$LassoCheckResult]: stem already infeasible [2018-11-23 01:26:46,872 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 01:26:46,872 INFO L82 PathProgramCache]: Analyzing trace with hash 65256567, now seen corresponding path program 1 times [2018-11-23 01:26:46,872 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 01:26:46,873 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 01:26:46,877 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 01:26:46,877 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 01:26:46,877 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 01:26:46,884 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 01:26:46,914 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 01:26:46,915 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 01:26:46,915 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-23 01:26:46,915 INFO L811 eck$LassoCheckResult]: loop already infeasible [2018-11-23 01:26:46,915 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-23 01:26:46,915 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-23 01:26:46,916 INFO L87 Difference]: Start difference. First operand 2159 states and 3146 transitions. cyclomatic complexity: 991 Second operand 3 states. [2018-11-23 01:26:47,000 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 01:26:47,000 INFO L93 Difference]: Finished difference Result 4008 states and 5807 transitions. [2018-11-23 01:26:47,002 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-23 01:26:47,002 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 4008 states and 5807 transitions. [2018-11-23 01:26:47,019 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 3900 [2018-11-23 01:26:47,036 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 4008 states to 4008 states and 5807 transitions. [2018-11-23 01:26:47,036 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 4008 [2018-11-23 01:26:47,039 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 4008 [2018-11-23 01:26:47,039 INFO L73 IsDeterministic]: Start isDeterministic. Operand 4008 states and 5807 transitions. [2018-11-23 01:26:47,044 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-23 01:26:47,044 INFO L705 BuchiCegarLoop]: Abstraction has 4008 states and 5807 transitions. [2018-11-23 01:26:47,047 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 4008 states and 5807 transitions. [2018-11-23 01:26:47,116 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 4008 to 4000. [2018-11-23 01:26:47,116 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 4000 states. [2018-11-23 01:26:47,123 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 4000 states to 4000 states and 5799 transitions. [2018-11-23 01:26:47,123 INFO L728 BuchiCegarLoop]: Abstraction has 4000 states and 5799 transitions. [2018-11-23 01:26:47,124 INFO L608 BuchiCegarLoop]: Abstraction has 4000 states and 5799 transitions. [2018-11-23 01:26:47,124 INFO L442 BuchiCegarLoop]: ======== Iteration 12============ [2018-11-23 01:26:47,124 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 4000 states and 5799 transitions. [2018-11-23 01:26:47,134 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 3892 [2018-11-23 01:26:47,134 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-23 01:26:47,134 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-23 01:26:47,135 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 01:26:47,135 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 01:26:47,135 INFO L794 eck$LassoCheckResult]: Stem: 22717#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0; 22596#L-1 havoc main_#res;havoc main_~__retres1~8;havoc main_~__retres1~8;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 22360#L1018 havoc start_simulation_#t~ret18, start_simulation_#t~ret19, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 22361#L470 assume 1 == ~m_i~0;~m_st~0 := 0; 22191#L477-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 22192#L482-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 22552#L487-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 22553#L492-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 22386#L497-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 22387#L502-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 22481#L507-1 assume !(0 == ~M_E~0); 22206#L686-1 assume !(0 == ~T1_E~0); 22207#L691-1 assume !(0 == ~T2_E~0); 22564#L696-1 assume !(0 == ~T3_E~0); 22565#L701-1 assume !(0 == ~T4_E~0); 22395#L706-1 assume !(0 == ~T5_E~0); 22396#L711-1 assume !(0 == ~T6_E~0); 22687#L716-1 assume !(0 == ~E_M~0); 22346#L721-1 assume !(0 == ~E_1~0); 22347#L726-1 assume !(0 == ~E_2~0); 22111#L731-1 assume !(0 == ~E_3~0); 22112#L736-1 assume !(0 == ~E_4~0); 22197#L741-1 assume !(0 == ~E_5~0); 22198#L746-1 assume !(0 == ~E_6~0); 22559#L751-1 havoc activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 22306#L336 assume !(1 == ~m_pc~0); 22243#L336-2 is_master_triggered_~__retres1~0 := 0; 22244#L347 is_master_triggered_#res := is_master_triggered_~__retres1~0; 22302#L348 activate_threads_#t~ret10 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 22219#L851 assume !(0 != activate_threads_~tmp~1); 22220#L851-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 22223#L355 assume !(1 == ~t1_pc~0); 22525#L355-2 is_transmit1_triggered_~__retres1~1 := 0; 22522#L366 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 22195#L367 activate_threads_#t~ret11 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 22196#L859 assume !(0 != activate_threads_~tmp___0~0); 22679#L859-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 22680#L374 assume !(1 == ~t2_pc~0); 22709#L374-2 is_transmit2_triggered_~__retres1~2 := 0; 22710#L385 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 22456#L386 activate_threads_#t~ret12 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 22457#L867 assume !(0 != activate_threads_~tmp___1~0); 22812#L867-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 22814#L393 assume !(1 == ~t3_pc~0); 22803#L393-2 is_transmit3_triggered_~__retres1~3 := 0; 22822#L404 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 22800#L405 activate_threads_#t~ret13 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 22354#L875 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 22333#L875-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 22334#L412 assume !(1 == ~t4_pc~0); 22370#L412-2 is_transmit4_triggered_~__retres1~4 := 0; 22369#L423 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 22287#L424 activate_threads_#t~ret14 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 22288#L883 assume !(0 != activate_threads_~tmp___3~0); 22575#L883-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 22389#L431 assume !(1 == ~t5_pc~0); 22375#L431-2 is_transmit5_triggered_~__retres1~5 := 0; 22376#L442 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 22388#L443 activate_threads_#t~ret15 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 22556#L891 assume !(0 != activate_threads_~tmp___4~0); 22752#L891-2 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 22617#L450 assume 1 == ~t6_pc~0; 22618#L451 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6 := 1; 22615#L461 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 22616#L462 activate_threads_#t~ret16 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 22734#L899 assume !(0 != activate_threads_~tmp___5~0); 22756#L899-2 assume !(1 == ~M_E~0); 22107#L764-1 assume !(1 == ~T1_E~0); 22108#L769-1 assume !(1 == ~T2_E~0); 22226#L774-1 assume !(1 == ~T3_E~0); 22227#L779-1 assume !(1 == ~T4_E~0); 22576#L784-1 assume !(1 == ~T5_E~0); 22577#L789-1 assume 1 == ~T6_E~0;~T6_E~0 := 2; 22391#L794-1 assume !(1 == ~E_M~0); 22392#L799-1 assume !(1 == ~E_1~0); 22681#L804-1 assume !(1 == ~E_2~0); 22335#L809-1 assume !(1 == ~E_3~0); 22336#L814-1 assume !(1 == ~E_4~0); 22105#L819-1 assume !(1 == ~E_5~0); 22106#L824-1 assume !(1 == ~E_6~0); 22626#L1055-1 [2018-11-23 01:26:47,136 INFO L796 eck$LassoCheckResult]: Loop: 22626#L1055-1 assume !false; 22595#L1056 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret2, eval_#t~nondet3, eval_~tmp_ndt_1~0, eval_#t~nondet4, eval_~tmp_ndt_2~0, eval_#t~nondet5, eval_~tmp_ndt_3~0, eval_#t~nondet6, eval_~tmp_ndt_4~0, eval_#t~nondet7, eval_~tmp_ndt_5~0, eval_#t~nondet8, eval_~tmp_ndt_6~0, eval_#t~nondet9, eval_~tmp_ndt_7~0, eval_~tmp~0;havoc eval_~tmp~0; 22152#L661 assume !false; 22688#L568 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~7;havoc exists_runnable_thread_~__retres1~7; 22543#L520 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7 := 1; 22102#L557 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~7; 22783#L558 eval_#t~ret2 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret2;havoc eval_#t~ret2; 22746#L572 assume !(0 != eval_~tmp~0); 22748#L676 start_simulation_~kernel_st~0 := 2; 26001#L470-1 start_simulation_~kernel_st~0 := 3; 26000#L686-2 assume 0 == ~M_E~0;~M_E~0 := 1; 25999#L686-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 25998#L691-3 assume !(0 == ~T2_E~0); 25997#L696-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 25996#L701-3 assume !(0 == ~T4_E~0); 25995#L706-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 25994#L711-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 25993#L716-3 assume 0 == ~E_M~0;~E_M~0 := 1; 25992#L721-3 assume 0 == ~E_1~0;~E_1~0 := 1; 25991#L726-3 assume 0 == ~E_2~0;~E_2~0 := 1; 25990#L731-3 assume !(0 == ~E_3~0); 25989#L736-3 assume 0 == ~E_4~0;~E_4~0 := 1; 25988#L741-3 assume !(0 == ~E_5~0); 25987#L746-3 assume 0 == ~E_6~0;~E_6~0 := 1; 25986#L751-3 havoc activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 25985#L336-24 assume !(1 == ~m_pc~0); 25984#L336-26 is_master_triggered_~__retres1~0 := 0; 25982#L347-8 is_master_triggered_#res := is_master_triggered_~__retres1~0; 25981#L348-8 activate_threads_#t~ret10 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 25980#L851-24 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 25979#L851-26 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 25978#L355-24 assume !(1 == ~t1_pc~0); 25977#L355-26 is_transmit1_triggered_~__retres1~1 := 0; 25976#L366-8 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 25975#L367-8 activate_threads_#t~ret11 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 25974#L859-24 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 25973#L859-26 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 25972#L374-24 assume !(1 == ~t2_pc~0); 25971#L374-26 is_transmit2_triggered_~__retres1~2 := 0; 25970#L385-8 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 25969#L386-8 activate_threads_#t~ret12 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 25968#L867-24 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 25967#L867-26 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 25966#L393-24 assume !(1 == ~t3_pc~0); 25964#L393-26 is_transmit3_triggered_~__retres1~3 := 0; 25963#L404-8 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 25962#L405-8 activate_threads_#t~ret13 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 25961#L875-24 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 25960#L875-26 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 25959#L412-24 assume !(1 == ~t4_pc~0); 25958#L412-26 is_transmit4_triggered_~__retres1~4 := 0; 25956#L423-8 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 25955#L424-8 activate_threads_#t~ret14 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 25954#L883-24 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 25953#L883-26 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 25952#L431-24 assume 1 == ~t5_pc~0; 25950#L432-8 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 25949#L442-8 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 25947#L443-8 activate_threads_#t~ret15 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 25945#L891-24 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 25943#L891-26 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 25942#L450-24 assume !(1 == ~t6_pc~0); 25940#L450-26 is_transmit6_triggered_~__retres1~6 := 0; 25938#L461-8 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 25936#L462-8 activate_threads_#t~ret16 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 25934#L899-24 assume 0 != activate_threads_~tmp___5~0;~t6_st~0 := 0; 25932#L899-26 assume !(1 == ~M_E~0); 25930#L764-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 25928#L769-3 assume !(1 == ~T2_E~0); 25926#L774-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 25923#L779-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 25922#L784-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 22834#L789-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 22393#L794-3 assume 1 == ~E_M~0;~E_M~0 := 2; 22394#L799-3 assume !(1 == ~E_1~0); 22685#L804-3 assume 1 == ~E_2~0;~E_2~0 := 2; 22344#L809-3 assume !(1 == ~E_3~0); 22345#L814-3 assume 1 == ~E_4~0;~E_4~0 := 2; 22109#L819-3 assume 1 == ~E_5~0;~E_5~0 := 2; 22110#L824-3 assume 1 == ~E_6~0;~E_6~0 := 2; 22228#L829-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~7;havoc exists_runnable_thread_~__retres1~7; 22229#L520-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7 := 1; 22104#L557-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~7; 22784#L558-1 start_simulation_#t~ret18 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret18;havoc start_simulation_#t~ret18; 22793#L1074 assume !(0 == start_simulation_~tmp~3); 22417#L1074-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret17, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~7;havoc exists_runnable_thread_~__retres1~7; 22554#L520-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7 := 1; 22185#L557-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~7; 22785#L558-2 stop_simulation_#t~ret17 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret17;havoc stop_simulation_#t~ret17; 22358#L1029 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 22359#L1036 stop_simulation_#res := stop_simulation_~__retres2~0; 22412#L1037 start_simulation_#t~ret19 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret19;havoc start_simulation_#t~ret19; 22581#L1087 assume !(0 != start_simulation_~tmp___0~1); 22626#L1055-1 [2018-11-23 01:26:47,136 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 01:26:47,136 INFO L82 PathProgramCache]: Analyzing trace with hash -910072669, now seen corresponding path program 1 times [2018-11-23 01:26:47,136 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 01:26:47,136 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 01:26:47,137 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 01:26:47,137 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 01:26:47,137 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 01:26:47,141 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 01:26:47,174 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 01:26:47,174 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 01:26:47,174 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2018-11-23 01:26:47,174 INFO L799 eck$LassoCheckResult]: stem already infeasible [2018-11-23 01:26:47,174 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 01:26:47,174 INFO L82 PathProgramCache]: Analyzing trace with hash 1546941524, now seen corresponding path program 1 times [2018-11-23 01:26:47,175 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 01:26:47,175 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 01:26:47,175 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 01:26:47,175 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 01:26:47,175 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 01:26:47,180 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 01:26:47,209 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 01:26:47,210 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 01:26:47,210 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-23 01:26:47,210 INFO L811 eck$LassoCheckResult]: loop already infeasible [2018-11-23 01:26:47,210 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-23 01:26:47,210 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-23 01:26:47,211 INFO L87 Difference]: Start difference. First operand 4000 states and 5799 transitions. cyclomatic complexity: 1807 Second operand 3 states. [2018-11-23 01:26:47,294 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 01:26:47,295 INFO L93 Difference]: Finished difference Result 7475 states and 10784 transitions. [2018-11-23 01:26:47,296 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-23 01:26:47,296 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 7475 states and 10784 transitions. [2018-11-23 01:26:47,321 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 7328 [2018-11-23 01:26:47,348 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 7475 states to 7475 states and 10784 transitions. [2018-11-23 01:26:47,349 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 7475 [2018-11-23 01:26:47,353 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 7475 [2018-11-23 01:26:47,353 INFO L73 IsDeterministic]: Start isDeterministic. Operand 7475 states and 10784 transitions. [2018-11-23 01:26:47,360 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-23 01:26:47,360 INFO L705 BuchiCegarLoop]: Abstraction has 7475 states and 10784 transitions. [2018-11-23 01:26:47,365 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 7475 states and 10784 transitions. [2018-11-23 01:26:47,441 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 7475 to 7459. [2018-11-23 01:26:47,442 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 7459 states. [2018-11-23 01:26:47,454 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 7459 states to 7459 states and 10768 transitions. [2018-11-23 01:26:47,454 INFO L728 BuchiCegarLoop]: Abstraction has 7459 states and 10768 transitions. [2018-11-23 01:26:47,454 INFO L608 BuchiCegarLoop]: Abstraction has 7459 states and 10768 transitions. [2018-11-23 01:26:47,454 INFO L442 BuchiCegarLoop]: ======== Iteration 13============ [2018-11-23 01:26:47,454 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 7459 states and 10768 transitions. [2018-11-23 01:26:47,472 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 7312 [2018-11-23 01:26:47,472 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-23 01:26:47,473 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-23 01:26:47,473 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 01:26:47,474 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 01:26:47,474 INFO L794 eck$LassoCheckResult]: Stem: 34183#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0; 34071#L-1 havoc main_#res;havoc main_~__retres1~8;havoc main_~__retres1~8;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 33837#L1018 havoc start_simulation_#t~ret18, start_simulation_#t~ret19, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 33838#L470 assume 1 == ~m_i~0;~m_st~0 := 0; 33672#L477-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 33673#L482-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 34025#L487-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 34026#L492-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 33862#L497-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 33863#L502-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 33958#L507-1 assume !(0 == ~M_E~0); 33687#L686-1 assume !(0 == ~T1_E~0); 33688#L691-1 assume !(0 == ~T2_E~0); 34037#L696-1 assume !(0 == ~T3_E~0); 34038#L701-1 assume !(0 == ~T4_E~0); 33871#L706-1 assume !(0 == ~T5_E~0); 33872#L711-1 assume !(0 == ~T6_E~0); 34155#L716-1 assume !(0 == ~E_M~0); 33825#L721-1 assume !(0 == ~E_1~0); 33826#L726-1 assume !(0 == ~E_2~0); 33593#L731-1 assume !(0 == ~E_3~0); 33594#L736-1 assume !(0 == ~E_4~0); 33677#L741-1 assume !(0 == ~E_5~0); 33678#L746-1 assume !(0 == ~E_6~0); 34032#L751-1 havoc activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 33784#L336 assume !(1 == ~m_pc~0); 33721#L336-2 is_master_triggered_~__retres1~0 := 0; 33722#L347 is_master_triggered_#res := is_master_triggered_~__retres1~0; 33780#L348 activate_threads_#t~ret10 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 33701#L851 assume !(0 != activate_threads_~tmp~1); 33702#L851-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 33703#L355 assume !(1 == ~t1_pc~0); 33996#L355-2 is_transmit1_triggered_~__retres1~1 := 0; 33993#L366 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 33675#L367 activate_threads_#t~ret11 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 33676#L859 assume !(0 != activate_threads_~tmp___0~0); 34146#L859-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 34147#L374 assume !(1 == ~t2_pc~0); 34176#L374-2 is_transmit2_triggered_~__retres1~2 := 0; 34177#L385 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 33932#L386 activate_threads_#t~ret12 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 33933#L867 assume !(0 != activate_threads_~tmp___1~0); 34291#L867-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 34293#L393 assume !(1 == ~t3_pc~0); 34282#L393-2 is_transmit3_triggered_~__retres1~3 := 0; 34301#L404 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 34279#L405 activate_threads_#t~ret13 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 33833#L875 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 33812#L875-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 33813#L412 assume !(1 == ~t4_pc~0); 33846#L412-2 is_transmit4_triggered_~__retres1~4 := 0; 33845#L423 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 33765#L424 activate_threads_#t~ret14 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 33766#L883 assume !(0 != activate_threads_~tmp___3~0); 34048#L883-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 33865#L431 assume !(1 == ~t5_pc~0); 33851#L431-2 is_transmit5_triggered_~__retres1~5 := 0; 33852#L442 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 33864#L443 activate_threads_#t~ret15 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 34029#L891 assume !(0 != activate_threads_~tmp___4~0); 34232#L891-2 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 34091#L450 assume !(1 == ~t6_pc~0); 34092#L450-2 is_transmit6_triggered_~__retres1~6 := 0; 34089#L461 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 34090#L462 activate_threads_#t~ret16 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 34202#L899 assume !(0 != activate_threads_~tmp___5~0); 34237#L899-2 assume !(1 == ~M_E~0); 33589#L764-1 assume !(1 == ~T1_E~0); 33590#L769-1 assume !(1 == ~T2_E~0); 33706#L774-1 assume !(1 == ~T3_E~0); 33707#L779-1 assume !(1 == ~T4_E~0); 34050#L784-1 assume !(1 == ~T5_E~0); 34051#L789-1 assume 1 == ~T6_E~0;~T6_E~0 := 2; 33867#L794-1 assume !(1 == ~E_M~0); 33868#L799-1 assume !(1 == ~E_1~0); 34148#L804-1 assume !(1 == ~E_2~0); 33814#L809-1 assume !(1 == ~E_3~0); 33815#L814-1 assume !(1 == ~E_4~0); 33587#L819-1 assume !(1 == ~E_5~0); 33588#L824-1 assume !(1 == ~E_6~0); 34097#L1055-1 [2018-11-23 01:26:47,474 INFO L796 eck$LassoCheckResult]: Loop: 34097#L1055-1 assume !false; 34804#L1056 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret2, eval_#t~nondet3, eval_~tmp_ndt_1~0, eval_#t~nondet4, eval_~tmp_ndt_2~0, eval_#t~nondet5, eval_~tmp_ndt_3~0, eval_#t~nondet6, eval_~tmp_ndt_4~0, eval_#t~nondet7, eval_~tmp_ndt_5~0, eval_#t~nondet8, eval_~tmp_ndt_6~0, eval_#t~nondet9, eval_~tmp_ndt_7~0, eval_~tmp~0;havoc eval_~tmp~0; 34800#L661 assume !false; 34795#L568 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~7;havoc exists_runnable_thread_~__retres1~7; 34709#L520 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7 := 1; 34704#L557 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~7; 34702#L558 eval_#t~ret2 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret2;havoc eval_#t~ret2; 34699#L572 assume !(0 != eval_~tmp~0); 34700#L676 start_simulation_~kernel_st~0 := 2; 35930#L470-1 start_simulation_~kernel_st~0 := 3; 35823#L686-2 assume 0 == ~M_E~0;~M_E~0 := 1; 35805#L686-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 35785#L691-3 assume !(0 == ~T2_E~0); 35771#L696-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 35558#L701-3 assume !(0 == ~T4_E~0); 35555#L706-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 35553#L711-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 35551#L716-3 assume 0 == ~E_M~0;~E_M~0 := 1; 35549#L721-3 assume 0 == ~E_1~0;~E_1~0 := 1; 35547#L726-3 assume 0 == ~E_2~0;~E_2~0 := 1; 35545#L731-3 assume !(0 == ~E_3~0); 35543#L736-3 assume 0 == ~E_4~0;~E_4~0 := 1; 35540#L741-3 assume !(0 == ~E_5~0); 35538#L746-3 assume 0 == ~E_6~0;~E_6~0 := 1; 35536#L751-3 havoc activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 35534#L336-24 assume 1 == ~m_pc~0; 35531#L337-8 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 35529#L347-8 is_master_triggered_#res := is_master_triggered_~__retres1~0; 35528#L348-8 activate_threads_#t~ret10 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 35527#L851-24 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 35526#L851-26 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 35524#L355-24 assume !(1 == ~t1_pc~0); 35509#L355-26 is_transmit1_triggered_~__retres1~1 := 0; 35502#L366-8 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 35496#L367-8 activate_threads_#t~ret11 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 35489#L859-24 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 35481#L859-26 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 35472#L374-24 assume !(1 == ~t2_pc~0); 35464#L374-26 is_transmit2_triggered_~__retres1~2 := 0; 35457#L385-8 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 35453#L386-8 activate_threads_#t~ret12 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 35448#L867-24 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 35443#L867-26 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 35441#L393-24 assume !(1 == ~t3_pc~0); 35438#L393-26 is_transmit3_triggered_~__retres1~3 := 0; 35436#L404-8 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 35434#L405-8 activate_threads_#t~ret13 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 35431#L875-24 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 35427#L875-26 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 35423#L412-24 assume !(1 == ~t4_pc~0); 35420#L412-26 is_transmit4_triggered_~__retres1~4 := 0; 35417#L423-8 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 35414#L424-8 activate_threads_#t~ret14 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 35411#L883-24 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 35408#L883-26 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 35405#L431-24 assume 1 == ~t5_pc~0; 35401#L432-8 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 35398#L442-8 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 35395#L443-8 activate_threads_#t~ret15 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 35392#L891-24 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 35389#L891-26 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 35386#L450-24 assume !(1 == ~t6_pc~0); 35382#L450-26 is_transmit6_triggered_~__retres1~6 := 0; 35379#L461-8 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 35376#L462-8 activate_threads_#t~ret16 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 35372#L899-24 assume 0 != activate_threads_~tmp___5~0;~t6_st~0 := 0; 35369#L899-26 assume !(1 == ~M_E~0); 35366#L764-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 35363#L769-3 assume !(1 == ~T2_E~0); 35360#L774-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 35357#L779-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 35354#L784-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 35350#L789-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 35347#L794-3 assume 1 == ~E_M~0;~E_M~0 := 2; 35344#L799-3 assume !(1 == ~E_1~0); 35341#L804-3 assume 1 == ~E_2~0;~E_2~0 := 2; 35338#L809-3 assume !(1 == ~E_3~0); 35335#L814-3 assume 1 == ~E_4~0;~E_4~0 := 2; 35331#L819-3 assume 1 == ~E_5~0;~E_5~0 := 2; 35329#L824-3 assume 1 == ~E_6~0;~E_6~0 := 2; 35327#L829-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~7;havoc exists_runnable_thread_~__retres1~7; 35321#L520-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7 := 1; 35314#L557-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~7; 35311#L558-1 start_simulation_#t~ret18 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret18;havoc start_simulation_#t~ret18; 35307#L1074 assume !(0 == start_simulation_~tmp~3); 35304#L1074-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret17, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~7;havoc exists_runnable_thread_~__retres1~7; 34967#L520-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7 := 1; 34961#L557-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~7; 34959#L558-2 stop_simulation_#t~ret17 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret17;havoc stop_simulation_#t~ret17; 34957#L1029 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 34954#L1036 stop_simulation_#res := stop_simulation_~__retres2~0; 34830#L1037 start_simulation_#t~ret19 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret19;havoc start_simulation_#t~ret19; 34829#L1087 assume !(0 != start_simulation_~tmp___0~1); 34097#L1055-1 [2018-11-23 01:26:47,474 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 01:26:47,474 INFO L82 PathProgramCache]: Analyzing trace with hash 81092004, now seen corresponding path program 1 times [2018-11-23 01:26:47,474 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 01:26:47,474 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 01:26:47,475 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 01:26:47,475 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 01:26:47,475 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 01:26:47,479 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 01:26:47,515 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 01:26:47,515 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 01:26:47,516 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2018-11-23 01:26:47,516 INFO L799 eck$LassoCheckResult]: stem already infeasible [2018-11-23 01:26:47,516 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 01:26:47,516 INFO L82 PathProgramCache]: Analyzing trace with hash -290871499, now seen corresponding path program 1 times [2018-11-23 01:26:47,516 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 01:26:47,516 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 01:26:47,517 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 01:26:47,517 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 01:26:47,517 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 01:26:47,521 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 01:26:47,540 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 01:26:47,540 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 01:26:47,540 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-23 01:26:47,541 INFO L811 eck$LassoCheckResult]: loop already infeasible [2018-11-23 01:26:47,542 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-23 01:26:47,542 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-23 01:26:47,542 INFO L87 Difference]: Start difference. First operand 7459 states and 10768 transitions. cyclomatic complexity: 3325 Second operand 3 states. [2018-11-23 01:26:47,592 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 01:26:47,593 INFO L93 Difference]: Finished difference Result 7459 states and 10718 transitions. [2018-11-23 01:26:47,593 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-23 01:26:47,594 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 7459 states and 10718 transitions. [2018-11-23 01:26:47,618 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 7312 [2018-11-23 01:26:47,643 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 7459 states to 7459 states and 10718 transitions. [2018-11-23 01:26:47,644 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 7459 [2018-11-23 01:26:47,648 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 7459 [2018-11-23 01:26:47,648 INFO L73 IsDeterministic]: Start isDeterministic. Operand 7459 states and 10718 transitions. [2018-11-23 01:26:47,655 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-23 01:26:47,655 INFO L705 BuchiCegarLoop]: Abstraction has 7459 states and 10718 transitions. [2018-11-23 01:26:47,660 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 7459 states and 10718 transitions. [2018-11-23 01:26:47,724 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 7459 to 7459. [2018-11-23 01:26:47,724 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 7459 states. [2018-11-23 01:26:47,736 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 7459 states to 7459 states and 10718 transitions. [2018-11-23 01:26:47,737 INFO L728 BuchiCegarLoop]: Abstraction has 7459 states and 10718 transitions. [2018-11-23 01:26:47,737 INFO L608 BuchiCegarLoop]: Abstraction has 7459 states and 10718 transitions. [2018-11-23 01:26:47,737 INFO L442 BuchiCegarLoop]: ======== Iteration 14============ [2018-11-23 01:26:47,737 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 7459 states and 10718 transitions. [2018-11-23 01:26:47,756 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 7312 [2018-11-23 01:26:47,757 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-23 01:26:47,757 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-23 01:26:47,758 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 01:26:47,758 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 01:26:47,758 INFO L794 eck$LassoCheckResult]: Stem: 49120#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0; 49013#L-1 havoc main_#res;havoc main_~__retres1~8;havoc main_~__retres1~8;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 48771#L1018 havoc start_simulation_#t~ret18, start_simulation_#t~ret19, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 48772#L470 assume 1 == ~m_i~0;~m_st~0 := 0; 48601#L477-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 48602#L482-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 48961#L487-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 48962#L492-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 48800#L497-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 48801#L502-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 48893#L507-1 assume !(0 == ~M_E~0); 48616#L686-1 assume !(0 == ~T1_E~0); 48617#L691-1 assume !(0 == ~T2_E~0); 48973#L696-1 assume !(0 == ~T3_E~0); 48974#L701-1 assume !(0 == ~T4_E~0); 48809#L706-1 assume !(0 == ~T5_E~0); 48810#L711-1 assume !(0 == ~T6_E~0); 49098#L716-1 assume !(0 == ~E_M~0); 48756#L721-1 assume !(0 == ~E_1~0); 48757#L726-1 assume !(0 == ~E_2~0); 48518#L731-1 assume !(0 == ~E_3~0); 48519#L736-1 assume !(0 == ~E_4~0); 48606#L741-1 assume !(0 == ~E_5~0); 48607#L746-1 assume !(0 == ~E_6~0); 48968#L751-1 havoc activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 48716#L336 assume !(1 == ~m_pc~0); 48652#L336-2 is_master_triggered_~__retres1~0 := 0; 48653#L347 is_master_triggered_#res := is_master_triggered_~__retres1~0; 48712#L348 activate_threads_#t~ret10 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 48630#L851 assume !(0 != activate_threads_~tmp~1); 48631#L851-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 48633#L355 assume !(1 == ~t1_pc~0); 48933#L355-2 is_transmit1_triggered_~__retres1~1 := 0; 48930#L366 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 48604#L367 activate_threads_#t~ret11 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 48605#L859 assume !(0 != activate_threads_~tmp___0~0); 49091#L859-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 49092#L374 assume !(1 == ~t2_pc~0); 49113#L374-2 is_transmit2_triggered_~__retres1~2 := 0; 49114#L385 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 48870#L386 activate_threads_#t~ret12 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 48871#L867 assume !(0 != activate_threads_~tmp___1~0); 49236#L867-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 49239#L393 assume !(1 == ~t3_pc~0); 49226#L393-2 is_transmit3_triggered_~__retres1~3 := 0; 49253#L404 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 49223#L405 activate_threads_#t~ret13 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 48762#L875 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 48745#L875-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 48746#L412 assume !(1 == ~t4_pc~0); 48784#L412-2 is_transmit4_triggered_~__retres1~4 := 0; 48783#L423 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 48697#L424 activate_threads_#t~ret14 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 48698#L883 assume !(0 != activate_threads_~tmp___3~0); 48985#L883-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 48803#L431 assume !(1 == ~t5_pc~0); 48789#L431-2 is_transmit5_triggered_~__retres1~5 := 0; 48790#L442 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 48802#L443 activate_threads_#t~ret15 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 48965#L891 assume !(0 != activate_threads_~tmp___4~0); 49163#L891-2 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 49034#L450 assume !(1 == ~t6_pc~0); 49035#L450-2 is_transmit6_triggered_~__retres1~6 := 0; 49032#L461 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 49033#L462 activate_threads_#t~ret16 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 49139#L899 assume !(0 != activate_threads_~tmp___5~0); 49169#L899-2 assume !(1 == ~M_E~0); 48514#L764-1 assume !(1 == ~T1_E~0); 48515#L769-1 assume !(1 == ~T2_E~0); 48637#L774-1 assume !(1 == ~T3_E~0); 48638#L779-1 assume !(1 == ~T4_E~0); 48989#L784-1 assume !(1 == ~T5_E~0); 48990#L789-1 assume !(1 == ~T6_E~0); 48805#L794-1 assume !(1 == ~E_M~0); 48806#L799-1 assume !(1 == ~E_1~0); 49093#L804-1 assume !(1 == ~E_2~0); 48747#L809-1 assume !(1 == ~E_3~0); 48748#L814-1 assume !(1 == ~E_4~0); 48512#L819-1 assume !(1 == ~E_5~0); 48513#L824-1 assume !(1 == ~E_6~0); 49041#L1055-1 [2018-11-23 01:26:47,758 INFO L796 eck$LassoCheckResult]: Loop: 49041#L1055-1 assume !false; 50772#L1056 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret2, eval_#t~nondet3, eval_~tmp_ndt_1~0, eval_#t~nondet4, eval_~tmp_ndt_2~0, eval_#t~nondet5, eval_~tmp_ndt_3~0, eval_#t~nondet6, eval_~tmp_ndt_4~0, eval_#t~nondet7, eval_~tmp_ndt_5~0, eval_#t~nondet8, eval_~tmp_ndt_6~0, eval_#t~nondet9, eval_~tmp_ndt_7~0, eval_~tmp~0;havoc eval_~tmp~0; 50771#L661 assume !false; 50770#L568 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~7;havoc exists_runnable_thread_~__retres1~7; 50512#L520 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7 := 1; 50502#L557 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~7; 50494#L558 eval_#t~ret2 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret2;havoc eval_#t~ret2; 50486#L572 assume !(0 != eval_~tmp~0); 50487#L676 start_simulation_~kernel_st~0 := 2; 52176#L470-1 start_simulation_~kernel_st~0 := 3; 52174#L686-2 assume 0 == ~M_E~0;~M_E~0 := 1; 52172#L686-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 52170#L691-3 assume !(0 == ~T2_E~0); 52168#L696-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 52166#L701-3 assume !(0 == ~T4_E~0); 52164#L706-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 52162#L711-3 assume !(0 == ~T6_E~0); 52160#L716-3 assume 0 == ~E_M~0;~E_M~0 := 1; 52158#L721-3 assume 0 == ~E_1~0;~E_1~0 := 1; 52156#L726-3 assume 0 == ~E_2~0;~E_2~0 := 1; 52154#L731-3 assume !(0 == ~E_3~0); 52152#L736-3 assume 0 == ~E_4~0;~E_4~0 := 1; 52140#L741-3 assume !(0 == ~E_5~0); 52133#L746-3 assume 0 == ~E_6~0;~E_6~0 := 1; 52127#L751-3 havoc activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 52120#L336-24 assume 1 == ~m_pc~0; 52115#L337-8 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 52112#L347-8 is_master_triggered_#res := is_master_triggered_~__retres1~0; 51885#L348-8 activate_threads_#t~ret10 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 51842#L851-24 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 51832#L851-26 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 51827#L355-24 assume !(1 == ~t1_pc~0); 51825#L355-26 is_transmit1_triggered_~__retres1~1 := 0; 51820#L366-8 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 51818#L367-8 activate_threads_#t~ret11 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 51816#L859-24 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 51814#L859-26 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 51812#L374-24 assume !(1 == ~t2_pc~0); 51807#L374-26 is_transmit2_triggered_~__retres1~2 := 0; 51804#L385-8 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 51802#L386-8 activate_threads_#t~ret12 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 51800#L867-24 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 51798#L867-26 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 51796#L393-24 assume !(1 == ~t3_pc~0); 51793#L393-26 is_transmit3_triggered_~__retres1~3 := 0; 51791#L404-8 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 51789#L405-8 activate_threads_#t~ret13 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 51787#L875-24 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 51780#L875-26 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 51453#L412-24 assume !(1 == ~t4_pc~0); 51450#L412-26 is_transmit4_triggered_~__retres1~4 := 0; 51448#L423-8 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 51446#L424-8 activate_threads_#t~ret14 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 51444#L883-24 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 51442#L883-26 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 51440#L431-24 assume 1 == ~t5_pc~0; 51437#L432-8 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 51434#L442-8 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 51432#L443-8 activate_threads_#t~ret15 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 51430#L891-24 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 51428#L891-26 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 51426#L450-24 assume !(1 == ~t6_pc~0); 51424#L450-26 is_transmit6_triggered_~__retres1~6 := 0; 51421#L461-8 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 51419#L462-8 activate_threads_#t~ret16 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 51392#L899-24 assume 0 != activate_threads_~tmp___5~0;~t6_st~0 := 0; 50910#L899-26 assume !(1 == ~M_E~0); 50902#L764-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 50900#L769-3 assume !(1 == ~T2_E~0); 50898#L774-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 50894#L779-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 50892#L784-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 50891#L789-3 assume !(1 == ~T6_E~0); 50890#L794-3 assume 1 == ~E_M~0;~E_M~0 := 2; 50882#L799-3 assume !(1 == ~E_1~0); 50880#L804-3 assume 1 == ~E_2~0;~E_2~0 := 2; 50878#L809-3 assume !(1 == ~E_3~0); 50876#L814-3 assume 1 == ~E_4~0;~E_4~0 := 2; 50874#L819-3 assume 1 == ~E_5~0;~E_5~0 := 2; 50872#L824-3 assume 1 == ~E_6~0;~E_6~0 := 2; 50870#L829-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~7;havoc exists_runnable_thread_~__retres1~7; 50862#L520-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7 := 1; 50857#L557-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~7; 50855#L558-1 start_simulation_#t~ret18 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret18;havoc start_simulation_#t~ret18; 50852#L1074 assume !(0 == start_simulation_~tmp~3); 50849#L1074-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret17, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~7;havoc exists_runnable_thread_~__retres1~7; 50844#L520-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7 := 1; 50837#L557-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~7; 50835#L558-2 stop_simulation_#t~ret17 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret17;havoc stop_simulation_#t~ret17; 50833#L1029 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 50831#L1036 stop_simulation_#res := stop_simulation_~__retres2~0; 50829#L1037 start_simulation_#t~ret19 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret19;havoc start_simulation_#t~ret19; 50827#L1087 assume !(0 != start_simulation_~tmp___0~1); 49041#L1055-1 [2018-11-23 01:26:47,758 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 01:26:47,758 INFO L82 PathProgramCache]: Analyzing trace with hash -728254622, now seen corresponding path program 1 times [2018-11-23 01:26:47,759 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 01:26:47,759 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 01:26:47,759 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 01:26:47,759 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 01:26:47,759 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 01:26:47,766 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 01:26:47,880 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 01:26:47,881 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 01:26:47,881 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-11-23 01:26:47,881 INFO L799 eck$LassoCheckResult]: stem already infeasible [2018-11-23 01:26:47,881 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 01:26:47,881 INFO L82 PathProgramCache]: Analyzing trace with hash 158895929, now seen corresponding path program 1 times [2018-11-23 01:26:47,881 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 01:26:47,881 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 01:26:47,882 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 01:26:47,882 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 01:26:47,882 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 01:26:47,887 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 01:26:47,907 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 01:26:47,908 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 01:26:47,908 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-23 01:26:47,908 INFO L811 eck$LassoCheckResult]: loop already infeasible [2018-11-23 01:26:47,908 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-11-23 01:26:47,908 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-11-23 01:26:47,908 INFO L87 Difference]: Start difference. First operand 7459 states and 10718 transitions. cyclomatic complexity: 3275 Second operand 5 states. [2018-11-23 01:26:48,142 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 01:26:48,143 INFO L93 Difference]: Finished difference Result 10143 states and 14621 transitions. [2018-11-23 01:26:48,144 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2018-11-23 01:26:48,144 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 10143 states and 14621 transitions. [2018-11-23 01:26:48,175 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 9948 [2018-11-23 01:26:48,204 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 10143 states to 10143 states and 14621 transitions. [2018-11-23 01:26:48,204 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 10143 [2018-11-23 01:26:48,210 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 10143 [2018-11-23 01:26:48,210 INFO L73 IsDeterministic]: Start isDeterministic. Operand 10143 states and 14621 transitions. [2018-11-23 01:26:48,218 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-23 01:26:48,219 INFO L705 BuchiCegarLoop]: Abstraction has 10143 states and 14621 transitions. [2018-11-23 01:26:48,226 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 10143 states and 14621 transitions. [2018-11-23 01:26:48,295 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 10143 to 7483. [2018-11-23 01:26:48,296 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 7483 states. [2018-11-23 01:26:48,309 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 7483 states to 7483 states and 10637 transitions. [2018-11-23 01:26:48,309 INFO L728 BuchiCegarLoop]: Abstraction has 7483 states and 10637 transitions. [2018-11-23 01:26:48,309 INFO L608 BuchiCegarLoop]: Abstraction has 7483 states and 10637 transitions. [2018-11-23 01:26:48,309 INFO L442 BuchiCegarLoop]: ======== Iteration 15============ [2018-11-23 01:26:48,309 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 7483 states and 10637 transitions. [2018-11-23 01:26:48,329 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 7336 [2018-11-23 01:26:48,329 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-23 01:26:48,329 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-23 01:26:48,330 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 01:26:48,330 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 01:26:48,330 INFO L794 eck$LassoCheckResult]: Stem: 66733#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0; 66625#L-1 havoc main_#res;havoc main_~__retres1~8;havoc main_~__retres1~8;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 66378#L1018 havoc start_simulation_#t~ret18, start_simulation_#t~ret19, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 66379#L470 assume 1 == ~m_i~0;~m_st~0 := 0; 66215#L477-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 66216#L482-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 66574#L487-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 66575#L492-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 66405#L497-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 66406#L502-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 66498#L507-1 assume !(0 == ~M_E~0); 66230#L686-1 assume !(0 == ~T1_E~0); 66231#L691-1 assume !(0 == ~T2_E~0); 66589#L696-1 assume !(0 == ~T3_E~0); 66590#L701-1 assume !(0 == ~T4_E~0); 66414#L706-1 assume !(0 == ~T5_E~0); 66415#L711-1 assume !(0 == ~T6_E~0); 66712#L716-1 assume !(0 == ~E_M~0); 66367#L721-1 assume !(0 == ~E_1~0); 66368#L726-1 assume !(0 == ~E_2~0); 66133#L731-1 assume !(0 == ~E_3~0); 66134#L736-1 assume !(0 == ~E_4~0); 66221#L741-1 assume !(0 == ~E_5~0); 66222#L746-1 assume !(0 == ~E_6~0); 66583#L751-1 havoc activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 66327#L336 assume !(1 == ~m_pc~0); 66264#L336-2 is_master_triggered_~__retres1~0 := 0; 66265#L347 is_master_triggered_#res := is_master_triggered_~__retres1~0; 66323#L348 activate_threads_#t~ret10 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 66242#L851 assume !(0 != activate_threads_~tmp~1); 66243#L851-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 66245#L355 assume !(1 == ~t1_pc~0); 66541#L355-2 is_transmit1_triggered_~__retres1~1 := 0; 66537#L366 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 66219#L367 activate_threads_#t~ret11 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 66220#L859 assume !(0 != activate_threads_~tmp___0~0); 66706#L859-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 66707#L374 assume !(1 == ~t2_pc~0); 66726#L374-2 is_transmit2_triggered_~__retres1~2 := 0; 66727#L385 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 66474#L386 activate_threads_#t~ret12 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 66475#L867 assume !(0 != activate_threads_~tmp___1~0); 66832#L867-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 66835#L393 assume !(1 == ~t3_pc~0); 66822#L393-2 is_transmit3_triggered_~__retres1~3 := 0; 66851#L404 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 66819#L405 activate_threads_#t~ret13 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 66372#L875 assume !(0 != activate_threads_~tmp___2~0); 66356#L875-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 66357#L412 assume !(1 == ~t4_pc~0); 66388#L412-2 is_transmit4_triggered_~__retres1~4 := 0; 66387#L423 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 66308#L424 activate_threads_#t~ret14 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 66309#L883 assume !(0 != activate_threads_~tmp___3~0); 66600#L883-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 66408#L431 assume !(1 == ~t5_pc~0); 66393#L431-2 is_transmit5_triggered_~__retres1~5 := 0; 66394#L442 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 66407#L443 activate_threads_#t~ret15 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 66578#L891 assume !(0 != activate_threads_~tmp___4~0); 66769#L891-2 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 66646#L450 assume !(1 == ~t6_pc~0); 66647#L450-2 is_transmit6_triggered_~__retres1~6 := 0; 66644#L461 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 66645#L462 activate_threads_#t~ret16 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 66750#L899 assume !(0 != activate_threads_~tmp___5~0); 66776#L899-2 assume !(1 == ~M_E~0); 66129#L764-1 assume !(1 == ~T1_E~0); 66130#L769-1 assume !(1 == ~T2_E~0); 66248#L774-1 assume !(1 == ~T3_E~0); 66249#L779-1 assume !(1 == ~T4_E~0); 66601#L784-1 assume !(1 == ~T5_E~0); 66602#L789-1 assume !(1 == ~T6_E~0); 66410#L794-1 assume !(1 == ~E_M~0); 66411#L799-1 assume !(1 == ~E_1~0); 66708#L804-1 assume !(1 == ~E_2~0); 66358#L809-1 assume !(1 == ~E_3~0); 66359#L814-1 assume !(1 == ~E_4~0); 66127#L819-1 assume !(1 == ~E_5~0); 66128#L824-1 assume !(1 == ~E_6~0); 66655#L1055-1 [2018-11-23 01:26:48,331 INFO L796 eck$LassoCheckResult]: Loop: 66655#L1055-1 assume !false; 68114#L1056 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret2, eval_#t~nondet3, eval_~tmp_ndt_1~0, eval_#t~nondet4, eval_~tmp_ndt_2~0, eval_#t~nondet5, eval_~tmp_ndt_3~0, eval_#t~nondet6, eval_~tmp_ndt_4~0, eval_#t~nondet7, eval_~tmp_ndt_5~0, eval_#t~nondet8, eval_~tmp_ndt_6~0, eval_#t~nondet9, eval_~tmp_ndt_7~0, eval_~tmp~0;havoc eval_~tmp~0; 68104#L661 assume !false; 68105#L568 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~7;havoc exists_runnable_thread_~__retres1~7; 67939#L520 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7 := 1; 67927#L557 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~7; 67921#L558 eval_#t~ret2 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret2;havoc eval_#t~ret2; 67913#L572 assume !(0 != eval_~tmp~0); 67914#L676 start_simulation_~kernel_st~0 := 2; 68406#L470-1 start_simulation_~kernel_st~0 := 3; 68400#L686-2 assume 0 == ~M_E~0;~M_E~0 := 1; 68394#L686-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 68371#L691-3 assume !(0 == ~T2_E~0); 68368#L696-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 68366#L701-3 assume !(0 == ~T4_E~0); 68364#L706-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 68362#L711-3 assume !(0 == ~T6_E~0); 68360#L716-3 assume 0 == ~E_M~0;~E_M~0 := 1; 68358#L721-3 assume 0 == ~E_1~0;~E_1~0 := 1; 68356#L726-3 assume 0 == ~E_2~0;~E_2~0 := 1; 68354#L731-3 assume !(0 == ~E_3~0); 68352#L736-3 assume 0 == ~E_4~0;~E_4~0 := 1; 68350#L741-3 assume !(0 == ~E_5~0); 68348#L746-3 assume 0 == ~E_6~0;~E_6~0 := 1; 68346#L751-3 havoc activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 68344#L336-24 assume 1 == ~m_pc~0; 68341#L337-8 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 68338#L347-8 is_master_triggered_#res := is_master_triggered_~__retres1~0; 68336#L348-8 activate_threads_#t~ret10 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 68334#L851-24 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 68332#L851-26 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 68330#L355-24 assume !(1 == ~t1_pc~0); 68328#L355-26 is_transmit1_triggered_~__retres1~1 := 0; 68326#L366-8 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 68324#L367-8 activate_threads_#t~ret11 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 68322#L859-24 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 68320#L859-26 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 68318#L374-24 assume !(1 == ~t2_pc~0); 68316#L374-26 is_transmit2_triggered_~__retres1~2 := 0; 68314#L385-8 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 68311#L386-8 activate_threads_#t~ret12 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 68309#L867-24 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 68307#L867-26 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 68305#L393-24 assume !(1 == ~t3_pc~0); 68302#L393-26 is_transmit3_triggered_~__retres1~3 := 0; 68300#L404-8 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 68298#L405-8 activate_threads_#t~ret13 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 68296#L875-24 assume !(0 != activate_threads_~tmp___2~0); 68294#L875-26 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 68292#L412-24 assume !(1 == ~t4_pc~0); 68290#L412-26 is_transmit4_triggered_~__retres1~4 := 0; 68288#L423-8 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 68286#L424-8 activate_threads_#t~ret14 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 68284#L883-24 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 68282#L883-26 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 68280#L431-24 assume !(1 == ~t5_pc~0); 68277#L431-26 is_transmit5_triggered_~__retres1~5 := 0; 68274#L442-8 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 68272#L443-8 activate_threads_#t~ret15 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 68269#L891-24 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 68267#L891-26 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 68265#L450-24 assume !(1 == ~t6_pc~0); 68263#L450-26 is_transmit6_triggered_~__retres1~6 := 0; 68252#L461-8 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 68246#L462-8 activate_threads_#t~ret16 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 68240#L899-24 assume 0 != activate_threads_~tmp___5~0;~t6_st~0 := 0; 68233#L899-26 assume !(1 == ~M_E~0); 68228#L764-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 68225#L769-3 assume !(1 == ~T2_E~0); 68224#L774-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 68223#L779-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 68222#L784-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 68221#L789-3 assume !(1 == ~T6_E~0); 68220#L794-3 assume 1 == ~E_M~0;~E_M~0 := 2; 68218#L799-3 assume !(1 == ~E_1~0); 68215#L804-3 assume 1 == ~E_2~0;~E_2~0 := 2; 68213#L809-3 assume !(1 == ~E_3~0); 68211#L814-3 assume 1 == ~E_4~0;~E_4~0 := 2; 68209#L819-3 assume 1 == ~E_5~0;~E_5~0 := 2; 68207#L824-3 assume 1 == ~E_6~0;~E_6~0 := 2; 68205#L829-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~7;havoc exists_runnable_thread_~__retres1~7; 68182#L520-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7 := 1; 68177#L557-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~7; 68175#L558-1 start_simulation_#t~ret18 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret18;havoc start_simulation_#t~ret18; 68172#L1074 assume !(0 == start_simulation_~tmp~3); 68169#L1074-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret17, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~7;havoc exists_runnable_thread_~__retres1~7; 68146#L520-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7 := 1; 68139#L557-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~7; 68137#L558-2 stop_simulation_#t~ret17 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret17;havoc stop_simulation_#t~ret17; 68135#L1029 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 68133#L1036 stop_simulation_#res := stop_simulation_~__retres2~0; 68131#L1037 start_simulation_#t~ret19 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret19;havoc start_simulation_#t~ret19; 68129#L1087 assume !(0 != start_simulation_~tmp___0~1); 66655#L1055-1 [2018-11-23 01:26:48,331 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 01:26:48,331 INFO L82 PathProgramCache]: Analyzing trace with hash -800641180, now seen corresponding path program 1 times [2018-11-23 01:26:48,331 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 01:26:48,331 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 01:26:48,332 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 01:26:48,332 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 01:26:48,332 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 01:26:48,337 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-23 01:26:48,342 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-23 01:26:48,377 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 01:26:48,377 INFO L82 PathProgramCache]: Analyzing trace with hash -1684477994, now seen corresponding path program 1 times [2018-11-23 01:26:48,377 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 01:26:48,377 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 01:26:48,378 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 01:26:48,378 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 01:26:48,378 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 01:26:48,383 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 01:26:48,415 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 01:26:48,415 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 01:26:48,415 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-23 01:26:48,415 INFO L811 eck$LassoCheckResult]: loop already infeasible [2018-11-23 01:26:48,416 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-23 01:26:48,416 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-23 01:26:48,416 INFO L87 Difference]: Start difference. First operand 7483 states and 10637 transitions. cyclomatic complexity: 3170 Second operand 3 states. [2018-11-23 01:26:48,462 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 01:26:48,463 INFO L93 Difference]: Finished difference Result 8518 states and 12077 transitions. [2018-11-23 01:26:48,465 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-23 01:26:48,465 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 8518 states and 12077 transitions. [2018-11-23 01:26:48,485 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 8312 [2018-11-23 01:26:48,502 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 8518 states to 8518 states and 12077 transitions. [2018-11-23 01:26:48,502 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 8518 [2018-11-23 01:26:48,506 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 8518 [2018-11-23 01:26:48,507 INFO L73 IsDeterministic]: Start isDeterministic. Operand 8518 states and 12077 transitions. [2018-11-23 01:26:48,511 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-23 01:26:48,511 INFO L705 BuchiCegarLoop]: Abstraction has 8518 states and 12077 transitions. [2018-11-23 01:26:48,516 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 8518 states and 12077 transitions. [2018-11-23 01:26:48,595 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 8518 to 8518. [2018-11-23 01:26:48,595 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 8518 states. [2018-11-23 01:26:48,603 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 8518 states to 8518 states and 12077 transitions. [2018-11-23 01:26:48,604 INFO L728 BuchiCegarLoop]: Abstraction has 8518 states and 12077 transitions. [2018-11-23 01:26:48,604 INFO L608 BuchiCegarLoop]: Abstraction has 8518 states and 12077 transitions. [2018-11-23 01:26:48,604 INFO L442 BuchiCegarLoop]: ======== Iteration 16============ [2018-11-23 01:26:48,604 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 8518 states and 12077 transitions. [2018-11-23 01:26:48,618 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 8312 [2018-11-23 01:26:48,618 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-23 01:26:48,618 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-23 01:26:48,619 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 01:26:48,619 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 01:26:48,619 INFO L794 eck$LassoCheckResult]: Stem: 82730#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0; 82622#L-1 havoc main_#res;havoc main_~__retres1~8;havoc main_~__retres1~8;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 82384#L1018 havoc start_simulation_#t~ret18, start_simulation_#t~ret19, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 82385#L470 assume 1 == ~m_i~0;~m_st~0 := 0; 82220#L477-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 82221#L482-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 82573#L487-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 82574#L492-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 82409#L497-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 82410#L502-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 82503#L507-1 assume 0 == ~M_E~0;~M_E~0 := 1; 82504#L686-1 assume !(0 == ~T1_E~0); 82829#L691-1 assume !(0 == ~T2_E~0); 82830#L696-1 assume !(0 == ~T3_E~0); 82859#L701-1 assume !(0 == ~T4_E~0); 82418#L706-1 assume !(0 == ~T5_E~0); 82419#L711-1 assume !(0 == ~T6_E~0); 82900#L716-1 assume !(0 == ~E_M~0); 82371#L721-1 assume !(0 == ~E_1~0); 82372#L726-1 assume !(0 == ~E_2~0); 82140#L731-1 assume !(0 == ~E_3~0); 82141#L736-1 assume !(0 == ~E_4~0); 82226#L741-1 assume !(0 == ~E_5~0); 82227#L746-1 assume !(0 == ~E_6~0); 82580#L751-1 havoc activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 82332#L336 assume !(1 == ~m_pc~0); 82269#L336-2 is_master_triggered_~__retres1~0 := 0; 82270#L347 is_master_triggered_#res := is_master_triggered_~__retres1~0; 82328#L348 activate_threads_#t~ret10 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 82800#L851 assume !(0 != activate_threads_~tmp~1); 82250#L851-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 82251#L355 assume !(1 == ~t1_pc~0); 82541#L355-2 is_transmit1_triggered_~__retres1~1 := 0; 82889#L366 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 82888#L367 activate_threads_#t~ret11 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 82887#L859 assume !(0 != activate_threads_~tmp___0~0); 82886#L859-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 82885#L374 assume !(1 == ~t2_pc~0); 82884#L374-2 is_transmit2_triggered_~__retres1~2 := 0; 82883#L385 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 82882#L386 activate_threads_#t~ret12 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 82835#L867 assume !(0 != activate_threads_~tmp___1~0); 82836#L867-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 82851#L393 assume !(1 == ~t3_pc~0); 82823#L393-2 is_transmit3_triggered_~__retres1~3 := 0; 82849#L404 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 82820#L405 activate_threads_#t~ret13 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 82379#L875 assume !(0 != activate_threads_~tmp___2~0); 82358#L875-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 82359#L412 assume !(1 == ~t4_pc~0); 82393#L412-2 is_transmit4_triggered_~__retres1~4 := 0; 82392#L423 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 82313#L424 activate_threads_#t~ret14 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 82314#L883 assume !(0 != activate_threads_~tmp___3~0); 82597#L883-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 82412#L431 assume !(1 == ~t5_pc~0); 82398#L431-2 is_transmit5_triggered_~__retres1~5 := 0; 82399#L442 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 82411#L443 activate_threads_#t~ret15 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 82577#L891 assume !(0 != activate_threads_~tmp___4~0); 82772#L891-2 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 82642#L450 assume !(1 == ~t6_pc~0); 82643#L450-2 is_transmit6_triggered_~__retres1~6 := 0; 82640#L461 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 82641#L462 activate_threads_#t~ret16 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 82747#L899 assume !(0 != activate_threads_~tmp___5~0); 82776#L899-2 assume 1 == ~M_E~0;~M_E~0 := 2; 82136#L764-1 assume !(1 == ~T1_E~0); 82137#L769-1 assume !(1 == ~T2_E~0); 82254#L774-1 assume !(1 == ~T3_E~0); 82255#L779-1 assume !(1 == ~T4_E~0); 82601#L784-1 assume !(1 == ~T5_E~0); 82602#L789-1 assume !(1 == ~T6_E~0); 82414#L794-1 assume !(1 == ~E_M~0); 82415#L799-1 assume !(1 == ~E_1~0); 82700#L804-1 assume !(1 == ~E_2~0); 82360#L809-1 assume !(1 == ~E_3~0); 82361#L814-1 assume !(1 == ~E_4~0); 82134#L819-1 assume !(1 == ~E_5~0); 82135#L824-1 assume !(1 == ~E_6~0); 82648#L1055-1 [2018-11-23 01:26:48,619 INFO L796 eck$LassoCheckResult]: Loop: 82648#L1055-1 assume !false; 86928#L1056 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret2, eval_#t~nondet3, eval_~tmp_ndt_1~0, eval_#t~nondet4, eval_~tmp_ndt_2~0, eval_#t~nondet5, eval_~tmp_ndt_3~0, eval_#t~nondet6, eval_~tmp_ndt_4~0, eval_#t~nondet7, eval_~tmp_ndt_5~0, eval_#t~nondet8, eval_~tmp_ndt_6~0, eval_#t~nondet9, eval_~tmp_ndt_7~0, eval_~tmp~0;havoc eval_~tmp~0; 86792#L661 assume !false; 86925#L568 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~7;havoc exists_runnable_thread_~__retres1~7; 86914#L520 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7 := 1; 86909#L557 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~7; 86907#L558 eval_#t~ret2 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret2;havoc eval_#t~ret2; 86904#L572 assume !(0 != eval_~tmp~0); 86905#L676 start_simulation_~kernel_st~0 := 2; 87118#L470-1 start_simulation_~kernel_st~0 := 3; 87115#L686-2 assume 0 == ~M_E~0;~M_E~0 := 1; 87113#L686-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 87111#L691-3 assume !(0 == ~T2_E~0); 87109#L696-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 87107#L701-3 assume !(0 == ~T4_E~0); 87105#L706-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 87103#L711-3 assume !(0 == ~T6_E~0); 87102#L716-3 assume 0 == ~E_M~0;~E_M~0 := 1; 87101#L721-3 assume 0 == ~E_1~0;~E_1~0 := 1; 87100#L726-3 assume 0 == ~E_2~0;~E_2~0 := 1; 87099#L731-3 assume !(0 == ~E_3~0); 87098#L736-3 assume 0 == ~E_4~0;~E_4~0 := 1; 87097#L741-3 assume !(0 == ~E_5~0); 87096#L746-3 assume 0 == ~E_6~0;~E_6~0 := 1; 87095#L751-3 havoc activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 87093#L336-24 assume 1 == ~m_pc~0; 87089#L337-8 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 87087#L347-8 is_master_triggered_#res := is_master_triggered_~__retres1~0; 87085#L348-8 activate_threads_#t~ret10 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 87083#L851-24 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 87081#L851-26 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 87079#L355-24 assume !(1 == ~t1_pc~0); 87077#L355-26 is_transmit1_triggered_~__retres1~1 := 0; 87075#L366-8 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 87073#L367-8 activate_threads_#t~ret11 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 87071#L859-24 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 87069#L859-26 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 87067#L374-24 assume !(1 == ~t2_pc~0); 87065#L374-26 is_transmit2_triggered_~__retres1~2 := 0; 87063#L385-8 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 87061#L386-8 activate_threads_#t~ret12 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 87059#L867-24 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 87057#L867-26 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 87054#L393-24 assume !(1 == ~t3_pc~0); 87051#L393-26 is_transmit3_triggered_~__retres1~3 := 0; 87049#L404-8 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 87047#L405-8 activate_threads_#t~ret13 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 87045#L875-24 assume !(0 != activate_threads_~tmp___2~0); 87043#L875-26 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 87041#L412-24 assume !(1 == ~t4_pc~0); 87039#L412-26 is_transmit4_triggered_~__retres1~4 := 0; 87037#L423-8 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 87035#L424-8 activate_threads_#t~ret14 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 87033#L883-24 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 87031#L883-26 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 87029#L431-24 assume 1 == ~t5_pc~0; 87025#L432-8 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 87023#L442-8 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 87021#L443-8 activate_threads_#t~ret15 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 87019#L891-24 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 87017#L891-26 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 87015#L450-24 assume !(1 == ~t6_pc~0); 87013#L450-26 is_transmit6_triggered_~__retres1~6 := 0; 87011#L461-8 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 87009#L462-8 activate_threads_#t~ret16 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 87007#L899-24 assume 0 != activate_threads_~tmp___5~0;~t6_st~0 := 0; 87005#L899-26 assume 1 == ~M_E~0;~M_E~0 := 2; 87002#L764-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 87000#L769-3 assume !(1 == ~T2_E~0); 86998#L774-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 86996#L779-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 86994#L784-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 86992#L789-3 assume !(1 == ~T6_E~0); 86990#L794-3 assume 1 == ~E_M~0;~E_M~0 := 2; 86988#L799-3 assume !(1 == ~E_1~0); 86986#L804-3 assume 1 == ~E_2~0;~E_2~0 := 2; 86984#L809-3 assume !(1 == ~E_3~0); 86982#L814-3 assume 1 == ~E_4~0;~E_4~0 := 2; 86980#L819-3 assume 1 == ~E_5~0;~E_5~0 := 2; 86979#L824-3 assume 1 == ~E_6~0;~E_6~0 := 2; 86978#L829-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~7;havoc exists_runnable_thread_~__retres1~7; 86967#L520-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7 := 1; 86962#L557-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~7; 86960#L558-1 start_simulation_#t~ret18 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret18;havoc start_simulation_#t~ret18; 86957#L1074 assume !(0 == start_simulation_~tmp~3); 86953#L1074-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret17, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~7;havoc exists_runnable_thread_~__retres1~7; 86948#L520-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7 := 1; 86941#L557-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~7; 86939#L558-2 stop_simulation_#t~ret17 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret17;havoc stop_simulation_#t~ret17; 86937#L1029 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 86935#L1036 stop_simulation_#res := stop_simulation_~__retres2~0; 86933#L1037 start_simulation_#t~ret19 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret19;havoc start_simulation_#t~ret19; 86931#L1087 assume !(0 != start_simulation_~tmp___0~1); 82648#L1055-1 [2018-11-23 01:26:48,620 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 01:26:48,620 INFO L82 PathProgramCache]: Analyzing trace with hash -1697981720, now seen corresponding path program 1 times [2018-11-23 01:26:48,620 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 01:26:48,620 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 01:26:48,620 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 01:26:48,621 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 01:26:48,621 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 01:26:48,624 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 01:26:48,651 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 01:26:48,651 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 01:26:48,652 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2018-11-23 01:26:48,652 INFO L799 eck$LassoCheckResult]: stem already infeasible [2018-11-23 01:26:48,652 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 01:26:48,652 INFO L82 PathProgramCache]: Analyzing trace with hash 163940597, now seen corresponding path program 1 times [2018-11-23 01:26:48,652 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 01:26:48,652 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 01:26:48,653 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 01:26:48,653 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 01:26:48,653 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 01:26:48,657 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 01:26:48,671 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 01:26:48,671 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 01:26:48,671 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-23 01:26:48,672 INFO L811 eck$LassoCheckResult]: loop already infeasible [2018-11-23 01:26:48,672 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-23 01:26:48,672 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-23 01:26:48,672 INFO L87 Difference]: Start difference. First operand 8518 states and 12077 transitions. cyclomatic complexity: 3575 Second operand 3 states. [2018-11-23 01:26:48,695 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 01:26:48,695 INFO L93 Difference]: Finished difference Result 7483 states and 10587 transitions. [2018-11-23 01:26:48,696 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-23 01:26:48,697 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 7483 states and 10587 transitions. [2018-11-23 01:26:48,711 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 7336 [2018-11-23 01:26:48,723 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 7483 states to 7483 states and 10587 transitions. [2018-11-23 01:26:48,724 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 7483 [2018-11-23 01:26:48,727 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 7483 [2018-11-23 01:26:48,727 INFO L73 IsDeterministic]: Start isDeterministic. Operand 7483 states and 10587 transitions. [2018-11-23 01:26:48,731 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-23 01:26:48,731 INFO L705 BuchiCegarLoop]: Abstraction has 7483 states and 10587 transitions. [2018-11-23 01:26:48,736 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 7483 states and 10587 transitions. [2018-11-23 01:26:48,773 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 7483 to 7483. [2018-11-23 01:26:48,774 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 7483 states. [2018-11-23 01:26:48,780 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 7483 states to 7483 states and 10587 transitions. [2018-11-23 01:26:48,781 INFO L728 BuchiCegarLoop]: Abstraction has 7483 states and 10587 transitions. [2018-11-23 01:26:48,781 INFO L608 BuchiCegarLoop]: Abstraction has 7483 states and 10587 transitions. [2018-11-23 01:26:48,781 INFO L442 BuchiCegarLoop]: ======== Iteration 17============ [2018-11-23 01:26:48,781 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 7483 states and 10587 transitions. [2018-11-23 01:26:48,794 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 7336 [2018-11-23 01:26:48,794 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-23 01:26:48,794 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-23 01:26:48,795 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 01:26:48,795 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 01:26:48,795 INFO L794 eck$LassoCheckResult]: Stem: 98729#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0; 98616#L-1 havoc main_#res;havoc main_~__retres1~8;havoc main_~__retres1~8;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 98392#L1018 havoc start_simulation_#t~ret18, start_simulation_#t~ret19, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 98393#L470 assume 1 == ~m_i~0;~m_st~0 := 0; 98232#L477-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 98233#L482-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 98573#L487-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 98574#L492-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 98417#L497-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 98418#L502-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 98508#L507-1 assume !(0 == ~M_E~0); 98247#L686-1 assume !(0 == ~T1_E~0); 98248#L691-1 assume !(0 == ~T2_E~0); 98585#L696-1 assume !(0 == ~T3_E~0); 98586#L701-1 assume !(0 == ~T4_E~0); 98426#L706-1 assume !(0 == ~T5_E~0); 98427#L711-1 assume !(0 == ~T6_E~0); 98700#L716-1 assume !(0 == ~E_M~0); 98382#L721-1 assume !(0 == ~E_1~0); 98383#L726-1 assume !(0 == ~E_2~0); 98148#L731-1 assume !(0 == ~E_3~0); 98149#L736-1 assume !(0 == ~E_4~0); 98237#L741-1 assume !(0 == ~E_5~0); 98238#L746-1 assume !(0 == ~E_6~0); 98580#L751-1 havoc activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 98344#L336 assume !(1 == ~m_pc~0); 98280#L336-2 is_master_triggered_~__retres1~0 := 0; 98281#L347 is_master_triggered_#res := is_master_triggered_~__retres1~0; 98340#L348 activate_threads_#t~ret10 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 98260#L851 assume !(0 != activate_threads_~tmp~1); 98261#L851-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 98262#L355 assume !(1 == ~t1_pc~0); 98545#L355-2 is_transmit1_triggered_~__retres1~1 := 0; 98542#L366 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 98235#L367 activate_threads_#t~ret11 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 98236#L859 assume !(0 != activate_threads_~tmp___0~0); 98692#L859-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 98693#L374 assume !(1 == ~t2_pc~0); 98721#L374-2 is_transmit2_triggered_~__retres1~2 := 0; 98722#L385 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 98485#L386 activate_threads_#t~ret12 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 98486#L867 assume !(0 != activate_threads_~tmp___1~0); 98831#L867-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 98833#L393 assume !(1 == ~t3_pc~0); 98823#L393-2 is_transmit3_triggered_~__retres1~3 := 0; 98842#L404 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 98820#L405 activate_threads_#t~ret13 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 98389#L875 assume !(0 != activate_threads_~tmp___2~0); 98371#L875-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 98372#L412 assume !(1 == ~t4_pc~0); 98401#L412-2 is_transmit4_triggered_~__retres1~4 := 0; 98400#L423 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 98325#L424 activate_threads_#t~ret14 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 98326#L883 assume !(0 != activate_threads_~tmp___3~0); 98596#L883-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 98420#L431 assume !(1 == ~t5_pc~0); 98406#L431-2 is_transmit5_triggered_~__retres1~5 := 0; 98407#L442 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 98419#L443 activate_threads_#t~ret15 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 98577#L891 assume !(0 != activate_threads_~tmp___4~0); 98776#L891-2 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 98637#L450 assume !(1 == ~t6_pc~0); 98638#L450-2 is_transmit6_triggered_~__retres1~6 := 0; 98635#L461 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 98636#L462 activate_threads_#t~ret16 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 98747#L899 assume !(0 != activate_threads_~tmp___5~0); 98780#L899-2 assume !(1 == ~M_E~0); 98144#L764-1 assume !(1 == ~T1_E~0); 98145#L769-1 assume !(1 == ~T2_E~0); 98265#L774-1 assume !(1 == ~T3_E~0); 98266#L779-1 assume !(1 == ~T4_E~0); 98597#L784-1 assume !(1 == ~T5_E~0); 98598#L789-1 assume !(1 == ~T6_E~0); 98422#L794-1 assume !(1 == ~E_M~0); 98423#L799-1 assume !(1 == ~E_1~0); 98694#L804-1 assume !(1 == ~E_2~0); 98373#L809-1 assume !(1 == ~E_3~0); 98374#L814-1 assume !(1 == ~E_4~0); 98142#L819-1 assume !(1 == ~E_5~0); 98143#L824-1 assume !(1 == ~E_6~0); 98643#L1055-1 [2018-11-23 01:26:48,796 INFO L796 eck$LassoCheckResult]: Loop: 98643#L1055-1 assume !false; 99837#L1056 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret2, eval_#t~nondet3, eval_~tmp_ndt_1~0, eval_#t~nondet4, eval_~tmp_ndt_2~0, eval_#t~nondet5, eval_~tmp_ndt_3~0, eval_#t~nondet6, eval_~tmp_ndt_4~0, eval_#t~nondet7, eval_~tmp_ndt_5~0, eval_#t~nondet8, eval_~tmp_ndt_6~0, eval_#t~nondet9, eval_~tmp_ndt_7~0, eval_~tmp~0;havoc eval_~tmp~0; 99835#L661 assume !false; 99832#L568 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~7;havoc exists_runnable_thread_~__retres1~7; 99783#L520 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7 := 1; 99778#L557 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~7; 99776#L558 eval_#t~ret2 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret2;havoc eval_#t~ret2; 99773#L572 assume !(0 != eval_~tmp~0); 99774#L676 start_simulation_~kernel_st~0 := 2; 100560#L470-1 start_simulation_~kernel_st~0 := 3; 100558#L686-2 assume !(0 == ~M_E~0); 100556#L686-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 100554#L691-3 assume !(0 == ~T2_E~0); 100552#L696-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 100550#L701-3 assume !(0 == ~T4_E~0); 100548#L706-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 100546#L711-3 assume !(0 == ~T6_E~0); 100524#L716-3 assume 0 == ~E_M~0;~E_M~0 := 1; 100519#L721-3 assume 0 == ~E_1~0;~E_1~0 := 1; 100518#L726-3 assume 0 == ~E_2~0;~E_2~0 := 1; 100510#L731-3 assume !(0 == ~E_3~0); 100502#L736-3 assume 0 == ~E_4~0;~E_4~0 := 1; 100501#L741-3 assume !(0 == ~E_5~0); 100500#L746-3 assume 0 == ~E_6~0;~E_6~0 := 1; 100499#L751-3 havoc activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 100498#L336-24 assume 1 == ~m_pc~0; 100451#L337-8 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 100449#L347-8 is_master_triggered_#res := is_master_triggered_~__retres1~0; 100447#L348-8 activate_threads_#t~ret10 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 100445#L851-24 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 100443#L851-26 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 100441#L355-24 assume !(1 == ~t1_pc~0); 100439#L355-26 is_transmit1_triggered_~__retres1~1 := 0; 100437#L366-8 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 100435#L367-8 activate_threads_#t~ret11 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 100433#L859-24 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 100425#L859-26 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 100423#L374-24 assume !(1 == ~t2_pc~0); 100421#L374-26 is_transmit2_triggered_~__retres1~2 := 0; 100419#L385-8 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 100417#L386-8 activate_threads_#t~ret12 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 100415#L867-24 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 100413#L867-26 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 100411#L393-24 assume !(1 == ~t3_pc~0); 100409#L393-26 is_transmit3_triggered_~__retres1~3 := 0; 100384#L404-8 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 100379#L405-8 activate_threads_#t~ret13 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 100378#L875-24 assume !(0 != activate_threads_~tmp___2~0); 100377#L875-26 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 100376#L412-24 assume !(1 == ~t4_pc~0); 100375#L412-26 is_transmit4_triggered_~__retres1~4 := 0; 100365#L423-8 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 100361#L424-8 activate_threads_#t~ret14 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 100315#L883-24 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 100312#L883-26 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 100310#L431-24 assume 1 == ~t5_pc~0; 100307#L432-8 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 100304#L442-8 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 100302#L443-8 activate_threads_#t~ret15 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 100300#L891-24 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 100298#L891-26 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 100296#L450-24 assume !(1 == ~t6_pc~0); 100294#L450-26 is_transmit6_triggered_~__retres1~6 := 0; 100291#L461-8 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 100289#L462-8 activate_threads_#t~ret16 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 100287#L899-24 assume 0 != activate_threads_~tmp___5~0;~t6_st~0 := 0; 100285#L899-26 assume !(1 == ~M_E~0); 100283#L764-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 100281#L769-3 assume !(1 == ~T2_E~0); 100279#L774-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 100268#L779-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 100262#L784-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 100256#L789-3 assume !(1 == ~T6_E~0); 100250#L794-3 assume 1 == ~E_M~0;~E_M~0 := 2; 100243#L799-3 assume !(1 == ~E_1~0); 100237#L804-3 assume 1 == ~E_2~0;~E_2~0 := 2; 100231#L809-3 assume !(1 == ~E_3~0); 100226#L814-3 assume 1 == ~E_4~0;~E_4~0 := 2; 100221#L819-3 assume 1 == ~E_5~0;~E_5~0 := 2; 100216#L824-3 assume 1 == ~E_6~0;~E_6~0 := 2; 100190#L829-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~7;havoc exists_runnable_thread_~__retres1~7; 99899#L520-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7 := 1; 99894#L557-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~7; 99892#L558-1 start_simulation_#t~ret18 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret18;havoc start_simulation_#t~ret18; 99889#L1074 assume !(0 == start_simulation_~tmp~3); 99886#L1074-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret17, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~7;havoc exists_runnable_thread_~__retres1~7; 99881#L520-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7 := 1; 99874#L557-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~7; 99872#L558-2 stop_simulation_#t~ret17 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret17;havoc stop_simulation_#t~ret17; 99870#L1029 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 99868#L1036 stop_simulation_#res := stop_simulation_~__retres2~0; 99866#L1037 start_simulation_#t~ret19 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret19;havoc start_simulation_#t~ret19; 99863#L1087 assume !(0 != start_simulation_~tmp___0~1); 98643#L1055-1 [2018-11-23 01:26:48,796 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 01:26:48,796 INFO L82 PathProgramCache]: Analyzing trace with hash -800641180, now seen corresponding path program 2 times [2018-11-23 01:26:48,796 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 01:26:48,796 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 01:26:48,797 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 01:26:48,797 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 01:26:48,797 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 01:26:48,801 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-23 01:26:48,806 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-23 01:26:48,821 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 01:26:48,821 INFO L82 PathProgramCache]: Analyzing trace with hash -882942471, now seen corresponding path program 1 times [2018-11-23 01:26:48,821 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 01:26:48,821 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 01:26:48,822 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 01:26:48,822 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-23 01:26:48,822 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 01:26:48,826 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 01:26:48,857 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 01:26:48,857 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 01:26:48,857 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-23 01:26:48,857 INFO L811 eck$LassoCheckResult]: loop already infeasible [2018-11-23 01:26:48,857 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-23 01:26:48,858 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-23 01:26:48,858 INFO L87 Difference]: Start difference. First operand 7483 states and 10587 transitions. cyclomatic complexity: 3120 Second operand 3 states. [2018-11-23 01:26:48,933 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 01:26:48,933 INFO L93 Difference]: Finished difference Result 11190 states and 15718 transitions. [2018-11-23 01:26:48,934 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-23 01:26:48,934 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 11190 states and 15718 transitions. [2018-11-23 01:26:48,956 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 10960 [2018-11-23 01:26:48,972 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 11190 states to 11190 states and 15718 transitions. [2018-11-23 01:26:48,972 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 11190 [2018-11-23 01:26:48,978 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 11190 [2018-11-23 01:26:48,978 INFO L73 IsDeterministic]: Start isDeterministic. Operand 11190 states and 15718 transitions. [2018-11-23 01:26:48,984 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-23 01:26:48,984 INFO L705 BuchiCegarLoop]: Abstraction has 11190 states and 15718 transitions. [2018-11-23 01:26:48,989 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 11190 states and 15718 transitions. [2018-11-23 01:26:49,040 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 11190 to 11110. [2018-11-23 01:26:49,040 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 11110 states. [2018-11-23 01:26:49,050 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 11110 states to 11110 states and 15590 transitions. [2018-11-23 01:26:49,050 INFO L728 BuchiCegarLoop]: Abstraction has 11110 states and 15590 transitions. [2018-11-23 01:26:49,050 INFO L608 BuchiCegarLoop]: Abstraction has 11110 states and 15590 transitions. [2018-11-23 01:26:49,050 INFO L442 BuchiCegarLoop]: ======== Iteration 18============ [2018-11-23 01:26:49,050 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 11110 states and 15590 transitions. [2018-11-23 01:26:49,069 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 10880 [2018-11-23 01:26:49,069 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-23 01:26:49,069 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-23 01:26:49,070 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 01:26:49,070 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 01:26:49,071 INFO L794 eck$LassoCheckResult]: Stem: 117437#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0; 117324#L-1 havoc main_#res;havoc main_~__retres1~8;havoc main_~__retres1~8;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 117072#L1018 havoc start_simulation_#t~ret18, start_simulation_#t~ret19, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 117073#L470 assume 1 == ~m_i~0;~m_st~0 := 0; 116901#L477-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 116902#L482-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 117275#L487-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 117276#L492-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 117101#L497-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 117102#L502-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 117197#L507-1 assume !(0 == ~M_E~0); 116918#L686-1 assume !(0 == ~T1_E~0); 116919#L691-1 assume !(0 == ~T2_E~0); 117287#L696-1 assume !(0 == ~T3_E~0); 117288#L701-1 assume !(0 == ~T4_E~0); 117110#L706-1 assume !(0 == ~T5_E~0); 117111#L711-1 assume !(0 == ~T6_E~0); 117413#L716-1 assume !(0 == ~E_M~0); 117059#L721-1 assume 0 == ~E_1~0;~E_1~0 := 1; 117060#L726-1 assume !(0 == ~E_2~0); 117477#L731-1 assume !(0 == ~E_3~0); 117612#L736-1 assume !(0 == ~E_4~0); 117611#L741-1 assume !(0 == ~E_5~0); 117536#L746-1 assume !(0 == ~E_6~0); 117537#L751-1 havoc activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 117610#L336 assume !(1 == ~m_pc~0); 116952#L336-2 is_master_triggered_~__retres1~0 := 0; 116953#L347 is_master_triggered_#res := is_master_triggered_~__retres1~0; 117011#L348 activate_threads_#t~ret10 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 116929#L851 assume !(0 != activate_threads_~tmp~1); 116930#L851-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 117238#L355 assume !(1 == ~t1_pc~0); 117239#L355-2 is_transmit1_triggered_~__retres1~1 := 0; 117235#L366 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 116905#L367 activate_threads_#t~ret11 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 116906#L859 assume !(0 != activate_threads_~tmp___0~0); 117405#L859-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 117406#L374 assume !(1 == ~t2_pc~0); 117431#L374-2 is_transmit2_triggered_~__retres1~2 := 0; 117432#L385 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 117173#L386 activate_threads_#t~ret12 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 117174#L867 assume !(0 != activate_threads_~tmp___1~0); 117549#L867-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 117550#L393 assume !(1 == ~t3_pc~0); 117571#L393-2 is_transmit3_triggered_~__retres1~3 := 0; 117572#L404 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 117531#L405 activate_threads_#t~ret13 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 117532#L875 assume !(0 != activate_threads_~tmp___2~0); 117600#L875-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 117082#L412 assume !(1 == ~t4_pc~0); 117083#L412-2 is_transmit4_triggered_~__retres1~4 := 0; 117081#L423 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 116996#L424 activate_threads_#t~ret14 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 116997#L883 assume !(0 != activate_threads_~tmp___3~0); 117299#L883-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 117104#L431 assume !(1 == ~t5_pc~0); 117090#L431-2 is_transmit5_triggered_~__retres1~5 := 0; 117091#L442 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 117103#L443 activate_threads_#t~ret15 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 117594#L891 assume !(0 != activate_threads_~tmp___4~0); 117593#L891-2 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 117592#L450 assume !(1 == ~t6_pc~0); 117591#L450-2 is_transmit6_triggered_~__retres1~6 := 0; 117590#L461 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 117589#L462 activate_threads_#t~ret16 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 117588#L899 assume !(0 != activate_threads_~tmp___5~0); 117587#L899-2 assume !(1 == ~M_E~0); 116823#L764-1 assume !(1 == ~T1_E~0); 116824#L769-1 assume !(1 == ~T2_E~0); 117355#L774-1 assume !(1 == ~T3_E~0); 117553#L779-1 assume !(1 == ~T4_E~0); 117554#L784-1 assume !(1 == ~T5_E~0); 117582#L789-1 assume !(1 == ~T6_E~0); 117106#L794-1 assume !(1 == ~E_M~0); 117107#L799-1 assume 1 == ~E_1~0;~E_1~0 := 2; 117407#L804-1 assume !(1 == ~E_2~0); 117048#L809-1 assume !(1 == ~E_3~0); 117049#L814-1 assume !(1 == ~E_4~0); 116821#L819-1 assume !(1 == ~E_5~0); 116822#L824-1 assume !(1 == ~E_6~0); 117354#L1055-1 [2018-11-23 01:26:49,071 INFO L796 eck$LassoCheckResult]: Loop: 117354#L1055-1 assume !false; 123401#L1056 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret2, eval_#t~nondet3, eval_~tmp_ndt_1~0, eval_#t~nondet4, eval_~tmp_ndt_2~0, eval_#t~nondet5, eval_~tmp_ndt_3~0, eval_#t~nondet6, eval_~tmp_ndt_4~0, eval_#t~nondet7, eval_~tmp_ndt_5~0, eval_#t~nondet8, eval_~tmp_ndt_6~0, eval_#t~nondet9, eval_~tmp_ndt_7~0, eval_~tmp~0;havoc eval_~tmp~0; 123258#L661 assume !false; 123400#L568 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~7;havoc exists_runnable_thread_~__retres1~7; 123396#L520 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7 := 1; 123392#L557 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~7; 123391#L558 eval_#t~ret2 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret2;havoc eval_#t~ret2; 123389#L572 assume !(0 != eval_~tmp~0); 123390#L676 start_simulation_~kernel_st~0 := 2; 123595#L470-1 start_simulation_~kernel_st~0 := 3; 123593#L686-2 assume !(0 == ~M_E~0); 123591#L686-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 123589#L691-3 assume !(0 == ~T2_E~0); 123587#L696-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 123585#L701-3 assume !(0 == ~T4_E~0); 123583#L706-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 123581#L711-3 assume !(0 == ~T6_E~0); 123579#L716-3 assume 0 == ~E_M~0;~E_M~0 := 1; 123576#L721-3 assume 0 == ~E_1~0;~E_1~0 := 1; 123574#L726-3 assume 0 == ~E_2~0;~E_2~0 := 1; 123571#L731-3 assume !(0 == ~E_3~0); 123569#L736-3 assume 0 == ~E_4~0;~E_4~0 := 1; 123567#L741-3 assume !(0 == ~E_5~0); 123565#L746-3 assume 0 == ~E_6~0;~E_6~0 := 1; 123563#L751-3 havoc activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 123561#L336-24 assume !(1 == ~m_pc~0); 123559#L336-26 is_master_triggered_~__retres1~0 := 0; 123556#L347-8 is_master_triggered_#res := is_master_triggered_~__retres1~0; 123554#L348-8 activate_threads_#t~ret10 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 123552#L851-24 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 123550#L851-26 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 123548#L355-24 assume !(1 == ~t1_pc~0); 123546#L355-26 is_transmit1_triggered_~__retres1~1 := 0; 123543#L366-8 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 123541#L367-8 activate_threads_#t~ret11 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 123539#L859-24 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 123537#L859-26 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 123535#L374-24 assume !(1 == ~t2_pc~0); 123533#L374-26 is_transmit2_triggered_~__retres1~2 := 0; 123531#L385-8 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 123529#L386-8 activate_threads_#t~ret12 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 123527#L867-24 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 123525#L867-26 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 123523#L393-24 assume !(1 == ~t3_pc~0); 123520#L393-26 is_transmit3_triggered_~__retres1~3 := 0; 123518#L404-8 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 123516#L405-8 activate_threads_#t~ret13 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 123514#L875-24 assume !(0 != activate_threads_~tmp___2~0); 123512#L875-26 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 123510#L412-24 assume !(1 == ~t4_pc~0); 123508#L412-26 is_transmit4_triggered_~__retres1~4 := 0; 123507#L423-8 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 123506#L424-8 activate_threads_#t~ret14 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 123505#L883-24 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 123504#L883-26 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 123502#L431-24 assume !(1 == ~t5_pc~0); 123499#L431-26 is_transmit5_triggered_~__retres1~5 := 0; 123496#L442-8 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 123494#L443-8 activate_threads_#t~ret15 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 123492#L891-24 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 123490#L891-26 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 123488#L450-24 assume !(1 == ~t6_pc~0); 123486#L450-26 is_transmit6_triggered_~__retres1~6 := 0; 123484#L461-8 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 123482#L462-8 activate_threads_#t~ret16 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 123480#L899-24 assume 0 != activate_threads_~tmp___5~0;~t6_st~0 := 0; 123478#L899-26 assume !(1 == ~M_E~0); 123476#L764-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 123474#L769-3 assume !(1 == ~T2_E~0); 123472#L774-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 123470#L779-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 123468#L784-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 123466#L789-3 assume !(1 == ~T6_E~0); 123465#L794-3 assume 1 == ~E_M~0;~E_M~0 := 2; 123462#L799-3 assume 1 == ~E_1~0;~E_1~0 := 2; 123459#L804-3 assume 1 == ~E_2~0;~E_2~0 := 2; 123457#L809-3 assume !(1 == ~E_3~0); 123455#L814-3 assume 1 == ~E_4~0;~E_4~0 := 2; 123453#L819-3 assume 1 == ~E_5~0;~E_5~0 := 2; 123451#L824-3 assume 1 == ~E_6~0;~E_6~0 := 2; 123449#L829-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~7;havoc exists_runnable_thread_~__retres1~7; 123440#L520-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7 := 1; 123435#L557-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~7; 123432#L558-1 start_simulation_#t~ret18 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret18;havoc start_simulation_#t~ret18; 123429#L1074 assume !(0 == start_simulation_~tmp~3); 123426#L1074-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret17, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~7;havoc exists_runnable_thread_~__retres1~7; 123421#L520-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7 := 1; 123414#L557-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~7; 123412#L558-2 stop_simulation_#t~ret17 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret17;havoc stop_simulation_#t~ret17; 123410#L1029 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 123408#L1036 stop_simulation_#res := stop_simulation_~__retres2~0; 123407#L1037 start_simulation_#t~ret19 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret19;havoc start_simulation_#t~ret19; 123403#L1087 assume !(0 != start_simulation_~tmp___0~1); 117354#L1055-1 [2018-11-23 01:26:49,071 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 01:26:49,071 INFO L82 PathProgramCache]: Analyzing trace with hash -1537171736, now seen corresponding path program 1 times [2018-11-23 01:26:49,071 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 01:26:49,071 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 01:26:49,072 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 01:26:49,072 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 01:26:49,072 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 01:26:49,076 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 01:26:49,095 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 01:26:49,096 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 01:26:49,096 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2018-11-23 01:26:49,096 INFO L799 eck$LassoCheckResult]: stem already infeasible [2018-11-23 01:26:49,096 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 01:26:49,096 INFO L82 PathProgramCache]: Analyzing trace with hash -1127832331, now seen corresponding path program 1 times [2018-11-23 01:26:49,096 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 01:26:49,096 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 01:26:49,097 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 01:26:49,097 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 01:26:49,097 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 01:26:49,101 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 01:26:49,126 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 01:26:49,126 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 01:26:49,126 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-11-23 01:26:49,126 INFO L811 eck$LassoCheckResult]: loop already infeasible [2018-11-23 01:26:49,126 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-23 01:26:49,126 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-23 01:26:49,127 INFO L87 Difference]: Start difference. First operand 11110 states and 15590 transitions. cyclomatic complexity: 4496 Second operand 3 states. [2018-11-23 01:26:49,173 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 01:26:49,173 INFO L93 Difference]: Finished difference Result 7483 states and 10477 transitions. [2018-11-23 01:26:49,174 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-23 01:26:49,174 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 7483 states and 10477 transitions. [2018-11-23 01:26:49,189 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 7336 [2018-11-23 01:26:49,199 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 7483 states to 7483 states and 10477 transitions. [2018-11-23 01:26:49,199 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 7483 [2018-11-23 01:26:49,203 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 7483 [2018-11-23 01:26:49,203 INFO L73 IsDeterministic]: Start isDeterministic. Operand 7483 states and 10477 transitions. [2018-11-23 01:26:49,207 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-23 01:26:49,207 INFO L705 BuchiCegarLoop]: Abstraction has 7483 states and 10477 transitions. [2018-11-23 01:26:49,210 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 7483 states and 10477 transitions. [2018-11-23 01:26:49,242 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 7483 to 7483. [2018-11-23 01:26:49,242 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 7483 states. [2018-11-23 01:26:49,249 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 7483 states to 7483 states and 10477 transitions. [2018-11-23 01:26:49,249 INFO L728 BuchiCegarLoop]: Abstraction has 7483 states and 10477 transitions. [2018-11-23 01:26:49,249 INFO L608 BuchiCegarLoop]: Abstraction has 7483 states and 10477 transitions. [2018-11-23 01:26:49,249 INFO L442 BuchiCegarLoop]: ======== Iteration 19============ [2018-11-23 01:26:49,249 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 7483 states and 10477 transitions. [2018-11-23 01:26:49,262 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 7336 [2018-11-23 01:26:49,262 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-23 01:26:49,262 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-23 01:26:49,263 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 01:26:49,263 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 01:26:49,264 INFO L794 eck$LassoCheckResult]: Stem: 136042#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0; 135928#L-1 havoc main_#res;havoc main_~__retres1~8;havoc main_~__retres1~8;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 135673#L1018 havoc start_simulation_#t~ret18, start_simulation_#t~ret19, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 135674#L470 assume 1 == ~m_i~0;~m_st~0 := 0; 135502#L477-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 135503#L482-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 135878#L487-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 135879#L492-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 135703#L497-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 135704#L502-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 135801#L507-1 assume !(0 == ~M_E~0); 135518#L686-1 assume !(0 == ~T1_E~0); 135519#L691-1 assume !(0 == ~T2_E~0); 135890#L696-1 assume !(0 == ~T3_E~0); 135891#L701-1 assume !(0 == ~T4_E~0); 135712#L706-1 assume !(0 == ~T5_E~0); 135713#L711-1 assume !(0 == ~T6_E~0); 136014#L716-1 assume !(0 == ~E_M~0); 135658#L721-1 assume !(0 == ~E_1~0); 135659#L726-1 assume !(0 == ~E_2~0); 135429#L731-1 assume !(0 == ~E_3~0); 135430#L736-1 assume !(0 == ~E_4~0); 135508#L741-1 assume !(0 == ~E_5~0); 135509#L746-1 assume !(0 == ~E_6~0); 135885#L751-1 havoc activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 135617#L336 assume !(1 == ~m_pc~0); 135554#L336-2 is_master_triggered_~__retres1~0 := 0; 135555#L347 is_master_triggered_#res := is_master_triggered_~__retres1~0; 135616#L348 activate_threads_#t~ret10 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 135531#L851 assume !(0 != activate_threads_~tmp~1); 135532#L851-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 135534#L355 assume !(1 == ~t1_pc~0); 135841#L355-2 is_transmit1_triggered_~__retres1~1 := 0; 135840#L366 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 135506#L367 activate_threads_#t~ret11 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 135507#L859 assume !(0 != activate_threads_~tmp___0~0); 136005#L859-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 136006#L374 assume !(1 == ~t2_pc~0); 136035#L374-2 is_transmit2_triggered_~__retres1~2 := 0; 136036#L385 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 135775#L386 activate_threads_#t~ret12 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 135776#L867 assume !(0 != activate_threads_~tmp___1~0); 136146#L867-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 136148#L393 assume !(1 == ~t3_pc~0); 136135#L393-2 is_transmit3_triggered_~__retres1~3 := 0; 136161#L404 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 136133#L405 activate_threads_#t~ret13 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 135666#L875 assume !(0 != activate_threads_~tmp___2~0); 135645#L875-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 135646#L412 assume !(1 == ~t4_pc~0); 135686#L412-2 is_transmit4_triggered_~__retres1~4 := 0; 135685#L423 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 135598#L424 activate_threads_#t~ret14 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 135599#L883 assume !(0 != activate_threads_~tmp___3~0); 135902#L883-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 135706#L431 assume !(1 == ~t5_pc~0); 135692#L431-2 is_transmit5_triggered_~__retres1~5 := 0; 135693#L442 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 135705#L443 activate_threads_#t~ret15 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 135880#L891 assume !(0 != activate_threads_~tmp___4~0); 136079#L891-2 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 135949#L450 assume !(1 == ~t6_pc~0); 135950#L450-2 is_transmit6_triggered_~__retres1~6 := 0; 135947#L461 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 135948#L462 activate_threads_#t~ret16 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 136059#L899 assume !(0 != activate_threads_~tmp___5~0); 136083#L899-2 assume !(1 == ~M_E~0); 135425#L764-1 assume !(1 == ~T1_E~0); 135426#L769-1 assume !(1 == ~T2_E~0); 135538#L774-1 assume !(1 == ~T3_E~0); 135539#L779-1 assume !(1 == ~T4_E~0); 135906#L784-1 assume !(1 == ~T5_E~0); 135907#L789-1 assume !(1 == ~T6_E~0); 135708#L794-1 assume !(1 == ~E_M~0); 135709#L799-1 assume !(1 == ~E_1~0); 136007#L804-1 assume !(1 == ~E_2~0); 135651#L809-1 assume !(1 == ~E_3~0); 135652#L814-1 assume !(1 == ~E_4~0); 135423#L819-1 assume !(1 == ~E_5~0); 135424#L824-1 assume !(1 == ~E_6~0); 135956#L1055-1 [2018-11-23 01:26:49,264 INFO L796 eck$LassoCheckResult]: Loop: 135956#L1055-1 assume !false; 139032#L1056 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret2, eval_#t~nondet3, eval_~tmp_ndt_1~0, eval_#t~nondet4, eval_~tmp_ndt_2~0, eval_#t~nondet5, eval_~tmp_ndt_3~0, eval_#t~nondet6, eval_~tmp_ndt_4~0, eval_#t~nondet7, eval_~tmp_ndt_5~0, eval_#t~nondet8, eval_~tmp_ndt_6~0, eval_#t~nondet9, eval_~tmp_ndt_7~0, eval_~tmp~0;havoc eval_~tmp~0; 139030#L661 assume !false; 139026#L568 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~7;havoc exists_runnable_thread_~__retres1~7; 138774#L520 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7 := 1; 138731#L557 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~7; 138724#L558 eval_#t~ret2 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret2;havoc eval_#t~ret2; 138716#L572 assume !(0 != eval_~tmp~0); 138717#L676 start_simulation_~kernel_st~0 := 2; 139549#L470-1 start_simulation_~kernel_st~0 := 3; 139548#L686-2 assume !(0 == ~M_E~0); 139547#L686-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 139546#L691-3 assume !(0 == ~T2_E~0); 139545#L696-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 139544#L701-3 assume !(0 == ~T4_E~0); 139543#L706-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 139542#L711-3 assume !(0 == ~T6_E~0); 139541#L716-3 assume 0 == ~E_M~0;~E_M~0 := 1; 139540#L721-3 assume !(0 == ~E_1~0); 139539#L726-3 assume 0 == ~E_2~0;~E_2~0 := 1; 139538#L731-3 assume !(0 == ~E_3~0); 139537#L736-3 assume 0 == ~E_4~0;~E_4~0 := 1; 139536#L741-3 assume !(0 == ~E_5~0); 139535#L746-3 assume 0 == ~E_6~0;~E_6~0 := 1; 139534#L751-3 havoc activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 139533#L336-24 assume 1 == ~m_pc~0; 139531#L337-8 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 139530#L347-8 is_master_triggered_#res := is_master_triggered_~__retres1~0; 139529#L348-8 activate_threads_#t~ret10 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 139528#L851-24 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 139526#L851-26 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 139524#L355-24 assume !(1 == ~t1_pc~0); 139521#L355-26 is_transmit1_triggered_~__retres1~1 := 0; 139518#L366-8 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 139515#L367-8 activate_threads_#t~ret11 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 139512#L859-24 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 139509#L859-26 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 139506#L374-24 assume !(1 == ~t2_pc~0); 139503#L374-26 is_transmit2_triggered_~__retres1~2 := 0; 139500#L385-8 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 139497#L386-8 activate_threads_#t~ret12 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 139494#L867-24 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 139491#L867-26 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 139488#L393-24 assume !(1 == ~t3_pc~0); 139484#L393-26 is_transmit3_triggered_~__retres1~3 := 0; 139479#L404-8 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 139471#L405-8 activate_threads_#t~ret13 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 139466#L875-24 assume !(0 != activate_threads_~tmp___2~0); 139462#L875-26 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 139457#L412-24 assume !(1 == ~t4_pc~0); 139452#L412-26 is_transmit4_triggered_~__retres1~4 := 0; 139448#L423-8 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 139443#L424-8 activate_threads_#t~ret14 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 139439#L883-24 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 139434#L883-26 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 139430#L431-24 assume !(1 == ~t5_pc~0); 139426#L431-26 is_transmit5_triggered_~__retres1~5 := 0; 139421#L442-8 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 139417#L443-8 activate_threads_#t~ret15 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 139413#L891-24 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 139409#L891-26 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 139404#L450-24 assume !(1 == ~t6_pc~0); 139399#L450-26 is_transmit6_triggered_~__retres1~6 := 0; 139394#L461-8 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 139387#L462-8 activate_threads_#t~ret16 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 139382#L899-24 assume 0 != activate_threads_~tmp___5~0;~t6_st~0 := 0; 139376#L899-26 assume !(1 == ~M_E~0); 139370#L764-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 139365#L769-3 assume !(1 == ~T2_E~0); 139360#L774-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 139356#L779-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 139352#L784-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 139347#L789-3 assume !(1 == ~T6_E~0); 139342#L794-3 assume 1 == ~E_M~0;~E_M~0 := 2; 139337#L799-3 assume !(1 == ~E_1~0); 139331#L804-3 assume 1 == ~E_2~0;~E_2~0 := 2; 139327#L809-3 assume !(1 == ~E_3~0); 139322#L814-3 assume 1 == ~E_4~0;~E_4~0 := 2; 139319#L819-3 assume 1 == ~E_5~0;~E_5~0 := 2; 139314#L824-3 assume 1 == ~E_6~0;~E_6~0 := 2; 139309#L829-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~7;havoc exists_runnable_thread_~__retres1~7; 139292#L520-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7 := 1; 139284#L557-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~7; 139094#L558-1 start_simulation_#t~ret18 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret18;havoc start_simulation_#t~ret18; 139090#L1074 assume !(0 == start_simulation_~tmp~3); 139084#L1074-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret17, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~7;havoc exists_runnable_thread_~__retres1~7; 139069#L520-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7 := 1; 139062#L557-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~7; 139060#L558-2 stop_simulation_#t~ret17 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret17;havoc stop_simulation_#t~ret17; 139058#L1029 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 139056#L1036 stop_simulation_#res := stop_simulation_~__retres2~0; 139047#L1037 start_simulation_#t~ret19 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret19;havoc start_simulation_#t~ret19; 139042#L1087 assume !(0 != start_simulation_~tmp___0~1); 135956#L1055-1 [2018-11-23 01:26:49,264 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 01:26:49,264 INFO L82 PathProgramCache]: Analyzing trace with hash -800641180, now seen corresponding path program 3 times [2018-11-23 01:26:49,264 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 01:26:49,264 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 01:26:49,265 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 01:26:49,265 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 01:26:49,265 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 01:26:49,270 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-23 01:26:49,276 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-23 01:26:49,288 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 01:26:49,289 INFO L82 PathProgramCache]: Analyzing trace with hash 1374482650, now seen corresponding path program 1 times [2018-11-23 01:26:49,289 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 01:26:49,289 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 01:26:49,289 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 01:26:49,289 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-23 01:26:49,290 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 01:26:49,294 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 01:26:49,320 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 01:26:49,320 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 01:26:49,320 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-11-23 01:26:49,320 INFO L811 eck$LassoCheckResult]: loop already infeasible [2018-11-23 01:26:49,320 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-11-23 01:26:49,321 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-11-23 01:26:49,321 INFO L87 Difference]: Start difference. First operand 7483 states and 10477 transitions. cyclomatic complexity: 3010 Second operand 5 states. [2018-11-23 01:26:49,416 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 01:26:49,416 INFO L93 Difference]: Finished difference Result 13507 states and 18705 transitions. [2018-11-23 01:26:49,418 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2018-11-23 01:26:49,418 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 13507 states and 18705 transitions. [2018-11-23 01:26:49,488 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 13296 [2018-11-23 01:26:49,503 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 13507 states to 13507 states and 18705 transitions. [2018-11-23 01:26:49,503 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 13507 [2018-11-23 01:26:49,508 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 13507 [2018-11-23 01:26:49,509 INFO L73 IsDeterministic]: Start isDeterministic. Operand 13507 states and 18705 transitions. [2018-11-23 01:26:49,514 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-23 01:26:49,514 INFO L705 BuchiCegarLoop]: Abstraction has 13507 states and 18705 transitions. [2018-11-23 01:26:49,519 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 13507 states and 18705 transitions. [2018-11-23 01:26:49,562 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 13507 to 7531. [2018-11-23 01:26:49,562 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 7531 states. [2018-11-23 01:26:49,569 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 7531 states to 7531 states and 10525 transitions. [2018-11-23 01:26:49,569 INFO L728 BuchiCegarLoop]: Abstraction has 7531 states and 10525 transitions. [2018-11-23 01:26:49,569 INFO L608 BuchiCegarLoop]: Abstraction has 7531 states and 10525 transitions. [2018-11-23 01:26:49,569 INFO L442 BuchiCegarLoop]: ======== Iteration 20============ [2018-11-23 01:26:49,569 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 7531 states and 10525 transitions. [2018-11-23 01:26:49,582 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 7384 [2018-11-23 01:26:49,582 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-23 01:26:49,582 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-23 01:26:49,583 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 01:26:49,583 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 01:26:49,584 INFO L794 eck$LassoCheckResult]: Stem: 157019#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0; 156912#L-1 havoc main_#res;havoc main_~__retres1~8;havoc main_~__retres1~8;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 156672#L1018 havoc start_simulation_#t~ret18, start_simulation_#t~ret19, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 156673#L470 assume 1 == ~m_i~0;~m_st~0 := 0; 156508#L477-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 156509#L482-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 156864#L487-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 156865#L492-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 156697#L497-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 156698#L502-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 156792#L507-1 assume !(0 == ~M_E~0); 156524#L686-1 assume !(0 == ~T1_E~0); 156525#L691-1 assume !(0 == ~T2_E~0); 156876#L696-1 assume !(0 == ~T3_E~0); 156877#L701-1 assume !(0 == ~T4_E~0); 156706#L706-1 assume !(0 == ~T5_E~0); 156707#L711-1 assume !(0 == ~T6_E~0); 156994#L716-1 assume !(0 == ~E_M~0); 156662#L721-1 assume !(0 == ~E_1~0); 156663#L726-1 assume !(0 == ~E_2~0); 156436#L731-1 assume !(0 == ~E_3~0); 156437#L736-1 assume !(0 == ~E_4~0); 156515#L741-1 assume !(0 == ~E_5~0); 156516#L746-1 assume !(0 == ~E_6~0); 156871#L751-1 havoc activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 156623#L336 assume !(1 == ~m_pc~0); 156560#L336-2 is_master_triggered_~__retres1~0 := 0; 156561#L347 is_master_triggered_#res := is_master_triggered_~__retres1~0; 156619#L348 activate_threads_#t~ret10 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 156538#L851 assume !(0 != activate_threads_~tmp~1); 156539#L851-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 156541#L355 assume !(1 == ~t1_pc~0); 156836#L355-2 is_transmit1_triggered_~__retres1~1 := 0; 156833#L366 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 156513#L367 activate_threads_#t~ret11 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 156514#L859 assume !(0 != activate_threads_~tmp___0~0); 156986#L859-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 156987#L374 assume !(1 == ~t2_pc~0); 157013#L374-2 is_transmit2_triggered_~__retres1~2 := 0; 157014#L385 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 156767#L386 activate_threads_#t~ret12 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 156768#L867 assume !(0 != activate_threads_~tmp___1~0); 157132#L867-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 157134#L393 assume !(1 == ~t3_pc~0); 157123#L393-2 is_transmit3_triggered_~__retres1~3 := 0; 157147#L404 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 157120#L405 activate_threads_#t~ret13 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 156667#L875 assume !(0 != activate_threads_~tmp___2~0); 156651#L875-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 156652#L412 assume !(1 == ~t4_pc~0); 156681#L412-2 is_transmit4_triggered_~__retres1~4 := 0; 156680#L423 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 156604#L424 activate_threads_#t~ret14 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 156605#L883 assume !(0 != activate_threads_~tmp___3~0); 156889#L883-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 156700#L431 assume !(1 == ~t5_pc~0); 156686#L431-2 is_transmit5_triggered_~__retres1~5 := 0; 156687#L442 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 156699#L443 activate_threads_#t~ret15 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 156868#L891 assume !(0 != activate_threads_~tmp___4~0); 157059#L891-2 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 156932#L450 assume !(1 == ~t6_pc~0); 156933#L450-2 is_transmit6_triggered_~__retres1~6 := 0; 156930#L461 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 156931#L462 activate_threads_#t~ret16 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 157039#L899 assume !(0 != activate_threads_~tmp___5~0); 157064#L899-2 assume !(1 == ~M_E~0); 156432#L764-1 assume !(1 == ~T1_E~0); 156433#L769-1 assume !(1 == ~T2_E~0); 156544#L774-1 assume !(1 == ~T3_E~0); 156545#L779-1 assume !(1 == ~T4_E~0); 156891#L784-1 assume !(1 == ~T5_E~0); 156892#L789-1 assume !(1 == ~T6_E~0); 156702#L794-1 assume !(1 == ~E_M~0); 156703#L799-1 assume !(1 == ~E_1~0); 156988#L804-1 assume !(1 == ~E_2~0); 156653#L809-1 assume !(1 == ~E_3~0); 156654#L814-1 assume !(1 == ~E_4~0); 156430#L819-1 assume !(1 == ~E_5~0); 156431#L824-1 assume !(1 == ~E_6~0); 156939#L1055-1 [2018-11-23 01:26:49,584 INFO L796 eck$LassoCheckResult]: Loop: 156939#L1055-1 assume !false; 161490#L1056 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret2, eval_#t~nondet3, eval_~tmp_ndt_1~0, eval_#t~nondet4, eval_~tmp_ndt_2~0, eval_#t~nondet5, eval_~tmp_ndt_3~0, eval_#t~nondet6, eval_~tmp_ndt_4~0, eval_#t~nondet7, eval_~tmp_ndt_5~0, eval_#t~nondet8, eval_~tmp_ndt_6~0, eval_#t~nondet9, eval_~tmp_ndt_7~0, eval_~tmp~0;havoc eval_~tmp~0; 161489#L661 assume !false; 161488#L568 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~7;havoc exists_runnable_thread_~__retres1~7; 161484#L520 assume !(0 == ~m_st~0); 161485#L524 assume !(0 == ~t1_st~0); 161487#L528 assume !(0 == ~t2_st~0); 161482#L532 assume !(0 == ~t3_st~0); 161483#L536 assume !(0 == ~t4_st~0); 161486#L540 assume !(0 == ~t5_st~0); 161480#L544 assume !(0 == ~t6_st~0);exists_runnable_thread_~__retres1~7 := 0; 161481#L557 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~7; 158617#L558 eval_#t~ret2 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret2;havoc eval_#t~ret2; 158618#L572 assume !(0 != eval_~tmp~0); 161670#L676 start_simulation_~kernel_st~0 := 2; 161669#L470-1 start_simulation_~kernel_st~0 := 3; 161668#L686-2 assume !(0 == ~M_E~0); 161667#L686-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 161666#L691-3 assume !(0 == ~T2_E~0); 161665#L696-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 161664#L701-3 assume !(0 == ~T4_E~0); 161663#L706-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 161662#L711-3 assume !(0 == ~T6_E~0); 161661#L716-3 assume 0 == ~E_M~0;~E_M~0 := 1; 161660#L721-3 assume !(0 == ~E_1~0); 161659#L726-3 assume 0 == ~E_2~0;~E_2~0 := 1; 161658#L731-3 assume !(0 == ~E_3~0); 161657#L736-3 assume 0 == ~E_4~0;~E_4~0 := 1; 161656#L741-3 assume !(0 == ~E_5~0); 161655#L746-3 assume 0 == ~E_6~0;~E_6~0 := 1; 161654#L751-3 havoc activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 161653#L336-24 assume 1 == ~m_pc~0; 161651#L337-8 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 161650#L347-8 is_master_triggered_#res := is_master_triggered_~__retres1~0; 161649#L348-8 activate_threads_#t~ret10 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 161648#L851-24 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 161647#L851-26 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 161646#L355-24 assume !(1 == ~t1_pc~0); 161645#L355-26 is_transmit1_triggered_~__retres1~1 := 0; 161644#L366-8 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 161643#L367-8 activate_threads_#t~ret11 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 161642#L859-24 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 161641#L859-26 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 161640#L374-24 assume !(1 == ~t2_pc~0); 161639#L374-26 is_transmit2_triggered_~__retres1~2 := 0; 161638#L385-8 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 161637#L386-8 activate_threads_#t~ret12 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 161636#L867-24 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 161635#L867-26 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 161634#L393-24 assume !(1 == ~t3_pc~0); 161632#L393-26 is_transmit3_triggered_~__retres1~3 := 0; 161631#L404-8 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 161630#L405-8 activate_threads_#t~ret13 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 161629#L875-24 assume !(0 != activate_threads_~tmp___2~0); 161628#L875-26 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 161627#L412-24 assume !(1 == ~t4_pc~0); 161626#L412-26 is_transmit4_triggered_~__retres1~4 := 0; 161625#L423-8 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 161624#L424-8 activate_threads_#t~ret14 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 161623#L883-24 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 161622#L883-26 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 161621#L431-24 assume 1 == ~t5_pc~0; 161619#L432-8 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 161618#L442-8 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 161617#L443-8 activate_threads_#t~ret15 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 161616#L891-24 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 161615#L891-26 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 161614#L450-24 assume !(1 == ~t6_pc~0); 161613#L450-26 is_transmit6_triggered_~__retres1~6 := 0; 161612#L461-8 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 161611#L462-8 activate_threads_#t~ret16 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 161610#L899-24 assume 0 != activate_threads_~tmp___5~0;~t6_st~0 := 0; 161609#L899-26 assume !(1 == ~M_E~0); 161608#L764-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 161607#L769-3 assume !(1 == ~T2_E~0); 161606#L774-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 161605#L779-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 161604#L784-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 161603#L789-3 assume !(1 == ~T6_E~0); 161602#L794-3 assume 1 == ~E_M~0;~E_M~0 := 2; 161601#L799-3 assume !(1 == ~E_1~0); 161600#L804-3 assume 1 == ~E_2~0;~E_2~0 := 2; 161599#L809-3 assume !(1 == ~E_3~0); 161598#L814-3 assume 1 == ~E_4~0;~E_4~0 := 2; 161597#L819-3 assume 1 == ~E_5~0;~E_5~0 := 2; 161596#L824-3 assume 1 == ~E_6~0;~E_6~0 := 2; 161595#L829-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~7;havoc exists_runnable_thread_~__retres1~7; 161591#L520-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7 := 1; 161581#L557-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~7; 161577#L558-1 start_simulation_#t~ret18 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret18;havoc start_simulation_#t~ret18; 161572#L1074 assume !(0 == start_simulation_~tmp~3); 161570#L1074-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret17, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~7;havoc exists_runnable_thread_~__retres1~7; 161568#L520-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7 := 1; 161561#L557-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~7; 161559#L558-2 stop_simulation_#t~ret17 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret17;havoc stop_simulation_#t~ret17; 161557#L1029 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 161555#L1036 stop_simulation_#res := stop_simulation_~__retres2~0; 161553#L1037 start_simulation_#t~ret19 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret19;havoc start_simulation_#t~ret19; 161551#L1087 assume !(0 != start_simulation_~tmp___0~1); 156939#L1055-1 [2018-11-23 01:26:49,584 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 01:26:49,584 INFO L82 PathProgramCache]: Analyzing trace with hash -800641180, now seen corresponding path program 4 times [2018-11-23 01:26:49,584 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 01:26:49,585 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 01:26:49,585 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 01:26:49,585 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 01:26:49,585 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 01:26:49,590 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-23 01:26:49,594 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-23 01:26:49,608 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 01:26:49,608 INFO L82 PathProgramCache]: Analyzing trace with hash 451201420, now seen corresponding path program 1 times [2018-11-23 01:26:49,608 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 01:26:49,609 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 01:26:49,609 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 01:26:49,609 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-23 01:26:49,609 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 01:26:49,615 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 01:26:49,668 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 01:26:49,669 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 01:26:49,669 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-11-23 01:26:49,669 INFO L811 eck$LassoCheckResult]: loop already infeasible [2018-11-23 01:26:49,669 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-11-23 01:26:49,669 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-11-23 01:26:49,669 INFO L87 Difference]: Start difference. First operand 7531 states and 10525 transitions. cyclomatic complexity: 3010 Second operand 5 states. [2018-11-23 01:26:49,766 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 01:26:49,766 INFO L93 Difference]: Finished difference Result 9775 states and 13740 transitions. [2018-11-23 01:26:49,766 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2018-11-23 01:26:49,767 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 9775 states and 13740 transitions. [2018-11-23 01:26:49,787 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 9580 [2018-11-23 01:26:49,801 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 9775 states to 9775 states and 13740 transitions. [2018-11-23 01:26:49,801 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 9775 [2018-11-23 01:26:49,806 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 9775 [2018-11-23 01:26:49,806 INFO L73 IsDeterministic]: Start isDeterministic. Operand 9775 states and 13740 transitions. [2018-11-23 01:26:49,810 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-23 01:26:49,811 INFO L705 BuchiCegarLoop]: Abstraction has 9775 states and 13740 transitions. [2018-11-23 01:26:49,815 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 9775 states and 13740 transitions. [2018-11-23 01:26:49,854 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 9775 to 7555. [2018-11-23 01:26:49,854 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 7555 states. [2018-11-23 01:26:49,861 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 7555 states to 7555 states and 10444 transitions. [2018-11-23 01:26:49,861 INFO L728 BuchiCegarLoop]: Abstraction has 7555 states and 10444 transitions. [2018-11-23 01:26:49,861 INFO L608 BuchiCegarLoop]: Abstraction has 7555 states and 10444 transitions. [2018-11-23 01:26:49,862 INFO L442 BuchiCegarLoop]: ======== Iteration 21============ [2018-11-23 01:26:49,862 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 7555 states and 10444 transitions. [2018-11-23 01:26:49,875 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 7408 [2018-11-23 01:26:49,875 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-23 01:26:49,875 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-23 01:26:49,876 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 01:26:49,876 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 01:26:49,877 INFO L794 eck$LassoCheckResult]: Stem: 174438#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0; 174306#L-1 havoc main_#res;havoc main_~__retres1~8;havoc main_~__retres1~8;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 174012#L1018 havoc start_simulation_#t~ret18, start_simulation_#t~ret19, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 174013#L470 assume 1 == ~m_i~0;~m_st~0 := 0; 173829#L477-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 173830#L482-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 174242#L487-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 174243#L492-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 174050#L497-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 174051#L502-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 174150#L507-1 assume !(0 == ~M_E~0); 173846#L686-1 assume !(0 == ~T1_E~0); 173847#L691-1 assume !(0 == ~T2_E~0); 174256#L696-1 assume !(0 == ~T3_E~0); 174257#L701-1 assume !(0 == ~T4_E~0); 174059#L706-1 assume !(0 == ~T5_E~0); 174060#L711-1 assume !(0 == ~T6_E~0); 174403#L716-1 assume !(0 == ~E_M~0); 173990#L721-1 assume !(0 == ~E_1~0); 173991#L726-1 assume !(0 == ~E_2~0); 173756#L731-1 assume !(0 == ~E_3~0); 173757#L736-1 assume !(0 == ~E_4~0); 173836#L741-1 assume !(0 == ~E_5~0); 173837#L746-1 assume !(0 == ~E_6~0); 174250#L751-1 havoc activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 173947#L336 assume !(1 == ~m_pc~0); 173883#L336-2 is_master_triggered_~__retres1~0 := 0; 173884#L347 is_master_triggered_#res := is_master_triggered_~__retres1~0; 173943#L348 activate_threads_#t~ret10 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 173859#L851 assume !(0 != activate_threads_~tmp~1); 173860#L851-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 173863#L355 assume !(1 == ~t1_pc~0); 174201#L355-2 is_transmit1_triggered_~__retres1~1 := 0; 174198#L366 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 173834#L367 activate_threads_#t~ret11 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 173835#L859 assume !(0 != activate_threads_~tmp___0~0); 174394#L859-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 174395#L374 assume !(1 == ~t2_pc~0); 174429#L374-2 is_transmit2_triggered_~__retres1~2 := 0; 174430#L385 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 174125#L386 activate_threads_#t~ret12 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 174126#L867 assume !(0 != activate_threads_~tmp___1~0); 174586#L867-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 174590#L393 assume !(1 == ~t3_pc~0); 174570#L393-2 is_transmit3_triggered_~__retres1~3 := 0; 174615#L404 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 174566#L405 activate_threads_#t~ret13 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 174002#L875 assume !(0 != activate_threads_~tmp___2~0); 173977#L875-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 173978#L412 assume !(1 == ~t4_pc~0); 174034#L412-2 is_transmit4_triggered_~__retres1~4 := 0; 174033#L423 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 173928#L424 activate_threads_#t~ret14 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 173929#L883 assume !(0 != activate_threads_~tmp___3~0); 174269#L883-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 174053#L431 assume !(1 == ~t5_pc~0); 174039#L431-2 is_transmit5_triggered_~__retres1~5 := 0; 174040#L442 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 174052#L443 activate_threads_#t~ret15 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 174246#L891 assume !(0 != activate_threads_~tmp___4~0); 174496#L891-2 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 174326#L450 assume !(1 == ~t6_pc~0); 174327#L450-2 is_transmit6_triggered_~__retres1~6 := 0; 174324#L461 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 174325#L462 activate_threads_#t~ret16 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 174462#L899 assume !(0 != activate_threads_~tmp___5~0); 174509#L899-2 assume !(1 == ~M_E~0); 173752#L764-1 assume !(1 == ~T1_E~0); 173753#L769-1 assume !(1 == ~T2_E~0); 173866#L774-1 assume !(1 == ~T3_E~0); 173867#L779-1 assume !(1 == ~T4_E~0); 174276#L784-1 assume !(1 == ~T5_E~0); 174277#L789-1 assume !(1 == ~T6_E~0); 174055#L794-1 assume !(1 == ~E_M~0); 174056#L799-1 assume !(1 == ~E_1~0); 174396#L804-1 assume !(1 == ~E_2~0); 173979#L809-1 assume !(1 == ~E_3~0); 173980#L814-1 assume !(1 == ~E_4~0); 173750#L819-1 assume !(1 == ~E_5~0); 173751#L824-1 assume !(1 == ~E_6~0); 174334#L1055-1 [2018-11-23 01:26:49,877 INFO L796 eck$LassoCheckResult]: Loop: 174334#L1055-1 assume !false; 178085#L1056 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret2, eval_#t~nondet3, eval_~tmp_ndt_1~0, eval_#t~nondet4, eval_~tmp_ndt_2~0, eval_#t~nondet5, eval_~tmp_ndt_3~0, eval_#t~nondet6, eval_~tmp_ndt_4~0, eval_#t~nondet7, eval_~tmp_ndt_5~0, eval_#t~nondet8, eval_~tmp_ndt_6~0, eval_#t~nondet9, eval_~tmp_ndt_7~0, eval_~tmp~0;havoc eval_~tmp~0; 177296#L661 assume !false; 178084#L568 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~7;havoc exists_runnable_thread_~__retres1~7; 178080#L520 assume !(0 == ~m_st~0); 178081#L524 assume !(0 == ~t1_st~0); 178083#L528 assume !(0 == ~t2_st~0); 178078#L532 assume !(0 == ~t3_st~0); 178079#L536 assume !(0 == ~t4_st~0); 178082#L540 assume !(0 == ~t5_st~0); 178076#L544 assume !(0 == ~t6_st~0);exists_runnable_thread_~__retres1~7 := 0; 178077#L557 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~7; 176077#L558 eval_#t~ret2 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret2;havoc eval_#t~ret2; 176078#L572 assume !(0 != eval_~tmp~0); 178244#L676 start_simulation_~kernel_st~0 := 2; 178243#L470-1 start_simulation_~kernel_st~0 := 3; 178242#L686-2 assume !(0 == ~M_E~0); 178241#L686-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 178240#L691-3 assume !(0 == ~T2_E~0); 178239#L696-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 178238#L701-3 assume !(0 == ~T4_E~0); 178237#L706-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 178236#L711-3 assume !(0 == ~T6_E~0); 178235#L716-3 assume 0 == ~E_M~0;~E_M~0 := 1; 178234#L721-3 assume !(0 == ~E_1~0); 178233#L726-3 assume 0 == ~E_2~0;~E_2~0 := 1; 178232#L731-3 assume !(0 == ~E_3~0); 178231#L736-3 assume 0 == ~E_4~0;~E_4~0 := 1; 178230#L741-3 assume !(0 == ~E_5~0); 178229#L746-3 assume 0 == ~E_6~0;~E_6~0 := 1; 178228#L751-3 havoc activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 178227#L336-24 assume !(1 == ~m_pc~0); 178226#L336-26 is_master_triggered_~__retres1~0 := 0; 178224#L347-8 is_master_triggered_#res := is_master_triggered_~__retres1~0; 178223#L348-8 activate_threads_#t~ret10 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 178222#L851-24 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 178221#L851-26 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 178219#L355-24 assume !(1 == ~t1_pc~0); 178216#L355-26 is_transmit1_triggered_~__retres1~1 := 0; 178214#L366-8 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 178212#L367-8 activate_threads_#t~ret11 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 178210#L859-24 assume !(0 != activate_threads_~tmp___0~0); 178208#L859-26 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 178206#L374-24 assume !(1 == ~t2_pc~0); 178204#L374-26 is_transmit2_triggered_~__retres1~2 := 0; 178202#L385-8 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 178200#L386-8 activate_threads_#t~ret12 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 178198#L867-24 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 178196#L867-26 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 178194#L393-24 assume !(1 == ~t3_pc~0); 178191#L393-26 is_transmit3_triggered_~__retres1~3 := 0; 178189#L404-8 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 178187#L405-8 activate_threads_#t~ret13 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 178185#L875-24 assume !(0 != activate_threads_~tmp___2~0); 178183#L875-26 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 178180#L412-24 assume !(1 == ~t4_pc~0); 178178#L412-26 is_transmit4_triggered_~__retres1~4 := 0; 178176#L423-8 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 178174#L424-8 activate_threads_#t~ret14 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 178172#L883-24 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 178170#L883-26 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 178168#L431-24 assume !(1 == ~t5_pc~0); 178166#L431-26 is_transmit5_triggered_~__retres1~5 := 0; 178163#L442-8 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 178161#L443-8 activate_threads_#t~ret15 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 178159#L891-24 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 178157#L891-26 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 178155#L450-24 assume !(1 == ~t6_pc~0); 178152#L450-26 is_transmit6_triggered_~__retres1~6 := 0; 178150#L461-8 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 178148#L462-8 activate_threads_#t~ret16 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 178146#L899-24 assume 0 != activate_threads_~tmp___5~0;~t6_st~0 := 0; 178144#L899-26 assume !(1 == ~M_E~0); 178142#L764-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 178140#L769-3 assume !(1 == ~T2_E~0); 178138#L774-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 178136#L779-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 178134#L784-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 178132#L789-3 assume !(1 == ~T6_E~0); 178130#L794-3 assume 1 == ~E_M~0;~E_M~0 := 2; 178128#L799-3 assume !(1 == ~E_1~0); 178126#L804-3 assume 1 == ~E_2~0;~E_2~0 := 2; 178124#L809-3 assume !(1 == ~E_3~0); 178122#L814-3 assume 1 == ~E_4~0;~E_4~0 := 2; 178120#L819-3 assume 1 == ~E_5~0;~E_5~0 := 2; 178118#L824-3 assume 1 == ~E_6~0;~E_6~0 := 2; 178116#L829-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~7;havoc exists_runnable_thread_~__retres1~7; 178111#L520-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7 := 1; 178106#L557-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~7; 178104#L558-1 start_simulation_#t~ret18 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret18;havoc start_simulation_#t~ret18; 178101#L1074 assume !(0 == start_simulation_~tmp~3); 178099#L1074-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret17, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~7;havoc exists_runnable_thread_~__retres1~7; 178097#L520-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7 := 1; 178091#L557-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~7; 178090#L558-2 stop_simulation_#t~ret17 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret17;havoc stop_simulation_#t~ret17; 178089#L1029 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 178088#L1036 stop_simulation_#res := stop_simulation_~__retres2~0; 178087#L1037 start_simulation_#t~ret19 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret19;havoc start_simulation_#t~ret19; 178086#L1087 assume !(0 != start_simulation_~tmp___0~1); 174334#L1055-1 [2018-11-23 01:26:49,877 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 01:26:49,877 INFO L82 PathProgramCache]: Analyzing trace with hash -800641180, now seen corresponding path program 5 times [2018-11-23 01:26:49,878 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 01:26:49,878 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 01:26:49,878 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 01:26:49,878 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 01:26:49,879 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 01:26:49,884 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-23 01:26:49,889 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-23 01:26:49,903 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 01:26:49,903 INFO L82 PathProgramCache]: Analyzing trace with hash -1048903096, now seen corresponding path program 1 times [2018-11-23 01:26:49,903 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 01:26:49,903 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 01:26:49,904 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 01:26:49,904 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-23 01:26:49,904 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 01:26:49,909 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 01:26:49,969 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 01:26:49,969 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 01:26:49,970 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-11-23 01:26:49,970 INFO L811 eck$LassoCheckResult]: loop already infeasible [2018-11-23 01:26:49,970 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-11-23 01:26:49,970 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-11-23 01:26:49,970 INFO L87 Difference]: Start difference. First operand 7555 states and 10444 transitions. cyclomatic complexity: 2905 Second operand 5 states. [2018-11-23 01:26:50,121 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 01:26:50,121 INFO L93 Difference]: Finished difference Result 21598 states and 29567 transitions. [2018-11-23 01:26:50,121 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2018-11-23 01:26:50,122 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 21598 states and 29567 transitions. [2018-11-23 01:26:50,169 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 21216 [2018-11-23 01:26:50,201 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 21598 states to 21598 states and 29567 transitions. [2018-11-23 01:26:50,201 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 21598 [2018-11-23 01:26:50,211 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 21598 [2018-11-23 01:26:50,211 INFO L73 IsDeterministic]: Start isDeterministic. Operand 21598 states and 29567 transitions. [2018-11-23 01:26:50,220 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-23 01:26:50,220 INFO L705 BuchiCegarLoop]: Abstraction has 21598 states and 29567 transitions. [2018-11-23 01:26:50,229 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 21598 states and 29567 transitions. [2018-11-23 01:26:50,291 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 21598 to 7894. [2018-11-23 01:26:50,291 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 7894 states. [2018-11-23 01:26:50,298 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 7894 states to 7894 states and 10783 transitions. [2018-11-23 01:26:50,299 INFO L728 BuchiCegarLoop]: Abstraction has 7894 states and 10783 transitions. [2018-11-23 01:26:50,299 INFO L608 BuchiCegarLoop]: Abstraction has 7894 states and 10783 transitions. [2018-11-23 01:26:50,299 INFO L442 BuchiCegarLoop]: ======== Iteration 22============ [2018-11-23 01:26:50,299 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 7894 states and 10783 transitions. [2018-11-23 01:26:50,314 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 7744 [2018-11-23 01:26:50,314 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-23 01:26:50,314 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-23 01:26:50,315 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 01:26:50,315 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 01:26:50,315 INFO L794 eck$LassoCheckResult]: Stem: 203535#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0; 203424#L-1 havoc main_#res;havoc main_~__retres1~8;havoc main_~__retres1~8;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 203166#L1018 havoc start_simulation_#t~ret18, start_simulation_#t~ret19, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 203167#L470 assume 1 == ~m_i~0;~m_st~0 := 0; 202995#L477-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 202996#L482-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 203374#L487-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 203375#L492-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 203193#L497-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 203194#L502-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 203292#L507-1 assume !(0 == ~M_E~0); 203011#L686-1 assume !(0 == ~T1_E~0); 203012#L691-1 assume !(0 == ~T2_E~0); 203384#L696-1 assume !(0 == ~T3_E~0); 203385#L701-1 assume !(0 == ~T4_E~0); 203202#L706-1 assume !(0 == ~T5_E~0); 203203#L711-1 assume !(0 == ~T6_E~0); 203509#L716-1 assume !(0 == ~E_M~0); 203149#L721-1 assume !(0 == ~E_1~0); 203150#L726-1 assume !(0 == ~E_2~0); 202922#L731-1 assume !(0 == ~E_3~0); 202923#L736-1 assume !(0 == ~E_4~0); 203001#L741-1 assume !(0 == ~E_5~0); 203002#L746-1 assume !(0 == ~E_6~0); 203379#L751-1 havoc activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 203110#L336 assume !(1 == ~m_pc~0); 203046#L336-2 is_master_triggered_~__retres1~0 := 0; 203047#L347 is_master_triggered_#res := is_master_triggered_~__retres1~0; 203106#L348 activate_threads_#t~ret10 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 203024#L851 assume !(0 != activate_threads_~tmp~1); 203025#L851-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 203027#L355 assume !(1 == ~t1_pc~0); 203340#L355-2 is_transmit1_triggered_~__retres1~1 := 0; 203337#L366 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 202999#L367 activate_threads_#t~ret11 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 203000#L859 assume !(0 != activate_threads_~tmp___0~0); 203501#L859-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 203502#L374 assume !(1 == ~t2_pc~0); 203528#L374-2 is_transmit2_triggered_~__retres1~2 := 0; 203529#L385 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 203264#L386 activate_threads_#t~ret12 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 203265#L867 assume !(0 != activate_threads_~tmp___1~0); 203689#L867-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 203691#L393 assume !(1 == ~t3_pc~0); 203677#L393-2 is_transmit3_triggered_~__retres1~3 := 0; 203706#L404 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 203674#L405 activate_threads_#t~ret13 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 203154#L875 assume !(0 != activate_threads_~tmp___2~0); 203138#L875-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 203139#L412 assume !(1 == ~t4_pc~0); 203177#L412-2 is_transmit4_triggered_~__retres1~4 := 0; 203176#L423 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 203091#L424 activate_threads_#t~ret14 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 203092#L883 assume !(0 != activate_threads_~tmp___3~0); 203397#L883-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 203196#L431 assume !(1 == ~t5_pc~0); 203182#L431-2 is_transmit5_triggered_~__retres1~5 := 0; 203183#L442 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 203195#L443 activate_threads_#t~ret15 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 203376#L891 assume !(0 != activate_threads_~tmp___4~0); 203576#L891-2 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 203445#L450 assume !(1 == ~t6_pc~0); 203446#L450-2 is_transmit6_triggered_~__retres1~6 := 0; 203443#L461 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 203444#L462 activate_threads_#t~ret16 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 203557#L899 assume !(0 != activate_threads_~tmp___5~0); 203582#L899-2 assume !(1 == ~M_E~0); 202918#L764-1 assume !(1 == ~T1_E~0); 202919#L769-1 assume !(1 == ~T2_E~0); 203030#L774-1 assume !(1 == ~T3_E~0); 203031#L779-1 assume !(1 == ~T4_E~0); 203398#L784-1 assume !(1 == ~T5_E~0); 203399#L789-1 assume !(1 == ~T6_E~0); 203198#L794-1 assume !(1 == ~E_M~0); 203199#L799-1 assume !(1 == ~E_1~0); 203503#L804-1 assume !(1 == ~E_2~0); 203140#L809-1 assume !(1 == ~E_3~0); 203141#L814-1 assume !(1 == ~E_4~0); 202916#L819-1 assume !(1 == ~E_5~0); 202917#L824-1 assume !(1 == ~E_6~0); 203452#L1055-1 [2018-11-23 01:26:50,316 INFO L796 eck$LassoCheckResult]: Loop: 203452#L1055-1 assume !false; 210585#L1056 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret2, eval_#t~nondet3, eval_~tmp_ndt_1~0, eval_#t~nondet4, eval_~tmp_ndt_2~0, eval_#t~nondet5, eval_~tmp_ndt_3~0, eval_#t~nondet6, eval_~tmp_ndt_4~0, eval_#t~nondet7, eval_~tmp_ndt_5~0, eval_#t~nondet8, eval_~tmp_ndt_6~0, eval_#t~nondet9, eval_~tmp_ndt_7~0, eval_~tmp~0;havoc eval_~tmp~0; 207327#L661 assume !false; 210582#L568 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~7;havoc exists_runnable_thread_~__retres1~7; 210581#L520 assume !(0 == ~m_st~0); 210579#L524 assume !(0 == ~t1_st~0); 210577#L528 assume !(0 == ~t2_st~0); 210575#L532 assume !(0 == ~t3_st~0); 210573#L536 assume !(0 == ~t4_st~0); 210571#L540 assume !(0 == ~t5_st~0); 210569#L544 assume !(0 == ~t6_st~0);exists_runnable_thread_~__retres1~7 := 0; 210567#L557 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~7; 210565#L558 eval_#t~ret2 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret2;havoc eval_#t~ret2; 210563#L572 assume !(0 != eval_~tmp~0); 210561#L676 start_simulation_~kernel_st~0 := 2; 210559#L470-1 start_simulation_~kernel_st~0 := 3; 210557#L686-2 assume !(0 == ~M_E~0); 210555#L686-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 210553#L691-3 assume !(0 == ~T2_E~0); 210551#L696-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 210549#L701-3 assume !(0 == ~T4_E~0); 210547#L706-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 210545#L711-3 assume !(0 == ~T6_E~0); 210543#L716-3 assume 0 == ~E_M~0;~E_M~0 := 1; 210541#L721-3 assume !(0 == ~E_1~0); 210539#L726-3 assume 0 == ~E_2~0;~E_2~0 := 1; 210537#L731-3 assume !(0 == ~E_3~0); 210535#L736-3 assume 0 == ~E_4~0;~E_4~0 := 1; 210510#L741-3 assume !(0 == ~E_5~0); 210505#L746-3 assume 0 == ~E_6~0;~E_6~0 := 1; 210501#L751-3 havoc activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 203635#L336-24 assume !(1 == ~m_pc~0); 203587#L336-26 is_master_triggered_~__retres1~0 := 0; 203638#L347-8 is_master_triggered_#res := is_master_triggered_~__retres1~0; 203584#L348-8 activate_threads_#t~ret10 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 202950#L851-24 assume !(0 != activate_threads_~tmp~1); 202924#L851-26 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 202925#L355-24 assume !(1 == ~t1_pc~0); 202981#L355-26 is_transmit1_triggered_~__retres1~1 := 0; 202982#L366-8 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 203331#L367-8 activate_threads_#t~ret11 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 210711#L859-24 assume !(0 != activate_threads_~tmp___0~0); 210710#L859-26 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 210708#L374-24 assume !(1 == ~t2_pc~0); 210706#L374-26 is_transmit2_triggered_~__retres1~2 := 0; 210704#L385-8 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 210702#L386-8 activate_threads_#t~ret12 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 210701#L867-24 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 210700#L867-26 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 203684#L393-24 assume !(1 == ~t3_pc~0); 203469#L393-26 is_transmit3_triggered_~__retres1~3 := 0; 203688#L404-8 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 203466#L405-8 activate_threads_#t~ret13 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 203467#L875-24 assume !(0 != activate_threads_~tmp___2~0); 203662#L875-26 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 203119#L412-24 assume !(1 == ~t4_pc~0); 203120#L412-26 is_transmit4_triggered_~__retres1~4 := 0; 203130#L423-8 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 203077#L424-8 activate_threads_#t~ret14 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 203078#L883-24 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 203294#L883-26 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 203295#L431-24 assume !(1 == ~t5_pc~0); 203323#L431-26 is_transmit5_triggered_~__retres1~5 := 0; 203322#L442-8 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 203319#L443-8 activate_threads_#t~ret15 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 203320#L891-24 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 203522#L891-26 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 203525#L450-24 assume !(1 == ~t6_pc~0); 203568#L450-26 is_transmit6_triggered_~__retres1~6 := 0; 203439#L461-8 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 203440#L462-8 activate_threads_#t~ret16 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 203546#L899-24 assume 0 != activate_threads_~tmp___5~0;~t6_st~0 := 0; 203693#L899-26 assume !(1 == ~M_E~0); 202904#L764-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 202905#L769-3 assume !(1 == ~T2_E~0); 203006#L774-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 203007#L779-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 203381#L784-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 203382#L789-3 assume !(1 == ~T6_E~0); 203200#L794-3 assume 1 == ~E_M~0;~E_M~0 := 2; 203201#L799-3 assume !(1 == ~E_1~0); 203506#L804-3 assume 1 == ~E_2~0;~E_2~0 := 2; 203146#L809-3 assume !(1 == ~E_3~0); 203147#L814-3 assume 1 == ~E_4~0;~E_4~0 := 2; 202920#L819-3 assume 1 == ~E_5~0;~E_5~0 := 2; 202921#L824-3 assume 1 == ~E_6~0;~E_6~0 := 2; 203032#L829-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~7;havoc exists_runnable_thread_~__retres1~7; 203033#L520-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7 := 1; 202915#L557-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~7; 203637#L558-1 start_simulation_#t~ret18 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret18;havoc start_simulation_#t~ret18; 203665#L1074 assume !(0 == start_simulation_~tmp~3); 203666#L1074-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret17, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~7;havoc exists_runnable_thread_~__retres1~7; 210610#L520-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7 := 1; 210604#L557-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~7; 210596#L558-2 stop_simulation_#t~ret17 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret17;havoc stop_simulation_#t~ret17; 210594#L1029 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 210592#L1036 stop_simulation_#res := stop_simulation_~__retres2~0; 210590#L1037 start_simulation_#t~ret19 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret19;havoc start_simulation_#t~ret19; 210588#L1087 assume !(0 != start_simulation_~tmp___0~1); 203452#L1055-1 [2018-11-23 01:26:50,316 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 01:26:50,316 INFO L82 PathProgramCache]: Analyzing trace with hash -800641180, now seen corresponding path program 6 times [2018-11-23 01:26:50,316 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 01:26:50,316 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 01:26:50,317 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 01:26:50,317 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 01:26:50,317 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 01:26:50,322 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-23 01:26:50,327 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-23 01:26:50,341 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 01:26:50,341 INFO L82 PathProgramCache]: Analyzing trace with hash -1103295994, now seen corresponding path program 1 times [2018-11-23 01:26:50,341 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 01:26:50,341 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 01:26:50,342 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 01:26:50,342 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-23 01:26:50,342 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 01:26:50,346 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 01:26:50,366 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 01:26:50,367 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 01:26:50,367 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-23 01:26:50,367 INFO L811 eck$LassoCheckResult]: loop already infeasible [2018-11-23 01:26:50,367 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-23 01:26:50,367 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-23 01:26:50,367 INFO L87 Difference]: Start difference. First operand 7894 states and 10783 transitions. cyclomatic complexity: 2905 Second operand 3 states. [2018-11-23 01:26:50,425 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 01:26:50,425 INFO L93 Difference]: Finished difference Result 14630 states and 19659 transitions. [2018-11-23 01:26:50,427 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-23 01:26:50,427 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 14630 states and 19659 transitions. [2018-11-23 01:26:50,459 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 14416 [2018-11-23 01:26:50,480 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 14630 states to 14630 states and 19659 transitions. [2018-11-23 01:26:50,481 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 14630 [2018-11-23 01:26:50,488 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 14630 [2018-11-23 01:26:50,488 INFO L73 IsDeterministic]: Start isDeterministic. Operand 14630 states and 19659 transitions. [2018-11-23 01:26:50,494 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-23 01:26:50,494 INFO L705 BuchiCegarLoop]: Abstraction has 14630 states and 19659 transitions. [2018-11-23 01:26:50,500 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 14630 states and 19659 transitions. [2018-11-23 01:26:50,568 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 14630 to 13950. [2018-11-23 01:26:50,568 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 13950 states. [2018-11-23 01:26:50,584 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 13950 states to 13950 states and 18803 transitions. [2018-11-23 01:26:50,584 INFO L728 BuchiCegarLoop]: Abstraction has 13950 states and 18803 transitions. [2018-11-23 01:26:50,584 INFO L608 BuchiCegarLoop]: Abstraction has 13950 states and 18803 transitions. [2018-11-23 01:26:50,585 INFO L442 BuchiCegarLoop]: ======== Iteration 23============ [2018-11-23 01:26:50,585 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 13950 states and 18803 transitions. [2018-11-23 01:26:50,614 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 13736 [2018-11-23 01:26:50,614 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-23 01:26:50,614 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-23 01:26:50,615 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 01:26:50,615 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 01:26:50,616 INFO L794 eck$LassoCheckResult]: Stem: 226059#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0; 225946#L-1 havoc main_#res;havoc main_~__retres1~8;havoc main_~__retres1~8;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 225692#L1018 havoc start_simulation_#t~ret18, start_simulation_#t~ret19, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 225693#L470 assume 1 == ~m_i~0;~m_st~0 := 0; 225526#L477-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 225527#L482-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 225893#L487-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 225894#L492-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 225721#L497-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 225722#L502-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 225815#L507-1 assume !(0 == ~M_E~0); 225542#L686-1 assume !(0 == ~T1_E~0); 225543#L691-1 assume !(0 == ~T2_E~0); 225907#L696-1 assume !(0 == ~T3_E~0); 225908#L701-1 assume !(0 == ~T4_E~0); 225730#L706-1 assume !(0 == ~T5_E~0); 225731#L711-1 assume !(0 == ~T6_E~0); 226028#L716-1 assume !(0 == ~E_M~0); 225682#L721-1 assume !(0 == ~E_1~0); 225683#L726-1 assume !(0 == ~E_2~0); 225452#L731-1 assume !(0 == ~E_3~0); 225453#L736-1 assume !(0 == ~E_4~0); 225533#L741-1 assume !(0 == ~E_5~0); 225534#L746-1 assume !(0 == ~E_6~0); 225902#L751-1 havoc activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 225644#L336 assume !(1 == ~m_pc~0); 225580#L336-2 is_master_triggered_~__retres1~0 := 0; 225581#L347 is_master_triggered_#res := is_master_triggered_~__retres1~0; 225640#L348 activate_threads_#t~ret10 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 225557#L851 assume !(0 != activate_threads_~tmp~1); 225558#L851-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 225560#L355 assume !(1 == ~t1_pc~0); 225860#L355-2 is_transmit1_triggered_~__retres1~1 := 0; 225857#L366 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 225531#L367 activate_threads_#t~ret11 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 225532#L859 assume !(0 != activate_threads_~tmp___0~0); 226021#L859-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 226022#L374 assume !(1 == ~t2_pc~0); 226052#L374-2 is_transmit2_triggered_~__retres1~2 := 0; 226053#L385 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 225791#L386 activate_threads_#t~ret12 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 225792#L867 assume !(0 != activate_threads_~tmp___1~0); 226197#L867-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 226199#L393 assume !(1 == ~t3_pc~0); 226188#L393-2 is_transmit3_triggered_~__retres1~3 := 0; 226214#L404 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 226185#L405 activate_threads_#t~ret13 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 225687#L875 assume !(0 != activate_threads_~tmp___2~0); 225672#L875-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 225673#L412 assume !(1 == ~t4_pc~0); 225705#L412-2 is_transmit4_triggered_~__retres1~4 := 0; 225704#L423 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 225625#L424 activate_threads_#t~ret14 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 225626#L883 assume !(0 != activate_threads_~tmp___3~0); 225919#L883-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 225724#L431 assume !(1 == ~t5_pc~0); 225710#L431-2 is_transmit5_triggered_~__retres1~5 := 0; 225711#L442 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 225723#L443 activate_threads_#t~ret15 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 225897#L891 assume !(0 != activate_threads_~tmp___4~0); 226104#L891-2 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 225966#L450 assume !(1 == ~t6_pc~0); 225967#L450-2 is_transmit6_triggered_~__retres1~6 := 0; 225964#L461 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 225965#L462 activate_threads_#t~ret16 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 226076#L899 assume !(0 != activate_threads_~tmp___5~0); 226106#L899-2 assume !(1 == ~M_E~0); 225448#L764-1 assume !(1 == ~T1_E~0); 225449#L769-1 assume !(1 == ~T2_E~0); 225564#L774-1 assume !(1 == ~T3_E~0); 225565#L779-1 assume !(1 == ~T4_E~0); 225920#L784-1 assume !(1 == ~T5_E~0); 225921#L789-1 assume !(1 == ~T6_E~0); 225726#L794-1 assume !(1 == ~E_M~0); 225727#L799-1 assume !(1 == ~E_1~0); 226023#L804-1 assume !(1 == ~E_2~0); 225674#L809-1 assume !(1 == ~E_3~0); 225675#L814-1 assume !(1 == ~E_4~0); 225446#L819-1 assume !(1 == ~E_5~0); 225447#L824-1 assume !(1 == ~E_6~0); 225973#L1055-1 [2018-11-23 01:26:50,616 INFO L796 eck$LassoCheckResult]: Loop: 225973#L1055-1 assume !false; 228618#L1056 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret2, eval_#t~nondet3, eval_~tmp_ndt_1~0, eval_#t~nondet4, eval_~tmp_ndt_2~0, eval_#t~nondet5, eval_~tmp_ndt_3~0, eval_#t~nondet6, eval_~tmp_ndt_4~0, eval_#t~nondet7, eval_~tmp_ndt_5~0, eval_#t~nondet8, eval_~tmp_ndt_6~0, eval_#t~nondet9, eval_~tmp_ndt_7~0, eval_~tmp~0;havoc eval_~tmp~0; 228616#L661 assume !false; 228614#L568 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~7;havoc exists_runnable_thread_~__retres1~7; 228611#L520 assume !(0 == ~m_st~0); 228612#L524 assume !(0 == ~t1_st~0); 229167#L528 assume !(0 == ~t2_st~0); 229163#L532 assume !(0 == ~t3_st~0); 229161#L536 assume !(0 == ~t4_st~0); 229159#L540 assume !(0 == ~t5_st~0); 229152#L544 assume !(0 == ~t6_st~0);exists_runnable_thread_~__retres1~7 := 0; 229150#L557 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~7; 229148#L558 eval_#t~ret2 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret2;havoc eval_#t~ret2; 229146#L572 assume !(0 != eval_~tmp~0); 229144#L676 start_simulation_~kernel_st~0 := 2; 229142#L470-1 start_simulation_~kernel_st~0 := 3; 229140#L686-2 assume !(0 == ~M_E~0); 229138#L686-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 229137#L691-3 assume !(0 == ~T2_E~0); 229136#L696-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 229135#L701-3 assume !(0 == ~T4_E~0); 229134#L706-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 229133#L711-3 assume !(0 == ~T6_E~0); 229132#L716-3 assume 0 == ~E_M~0;~E_M~0 := 1; 229131#L721-3 assume !(0 == ~E_1~0); 229130#L726-3 assume 0 == ~E_2~0;~E_2~0 := 1; 229128#L731-3 assume !(0 == ~E_3~0); 229126#L736-3 assume 0 == ~E_4~0;~E_4~0 := 1; 229124#L741-3 assume !(0 == ~E_5~0); 229123#L746-3 assume 0 == ~E_6~0;~E_6~0 := 1; 229121#L751-3 havoc activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 229119#L336-24 assume 1 == ~m_pc~0; 229116#L337-8 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 229114#L347-8 is_master_triggered_#res := is_master_triggered_~__retres1~0; 229112#L348-8 activate_threads_#t~ret10 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 229109#L851-24 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 229107#L851-26 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 229104#L355-24 assume !(1 == ~t1_pc~0); 229102#L355-26 is_transmit1_triggered_~__retres1~1 := 0; 229100#L366-8 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 229098#L367-8 activate_threads_#t~ret11 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 229096#L859-24 assume !(0 != activate_threads_~tmp___0~0); 229093#L859-26 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 229091#L374-24 assume !(1 == ~t2_pc~0); 229089#L374-26 is_transmit2_triggered_~__retres1~2 := 0; 229087#L385-8 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 229085#L386-8 activate_threads_#t~ret12 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 229083#L867-24 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 229081#L867-26 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 229079#L393-24 assume !(1 == ~t3_pc~0); 229076#L393-26 is_transmit3_triggered_~__retres1~3 := 0; 229074#L404-8 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 229072#L405-8 activate_threads_#t~ret13 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 229070#L875-24 assume !(0 != activate_threads_~tmp___2~0); 229068#L875-26 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 229065#L412-24 assume !(1 == ~t4_pc~0); 229063#L412-26 is_transmit4_triggered_~__retres1~4 := 0; 229061#L423-8 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 229059#L424-8 activate_threads_#t~ret14 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 229057#L883-24 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 229055#L883-26 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 229053#L431-24 assume !(1 == ~t5_pc~0); 229051#L431-26 is_transmit5_triggered_~__retres1~5 := 0; 229048#L442-8 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 229046#L443-8 activate_threads_#t~ret15 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 229044#L891-24 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 229043#L891-26 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 229041#L450-24 assume !(1 == ~t6_pc~0); 229037#L450-26 is_transmit6_triggered_~__retres1~6 := 0; 229035#L461-8 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 229033#L462-8 activate_threads_#t~ret16 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 229031#L899-24 assume 0 != activate_threads_~tmp___5~0;~t6_st~0 := 0; 229030#L899-26 assume !(1 == ~M_E~0); 229028#L764-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 229026#L769-3 assume !(1 == ~T2_E~0); 229024#L774-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 229022#L779-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 229019#L784-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 229017#L789-3 assume !(1 == ~T6_E~0); 229015#L794-3 assume 1 == ~E_M~0;~E_M~0 := 2; 229013#L799-3 assume !(1 == ~E_1~0); 229011#L804-3 assume 1 == ~E_2~0;~E_2~0 := 2; 229009#L809-3 assume !(1 == ~E_3~0); 229007#L814-3 assume 1 == ~E_4~0;~E_4~0 := 2; 229005#L819-3 assume 1 == ~E_5~0;~E_5~0 := 2; 229003#L824-3 assume 1 == ~E_6~0;~E_6~0 := 2; 229001#L829-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~7;havoc exists_runnable_thread_~__retres1~7; 228998#L520-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7 := 1; 228996#L557-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~7; 228994#L558-1 start_simulation_#t~ret18 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret18;havoc start_simulation_#t~ret18; 228991#L1074 assume !(0 == start_simulation_~tmp~3); 228988#L1074-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret17, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~7;havoc exists_runnable_thread_~__retres1~7; 228985#L520-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7 := 1; 228983#L557-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~7; 228981#L558-2 stop_simulation_#t~ret17 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret17;havoc stop_simulation_#t~ret17; 228979#L1029 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 228977#L1036 stop_simulation_#res := stop_simulation_~__retres2~0; 228975#L1037 start_simulation_#t~ret19 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret19;havoc start_simulation_#t~ret19; 228973#L1087 assume !(0 != start_simulation_~tmp___0~1); 225973#L1055-1 [2018-11-23 01:26:50,616 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 01:26:50,616 INFO L82 PathProgramCache]: Analyzing trace with hash -800641180, now seen corresponding path program 7 times [2018-11-23 01:26:50,616 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 01:26:50,617 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 01:26:50,617 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 01:26:50,617 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 01:26:50,618 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 01:26:50,622 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-23 01:26:50,628 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-23 01:26:50,641 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 01:26:50,642 INFO L82 PathProgramCache]: Analyzing trace with hash 1408251177, now seen corresponding path program 1 times [2018-11-23 01:26:50,642 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 01:26:50,642 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 01:26:50,642 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 01:26:50,643 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 01:26:50,643 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 01:26:50,648 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 01:26:50,727 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 01:26:50,727 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 01:26:50,727 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-11-23 01:26:50,727 INFO L811 eck$LassoCheckResult]: loop already infeasible [2018-11-23 01:26:50,727 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-11-23 01:26:50,727 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-11-23 01:26:50,728 INFO L87 Difference]: Start difference. First operand 13950 states and 18803 transitions. cyclomatic complexity: 4869 Second operand 5 states. [2018-11-23 01:26:50,913 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 01:26:50,913 INFO L93 Difference]: Finished difference Result 26014 states and 35018 transitions. [2018-11-23 01:26:50,914 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2018-11-23 01:26:50,914 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 26014 states and 35018 transitions. [2018-11-23 01:26:50,972 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 25704 [2018-11-23 01:26:51,011 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 26014 states to 26014 states and 35018 transitions. [2018-11-23 01:26:51,011 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 26014 [2018-11-23 01:26:51,022 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 26014 [2018-11-23 01:26:51,023 INFO L73 IsDeterministic]: Start isDeterministic. Operand 26014 states and 35018 transitions. [2018-11-23 01:26:51,032 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-23 01:26:51,032 INFO L705 BuchiCegarLoop]: Abstraction has 26014 states and 35018 transitions. [2018-11-23 01:26:51,043 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 26014 states and 35018 transitions. [2018-11-23 01:26:51,129 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 26014 to 14286. [2018-11-23 01:26:51,129 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 14286 states. [2018-11-23 01:26:51,143 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 14286 states to 14286 states and 19042 transitions. [2018-11-23 01:26:51,143 INFO L728 BuchiCegarLoop]: Abstraction has 14286 states and 19042 transitions. [2018-11-23 01:26:51,143 INFO L608 BuchiCegarLoop]: Abstraction has 14286 states and 19042 transitions. [2018-11-23 01:26:51,143 INFO L442 BuchiCegarLoop]: ======== Iteration 24============ [2018-11-23 01:26:51,143 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 14286 states and 19042 transitions. [2018-11-23 01:26:51,166 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 14072 [2018-11-23 01:26:51,166 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-23 01:26:51,166 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-23 01:26:51,167 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 01:26:51,167 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 01:26:51,167 INFO L794 eck$LassoCheckResult]: Stem: 266033#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0; 265913#L-1 havoc main_#res;havoc main_~__retres1~8;havoc main_~__retres1~8;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 265676#L1018 havoc start_simulation_#t~ret18, start_simulation_#t~ret19, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 265677#L470 assume 1 == ~m_i~0;~m_st~0 := 0; 265504#L477-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 265505#L482-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 265873#L487-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 265874#L492-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 265702#L497-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 265703#L502-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 265803#L507-1 assume !(0 == ~M_E~0); 265520#L686-1 assume !(0 == ~T1_E~0); 265521#L691-1 assume !(0 == ~T2_E~0); 265883#L696-1 assume !(0 == ~T3_E~0); 265884#L701-1 assume !(0 == ~T4_E~0); 265711#L706-1 assume !(0 == ~T5_E~0); 265712#L711-1 assume !(0 == ~T6_E~0); 266001#L716-1 assume !(0 == ~E_M~0); 265659#L721-1 assume !(0 == ~E_1~0); 265660#L726-1 assume !(0 == ~E_2~0); 265430#L731-1 assume !(0 == ~E_3~0); 265431#L736-1 assume !(0 == ~E_4~0); 265510#L741-1 assume !(0 == ~E_5~0); 265511#L746-1 assume !(0 == ~E_6~0); 265878#L751-1 havoc activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 265618#L336 assume !(1 == ~m_pc~0); 265555#L336-2 is_master_triggered_~__retres1~0 := 0; 265556#L347 is_master_triggered_#res := is_master_triggered_~__retres1~0; 265614#L348 activate_threads_#t~ret10 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 265534#L851 assume !(0 != activate_threads_~tmp~1); 265535#L851-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 265537#L355 assume !(1 == ~t1_pc~0); 265844#L355-2 is_transmit1_triggered_~__retres1~1 := 0; 265841#L366 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 265508#L367 activate_threads_#t~ret11 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 265509#L859 assume !(0 != activate_threads_~tmp___0~0); 265993#L859-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 265994#L374 assume !(1 == ~t2_pc~0); 266025#L374-2 is_transmit2_triggered_~__retres1~2 := 0; 266026#L385 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 265772#L386 activate_threads_#t~ret12 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 265773#L867 assume !(0 != activate_threads_~tmp___1~0); 266178#L867-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 266180#L393 assume !(1 == ~t3_pc~0); 266167#L393-2 is_transmit3_triggered_~__retres1~3 := 0; 266191#L404 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 266164#L405 activate_threads_#t~ret13 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 265667#L875 assume !(0 != activate_threads_~tmp___2~0); 265646#L875-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 265647#L412 assume !(1 == ~t4_pc~0); 265686#L412-2 is_transmit4_triggered_~__retres1~4 := 0; 265685#L423 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 265599#L424 activate_threads_#t~ret14 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 265600#L883 assume !(0 != activate_threads_~tmp___3~0); 265894#L883-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 265705#L431 assume !(1 == ~t5_pc~0); 265691#L431-2 is_transmit5_triggered_~__retres1~5 := 0; 265692#L442 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 265704#L443 activate_threads_#t~ret15 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 265875#L891 assume !(0 != activate_threads_~tmp___4~0); 266089#L891-2 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 265934#L450 assume !(1 == ~t6_pc~0); 265935#L450-2 is_transmit6_triggered_~__retres1~6 := 0; 265932#L461 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 265933#L462 activate_threads_#t~ret16 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 266058#L899 assume !(0 != activate_threads_~tmp___5~0); 266094#L899-2 assume !(1 == ~M_E~0); 265426#L764-1 assume !(1 == ~T1_E~0); 265427#L769-1 assume !(1 == ~T2_E~0); 265539#L774-1 assume !(1 == ~T3_E~0); 265540#L779-1 assume !(1 == ~T4_E~0); 265895#L784-1 assume !(1 == ~T5_E~0); 265896#L789-1 assume !(1 == ~T6_E~0); 265707#L794-1 assume !(1 == ~E_M~0); 265708#L799-1 assume !(1 == ~E_1~0); 265995#L804-1 assume !(1 == ~E_2~0); 265648#L809-1 assume !(1 == ~E_3~0); 265649#L814-1 assume !(1 == ~E_4~0); 265424#L819-1 assume !(1 == ~E_5~0); 265425#L824-1 assume !(1 == ~E_6~0); 265940#L1055-1 [2018-11-23 01:26:51,168 INFO L796 eck$LassoCheckResult]: Loop: 265940#L1055-1 assume !false; 268700#L1056 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret2, eval_#t~nondet3, eval_~tmp_ndt_1~0, eval_#t~nondet4, eval_~tmp_ndt_2~0, eval_#t~nondet5, eval_~tmp_ndt_3~0, eval_#t~nondet6, eval_~tmp_ndt_4~0, eval_#t~nondet7, eval_~tmp_ndt_5~0, eval_#t~nondet8, eval_~tmp_ndt_6~0, eval_#t~nondet9, eval_~tmp_ndt_7~0, eval_~tmp~0;havoc eval_~tmp~0; 268698#L661 assume !false; 268695#L568 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~7;havoc exists_runnable_thread_~__retres1~7; 268692#L520 assume !(0 == ~m_st~0); 268693#L524 assume !(0 == ~t1_st~0); 269172#L528 assume !(0 == ~t2_st~0); 269170#L532 assume !(0 == ~t3_st~0); 269169#L536 assume !(0 == ~t4_st~0); 269168#L540 assume !(0 == ~t5_st~0); 269165#L544 assume !(0 == ~t6_st~0);exists_runnable_thread_~__retres1~7 := 0; 269162#L557 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~7; 269160#L558 eval_#t~ret2 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret2;havoc eval_#t~ret2; 269158#L572 assume !(0 != eval_~tmp~0); 269153#L676 start_simulation_~kernel_st~0 := 2; 269151#L470-1 start_simulation_~kernel_st~0 := 3; 269149#L686-2 assume !(0 == ~M_E~0); 269147#L686-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 269145#L691-3 assume !(0 == ~T2_E~0); 269143#L696-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 269141#L701-3 assume !(0 == ~T4_E~0); 269139#L706-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 269137#L711-3 assume !(0 == ~T6_E~0); 269135#L716-3 assume 0 == ~E_M~0;~E_M~0 := 1; 269133#L721-3 assume !(0 == ~E_1~0); 269131#L726-3 assume 0 == ~E_2~0;~E_2~0 := 1; 269129#L731-3 assume !(0 == ~E_3~0); 269127#L736-3 assume 0 == ~E_4~0;~E_4~0 := 1; 269124#L741-3 assume !(0 == ~E_5~0); 269122#L746-3 assume 0 == ~E_6~0;~E_6~0 := 1; 269120#L751-3 havoc activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 269118#L336-24 assume 1 == ~m_pc~0; 269115#L337-8 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 269113#L347-8 is_master_triggered_#res := is_master_triggered_~__retres1~0; 269111#L348-8 activate_threads_#t~ret10 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 269108#L851-24 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 269106#L851-26 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 269104#L355-24 assume !(1 == ~t1_pc~0); 269102#L355-26 is_transmit1_triggered_~__retres1~1 := 0; 269100#L366-8 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 269098#L367-8 activate_threads_#t~ret11 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 269095#L859-24 assume !(0 != activate_threads_~tmp___0~0); 269093#L859-26 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 269091#L374-24 assume !(1 == ~t2_pc~0); 269089#L374-26 is_transmit2_triggered_~__retres1~2 := 0; 269087#L385-8 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 269085#L386-8 activate_threads_#t~ret12 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 269083#L867-24 assume !(0 != activate_threads_~tmp___1~0); 269081#L867-26 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 269079#L393-24 assume !(1 == ~t3_pc~0); 269076#L393-26 is_transmit3_triggered_~__retres1~3 := 0; 269074#L404-8 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 269072#L405-8 activate_threads_#t~ret13 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 269070#L875-24 assume !(0 != activate_threads_~tmp___2~0); 269068#L875-26 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 269066#L412-24 assume !(1 == ~t4_pc~0); 269064#L412-26 is_transmit4_triggered_~__retres1~4 := 0; 269062#L423-8 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 269060#L424-8 activate_threads_#t~ret14 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 269058#L883-24 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 269056#L883-26 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 269054#L431-24 assume !(1 == ~t5_pc~0); 269052#L431-26 is_transmit5_triggered_~__retres1~5 := 0; 269049#L442-8 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 269048#L443-8 activate_threads_#t~ret15 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 269047#L891-24 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 269045#L891-26 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 269043#L450-24 assume !(1 == ~t6_pc~0); 269041#L450-26 is_transmit6_triggered_~__retres1~6 := 0; 269040#L461-8 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 269038#L462-8 activate_threads_#t~ret16 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 269036#L899-24 assume 0 != activate_threads_~tmp___5~0;~t6_st~0 := 0; 269034#L899-26 assume !(1 == ~M_E~0); 269032#L764-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 269030#L769-3 assume !(1 == ~T2_E~0); 269028#L774-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 269026#L779-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 269024#L784-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 269022#L789-3 assume !(1 == ~T6_E~0); 269020#L794-3 assume 1 == ~E_M~0;~E_M~0 := 2; 269018#L799-3 assume !(1 == ~E_1~0); 269016#L804-3 assume 1 == ~E_2~0;~E_2~0 := 2; 269015#L809-3 assume !(1 == ~E_3~0); 269012#L814-3 assume 1 == ~E_4~0;~E_4~0 := 2; 269010#L819-3 assume 1 == ~E_5~0;~E_5~0 := 2; 269008#L824-3 assume 1 == ~E_6~0;~E_6~0 := 2; 269006#L829-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~7;havoc exists_runnable_thread_~__retres1~7; 269003#L520-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7 := 1; 269001#L557-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~7; 268999#L558-1 start_simulation_#t~ret18 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret18;havoc start_simulation_#t~ret18; 268996#L1074 assume !(0 == start_simulation_~tmp~3); 268993#L1074-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret17, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~7;havoc exists_runnable_thread_~__retres1~7; 268990#L520-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7 := 1; 268988#L557-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~7; 268986#L558-2 stop_simulation_#t~ret17 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret17;havoc stop_simulation_#t~ret17; 268984#L1029 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 268981#L1036 stop_simulation_#res := stop_simulation_~__retres2~0; 268979#L1037 start_simulation_#t~ret19 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret19;havoc start_simulation_#t~ret19; 268977#L1087 assume !(0 != start_simulation_~tmp___0~1); 265940#L1055-1 [2018-11-23 01:26:51,168 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 01:26:51,168 INFO L82 PathProgramCache]: Analyzing trace with hash -800641180, now seen corresponding path program 8 times [2018-11-23 01:26:51,168 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 01:26:51,168 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 01:26:51,169 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 01:26:51,169 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 01:26:51,169 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 01:26:51,175 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-23 01:26:51,180 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-23 01:26:51,193 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 01:26:51,193 INFO L82 PathProgramCache]: Analyzing trace with hash -1348376089, now seen corresponding path program 1 times [2018-11-23 01:26:51,193 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 01:26:51,193 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 01:26:51,194 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 01:26:51,194 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-23 01:26:51,194 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 01:26:51,199 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 01:26:51,256 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 01:26:51,256 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 01:26:51,256 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-11-23 01:26:51,257 INFO L811 eck$LassoCheckResult]: loop already infeasible [2018-11-23 01:26:51,257 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-11-23 01:26:51,257 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-11-23 01:26:51,257 INFO L87 Difference]: Start difference. First operand 14286 states and 19042 transitions. cyclomatic complexity: 4772 Second operand 5 states. [2018-11-23 01:26:51,459 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 01:26:51,459 INFO L93 Difference]: Finished difference Result 24942 states and 33405 transitions. [2018-11-23 01:26:51,462 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2018-11-23 01:26:51,462 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 24942 states and 33405 transitions. [2018-11-23 01:26:51,531 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 24632 [2018-11-23 01:26:51,569 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 24942 states to 24942 states and 33405 transitions. [2018-11-23 01:26:51,569 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 24942 [2018-11-23 01:26:51,580 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 24942 [2018-11-23 01:26:51,580 INFO L73 IsDeterministic]: Start isDeterministic. Operand 24942 states and 33405 transitions. [2018-11-23 01:26:51,590 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-23 01:26:51,590 INFO L705 BuchiCegarLoop]: Abstraction has 24942 states and 33405 transitions. [2018-11-23 01:26:51,600 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 24942 states and 33405 transitions. [2018-11-23 01:26:51,680 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 24942 to 14622. [2018-11-23 01:26:51,681 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 14622 states. [2018-11-23 01:26:51,694 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 14622 states to 14622 states and 19281 transitions. [2018-11-23 01:26:51,694 INFO L728 BuchiCegarLoop]: Abstraction has 14622 states and 19281 transitions. [2018-11-23 01:26:51,694 INFO L608 BuchiCegarLoop]: Abstraction has 14622 states and 19281 transitions. [2018-11-23 01:26:51,694 INFO L442 BuchiCegarLoop]: ======== Iteration 25============ [2018-11-23 01:26:51,694 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 14622 states and 19281 transitions. [2018-11-23 01:26:51,719 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 14408 [2018-11-23 01:26:51,719 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-23 01:26:51,719 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-23 01:26:51,720 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 01:26:51,720 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 01:26:51,721 INFO L794 eck$LassoCheckResult]: Stem: 305287#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0; 305173#L-1 havoc main_#res;havoc main_~__retres1~8;havoc main_~__retres1~8;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 304924#L1018 havoc start_simulation_#t~ret18, start_simulation_#t~ret19, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 304925#L470 assume 1 == ~m_i~0;~m_st~0 := 0; 304746#L477-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 304747#L482-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 305126#L487-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 305127#L492-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 304956#L497-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 304957#L502-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 305051#L507-1 assume !(0 == ~M_E~0); 304762#L686-1 assume !(0 == ~T1_E~0); 304763#L691-1 assume !(0 == ~T2_E~0); 305139#L696-1 assume !(0 == ~T3_E~0); 305140#L701-1 assume !(0 == ~T4_E~0); 304965#L706-1 assume !(0 == ~T5_E~0); 304966#L711-1 assume !(0 == ~T6_E~0); 305257#L716-1 assume !(0 == ~E_M~0); 304901#L721-1 assume !(0 == ~E_1~0); 304902#L726-1 assume !(0 == ~E_2~0); 304672#L731-1 assume !(0 == ~E_3~0); 304673#L736-1 assume !(0 == ~E_4~0); 304752#L741-1 assume !(0 == ~E_5~0); 304753#L746-1 assume !(0 == ~E_6~0); 305133#L751-1 havoc activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 304861#L336 assume !(1 == ~m_pc~0); 304798#L336-2 is_master_triggered_~__retres1~0 := 0; 304799#L347 is_master_triggered_#res := is_master_triggered_~__retres1~0; 304857#L348 activate_threads_#t~ret10 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 304776#L851 assume !(0 != activate_threads_~tmp~1); 304777#L851-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 304779#L355 assume !(1 == ~t1_pc~0); 305097#L355-2 is_transmit1_triggered_~__retres1~1 := 0; 305094#L366 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 304750#L367 activate_threads_#t~ret11 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 304751#L859 assume !(0 != activate_threads_~tmp___0~0); 305248#L859-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 305249#L374 assume !(1 == ~t2_pc~0); 305280#L374-2 is_transmit2_triggered_~__retres1~2 := 0; 305281#L385 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 305026#L386 activate_threads_#t~ret12 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 305027#L867 assume !(0 != activate_threads_~tmp___1~0); 305400#L867-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 305402#L393 assume !(1 == ~t3_pc~0); 305392#L393-2 is_transmit3_triggered_~__retres1~3 := 0; 305412#L404 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 305389#L405 activate_threads_#t~ret13 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 304912#L875 assume !(0 != activate_threads_~tmp___2~0); 304889#L875-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 304890#L412 assume !(1 == ~t4_pc~0); 304939#L412-2 is_transmit4_triggered_~__retres1~4 := 0; 304938#L423 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 304842#L424 activate_threads_#t~ret14 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 304843#L883 assume !(0 != activate_threads_~tmp___3~0); 305150#L883-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 304959#L431 assume !(1 == ~t5_pc~0); 304945#L431-2 is_transmit5_triggered_~__retres1~5 := 0; 304946#L442 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 304958#L443 activate_threads_#t~ret15 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 305130#L891 assume !(0 != activate_threads_~tmp___4~0); 305326#L891-2 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 305194#L450 assume !(1 == ~t6_pc~0); 305195#L450-2 is_transmit6_triggered_~__retres1~6 := 0; 305192#L461 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 305193#L462 activate_threads_#t~ret16 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 305306#L899 assume !(0 != activate_threads_~tmp___5~0); 305330#L899-2 assume !(1 == ~M_E~0); 304668#L764-1 assume !(1 == ~T1_E~0); 304669#L769-1 assume !(1 == ~T2_E~0); 304782#L774-1 assume !(1 == ~T3_E~0); 304783#L779-1 assume !(1 == ~T4_E~0); 305152#L784-1 assume !(1 == ~T5_E~0); 305153#L789-1 assume !(1 == ~T6_E~0); 304961#L794-1 assume !(1 == ~E_M~0); 304962#L799-1 assume !(1 == ~E_1~0); 305250#L804-1 assume !(1 == ~E_2~0); 304891#L809-1 assume !(1 == ~E_3~0); 304892#L814-1 assume !(1 == ~E_4~0); 304666#L819-1 assume !(1 == ~E_5~0); 304667#L824-1 assume !(1 == ~E_6~0); 305201#L1055-1 [2018-11-23 01:26:51,721 INFO L796 eck$LassoCheckResult]: Loop: 305201#L1055-1 assume !false; 307241#L1056 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret2, eval_#t~nondet3, eval_~tmp_ndt_1~0, eval_#t~nondet4, eval_~tmp_ndt_2~0, eval_#t~nondet5, eval_~tmp_ndt_3~0, eval_#t~nondet6, eval_~tmp_ndt_4~0, eval_#t~nondet7, eval_~tmp_ndt_5~0, eval_#t~nondet8, eval_~tmp_ndt_6~0, eval_#t~nondet9, eval_~tmp_ndt_7~0, eval_~tmp~0;havoc eval_~tmp~0; 306981#L661 assume !false; 307238#L568 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~7;havoc exists_runnable_thread_~__retres1~7; 307235#L520 assume !(0 == ~m_st~0); 307236#L524 assume !(0 == ~t1_st~0); 307446#L528 assume !(0 == ~t2_st~0); 307444#L532 assume !(0 == ~t3_st~0); 307441#L536 assume !(0 == ~t4_st~0); 307439#L540 assume !(0 == ~t5_st~0); 307436#L544 assume !(0 == ~t6_st~0);exists_runnable_thread_~__retres1~7 := 0; 307433#L557 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~7; 307431#L558 eval_#t~ret2 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret2;havoc eval_#t~ret2; 307429#L572 assume !(0 != eval_~tmp~0); 307428#L676 start_simulation_~kernel_st~0 := 2; 307427#L470-1 start_simulation_~kernel_st~0 := 3; 307426#L686-2 assume !(0 == ~M_E~0); 307421#L686-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 307419#L691-3 assume !(0 == ~T2_E~0); 307417#L696-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 307415#L701-3 assume !(0 == ~T4_E~0); 307413#L706-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 307411#L711-3 assume !(0 == ~T6_E~0); 307409#L716-3 assume 0 == ~E_M~0;~E_M~0 := 1; 307407#L721-3 assume !(0 == ~E_1~0); 307405#L726-3 assume 0 == ~E_2~0;~E_2~0 := 1; 307403#L731-3 assume !(0 == ~E_3~0); 307401#L736-3 assume 0 == ~E_4~0;~E_4~0 := 1; 307399#L741-3 assume !(0 == ~E_5~0); 307397#L746-3 assume 0 == ~E_6~0;~E_6~0 := 1; 307395#L751-3 havoc activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 307392#L336-24 assume 1 == ~m_pc~0; 307389#L337-8 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 307387#L347-8 is_master_triggered_#res := is_master_triggered_~__retres1~0; 307385#L348-8 activate_threads_#t~ret10 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 307382#L851-24 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 307380#L851-26 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 307378#L355-24 assume !(1 == ~t1_pc~0); 307376#L355-26 is_transmit1_triggered_~__retres1~1 := 0; 307374#L366-8 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 307372#L367-8 activate_threads_#t~ret11 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 307370#L859-24 assume !(0 != activate_threads_~tmp___0~0); 307368#L859-26 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 307366#L374-24 assume !(1 == ~t2_pc~0); 307363#L374-26 is_transmit2_triggered_~__retres1~2 := 0; 307361#L385-8 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 307359#L386-8 activate_threads_#t~ret12 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 307357#L867-24 assume !(0 != activate_threads_~tmp___1~0); 307355#L867-26 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 307353#L393-24 assume !(1 == ~t3_pc~0); 307350#L393-26 is_transmit3_triggered_~__retres1~3 := 0; 307348#L404-8 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 307346#L405-8 activate_threads_#t~ret13 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 307344#L875-24 assume !(0 != activate_threads_~tmp___2~0); 307342#L875-26 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 307340#L412-24 assume !(1 == ~t4_pc~0); 307338#L412-26 is_transmit4_triggered_~__retres1~4 := 0; 307336#L423-8 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 307334#L424-8 activate_threads_#t~ret14 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 307332#L883-24 assume !(0 != activate_threads_~tmp___3~0); 307330#L883-26 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 307328#L431-24 assume 1 == ~t5_pc~0; 307325#L432-8 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 307323#L442-8 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 307321#L443-8 activate_threads_#t~ret15 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 307319#L891-24 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 307317#L891-26 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 307316#L450-24 assume !(1 == ~t6_pc~0); 307315#L450-26 is_transmit6_triggered_~__retres1~6 := 0; 307314#L461-8 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 307311#L462-8 activate_threads_#t~ret16 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 307309#L899-24 assume 0 != activate_threads_~tmp___5~0;~t6_st~0 := 0; 307307#L899-26 assume !(1 == ~M_E~0); 307305#L764-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 307303#L769-3 assume !(1 == ~T2_E~0); 307301#L774-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 307299#L779-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 307297#L784-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 307295#L789-3 assume !(1 == ~T6_E~0); 307293#L794-3 assume 1 == ~E_M~0;~E_M~0 := 2; 307291#L799-3 assume !(1 == ~E_1~0); 307289#L804-3 assume 1 == ~E_2~0;~E_2~0 := 2; 307287#L809-3 assume !(1 == ~E_3~0); 307284#L814-3 assume 1 == ~E_4~0;~E_4~0 := 2; 307282#L819-3 assume 1 == ~E_5~0;~E_5~0 := 2; 307280#L824-3 assume 1 == ~E_6~0;~E_6~0 := 2; 307278#L829-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~7;havoc exists_runnable_thread_~__retres1~7; 307275#L520-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7 := 1; 307273#L557-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~7; 307271#L558-1 start_simulation_#t~ret18 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret18;havoc start_simulation_#t~ret18; 307268#L1074 assume !(0 == start_simulation_~tmp~3); 307265#L1074-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret17, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~7;havoc exists_runnable_thread_~__retres1~7; 307262#L520-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7 := 1; 307258#L557-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~7; 307256#L558-2 stop_simulation_#t~ret17 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret17;havoc stop_simulation_#t~ret17; 307255#L1029 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 307250#L1036 stop_simulation_#res := stop_simulation_~__retres2~0; 307248#L1037 start_simulation_#t~ret19 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret19;havoc start_simulation_#t~ret19; 307245#L1087 assume !(0 != start_simulation_~tmp___0~1); 305201#L1055-1 [2018-11-23 01:26:51,721 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 01:26:51,721 INFO L82 PathProgramCache]: Analyzing trace with hash -800641180, now seen corresponding path program 9 times [2018-11-23 01:26:51,721 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 01:26:51,721 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 01:26:51,722 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 01:26:51,722 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 01:26:51,722 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 01:26:51,727 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-23 01:26:51,731 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-23 01:26:51,744 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 01:26:51,744 INFO L82 PathProgramCache]: Analyzing trace with hash 1051463238, now seen corresponding path program 1 times [2018-11-23 01:26:51,745 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 01:26:51,745 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 01:26:51,745 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 01:26:51,745 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-23 01:26:51,745 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 01:26:51,750 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 01:26:51,846 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 01:26:51,846 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 01:26:51,846 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-11-23 01:26:51,846 INFO L811 eck$LassoCheckResult]: loop already infeasible [2018-11-23 01:26:51,847 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-11-23 01:26:51,847 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-11-23 01:26:51,847 INFO L87 Difference]: Start difference. First operand 14622 states and 19281 transitions. cyclomatic complexity: 4675 Second operand 5 states. [2018-11-23 01:26:52,117 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 01:26:52,117 INFO L93 Difference]: Finished difference Result 23942 states and 31688 transitions. [2018-11-23 01:26:52,118 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2018-11-23 01:26:52,118 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 23942 states and 31688 transitions. [2018-11-23 01:26:52,220 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 23632 [2018-11-23 01:26:52,247 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 23942 states to 23942 states and 31688 transitions. [2018-11-23 01:26:52,247 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 23942 [2018-11-23 01:26:52,257 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 23942 [2018-11-23 01:26:52,257 INFO L73 IsDeterministic]: Start isDeterministic. Operand 23942 states and 31688 transitions. [2018-11-23 01:26:52,265 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-23 01:26:52,265 INFO L705 BuchiCegarLoop]: Abstraction has 23942 states and 31688 transitions. [2018-11-23 01:26:52,274 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 23942 states and 31688 transitions. [2018-11-23 01:26:52,348 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 23942 to 14958. [2018-11-23 01:26:52,348 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 14958 states. [2018-11-23 01:26:52,361 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 14958 states to 14958 states and 19520 transitions. [2018-11-23 01:26:52,361 INFO L728 BuchiCegarLoop]: Abstraction has 14958 states and 19520 transitions. [2018-11-23 01:26:52,362 INFO L608 BuchiCegarLoop]: Abstraction has 14958 states and 19520 transitions. [2018-11-23 01:26:52,362 INFO L442 BuchiCegarLoop]: ======== Iteration 26============ [2018-11-23 01:26:52,362 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 14958 states and 19520 transitions. [2018-11-23 01:26:52,387 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 14744 [2018-11-23 01:26:52,387 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-23 01:26:52,387 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-23 01:26:52,388 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 01:26:52,388 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 01:26:52,388 INFO L794 eck$LassoCheckResult]: Stem: 343851#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0; 343733#L-1 havoc main_#res;havoc main_~__retres1~8;havoc main_~__retres1~8;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 343490#L1018 havoc start_simulation_#t~ret18, start_simulation_#t~ret19, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 343491#L470 assume 1 == ~m_i~0;~m_st~0 := 0; 343321#L477-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 343322#L482-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 343689#L487-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 343690#L492-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 343519#L497-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 343520#L502-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 343616#L507-1 assume !(0 == ~M_E~0); 343339#L686-1 assume !(0 == ~T1_E~0); 343340#L691-1 assume !(0 == ~T2_E~0); 343700#L696-1 assume !(0 == ~T3_E~0); 343701#L701-1 assume !(0 == ~T4_E~0); 343528#L706-1 assume !(0 == ~T5_E~0); 343529#L711-1 assume !(0 == ~T6_E~0); 343821#L716-1 assume !(0 == ~E_M~0); 343474#L721-1 assume !(0 == ~E_1~0); 343475#L726-1 assume !(0 == ~E_2~0); 343250#L731-1 assume !(0 == ~E_3~0); 343251#L736-1 assume !(0 == ~E_4~0); 343327#L741-1 assume !(0 == ~E_5~0); 343328#L746-1 assume !(0 == ~E_6~0); 343696#L751-1 havoc activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 343434#L336 assume !(1 == ~m_pc~0); 343371#L336-2 is_master_triggered_~__retres1~0 := 0; 343372#L347 is_master_triggered_#res := is_master_triggered_~__retres1~0; 343433#L348 activate_threads_#t~ret10 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 343350#L851 assume !(0 != activate_threads_~tmp~1); 343351#L851-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 343353#L355 assume !(1 == ~t1_pc~0); 343657#L355-2 is_transmit1_triggered_~__retres1~1 := 0; 343656#L366 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 343325#L367 activate_threads_#t~ret11 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 343326#L859 assume !(0 != activate_threads_~tmp___0~0); 343813#L859-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 343814#L374 assume !(1 == ~t2_pc~0); 343843#L374-2 is_transmit2_triggered_~__retres1~2 := 0; 343844#L385 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 343591#L386 activate_threads_#t~ret12 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 343592#L867 assume !(0 != activate_threads_~tmp___1~0); 343976#L867-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 343978#L393 assume !(1 == ~t3_pc~0); 343968#L393-2 is_transmit3_triggered_~__retres1~3 := 0; 343992#L404 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 343966#L405 activate_threads_#t~ret13 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 343483#L875 assume !(0 != activate_threads_~tmp___2~0); 343463#L875-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 343464#L412 assume !(1 == ~t4_pc~0); 343503#L412-2 is_transmit4_triggered_~__retres1~4 := 0; 343502#L423 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 343415#L424 activate_threads_#t~ret14 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 343416#L883 assume !(0 != activate_threads_~tmp___3~0); 343712#L883-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 343522#L431 assume !(1 == ~t5_pc~0); 343508#L431-2 is_transmit5_triggered_~__retres1~5 := 0; 343509#L442 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 343521#L443 activate_threads_#t~ret15 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 343691#L891 assume !(0 != activate_threads_~tmp___4~0); 343901#L891-2 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 343754#L450 assume !(1 == ~t6_pc~0); 343755#L450-2 is_transmit6_triggered_~__retres1~6 := 0; 343752#L461 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 343753#L462 activate_threads_#t~ret16 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 343873#L899 assume !(0 != activate_threads_~tmp___5~0); 343908#L899-2 assume !(1 == ~M_E~0); 343246#L764-1 assume !(1 == ~T1_E~0); 343247#L769-1 assume !(1 == ~T2_E~0); 343355#L774-1 assume !(1 == ~T3_E~0); 343356#L779-1 assume !(1 == ~T4_E~0); 343713#L784-1 assume !(1 == ~T5_E~0); 343714#L789-1 assume !(1 == ~T6_E~0); 343524#L794-1 assume !(1 == ~E_M~0); 343525#L799-1 assume !(1 == ~E_1~0); 343815#L804-1 assume !(1 == ~E_2~0); 343468#L809-1 assume !(1 == ~E_3~0); 343469#L814-1 assume !(1 == ~E_4~0); 343244#L819-1 assume !(1 == ~E_5~0); 343245#L824-1 assume !(1 == ~E_6~0); 343762#L1055-1 [2018-11-23 01:26:52,389 INFO L796 eck$LassoCheckResult]: Loop: 343762#L1055-1 assume !false; 344940#L1056 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret2, eval_#t~nondet3, eval_~tmp_ndt_1~0, eval_#t~nondet4, eval_~tmp_ndt_2~0, eval_#t~nondet5, eval_~tmp_ndt_3~0, eval_#t~nondet6, eval_~tmp_ndt_4~0, eval_#t~nondet7, eval_~tmp_ndt_5~0, eval_#t~nondet8, eval_~tmp_ndt_6~0, eval_#t~nondet9, eval_~tmp_ndt_7~0, eval_~tmp~0;havoc eval_~tmp~0; 344938#L661 assume !false; 344936#L568 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~7;havoc exists_runnable_thread_~__retres1~7; 344933#L520 assume !(0 == ~m_st~0); 344934#L524 assume !(0 == ~t1_st~0); 346411#L528 assume !(0 == ~t2_st~0); 346409#L532 assume !(0 == ~t3_st~0); 346407#L536 assume !(0 == ~t4_st~0); 346405#L540 assume !(0 == ~t5_st~0); 346402#L544 assume !(0 == ~t6_st~0);exists_runnable_thread_~__retres1~7 := 0; 346400#L557 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~7; 346398#L558 eval_#t~ret2 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret2;havoc eval_#t~ret2; 346396#L572 assume !(0 != eval_~tmp~0); 346394#L676 start_simulation_~kernel_st~0 := 2; 346392#L470-1 start_simulation_~kernel_st~0 := 3; 346389#L686-2 assume !(0 == ~M_E~0); 346387#L686-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 346385#L691-3 assume !(0 == ~T2_E~0); 346383#L696-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 346381#L701-3 assume !(0 == ~T4_E~0); 346379#L706-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 346377#L711-3 assume !(0 == ~T6_E~0); 346374#L716-3 assume 0 == ~E_M~0;~E_M~0 := 1; 346372#L721-3 assume !(0 == ~E_1~0); 346370#L726-3 assume 0 == ~E_2~0;~E_2~0 := 1; 346369#L731-3 assume !(0 == ~E_3~0); 346368#L736-3 assume 0 == ~E_4~0;~E_4~0 := 1; 346366#L741-3 assume !(0 == ~E_5~0); 346364#L746-3 assume 0 == ~E_6~0;~E_6~0 := 1; 346362#L751-3 havoc activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 346361#L336-24 assume 1 == ~m_pc~0; 346358#L337-8 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 346356#L347-8 is_master_triggered_#res := is_master_triggered_~__retres1~0; 346354#L348-8 activate_threads_#t~ret10 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 346351#L851-24 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 346349#L851-26 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 346347#L355-24 assume !(1 == ~t1_pc~0); 346344#L355-26 is_transmit1_triggered_~__retres1~1 := 0; 346342#L366-8 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 346340#L367-8 activate_threads_#t~ret11 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 346337#L859-24 assume !(0 != activate_threads_~tmp___0~0); 346335#L859-26 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 346333#L374-24 assume !(1 == ~t2_pc~0); 346331#L374-26 is_transmit2_triggered_~__retres1~2 := 0; 346328#L385-8 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 346326#L386-8 activate_threads_#t~ret12 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 346324#L867-24 assume !(0 != activate_threads_~tmp___1~0); 346322#L867-26 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 346320#L393-24 assume !(1 == ~t3_pc~0); 346317#L393-26 is_transmit3_triggered_~__retres1~3 := 0; 346315#L404-8 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 346305#L405-8 activate_threads_#t~ret13 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 346297#L875-24 assume !(0 != activate_threads_~tmp___2~0); 346288#L875-26 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 346279#L412-24 assume !(1 == ~t4_pc~0); 346270#L412-26 is_transmit4_triggered_~__retres1~4 := 0; 346263#L423-8 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 346262#L424-8 activate_threads_#t~ret14 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 346261#L883-24 assume !(0 != activate_threads_~tmp___3~0); 346259#L883-26 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 346258#L431-24 assume !(1 == ~t5_pc~0); 346257#L431-26 is_transmit5_triggered_~__retres1~5 := 0; 346255#L442-8 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 346254#L443-8 activate_threads_#t~ret15 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 346252#L891-24 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 346250#L891-26 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 346248#L450-24 assume !(1 == ~t6_pc~0); 346211#L450-26 is_transmit6_triggered_~__retres1~6 := 0; 346204#L461-8 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 346194#L462-8 activate_threads_#t~ret16 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 346186#L899-24 assume !(0 != activate_threads_~tmp___5~0); 346175#L899-26 assume !(1 == ~M_E~0); 346174#L764-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 346171#L769-3 assume !(1 == ~T2_E~0); 346169#L774-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 346153#L779-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 346132#L784-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 346121#L789-3 assume !(1 == ~T6_E~0); 346113#L794-3 assume 1 == ~E_M~0;~E_M~0 := 2; 346107#L799-3 assume !(1 == ~E_1~0); 346101#L804-3 assume 1 == ~E_2~0;~E_2~0 := 2; 346094#L809-3 assume !(1 == ~E_3~0); 345936#L814-3 assume 1 == ~E_4~0;~E_4~0 := 2; 345935#L819-3 assume 1 == ~E_5~0;~E_5~0 := 2; 345934#L824-3 assume 1 == ~E_6~0;~E_6~0 := 2; 345933#L829-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~7;havoc exists_runnable_thread_~__retres1~7; 345931#L520-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7 := 1; 345929#L557-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~7; 345922#L558-1 start_simulation_#t~ret18 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret18;havoc start_simulation_#t~ret18; 345903#L1074 assume !(0 == start_simulation_~tmp~3); 345897#L1074-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret17, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~7;havoc exists_runnable_thread_~__retres1~7; 345888#L520-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7 := 1; 345879#L557-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~7; 345871#L558-2 stop_simulation_#t~ret17 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret17;havoc stop_simulation_#t~ret17; 345858#L1029 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 345848#L1036 stop_simulation_#res := stop_simulation_~__retres2~0; 345840#L1037 start_simulation_#t~ret19 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret19;havoc start_simulation_#t~ret19; 345831#L1087 assume !(0 != start_simulation_~tmp___0~1); 343762#L1055-1 [2018-11-23 01:26:52,389 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 01:26:52,389 INFO L82 PathProgramCache]: Analyzing trace with hash -800641180, now seen corresponding path program 10 times [2018-11-23 01:26:52,389 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 01:26:52,389 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 01:26:52,390 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 01:26:52,390 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 01:26:52,390 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 01:26:52,394 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-23 01:26:52,399 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-23 01:26:52,413 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 01:26:52,413 INFO L82 PathProgramCache]: Analyzing trace with hash 1065310819, now seen corresponding path program 1 times [2018-11-23 01:26:52,413 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 01:26:52,413 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 01:26:52,414 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 01:26:52,414 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-23 01:26:52,414 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 01:26:52,418 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 01:26:52,462 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 01:26:52,463 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 01:26:52,463 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-11-23 01:26:52,463 INFO L811 eck$LassoCheckResult]: loop already infeasible [2018-11-23 01:26:52,463 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-11-23 01:26:52,463 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-11-23 01:26:52,463 INFO L87 Difference]: Start difference. First operand 14958 states and 19520 transitions. cyclomatic complexity: 4578 Second operand 5 states. [2018-11-23 01:26:52,705 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 01:26:52,705 INFO L93 Difference]: Finished difference Result 34657 states and 45453 transitions. [2018-11-23 01:26:52,705 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2018-11-23 01:26:52,705 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 34657 states and 45453 transitions. [2018-11-23 01:26:52,779 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 34144 [2018-11-23 01:26:52,830 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 34657 states to 34657 states and 45453 transitions. [2018-11-23 01:26:52,830 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 34657 [2018-11-23 01:26:52,845 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 34657 [2018-11-23 01:26:52,845 INFO L73 IsDeterministic]: Start isDeterministic. Operand 34657 states and 45453 transitions. [2018-11-23 01:26:52,857 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-23 01:26:52,857 INFO L705 BuchiCegarLoop]: Abstraction has 34657 states and 45453 transitions. [2018-11-23 01:26:52,870 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 34657 states and 45453 transitions. [2018-11-23 01:26:52,965 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 34657 to 15585. [2018-11-23 01:26:52,965 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 15585 states. [2018-11-23 01:26:52,978 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 15585 states to 15585 states and 20147 transitions. [2018-11-23 01:26:52,979 INFO L728 BuchiCegarLoop]: Abstraction has 15585 states and 20147 transitions. [2018-11-23 01:26:52,979 INFO L608 BuchiCegarLoop]: Abstraction has 15585 states and 20147 transitions. [2018-11-23 01:26:52,979 INFO L442 BuchiCegarLoop]: ======== Iteration 27============ [2018-11-23 01:26:52,979 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 15585 states and 20147 transitions. [2018-11-23 01:26:53,005 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 15368 [2018-11-23 01:26:53,005 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-23 01:26:53,005 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-23 01:26:53,006 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 01:26:53,006 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 01:26:53,006 INFO L794 eck$LassoCheckResult]: Stem: 393505#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0; 393384#L-1 havoc main_#res;havoc main_~__retres1~8;havoc main_~__retres1~8;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 393124#L1018 havoc start_simulation_#t~ret18, start_simulation_#t~ret19, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 393125#L470 assume 1 == ~m_i~0;~m_st~0 := 0; 392953#L477-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 392954#L482-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 393322#L487-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 393323#L492-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 393152#L497-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 393153#L502-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 393247#L507-1 assume !(0 == ~M_E~0); 392969#L686-1 assume !(0 == ~T1_E~0); 392970#L691-1 assume !(0 == ~T2_E~0); 393339#L696-1 assume !(0 == ~T3_E~0); 393340#L701-1 assume !(0 == ~T4_E~0); 393161#L706-1 assume !(0 == ~T5_E~0); 393162#L711-1 assume !(0 == ~T6_E~0); 393473#L716-1 assume !(0 == ~E_M~0); 393108#L721-1 assume !(0 == ~E_1~0); 393109#L726-1 assume !(0 == ~E_2~0); 392879#L731-1 assume !(0 == ~E_3~0); 392880#L736-1 assume !(0 == ~E_4~0); 392959#L741-1 assume !(0 == ~E_5~0); 392960#L746-1 assume !(0 == ~E_6~0); 393333#L751-1 havoc activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 393066#L336 assume !(1 == ~m_pc~0); 393003#L336-2 is_master_triggered_~__retres1~0 := 0; 393004#L347 is_master_triggered_#res := is_master_triggered_~__retres1~0; 393062#L348 activate_threads_#t~ret10 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 392982#L851 assume !(0 != activate_threads_~tmp~1); 392983#L851-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 392985#L355 assume !(1 == ~t1_pc~0); 393290#L355-2 is_transmit1_triggered_~__retres1~1 := 0; 393286#L366 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 392957#L367 activate_threads_#t~ret11 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 392958#L859 assume !(0 != activate_threads_~tmp___0~0); 393464#L859-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 393465#L374 assume !(1 == ~t2_pc~0); 393497#L374-2 is_transmit2_triggered_~__retres1~2 := 0; 393498#L385 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 393222#L386 activate_threads_#t~ret12 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 393223#L867 assume !(0 != activate_threads_~tmp___1~0); 393632#L867-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 393634#L393 assume !(1 == ~t3_pc~0); 393624#L393-2 is_transmit3_triggered_~__retres1~3 := 0; 393647#L404 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 393621#L405 activate_threads_#t~ret13 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 393116#L875 assume !(0 != activate_threads_~tmp___2~0); 393095#L875-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 393096#L412 assume !(1 == ~t4_pc~0); 393136#L412-2 is_transmit4_triggered_~__retres1~4 := 0; 393135#L423 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 393047#L424 activate_threads_#t~ret14 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 393048#L883 assume !(0 != activate_threads_~tmp___3~0); 393351#L883-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 393155#L431 assume !(1 == ~t5_pc~0); 393141#L431-2 is_transmit5_triggered_~__retres1~5 := 0; 393142#L442 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 393154#L443 activate_threads_#t~ret15 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 393555#L891 assume !(0 != activate_threads_~tmp___4~0); 393550#L891-2 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 393408#L450 assume !(1 == ~t6_pc~0); 393409#L450-2 is_transmit6_triggered_~__retres1~6 := 0; 393406#L461 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 393407#L462 activate_threads_#t~ret16 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 393525#L899 assume !(0 != activate_threads_~tmp___5~0); 393556#L899-2 assume !(1 == ~M_E~0); 392875#L764-1 assume !(1 == ~T1_E~0); 392876#L769-1 assume !(1 == ~T2_E~0); 392987#L774-1 assume !(1 == ~T3_E~0); 392988#L779-1 assume !(1 == ~T4_E~0); 393355#L784-1 assume !(1 == ~T5_E~0); 393356#L789-1 assume !(1 == ~T6_E~0); 393157#L794-1 assume !(1 == ~E_M~0); 393158#L799-1 assume !(1 == ~E_1~0); 393466#L804-1 assume !(1 == ~E_2~0); 393097#L809-1 assume !(1 == ~E_3~0); 393098#L814-1 assume !(1 == ~E_4~0); 392873#L819-1 assume !(1 == ~E_5~0); 392874#L824-1 assume !(1 == ~E_6~0); 393415#L1055-1 [2018-11-23 01:26:53,006 INFO L796 eck$LassoCheckResult]: Loop: 393415#L1055-1 assume !false; 401208#L1056 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret2, eval_#t~nondet3, eval_~tmp_ndt_1~0, eval_#t~nondet4, eval_~tmp_ndt_2~0, eval_#t~nondet5, eval_~tmp_ndt_3~0, eval_#t~nondet6, eval_~tmp_ndt_4~0, eval_#t~nondet7, eval_~tmp_ndt_5~0, eval_#t~nondet8, eval_~tmp_ndt_6~0, eval_#t~nondet9, eval_~tmp_ndt_7~0, eval_~tmp~0;havoc eval_~tmp~0; 399560#L661 assume !false; 399558#L568 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~7;havoc exists_runnable_thread_~__retres1~7; 399556#L520 assume !(0 == ~m_st~0); 399557#L524 assume !(0 == ~t1_st~0); 405815#L528 assume !(0 == ~t2_st~0); 405811#L532 assume !(0 == ~t3_st~0); 405806#L536 assume !(0 == ~t4_st~0); 405801#L540 assume !(0 == ~t5_st~0); 405795#L544 assume !(0 == ~t6_st~0);exists_runnable_thread_~__retres1~7 := 0; 405790#L557 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~7; 405784#L558 eval_#t~ret2 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret2;havoc eval_#t~ret2; 405779#L572 assume !(0 != eval_~tmp~0); 405774#L676 start_simulation_~kernel_st~0 := 2; 405727#L470-1 start_simulation_~kernel_st~0 := 3; 405655#L686-2 assume !(0 == ~M_E~0); 405649#L686-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 405643#L691-3 assume !(0 == ~T2_E~0); 405636#L696-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 405583#L701-3 assume !(0 == ~T4_E~0); 405562#L706-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 405556#L711-3 assume !(0 == ~T6_E~0); 405554#L716-3 assume 0 == ~E_M~0;~E_M~0 := 1; 405552#L721-3 assume !(0 == ~E_1~0); 405550#L726-3 assume 0 == ~E_2~0;~E_2~0 := 1; 405509#L731-3 assume !(0 == ~E_3~0); 405506#L736-3 assume 0 == ~E_4~0;~E_4~0 := 1; 405503#L741-3 assume !(0 == ~E_5~0); 405499#L746-3 assume 0 == ~E_6~0;~E_6~0 := 1; 405495#L751-3 havoc activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 405494#L336-24 assume 1 == ~m_pc~0; 405492#L337-8 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 405491#L347-8 is_master_triggered_#res := is_master_triggered_~__retres1~0; 405490#L348-8 activate_threads_#t~ret10 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 405489#L851-24 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 405488#L851-26 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 405487#L355-24 assume !(1 == ~t1_pc~0); 405486#L355-26 is_transmit1_triggered_~__retres1~1 := 0; 405485#L366-8 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 405484#L367-8 activate_threads_#t~ret11 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 405483#L859-24 assume !(0 != activate_threads_~tmp___0~0); 405482#L859-26 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 405481#L374-24 assume !(1 == ~t2_pc~0); 405480#L374-26 is_transmit2_triggered_~__retres1~2 := 0; 405479#L385-8 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 405478#L386-8 activate_threads_#t~ret12 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 405477#L867-24 assume !(0 != activate_threads_~tmp___1~0); 405476#L867-26 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 405475#L393-24 assume !(1 == ~t3_pc~0); 405473#L393-26 is_transmit3_triggered_~__retres1~3 := 0; 405472#L404-8 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 405471#L405-8 activate_threads_#t~ret13 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 405470#L875-24 assume !(0 != activate_threads_~tmp___2~0); 405469#L875-26 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 405468#L412-24 assume !(1 == ~t4_pc~0); 405467#L412-26 is_transmit4_triggered_~__retres1~4 := 0; 405466#L423-8 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 405465#L424-8 activate_threads_#t~ret14 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 405464#L883-24 assume !(0 != activate_threads_~tmp___3~0); 405463#L883-26 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 405462#L431-24 assume 1 == ~t5_pc~0; 405460#L432-8 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 405458#L442-8 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 405456#L443-8 activate_threads_#t~ret15 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 405454#L891-24 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 405450#L891-26 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 405446#L450-24 assume !(1 == ~t6_pc~0); 405443#L450-26 is_transmit6_triggered_~__retres1~6 := 0; 405440#L461-8 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 405437#L462-8 activate_threads_#t~ret16 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 405434#L899-24 assume !(0 != activate_threads_~tmp___5~0); 405431#L899-26 assume !(1 == ~M_E~0); 405426#L764-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 405422#L769-3 assume !(1 == ~T2_E~0); 405272#L774-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 405227#L779-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 405225#L784-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 405223#L789-3 assume !(1 == ~T6_E~0); 405221#L794-3 assume 1 == ~E_M~0;~E_M~0 := 2; 405219#L799-3 assume !(1 == ~E_1~0); 401478#L804-3 assume 1 == ~E_2~0;~E_2~0 := 2; 401476#L809-3 assume !(1 == ~E_3~0); 401474#L814-3 assume 1 == ~E_4~0;~E_4~0 := 2; 401472#L819-3 assume 1 == ~E_5~0;~E_5~0 := 2; 401470#L824-3 assume 1 == ~E_6~0;~E_6~0 := 2; 401468#L829-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~7;havoc exists_runnable_thread_~__retres1~7; 401465#L520-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7 := 1; 401463#L557-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~7; 401461#L558-1 start_simulation_#t~ret18 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret18;havoc start_simulation_#t~ret18; 401458#L1074 assume !(0 == start_simulation_~tmp~3); 401455#L1074-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret17, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~7;havoc exists_runnable_thread_~__retres1~7; 401452#L520-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7 := 1; 401450#L557-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~7; 401448#L558-2 stop_simulation_#t~ret17 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret17;havoc stop_simulation_#t~ret17; 401446#L1029 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 401444#L1036 stop_simulation_#res := stop_simulation_~__retres2~0; 401442#L1037 start_simulation_#t~ret19 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret19;havoc start_simulation_#t~ret19; 401440#L1087 assume !(0 != start_simulation_~tmp___0~1); 393415#L1055-1 [2018-11-23 01:26:53,007 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 01:26:53,007 INFO L82 PathProgramCache]: Analyzing trace with hash -800641180, now seen corresponding path program 11 times [2018-11-23 01:26:53,007 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 01:26:53,007 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 01:26:53,008 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 01:26:53,008 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 01:26:53,008 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 01:26:53,012 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-23 01:26:53,016 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-23 01:26:53,030 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 01:26:53,030 INFO L82 PathProgramCache]: Analyzing trace with hash 541990148, now seen corresponding path program 1 times [2018-11-23 01:26:53,030 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 01:26:53,030 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 01:26:53,031 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 01:26:53,031 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-23 01:26:53,031 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 01:26:53,035 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-23 01:26:53,039 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-23 01:26:53,053 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 01:26:53,053 INFO L82 PathProgramCache]: Analyzing trace with hash -530124095, now seen corresponding path program 1 times [2018-11-23 01:26:53,053 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 01:26:53,053 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 01:26:53,054 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 01:26:53,054 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 01:26:53,054 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 01:26:53,059 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 01:26:53,104 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 01:26:53,104 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 01:26:53,104 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-23 01:26:53,573 WARN L180 SmtUtils]: Spent 460.00 ms on a formula simplification. DAG size of input: 215 DAG size of output: 196 [2018-11-23 01:26:53,746 WARN L180 SmtUtils]: Spent 165.00 ms on a formula simplification that was a NOOP. DAG size: 170 [2018-11-23 01:26:53,756 INFO L216 LassoAnalysis]: Preferences: [2018-11-23 01:26:53,756 INFO L124 ssoRankerPreferences]: Compute integeral hull: false [2018-11-23 01:26:53,756 INFO L125 ssoRankerPreferences]: Enable LassoPartitioneer: true [2018-11-23 01:26:53,757 INFO L126 ssoRankerPreferences]: Term annotations enabled: false [2018-11-23 01:26:53,757 INFO L127 ssoRankerPreferences]: Use exernal solver: true [2018-11-23 01:26:53,757 INFO L128 ssoRankerPreferences]: SMT solver command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2018-11-23 01:26:53,757 INFO L129 ssoRankerPreferences]: Dump SMT script to file: false [2018-11-23 01:26:53,757 INFO L130 ssoRankerPreferences]: Path of dumped script: [2018-11-23 01:26:53,757 INFO L131 ssoRankerPreferences]: Filename of dumped script: token_ring.06_false-unreach-call_false-termination.cil.c_Iteration27_Loop [2018-11-23 01:26:53,757 INFO L132 ssoRankerPreferences]: MapElimAlgo: Frank [2018-11-23 01:26:53,757 INFO L282 LassoAnalysis]: Starting lasso preprocessing... [2018-11-23 01:26:53,775 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 01:26:53,789 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 01:26:53,794 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 01:26:53,804 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 01:26:53,811 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 01:26:53,814 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 01:26:53,820 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 01:26:53,822 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 01:26:53,826 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 01:26:53,829 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 01:26:53,832 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 01:26:53,834 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 01:26:53,837 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 01:26:53,839 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 01:26:53,842 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 01:26:53,844 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 01:26:53,847 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 01:26:53,852 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 01:26:53,855 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 01:26:53,860 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 01:26:53,862 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 01:26:53,865 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 01:26:53,867 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 01:26:53,871 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 01:26:53,874 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 01:26:53,877 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 01:26:53,881 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 01:26:53,885 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 01:26:53,890 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 01:26:53,893 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 01:26:53,894 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 01:26:53,899 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 01:26:53,900 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 01:26:53,904 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 01:26:53,905 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 01:26:53,908 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 01:26:53,909 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 01:26:53,910 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 01:26:53,913 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 01:26:53,915 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 01:26:53,917 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 01:26:53,920 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 01:26:53,921 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 01:26:53,922 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 01:26:53,925 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 01:26:53,927 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 01:26:53,928 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 01:26:53,929 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 01:26:53,930 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 01:26:53,932 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 01:26:53,935 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 01:26:53,938 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 01:26:53,941 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 01:26:53,942 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 01:26:53,946 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 01:26:53,947 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 01:26:53,949 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 01:26:53,950 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 01:26:53,993 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 01:26:53,994 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 01:26:53,997 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 01:26:53,999 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 01:26:54,001 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 01:26:54,003 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 01:26:54,004 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 01:26:54,006 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 01:26:54,011 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 01:26:54,381 INFO L300 LassoAnalysis]: Preprocessing complete. [2018-11-23 01:26:54,382 INFO L412 LassoAnalysis]: Checking for nontermination... No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_3cb46500-1f11-408a-a24e-b9ac197b8b4e/bin-2019/uautomizer/z3 Starting monitored process 2 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 2 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2018-11-23 01:26:54,403 INFO L151 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2018-11-23 01:26:54,403 INFO L163 nArgumentSynthesizer]: Using integer mode. [2018-11-23 01:26:54,409 INFO L445 LassoAnalysis]: Proved nontermination for one component. [2018-11-23 01:26:54,409 INFO L448 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {ULTIMATE.start_start_simulation_#t~ret18=0} Honda state: {ULTIMATE.start_start_simulation_#t~ret18=0} Generalized eigenvectors: [] Lambdas: [] Nus: [] No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_3cb46500-1f11-408a-a24e-b9ac197b8b4e/bin-2019/uautomizer/z3 Starting monitored process 3 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 3 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2018-11-23 01:26:54,429 INFO L151 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2018-11-23 01:26:54,429 INFO L163 nArgumentSynthesizer]: Using integer mode. [2018-11-23 01:26:54,435 INFO L445 LassoAnalysis]: Proved nontermination for one component. [2018-11-23 01:26:54,435 INFO L448 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {ULTIMATE.start_is_transmit6_triggered_#res=0, ULTIMATE.start_is_transmit6_triggered_~__retres1~6=0, ULTIMATE.start_activate_threads_~tmp___5~0=0} Honda state: {ULTIMATE.start_is_transmit6_triggered_#res=0, ULTIMATE.start_is_transmit6_triggered_~__retres1~6=0, ULTIMATE.start_activate_threads_~tmp___5~0=0} Generalized eigenvectors: [] Lambdas: [] Nus: [] No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_3cb46500-1f11-408a-a24e-b9ac197b8b4e/bin-2019/uautomizer/z3 Starting monitored process 4 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 4 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2018-11-23 01:26:54,461 INFO L151 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2018-11-23 01:26:54,462 INFO L163 nArgumentSynthesizer]: Using integer mode. [2018-11-23 01:26:54,464 INFO L445 LassoAnalysis]: Proved nontermination for one component. [2018-11-23 01:26:54,465 INFO L448 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {ULTIMATE.start_eval_~tmp_ndt_7~0=0} Honda state: {ULTIMATE.start_eval_~tmp_ndt_7~0=0} Generalized eigenvectors: [] Lambdas: [] Nus: [] No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_3cb46500-1f11-408a-a24e-b9ac197b8b4e/bin-2019/uautomizer/z3 Starting monitored process 5 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 5 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2018-11-23 01:26:54,483 INFO L151 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2018-11-23 01:26:54,483 INFO L163 nArgumentSynthesizer]: Using integer mode. [2018-11-23 01:26:54,486 INFO L445 LassoAnalysis]: Proved nontermination for one component. [2018-11-23 01:26:54,486 INFO L448 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {ULTIMATE.start_stop_simulation_~__retres2~0=0, ULTIMATE.start_start_simulation_~tmp___0~1=0, ULTIMATE.start_stop_simulation_#res=0} Honda state: {ULTIMATE.start_stop_simulation_~__retres2~0=0, ULTIMATE.start_start_simulation_~tmp___0~1=0, ULTIMATE.start_stop_simulation_#res=0} Generalized eigenvectors: [] Lambdas: [] Nus: [] No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_3cb46500-1f11-408a-a24e-b9ac197b8b4e/bin-2019/uautomizer/z3 Starting monitored process 6 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 6 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2018-11-23 01:26:54,521 INFO L151 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2018-11-23 01:26:54,521 INFO L163 nArgumentSynthesizer]: Using integer mode. [2018-11-23 01:26:54,527 INFO L445 LassoAnalysis]: Proved nontermination for one component. [2018-11-23 01:26:54,527 INFO L448 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {~t4_st~0=-1} Honda state: {~t4_st~0=-1} Generalized eigenvectors: [] Lambdas: [] Nus: [] No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_3cb46500-1f11-408a-a24e-b9ac197b8b4e/bin-2019/uautomizer/z3 Starting monitored process 7 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 7 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2018-11-23 01:26:54,566 INFO L151 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2018-11-23 01:26:54,566 INFO L163 nArgumentSynthesizer]: Using integer mode. No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_3cb46500-1f11-408a-a24e-b9ac197b8b4e/bin-2019/uautomizer/z3 Starting monitored process 8 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 8 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2018-11-23 01:26:54,588 INFO L151 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 3 Nilpotent components: true [2018-11-23 01:26:54,588 INFO L163 nArgumentSynthesizer]: Using integer mode. [2018-11-23 01:26:54,591 INFO L452 LassoAnalysis]: Proving nontermination failed: No geometric nontermination argument exists. [2018-11-23 01:26:54,609 INFO L216 LassoAnalysis]: Preferences: [2018-11-23 01:26:54,609 INFO L124 ssoRankerPreferences]: Compute integeral hull: false [2018-11-23 01:26:54,609 INFO L125 ssoRankerPreferences]: Enable LassoPartitioneer: true [2018-11-23 01:26:54,609 INFO L126 ssoRankerPreferences]: Term annotations enabled: false [2018-11-23 01:26:54,609 INFO L127 ssoRankerPreferences]: Use exernal solver: false [2018-11-23 01:26:54,609 INFO L128 ssoRankerPreferences]: SMT solver command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2018-11-23 01:26:54,609 INFO L129 ssoRankerPreferences]: Dump SMT script to file: false [2018-11-23 01:26:54,609 INFO L130 ssoRankerPreferences]: Path of dumped script: [2018-11-23 01:26:54,609 INFO L131 ssoRankerPreferences]: Filename of dumped script: token_ring.06_false-unreach-call_false-termination.cil.c_Iteration27_Loop [2018-11-23 01:26:54,609 INFO L132 ssoRankerPreferences]: MapElimAlgo: Frank [2018-11-23 01:26:54,609 INFO L282 LassoAnalysis]: Starting lasso preprocessing... [2018-11-23 01:26:54,612 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 01:26:54,619 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 01:26:54,620 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 01:26:54,622 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 01:26:54,626 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 01:26:54,628 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 01:26:54,638 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 01:26:54,639 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 01:26:54,641 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 01:26:54,642 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 01:26:54,644 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 01:26:54,645 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 01:26:54,646 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 01:26:54,650 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 01:26:54,653 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 01:26:54,654 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 01:26:54,662 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 01:26:54,665 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 01:26:54,669 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 01:26:54,676 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 01:26:54,686 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 01:26:54,691 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 01:26:54,694 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 01:26:54,699 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 01:26:54,704 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 01:26:54,707 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 01:26:54,710 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 01:26:54,713 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 01:26:54,717 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 01:26:54,731 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 01:26:54,734 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 01:26:54,735 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 01:26:54,737 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 01:26:54,740 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 01:26:54,745 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 01:26:54,749 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 01:26:54,752 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 01:26:54,753 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 01:26:54,757 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 01:26:54,760 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 01:26:54,763 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 01:26:54,767 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 01:26:54,769 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 01:26:54,774 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 01:26:54,777 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 01:26:54,779 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 01:26:54,781 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 01:26:54,782 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 01:26:54,786 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 01:26:54,789 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 01:26:54,793 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 01:26:54,799 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 01:26:54,803 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 01:26:54,805 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 01:26:54,813 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 01:26:54,816 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 01:26:54,819 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 01:26:54,821 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 01:26:54,825 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 01:26:54,828 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 01:26:54,831 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 01:26:54,838 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 01:26:54,845 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 01:26:54,848 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 01:26:54,852 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 01:26:54,854 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 01:26:54,860 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 01:26:55,255 INFO L300 LassoAnalysis]: Preprocessing complete. [2018-11-23 01:26:55,259 INFO L497 LassoAnalysis]: Using template 'affine'. [2018-11-23 01:26:55,260 INFO L122 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSES Number of strict supporting invariants: 0 Number of non-strict supporting invariants: 1 Consider only non-deceasing supporting invariants: true Simplify termination arguments: true Simplify supporting invariants: trueOverapproximate stem: false [2018-11-23 01:26:55,262 INFO L339 nArgumentSynthesizer]: Template has degree 0. [2018-11-23 01:26:55,262 INFO L352 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2018-11-23 01:26:55,262 INFO L205 nArgumentSynthesizer]: 1 stem disjuncts [2018-11-23 01:26:55,262 INFO L206 nArgumentSynthesizer]: 1 loop disjuncts [2018-11-23 01:26:55,262 INFO L207 nArgumentSynthesizer]: 2 template conjuncts. [2018-11-23 01:26:55,264 INFO L402 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2018-11-23 01:26:55,264 INFO L403 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2018-11-23 01:26:55,266 INFO L530 LassoAnalysis]: Proving termination failed for this template and these settings. [2018-11-23 01:26:55,266 INFO L122 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSES Number of strict supporting invariants: 0 Number of non-strict supporting invariants: 1 Consider only non-deceasing supporting invariants: true Simplify termination arguments: true Simplify supporting invariants: trueOverapproximate stem: false [2018-11-23 01:26:55,266 INFO L339 nArgumentSynthesizer]: Template has degree 0. [2018-11-23 01:26:55,266 INFO L352 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2018-11-23 01:26:55,267 INFO L205 nArgumentSynthesizer]: 1 stem disjuncts [2018-11-23 01:26:55,267 INFO L206 nArgumentSynthesizer]: 1 loop disjuncts [2018-11-23 01:26:55,267 INFO L207 nArgumentSynthesizer]: 2 template conjuncts. [2018-11-23 01:26:55,267 INFO L402 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2018-11-23 01:26:55,267 INFO L403 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2018-11-23 01:26:55,268 INFO L530 LassoAnalysis]: Proving termination failed for this template and these settings. [2018-11-23 01:26:55,268 INFO L122 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSES Number of strict supporting invariants: 0 Number of non-strict supporting invariants: 1 Consider only non-deceasing supporting invariants: true Simplify termination arguments: true Simplify supporting invariants: trueOverapproximate stem: false [2018-11-23 01:26:55,268 INFO L339 nArgumentSynthesizer]: Template has degree 0. [2018-11-23 01:26:55,268 INFO L352 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2018-11-23 01:26:55,269 INFO L205 nArgumentSynthesizer]: 1 stem disjuncts [2018-11-23 01:26:55,269 INFO L206 nArgumentSynthesizer]: 2 loop disjuncts [2018-11-23 01:26:55,269 INFO L207 nArgumentSynthesizer]: 2 template conjuncts. [2018-11-23 01:26:55,269 INFO L402 nArgumentSynthesizer]: We have 4 Motzkin's Theorem applications. [2018-11-23 01:26:55,269 INFO L403 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2018-11-23 01:26:55,270 INFO L530 LassoAnalysis]: Proving termination failed for this template and these settings. [2018-11-23 01:26:55,270 INFO L122 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSES Number of strict supporting invariants: 0 Number of non-strict supporting invariants: 1 Consider only non-deceasing supporting invariants: true Simplify termination arguments: true Simplify supporting invariants: trueOverapproximate stem: false [2018-11-23 01:26:55,271 INFO L339 nArgumentSynthesizer]: Template has degree 0. [2018-11-23 01:26:55,271 INFO L352 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2018-11-23 01:26:55,271 INFO L205 nArgumentSynthesizer]: 1 stem disjuncts [2018-11-23 01:26:55,271 INFO L206 nArgumentSynthesizer]: 1 loop disjuncts [2018-11-23 01:26:55,271 INFO L207 nArgumentSynthesizer]: 2 template conjuncts. [2018-11-23 01:26:55,272 INFO L402 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2018-11-23 01:26:55,272 INFO L403 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2018-11-23 01:26:55,274 INFO L421 nArgumentSynthesizer]: Found a termination argument, trying to simplify. [2018-11-23 01:26:55,276 INFO L443 ModelExtractionUtils]: Simplification made 3 calls to the SMT solver. [2018-11-23 01:26:55,277 INFO L444 ModelExtractionUtils]: 0 out of 3 variables were initially zero. Simplification set additionally 0 variables to zero. [2018-11-23 01:26:55,278 INFO L437 nArgumentSynthesizer]: Simplifying supporting invariants... [2018-11-23 01:26:55,278 INFO L440 nArgumentSynthesizer]: Removed 0 redundant supporting invariants from a total of 0. [2018-11-23 01:26:55,279 INFO L518 LassoAnalysis]: Proved termination. [2018-11-23 01:26:55,279 INFO L520 LassoAnalysis]: Termination argument consisting of: Ranking function f(~E_4~0) = -1*~E_4~0 + 1 Supporting invariants [] [2018-11-23 01:26:55,280 INFO L297 tatePredicateManager]: 0 out of 0 supporting invariants were superfluous and have been removed [2018-11-23 01:26:55,341 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 01:26:55,373 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 01:26:55,377 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-23 01:26:55,414 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 01:26:55,417 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-23 01:26:55,465 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 01:26:55,469 INFO L152 lantAutomatonBouncer]: Defining deterministic Buchi interpolant automaton with honda bouncer for stem and without honda bouncer for loop.1 stem predicates 3 loop predicates [2018-11-23 01:26:55,470 INFO L72 iDifferenceNCSBLazy3]: Start buchiDifferenceNCSBLazy3. First operand 15585 states and 20147 transitions. cyclomatic complexity: 4578 Second operand 5 states. [2018-11-23 01:26:55,843 INFO L76 iDifferenceNCSBLazy3]: Finished buchiDifferenceNCSBLazy3. First operand 15585 states and 20147 transitions. cyclomatic complexity: 4578. Second operand 5 states. Result 58555 states and 76166 transitions. Complement of second has 5 states. [2018-11-23 01:26:55,845 INFO L142 InterpolantAutomaton]: Switched to read-only mode: Buchi interpolant automaton has 3 states 1 stem states 1 non-accepting loop states 1 accepting loop states [2018-11-23 01:26:55,845 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 5 states. [2018-11-23 01:26:55,847 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3 states to 3 states and 1683 transitions. [2018-11-23 01:26:55,848 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 3 states and 1683 transitions. Stem has 80 letters. Loop has 99 letters. [2018-11-23 01:26:55,851 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2018-11-23 01:26:55,851 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 3 states and 1683 transitions. Stem has 179 letters. Loop has 99 letters. [2018-11-23 01:26:55,852 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2018-11-23 01:26:55,852 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 3 states and 1683 transitions. Stem has 80 letters. Loop has 198 letters. [2018-11-23 01:26:55,854 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2018-11-23 01:26:55,854 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 58555 states and 76166 transitions. [2018-11-23 01:26:56,087 INFO L131 ngComponentsAnalysis]: Automaton has 48 accepting balls. 44232 [2018-11-23 01:26:56,240 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 58555 states to 58523 states and 76134 transitions. [2018-11-23 01:26:56,241 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 44738 [2018-11-23 01:26:56,273 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 44819 [2018-11-23 01:26:56,273 INFO L73 IsDeterministic]: Start isDeterministic. Operand 58523 states and 76134 transitions. [2018-11-23 01:26:56,273 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2018-11-23 01:26:56,273 INFO L705 BuchiCegarLoop]: Abstraction has 58523 states and 76134 transitions. [2018-11-23 01:26:56,301 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 58523 states and 76134 transitions. [2018-11-23 01:26:56,887 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 58523 to 42914. [2018-11-23 01:26:56,888 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 42914 states. [2018-11-23 01:26:56,942 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 42914 states to 42914 states and 55909 transitions. [2018-11-23 01:26:56,942 INFO L728 BuchiCegarLoop]: Abstraction has 42914 states and 55909 transitions. [2018-11-23 01:26:56,942 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-23 01:26:56,942 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-23 01:26:56,942 INFO L87 Difference]: Start difference. First operand 42914 states and 55909 transitions. Second operand 3 states. [2018-11-23 01:26:57,147 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 01:26:57,147 INFO L93 Difference]: Finished difference Result 45314 states and 58573 transitions. [2018-11-23 01:26:57,149 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-23 01:26:57,149 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 45314 states and 58573 transitions. [2018-11-23 01:26:57,290 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 30464 [2018-11-23 01:26:57,383 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 45314 states to 45314 states and 58573 transitions. [2018-11-23 01:26:57,383 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 30810 [2018-11-23 01:26:57,400 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 30810 [2018-11-23 01:26:57,400 INFO L73 IsDeterministic]: Start isDeterministic. Operand 45314 states and 58573 transitions. [2018-11-23 01:26:57,406 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2018-11-23 01:26:57,407 INFO L705 BuchiCegarLoop]: Abstraction has 45314 states and 58573 transitions. [2018-11-23 01:26:57,427 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 45314 states and 58573 transitions. [2018-11-23 01:26:57,671 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 45314 to 42914. [2018-11-23 01:26:57,671 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 42914 states. [2018-11-23 01:26:57,708 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 42914 states to 42914 states and 55717 transitions. [2018-11-23 01:26:57,709 INFO L728 BuchiCegarLoop]: Abstraction has 42914 states and 55717 transitions. [2018-11-23 01:26:57,709 INFO L608 BuchiCegarLoop]: Abstraction has 42914 states and 55717 transitions. [2018-11-23 01:26:57,709 INFO L442 BuchiCegarLoop]: ======== Iteration 28============ [2018-11-23 01:26:57,709 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 42914 states and 55717 transitions. [2018-11-23 01:26:57,794 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 28864 [2018-11-23 01:26:57,794 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-23 01:26:57,794 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-23 01:26:57,795 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 01:26:57,795 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 01:26:57,795 INFO L794 eck$LassoCheckResult]: Stem: 556995#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0; 556765#L-1 havoc main_#res;havoc main_~__retres1~8;havoc main_~__retres1~8;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 556277#L1018 havoc start_simulation_#t~ret18, start_simulation_#t~ret19, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 556278#L470 assume 1 == ~m_i~0;~m_st~0 := 0; 555963#L477-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 555964#L482-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 556663#L487-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 556664#L492-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 556325#L497-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 556326#L502-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 556513#L507-1 assume !(0 == ~M_E~0); 555993#L686-1 assume !(0 == ~T1_E~0); 555994#L691-1 assume !(0 == ~T2_E~0); 556688#L696-1 assume !(0 == ~T3_E~0); 556689#L701-1 assume !(0 == ~T4_E~0); 556337#L706-1 assume !(0 == ~T5_E~0); 556338#L711-1 assume !(0 == ~T6_E~0); 556934#L716-1 assume !(0 == ~E_M~0); 556246#L721-1 assume !(0 == ~E_1~0); 556247#L726-1 assume !(0 == ~E_2~0); 555823#L731-1 assume !(0 == ~E_3~0); 555824#L736-1 assume !(0 == ~E_4~0); 555970#L741-1 assume !(0 == ~E_5~0); 555971#L746-1 assume !(0 == ~E_6~0); 556676#L751-1 havoc activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 556170#L336 assume !(1 == ~m_pc~0); 556051#L336-2 is_master_triggered_~__retres1~0 := 0; 556052#L347 is_master_triggered_#res := is_master_triggered_~__retres1~0; 556169#L348 activate_threads_#t~ret10 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 556014#L851 assume !(0 != activate_threads_~tmp~1); 556015#L851-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 556022#L355 assume !(1 == ~t1_pc~0); 556599#L355-2 is_transmit1_triggered_~__retres1~1 := 0; 556598#L366 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 555968#L367 activate_threads_#t~ret11 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 555969#L859 assume !(0 != activate_threads_~tmp___0~0); 556919#L859-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 556920#L374 assume !(1 == ~t2_pc~0); 556982#L374-2 is_transmit2_triggered_~__retres1~2 := 0; 556983#L385 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 556456#L386 activate_threads_#t~ret12 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 556457#L867 assume !(0 != activate_threads_~tmp___1~0); 557270#L867-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 557273#L393 assume !(1 == ~t3_pc~0); 557247#L393-2 is_transmit3_triggered_~__retres1~3 := 0; 557301#L404 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 557245#L405 activate_threads_#t~ret13 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 556259#L875 assume !(0 != activate_threads_~tmp___2~0); 556224#L875-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 556225#L412 assume !(1 == ~t4_pc~0); 556296#L412-2 is_transmit4_triggered_~__retres1~4 := 0; 556295#L423 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 556137#L424 activate_threads_#t~ret14 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 556138#L883 assume !(0 != activate_threads_~tmp___3~0); 556713#L883-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 556329#L431 assume !(1 == ~t5_pc~0); 556306#L431-2 is_transmit5_triggered_~__retres1~5 := 0; 556307#L442 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 556665#L443 activate_threads_#t~ret15 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 556666#L891 assume !(0 != activate_threads_~tmp___4~0); 557096#L891-2 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 556804#L450 assume !(1 == ~t6_pc~0); 556805#L450-2 is_transmit6_triggered_~__retres1~6 := 0; 556802#L461 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 556803#L462 activate_threads_#t~ret16 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 557044#L899 assume !(0 != activate_threads_~tmp___5~0); 557110#L899-2 assume !(1 == ~M_E~0); 555817#L764-1 assume !(1 == ~T1_E~0); 555818#L769-1 assume !(1 == ~T2_E~0); 556025#L774-1 assume !(1 == ~T3_E~0); 556026#L779-1 assume !(1 == ~T4_E~0); 556723#L784-1 assume !(1 == ~T5_E~0); 556724#L789-1 assume !(1 == ~T6_E~0); 556331#L794-1 assume !(1 == ~E_M~0); 556332#L799-1 assume !(1 == ~E_1~0); 556921#L804-1 assume !(1 == ~E_2~0); 556229#L809-1 assume !(1 == ~E_3~0); 556230#L814-1 assume !(1 == ~E_4~0); 555815#L819-1 assume !(1 == ~E_5~0); 555816#L824-1 assume 1 == ~E_6~0;~E_6~0 := 2; 556817#L1055-1 [2018-11-23 01:26:57,796 INFO L796 eck$LassoCheckResult]: Loop: 556817#L1055-1 assume !false; 576347#L1056 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret2, eval_#t~nondet3, eval_~tmp_ndt_1~0, eval_#t~nondet4, eval_~tmp_ndt_2~0, eval_#t~nondet5, eval_~tmp_ndt_3~0, eval_#t~nondet6, eval_~tmp_ndt_4~0, eval_#t~nondet7, eval_~tmp_ndt_5~0, eval_#t~nondet8, eval_~tmp_ndt_6~0, eval_#t~nondet9, eval_~tmp_ndt_7~0, eval_~tmp~0;havoc eval_~tmp~0; 576346#L661 assume !false; 576345#L568 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~7;havoc exists_runnable_thread_~__retres1~7; 576344#L520 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7 := 1; 576343#L557 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~7; 576341#L558 eval_#t~ret2 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret2;havoc eval_#t~ret2; 576339#L572 assume 0 != eval_~tmp~0; 576337#L572-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0;eval_~tmp_ndt_1~0 := eval_#t~nondet3;havoc eval_#t~nondet3; 576333#L580 assume 0 != eval_~tmp_ndt_1~0;~m_st~0 := 1;havoc master_#t~nondet0, master_#t~nondet1, master_~tmp_var~0;master_~tmp_var~0 := master_#t~nondet0;havoc master_#t~nondet0; 576334#L64 assume 0 == ~m_pc~0; 593996#L100 assume !false; 593995#L76 ~token~0 := master_#t~nondet1;havoc master_#t~nondet1;~local~0 := ~token~0;~E_1~0 := 1;havoc activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 593994#L336-3 assume !(1 == ~m_pc~0); 593992#L336-5 is_master_triggered_~__retres1~0 := 0; 598013#L347-1 is_master_triggered_#res := is_master_triggered_~__retres1~0; 598012#L348-1 activate_threads_#t~ret10 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 593987#L851-3 assume !(0 != activate_threads_~tmp~1); 593984#L851-5 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 593982#L355-3 assume !(1 == ~t1_pc~0); 593979#L355-5 is_transmit1_triggered_~__retres1~1 := 0; 593977#L366-1 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 593975#L367-1 activate_threads_#t~ret11 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 593973#L859-3 assume !(0 != activate_threads_~tmp___0~0); 593971#L859-5 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 593969#L374-3 assume !(1 == ~t2_pc~0); 593967#L374-5 is_transmit2_triggered_~__retres1~2 := 0; 593965#L385-1 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 593963#L386-1 activate_threads_#t~ret12 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 593961#L867-3 assume !(0 != activate_threads_~tmp___1~0); 593959#L867-5 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 593957#L393-3 assume !(1 == ~t3_pc~0); 593954#L393-5 is_transmit3_triggered_~__retres1~3 := 0; 593952#L404-1 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 593950#L405-1 activate_threads_#t~ret13 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 593948#L875-3 assume !(0 != activate_threads_~tmp___2~0); 593946#L875-5 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 593944#L412-3 assume !(1 == ~t4_pc~0); 593942#L412-5 is_transmit4_triggered_~__retres1~4 := 0; 593940#L423-1 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 593938#L424-1 activate_threads_#t~ret14 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 593936#L883-3 assume !(0 != activate_threads_~tmp___3~0); 593935#L883-5 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 593934#L431-3 assume !(1 == ~t5_pc~0); 593931#L431-5 is_transmit5_triggered_~__retres1~5 := 0; 593929#L442-1 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 593927#L443-1 activate_threads_#t~ret15 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 593923#L891-3 assume !(0 != activate_threads_~tmp___4~0); 593920#L891-5 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 593918#L450-3 assume !(1 == ~t6_pc~0); 593917#L450-5 is_transmit6_triggered_~__retres1~6 := 0; 593911#L461-1 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 593909#L462-1 activate_threads_#t~ret16 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 593907#L899-3 assume !(0 != activate_threads_~tmp___5~0); 579045#L899-5 ~E_1~0 := 2;~m_pc~0 := 1;~m_st~0 := 2; 579042#L577 assume !(0 == ~t1_st~0); 579040#L591 assume !(0 == ~t2_st~0); 581807#L605 assume !(0 == ~t3_st~0); 581803#L619 assume !(0 == ~t4_st~0); 581714#L633 assume !(0 == ~t5_st~0); 581710#L647 assume !(0 == ~t6_st~0); 581705#L661 assume !false; 581703#L568 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~7;havoc exists_runnable_thread_~__retres1~7; 581701#L520 assume !(0 == ~m_st~0); 581698#L524 assume !(0 == ~t1_st~0); 581696#L528 assume !(0 == ~t2_st~0); 581694#L532 assume !(0 == ~t3_st~0); 581692#L536 assume !(0 == ~t4_st~0); 581690#L540 assume !(0 == ~t5_st~0); 581687#L544 assume !(0 == ~t6_st~0);exists_runnable_thread_~__retres1~7 := 0; 581685#L557 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~7; 581681#L558 eval_#t~ret2 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret2;havoc eval_#t~ret2; 581679#L572 assume !(0 != eval_~tmp~0); 581674#L676 start_simulation_~kernel_st~0 := 2; 581672#L470-1 start_simulation_~kernel_st~0 := 3; 581669#L686-2 assume !(0 == ~M_E~0); 581667#L686-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 581664#L691-3 assume !(0 == ~T2_E~0); 581662#L696-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 581660#L701-3 assume !(0 == ~T4_E~0); 581657#L706-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 581655#L711-3 assume !(0 == ~T6_E~0); 581653#L716-3 assume 0 == ~E_M~0;~E_M~0 := 1; 581652#L721-3 assume !(0 == ~E_1~0); 581651#L726-3 assume 0 == ~E_2~0;~E_2~0 := 1; 581649#L731-3 assume !(0 == ~E_3~0); 581648#L736-3 assume 0 == ~E_4~0;~E_4~0 := 1; 581647#L741-3 assume !(0 == ~E_5~0); 581646#L746-3 assume 0 == ~E_6~0;~E_6~0 := 1; 581642#L751-3 havoc activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 581640#L336-24 assume 1 == ~m_pc~0; 581637#L337-8 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 581635#L347-8 is_master_triggered_#res := is_master_triggered_~__retres1~0; 581630#L348-8 activate_threads_#t~ret10 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 581627#L851-24 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 581625#L851-26 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 581623#L355-24 assume !(1 == ~t1_pc~0); 581621#L355-26 is_transmit1_triggered_~__retres1~1 := 0; 581619#L366-8 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 581617#L367-8 activate_threads_#t~ret11 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 581615#L859-24 assume !(0 != activate_threads_~tmp___0~0); 581611#L859-26 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 581609#L374-24 assume !(1 == ~t2_pc~0); 581607#L374-26 is_transmit2_triggered_~__retres1~2 := 0; 581605#L385-8 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 581602#L386-8 activate_threads_#t~ret12 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 581600#L867-24 assume !(0 != activate_threads_~tmp___1~0); 581597#L867-26 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 581595#L393-24 assume !(1 == ~t3_pc~0); 581592#L393-26 is_transmit3_triggered_~__retres1~3 := 0; 581590#L404-8 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 581588#L405-8 activate_threads_#t~ret13 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 581586#L875-24 assume !(0 != activate_threads_~tmp___2~0); 581582#L875-26 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 581580#L412-24 assume !(1 == ~t4_pc~0); 581578#L412-26 is_transmit4_triggered_~__retres1~4 := 0; 581576#L423-8 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 581573#L424-8 activate_threads_#t~ret14 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 581571#L883-24 assume !(0 != activate_threads_~tmp___3~0); 581567#L883-26 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 581565#L431-24 assume !(1 == ~t5_pc~0); 581561#L431-26 is_transmit5_triggered_~__retres1~5 := 0; 581559#L442-8 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 581556#L443-8 activate_threads_#t~ret15 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 581554#L891-24 assume !(0 != activate_threads_~tmp___4~0); 581551#L891-26 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 581549#L450-24 assume !(1 == ~t6_pc~0); 581547#L450-26 is_transmit6_triggered_~__retres1~6 := 0; 581545#L461-8 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 581543#L462-8 activate_threads_#t~ret16 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 581539#L899-24 assume !(0 != activate_threads_~tmp___5~0); 581537#L899-26 assume !(1 == ~M_E~0); 581536#L764-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 581531#L769-3 assume !(1 == ~T2_E~0); 581526#L774-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 581524#L779-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 581522#L784-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 581520#L789-3 assume !(1 == ~T6_E~0); 581518#L794-3 assume 1 == ~E_M~0;~E_M~0 := 2; 581516#L799-3 assume !(1 == ~E_1~0); 581514#L804-3 assume 1 == ~E_2~0;~E_2~0 := 2; 581512#L809-3 assume !(1 == ~E_3~0); 581509#L814-3 assume 1 == ~E_4~0;~E_4~0 := 2; 581507#L819-3 assume 1 == ~E_5~0;~E_5~0 := 2; 581504#L824-3 assume 1 == ~E_6~0;~E_6~0 := 2; 581500#L829-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~7;havoc exists_runnable_thread_~__retres1~7; 581498#L520-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7 := 1; 581492#L557-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~7; 581490#L558-1 start_simulation_#t~ret18 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret18;havoc start_simulation_#t~ret18; 581487#L1074 assume !(0 == start_simulation_~tmp~3); 581484#L1074-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret17, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~7;havoc exists_runnable_thread_~__retres1~7; 581482#L520-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7 := 1; 581480#L557-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~7; 581478#L558-2 stop_simulation_#t~ret17 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret17;havoc stop_simulation_#t~ret17; 581476#L1029 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 581474#L1036 stop_simulation_#res := stop_simulation_~__retres2~0; 581472#L1037 start_simulation_#t~ret19 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret19;havoc start_simulation_#t~ret19; 581469#L1087 assume !(0 != start_simulation_~tmp___0~1); 556817#L1055-1 [2018-11-23 01:26:57,796 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 01:26:57,796 INFO L82 PathProgramCache]: Analyzing trace with hash -800641182, now seen corresponding path program 1 times [2018-11-23 01:26:57,796 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 01:26:57,796 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 01:26:57,797 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 01:26:57,797 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 01:26:57,797 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 01:26:57,803 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 01:26:57,858 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 01:26:57,858 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 01:26:57,858 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [1] imperfect sequences [] total 1 [2018-11-23 01:26:57,859 INFO L799 eck$LassoCheckResult]: stem already infeasible [2018-11-23 01:26:57,859 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 01:26:57,859 INFO L82 PathProgramCache]: Analyzing trace with hash -1669011171, now seen corresponding path program 1 times [2018-11-23 01:26:57,859 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 01:26:57,859 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 01:26:57,859 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 01:26:57,860 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 01:26:57,860 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 01:26:57,868 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-23 01:26:57,875 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-23 01:26:58,976 WARN L180 SmtUtils]: Spent 1.06 s on a formula simplification. DAG size of input: 292 DAG size of output: 257 [2018-11-23 01:26:59,249 WARN L180 SmtUtils]: Spent 266.00 ms on a formula simplification that was a NOOP. DAG size: 173 [2018-11-23 01:26:59,251 INFO L216 LassoAnalysis]: Preferences: [2018-11-23 01:26:59,251 INFO L124 ssoRankerPreferences]: Compute integeral hull: false [2018-11-23 01:26:59,251 INFO L125 ssoRankerPreferences]: Enable LassoPartitioneer: true [2018-11-23 01:26:59,251 INFO L126 ssoRankerPreferences]: Term annotations enabled: false [2018-11-23 01:26:59,252 INFO L127 ssoRankerPreferences]: Use exernal solver: true [2018-11-23 01:26:59,252 INFO L128 ssoRankerPreferences]: SMT solver command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2018-11-23 01:26:59,252 INFO L129 ssoRankerPreferences]: Dump SMT script to file: false [2018-11-23 01:26:59,252 INFO L130 ssoRankerPreferences]: Path of dumped script: [2018-11-23 01:26:59,252 INFO L131 ssoRankerPreferences]: Filename of dumped script: token_ring.06_false-unreach-call_false-termination.cil.c_Iteration28_Loop [2018-11-23 01:26:59,252 INFO L132 ssoRankerPreferences]: MapElimAlgo: Frank [2018-11-23 01:26:59,252 INFO L282 LassoAnalysis]: Starting lasso preprocessing... [2018-11-23 01:26:59,255 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 01:26:59,258 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 01:26:59,261 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 01:26:59,262 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 01:26:59,263 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 01:26:59,266 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 01:26:59,267 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 01:26:59,302 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 01:26:59,304 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 01:26:59,306 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 01:26:59,310 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 01:26:59,313 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 01:26:59,317 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 01:26:59,326 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 01:26:59,328 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 01:26:59,332 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 01:26:59,335 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 01:26:59,337 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 01:26:59,340 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 01:26:59,342 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 01:26:59,346 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 01:26:59,347 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 01:26:59,351 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 01:26:59,354 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 01:26:59,355 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 01:26:59,356 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 01:26:59,366 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 01:26:59,370 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 01:26:59,376 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 01:26:59,379 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 01:26:59,383 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 01:26:59,384 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 01:26:59,388 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 01:26:59,389 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 01:26:59,392 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 01:26:59,411 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 01:26:59,413 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 01:26:59,415 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 01:26:59,418 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 01:26:59,420 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 01:26:59,425 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 01:26:59,429 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 01:26:59,433 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 01:26:59,436 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 01:26:59,438 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 01:26:59,441 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 01:26:59,443 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 01:26:59,444 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 01:26:59,447 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 01:26:59,449 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 01:26:59,452 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 01:26:59,454 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 01:26:59,456 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 01:26:59,460 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 01:26:59,463 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 01:26:59,466 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 01:26:59,469 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 01:26:59,472 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 01:26:59,487 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 01:26:59,490 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 01:26:59,492 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 01:26:59,494 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 01:26:59,497 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 01:26:59,500 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 01:26:59,502 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 01:26:59,505 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 01:26:59,508 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 01:26:59,510 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 01:26:59,513 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 01:26:59,518 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 01:26:59,522 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 01:26:59,526 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 01:26:59,529 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 01:26:59,844 INFO L300 LassoAnalysis]: Preprocessing complete. [2018-11-23 01:26:59,844 INFO L412 LassoAnalysis]: Checking for nontermination... No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_3cb46500-1f11-408a-a24e-b9ac197b8b4e/bin-2019/uautomizer/z3 Starting monitored process 9 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 9 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2018-11-23 01:26:59,849 INFO L151 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2018-11-23 01:26:59,849 INFO L163 nArgumentSynthesizer]: Using integer mode. No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_3cb46500-1f11-408a-a24e-b9ac197b8b4e/bin-2019/uautomizer/z3 Starting monitored process 10 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 10 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2018-11-23 01:26:59,867 INFO L151 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 3 Nilpotent components: true [2018-11-23 01:26:59,867 INFO L163 nArgumentSynthesizer]: Using integer mode. [2018-11-23 01:26:59,869 INFO L452 LassoAnalysis]: Proving nontermination failed: No geometric nontermination argument exists. [2018-11-23 01:26:59,882 INFO L216 LassoAnalysis]: Preferences: [2018-11-23 01:26:59,883 INFO L124 ssoRankerPreferences]: Compute integeral hull: false [2018-11-23 01:26:59,883 INFO L125 ssoRankerPreferences]: Enable LassoPartitioneer: true [2018-11-23 01:26:59,883 INFO L126 ssoRankerPreferences]: Term annotations enabled: false [2018-11-23 01:26:59,883 INFO L127 ssoRankerPreferences]: Use exernal solver: false [2018-11-23 01:26:59,883 INFO L128 ssoRankerPreferences]: SMT solver command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2018-11-23 01:26:59,883 INFO L129 ssoRankerPreferences]: Dump SMT script to file: false [2018-11-23 01:26:59,883 INFO L130 ssoRankerPreferences]: Path of dumped script: [2018-11-23 01:26:59,883 INFO L131 ssoRankerPreferences]: Filename of dumped script: token_ring.06_false-unreach-call_false-termination.cil.c_Iteration28_Loop [2018-11-23 01:26:59,883 INFO L132 ssoRankerPreferences]: MapElimAlgo: Frank [2018-11-23 01:26:59,883 INFO L282 LassoAnalysis]: Starting lasso preprocessing... [2018-11-23 01:26:59,885 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 01:26:59,892 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 01:26:59,895 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 01:26:59,896 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 01:26:59,897 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 01:26:59,898 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 01:26:59,899 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 01:26:59,899 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 01:26:59,901 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 01:26:59,901 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 01:26:59,902 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 01:26:59,906 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 01:26:59,908 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 01:26:59,909 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 01:26:59,911 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 01:26:59,913 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 01:26:59,915 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 01:26:59,916 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 01:26:59,917 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 01:26:59,924 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 01:26:59,930 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 01:26:59,933 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 01:26:59,935 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 01:26:59,936 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 01:26:59,938 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 01:26:59,938 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 01:26:59,939 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 01:26:59,941 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 01:26:59,942 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 01:26:59,943 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 01:26:59,945 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 01:26:59,947 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 01:26:59,948 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 01:26:59,951 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 01:26:59,952 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 01:26:59,955 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 01:26:59,958 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 01:26:59,959 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 01:26:59,960 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 01:26:59,962 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 01:26:59,963 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 01:26:59,964 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 01:26:59,966 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 01:26:59,966 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 01:26:59,970 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 01:26:59,972 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 01:26:59,974 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 01:26:59,977 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 01:26:59,981 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 01:26:59,987 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 01:26:59,988 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 01:26:59,991 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 01:26:59,992 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 01:26:59,994 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 01:26:59,995 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 01:26:59,996 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 01:26:59,997 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 01:26:59,999 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 01:27:00,001 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 01:27:00,004 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 01:27:00,005 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 01:27:00,006 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 01:27:00,006 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 01:27:00,007 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 01:27:00,008 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 01:27:00,009 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 01:27:00,010 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 01:27:00,011 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 01:27:00,012 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 01:27:00,015 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 01:27:00,016 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 01:27:00,019 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 01:27:00,034 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 01:27:00,384 INFO L300 LassoAnalysis]: Preprocessing complete. [2018-11-23 01:27:00,384 INFO L497 LassoAnalysis]: Using template 'affine'. [2018-11-23 01:27:00,384 INFO L122 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSES Number of strict supporting invariants: 0 Number of non-strict supporting invariants: 1 Consider only non-deceasing supporting invariants: true Simplify termination arguments: true Simplify supporting invariants: trueOverapproximate stem: false [2018-11-23 01:27:00,385 INFO L339 nArgumentSynthesizer]: Template has degree 0. [2018-11-23 01:27:00,385 INFO L352 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2018-11-23 01:27:00,385 INFO L205 nArgumentSynthesizer]: 1 stem disjuncts [2018-11-23 01:27:00,385 INFO L206 nArgumentSynthesizer]: 1 loop disjuncts [2018-11-23 01:27:00,385 INFO L207 nArgumentSynthesizer]: 2 template conjuncts. [2018-11-23 01:27:00,385 INFO L402 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2018-11-23 01:27:00,389 INFO L403 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2018-11-23 01:27:00,391 INFO L421 nArgumentSynthesizer]: Found a termination argument, trying to simplify. [2018-11-23 01:27:00,392 INFO L443 ModelExtractionUtils]: Simplification made 3 calls to the SMT solver. [2018-11-23 01:27:00,392 INFO L444 ModelExtractionUtils]: 0 out of 3 variables were initially zero. Simplification set additionally 0 variables to zero. [2018-11-23 01:27:00,392 INFO L437 nArgumentSynthesizer]: Simplifying supporting invariants... [2018-11-23 01:27:00,393 INFO L440 nArgumentSynthesizer]: Removed 0 redundant supporting invariants from a total of 0. [2018-11-23 01:27:00,393 INFO L518 LassoAnalysis]: Proved termination. [2018-11-23 01:27:00,393 INFO L520 LassoAnalysis]: Termination argument consisting of: Ranking function f(~T5_E~0) = -1*~T5_E~0 + 1 Supporting invariants [] [2018-11-23 01:27:00,393 INFO L297 tatePredicateManager]: 0 out of 0 supporting invariants were superfluous and have been removed [2018-11-23 01:27:00,409 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 01:27:00,441 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 01:27:00,444 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-23 01:27:00,496 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 01:27:00,501 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-23 01:27:00,525 INFO L134 CoverageAnalysis]: Checked inductivity of 6 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 6 trivial. 0 not checked. [2018-11-23 01:27:00,526 INFO L152 lantAutomatonBouncer]: Defining deterministic Buchi interpolant automaton with honda bouncer for stem and without honda bouncer for loop.1 stem predicates 3 loop predicates [2018-11-23 01:27:00,526 INFO L72 iDifferenceNCSBLazy3]: Start buchiDifferenceNCSBLazy3. First operand 42914 states and 55717 transitions. cyclomatic complexity: 12851 Second operand 5 states. [2018-11-23 01:27:00,883 INFO L76 iDifferenceNCSBLazy3]: Finished buchiDifferenceNCSBLazy3. First operand 42914 states and 55717 transitions. cyclomatic complexity: 12851. Second operand 5 states. Result 74068 states and 95896 transitions. Complement of second has 4 states. [2018-11-23 01:27:00,884 INFO L142 InterpolantAutomaton]: Switched to read-only mode: Buchi interpolant automaton has 3 states 1 stem states 1 non-accepting loop states 1 accepting loop states [2018-11-23 01:27:00,885 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 5 states. [2018-11-23 01:27:00,886 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3 states to 3 states and 1747 transitions. [2018-11-23 01:27:00,886 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 3 states and 1747 transitions. Stem has 80 letters. Loop has 158 letters. [2018-11-23 01:27:00,887 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2018-11-23 01:27:00,887 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 3 states and 1747 transitions. Stem has 238 letters. Loop has 158 letters. [2018-11-23 01:27:00,888 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2018-11-23 01:27:00,888 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 3 states and 1747 transitions. Stem has 80 letters. Loop has 316 letters. [2018-11-23 01:27:00,898 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2018-11-23 01:27:00,898 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 74068 states and 95896 transitions. [2018-11-23 01:27:01,123 INFO L131 ngComponentsAnalysis]: Automaton has 48 accepting balls. 44232 [2018-11-23 01:27:01,281 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 74068 states to 74068 states and 95896 transitions. [2018-11-23 01:27:01,282 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 44707 [2018-11-23 01:27:01,306 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 44788 [2018-11-23 01:27:01,306 INFO L73 IsDeterministic]: Start isDeterministic. Operand 74068 states and 95896 transitions. [2018-11-23 01:27:01,307 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2018-11-23 01:27:01,307 INFO L705 BuchiCegarLoop]: Abstraction has 74068 states and 95896 transitions. [2018-11-23 01:27:01,346 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 74068 states and 95896 transitions. [2018-11-23 01:27:01,923 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 74068 to 73987. [2018-11-23 01:27:01,923 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 73987 states. [2018-11-23 01:27:01,990 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 73987 states to 73987 states and 95735 transitions. [2018-11-23 01:27:01,990 INFO L728 BuchiCegarLoop]: Abstraction has 73987 states and 95735 transitions. [2018-11-23 01:27:01,990 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-23 01:27:01,990 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-23 01:27:01,991 INFO L87 Difference]: Start difference. First operand 73987 states and 95735 transitions. Second operand 3 states. [2018-11-23 01:27:02,093 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 01:27:02,093 INFO L93 Difference]: Finished difference Result 42146 states and 54195 transitions. [2018-11-23 01:27:02,093 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-23 01:27:02,094 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 42146 states and 54195 transitions. [2018-11-23 01:27:02,181 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 28336 [2018-11-23 01:27:02,243 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 42146 states to 42146 states and 54195 transitions. [2018-11-23 01:27:02,243 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 28682 [2018-11-23 01:27:02,256 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 28682 [2018-11-23 01:27:02,256 INFO L73 IsDeterministic]: Start isDeterministic. Operand 42146 states and 54195 transitions. [2018-11-23 01:27:02,257 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2018-11-23 01:27:02,257 INFO L705 BuchiCegarLoop]: Abstraction has 42146 states and 54195 transitions. [2018-11-23 01:27:02,274 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 42146 states and 54195 transitions. [2018-11-23 01:27:02,440 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 42146 to 42146. [2018-11-23 01:27:02,440 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 42146 states. [2018-11-23 01:27:02,479 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 42146 states to 42146 states and 54195 transitions. [2018-11-23 01:27:02,479 INFO L728 BuchiCegarLoop]: Abstraction has 42146 states and 54195 transitions. [2018-11-23 01:27:02,479 INFO L608 BuchiCegarLoop]: Abstraction has 42146 states and 54195 transitions. [2018-11-23 01:27:02,479 INFO L442 BuchiCegarLoop]: ======== Iteration 29============ [2018-11-23 01:27:02,479 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 42146 states and 54195 transitions. [2018-11-23 01:27:02,553 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 28336 [2018-11-23 01:27:02,553 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-23 01:27:02,553 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-23 01:27:02,554 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 01:27:02,554 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 01:27:02,555 INFO L794 eck$LassoCheckResult]: Stem: 790804#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0; 790590#L-1 havoc main_#res;havoc main_~__retres1~8;havoc main_~__retres1~8;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 790117#L1018 havoc start_simulation_#t~ret18, start_simulation_#t~ret19, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 790118#L470 assume 1 == ~m_i~0;~m_st~0 := 0; 789811#L477-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 789812#L482-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 790497#L487-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 790498#L492-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 790167#L497-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 790168#L502-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 790346#L507-1 assume !(0 == ~M_E~0); 789836#L686-1 assume !(0 == ~T1_E~0); 789837#L691-1 assume !(0 == ~T2_E~0); 790519#L696-1 assume !(0 == ~T3_E~0); 790520#L701-1 assume !(0 == ~T4_E~0); 790179#L706-1 assume !(0 == ~T5_E~0); 790180#L711-1 assume !(0 == ~T6_E~0); 790750#L716-1 assume !(0 == ~E_M~0); 790089#L721-1 assume !(0 == ~E_1~0); 790090#L726-1 assume !(0 == ~E_2~0); 789672#L731-1 assume !(0 == ~E_3~0); 789673#L736-1 assume !(0 == ~E_4~0); 789818#L741-1 assume !(0 == ~E_5~0); 789819#L746-1 assume !(0 == ~E_6~0); 790507#L751-1 havoc activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 790014#L336 assume !(1 == ~m_pc~0); 789897#L336-2 is_master_triggered_~__retres1~0 := 0; 789898#L347 is_master_triggered_#res := is_master_triggered_~__retres1~0; 790007#L348 activate_threads_#t~ret10 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 789863#L851 assume !(0 != activate_threads_~tmp~1); 789864#L851-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 789867#L355 assume !(1 == ~t1_pc~0); 790434#L355-2 is_transmit1_triggered_~__retres1~1 := 0; 790427#L366 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 789816#L367 activate_threads_#t~ret11 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 789817#L859 assume !(0 != activate_threads_~tmp___0~0); 790736#L859-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 790737#L374 assume !(1 == ~t2_pc~0); 790794#L374-2 is_transmit2_triggered_~__retres1~2 := 0; 790795#L385 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 790295#L386 activate_threads_#t~ret12 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 790296#L867 assume !(0 != activate_threads_~tmp___1~0); 791039#L867-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 791043#L393 assume !(1 == ~t3_pc~0); 791016#L393-2 is_transmit3_triggered_~__retres1~3 := 0; 791069#L404 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 791013#L405 activate_threads_#t~ret13 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 790100#L875 assume !(0 != activate_threads_~tmp___2~0); 790068#L875-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 790069#L412 assume !(1 == ~t4_pc~0); 790139#L412-2 is_transmit4_triggered_~__retres1~4 := 0; 790138#L423 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 789981#L424 activate_threads_#t~ret14 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 789982#L883 assume !(0 != activate_threads_~tmp___3~0); 790545#L883-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 790171#L431 assume !(1 == ~t5_pc~0); 790148#L431-2 is_transmit5_triggered_~__retres1~5 := 0; 790149#L442 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 790499#L443 activate_threads_#t~ret15 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 790500#L891 assume !(0 != activate_threads_~tmp___4~0); 790884#L891-2 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 790627#L450 assume !(1 == ~t6_pc~0); 790628#L450-2 is_transmit6_triggered_~__retres1~6 := 0; 790625#L461 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 790626#L462 activate_threads_#t~ret16 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 790845#L899 assume !(0 != activate_threads_~tmp___5~0); 790897#L899-2 assume !(1 == ~M_E~0); 789666#L764-1 assume !(1 == ~T1_E~0); 789667#L769-1 assume !(1 == ~T2_E~0); 789872#L774-1 assume !(1 == ~T3_E~0); 789873#L779-1 assume !(1 == ~T4_E~0); 790550#L784-1 assume !(1 == ~T5_E~0); 790551#L789-1 assume !(1 == ~T6_E~0); 790173#L794-1 assume !(1 == ~E_M~0); 790174#L799-1 assume !(1 == ~E_1~0); 790738#L804-1 assume !(1 == ~E_2~0); 790070#L809-1 assume !(1 == ~E_3~0); 790071#L814-1 assume !(1 == ~E_4~0); 789664#L819-1 assume !(1 == ~E_5~0); 789665#L824-1 assume !(1 == ~E_6~0); 790645#L1055-1 assume !false; 793114#L1056 [2018-11-23 01:27:02,555 INFO L796 eck$LassoCheckResult]: Loop: 793114#L1056 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret2, eval_#t~nondet3, eval_~tmp_ndt_1~0, eval_#t~nondet4, eval_~tmp_ndt_2~0, eval_#t~nondet5, eval_~tmp_ndt_3~0, eval_#t~nondet6, eval_~tmp_ndt_4~0, eval_#t~nondet7, eval_~tmp_ndt_5~0, eval_#t~nondet8, eval_~tmp_ndt_6~0, eval_#t~nondet9, eval_~tmp_ndt_7~0, eval_~tmp~0;havoc eval_~tmp~0; 808756#L661 assume !false; 808754#L568 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~7;havoc exists_runnable_thread_~__retres1~7; 808752#L520 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7 := 1; 808750#L557 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~7; 808748#L558 eval_#t~ret2 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret2;havoc eval_#t~ret2; 808746#L572 assume 0 != eval_~tmp~0; 808744#L572-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0;eval_~tmp_ndt_1~0 := eval_#t~nondet3;havoc eval_#t~nondet3; 808741#L580 assume 0 != eval_~tmp_ndt_1~0;~m_st~0 := 1;havoc master_#t~nondet0, master_#t~nondet1, master_~tmp_var~0;master_~tmp_var~0 := master_#t~nondet0;havoc master_#t~nondet0; 808742#L64 assume 0 == ~m_pc~0; 808791#L100 assume !false; 808788#L76 ~token~0 := master_#t~nondet1;havoc master_#t~nondet1;~local~0 := ~token~0;~E_1~0 := 1;havoc activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 808786#L336-3 assume !(1 == ~m_pc~0); 808782#L336-5 is_master_triggered_~__retres1~0 := 0; 808780#L347-1 is_master_triggered_#res := is_master_triggered_~__retres1~0; 808778#L348-1 activate_threads_#t~ret10 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 808776#L851-3 assume !(0 != activate_threads_~tmp~1); 808773#L851-5 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 808769#L355-3 assume !(1 == ~t1_pc~0); 808767#L355-5 is_transmit1_triggered_~__retres1~1 := 0; 808766#L366-1 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 808761#L367-1 activate_threads_#t~ret11 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 808757#L859-3 assume !(0 != activate_threads_~tmp___0~0); 808755#L859-5 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 808753#L374-3 assume !(1 == ~t2_pc~0); 808751#L374-5 is_transmit2_triggered_~__retres1~2 := 0; 808749#L385-1 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 808747#L386-1 activate_threads_#t~ret12 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 808745#L867-3 assume !(0 != activate_threads_~tmp___1~0); 808743#L867-5 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 808740#L393-3 assume !(1 == ~t3_pc~0); 808735#L393-5 is_transmit3_triggered_~__retres1~3 := 0; 808732#L404-1 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 808730#L405-1 activate_threads_#t~ret13 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 808727#L875-3 assume !(0 != activate_threads_~tmp___2~0); 808725#L875-5 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 808722#L412-3 assume !(1 == ~t4_pc~0); 808721#L412-5 is_transmit4_triggered_~__retres1~4 := 0; 808717#L423-1 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 808715#L424-1 activate_threads_#t~ret14 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 808713#L883-3 assume !(0 != activate_threads_~tmp___3~0); 808711#L883-5 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 808707#L431-3 assume !(1 == ~t5_pc~0); 808703#L431-5 is_transmit5_triggered_~__retres1~5 := 0; 808701#L442-1 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 808699#L443-1 activate_threads_#t~ret15 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 808697#L891-3 assume !(0 != activate_threads_~tmp___4~0); 808694#L891-5 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 808692#L450-3 assume !(1 == ~t6_pc~0); 808690#L450-5 is_transmit6_triggered_~__retres1~6 := 0; 808688#L461-1 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 808686#L462-1 activate_threads_#t~ret16 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 808684#L899-3 assume !(0 != activate_threads_~tmp___5~0); 808682#L899-5 ~E_1~0 := 2;~m_pc~0 := 1;~m_st~0 := 2; 808679#L577 assume !(0 == ~t1_st~0); 808675#L591 assume !(0 == ~t2_st~0); 808672#L605 assume !(0 == ~t3_st~0); 808669#L619 assume !(0 == ~t4_st~0); 808874#L633 assume !(0 == ~t5_st~0); 808872#L647 assume !(0 == ~t6_st~0); 809125#L661 assume !false; 809123#L568 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~7;havoc exists_runnable_thread_~__retres1~7; 809121#L520 assume !(0 == ~m_st~0); 809119#L524 assume !(0 == ~t1_st~0); 809117#L528 assume !(0 == ~t2_st~0); 809110#L532 assume !(0 == ~t3_st~0); 809108#L536 assume !(0 == ~t4_st~0); 809106#L540 assume !(0 == ~t5_st~0); 809102#L544 assume !(0 == ~t6_st~0);exists_runnable_thread_~__retres1~7 := 0; 809100#L557 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~7; 809098#L558 eval_#t~ret2 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret2;havoc eval_#t~ret2; 809095#L572 assume !(0 != eval_~tmp~0); 809093#L676 start_simulation_~kernel_st~0 := 2; 809091#L470-1 start_simulation_~kernel_st~0 := 3; 809090#L686-2 assume !(0 == ~M_E~0); 809089#L686-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 809087#L691-3 assume !(0 == ~T2_E~0); 809086#L696-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 809085#L701-3 assume !(0 == ~T4_E~0); 809084#L706-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 809080#L711-3 assume !(0 == ~T6_E~0); 809078#L716-3 assume 0 == ~E_M~0;~E_M~0 := 1; 809076#L721-3 assume !(0 == ~E_1~0); 809074#L726-3 assume 0 == ~E_2~0;~E_2~0 := 1; 809069#L731-3 assume !(0 == ~E_3~0); 809067#L736-3 assume !(0 == ~E_4~0); 809065#L741-3 assume !(0 == ~E_5~0); 809063#L746-3 assume !(0 == ~E_6~0); 809061#L751-3 havoc activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 809059#L336-24 assume 1 == ~m_pc~0; 809056#L337-8 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 809054#L347-8 is_master_triggered_#res := is_master_triggered_~__retres1~0; 809052#L348-8 activate_threads_#t~ret10 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 809049#L851-24 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 809047#L851-26 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 809045#L355-24 assume !(1 == ~t1_pc~0); 809043#L355-26 is_transmit1_triggered_~__retres1~1 := 0; 809041#L366-8 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 809038#L367-8 activate_threads_#t~ret11 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 809036#L859-24 assume !(0 != activate_threads_~tmp___0~0); 809034#L859-26 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 809032#L374-24 assume !(1 == ~t2_pc~0); 809030#L374-26 is_transmit2_triggered_~__retres1~2 := 0; 809028#L385-8 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 809026#L386-8 activate_threads_#t~ret12 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 809024#L867-24 assume !(0 != activate_threads_~tmp___1~0); 809022#L867-26 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 809020#L393-24 assume !(1 == ~t3_pc~0); 809017#L393-26 is_transmit3_triggered_~__retres1~3 := 0; 809015#L404-8 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 809011#L405-8 activate_threads_#t~ret13 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 809009#L875-24 assume !(0 != activate_threads_~tmp___2~0); 809007#L875-26 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 809005#L412-24 assume !(1 == ~t4_pc~0); 809002#L412-26 is_transmit4_triggered_~__retres1~4 := 0; 809000#L423-8 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 808998#L424-8 activate_threads_#t~ret14 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 808996#L883-24 assume !(0 != activate_threads_~tmp___3~0); 808994#L883-26 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 808992#L431-24 assume !(1 == ~t5_pc~0); 808988#L431-26 is_transmit5_triggered_~__retres1~5 := 0; 808986#L442-8 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 808984#L443-8 activate_threads_#t~ret15 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 808982#L891-24 assume !(0 != activate_threads_~tmp___4~0); 808979#L891-26 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 808977#L450-24 assume !(1 == ~t6_pc~0); 808975#L450-26 is_transmit6_triggered_~__retres1~6 := 0; 808973#L461-8 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 808971#L462-8 activate_threads_#t~ret16 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 808969#L899-24 assume !(0 != activate_threads_~tmp___5~0); 808967#L899-26 assume !(1 == ~M_E~0); 808965#L764-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 808963#L769-3 assume !(1 == ~T2_E~0); 808962#L774-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 808961#L779-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 808959#L784-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 808958#L789-3 assume !(1 == ~T6_E~0); 808957#L794-3 assume 1 == ~E_M~0;~E_M~0 := 2; 808956#L799-3 assume !(1 == ~E_1~0); 808954#L804-3 assume 1 == ~E_2~0;~E_2~0 := 2; 808953#L809-3 assume !(1 == ~E_3~0); 808952#L814-3 assume !(1 == ~E_4~0); 808945#L819-3 assume 1 == ~E_5~0;~E_5~0 := 2; 808943#L824-3 assume !(1 == ~E_6~0); 808941#L829-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~7;havoc exists_runnable_thread_~__retres1~7; 808938#L520-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7 := 1; 808936#L557-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~7; 808933#L558-1 start_simulation_#t~ret18 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret18;havoc start_simulation_#t~ret18; 808930#L1074 assume !(0 == start_simulation_~tmp~3); 808927#L1074-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret17, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~7;havoc exists_runnable_thread_~__retres1~7; 808925#L520-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7 := 1; 808923#L557-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~7; 808921#L558-2 stop_simulation_#t~ret17 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret17;havoc stop_simulation_#t~ret17; 808920#L1029 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 808916#L1036 stop_simulation_#res := stop_simulation_~__retres2~0; 808914#L1037 start_simulation_#t~ret19 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret19;havoc start_simulation_#t~ret19; 808912#L1087 assume !(0 != start_simulation_~tmp___0~1); 808910#L1055-1 assume !false; 793114#L1056 [2018-11-23 01:27:02,555 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 01:27:02,555 INFO L82 PathProgramCache]: Analyzing trace with hash 949927585, now seen corresponding path program 1 times [2018-11-23 01:27:02,555 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 01:27:02,555 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 01:27:02,556 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 01:27:02,556 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 01:27:02,556 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 01:27:02,560 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-23 01:27:02,564 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-23 01:27:02,576 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 01:27:02,576 INFO L82 PathProgramCache]: Analyzing trace with hash -1881444691, now seen corresponding path program 1 times [2018-11-23 01:27:02,577 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 01:27:02,577 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 01:27:02,577 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 01:27:02,577 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 01:27:02,577 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 01:27:02,583 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-23 01:27:02,589 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-23 01:27:02,611 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 01:27:02,611 INFO L82 PathProgramCache]: Analyzing trace with hash -250817203, now seen corresponding path program 1 times [2018-11-23 01:27:02,611 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 01:27:02,611 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 01:27:02,612 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 01:27:02,612 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 01:27:02,612 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 01:27:02,619 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 01:27:02,667 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 7 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 01:27:02,667 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 01:27:02,667 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-23 01:27:03,411 WARN L180 SmtUtils]: Spent 738.00 ms on a formula simplification. DAG size of input: 290 DAG size of output: 255 [2018-11-23 01:27:03,568 WARN L180 SmtUtils]: Spent 153.00 ms on a formula simplification that was a NOOP. DAG size: 175 [2018-11-23 01:27:03,573 INFO L216 LassoAnalysis]: Preferences: [2018-11-23 01:27:03,574 INFO L124 ssoRankerPreferences]: Compute integeral hull: false [2018-11-23 01:27:03,574 INFO L125 ssoRankerPreferences]: Enable LassoPartitioneer: true [2018-11-23 01:27:03,574 INFO L126 ssoRankerPreferences]: Term annotations enabled: false [2018-11-23 01:27:03,574 INFO L127 ssoRankerPreferences]: Use exernal solver: true [2018-11-23 01:27:03,574 INFO L128 ssoRankerPreferences]: SMT solver command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2018-11-23 01:27:03,574 INFO L129 ssoRankerPreferences]: Dump SMT script to file: false [2018-11-23 01:27:03,574 INFO L130 ssoRankerPreferences]: Path of dumped script: [2018-11-23 01:27:03,574 INFO L131 ssoRankerPreferences]: Filename of dumped script: token_ring.06_false-unreach-call_false-termination.cil.c_Iteration29_Loop [2018-11-23 01:27:03,574 INFO L132 ssoRankerPreferences]: MapElimAlgo: Frank [2018-11-23 01:27:03,574 INFO L282 LassoAnalysis]: Starting lasso preprocessing... [2018-11-23 01:27:03,577 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 01:27:03,579 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 01:27:03,580 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 01:27:03,581 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 01:27:03,586 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 01:27:03,591 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 01:27:03,594 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 01:27:03,595 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 01:27:03,597 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 01:27:03,600 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 01:27:03,602 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 01:27:03,603 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 01:27:03,606 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 01:27:03,607 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 01:27:03,608 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 01:27:03,614 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 01:27:03,615 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 01:27:03,616 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 01:27:03,617 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 01:27:03,620 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 01:27:03,621 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 01:27:03,623 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 01:27:03,624 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 01:27:03,625 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 01:27:03,628 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 01:27:03,629 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 01:27:03,632 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 01:27:03,633 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 01:27:03,634 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 01:27:03,637 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 01:27:03,640 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 01:27:03,642 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 01:27:03,643 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 01:27:03,644 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 01:27:03,646 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 01:27:03,649 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 01:27:03,650 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 01:27:03,651 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 01:27:03,652 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 01:27:03,653 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 01:27:03,657 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 01:27:03,659 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 01:27:03,662 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 01:27:03,663 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 01:27:03,666 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 01:27:03,667 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 01:27:03,670 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 01:27:03,671 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 01:27:03,672 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 01:27:03,674 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 01:27:03,675 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 01:27:03,677 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 01:27:03,678 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 01:27:03,679 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 01:27:03,680 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 01:27:03,680 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 01:27:03,681 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 01:27:03,682 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 01:27:03,683 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 01:27:03,684 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 01:27:03,685 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 01:27:03,685 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 01:27:03,688 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 01:27:03,689 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 01:27:03,690 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 01:27:03,691 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 01:27:03,693 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 01:27:03,694 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 01:27:03,696 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 01:27:03,698 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 01:27:03,700 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 01:27:03,701 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 01:27:04,066 WARN L180 SmtUtils]: Spent 167.00 ms on a formula simplification that was a NOOP. DAG size: 9 [2018-11-23 01:27:04,204 INFO L300 LassoAnalysis]: Preprocessing complete. [2018-11-23 01:27:04,204 INFO L412 LassoAnalysis]: Checking for nontermination... No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_3cb46500-1f11-408a-a24e-b9ac197b8b4e/bin-2019/uautomizer/z3 Starting monitored process 11 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 11 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2018-11-23 01:27:04,222 INFO L151 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2018-11-23 01:27:04,223 INFO L163 nArgumentSynthesizer]: Using integer mode. [2018-11-23 01:27:04,226 INFO L445 LassoAnalysis]: Proved nontermination for one component. [2018-11-23 01:27:04,226 INFO L448 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {~t4_st~0=-1} Honda state: {~t4_st~0=-1} Generalized eigenvectors: [] Lambdas: [] Nus: [] No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_3cb46500-1f11-408a-a24e-b9ac197b8b4e/bin-2019/uautomizer/z3 Starting monitored process 12 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 12 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2018-11-23 01:27:04,243 INFO L151 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2018-11-23 01:27:04,243 INFO L163 nArgumentSynthesizer]: Using integer mode. [2018-11-23 01:27:04,245 INFO L445 LassoAnalysis]: Proved nontermination for one component. [2018-11-23 01:27:04,245 INFO L448 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {ULTIMATE.start_stop_simulation_#t~ret17=0} Honda state: {ULTIMATE.start_stop_simulation_#t~ret17=0} Generalized eigenvectors: [] Lambdas: [] Nus: [] No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_3cb46500-1f11-408a-a24e-b9ac197b8b4e/bin-2019/uautomizer/z3 Starting monitored process 13 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 13 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2018-11-23 01:27:04,272 INFO L151 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2018-11-23 01:27:04,272 INFO L163 nArgumentSynthesizer]: Using integer mode. [2018-11-23 01:27:04,274 INFO L445 LassoAnalysis]: Proved nontermination for one component. [2018-11-23 01:27:04,274 INFO L448 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {ULTIMATE.start_eval_~tmp_ndt_5~0=0} Honda state: {ULTIMATE.start_eval_~tmp_ndt_5~0=0} Generalized eigenvectors: [] Lambdas: [] Nus: [] No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_3cb46500-1f11-408a-a24e-b9ac197b8b4e/bin-2019/uautomizer/z3 Starting monitored process 14 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 14 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2018-11-23 01:27:04,290 INFO L151 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2018-11-23 01:27:04,290 INFO L163 nArgumentSynthesizer]: Using integer mode. [2018-11-23 01:27:04,292 INFO L445 LassoAnalysis]: Proved nontermination for one component. [2018-11-23 01:27:04,292 INFO L448 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {ULTIMATE.start_eval_~tmp_ndt_6~0=0} Honda state: {ULTIMATE.start_eval_~tmp_ndt_6~0=0} Generalized eigenvectors: [] Lambdas: [] Nus: [] No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_3cb46500-1f11-408a-a24e-b9ac197b8b4e/bin-2019/uautomizer/z3 Starting monitored process 15 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 15 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2018-11-23 01:27:04,308 INFO L151 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2018-11-23 01:27:04,309 INFO L163 nArgumentSynthesizer]: Using integer mode. [2018-11-23 01:27:04,313 INFO L445 LassoAnalysis]: Proved nontermination for one component. [2018-11-23 01:27:04,313 INFO L448 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {~E_3~0=-5} Honda state: {~E_3~0=-5} Generalized eigenvectors: [] Lambdas: [] Nus: [] No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_3cb46500-1f11-408a-a24e-b9ac197b8b4e/bin-2019/uautomizer/z3 Starting monitored process 16 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 16 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2018-11-23 01:27:04,330 INFO L151 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2018-11-23 01:27:04,330 INFO L163 nArgumentSynthesizer]: Using integer mode. No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_3cb46500-1f11-408a-a24e-b9ac197b8b4e/bin-2019/uautomizer/z3 Starting monitored process 17 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 17 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2018-11-23 01:27:04,348 INFO L151 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 3 Nilpotent components: true [2018-11-23 01:27:04,348 INFO L163 nArgumentSynthesizer]: Using integer mode. [2018-11-23 01:27:04,350 INFO L452 LassoAnalysis]: Proving nontermination failed: No geometric nontermination argument exists. [2018-11-23 01:27:04,364 INFO L216 LassoAnalysis]: Preferences: [2018-11-23 01:27:04,364 INFO L124 ssoRankerPreferences]: Compute integeral hull: false [2018-11-23 01:27:04,364 INFO L125 ssoRankerPreferences]: Enable LassoPartitioneer: true [2018-11-23 01:27:04,364 INFO L126 ssoRankerPreferences]: Term annotations enabled: false [2018-11-23 01:27:04,364 INFO L127 ssoRankerPreferences]: Use exernal solver: false [2018-11-23 01:27:04,364 INFO L128 ssoRankerPreferences]: SMT solver command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2018-11-23 01:27:04,364 INFO L129 ssoRankerPreferences]: Dump SMT script to file: false [2018-11-23 01:27:04,364 INFO L130 ssoRankerPreferences]: Path of dumped script: [2018-11-23 01:27:04,364 INFO L131 ssoRankerPreferences]: Filename of dumped script: token_ring.06_false-unreach-call_false-termination.cil.c_Iteration29_Loop [2018-11-23 01:27:04,364 INFO L132 ssoRankerPreferences]: MapElimAlgo: Frank [2018-11-23 01:27:04,364 INFO L282 LassoAnalysis]: Starting lasso preprocessing... [2018-11-23 01:27:04,366 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 01:27:04,367 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 01:27:04,369 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 01:27:04,370 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 01:27:04,373 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 01:27:04,376 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 01:27:04,379 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 01:27:04,380 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 01:27:04,382 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 01:27:04,384 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 01:27:04,386 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 01:27:04,389 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 01:27:04,390 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 01:27:04,391 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 01:27:04,394 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 01:27:04,396 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 01:27:04,396 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 01:27:04,397 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 01:27:04,399 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 01:27:04,401 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 01:27:04,402 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 01:27:04,404 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 01:27:04,405 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 01:27:04,407 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 01:27:04,408 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 01:27:04,411 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 01:27:04,414 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 01:27:04,415 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 01:27:04,416 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 01:27:04,417 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 01:27:04,419 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 01:27:04,422 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 01:27:04,425 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 01:27:04,426 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 01:27:04,430 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 01:27:04,432 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 01:27:04,434 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 01:27:04,434 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 01:27:04,436 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 01:27:04,438 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 01:27:04,443 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 01:27:04,446 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 01:27:04,449 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 01:27:04,450 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 01:27:04,451 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 01:27:04,452 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 01:27:04,452 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 01:27:04,454 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 01:27:04,456 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 01:27:04,462 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 01:27:04,463 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 01:27:04,464 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 01:27:04,465 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 01:27:04,466 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 01:27:04,467 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 01:27:04,468 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 01:27:04,469 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 01:27:04,470 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 01:27:04,471 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 01:27:04,472 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 01:27:04,474 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 01:27:04,475 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 01:27:04,476 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 01:27:04,477 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 01:27:04,478 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 01:27:04,479 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 01:27:04,480 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 01:27:04,490 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 01:27:04,492 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 01:27:04,494 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 01:27:04,495 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 01:27:04,496 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 01:27:04,816 INFO L300 LassoAnalysis]: Preprocessing complete. [2018-11-23 01:27:04,816 INFO L497 LassoAnalysis]: Using template 'affine'. [2018-11-23 01:27:04,816 INFO L122 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSES Number of strict supporting invariants: 0 Number of non-strict supporting invariants: 1 Consider only non-deceasing supporting invariants: true Simplify termination arguments: true Simplify supporting invariants: trueOverapproximate stem: false [2018-11-23 01:27:04,816 INFO L339 nArgumentSynthesizer]: Template has degree 0. [2018-11-23 01:27:04,816 INFO L352 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2018-11-23 01:27:04,817 INFO L205 nArgumentSynthesizer]: 1 stem disjuncts [2018-11-23 01:27:04,817 INFO L206 nArgumentSynthesizer]: 2 loop disjuncts [2018-11-23 01:27:04,817 INFO L207 nArgumentSynthesizer]: 2 template conjuncts. [2018-11-23 01:27:04,817 INFO L402 nArgumentSynthesizer]: We have 4 Motzkin's Theorem applications. [2018-11-23 01:27:04,817 INFO L403 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2018-11-23 01:27:04,818 INFO L530 LassoAnalysis]: Proving termination failed for this template and these settings. [2018-11-23 01:27:04,818 INFO L122 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSES Number of strict supporting invariants: 0 Number of non-strict supporting invariants: 1 Consider only non-deceasing supporting invariants: true Simplify termination arguments: true Simplify supporting invariants: trueOverapproximate stem: false [2018-11-23 01:27:04,818 INFO L339 nArgumentSynthesizer]: Template has degree 0. [2018-11-23 01:27:04,818 INFO L352 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2018-11-23 01:27:04,819 INFO L205 nArgumentSynthesizer]: 1 stem disjuncts [2018-11-23 01:27:04,819 INFO L206 nArgumentSynthesizer]: 1 loop disjuncts [2018-11-23 01:27:04,819 INFO L207 nArgumentSynthesizer]: 2 template conjuncts. [2018-11-23 01:27:04,819 INFO L402 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2018-11-23 01:27:04,819 INFO L403 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2018-11-23 01:27:04,820 INFO L530 LassoAnalysis]: Proving termination failed for this template and these settings. [2018-11-23 01:27:04,820 INFO L122 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSES Number of strict supporting invariants: 0 Number of non-strict supporting invariants: 1 Consider only non-deceasing supporting invariants: true Simplify termination arguments: true Simplify supporting invariants: trueOverapproximate stem: false [2018-11-23 01:27:04,820 INFO L339 nArgumentSynthesizer]: Template has degree 0. [2018-11-23 01:27:04,820 INFO L352 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2018-11-23 01:27:04,820 INFO L205 nArgumentSynthesizer]: 1 stem disjuncts [2018-11-23 01:27:04,820 INFO L206 nArgumentSynthesizer]: 1 loop disjuncts [2018-11-23 01:27:04,820 INFO L207 nArgumentSynthesizer]: 2 template conjuncts. [2018-11-23 01:27:04,821 INFO L402 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2018-11-23 01:27:04,821 INFO L403 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2018-11-23 01:27:04,821 INFO L530 LassoAnalysis]: Proving termination failed for this template and these settings. [2018-11-23 01:27:04,821 INFO L122 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSES Number of strict supporting invariants: 0 Number of non-strict supporting invariants: 1 Consider only non-deceasing supporting invariants: true Simplify termination arguments: true Simplify supporting invariants: trueOverapproximate stem: false [2018-11-23 01:27:04,822 INFO L339 nArgumentSynthesizer]: Template has degree 0. [2018-11-23 01:27:04,822 INFO L352 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2018-11-23 01:27:04,822 INFO L205 nArgumentSynthesizer]: 1 stem disjuncts [2018-11-23 01:27:04,822 INFO L206 nArgumentSynthesizer]: 1 loop disjuncts [2018-11-23 01:27:04,822 INFO L207 nArgumentSynthesizer]: 2 template conjuncts. [2018-11-23 01:27:04,822 INFO L402 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2018-11-23 01:27:04,823 INFO L403 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2018-11-23 01:27:04,823 INFO L530 LassoAnalysis]: Proving termination failed for this template and these settings. [2018-11-23 01:27:04,824 INFO L122 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSES Number of strict supporting invariants: 0 Number of non-strict supporting invariants: 1 Consider only non-deceasing supporting invariants: true Simplify termination arguments: true Simplify supporting invariants: trueOverapproximate stem: false [2018-11-23 01:27:04,824 INFO L339 nArgumentSynthesizer]: Template has degree 0. [2018-11-23 01:27:04,824 INFO L352 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2018-11-23 01:27:04,824 INFO L205 nArgumentSynthesizer]: 1 stem disjuncts [2018-11-23 01:27:04,824 INFO L206 nArgumentSynthesizer]: 2 loop disjuncts [2018-11-23 01:27:04,824 INFO L207 nArgumentSynthesizer]: 2 template conjuncts. [2018-11-23 01:27:04,825 INFO L402 nArgumentSynthesizer]: We have 4 Motzkin's Theorem applications. [2018-11-23 01:27:04,825 INFO L403 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2018-11-23 01:27:04,825 INFO L530 LassoAnalysis]: Proving termination failed for this template and these settings. [2018-11-23 01:27:04,825 INFO L122 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSES Number of strict supporting invariants: 0 Number of non-strict supporting invariants: 1 Consider only non-deceasing supporting invariants: true Simplify termination arguments: true Simplify supporting invariants: trueOverapproximate stem: false [2018-11-23 01:27:04,826 INFO L339 nArgumentSynthesizer]: Template has degree 0. [2018-11-23 01:27:04,826 INFO L352 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2018-11-23 01:27:04,826 INFO L205 nArgumentSynthesizer]: 1 stem disjuncts [2018-11-23 01:27:04,826 INFO L206 nArgumentSynthesizer]: 1 loop disjuncts [2018-11-23 01:27:04,826 INFO L207 nArgumentSynthesizer]: 2 template conjuncts. [2018-11-23 01:27:04,826 INFO L402 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2018-11-23 01:27:04,826 INFO L403 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2018-11-23 01:27:04,828 INFO L421 nArgumentSynthesizer]: Found a termination argument, trying to simplify. [2018-11-23 01:27:04,829 INFO L443 ModelExtractionUtils]: Simplification made 3 calls to the SMT solver. [2018-11-23 01:27:04,829 INFO L444 ModelExtractionUtils]: 0 out of 3 variables were initially zero. Simplification set additionally 0 variables to zero. [2018-11-23 01:27:04,829 INFO L437 nArgumentSynthesizer]: Simplifying supporting invariants... [2018-11-23 01:27:04,829 INFO L440 nArgumentSynthesizer]: Removed 0 redundant supporting invariants from a total of 0. [2018-11-23 01:27:04,829 INFO L518 LassoAnalysis]: Proved termination. [2018-11-23 01:27:04,829 INFO L520 LassoAnalysis]: Termination argument consisting of: Ranking function f(~T4_E~0) = -2*~T4_E~0 + 3 Supporting invariants [] [2018-11-23 01:27:04,830 INFO L297 tatePredicateManager]: 0 out of 0 supporting invariants were superfluous and have been removed [2018-11-23 01:27:04,894 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 01:27:04,915 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 01:27:04,917 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-23 01:27:04,953 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 01:27:04,955 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-23 01:27:04,998 INFO L134 CoverageAnalysis]: Checked inductivity of 6 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 6 trivial. 0 not checked. [2018-11-23 01:27:04,998 INFO L152 lantAutomatonBouncer]: Defining deterministic Buchi interpolant automaton with honda bouncer for stem and without honda bouncer for loop.1 stem predicates 2 loop predicates [2018-11-23 01:27:04,998 INFO L72 iDifferenceNCSBLazy3]: Start buchiDifferenceNCSBLazy3. First operand 42146 states and 54195 transitions. cyclomatic complexity: 12097 Second operand 4 states. [2018-11-23 01:27:05,296 INFO L76 iDifferenceNCSBLazy3]: Finished buchiDifferenceNCSBLazy3. First operand 42146 states and 54195 transitions. cyclomatic complexity: 12097. Second operand 4 states. Result 84685 states and 109240 transitions. Complement of second has 4 states. [2018-11-23 01:27:05,296 INFO L142 InterpolantAutomaton]: Switched to read-only mode: Buchi interpolant automaton has 3 states 1 stem states 1 non-accepting loop states 1 accepting loop states [2018-11-23 01:27:05,296 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 4 states. [2018-11-23 01:27:05,297 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3 states to 3 states and 913 transitions. [2018-11-23 01:27:05,297 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 3 states and 913 transitions. Stem has 81 letters. Loop has 158 letters. [2018-11-23 01:27:05,298 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2018-11-23 01:27:05,298 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 3 states and 913 transitions. Stem has 239 letters. Loop has 158 letters. [2018-11-23 01:27:05,298 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2018-11-23 01:27:05,298 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 3 states and 913 transitions. Stem has 81 letters. Loop has 316 letters. [2018-11-23 01:27:05,299 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2018-11-23 01:27:05,299 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 84685 states and 109240 transitions. [2018-11-23 01:27:05,471 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 28336 [2018-11-23 01:27:05,626 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 84685 states to 84685 states and 109240 transitions. [2018-11-23 01:27:05,626 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 28763 [2018-11-23 01:27:05,639 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 28924 [2018-11-23 01:27:05,640 INFO L73 IsDeterministic]: Start isDeterministic. Operand 84685 states and 109240 transitions. [2018-11-23 01:27:05,640 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2018-11-23 01:27:05,640 INFO L705 BuchiCegarLoop]: Abstraction has 84685 states and 109240 transitions. [2018-11-23 01:27:05,680 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 84685 states and 109240 transitions. [2018-11-23 01:27:06,026 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 84685 to 84524. [2018-11-23 01:27:06,026 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 84524 states. [2018-11-23 01:27:06,105 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 84524 states to 84524 states and 109079 transitions. [2018-11-23 01:27:06,105 INFO L728 BuchiCegarLoop]: Abstraction has 84524 states and 109079 transitions. [2018-11-23 01:27:06,105 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-23 01:27:06,105 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-23 01:27:06,105 INFO L87 Difference]: Start difference. First operand 84524 states and 109079 transitions. Second operand 3 states. [2018-11-23 01:27:06,603 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 01:27:06,603 INFO L93 Difference]: Finished difference Result 144995 states and 185512 transitions. [2018-11-23 01:27:06,603 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-23 01:27:06,603 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 144995 states and 185512 transitions. [2018-11-23 01:27:06,898 INFO L131 ngComponentsAnalysis]: Automaton has 48 accepting balls. 46368 [2018-11-23 01:27:07,108 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 144995 states to 144995 states and 185512 transitions. [2018-11-23 01:27:07,109 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 49553 [2018-11-23 01:27:07,131 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 49553 [2018-11-23 01:27:07,131 INFO L73 IsDeterministic]: Start isDeterministic. Operand 144995 states and 185512 transitions. [2018-11-23 01:27:07,132 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2018-11-23 01:27:07,132 INFO L705 BuchiCegarLoop]: Abstraction has 144995 states and 185512 transitions. [2018-11-23 01:27:07,187 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 144995 states and 185512 transitions. [2018-11-23 01:27:07,791 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 144995 to 144995. [2018-11-23 01:27:07,791 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 144995 states. [2018-11-23 01:27:07,932 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 144995 states to 144995 states and 185512 transitions. [2018-11-23 01:27:07,932 INFO L728 BuchiCegarLoop]: Abstraction has 144995 states and 185512 transitions. [2018-11-23 01:27:07,932 INFO L608 BuchiCegarLoop]: Abstraction has 144995 states and 185512 transitions. [2018-11-23 01:27:07,932 INFO L442 BuchiCegarLoop]: ======== Iteration 30============ [2018-11-23 01:27:07,932 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 144995 states and 185512 transitions. [2018-11-23 01:27:08,146 INFO L131 ngComponentsAnalysis]: Automaton has 48 accepting balls. 46368 [2018-11-23 01:27:08,146 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-23 01:27:08,146 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-23 01:27:08,147 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 01:27:08,147 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 01:27:08,148 INFO L794 eck$LassoCheckResult]: Stem: 1147966#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0; 1147733#L-1 havoc main_#res;havoc main_~__retres1~8;havoc main_~__retres1~8;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 1147232#L1018 havoc start_simulation_#t~ret18, start_simulation_#t~ret19, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 1147233#L470 assume 1 == ~m_i~0;~m_st~0 := 0; 1146904#L477-1 assume !(1 == ~t1_i~0);~t1_st~0 := 2; 1146905#L482-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1148242#L487-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 1148326#L492-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 1148327#L497-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 1148189#L502-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 1148190#L507-1 assume !(0 == ~M_E~0); 1146936#L686-1 assume !(0 == ~T1_E~0); 1146937#L691-1 assume !(0 == ~T2_E~0); 1147662#L696-1 assume !(0 == ~T3_E~0); 1147663#L701-1 assume !(0 == ~T4_E~0); 1148333#L706-1 assume !(0 == ~T5_E~0); 1148197#L711-1 assume !(0 == ~T6_E~0); 1148198#L716-1 assume !(0 == ~E_M~0); 1147200#L721-1 assume !(0 == ~E_1~0); 1147201#L726-1 assume !(0 == ~E_2~0); 1146758#L731-1 assume !(0 == ~E_3~0); 1146759#L736-1 assume !(0 == ~E_4~0); 1146914#L741-1 assume !(0 == ~E_5~0); 1146915#L746-1 assume !(0 == ~E_6~0); 1147649#L751-1 havoc activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 1147650#L336 assume !(1 == ~m_pc~0); 1146998#L336-2 is_master_triggered_~__retres1~0 := 0; 1146999#L347 is_master_triggered_#res := is_master_triggered_~__retres1~0; 1148340#L348 activate_threads_#t~ret10 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 1148341#L851 assume !(0 != activate_threads_~tmp~1); 1146963#L851-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 1146964#L355 assume !(1 == ~t1_pc~0); 1147582#L355-2 is_transmit1_triggered_~__retres1~1 := 0; 1147583#L366 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 1146912#L367 activate_threads_#t~ret11 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 1146913#L859 assume !(0 != activate_threads_~tmp___0~0); 1147887#L859-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 1147888#L374 assume !(1 == ~t2_pc~0); 1147953#L374-2 is_transmit2_triggered_~__retres1~2 := 0; 1147954#L385 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 1147421#L386 activate_threads_#t~ret12 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 1147422#L867 assume !(0 != activate_threads_~tmp___1~0); 1148272#L867-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 1148273#L393 assume !(1 == ~t3_pc~0); 1181011#L393-2 is_transmit3_triggered_~__retres1~3 := 0; 1181010#L404 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 1181009#L405 activate_threads_#t~ret13 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 1181008#L875 assume !(0 != activate_threads_~tmp___2~0); 1181007#L875-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 1181004#L412 assume !(1 == ~t4_pc~0); 1181002#L412-2 is_transmit4_triggered_~__retres1~4 := 0; 1181000#L423 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 1180998#L424 activate_threads_#t~ret14 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 1180996#L883 assume !(0 != activate_threads_~tmp___3~0); 1180994#L883-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 1180992#L431 assume !(1 == ~t5_pc~0); 1180988#L431-2 is_transmit5_triggered_~__retres1~5 := 0; 1180986#L442 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 1180984#L443 activate_threads_#t~ret15 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 1180982#L891 assume !(0 != activate_threads_~tmp___4~0); 1180979#L891-2 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 1180975#L450 assume !(1 == ~t6_pc~0); 1180973#L450-2 is_transmit6_triggered_~__retres1~6 := 0; 1180971#L461 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 1180969#L462 activate_threads_#t~ret16 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 1180966#L899 assume !(0 != activate_threads_~tmp___5~0); 1180964#L899-2 assume !(1 == ~M_E~0); 1180962#L764-1 assume !(1 == ~T1_E~0); 1180960#L769-1 assume !(1 == ~T2_E~0); 1180958#L774-1 assume !(1 == ~T3_E~0); 1180956#L779-1 assume !(1 == ~T4_E~0); 1180954#L784-1 assume !(1 == ~T5_E~0); 1180952#L789-1 assume !(1 == ~T6_E~0); 1180950#L794-1 assume !(1 == ~E_M~0); 1180948#L799-1 assume !(1 == ~E_1~0); 1180946#L804-1 assume !(1 == ~E_2~0); 1180943#L809-1 assume !(1 == ~E_3~0); 1180941#L814-1 assume !(1 == ~E_4~0); 1180939#L819-1 assume !(1 == ~E_5~0); 1180937#L824-1 assume !(1 == ~E_6~0); 1180476#L1055-1 assume !false; 1180478#L1056 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret2, eval_#t~nondet3, eval_~tmp_ndt_1~0, eval_#t~nondet4, eval_~tmp_ndt_2~0, eval_#t~nondet5, eval_~tmp_ndt_3~0, eval_#t~nondet6, eval_~tmp_ndt_4~0, eval_#t~nondet7, eval_~tmp_ndt_5~0, eval_#t~nondet8, eval_~tmp_ndt_6~0, eval_#t~nondet9, eval_~tmp_ndt_7~0, eval_~tmp~0;havoc eval_~tmp~0; 1186907#L661 [2018-11-23 01:27:08,148 INFO L796 eck$LassoCheckResult]: Loop: 1186907#L661 assume !false; 1205070#L568 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~7;havoc exists_runnable_thread_~__retres1~7; 1205063#L520 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7 := 1; 1205055#L557 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~7; 1205047#L558 eval_#t~ret2 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret2;havoc eval_#t~ret2; 1205040#L572 assume 0 != eval_~tmp~0; 1205032#L572-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0;eval_~tmp_ndt_1~0 := eval_#t~nondet3;havoc eval_#t~nondet3; 1205022#L580 assume !(0 != eval_~tmp_ndt_1~0); 1205015#L577 assume !(0 == ~t1_st~0); 1205006#L591 assume !(0 == ~t2_st~0); 1204998#L605 assume !(0 == ~t3_st~0); 1205105#L619 assume !(0 == ~t4_st~0); 1205093#L633 assume !(0 == ~t5_st~0); 1205087#L647 assume !(0 == ~t6_st~0); 1186907#L661 [2018-11-23 01:27:08,148 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 01:27:08,148 INFO L82 PathProgramCache]: Analyzing trace with hash 222018116, now seen corresponding path program 1 times [2018-11-23 01:27:08,148 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 01:27:08,148 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 01:27:08,149 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 01:27:08,149 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 01:27:08,149 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 01:27:08,152 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 01:27:08,179 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 01:27:08,179 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 01:27:08,179 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-23 01:27:08,180 INFO L799 eck$LassoCheckResult]: stem already infeasible [2018-11-23 01:27:08,180 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 01:27:08,180 INFO L82 PathProgramCache]: Analyzing trace with hash -1700136271, now seen corresponding path program 1 times [2018-11-23 01:27:08,180 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 01:27:08,180 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 01:27:08,181 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 01:27:08,181 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 01:27:08,181 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 01:27:08,182 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-23 01:27:08,183 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-23 01:27:08,244 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-23 01:27:08,244 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-23 01:27:08,244 INFO L87 Difference]: Start difference. First operand 144995 states and 185512 transitions. cyclomatic complexity: 40661 Second operand 3 states. [2018-11-23 01:27:08,423 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 01:27:08,423 INFO L93 Difference]: Finished difference Result 98724 states and 126086 transitions. [2018-11-23 01:27:08,423 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-23 01:27:08,424 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 98724 states and 126086 transitions. [2018-11-23 01:27:08,634 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 33328 [2018-11-23 01:27:09,223 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 98724 states to 98724 states and 126086 transitions. [2018-11-23 01:27:09,223 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 33827 [2018-11-23 01:27:09,237 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 33827 [2018-11-23 01:27:09,237 INFO L73 IsDeterministic]: Start isDeterministic. Operand 98724 states and 126086 transitions. [2018-11-23 01:27:09,244 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2018-11-23 01:27:09,245 INFO L705 BuchiCegarLoop]: Abstraction has 98724 states and 126086 transitions. [2018-11-23 01:27:09,287 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 98724 states and 126086 transitions. [2018-11-23 01:27:09,696 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 98724 to 98724. [2018-11-23 01:27:09,697 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 98724 states. [2018-11-23 01:27:09,793 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 98724 states to 98724 states and 126086 transitions. [2018-11-23 01:27:09,793 INFO L728 BuchiCegarLoop]: Abstraction has 98724 states and 126086 transitions. [2018-11-23 01:27:09,793 INFO L608 BuchiCegarLoop]: Abstraction has 98724 states and 126086 transitions. [2018-11-23 01:27:09,793 INFO L442 BuchiCegarLoop]: ======== Iteration 31============ [2018-11-23 01:27:09,793 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 98724 states and 126086 transitions. [2018-11-23 01:27:09,939 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 33328 [2018-11-23 01:27:09,939 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-23 01:27:09,939 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-23 01:27:09,940 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 01:27:09,940 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 01:27:09,940 INFO L794 eck$LassoCheckResult]: Stem: 1391630#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0; 1391414#L-1 havoc main_#res;havoc main_~__retres1~8;havoc main_~__retres1~8;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 1390939#L1018 havoc start_simulation_#t~ret18, start_simulation_#t~ret19, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 1390940#L470 assume 1 == ~m_i~0;~m_st~0 := 0; 1390625#L477-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1390626#L482-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1391322#L487-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 1391323#L492-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 1390989#L497-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 1390990#L502-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 1391173#L507-1 assume !(0 == ~M_E~0); 1390653#L686-1 assume !(0 == ~T1_E~0); 1390654#L691-1 assume !(0 == ~T2_E~0); 1391344#L696-1 assume !(0 == ~T3_E~0); 1391345#L701-1 assume !(0 == ~T4_E~0); 1391001#L706-1 assume !(0 == ~T5_E~0); 1391002#L711-1 assume !(0 == ~T6_E~0); 1391574#L716-1 assume !(0 == ~E_M~0); 1390910#L721-1 assume !(0 == ~E_1~0); 1390911#L726-1 assume !(0 == ~E_2~0); 1390483#L731-1 assume !(0 == ~E_3~0); 1390484#L736-1 assume !(0 == ~E_4~0); 1390633#L741-1 assume !(0 == ~E_5~0); 1390634#L746-1 assume !(0 == ~E_6~0); 1391335#L751-1 havoc activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 1390834#L336 assume !(1 == ~m_pc~0); 1390712#L336-2 is_master_triggered_~__retres1~0 := 0; 1390713#L347 is_master_triggered_#res := is_master_triggered_~__retres1~0; 1391944#L348 activate_threads_#t~ret10 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 1390675#L851 assume !(0 != activate_threads_~tmp~1); 1390676#L851-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 1390679#L355 assume !(1 == ~t1_pc~0); 1391251#L355-2 is_transmit1_triggered_~__retres1~1 := 0; 1391250#L366 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 1390631#L367 activate_threads_#t~ret11 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 1390632#L859 assume !(0 != activate_threads_~tmp___0~0); 1391561#L859-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 1391562#L374 assume !(1 == ~t2_pc~0); 1391618#L374-2 is_transmit2_triggered_~__retres1~2 := 0; 1391619#L385 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 1391122#L386 activate_threads_#t~ret12 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 1391123#L867 assume !(0 != activate_threads_~tmp___1~0); 1391892#L867-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 1391895#L393 assume !(1 == ~t3_pc~0); 1391871#L393-2 is_transmit3_triggered_~__retres1~3 := 0; 1391917#L404 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 1391869#L405 activate_threads_#t~ret13 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 1390925#L875 assume !(0 != activate_threads_~tmp___2~0); 1390890#L875-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 1390891#L412 assume !(1 == ~t4_pc~0); 1390958#L412-2 is_transmit4_triggered_~__retres1~4 := 0; 1390957#L423 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 1390798#L424 activate_threads_#t~ret14 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 1390799#L883 assume !(0 != activate_threads_~tmp___3~0); 1391367#L883-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 1390993#L431 assume !(1 == ~t5_pc~0); 1390969#L431-2 is_transmit5_triggered_~__retres1~5 := 0; 1390970#L442 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 1391324#L443 activate_threads_#t~ret15 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 1391325#L891 assume !(0 != activate_threads_~tmp___4~0); 1391719#L891-2 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 1391453#L450 assume !(1 == ~t6_pc~0); 1391454#L450-2 is_transmit6_triggered_~__retres1~6 := 0; 1391451#L461 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 1391452#L462 activate_threads_#t~ret16 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 1391672#L899 assume !(0 != activate_threads_~tmp___5~0); 1391730#L899-2 assume !(1 == ~M_E~0); 1390477#L764-1 assume !(1 == ~T1_E~0); 1390478#L769-1 assume !(1 == ~T2_E~0); 1390682#L774-1 assume !(1 == ~T3_E~0); 1390683#L779-1 assume !(1 == ~T4_E~0); 1391371#L784-1 assume !(1 == ~T5_E~0); 1391372#L789-1 assume !(1 == ~T6_E~0); 1390995#L794-1 assume !(1 == ~E_M~0); 1390996#L799-1 assume !(1 == ~E_1~0); 1391563#L804-1 assume !(1 == ~E_2~0); 1390898#L809-1 assume !(1 == ~E_3~0); 1390899#L814-1 assume !(1 == ~E_4~0); 1390475#L819-1 assume !(1 == ~E_5~0); 1390476#L824-1 assume !(1 == ~E_6~0); 1391466#L1055-1 assume !false; 1400748#L1056 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret2, eval_#t~nondet3, eval_~tmp_ndt_1~0, eval_#t~nondet4, eval_~tmp_ndt_2~0, eval_#t~nondet5, eval_~tmp_ndt_3~0, eval_#t~nondet6, eval_~tmp_ndt_4~0, eval_#t~nondet7, eval_~tmp_ndt_5~0, eval_#t~nondet8, eval_~tmp_ndt_6~0, eval_#t~nondet9, eval_~tmp_ndt_7~0, eval_~tmp~0;havoc eval_~tmp~0; 1426324#L661 [2018-11-23 01:27:09,940 INFO L796 eck$LassoCheckResult]: Loop: 1426324#L661 assume !false; 1426323#L568 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~7;havoc exists_runnable_thread_~__retres1~7; 1426322#L520 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7 := 1; 1426321#L557 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~7; 1426320#L558 eval_#t~ret2 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret2;havoc eval_#t~ret2; 1426319#L572 assume 0 != eval_~tmp~0; 1426316#L572-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0;eval_~tmp_ndt_1~0 := eval_#t~nondet3;havoc eval_#t~nondet3; 1426314#L580 assume !(0 != eval_~tmp_ndt_1~0); 1426315#L577 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0;eval_~tmp_ndt_2~0 := eval_#t~nondet4;havoc eval_#t~nondet4; 1426876#L594 assume !(0 != eval_~tmp_ndt_2~0); 1426875#L591 assume !(0 == ~t2_st~0); 1426344#L605 assume !(0 == ~t3_st~0); 1426337#L619 assume !(0 == ~t4_st~0); 1426330#L633 assume !(0 == ~t5_st~0); 1426329#L647 assume !(0 == ~t6_st~0); 1426324#L661 [2018-11-23 01:27:09,940 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 01:27:09,940 INFO L82 PathProgramCache]: Analyzing trace with hash -617015546, now seen corresponding path program 1 times [2018-11-23 01:27:09,940 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 01:27:09,940 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 01:27:09,941 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 01:27:09,941 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 01:27:09,941 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 01:27:09,944 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-23 01:27:09,949 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-23 01:27:09,964 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 01:27:09,964 INFO L82 PathProgramCache]: Analyzing trace with hash 1731504578, now seen corresponding path program 1 times [2018-11-23 01:27:09,964 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 01:27:09,964 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 01:27:09,965 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 01:27:09,965 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 01:27:09,965 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 01:27:09,966 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-23 01:27:09,968 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-23 01:27:09,969 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 01:27:09,969 INFO L82 PathProgramCache]: Analyzing trace with hash 363071517, now seen corresponding path program 1 times [2018-11-23 01:27:09,969 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 01:27:09,969 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 01:27:09,970 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 01:27:09,970 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 01:27:09,970 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 01:27:09,974 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 01:27:10,020 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 01:27:10,020 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 01:27:10,020 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-23 01:27:10,073 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-23 01:27:10,073 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-23 01:27:10,073 INFO L87 Difference]: Start difference. First operand 98724 states and 126086 transitions. cyclomatic complexity: 27458 Second operand 3 states. [2018-11-23 01:27:10,305 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 01:27:10,305 INFO L93 Difference]: Finished difference Result 136076 states and 173054 transitions. [2018-11-23 01:27:10,305 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-23 01:27:10,305 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 136076 states and 173054 transitions. [2018-11-23 01:27:10,579 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 46132 [2018-11-23 01:27:10,776 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 136076 states to 136076 states and 173054 transitions. [2018-11-23 01:27:10,776 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 46755 [2018-11-23 01:27:10,797 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 46755 [2018-11-23 01:27:10,797 INFO L73 IsDeterministic]: Start isDeterministic. Operand 136076 states and 173054 transitions. [2018-11-23 01:27:10,822 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2018-11-23 01:27:10,822 INFO L705 BuchiCegarLoop]: Abstraction has 136076 states and 173054 transitions. [2018-11-23 01:27:10,888 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 136076 states and 173054 transitions. [2018-11-23 01:27:14,062 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 136076 to 130676. [2018-11-23 01:27:14,062 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 130676 states. [2018-11-23 01:27:14,200 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 130676 states to 130676 states and 166502 transitions. [2018-11-23 01:27:14,200 INFO L728 BuchiCegarLoop]: Abstraction has 130676 states and 166502 transitions. [2018-11-23 01:27:14,200 INFO L608 BuchiCegarLoop]: Abstraction has 130676 states and 166502 transitions. [2018-11-23 01:27:14,201 INFO L442 BuchiCegarLoop]: ======== Iteration 32============ [2018-11-23 01:27:14,201 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 130676 states and 166502 transitions. [2018-11-23 01:27:14,387 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 44332 [2018-11-23 01:27:14,387 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-23 01:27:14,388 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-23 01:27:14,388 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 01:27:14,388 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 01:27:14,388 INFO L794 eck$LassoCheckResult]: Stem: 1626495#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0; 1626259#L-1 havoc main_#res;havoc main_~__retres1~8;havoc main_~__retres1~8;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 1625750#L1018 havoc start_simulation_#t~ret18, start_simulation_#t~ret19, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 1625751#L470 assume 1 == ~m_i~0;~m_st~0 := 0; 1625435#L477-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1625436#L482-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1626157#L487-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 1626158#L492-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 1625802#L497-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 1625803#L502-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 1625997#L507-1 assume !(0 == ~M_E~0); 1625465#L686-1 assume !(0 == ~T1_E~0); 1625466#L691-1 assume !(0 == ~T2_E~0); 1626180#L696-1 assume !(0 == ~T3_E~0); 1626181#L701-1 assume !(0 == ~T4_E~0); 1625814#L706-1 assume !(0 == ~T5_E~0); 1625815#L711-1 assume !(0 == ~T6_E~0); 1626428#L716-1 assume !(0 == ~E_M~0); 1625721#L721-1 assume !(0 == ~E_1~0); 1625722#L726-1 assume !(0 == ~E_2~0); 1625291#L731-1 assume !(0 == ~E_3~0); 1625292#L736-1 assume !(0 == ~E_4~0); 1625444#L741-1 assume !(0 == ~E_5~0); 1625445#L746-1 assume !(0 == ~E_6~0); 1626169#L751-1 havoc activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 1625646#L336 assume !(1 == ~m_pc~0); 1625524#L336-2 is_master_triggered_~__retres1~0 := 0; 1625525#L347 is_master_triggered_#res := is_master_triggered_~__retres1~0; 1626865#L348 activate_threads_#t~ret10 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 1625486#L851 assume !(0 != activate_threads_~tmp~1); 1625487#L851-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 1625490#L355 assume !(1 == ~t1_pc~0); 1626079#L355-2 is_transmit1_triggered_~__retres1~1 := 0; 1626078#L366 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 1625442#L367 activate_threads_#t~ret11 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 1625443#L859 assume !(0 != activate_threads_~tmp___0~0); 1626413#L859-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 1626414#L374 assume !(1 == ~t2_pc~0); 1626484#L374-2 is_transmit2_triggered_~__retres1~2 := 0; 1626485#L385 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 1625936#L386 activate_threads_#t~ret12 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 1625937#L867 assume !(0 != activate_threads_~tmp___1~0); 1626798#L867-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 1626801#L393 assume !(1 == ~t3_pc~0); 1626772#L393-2 is_transmit3_triggered_~__retres1~3 := 0; 1626828#L404 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 1626768#L405 activate_threads_#t~ret13 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 1625738#L875 assume !(0 != activate_threads_~tmp___2~0); 1625701#L875-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 1625702#L412 assume !(1 == ~t4_pc~0); 1625770#L412-2 is_transmit4_triggered_~__retres1~4 := 0; 1625769#L423 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 1625610#L424 activate_threads_#t~ret14 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 1625611#L883 assume !(0 != activate_threads_~tmp___3~0); 1626209#L883-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 1625806#L431 assume !(1 == ~t5_pc~0); 1625781#L431-2 is_transmit5_triggered_~__retres1~5 := 0; 1625782#L442 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 1626159#L443 activate_threads_#t~ret15 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 1626160#L891 assume !(0 != activate_threads_~tmp___4~0); 1626605#L891-2 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 1626299#L450 assume !(1 == ~t6_pc~0); 1626300#L450-2 is_transmit6_triggered_~__retres1~6 := 0; 1626297#L461 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 1626298#L462 activate_threads_#t~ret16 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 1626543#L899 assume !(0 != activate_threads_~tmp___5~0); 1626620#L899-2 assume !(1 == ~M_E~0); 1625285#L764-1 assume !(1 == ~T1_E~0); 1625286#L769-1 assume !(1 == ~T2_E~0); 1625494#L774-1 assume !(1 == ~T3_E~0); 1625495#L779-1 assume !(1 == ~T4_E~0); 1626214#L784-1 assume !(1 == ~T5_E~0); 1626215#L789-1 assume !(1 == ~T6_E~0); 1625808#L794-1 assume !(1 == ~E_M~0); 1625809#L799-1 assume !(1 == ~E_1~0); 1626415#L804-1 assume !(1 == ~E_2~0); 1625705#L809-1 assume !(1 == ~E_3~0); 1625706#L814-1 assume !(1 == ~E_4~0); 1625283#L819-1 assume !(1 == ~E_5~0); 1625284#L824-1 assume !(1 == ~E_6~0); 1626314#L1055-1 assume !false; 1636538#L1056 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret2, eval_#t~nondet3, eval_~tmp_ndt_1~0, eval_#t~nondet4, eval_~tmp_ndt_2~0, eval_#t~nondet5, eval_~tmp_ndt_3~0, eval_#t~nondet6, eval_~tmp_ndt_4~0, eval_#t~nondet7, eval_~tmp_ndt_5~0, eval_#t~nondet8, eval_~tmp_ndt_6~0, eval_#t~nondet9, eval_~tmp_ndt_7~0, eval_~tmp~0;havoc eval_~tmp~0; 1681376#L661 [2018-11-23 01:27:14,388 INFO L796 eck$LassoCheckResult]: Loop: 1681376#L661 assume !false; 1724550#L568 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~7;havoc exists_runnable_thread_~__retres1~7; 1724548#L520 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7 := 1; 1724546#L557 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~7; 1724544#L558 eval_#t~ret2 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret2;havoc eval_#t~ret2; 1724542#L572 assume 0 != eval_~tmp~0; 1724540#L572-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0;eval_~tmp_ndt_1~0 := eval_#t~nondet3;havoc eval_#t~nondet3; 1724537#L580 assume !(0 != eval_~tmp_ndt_1~0); 1724534#L577 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0;eval_~tmp_ndt_2~0 := eval_#t~nondet4;havoc eval_#t~nondet4; 1724532#L594 assume !(0 != eval_~tmp_ndt_2~0); 1724530#L591 assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0;eval_~tmp_ndt_3~0 := eval_#t~nondet5;havoc eval_#t~nondet5; 1724527#L608 assume !(0 != eval_~tmp_ndt_3~0); 1724525#L605 assume !(0 == ~t3_st~0); 1724519#L619 assume !(0 == ~t4_st~0); 1724193#L633 assume !(0 == ~t5_st~0); 1724191#L647 assume !(0 == ~t6_st~0); 1681376#L661 [2018-11-23 01:27:14,389 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 01:27:14,389 INFO L82 PathProgramCache]: Analyzing trace with hash -617015546, now seen corresponding path program 2 times [2018-11-23 01:27:14,389 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 01:27:14,389 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 01:27:14,389 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 01:27:14,390 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 01:27:14,390 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 01:27:14,396 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-23 01:27:14,399 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-23 01:27:14,416 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 01:27:14,416 INFO L82 PathProgramCache]: Analyzing trace with hash 567891693, now seen corresponding path program 1 times [2018-11-23 01:27:14,416 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 01:27:14,417 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 01:27:14,417 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 01:27:14,417 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-23 01:27:14,417 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 01:27:14,418 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-23 01:27:14,419 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-23 01:27:14,421 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 01:27:14,421 INFO L82 PathProgramCache]: Analyzing trace with hash 1096139762, now seen corresponding path program 1 times [2018-11-23 01:27:14,421 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 01:27:14,421 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 01:27:14,422 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 01:27:14,422 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 01:27:14,422 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 01:27:14,425 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 01:27:14,453 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 01:27:14,453 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 01:27:14,453 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-23 01:27:14,516 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-23 01:27:14,516 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-23 01:27:14,516 INFO L87 Difference]: Start difference. First operand 130676 states and 166502 transitions. cyclomatic complexity: 35922 Second operand 3 states. [2018-11-23 01:27:14,944 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 01:27:14,944 INFO L93 Difference]: Finished difference Result 235148 states and 298518 transitions. [2018-11-23 01:27:14,945 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-23 01:27:14,945 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 235148 states and 298518 transitions. [2018-11-23 01:27:15,475 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 78644 [2018-11-23 01:27:15,833 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 235148 states to 235148 states and 298518 transitions. [2018-11-23 01:27:15,833 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 79763 [2018-11-23 01:27:15,870 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 79763 [2018-11-23 01:27:15,870 INFO L73 IsDeterministic]: Start isDeterministic. Operand 235148 states and 298518 transitions. [2018-11-23 01:27:15,870 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2018-11-23 01:27:15,870 INFO L705 BuchiCegarLoop]: Abstraction has 235148 states and 298518 transitions. [2018-11-23 01:27:15,968 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 235148 states and 298518 transitions. [2018-11-23 01:27:16,980 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 235148 to 235148. [2018-11-23 01:27:16,980 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 235148 states. [2018-11-23 01:27:17,877 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 235148 states to 235148 states and 298518 transitions. [2018-11-23 01:27:17,877 INFO L728 BuchiCegarLoop]: Abstraction has 235148 states and 298518 transitions. [2018-11-23 01:27:17,877 INFO L608 BuchiCegarLoop]: Abstraction has 235148 states and 298518 transitions. [2018-11-23 01:27:17,877 INFO L442 BuchiCegarLoop]: ======== Iteration 33============ [2018-11-23 01:27:17,877 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 235148 states and 298518 transitions. [2018-11-23 01:27:18,208 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 78644 [2018-11-23 01:27:18,208 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-23 01:27:18,208 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-23 01:27:18,209 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 01:27:18,209 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 01:27:18,209 INFO L794 eck$LassoCheckResult]: Stem: 1992341#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0; 1992094#L-1 havoc main_#res;havoc main_~__retres1~8;havoc main_~__retres1~8;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 1991583#L1018 havoc start_simulation_#t~ret18, start_simulation_#t~ret19, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 1991584#L470 assume 1 == ~m_i~0;~m_st~0 := 0; 1991265#L477-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1991266#L482-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1991992#L487-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 1991993#L492-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 1991638#L497-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 1991639#L502-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 1991831#L507-1 assume !(0 == ~M_E~0); 1991290#L686-1 assume !(0 == ~T1_E~0); 1991291#L691-1 assume !(0 == ~T2_E~0); 1992018#L696-1 assume !(0 == ~T3_E~0); 1992019#L701-1 assume !(0 == ~T4_E~0); 1991650#L706-1 assume !(0 == ~T5_E~0); 1991651#L711-1 assume !(0 == ~T6_E~0); 1992274#L716-1 assume !(0 == ~E_M~0); 1991552#L721-1 assume !(0 == ~E_1~0); 1991553#L726-1 assume !(0 == ~E_2~0); 1991123#L731-1 assume !(0 == ~E_3~0); 1991124#L736-1 assume !(0 == ~E_4~0); 1991273#L741-1 assume !(0 == ~E_5~0); 1991274#L746-1 assume !(0 == ~E_6~0); 1992006#L751-1 havoc activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 1991474#L336 assume !(1 == ~m_pc~0); 1991352#L336-2 is_master_triggered_~__retres1~0 := 0; 1991353#L347 is_master_triggered_#res := is_master_triggered_~__retres1~0; 1992731#L348 activate_threads_#t~ret10 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 1991314#L851 assume !(0 != activate_threads_~tmp~1); 1991315#L851-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 1991318#L355 assume !(1 == ~t1_pc~0); 1991921#L355-2 is_transmit1_triggered_~__retres1~1 := 0; 1991915#L366 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 1991271#L367 activate_threads_#t~ret11 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 1991272#L859 assume !(0 != activate_threads_~tmp___0~0); 1992258#L859-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 1992259#L374 assume !(1 == ~t2_pc~0); 1992328#L374-2 is_transmit2_triggered_~__retres1~2 := 0; 1992329#L385 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 1991773#L386 activate_threads_#t~ret12 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 1991774#L867 assume !(0 != activate_threads_~tmp___1~0); 1992650#L867-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 1992654#L393 assume !(1 == ~t3_pc~0); 1992616#L393-2 is_transmit3_triggered_~__retres1~3 := 0; 1992688#L404 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 1992612#L405 activate_threads_#t~ret13 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 1991565#L875 assume !(0 != activate_threads_~tmp___2~0); 1991531#L875-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 1991532#L412 assume !(1 == ~t4_pc~0); 1991607#L412-2 is_transmit4_triggered_~__retres1~4 := 0; 1991606#L423 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 1991438#L424 activate_threads_#t~ret14 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 1991439#L883 assume !(0 != activate_threads_~tmp___3~0); 1992044#L883-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 1991642#L431 assume !(1 == ~t5_pc~0); 1991617#L431-2 is_transmit5_triggered_~__retres1~5 := 0; 1991618#L442 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 1991998#L443 activate_threads_#t~ret15 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 1991999#L891 assume !(0 != activate_threads_~tmp___4~0); 1992450#L891-2 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 1992133#L450 assume !(1 == ~t6_pc~0); 1992134#L450-2 is_transmit6_triggered_~__retres1~6 := 0; 1992131#L461 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 1992132#L462 activate_threads_#t~ret16 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 1992386#L899 assume !(0 != activate_threads_~tmp___5~0); 1992459#L899-2 assume !(1 == ~M_E~0); 1991117#L764-1 assume !(1 == ~T1_E~0); 1991118#L769-1 assume !(1 == ~T2_E~0); 1991322#L774-1 assume !(1 == ~T3_E~0); 1991323#L779-1 assume !(1 == ~T4_E~0); 1992047#L784-1 assume !(1 == ~T5_E~0); 1992048#L789-1 assume !(1 == ~T6_E~0); 1991644#L794-1 assume !(1 == ~E_M~0); 1991645#L799-1 assume !(1 == ~E_1~0); 1992260#L804-1 assume !(1 == ~E_2~0); 1991533#L809-1 assume !(1 == ~E_3~0); 1991534#L814-1 assume !(1 == ~E_4~0); 1991115#L819-1 assume !(1 == ~E_5~0); 1991116#L824-1 assume !(1 == ~E_6~0); 1992150#L1055-1 assume !false; 2007973#L1056 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret2, eval_#t~nondet3, eval_~tmp_ndt_1~0, eval_#t~nondet4, eval_~tmp_ndt_2~0, eval_#t~nondet5, eval_~tmp_ndt_3~0, eval_#t~nondet6, eval_~tmp_ndt_4~0, eval_#t~nondet7, eval_~tmp_ndt_5~0, eval_#t~nondet8, eval_~tmp_ndt_6~0, eval_#t~nondet9, eval_~tmp_ndt_7~0, eval_~tmp~0;havoc eval_~tmp~0; 2089666#L661 [2018-11-23 01:27:18,209 INFO L796 eck$LassoCheckResult]: Loop: 2089666#L661 assume !false; 2089660#L568 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~7;havoc exists_runnable_thread_~__retres1~7; 2089653#L520 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7 := 1; 2089652#L557 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~7; 2089651#L558 eval_#t~ret2 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret2;havoc eval_#t~ret2; 2089649#L572 assume 0 != eval_~tmp~0; 2089647#L572-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0;eval_~tmp_ndt_1~0 := eval_#t~nondet3;havoc eval_#t~nondet3; 2089644#L580 assume !(0 != eval_~tmp_ndt_1~0); 2089642#L577 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0;eval_~tmp_ndt_2~0 := eval_#t~nondet4;havoc eval_#t~nondet4; 2089639#L594 assume !(0 != eval_~tmp_ndt_2~0); 2089637#L591 assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0;eval_~tmp_ndt_3~0 := eval_#t~nondet5;havoc eval_#t~nondet5; 2089633#L608 assume !(0 != eval_~tmp_ndt_3~0); 2089631#L605 assume 0 == ~t3_st~0;havoc eval_~tmp_ndt_4~0;eval_~tmp_ndt_4~0 := eval_#t~nondet6;havoc eval_#t~nondet6; 2089606#L622 assume !(0 != eval_~tmp_ndt_4~0); 2089628#L619 assume !(0 == ~t4_st~0); 2089684#L633 assume !(0 == ~t5_st~0); 2089676#L647 assume !(0 == ~t6_st~0); 2089666#L661 [2018-11-23 01:27:18,209 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 01:27:18,210 INFO L82 PathProgramCache]: Analyzing trace with hash -617015546, now seen corresponding path program 3 times [2018-11-23 01:27:18,210 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 01:27:18,210 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 01:27:18,210 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 01:27:18,210 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 01:27:18,210 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 01:27:18,214 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-23 01:27:18,218 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-23 01:27:18,229 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 01:27:18,229 INFO L82 PathProgramCache]: Analyzing trace with hash 235610502, now seen corresponding path program 1 times [2018-11-23 01:27:18,229 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 01:27:18,229 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 01:27:18,229 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 01:27:18,230 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-23 01:27:18,230 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 01:27:18,231 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-23 01:27:18,232 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-23 01:27:18,234 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 01:27:18,234 INFO L82 PathProgramCache]: Analyzing trace with hash -568568543, now seen corresponding path program 1 times [2018-11-23 01:27:18,234 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 01:27:18,234 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 01:27:18,235 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 01:27:18,235 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 01:27:18,235 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 01:27:18,238 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 01:27:18,273 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 01:27:18,273 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 01:27:18,273 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-23 01:27:18,366 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-23 01:27:18,366 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-23 01:27:18,366 INFO L87 Difference]: Start difference. First operand 235148 states and 298518 transitions. cyclomatic complexity: 63466 Second operand 3 states. [2018-11-23 01:27:18,983 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 01:27:18,983 INFO L93 Difference]: Finished difference Result 333152 states and 422278 transitions. [2018-11-23 01:27:18,984 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-23 01:27:18,984 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 333152 states and 422278 transitions. [2018-11-23 01:27:19,716 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 111698 [2018-11-23 01:27:20,236 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 333152 states to 333152 states and 422278 transitions. [2018-11-23 01:27:20,236 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 113151 [2018-11-23 01:27:20,287 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 113151 [2018-11-23 01:27:20,287 INFO L73 IsDeterministic]: Start isDeterministic. Operand 333152 states and 422278 transitions. [2018-11-23 01:27:20,287 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2018-11-23 01:27:20,287 INFO L705 BuchiCegarLoop]: Abstraction has 333152 states and 422278 transitions. [2018-11-23 01:27:20,425 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 333152 states and 422278 transitions. [2018-11-23 01:27:22,529 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 333152 to 324728. [2018-11-23 01:27:22,529 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 324728 states. [2018-11-23 01:27:22,883 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 324728 states to 324728 states and 412342 transitions. [2018-11-23 01:27:22,883 INFO L728 BuchiCegarLoop]: Abstraction has 324728 states and 412342 transitions. [2018-11-23 01:27:22,883 INFO L608 BuchiCegarLoop]: Abstraction has 324728 states and 412342 transitions. [2018-11-23 01:27:22,883 INFO L442 BuchiCegarLoop]: ======== Iteration 34============ [2018-11-23 01:27:22,883 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 324728 states and 412342 transitions. [2018-11-23 01:27:23,378 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 108890 [2018-11-23 01:27:23,378 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-23 01:27:23,378 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-23 01:27:23,378 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 01:27:23,378 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 01:27:23,379 INFO L794 eck$LassoCheckResult]: Stem: 2560682#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0; 2560437#L-1 havoc main_#res;havoc main_~__retres1~8;havoc main_~__retres1~8;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 2559898#L1018 havoc start_simulation_#t~ret18, start_simulation_#t~ret19, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 2559899#L470 assume 1 == ~m_i~0;~m_st~0 := 0; 2559574#L477-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 2559575#L482-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 2560329#L487-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 2560330#L492-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 2559971#L497-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 2559972#L502-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 2560157#L507-1 assume !(0 == ~M_E~0); 2559600#L686-1 assume !(0 == ~T1_E~0); 2559601#L691-1 assume !(0 == ~T2_E~0); 2560356#L696-1 assume !(0 == ~T3_E~0); 2560357#L701-1 assume !(0 == ~T4_E~0); 2559983#L706-1 assume !(0 == ~T5_E~0); 2559984#L711-1 assume !(0 == ~T6_E~0); 2560610#L716-1 assume !(0 == ~E_M~0); 2559870#L721-1 assume !(0 == ~E_1~0); 2559871#L726-1 assume !(0 == ~E_2~0); 2559431#L731-1 assume !(0 == ~E_3~0); 2559432#L736-1 assume !(0 == ~E_4~0); 2559583#L741-1 assume !(0 == ~E_5~0); 2559584#L746-1 assume !(0 == ~E_6~0); 2560344#L751-1 havoc activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 2559789#L336 assume !(1 == ~m_pc~0); 2559666#L336-2 is_master_triggered_~__retres1~0 := 0; 2559667#L347 is_master_triggered_#res := is_master_triggered_~__retres1~0; 2561086#L348 activate_threads_#t~ret10 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 2559627#L851 assume !(0 != activate_threads_~tmp~1); 2559628#L851-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 2559631#L355 assume !(1 == ~t1_pc~0); 2560252#L355-2 is_transmit1_triggered_~__retres1~1 := 0; 2560245#L366 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 2559581#L367 activate_threads_#t~ret11 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 2559582#L859 assume !(0 != activate_threads_~tmp___0~0); 2560593#L859-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 2560594#L374 assume !(1 == ~t2_pc~0); 2560670#L374-2 is_transmit2_triggered_~__retres1~2 := 0; 2560671#L385 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 2560104#L386 activate_threads_#t~ret12 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 2560105#L867 assume !(0 != activate_threads_~tmp___1~0); 2560995#L867-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 2560999#L393 assume !(1 == ~t3_pc~0); 2560969#L393-2 is_transmit3_triggered_~__retres1~3 := 0; 2561031#L404 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 2560965#L405 activate_threads_#t~ret13 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 2559884#L875 assume !(0 != activate_threads_~tmp___2~0); 2559849#L875-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 2559850#L412 assume !(1 == ~t4_pc~0); 2559937#L412-2 is_transmit4_triggered_~__retres1~4 := 0; 2559936#L423 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 2559753#L424 activate_threads_#t~ret14 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 2559754#L883 assume !(0 != activate_threads_~tmp___3~0); 2560381#L883-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 2559975#L431 assume !(1 == ~t5_pc~0); 2559950#L431-2 is_transmit5_triggered_~__retres1~5 := 0; 2559951#L442 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 2560335#L443 activate_threads_#t~ret15 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 2560336#L891 assume !(0 != activate_threads_~tmp___4~0); 2560800#L891-2 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 2560477#L450 assume !(1 == ~t6_pc~0); 2560478#L450-2 is_transmit6_triggered_~__retres1~6 := 0; 2560475#L461 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 2560476#L462 activate_threads_#t~ret16 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 2560726#L899 assume !(0 != activate_threads_~tmp___5~0); 2560812#L899-2 assume !(1 == ~M_E~0); 2559425#L764-1 assume !(1 == ~T1_E~0); 2559426#L769-1 assume !(1 == ~T2_E~0); 2559635#L774-1 assume !(1 == ~T3_E~0); 2559636#L779-1 assume !(1 == ~T4_E~0); 2560388#L784-1 assume !(1 == ~T5_E~0); 2560389#L789-1 assume !(1 == ~T6_E~0); 2559977#L794-1 assume !(1 == ~E_M~0); 2559978#L799-1 assume !(1 == ~E_1~0); 2560595#L804-1 assume !(1 == ~E_2~0); 2559851#L809-1 assume !(1 == ~E_3~0); 2559852#L814-1 assume !(1 == ~E_4~0); 2559423#L819-1 assume !(1 == ~E_5~0); 2559424#L824-1 assume !(1 == ~E_6~0); 2560493#L1055-1 assume !false; 2577335#L1056 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret2, eval_#t~nondet3, eval_~tmp_ndt_1~0, eval_#t~nondet4, eval_~tmp_ndt_2~0, eval_#t~nondet5, eval_~tmp_ndt_3~0, eval_#t~nondet6, eval_~tmp_ndt_4~0, eval_#t~nondet7, eval_~tmp_ndt_5~0, eval_#t~nondet8, eval_~tmp_ndt_6~0, eval_#t~nondet9, eval_~tmp_ndt_7~0, eval_~tmp~0;havoc eval_~tmp~0; 2703720#L661 [2018-11-23 01:27:23,379 INFO L796 eck$LassoCheckResult]: Loop: 2703720#L661 assume !false; 2781215#L568 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~7;havoc exists_runnable_thread_~__retres1~7; 2781213#L520 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7 := 1; 2781211#L557 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~7; 2781209#L558 eval_#t~ret2 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret2;havoc eval_#t~ret2; 2781207#L572 assume 0 != eval_~tmp~0; 2781205#L572-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0;eval_~tmp_ndt_1~0 := eval_#t~nondet3;havoc eval_#t~nondet3; 2781202#L580 assume !(0 != eval_~tmp_ndt_1~0); 2781198#L577 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0;eval_~tmp_ndt_2~0 := eval_#t~nondet4;havoc eval_#t~nondet4; 2781195#L594 assume !(0 != eval_~tmp_ndt_2~0); 2781196#L591 assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0;eval_~tmp_ndt_3~0 := eval_#t~nondet5;havoc eval_#t~nondet5; 2782934#L608 assume !(0 != eval_~tmp_ndt_3~0); 2781251#L605 assume 0 == ~t3_st~0;havoc eval_~tmp_ndt_4~0;eval_~tmp_ndt_4~0 := eval_#t~nondet6;havoc eval_#t~nondet6; 2781248#L622 assume !(0 != eval_~tmp_ndt_4~0); 2781245#L619 assume 0 == ~t4_st~0;havoc eval_~tmp_ndt_5~0;eval_~tmp_ndt_5~0 := eval_#t~nondet7;havoc eval_#t~nondet7; 2781242#L636 assume !(0 != eval_~tmp_ndt_5~0); 2781223#L633 assume !(0 == ~t5_st~0); 2781221#L647 assume !(0 == ~t6_st~0); 2703720#L661 [2018-11-23 01:27:23,379 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 01:27:23,379 INFO L82 PathProgramCache]: Analyzing trace with hash -617015546, now seen corresponding path program 4 times [2018-11-23 01:27:23,379 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 01:27:23,379 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 01:27:23,380 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 01:27:23,380 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 01:27:23,380 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 01:27:23,384 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-23 01:27:23,387 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-23 01:27:23,398 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 01:27:23,398 INFO L82 PathProgramCache]: Analyzing trace with hash -1292109015, now seen corresponding path program 1 times [2018-11-23 01:27:23,398 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 01:27:23,398 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 01:27:23,399 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 01:27:23,399 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-23 01:27:23,399 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 01:27:23,400 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-23 01:27:23,402 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-23 01:27:23,404 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 01:27:23,404 INFO L82 PathProgramCache]: Analyzing trace with hash -451855634, now seen corresponding path program 1 times [2018-11-23 01:27:23,404 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 01:27:23,404 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 01:27:23,405 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 01:27:23,405 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 01:27:23,405 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 01:27:23,408 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 01:27:23,445 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 01:27:23,445 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 01:27:23,445 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-23 01:27:23,528 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-23 01:27:23,528 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-23 01:27:23,528 INFO L87 Difference]: Start difference. First operand 324728 states and 412342 transitions. cyclomatic complexity: 87710 Second operand 3 states. [2018-11-23 01:27:24,581 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 01:27:24,581 INFO L93 Difference]: Finished difference Result 576800 states and 730886 transitions. [2018-11-23 01:27:24,581 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-23 01:27:24,582 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 576800 states and 730886 transitions. [2018-11-23 01:27:26,887 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 193596 [2018-11-23 01:27:27,677 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 576800 states to 576800 states and 730886 transitions. [2018-11-23 01:27:27,678 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 196409 [2018-11-23 01:27:27,736 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 196409 [2018-11-23 01:27:27,736 INFO L73 IsDeterministic]: Start isDeterministic. Operand 576800 states and 730886 transitions. [2018-11-23 01:27:27,741 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2018-11-23 01:27:27,741 INFO L705 BuchiCegarLoop]: Abstraction has 576800 states and 730886 transitions. [2018-11-23 01:27:27,962 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 576800 states and 730886 transitions. [2018-11-23 01:27:36,563 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 576800 to 562544. [2018-11-23 01:27:36,563 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 562544 states. [2018-11-23 01:27:37,228 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 562544 states to 562544 states and 714686 transitions. [2018-11-23 01:27:37,228 INFO L728 BuchiCegarLoop]: Abstraction has 562544 states and 714686 transitions. [2018-11-23 01:27:37,228 INFO L608 BuchiCegarLoop]: Abstraction has 562544 states and 714686 transitions. [2018-11-23 01:27:37,229 INFO L442 BuchiCegarLoop]: ======== Iteration 35============ [2018-11-23 01:27:37,229 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 562544 states and 714686 transitions. [2018-11-23 01:27:38,658 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 188844 [2018-11-23 01:27:38,658 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-23 01:27:38,658 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-23 01:27:38,659 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 01:27:38,659 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 01:27:38,659 INFO L794 eck$LassoCheckResult]: Stem: 3462224#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0; 3461967#L-1 havoc main_#res;havoc main_~__retres1~8;havoc main_~__retres1~8;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 3461437#L1018 havoc start_simulation_#t~ret18, start_simulation_#t~ret19, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 3461438#L470 assume 1 == ~m_i~0;~m_st~0 := 0; 3461111#L477-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 3461112#L482-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 3461853#L487-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 3461854#L492-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 3461501#L497-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 3461502#L502-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 3461690#L507-1 assume !(0 == ~M_E~0); 3461139#L686-1 assume !(0 == ~T1_E~0); 3461140#L691-1 assume !(0 == ~T2_E~0); 3461877#L696-1 assume !(0 == ~T3_E~0); 3461878#L701-1 assume !(0 == ~T4_E~0); 3461513#L706-1 assume !(0 == ~T5_E~0); 3461514#L711-1 assume !(0 == ~T6_E~0); 3462144#L716-1 assume !(0 == ~E_M~0); 3461403#L721-1 assume !(0 == ~E_1~0); 3461404#L726-1 assume !(0 == ~E_2~0); 3460967#L731-1 assume !(0 == ~E_3~0); 3460968#L736-1 assume !(0 == ~E_4~0); 3461119#L741-1 assume !(0 == ~E_5~0); 3461120#L746-1 assume !(0 == ~E_6~0); 3461866#L751-1 havoc activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 3461323#L336 assume !(1 == ~m_pc~0); 3461199#L336-2 is_master_triggered_~__retres1~0 := 0; 3461200#L347 is_master_triggered_#res := is_master_triggered_~__retres1~0; 3462610#L348 activate_threads_#t~ret10 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 3461159#L851 assume !(0 != activate_threads_~tmp~1); 3461160#L851-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 3461164#L355 assume !(1 == ~t1_pc~0); 3461778#L355-2 is_transmit1_triggered_~__retres1~1 := 0; 3461777#L366 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 3461117#L367 activate_threads_#t~ret11 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 3461118#L859 assume !(0 != activate_threads_~tmp___0~0); 3462129#L859-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 3462130#L374 assume !(1 == ~t2_pc~0); 3462210#L374-2 is_transmit2_triggered_~__retres1~2 := 0; 3462211#L385 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 3461634#L386 activate_threads_#t~ret12 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 3461635#L867 assume !(0 != activate_threads_~tmp___1~0); 3462531#L867-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 3462535#L393 assume !(1 == ~t3_pc~0); 3462501#L393-2 is_transmit3_triggered_~__retres1~3 := 0; 3462561#L404 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 3462499#L405 activate_threads_#t~ret13 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 3461420#L875 assume !(0 != activate_threads_~tmp___2~0); 3461383#L875-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 3461384#L412 assume !(1 == ~t4_pc~0); 3461469#L412-2 is_transmit4_triggered_~__retres1~4 := 0; 3461468#L423 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 3461287#L424 activate_threads_#t~ret14 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 3461288#L883 assume !(0 != activate_threads_~tmp___3~0); 3461909#L883-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 3461505#L431 assume !(1 == ~t5_pc~0); 3461480#L431-2 is_transmit5_triggered_~__retres1~5 := 0; 3461481#L442 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 3461855#L443 activate_threads_#t~ret15 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 3461856#L891 assume !(0 != activate_threads_~tmp___4~0); 3462335#L891-2 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 3462006#L450 assume !(1 == ~t6_pc~0); 3462007#L450-2 is_transmit6_triggered_~__retres1~6 := 0; 3462004#L461 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 3462005#L462 activate_threads_#t~ret16 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 3462268#L899 assume !(0 != activate_threads_~tmp___5~0); 3462354#L899-2 assume !(1 == ~M_E~0); 3460961#L764-1 assume !(1 == ~T1_E~0); 3460962#L769-1 assume !(1 == ~T2_E~0); 3461168#L774-1 assume !(1 == ~T3_E~0); 3461169#L779-1 assume !(1 == ~T4_E~0); 3461915#L784-1 assume !(1 == ~T5_E~0); 3461916#L789-1 assume !(1 == ~T6_E~0); 3461507#L794-1 assume !(1 == ~E_M~0); 3461508#L799-1 assume !(1 == ~E_1~0); 3462131#L804-1 assume !(1 == ~E_2~0); 3461392#L809-1 assume !(1 == ~E_3~0); 3461393#L814-1 assume !(1 == ~E_4~0); 3460959#L819-1 assume !(1 == ~E_5~0); 3460960#L824-1 assume !(1 == ~E_6~0); 3462021#L1055-1 assume !false; 3476545#L1056 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret2, eval_#t~nondet3, eval_~tmp_ndt_1~0, eval_#t~nondet4, eval_~tmp_ndt_2~0, eval_#t~nondet5, eval_~tmp_ndt_3~0, eval_#t~nondet6, eval_~tmp_ndt_4~0, eval_#t~nondet7, eval_~tmp_ndt_5~0, eval_#t~nondet8, eval_~tmp_ndt_6~0, eval_#t~nondet9, eval_~tmp_ndt_7~0, eval_~tmp~0;havoc eval_~tmp~0; 3676641#L661 [2018-11-23 01:27:38,659 INFO L796 eck$LassoCheckResult]: Loop: 3676641#L661 assume !false; 3882706#L568 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~7;havoc exists_runnable_thread_~__retres1~7; 3882704#L520 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7 := 1; 3882703#L557 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~7; 3882702#L558 eval_#t~ret2 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret2;havoc eval_#t~ret2; 3882700#L572 assume 0 != eval_~tmp~0; 3882699#L572-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0;eval_~tmp_ndt_1~0 := eval_#t~nondet3;havoc eval_#t~nondet3; 3882697#L580 assume !(0 != eval_~tmp_ndt_1~0); 3882696#L577 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0;eval_~tmp_ndt_2~0 := eval_#t~nondet4;havoc eval_#t~nondet4; 3882695#L594 assume !(0 != eval_~tmp_ndt_2~0); 3882694#L591 assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0;eval_~tmp_ndt_3~0 := eval_#t~nondet5;havoc eval_#t~nondet5; 3882693#L608 assume !(0 != eval_~tmp_ndt_3~0); 3882692#L605 assume 0 == ~t3_st~0;havoc eval_~tmp_ndt_4~0;eval_~tmp_ndt_4~0 := eval_#t~nondet6;havoc eval_#t~nondet6; 3882675#L622 assume !(0 != eval_~tmp_ndt_4~0); 3882691#L619 assume 0 == ~t4_st~0;havoc eval_~tmp_ndt_5~0;eval_~tmp_ndt_5~0 := eval_#t~nondet7;havoc eval_#t~nondet7; 3882712#L636 assume !(0 != eval_~tmp_ndt_5~0); 3882711#L633 assume 0 == ~t5_st~0;havoc eval_~tmp_ndt_6~0;eval_~tmp_ndt_6~0 := eval_#t~nondet8;havoc eval_#t~nondet8; 3874030#L650 assume !(0 != eval_~tmp_ndt_6~0); 3882708#L647 assume !(0 == ~t6_st~0); 3676641#L661 [2018-11-23 01:27:38,660 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 01:27:38,660 INFO L82 PathProgramCache]: Analyzing trace with hash -617015546, now seen corresponding path program 5 times [2018-11-23 01:27:38,660 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 01:27:38,660 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 01:27:38,660 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 01:27:38,661 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 01:27:38,661 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 01:27:38,664 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-23 01:27:38,667 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-23 01:27:38,676 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 01:27:38,676 INFO L82 PathProgramCache]: Analyzing trace with hash -1400868534, now seen corresponding path program 1 times [2018-11-23 01:27:38,677 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 01:27:38,677 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 01:27:38,677 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 01:27:38,677 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-23 01:27:38,677 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 01:27:38,679 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-23 01:27:38,680 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-23 01:27:38,682 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 01:27:38,682 INFO L82 PathProgramCache]: Analyzing trace with hash -1122817499, now seen corresponding path program 1 times [2018-11-23 01:27:38,682 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 01:27:38,682 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 01:27:38,682 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 01:27:38,682 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 01:27:38,683 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 01:27:38,686 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 01:27:38,740 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 01:27:38,740 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 01:27:38,740 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2018-11-23 01:27:38,828 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-23 01:27:38,828 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-23 01:27:38,829 INFO L87 Difference]: Start difference. First operand 562544 states and 714686 transitions. cyclomatic complexity: 152238 Second operand 3 states. [2018-11-23 01:27:40,250 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 01:27:40,250 INFO L93 Difference]: Finished difference Result 752852 states and 953722 transitions. [2018-11-23 01:27:40,250 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-23 01:27:40,250 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 752852 states and 953722 transitions. [2018-11-23 01:27:42,973 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 253638 [2018-11-23 01:27:44,171 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 752852 states to 752852 states and 953722 transitions. [2018-11-23 01:27:44,171 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 257266 [2018-11-23 01:27:44,264 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 257266 [2018-11-23 01:27:44,264 INFO L73 IsDeterministic]: Start isDeterministic. Operand 752852 states and 953722 transitions. [2018-11-23 01:27:44,337 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2018-11-23 01:27:44,337 INFO L705 BuchiCegarLoop]: Abstraction has 752852 states and 953722 transitions. [2018-11-23 01:27:44,644 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 752852 states and 953722 transitions. [2018-11-23 01:27:55,908 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 752852 to 752852. [2018-11-23 01:27:55,908 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 752852 states. [2018-11-23 01:27:57,579 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 752852 states to 752852 states and 953722 transitions. [2018-11-23 01:27:57,579 INFO L728 BuchiCegarLoop]: Abstraction has 752852 states and 953722 transitions. [2018-11-23 01:27:57,579 INFO L608 BuchiCegarLoop]: Abstraction has 752852 states and 953722 transitions. [2018-11-23 01:27:57,579 INFO L442 BuchiCegarLoop]: ======== Iteration 36============ [2018-11-23 01:27:57,579 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 752852 states and 953722 transitions. [2018-11-23 01:27:58,612 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 253638 [2018-11-23 01:27:58,612 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-23 01:27:58,612 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-23 01:27:58,613 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 01:27:58,613 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 01:27:58,613 INFO L794 eck$LassoCheckResult]: Stem: 4777617#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0; 4777369#L-1 havoc main_#res;havoc main_~__retres1~8;havoc main_~__retres1~8;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 4776838#L1018 havoc start_simulation_#t~ret18, start_simulation_#t~ret19, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 4776839#L470 assume 1 == ~m_i~0;~m_st~0 := 0; 4776516#L477-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 4776517#L482-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 4777263#L487-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 4777264#L492-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 4776907#L497-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 4776908#L502-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 4777106#L507-1 assume !(0 == ~M_E~0); 4776546#L686-1 assume !(0 == ~T1_E~0); 4776547#L691-1 assume !(0 == ~T2_E~0); 4777289#L696-1 assume !(0 == ~T3_E~0); 4777290#L701-1 assume !(0 == ~T4_E~0); 4776919#L706-1 assume !(0 == ~T5_E~0); 4776920#L711-1 assume !(0 == ~T6_E~0); 4777546#L716-1 assume !(0 == ~E_M~0); 4776808#L721-1 assume !(0 == ~E_1~0); 4776809#L726-1 assume !(0 == ~E_2~0); 4776371#L731-1 assume !(0 == ~E_3~0); 4776372#L736-1 assume !(0 == ~E_4~0); 4776525#L741-1 assume !(0 == ~E_5~0); 4776526#L746-1 assume !(0 == ~E_6~0); 4777277#L751-1 havoc activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 4776726#L336 assume !(1 == ~m_pc~0); 4776602#L336-2 is_master_triggered_~__retres1~0 := 0; 4776603#L347 is_master_triggered_#res := is_master_triggered_~__retres1~0; 4778001#L348 activate_threads_#t~ret10 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 4776564#L851 assume !(0 != activate_threads_~tmp~1); 4776565#L851-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 4776569#L355 assume !(1 == ~t1_pc~0); 4777191#L355-2 is_transmit1_triggered_~__retres1~1 := 0; 4777190#L366 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 4776523#L367 activate_threads_#t~ret11 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 4776524#L859 assume !(0 != activate_threads_~tmp___0~0); 4777531#L859-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 4777532#L374 assume !(1 == ~t2_pc~0); 4777605#L374-2 is_transmit2_triggered_~__retres1~2 := 0; 4777606#L385 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 4777043#L386 activate_threads_#t~ret12 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 4777044#L867 assume !(0 != activate_threads_~tmp___1~0); 4777923#L867-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 4777926#L393 assume !(1 == ~t3_pc~0); 4777895#L393-2 is_transmit3_triggered_~__retres1~3 := 0; 4777956#L404 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 4777893#L405 activate_threads_#t~ret13 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 4776822#L875 assume !(0 != activate_threads_~tmp___2~0); 4776786#L875-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 4776787#L412 assume !(1 == ~t4_pc~0); 4776871#L412-2 is_transmit4_triggered_~__retres1~4 := 0; 4776870#L423 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 4776690#L424 activate_threads_#t~ret14 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 4776691#L883 assume !(0 != activate_threads_~tmp___3~0); 4777316#L883-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 4776911#L431 assume !(1 == ~t5_pc~0); 4776883#L431-2 is_transmit5_triggered_~__retres1~5 := 0; 4776884#L442 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 4777265#L443 activate_threads_#t~ret15 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 4777266#L891 assume !(0 != activate_threads_~tmp___4~0); 4777724#L891-2 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 4777408#L450 assume !(1 == ~t6_pc~0); 4777409#L450-2 is_transmit6_triggered_~__retres1~6 := 0; 4777406#L461 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 4777407#L462 activate_threads_#t~ret16 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 4777665#L899 assume !(0 != activate_threads_~tmp___5~0); 4777740#L899-2 assume !(1 == ~M_E~0); 4776365#L764-1 assume !(1 == ~T1_E~0); 4776366#L769-1 assume !(1 == ~T2_E~0); 4776572#L774-1 assume !(1 == ~T3_E~0); 4776573#L779-1 assume !(1 == ~T4_E~0); 4777321#L784-1 assume !(1 == ~T5_E~0); 4777322#L789-1 assume !(1 == ~T6_E~0); 4776913#L794-1 assume !(1 == ~E_M~0); 4776914#L799-1 assume !(1 == ~E_1~0); 4777533#L804-1 assume !(1 == ~E_2~0); 4776796#L809-1 assume !(1 == ~E_3~0); 4776797#L814-1 assume !(1 == ~E_4~0); 4776363#L819-1 assume !(1 == ~E_5~0); 4776364#L824-1 assume !(1 == ~E_6~0); 4777424#L1055-1 assume !false; 4813952#L1056 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret2, eval_#t~nondet3, eval_~tmp_ndt_1~0, eval_#t~nondet4, eval_~tmp_ndt_2~0, eval_#t~nondet5, eval_~tmp_ndt_3~0, eval_#t~nondet6, eval_~tmp_ndt_4~0, eval_#t~nondet7, eval_~tmp_ndt_5~0, eval_#t~nondet8, eval_~tmp_ndt_6~0, eval_#t~nondet9, eval_~tmp_ndt_7~0, eval_~tmp~0;havoc eval_~tmp~0; 4968570#L661 [2018-11-23 01:27:58,613 INFO L796 eck$LassoCheckResult]: Loop: 4968570#L661 assume !false; 5290015#L568 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~7;havoc exists_runnable_thread_~__retres1~7; 5290013#L520 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7 := 1; 5290010#L557 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~7; 5290008#L558 eval_#t~ret2 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret2;havoc eval_#t~ret2; 5290005#L572 assume 0 != eval_~tmp~0; 5290002#L572-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0;eval_~tmp_ndt_1~0 := eval_#t~nondet3;havoc eval_#t~nondet3; 5289999#L580 assume !(0 != eval_~tmp_ndt_1~0); 5289996#L577 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0;eval_~tmp_ndt_2~0 := eval_#t~nondet4;havoc eval_#t~nondet4; 5289994#L594 assume !(0 != eval_~tmp_ndt_2~0); 5289995#L591 assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0;eval_~tmp_ndt_3~0 := eval_#t~nondet5;havoc eval_#t~nondet5; 5290060#L608 assume !(0 != eval_~tmp_ndt_3~0); 5289150#L605 assume 0 == ~t3_st~0;havoc eval_~tmp_ndt_4~0;eval_~tmp_ndt_4~0 := eval_#t~nondet6;havoc eval_#t~nondet6; 5289147#L622 assume !(0 != eval_~tmp_ndt_4~0); 5289145#L619 assume 0 == ~t4_st~0;havoc eval_~tmp_ndt_5~0;eval_~tmp_ndt_5~0 := eval_#t~nondet7;havoc eval_#t~nondet7; 5289142#L636 assume !(0 != eval_~tmp_ndt_5~0); 5289140#L633 assume 0 == ~t5_st~0;havoc eval_~tmp_ndt_6~0;eval_~tmp_ndt_6~0 := eval_#t~nondet8;havoc eval_#t~nondet8; 5288993#L650 assume !(0 != eval_~tmp_ndt_6~0); 5289137#L647 assume 0 == ~t6_st~0;havoc eval_~tmp_ndt_7~0;eval_~tmp_ndt_7~0 := eval_#t~nondet9;havoc eval_#t~nondet9; 5290019#L664 assume !(0 != eval_~tmp_ndt_7~0); 4968570#L661 [2018-11-23 01:27:58,614 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 01:27:58,614 INFO L82 PathProgramCache]: Analyzing trace with hash -617015546, now seen corresponding path program 6 times [2018-11-23 01:27:58,614 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 01:27:58,614 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 01:27:58,614 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 01:27:58,614 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 01:27:58,615 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 01:27:58,618 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-23 01:27:58,621 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-23 01:27:58,631 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 01:27:58,631 INFO L82 PathProgramCache]: Analyzing trace with hash -477255835, now seen corresponding path program 1 times [2018-11-23 01:27:58,631 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 01:27:58,631 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 01:27:58,632 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 01:27:58,632 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-23 01:27:58,632 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 01:27:58,633 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-23 01:27:58,635 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-23 01:27:58,636 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 01:27:58,636 INFO L82 PathProgramCache]: Analyzing trace with hash -447608342, now seen corresponding path program 1 times [2018-11-23 01:27:58,637 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 01:27:58,637 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 01:27:58,637 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 01:27:58,637 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 01:27:58,637 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 01:27:58,641 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-23 01:27:58,645 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-23 01:27:59,142 WARN L180 SmtUtils]: Spent 378.00 ms on a formula simplification. DAG size of input: 229 DAG size of output: 152 ----- class de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder.RCFGBacktranslator [?] ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0; [?] havoc main_#res;havoc main_~__retres1~8;havoc main_~__retres1~8;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; [?] havoc start_simulation_#t~ret18, start_simulation_#t~ret19, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; [?] assume 1 == ~m_i~0;~m_st~0 := 0; [?] assume 1 == ~t1_i~0;~t1_st~0 := 0; [?] assume 1 == ~t2_i~0;~t2_st~0 := 0; [?] assume 1 == ~t3_i~0;~t3_st~0 := 0; [?] assume 1 == ~t4_i~0;~t4_st~0 := 0; [?] assume 1 == ~t5_i~0;~t5_st~0 := 0; [?] assume 1 == ~t6_i~0;~t6_st~0 := 0; [?] assume !(0 == ~M_E~0); [?] assume !(0 == ~T1_E~0); [?] assume !(0 == ~T2_E~0); [?] assume !(0 == ~T3_E~0); [?] assume !(0 == ~T4_E~0); [?] assume !(0 == ~T5_E~0); [?] assume !(0 == ~T6_E~0); [?] assume !(0 == ~E_M~0); [?] assume !(0 == ~E_1~0); [?] assume !(0 == ~E_2~0); [?] assume !(0 == ~E_3~0); [?] assume !(0 == ~E_4~0); [?] assume !(0 == ~E_5~0); [?] assume !(0 == ~E_6~0); [?] havoc activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; [?] assume !(1 == ~m_pc~0); [?] is_master_triggered_~__retres1~0 := 0; [?] is_master_triggered_#res := is_master_triggered_~__retres1~0; [?] activate_threads_#t~ret10 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; [?] assume !(0 != activate_threads_~tmp~1); [?] havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; [?] assume !(1 == ~t1_pc~0); [?] is_transmit1_triggered_~__retres1~1 := 0; [?] is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; [?] activate_threads_#t~ret11 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; [?] assume !(0 != activate_threads_~tmp___0~0); [?] havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; [?] assume !(1 == ~t2_pc~0); [?] is_transmit2_triggered_~__retres1~2 := 0; [?] is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; [?] activate_threads_#t~ret12 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; [?] assume !(0 != activate_threads_~tmp___1~0); [?] havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; [?] assume !(1 == ~t3_pc~0); [?] is_transmit3_triggered_~__retres1~3 := 0; [?] is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; [?] activate_threads_#t~ret13 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; [?] assume !(0 != activate_threads_~tmp___2~0); [?] havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; [?] assume !(1 == ~t4_pc~0); [?] is_transmit4_triggered_~__retres1~4 := 0; [?] is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; [?] activate_threads_#t~ret14 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; [?] assume !(0 != activate_threads_~tmp___3~0); [?] havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; [?] assume !(1 == ~t5_pc~0); [?] is_transmit5_triggered_~__retres1~5 := 0; [?] is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; [?] activate_threads_#t~ret15 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; [?] assume !(0 != activate_threads_~tmp___4~0); [?] havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; [?] assume !(1 == ~t6_pc~0); [?] is_transmit6_triggered_~__retres1~6 := 0; [?] is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; [?] activate_threads_#t~ret16 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; [?] assume !(0 != activate_threads_~tmp___5~0); [?] assume !(1 == ~M_E~0); [?] assume !(1 == ~T1_E~0); [?] assume !(1 == ~T2_E~0); [?] assume !(1 == ~T3_E~0); [?] assume !(1 == ~T4_E~0); [?] assume !(1 == ~T5_E~0); [?] assume !(1 == ~T6_E~0); [?] assume !(1 == ~E_M~0); [?] assume !(1 == ~E_1~0); [?] assume !(1 == ~E_2~0); [?] assume !(1 == ~E_3~0); [?] assume !(1 == ~E_4~0); [?] assume !(1 == ~E_5~0); [?] assume !(1 == ~E_6~0); [?] assume !false; [?] start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret2, eval_#t~nondet3, eval_~tmp_ndt_1~0, eval_#t~nondet4, eval_~tmp_ndt_2~0, eval_#t~nondet5, eval_~tmp_ndt_3~0, eval_#t~nondet6, eval_~tmp_ndt_4~0, eval_#t~nondet7, eval_~tmp_ndt_5~0, eval_#t~nondet8, eval_~tmp_ndt_6~0, eval_#t~nondet9, eval_~tmp_ndt_7~0, eval_~tmp~0;havoc eval_~tmp~0; [L14] ~m_pc~0 := 0; [L15] ~t1_pc~0 := 0; [L16] ~t2_pc~0 := 0; [L17] ~t3_pc~0 := 0; [L18] ~t4_pc~0 := 0; [L19] ~t5_pc~0 := 0; [L20] ~t6_pc~0 := 0; [L21] ~m_st~0 := 0; [L22] ~t1_st~0 := 0; [L23] ~t2_st~0 := 0; [L24] ~t3_st~0 := 0; [L25] ~t4_st~0 := 0; [L26] ~t5_st~0 := 0; [L27] ~t6_st~0 := 0; [L28] ~m_i~0 := 0; [L29] ~t1_i~0 := 0; [L30] ~t2_i~0 := 0; [L31] ~t3_i~0 := 0; [L32] ~t4_i~0 := 0; [L33] ~t5_i~0 := 0; [L34] ~t6_i~0 := 0; [L35] ~M_E~0 := 2; [L36] ~T1_E~0 := 2; [L37] ~T2_E~0 := 2; [L38] ~T3_E~0 := 2; [L39] ~T4_E~0 := 2; [L40] ~T5_E~0 := 2; [L41] ~T6_E~0 := 2; [L42] ~E_M~0 := 2; [L43] ~E_1~0 := 2; [L44] ~E_2~0 := 2; [L45] ~E_3~0 := 2; [L46] ~E_4~0 := 2; [L47] ~E_5~0 := 2; [L48] ~E_6~0 := 2; [L57] ~token~0 := 0; [L59] ~local~0 := 0; [?] havoc main_#res; [?] havoc main_~__retres1~8; [L1100] havoc main_~__retres1~8; [L1010] ~m_i~0 := 1; [L1011] ~t1_i~0 := 1; [L1012] ~t2_i~0 := 1; [L1013] ~t3_i~0 := 1; [L1014] ~t4_i~0 := 1; [L1015] ~t5_i~0 := 1; [L1016] ~t6_i~0 := 1; [L1105] havoc start_simulation_#t~ret18, start_simulation_#t~ret19, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1; [L1041] havoc start_simulation_~kernel_st~0; [L1042] havoc start_simulation_~tmp~3; [L1043] havoc start_simulation_~tmp___0~1; [L1047] start_simulation_~kernel_st~0 := 0; [L477-L481] assume 1 == ~m_i~0; [L478] ~m_st~0 := 0; [L482-L486] assume 1 == ~t1_i~0; [L483] ~t1_st~0 := 0; [L487-L491] assume 1 == ~t2_i~0; [L488] ~t2_st~0 := 0; [L492-L496] assume 1 == ~t3_i~0; [L493] ~t3_st~0 := 0; [L497-L501] assume 1 == ~t4_i~0; [L498] ~t4_st~0 := 0; [L502-L506] assume 1 == ~t5_i~0; [L503] ~t5_st~0 := 0; [L507-L511] assume 1 == ~t6_i~0; [L508] ~t6_st~0 := 0; [L686-L690] assume !(0 == ~M_E~0); [L691-L695] assume !(0 == ~T1_E~0); [L696-L700] assume !(0 == ~T2_E~0); [L701-L705] assume !(0 == ~T3_E~0); [L706-L710] assume !(0 == ~T4_E~0); [L711-L715] assume !(0 == ~T5_E~0); [L716-L720] assume !(0 == ~T6_E~0); [L721-L725] assume !(0 == ~E_M~0); [L726-L730] assume !(0 == ~E_1~0); [L731-L735] assume !(0 == ~E_2~0); [L736-L740] assume !(0 == ~E_3~0); [L741-L745] assume !(0 == ~E_4~0); [L746-L750] assume !(0 == ~E_5~0); [L751-L755] assume !(0 == ~E_6~0); [L1051] havoc activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0; [L839] havoc activate_threads_~tmp~1; [L840] havoc activate_threads_~tmp___0~0; [L841] havoc activate_threads_~tmp___1~0; [L842] havoc activate_threads_~tmp___2~0; [L843] havoc activate_threads_~tmp___3~0; [L844] havoc activate_threads_~tmp___4~0; [L845] havoc activate_threads_~tmp___5~0; [L849] havoc is_master_triggered_#res; [L849] havoc is_master_triggered_~__retres1~0; [L333] havoc is_master_triggered_~__retres1~0; [L336-L345] assume !(1 == ~m_pc~0); [L346] is_master_triggered_~__retres1~0 := 0; [L348] is_master_triggered_#res := is_master_triggered_~__retres1~0; [L849] activate_threads_#t~ret10 := is_master_triggered_#res; [L849] activate_threads_~tmp~1 := activate_threads_#t~ret10; [L849] havoc activate_threads_#t~ret10; [L851-L855] assume !(0 != activate_threads_~tmp~1); [L857] havoc is_transmit1_triggered_#res; [L857] havoc is_transmit1_triggered_~__retres1~1; [L352] havoc is_transmit1_triggered_~__retres1~1; [L355-L364] assume !(1 == ~t1_pc~0); [L365] is_transmit1_triggered_~__retres1~1 := 0; [L367] is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; [L857] activate_threads_#t~ret11 := is_transmit1_triggered_#res; [L857] activate_threads_~tmp___0~0 := activate_threads_#t~ret11; [L857] havoc activate_threads_#t~ret11; [L859-L863] assume !(0 != activate_threads_~tmp___0~0); [L865] havoc is_transmit2_triggered_#res; [L865] havoc is_transmit2_triggered_~__retres1~2; [L371] havoc is_transmit2_triggered_~__retres1~2; [L374-L383] assume !(1 == ~t2_pc~0); [L384] is_transmit2_triggered_~__retres1~2 := 0; [L386] is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; [L865] activate_threads_#t~ret12 := is_transmit2_triggered_#res; [L865] activate_threads_~tmp___1~0 := activate_threads_#t~ret12; [L865] havoc activate_threads_#t~ret12; [L867-L871] assume !(0 != activate_threads_~tmp___1~0); [L873] havoc is_transmit3_triggered_#res; [L873] havoc is_transmit3_triggered_~__retres1~3; [L390] havoc is_transmit3_triggered_~__retres1~3; [L393-L402] assume !(1 == ~t3_pc~0); [L403] is_transmit3_triggered_~__retres1~3 := 0; [L405] is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; [L873] activate_threads_#t~ret13 := is_transmit3_triggered_#res; [L873] activate_threads_~tmp___2~0 := activate_threads_#t~ret13; [L873] havoc activate_threads_#t~ret13; [L875-L879] assume !(0 != activate_threads_~tmp___2~0); [L881] havoc is_transmit4_triggered_#res; [L881] havoc is_transmit4_triggered_~__retres1~4; [L409] havoc is_transmit4_triggered_~__retres1~4; [L412-L421] assume !(1 == ~t4_pc~0); [L422] is_transmit4_triggered_~__retres1~4 := 0; [L424] is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; [L881] activate_threads_#t~ret14 := is_transmit4_triggered_#res; [L881] activate_threads_~tmp___3~0 := activate_threads_#t~ret14; [L881] havoc activate_threads_#t~ret14; [L883-L887] assume !(0 != activate_threads_~tmp___3~0); [L889] havoc is_transmit5_triggered_#res; [L889] havoc is_transmit5_triggered_~__retres1~5; [L428] havoc is_transmit5_triggered_~__retres1~5; [L431-L440] assume !(1 == ~t5_pc~0); [L441] is_transmit5_triggered_~__retres1~5 := 0; [L443] is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; [L889] activate_threads_#t~ret15 := is_transmit5_triggered_#res; [L889] activate_threads_~tmp___4~0 := activate_threads_#t~ret15; [L889] havoc activate_threads_#t~ret15; [L891-L895] assume !(0 != activate_threads_~tmp___4~0); [L897] havoc is_transmit6_triggered_#res; [L897] havoc is_transmit6_triggered_~__retres1~6; [L447] havoc is_transmit6_triggered_~__retres1~6; [L450-L459] assume !(1 == ~t6_pc~0); [L460] is_transmit6_triggered_~__retres1~6 := 0; [L462] is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; [L897] activate_threads_#t~ret16 := is_transmit6_triggered_#res; [L897] activate_threads_~tmp___5~0 := activate_threads_#t~ret16; [L897] havoc activate_threads_#t~ret16; [L899-L903] assume !(0 != activate_threads_~tmp___5~0); [L764-L768] assume !(1 == ~M_E~0); [L769-L773] assume !(1 == ~T1_E~0); [L774-L778] assume !(1 == ~T2_E~0); [L779-L783] assume !(1 == ~T3_E~0); [L784-L788] assume !(1 == ~T4_E~0); [L789-L793] assume !(1 == ~T5_E~0); [L794-L798] assume !(1 == ~T6_E~0); [L799-L803] assume !(1 == ~E_M~0); [L804-L808] assume !(1 == ~E_1~0); [L809-L813] assume !(1 == ~E_2~0); [L814-L818] assume !(1 == ~E_3~0); [L819-L823] assume !(1 == ~E_4~0); [L824-L828] assume !(1 == ~E_5~0); [L829-L833] assume !(1 == ~E_6~0); [L1055-L1092] assume !false; [L1058] start_simulation_~kernel_st~0 := 1; [L1059] havoc eval_#t~ret2, eval_#t~nondet3, eval_~tmp_ndt_1~0, eval_#t~nondet4, eval_~tmp_ndt_2~0, eval_#t~nondet5, eval_~tmp_ndt_3~0, eval_#t~nondet6, eval_~tmp_ndt_4~0, eval_#t~nondet7, eval_~tmp_ndt_5~0, eval_#t~nondet8, eval_~tmp_ndt_6~0, eval_#t~nondet9, eval_~tmp_ndt_7~0, eval_~tmp~0; [L563] havoc eval_~tmp~0; ----- ----- class de.uni_freiburg.informatik.ultimate.boogie.preprocessor.BoogiePreprocessorBacktranslator [L14] ~m_pc~0 := 0; [L15] ~t1_pc~0 := 0; [L16] ~t2_pc~0 := 0; [L17] ~t3_pc~0 := 0; [L18] ~t4_pc~0 := 0; [L19] ~t5_pc~0 := 0; [L20] ~t6_pc~0 := 0; [L21] ~m_st~0 := 0; [L22] ~t1_st~0 := 0; [L23] ~t2_st~0 := 0; [L24] ~t3_st~0 := 0; [L25] ~t4_st~0 := 0; [L26] ~t5_st~0 := 0; [L27] ~t6_st~0 := 0; [L28] ~m_i~0 := 0; [L29] ~t1_i~0 := 0; [L30] ~t2_i~0 := 0; [L31] ~t3_i~0 := 0; [L32] ~t4_i~0 := 0; [L33] ~t5_i~0 := 0; [L34] ~t6_i~0 := 0; [L35] ~M_E~0 := 2; [L36] ~T1_E~0 := 2; [L37] ~T2_E~0 := 2; [L38] ~T3_E~0 := 2; [L39] ~T4_E~0 := 2; [L40] ~T5_E~0 := 2; [L41] ~T6_E~0 := 2; [L42] ~E_M~0 := 2; [L43] ~E_1~0 := 2; [L44] ~E_2~0 := 2; [L45] ~E_3~0 := 2; [L46] ~E_4~0 := 2; [L47] ~E_5~0 := 2; [L48] ~E_6~0 := 2; [L57] ~token~0 := 0; [L59] ~local~0 := 0; [?] havoc main_#res; [?] havoc main_~__retres1~8; [L1100] havoc main_~__retres1~8; [L1010] ~m_i~0 := 1; [L1011] ~t1_i~0 := 1; [L1012] ~t2_i~0 := 1; [L1013] ~t3_i~0 := 1; [L1014] ~t4_i~0 := 1; [L1015] ~t5_i~0 := 1; [L1016] ~t6_i~0 := 1; [L1105] havoc start_simulation_#t~ret18, start_simulation_#t~ret19, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1; [L1041] havoc start_simulation_~kernel_st~0; [L1042] havoc start_simulation_~tmp~3; [L1043] havoc start_simulation_~tmp___0~1; [L1047] start_simulation_~kernel_st~0 := 0; [L477-L481] assume 1 == ~m_i~0; [L478] ~m_st~0 := 0; [L482-L486] assume 1 == ~t1_i~0; [L483] ~t1_st~0 := 0; [L487-L491] assume 1 == ~t2_i~0; [L488] ~t2_st~0 := 0; [L492-L496] assume 1 == ~t3_i~0; [L493] ~t3_st~0 := 0; [L497-L501] assume 1 == ~t4_i~0; [L498] ~t4_st~0 := 0; [L502-L506] assume 1 == ~t5_i~0; [L503] ~t5_st~0 := 0; [L507-L511] assume 1 == ~t6_i~0; [L508] ~t6_st~0 := 0; [L686-L690] assume !(0 == ~M_E~0); [L691-L695] assume !(0 == ~T1_E~0); [L696-L700] assume !(0 == ~T2_E~0); [L701-L705] assume !(0 == ~T3_E~0); [L706-L710] assume !(0 == ~T4_E~0); [L711-L715] assume !(0 == ~T5_E~0); [L716-L720] assume !(0 == ~T6_E~0); [L721-L725] assume !(0 == ~E_M~0); [L726-L730] assume !(0 == ~E_1~0); [L731-L735] assume !(0 == ~E_2~0); [L736-L740] assume !(0 == ~E_3~0); [L741-L745] assume !(0 == ~E_4~0); [L746-L750] assume !(0 == ~E_5~0); [L751-L755] assume !(0 == ~E_6~0); [L1051] havoc activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0; [L839] havoc activate_threads_~tmp~1; [L840] havoc activate_threads_~tmp___0~0; [L841] havoc activate_threads_~tmp___1~0; [L842] havoc activate_threads_~tmp___2~0; [L843] havoc activate_threads_~tmp___3~0; [L844] havoc activate_threads_~tmp___4~0; [L845] havoc activate_threads_~tmp___5~0; [L849] havoc is_master_triggered_#res; [L849] havoc is_master_triggered_~__retres1~0; [L333] havoc is_master_triggered_~__retres1~0; [L336-L345] assume !(1 == ~m_pc~0); [L346] is_master_triggered_~__retres1~0 := 0; [L348] is_master_triggered_#res := is_master_triggered_~__retres1~0; [L849] activate_threads_#t~ret10 := is_master_triggered_#res; [L849] activate_threads_~tmp~1 := activate_threads_#t~ret10; [L849] havoc activate_threads_#t~ret10; [L851-L855] assume !(0 != activate_threads_~tmp~1); [L857] havoc is_transmit1_triggered_#res; [L857] havoc is_transmit1_triggered_~__retres1~1; [L352] havoc is_transmit1_triggered_~__retres1~1; [L355-L364] assume !(1 == ~t1_pc~0); [L365] is_transmit1_triggered_~__retres1~1 := 0; [L367] is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; [L857] activate_threads_#t~ret11 := is_transmit1_triggered_#res; [L857] activate_threads_~tmp___0~0 := activate_threads_#t~ret11; [L857] havoc activate_threads_#t~ret11; [L859-L863] assume !(0 != activate_threads_~tmp___0~0); [L865] havoc is_transmit2_triggered_#res; [L865] havoc is_transmit2_triggered_~__retres1~2; [L371] havoc is_transmit2_triggered_~__retres1~2; [L374-L383] assume !(1 == ~t2_pc~0); [L384] is_transmit2_triggered_~__retres1~2 := 0; [L386] is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; [L865] activate_threads_#t~ret12 := is_transmit2_triggered_#res; [L865] activate_threads_~tmp___1~0 := activate_threads_#t~ret12; [L865] havoc activate_threads_#t~ret12; [L867-L871] assume !(0 != activate_threads_~tmp___1~0); [L873] havoc is_transmit3_triggered_#res; [L873] havoc is_transmit3_triggered_~__retres1~3; [L390] havoc is_transmit3_triggered_~__retres1~3; [L393-L402] assume !(1 == ~t3_pc~0); [L403] is_transmit3_triggered_~__retres1~3 := 0; [L405] is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; [L873] activate_threads_#t~ret13 := is_transmit3_triggered_#res; [L873] activate_threads_~tmp___2~0 := activate_threads_#t~ret13; [L873] havoc activate_threads_#t~ret13; [L875-L879] assume !(0 != activate_threads_~tmp___2~0); [L881] havoc is_transmit4_triggered_#res; [L881] havoc is_transmit4_triggered_~__retres1~4; [L409] havoc is_transmit4_triggered_~__retres1~4; [L412-L421] assume !(1 == ~t4_pc~0); [L422] is_transmit4_triggered_~__retres1~4 := 0; [L424] is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; [L881] activate_threads_#t~ret14 := is_transmit4_triggered_#res; [L881] activate_threads_~tmp___3~0 := activate_threads_#t~ret14; [L881] havoc activate_threads_#t~ret14; [L883-L887] assume !(0 != activate_threads_~tmp___3~0); [L889] havoc is_transmit5_triggered_#res; [L889] havoc is_transmit5_triggered_~__retres1~5; [L428] havoc is_transmit5_triggered_~__retres1~5; [L431-L440] assume !(1 == ~t5_pc~0); [L441] is_transmit5_triggered_~__retres1~5 := 0; [L443] is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; [L889] activate_threads_#t~ret15 := is_transmit5_triggered_#res; [L889] activate_threads_~tmp___4~0 := activate_threads_#t~ret15; [L889] havoc activate_threads_#t~ret15; [L891-L895] assume !(0 != activate_threads_~tmp___4~0); [L897] havoc is_transmit6_triggered_#res; [L897] havoc is_transmit6_triggered_~__retres1~6; [L447] havoc is_transmit6_triggered_~__retres1~6; [L450-L459] assume !(1 == ~t6_pc~0); [L460] is_transmit6_triggered_~__retres1~6 := 0; [L462] is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; [L897] activate_threads_#t~ret16 := is_transmit6_triggered_#res; [L897] activate_threads_~tmp___5~0 := activate_threads_#t~ret16; [L897] havoc activate_threads_#t~ret16; [L899-L903] assume !(0 != activate_threads_~tmp___5~0); [L764-L768] assume !(1 == ~M_E~0); [L769-L773] assume !(1 == ~T1_E~0); [L774-L778] assume !(1 == ~T2_E~0); [L779-L783] assume !(1 == ~T3_E~0); [L784-L788] assume !(1 == ~T4_E~0); [L789-L793] assume !(1 == ~T5_E~0); [L794-L798] assume !(1 == ~T6_E~0); [L799-L803] assume !(1 == ~E_M~0); [L804-L808] assume !(1 == ~E_1~0); [L809-L813] assume !(1 == ~E_2~0); [L814-L818] assume !(1 == ~E_3~0); [L819-L823] assume !(1 == ~E_4~0); [L824-L828] assume !(1 == ~E_5~0); [L829-L833] assume !(1 == ~E_6~0); [L1055-L1092] assume !false; [L1058] start_simulation_~kernel_st~0 := 1; [L1059] havoc eval_#t~ret2, eval_#t~nondet3, eval_~tmp_ndt_1~0, eval_#t~nondet4, eval_~tmp_ndt_2~0, eval_#t~nondet5, eval_~tmp_ndt_3~0, eval_#t~nondet6, eval_~tmp_ndt_4~0, eval_#t~nondet7, eval_~tmp_ndt_5~0, eval_#t~nondet8, eval_~tmp_ndt_6~0, eval_#t~nondet9, eval_~tmp_ndt_7~0, eval_~tmp~0; [L563] havoc eval_~tmp~0; [L14] ~m_pc~0 := 0; [L15] ~t1_pc~0 := 0; [L16] ~t2_pc~0 := 0; [L17] ~t3_pc~0 := 0; [L18] ~t4_pc~0 := 0; [L19] ~t5_pc~0 := 0; [L20] ~t6_pc~0 := 0; [L21] ~m_st~0 := 0; [L22] ~t1_st~0 := 0; [L23] ~t2_st~0 := 0; [L24] ~t3_st~0 := 0; [L25] ~t4_st~0 := 0; [L26] ~t5_st~0 := 0; [L27] ~t6_st~0 := 0; [L28] ~m_i~0 := 0; [L29] ~t1_i~0 := 0; [L30] ~t2_i~0 := 0; [L31] ~t3_i~0 := 0; [L32] ~t4_i~0 := 0; [L33] ~t5_i~0 := 0; [L34] ~t6_i~0 := 0; [L35] ~M_E~0 := 2; [L36] ~T1_E~0 := 2; [L37] ~T2_E~0 := 2; [L38] ~T3_E~0 := 2; [L39] ~T4_E~0 := 2; [L40] ~T5_E~0 := 2; [L41] ~T6_E~0 := 2; [L42] ~E_M~0 := 2; [L43] ~E_1~0 := 2; [L44] ~E_2~0 := 2; [L45] ~E_3~0 := 2; [L46] ~E_4~0 := 2; [L47] ~E_5~0 := 2; [L48] ~E_6~0 := 2; [L57] ~token~0 := 0; [L59] ~local~0 := 0; [?] havoc main_#res; [?] havoc main_~__retres1~8; [L1100] havoc main_~__retres1~8; [L1010] ~m_i~0 := 1; [L1011] ~t1_i~0 := 1; [L1012] ~t2_i~0 := 1; [L1013] ~t3_i~0 := 1; [L1014] ~t4_i~0 := 1; [L1015] ~t5_i~0 := 1; [L1016] ~t6_i~0 := 1; [L1105] havoc start_simulation_#t~ret18, start_simulation_#t~ret19, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1; [L1041] havoc start_simulation_~kernel_st~0; [L1042] havoc start_simulation_~tmp~3; [L1043] havoc start_simulation_~tmp___0~1; [L1047] start_simulation_~kernel_st~0 := 0; [L477] COND TRUE 1 == ~m_i~0 [L478] ~m_st~0 := 0; [L482] COND TRUE 1 == ~t1_i~0 [L483] ~t1_st~0 := 0; [L487] COND TRUE 1 == ~t2_i~0 [L488] ~t2_st~0 := 0; [L492] COND TRUE 1 == ~t3_i~0 [L493] ~t3_st~0 := 0; [L497] COND TRUE 1 == ~t4_i~0 [L498] ~t4_st~0 := 0; [L502] COND TRUE 1 == ~t5_i~0 [L503] ~t5_st~0 := 0; [L507] COND TRUE 1 == ~t6_i~0 [L508] ~t6_st~0 := 0; [L686] COND FALSE !(0 == ~M_E~0) [L691] COND FALSE !(0 == ~T1_E~0) [L696] COND FALSE !(0 == ~T2_E~0) [L701] COND FALSE !(0 == ~T3_E~0) [L706] COND FALSE !(0 == ~T4_E~0) [L711] COND FALSE !(0 == ~T5_E~0) [L716] COND FALSE !(0 == ~T6_E~0) [L721] COND FALSE !(0 == ~E_M~0) [L726] COND FALSE !(0 == ~E_1~0) [L731] COND FALSE !(0 == ~E_2~0) [L736] COND FALSE !(0 == ~E_3~0) [L741] COND FALSE !(0 == ~E_4~0) [L746] COND FALSE !(0 == ~E_5~0) [L751] COND FALSE !(0 == ~E_6~0) [L1051] havoc activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0; [L839] havoc activate_threads_~tmp~1; [L840] havoc activate_threads_~tmp___0~0; [L841] havoc activate_threads_~tmp___1~0; [L842] havoc activate_threads_~tmp___2~0; [L843] havoc activate_threads_~tmp___3~0; [L844] havoc activate_threads_~tmp___4~0; [L845] havoc activate_threads_~tmp___5~0; [L849] havoc is_master_triggered_#res; [L849] havoc is_master_triggered_~__retres1~0; [L333] havoc is_master_triggered_~__retres1~0; [L336] COND FALSE !(1 == ~m_pc~0) [L346] is_master_triggered_~__retres1~0 := 0; [L348] is_master_triggered_#res := is_master_triggered_~__retres1~0; [L849] activate_threads_#t~ret10 := is_master_triggered_#res; [L849] activate_threads_~tmp~1 := activate_threads_#t~ret10; [L849] havoc activate_threads_#t~ret10; [L851-L855] COND FALSE !(0 != activate_threads_~tmp~1) [L857] havoc is_transmit1_triggered_#res; [L857] havoc is_transmit1_triggered_~__retres1~1; [L352] havoc is_transmit1_triggered_~__retres1~1; [L355] COND FALSE !(1 == ~t1_pc~0) [L365] is_transmit1_triggered_~__retres1~1 := 0; [L367] is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; [L857] activate_threads_#t~ret11 := is_transmit1_triggered_#res; [L857] activate_threads_~tmp___0~0 := activate_threads_#t~ret11; [L857] havoc activate_threads_#t~ret11; [L859-L863] COND FALSE !(0 != activate_threads_~tmp___0~0) [L865] havoc is_transmit2_triggered_#res; [L865] havoc is_transmit2_triggered_~__retres1~2; [L371] havoc is_transmit2_triggered_~__retres1~2; [L374] COND FALSE !(1 == ~t2_pc~0) [L384] is_transmit2_triggered_~__retres1~2 := 0; [L386] is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; [L865] activate_threads_#t~ret12 := is_transmit2_triggered_#res; [L865] activate_threads_~tmp___1~0 := activate_threads_#t~ret12; [L865] havoc activate_threads_#t~ret12; [L867-L871] COND FALSE !(0 != activate_threads_~tmp___1~0) [L873] havoc is_transmit3_triggered_#res; [L873] havoc is_transmit3_triggered_~__retres1~3; [L390] havoc is_transmit3_triggered_~__retres1~3; [L393] COND FALSE !(1 == ~t3_pc~0) [L403] is_transmit3_triggered_~__retres1~3 := 0; [L405] is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; [L873] activate_threads_#t~ret13 := is_transmit3_triggered_#res; [L873] activate_threads_~tmp___2~0 := activate_threads_#t~ret13; [L873] havoc activate_threads_#t~ret13; [L875-L879] COND FALSE !(0 != activate_threads_~tmp___2~0) [L881] havoc is_transmit4_triggered_#res; [L881] havoc is_transmit4_triggered_~__retres1~4; [L409] havoc is_transmit4_triggered_~__retres1~4; [L412] COND FALSE !(1 == ~t4_pc~0) [L422] is_transmit4_triggered_~__retres1~4 := 0; [L424] is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; [L881] activate_threads_#t~ret14 := is_transmit4_triggered_#res; [L881] activate_threads_~tmp___3~0 := activate_threads_#t~ret14; [L881] havoc activate_threads_#t~ret14; [L883-L887] COND FALSE !(0 != activate_threads_~tmp___3~0) [L889] havoc is_transmit5_triggered_#res; [L889] havoc is_transmit5_triggered_~__retres1~5; [L428] havoc is_transmit5_triggered_~__retres1~5; [L431] COND FALSE !(1 == ~t5_pc~0) [L441] is_transmit5_triggered_~__retres1~5 := 0; [L443] is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; [L889] activate_threads_#t~ret15 := is_transmit5_triggered_#res; [L889] activate_threads_~tmp___4~0 := activate_threads_#t~ret15; [L889] havoc activate_threads_#t~ret15; [L891-L895] COND FALSE !(0 != activate_threads_~tmp___4~0) [L897] havoc is_transmit6_triggered_#res; [L897] havoc is_transmit6_triggered_~__retres1~6; [L447] havoc is_transmit6_triggered_~__retres1~6; [L450] COND FALSE !(1 == ~t6_pc~0) [L460] is_transmit6_triggered_~__retres1~6 := 0; [L462] is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; [L897] activate_threads_#t~ret16 := is_transmit6_triggered_#res; [L897] activate_threads_~tmp___5~0 := activate_threads_#t~ret16; [L897] havoc activate_threads_#t~ret16; [L899-L903] COND FALSE !(0 != activate_threads_~tmp___5~0) [L764] COND FALSE !(1 == ~M_E~0) [L769] COND FALSE !(1 == ~T1_E~0) [L774] COND FALSE !(1 == ~T2_E~0) [L779] COND FALSE !(1 == ~T3_E~0) [L784] COND FALSE !(1 == ~T4_E~0) [L789] COND FALSE !(1 == ~T5_E~0) [L794] COND FALSE !(1 == ~T6_E~0) [L799] COND FALSE !(1 == ~E_M~0) [L804] COND FALSE !(1 == ~E_1~0) [L809] COND FALSE !(1 == ~E_2~0) [L814] COND FALSE !(1 == ~E_3~0) [L819] COND FALSE !(1 == ~E_4~0) [L824] COND FALSE !(1 == ~E_5~0) [L829] COND FALSE !(1 == ~E_6~0) [L1055-L1092] COND FALSE !(false) [L1058] start_simulation_~kernel_st~0 := 1; [L1059] havoc eval_#t~ret2, eval_#t~nondet3, eval_~tmp_ndt_1~0, eval_#t~nondet4, eval_~tmp_ndt_2~0, eval_#t~nondet5, eval_~tmp_ndt_3~0, eval_#t~nondet6, eval_~tmp_ndt_4~0, eval_#t~nondet7, eval_~tmp_ndt_5~0, eval_#t~nondet8, eval_~tmp_ndt_6~0, eval_#t~nondet9, eval_~tmp_ndt_7~0, eval_~tmp~0; [L563] havoc eval_~tmp~0; ----- ----- class de.uni_freiburg.informatik.ultimate.boogie.procedureinliner.backtranslation.InlinerBacktranslator [L14] ~m_pc~0 := 0; [L15] ~t1_pc~0 := 0; [L16] ~t2_pc~0 := 0; [L17] ~t3_pc~0 := 0; [L18] ~t4_pc~0 := 0; [L19] ~t5_pc~0 := 0; [L20] ~t6_pc~0 := 0; [L21] ~m_st~0 := 0; [L22] ~t1_st~0 := 0; [L23] ~t2_st~0 := 0; [L24] ~t3_st~0 := 0; [L25] ~t4_st~0 := 0; [L26] ~t5_st~0 := 0; [L27] ~t6_st~0 := 0; [L28] ~m_i~0 := 0; [L29] ~t1_i~0 := 0; [L30] ~t2_i~0 := 0; [L31] ~t3_i~0 := 0; [L32] ~t4_i~0 := 0; [L33] ~t5_i~0 := 0; [L34] ~t6_i~0 := 0; [L35] ~M_E~0 := 2; [L36] ~T1_E~0 := 2; [L37] ~T2_E~0 := 2; [L38] ~T3_E~0 := 2; [L39] ~T4_E~0 := 2; [L40] ~T5_E~0 := 2; [L41] ~T6_E~0 := 2; [L42] ~E_M~0 := 2; [L43] ~E_1~0 := 2; [L44] ~E_2~0 := 2; [L45] ~E_3~0 := 2; [L46] ~E_4~0 := 2; [L47] ~E_5~0 := 2; [L48] ~E_6~0 := 2; [L57] ~token~0 := 0; [L59] ~local~0 := 0; [?] havoc main_#res; [?] havoc main_~__retres1~8; [L1100] havoc main_~__retres1~8; [L1010] ~m_i~0 := 1; [L1011] ~t1_i~0 := 1; [L1012] ~t2_i~0 := 1; [L1013] ~t3_i~0 := 1; [L1014] ~t4_i~0 := 1; [L1015] ~t5_i~0 := 1; [L1016] ~t6_i~0 := 1; [L1105] havoc start_simulation_#t~ret18, start_simulation_#t~ret19, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1; [L1041] havoc start_simulation_~kernel_st~0; [L1042] havoc start_simulation_~tmp~3; [L1043] havoc start_simulation_~tmp___0~1; [L1047] start_simulation_~kernel_st~0 := 0; [L477] COND TRUE 1 == ~m_i~0 [L478] ~m_st~0 := 0; [L482] COND TRUE 1 == ~t1_i~0 [L483] ~t1_st~0 := 0; [L487] COND TRUE 1 == ~t2_i~0 [L488] ~t2_st~0 := 0; [L492] COND TRUE 1 == ~t3_i~0 [L493] ~t3_st~0 := 0; [L497] COND TRUE 1 == ~t4_i~0 [L498] ~t4_st~0 := 0; [L502] COND TRUE 1 == ~t5_i~0 [L503] ~t5_st~0 := 0; [L507] COND TRUE 1 == ~t6_i~0 [L508] ~t6_st~0 := 0; [L686] COND FALSE !(0 == ~M_E~0) [L691] COND FALSE !(0 == ~T1_E~0) [L696] COND FALSE !(0 == ~T2_E~0) [L701] COND FALSE !(0 == ~T3_E~0) [L706] COND FALSE !(0 == ~T4_E~0) [L711] COND FALSE !(0 == ~T5_E~0) [L716] COND FALSE !(0 == ~T6_E~0) [L721] COND FALSE !(0 == ~E_M~0) [L726] COND FALSE !(0 == ~E_1~0) [L731] COND FALSE !(0 == ~E_2~0) [L736] COND FALSE !(0 == ~E_3~0) [L741] COND FALSE !(0 == ~E_4~0) [L746] COND FALSE !(0 == ~E_5~0) [L751] COND FALSE !(0 == ~E_6~0) [L1051] havoc activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0; [L839] havoc activate_threads_~tmp~1; [L840] havoc activate_threads_~tmp___0~0; [L841] havoc activate_threads_~tmp___1~0; [L842] havoc activate_threads_~tmp___2~0; [L843] havoc activate_threads_~tmp___3~0; [L844] havoc activate_threads_~tmp___4~0; [L845] havoc activate_threads_~tmp___5~0; [L849] havoc is_master_triggered_#res; [L849] havoc is_master_triggered_~__retres1~0; [L333] havoc is_master_triggered_~__retres1~0; [L336] COND FALSE !(1 == ~m_pc~0) [L346] is_master_triggered_~__retres1~0 := 0; [L348] is_master_triggered_#res := is_master_triggered_~__retres1~0; [L849] activate_threads_#t~ret10 := is_master_triggered_#res; [L849] activate_threads_~tmp~1 := activate_threads_#t~ret10; [L849] havoc activate_threads_#t~ret10; [L851-L855] COND FALSE !(0 != activate_threads_~tmp~1) [L857] havoc is_transmit1_triggered_#res; [L857] havoc is_transmit1_triggered_~__retres1~1; [L352] havoc is_transmit1_triggered_~__retres1~1; [L355] COND FALSE !(1 == ~t1_pc~0) [L365] is_transmit1_triggered_~__retres1~1 := 0; [L367] is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; [L857] activate_threads_#t~ret11 := is_transmit1_triggered_#res; [L857] activate_threads_~tmp___0~0 := activate_threads_#t~ret11; [L857] havoc activate_threads_#t~ret11; [L859-L863] COND FALSE !(0 != activate_threads_~tmp___0~0) [L865] havoc is_transmit2_triggered_#res; [L865] havoc is_transmit2_triggered_~__retres1~2; [L371] havoc is_transmit2_triggered_~__retres1~2; [L374] COND FALSE !(1 == ~t2_pc~0) [L384] is_transmit2_triggered_~__retres1~2 := 0; [L386] is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; [L865] activate_threads_#t~ret12 := is_transmit2_triggered_#res; [L865] activate_threads_~tmp___1~0 := activate_threads_#t~ret12; [L865] havoc activate_threads_#t~ret12; [L867-L871] COND FALSE !(0 != activate_threads_~tmp___1~0) [L873] havoc is_transmit3_triggered_#res; [L873] havoc is_transmit3_triggered_~__retres1~3; [L390] havoc is_transmit3_triggered_~__retres1~3; [L393] COND FALSE !(1 == ~t3_pc~0) [L403] is_transmit3_triggered_~__retres1~3 := 0; [L405] is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; [L873] activate_threads_#t~ret13 := is_transmit3_triggered_#res; [L873] activate_threads_~tmp___2~0 := activate_threads_#t~ret13; [L873] havoc activate_threads_#t~ret13; [L875-L879] COND FALSE !(0 != activate_threads_~tmp___2~0) [L881] havoc is_transmit4_triggered_#res; [L881] havoc is_transmit4_triggered_~__retres1~4; [L409] havoc is_transmit4_triggered_~__retres1~4; [L412] COND FALSE !(1 == ~t4_pc~0) [L422] is_transmit4_triggered_~__retres1~4 := 0; [L424] is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; [L881] activate_threads_#t~ret14 := is_transmit4_triggered_#res; [L881] activate_threads_~tmp___3~0 := activate_threads_#t~ret14; [L881] havoc activate_threads_#t~ret14; [L883-L887] COND FALSE !(0 != activate_threads_~tmp___3~0) [L889] havoc is_transmit5_triggered_#res; [L889] havoc is_transmit5_triggered_~__retres1~5; [L428] havoc is_transmit5_triggered_~__retres1~5; [L431] COND FALSE !(1 == ~t5_pc~0) [L441] is_transmit5_triggered_~__retres1~5 := 0; [L443] is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; [L889] activate_threads_#t~ret15 := is_transmit5_triggered_#res; [L889] activate_threads_~tmp___4~0 := activate_threads_#t~ret15; [L889] havoc activate_threads_#t~ret15; [L891-L895] COND FALSE !(0 != activate_threads_~tmp___4~0) [L897] havoc is_transmit6_triggered_#res; [L897] havoc is_transmit6_triggered_~__retres1~6; [L447] havoc is_transmit6_triggered_~__retres1~6; [L450] COND FALSE !(1 == ~t6_pc~0) [L460] is_transmit6_triggered_~__retres1~6 := 0; [L462] is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; [L897] activate_threads_#t~ret16 := is_transmit6_triggered_#res; [L897] activate_threads_~tmp___5~0 := activate_threads_#t~ret16; [L897] havoc activate_threads_#t~ret16; [L899-L903] COND FALSE !(0 != activate_threads_~tmp___5~0) [L764] COND FALSE !(1 == ~M_E~0) [L769] COND FALSE !(1 == ~T1_E~0) [L774] COND FALSE !(1 == ~T2_E~0) [L779] COND FALSE !(1 == ~T3_E~0) [L784] COND FALSE !(1 == ~T4_E~0) [L789] COND FALSE !(1 == ~T5_E~0) [L794] COND FALSE !(1 == ~T6_E~0) [L799] COND FALSE !(1 == ~E_M~0) [L804] COND FALSE !(1 == ~E_1~0) [L809] COND FALSE !(1 == ~E_2~0) [L814] COND FALSE !(1 == ~E_3~0) [L819] COND FALSE !(1 == ~E_4~0) [L824] COND FALSE !(1 == ~E_5~0) [L829] COND FALSE !(1 == ~E_6~0) [L1055-L1092] COND FALSE !(false) [L1058] start_simulation_~kernel_st~0 := 1; [L1059] havoc eval_#t~ret2, eval_#t~nondet3, eval_~tmp_ndt_1~0, eval_#t~nondet4, eval_~tmp_ndt_2~0, eval_#t~nondet5, eval_~tmp_ndt_3~0, eval_#t~nondet6, eval_~tmp_ndt_4~0, eval_#t~nondet7, eval_~tmp_ndt_5~0, eval_#t~nondet8, eval_~tmp_ndt_6~0, eval_#t~nondet9, eval_~tmp_ndt_7~0, eval_~tmp~0; [L563] havoc eval_~tmp~0; [L14] ~m_pc~0 := 0; [L15] ~t1_pc~0 := 0; [L16] ~t2_pc~0 := 0; [L17] ~t3_pc~0 := 0; [L18] ~t4_pc~0 := 0; [L19] ~t5_pc~0 := 0; [L20] ~t6_pc~0 := 0; [L21] ~m_st~0 := 0; [L22] ~t1_st~0 := 0; [L23] ~t2_st~0 := 0; [L24] ~t3_st~0 := 0; [L25] ~t4_st~0 := 0; [L26] ~t5_st~0 := 0; [L27] ~t6_st~0 := 0; [L28] ~m_i~0 := 0; [L29] ~t1_i~0 := 0; [L30] ~t2_i~0 := 0; [L31] ~t3_i~0 := 0; [L32] ~t4_i~0 := 0; [L33] ~t5_i~0 := 0; [L34] ~t6_i~0 := 0; [L35] ~M_E~0 := 2; [L36] ~T1_E~0 := 2; [L37] ~T2_E~0 := 2; [L38] ~T3_E~0 := 2; [L39] ~T4_E~0 := 2; [L40] ~T5_E~0 := 2; [L41] ~T6_E~0 := 2; [L42] ~E_M~0 := 2; [L43] ~E_1~0 := 2; [L44] ~E_2~0 := 2; [L45] ~E_3~0 := 2; [L46] ~E_4~0 := 2; [L47] ~E_5~0 := 2; [L48] ~E_6~0 := 2; [L57] ~token~0 := 0; [L59] ~local~0 := 0; [L1100] havoc ~__retres1~8; [L1010] ~m_i~0 := 1; [L1011] ~t1_i~0 := 1; [L1012] ~t2_i~0 := 1; [L1013] ~t3_i~0 := 1; [L1014] ~t4_i~0 := 1; [L1015] ~t5_i~0 := 1; [L1016] ~t6_i~0 := 1; [L1041] havoc ~kernel_st~0; [L1042] havoc ~tmp~3; [L1043] havoc ~tmp___0~1; [L1047] ~kernel_st~0 := 0; [L477] COND TRUE 1 == ~m_i~0 [L478] ~m_st~0 := 0; [L482] COND TRUE 1 == ~t1_i~0 [L483] ~t1_st~0 := 0; [L487] COND TRUE 1 == ~t2_i~0 [L488] ~t2_st~0 := 0; [L492] COND TRUE 1 == ~t3_i~0 [L493] ~t3_st~0 := 0; [L497] COND TRUE 1 == ~t4_i~0 [L498] ~t4_st~0 := 0; [L502] COND TRUE 1 == ~t5_i~0 [L503] ~t5_st~0 := 0; [L507] COND TRUE 1 == ~t6_i~0 [L508] ~t6_st~0 := 0; [L686] COND FALSE !(0 == ~M_E~0) [L691] COND FALSE !(0 == ~T1_E~0) [L696] COND FALSE !(0 == ~T2_E~0) [L701] COND FALSE !(0 == ~T3_E~0) [L706] COND FALSE !(0 == ~T4_E~0) [L711] COND FALSE !(0 == ~T5_E~0) [L716] COND FALSE !(0 == ~T6_E~0) [L721] COND FALSE !(0 == ~E_M~0) [L726] COND FALSE !(0 == ~E_1~0) [L731] COND FALSE !(0 == ~E_2~0) [L736] COND FALSE !(0 == ~E_3~0) [L741] COND FALSE !(0 == ~E_4~0) [L746] COND FALSE !(0 == ~E_5~0) [L751] COND FALSE !(0 == ~E_6~0) [L839] havoc ~tmp~1; [L840] havoc ~tmp___0~0; [L841] havoc ~tmp___1~0; [L842] havoc ~tmp___2~0; [L843] havoc ~tmp___3~0; [L844] havoc ~tmp___4~0; [L845] havoc ~tmp___5~0; [L333] havoc ~__retres1~0; [L336] COND FALSE !(1 == ~m_pc~0) [L346] ~__retres1~0 := 0; [L348] #res := ~__retres1~0; [L849] ~tmp~1 := #t~ret10; [L849] havoc #t~ret10; [L851-L855] COND FALSE !(0 != ~tmp~1) [L352] havoc ~__retres1~1; [L355] COND FALSE !(1 == ~t1_pc~0) [L365] ~__retres1~1 := 0; [L367] #res := ~__retres1~1; [L857] ~tmp___0~0 := #t~ret11; [L857] havoc #t~ret11; [L859-L863] COND FALSE !(0 != ~tmp___0~0) [L371] havoc ~__retres1~2; [L374] COND FALSE !(1 == ~t2_pc~0) [L384] ~__retres1~2 := 0; [L386] #res := ~__retres1~2; [L865] ~tmp___1~0 := #t~ret12; [L865] havoc #t~ret12; [L867-L871] COND FALSE !(0 != ~tmp___1~0) [L390] havoc ~__retres1~3; [L393] COND FALSE !(1 == ~t3_pc~0) [L403] ~__retres1~3 := 0; [L405] #res := ~__retres1~3; [L873] ~tmp___2~0 := #t~ret13; [L873] havoc #t~ret13; [L875-L879] COND FALSE !(0 != ~tmp___2~0) [L409] havoc ~__retres1~4; [L412] COND FALSE !(1 == ~t4_pc~0) [L422] ~__retres1~4 := 0; [L424] #res := ~__retres1~4; [L881] ~tmp___3~0 := #t~ret14; [L881] havoc #t~ret14; [L883-L887] COND FALSE !(0 != ~tmp___3~0) [L428] havoc ~__retres1~5; [L431] COND FALSE !(1 == ~t5_pc~0) [L441] ~__retres1~5 := 0; [L443] #res := ~__retres1~5; [L889] ~tmp___4~0 := #t~ret15; [L889] havoc #t~ret15; [L891-L895] COND FALSE !(0 != ~tmp___4~0) [L447] havoc ~__retres1~6; [L450] COND FALSE !(1 == ~t6_pc~0) [L460] ~__retres1~6 := 0; [L462] #res := ~__retres1~6; [L897] ~tmp___5~0 := #t~ret16; [L897] havoc #t~ret16; [L899-L903] COND FALSE !(0 != ~tmp___5~0) [L764] COND FALSE !(1 == ~M_E~0) [L769] COND FALSE !(1 == ~T1_E~0) [L774] COND FALSE !(1 == ~T2_E~0) [L779] COND FALSE !(1 == ~T3_E~0) [L784] COND FALSE !(1 == ~T4_E~0) [L789] COND FALSE !(1 == ~T5_E~0) [L794] COND FALSE !(1 == ~T6_E~0) [L799] COND FALSE !(1 == ~E_M~0) [L804] COND FALSE !(1 == ~E_1~0) [L809] COND FALSE !(1 == ~E_2~0) [L814] COND FALSE !(1 == ~E_3~0) [L819] COND FALSE !(1 == ~E_4~0) [L824] COND FALSE !(1 == ~E_5~0) [L829] COND FALSE !(1 == ~E_6~0) [L1055-L1092] COND FALSE !(false) [L1058] ~kernel_st~0 := 1; [L563] havoc ~tmp~0; ----- ----- class de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.CACSL2BoogieBacktranslator [L14] ~m_pc~0 := 0; [L15] ~t1_pc~0 := 0; [L16] ~t2_pc~0 := 0; [L17] ~t3_pc~0 := 0; [L18] ~t4_pc~0 := 0; [L19] ~t5_pc~0 := 0; [L20] ~t6_pc~0 := 0; [L21] ~m_st~0 := 0; [L22] ~t1_st~0 := 0; [L23] ~t2_st~0 := 0; [L24] ~t3_st~0 := 0; [L25] ~t4_st~0 := 0; [L26] ~t5_st~0 := 0; [L27] ~t6_st~0 := 0; [L28] ~m_i~0 := 0; [L29] ~t1_i~0 := 0; [L30] ~t2_i~0 := 0; [L31] ~t3_i~0 := 0; [L32] ~t4_i~0 := 0; [L33] ~t5_i~0 := 0; [L34] ~t6_i~0 := 0; [L35] ~M_E~0 := 2; [L36] ~T1_E~0 := 2; [L37] ~T2_E~0 := 2; [L38] ~T3_E~0 := 2; [L39] ~T4_E~0 := 2; [L40] ~T5_E~0 := 2; [L41] ~T6_E~0 := 2; [L42] ~E_M~0 := 2; [L43] ~E_1~0 := 2; [L44] ~E_2~0 := 2; [L45] ~E_3~0 := 2; [L46] ~E_4~0 := 2; [L47] ~E_5~0 := 2; [L48] ~E_6~0 := 2; [L57] ~token~0 := 0; [L59] ~local~0 := 0; [L1100] havoc ~__retres1~8; [L1010] ~m_i~0 := 1; [L1011] ~t1_i~0 := 1; [L1012] ~t2_i~0 := 1; [L1013] ~t3_i~0 := 1; [L1014] ~t4_i~0 := 1; [L1015] ~t5_i~0 := 1; [L1016] ~t6_i~0 := 1; [L1041] havoc ~kernel_st~0; [L1042] havoc ~tmp~3; [L1043] havoc ~tmp___0~1; [L1047] ~kernel_st~0 := 0; [L477] COND TRUE 1 == ~m_i~0 [L478] ~m_st~0 := 0; [L482] COND TRUE 1 == ~t1_i~0 [L483] ~t1_st~0 := 0; [L487] COND TRUE 1 == ~t2_i~0 [L488] ~t2_st~0 := 0; [L492] COND TRUE 1 == ~t3_i~0 [L493] ~t3_st~0 := 0; [L497] COND TRUE 1 == ~t4_i~0 [L498] ~t4_st~0 := 0; [L502] COND TRUE 1 == ~t5_i~0 [L503] ~t5_st~0 := 0; [L507] COND TRUE 1 == ~t6_i~0 [L508] ~t6_st~0 := 0; [L686] COND FALSE !(0 == ~M_E~0) [L691] COND FALSE !(0 == ~T1_E~0) [L696] COND FALSE !(0 == ~T2_E~0) [L701] COND FALSE !(0 == ~T3_E~0) [L706] COND FALSE !(0 == ~T4_E~0) [L711] COND FALSE !(0 == ~T5_E~0) [L716] COND FALSE !(0 == ~T6_E~0) [L721] COND FALSE !(0 == ~E_M~0) [L726] COND FALSE !(0 == ~E_1~0) [L731] COND FALSE !(0 == ~E_2~0) [L736] COND FALSE !(0 == ~E_3~0) [L741] COND FALSE !(0 == ~E_4~0) [L746] COND FALSE !(0 == ~E_5~0) [L751] COND FALSE !(0 == ~E_6~0) [L839] havoc ~tmp~1; [L840] havoc ~tmp___0~0; [L841] havoc ~tmp___1~0; [L842] havoc ~tmp___2~0; [L843] havoc ~tmp___3~0; [L844] havoc ~tmp___4~0; [L845] havoc ~tmp___5~0; [L333] havoc ~__retres1~0; [L336] COND FALSE !(1 == ~m_pc~0) [L346] ~__retres1~0 := 0; [L348] #res := ~__retres1~0; [L849] ~tmp~1 := #t~ret10; [L849] havoc #t~ret10; [L851-L855] COND FALSE !(0 != ~tmp~1) [L352] havoc ~__retres1~1; [L355] COND FALSE !(1 == ~t1_pc~0) [L365] ~__retres1~1 := 0; [L367] #res := ~__retres1~1; [L857] ~tmp___0~0 := #t~ret11; [L857] havoc #t~ret11; [L859-L863] COND FALSE !(0 != ~tmp___0~0) [L371] havoc ~__retres1~2; [L374] COND FALSE !(1 == ~t2_pc~0) [L384] ~__retres1~2 := 0; [L386] #res := ~__retres1~2; [L865] ~tmp___1~0 := #t~ret12; [L865] havoc #t~ret12; [L867-L871] COND FALSE !(0 != ~tmp___1~0) [L390] havoc ~__retres1~3; [L393] COND FALSE !(1 == ~t3_pc~0) [L403] ~__retres1~3 := 0; [L405] #res := ~__retres1~3; [L873] ~tmp___2~0 := #t~ret13; [L873] havoc #t~ret13; [L875-L879] COND FALSE !(0 != ~tmp___2~0) [L409] havoc ~__retres1~4; [L412] COND FALSE !(1 == ~t4_pc~0) [L422] ~__retres1~4 := 0; [L424] #res := ~__retres1~4; [L881] ~tmp___3~0 := #t~ret14; [L881] havoc #t~ret14; [L883-L887] COND FALSE !(0 != ~tmp___3~0) [L428] havoc ~__retres1~5; [L431] COND FALSE !(1 == ~t5_pc~0) [L441] ~__retres1~5 := 0; [L443] #res := ~__retres1~5; [L889] ~tmp___4~0 := #t~ret15; [L889] havoc #t~ret15; [L891-L895] COND FALSE !(0 != ~tmp___4~0) [L447] havoc ~__retres1~6; [L450] COND FALSE !(1 == ~t6_pc~0) [L460] ~__retres1~6 := 0; [L462] #res := ~__retres1~6; [L897] ~tmp___5~0 := #t~ret16; [L897] havoc #t~ret16; [L899-L903] COND FALSE !(0 != ~tmp___5~0) [L764] COND FALSE !(1 == ~M_E~0) [L769] COND FALSE !(1 == ~T1_E~0) [L774] COND FALSE !(1 == ~T2_E~0) [L779] COND FALSE !(1 == ~T3_E~0) [L784] COND FALSE !(1 == ~T4_E~0) [L789] COND FALSE !(1 == ~T5_E~0) [L794] COND FALSE !(1 == ~T6_E~0) [L799] COND FALSE !(1 == ~E_M~0) [L804] COND FALSE !(1 == ~E_1~0) [L809] COND FALSE !(1 == ~E_2~0) [L814] COND FALSE !(1 == ~E_3~0) [L819] COND FALSE !(1 == ~E_4~0) [L824] COND FALSE !(1 == ~E_5~0) [L829] COND FALSE !(1 == ~E_6~0) [L1055-L1092] COND FALSE !(false) [L1058] ~kernel_st~0 := 1; [L563] havoc ~tmp~0; [L14] int m_pc = 0; [L15] int t1_pc = 0; [L16] int t2_pc = 0; [L17] int t3_pc = 0; [L18] int t4_pc = 0; [L19] int t5_pc = 0; [L20] int t6_pc = 0; [L21] int m_st ; [L22] int t1_st ; [L23] int t2_st ; [L24] int t3_st ; [L25] int t4_st ; [L26] int t5_st ; [L27] int t6_st ; [L28] int m_i ; [L29] int t1_i ; [L30] int t2_i ; [L31] int t3_i ; [L32] int t4_i ; [L33] int t5_i ; [L34] int t6_i ; [L35] int M_E = 2; [L36] int T1_E = 2; [L37] int T2_E = 2; [L38] int T3_E = 2; [L39] int T4_E = 2; [L40] int T5_E = 2; [L41] int T6_E = 2; [L42] int E_M = 2; [L43] int E_1 = 2; [L44] int E_2 = 2; [L45] int E_3 = 2; [L46] int E_4 = 2; [L47] int E_5 = 2; [L48] int E_6 = 2; [L57] int token ; [L59] int local ; [L1100] int __retres1 ; [L1010] m_i = 1 [L1011] t1_i = 1 [L1012] t2_i = 1 [L1013] t3_i = 1 [L1014] t4_i = 1 [L1015] t5_i = 1 [L1016] t6_i = 1 [L1041] int kernel_st ; [L1042] int tmp ; [L1043] int tmp___0 ; [L1047] kernel_st = 0 [L477] COND TRUE m_i == 1 [L478] m_st = 0 [L482] COND TRUE t1_i == 1 [L483] t1_st = 0 [L487] COND TRUE t2_i == 1 [L488] t2_st = 0 [L492] COND TRUE t3_i == 1 [L493] t3_st = 0 [L497] COND TRUE t4_i == 1 [L498] t4_st = 0 [L502] COND TRUE t5_i == 1 [L503] t5_st = 0 [L507] COND TRUE t6_i == 1 [L508] t6_st = 0 [L686] COND FALSE !(M_E == 0) [L691] COND FALSE !(T1_E == 0) [L696] COND FALSE !(T2_E == 0) [L701] COND FALSE !(T3_E == 0) [L706] COND FALSE !(T4_E == 0) [L711] COND FALSE !(T5_E == 0) [L716] COND FALSE !(T6_E == 0) [L721] COND FALSE !(E_M == 0) [L726] COND FALSE !(E_1 == 0) [L731] COND FALSE !(E_2 == 0) [L736] COND FALSE !(E_3 == 0) [L741] COND FALSE !(E_4 == 0) [L746] COND FALSE !(E_5 == 0) [L751] COND FALSE !(E_6 == 0) [L839] int tmp ; [L840] int tmp___0 ; [L841] int tmp___1 ; [L842] int tmp___2 ; [L843] int tmp___3 ; [L844] int tmp___4 ; [L845] int tmp___5 ; [L333] int __retres1 ; [L336] COND FALSE !(m_pc == 1) [L346] __retres1 = 0 [L348] return (__retres1); [L849] tmp = is_master_triggered() [L851] COND FALSE !(\read(tmp)) [L352] int __retres1 ; [L355] COND FALSE !(t1_pc == 1) [L365] __retres1 = 0 [L367] return (__retres1); [L857] tmp___0 = is_transmit1_triggered() [L859] COND FALSE !(\read(tmp___0)) [L371] int __retres1 ; [L374] COND FALSE !(t2_pc == 1) [L384] __retres1 = 0 [L386] return (__retres1); [L865] tmp___1 = is_transmit2_triggered() [L867] COND FALSE !(\read(tmp___1)) [L390] int __retres1 ; [L393] COND FALSE !(t3_pc == 1) [L403] __retres1 = 0 [L405] return (__retres1); [L873] tmp___2 = is_transmit3_triggered() [L875] COND FALSE !(\read(tmp___2)) [L409] int __retres1 ; [L412] COND FALSE !(t4_pc == 1) [L422] __retres1 = 0 [L424] return (__retres1); [L881] tmp___3 = is_transmit4_triggered() [L883] COND FALSE !(\read(tmp___3)) [L428] int __retres1 ; [L431] COND FALSE !(t5_pc == 1) [L441] __retres1 = 0 [L443] return (__retres1); [L889] tmp___4 = is_transmit5_triggered() [L891] COND FALSE !(\read(tmp___4)) [L447] int __retres1 ; [L450] COND FALSE !(t6_pc == 1) [L460] __retres1 = 0 [L462] return (__retres1); [L897] tmp___5 = is_transmit6_triggered() [L899] COND FALSE !(\read(tmp___5)) [L764] COND FALSE !(M_E == 1) [L769] COND FALSE !(T1_E == 1) [L774] COND FALSE !(T2_E == 1) [L779] COND FALSE !(T3_E == 1) [L784] COND FALSE !(T4_E == 1) [L789] COND FALSE !(T5_E == 1) [L794] COND FALSE !(T6_E == 1) [L799] COND FALSE !(E_M == 1) [L804] COND FALSE !(E_1 == 1) [L809] COND FALSE !(E_2 == 1) [L814] COND FALSE !(E_3 == 1) [L819] COND FALSE !(E_4 == 1) [L824] COND FALSE !(E_5 == 1) [L829] COND FALSE !(E_6 == 1) [L1055] COND TRUE 1 [L1058] kernel_st = 1 [L563] int tmp ; ----- ----- class de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder.RCFGBacktranslator [?] assume !false; [?] havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~7;havoc exists_runnable_thread_~__retres1~7; [?] assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7 := 1; [?] exists_runnable_thread_#res := exists_runnable_thread_~__retres1~7; [?] eval_#t~ret2 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret2;havoc eval_#t~ret2; [?] assume 0 != eval_~tmp~0; [?] assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0;eval_~tmp_ndt_1~0 := eval_#t~nondet3;havoc eval_#t~nondet3; [?] assume !(0 != eval_~tmp_ndt_1~0); [?] assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0;eval_~tmp_ndt_2~0 := eval_#t~nondet4;havoc eval_#t~nondet4; [?] assume !(0 != eval_~tmp_ndt_2~0); [?] assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0;eval_~tmp_ndt_3~0 := eval_#t~nondet5;havoc eval_#t~nondet5; [?] assume !(0 != eval_~tmp_ndt_3~0); [?] assume 0 == ~t3_st~0;havoc eval_~tmp_ndt_4~0;eval_~tmp_ndt_4~0 := eval_#t~nondet6;havoc eval_#t~nondet6; [?] assume !(0 != eval_~tmp_ndt_4~0); [?] assume 0 == ~t4_st~0;havoc eval_~tmp_ndt_5~0;eval_~tmp_ndt_5~0 := eval_#t~nondet7;havoc eval_#t~nondet7; [?] assume !(0 != eval_~tmp_ndt_5~0); [?] assume 0 == ~t5_st~0;havoc eval_~tmp_ndt_6~0;eval_~tmp_ndt_6~0 := eval_#t~nondet8;havoc eval_#t~nondet8; [?] assume !(0 != eval_~tmp_ndt_6~0); [?] assume 0 == ~t6_st~0;havoc eval_~tmp_ndt_7~0;eval_~tmp_ndt_7~0 := eval_#t~nondet9;havoc eval_#t~nondet9; [?] assume !(0 != eval_~tmp_ndt_7~0); [L567-L675] assume !false; [L570] havoc exists_runnable_thread_#res; [L570] havoc exists_runnable_thread_~__retres1~7; [L517] havoc exists_runnable_thread_~__retres1~7; [L520-L555] assume 0 == ~m_st~0; [L521] exists_runnable_thread_~__retres1~7 := 1; [L558] exists_runnable_thread_#res := exists_runnable_thread_~__retres1~7; [L570] eval_#t~ret2 := exists_runnable_thread_#res; [L570] eval_~tmp~0 := eval_#t~ret2; [L570] havoc eval_#t~ret2; [L572-L576] assume 0 != eval_~tmp~0; [L577-L590] assume 0 == ~m_st~0; [L578] havoc eval_~tmp_ndt_1~0; [L579] eval_~tmp_ndt_1~0 := eval_#t~nondet3; [L579] havoc eval_#t~nondet3; [L580-L587] assume !(0 != eval_~tmp_ndt_1~0); [L591-L604] assume 0 == ~t1_st~0; [L592] havoc eval_~tmp_ndt_2~0; [L593] eval_~tmp_ndt_2~0 := eval_#t~nondet4; [L593] havoc eval_#t~nondet4; [L594-L601] assume !(0 != eval_~tmp_ndt_2~0); [L605-L618] assume 0 == ~t2_st~0; [L606] havoc eval_~tmp_ndt_3~0; [L607] eval_~tmp_ndt_3~0 := eval_#t~nondet5; [L607] havoc eval_#t~nondet5; [L608-L615] assume !(0 != eval_~tmp_ndt_3~0); [L619-L632] assume 0 == ~t3_st~0; [L620] havoc eval_~tmp_ndt_4~0; [L621] eval_~tmp_ndt_4~0 := eval_#t~nondet6; [L621] havoc eval_#t~nondet6; [L622-L629] assume !(0 != eval_~tmp_ndt_4~0); [L633-L646] assume 0 == ~t4_st~0; [L634] havoc eval_~tmp_ndt_5~0; [L635] eval_~tmp_ndt_5~0 := eval_#t~nondet7; [L635] havoc eval_#t~nondet7; [L636-L643] assume !(0 != eval_~tmp_ndt_5~0); [L647-L660] assume 0 == ~t5_st~0; [L648] havoc eval_~tmp_ndt_6~0; [L649] eval_~tmp_ndt_6~0 := eval_#t~nondet8; [L649] havoc eval_#t~nondet8; [L650-L657] assume !(0 != eval_~tmp_ndt_6~0); [L661-L674] assume 0 == ~t6_st~0; [L662] havoc eval_~tmp_ndt_7~0; [L663] eval_~tmp_ndt_7~0 := eval_#t~nondet9; [L663] havoc eval_#t~nondet9; [L664-L671] assume !(0 != eval_~tmp_ndt_7~0); ----- ----- class de.uni_freiburg.informatik.ultimate.boogie.preprocessor.BoogiePreprocessorBacktranslator [L567-L675] assume !false; [L570] havoc exists_runnable_thread_#res; [L570] havoc exists_runnable_thread_~__retres1~7; [L517] havoc exists_runnable_thread_~__retres1~7; [L520-L555] assume 0 == ~m_st~0; [L521] exists_runnable_thread_~__retres1~7 := 1; [L558] exists_runnable_thread_#res := exists_runnable_thread_~__retres1~7; [L570] eval_#t~ret2 := exists_runnable_thread_#res; [L570] eval_~tmp~0 := eval_#t~ret2; [L570] havoc eval_#t~ret2; [L572-L576] assume 0 != eval_~tmp~0; [L577-L590] assume 0 == ~m_st~0; [L578] havoc eval_~tmp_ndt_1~0; [L579] eval_~tmp_ndt_1~0 := eval_#t~nondet3; [L579] havoc eval_#t~nondet3; [L580-L587] assume !(0 != eval_~tmp_ndt_1~0); [L591-L604] assume 0 == ~t1_st~0; [L592] havoc eval_~tmp_ndt_2~0; [L593] eval_~tmp_ndt_2~0 := eval_#t~nondet4; [L593] havoc eval_#t~nondet4; [L594-L601] assume !(0 != eval_~tmp_ndt_2~0); [L605-L618] assume 0 == ~t2_st~0; [L606] havoc eval_~tmp_ndt_3~0; [L607] eval_~tmp_ndt_3~0 := eval_#t~nondet5; [L607] havoc eval_#t~nondet5; [L608-L615] assume !(0 != eval_~tmp_ndt_3~0); [L619-L632] assume 0 == ~t3_st~0; [L620] havoc eval_~tmp_ndt_4~0; [L621] eval_~tmp_ndt_4~0 := eval_#t~nondet6; [L621] havoc eval_#t~nondet6; [L622-L629] assume !(0 != eval_~tmp_ndt_4~0); [L633-L646] assume 0 == ~t4_st~0; [L634] havoc eval_~tmp_ndt_5~0; [L635] eval_~tmp_ndt_5~0 := eval_#t~nondet7; [L635] havoc eval_#t~nondet7; [L636-L643] assume !(0 != eval_~tmp_ndt_5~0); [L647-L660] assume 0 == ~t5_st~0; [L648] havoc eval_~tmp_ndt_6~0; [L649] eval_~tmp_ndt_6~0 := eval_#t~nondet8; [L649] havoc eval_#t~nondet8; [L650-L657] assume !(0 != eval_~tmp_ndt_6~0); [L661-L674] assume 0 == ~t6_st~0; [L662] havoc eval_~tmp_ndt_7~0; [L663] eval_~tmp_ndt_7~0 := eval_#t~nondet9; [L663] havoc eval_#t~nondet9; [L664-L671] assume !(0 != eval_~tmp_ndt_7~0); [L567-L675] COND FALSE !(false) [L570] havoc exists_runnable_thread_#res; [L570] havoc exists_runnable_thread_~__retres1~7; [L517] havoc exists_runnable_thread_~__retres1~7; [L520] COND TRUE 0 == ~m_st~0 [L521] exists_runnable_thread_~__retres1~7 := 1; [L558] exists_runnable_thread_#res := exists_runnable_thread_~__retres1~7; [L570] eval_#t~ret2 := exists_runnable_thread_#res; [L570] eval_~tmp~0 := eval_#t~ret2; [L570] havoc eval_#t~ret2; [L572-L576] COND TRUE 0 != eval_~tmp~0 [L577] COND TRUE 0 == ~m_st~0 [L578] havoc eval_~tmp_ndt_1~0; [L579] eval_~tmp_ndt_1~0 := eval_#t~nondet3; [L579] havoc eval_#t~nondet3; [L580-L587] COND FALSE !(0 != eval_~tmp_ndt_1~0) [L591] COND TRUE 0 == ~t1_st~0 [L592] havoc eval_~tmp_ndt_2~0; [L593] eval_~tmp_ndt_2~0 := eval_#t~nondet4; [L593] havoc eval_#t~nondet4; [L594-L601] COND FALSE !(0 != eval_~tmp_ndt_2~0) [L605] COND TRUE 0 == ~t2_st~0 [L606] havoc eval_~tmp_ndt_3~0; [L607] eval_~tmp_ndt_3~0 := eval_#t~nondet5; [L607] havoc eval_#t~nondet5; [L608-L615] COND FALSE !(0 != eval_~tmp_ndt_3~0) [L619] COND TRUE 0 == ~t3_st~0 [L620] havoc eval_~tmp_ndt_4~0; [L621] eval_~tmp_ndt_4~0 := eval_#t~nondet6; [L621] havoc eval_#t~nondet6; [L622-L629] COND FALSE !(0 != eval_~tmp_ndt_4~0) [L633] COND TRUE 0 == ~t4_st~0 [L634] havoc eval_~tmp_ndt_5~0; [L635] eval_~tmp_ndt_5~0 := eval_#t~nondet7; [L635] havoc eval_#t~nondet7; [L636-L643] COND FALSE !(0 != eval_~tmp_ndt_5~0) [L647] COND TRUE 0 == ~t5_st~0 [L648] havoc eval_~tmp_ndt_6~0; [L649] eval_~tmp_ndt_6~0 := eval_#t~nondet8; [L649] havoc eval_#t~nondet8; [L650-L657] COND FALSE !(0 != eval_~tmp_ndt_6~0) [L661] COND TRUE 0 == ~t6_st~0 [L662] havoc eval_~tmp_ndt_7~0; [L663] eval_~tmp_ndt_7~0 := eval_#t~nondet9; [L663] havoc eval_#t~nondet9; [L664-L671] COND FALSE !(0 != eval_~tmp_ndt_7~0) ----- ----- class de.uni_freiburg.informatik.ultimate.boogie.procedureinliner.backtranslation.InlinerBacktranslator [L567-L675] COND FALSE !(false) [L570] havoc exists_runnable_thread_#res; [L570] havoc exists_runnable_thread_~__retres1~7; [L517] havoc exists_runnable_thread_~__retres1~7; [L520] COND TRUE 0 == ~m_st~0 [L521] exists_runnable_thread_~__retres1~7 := 1; [L558] exists_runnable_thread_#res := exists_runnable_thread_~__retres1~7; [L570] eval_#t~ret2 := exists_runnable_thread_#res; [L570] eval_~tmp~0 := eval_#t~ret2; [L570] havoc eval_#t~ret2; [L572-L576] COND TRUE 0 != eval_~tmp~0 [L577] COND TRUE 0 == ~m_st~0 [L578] havoc eval_~tmp_ndt_1~0; [L579] eval_~tmp_ndt_1~0 := eval_#t~nondet3; [L579] havoc eval_#t~nondet3; [L580-L587] COND FALSE !(0 != eval_~tmp_ndt_1~0) [L591] COND TRUE 0 == ~t1_st~0 [L592] havoc eval_~tmp_ndt_2~0; [L593] eval_~tmp_ndt_2~0 := eval_#t~nondet4; [L593] havoc eval_#t~nondet4; [L594-L601] COND FALSE !(0 != eval_~tmp_ndt_2~0) [L605] COND TRUE 0 == ~t2_st~0 [L606] havoc eval_~tmp_ndt_3~0; [L607] eval_~tmp_ndt_3~0 := eval_#t~nondet5; [L607] havoc eval_#t~nondet5; [L608-L615] COND FALSE !(0 != eval_~tmp_ndt_3~0) [L619] COND TRUE 0 == ~t3_st~0 [L620] havoc eval_~tmp_ndt_4~0; [L621] eval_~tmp_ndt_4~0 := eval_#t~nondet6; [L621] havoc eval_#t~nondet6; [L622-L629] COND FALSE !(0 != eval_~tmp_ndt_4~0) [L633] COND TRUE 0 == ~t4_st~0 [L634] havoc eval_~tmp_ndt_5~0; [L635] eval_~tmp_ndt_5~0 := eval_#t~nondet7; [L635] havoc eval_#t~nondet7; [L636-L643] COND FALSE !(0 != eval_~tmp_ndt_5~0) [L647] COND TRUE 0 == ~t5_st~0 [L648] havoc eval_~tmp_ndt_6~0; [L649] eval_~tmp_ndt_6~0 := eval_#t~nondet8; [L649] havoc eval_#t~nondet8; [L650-L657] COND FALSE !(0 != eval_~tmp_ndt_6~0) [L661] COND TRUE 0 == ~t6_st~0 [L662] havoc eval_~tmp_ndt_7~0; [L663] eval_~tmp_ndt_7~0 := eval_#t~nondet9; [L663] havoc eval_#t~nondet9; [L664-L671] COND FALSE !(0 != eval_~tmp_ndt_7~0) [L567-L675] COND FALSE !(false) [L517] havoc ~__retres1~7; [L520] COND TRUE 0 == ~m_st~0 [L521] ~__retres1~7 := 1; [L558] #res := ~__retres1~7; [L570] ~tmp~0 := #t~ret2; [L570] havoc #t~ret2; [L572-L576] COND TRUE 0 != ~tmp~0 [L577] COND TRUE 0 == ~m_st~0 [L578] havoc ~tmp_ndt_1~0; [L579] ~tmp_ndt_1~0 := #t~nondet3; [L579] havoc #t~nondet3; [L580-L587] COND FALSE !(0 != ~tmp_ndt_1~0) [L591] COND TRUE 0 == ~t1_st~0 [L592] havoc ~tmp_ndt_2~0; [L593] ~tmp_ndt_2~0 := #t~nondet4; [L593] havoc #t~nondet4; [L594-L601] COND FALSE !(0 != ~tmp_ndt_2~0) [L605] COND TRUE 0 == ~t2_st~0 [L606] havoc ~tmp_ndt_3~0; [L607] ~tmp_ndt_3~0 := #t~nondet5; [L607] havoc #t~nondet5; [L608-L615] COND FALSE !(0 != ~tmp_ndt_3~0) [L619] COND TRUE 0 == ~t3_st~0 [L620] havoc ~tmp_ndt_4~0; [L621] ~tmp_ndt_4~0 := #t~nondet6; [L621] havoc #t~nondet6; [L622-L629] COND FALSE !(0 != ~tmp_ndt_4~0) [L633] COND TRUE 0 == ~t4_st~0 [L634] havoc ~tmp_ndt_5~0; [L635] ~tmp_ndt_5~0 := #t~nondet7; [L635] havoc #t~nondet7; [L636-L643] COND FALSE !(0 != ~tmp_ndt_5~0) [L647] COND TRUE 0 == ~t5_st~0 [L648] havoc ~tmp_ndt_6~0; [L649] ~tmp_ndt_6~0 := #t~nondet8; [L649] havoc #t~nondet8; [L650-L657] COND FALSE !(0 != ~tmp_ndt_6~0) [L661] COND TRUE 0 == ~t6_st~0 [L662] havoc ~tmp_ndt_7~0; [L663] ~tmp_ndt_7~0 := #t~nondet9; [L663] havoc #t~nondet9; [L664-L671] COND FALSE !(0 != ~tmp_ndt_7~0) ----- ----- class de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.CACSL2BoogieBacktranslator [L567-L675] COND FALSE !(false) [L517] havoc ~__retres1~7; [L520] COND TRUE 0 == ~m_st~0 [L521] ~__retres1~7 := 1; [L558] #res := ~__retres1~7; [L570] ~tmp~0 := #t~ret2; [L570] havoc #t~ret2; [L572-L576] COND TRUE 0 != ~tmp~0 [L577] COND TRUE 0 == ~m_st~0 [L578] havoc ~tmp_ndt_1~0; [L579] ~tmp_ndt_1~0 := #t~nondet3; [L579] havoc #t~nondet3; [L580-L587] COND FALSE !(0 != ~tmp_ndt_1~0) [L591] COND TRUE 0 == ~t1_st~0 [L592] havoc ~tmp_ndt_2~0; [L593] ~tmp_ndt_2~0 := #t~nondet4; [L593] havoc #t~nondet4; [L594-L601] COND FALSE !(0 != ~tmp_ndt_2~0) [L605] COND TRUE 0 == ~t2_st~0 [L606] havoc ~tmp_ndt_3~0; [L607] ~tmp_ndt_3~0 := #t~nondet5; [L607] havoc #t~nondet5; [L608-L615] COND FALSE !(0 != ~tmp_ndt_3~0) [L619] COND TRUE 0 == ~t3_st~0 [L620] havoc ~tmp_ndt_4~0; [L621] ~tmp_ndt_4~0 := #t~nondet6; [L621] havoc #t~nondet6; [L622-L629] COND FALSE !(0 != ~tmp_ndt_4~0) [L633] COND TRUE 0 == ~t4_st~0 [L634] havoc ~tmp_ndt_5~0; [L635] ~tmp_ndt_5~0 := #t~nondet7; [L635] havoc #t~nondet7; [L636-L643] COND FALSE !(0 != ~tmp_ndt_5~0) [L647] COND TRUE 0 == ~t5_st~0 [L648] havoc ~tmp_ndt_6~0; [L649] ~tmp_ndt_6~0 := #t~nondet8; [L649] havoc #t~nondet8; [L650-L657] COND FALSE !(0 != ~tmp_ndt_6~0) [L661] COND TRUE 0 == ~t6_st~0 [L662] havoc ~tmp_ndt_7~0; [L663] ~tmp_ndt_7~0 := #t~nondet9; [L663] havoc #t~nondet9; [L664-L671] COND FALSE !(0 != ~tmp_ndt_7~0) [L567] COND TRUE 1 [L517] int __retres1 ; [L520] COND TRUE m_st == 0 [L521] __retres1 = 1 [L558] return (__retres1); [L570] tmp = exists_runnable_thread() [L572] COND TRUE \read(tmp) [L577] COND TRUE m_st == 0 [L578] int tmp_ndt_1; [L579] tmp_ndt_1 = __VERIFIER_nondet_int() [L580] COND FALSE !(\read(tmp_ndt_1)) [L591] COND TRUE t1_st == 0 [L592] int tmp_ndt_2; [L593] tmp_ndt_2 = __VERIFIER_nondet_int() [L594] COND FALSE !(\read(tmp_ndt_2)) [L605] COND TRUE t2_st == 0 [L606] int tmp_ndt_3; [L607] tmp_ndt_3 = __VERIFIER_nondet_int() [L608] COND FALSE !(\read(tmp_ndt_3)) [L619] COND TRUE t3_st == 0 [L620] int tmp_ndt_4; [L621] tmp_ndt_4 = __VERIFIER_nondet_int() [L622] COND FALSE !(\read(tmp_ndt_4)) [L633] COND TRUE t4_st == 0 [L634] int tmp_ndt_5; [L635] tmp_ndt_5 = __VERIFIER_nondet_int() [L636] COND FALSE !(\read(tmp_ndt_5)) [L647] COND TRUE t5_st == 0 [L648] int tmp_ndt_6; [L649] tmp_ndt_6 = __VERIFIER_nondet_int() [L650] COND FALSE !(\read(tmp_ndt_6)) [L661] COND TRUE t6_st == 0 [L662] int tmp_ndt_7; [L663] tmp_ndt_7 = __VERIFIER_nondet_int() [L664] COND FALSE !(\read(tmp_ndt_7)) ----- [2018-11-23 01:27:59,886 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer CFG 23.11 01:27:59 BoogieIcfgContainer [2018-11-23 01:27:59,886 INFO L132 PluginConnector]: ------------------------ END BuchiAutomizer---------------------------- [2018-11-23 01:27:59,887 INFO L113 PluginConnector]: ------------------------Witness Printer---------------------------- [2018-11-23 01:27:59,887 INFO L271 PluginConnector]: Initializing Witness Printer... [2018-11-23 01:27:59,887 INFO L276 PluginConnector]: Witness Printer initialized [2018-11-23 01:27:59,887 INFO L185 PluginConnector]: Executing the observer RCFGCatcher from plugin Witness Printer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 23.11 01:26:45" (3/4) ... [2018-11-23 01:27:59,890 INFO L141 WitnessPrinter]: Generating witness for non-termination counterexample ----- class de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder.RCFGBacktranslator [?] ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0; [?] havoc main_#res;havoc main_~__retres1~8;havoc main_~__retres1~8;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; [?] havoc start_simulation_#t~ret18, start_simulation_#t~ret19, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; [?] assume 1 == ~m_i~0;~m_st~0 := 0; [?] assume 1 == ~t1_i~0;~t1_st~0 := 0; [?] assume 1 == ~t2_i~0;~t2_st~0 := 0; [?] assume 1 == ~t3_i~0;~t3_st~0 := 0; [?] assume 1 == ~t4_i~0;~t4_st~0 := 0; [?] assume 1 == ~t5_i~0;~t5_st~0 := 0; [?] assume 1 == ~t6_i~0;~t6_st~0 := 0; [?] assume !(0 == ~M_E~0); [?] assume !(0 == ~T1_E~0); [?] assume !(0 == ~T2_E~0); [?] assume !(0 == ~T3_E~0); [?] assume !(0 == ~T4_E~0); [?] assume !(0 == ~T5_E~0); [?] assume !(0 == ~T6_E~0); [?] assume !(0 == ~E_M~0); [?] assume !(0 == ~E_1~0); [?] assume !(0 == ~E_2~0); [?] assume !(0 == ~E_3~0); [?] assume !(0 == ~E_4~0); [?] assume !(0 == ~E_5~0); [?] assume !(0 == ~E_6~0); [?] havoc activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; [?] assume !(1 == ~m_pc~0); [?] is_master_triggered_~__retres1~0 := 0; [?] is_master_triggered_#res := is_master_triggered_~__retres1~0; [?] activate_threads_#t~ret10 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; [?] assume !(0 != activate_threads_~tmp~1); [?] havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; [?] assume !(1 == ~t1_pc~0); [?] is_transmit1_triggered_~__retres1~1 := 0; [?] is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; [?] activate_threads_#t~ret11 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; [?] assume !(0 != activate_threads_~tmp___0~0); [?] havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; [?] assume !(1 == ~t2_pc~0); [?] is_transmit2_triggered_~__retres1~2 := 0; [?] is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; [?] activate_threads_#t~ret12 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; [?] assume !(0 != activate_threads_~tmp___1~0); [?] havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; [?] assume !(1 == ~t3_pc~0); [?] is_transmit3_triggered_~__retres1~3 := 0; [?] is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; [?] activate_threads_#t~ret13 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; [?] assume !(0 != activate_threads_~tmp___2~0); [?] havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; [?] assume !(1 == ~t4_pc~0); [?] is_transmit4_triggered_~__retres1~4 := 0; [?] is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; [?] activate_threads_#t~ret14 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; [?] assume !(0 != activate_threads_~tmp___3~0); [?] havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; [?] assume !(1 == ~t5_pc~0); [?] is_transmit5_triggered_~__retres1~5 := 0; [?] is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; [?] activate_threads_#t~ret15 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; [?] assume !(0 != activate_threads_~tmp___4~0); [?] havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; [?] assume !(1 == ~t6_pc~0); [?] is_transmit6_triggered_~__retres1~6 := 0; [?] is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; [?] activate_threads_#t~ret16 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; [?] assume !(0 != activate_threads_~tmp___5~0); [?] assume !(1 == ~M_E~0); [?] assume !(1 == ~T1_E~0); [?] assume !(1 == ~T2_E~0); [?] assume !(1 == ~T3_E~0); [?] assume !(1 == ~T4_E~0); [?] assume !(1 == ~T5_E~0); [?] assume !(1 == ~T6_E~0); [?] assume !(1 == ~E_M~0); [?] assume !(1 == ~E_1~0); [?] assume !(1 == ~E_2~0); [?] assume !(1 == ~E_3~0); [?] assume !(1 == ~E_4~0); [?] assume !(1 == ~E_5~0); [?] assume !(1 == ~E_6~0); [?] assume !false; [?] start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret2, eval_#t~nondet3, eval_~tmp_ndt_1~0, eval_#t~nondet4, eval_~tmp_ndt_2~0, eval_#t~nondet5, eval_~tmp_ndt_3~0, eval_#t~nondet6, eval_~tmp_ndt_4~0, eval_#t~nondet7, eval_~tmp_ndt_5~0, eval_#t~nondet8, eval_~tmp_ndt_6~0, eval_#t~nondet9, eval_~tmp_ndt_7~0, eval_~tmp~0;havoc eval_~tmp~0; [L14] ~m_pc~0 := 0; [L15] ~t1_pc~0 := 0; [L16] ~t2_pc~0 := 0; [L17] ~t3_pc~0 := 0; [L18] ~t4_pc~0 := 0; [L19] ~t5_pc~0 := 0; [L20] ~t6_pc~0 := 0; [L21] ~m_st~0 := 0; [L22] ~t1_st~0 := 0; [L23] ~t2_st~0 := 0; [L24] ~t3_st~0 := 0; [L25] ~t4_st~0 := 0; [L26] ~t5_st~0 := 0; [L27] ~t6_st~0 := 0; [L28] ~m_i~0 := 0; [L29] ~t1_i~0 := 0; [L30] ~t2_i~0 := 0; [L31] ~t3_i~0 := 0; [L32] ~t4_i~0 := 0; [L33] ~t5_i~0 := 0; [L34] ~t6_i~0 := 0; [L35] ~M_E~0 := 2; [L36] ~T1_E~0 := 2; [L37] ~T2_E~0 := 2; [L38] ~T3_E~0 := 2; [L39] ~T4_E~0 := 2; [L40] ~T5_E~0 := 2; [L41] ~T6_E~0 := 2; [L42] ~E_M~0 := 2; [L43] ~E_1~0 := 2; [L44] ~E_2~0 := 2; [L45] ~E_3~0 := 2; [L46] ~E_4~0 := 2; [L47] ~E_5~0 := 2; [L48] ~E_6~0 := 2; [L57] ~token~0 := 0; [L59] ~local~0 := 0; [?] havoc main_#res; [?] havoc main_~__retres1~8; [L1100] havoc main_~__retres1~8; [L1010] ~m_i~0 := 1; [L1011] ~t1_i~0 := 1; [L1012] ~t2_i~0 := 1; [L1013] ~t3_i~0 := 1; [L1014] ~t4_i~0 := 1; [L1015] ~t5_i~0 := 1; [L1016] ~t6_i~0 := 1; [L1105] havoc start_simulation_#t~ret18, start_simulation_#t~ret19, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1; [L1041] havoc start_simulation_~kernel_st~0; [L1042] havoc start_simulation_~tmp~3; [L1043] havoc start_simulation_~tmp___0~1; [L1047] start_simulation_~kernel_st~0 := 0; [L477-L481] assume 1 == ~m_i~0; [L478] ~m_st~0 := 0; [L482-L486] assume 1 == ~t1_i~0; [L483] ~t1_st~0 := 0; [L487-L491] assume 1 == ~t2_i~0; [L488] ~t2_st~0 := 0; [L492-L496] assume 1 == ~t3_i~0; [L493] ~t3_st~0 := 0; [L497-L501] assume 1 == ~t4_i~0; [L498] ~t4_st~0 := 0; [L502-L506] assume 1 == ~t5_i~0; [L503] ~t5_st~0 := 0; [L507-L511] assume 1 == ~t6_i~0; [L508] ~t6_st~0 := 0; [L686-L690] assume !(0 == ~M_E~0); [L691-L695] assume !(0 == ~T1_E~0); [L696-L700] assume !(0 == ~T2_E~0); [L701-L705] assume !(0 == ~T3_E~0); [L706-L710] assume !(0 == ~T4_E~0); [L711-L715] assume !(0 == ~T5_E~0); [L716-L720] assume !(0 == ~T6_E~0); [L721-L725] assume !(0 == ~E_M~0); [L726-L730] assume !(0 == ~E_1~0); [L731-L735] assume !(0 == ~E_2~0); [L736-L740] assume !(0 == ~E_3~0); [L741-L745] assume !(0 == ~E_4~0); [L746-L750] assume !(0 == ~E_5~0); [L751-L755] assume !(0 == ~E_6~0); [L1051] havoc activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0; [L839] havoc activate_threads_~tmp~1; [L840] havoc activate_threads_~tmp___0~0; [L841] havoc activate_threads_~tmp___1~0; [L842] havoc activate_threads_~tmp___2~0; [L843] havoc activate_threads_~tmp___3~0; [L844] havoc activate_threads_~tmp___4~0; [L845] havoc activate_threads_~tmp___5~0; [L849] havoc is_master_triggered_#res; [L849] havoc is_master_triggered_~__retres1~0; [L333] havoc is_master_triggered_~__retres1~0; [L336-L345] assume !(1 == ~m_pc~0); [L346] is_master_triggered_~__retres1~0 := 0; [L348] is_master_triggered_#res := is_master_triggered_~__retres1~0; [L849] activate_threads_#t~ret10 := is_master_triggered_#res; [L849] activate_threads_~tmp~1 := activate_threads_#t~ret10; [L849] havoc activate_threads_#t~ret10; [L851-L855] assume !(0 != activate_threads_~tmp~1); [L857] havoc is_transmit1_triggered_#res; [L857] havoc is_transmit1_triggered_~__retres1~1; [L352] havoc is_transmit1_triggered_~__retres1~1; [L355-L364] assume !(1 == ~t1_pc~0); [L365] is_transmit1_triggered_~__retres1~1 := 0; [L367] is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; [L857] activate_threads_#t~ret11 := is_transmit1_triggered_#res; [L857] activate_threads_~tmp___0~0 := activate_threads_#t~ret11; [L857] havoc activate_threads_#t~ret11; [L859-L863] assume !(0 != activate_threads_~tmp___0~0); [L865] havoc is_transmit2_triggered_#res; [L865] havoc is_transmit2_triggered_~__retres1~2; [L371] havoc is_transmit2_triggered_~__retres1~2; [L374-L383] assume !(1 == ~t2_pc~0); [L384] is_transmit2_triggered_~__retres1~2 := 0; [L386] is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; [L865] activate_threads_#t~ret12 := is_transmit2_triggered_#res; [L865] activate_threads_~tmp___1~0 := activate_threads_#t~ret12; [L865] havoc activate_threads_#t~ret12; [L867-L871] assume !(0 != activate_threads_~tmp___1~0); [L873] havoc is_transmit3_triggered_#res; [L873] havoc is_transmit3_triggered_~__retres1~3; [L390] havoc is_transmit3_triggered_~__retres1~3; [L393-L402] assume !(1 == ~t3_pc~0); [L403] is_transmit3_triggered_~__retres1~3 := 0; [L405] is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; [L873] activate_threads_#t~ret13 := is_transmit3_triggered_#res; [L873] activate_threads_~tmp___2~0 := activate_threads_#t~ret13; [L873] havoc activate_threads_#t~ret13; [L875-L879] assume !(0 != activate_threads_~tmp___2~0); [L881] havoc is_transmit4_triggered_#res; [L881] havoc is_transmit4_triggered_~__retres1~4; [L409] havoc is_transmit4_triggered_~__retres1~4; [L412-L421] assume !(1 == ~t4_pc~0); [L422] is_transmit4_triggered_~__retres1~4 := 0; [L424] is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; [L881] activate_threads_#t~ret14 := is_transmit4_triggered_#res; [L881] activate_threads_~tmp___3~0 := activate_threads_#t~ret14; [L881] havoc activate_threads_#t~ret14; [L883-L887] assume !(0 != activate_threads_~tmp___3~0); [L889] havoc is_transmit5_triggered_#res; [L889] havoc is_transmit5_triggered_~__retres1~5; [L428] havoc is_transmit5_triggered_~__retres1~5; [L431-L440] assume !(1 == ~t5_pc~0); [L441] is_transmit5_triggered_~__retres1~5 := 0; [L443] is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; [L889] activate_threads_#t~ret15 := is_transmit5_triggered_#res; [L889] activate_threads_~tmp___4~0 := activate_threads_#t~ret15; [L889] havoc activate_threads_#t~ret15; [L891-L895] assume !(0 != activate_threads_~tmp___4~0); [L897] havoc is_transmit6_triggered_#res; [L897] havoc is_transmit6_triggered_~__retres1~6; [L447] havoc is_transmit6_triggered_~__retres1~6; [L450-L459] assume !(1 == ~t6_pc~0); [L460] is_transmit6_triggered_~__retres1~6 := 0; [L462] is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; [L897] activate_threads_#t~ret16 := is_transmit6_triggered_#res; [L897] activate_threads_~tmp___5~0 := activate_threads_#t~ret16; [L897] havoc activate_threads_#t~ret16; [L899-L903] assume !(0 != activate_threads_~tmp___5~0); [L764-L768] assume !(1 == ~M_E~0); [L769-L773] assume !(1 == ~T1_E~0); [L774-L778] assume !(1 == ~T2_E~0); [L779-L783] assume !(1 == ~T3_E~0); [L784-L788] assume !(1 == ~T4_E~0); [L789-L793] assume !(1 == ~T5_E~0); [L794-L798] assume !(1 == ~T6_E~0); [L799-L803] assume !(1 == ~E_M~0); [L804-L808] assume !(1 == ~E_1~0); [L809-L813] assume !(1 == ~E_2~0); [L814-L818] assume !(1 == ~E_3~0); [L819-L823] assume !(1 == ~E_4~0); [L824-L828] assume !(1 == ~E_5~0); [L829-L833] assume !(1 == ~E_6~0); [L1055-L1092] assume !false; [L1058] start_simulation_~kernel_st~0 := 1; [L1059] havoc eval_#t~ret2, eval_#t~nondet3, eval_~tmp_ndt_1~0, eval_#t~nondet4, eval_~tmp_ndt_2~0, eval_#t~nondet5, eval_~tmp_ndt_3~0, eval_#t~nondet6, eval_~tmp_ndt_4~0, eval_#t~nondet7, eval_~tmp_ndt_5~0, eval_#t~nondet8, eval_~tmp_ndt_6~0, eval_#t~nondet9, eval_~tmp_ndt_7~0, eval_~tmp~0; [L563] havoc eval_~tmp~0; ----- ----- class de.uni_freiburg.informatik.ultimate.boogie.preprocessor.BoogiePreprocessorBacktranslator [L14] ~m_pc~0 := 0; [L15] ~t1_pc~0 := 0; [L16] ~t2_pc~0 := 0; [L17] ~t3_pc~0 := 0; [L18] ~t4_pc~0 := 0; [L19] ~t5_pc~0 := 0; [L20] ~t6_pc~0 := 0; [L21] ~m_st~0 := 0; [L22] ~t1_st~0 := 0; [L23] ~t2_st~0 := 0; [L24] ~t3_st~0 := 0; [L25] ~t4_st~0 := 0; [L26] ~t5_st~0 := 0; [L27] ~t6_st~0 := 0; [L28] ~m_i~0 := 0; [L29] ~t1_i~0 := 0; [L30] ~t2_i~0 := 0; [L31] ~t3_i~0 := 0; [L32] ~t4_i~0 := 0; [L33] ~t5_i~0 := 0; [L34] ~t6_i~0 := 0; [L35] ~M_E~0 := 2; [L36] ~T1_E~0 := 2; [L37] ~T2_E~0 := 2; [L38] ~T3_E~0 := 2; [L39] ~T4_E~0 := 2; [L40] ~T5_E~0 := 2; [L41] ~T6_E~0 := 2; [L42] ~E_M~0 := 2; [L43] ~E_1~0 := 2; [L44] ~E_2~0 := 2; [L45] ~E_3~0 := 2; [L46] ~E_4~0 := 2; [L47] ~E_5~0 := 2; [L48] ~E_6~0 := 2; [L57] ~token~0 := 0; [L59] ~local~0 := 0; [?] havoc main_#res; [?] havoc main_~__retres1~8; [L1100] havoc main_~__retres1~8; [L1010] ~m_i~0 := 1; [L1011] ~t1_i~0 := 1; [L1012] ~t2_i~0 := 1; [L1013] ~t3_i~0 := 1; [L1014] ~t4_i~0 := 1; [L1015] ~t5_i~0 := 1; [L1016] ~t6_i~0 := 1; [L1105] havoc start_simulation_#t~ret18, start_simulation_#t~ret19, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1; [L1041] havoc start_simulation_~kernel_st~0; [L1042] havoc start_simulation_~tmp~3; [L1043] havoc start_simulation_~tmp___0~1; [L1047] start_simulation_~kernel_st~0 := 0; [L477-L481] assume 1 == ~m_i~0; [L478] ~m_st~0 := 0; [L482-L486] assume 1 == ~t1_i~0; [L483] ~t1_st~0 := 0; [L487-L491] assume 1 == ~t2_i~0; [L488] ~t2_st~0 := 0; [L492-L496] assume 1 == ~t3_i~0; [L493] ~t3_st~0 := 0; [L497-L501] assume 1 == ~t4_i~0; [L498] ~t4_st~0 := 0; [L502-L506] assume 1 == ~t5_i~0; [L503] ~t5_st~0 := 0; [L507-L511] assume 1 == ~t6_i~0; [L508] ~t6_st~0 := 0; [L686-L690] assume !(0 == ~M_E~0); [L691-L695] assume !(0 == ~T1_E~0); [L696-L700] assume !(0 == ~T2_E~0); [L701-L705] assume !(0 == ~T3_E~0); [L706-L710] assume !(0 == ~T4_E~0); [L711-L715] assume !(0 == ~T5_E~0); [L716-L720] assume !(0 == ~T6_E~0); [L721-L725] assume !(0 == ~E_M~0); [L726-L730] assume !(0 == ~E_1~0); [L731-L735] assume !(0 == ~E_2~0); [L736-L740] assume !(0 == ~E_3~0); [L741-L745] assume !(0 == ~E_4~0); [L746-L750] assume !(0 == ~E_5~0); [L751-L755] assume !(0 == ~E_6~0); [L1051] havoc activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0; [L839] havoc activate_threads_~tmp~1; [L840] havoc activate_threads_~tmp___0~0; [L841] havoc activate_threads_~tmp___1~0; [L842] havoc activate_threads_~tmp___2~0; [L843] havoc activate_threads_~tmp___3~0; [L844] havoc activate_threads_~tmp___4~0; [L845] havoc activate_threads_~tmp___5~0; [L849] havoc is_master_triggered_#res; [L849] havoc is_master_triggered_~__retres1~0; [L333] havoc is_master_triggered_~__retres1~0; [L336-L345] assume !(1 == ~m_pc~0); [L346] is_master_triggered_~__retres1~0 := 0; [L348] is_master_triggered_#res := is_master_triggered_~__retres1~0; [L849] activate_threads_#t~ret10 := is_master_triggered_#res; [L849] activate_threads_~tmp~1 := activate_threads_#t~ret10; [L849] havoc activate_threads_#t~ret10; [L851-L855] assume !(0 != activate_threads_~tmp~1); [L857] havoc is_transmit1_triggered_#res; [L857] havoc is_transmit1_triggered_~__retres1~1; [L352] havoc is_transmit1_triggered_~__retres1~1; [L355-L364] assume !(1 == ~t1_pc~0); [L365] is_transmit1_triggered_~__retres1~1 := 0; [L367] is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; [L857] activate_threads_#t~ret11 := is_transmit1_triggered_#res; [L857] activate_threads_~tmp___0~0 := activate_threads_#t~ret11; [L857] havoc activate_threads_#t~ret11; [L859-L863] assume !(0 != activate_threads_~tmp___0~0); [L865] havoc is_transmit2_triggered_#res; [L865] havoc is_transmit2_triggered_~__retres1~2; [L371] havoc is_transmit2_triggered_~__retres1~2; [L374-L383] assume !(1 == ~t2_pc~0); [L384] is_transmit2_triggered_~__retres1~2 := 0; [L386] is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; [L865] activate_threads_#t~ret12 := is_transmit2_triggered_#res; [L865] activate_threads_~tmp___1~0 := activate_threads_#t~ret12; [L865] havoc activate_threads_#t~ret12; [L867-L871] assume !(0 != activate_threads_~tmp___1~0); [L873] havoc is_transmit3_triggered_#res; [L873] havoc is_transmit3_triggered_~__retres1~3; [L390] havoc is_transmit3_triggered_~__retres1~3; [L393-L402] assume !(1 == ~t3_pc~0); [L403] is_transmit3_triggered_~__retres1~3 := 0; [L405] is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; [L873] activate_threads_#t~ret13 := is_transmit3_triggered_#res; [L873] activate_threads_~tmp___2~0 := activate_threads_#t~ret13; [L873] havoc activate_threads_#t~ret13; [L875-L879] assume !(0 != activate_threads_~tmp___2~0); [L881] havoc is_transmit4_triggered_#res; [L881] havoc is_transmit4_triggered_~__retres1~4; [L409] havoc is_transmit4_triggered_~__retres1~4; [L412-L421] assume !(1 == ~t4_pc~0); [L422] is_transmit4_triggered_~__retres1~4 := 0; [L424] is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; [L881] activate_threads_#t~ret14 := is_transmit4_triggered_#res; [L881] activate_threads_~tmp___3~0 := activate_threads_#t~ret14; [L881] havoc activate_threads_#t~ret14; [L883-L887] assume !(0 != activate_threads_~tmp___3~0); [L889] havoc is_transmit5_triggered_#res; [L889] havoc is_transmit5_triggered_~__retres1~5; [L428] havoc is_transmit5_triggered_~__retres1~5; [L431-L440] assume !(1 == ~t5_pc~0); [L441] is_transmit5_triggered_~__retres1~5 := 0; [L443] is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; [L889] activate_threads_#t~ret15 := is_transmit5_triggered_#res; [L889] activate_threads_~tmp___4~0 := activate_threads_#t~ret15; [L889] havoc activate_threads_#t~ret15; [L891-L895] assume !(0 != activate_threads_~tmp___4~0); [L897] havoc is_transmit6_triggered_#res; [L897] havoc is_transmit6_triggered_~__retres1~6; [L447] havoc is_transmit6_triggered_~__retres1~6; [L450-L459] assume !(1 == ~t6_pc~0); [L460] is_transmit6_triggered_~__retres1~6 := 0; [L462] is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; [L897] activate_threads_#t~ret16 := is_transmit6_triggered_#res; [L897] activate_threads_~tmp___5~0 := activate_threads_#t~ret16; [L897] havoc activate_threads_#t~ret16; [L899-L903] assume !(0 != activate_threads_~tmp___5~0); [L764-L768] assume !(1 == ~M_E~0); [L769-L773] assume !(1 == ~T1_E~0); [L774-L778] assume !(1 == ~T2_E~0); [L779-L783] assume !(1 == ~T3_E~0); [L784-L788] assume !(1 == ~T4_E~0); [L789-L793] assume !(1 == ~T5_E~0); [L794-L798] assume !(1 == ~T6_E~0); [L799-L803] assume !(1 == ~E_M~0); [L804-L808] assume !(1 == ~E_1~0); [L809-L813] assume !(1 == ~E_2~0); [L814-L818] assume !(1 == ~E_3~0); [L819-L823] assume !(1 == ~E_4~0); [L824-L828] assume !(1 == ~E_5~0); [L829-L833] assume !(1 == ~E_6~0); [L1055-L1092] assume !false; [L1058] start_simulation_~kernel_st~0 := 1; [L1059] havoc eval_#t~ret2, eval_#t~nondet3, eval_~tmp_ndt_1~0, eval_#t~nondet4, eval_~tmp_ndt_2~0, eval_#t~nondet5, eval_~tmp_ndt_3~0, eval_#t~nondet6, eval_~tmp_ndt_4~0, eval_#t~nondet7, eval_~tmp_ndt_5~0, eval_#t~nondet8, eval_~tmp_ndt_6~0, eval_#t~nondet9, eval_~tmp_ndt_7~0, eval_~tmp~0; [L563] havoc eval_~tmp~0; [L14] ~m_pc~0 := 0; [L15] ~t1_pc~0 := 0; [L16] ~t2_pc~0 := 0; [L17] ~t3_pc~0 := 0; [L18] ~t4_pc~0 := 0; [L19] ~t5_pc~0 := 0; [L20] ~t6_pc~0 := 0; [L21] ~m_st~0 := 0; [L22] ~t1_st~0 := 0; [L23] ~t2_st~0 := 0; [L24] ~t3_st~0 := 0; [L25] ~t4_st~0 := 0; [L26] ~t5_st~0 := 0; [L27] ~t6_st~0 := 0; [L28] ~m_i~0 := 0; [L29] ~t1_i~0 := 0; [L30] ~t2_i~0 := 0; [L31] ~t3_i~0 := 0; [L32] ~t4_i~0 := 0; [L33] ~t5_i~0 := 0; [L34] ~t6_i~0 := 0; [L35] ~M_E~0 := 2; [L36] ~T1_E~0 := 2; [L37] ~T2_E~0 := 2; [L38] ~T3_E~0 := 2; [L39] ~T4_E~0 := 2; [L40] ~T5_E~0 := 2; [L41] ~T6_E~0 := 2; [L42] ~E_M~0 := 2; [L43] ~E_1~0 := 2; [L44] ~E_2~0 := 2; [L45] ~E_3~0 := 2; [L46] ~E_4~0 := 2; [L47] ~E_5~0 := 2; [L48] ~E_6~0 := 2; [L57] ~token~0 := 0; [L59] ~local~0 := 0; [?] havoc main_#res; [?] havoc main_~__retres1~8; [L1100] havoc main_~__retres1~8; [L1010] ~m_i~0 := 1; [L1011] ~t1_i~0 := 1; [L1012] ~t2_i~0 := 1; [L1013] ~t3_i~0 := 1; [L1014] ~t4_i~0 := 1; [L1015] ~t5_i~0 := 1; [L1016] ~t6_i~0 := 1; [L1105] havoc start_simulation_#t~ret18, start_simulation_#t~ret19, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1; [L1041] havoc start_simulation_~kernel_st~0; [L1042] havoc start_simulation_~tmp~3; [L1043] havoc start_simulation_~tmp___0~1; [L1047] start_simulation_~kernel_st~0 := 0; [L477] COND TRUE 1 == ~m_i~0 [L478] ~m_st~0 := 0; [L482] COND TRUE 1 == ~t1_i~0 [L483] ~t1_st~0 := 0; [L487] COND TRUE 1 == ~t2_i~0 [L488] ~t2_st~0 := 0; [L492] COND TRUE 1 == ~t3_i~0 [L493] ~t3_st~0 := 0; [L497] COND TRUE 1 == ~t4_i~0 [L498] ~t4_st~0 := 0; [L502] COND TRUE 1 == ~t5_i~0 [L503] ~t5_st~0 := 0; [L507] COND TRUE 1 == ~t6_i~0 [L508] ~t6_st~0 := 0; [L686] COND FALSE !(0 == ~M_E~0) [L691] COND FALSE !(0 == ~T1_E~0) [L696] COND FALSE !(0 == ~T2_E~0) [L701] COND FALSE !(0 == ~T3_E~0) [L706] COND FALSE !(0 == ~T4_E~0) [L711] COND FALSE !(0 == ~T5_E~0) [L716] COND FALSE !(0 == ~T6_E~0) [L721] COND FALSE !(0 == ~E_M~0) [L726] COND FALSE !(0 == ~E_1~0) [L731] COND FALSE !(0 == ~E_2~0) [L736] COND FALSE !(0 == ~E_3~0) [L741] COND FALSE !(0 == ~E_4~0) [L746] COND FALSE !(0 == ~E_5~0) [L751] COND FALSE !(0 == ~E_6~0) [L1051] havoc activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0; [L839] havoc activate_threads_~tmp~1; [L840] havoc activate_threads_~tmp___0~0; [L841] havoc activate_threads_~tmp___1~0; [L842] havoc activate_threads_~tmp___2~0; [L843] havoc activate_threads_~tmp___3~0; [L844] havoc activate_threads_~tmp___4~0; [L845] havoc activate_threads_~tmp___5~0; [L849] havoc is_master_triggered_#res; [L849] havoc is_master_triggered_~__retres1~0; [L333] havoc is_master_triggered_~__retres1~0; [L336] COND FALSE !(1 == ~m_pc~0) [L346] is_master_triggered_~__retres1~0 := 0; [L348] is_master_triggered_#res := is_master_triggered_~__retres1~0; [L849] activate_threads_#t~ret10 := is_master_triggered_#res; [L849] activate_threads_~tmp~1 := activate_threads_#t~ret10; [L849] havoc activate_threads_#t~ret10; [L851-L855] COND FALSE !(0 != activate_threads_~tmp~1) [L857] havoc is_transmit1_triggered_#res; [L857] havoc is_transmit1_triggered_~__retres1~1; [L352] havoc is_transmit1_triggered_~__retres1~1; [L355] COND FALSE !(1 == ~t1_pc~0) [L365] is_transmit1_triggered_~__retres1~1 := 0; [L367] is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; [L857] activate_threads_#t~ret11 := is_transmit1_triggered_#res; [L857] activate_threads_~tmp___0~0 := activate_threads_#t~ret11; [L857] havoc activate_threads_#t~ret11; [L859-L863] COND FALSE !(0 != activate_threads_~tmp___0~0) [L865] havoc is_transmit2_triggered_#res; [L865] havoc is_transmit2_triggered_~__retres1~2; [L371] havoc is_transmit2_triggered_~__retres1~2; [L374] COND FALSE !(1 == ~t2_pc~0) [L384] is_transmit2_triggered_~__retres1~2 := 0; [L386] is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; [L865] activate_threads_#t~ret12 := is_transmit2_triggered_#res; [L865] activate_threads_~tmp___1~0 := activate_threads_#t~ret12; [L865] havoc activate_threads_#t~ret12; [L867-L871] COND FALSE !(0 != activate_threads_~tmp___1~0) [L873] havoc is_transmit3_triggered_#res; [L873] havoc is_transmit3_triggered_~__retres1~3; [L390] havoc is_transmit3_triggered_~__retres1~3; [L393] COND FALSE !(1 == ~t3_pc~0) [L403] is_transmit3_triggered_~__retres1~3 := 0; [L405] is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; [L873] activate_threads_#t~ret13 := is_transmit3_triggered_#res; [L873] activate_threads_~tmp___2~0 := activate_threads_#t~ret13; [L873] havoc activate_threads_#t~ret13; [L875-L879] COND FALSE !(0 != activate_threads_~tmp___2~0) [L881] havoc is_transmit4_triggered_#res; [L881] havoc is_transmit4_triggered_~__retres1~4; [L409] havoc is_transmit4_triggered_~__retres1~4; [L412] COND FALSE !(1 == ~t4_pc~0) [L422] is_transmit4_triggered_~__retres1~4 := 0; [L424] is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; [L881] activate_threads_#t~ret14 := is_transmit4_triggered_#res; [L881] activate_threads_~tmp___3~0 := activate_threads_#t~ret14; [L881] havoc activate_threads_#t~ret14; [L883-L887] COND FALSE !(0 != activate_threads_~tmp___3~0) [L889] havoc is_transmit5_triggered_#res; [L889] havoc is_transmit5_triggered_~__retres1~5; [L428] havoc is_transmit5_triggered_~__retres1~5; [L431] COND FALSE !(1 == ~t5_pc~0) [L441] is_transmit5_triggered_~__retres1~5 := 0; [L443] is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; [L889] activate_threads_#t~ret15 := is_transmit5_triggered_#res; [L889] activate_threads_~tmp___4~0 := activate_threads_#t~ret15; [L889] havoc activate_threads_#t~ret15; [L891-L895] COND FALSE !(0 != activate_threads_~tmp___4~0) [L897] havoc is_transmit6_triggered_#res; [L897] havoc is_transmit6_triggered_~__retres1~6; [L447] havoc is_transmit6_triggered_~__retres1~6; [L450] COND FALSE !(1 == ~t6_pc~0) [L460] is_transmit6_triggered_~__retres1~6 := 0; [L462] is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; [L897] activate_threads_#t~ret16 := is_transmit6_triggered_#res; [L897] activate_threads_~tmp___5~0 := activate_threads_#t~ret16; [L897] havoc activate_threads_#t~ret16; [L899-L903] COND FALSE !(0 != activate_threads_~tmp___5~0) [L764] COND FALSE !(1 == ~M_E~0) [L769] COND FALSE !(1 == ~T1_E~0) [L774] COND FALSE !(1 == ~T2_E~0) [L779] COND FALSE !(1 == ~T3_E~0) [L784] COND FALSE !(1 == ~T4_E~0) [L789] COND FALSE !(1 == ~T5_E~0) [L794] COND FALSE !(1 == ~T6_E~0) [L799] COND FALSE !(1 == ~E_M~0) [L804] COND FALSE !(1 == ~E_1~0) [L809] COND FALSE !(1 == ~E_2~0) [L814] COND FALSE !(1 == ~E_3~0) [L819] COND FALSE !(1 == ~E_4~0) [L824] COND FALSE !(1 == ~E_5~0) [L829] COND FALSE !(1 == ~E_6~0) [L1055-L1092] COND FALSE !(false) [L1058] start_simulation_~kernel_st~0 := 1; [L1059] havoc eval_#t~ret2, eval_#t~nondet3, eval_~tmp_ndt_1~0, eval_#t~nondet4, eval_~tmp_ndt_2~0, eval_#t~nondet5, eval_~tmp_ndt_3~0, eval_#t~nondet6, eval_~tmp_ndt_4~0, eval_#t~nondet7, eval_~tmp_ndt_5~0, eval_#t~nondet8, eval_~tmp_ndt_6~0, eval_#t~nondet9, eval_~tmp_ndt_7~0, eval_~tmp~0; [L563] havoc eval_~tmp~0; ----- ----- class de.uni_freiburg.informatik.ultimate.boogie.procedureinliner.backtranslation.InlinerBacktranslator [L14] ~m_pc~0 := 0; [L15] ~t1_pc~0 := 0; [L16] ~t2_pc~0 := 0; [L17] ~t3_pc~0 := 0; [L18] ~t4_pc~0 := 0; [L19] ~t5_pc~0 := 0; [L20] ~t6_pc~0 := 0; [L21] ~m_st~0 := 0; [L22] ~t1_st~0 := 0; [L23] ~t2_st~0 := 0; [L24] ~t3_st~0 := 0; [L25] ~t4_st~0 := 0; [L26] ~t5_st~0 := 0; [L27] ~t6_st~0 := 0; [L28] ~m_i~0 := 0; [L29] ~t1_i~0 := 0; [L30] ~t2_i~0 := 0; [L31] ~t3_i~0 := 0; [L32] ~t4_i~0 := 0; [L33] ~t5_i~0 := 0; [L34] ~t6_i~0 := 0; [L35] ~M_E~0 := 2; [L36] ~T1_E~0 := 2; [L37] ~T2_E~0 := 2; [L38] ~T3_E~0 := 2; [L39] ~T4_E~0 := 2; [L40] ~T5_E~0 := 2; [L41] ~T6_E~0 := 2; [L42] ~E_M~0 := 2; [L43] ~E_1~0 := 2; [L44] ~E_2~0 := 2; [L45] ~E_3~0 := 2; [L46] ~E_4~0 := 2; [L47] ~E_5~0 := 2; [L48] ~E_6~0 := 2; [L57] ~token~0 := 0; [L59] ~local~0 := 0; [?] havoc main_#res; [?] havoc main_~__retres1~8; [L1100] havoc main_~__retres1~8; [L1010] ~m_i~0 := 1; [L1011] ~t1_i~0 := 1; [L1012] ~t2_i~0 := 1; [L1013] ~t3_i~0 := 1; [L1014] ~t4_i~0 := 1; [L1015] ~t5_i~0 := 1; [L1016] ~t6_i~0 := 1; [L1105] havoc start_simulation_#t~ret18, start_simulation_#t~ret19, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1; [L1041] havoc start_simulation_~kernel_st~0; [L1042] havoc start_simulation_~tmp~3; [L1043] havoc start_simulation_~tmp___0~1; [L1047] start_simulation_~kernel_st~0 := 0; [L477] COND TRUE 1 == ~m_i~0 [L478] ~m_st~0 := 0; [L482] COND TRUE 1 == ~t1_i~0 [L483] ~t1_st~0 := 0; [L487] COND TRUE 1 == ~t2_i~0 [L488] ~t2_st~0 := 0; [L492] COND TRUE 1 == ~t3_i~0 [L493] ~t3_st~0 := 0; [L497] COND TRUE 1 == ~t4_i~0 [L498] ~t4_st~0 := 0; [L502] COND TRUE 1 == ~t5_i~0 [L503] ~t5_st~0 := 0; [L507] COND TRUE 1 == ~t6_i~0 [L508] ~t6_st~0 := 0; [L686] COND FALSE !(0 == ~M_E~0) [L691] COND FALSE !(0 == ~T1_E~0) [L696] COND FALSE !(0 == ~T2_E~0) [L701] COND FALSE !(0 == ~T3_E~0) [L706] COND FALSE !(0 == ~T4_E~0) [L711] COND FALSE !(0 == ~T5_E~0) [L716] COND FALSE !(0 == ~T6_E~0) [L721] COND FALSE !(0 == ~E_M~0) [L726] COND FALSE !(0 == ~E_1~0) [L731] COND FALSE !(0 == ~E_2~0) [L736] COND FALSE !(0 == ~E_3~0) [L741] COND FALSE !(0 == ~E_4~0) [L746] COND FALSE !(0 == ~E_5~0) [L751] COND FALSE !(0 == ~E_6~0) [L1051] havoc activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0; [L839] havoc activate_threads_~tmp~1; [L840] havoc activate_threads_~tmp___0~0; [L841] havoc activate_threads_~tmp___1~0; [L842] havoc activate_threads_~tmp___2~0; [L843] havoc activate_threads_~tmp___3~0; [L844] havoc activate_threads_~tmp___4~0; [L845] havoc activate_threads_~tmp___5~0; [L849] havoc is_master_triggered_#res; [L849] havoc is_master_triggered_~__retres1~0; [L333] havoc is_master_triggered_~__retres1~0; [L336] COND FALSE !(1 == ~m_pc~0) [L346] is_master_triggered_~__retres1~0 := 0; [L348] is_master_triggered_#res := is_master_triggered_~__retres1~0; [L849] activate_threads_#t~ret10 := is_master_triggered_#res; [L849] activate_threads_~tmp~1 := activate_threads_#t~ret10; [L849] havoc activate_threads_#t~ret10; [L851-L855] COND FALSE !(0 != activate_threads_~tmp~1) [L857] havoc is_transmit1_triggered_#res; [L857] havoc is_transmit1_triggered_~__retres1~1; [L352] havoc is_transmit1_triggered_~__retres1~1; [L355] COND FALSE !(1 == ~t1_pc~0) [L365] is_transmit1_triggered_~__retres1~1 := 0; [L367] is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; [L857] activate_threads_#t~ret11 := is_transmit1_triggered_#res; [L857] activate_threads_~tmp___0~0 := activate_threads_#t~ret11; [L857] havoc activate_threads_#t~ret11; [L859-L863] COND FALSE !(0 != activate_threads_~tmp___0~0) [L865] havoc is_transmit2_triggered_#res; [L865] havoc is_transmit2_triggered_~__retres1~2; [L371] havoc is_transmit2_triggered_~__retres1~2; [L374] COND FALSE !(1 == ~t2_pc~0) [L384] is_transmit2_triggered_~__retres1~2 := 0; [L386] is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; [L865] activate_threads_#t~ret12 := is_transmit2_triggered_#res; [L865] activate_threads_~tmp___1~0 := activate_threads_#t~ret12; [L865] havoc activate_threads_#t~ret12; [L867-L871] COND FALSE !(0 != activate_threads_~tmp___1~0) [L873] havoc is_transmit3_triggered_#res; [L873] havoc is_transmit3_triggered_~__retres1~3; [L390] havoc is_transmit3_triggered_~__retres1~3; [L393] COND FALSE !(1 == ~t3_pc~0) [L403] is_transmit3_triggered_~__retres1~3 := 0; [L405] is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; [L873] activate_threads_#t~ret13 := is_transmit3_triggered_#res; [L873] activate_threads_~tmp___2~0 := activate_threads_#t~ret13; [L873] havoc activate_threads_#t~ret13; [L875-L879] COND FALSE !(0 != activate_threads_~tmp___2~0) [L881] havoc is_transmit4_triggered_#res; [L881] havoc is_transmit4_triggered_~__retres1~4; [L409] havoc is_transmit4_triggered_~__retres1~4; [L412] COND FALSE !(1 == ~t4_pc~0) [L422] is_transmit4_triggered_~__retres1~4 := 0; [L424] is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; [L881] activate_threads_#t~ret14 := is_transmit4_triggered_#res; [L881] activate_threads_~tmp___3~0 := activate_threads_#t~ret14; [L881] havoc activate_threads_#t~ret14; [L883-L887] COND FALSE !(0 != activate_threads_~tmp___3~0) [L889] havoc is_transmit5_triggered_#res; [L889] havoc is_transmit5_triggered_~__retres1~5; [L428] havoc is_transmit5_triggered_~__retres1~5; [L431] COND FALSE !(1 == ~t5_pc~0) [L441] is_transmit5_triggered_~__retres1~5 := 0; [L443] is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; [L889] activate_threads_#t~ret15 := is_transmit5_triggered_#res; [L889] activate_threads_~tmp___4~0 := activate_threads_#t~ret15; [L889] havoc activate_threads_#t~ret15; [L891-L895] COND FALSE !(0 != activate_threads_~tmp___4~0) [L897] havoc is_transmit6_triggered_#res; [L897] havoc is_transmit6_triggered_~__retres1~6; [L447] havoc is_transmit6_triggered_~__retres1~6; [L450] COND FALSE !(1 == ~t6_pc~0) [L460] is_transmit6_triggered_~__retres1~6 := 0; [L462] is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; [L897] activate_threads_#t~ret16 := is_transmit6_triggered_#res; [L897] activate_threads_~tmp___5~0 := activate_threads_#t~ret16; [L897] havoc activate_threads_#t~ret16; [L899-L903] COND FALSE !(0 != activate_threads_~tmp___5~0) [L764] COND FALSE !(1 == ~M_E~0) [L769] COND FALSE !(1 == ~T1_E~0) [L774] COND FALSE !(1 == ~T2_E~0) [L779] COND FALSE !(1 == ~T3_E~0) [L784] COND FALSE !(1 == ~T4_E~0) [L789] COND FALSE !(1 == ~T5_E~0) [L794] COND FALSE !(1 == ~T6_E~0) [L799] COND FALSE !(1 == ~E_M~0) [L804] COND FALSE !(1 == ~E_1~0) [L809] COND FALSE !(1 == ~E_2~0) [L814] COND FALSE !(1 == ~E_3~0) [L819] COND FALSE !(1 == ~E_4~0) [L824] COND FALSE !(1 == ~E_5~0) [L829] COND FALSE !(1 == ~E_6~0) [L1055-L1092] COND FALSE !(false) [L1058] start_simulation_~kernel_st~0 := 1; [L1059] havoc eval_#t~ret2, eval_#t~nondet3, eval_~tmp_ndt_1~0, eval_#t~nondet4, eval_~tmp_ndt_2~0, eval_#t~nondet5, eval_~tmp_ndt_3~0, eval_#t~nondet6, eval_~tmp_ndt_4~0, eval_#t~nondet7, eval_~tmp_ndt_5~0, eval_#t~nondet8, eval_~tmp_ndt_6~0, eval_#t~nondet9, eval_~tmp_ndt_7~0, eval_~tmp~0; [L563] havoc eval_~tmp~0; [L14] ~m_pc~0 := 0; [L15] ~t1_pc~0 := 0; [L16] ~t2_pc~0 := 0; [L17] ~t3_pc~0 := 0; [L18] ~t4_pc~0 := 0; [L19] ~t5_pc~0 := 0; [L20] ~t6_pc~0 := 0; [L21] ~m_st~0 := 0; [L22] ~t1_st~0 := 0; [L23] ~t2_st~0 := 0; [L24] ~t3_st~0 := 0; [L25] ~t4_st~0 := 0; [L26] ~t5_st~0 := 0; [L27] ~t6_st~0 := 0; [L28] ~m_i~0 := 0; [L29] ~t1_i~0 := 0; [L30] ~t2_i~0 := 0; [L31] ~t3_i~0 := 0; [L32] ~t4_i~0 := 0; [L33] ~t5_i~0 := 0; [L34] ~t6_i~0 := 0; [L35] ~M_E~0 := 2; [L36] ~T1_E~0 := 2; [L37] ~T2_E~0 := 2; [L38] ~T3_E~0 := 2; [L39] ~T4_E~0 := 2; [L40] ~T5_E~0 := 2; [L41] ~T6_E~0 := 2; [L42] ~E_M~0 := 2; [L43] ~E_1~0 := 2; [L44] ~E_2~0 := 2; [L45] ~E_3~0 := 2; [L46] ~E_4~0 := 2; [L47] ~E_5~0 := 2; [L48] ~E_6~0 := 2; [L57] ~token~0 := 0; [L59] ~local~0 := 0; [L1100] havoc ~__retres1~8; [L1010] ~m_i~0 := 1; [L1011] ~t1_i~0 := 1; [L1012] ~t2_i~0 := 1; [L1013] ~t3_i~0 := 1; [L1014] ~t4_i~0 := 1; [L1015] ~t5_i~0 := 1; [L1016] ~t6_i~0 := 1; [L1041] havoc ~kernel_st~0; [L1042] havoc ~tmp~3; [L1043] havoc ~tmp___0~1; [L1047] ~kernel_st~0 := 0; [L477] COND TRUE 1 == ~m_i~0 [L478] ~m_st~0 := 0; [L482] COND TRUE 1 == ~t1_i~0 [L483] ~t1_st~0 := 0; [L487] COND TRUE 1 == ~t2_i~0 [L488] ~t2_st~0 := 0; [L492] COND TRUE 1 == ~t3_i~0 [L493] ~t3_st~0 := 0; [L497] COND TRUE 1 == ~t4_i~0 [L498] ~t4_st~0 := 0; [L502] COND TRUE 1 == ~t5_i~0 [L503] ~t5_st~0 := 0; [L507] COND TRUE 1 == ~t6_i~0 [L508] ~t6_st~0 := 0; [L686] COND FALSE !(0 == ~M_E~0) [L691] COND FALSE !(0 == ~T1_E~0) [L696] COND FALSE !(0 == ~T2_E~0) [L701] COND FALSE !(0 == ~T3_E~0) [L706] COND FALSE !(0 == ~T4_E~0) [L711] COND FALSE !(0 == ~T5_E~0) [L716] COND FALSE !(0 == ~T6_E~0) [L721] COND FALSE !(0 == ~E_M~0) [L726] COND FALSE !(0 == ~E_1~0) [L731] COND FALSE !(0 == ~E_2~0) [L736] COND FALSE !(0 == ~E_3~0) [L741] COND FALSE !(0 == ~E_4~0) [L746] COND FALSE !(0 == ~E_5~0) [L751] COND FALSE !(0 == ~E_6~0) [L839] havoc ~tmp~1; [L840] havoc ~tmp___0~0; [L841] havoc ~tmp___1~0; [L842] havoc ~tmp___2~0; [L843] havoc ~tmp___3~0; [L844] havoc ~tmp___4~0; [L845] havoc ~tmp___5~0; [L333] havoc ~__retres1~0; [L336] COND FALSE !(1 == ~m_pc~0) [L346] ~__retres1~0 := 0; [L348] #res := ~__retres1~0; [L849] ~tmp~1 := #t~ret10; [L849] havoc #t~ret10; [L851-L855] COND FALSE !(0 != ~tmp~1) [L352] havoc ~__retres1~1; [L355] COND FALSE !(1 == ~t1_pc~0) [L365] ~__retres1~1 := 0; [L367] #res := ~__retres1~1; [L857] ~tmp___0~0 := #t~ret11; [L857] havoc #t~ret11; [L859-L863] COND FALSE !(0 != ~tmp___0~0) [L371] havoc ~__retres1~2; [L374] COND FALSE !(1 == ~t2_pc~0) [L384] ~__retres1~2 := 0; [L386] #res := ~__retres1~2; [L865] ~tmp___1~0 := #t~ret12; [L865] havoc #t~ret12; [L867-L871] COND FALSE !(0 != ~tmp___1~0) [L390] havoc ~__retres1~3; [L393] COND FALSE !(1 == ~t3_pc~0) [L403] ~__retres1~3 := 0; [L405] #res := ~__retres1~3; [L873] ~tmp___2~0 := #t~ret13; [L873] havoc #t~ret13; [L875-L879] COND FALSE !(0 != ~tmp___2~0) [L409] havoc ~__retres1~4; [L412] COND FALSE !(1 == ~t4_pc~0) [L422] ~__retres1~4 := 0; [L424] #res := ~__retres1~4; [L881] ~tmp___3~0 := #t~ret14; [L881] havoc #t~ret14; [L883-L887] COND FALSE !(0 != ~tmp___3~0) [L428] havoc ~__retres1~5; [L431] COND FALSE !(1 == ~t5_pc~0) [L441] ~__retres1~5 := 0; [L443] #res := ~__retres1~5; [L889] ~tmp___4~0 := #t~ret15; [L889] havoc #t~ret15; [L891-L895] COND FALSE !(0 != ~tmp___4~0) [L447] havoc ~__retres1~6; [L450] COND FALSE !(1 == ~t6_pc~0) [L460] ~__retres1~6 := 0; [L462] #res := ~__retres1~6; [L897] ~tmp___5~0 := #t~ret16; [L897] havoc #t~ret16; [L899-L903] COND FALSE !(0 != ~tmp___5~0) [L764] COND FALSE !(1 == ~M_E~0) [L769] COND FALSE !(1 == ~T1_E~0) [L774] COND FALSE !(1 == ~T2_E~0) [L779] COND FALSE !(1 == ~T3_E~0) [L784] COND FALSE !(1 == ~T4_E~0) [L789] COND FALSE !(1 == ~T5_E~0) [L794] COND FALSE !(1 == ~T6_E~0) [L799] COND FALSE !(1 == ~E_M~0) [L804] COND FALSE !(1 == ~E_1~0) [L809] COND FALSE !(1 == ~E_2~0) [L814] COND FALSE !(1 == ~E_3~0) [L819] COND FALSE !(1 == ~E_4~0) [L824] COND FALSE !(1 == ~E_5~0) [L829] COND FALSE !(1 == ~E_6~0) [L1055-L1092] COND FALSE !(false) [L1058] ~kernel_st~0 := 1; [L563] havoc ~tmp~0; ----- ----- class de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.CACSL2BoogieBacktranslator [L14] ~m_pc~0 := 0; [L15] ~t1_pc~0 := 0; [L16] ~t2_pc~0 := 0; [L17] ~t3_pc~0 := 0; [L18] ~t4_pc~0 := 0; [L19] ~t5_pc~0 := 0; [L20] ~t6_pc~0 := 0; [L21] ~m_st~0 := 0; [L22] ~t1_st~0 := 0; [L23] ~t2_st~0 := 0; [L24] ~t3_st~0 := 0; [L25] ~t4_st~0 := 0; [L26] ~t5_st~0 := 0; [L27] ~t6_st~0 := 0; [L28] ~m_i~0 := 0; [L29] ~t1_i~0 := 0; [L30] ~t2_i~0 := 0; [L31] ~t3_i~0 := 0; [L32] ~t4_i~0 := 0; [L33] ~t5_i~0 := 0; [L34] ~t6_i~0 := 0; [L35] ~M_E~0 := 2; [L36] ~T1_E~0 := 2; [L37] ~T2_E~0 := 2; [L38] ~T3_E~0 := 2; [L39] ~T4_E~0 := 2; [L40] ~T5_E~0 := 2; [L41] ~T6_E~0 := 2; [L42] ~E_M~0 := 2; [L43] ~E_1~0 := 2; [L44] ~E_2~0 := 2; [L45] ~E_3~0 := 2; [L46] ~E_4~0 := 2; [L47] ~E_5~0 := 2; [L48] ~E_6~0 := 2; [L57] ~token~0 := 0; [L59] ~local~0 := 0; [L1100] havoc ~__retres1~8; [L1010] ~m_i~0 := 1; [L1011] ~t1_i~0 := 1; [L1012] ~t2_i~0 := 1; [L1013] ~t3_i~0 := 1; [L1014] ~t4_i~0 := 1; [L1015] ~t5_i~0 := 1; [L1016] ~t6_i~0 := 1; [L1041] havoc ~kernel_st~0; [L1042] havoc ~tmp~3; [L1043] havoc ~tmp___0~1; [L1047] ~kernel_st~0 := 0; [L477] COND TRUE 1 == ~m_i~0 [L478] ~m_st~0 := 0; [L482] COND TRUE 1 == ~t1_i~0 [L483] ~t1_st~0 := 0; [L487] COND TRUE 1 == ~t2_i~0 [L488] ~t2_st~0 := 0; [L492] COND TRUE 1 == ~t3_i~0 [L493] ~t3_st~0 := 0; [L497] COND TRUE 1 == ~t4_i~0 [L498] ~t4_st~0 := 0; [L502] COND TRUE 1 == ~t5_i~0 [L503] ~t5_st~0 := 0; [L507] COND TRUE 1 == ~t6_i~0 [L508] ~t6_st~0 := 0; [L686] COND FALSE !(0 == ~M_E~0) [L691] COND FALSE !(0 == ~T1_E~0) [L696] COND FALSE !(0 == ~T2_E~0) [L701] COND FALSE !(0 == ~T3_E~0) [L706] COND FALSE !(0 == ~T4_E~0) [L711] COND FALSE !(0 == ~T5_E~0) [L716] COND FALSE !(0 == ~T6_E~0) [L721] COND FALSE !(0 == ~E_M~0) [L726] COND FALSE !(0 == ~E_1~0) [L731] COND FALSE !(0 == ~E_2~0) [L736] COND FALSE !(0 == ~E_3~0) [L741] COND FALSE !(0 == ~E_4~0) [L746] COND FALSE !(0 == ~E_5~0) [L751] COND FALSE !(0 == ~E_6~0) [L839] havoc ~tmp~1; [L840] havoc ~tmp___0~0; [L841] havoc ~tmp___1~0; [L842] havoc ~tmp___2~0; [L843] havoc ~tmp___3~0; [L844] havoc ~tmp___4~0; [L845] havoc ~tmp___5~0; [L333] havoc ~__retres1~0; [L336] COND FALSE !(1 == ~m_pc~0) [L346] ~__retres1~0 := 0; [L348] #res := ~__retres1~0; [L849] ~tmp~1 := #t~ret10; [L849] havoc #t~ret10; [L851-L855] COND FALSE !(0 != ~tmp~1) [L352] havoc ~__retres1~1; [L355] COND FALSE !(1 == ~t1_pc~0) [L365] ~__retres1~1 := 0; [L367] #res := ~__retres1~1; [L857] ~tmp___0~0 := #t~ret11; [L857] havoc #t~ret11; [L859-L863] COND FALSE !(0 != ~tmp___0~0) [L371] havoc ~__retres1~2; [L374] COND FALSE !(1 == ~t2_pc~0) [L384] ~__retres1~2 := 0; [L386] #res := ~__retres1~2; [L865] ~tmp___1~0 := #t~ret12; [L865] havoc #t~ret12; [L867-L871] COND FALSE !(0 != ~tmp___1~0) [L390] havoc ~__retres1~3; [L393] COND FALSE !(1 == ~t3_pc~0) [L403] ~__retres1~3 := 0; [L405] #res := ~__retres1~3; [L873] ~tmp___2~0 := #t~ret13; [L873] havoc #t~ret13; [L875-L879] COND FALSE !(0 != ~tmp___2~0) [L409] havoc ~__retres1~4; [L412] COND FALSE !(1 == ~t4_pc~0) [L422] ~__retres1~4 := 0; [L424] #res := ~__retres1~4; [L881] ~tmp___3~0 := #t~ret14; [L881] havoc #t~ret14; [L883-L887] COND FALSE !(0 != ~tmp___3~0) [L428] havoc ~__retres1~5; [L431] COND FALSE !(1 == ~t5_pc~0) [L441] ~__retres1~5 := 0; [L443] #res := ~__retres1~5; [L889] ~tmp___4~0 := #t~ret15; [L889] havoc #t~ret15; [L891-L895] COND FALSE !(0 != ~tmp___4~0) [L447] havoc ~__retres1~6; [L450] COND FALSE !(1 == ~t6_pc~0) [L460] ~__retres1~6 := 0; [L462] #res := ~__retres1~6; [L897] ~tmp___5~0 := #t~ret16; [L897] havoc #t~ret16; [L899-L903] COND FALSE !(0 != ~tmp___5~0) [L764] COND FALSE !(1 == ~M_E~0) [L769] COND FALSE !(1 == ~T1_E~0) [L774] COND FALSE !(1 == ~T2_E~0) [L779] COND FALSE !(1 == ~T3_E~0) [L784] COND FALSE !(1 == ~T4_E~0) [L789] COND FALSE !(1 == ~T5_E~0) [L794] COND FALSE !(1 == ~T6_E~0) [L799] COND FALSE !(1 == ~E_M~0) [L804] COND FALSE !(1 == ~E_1~0) [L809] COND FALSE !(1 == ~E_2~0) [L814] COND FALSE !(1 == ~E_3~0) [L819] COND FALSE !(1 == ~E_4~0) [L824] COND FALSE !(1 == ~E_5~0) [L829] COND FALSE !(1 == ~E_6~0) [L1055-L1092] COND FALSE !(false) [L1058] ~kernel_st~0 := 1; [L563] havoc ~tmp~0; [L14] int m_pc = 0; [L15] int t1_pc = 0; [L16] int t2_pc = 0; [L17] int t3_pc = 0; [L18] int t4_pc = 0; [L19] int t5_pc = 0; [L20] int t6_pc = 0; [L21] int m_st ; [L22] int t1_st ; [L23] int t2_st ; [L24] int t3_st ; [L25] int t4_st ; [L26] int t5_st ; [L27] int t6_st ; [L28] int m_i ; [L29] int t1_i ; [L30] int t2_i ; [L31] int t3_i ; [L32] int t4_i ; [L33] int t5_i ; [L34] int t6_i ; [L35] int M_E = 2; [L36] int T1_E = 2; [L37] int T2_E = 2; [L38] int T3_E = 2; [L39] int T4_E = 2; [L40] int T5_E = 2; [L41] int T6_E = 2; [L42] int E_M = 2; [L43] int E_1 = 2; [L44] int E_2 = 2; [L45] int E_3 = 2; [L46] int E_4 = 2; [L47] int E_5 = 2; [L48] int E_6 = 2; [L57] int token ; [L59] int local ; [L1100] int __retres1 ; [L1010] m_i = 1 [L1011] t1_i = 1 [L1012] t2_i = 1 [L1013] t3_i = 1 [L1014] t4_i = 1 [L1015] t5_i = 1 [L1016] t6_i = 1 [L1041] int kernel_st ; [L1042] int tmp ; [L1043] int tmp___0 ; [L1047] kernel_st = 0 [L477] COND TRUE m_i == 1 [L478] m_st = 0 [L482] COND TRUE t1_i == 1 [L483] t1_st = 0 [L487] COND TRUE t2_i == 1 [L488] t2_st = 0 [L492] COND TRUE t3_i == 1 [L493] t3_st = 0 [L497] COND TRUE t4_i == 1 [L498] t4_st = 0 [L502] COND TRUE t5_i == 1 [L503] t5_st = 0 [L507] COND TRUE t6_i == 1 [L508] t6_st = 0 [L686] COND FALSE !(M_E == 0) [L691] COND FALSE !(T1_E == 0) [L696] COND FALSE !(T2_E == 0) [L701] COND FALSE !(T3_E == 0) [L706] COND FALSE !(T4_E == 0) [L711] COND FALSE !(T5_E == 0) [L716] COND FALSE !(T6_E == 0) [L721] COND FALSE !(E_M == 0) [L726] COND FALSE !(E_1 == 0) [L731] COND FALSE !(E_2 == 0) [L736] COND FALSE !(E_3 == 0) [L741] COND FALSE !(E_4 == 0) [L746] COND FALSE !(E_5 == 0) [L751] COND FALSE !(E_6 == 0) [L839] int tmp ; [L840] int tmp___0 ; [L841] int tmp___1 ; [L842] int tmp___2 ; [L843] int tmp___3 ; [L844] int tmp___4 ; [L845] int tmp___5 ; [L333] int __retres1 ; [L336] COND FALSE !(m_pc == 1) [L346] __retres1 = 0 [L348] return (__retres1); [L849] tmp = is_master_triggered() [L851] COND FALSE !(\read(tmp)) [L352] int __retres1 ; [L355] COND FALSE !(t1_pc == 1) [L365] __retres1 = 0 [L367] return (__retres1); [L857] tmp___0 = is_transmit1_triggered() [L859] COND FALSE !(\read(tmp___0)) [L371] int __retres1 ; [L374] COND FALSE !(t2_pc == 1) [L384] __retres1 = 0 [L386] return (__retres1); [L865] tmp___1 = is_transmit2_triggered() [L867] COND FALSE !(\read(tmp___1)) [L390] int __retres1 ; [L393] COND FALSE !(t3_pc == 1) [L403] __retres1 = 0 [L405] return (__retres1); [L873] tmp___2 = is_transmit3_triggered() [L875] COND FALSE !(\read(tmp___2)) [L409] int __retres1 ; [L412] COND FALSE !(t4_pc == 1) [L422] __retres1 = 0 [L424] return (__retres1); [L881] tmp___3 = is_transmit4_triggered() [L883] COND FALSE !(\read(tmp___3)) [L428] int __retres1 ; [L431] COND FALSE !(t5_pc == 1) [L441] __retres1 = 0 [L443] return (__retres1); [L889] tmp___4 = is_transmit5_triggered() [L891] COND FALSE !(\read(tmp___4)) [L447] int __retres1 ; [L450] COND FALSE !(t6_pc == 1) [L460] __retres1 = 0 [L462] return (__retres1); [L897] tmp___5 = is_transmit6_triggered() [L899] COND FALSE !(\read(tmp___5)) [L764] COND FALSE !(M_E == 1) [L769] COND FALSE !(T1_E == 1) [L774] COND FALSE !(T2_E == 1) [L779] COND FALSE !(T3_E == 1) [L784] COND FALSE !(T4_E == 1) [L789] COND FALSE !(T5_E == 1) [L794] COND FALSE !(T6_E == 1) [L799] COND FALSE !(E_M == 1) [L804] COND FALSE !(E_1 == 1) [L809] COND FALSE !(E_2 == 1) [L814] COND FALSE !(E_3 == 1) [L819] COND FALSE !(E_4 == 1) [L824] COND FALSE !(E_5 == 1) [L829] COND FALSE !(E_6 == 1) [L1055] COND TRUE 1 [L1058] kernel_st = 1 [L563] int tmp ; ----- ----- class de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder.RCFGBacktranslator [?] assume !false; [?] havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~7;havoc exists_runnable_thread_~__retres1~7; [?] assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7 := 1; [?] exists_runnable_thread_#res := exists_runnable_thread_~__retres1~7; [?] eval_#t~ret2 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret2;havoc eval_#t~ret2; [?] assume 0 != eval_~tmp~0; [?] assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0;eval_~tmp_ndt_1~0 := eval_#t~nondet3;havoc eval_#t~nondet3; [?] assume !(0 != eval_~tmp_ndt_1~0); [?] assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0;eval_~tmp_ndt_2~0 := eval_#t~nondet4;havoc eval_#t~nondet4; [?] assume !(0 != eval_~tmp_ndt_2~0); [?] assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0;eval_~tmp_ndt_3~0 := eval_#t~nondet5;havoc eval_#t~nondet5; [?] assume !(0 != eval_~tmp_ndt_3~0); [?] assume 0 == ~t3_st~0;havoc eval_~tmp_ndt_4~0;eval_~tmp_ndt_4~0 := eval_#t~nondet6;havoc eval_#t~nondet6; [?] assume !(0 != eval_~tmp_ndt_4~0); [?] assume 0 == ~t4_st~0;havoc eval_~tmp_ndt_5~0;eval_~tmp_ndt_5~0 := eval_#t~nondet7;havoc eval_#t~nondet7; [?] assume !(0 != eval_~tmp_ndt_5~0); [?] assume 0 == ~t5_st~0;havoc eval_~tmp_ndt_6~0;eval_~tmp_ndt_6~0 := eval_#t~nondet8;havoc eval_#t~nondet8; [?] assume !(0 != eval_~tmp_ndt_6~0); [?] assume 0 == ~t6_st~0;havoc eval_~tmp_ndt_7~0;eval_~tmp_ndt_7~0 := eval_#t~nondet9;havoc eval_#t~nondet9; [?] assume !(0 != eval_~tmp_ndt_7~0); [L567-L675] assume !false; [L570] havoc exists_runnable_thread_#res; [L570] havoc exists_runnable_thread_~__retres1~7; [L517] havoc exists_runnable_thread_~__retres1~7; [L520-L555] assume 0 == ~m_st~0; [L521] exists_runnable_thread_~__retres1~7 := 1; [L558] exists_runnable_thread_#res := exists_runnable_thread_~__retres1~7; [L570] eval_#t~ret2 := exists_runnable_thread_#res; [L570] eval_~tmp~0 := eval_#t~ret2; [L570] havoc eval_#t~ret2; [L572-L576] assume 0 != eval_~tmp~0; [L577-L590] assume 0 == ~m_st~0; [L578] havoc eval_~tmp_ndt_1~0; [L579] eval_~tmp_ndt_1~0 := eval_#t~nondet3; [L579] havoc eval_#t~nondet3; [L580-L587] assume !(0 != eval_~tmp_ndt_1~0); [L591-L604] assume 0 == ~t1_st~0; [L592] havoc eval_~tmp_ndt_2~0; [L593] eval_~tmp_ndt_2~0 := eval_#t~nondet4; [L593] havoc eval_#t~nondet4; [L594-L601] assume !(0 != eval_~tmp_ndt_2~0); [L605-L618] assume 0 == ~t2_st~0; [L606] havoc eval_~tmp_ndt_3~0; [L607] eval_~tmp_ndt_3~0 := eval_#t~nondet5; [L607] havoc eval_#t~nondet5; [L608-L615] assume !(0 != eval_~tmp_ndt_3~0); [L619-L632] assume 0 == ~t3_st~0; [L620] havoc eval_~tmp_ndt_4~0; [L621] eval_~tmp_ndt_4~0 := eval_#t~nondet6; [L621] havoc eval_#t~nondet6; [L622-L629] assume !(0 != eval_~tmp_ndt_4~0); [L633-L646] assume 0 == ~t4_st~0; [L634] havoc eval_~tmp_ndt_5~0; [L635] eval_~tmp_ndt_5~0 := eval_#t~nondet7; [L635] havoc eval_#t~nondet7; [L636-L643] assume !(0 != eval_~tmp_ndt_5~0); [L647-L660] assume 0 == ~t5_st~0; [L648] havoc eval_~tmp_ndt_6~0; [L649] eval_~tmp_ndt_6~0 := eval_#t~nondet8; [L649] havoc eval_#t~nondet8; [L650-L657] assume !(0 != eval_~tmp_ndt_6~0); [L661-L674] assume 0 == ~t6_st~0; [L662] havoc eval_~tmp_ndt_7~0; [L663] eval_~tmp_ndt_7~0 := eval_#t~nondet9; [L663] havoc eval_#t~nondet9; [L664-L671] assume !(0 != eval_~tmp_ndt_7~0); ----- ----- class de.uni_freiburg.informatik.ultimate.boogie.preprocessor.BoogiePreprocessorBacktranslator [L567-L675] assume !false; [L570] havoc exists_runnable_thread_#res; [L570] havoc exists_runnable_thread_~__retres1~7; [L517] havoc exists_runnable_thread_~__retres1~7; [L520-L555] assume 0 == ~m_st~0; [L521] exists_runnable_thread_~__retres1~7 := 1; [L558] exists_runnable_thread_#res := exists_runnable_thread_~__retres1~7; [L570] eval_#t~ret2 := exists_runnable_thread_#res; [L570] eval_~tmp~0 := eval_#t~ret2; [L570] havoc eval_#t~ret2; [L572-L576] assume 0 != eval_~tmp~0; [L577-L590] assume 0 == ~m_st~0; [L578] havoc eval_~tmp_ndt_1~0; [L579] eval_~tmp_ndt_1~0 := eval_#t~nondet3; [L579] havoc eval_#t~nondet3; [L580-L587] assume !(0 != eval_~tmp_ndt_1~0); [L591-L604] assume 0 == ~t1_st~0; [L592] havoc eval_~tmp_ndt_2~0; [L593] eval_~tmp_ndt_2~0 := eval_#t~nondet4; [L593] havoc eval_#t~nondet4; [L594-L601] assume !(0 != eval_~tmp_ndt_2~0); [L605-L618] assume 0 == ~t2_st~0; [L606] havoc eval_~tmp_ndt_3~0; [L607] eval_~tmp_ndt_3~0 := eval_#t~nondet5; [L607] havoc eval_#t~nondet5; [L608-L615] assume !(0 != eval_~tmp_ndt_3~0); [L619-L632] assume 0 == ~t3_st~0; [L620] havoc eval_~tmp_ndt_4~0; [L621] eval_~tmp_ndt_4~0 := eval_#t~nondet6; [L621] havoc eval_#t~nondet6; [L622-L629] assume !(0 != eval_~tmp_ndt_4~0); [L633-L646] assume 0 == ~t4_st~0; [L634] havoc eval_~tmp_ndt_5~0; [L635] eval_~tmp_ndt_5~0 := eval_#t~nondet7; [L635] havoc eval_#t~nondet7; [L636-L643] assume !(0 != eval_~tmp_ndt_5~0); [L647-L660] assume 0 == ~t5_st~0; [L648] havoc eval_~tmp_ndt_6~0; [L649] eval_~tmp_ndt_6~0 := eval_#t~nondet8; [L649] havoc eval_#t~nondet8; [L650-L657] assume !(0 != eval_~tmp_ndt_6~0); [L661-L674] assume 0 == ~t6_st~0; [L662] havoc eval_~tmp_ndt_7~0; [L663] eval_~tmp_ndt_7~0 := eval_#t~nondet9; [L663] havoc eval_#t~nondet9; [L664-L671] assume !(0 != eval_~tmp_ndt_7~0); [L567-L675] COND FALSE !(false) [L570] havoc exists_runnable_thread_#res; [L570] havoc exists_runnable_thread_~__retres1~7; [L517] havoc exists_runnable_thread_~__retres1~7; [L520] COND TRUE 0 == ~m_st~0 [L521] exists_runnable_thread_~__retres1~7 := 1; [L558] exists_runnable_thread_#res := exists_runnable_thread_~__retres1~7; [L570] eval_#t~ret2 := exists_runnable_thread_#res; [L570] eval_~tmp~0 := eval_#t~ret2; [L570] havoc eval_#t~ret2; [L572-L576] COND TRUE 0 != eval_~tmp~0 [L577] COND TRUE 0 == ~m_st~0 [L578] havoc eval_~tmp_ndt_1~0; [L579] eval_~tmp_ndt_1~0 := eval_#t~nondet3; [L579] havoc eval_#t~nondet3; [L580-L587] COND FALSE !(0 != eval_~tmp_ndt_1~0) [L591] COND TRUE 0 == ~t1_st~0 [L592] havoc eval_~tmp_ndt_2~0; [L593] eval_~tmp_ndt_2~0 := eval_#t~nondet4; [L593] havoc eval_#t~nondet4; [L594-L601] COND FALSE !(0 != eval_~tmp_ndt_2~0) [L605] COND TRUE 0 == ~t2_st~0 [L606] havoc eval_~tmp_ndt_3~0; [L607] eval_~tmp_ndt_3~0 := eval_#t~nondet5; [L607] havoc eval_#t~nondet5; [L608-L615] COND FALSE !(0 != eval_~tmp_ndt_3~0) [L619] COND TRUE 0 == ~t3_st~0 [L620] havoc eval_~tmp_ndt_4~0; [L621] eval_~tmp_ndt_4~0 := eval_#t~nondet6; [L621] havoc eval_#t~nondet6; [L622-L629] COND FALSE !(0 != eval_~tmp_ndt_4~0) [L633] COND TRUE 0 == ~t4_st~0 [L634] havoc eval_~tmp_ndt_5~0; [L635] eval_~tmp_ndt_5~0 := eval_#t~nondet7; [L635] havoc eval_#t~nondet7; [L636-L643] COND FALSE !(0 != eval_~tmp_ndt_5~0) [L647] COND TRUE 0 == ~t5_st~0 [L648] havoc eval_~tmp_ndt_6~0; [L649] eval_~tmp_ndt_6~0 := eval_#t~nondet8; [L649] havoc eval_#t~nondet8; [L650-L657] COND FALSE !(0 != eval_~tmp_ndt_6~0) [L661] COND TRUE 0 == ~t6_st~0 [L662] havoc eval_~tmp_ndt_7~0; [L663] eval_~tmp_ndt_7~0 := eval_#t~nondet9; [L663] havoc eval_#t~nondet9; [L664-L671] COND FALSE !(0 != eval_~tmp_ndt_7~0) ----- ----- class de.uni_freiburg.informatik.ultimate.boogie.procedureinliner.backtranslation.InlinerBacktranslator [L567-L675] COND FALSE !(false) [L570] havoc exists_runnable_thread_#res; [L570] havoc exists_runnable_thread_~__retres1~7; [L517] havoc exists_runnable_thread_~__retres1~7; [L520] COND TRUE 0 == ~m_st~0 [L521] exists_runnable_thread_~__retres1~7 := 1; [L558] exists_runnable_thread_#res := exists_runnable_thread_~__retres1~7; [L570] eval_#t~ret2 := exists_runnable_thread_#res; [L570] eval_~tmp~0 := eval_#t~ret2; [L570] havoc eval_#t~ret2; [L572-L576] COND TRUE 0 != eval_~tmp~0 [L577] COND TRUE 0 == ~m_st~0 [L578] havoc eval_~tmp_ndt_1~0; [L579] eval_~tmp_ndt_1~0 := eval_#t~nondet3; [L579] havoc eval_#t~nondet3; [L580-L587] COND FALSE !(0 != eval_~tmp_ndt_1~0) [L591] COND TRUE 0 == ~t1_st~0 [L592] havoc eval_~tmp_ndt_2~0; [L593] eval_~tmp_ndt_2~0 := eval_#t~nondet4; [L593] havoc eval_#t~nondet4; [L594-L601] COND FALSE !(0 != eval_~tmp_ndt_2~0) [L605] COND TRUE 0 == ~t2_st~0 [L606] havoc eval_~tmp_ndt_3~0; [L607] eval_~tmp_ndt_3~0 := eval_#t~nondet5; [L607] havoc eval_#t~nondet5; [L608-L615] COND FALSE !(0 != eval_~tmp_ndt_3~0) [L619] COND TRUE 0 == ~t3_st~0 [L620] havoc eval_~tmp_ndt_4~0; [L621] eval_~tmp_ndt_4~0 := eval_#t~nondet6; [L621] havoc eval_#t~nondet6; [L622-L629] COND FALSE !(0 != eval_~tmp_ndt_4~0) [L633] COND TRUE 0 == ~t4_st~0 [L634] havoc eval_~tmp_ndt_5~0; [L635] eval_~tmp_ndt_5~0 := eval_#t~nondet7; [L635] havoc eval_#t~nondet7; [L636-L643] COND FALSE !(0 != eval_~tmp_ndt_5~0) [L647] COND TRUE 0 == ~t5_st~0 [L648] havoc eval_~tmp_ndt_6~0; [L649] eval_~tmp_ndt_6~0 := eval_#t~nondet8; [L649] havoc eval_#t~nondet8; [L650-L657] COND FALSE !(0 != eval_~tmp_ndt_6~0) [L661] COND TRUE 0 == ~t6_st~0 [L662] havoc eval_~tmp_ndt_7~0; [L663] eval_~tmp_ndt_7~0 := eval_#t~nondet9; [L663] havoc eval_#t~nondet9; [L664-L671] COND FALSE !(0 != eval_~tmp_ndt_7~0) [L567-L675] COND FALSE !(false) [L517] havoc ~__retres1~7; [L520] COND TRUE 0 == ~m_st~0 [L521] ~__retres1~7 := 1; [L558] #res := ~__retres1~7; [L570] ~tmp~0 := #t~ret2; [L570] havoc #t~ret2; [L572-L576] COND TRUE 0 != ~tmp~0 [L577] COND TRUE 0 == ~m_st~0 [L578] havoc ~tmp_ndt_1~0; [L579] ~tmp_ndt_1~0 := #t~nondet3; [L579] havoc #t~nondet3; [L580-L587] COND FALSE !(0 != ~tmp_ndt_1~0) [L591] COND TRUE 0 == ~t1_st~0 [L592] havoc ~tmp_ndt_2~0; [L593] ~tmp_ndt_2~0 := #t~nondet4; [L593] havoc #t~nondet4; [L594-L601] COND FALSE !(0 != ~tmp_ndt_2~0) [L605] COND TRUE 0 == ~t2_st~0 [L606] havoc ~tmp_ndt_3~0; [L607] ~tmp_ndt_3~0 := #t~nondet5; [L607] havoc #t~nondet5; [L608-L615] COND FALSE !(0 != ~tmp_ndt_3~0) [L619] COND TRUE 0 == ~t3_st~0 [L620] havoc ~tmp_ndt_4~0; [L621] ~tmp_ndt_4~0 := #t~nondet6; [L621] havoc #t~nondet6; [L622-L629] COND FALSE !(0 != ~tmp_ndt_4~0) [L633] COND TRUE 0 == ~t4_st~0 [L634] havoc ~tmp_ndt_5~0; [L635] ~tmp_ndt_5~0 := #t~nondet7; [L635] havoc #t~nondet7; [L636-L643] COND FALSE !(0 != ~tmp_ndt_5~0) [L647] COND TRUE 0 == ~t5_st~0 [L648] havoc ~tmp_ndt_6~0; [L649] ~tmp_ndt_6~0 := #t~nondet8; [L649] havoc #t~nondet8; [L650-L657] COND FALSE !(0 != ~tmp_ndt_6~0) [L661] COND TRUE 0 == ~t6_st~0 [L662] havoc ~tmp_ndt_7~0; [L663] ~tmp_ndt_7~0 := #t~nondet9; [L663] havoc #t~nondet9; [L664-L671] COND FALSE !(0 != ~tmp_ndt_7~0) ----- ----- class de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.CACSL2BoogieBacktranslator [L567-L675] COND FALSE !(false) [L517] havoc ~__retres1~7; [L520] COND TRUE 0 == ~m_st~0 [L521] ~__retres1~7 := 1; [L558] #res := ~__retres1~7; [L570] ~tmp~0 := #t~ret2; [L570] havoc #t~ret2; [L572-L576] COND TRUE 0 != ~tmp~0 [L577] COND TRUE 0 == ~m_st~0 [L578] havoc ~tmp_ndt_1~0; [L579] ~tmp_ndt_1~0 := #t~nondet3; [L579] havoc #t~nondet3; [L580-L587] COND FALSE !(0 != ~tmp_ndt_1~0) [L591] COND TRUE 0 == ~t1_st~0 [L592] havoc ~tmp_ndt_2~0; [L593] ~tmp_ndt_2~0 := #t~nondet4; [L593] havoc #t~nondet4; [L594-L601] COND FALSE !(0 != ~tmp_ndt_2~0) [L605] COND TRUE 0 == ~t2_st~0 [L606] havoc ~tmp_ndt_3~0; [L607] ~tmp_ndt_3~0 := #t~nondet5; [L607] havoc #t~nondet5; [L608-L615] COND FALSE !(0 != ~tmp_ndt_3~0) [L619] COND TRUE 0 == ~t3_st~0 [L620] havoc ~tmp_ndt_4~0; [L621] ~tmp_ndt_4~0 := #t~nondet6; [L621] havoc #t~nondet6; [L622-L629] COND FALSE !(0 != ~tmp_ndt_4~0) [L633] COND TRUE 0 == ~t4_st~0 [L634] havoc ~tmp_ndt_5~0; [L635] ~tmp_ndt_5~0 := #t~nondet7; [L635] havoc #t~nondet7; [L636-L643] COND FALSE !(0 != ~tmp_ndt_5~0) [L647] COND TRUE 0 == ~t5_st~0 [L648] havoc ~tmp_ndt_6~0; [L649] ~tmp_ndt_6~0 := #t~nondet8; [L649] havoc #t~nondet8; [L650-L657] COND FALSE !(0 != ~tmp_ndt_6~0) [L661] COND TRUE 0 == ~t6_st~0 [L662] havoc ~tmp_ndt_7~0; [L663] ~tmp_ndt_7~0 := #t~nondet9; [L663] havoc #t~nondet9; [L664-L671] COND FALSE !(0 != ~tmp_ndt_7~0) [L567] COND TRUE 1 [L517] int __retres1 ; [L520] COND TRUE m_st == 0 [L521] __retres1 = 1 [L558] return (__retres1); [L570] tmp = exists_runnable_thread() [L572] COND TRUE \read(tmp) [L577] COND TRUE m_st == 0 [L578] int tmp_ndt_1; [L579] tmp_ndt_1 = __VERIFIER_nondet_int() [L580] COND FALSE !(\read(tmp_ndt_1)) [L591] COND TRUE t1_st == 0 [L592] int tmp_ndt_2; [L593] tmp_ndt_2 = __VERIFIER_nondet_int() [L594] COND FALSE !(\read(tmp_ndt_2)) [L605] COND TRUE t2_st == 0 [L606] int tmp_ndt_3; [L607] tmp_ndt_3 = __VERIFIER_nondet_int() [L608] COND FALSE !(\read(tmp_ndt_3)) [L619] COND TRUE t3_st == 0 [L620] int tmp_ndt_4; [L621] tmp_ndt_4 = __VERIFIER_nondet_int() [L622] COND FALSE !(\read(tmp_ndt_4)) [L633] COND TRUE t4_st == 0 [L634] int tmp_ndt_5; [L635] tmp_ndt_5 = __VERIFIER_nondet_int() [L636] COND FALSE !(\read(tmp_ndt_5)) [L647] COND TRUE t5_st == 0 [L648] int tmp_ndt_6; [L649] tmp_ndt_6 = __VERIFIER_nondet_int() [L650] COND FALSE !(\read(tmp_ndt_6)) [L661] COND TRUE t6_st == 0 [L662] int tmp_ndt_7; [L663] tmp_ndt_7 = __VERIFIER_nondet_int() [L664] COND FALSE !(\read(tmp_ndt_7)) ----- [2018-11-23 01:28:01,819 INFO L145 WitnessManager]: Wrote witness to /tmp/vcloud-vcloud-master/worker/working_dir_3cb46500-1f11-408a-a24e-b9ac197b8b4e/bin-2019/uautomizer/witness.graphml [2018-11-23 01:28:01,819 INFO L132 PluginConnector]: ------------------------ END Witness Printer---------------------------- [2018-11-23 01:28:01,820 INFO L168 Benchmark]: Toolchain (without parser) took 78065.79 ms. Allocated memory was 1.0 GB in the beginning and 7.4 GB in the end (delta: 6.3 GB). Free memory was 952.7 MB in the beginning and 2.8 GB in the end (delta: -1.9 GB). Peak memory consumption was 4.4 GB. Max. memory is 11.5 GB. [2018-11-23 01:28:01,820 INFO L168 Benchmark]: CDTParser took 0.13 ms. Allocated memory is still 1.0 GB. Free memory is still 980.1 MB. There was no memory consumed. Max. memory is 11.5 GB. [2018-11-23 01:28:01,820 INFO L168 Benchmark]: CACSL2BoogieTranslator took 261.74 ms. Allocated memory is still 1.0 GB. Free memory was 952.7 MB in the beginning and 931.1 MB in the end (delta: 21.6 MB). Peak memory consumption was 21.6 MB. Max. memory is 11.5 GB. [2018-11-23 01:28:01,821 INFO L168 Benchmark]: Boogie Procedure Inliner took 90.78 ms. Allocated memory was 1.0 GB in the beginning and 1.2 GB in the end (delta: 170.9 MB). Free memory was 931.1 MB in the beginning and 1.2 GB in the end (delta: -231.9 MB). Peak memory consumption was 17.7 MB. Max. memory is 11.5 GB. [2018-11-23 01:28:01,821 INFO L168 Benchmark]: Boogie Preprocessor took 49.35 ms. Allocated memory is still 1.2 GB. Free memory was 1.2 GB in the beginning and 1.2 GB in the end (delta: 6.3 MB). Peak memory consumption was 6.3 MB. Max. memory is 11.5 GB. [2018-11-23 01:28:01,821 INFO L168 Benchmark]: RCFGBuilder took 1045.56 ms. Allocated memory is still 1.2 GB. Free memory was 1.2 GB in the beginning and 1.0 GB in the end (delta: 138.4 MB). Peak memory consumption was 138.4 MB. Max. memory is 11.5 GB. [2018-11-23 01:28:01,821 INFO L168 Benchmark]: BuchiAutomizer took 74682.67 ms. Allocated memory was 1.2 GB in the beginning and 7.4 GB in the end (delta: 6.2 GB). Free memory was 1.0 GB in the beginning and 2.8 GB in the end (delta: -1.8 GB). Peak memory consumption was 4.3 GB. Max. memory is 11.5 GB. [2018-11-23 01:28:01,821 INFO L168 Benchmark]: Witness Printer took 1932.29 ms. Allocated memory is still 7.4 GB. Free memory was 2.8 GB in the beginning and 2.8 GB in the end (delta: 96 B). Peak memory consumption was 96 B. Max. memory is 11.5 GB. [2018-11-23 01:28:01,823 INFO L336 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.13 ms. Allocated memory is still 1.0 GB. Free memory is still 980.1 MB. There was no memory consumed. Max. memory is 11.5 GB. * CACSL2BoogieTranslator took 261.74 ms. Allocated memory is still 1.0 GB. Free memory was 952.7 MB in the beginning and 931.1 MB in the end (delta: 21.6 MB). Peak memory consumption was 21.6 MB. Max. memory is 11.5 GB. * Boogie Procedure Inliner took 90.78 ms. Allocated memory was 1.0 GB in the beginning and 1.2 GB in the end (delta: 170.9 MB). Free memory was 931.1 MB in the beginning and 1.2 GB in the end (delta: -231.9 MB). Peak memory consumption was 17.7 MB. Max. memory is 11.5 GB. * Boogie Preprocessor took 49.35 ms. Allocated memory is still 1.2 GB. Free memory was 1.2 GB in the beginning and 1.2 GB in the end (delta: 6.3 MB). Peak memory consumption was 6.3 MB. Max. memory is 11.5 GB. * RCFGBuilder took 1045.56 ms. Allocated memory is still 1.2 GB. Free memory was 1.2 GB in the beginning and 1.0 GB in the end (delta: 138.4 MB). Peak memory consumption was 138.4 MB. Max. memory is 11.5 GB. * BuchiAutomizer took 74682.67 ms. Allocated memory was 1.2 GB in the beginning and 7.4 GB in the end (delta: 6.2 GB). Free memory was 1.0 GB in the beginning and 2.8 GB in the end (delta: -1.8 GB). Peak memory consumption was 4.3 GB. Max. memory is 11.5 GB. * Witness Printer took 1932.29 ms. Allocated memory is still 7.4 GB. Free memory was 2.8 GB in the beginning and 2.8 GB in the end (delta: 96 B). Peak memory consumption was 96 B. Max. memory is 11.5 GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - StatisticsResult: Constructed decomposition of program Your program was decomposed into 38 terminating modules (35 trivial, 3 deterministic, 0 nondeterministic) and one nonterminating remainder module.One deterministic module has affine ranking function -1 * E_4 + 1 and consists of 3 locations. One deterministic module has affine ranking function -1 * T5_E + 1 and consists of 3 locations. One deterministic module has affine ranking function -2 * T4_E + 3 and consists of 3 locations. 35 modules have a trivial ranking function, the largest among these consists of 5 locations. The remainder module has 752852 locations. - StatisticsResult: Timing statistics BüchiAutomizer plugin needed 74.0s and 36 iterations. TraceHistogramMax:2. Analysis of lassos took 10.7s. Construction of modules took 1.6s. Büchi inclusion checks took 6.9s. Highest rank in rank-based complementation 3. Minimization of det autom 26. Minimization of nondet autom 12. Automata minimization 35.8s AutomataMinimizationTime, 38 MinimizatonAttempts, 121785 StatesRemovedByMinimization, 21 NontrivialMinimizations. Non-live state removal took 13.5s Buchi closure took 0.5s. Biggest automaton had 752852 states and ocurred in iteration 35. Nontrivial modules had stage [3, 0, 0, 0, 0]. InterpolantCoveringCapabilityFinite: 0/0 InterpolantCoveringCapabilityBuchi: 12/12 HoareTripleCheckerStatistics: 40439 SDtfs, 45121 SDslu, 38883 SDs, 0 SdLazy, 1263 SolverSat, 563 SolverUnsat, 0 SolverUnknown, 0 SolverNotchecked, 1.6s Time LassoAnalysisResults: nont1 unkn0 SFLI10 SFLT0 conc5 concLT2 SILN1 SILU0 SILI16 SILT1 lasso0 LassoPreprocessingBenchmarks: Lassos: inital248 mio100 ax100 hnf100 lsp4 ukn100 mio100 lsp100 div100 bol100 ite100 ukn100 eq209 hnf86 smp100 dnf189 smp56 tf109 neg97 sie105 LassoTerminationAnalysisBenchmarks: ConstraintsSatisfiability: unsat Degree: 0 Time: 2ms VariablesStem: 0 VariablesLoop: 1 DisjunctsStem: 1 DisjunctsLoop: 2 SupportingInvariants: 0 MotzkinApplications: 4 LassoTerminationAnalysisBenchmarks: LassoNonterminationAnalysisSatFixpoint: 10 LassoNonterminationAnalysisSatUnbounded: 0 LassoNonterminationAnalysisUnsat: 3 LassoNonterminationAnalysisUnknown: 0 LassoNonterminationAnalysisTime: 0.1s - TerminationAnalysisResult: Nontermination possible Buchi Automizer proved that your program is nonterminating for some inputs - FixpointNonTerminationResult [Line: 567]: Nontermination argument in form of an infinite program execution. Nontermination argument in form of an infinite execution State at position 0 is {} State at position 1 is {__retres1=0, t3_st=0, token=0, tmp=1, t5_i=1, __retres1=0, kernel_st=1, \result=0, t2_st=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@74d667db=0, t4_i=1, E_3=2, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@279d2f6c=0, t4_pc=0, E_5=2, T6_E=2, \result=0, E_1=2, tmp_ndt_2=0, \result=0, __retres1=0, \result=0, tmp_ndt_4=0, tmp_ndt_6=0, m_st=0, t6_pc=0, tmp___2=0, tmp___0=0, t3_pc=0, tmp=0, __retres1=0, \result=0, t6_i=1, m_pc=0, tmp___4=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@4cfb4e27=0, \result=0, __retres1=0, t6_st=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@7f64f3b9=0, E_6=2, \result=0, __retres1=0, \result=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@49f23c74=0, T2_E=2, tmp___0=0, t1_pc=0, __retres1=1, t5_st=0, E_2=2, E_4=2, T1_E=2, tmp_ndt_1=0, M_E=2, tmp=0, tmp_ndt_3=0, __retres1=0, T5_E=2, t2_i=1, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@7e22e334=0, T4_E=2, t3_i=1, t4_st=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@629ee969=0, m_i=1, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@7c06f7e=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@5db5c01e=0, t1_st=0, tmp_ndt_5=0, t5_pc=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@34e7bef5=0, __retres1=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@21a7de09=0, local=0, t2_pc=0, tmp_ndt_7=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@2518ee4b=0, tmp___3=0, E_M=2, tmp___1=0, T3_E=2, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@11e7cb3=0, t1_i=1, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@459a7a34=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@199837ee=0, \result=1, tmp___5=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@2acea6fd=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@16cd39c1=0} - StatisticsResult: NonterminationArgumentStatistics Fixpoint - NonterminatingLassoResult [Line: 567]: Nonterminating execution ----- class de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder.RCFGBacktranslator [?] ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0; [?] havoc main_#res;havoc main_~__retres1~8;havoc main_~__retres1~8;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; [?] havoc start_simulation_#t~ret18, start_simulation_#t~ret19, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; [?] assume 1 == ~m_i~0;~m_st~0 := 0; [?] assume 1 == ~t1_i~0;~t1_st~0 := 0; [?] assume 1 == ~t2_i~0;~t2_st~0 := 0; [?] assume 1 == ~t3_i~0;~t3_st~0 := 0; [?] assume 1 == ~t4_i~0;~t4_st~0 := 0; [?] assume 1 == ~t5_i~0;~t5_st~0 := 0; [?] assume 1 == ~t6_i~0;~t6_st~0 := 0; [?] assume !(0 == ~M_E~0); [?] assume !(0 == ~T1_E~0); [?] assume !(0 == ~T2_E~0); [?] assume !(0 == ~T3_E~0); [?] assume !(0 == ~T4_E~0); [?] assume !(0 == ~T5_E~0); [?] assume !(0 == ~T6_E~0); [?] assume !(0 == ~E_M~0); [?] assume !(0 == ~E_1~0); [?] assume !(0 == ~E_2~0); [?] assume !(0 == ~E_3~0); [?] assume !(0 == ~E_4~0); [?] assume !(0 == ~E_5~0); [?] assume !(0 == ~E_6~0); [?] havoc activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; [?] assume !(1 == ~m_pc~0); [?] is_master_triggered_~__retres1~0 := 0; [?] is_master_triggered_#res := is_master_triggered_~__retres1~0; [?] activate_threads_#t~ret10 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; [?] assume !(0 != activate_threads_~tmp~1); [?] havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; [?] assume !(1 == ~t1_pc~0); [?] is_transmit1_triggered_~__retres1~1 := 0; [?] is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; [?] activate_threads_#t~ret11 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; [?] assume !(0 != activate_threads_~tmp___0~0); [?] havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; [?] assume !(1 == ~t2_pc~0); [?] is_transmit2_triggered_~__retres1~2 := 0; [?] is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; [?] activate_threads_#t~ret12 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; [?] assume !(0 != activate_threads_~tmp___1~0); [?] havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; [?] assume !(1 == ~t3_pc~0); [?] is_transmit3_triggered_~__retres1~3 := 0; [?] is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; [?] activate_threads_#t~ret13 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; [?] assume !(0 != activate_threads_~tmp___2~0); [?] havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; [?] assume !(1 == ~t4_pc~0); [?] is_transmit4_triggered_~__retres1~4 := 0; [?] is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; [?] activate_threads_#t~ret14 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; [?] assume !(0 != activate_threads_~tmp___3~0); [?] havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; [?] assume !(1 == ~t5_pc~0); [?] is_transmit5_triggered_~__retres1~5 := 0; [?] is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; [?] activate_threads_#t~ret15 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; [?] assume !(0 != activate_threads_~tmp___4~0); [?] havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; [?] assume !(1 == ~t6_pc~0); [?] is_transmit6_triggered_~__retres1~6 := 0; [?] is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; [?] activate_threads_#t~ret16 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; [?] assume !(0 != activate_threads_~tmp___5~0); [?] assume !(1 == ~M_E~0); [?] assume !(1 == ~T1_E~0); [?] assume !(1 == ~T2_E~0); [?] assume !(1 == ~T3_E~0); [?] assume !(1 == ~T4_E~0); [?] assume !(1 == ~T5_E~0); [?] assume !(1 == ~T6_E~0); [?] assume !(1 == ~E_M~0); [?] assume !(1 == ~E_1~0); [?] assume !(1 == ~E_2~0); [?] assume !(1 == ~E_3~0); [?] assume !(1 == ~E_4~0); [?] assume !(1 == ~E_5~0); [?] assume !(1 == ~E_6~0); [?] assume !false; [?] start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret2, eval_#t~nondet3, eval_~tmp_ndt_1~0, eval_#t~nondet4, eval_~tmp_ndt_2~0, eval_#t~nondet5, eval_~tmp_ndt_3~0, eval_#t~nondet6, eval_~tmp_ndt_4~0, eval_#t~nondet7, eval_~tmp_ndt_5~0, eval_#t~nondet8, eval_~tmp_ndt_6~0, eval_#t~nondet9, eval_~tmp_ndt_7~0, eval_~tmp~0;havoc eval_~tmp~0; [L14] ~m_pc~0 := 0; [L15] ~t1_pc~0 := 0; [L16] ~t2_pc~0 := 0; [L17] ~t3_pc~0 := 0; [L18] ~t4_pc~0 := 0; [L19] ~t5_pc~0 := 0; [L20] ~t6_pc~0 := 0; [L21] ~m_st~0 := 0; [L22] ~t1_st~0 := 0; [L23] ~t2_st~0 := 0; [L24] ~t3_st~0 := 0; [L25] ~t4_st~0 := 0; [L26] ~t5_st~0 := 0; [L27] ~t6_st~0 := 0; [L28] ~m_i~0 := 0; [L29] ~t1_i~0 := 0; [L30] ~t2_i~0 := 0; [L31] ~t3_i~0 := 0; [L32] ~t4_i~0 := 0; [L33] ~t5_i~0 := 0; [L34] ~t6_i~0 := 0; [L35] ~M_E~0 := 2; [L36] ~T1_E~0 := 2; [L37] ~T2_E~0 := 2; [L38] ~T3_E~0 := 2; [L39] ~T4_E~0 := 2; [L40] ~T5_E~0 := 2; [L41] ~T6_E~0 := 2; [L42] ~E_M~0 := 2; [L43] ~E_1~0 := 2; [L44] ~E_2~0 := 2; [L45] ~E_3~0 := 2; [L46] ~E_4~0 := 2; [L47] ~E_5~0 := 2; [L48] ~E_6~0 := 2; [L57] ~token~0 := 0; [L59] ~local~0 := 0; [?] havoc main_#res; [?] havoc main_~__retres1~8; [L1100] havoc main_~__retres1~8; [L1010] ~m_i~0 := 1; [L1011] ~t1_i~0 := 1; [L1012] ~t2_i~0 := 1; [L1013] ~t3_i~0 := 1; [L1014] ~t4_i~0 := 1; [L1015] ~t5_i~0 := 1; [L1016] ~t6_i~0 := 1; [L1105] havoc start_simulation_#t~ret18, start_simulation_#t~ret19, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1; [L1041] havoc start_simulation_~kernel_st~0; [L1042] havoc start_simulation_~tmp~3; [L1043] havoc start_simulation_~tmp___0~1; [L1047] start_simulation_~kernel_st~0 := 0; [L477-L481] assume 1 == ~m_i~0; [L478] ~m_st~0 := 0; [L482-L486] assume 1 == ~t1_i~0; [L483] ~t1_st~0 := 0; [L487-L491] assume 1 == ~t2_i~0; [L488] ~t2_st~0 := 0; [L492-L496] assume 1 == ~t3_i~0; [L493] ~t3_st~0 := 0; [L497-L501] assume 1 == ~t4_i~0; [L498] ~t4_st~0 := 0; [L502-L506] assume 1 == ~t5_i~0; [L503] ~t5_st~0 := 0; [L507-L511] assume 1 == ~t6_i~0; [L508] ~t6_st~0 := 0; [L686-L690] assume !(0 == ~M_E~0); [L691-L695] assume !(0 == ~T1_E~0); [L696-L700] assume !(0 == ~T2_E~0); [L701-L705] assume !(0 == ~T3_E~0); [L706-L710] assume !(0 == ~T4_E~0); [L711-L715] assume !(0 == ~T5_E~0); [L716-L720] assume !(0 == ~T6_E~0); [L721-L725] assume !(0 == ~E_M~0); [L726-L730] assume !(0 == ~E_1~0); [L731-L735] assume !(0 == ~E_2~0); [L736-L740] assume !(0 == ~E_3~0); [L741-L745] assume !(0 == ~E_4~0); [L746-L750] assume !(0 == ~E_5~0); [L751-L755] assume !(0 == ~E_6~0); [L1051] havoc activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0; [L839] havoc activate_threads_~tmp~1; [L840] havoc activate_threads_~tmp___0~0; [L841] havoc activate_threads_~tmp___1~0; [L842] havoc activate_threads_~tmp___2~0; [L843] havoc activate_threads_~tmp___3~0; [L844] havoc activate_threads_~tmp___4~0; [L845] havoc activate_threads_~tmp___5~0; [L849] havoc is_master_triggered_#res; [L849] havoc is_master_triggered_~__retres1~0; [L333] havoc is_master_triggered_~__retres1~0; [L336-L345] assume !(1 == ~m_pc~0); [L346] is_master_triggered_~__retres1~0 := 0; [L348] is_master_triggered_#res := is_master_triggered_~__retres1~0; [L849] activate_threads_#t~ret10 := is_master_triggered_#res; [L849] activate_threads_~tmp~1 := activate_threads_#t~ret10; [L849] havoc activate_threads_#t~ret10; [L851-L855] assume !(0 != activate_threads_~tmp~1); [L857] havoc is_transmit1_triggered_#res; [L857] havoc is_transmit1_triggered_~__retres1~1; [L352] havoc is_transmit1_triggered_~__retres1~1; [L355-L364] assume !(1 == ~t1_pc~0); [L365] is_transmit1_triggered_~__retres1~1 := 0; [L367] is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; [L857] activate_threads_#t~ret11 := is_transmit1_triggered_#res; [L857] activate_threads_~tmp___0~0 := activate_threads_#t~ret11; [L857] havoc activate_threads_#t~ret11; [L859-L863] assume !(0 != activate_threads_~tmp___0~0); [L865] havoc is_transmit2_triggered_#res; [L865] havoc is_transmit2_triggered_~__retres1~2; [L371] havoc is_transmit2_triggered_~__retres1~2; [L374-L383] assume !(1 == ~t2_pc~0); [L384] is_transmit2_triggered_~__retres1~2 := 0; [L386] is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; [L865] activate_threads_#t~ret12 := is_transmit2_triggered_#res; [L865] activate_threads_~tmp___1~0 := activate_threads_#t~ret12; [L865] havoc activate_threads_#t~ret12; [L867-L871] assume !(0 != activate_threads_~tmp___1~0); [L873] havoc is_transmit3_triggered_#res; [L873] havoc is_transmit3_triggered_~__retres1~3; [L390] havoc is_transmit3_triggered_~__retres1~3; [L393-L402] assume !(1 == ~t3_pc~0); [L403] is_transmit3_triggered_~__retres1~3 := 0; [L405] is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; [L873] activate_threads_#t~ret13 := is_transmit3_triggered_#res; [L873] activate_threads_~tmp___2~0 := activate_threads_#t~ret13; [L873] havoc activate_threads_#t~ret13; [L875-L879] assume !(0 != activate_threads_~tmp___2~0); [L881] havoc is_transmit4_triggered_#res; [L881] havoc is_transmit4_triggered_~__retres1~4; [L409] havoc is_transmit4_triggered_~__retres1~4; [L412-L421] assume !(1 == ~t4_pc~0); [L422] is_transmit4_triggered_~__retres1~4 := 0; [L424] is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; [L881] activate_threads_#t~ret14 := is_transmit4_triggered_#res; [L881] activate_threads_~tmp___3~0 := activate_threads_#t~ret14; [L881] havoc activate_threads_#t~ret14; [L883-L887] assume !(0 != activate_threads_~tmp___3~0); [L889] havoc is_transmit5_triggered_#res; [L889] havoc is_transmit5_triggered_~__retres1~5; [L428] havoc is_transmit5_triggered_~__retres1~5; [L431-L440] assume !(1 == ~t5_pc~0); [L441] is_transmit5_triggered_~__retres1~5 := 0; [L443] is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; [L889] activate_threads_#t~ret15 := is_transmit5_triggered_#res; [L889] activate_threads_~tmp___4~0 := activate_threads_#t~ret15; [L889] havoc activate_threads_#t~ret15; [L891-L895] assume !(0 != activate_threads_~tmp___4~0); [L897] havoc is_transmit6_triggered_#res; [L897] havoc is_transmit6_triggered_~__retres1~6; [L447] havoc is_transmit6_triggered_~__retres1~6; [L450-L459] assume !(1 == ~t6_pc~0); [L460] is_transmit6_triggered_~__retres1~6 := 0; [L462] is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; [L897] activate_threads_#t~ret16 := is_transmit6_triggered_#res; [L897] activate_threads_~tmp___5~0 := activate_threads_#t~ret16; [L897] havoc activate_threads_#t~ret16; [L899-L903] assume !(0 != activate_threads_~tmp___5~0); [L764-L768] assume !(1 == ~M_E~0); [L769-L773] assume !(1 == ~T1_E~0); [L774-L778] assume !(1 == ~T2_E~0); [L779-L783] assume !(1 == ~T3_E~0); [L784-L788] assume !(1 == ~T4_E~0); [L789-L793] assume !(1 == ~T5_E~0); [L794-L798] assume !(1 == ~T6_E~0); [L799-L803] assume !(1 == ~E_M~0); [L804-L808] assume !(1 == ~E_1~0); [L809-L813] assume !(1 == ~E_2~0); [L814-L818] assume !(1 == ~E_3~0); [L819-L823] assume !(1 == ~E_4~0); [L824-L828] assume !(1 == ~E_5~0); [L829-L833] assume !(1 == ~E_6~0); [L1055-L1092] assume !false; [L1058] start_simulation_~kernel_st~0 := 1; [L1059] havoc eval_#t~ret2, eval_#t~nondet3, eval_~tmp_ndt_1~0, eval_#t~nondet4, eval_~tmp_ndt_2~0, eval_#t~nondet5, eval_~tmp_ndt_3~0, eval_#t~nondet6, eval_~tmp_ndt_4~0, eval_#t~nondet7, eval_~tmp_ndt_5~0, eval_#t~nondet8, eval_~tmp_ndt_6~0, eval_#t~nondet9, eval_~tmp_ndt_7~0, eval_~tmp~0; [L563] havoc eval_~tmp~0; ----- ----- class de.uni_freiburg.informatik.ultimate.boogie.preprocessor.BoogiePreprocessorBacktranslator [L14] ~m_pc~0 := 0; [L15] ~t1_pc~0 := 0; [L16] ~t2_pc~0 := 0; [L17] ~t3_pc~0 := 0; [L18] ~t4_pc~0 := 0; [L19] ~t5_pc~0 := 0; [L20] ~t6_pc~0 := 0; [L21] ~m_st~0 := 0; [L22] ~t1_st~0 := 0; [L23] ~t2_st~0 := 0; [L24] ~t3_st~0 := 0; [L25] ~t4_st~0 := 0; [L26] ~t5_st~0 := 0; [L27] ~t6_st~0 := 0; [L28] ~m_i~0 := 0; [L29] ~t1_i~0 := 0; [L30] ~t2_i~0 := 0; [L31] ~t3_i~0 := 0; [L32] ~t4_i~0 := 0; [L33] ~t5_i~0 := 0; [L34] ~t6_i~0 := 0; [L35] ~M_E~0 := 2; [L36] ~T1_E~0 := 2; [L37] ~T2_E~0 := 2; [L38] ~T3_E~0 := 2; [L39] ~T4_E~0 := 2; [L40] ~T5_E~0 := 2; [L41] ~T6_E~0 := 2; [L42] ~E_M~0 := 2; [L43] ~E_1~0 := 2; [L44] ~E_2~0 := 2; [L45] ~E_3~0 := 2; [L46] ~E_4~0 := 2; [L47] ~E_5~0 := 2; [L48] ~E_6~0 := 2; [L57] ~token~0 := 0; [L59] ~local~0 := 0; [?] havoc main_#res; [?] havoc main_~__retres1~8; [L1100] havoc main_~__retres1~8; [L1010] ~m_i~0 := 1; [L1011] ~t1_i~0 := 1; [L1012] ~t2_i~0 := 1; [L1013] ~t3_i~0 := 1; [L1014] ~t4_i~0 := 1; [L1015] ~t5_i~0 := 1; [L1016] ~t6_i~0 := 1; [L1105] havoc start_simulation_#t~ret18, start_simulation_#t~ret19, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1; [L1041] havoc start_simulation_~kernel_st~0; [L1042] havoc start_simulation_~tmp~3; [L1043] havoc start_simulation_~tmp___0~1; [L1047] start_simulation_~kernel_st~0 := 0; [L477-L481] assume 1 == ~m_i~0; [L478] ~m_st~0 := 0; [L482-L486] assume 1 == ~t1_i~0; [L483] ~t1_st~0 := 0; [L487-L491] assume 1 == ~t2_i~0; [L488] ~t2_st~0 := 0; [L492-L496] assume 1 == ~t3_i~0; [L493] ~t3_st~0 := 0; [L497-L501] assume 1 == ~t4_i~0; [L498] ~t4_st~0 := 0; [L502-L506] assume 1 == ~t5_i~0; [L503] ~t5_st~0 := 0; [L507-L511] assume 1 == ~t6_i~0; [L508] ~t6_st~0 := 0; [L686-L690] assume !(0 == ~M_E~0); [L691-L695] assume !(0 == ~T1_E~0); [L696-L700] assume !(0 == ~T2_E~0); [L701-L705] assume !(0 == ~T3_E~0); [L706-L710] assume !(0 == ~T4_E~0); [L711-L715] assume !(0 == ~T5_E~0); [L716-L720] assume !(0 == ~T6_E~0); [L721-L725] assume !(0 == ~E_M~0); [L726-L730] assume !(0 == ~E_1~0); [L731-L735] assume !(0 == ~E_2~0); [L736-L740] assume !(0 == ~E_3~0); [L741-L745] assume !(0 == ~E_4~0); [L746-L750] assume !(0 == ~E_5~0); [L751-L755] assume !(0 == ~E_6~0); [L1051] havoc activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0; [L839] havoc activate_threads_~tmp~1; [L840] havoc activate_threads_~tmp___0~0; [L841] havoc activate_threads_~tmp___1~0; [L842] havoc activate_threads_~tmp___2~0; [L843] havoc activate_threads_~tmp___3~0; [L844] havoc activate_threads_~tmp___4~0; [L845] havoc activate_threads_~tmp___5~0; [L849] havoc is_master_triggered_#res; [L849] havoc is_master_triggered_~__retres1~0; [L333] havoc is_master_triggered_~__retres1~0; [L336-L345] assume !(1 == ~m_pc~0); [L346] is_master_triggered_~__retres1~0 := 0; [L348] is_master_triggered_#res := is_master_triggered_~__retres1~0; [L849] activate_threads_#t~ret10 := is_master_triggered_#res; [L849] activate_threads_~tmp~1 := activate_threads_#t~ret10; [L849] havoc activate_threads_#t~ret10; [L851-L855] assume !(0 != activate_threads_~tmp~1); [L857] havoc is_transmit1_triggered_#res; [L857] havoc is_transmit1_triggered_~__retres1~1; [L352] havoc is_transmit1_triggered_~__retres1~1; [L355-L364] assume !(1 == ~t1_pc~0); [L365] is_transmit1_triggered_~__retres1~1 := 0; [L367] is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; [L857] activate_threads_#t~ret11 := is_transmit1_triggered_#res; [L857] activate_threads_~tmp___0~0 := activate_threads_#t~ret11; [L857] havoc activate_threads_#t~ret11; [L859-L863] assume !(0 != activate_threads_~tmp___0~0); [L865] havoc is_transmit2_triggered_#res; [L865] havoc is_transmit2_triggered_~__retres1~2; [L371] havoc is_transmit2_triggered_~__retres1~2; [L374-L383] assume !(1 == ~t2_pc~0); [L384] is_transmit2_triggered_~__retres1~2 := 0; [L386] is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; [L865] activate_threads_#t~ret12 := is_transmit2_triggered_#res; [L865] activate_threads_~tmp___1~0 := activate_threads_#t~ret12; [L865] havoc activate_threads_#t~ret12; [L867-L871] assume !(0 != activate_threads_~tmp___1~0); [L873] havoc is_transmit3_triggered_#res; [L873] havoc is_transmit3_triggered_~__retres1~3; [L390] havoc is_transmit3_triggered_~__retres1~3; [L393-L402] assume !(1 == ~t3_pc~0); [L403] is_transmit3_triggered_~__retres1~3 := 0; [L405] is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; [L873] activate_threads_#t~ret13 := is_transmit3_triggered_#res; [L873] activate_threads_~tmp___2~0 := activate_threads_#t~ret13; [L873] havoc activate_threads_#t~ret13; [L875-L879] assume !(0 != activate_threads_~tmp___2~0); [L881] havoc is_transmit4_triggered_#res; [L881] havoc is_transmit4_triggered_~__retres1~4; [L409] havoc is_transmit4_triggered_~__retres1~4; [L412-L421] assume !(1 == ~t4_pc~0); [L422] is_transmit4_triggered_~__retres1~4 := 0; [L424] is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; [L881] activate_threads_#t~ret14 := is_transmit4_triggered_#res; [L881] activate_threads_~tmp___3~0 := activate_threads_#t~ret14; [L881] havoc activate_threads_#t~ret14; [L883-L887] assume !(0 != activate_threads_~tmp___3~0); [L889] havoc is_transmit5_triggered_#res; [L889] havoc is_transmit5_triggered_~__retres1~5; [L428] havoc is_transmit5_triggered_~__retres1~5; [L431-L440] assume !(1 == ~t5_pc~0); [L441] is_transmit5_triggered_~__retres1~5 := 0; [L443] is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; [L889] activate_threads_#t~ret15 := is_transmit5_triggered_#res; [L889] activate_threads_~tmp___4~0 := activate_threads_#t~ret15; [L889] havoc activate_threads_#t~ret15; [L891-L895] assume !(0 != activate_threads_~tmp___4~0); [L897] havoc is_transmit6_triggered_#res; [L897] havoc is_transmit6_triggered_~__retres1~6; [L447] havoc is_transmit6_triggered_~__retres1~6; [L450-L459] assume !(1 == ~t6_pc~0); [L460] is_transmit6_triggered_~__retres1~6 := 0; [L462] is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; [L897] activate_threads_#t~ret16 := is_transmit6_triggered_#res; [L897] activate_threads_~tmp___5~0 := activate_threads_#t~ret16; [L897] havoc activate_threads_#t~ret16; [L899-L903] assume !(0 != activate_threads_~tmp___5~0); [L764-L768] assume !(1 == ~M_E~0); [L769-L773] assume !(1 == ~T1_E~0); [L774-L778] assume !(1 == ~T2_E~0); [L779-L783] assume !(1 == ~T3_E~0); [L784-L788] assume !(1 == ~T4_E~0); [L789-L793] assume !(1 == ~T5_E~0); [L794-L798] assume !(1 == ~T6_E~0); [L799-L803] assume !(1 == ~E_M~0); [L804-L808] assume !(1 == ~E_1~0); [L809-L813] assume !(1 == ~E_2~0); [L814-L818] assume !(1 == ~E_3~0); [L819-L823] assume !(1 == ~E_4~0); [L824-L828] assume !(1 == ~E_5~0); [L829-L833] assume !(1 == ~E_6~0); [L1055-L1092] assume !false; [L1058] start_simulation_~kernel_st~0 := 1; [L1059] havoc eval_#t~ret2, eval_#t~nondet3, eval_~tmp_ndt_1~0, eval_#t~nondet4, eval_~tmp_ndt_2~0, eval_#t~nondet5, eval_~tmp_ndt_3~0, eval_#t~nondet6, eval_~tmp_ndt_4~0, eval_#t~nondet7, eval_~tmp_ndt_5~0, eval_#t~nondet8, eval_~tmp_ndt_6~0, eval_#t~nondet9, eval_~tmp_ndt_7~0, eval_~tmp~0; [L563] havoc eval_~tmp~0; [L14] ~m_pc~0 := 0; [L15] ~t1_pc~0 := 0; [L16] ~t2_pc~0 := 0; [L17] ~t3_pc~0 := 0; [L18] ~t4_pc~0 := 0; [L19] ~t5_pc~0 := 0; [L20] ~t6_pc~0 := 0; [L21] ~m_st~0 := 0; [L22] ~t1_st~0 := 0; [L23] ~t2_st~0 := 0; [L24] ~t3_st~0 := 0; [L25] ~t4_st~0 := 0; [L26] ~t5_st~0 := 0; [L27] ~t6_st~0 := 0; [L28] ~m_i~0 := 0; [L29] ~t1_i~0 := 0; [L30] ~t2_i~0 := 0; [L31] ~t3_i~0 := 0; [L32] ~t4_i~0 := 0; [L33] ~t5_i~0 := 0; [L34] ~t6_i~0 := 0; [L35] ~M_E~0 := 2; [L36] ~T1_E~0 := 2; [L37] ~T2_E~0 := 2; [L38] ~T3_E~0 := 2; [L39] ~T4_E~0 := 2; [L40] ~T5_E~0 := 2; [L41] ~T6_E~0 := 2; [L42] ~E_M~0 := 2; [L43] ~E_1~0 := 2; [L44] ~E_2~0 := 2; [L45] ~E_3~0 := 2; [L46] ~E_4~0 := 2; [L47] ~E_5~0 := 2; [L48] ~E_6~0 := 2; [L57] ~token~0 := 0; [L59] ~local~0 := 0; [?] havoc main_#res; [?] havoc main_~__retres1~8; [L1100] havoc main_~__retres1~8; [L1010] ~m_i~0 := 1; [L1011] ~t1_i~0 := 1; [L1012] ~t2_i~0 := 1; [L1013] ~t3_i~0 := 1; [L1014] ~t4_i~0 := 1; [L1015] ~t5_i~0 := 1; [L1016] ~t6_i~0 := 1; [L1105] havoc start_simulation_#t~ret18, start_simulation_#t~ret19, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1; [L1041] havoc start_simulation_~kernel_st~0; [L1042] havoc start_simulation_~tmp~3; [L1043] havoc start_simulation_~tmp___0~1; [L1047] start_simulation_~kernel_st~0 := 0; [L477] COND TRUE 1 == ~m_i~0 [L478] ~m_st~0 := 0; [L482] COND TRUE 1 == ~t1_i~0 [L483] ~t1_st~0 := 0; [L487] COND TRUE 1 == ~t2_i~0 [L488] ~t2_st~0 := 0; [L492] COND TRUE 1 == ~t3_i~0 [L493] ~t3_st~0 := 0; [L497] COND TRUE 1 == ~t4_i~0 [L498] ~t4_st~0 := 0; [L502] COND TRUE 1 == ~t5_i~0 [L503] ~t5_st~0 := 0; [L507] COND TRUE 1 == ~t6_i~0 [L508] ~t6_st~0 := 0; [L686] COND FALSE !(0 == ~M_E~0) [L691] COND FALSE !(0 == ~T1_E~0) [L696] COND FALSE !(0 == ~T2_E~0) [L701] COND FALSE !(0 == ~T3_E~0) [L706] COND FALSE !(0 == ~T4_E~0) [L711] COND FALSE !(0 == ~T5_E~0) [L716] COND FALSE !(0 == ~T6_E~0) [L721] COND FALSE !(0 == ~E_M~0) [L726] COND FALSE !(0 == ~E_1~0) [L731] COND FALSE !(0 == ~E_2~0) [L736] COND FALSE !(0 == ~E_3~0) [L741] COND FALSE !(0 == ~E_4~0) [L746] COND FALSE !(0 == ~E_5~0) [L751] COND FALSE !(0 == ~E_6~0) [L1051] havoc activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0; [L839] havoc activate_threads_~tmp~1; [L840] havoc activate_threads_~tmp___0~0; [L841] havoc activate_threads_~tmp___1~0; [L842] havoc activate_threads_~tmp___2~0; [L843] havoc activate_threads_~tmp___3~0; [L844] havoc activate_threads_~tmp___4~0; [L845] havoc activate_threads_~tmp___5~0; [L849] havoc is_master_triggered_#res; [L849] havoc is_master_triggered_~__retres1~0; [L333] havoc is_master_triggered_~__retres1~0; [L336] COND FALSE !(1 == ~m_pc~0) [L346] is_master_triggered_~__retres1~0 := 0; [L348] is_master_triggered_#res := is_master_triggered_~__retres1~0; [L849] activate_threads_#t~ret10 := is_master_triggered_#res; [L849] activate_threads_~tmp~1 := activate_threads_#t~ret10; [L849] havoc activate_threads_#t~ret10; [L851-L855] COND FALSE !(0 != activate_threads_~tmp~1) [L857] havoc is_transmit1_triggered_#res; [L857] havoc is_transmit1_triggered_~__retres1~1; [L352] havoc is_transmit1_triggered_~__retres1~1; [L355] COND FALSE !(1 == ~t1_pc~0) [L365] is_transmit1_triggered_~__retres1~1 := 0; [L367] is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; [L857] activate_threads_#t~ret11 := is_transmit1_triggered_#res; [L857] activate_threads_~tmp___0~0 := activate_threads_#t~ret11; [L857] havoc activate_threads_#t~ret11; [L859-L863] COND FALSE !(0 != activate_threads_~tmp___0~0) [L865] havoc is_transmit2_triggered_#res; [L865] havoc is_transmit2_triggered_~__retres1~2; [L371] havoc is_transmit2_triggered_~__retres1~2; [L374] COND FALSE !(1 == ~t2_pc~0) [L384] is_transmit2_triggered_~__retres1~2 := 0; [L386] is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; [L865] activate_threads_#t~ret12 := is_transmit2_triggered_#res; [L865] activate_threads_~tmp___1~0 := activate_threads_#t~ret12; [L865] havoc activate_threads_#t~ret12; [L867-L871] COND FALSE !(0 != activate_threads_~tmp___1~0) [L873] havoc is_transmit3_triggered_#res; [L873] havoc is_transmit3_triggered_~__retres1~3; [L390] havoc is_transmit3_triggered_~__retres1~3; [L393] COND FALSE !(1 == ~t3_pc~0) [L403] is_transmit3_triggered_~__retres1~3 := 0; [L405] is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; [L873] activate_threads_#t~ret13 := is_transmit3_triggered_#res; [L873] activate_threads_~tmp___2~0 := activate_threads_#t~ret13; [L873] havoc activate_threads_#t~ret13; [L875-L879] COND FALSE !(0 != activate_threads_~tmp___2~0) [L881] havoc is_transmit4_triggered_#res; [L881] havoc is_transmit4_triggered_~__retres1~4; [L409] havoc is_transmit4_triggered_~__retres1~4; [L412] COND FALSE !(1 == ~t4_pc~0) [L422] is_transmit4_triggered_~__retres1~4 := 0; [L424] is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; [L881] activate_threads_#t~ret14 := is_transmit4_triggered_#res; [L881] activate_threads_~tmp___3~0 := activate_threads_#t~ret14; [L881] havoc activate_threads_#t~ret14; [L883-L887] COND FALSE !(0 != activate_threads_~tmp___3~0) [L889] havoc is_transmit5_triggered_#res; [L889] havoc is_transmit5_triggered_~__retres1~5; [L428] havoc is_transmit5_triggered_~__retres1~5; [L431] COND FALSE !(1 == ~t5_pc~0) [L441] is_transmit5_triggered_~__retres1~5 := 0; [L443] is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; [L889] activate_threads_#t~ret15 := is_transmit5_triggered_#res; [L889] activate_threads_~tmp___4~0 := activate_threads_#t~ret15; [L889] havoc activate_threads_#t~ret15; [L891-L895] COND FALSE !(0 != activate_threads_~tmp___4~0) [L897] havoc is_transmit6_triggered_#res; [L897] havoc is_transmit6_triggered_~__retres1~6; [L447] havoc is_transmit6_triggered_~__retres1~6; [L450] COND FALSE !(1 == ~t6_pc~0) [L460] is_transmit6_triggered_~__retres1~6 := 0; [L462] is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; [L897] activate_threads_#t~ret16 := is_transmit6_triggered_#res; [L897] activate_threads_~tmp___5~0 := activate_threads_#t~ret16; [L897] havoc activate_threads_#t~ret16; [L899-L903] COND FALSE !(0 != activate_threads_~tmp___5~0) [L764] COND FALSE !(1 == ~M_E~0) [L769] COND FALSE !(1 == ~T1_E~0) [L774] COND FALSE !(1 == ~T2_E~0) [L779] COND FALSE !(1 == ~T3_E~0) [L784] COND FALSE !(1 == ~T4_E~0) [L789] COND FALSE !(1 == ~T5_E~0) [L794] COND FALSE !(1 == ~T6_E~0) [L799] COND FALSE !(1 == ~E_M~0) [L804] COND FALSE !(1 == ~E_1~0) [L809] COND FALSE !(1 == ~E_2~0) [L814] COND FALSE !(1 == ~E_3~0) [L819] COND FALSE !(1 == ~E_4~0) [L824] COND FALSE !(1 == ~E_5~0) [L829] COND FALSE !(1 == ~E_6~0) [L1055-L1092] COND FALSE !(false) [L1058] start_simulation_~kernel_st~0 := 1; [L1059] havoc eval_#t~ret2, eval_#t~nondet3, eval_~tmp_ndt_1~0, eval_#t~nondet4, eval_~tmp_ndt_2~0, eval_#t~nondet5, eval_~tmp_ndt_3~0, eval_#t~nondet6, eval_~tmp_ndt_4~0, eval_#t~nondet7, eval_~tmp_ndt_5~0, eval_#t~nondet8, eval_~tmp_ndt_6~0, eval_#t~nondet9, eval_~tmp_ndt_7~0, eval_~tmp~0; [L563] havoc eval_~tmp~0; ----- ----- class de.uni_freiburg.informatik.ultimate.boogie.procedureinliner.backtranslation.InlinerBacktranslator [L14] ~m_pc~0 := 0; [L15] ~t1_pc~0 := 0; [L16] ~t2_pc~0 := 0; [L17] ~t3_pc~0 := 0; [L18] ~t4_pc~0 := 0; [L19] ~t5_pc~0 := 0; [L20] ~t6_pc~0 := 0; [L21] ~m_st~0 := 0; [L22] ~t1_st~0 := 0; [L23] ~t2_st~0 := 0; [L24] ~t3_st~0 := 0; [L25] ~t4_st~0 := 0; [L26] ~t5_st~0 := 0; [L27] ~t6_st~0 := 0; [L28] ~m_i~0 := 0; [L29] ~t1_i~0 := 0; [L30] ~t2_i~0 := 0; [L31] ~t3_i~0 := 0; [L32] ~t4_i~0 := 0; [L33] ~t5_i~0 := 0; [L34] ~t6_i~0 := 0; [L35] ~M_E~0 := 2; [L36] ~T1_E~0 := 2; [L37] ~T2_E~0 := 2; [L38] ~T3_E~0 := 2; [L39] ~T4_E~0 := 2; [L40] ~T5_E~0 := 2; [L41] ~T6_E~0 := 2; [L42] ~E_M~0 := 2; [L43] ~E_1~0 := 2; [L44] ~E_2~0 := 2; [L45] ~E_3~0 := 2; [L46] ~E_4~0 := 2; [L47] ~E_5~0 := 2; [L48] ~E_6~0 := 2; [L57] ~token~0 := 0; [L59] ~local~0 := 0; [?] havoc main_#res; [?] havoc main_~__retres1~8; [L1100] havoc main_~__retres1~8; [L1010] ~m_i~0 := 1; [L1011] ~t1_i~0 := 1; [L1012] ~t2_i~0 := 1; [L1013] ~t3_i~0 := 1; [L1014] ~t4_i~0 := 1; [L1015] ~t5_i~0 := 1; [L1016] ~t6_i~0 := 1; [L1105] havoc start_simulation_#t~ret18, start_simulation_#t~ret19, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1; [L1041] havoc start_simulation_~kernel_st~0; [L1042] havoc start_simulation_~tmp~3; [L1043] havoc start_simulation_~tmp___0~1; [L1047] start_simulation_~kernel_st~0 := 0; [L477] COND TRUE 1 == ~m_i~0 [L478] ~m_st~0 := 0; [L482] COND TRUE 1 == ~t1_i~0 [L483] ~t1_st~0 := 0; [L487] COND TRUE 1 == ~t2_i~0 [L488] ~t2_st~0 := 0; [L492] COND TRUE 1 == ~t3_i~0 [L493] ~t3_st~0 := 0; [L497] COND TRUE 1 == ~t4_i~0 [L498] ~t4_st~0 := 0; [L502] COND TRUE 1 == ~t5_i~0 [L503] ~t5_st~0 := 0; [L507] COND TRUE 1 == ~t6_i~0 [L508] ~t6_st~0 := 0; [L686] COND FALSE !(0 == ~M_E~0) [L691] COND FALSE !(0 == ~T1_E~0) [L696] COND FALSE !(0 == ~T2_E~0) [L701] COND FALSE !(0 == ~T3_E~0) [L706] COND FALSE !(0 == ~T4_E~0) [L711] COND FALSE !(0 == ~T5_E~0) [L716] COND FALSE !(0 == ~T6_E~0) [L721] COND FALSE !(0 == ~E_M~0) [L726] COND FALSE !(0 == ~E_1~0) [L731] COND FALSE !(0 == ~E_2~0) [L736] COND FALSE !(0 == ~E_3~0) [L741] COND FALSE !(0 == ~E_4~0) [L746] COND FALSE !(0 == ~E_5~0) [L751] COND FALSE !(0 == ~E_6~0) [L1051] havoc activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0; [L839] havoc activate_threads_~tmp~1; [L840] havoc activate_threads_~tmp___0~0; [L841] havoc activate_threads_~tmp___1~0; [L842] havoc activate_threads_~tmp___2~0; [L843] havoc activate_threads_~tmp___3~0; [L844] havoc activate_threads_~tmp___4~0; [L845] havoc activate_threads_~tmp___5~0; [L849] havoc is_master_triggered_#res; [L849] havoc is_master_triggered_~__retres1~0; [L333] havoc is_master_triggered_~__retres1~0; [L336] COND FALSE !(1 == ~m_pc~0) [L346] is_master_triggered_~__retres1~0 := 0; [L348] is_master_triggered_#res := is_master_triggered_~__retres1~0; [L849] activate_threads_#t~ret10 := is_master_triggered_#res; [L849] activate_threads_~tmp~1 := activate_threads_#t~ret10; [L849] havoc activate_threads_#t~ret10; [L851-L855] COND FALSE !(0 != activate_threads_~tmp~1) [L857] havoc is_transmit1_triggered_#res; [L857] havoc is_transmit1_triggered_~__retres1~1; [L352] havoc is_transmit1_triggered_~__retres1~1; [L355] COND FALSE !(1 == ~t1_pc~0) [L365] is_transmit1_triggered_~__retres1~1 := 0; [L367] is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; [L857] activate_threads_#t~ret11 := is_transmit1_triggered_#res; [L857] activate_threads_~tmp___0~0 := activate_threads_#t~ret11; [L857] havoc activate_threads_#t~ret11; [L859-L863] COND FALSE !(0 != activate_threads_~tmp___0~0) [L865] havoc is_transmit2_triggered_#res; [L865] havoc is_transmit2_triggered_~__retres1~2; [L371] havoc is_transmit2_triggered_~__retres1~2; [L374] COND FALSE !(1 == ~t2_pc~0) [L384] is_transmit2_triggered_~__retres1~2 := 0; [L386] is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; [L865] activate_threads_#t~ret12 := is_transmit2_triggered_#res; [L865] activate_threads_~tmp___1~0 := activate_threads_#t~ret12; [L865] havoc activate_threads_#t~ret12; [L867-L871] COND FALSE !(0 != activate_threads_~tmp___1~0) [L873] havoc is_transmit3_triggered_#res; [L873] havoc is_transmit3_triggered_~__retres1~3; [L390] havoc is_transmit3_triggered_~__retres1~3; [L393] COND FALSE !(1 == ~t3_pc~0) [L403] is_transmit3_triggered_~__retres1~3 := 0; [L405] is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; [L873] activate_threads_#t~ret13 := is_transmit3_triggered_#res; [L873] activate_threads_~tmp___2~0 := activate_threads_#t~ret13; [L873] havoc activate_threads_#t~ret13; [L875-L879] COND FALSE !(0 != activate_threads_~tmp___2~0) [L881] havoc is_transmit4_triggered_#res; [L881] havoc is_transmit4_triggered_~__retres1~4; [L409] havoc is_transmit4_triggered_~__retres1~4; [L412] COND FALSE !(1 == ~t4_pc~0) [L422] is_transmit4_triggered_~__retres1~4 := 0; [L424] is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; [L881] activate_threads_#t~ret14 := is_transmit4_triggered_#res; [L881] activate_threads_~tmp___3~0 := activate_threads_#t~ret14; [L881] havoc activate_threads_#t~ret14; [L883-L887] COND FALSE !(0 != activate_threads_~tmp___3~0) [L889] havoc is_transmit5_triggered_#res; [L889] havoc is_transmit5_triggered_~__retres1~5; [L428] havoc is_transmit5_triggered_~__retres1~5; [L431] COND FALSE !(1 == ~t5_pc~0) [L441] is_transmit5_triggered_~__retres1~5 := 0; [L443] is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; [L889] activate_threads_#t~ret15 := is_transmit5_triggered_#res; [L889] activate_threads_~tmp___4~0 := activate_threads_#t~ret15; [L889] havoc activate_threads_#t~ret15; [L891-L895] COND FALSE !(0 != activate_threads_~tmp___4~0) [L897] havoc is_transmit6_triggered_#res; [L897] havoc is_transmit6_triggered_~__retres1~6; [L447] havoc is_transmit6_triggered_~__retres1~6; [L450] COND FALSE !(1 == ~t6_pc~0) [L460] is_transmit6_triggered_~__retres1~6 := 0; [L462] is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; [L897] activate_threads_#t~ret16 := is_transmit6_triggered_#res; [L897] activate_threads_~tmp___5~0 := activate_threads_#t~ret16; [L897] havoc activate_threads_#t~ret16; [L899-L903] COND FALSE !(0 != activate_threads_~tmp___5~0) [L764] COND FALSE !(1 == ~M_E~0) [L769] COND FALSE !(1 == ~T1_E~0) [L774] COND FALSE !(1 == ~T2_E~0) [L779] COND FALSE !(1 == ~T3_E~0) [L784] COND FALSE !(1 == ~T4_E~0) [L789] COND FALSE !(1 == ~T5_E~0) [L794] COND FALSE !(1 == ~T6_E~0) [L799] COND FALSE !(1 == ~E_M~0) [L804] COND FALSE !(1 == ~E_1~0) [L809] COND FALSE !(1 == ~E_2~0) [L814] COND FALSE !(1 == ~E_3~0) [L819] COND FALSE !(1 == ~E_4~0) [L824] COND FALSE !(1 == ~E_5~0) [L829] COND FALSE !(1 == ~E_6~0) [L1055-L1092] COND FALSE !(false) [L1058] start_simulation_~kernel_st~0 := 1; [L1059] havoc eval_#t~ret2, eval_#t~nondet3, eval_~tmp_ndt_1~0, eval_#t~nondet4, eval_~tmp_ndt_2~0, eval_#t~nondet5, eval_~tmp_ndt_3~0, eval_#t~nondet6, eval_~tmp_ndt_4~0, eval_#t~nondet7, eval_~tmp_ndt_5~0, eval_#t~nondet8, eval_~tmp_ndt_6~0, eval_#t~nondet9, eval_~tmp_ndt_7~0, eval_~tmp~0; [L563] havoc eval_~tmp~0; [L14] ~m_pc~0 := 0; [L15] ~t1_pc~0 := 0; [L16] ~t2_pc~0 := 0; [L17] ~t3_pc~0 := 0; [L18] ~t4_pc~0 := 0; [L19] ~t5_pc~0 := 0; [L20] ~t6_pc~0 := 0; [L21] ~m_st~0 := 0; [L22] ~t1_st~0 := 0; [L23] ~t2_st~0 := 0; [L24] ~t3_st~0 := 0; [L25] ~t4_st~0 := 0; [L26] ~t5_st~0 := 0; [L27] ~t6_st~0 := 0; [L28] ~m_i~0 := 0; [L29] ~t1_i~0 := 0; [L30] ~t2_i~0 := 0; [L31] ~t3_i~0 := 0; [L32] ~t4_i~0 := 0; [L33] ~t5_i~0 := 0; [L34] ~t6_i~0 := 0; [L35] ~M_E~0 := 2; [L36] ~T1_E~0 := 2; [L37] ~T2_E~0 := 2; [L38] ~T3_E~0 := 2; [L39] ~T4_E~0 := 2; [L40] ~T5_E~0 := 2; [L41] ~T6_E~0 := 2; [L42] ~E_M~0 := 2; [L43] ~E_1~0 := 2; [L44] ~E_2~0 := 2; [L45] ~E_3~0 := 2; [L46] ~E_4~0 := 2; [L47] ~E_5~0 := 2; [L48] ~E_6~0 := 2; [L57] ~token~0 := 0; [L59] ~local~0 := 0; [L1100] havoc ~__retres1~8; [L1010] ~m_i~0 := 1; [L1011] ~t1_i~0 := 1; [L1012] ~t2_i~0 := 1; [L1013] ~t3_i~0 := 1; [L1014] ~t4_i~0 := 1; [L1015] ~t5_i~0 := 1; [L1016] ~t6_i~0 := 1; [L1041] havoc ~kernel_st~0; [L1042] havoc ~tmp~3; [L1043] havoc ~tmp___0~1; [L1047] ~kernel_st~0 := 0; [L477] COND TRUE 1 == ~m_i~0 [L478] ~m_st~0 := 0; [L482] COND TRUE 1 == ~t1_i~0 [L483] ~t1_st~0 := 0; [L487] COND TRUE 1 == ~t2_i~0 [L488] ~t2_st~0 := 0; [L492] COND TRUE 1 == ~t3_i~0 [L493] ~t3_st~0 := 0; [L497] COND TRUE 1 == ~t4_i~0 [L498] ~t4_st~0 := 0; [L502] COND TRUE 1 == ~t5_i~0 [L503] ~t5_st~0 := 0; [L507] COND TRUE 1 == ~t6_i~0 [L508] ~t6_st~0 := 0; [L686] COND FALSE !(0 == ~M_E~0) [L691] COND FALSE !(0 == ~T1_E~0) [L696] COND FALSE !(0 == ~T2_E~0) [L701] COND FALSE !(0 == ~T3_E~0) [L706] COND FALSE !(0 == ~T4_E~0) [L711] COND FALSE !(0 == ~T5_E~0) [L716] COND FALSE !(0 == ~T6_E~0) [L721] COND FALSE !(0 == ~E_M~0) [L726] COND FALSE !(0 == ~E_1~0) [L731] COND FALSE !(0 == ~E_2~0) [L736] COND FALSE !(0 == ~E_3~0) [L741] COND FALSE !(0 == ~E_4~0) [L746] COND FALSE !(0 == ~E_5~0) [L751] COND FALSE !(0 == ~E_6~0) [L839] havoc ~tmp~1; [L840] havoc ~tmp___0~0; [L841] havoc ~tmp___1~0; [L842] havoc ~tmp___2~0; [L843] havoc ~tmp___3~0; [L844] havoc ~tmp___4~0; [L845] havoc ~tmp___5~0; [L333] havoc ~__retres1~0; [L336] COND FALSE !(1 == ~m_pc~0) [L346] ~__retres1~0 := 0; [L348] #res := ~__retres1~0; [L849] ~tmp~1 := #t~ret10; [L849] havoc #t~ret10; [L851-L855] COND FALSE !(0 != ~tmp~1) [L352] havoc ~__retres1~1; [L355] COND FALSE !(1 == ~t1_pc~0) [L365] ~__retres1~1 := 0; [L367] #res := ~__retres1~1; [L857] ~tmp___0~0 := #t~ret11; [L857] havoc #t~ret11; [L859-L863] COND FALSE !(0 != ~tmp___0~0) [L371] havoc ~__retres1~2; [L374] COND FALSE !(1 == ~t2_pc~0) [L384] ~__retres1~2 := 0; [L386] #res := ~__retres1~2; [L865] ~tmp___1~0 := #t~ret12; [L865] havoc #t~ret12; [L867-L871] COND FALSE !(0 != ~tmp___1~0) [L390] havoc ~__retres1~3; [L393] COND FALSE !(1 == ~t3_pc~0) [L403] ~__retres1~3 := 0; [L405] #res := ~__retres1~3; [L873] ~tmp___2~0 := #t~ret13; [L873] havoc #t~ret13; [L875-L879] COND FALSE !(0 != ~tmp___2~0) [L409] havoc ~__retres1~4; [L412] COND FALSE !(1 == ~t4_pc~0) [L422] ~__retres1~4 := 0; [L424] #res := ~__retres1~4; [L881] ~tmp___3~0 := #t~ret14; [L881] havoc #t~ret14; [L883-L887] COND FALSE !(0 != ~tmp___3~0) [L428] havoc ~__retres1~5; [L431] COND FALSE !(1 == ~t5_pc~0) [L441] ~__retres1~5 := 0; [L443] #res := ~__retres1~5; [L889] ~tmp___4~0 := #t~ret15; [L889] havoc #t~ret15; [L891-L895] COND FALSE !(0 != ~tmp___4~0) [L447] havoc ~__retres1~6; [L450] COND FALSE !(1 == ~t6_pc~0) [L460] ~__retres1~6 := 0; [L462] #res := ~__retres1~6; [L897] ~tmp___5~0 := #t~ret16; [L897] havoc #t~ret16; [L899-L903] COND FALSE !(0 != ~tmp___5~0) [L764] COND FALSE !(1 == ~M_E~0) [L769] COND FALSE !(1 == ~T1_E~0) [L774] COND FALSE !(1 == ~T2_E~0) [L779] COND FALSE !(1 == ~T3_E~0) [L784] COND FALSE !(1 == ~T4_E~0) [L789] COND FALSE !(1 == ~T5_E~0) [L794] COND FALSE !(1 == ~T6_E~0) [L799] COND FALSE !(1 == ~E_M~0) [L804] COND FALSE !(1 == ~E_1~0) [L809] COND FALSE !(1 == ~E_2~0) [L814] COND FALSE !(1 == ~E_3~0) [L819] COND FALSE !(1 == ~E_4~0) [L824] COND FALSE !(1 == ~E_5~0) [L829] COND FALSE !(1 == ~E_6~0) [L1055-L1092] COND FALSE !(false) [L1058] ~kernel_st~0 := 1; [L563] havoc ~tmp~0; ----- ----- class de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.CACSL2BoogieBacktranslator [L14] ~m_pc~0 := 0; [L15] ~t1_pc~0 := 0; [L16] ~t2_pc~0 := 0; [L17] ~t3_pc~0 := 0; [L18] ~t4_pc~0 := 0; [L19] ~t5_pc~0 := 0; [L20] ~t6_pc~0 := 0; [L21] ~m_st~0 := 0; [L22] ~t1_st~0 := 0; [L23] ~t2_st~0 := 0; [L24] ~t3_st~0 := 0; [L25] ~t4_st~0 := 0; [L26] ~t5_st~0 := 0; [L27] ~t6_st~0 := 0; [L28] ~m_i~0 := 0; [L29] ~t1_i~0 := 0; [L30] ~t2_i~0 := 0; [L31] ~t3_i~0 := 0; [L32] ~t4_i~0 := 0; [L33] ~t5_i~0 := 0; [L34] ~t6_i~0 := 0; [L35] ~M_E~0 := 2; [L36] ~T1_E~0 := 2; [L37] ~T2_E~0 := 2; [L38] ~T3_E~0 := 2; [L39] ~T4_E~0 := 2; [L40] ~T5_E~0 := 2; [L41] ~T6_E~0 := 2; [L42] ~E_M~0 := 2; [L43] ~E_1~0 := 2; [L44] ~E_2~0 := 2; [L45] ~E_3~0 := 2; [L46] ~E_4~0 := 2; [L47] ~E_5~0 := 2; [L48] ~E_6~0 := 2; [L57] ~token~0 := 0; [L59] ~local~0 := 0; [L1100] havoc ~__retres1~8; [L1010] ~m_i~0 := 1; [L1011] ~t1_i~0 := 1; [L1012] ~t2_i~0 := 1; [L1013] ~t3_i~0 := 1; [L1014] ~t4_i~0 := 1; [L1015] ~t5_i~0 := 1; [L1016] ~t6_i~0 := 1; [L1041] havoc ~kernel_st~0; [L1042] havoc ~tmp~3; [L1043] havoc ~tmp___0~1; [L1047] ~kernel_st~0 := 0; [L477] COND TRUE 1 == ~m_i~0 [L478] ~m_st~0 := 0; [L482] COND TRUE 1 == ~t1_i~0 [L483] ~t1_st~0 := 0; [L487] COND TRUE 1 == ~t2_i~0 [L488] ~t2_st~0 := 0; [L492] COND TRUE 1 == ~t3_i~0 [L493] ~t3_st~0 := 0; [L497] COND TRUE 1 == ~t4_i~0 [L498] ~t4_st~0 := 0; [L502] COND TRUE 1 == ~t5_i~0 [L503] ~t5_st~0 := 0; [L507] COND TRUE 1 == ~t6_i~0 [L508] ~t6_st~0 := 0; [L686] COND FALSE !(0 == ~M_E~0) [L691] COND FALSE !(0 == ~T1_E~0) [L696] COND FALSE !(0 == ~T2_E~0) [L701] COND FALSE !(0 == ~T3_E~0) [L706] COND FALSE !(0 == ~T4_E~0) [L711] COND FALSE !(0 == ~T5_E~0) [L716] COND FALSE !(0 == ~T6_E~0) [L721] COND FALSE !(0 == ~E_M~0) [L726] COND FALSE !(0 == ~E_1~0) [L731] COND FALSE !(0 == ~E_2~0) [L736] COND FALSE !(0 == ~E_3~0) [L741] COND FALSE !(0 == ~E_4~0) [L746] COND FALSE !(0 == ~E_5~0) [L751] COND FALSE !(0 == ~E_6~0) [L839] havoc ~tmp~1; [L840] havoc ~tmp___0~0; [L841] havoc ~tmp___1~0; [L842] havoc ~tmp___2~0; [L843] havoc ~tmp___3~0; [L844] havoc ~tmp___4~0; [L845] havoc ~tmp___5~0; [L333] havoc ~__retres1~0; [L336] COND FALSE !(1 == ~m_pc~0) [L346] ~__retres1~0 := 0; [L348] #res := ~__retres1~0; [L849] ~tmp~1 := #t~ret10; [L849] havoc #t~ret10; [L851-L855] COND FALSE !(0 != ~tmp~1) [L352] havoc ~__retres1~1; [L355] COND FALSE !(1 == ~t1_pc~0) [L365] ~__retres1~1 := 0; [L367] #res := ~__retres1~1; [L857] ~tmp___0~0 := #t~ret11; [L857] havoc #t~ret11; [L859-L863] COND FALSE !(0 != ~tmp___0~0) [L371] havoc ~__retres1~2; [L374] COND FALSE !(1 == ~t2_pc~0) [L384] ~__retres1~2 := 0; [L386] #res := ~__retres1~2; [L865] ~tmp___1~0 := #t~ret12; [L865] havoc #t~ret12; [L867-L871] COND FALSE !(0 != ~tmp___1~0) [L390] havoc ~__retres1~3; [L393] COND FALSE !(1 == ~t3_pc~0) [L403] ~__retres1~3 := 0; [L405] #res := ~__retres1~3; [L873] ~tmp___2~0 := #t~ret13; [L873] havoc #t~ret13; [L875-L879] COND FALSE !(0 != ~tmp___2~0) [L409] havoc ~__retres1~4; [L412] COND FALSE !(1 == ~t4_pc~0) [L422] ~__retres1~4 := 0; [L424] #res := ~__retres1~4; [L881] ~tmp___3~0 := #t~ret14; [L881] havoc #t~ret14; [L883-L887] COND FALSE !(0 != ~tmp___3~0) [L428] havoc ~__retres1~5; [L431] COND FALSE !(1 == ~t5_pc~0) [L441] ~__retres1~5 := 0; [L443] #res := ~__retres1~5; [L889] ~tmp___4~0 := #t~ret15; [L889] havoc #t~ret15; [L891-L895] COND FALSE !(0 != ~tmp___4~0) [L447] havoc ~__retres1~6; [L450] COND FALSE !(1 == ~t6_pc~0) [L460] ~__retres1~6 := 0; [L462] #res := ~__retres1~6; [L897] ~tmp___5~0 := #t~ret16; [L897] havoc #t~ret16; [L899-L903] COND FALSE !(0 != ~tmp___5~0) [L764] COND FALSE !(1 == ~M_E~0) [L769] COND FALSE !(1 == ~T1_E~0) [L774] COND FALSE !(1 == ~T2_E~0) [L779] COND FALSE !(1 == ~T3_E~0) [L784] COND FALSE !(1 == ~T4_E~0) [L789] COND FALSE !(1 == ~T5_E~0) [L794] COND FALSE !(1 == ~T6_E~0) [L799] COND FALSE !(1 == ~E_M~0) [L804] COND FALSE !(1 == ~E_1~0) [L809] COND FALSE !(1 == ~E_2~0) [L814] COND FALSE !(1 == ~E_3~0) [L819] COND FALSE !(1 == ~E_4~0) [L824] COND FALSE !(1 == ~E_5~0) [L829] COND FALSE !(1 == ~E_6~0) [L1055-L1092] COND FALSE !(false) [L1058] ~kernel_st~0 := 1; [L563] havoc ~tmp~0; [L14] int m_pc = 0; [L15] int t1_pc = 0; [L16] int t2_pc = 0; [L17] int t3_pc = 0; [L18] int t4_pc = 0; [L19] int t5_pc = 0; [L20] int t6_pc = 0; [L21] int m_st ; [L22] int t1_st ; [L23] int t2_st ; [L24] int t3_st ; [L25] int t4_st ; [L26] int t5_st ; [L27] int t6_st ; [L28] int m_i ; [L29] int t1_i ; [L30] int t2_i ; [L31] int t3_i ; [L32] int t4_i ; [L33] int t5_i ; [L34] int t6_i ; [L35] int M_E = 2; [L36] int T1_E = 2; [L37] int T2_E = 2; [L38] int T3_E = 2; [L39] int T4_E = 2; [L40] int T5_E = 2; [L41] int T6_E = 2; [L42] int E_M = 2; [L43] int E_1 = 2; [L44] int E_2 = 2; [L45] int E_3 = 2; [L46] int E_4 = 2; [L47] int E_5 = 2; [L48] int E_6 = 2; [L57] int token ; [L59] int local ; [L1100] int __retres1 ; [L1010] m_i = 1 [L1011] t1_i = 1 [L1012] t2_i = 1 [L1013] t3_i = 1 [L1014] t4_i = 1 [L1015] t5_i = 1 [L1016] t6_i = 1 [L1041] int kernel_st ; [L1042] int tmp ; [L1043] int tmp___0 ; [L1047] kernel_st = 0 [L477] COND TRUE m_i == 1 [L478] m_st = 0 [L482] COND TRUE t1_i == 1 [L483] t1_st = 0 [L487] COND TRUE t2_i == 1 [L488] t2_st = 0 [L492] COND TRUE t3_i == 1 [L493] t3_st = 0 [L497] COND TRUE t4_i == 1 [L498] t4_st = 0 [L502] COND TRUE t5_i == 1 [L503] t5_st = 0 [L507] COND TRUE t6_i == 1 [L508] t6_st = 0 [L686] COND FALSE !(M_E == 0) [L691] COND FALSE !(T1_E == 0) [L696] COND FALSE !(T2_E == 0) [L701] COND FALSE !(T3_E == 0) [L706] COND FALSE !(T4_E == 0) [L711] COND FALSE !(T5_E == 0) [L716] COND FALSE !(T6_E == 0) [L721] COND FALSE !(E_M == 0) [L726] COND FALSE !(E_1 == 0) [L731] COND FALSE !(E_2 == 0) [L736] COND FALSE !(E_3 == 0) [L741] COND FALSE !(E_4 == 0) [L746] COND FALSE !(E_5 == 0) [L751] COND FALSE !(E_6 == 0) [L839] int tmp ; [L840] int tmp___0 ; [L841] int tmp___1 ; [L842] int tmp___2 ; [L843] int tmp___3 ; [L844] int tmp___4 ; [L845] int tmp___5 ; [L333] int __retres1 ; [L336] COND FALSE !(m_pc == 1) [L346] __retres1 = 0 [L348] return (__retres1); [L849] tmp = is_master_triggered() [L851] COND FALSE !(\read(tmp)) [L352] int __retres1 ; [L355] COND FALSE !(t1_pc == 1) [L365] __retres1 = 0 [L367] return (__retres1); [L857] tmp___0 = is_transmit1_triggered() [L859] COND FALSE !(\read(tmp___0)) [L371] int __retres1 ; [L374] COND FALSE !(t2_pc == 1) [L384] __retres1 = 0 [L386] return (__retres1); [L865] tmp___1 = is_transmit2_triggered() [L867] COND FALSE !(\read(tmp___1)) [L390] int __retres1 ; [L393] COND FALSE !(t3_pc == 1) [L403] __retres1 = 0 [L405] return (__retres1); [L873] tmp___2 = is_transmit3_triggered() [L875] COND FALSE !(\read(tmp___2)) [L409] int __retres1 ; [L412] COND FALSE !(t4_pc == 1) [L422] __retres1 = 0 [L424] return (__retres1); [L881] tmp___3 = is_transmit4_triggered() [L883] COND FALSE !(\read(tmp___3)) [L428] int __retres1 ; [L431] COND FALSE !(t5_pc == 1) [L441] __retres1 = 0 [L443] return (__retres1); [L889] tmp___4 = is_transmit5_triggered() [L891] COND FALSE !(\read(tmp___4)) [L447] int __retres1 ; [L450] COND FALSE !(t6_pc == 1) [L460] __retres1 = 0 [L462] return (__retres1); [L897] tmp___5 = is_transmit6_triggered() [L899] COND FALSE !(\read(tmp___5)) [L764] COND FALSE !(M_E == 1) [L769] COND FALSE !(T1_E == 1) [L774] COND FALSE !(T2_E == 1) [L779] COND FALSE !(T3_E == 1) [L784] COND FALSE !(T4_E == 1) [L789] COND FALSE !(T5_E == 1) [L794] COND FALSE !(T6_E == 1) [L799] COND FALSE !(E_M == 1) [L804] COND FALSE !(E_1 == 1) [L809] COND FALSE !(E_2 == 1) [L814] COND FALSE !(E_3 == 1) [L819] COND FALSE !(E_4 == 1) [L824] COND FALSE !(E_5 == 1) [L829] COND FALSE !(E_6 == 1) [L1055] COND TRUE 1 [L1058] kernel_st = 1 [L563] int tmp ; ----- ----- class de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder.RCFGBacktranslator [?] assume !false; [?] havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~7;havoc exists_runnable_thread_~__retres1~7; [?] assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7 := 1; [?] exists_runnable_thread_#res := exists_runnable_thread_~__retres1~7; [?] eval_#t~ret2 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret2;havoc eval_#t~ret2; [?] assume 0 != eval_~tmp~0; [?] assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0;eval_~tmp_ndt_1~0 := eval_#t~nondet3;havoc eval_#t~nondet3; [?] assume !(0 != eval_~tmp_ndt_1~0); [?] assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0;eval_~tmp_ndt_2~0 := eval_#t~nondet4;havoc eval_#t~nondet4; [?] assume !(0 != eval_~tmp_ndt_2~0); [?] assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0;eval_~tmp_ndt_3~0 := eval_#t~nondet5;havoc eval_#t~nondet5; [?] assume !(0 != eval_~tmp_ndt_3~0); [?] assume 0 == ~t3_st~0;havoc eval_~tmp_ndt_4~0;eval_~tmp_ndt_4~0 := eval_#t~nondet6;havoc eval_#t~nondet6; [?] assume !(0 != eval_~tmp_ndt_4~0); [?] assume 0 == ~t4_st~0;havoc eval_~tmp_ndt_5~0;eval_~tmp_ndt_5~0 := eval_#t~nondet7;havoc eval_#t~nondet7; [?] assume !(0 != eval_~tmp_ndt_5~0); [?] assume 0 == ~t5_st~0;havoc eval_~tmp_ndt_6~0;eval_~tmp_ndt_6~0 := eval_#t~nondet8;havoc eval_#t~nondet8; [?] assume !(0 != eval_~tmp_ndt_6~0); [?] assume 0 == ~t6_st~0;havoc eval_~tmp_ndt_7~0;eval_~tmp_ndt_7~0 := eval_#t~nondet9;havoc eval_#t~nondet9; [?] assume !(0 != eval_~tmp_ndt_7~0); [L567-L675] assume !false; [L570] havoc exists_runnable_thread_#res; [L570] havoc exists_runnable_thread_~__retres1~7; [L517] havoc exists_runnable_thread_~__retres1~7; [L520-L555] assume 0 == ~m_st~0; [L521] exists_runnable_thread_~__retres1~7 := 1; [L558] exists_runnable_thread_#res := exists_runnable_thread_~__retres1~7; [L570] eval_#t~ret2 := exists_runnable_thread_#res; [L570] eval_~tmp~0 := eval_#t~ret2; [L570] havoc eval_#t~ret2; [L572-L576] assume 0 != eval_~tmp~0; [L577-L590] assume 0 == ~m_st~0; [L578] havoc eval_~tmp_ndt_1~0; [L579] eval_~tmp_ndt_1~0 := eval_#t~nondet3; [L579] havoc eval_#t~nondet3; [L580-L587] assume !(0 != eval_~tmp_ndt_1~0); [L591-L604] assume 0 == ~t1_st~0; [L592] havoc eval_~tmp_ndt_2~0; [L593] eval_~tmp_ndt_2~0 := eval_#t~nondet4; [L593] havoc eval_#t~nondet4; [L594-L601] assume !(0 != eval_~tmp_ndt_2~0); [L605-L618] assume 0 == ~t2_st~0; [L606] havoc eval_~tmp_ndt_3~0; [L607] eval_~tmp_ndt_3~0 := eval_#t~nondet5; [L607] havoc eval_#t~nondet5; [L608-L615] assume !(0 != eval_~tmp_ndt_3~0); [L619-L632] assume 0 == ~t3_st~0; [L620] havoc eval_~tmp_ndt_4~0; [L621] eval_~tmp_ndt_4~0 := eval_#t~nondet6; [L621] havoc eval_#t~nondet6; [L622-L629] assume !(0 != eval_~tmp_ndt_4~0); [L633-L646] assume 0 == ~t4_st~0; [L634] havoc eval_~tmp_ndt_5~0; [L635] eval_~tmp_ndt_5~0 := eval_#t~nondet7; [L635] havoc eval_#t~nondet7; [L636-L643] assume !(0 != eval_~tmp_ndt_5~0); [L647-L660] assume 0 == ~t5_st~0; [L648] havoc eval_~tmp_ndt_6~0; [L649] eval_~tmp_ndt_6~0 := eval_#t~nondet8; [L649] havoc eval_#t~nondet8; [L650-L657] assume !(0 != eval_~tmp_ndt_6~0); [L661-L674] assume 0 == ~t6_st~0; [L662] havoc eval_~tmp_ndt_7~0; [L663] eval_~tmp_ndt_7~0 := eval_#t~nondet9; [L663] havoc eval_#t~nondet9; [L664-L671] assume !(0 != eval_~tmp_ndt_7~0); ----- ----- class de.uni_freiburg.informatik.ultimate.boogie.preprocessor.BoogiePreprocessorBacktranslator [L567-L675] assume !false; [L570] havoc exists_runnable_thread_#res; [L570] havoc exists_runnable_thread_~__retres1~7; [L517] havoc exists_runnable_thread_~__retres1~7; [L520-L555] assume 0 == ~m_st~0; [L521] exists_runnable_thread_~__retres1~7 := 1; [L558] exists_runnable_thread_#res := exists_runnable_thread_~__retres1~7; [L570] eval_#t~ret2 := exists_runnable_thread_#res; [L570] eval_~tmp~0 := eval_#t~ret2; [L570] havoc eval_#t~ret2; [L572-L576] assume 0 != eval_~tmp~0; [L577-L590] assume 0 == ~m_st~0; [L578] havoc eval_~tmp_ndt_1~0; [L579] eval_~tmp_ndt_1~0 := eval_#t~nondet3; [L579] havoc eval_#t~nondet3; [L580-L587] assume !(0 != eval_~tmp_ndt_1~0); [L591-L604] assume 0 == ~t1_st~0; [L592] havoc eval_~tmp_ndt_2~0; [L593] eval_~tmp_ndt_2~0 := eval_#t~nondet4; [L593] havoc eval_#t~nondet4; [L594-L601] assume !(0 != eval_~tmp_ndt_2~0); [L605-L618] assume 0 == ~t2_st~0; [L606] havoc eval_~tmp_ndt_3~0; [L607] eval_~tmp_ndt_3~0 := eval_#t~nondet5; [L607] havoc eval_#t~nondet5; [L608-L615] assume !(0 != eval_~tmp_ndt_3~0); [L619-L632] assume 0 == ~t3_st~0; [L620] havoc eval_~tmp_ndt_4~0; [L621] eval_~tmp_ndt_4~0 := eval_#t~nondet6; [L621] havoc eval_#t~nondet6; [L622-L629] assume !(0 != eval_~tmp_ndt_4~0); [L633-L646] assume 0 == ~t4_st~0; [L634] havoc eval_~tmp_ndt_5~0; [L635] eval_~tmp_ndt_5~0 := eval_#t~nondet7; [L635] havoc eval_#t~nondet7; [L636-L643] assume !(0 != eval_~tmp_ndt_5~0); [L647-L660] assume 0 == ~t5_st~0; [L648] havoc eval_~tmp_ndt_6~0; [L649] eval_~tmp_ndt_6~0 := eval_#t~nondet8; [L649] havoc eval_#t~nondet8; [L650-L657] assume !(0 != eval_~tmp_ndt_6~0); [L661-L674] assume 0 == ~t6_st~0; [L662] havoc eval_~tmp_ndt_7~0; [L663] eval_~tmp_ndt_7~0 := eval_#t~nondet9; [L663] havoc eval_#t~nondet9; [L664-L671] assume !(0 != eval_~tmp_ndt_7~0); [L567-L675] COND FALSE !(false) [L570] havoc exists_runnable_thread_#res; [L570] havoc exists_runnable_thread_~__retres1~7; [L517] havoc exists_runnable_thread_~__retres1~7; [L520] COND TRUE 0 == ~m_st~0 [L521] exists_runnable_thread_~__retres1~7 := 1; [L558] exists_runnable_thread_#res := exists_runnable_thread_~__retres1~7; [L570] eval_#t~ret2 := exists_runnable_thread_#res; [L570] eval_~tmp~0 := eval_#t~ret2; [L570] havoc eval_#t~ret2; [L572-L576] COND TRUE 0 != eval_~tmp~0 [L577] COND TRUE 0 == ~m_st~0 [L578] havoc eval_~tmp_ndt_1~0; [L579] eval_~tmp_ndt_1~0 := eval_#t~nondet3; [L579] havoc eval_#t~nondet3; [L580-L587] COND FALSE !(0 != eval_~tmp_ndt_1~0) [L591] COND TRUE 0 == ~t1_st~0 [L592] havoc eval_~tmp_ndt_2~0; [L593] eval_~tmp_ndt_2~0 := eval_#t~nondet4; [L593] havoc eval_#t~nondet4; [L594-L601] COND FALSE !(0 != eval_~tmp_ndt_2~0) [L605] COND TRUE 0 == ~t2_st~0 [L606] havoc eval_~tmp_ndt_3~0; [L607] eval_~tmp_ndt_3~0 := eval_#t~nondet5; [L607] havoc eval_#t~nondet5; [L608-L615] COND FALSE !(0 != eval_~tmp_ndt_3~0) [L619] COND TRUE 0 == ~t3_st~0 [L620] havoc eval_~tmp_ndt_4~0; [L621] eval_~tmp_ndt_4~0 := eval_#t~nondet6; [L621] havoc eval_#t~nondet6; [L622-L629] COND FALSE !(0 != eval_~tmp_ndt_4~0) [L633] COND TRUE 0 == ~t4_st~0 [L634] havoc eval_~tmp_ndt_5~0; [L635] eval_~tmp_ndt_5~0 := eval_#t~nondet7; [L635] havoc eval_#t~nondet7; [L636-L643] COND FALSE !(0 != eval_~tmp_ndt_5~0) [L647] COND TRUE 0 == ~t5_st~0 [L648] havoc eval_~tmp_ndt_6~0; [L649] eval_~tmp_ndt_6~0 := eval_#t~nondet8; [L649] havoc eval_#t~nondet8; [L650-L657] COND FALSE !(0 != eval_~tmp_ndt_6~0) [L661] COND TRUE 0 == ~t6_st~0 [L662] havoc eval_~tmp_ndt_7~0; [L663] eval_~tmp_ndt_7~0 := eval_#t~nondet9; [L663] havoc eval_#t~nondet9; [L664-L671] COND FALSE !(0 != eval_~tmp_ndt_7~0) ----- ----- class de.uni_freiburg.informatik.ultimate.boogie.procedureinliner.backtranslation.InlinerBacktranslator [L567-L675] COND FALSE !(false) [L570] havoc exists_runnable_thread_#res; [L570] havoc exists_runnable_thread_~__retres1~7; [L517] havoc exists_runnable_thread_~__retres1~7; [L520] COND TRUE 0 == ~m_st~0 [L521] exists_runnable_thread_~__retres1~7 := 1; [L558] exists_runnable_thread_#res := exists_runnable_thread_~__retres1~7; [L570] eval_#t~ret2 := exists_runnable_thread_#res; [L570] eval_~tmp~0 := eval_#t~ret2; [L570] havoc eval_#t~ret2; [L572-L576] COND TRUE 0 != eval_~tmp~0 [L577] COND TRUE 0 == ~m_st~0 [L578] havoc eval_~tmp_ndt_1~0; [L579] eval_~tmp_ndt_1~0 := eval_#t~nondet3; [L579] havoc eval_#t~nondet3; [L580-L587] COND FALSE !(0 != eval_~tmp_ndt_1~0) [L591] COND TRUE 0 == ~t1_st~0 [L592] havoc eval_~tmp_ndt_2~0; [L593] eval_~tmp_ndt_2~0 := eval_#t~nondet4; [L593] havoc eval_#t~nondet4; [L594-L601] COND FALSE !(0 != eval_~tmp_ndt_2~0) [L605] COND TRUE 0 == ~t2_st~0 [L606] havoc eval_~tmp_ndt_3~0; [L607] eval_~tmp_ndt_3~0 := eval_#t~nondet5; [L607] havoc eval_#t~nondet5; [L608-L615] COND FALSE !(0 != eval_~tmp_ndt_3~0) [L619] COND TRUE 0 == ~t3_st~0 [L620] havoc eval_~tmp_ndt_4~0; [L621] eval_~tmp_ndt_4~0 := eval_#t~nondet6; [L621] havoc eval_#t~nondet6; [L622-L629] COND FALSE !(0 != eval_~tmp_ndt_4~0) [L633] COND TRUE 0 == ~t4_st~0 [L634] havoc eval_~tmp_ndt_5~0; [L635] eval_~tmp_ndt_5~0 := eval_#t~nondet7; [L635] havoc eval_#t~nondet7; [L636-L643] COND FALSE !(0 != eval_~tmp_ndt_5~0) [L647] COND TRUE 0 == ~t5_st~0 [L648] havoc eval_~tmp_ndt_6~0; [L649] eval_~tmp_ndt_6~0 := eval_#t~nondet8; [L649] havoc eval_#t~nondet8; [L650-L657] COND FALSE !(0 != eval_~tmp_ndt_6~0) [L661] COND TRUE 0 == ~t6_st~0 [L662] havoc eval_~tmp_ndt_7~0; [L663] eval_~tmp_ndt_7~0 := eval_#t~nondet9; [L663] havoc eval_#t~nondet9; [L664-L671] COND FALSE !(0 != eval_~tmp_ndt_7~0) [L567-L675] COND FALSE !(false) [L517] havoc ~__retres1~7; [L520] COND TRUE 0 == ~m_st~0 [L521] ~__retres1~7 := 1; [L558] #res := ~__retres1~7; [L570] ~tmp~0 := #t~ret2; [L570] havoc #t~ret2; [L572-L576] COND TRUE 0 != ~tmp~0 [L577] COND TRUE 0 == ~m_st~0 [L578] havoc ~tmp_ndt_1~0; [L579] ~tmp_ndt_1~0 := #t~nondet3; [L579] havoc #t~nondet3; [L580-L587] COND FALSE !(0 != ~tmp_ndt_1~0) [L591] COND TRUE 0 == ~t1_st~0 [L592] havoc ~tmp_ndt_2~0; [L593] ~tmp_ndt_2~0 := #t~nondet4; [L593] havoc #t~nondet4; [L594-L601] COND FALSE !(0 != ~tmp_ndt_2~0) [L605] COND TRUE 0 == ~t2_st~0 [L606] havoc ~tmp_ndt_3~0; [L607] ~tmp_ndt_3~0 := #t~nondet5; [L607] havoc #t~nondet5; [L608-L615] COND FALSE !(0 != ~tmp_ndt_3~0) [L619] COND TRUE 0 == ~t3_st~0 [L620] havoc ~tmp_ndt_4~0; [L621] ~tmp_ndt_4~0 := #t~nondet6; [L621] havoc #t~nondet6; [L622-L629] COND FALSE !(0 != ~tmp_ndt_4~0) [L633] COND TRUE 0 == ~t4_st~0 [L634] havoc ~tmp_ndt_5~0; [L635] ~tmp_ndt_5~0 := #t~nondet7; [L635] havoc #t~nondet7; [L636-L643] COND FALSE !(0 != ~tmp_ndt_5~0) [L647] COND TRUE 0 == ~t5_st~0 [L648] havoc ~tmp_ndt_6~0; [L649] ~tmp_ndt_6~0 := #t~nondet8; [L649] havoc #t~nondet8; [L650-L657] COND FALSE !(0 != ~tmp_ndt_6~0) [L661] COND TRUE 0 == ~t6_st~0 [L662] havoc ~tmp_ndt_7~0; [L663] ~tmp_ndt_7~0 := #t~nondet9; [L663] havoc #t~nondet9; [L664-L671] COND FALSE !(0 != ~tmp_ndt_7~0) ----- ----- class de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.CACSL2BoogieBacktranslator [L567-L675] COND FALSE !(false) [L517] havoc ~__retres1~7; [L520] COND TRUE 0 == ~m_st~0 [L521] ~__retres1~7 := 1; [L558] #res := ~__retres1~7; [L570] ~tmp~0 := #t~ret2; [L570] havoc #t~ret2; [L572-L576] COND TRUE 0 != ~tmp~0 [L577] COND TRUE 0 == ~m_st~0 [L578] havoc ~tmp_ndt_1~0; [L579] ~tmp_ndt_1~0 := #t~nondet3; [L579] havoc #t~nondet3; [L580-L587] COND FALSE !(0 != ~tmp_ndt_1~0) [L591] COND TRUE 0 == ~t1_st~0 [L592] havoc ~tmp_ndt_2~0; [L593] ~tmp_ndt_2~0 := #t~nondet4; [L593] havoc #t~nondet4; [L594-L601] COND FALSE !(0 != ~tmp_ndt_2~0) [L605] COND TRUE 0 == ~t2_st~0 [L606] havoc ~tmp_ndt_3~0; [L607] ~tmp_ndt_3~0 := #t~nondet5; [L607] havoc #t~nondet5; [L608-L615] COND FALSE !(0 != ~tmp_ndt_3~0) [L619] COND TRUE 0 == ~t3_st~0 [L620] havoc ~tmp_ndt_4~0; [L621] ~tmp_ndt_4~0 := #t~nondet6; [L621] havoc #t~nondet6; [L622-L629] COND FALSE !(0 != ~tmp_ndt_4~0) [L633] COND TRUE 0 == ~t4_st~0 [L634] havoc ~tmp_ndt_5~0; [L635] ~tmp_ndt_5~0 := #t~nondet7; [L635] havoc #t~nondet7; [L636-L643] COND FALSE !(0 != ~tmp_ndt_5~0) [L647] COND TRUE 0 == ~t5_st~0 [L648] havoc ~tmp_ndt_6~0; [L649] ~tmp_ndt_6~0 := #t~nondet8; [L649] havoc #t~nondet8; [L650-L657] COND FALSE !(0 != ~tmp_ndt_6~0) [L661] COND TRUE 0 == ~t6_st~0 [L662] havoc ~tmp_ndt_7~0; [L663] ~tmp_ndt_7~0 := #t~nondet9; [L663] havoc #t~nondet9; [L664-L671] COND FALSE !(0 != ~tmp_ndt_7~0) [L567] COND TRUE 1 [L517] int __retres1 ; [L520] COND TRUE m_st == 0 [L521] __retres1 = 1 [L558] return (__retres1); [L570] tmp = exists_runnable_thread() [L572] COND TRUE \read(tmp) [L577] COND TRUE m_st == 0 [L578] int tmp_ndt_1; [L579] tmp_ndt_1 = __VERIFIER_nondet_int() [L580] COND FALSE !(\read(tmp_ndt_1)) [L591] COND TRUE t1_st == 0 [L592] int tmp_ndt_2; [L593] tmp_ndt_2 = __VERIFIER_nondet_int() [L594] COND FALSE !(\read(tmp_ndt_2)) [L605] COND TRUE t2_st == 0 [L606] int tmp_ndt_3; [L607] tmp_ndt_3 = __VERIFIER_nondet_int() [L608] COND FALSE !(\read(tmp_ndt_3)) [L619] COND TRUE t3_st == 0 [L620] int tmp_ndt_4; [L621] tmp_ndt_4 = __VERIFIER_nondet_int() [L622] COND FALSE !(\read(tmp_ndt_4)) [L633] COND TRUE t4_st == 0 [L634] int tmp_ndt_5; [L635] tmp_ndt_5 = __VERIFIER_nondet_int() [L636] COND FALSE !(\read(tmp_ndt_5)) [L647] COND TRUE t5_st == 0 [L648] int tmp_ndt_6; [L649] tmp_ndt_6 = __VERIFIER_nondet_int() [L650] COND FALSE !(\read(tmp_ndt_6)) [L661] COND TRUE t6_st == 0 [L662] int tmp_ndt_7; [L663] tmp_ndt_7 = __VERIFIER_nondet_int() [L664] COND FALSE !(\read(tmp_ndt_7)) ----- ----- class de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder.RCFGBacktranslator [?] ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0; [?] havoc main_#res;havoc main_~__retres1~8;havoc main_~__retres1~8;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; [?] havoc start_simulation_#t~ret18, start_simulation_#t~ret19, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; [?] assume 1 == ~m_i~0;~m_st~0 := 0; [?] assume 1 == ~t1_i~0;~t1_st~0 := 0; [?] assume 1 == ~t2_i~0;~t2_st~0 := 0; [?] assume 1 == ~t3_i~0;~t3_st~0 := 0; [?] assume 1 == ~t4_i~0;~t4_st~0 := 0; [?] assume 1 == ~t5_i~0;~t5_st~0 := 0; [?] assume 1 == ~t6_i~0;~t6_st~0 := 0; [?] assume !(0 == ~M_E~0); [?] assume !(0 == ~T1_E~0); [?] assume !(0 == ~T2_E~0); [?] assume !(0 == ~T3_E~0); [?] assume !(0 == ~T4_E~0); [?] assume !(0 == ~T5_E~0); [?] assume !(0 == ~T6_E~0); [?] assume !(0 == ~E_M~0); [?] assume !(0 == ~E_1~0); [?] assume !(0 == ~E_2~0); [?] assume !(0 == ~E_3~0); [?] assume !(0 == ~E_4~0); [?] assume !(0 == ~E_5~0); [?] assume !(0 == ~E_6~0); [?] havoc activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; [?] assume !(1 == ~m_pc~0); [?] is_master_triggered_~__retres1~0 := 0; [?] is_master_triggered_#res := is_master_triggered_~__retres1~0; [?] activate_threads_#t~ret10 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; [?] assume !(0 != activate_threads_~tmp~1); [?] havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; [?] assume !(1 == ~t1_pc~0); [?] is_transmit1_triggered_~__retres1~1 := 0; [?] is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; [?] activate_threads_#t~ret11 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; [?] assume !(0 != activate_threads_~tmp___0~0); [?] havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; [?] assume !(1 == ~t2_pc~0); [?] is_transmit2_triggered_~__retres1~2 := 0; [?] is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; [?] activate_threads_#t~ret12 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; [?] assume !(0 != activate_threads_~tmp___1~0); [?] havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; [?] assume !(1 == ~t3_pc~0); [?] is_transmit3_triggered_~__retres1~3 := 0; [?] is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; [?] activate_threads_#t~ret13 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; [?] assume !(0 != activate_threads_~tmp___2~0); [?] havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; [?] assume !(1 == ~t4_pc~0); [?] is_transmit4_triggered_~__retres1~4 := 0; [?] is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; [?] activate_threads_#t~ret14 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; [?] assume !(0 != activate_threads_~tmp___3~0); [?] havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; [?] assume !(1 == ~t5_pc~0); [?] is_transmit5_triggered_~__retres1~5 := 0; [?] is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; [?] activate_threads_#t~ret15 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; [?] assume !(0 != activate_threads_~tmp___4~0); [?] havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; [?] assume !(1 == ~t6_pc~0); [?] is_transmit6_triggered_~__retres1~6 := 0; [?] is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; [?] activate_threads_#t~ret16 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; [?] assume !(0 != activate_threads_~tmp___5~0); [?] assume !(1 == ~M_E~0); [?] assume !(1 == ~T1_E~0); [?] assume !(1 == ~T2_E~0); [?] assume !(1 == ~T3_E~0); [?] assume !(1 == ~T4_E~0); [?] assume !(1 == ~T5_E~0); [?] assume !(1 == ~T6_E~0); [?] assume !(1 == ~E_M~0); [?] assume !(1 == ~E_1~0); [?] assume !(1 == ~E_2~0); [?] assume !(1 == ~E_3~0); [?] assume !(1 == ~E_4~0); [?] assume !(1 == ~E_5~0); [?] assume !(1 == ~E_6~0); [?] assume !false; [?] start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret2, eval_#t~nondet3, eval_~tmp_ndt_1~0, eval_#t~nondet4, eval_~tmp_ndt_2~0, eval_#t~nondet5, eval_~tmp_ndt_3~0, eval_#t~nondet6, eval_~tmp_ndt_4~0, eval_#t~nondet7, eval_~tmp_ndt_5~0, eval_#t~nondet8, eval_~tmp_ndt_6~0, eval_#t~nondet9, eval_~tmp_ndt_7~0, eval_~tmp~0;havoc eval_~tmp~0; [L14] ~m_pc~0 := 0; [L15] ~t1_pc~0 := 0; [L16] ~t2_pc~0 := 0; [L17] ~t3_pc~0 := 0; [L18] ~t4_pc~0 := 0; [L19] ~t5_pc~0 := 0; [L20] ~t6_pc~0 := 0; [L21] ~m_st~0 := 0; [L22] ~t1_st~0 := 0; [L23] ~t2_st~0 := 0; [L24] ~t3_st~0 := 0; [L25] ~t4_st~0 := 0; [L26] ~t5_st~0 := 0; [L27] ~t6_st~0 := 0; [L28] ~m_i~0 := 0; [L29] ~t1_i~0 := 0; [L30] ~t2_i~0 := 0; [L31] ~t3_i~0 := 0; [L32] ~t4_i~0 := 0; [L33] ~t5_i~0 := 0; [L34] ~t6_i~0 := 0; [L35] ~M_E~0 := 2; [L36] ~T1_E~0 := 2; [L37] ~T2_E~0 := 2; [L38] ~T3_E~0 := 2; [L39] ~T4_E~0 := 2; [L40] ~T5_E~0 := 2; [L41] ~T6_E~0 := 2; [L42] ~E_M~0 := 2; [L43] ~E_1~0 := 2; [L44] ~E_2~0 := 2; [L45] ~E_3~0 := 2; [L46] ~E_4~0 := 2; [L47] ~E_5~0 := 2; [L48] ~E_6~0 := 2; [L57] ~token~0 := 0; [L59] ~local~0 := 0; [?] havoc main_#res; [?] havoc main_~__retres1~8; [L1100] havoc main_~__retres1~8; [L1010] ~m_i~0 := 1; [L1011] ~t1_i~0 := 1; [L1012] ~t2_i~0 := 1; [L1013] ~t3_i~0 := 1; [L1014] ~t4_i~0 := 1; [L1015] ~t5_i~0 := 1; [L1016] ~t6_i~0 := 1; [L1105] havoc start_simulation_#t~ret18, start_simulation_#t~ret19, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1; [L1041] havoc start_simulation_~kernel_st~0; [L1042] havoc start_simulation_~tmp~3; [L1043] havoc start_simulation_~tmp___0~1; [L1047] start_simulation_~kernel_st~0 := 0; [L477-L481] assume 1 == ~m_i~0; [L478] ~m_st~0 := 0; [L482-L486] assume 1 == ~t1_i~0; [L483] ~t1_st~0 := 0; [L487-L491] assume 1 == ~t2_i~0; [L488] ~t2_st~0 := 0; [L492-L496] assume 1 == ~t3_i~0; [L493] ~t3_st~0 := 0; [L497-L501] assume 1 == ~t4_i~0; [L498] ~t4_st~0 := 0; [L502-L506] assume 1 == ~t5_i~0; [L503] ~t5_st~0 := 0; [L507-L511] assume 1 == ~t6_i~0; [L508] ~t6_st~0 := 0; [L686-L690] assume !(0 == ~M_E~0); [L691-L695] assume !(0 == ~T1_E~0); [L696-L700] assume !(0 == ~T2_E~0); [L701-L705] assume !(0 == ~T3_E~0); [L706-L710] assume !(0 == ~T4_E~0); [L711-L715] assume !(0 == ~T5_E~0); [L716-L720] assume !(0 == ~T6_E~0); [L721-L725] assume !(0 == ~E_M~0); [L726-L730] assume !(0 == ~E_1~0); [L731-L735] assume !(0 == ~E_2~0); [L736-L740] assume !(0 == ~E_3~0); [L741-L745] assume !(0 == ~E_4~0); [L746-L750] assume !(0 == ~E_5~0); [L751-L755] assume !(0 == ~E_6~0); [L1051] havoc activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0; [L839] havoc activate_threads_~tmp~1; [L840] havoc activate_threads_~tmp___0~0; [L841] havoc activate_threads_~tmp___1~0; [L842] havoc activate_threads_~tmp___2~0; [L843] havoc activate_threads_~tmp___3~0; [L844] havoc activate_threads_~tmp___4~0; [L845] havoc activate_threads_~tmp___5~0; [L849] havoc is_master_triggered_#res; [L849] havoc is_master_triggered_~__retres1~0; [L333] havoc is_master_triggered_~__retres1~0; [L336-L345] assume !(1 == ~m_pc~0); [L346] is_master_triggered_~__retres1~0 := 0; [L348] is_master_triggered_#res := is_master_triggered_~__retres1~0; [L849] activate_threads_#t~ret10 := is_master_triggered_#res; [L849] activate_threads_~tmp~1 := activate_threads_#t~ret10; [L849] havoc activate_threads_#t~ret10; [L851-L855] assume !(0 != activate_threads_~tmp~1); [L857] havoc is_transmit1_triggered_#res; [L857] havoc is_transmit1_triggered_~__retres1~1; [L352] havoc is_transmit1_triggered_~__retres1~1; [L355-L364] assume !(1 == ~t1_pc~0); [L365] is_transmit1_triggered_~__retres1~1 := 0; [L367] is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; [L857] activate_threads_#t~ret11 := is_transmit1_triggered_#res; [L857] activate_threads_~tmp___0~0 := activate_threads_#t~ret11; [L857] havoc activate_threads_#t~ret11; [L859-L863] assume !(0 != activate_threads_~tmp___0~0); [L865] havoc is_transmit2_triggered_#res; [L865] havoc is_transmit2_triggered_~__retres1~2; [L371] havoc is_transmit2_triggered_~__retres1~2; [L374-L383] assume !(1 == ~t2_pc~0); [L384] is_transmit2_triggered_~__retres1~2 := 0; [L386] is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; [L865] activate_threads_#t~ret12 := is_transmit2_triggered_#res; [L865] activate_threads_~tmp___1~0 := activate_threads_#t~ret12; [L865] havoc activate_threads_#t~ret12; [L867-L871] assume !(0 != activate_threads_~tmp___1~0); [L873] havoc is_transmit3_triggered_#res; [L873] havoc is_transmit3_triggered_~__retres1~3; [L390] havoc is_transmit3_triggered_~__retres1~3; [L393-L402] assume !(1 == ~t3_pc~0); [L403] is_transmit3_triggered_~__retres1~3 := 0; [L405] is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; [L873] activate_threads_#t~ret13 := is_transmit3_triggered_#res; [L873] activate_threads_~tmp___2~0 := activate_threads_#t~ret13; [L873] havoc activate_threads_#t~ret13; [L875-L879] assume !(0 != activate_threads_~tmp___2~0); [L881] havoc is_transmit4_triggered_#res; [L881] havoc is_transmit4_triggered_~__retres1~4; [L409] havoc is_transmit4_triggered_~__retres1~4; [L412-L421] assume !(1 == ~t4_pc~0); [L422] is_transmit4_triggered_~__retres1~4 := 0; [L424] is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; [L881] activate_threads_#t~ret14 := is_transmit4_triggered_#res; [L881] activate_threads_~tmp___3~0 := activate_threads_#t~ret14; [L881] havoc activate_threads_#t~ret14; [L883-L887] assume !(0 != activate_threads_~tmp___3~0); [L889] havoc is_transmit5_triggered_#res; [L889] havoc is_transmit5_triggered_~__retres1~5; [L428] havoc is_transmit5_triggered_~__retres1~5; [L431-L440] assume !(1 == ~t5_pc~0); [L441] is_transmit5_triggered_~__retres1~5 := 0; [L443] is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; [L889] activate_threads_#t~ret15 := is_transmit5_triggered_#res; [L889] activate_threads_~tmp___4~0 := activate_threads_#t~ret15; [L889] havoc activate_threads_#t~ret15; [L891-L895] assume !(0 != activate_threads_~tmp___4~0); [L897] havoc is_transmit6_triggered_#res; [L897] havoc is_transmit6_triggered_~__retres1~6; [L447] havoc is_transmit6_triggered_~__retres1~6; [L450-L459] assume !(1 == ~t6_pc~0); [L460] is_transmit6_triggered_~__retres1~6 := 0; [L462] is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; [L897] activate_threads_#t~ret16 := is_transmit6_triggered_#res; [L897] activate_threads_~tmp___5~0 := activate_threads_#t~ret16; [L897] havoc activate_threads_#t~ret16; [L899-L903] assume !(0 != activate_threads_~tmp___5~0); [L764-L768] assume !(1 == ~M_E~0); [L769-L773] assume !(1 == ~T1_E~0); [L774-L778] assume !(1 == ~T2_E~0); [L779-L783] assume !(1 == ~T3_E~0); [L784-L788] assume !(1 == ~T4_E~0); [L789-L793] assume !(1 == ~T5_E~0); [L794-L798] assume !(1 == ~T6_E~0); [L799-L803] assume !(1 == ~E_M~0); [L804-L808] assume !(1 == ~E_1~0); [L809-L813] assume !(1 == ~E_2~0); [L814-L818] assume !(1 == ~E_3~0); [L819-L823] assume !(1 == ~E_4~0); [L824-L828] assume !(1 == ~E_5~0); [L829-L833] assume !(1 == ~E_6~0); [L1055-L1092] assume !false; [L1058] start_simulation_~kernel_st~0 := 1; [L1059] havoc eval_#t~ret2, eval_#t~nondet3, eval_~tmp_ndt_1~0, eval_#t~nondet4, eval_~tmp_ndt_2~0, eval_#t~nondet5, eval_~tmp_ndt_3~0, eval_#t~nondet6, eval_~tmp_ndt_4~0, eval_#t~nondet7, eval_~tmp_ndt_5~0, eval_#t~nondet8, eval_~tmp_ndt_6~0, eval_#t~nondet9, eval_~tmp_ndt_7~0, eval_~tmp~0; [L563] havoc eval_~tmp~0; ----- ----- class de.uni_freiburg.informatik.ultimate.boogie.preprocessor.BoogiePreprocessorBacktranslator [L14] ~m_pc~0 := 0; [L15] ~t1_pc~0 := 0; [L16] ~t2_pc~0 := 0; [L17] ~t3_pc~0 := 0; [L18] ~t4_pc~0 := 0; [L19] ~t5_pc~0 := 0; [L20] ~t6_pc~0 := 0; [L21] ~m_st~0 := 0; [L22] ~t1_st~0 := 0; [L23] ~t2_st~0 := 0; [L24] ~t3_st~0 := 0; [L25] ~t4_st~0 := 0; [L26] ~t5_st~0 := 0; [L27] ~t6_st~0 := 0; [L28] ~m_i~0 := 0; [L29] ~t1_i~0 := 0; [L30] ~t2_i~0 := 0; [L31] ~t3_i~0 := 0; [L32] ~t4_i~0 := 0; [L33] ~t5_i~0 := 0; [L34] ~t6_i~0 := 0; [L35] ~M_E~0 := 2; [L36] ~T1_E~0 := 2; [L37] ~T2_E~0 := 2; [L38] ~T3_E~0 := 2; [L39] ~T4_E~0 := 2; [L40] ~T5_E~0 := 2; [L41] ~T6_E~0 := 2; [L42] ~E_M~0 := 2; [L43] ~E_1~0 := 2; [L44] ~E_2~0 := 2; [L45] ~E_3~0 := 2; [L46] ~E_4~0 := 2; [L47] ~E_5~0 := 2; [L48] ~E_6~0 := 2; [L57] ~token~0 := 0; [L59] ~local~0 := 0; [?] havoc main_#res; [?] havoc main_~__retres1~8; [L1100] havoc main_~__retres1~8; [L1010] ~m_i~0 := 1; [L1011] ~t1_i~0 := 1; [L1012] ~t2_i~0 := 1; [L1013] ~t3_i~0 := 1; [L1014] ~t4_i~0 := 1; [L1015] ~t5_i~0 := 1; [L1016] ~t6_i~0 := 1; [L1105] havoc start_simulation_#t~ret18, start_simulation_#t~ret19, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1; [L1041] havoc start_simulation_~kernel_st~0; [L1042] havoc start_simulation_~tmp~3; [L1043] havoc start_simulation_~tmp___0~1; [L1047] start_simulation_~kernel_st~0 := 0; [L477-L481] assume 1 == ~m_i~0; [L478] ~m_st~0 := 0; [L482-L486] assume 1 == ~t1_i~0; [L483] ~t1_st~0 := 0; [L487-L491] assume 1 == ~t2_i~0; [L488] ~t2_st~0 := 0; [L492-L496] assume 1 == ~t3_i~0; [L493] ~t3_st~0 := 0; [L497-L501] assume 1 == ~t4_i~0; [L498] ~t4_st~0 := 0; [L502-L506] assume 1 == ~t5_i~0; [L503] ~t5_st~0 := 0; [L507-L511] assume 1 == ~t6_i~0; [L508] ~t6_st~0 := 0; [L686-L690] assume !(0 == ~M_E~0); [L691-L695] assume !(0 == ~T1_E~0); [L696-L700] assume !(0 == ~T2_E~0); [L701-L705] assume !(0 == ~T3_E~0); [L706-L710] assume !(0 == ~T4_E~0); [L711-L715] assume !(0 == ~T5_E~0); [L716-L720] assume !(0 == ~T6_E~0); [L721-L725] assume !(0 == ~E_M~0); [L726-L730] assume !(0 == ~E_1~0); [L731-L735] assume !(0 == ~E_2~0); [L736-L740] assume !(0 == ~E_3~0); [L741-L745] assume !(0 == ~E_4~0); [L746-L750] assume !(0 == ~E_5~0); [L751-L755] assume !(0 == ~E_6~0); [L1051] havoc activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0; [L839] havoc activate_threads_~tmp~1; [L840] havoc activate_threads_~tmp___0~0; [L841] havoc activate_threads_~tmp___1~0; [L842] havoc activate_threads_~tmp___2~0; [L843] havoc activate_threads_~tmp___3~0; [L844] havoc activate_threads_~tmp___4~0; [L845] havoc activate_threads_~tmp___5~0; [L849] havoc is_master_triggered_#res; [L849] havoc is_master_triggered_~__retres1~0; [L333] havoc is_master_triggered_~__retres1~0; [L336-L345] assume !(1 == ~m_pc~0); [L346] is_master_triggered_~__retres1~0 := 0; [L348] is_master_triggered_#res := is_master_triggered_~__retres1~0; [L849] activate_threads_#t~ret10 := is_master_triggered_#res; [L849] activate_threads_~tmp~1 := activate_threads_#t~ret10; [L849] havoc activate_threads_#t~ret10; [L851-L855] assume !(0 != activate_threads_~tmp~1); [L857] havoc is_transmit1_triggered_#res; [L857] havoc is_transmit1_triggered_~__retres1~1; [L352] havoc is_transmit1_triggered_~__retres1~1; [L355-L364] assume !(1 == ~t1_pc~0); [L365] is_transmit1_triggered_~__retres1~1 := 0; [L367] is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; [L857] activate_threads_#t~ret11 := is_transmit1_triggered_#res; [L857] activate_threads_~tmp___0~0 := activate_threads_#t~ret11; [L857] havoc activate_threads_#t~ret11; [L859-L863] assume !(0 != activate_threads_~tmp___0~0); [L865] havoc is_transmit2_triggered_#res; [L865] havoc is_transmit2_triggered_~__retres1~2; [L371] havoc is_transmit2_triggered_~__retres1~2; [L374-L383] assume !(1 == ~t2_pc~0); [L384] is_transmit2_triggered_~__retres1~2 := 0; [L386] is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; [L865] activate_threads_#t~ret12 := is_transmit2_triggered_#res; [L865] activate_threads_~tmp___1~0 := activate_threads_#t~ret12; [L865] havoc activate_threads_#t~ret12; [L867-L871] assume !(0 != activate_threads_~tmp___1~0); [L873] havoc is_transmit3_triggered_#res; [L873] havoc is_transmit3_triggered_~__retres1~3; [L390] havoc is_transmit3_triggered_~__retres1~3; [L393-L402] assume !(1 == ~t3_pc~0); [L403] is_transmit3_triggered_~__retres1~3 := 0; [L405] is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; [L873] activate_threads_#t~ret13 := is_transmit3_triggered_#res; [L873] activate_threads_~tmp___2~0 := activate_threads_#t~ret13; [L873] havoc activate_threads_#t~ret13; [L875-L879] assume !(0 != activate_threads_~tmp___2~0); [L881] havoc is_transmit4_triggered_#res; [L881] havoc is_transmit4_triggered_~__retres1~4; [L409] havoc is_transmit4_triggered_~__retres1~4; [L412-L421] assume !(1 == ~t4_pc~0); [L422] is_transmit4_triggered_~__retres1~4 := 0; [L424] is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; [L881] activate_threads_#t~ret14 := is_transmit4_triggered_#res; [L881] activate_threads_~tmp___3~0 := activate_threads_#t~ret14; [L881] havoc activate_threads_#t~ret14; [L883-L887] assume !(0 != activate_threads_~tmp___3~0); [L889] havoc is_transmit5_triggered_#res; [L889] havoc is_transmit5_triggered_~__retres1~5; [L428] havoc is_transmit5_triggered_~__retres1~5; [L431-L440] assume !(1 == ~t5_pc~0); [L441] is_transmit5_triggered_~__retres1~5 := 0; [L443] is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; [L889] activate_threads_#t~ret15 := is_transmit5_triggered_#res; [L889] activate_threads_~tmp___4~0 := activate_threads_#t~ret15; [L889] havoc activate_threads_#t~ret15; [L891-L895] assume !(0 != activate_threads_~tmp___4~0); [L897] havoc is_transmit6_triggered_#res; [L897] havoc is_transmit6_triggered_~__retres1~6; [L447] havoc is_transmit6_triggered_~__retres1~6; [L450-L459] assume !(1 == ~t6_pc~0); [L460] is_transmit6_triggered_~__retres1~6 := 0; [L462] is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; [L897] activate_threads_#t~ret16 := is_transmit6_triggered_#res; [L897] activate_threads_~tmp___5~0 := activate_threads_#t~ret16; [L897] havoc activate_threads_#t~ret16; [L899-L903] assume !(0 != activate_threads_~tmp___5~0); [L764-L768] assume !(1 == ~M_E~0); [L769-L773] assume !(1 == ~T1_E~0); [L774-L778] assume !(1 == ~T2_E~0); [L779-L783] assume !(1 == ~T3_E~0); [L784-L788] assume !(1 == ~T4_E~0); [L789-L793] assume !(1 == ~T5_E~0); [L794-L798] assume !(1 == ~T6_E~0); [L799-L803] assume !(1 == ~E_M~0); [L804-L808] assume !(1 == ~E_1~0); [L809-L813] assume !(1 == ~E_2~0); [L814-L818] assume !(1 == ~E_3~0); [L819-L823] assume !(1 == ~E_4~0); [L824-L828] assume !(1 == ~E_5~0); [L829-L833] assume !(1 == ~E_6~0); [L1055-L1092] assume !false; [L1058] start_simulation_~kernel_st~0 := 1; [L1059] havoc eval_#t~ret2, eval_#t~nondet3, eval_~tmp_ndt_1~0, eval_#t~nondet4, eval_~tmp_ndt_2~0, eval_#t~nondet5, eval_~tmp_ndt_3~0, eval_#t~nondet6, eval_~tmp_ndt_4~0, eval_#t~nondet7, eval_~tmp_ndt_5~0, eval_#t~nondet8, eval_~tmp_ndt_6~0, eval_#t~nondet9, eval_~tmp_ndt_7~0, eval_~tmp~0; [L563] havoc eval_~tmp~0; [L14] ~m_pc~0 := 0; [L15] ~t1_pc~0 := 0; [L16] ~t2_pc~0 := 0; [L17] ~t3_pc~0 := 0; [L18] ~t4_pc~0 := 0; [L19] ~t5_pc~0 := 0; [L20] ~t6_pc~0 := 0; [L21] ~m_st~0 := 0; [L22] ~t1_st~0 := 0; [L23] ~t2_st~0 := 0; [L24] ~t3_st~0 := 0; [L25] ~t4_st~0 := 0; [L26] ~t5_st~0 := 0; [L27] ~t6_st~0 := 0; [L28] ~m_i~0 := 0; [L29] ~t1_i~0 := 0; [L30] ~t2_i~0 := 0; [L31] ~t3_i~0 := 0; [L32] ~t4_i~0 := 0; [L33] ~t5_i~0 := 0; [L34] ~t6_i~0 := 0; [L35] ~M_E~0 := 2; [L36] ~T1_E~0 := 2; [L37] ~T2_E~0 := 2; [L38] ~T3_E~0 := 2; [L39] ~T4_E~0 := 2; [L40] ~T5_E~0 := 2; [L41] ~T6_E~0 := 2; [L42] ~E_M~0 := 2; [L43] ~E_1~0 := 2; [L44] ~E_2~0 := 2; [L45] ~E_3~0 := 2; [L46] ~E_4~0 := 2; [L47] ~E_5~0 := 2; [L48] ~E_6~0 := 2; [L57] ~token~0 := 0; [L59] ~local~0 := 0; [?] havoc main_#res; [?] havoc main_~__retres1~8; [L1100] havoc main_~__retres1~8; [L1010] ~m_i~0 := 1; [L1011] ~t1_i~0 := 1; [L1012] ~t2_i~0 := 1; [L1013] ~t3_i~0 := 1; [L1014] ~t4_i~0 := 1; [L1015] ~t5_i~0 := 1; [L1016] ~t6_i~0 := 1; [L1105] havoc start_simulation_#t~ret18, start_simulation_#t~ret19, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1; [L1041] havoc start_simulation_~kernel_st~0; [L1042] havoc start_simulation_~tmp~3; [L1043] havoc start_simulation_~tmp___0~1; [L1047] start_simulation_~kernel_st~0 := 0; [L477] COND TRUE 1 == ~m_i~0 [L478] ~m_st~0 := 0; [L482] COND TRUE 1 == ~t1_i~0 [L483] ~t1_st~0 := 0; [L487] COND TRUE 1 == ~t2_i~0 [L488] ~t2_st~0 := 0; [L492] COND TRUE 1 == ~t3_i~0 [L493] ~t3_st~0 := 0; [L497] COND TRUE 1 == ~t4_i~0 [L498] ~t4_st~0 := 0; [L502] COND TRUE 1 == ~t5_i~0 [L503] ~t5_st~0 := 0; [L507] COND TRUE 1 == ~t6_i~0 [L508] ~t6_st~0 := 0; [L686] COND FALSE !(0 == ~M_E~0) [L691] COND FALSE !(0 == ~T1_E~0) [L696] COND FALSE !(0 == ~T2_E~0) [L701] COND FALSE !(0 == ~T3_E~0) [L706] COND FALSE !(0 == ~T4_E~0) [L711] COND FALSE !(0 == ~T5_E~0) [L716] COND FALSE !(0 == ~T6_E~0) [L721] COND FALSE !(0 == ~E_M~0) [L726] COND FALSE !(0 == ~E_1~0) [L731] COND FALSE !(0 == ~E_2~0) [L736] COND FALSE !(0 == ~E_3~0) [L741] COND FALSE !(0 == ~E_4~0) [L746] COND FALSE !(0 == ~E_5~0) [L751] COND FALSE !(0 == ~E_6~0) [L1051] havoc activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0; [L839] havoc activate_threads_~tmp~1; [L840] havoc activate_threads_~tmp___0~0; [L841] havoc activate_threads_~tmp___1~0; [L842] havoc activate_threads_~tmp___2~0; [L843] havoc activate_threads_~tmp___3~0; [L844] havoc activate_threads_~tmp___4~0; [L845] havoc activate_threads_~tmp___5~0; [L849] havoc is_master_triggered_#res; [L849] havoc is_master_triggered_~__retres1~0; [L333] havoc is_master_triggered_~__retres1~0; [L336] COND FALSE !(1 == ~m_pc~0) [L346] is_master_triggered_~__retres1~0 := 0; [L348] is_master_triggered_#res := is_master_triggered_~__retres1~0; [L849] activate_threads_#t~ret10 := is_master_triggered_#res; [L849] activate_threads_~tmp~1 := activate_threads_#t~ret10; [L849] havoc activate_threads_#t~ret10; [L851-L855] COND FALSE !(0 != activate_threads_~tmp~1) [L857] havoc is_transmit1_triggered_#res; [L857] havoc is_transmit1_triggered_~__retres1~1; [L352] havoc is_transmit1_triggered_~__retres1~1; [L355] COND FALSE !(1 == ~t1_pc~0) [L365] is_transmit1_triggered_~__retres1~1 := 0; [L367] is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; [L857] activate_threads_#t~ret11 := is_transmit1_triggered_#res; [L857] activate_threads_~tmp___0~0 := activate_threads_#t~ret11; [L857] havoc activate_threads_#t~ret11; [L859-L863] COND FALSE !(0 != activate_threads_~tmp___0~0) [L865] havoc is_transmit2_triggered_#res; [L865] havoc is_transmit2_triggered_~__retres1~2; [L371] havoc is_transmit2_triggered_~__retres1~2; [L374] COND FALSE !(1 == ~t2_pc~0) [L384] is_transmit2_triggered_~__retres1~2 := 0; [L386] is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; [L865] activate_threads_#t~ret12 := is_transmit2_triggered_#res; [L865] activate_threads_~tmp___1~0 := activate_threads_#t~ret12; [L865] havoc activate_threads_#t~ret12; [L867-L871] COND FALSE !(0 != activate_threads_~tmp___1~0) [L873] havoc is_transmit3_triggered_#res; [L873] havoc is_transmit3_triggered_~__retres1~3; [L390] havoc is_transmit3_triggered_~__retres1~3; [L393] COND FALSE !(1 == ~t3_pc~0) [L403] is_transmit3_triggered_~__retres1~3 := 0; [L405] is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; [L873] activate_threads_#t~ret13 := is_transmit3_triggered_#res; [L873] activate_threads_~tmp___2~0 := activate_threads_#t~ret13; [L873] havoc activate_threads_#t~ret13; [L875-L879] COND FALSE !(0 != activate_threads_~tmp___2~0) [L881] havoc is_transmit4_triggered_#res; [L881] havoc is_transmit4_triggered_~__retres1~4; [L409] havoc is_transmit4_triggered_~__retres1~4; [L412] COND FALSE !(1 == ~t4_pc~0) [L422] is_transmit4_triggered_~__retres1~4 := 0; [L424] is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; [L881] activate_threads_#t~ret14 := is_transmit4_triggered_#res; [L881] activate_threads_~tmp___3~0 := activate_threads_#t~ret14; [L881] havoc activate_threads_#t~ret14; [L883-L887] COND FALSE !(0 != activate_threads_~tmp___3~0) [L889] havoc is_transmit5_triggered_#res; [L889] havoc is_transmit5_triggered_~__retres1~5; [L428] havoc is_transmit5_triggered_~__retres1~5; [L431] COND FALSE !(1 == ~t5_pc~0) [L441] is_transmit5_triggered_~__retres1~5 := 0; [L443] is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; [L889] activate_threads_#t~ret15 := is_transmit5_triggered_#res; [L889] activate_threads_~tmp___4~0 := activate_threads_#t~ret15; [L889] havoc activate_threads_#t~ret15; [L891-L895] COND FALSE !(0 != activate_threads_~tmp___4~0) [L897] havoc is_transmit6_triggered_#res; [L897] havoc is_transmit6_triggered_~__retres1~6; [L447] havoc is_transmit6_triggered_~__retres1~6; [L450] COND FALSE !(1 == ~t6_pc~0) [L460] is_transmit6_triggered_~__retres1~6 := 0; [L462] is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; [L897] activate_threads_#t~ret16 := is_transmit6_triggered_#res; [L897] activate_threads_~tmp___5~0 := activate_threads_#t~ret16; [L897] havoc activate_threads_#t~ret16; [L899-L903] COND FALSE !(0 != activate_threads_~tmp___5~0) [L764] COND FALSE !(1 == ~M_E~0) [L769] COND FALSE !(1 == ~T1_E~0) [L774] COND FALSE !(1 == ~T2_E~0) [L779] COND FALSE !(1 == ~T3_E~0) [L784] COND FALSE !(1 == ~T4_E~0) [L789] COND FALSE !(1 == ~T5_E~0) [L794] COND FALSE !(1 == ~T6_E~0) [L799] COND FALSE !(1 == ~E_M~0) [L804] COND FALSE !(1 == ~E_1~0) [L809] COND FALSE !(1 == ~E_2~0) [L814] COND FALSE !(1 == ~E_3~0) [L819] COND FALSE !(1 == ~E_4~0) [L824] COND FALSE !(1 == ~E_5~0) [L829] COND FALSE !(1 == ~E_6~0) [L1055-L1092] COND FALSE !(false) [L1058] start_simulation_~kernel_st~0 := 1; [L1059] havoc eval_#t~ret2, eval_#t~nondet3, eval_~tmp_ndt_1~0, eval_#t~nondet4, eval_~tmp_ndt_2~0, eval_#t~nondet5, eval_~tmp_ndt_3~0, eval_#t~nondet6, eval_~tmp_ndt_4~0, eval_#t~nondet7, eval_~tmp_ndt_5~0, eval_#t~nondet8, eval_~tmp_ndt_6~0, eval_#t~nondet9, eval_~tmp_ndt_7~0, eval_~tmp~0; [L563] havoc eval_~tmp~0; ----- ----- class de.uni_freiburg.informatik.ultimate.boogie.procedureinliner.backtranslation.InlinerBacktranslator [L14] ~m_pc~0 := 0; [L15] ~t1_pc~0 := 0; [L16] ~t2_pc~0 := 0; [L17] ~t3_pc~0 := 0; [L18] ~t4_pc~0 := 0; [L19] ~t5_pc~0 := 0; [L20] ~t6_pc~0 := 0; [L21] ~m_st~0 := 0; [L22] ~t1_st~0 := 0; [L23] ~t2_st~0 := 0; [L24] ~t3_st~0 := 0; [L25] ~t4_st~0 := 0; [L26] ~t5_st~0 := 0; [L27] ~t6_st~0 := 0; [L28] ~m_i~0 := 0; [L29] ~t1_i~0 := 0; [L30] ~t2_i~0 := 0; [L31] ~t3_i~0 := 0; [L32] ~t4_i~0 := 0; [L33] ~t5_i~0 := 0; [L34] ~t6_i~0 := 0; [L35] ~M_E~0 := 2; [L36] ~T1_E~0 := 2; [L37] ~T2_E~0 := 2; [L38] ~T3_E~0 := 2; [L39] ~T4_E~0 := 2; [L40] ~T5_E~0 := 2; [L41] ~T6_E~0 := 2; [L42] ~E_M~0 := 2; [L43] ~E_1~0 := 2; [L44] ~E_2~0 := 2; [L45] ~E_3~0 := 2; [L46] ~E_4~0 := 2; [L47] ~E_5~0 := 2; [L48] ~E_6~0 := 2; [L57] ~token~0 := 0; [L59] ~local~0 := 0; [?] havoc main_#res; [?] havoc main_~__retres1~8; [L1100] havoc main_~__retres1~8; [L1010] ~m_i~0 := 1; [L1011] ~t1_i~0 := 1; [L1012] ~t2_i~0 := 1; [L1013] ~t3_i~0 := 1; [L1014] ~t4_i~0 := 1; [L1015] ~t5_i~0 := 1; [L1016] ~t6_i~0 := 1; [L1105] havoc start_simulation_#t~ret18, start_simulation_#t~ret19, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1; [L1041] havoc start_simulation_~kernel_st~0; [L1042] havoc start_simulation_~tmp~3; [L1043] havoc start_simulation_~tmp___0~1; [L1047] start_simulation_~kernel_st~0 := 0; [L477] COND TRUE 1 == ~m_i~0 [L478] ~m_st~0 := 0; [L482] COND TRUE 1 == ~t1_i~0 [L483] ~t1_st~0 := 0; [L487] COND TRUE 1 == ~t2_i~0 [L488] ~t2_st~0 := 0; [L492] COND TRUE 1 == ~t3_i~0 [L493] ~t3_st~0 := 0; [L497] COND TRUE 1 == ~t4_i~0 [L498] ~t4_st~0 := 0; [L502] COND TRUE 1 == ~t5_i~0 [L503] ~t5_st~0 := 0; [L507] COND TRUE 1 == ~t6_i~0 [L508] ~t6_st~0 := 0; [L686] COND FALSE !(0 == ~M_E~0) [L691] COND FALSE !(0 == ~T1_E~0) [L696] COND FALSE !(0 == ~T2_E~0) [L701] COND FALSE !(0 == ~T3_E~0) [L706] COND FALSE !(0 == ~T4_E~0) [L711] COND FALSE !(0 == ~T5_E~0) [L716] COND FALSE !(0 == ~T6_E~0) [L721] COND FALSE !(0 == ~E_M~0) [L726] COND FALSE !(0 == ~E_1~0) [L731] COND FALSE !(0 == ~E_2~0) [L736] COND FALSE !(0 == ~E_3~0) [L741] COND FALSE !(0 == ~E_4~0) [L746] COND FALSE !(0 == ~E_5~0) [L751] COND FALSE !(0 == ~E_6~0) [L1051] havoc activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0; [L839] havoc activate_threads_~tmp~1; [L840] havoc activate_threads_~tmp___0~0; [L841] havoc activate_threads_~tmp___1~0; [L842] havoc activate_threads_~tmp___2~0; [L843] havoc activate_threads_~tmp___3~0; [L844] havoc activate_threads_~tmp___4~0; [L845] havoc activate_threads_~tmp___5~0; [L849] havoc is_master_triggered_#res; [L849] havoc is_master_triggered_~__retres1~0; [L333] havoc is_master_triggered_~__retres1~0; [L336] COND FALSE !(1 == ~m_pc~0) [L346] is_master_triggered_~__retres1~0 := 0; [L348] is_master_triggered_#res := is_master_triggered_~__retres1~0; [L849] activate_threads_#t~ret10 := is_master_triggered_#res; [L849] activate_threads_~tmp~1 := activate_threads_#t~ret10; [L849] havoc activate_threads_#t~ret10; [L851-L855] COND FALSE !(0 != activate_threads_~tmp~1) [L857] havoc is_transmit1_triggered_#res; [L857] havoc is_transmit1_triggered_~__retres1~1; [L352] havoc is_transmit1_triggered_~__retres1~1; [L355] COND FALSE !(1 == ~t1_pc~0) [L365] is_transmit1_triggered_~__retres1~1 := 0; [L367] is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; [L857] activate_threads_#t~ret11 := is_transmit1_triggered_#res; [L857] activate_threads_~tmp___0~0 := activate_threads_#t~ret11; [L857] havoc activate_threads_#t~ret11; [L859-L863] COND FALSE !(0 != activate_threads_~tmp___0~0) [L865] havoc is_transmit2_triggered_#res; [L865] havoc is_transmit2_triggered_~__retres1~2; [L371] havoc is_transmit2_triggered_~__retres1~2; [L374] COND FALSE !(1 == ~t2_pc~0) [L384] is_transmit2_triggered_~__retres1~2 := 0; [L386] is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; [L865] activate_threads_#t~ret12 := is_transmit2_triggered_#res; [L865] activate_threads_~tmp___1~0 := activate_threads_#t~ret12; [L865] havoc activate_threads_#t~ret12; [L867-L871] COND FALSE !(0 != activate_threads_~tmp___1~0) [L873] havoc is_transmit3_triggered_#res; [L873] havoc is_transmit3_triggered_~__retres1~3; [L390] havoc is_transmit3_triggered_~__retres1~3; [L393] COND FALSE !(1 == ~t3_pc~0) [L403] is_transmit3_triggered_~__retres1~3 := 0; [L405] is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; [L873] activate_threads_#t~ret13 := is_transmit3_triggered_#res; [L873] activate_threads_~tmp___2~0 := activate_threads_#t~ret13; [L873] havoc activate_threads_#t~ret13; [L875-L879] COND FALSE !(0 != activate_threads_~tmp___2~0) [L881] havoc is_transmit4_triggered_#res; [L881] havoc is_transmit4_triggered_~__retres1~4; [L409] havoc is_transmit4_triggered_~__retres1~4; [L412] COND FALSE !(1 == ~t4_pc~0) [L422] is_transmit4_triggered_~__retres1~4 := 0; [L424] is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; [L881] activate_threads_#t~ret14 := is_transmit4_triggered_#res; [L881] activate_threads_~tmp___3~0 := activate_threads_#t~ret14; [L881] havoc activate_threads_#t~ret14; [L883-L887] COND FALSE !(0 != activate_threads_~tmp___3~0) [L889] havoc is_transmit5_triggered_#res; [L889] havoc is_transmit5_triggered_~__retres1~5; [L428] havoc is_transmit5_triggered_~__retres1~5; [L431] COND FALSE !(1 == ~t5_pc~0) [L441] is_transmit5_triggered_~__retres1~5 := 0; [L443] is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; [L889] activate_threads_#t~ret15 := is_transmit5_triggered_#res; [L889] activate_threads_~tmp___4~0 := activate_threads_#t~ret15; [L889] havoc activate_threads_#t~ret15; [L891-L895] COND FALSE !(0 != activate_threads_~tmp___4~0) [L897] havoc is_transmit6_triggered_#res; [L897] havoc is_transmit6_triggered_~__retres1~6; [L447] havoc is_transmit6_triggered_~__retres1~6; [L450] COND FALSE !(1 == ~t6_pc~0) [L460] is_transmit6_triggered_~__retres1~6 := 0; [L462] is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; [L897] activate_threads_#t~ret16 := is_transmit6_triggered_#res; [L897] activate_threads_~tmp___5~0 := activate_threads_#t~ret16; [L897] havoc activate_threads_#t~ret16; [L899-L903] COND FALSE !(0 != activate_threads_~tmp___5~0) [L764] COND FALSE !(1 == ~M_E~0) [L769] COND FALSE !(1 == ~T1_E~0) [L774] COND FALSE !(1 == ~T2_E~0) [L779] COND FALSE !(1 == ~T3_E~0) [L784] COND FALSE !(1 == ~T4_E~0) [L789] COND FALSE !(1 == ~T5_E~0) [L794] COND FALSE !(1 == ~T6_E~0) [L799] COND FALSE !(1 == ~E_M~0) [L804] COND FALSE !(1 == ~E_1~0) [L809] COND FALSE !(1 == ~E_2~0) [L814] COND FALSE !(1 == ~E_3~0) [L819] COND FALSE !(1 == ~E_4~0) [L824] COND FALSE !(1 == ~E_5~0) [L829] COND FALSE !(1 == ~E_6~0) [L1055-L1092] COND FALSE !(false) [L1058] start_simulation_~kernel_st~0 := 1; [L1059] havoc eval_#t~ret2, eval_#t~nondet3, eval_~tmp_ndt_1~0, eval_#t~nondet4, eval_~tmp_ndt_2~0, eval_#t~nondet5, eval_~tmp_ndt_3~0, eval_#t~nondet6, eval_~tmp_ndt_4~0, eval_#t~nondet7, eval_~tmp_ndt_5~0, eval_#t~nondet8, eval_~tmp_ndt_6~0, eval_#t~nondet9, eval_~tmp_ndt_7~0, eval_~tmp~0; [L563] havoc eval_~tmp~0; [L14] ~m_pc~0 := 0; [L15] ~t1_pc~0 := 0; [L16] ~t2_pc~0 := 0; [L17] ~t3_pc~0 := 0; [L18] ~t4_pc~0 := 0; [L19] ~t5_pc~0 := 0; [L20] ~t6_pc~0 := 0; [L21] ~m_st~0 := 0; [L22] ~t1_st~0 := 0; [L23] ~t2_st~0 := 0; [L24] ~t3_st~0 := 0; [L25] ~t4_st~0 := 0; [L26] ~t5_st~0 := 0; [L27] ~t6_st~0 := 0; [L28] ~m_i~0 := 0; [L29] ~t1_i~0 := 0; [L30] ~t2_i~0 := 0; [L31] ~t3_i~0 := 0; [L32] ~t4_i~0 := 0; [L33] ~t5_i~0 := 0; [L34] ~t6_i~0 := 0; [L35] ~M_E~0 := 2; [L36] ~T1_E~0 := 2; [L37] ~T2_E~0 := 2; [L38] ~T3_E~0 := 2; [L39] ~T4_E~0 := 2; [L40] ~T5_E~0 := 2; [L41] ~T6_E~0 := 2; [L42] ~E_M~0 := 2; [L43] ~E_1~0 := 2; [L44] ~E_2~0 := 2; [L45] ~E_3~0 := 2; [L46] ~E_4~0 := 2; [L47] ~E_5~0 := 2; [L48] ~E_6~0 := 2; [L57] ~token~0 := 0; [L59] ~local~0 := 0; [L1100] havoc ~__retres1~8; [L1010] ~m_i~0 := 1; [L1011] ~t1_i~0 := 1; [L1012] ~t2_i~0 := 1; [L1013] ~t3_i~0 := 1; [L1014] ~t4_i~0 := 1; [L1015] ~t5_i~0 := 1; [L1016] ~t6_i~0 := 1; [L1041] havoc ~kernel_st~0; [L1042] havoc ~tmp~3; [L1043] havoc ~tmp___0~1; [L1047] ~kernel_st~0 := 0; [L477] COND TRUE 1 == ~m_i~0 [L478] ~m_st~0 := 0; [L482] COND TRUE 1 == ~t1_i~0 [L483] ~t1_st~0 := 0; [L487] COND TRUE 1 == ~t2_i~0 [L488] ~t2_st~0 := 0; [L492] COND TRUE 1 == ~t3_i~0 [L493] ~t3_st~0 := 0; [L497] COND TRUE 1 == ~t4_i~0 [L498] ~t4_st~0 := 0; [L502] COND TRUE 1 == ~t5_i~0 [L503] ~t5_st~0 := 0; [L507] COND TRUE 1 == ~t6_i~0 [L508] ~t6_st~0 := 0; [L686] COND FALSE !(0 == ~M_E~0) [L691] COND FALSE !(0 == ~T1_E~0) [L696] COND FALSE !(0 == ~T2_E~0) [L701] COND FALSE !(0 == ~T3_E~0) [L706] COND FALSE !(0 == ~T4_E~0) [L711] COND FALSE !(0 == ~T5_E~0) [L716] COND FALSE !(0 == ~T6_E~0) [L721] COND FALSE !(0 == ~E_M~0) [L726] COND FALSE !(0 == ~E_1~0) [L731] COND FALSE !(0 == ~E_2~0) [L736] COND FALSE !(0 == ~E_3~0) [L741] COND FALSE !(0 == ~E_4~0) [L746] COND FALSE !(0 == ~E_5~0) [L751] COND FALSE !(0 == ~E_6~0) [L839] havoc ~tmp~1; [L840] havoc ~tmp___0~0; [L841] havoc ~tmp___1~0; [L842] havoc ~tmp___2~0; [L843] havoc ~tmp___3~0; [L844] havoc ~tmp___4~0; [L845] havoc ~tmp___5~0; [L333] havoc ~__retres1~0; [L336] COND FALSE !(1 == ~m_pc~0) [L346] ~__retres1~0 := 0; [L348] #res := ~__retres1~0; [L849] ~tmp~1 := #t~ret10; [L849] havoc #t~ret10; [L851-L855] COND FALSE !(0 != ~tmp~1) [L352] havoc ~__retres1~1; [L355] COND FALSE !(1 == ~t1_pc~0) [L365] ~__retres1~1 := 0; [L367] #res := ~__retres1~1; [L857] ~tmp___0~0 := #t~ret11; [L857] havoc #t~ret11; [L859-L863] COND FALSE !(0 != ~tmp___0~0) [L371] havoc ~__retres1~2; [L374] COND FALSE !(1 == ~t2_pc~0) [L384] ~__retres1~2 := 0; [L386] #res := ~__retres1~2; [L865] ~tmp___1~0 := #t~ret12; [L865] havoc #t~ret12; [L867-L871] COND FALSE !(0 != ~tmp___1~0) [L390] havoc ~__retres1~3; [L393] COND FALSE !(1 == ~t3_pc~0) [L403] ~__retres1~3 := 0; [L405] #res := ~__retres1~3; [L873] ~tmp___2~0 := #t~ret13; [L873] havoc #t~ret13; [L875-L879] COND FALSE !(0 != ~tmp___2~0) [L409] havoc ~__retres1~4; [L412] COND FALSE !(1 == ~t4_pc~0) [L422] ~__retres1~4 := 0; [L424] #res := ~__retres1~4; [L881] ~tmp___3~0 := #t~ret14; [L881] havoc #t~ret14; [L883-L887] COND FALSE !(0 != ~tmp___3~0) [L428] havoc ~__retres1~5; [L431] COND FALSE !(1 == ~t5_pc~0) [L441] ~__retres1~5 := 0; [L443] #res := ~__retres1~5; [L889] ~tmp___4~0 := #t~ret15; [L889] havoc #t~ret15; [L891-L895] COND FALSE !(0 != ~tmp___4~0) [L447] havoc ~__retres1~6; [L450] COND FALSE !(1 == ~t6_pc~0) [L460] ~__retres1~6 := 0; [L462] #res := ~__retres1~6; [L897] ~tmp___5~0 := #t~ret16; [L897] havoc #t~ret16; [L899-L903] COND FALSE !(0 != ~tmp___5~0) [L764] COND FALSE !(1 == ~M_E~0) [L769] COND FALSE !(1 == ~T1_E~0) [L774] COND FALSE !(1 == ~T2_E~0) [L779] COND FALSE !(1 == ~T3_E~0) [L784] COND FALSE !(1 == ~T4_E~0) [L789] COND FALSE !(1 == ~T5_E~0) [L794] COND FALSE !(1 == ~T6_E~0) [L799] COND FALSE !(1 == ~E_M~0) [L804] COND FALSE !(1 == ~E_1~0) [L809] COND FALSE !(1 == ~E_2~0) [L814] COND FALSE !(1 == ~E_3~0) [L819] COND FALSE !(1 == ~E_4~0) [L824] COND FALSE !(1 == ~E_5~0) [L829] COND FALSE !(1 == ~E_6~0) [L1055-L1092] COND FALSE !(false) [L1058] ~kernel_st~0 := 1; [L563] havoc ~tmp~0; ----- ----- class de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.CACSL2BoogieBacktranslator [L14] ~m_pc~0 := 0; [L15] ~t1_pc~0 := 0; [L16] ~t2_pc~0 := 0; [L17] ~t3_pc~0 := 0; [L18] ~t4_pc~0 := 0; [L19] ~t5_pc~0 := 0; [L20] ~t6_pc~0 := 0; [L21] ~m_st~0 := 0; [L22] ~t1_st~0 := 0; [L23] ~t2_st~0 := 0; [L24] ~t3_st~0 := 0; [L25] ~t4_st~0 := 0; [L26] ~t5_st~0 := 0; [L27] ~t6_st~0 := 0; [L28] ~m_i~0 := 0; [L29] ~t1_i~0 := 0; [L30] ~t2_i~0 := 0; [L31] ~t3_i~0 := 0; [L32] ~t4_i~0 := 0; [L33] ~t5_i~0 := 0; [L34] ~t6_i~0 := 0; [L35] ~M_E~0 := 2; [L36] ~T1_E~0 := 2; [L37] ~T2_E~0 := 2; [L38] ~T3_E~0 := 2; [L39] ~T4_E~0 := 2; [L40] ~T5_E~0 := 2; [L41] ~T6_E~0 := 2; [L42] ~E_M~0 := 2; [L43] ~E_1~0 := 2; [L44] ~E_2~0 := 2; [L45] ~E_3~0 := 2; [L46] ~E_4~0 := 2; [L47] ~E_5~0 := 2; [L48] ~E_6~0 := 2; [L57] ~token~0 := 0; [L59] ~local~0 := 0; [L1100] havoc ~__retres1~8; [L1010] ~m_i~0 := 1; [L1011] ~t1_i~0 := 1; [L1012] ~t2_i~0 := 1; [L1013] ~t3_i~0 := 1; [L1014] ~t4_i~0 := 1; [L1015] ~t5_i~0 := 1; [L1016] ~t6_i~0 := 1; [L1041] havoc ~kernel_st~0; [L1042] havoc ~tmp~3; [L1043] havoc ~tmp___0~1; [L1047] ~kernel_st~0 := 0; [L477] COND TRUE 1 == ~m_i~0 [L478] ~m_st~0 := 0; [L482] COND TRUE 1 == ~t1_i~0 [L483] ~t1_st~0 := 0; [L487] COND TRUE 1 == ~t2_i~0 [L488] ~t2_st~0 := 0; [L492] COND TRUE 1 == ~t3_i~0 [L493] ~t3_st~0 := 0; [L497] COND TRUE 1 == ~t4_i~0 [L498] ~t4_st~0 := 0; [L502] COND TRUE 1 == ~t5_i~0 [L503] ~t5_st~0 := 0; [L507] COND TRUE 1 == ~t6_i~0 [L508] ~t6_st~0 := 0; [L686] COND FALSE !(0 == ~M_E~0) [L691] COND FALSE !(0 == ~T1_E~0) [L696] COND FALSE !(0 == ~T2_E~0) [L701] COND FALSE !(0 == ~T3_E~0) [L706] COND FALSE !(0 == ~T4_E~0) [L711] COND FALSE !(0 == ~T5_E~0) [L716] COND FALSE !(0 == ~T6_E~0) [L721] COND FALSE !(0 == ~E_M~0) [L726] COND FALSE !(0 == ~E_1~0) [L731] COND FALSE !(0 == ~E_2~0) [L736] COND FALSE !(0 == ~E_3~0) [L741] COND FALSE !(0 == ~E_4~0) [L746] COND FALSE !(0 == ~E_5~0) [L751] COND FALSE !(0 == ~E_6~0) [L839] havoc ~tmp~1; [L840] havoc ~tmp___0~0; [L841] havoc ~tmp___1~0; [L842] havoc ~tmp___2~0; [L843] havoc ~tmp___3~0; [L844] havoc ~tmp___4~0; [L845] havoc ~tmp___5~0; [L333] havoc ~__retres1~0; [L336] COND FALSE !(1 == ~m_pc~0) [L346] ~__retres1~0 := 0; [L348] #res := ~__retres1~0; [L849] ~tmp~1 := #t~ret10; [L849] havoc #t~ret10; [L851-L855] COND FALSE !(0 != ~tmp~1) [L352] havoc ~__retres1~1; [L355] COND FALSE !(1 == ~t1_pc~0) [L365] ~__retres1~1 := 0; [L367] #res := ~__retres1~1; [L857] ~tmp___0~0 := #t~ret11; [L857] havoc #t~ret11; [L859-L863] COND FALSE !(0 != ~tmp___0~0) [L371] havoc ~__retres1~2; [L374] COND FALSE !(1 == ~t2_pc~0) [L384] ~__retres1~2 := 0; [L386] #res := ~__retres1~2; [L865] ~tmp___1~0 := #t~ret12; [L865] havoc #t~ret12; [L867-L871] COND FALSE !(0 != ~tmp___1~0) [L390] havoc ~__retres1~3; [L393] COND FALSE !(1 == ~t3_pc~0) [L403] ~__retres1~3 := 0; [L405] #res := ~__retres1~3; [L873] ~tmp___2~0 := #t~ret13; [L873] havoc #t~ret13; [L875-L879] COND FALSE !(0 != ~tmp___2~0) [L409] havoc ~__retres1~4; [L412] COND FALSE !(1 == ~t4_pc~0) [L422] ~__retres1~4 := 0; [L424] #res := ~__retres1~4; [L881] ~tmp___3~0 := #t~ret14; [L881] havoc #t~ret14; [L883-L887] COND FALSE !(0 != ~tmp___3~0) [L428] havoc ~__retres1~5; [L431] COND FALSE !(1 == ~t5_pc~0) [L441] ~__retres1~5 := 0; [L443] #res := ~__retres1~5; [L889] ~tmp___4~0 := #t~ret15; [L889] havoc #t~ret15; [L891-L895] COND FALSE !(0 != ~tmp___4~0) [L447] havoc ~__retres1~6; [L450] COND FALSE !(1 == ~t6_pc~0) [L460] ~__retres1~6 := 0; [L462] #res := ~__retres1~6; [L897] ~tmp___5~0 := #t~ret16; [L897] havoc #t~ret16; [L899-L903] COND FALSE !(0 != ~tmp___5~0) [L764] COND FALSE !(1 == ~M_E~0) [L769] COND FALSE !(1 == ~T1_E~0) [L774] COND FALSE !(1 == ~T2_E~0) [L779] COND FALSE !(1 == ~T3_E~0) [L784] COND FALSE !(1 == ~T4_E~0) [L789] COND FALSE !(1 == ~T5_E~0) [L794] COND FALSE !(1 == ~T6_E~0) [L799] COND FALSE !(1 == ~E_M~0) [L804] COND FALSE !(1 == ~E_1~0) [L809] COND FALSE !(1 == ~E_2~0) [L814] COND FALSE !(1 == ~E_3~0) [L819] COND FALSE !(1 == ~E_4~0) [L824] COND FALSE !(1 == ~E_5~0) [L829] COND FALSE !(1 == ~E_6~0) [L1055-L1092] COND FALSE !(false) [L1058] ~kernel_st~0 := 1; [L563] havoc ~tmp~0; [L14] int m_pc = 0; [L15] int t1_pc = 0; [L16] int t2_pc = 0; [L17] int t3_pc = 0; [L18] int t4_pc = 0; [L19] int t5_pc = 0; [L20] int t6_pc = 0; [L21] int m_st ; [L22] int t1_st ; [L23] int t2_st ; [L24] int t3_st ; [L25] int t4_st ; [L26] int t5_st ; [L27] int t6_st ; [L28] int m_i ; [L29] int t1_i ; [L30] int t2_i ; [L31] int t3_i ; [L32] int t4_i ; [L33] int t5_i ; [L34] int t6_i ; [L35] int M_E = 2; [L36] int T1_E = 2; [L37] int T2_E = 2; [L38] int T3_E = 2; [L39] int T4_E = 2; [L40] int T5_E = 2; [L41] int T6_E = 2; [L42] int E_M = 2; [L43] int E_1 = 2; [L44] int E_2 = 2; [L45] int E_3 = 2; [L46] int E_4 = 2; [L47] int E_5 = 2; [L48] int E_6 = 2; [L57] int token ; [L59] int local ; [L1100] int __retres1 ; [L1010] m_i = 1 [L1011] t1_i = 1 [L1012] t2_i = 1 [L1013] t3_i = 1 [L1014] t4_i = 1 [L1015] t5_i = 1 [L1016] t6_i = 1 [L1041] int kernel_st ; [L1042] int tmp ; [L1043] int tmp___0 ; [L1047] kernel_st = 0 [L477] COND TRUE m_i == 1 [L478] m_st = 0 [L482] COND TRUE t1_i == 1 [L483] t1_st = 0 [L487] COND TRUE t2_i == 1 [L488] t2_st = 0 [L492] COND TRUE t3_i == 1 [L493] t3_st = 0 [L497] COND TRUE t4_i == 1 [L498] t4_st = 0 [L502] COND TRUE t5_i == 1 [L503] t5_st = 0 [L507] COND TRUE t6_i == 1 [L508] t6_st = 0 [L686] COND FALSE !(M_E == 0) [L691] COND FALSE !(T1_E == 0) [L696] COND FALSE !(T2_E == 0) [L701] COND FALSE !(T3_E == 0) [L706] COND FALSE !(T4_E == 0) [L711] COND FALSE !(T5_E == 0) [L716] COND FALSE !(T6_E == 0) [L721] COND FALSE !(E_M == 0) [L726] COND FALSE !(E_1 == 0) [L731] COND FALSE !(E_2 == 0) [L736] COND FALSE !(E_3 == 0) [L741] COND FALSE !(E_4 == 0) [L746] COND FALSE !(E_5 == 0) [L751] COND FALSE !(E_6 == 0) [L839] int tmp ; [L840] int tmp___0 ; [L841] int tmp___1 ; [L842] int tmp___2 ; [L843] int tmp___3 ; [L844] int tmp___4 ; [L845] int tmp___5 ; [L333] int __retres1 ; [L336] COND FALSE !(m_pc == 1) [L346] __retres1 = 0 [L348] return (__retres1); [L849] tmp = is_master_triggered() [L851] COND FALSE !(\read(tmp)) [L352] int __retres1 ; [L355] COND FALSE !(t1_pc == 1) [L365] __retres1 = 0 [L367] return (__retres1); [L857] tmp___0 = is_transmit1_triggered() [L859] COND FALSE !(\read(tmp___0)) [L371] int __retres1 ; [L374] COND FALSE !(t2_pc == 1) [L384] __retres1 = 0 [L386] return (__retres1); [L865] tmp___1 = is_transmit2_triggered() [L867] COND FALSE !(\read(tmp___1)) [L390] int __retres1 ; [L393] COND FALSE !(t3_pc == 1) [L403] __retres1 = 0 [L405] return (__retres1); [L873] tmp___2 = is_transmit3_triggered() [L875] COND FALSE !(\read(tmp___2)) [L409] int __retres1 ; [L412] COND FALSE !(t4_pc == 1) [L422] __retres1 = 0 [L424] return (__retres1); [L881] tmp___3 = is_transmit4_triggered() [L883] COND FALSE !(\read(tmp___3)) [L428] int __retres1 ; [L431] COND FALSE !(t5_pc == 1) [L441] __retres1 = 0 [L443] return (__retres1); [L889] tmp___4 = is_transmit5_triggered() [L891] COND FALSE !(\read(tmp___4)) [L447] int __retres1 ; [L450] COND FALSE !(t6_pc == 1) [L460] __retres1 = 0 [L462] return (__retres1); [L897] tmp___5 = is_transmit6_triggered() [L899] COND FALSE !(\read(tmp___5)) [L764] COND FALSE !(M_E == 1) [L769] COND FALSE !(T1_E == 1) [L774] COND FALSE !(T2_E == 1) [L779] COND FALSE !(T3_E == 1) [L784] COND FALSE !(T4_E == 1) [L789] COND FALSE !(T5_E == 1) [L794] COND FALSE !(T6_E == 1) [L799] COND FALSE !(E_M == 1) [L804] COND FALSE !(E_1 == 1) [L809] COND FALSE !(E_2 == 1) [L814] COND FALSE !(E_3 == 1) [L819] COND FALSE !(E_4 == 1) [L824] COND FALSE !(E_5 == 1) [L829] COND FALSE !(E_6 == 1) [L1055] COND TRUE 1 [L1058] kernel_st = 1 [L563] int tmp ; ----- ----- class de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder.RCFGBacktranslator [?] assume !false; [?] havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~7;havoc exists_runnable_thread_~__retres1~7; [?] assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7 := 1; [?] exists_runnable_thread_#res := exists_runnable_thread_~__retres1~7; [?] eval_#t~ret2 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret2;havoc eval_#t~ret2; [?] assume 0 != eval_~tmp~0; [?] assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0;eval_~tmp_ndt_1~0 := eval_#t~nondet3;havoc eval_#t~nondet3; [?] assume !(0 != eval_~tmp_ndt_1~0); [?] assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0;eval_~tmp_ndt_2~0 := eval_#t~nondet4;havoc eval_#t~nondet4; [?] assume !(0 != eval_~tmp_ndt_2~0); [?] assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0;eval_~tmp_ndt_3~0 := eval_#t~nondet5;havoc eval_#t~nondet5; [?] assume !(0 != eval_~tmp_ndt_3~0); [?] assume 0 == ~t3_st~0;havoc eval_~tmp_ndt_4~0;eval_~tmp_ndt_4~0 := eval_#t~nondet6;havoc eval_#t~nondet6; [?] assume !(0 != eval_~tmp_ndt_4~0); [?] assume 0 == ~t4_st~0;havoc eval_~tmp_ndt_5~0;eval_~tmp_ndt_5~0 := eval_#t~nondet7;havoc eval_#t~nondet7; [?] assume !(0 != eval_~tmp_ndt_5~0); [?] assume 0 == ~t5_st~0;havoc eval_~tmp_ndt_6~0;eval_~tmp_ndt_6~0 := eval_#t~nondet8;havoc eval_#t~nondet8; [?] assume !(0 != eval_~tmp_ndt_6~0); [?] assume 0 == ~t6_st~0;havoc eval_~tmp_ndt_7~0;eval_~tmp_ndt_7~0 := eval_#t~nondet9;havoc eval_#t~nondet9; [?] assume !(0 != eval_~tmp_ndt_7~0); [L567-L675] assume !false; [L570] havoc exists_runnable_thread_#res; [L570] havoc exists_runnable_thread_~__retres1~7; [L517] havoc exists_runnable_thread_~__retres1~7; [L520-L555] assume 0 == ~m_st~0; [L521] exists_runnable_thread_~__retres1~7 := 1; [L558] exists_runnable_thread_#res := exists_runnable_thread_~__retres1~7; [L570] eval_#t~ret2 := exists_runnable_thread_#res; [L570] eval_~tmp~0 := eval_#t~ret2; [L570] havoc eval_#t~ret2; [L572-L576] assume 0 != eval_~tmp~0; [L577-L590] assume 0 == ~m_st~0; [L578] havoc eval_~tmp_ndt_1~0; [L579] eval_~tmp_ndt_1~0 := eval_#t~nondet3; [L579] havoc eval_#t~nondet3; [L580-L587] assume !(0 != eval_~tmp_ndt_1~0); [L591-L604] assume 0 == ~t1_st~0; [L592] havoc eval_~tmp_ndt_2~0; [L593] eval_~tmp_ndt_2~0 := eval_#t~nondet4; [L593] havoc eval_#t~nondet4; [L594-L601] assume !(0 != eval_~tmp_ndt_2~0); [L605-L618] assume 0 == ~t2_st~0; [L606] havoc eval_~tmp_ndt_3~0; [L607] eval_~tmp_ndt_3~0 := eval_#t~nondet5; [L607] havoc eval_#t~nondet5; [L608-L615] assume !(0 != eval_~tmp_ndt_3~0); [L619-L632] assume 0 == ~t3_st~0; [L620] havoc eval_~tmp_ndt_4~0; [L621] eval_~tmp_ndt_4~0 := eval_#t~nondet6; [L621] havoc eval_#t~nondet6; [L622-L629] assume !(0 != eval_~tmp_ndt_4~0); [L633-L646] assume 0 == ~t4_st~0; [L634] havoc eval_~tmp_ndt_5~0; [L635] eval_~tmp_ndt_5~0 := eval_#t~nondet7; [L635] havoc eval_#t~nondet7; [L636-L643] assume !(0 != eval_~tmp_ndt_5~0); [L647-L660] assume 0 == ~t5_st~0; [L648] havoc eval_~tmp_ndt_6~0; [L649] eval_~tmp_ndt_6~0 := eval_#t~nondet8; [L649] havoc eval_#t~nondet8; [L650-L657] assume !(0 != eval_~tmp_ndt_6~0); [L661-L674] assume 0 == ~t6_st~0; [L662] havoc eval_~tmp_ndt_7~0; [L663] eval_~tmp_ndt_7~0 := eval_#t~nondet9; [L663] havoc eval_#t~nondet9; [L664-L671] assume !(0 != eval_~tmp_ndt_7~0); ----- ----- class de.uni_freiburg.informatik.ultimate.boogie.preprocessor.BoogiePreprocessorBacktranslator [L567-L675] assume !false; [L570] havoc exists_runnable_thread_#res; [L570] havoc exists_runnable_thread_~__retres1~7; [L517] havoc exists_runnable_thread_~__retres1~7; [L520-L555] assume 0 == ~m_st~0; [L521] exists_runnable_thread_~__retres1~7 := 1; [L558] exists_runnable_thread_#res := exists_runnable_thread_~__retres1~7; [L570] eval_#t~ret2 := exists_runnable_thread_#res; [L570] eval_~tmp~0 := eval_#t~ret2; [L570] havoc eval_#t~ret2; [L572-L576] assume 0 != eval_~tmp~0; [L577-L590] assume 0 == ~m_st~0; [L578] havoc eval_~tmp_ndt_1~0; [L579] eval_~tmp_ndt_1~0 := eval_#t~nondet3; [L579] havoc eval_#t~nondet3; [L580-L587] assume !(0 != eval_~tmp_ndt_1~0); [L591-L604] assume 0 == ~t1_st~0; [L592] havoc eval_~tmp_ndt_2~0; [L593] eval_~tmp_ndt_2~0 := eval_#t~nondet4; [L593] havoc eval_#t~nondet4; [L594-L601] assume !(0 != eval_~tmp_ndt_2~0); [L605-L618] assume 0 == ~t2_st~0; [L606] havoc eval_~tmp_ndt_3~0; [L607] eval_~tmp_ndt_3~0 := eval_#t~nondet5; [L607] havoc eval_#t~nondet5; [L608-L615] assume !(0 != eval_~tmp_ndt_3~0); [L619-L632] assume 0 == ~t3_st~0; [L620] havoc eval_~tmp_ndt_4~0; [L621] eval_~tmp_ndt_4~0 := eval_#t~nondet6; [L621] havoc eval_#t~nondet6; [L622-L629] assume !(0 != eval_~tmp_ndt_4~0); [L633-L646] assume 0 == ~t4_st~0; [L634] havoc eval_~tmp_ndt_5~0; [L635] eval_~tmp_ndt_5~0 := eval_#t~nondet7; [L635] havoc eval_#t~nondet7; [L636-L643] assume !(0 != eval_~tmp_ndt_5~0); [L647-L660] assume 0 == ~t5_st~0; [L648] havoc eval_~tmp_ndt_6~0; [L649] eval_~tmp_ndt_6~0 := eval_#t~nondet8; [L649] havoc eval_#t~nondet8; [L650-L657] assume !(0 != eval_~tmp_ndt_6~0); [L661-L674] assume 0 == ~t6_st~0; [L662] havoc eval_~tmp_ndt_7~0; [L663] eval_~tmp_ndt_7~0 := eval_#t~nondet9; [L663] havoc eval_#t~nondet9; [L664-L671] assume !(0 != eval_~tmp_ndt_7~0); [L567-L675] COND FALSE !(false) [L570] havoc exists_runnable_thread_#res; [L570] havoc exists_runnable_thread_~__retres1~7; [L517] havoc exists_runnable_thread_~__retres1~7; [L520] COND TRUE 0 == ~m_st~0 [L521] exists_runnable_thread_~__retres1~7 := 1; [L558] exists_runnable_thread_#res := exists_runnable_thread_~__retres1~7; [L570] eval_#t~ret2 := exists_runnable_thread_#res; [L570] eval_~tmp~0 := eval_#t~ret2; [L570] havoc eval_#t~ret2; [L572-L576] COND TRUE 0 != eval_~tmp~0 [L577] COND TRUE 0 == ~m_st~0 [L578] havoc eval_~tmp_ndt_1~0; [L579] eval_~tmp_ndt_1~0 := eval_#t~nondet3; [L579] havoc eval_#t~nondet3; [L580-L587] COND FALSE !(0 != eval_~tmp_ndt_1~0) [L591] COND TRUE 0 == ~t1_st~0 [L592] havoc eval_~tmp_ndt_2~0; [L593] eval_~tmp_ndt_2~0 := eval_#t~nondet4; [L593] havoc eval_#t~nondet4; [L594-L601] COND FALSE !(0 != eval_~tmp_ndt_2~0) [L605] COND TRUE 0 == ~t2_st~0 [L606] havoc eval_~tmp_ndt_3~0; [L607] eval_~tmp_ndt_3~0 := eval_#t~nondet5; [L607] havoc eval_#t~nondet5; [L608-L615] COND FALSE !(0 != eval_~tmp_ndt_3~0) [L619] COND TRUE 0 == ~t3_st~0 [L620] havoc eval_~tmp_ndt_4~0; [L621] eval_~tmp_ndt_4~0 := eval_#t~nondet6; [L621] havoc eval_#t~nondet6; [L622-L629] COND FALSE !(0 != eval_~tmp_ndt_4~0) [L633] COND TRUE 0 == ~t4_st~0 [L634] havoc eval_~tmp_ndt_5~0; [L635] eval_~tmp_ndt_5~0 := eval_#t~nondet7; [L635] havoc eval_#t~nondet7; [L636-L643] COND FALSE !(0 != eval_~tmp_ndt_5~0) [L647] COND TRUE 0 == ~t5_st~0 [L648] havoc eval_~tmp_ndt_6~0; [L649] eval_~tmp_ndt_6~0 := eval_#t~nondet8; [L649] havoc eval_#t~nondet8; [L650-L657] COND FALSE !(0 != eval_~tmp_ndt_6~0) [L661] COND TRUE 0 == ~t6_st~0 [L662] havoc eval_~tmp_ndt_7~0; [L663] eval_~tmp_ndt_7~0 := eval_#t~nondet9; [L663] havoc eval_#t~nondet9; [L664-L671] COND FALSE !(0 != eval_~tmp_ndt_7~0) ----- ----- class de.uni_freiburg.informatik.ultimate.boogie.procedureinliner.backtranslation.InlinerBacktranslator [L567-L675] COND FALSE !(false) [L570] havoc exists_runnable_thread_#res; [L570] havoc exists_runnable_thread_~__retres1~7; [L517] havoc exists_runnable_thread_~__retres1~7; [L520] COND TRUE 0 == ~m_st~0 [L521] exists_runnable_thread_~__retres1~7 := 1; [L558] exists_runnable_thread_#res := exists_runnable_thread_~__retres1~7; [L570] eval_#t~ret2 := exists_runnable_thread_#res; [L570] eval_~tmp~0 := eval_#t~ret2; [L570] havoc eval_#t~ret2; [L572-L576] COND TRUE 0 != eval_~tmp~0 [L577] COND TRUE 0 == ~m_st~0 [L578] havoc eval_~tmp_ndt_1~0; [L579] eval_~tmp_ndt_1~0 := eval_#t~nondet3; [L579] havoc eval_#t~nondet3; [L580-L587] COND FALSE !(0 != eval_~tmp_ndt_1~0) [L591] COND TRUE 0 == ~t1_st~0 [L592] havoc eval_~tmp_ndt_2~0; [L593] eval_~tmp_ndt_2~0 := eval_#t~nondet4; [L593] havoc eval_#t~nondet4; [L594-L601] COND FALSE !(0 != eval_~tmp_ndt_2~0) [L605] COND TRUE 0 == ~t2_st~0 [L606] havoc eval_~tmp_ndt_3~0; [L607] eval_~tmp_ndt_3~0 := eval_#t~nondet5; [L607] havoc eval_#t~nondet5; [L608-L615] COND FALSE !(0 != eval_~tmp_ndt_3~0) [L619] COND TRUE 0 == ~t3_st~0 [L620] havoc eval_~tmp_ndt_4~0; [L621] eval_~tmp_ndt_4~0 := eval_#t~nondet6; [L621] havoc eval_#t~nondet6; [L622-L629] COND FALSE !(0 != eval_~tmp_ndt_4~0) [L633] COND TRUE 0 == ~t4_st~0 [L634] havoc eval_~tmp_ndt_5~0; [L635] eval_~tmp_ndt_5~0 := eval_#t~nondet7; [L635] havoc eval_#t~nondet7; [L636-L643] COND FALSE !(0 != eval_~tmp_ndt_5~0) [L647] COND TRUE 0 == ~t5_st~0 [L648] havoc eval_~tmp_ndt_6~0; [L649] eval_~tmp_ndt_6~0 := eval_#t~nondet8; [L649] havoc eval_#t~nondet8; [L650-L657] COND FALSE !(0 != eval_~tmp_ndt_6~0) [L661] COND TRUE 0 == ~t6_st~0 [L662] havoc eval_~tmp_ndt_7~0; [L663] eval_~tmp_ndt_7~0 := eval_#t~nondet9; [L663] havoc eval_#t~nondet9; [L664-L671] COND FALSE !(0 != eval_~tmp_ndt_7~0) [L567-L675] COND FALSE !(false) [L517] havoc ~__retres1~7; [L520] COND TRUE 0 == ~m_st~0 [L521] ~__retres1~7 := 1; [L558] #res := ~__retres1~7; [L570] ~tmp~0 := #t~ret2; [L570] havoc #t~ret2; [L572-L576] COND TRUE 0 != ~tmp~0 [L577] COND TRUE 0 == ~m_st~0 [L578] havoc ~tmp_ndt_1~0; [L579] ~tmp_ndt_1~0 := #t~nondet3; [L579] havoc #t~nondet3; [L580-L587] COND FALSE !(0 != ~tmp_ndt_1~0) [L591] COND TRUE 0 == ~t1_st~0 [L592] havoc ~tmp_ndt_2~0; [L593] ~tmp_ndt_2~0 := #t~nondet4; [L593] havoc #t~nondet4; [L594-L601] COND FALSE !(0 != ~tmp_ndt_2~0) [L605] COND TRUE 0 == ~t2_st~0 [L606] havoc ~tmp_ndt_3~0; [L607] ~tmp_ndt_3~0 := #t~nondet5; [L607] havoc #t~nondet5; [L608-L615] COND FALSE !(0 != ~tmp_ndt_3~0) [L619] COND TRUE 0 == ~t3_st~0 [L620] havoc ~tmp_ndt_4~0; [L621] ~tmp_ndt_4~0 := #t~nondet6; [L621] havoc #t~nondet6; [L622-L629] COND FALSE !(0 != ~tmp_ndt_4~0) [L633] COND TRUE 0 == ~t4_st~0 [L634] havoc ~tmp_ndt_5~0; [L635] ~tmp_ndt_5~0 := #t~nondet7; [L635] havoc #t~nondet7; [L636-L643] COND FALSE !(0 != ~tmp_ndt_5~0) [L647] COND TRUE 0 == ~t5_st~0 [L648] havoc ~tmp_ndt_6~0; [L649] ~tmp_ndt_6~0 := #t~nondet8; [L649] havoc #t~nondet8; [L650-L657] COND FALSE !(0 != ~tmp_ndt_6~0) [L661] COND TRUE 0 == ~t6_st~0 [L662] havoc ~tmp_ndt_7~0; [L663] ~tmp_ndt_7~0 := #t~nondet9; [L663] havoc #t~nondet9; [L664-L671] COND FALSE !(0 != ~tmp_ndt_7~0) ----- ----- class de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.CACSL2BoogieBacktranslator [L567-L675] COND FALSE !(false) [L517] havoc ~__retres1~7; [L520] COND TRUE 0 == ~m_st~0 [L521] ~__retres1~7 := 1; [L558] #res := ~__retres1~7; [L570] ~tmp~0 := #t~ret2; [L570] havoc #t~ret2; [L572-L576] COND TRUE 0 != ~tmp~0 [L577] COND TRUE 0 == ~m_st~0 [L578] havoc ~tmp_ndt_1~0; [L579] ~tmp_ndt_1~0 := #t~nondet3; [L579] havoc #t~nondet3; [L580-L587] COND FALSE !(0 != ~tmp_ndt_1~0) [L591] COND TRUE 0 == ~t1_st~0 [L592] havoc ~tmp_ndt_2~0; [L593] ~tmp_ndt_2~0 := #t~nondet4; [L593] havoc #t~nondet4; [L594-L601] COND FALSE !(0 != ~tmp_ndt_2~0) [L605] COND TRUE 0 == ~t2_st~0 [L606] havoc ~tmp_ndt_3~0; [L607] ~tmp_ndt_3~0 := #t~nondet5; [L607] havoc #t~nondet5; [L608-L615] COND FALSE !(0 != ~tmp_ndt_3~0) [L619] COND TRUE 0 == ~t3_st~0 [L620] havoc ~tmp_ndt_4~0; [L621] ~tmp_ndt_4~0 := #t~nondet6; [L621] havoc #t~nondet6; [L622-L629] COND FALSE !(0 != ~tmp_ndt_4~0) [L633] COND TRUE 0 == ~t4_st~0 [L634] havoc ~tmp_ndt_5~0; [L635] ~tmp_ndt_5~0 := #t~nondet7; [L635] havoc #t~nondet7; [L636-L643] COND FALSE !(0 != ~tmp_ndt_5~0) [L647] COND TRUE 0 == ~t5_st~0 [L648] havoc ~tmp_ndt_6~0; [L649] ~tmp_ndt_6~0 := #t~nondet8; [L649] havoc #t~nondet8; [L650-L657] COND FALSE !(0 != ~tmp_ndt_6~0) [L661] COND TRUE 0 == ~t6_st~0 [L662] havoc ~tmp_ndt_7~0; [L663] ~tmp_ndt_7~0 := #t~nondet9; [L663] havoc #t~nondet9; [L664-L671] COND FALSE !(0 != ~tmp_ndt_7~0) [L567] COND TRUE 1 [L517] int __retres1 ; [L520] COND TRUE m_st == 0 [L521] __retres1 = 1 [L558] return (__retres1); [L570] tmp = exists_runnable_thread() [L572] COND TRUE \read(tmp) [L577] COND TRUE m_st == 0 [L578] int tmp_ndt_1; [L579] tmp_ndt_1 = __VERIFIER_nondet_int() [L580] COND FALSE !(\read(tmp_ndt_1)) [L591] COND TRUE t1_st == 0 [L592] int tmp_ndt_2; [L593] tmp_ndt_2 = __VERIFIER_nondet_int() [L594] COND FALSE !(\read(tmp_ndt_2)) [L605] COND TRUE t2_st == 0 [L606] int tmp_ndt_3; [L607] tmp_ndt_3 = __VERIFIER_nondet_int() [L608] COND FALSE !(\read(tmp_ndt_3)) [L619] COND TRUE t3_st == 0 [L620] int tmp_ndt_4; [L621] tmp_ndt_4 = __VERIFIER_nondet_int() [L622] COND FALSE !(\read(tmp_ndt_4)) [L633] COND TRUE t4_st == 0 [L634] int tmp_ndt_5; [L635] tmp_ndt_5 = __VERIFIER_nondet_int() [L636] COND FALSE !(\read(tmp_ndt_5)) [L647] COND TRUE t5_st == 0 [L648] int tmp_ndt_6; [L649] tmp_ndt_6 = __VERIFIER_nondet_int() [L650] COND FALSE !(\read(tmp_ndt_6)) [L661] COND TRUE t6_st == 0 [L662] int tmp_ndt_7; [L663] tmp_ndt_7 = __VERIFIER_nondet_int() [L664] COND FALSE !(\read(tmp_ndt_7)) ----- Found a nonterminating execution for the following lasso shaped sequence of statements. Stem: [L14] int m_pc = 0; [L15] int t1_pc = 0; [L16] int t2_pc = 0; [L17] int t3_pc = 0; [L18] int t4_pc = 0; [L19] int t5_pc = 0; [L20] int t6_pc = 0; [L21] int m_st ; [L22] int t1_st ; [L23] int t2_st ; [L24] int t3_st ; [L25] int t4_st ; [L26] int t5_st ; [L27] int t6_st ; [L28] int m_i ; [L29] int t1_i ; [L30] int t2_i ; [L31] int t3_i ; [L32] int t4_i ; [L33] int t5_i ; [L34] int t6_i ; [L35] int M_E = 2; [L36] int T1_E = 2; [L37] int T2_E = 2; [L38] int T3_E = 2; [L39] int T4_E = 2; [L40] int T5_E = 2; [L41] int T6_E = 2; [L42] int E_M = 2; [L43] int E_1 = 2; [L44] int E_2 = 2; [L45] int E_3 = 2; [L46] int E_4 = 2; [L47] int E_5 = 2; [L48] int E_6 = 2; [L57] int token ; [L59] int local ; [L1100] int __retres1 ; [L1010] m_i = 1 [L1011] t1_i = 1 [L1012] t2_i = 1 [L1013] t3_i = 1 [L1014] t4_i = 1 [L1015] t5_i = 1 [L1016] t6_i = 1 [L1041] int kernel_st ; [L1042] int tmp ; [L1043] int tmp___0 ; [L1047] kernel_st = 0 [L477] COND TRUE m_i == 1 [L478] m_st = 0 [L482] COND TRUE t1_i == 1 [L483] t1_st = 0 [L487] COND TRUE t2_i == 1 [L488] t2_st = 0 [L492] COND TRUE t3_i == 1 [L493] t3_st = 0 [L497] COND TRUE t4_i == 1 [L498] t4_st = 0 [L502] COND TRUE t5_i == 1 [L503] t5_st = 0 [L507] COND TRUE t6_i == 1 [L508] t6_st = 0 [L686] COND FALSE !(M_E == 0) [L691] COND FALSE !(T1_E == 0) [L696] COND FALSE !(T2_E == 0) [L701] COND FALSE !(T3_E == 0) [L706] COND FALSE !(T4_E == 0) [L711] COND FALSE !(T5_E == 0) [L716] COND FALSE !(T6_E == 0) [L721] COND FALSE !(E_M == 0) [L726] COND FALSE !(E_1 == 0) [L731] COND FALSE !(E_2 == 0) [L736] COND FALSE !(E_3 == 0) [L741] COND FALSE !(E_4 == 0) [L746] COND FALSE !(E_5 == 0) [L751] COND FALSE !(E_6 == 0) [L839] int tmp ; [L840] int tmp___0 ; [L841] int tmp___1 ; [L842] int tmp___2 ; [L843] int tmp___3 ; [L844] int tmp___4 ; [L845] int tmp___5 ; [L333] int __retres1 ; [L336] COND FALSE !(m_pc == 1) [L346] __retres1 = 0 [L348] return (__retres1); [L849] tmp = is_master_triggered() [L851] COND FALSE !(\read(tmp)) [L352] int __retres1 ; [L355] COND FALSE !(t1_pc == 1) [L365] __retres1 = 0 [L367] return (__retres1); [L857] tmp___0 = is_transmit1_triggered() [L859] COND FALSE !(\read(tmp___0)) [L371] int __retres1 ; [L374] COND FALSE !(t2_pc == 1) [L384] __retres1 = 0 [L386] return (__retres1); [L865] tmp___1 = is_transmit2_triggered() [L867] COND FALSE !(\read(tmp___1)) [L390] int __retres1 ; [L393] COND FALSE !(t3_pc == 1) [L403] __retres1 = 0 [L405] return (__retres1); [L873] tmp___2 = is_transmit3_triggered() [L875] COND FALSE !(\read(tmp___2)) [L409] int __retres1 ; [L412] COND FALSE !(t4_pc == 1) [L422] __retres1 = 0 [L424] return (__retres1); [L881] tmp___3 = is_transmit4_triggered() [L883] COND FALSE !(\read(tmp___3)) [L428] int __retres1 ; [L431] COND FALSE !(t5_pc == 1) [L441] __retres1 = 0 [L443] return (__retres1); [L889] tmp___4 = is_transmit5_triggered() [L891] COND FALSE !(\read(tmp___4)) [L447] int __retres1 ; [L450] COND FALSE !(t6_pc == 1) [L460] __retres1 = 0 [L462] return (__retres1); [L897] tmp___5 = is_transmit6_triggered() [L899] COND FALSE !(\read(tmp___5)) [L764] COND FALSE !(M_E == 1) [L769] COND FALSE !(T1_E == 1) [L774] COND FALSE !(T2_E == 1) [L779] COND FALSE !(T3_E == 1) [L784] COND FALSE !(T4_E == 1) [L789] COND FALSE !(T5_E == 1) [L794] COND FALSE !(T6_E == 1) [L799] COND FALSE !(E_M == 1) [L804] COND FALSE !(E_1 == 1) [L809] COND FALSE !(E_2 == 1) [L814] COND FALSE !(E_3 == 1) [L819] COND FALSE !(E_4 == 1) [L824] COND FALSE !(E_5 == 1) [L829] COND FALSE !(E_6 == 1) [L1055] COND TRUE 1 [L1058] kernel_st = 1 [L563] int tmp ; Loop: [L567] COND TRUE 1 [L517] int __retres1 ; [L520] COND TRUE m_st == 0 [L521] __retres1 = 1 [L558] return (__retres1); [L570] tmp = exists_runnable_thread() [L572] COND TRUE \read(tmp) [L577] COND TRUE m_st == 0 [L578] int tmp_ndt_1; [L579] tmp_ndt_1 = __VERIFIER_nondet_int() [L580] COND FALSE !(\read(tmp_ndt_1)) [L591] COND TRUE t1_st == 0 [L592] int tmp_ndt_2; [L593] tmp_ndt_2 = __VERIFIER_nondet_int() [L594] COND FALSE !(\read(tmp_ndt_2)) [L605] COND TRUE t2_st == 0 [L606] int tmp_ndt_3; [L607] tmp_ndt_3 = __VERIFIER_nondet_int() [L608] COND FALSE !(\read(tmp_ndt_3)) [L619] COND TRUE t3_st == 0 [L620] int tmp_ndt_4; [L621] tmp_ndt_4 = __VERIFIER_nondet_int() [L622] COND FALSE !(\read(tmp_ndt_4)) [L633] COND TRUE t4_st == 0 [L634] int tmp_ndt_5; [L635] tmp_ndt_5 = __VERIFIER_nondet_int() [L636] COND FALSE !(\read(tmp_ndt_5)) [L647] COND TRUE t5_st == 0 [L648] int tmp_ndt_6; [L649] tmp_ndt_6 = __VERIFIER_nondet_int() [L650] COND FALSE !(\read(tmp_ndt_6)) [L661] COND TRUE t6_st == 0 [L662] int tmp_ndt_7; [L663] tmp_ndt_7 = __VERIFIER_nondet_int() [L664] COND FALSE !(\read(tmp_ndt_7)) End of lasso representation. RESULT: Ultimate proved your program to be incorrect! Received shutdown request...