./Ultimate.py --spec ../../sv-benchmarks/c/properties/termination.prp --file ../../sv-benchmarks/c/systemc/token_ring.06_true-unreach-call_false-termination.cil.c --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for termination Using default analysis Version aa418289 Calling Ultimate with: java -Dosgi.configuration.area=/tmp/vcloud-vcloud-master/worker/working_dir_14a495c8-4465-4fa3-a7af-a201bd4dc887/bin-2019/uautomizer/data/config -Xmx12G -Xms1G -jar /tmp/vcloud-vcloud-master/worker/working_dir_14a495c8-4465-4fa3-a7af-a201bd4dc887/bin-2019/uautomizer/plugins/org.eclipse.equinox.launcher_1.3.100.v20150511-1540.jar -data @noDefault -ultimatedata /tmp/vcloud-vcloud-master/worker/working_dir_14a495c8-4465-4fa3-a7af-a201bd4dc887/bin-2019/uautomizer/data -tc /tmp/vcloud-vcloud-master/worker/working_dir_14a495c8-4465-4fa3-a7af-a201bd4dc887/bin-2019/uautomizer/config/AutomizerTermination.xml -i ../../sv-benchmarks/c/systemc/token_ring.06_true-unreach-call_false-termination.cil.c -s /tmp/vcloud-vcloud-master/worker/working_dir_14a495c8-4465-4fa3-a7af-a201bd4dc887/bin-2019/uautomizer/config/svcomp-Termination-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud-vcloud-master/worker/working_dir_14a495c8-4465-4fa3-a7af-a201bd4dc887/bin-2019/uautomizer --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash 1a4f705a2aeda6c2b85d5987770b408257af07ab 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Execution finished normally Writing output log to file Ultimate.log Writing human readable error path to file UltimateCounterExample.errorpath Result: FALSE(TERM) --- Real Ultimate output --- This is Ultimate 0.1.23-aa41828 [2018-11-23 14:59:42,301 INFO L170 SettingsManager]: Resetting all preferences to default values... [2018-11-23 14:59:42,302 INFO L174 SettingsManager]: Resetting UltimateCore preferences to default values [2018-11-23 14:59:42,308 INFO L177 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2018-11-23 14:59:42,308 INFO L174 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2018-11-23 14:59:42,309 INFO L174 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2018-11-23 14:59:42,310 INFO L174 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2018-11-23 14:59:42,311 INFO L174 SettingsManager]: Resetting LassoRanker preferences to default values [2018-11-23 14:59:42,312 INFO L174 SettingsManager]: Resetting Reaching Definitions preferences to default values [2018-11-23 14:59:42,313 INFO L174 SettingsManager]: Resetting SyntaxChecker preferences to default values [2018-11-23 14:59:42,314 INFO L177 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2018-11-23 14:59:42,314 INFO L174 SettingsManager]: Resetting LTL2Aut preferences to default values [2018-11-23 14:59:42,314 INFO L174 SettingsManager]: Resetting PEA to Boogie preferences to default values [2018-11-23 14:59:42,315 INFO L174 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2018-11-23 14:59:42,315 INFO L174 SettingsManager]: Resetting ChcToBoogie preferences to default values [2018-11-23 14:59:42,316 INFO L174 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2018-11-23 14:59:42,316 INFO L174 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2018-11-23 14:59:42,318 INFO L174 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2018-11-23 14:59:42,319 INFO L174 SettingsManager]: Resetting CodeCheck preferences to default values [2018-11-23 14:59:42,320 INFO L174 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2018-11-23 14:59:42,321 INFO L174 SettingsManager]: Resetting RCFGBuilder preferences to default values [2018-11-23 14:59:42,321 INFO L174 SettingsManager]: Resetting TraceAbstraction preferences to default values [2018-11-23 14:59:42,323 INFO L177 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2018-11-23 14:59:42,323 INFO L177 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2018-11-23 14:59:42,323 INFO L174 SettingsManager]: Resetting TreeAutomizer preferences to default values [2018-11-23 14:59:42,324 INFO L174 SettingsManager]: Resetting IcfgTransformer preferences to default values [2018-11-23 14:59:42,324 INFO L174 SettingsManager]: Resetting Boogie Printer preferences to default values [2018-11-23 14:59:42,325 INFO L174 SettingsManager]: Resetting ReqPrinter preferences to default values [2018-11-23 14:59:42,325 INFO L174 SettingsManager]: Resetting Witness Printer preferences to default values [2018-11-23 14:59:42,326 INFO L177 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2018-11-23 14:59:42,326 INFO L174 SettingsManager]: Resetting CDTParser preferences to default values [2018-11-23 14:59:42,326 INFO L177 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2018-11-23 14:59:42,326 INFO L177 SettingsManager]: ReqParser provides no preferences, ignoring... [2018-11-23 14:59:42,326 INFO L174 SettingsManager]: Resetting SmtParser preferences to default values [2018-11-23 14:59:42,327 INFO L174 SettingsManager]: Resetting Witness Parser preferences to default values [2018-11-23 14:59:42,327 INFO L181 SettingsManager]: Finished resetting all preferences to default values... [2018-11-23 14:59:42,327 INFO L98 SettingsManager]: Beginning loading settings from /tmp/vcloud-vcloud-master/worker/working_dir_14a495c8-4465-4fa3-a7af-a201bd4dc887/bin-2019/uautomizer/config/svcomp-Termination-32bit-Automizer_Default.epf [2018-11-23 14:59:42,336 INFO L110 SettingsManager]: Loading preferences was successful [2018-11-23 14:59:42,336 INFO L112 SettingsManager]: Preferences different from defaults after loading the file: [2018-11-23 14:59:42,337 INFO L131 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2018-11-23 14:59:42,337 INFO L133 SettingsManager]: * Create parallel compositions if possible=false [2018-11-23 14:59:42,337 INFO L133 SettingsManager]: * Use SBE=true [2018-11-23 14:59:42,337 INFO L131 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: [2018-11-23 14:59:42,338 INFO L133 SettingsManager]: * NCSB implementation=INTSET_LAZY3 [2018-11-23 14:59:42,338 INFO L133 SettingsManager]: * Use old map elimination=false [2018-11-23 14:59:42,338 INFO L133 SettingsManager]: * Use external solver (rank synthesis)=false [2018-11-23 14:59:42,338 INFO L133 SettingsManager]: * Use only trivial implications for array writes=true [2018-11-23 14:59:42,338 INFO L133 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES [2018-11-23 14:59:42,338 INFO L131 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2018-11-23 14:59:42,338 INFO L133 SettingsManager]: * sizeof long=4 [2018-11-23 14:59:42,338 INFO L133 SettingsManager]: * Check unreachability of error function in SV-COMP mode=false [2018-11-23 14:59:42,339 INFO L133 SettingsManager]: * Overapproximate operations on floating types=true [2018-11-23 14:59:42,339 INFO L133 SettingsManager]: * sizeof POINTER=4 [2018-11-23 14:59:42,339 INFO L133 SettingsManager]: * Check division by zero=IGNORE [2018-11-23 14:59:42,339 INFO L133 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME [2018-11-23 14:59:42,339 INFO L133 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME [2018-11-23 14:59:42,339 INFO L133 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME [2018-11-23 14:59:42,339 INFO L133 SettingsManager]: * sizeof long double=12 [2018-11-23 14:59:42,340 INFO L133 SettingsManager]: * Check if freed pointer was valid=false [2018-11-23 14:59:42,340 INFO L133 SettingsManager]: * Assume nondeterminstic values are in range=false [2018-11-23 14:59:42,340 INFO L133 SettingsManager]: * Use constant arrays=true [2018-11-23 14:59:42,340 INFO L133 SettingsManager]: * Pointer base address is valid at dereference=ASSUME [2018-11-23 14:59:42,340 INFO L131 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2018-11-23 14:59:42,340 INFO L133 SettingsManager]: * Size of a code block=SequenceOfStatements [2018-11-23 14:59:42,340 INFO L133 SettingsManager]: * To the following directory=/home/matthias/ultimate/dump [2018-11-23 14:59:42,340 INFO L131 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2018-11-23 14:59:42,341 INFO L133 SettingsManager]: * Trace refinement strategy=CAMEL [2018-11-23 14:59:42,341 INFO L133 SettingsManager]: * Dump automata to the following directory=/home/matthias/ultimate/dump/auto [2018-11-23 14:59:42,341 INFO L131 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2018-11-23 14:59:42,342 INFO L133 SettingsManager]: * TransformationType=MODULO_NEIGHBOR Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud-vcloud-master/worker/working_dir_14a495c8-4465-4fa3-a7af-a201bd4dc887/bin-2019/uautomizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> 1a4f705a2aeda6c2b85d5987770b408257af07ab [2018-11-23 14:59:42,364 INFO L81 nceAwareModelManager]: Repository-Root is: /tmp [2018-11-23 14:59:42,373 INFO L258 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2018-11-23 14:59:42,376 INFO L214 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2018-11-23 14:59:42,377 INFO L271 PluginConnector]: Initializing CDTParser... [2018-11-23 14:59:42,378 INFO L276 PluginConnector]: CDTParser initialized [2018-11-23 14:59:42,378 INFO L418 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud-vcloud-master/worker/working_dir_14a495c8-4465-4fa3-a7af-a201bd4dc887/bin-2019/uautomizer/../../sv-benchmarks/c/systemc/token_ring.06_true-unreach-call_false-termination.cil.c [2018-11-23 14:59:42,421 INFO L221 CDTParser]: Created temporary CDT project at /tmp/vcloud-vcloud-master/worker/working_dir_14a495c8-4465-4fa3-a7af-a201bd4dc887/bin-2019/uautomizer/data/558632671/65b25ac0b9e74072860365db294324dc/FLAG32f3e4b70 [2018-11-23 14:59:42,834 INFO L307 CDTParser]: Found 1 translation units. [2018-11-23 14:59:42,834 INFO L161 CDTParser]: Scanning /tmp/vcloud-vcloud-master/worker/working_dir_14a495c8-4465-4fa3-a7af-a201bd4dc887/sv-benchmarks/c/systemc/token_ring.06_true-unreach-call_false-termination.cil.c [2018-11-23 14:59:42,840 INFO L355 CDTParser]: About to delete temporary CDT project at /tmp/vcloud-vcloud-master/worker/working_dir_14a495c8-4465-4fa3-a7af-a201bd4dc887/bin-2019/uautomizer/data/558632671/65b25ac0b9e74072860365db294324dc/FLAG32f3e4b70 [2018-11-23 14:59:42,850 INFO L363 CDTParser]: Successfully deleted /tmp/vcloud-vcloud-master/worker/working_dir_14a495c8-4465-4fa3-a7af-a201bd4dc887/bin-2019/uautomizer/data/558632671/65b25ac0b9e74072860365db294324dc [2018-11-23 14:59:42,853 INFO L296 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2018-11-23 14:59:42,854 INFO L131 ToolchainWalker]: Walking toolchain with 6 elements. [2018-11-23 14:59:42,855 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2018-11-23 14:59:42,855 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2018-11-23 14:59:42,857 INFO L276 PluginConnector]: CACSL2BoogieTranslator initialized [2018-11-23 14:59:42,858 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 23.11 02:59:42" (1/1) ... [2018-11-23 14:59:42,860 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@2ac28ad0 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 02:59:42, skipping insertion in model container [2018-11-23 14:59:42,860 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 23.11 02:59:42" (1/1) ... [2018-11-23 14:59:42,868 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2018-11-23 14:59:42,899 INFO L176 MainTranslator]: Built tables and reachable declarations [2018-11-23 14:59:43,059 INFO L201 PostProcessor]: Analyzing one entry point: main [2018-11-23 14:59:43,063 INFO L191 MainTranslator]: Completed pre-run [2018-11-23 14:59:43,100 INFO L201 PostProcessor]: Analyzing one entry point: main [2018-11-23 14:59:43,114 INFO L195 MainTranslator]: Completed translation [2018-11-23 14:59:43,114 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 02:59:43 WrapperNode [2018-11-23 14:59:43,114 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2018-11-23 14:59:43,114 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2018-11-23 14:59:43,115 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2018-11-23 14:59:43,115 INFO L276 PluginConnector]: Boogie Procedure Inliner initialized [2018-11-23 14:59:43,119 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 02:59:43" (1/1) ... [2018-11-23 14:59:43,169 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 02:59:43" (1/1) ... [2018-11-23 14:59:43,212 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2018-11-23 14:59:43,212 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2018-11-23 14:59:43,213 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2018-11-23 14:59:43,213 INFO L276 PluginConnector]: Boogie Preprocessor initialized [2018-11-23 14:59:43,221 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 02:59:43" (1/1) ... [2018-11-23 14:59:43,222 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 02:59:43" (1/1) ... [2018-11-23 14:59:43,227 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 02:59:43" (1/1) ... [2018-11-23 14:59:43,227 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 02:59:43" (1/1) ... [2018-11-23 14:59:43,241 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 02:59:43" (1/1) ... [2018-11-23 14:59:43,258 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 02:59:43" (1/1) ... [2018-11-23 14:59:43,261 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 02:59:43" (1/1) ... [2018-11-23 14:59:43,266 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2018-11-23 14:59:43,267 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2018-11-23 14:59:43,267 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2018-11-23 14:59:43,267 INFO L276 PluginConnector]: RCFGBuilder initialized [2018-11-23 14:59:43,268 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 02:59:43" (1/1) ... No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_14a495c8-4465-4fa3-a7af-a201bd4dc887/bin-2019/uautomizer/z3 Starting monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2018-11-23 14:59:43,321 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2018-11-23 14:59:43,321 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2018-11-23 14:59:44,257 INFO L275 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2018-11-23 14:59:44,258 INFO L280 CfgBuilder]: Removed 235 assue(true) statements. [2018-11-23 14:59:44,258 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 23.11 02:59:44 BoogieIcfgContainer [2018-11-23 14:59:44,258 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2018-11-23 14:59:44,259 INFO L113 PluginConnector]: ------------------------BuchiAutomizer---------------------------- [2018-11-23 14:59:44,259 INFO L271 PluginConnector]: Initializing BuchiAutomizer... [2018-11-23 14:59:44,261 INFO L276 PluginConnector]: BuchiAutomizer initialized [2018-11-23 14:59:44,261 INFO L102 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2018-11-23 14:59:44,262 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 23.11 02:59:42" (1/3) ... [2018-11-23 14:59:44,262 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@53d87879 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 23.11 02:59:44, skipping insertion in model container [2018-11-23 14:59:44,262 INFO L102 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2018-11-23 14:59:44,263 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 02:59:43" (2/3) ... [2018-11-23 14:59:44,263 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@53d87879 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 23.11 02:59:44, skipping insertion in model container [2018-11-23 14:59:44,263 INFO L102 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2018-11-23 14:59:44,263 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 23.11 02:59:44" (3/3) ... [2018-11-23 14:59:44,265 INFO L375 chiAutomizerObserver]: Analyzing ICFG token_ring.06_true-unreach-call_false-termination.cil.c [2018-11-23 14:59:44,302 INFO L133 ementStrategyFactory]: Using default assertion order modulation [2018-11-23 14:59:44,303 INFO L374 BuchiCegarLoop]: Interprodecural is true [2018-11-23 14:59:44,303 INFO L375 BuchiCegarLoop]: Hoare is false [2018-11-23 14:59:44,303 INFO L376 BuchiCegarLoop]: Compute interpolants for ForwardPredicates [2018-11-23 14:59:44,303 INFO L377 BuchiCegarLoop]: Backedges is STRAIGHT_LINE [2018-11-23 14:59:44,303 INFO L378 BuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2018-11-23 14:59:44,304 INFO L379 BuchiCegarLoop]: Difference is false [2018-11-23 14:59:44,304 INFO L380 BuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2018-11-23 14:59:44,304 INFO L383 BuchiCegarLoop]: ======== Iteration 0==of CEGAR loop == BuchiCegarLoop======== [2018-11-23 14:59:44,325 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 665 states. [2018-11-23 14:59:44,363 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 574 [2018-11-23 14:59:44,363 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-23 14:59:44,363 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-23 14:59:44,372 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 14:59:44,372 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 14:59:44,372 INFO L442 BuchiCegarLoop]: ======== Iteration 1============ [2018-11-23 14:59:44,372 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 665 states. [2018-11-23 14:59:44,382 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 574 [2018-11-23 14:59:44,382 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-23 14:59:44,382 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-23 14:59:44,384 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 14:59:44,384 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 14:59:44,390 INFO L794 eck$LassoCheckResult]: Stem: 470#ULTIMATE.startENTRYtrue ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0; 359#L-1true havoc main_#res;havoc main_~__retres1~8;havoc main_~__retres1~8;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 24#L1006true havoc start_simulation_#t~ret17, start_simulation_#t~ret18, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 577#L458true assume !(1 == ~m_i~0);~m_st~0 := 2; 287#L465-1true assume 1 == ~t1_i~0;~t1_st~0 := 0; 652#L470-1true assume !(1 == ~t2_i~0);~t2_st~0 := 2; 193#L475-1true assume !(1 == ~t3_i~0);~t3_st~0 := 2; 579#L480-1true assume !(1 == ~t4_i~0);~t4_st~0 := 2; 234#L485-1true assume !(1 == ~t5_i~0);~t5_st~0 := 2; 73#L490-1true assume !(1 == ~t6_i~0);~t6_st~0 := 2; 484#L495-1true assume !(0 == ~M_E~0); 298#L674-1true assume !(0 == ~T1_E~0); 661#L679-1true assume 0 == ~T2_E~0;~T2_E~0 := 1; 204#L684-1true assume !(0 == ~T3_E~0); 585#L689-1true assume !(0 == ~T4_E~0); 451#L694-1true assume !(0 == ~T5_E~0); 96#L699-1true assume !(0 == ~T6_E~0); 515#L704-1true assume !(0 == ~E_M~0); 3#L709-1true assume !(0 == ~E_1~0); 404#L714-1true assume !(0 == ~E_2~0); 55#L719-1true assume 0 == ~E_3~0;~E_3~0 := 1; 604#L724-1true assume !(0 == ~E_4~0); 293#L729-1true assume !(0 == ~E_5~0); 657#L734-1true assume !(0 == ~E_6~0); 199#L739-1true havoc activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 122#L324true assume !(1 == ~m_pc~0); 131#L324-2true is_master_triggered_~__retres1~0 := 0; 157#L335true is_master_triggered_#res := is_master_triggered_~__retres1~0; 77#L336true activate_threads_#t~ret9 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 307#L839true assume !(0 != activate_threads_~tmp~1); 309#L839-2true havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 167#L343true assume 1 == ~t1_pc~0; 265#L344true assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 165#L354true is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 264#L355true activate_threads_#t~ret10 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 523#L847true assume !(0 != activate_threads_~tmp___0~0); 508#L847-2true havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 402#L362true assume 1 == ~t2_pc~0; 490#L363true assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 400#L373true is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 489#L374true activate_threads_#t~ret11 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 526#L855true assume !(0 != activate_threads_~tmp___1~0); 529#L855-2true havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 555#L381true assume !(1 == ~t3_pc~0); 561#L381-2true is_transmit3_triggered_~__retres1~3 := 0; 553#L392true is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 629#L393true activate_threads_#t~ret12 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 30#L863true assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 15#L863-2true havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 52#L400true assume 1 == ~t4_pc~0; 150#L401true assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 51#L411true is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 149#L412true activate_threads_#t~ret13 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 212#L871true assume !(0 != activate_threads_~tmp___3~0); 214#L871-2true havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 236#L419true assume !(1 == ~t5_pc~0); 239#L419-2true is_transmit5_triggered_~__retres1~5 := 0; 235#L430true is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 195#L431true activate_threads_#t~ret14 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 430#L879true assume !(0 != activate_threads_~tmp___4~0); 417#L879-2true havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 599#L438true assume 1 == ~t6_pc~0; 394#L439true assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6 := 1; 598#L449true is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 392#L450true activate_threads_#t~ret15 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 588#L887true assume !(0 != activate_threads_~tmp___5~0); 590#L887-2true assume !(1 == ~M_E~0); 61#L752-1true assume !(1 == ~T1_E~0); 602#L757-1true assume !(1 == ~T2_E~0); 290#L762-1true assume !(1 == ~T3_E~0); 655#L767-1true assume !(1 == ~T4_E~0); 198#L772-1true assume !(1 == ~T5_E~0); 581#L777-1true assume 1 == ~T6_E~0;~T6_E~0 := 2; 449#L782-1true assume !(1 == ~E_M~0); 92#L787-1true assume !(1 == ~E_1~0); 509#L792-1true assume !(1 == ~E_2~0); 16#L797-1true assume !(1 == ~E_3~0); 420#L802-1true assume !(1 == ~E_4~0); 60#L807-1true assume !(1 == ~E_5~0); 609#L812-1true assume !(1 == ~E_6~0); 611#L1043-1true [2018-11-23 14:59:44,392 INFO L796 eck$LassoCheckResult]: Loop: 611#L1043-1true assume !false; 425#L1044true start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret1, eval_#t~nondet2, eval_~tmp_ndt_1~0, eval_#t~nondet3, eval_~tmp_ndt_2~0, eval_#t~nondet4, eval_~tmp_ndt_3~0, eval_#t~nondet5, eval_~tmp_ndt_4~0, eval_#t~nondet6, eval_~tmp_ndt_5~0, eval_#t~nondet7, eval_~tmp_ndt_6~0, eval_#t~nondet8, eval_~tmp_ndt_7~0, eval_~tmp~0;havoc eval_~tmp~0; 494#L649true assume false; 56#L664true start_simulation_~kernel_st~0 := 2; 551#L458-1true start_simulation_~kernel_st~0 := 3; 301#L674-2true assume 0 == ~M_E~0;~M_E~0 := 1; 276#L674-4true assume 0 == ~T1_E~0;~T1_E~0 := 1; 645#L679-3true assume 0 == ~T2_E~0;~T2_E~0 := 1; 182#L684-3true assume 0 == ~T3_E~0;~T3_E~0 := 1; 566#L689-3true assume !(0 == ~T4_E~0); 243#L694-3true assume 0 == ~T5_E~0;~T5_E~0 := 1; 81#L699-3true assume 0 == ~T6_E~0;~T6_E~0 := 1; 498#L704-3true assume 0 == ~E_M~0;~E_M~0 := 1; 9#L709-3true assume 0 == ~E_1~0;~E_1~0 := 1; 407#L714-3true assume 0 == ~E_2~0;~E_2~0 := 1; 58#L719-3true assume 0 == ~E_3~0;~E_3~0 := 1; 607#L724-3true assume 0 == ~E_4~0;~E_4~0 := 1; 300#L729-3true assume !(0 == ~E_5~0); 664#L734-3true assume 0 == ~E_6~0;~E_6~0 := 1; 206#L739-3true havoc activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 84#L324-24true assume 1 == ~m_pc~0; 595#L325-8true assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 114#L335-8true is_master_triggered_#res := is_master_triggered_~__retres1~0; 593#L336-8true activate_threads_#t~ret9 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 261#L839-24true assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 244#L839-26true havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 304#L343-24true assume 1 == ~t1_pc~0; 259#L344-8true assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 340#L354-8true is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 257#L355-8true activate_threads_#t~ret10 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 463#L847-24true assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 465#L847-26true havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 499#L362-24true assume !(1 == ~t2_pc~0); 503#L362-26true is_transmit2_triggered_~__retres1~2 := 0; 351#L373-8true is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 457#L374-8true activate_threads_#t~ret11 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 628#L855-24true assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 610#L855-26true havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 666#L381-24true assume 1 == ~t3_pc~0; 624#L382-8true assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 546#L392-8true is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 623#L393-8true activate_threads_#t~ret12 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 115#L863-24true assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 121#L863-26true havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 6#L400-24true assume !(1 == ~t4_pc~0); 12#L400-26true is_transmit4_triggered_~__retres1~4 := 0; 34#L411-8true is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 106#L412-8true activate_threads_#t~ret13 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 343#L871-24true assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 315#L871-26true havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 205#L419-24true assume !(1 == ~t5_pc~0); 184#L419-26true is_transmit5_triggered_~__retres1~5 := 0; 228#L430-8true is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 332#L431-8true activate_threads_#t~ret14 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 354#L879-24true assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 357#L879-26true havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 406#L438-24true assume 1 == ~t6_pc~0; 386#L439-8true assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6 := 1; 431#L449-8true is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 384#L450-8true activate_threads_#t~ret15 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 549#L887-24true assume 0 != activate_threads_~tmp___5~0;~t6_st~0 := 0; 532#L887-26true assume !(1 == ~M_E~0); 57#L752-3true assume 1 == ~T1_E~0;~T1_E~0 := 2; 605#L757-3true assume 1 == ~T2_E~0;~T2_E~0 := 2; 296#L762-3true assume 1 == ~T3_E~0;~T3_E~0 := 2; 659#L767-3true assume 1 == ~T4_E~0;~T4_E~0 := 2; 203#L772-3true assume 1 == ~T5_E~0;~T5_E~0 := 2; 584#L777-3true assume 1 == ~T6_E~0;~T6_E~0 := 2; 450#L782-3true assume 1 == ~E_M~0;~E_M~0 := 2; 95#L787-3true assume !(1 == ~E_1~0); 513#L792-3true assume 1 == ~E_2~0;~E_2~0 := 2; 21#L797-3true assume 1 == ~E_3~0;~E_3~0 := 2; 424#L802-3true assume 1 == ~E_4~0;~E_4~0 := 2; 54#L807-3true assume 1 == ~E_5~0;~E_5~0 := 2; 603#L812-3true assume 1 == ~E_6~0;~E_6~0 := 2; 291#L817-3true havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~7;havoc exists_runnable_thread_~__retres1~7; 192#L508-1true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7 := 1; 87#L545-1true exists_runnable_thread_#res := exists_runnable_thread_~__retres1~7; 573#L546-1true start_simulation_#t~ret17 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret17;havoc start_simulation_#t~ret17; 119#L1062true assume !(0 == start_simulation_~tmp~3); 120#L1062-1true havoc stop_simulation_#res;havoc stop_simulation_#t~ret16, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~7;havoc exists_runnable_thread_~__retres1~7; 194#L508-2true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7 := 1; 90#L545-2true exists_runnable_thread_#res := exists_runnable_thread_~__retres1~7; 576#L546-2true stop_simulation_#t~ret16 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret16;havoc stop_simulation_#t~ret16; 23#L1017true assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 466#L1024true stop_simulation_#res := stop_simulation_~__retres2~0; 221#L1025true start_simulation_#t~ret18 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret18;havoc start_simulation_#t~ret18; 531#L1075true assume !(0 != start_simulation_~tmp___0~1); 611#L1043-1true [2018-11-23 14:59:44,397 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 14:59:44,397 INFO L82 PathProgramCache]: Analyzing trace with hash 480768360, now seen corresponding path program 1 times [2018-11-23 14:59:44,398 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 14:59:44,399 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 14:59:44,428 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 14:59:44,428 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 14:59:44,428 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 14:59:44,457 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 14:59:44,513 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 14:59:44,515 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 14:59:44,515 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-23 14:59:44,519 INFO L799 eck$LassoCheckResult]: stem already infeasible [2018-11-23 14:59:44,520 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 14:59:44,520 INFO L82 PathProgramCache]: Analyzing trace with hash 1017026800, now seen corresponding path program 1 times [2018-11-23 14:59:44,520 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 14:59:44,520 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 14:59:44,521 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 14:59:44,521 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 14:59:44,521 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 14:59:44,526 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 14:59:44,542 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 14:59:44,542 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 14:59:44,542 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2018-11-23 14:59:44,544 INFO L811 eck$LassoCheckResult]: loop already infeasible [2018-11-23 14:59:44,557 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-23 14:59:44,557 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-23 14:59:44,559 INFO L87 Difference]: Start difference. First operand 665 states. Second operand 3 states. [2018-11-23 14:59:44,598 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 14:59:44,598 INFO L93 Difference]: Finished difference Result 665 states and 1003 transitions. [2018-11-23 14:59:44,599 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-23 14:59:44,600 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 665 states and 1003 transitions. [2018-11-23 14:59:44,605 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 573 [2018-11-23 14:59:44,613 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 665 states to 660 states and 998 transitions. [2018-11-23 14:59:44,614 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 660 [2018-11-23 14:59:44,615 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 660 [2018-11-23 14:59:44,616 INFO L73 IsDeterministic]: Start isDeterministic. Operand 660 states and 998 transitions. [2018-11-23 14:59:44,619 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-23 14:59:44,619 INFO L705 BuchiCegarLoop]: Abstraction has 660 states and 998 transitions. [2018-11-23 14:59:44,637 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 660 states and 998 transitions. [2018-11-23 14:59:44,659 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 660 to 660. [2018-11-23 14:59:44,659 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 660 states. [2018-11-23 14:59:44,661 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 660 states to 660 states and 998 transitions. [2018-11-23 14:59:44,662 INFO L728 BuchiCegarLoop]: Abstraction has 660 states and 998 transitions. [2018-11-23 14:59:44,663 INFO L608 BuchiCegarLoop]: Abstraction has 660 states and 998 transitions. [2018-11-23 14:59:44,663 INFO L442 BuchiCegarLoop]: ======== Iteration 2============ [2018-11-23 14:59:44,663 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 660 states and 998 transitions. [2018-11-23 14:59:44,666 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 573 [2018-11-23 14:59:44,667 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-23 14:59:44,667 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-23 14:59:44,668 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 14:59:44,669 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 14:59:44,669 INFO L794 eck$LassoCheckResult]: Stem: 1898#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0; 1793#L-1 havoc main_#res;havoc main_~__retres1~8;havoc main_~__retres1~8;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 1383#L1006 havoc start_simulation_#t~ret17, start_simulation_#t~ret18, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 1384#L458 assume 1 == ~m_i~0;~m_st~0 := 0; 1733#L465-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1734#L470-1 assume !(1 == ~t2_i~0);~t2_st~0 := 2; 1618#L475-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 1619#L480-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 1663#L485-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 1477#L490-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 1478#L495-1 assume !(0 == ~M_E~0); 1745#L674-1 assume !(0 == ~T1_E~0); 1746#L679-1 assume 0 == ~T2_E~0;~T2_E~0 := 1; 1636#L684-1 assume !(0 == ~T3_E~0); 1637#L689-1 assume !(0 == ~T4_E~0); 1878#L694-1 assume !(0 == ~T5_E~0); 1513#L699-1 assume !(0 == ~T6_E~0); 1514#L704-1 assume !(0 == ~E_M~0); 1339#L709-1 assume !(0 == ~E_1~0); 1340#L714-1 assume !(0 == ~E_2~0); 1431#L719-1 assume 0 == ~E_3~0;~E_3~0 := 1; 1432#L724-1 assume !(0 == ~E_4~0); 1739#L729-1 assume !(0 == ~E_5~0); 1740#L734-1 assume !(0 == ~E_6~0); 1629#L739-1 havoc activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 1536#L324 assume !(1 == ~m_pc~0); 1486#L324-2 is_master_triggered_~__retres1~0 := 0; 1485#L335 is_master_triggered_#res := is_master_triggered_~__retres1~0; 1482#L336 activate_threads_#t~ret9 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 1483#L839 assume !(0 != activate_threads_~tmp~1); 1752#L839-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 1573#L343 assume 1 == ~t1_pc~0; 1574#L344 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 1571#L354 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 1572#L355 activate_threads_#t~ret10 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 1708#L847 assume !(0 != activate_threads_~tmp___0~0); 1921#L847-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 1859#L362 assume 1 == ~t2_pc~0; 1860#L363 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 1805#L373 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 1858#L374 activate_threads_#t~ret11 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 1916#L855 assume !(0 != activate_threads_~tmp___1~0); 1927#L855-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 1932#L381 assume !(1 == ~t3_pc~0); 1967#L381-2 is_transmit3_triggered_~__retres1~3 := 0; 1965#L392 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 1966#L393 activate_threads_#t~ret12 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 1397#L863 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 1366#L863-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 1367#L400 assume 1 == ~t4_pc~0; 1427#L401 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 1411#L411 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 1426#L412 activate_threads_#t~ret13 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 1549#L871 assume !(0 != activate_threads_~tmp___3~0); 1643#L871-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 1647#L419 assume !(1 == ~t5_pc~0); 1556#L419-2 is_transmit5_triggered_~__retres1~5 := 0; 1557#L430 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 1620#L431 activate_threads_#t~ret14 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 1621#L879 assume !(0 != activate_threads_~tmp___4~0); 1870#L879-2 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 1871#L438 assume 1 == ~t6_pc~0; 1844#L439 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6 := 1; 1845#L449 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 1842#L450 activate_threads_#t~ret15 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 1843#L887 assume !(0 != activate_threads_~tmp___5~0); 1980#L887-2 assume !(1 == ~M_E~0); 1444#L752-1 assume !(1 == ~T1_E~0); 1445#L757-1 assume !(1 == ~T2_E~0); 1736#L762-1 assume !(1 == ~T3_E~0); 1737#L767-1 assume !(1 == ~T4_E~0); 1626#L772-1 assume !(1 == ~T5_E~0); 1627#L777-1 assume 1 == ~T6_E~0;~T6_E~0 := 2; 1876#L782-1 assume !(1 == ~E_M~0); 1508#L787-1 assume !(1 == ~E_1~0); 1509#L792-1 assume !(1 == ~E_2~0); 1369#L797-1 assume !(1 == ~E_3~0); 1370#L802-1 assume !(1 == ~E_4~0); 1442#L807-1 assume !(1 == ~E_5~0); 1443#L812-1 assume !(1 == ~E_6~0); 1936#L1043-1 [2018-11-23 14:59:44,669 INFO L796 eck$LassoCheckResult]: Loop: 1936#L1043-1 assume !false; 1874#L1044 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret1, eval_#t~nondet2, eval_~tmp_ndt_1~0, eval_#t~nondet3, eval_~tmp_ndt_2~0, eval_#t~nondet4, eval_~tmp_ndt_3~0, eval_#t~nondet5, eval_~tmp_ndt_4~0, eval_#t~nondet6, eval_~tmp_ndt_5~0, eval_#t~nondet7, eval_~tmp_ndt_6~0, eval_#t~nondet8, eval_~tmp_ndt_7~0, eval_~tmp~0;havoc eval_~tmp~0; 1729#L649 assume !false; 1495#L556 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~7;havoc exists_runnable_thread_~__retres1~7; 1496#L508 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7 := 1; 1421#L545 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~7; 1500#L546 eval_#t~ret1 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret1;havoc eval_#t~ret1; 1867#L560 assume !(0 != eval_~tmp~0); 1433#L664 start_simulation_~kernel_st~0 := 2; 1434#L458-1 start_simulation_~kernel_st~0 := 3; 1750#L674-2 assume 0 == ~M_E~0;~M_E~0 := 1; 1722#L674-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 1723#L679-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 1607#L684-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 1608#L689-3 assume !(0 == ~T4_E~0); 1664#L694-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 1491#L699-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 1492#L704-3 assume 0 == ~E_M~0;~E_M~0 := 1; 1354#L709-3 assume 0 == ~E_1~0;~E_1~0 := 1; 1355#L714-3 assume 0 == ~E_2~0;~E_2~0 := 1; 1437#L719-3 assume 0 == ~E_3~0;~E_3~0 := 1; 1438#L724-3 assume 0 == ~E_4~0;~E_4~0 := 1; 1748#L729-3 assume !(0 == ~E_5~0); 1749#L734-3 assume 0 == ~E_6~0;~E_6~0 := 1; 1638#L739-3 havoc activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 1497#L324-24 assume !(1 == ~m_pc~0); 1498#L324-26 is_master_triggered_~__retres1~0 := 0; 1504#L335-8 is_master_triggered_#res := is_master_triggered_~__retres1~0; 1530#L336-8 activate_threads_#t~ret9 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 1705#L839-24 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 1665#L839-26 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 1666#L343-24 assume 1 == ~t1_pc~0; 1697#L344-8 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 1698#L354-8 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 1694#L355-8 activate_threads_#t~ret10 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 1695#L847-24 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 1893#L847-26 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 1894#L362-24 assume 1 == ~t2_pc~0; 1886#L363-8 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 1777#L373-8 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 1778#L374-8 activate_threads_#t~ret11 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 1885#L855-24 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 1981#L855-26 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 1982#L381-24 assume 1 == ~t3_pc~0; 1989#L382-8 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 1958#L392-8 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 1959#L393-8 activate_threads_#t~ret12 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 1528#L863-24 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 1529#L863-26 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 1345#L400-24 assume !(1 == ~t4_pc~0); 1346#L400-26 is_transmit4_triggered_~__retres1~4 := 0; 1359#L411-8 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 1400#L412-8 activate_threads_#t~ret13 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 1523#L871-24 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 1753#L871-26 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 1634#L419-24 assume 1 == ~t5_pc~0; 1635#L420-8 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 1606#L430-8 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 1657#L431-8 activate_threads_#t~ret14 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 1760#L879-24 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 1781#L879-26 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 1788#L438-24 assume 1 == ~t6_pc~0; 1834#L439-8 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6 := 1; 1835#L449-8 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 1832#L450-8 activate_threads_#t~ret15 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 1833#L887-24 assume 0 != activate_threads_~tmp___5~0;~t6_st~0 := 0; 1937#L887-26 assume !(1 == ~M_E~0); 1435#L752-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 1436#L757-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 1742#L762-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 1743#L767-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 1632#L772-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 1633#L777-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 1877#L782-3 assume 1 == ~E_M~0;~E_M~0 := 2; 1511#L787-3 assume !(1 == ~E_1~0); 1512#L792-3 assume 1 == ~E_2~0;~E_2~0 := 2; 1376#L797-3 assume 1 == ~E_3~0;~E_3~0 := 2; 1377#L802-3 assume 1 == ~E_4~0;~E_4~0 := 2; 1429#L807-3 assume 1 == ~E_5~0;~E_5~0 := 2; 1430#L812-3 assume 1 == ~E_6~0;~E_6~0 := 2; 1738#L817-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~7;havoc exists_runnable_thread_~__retres1~7; 1617#L508-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7 := 1; 1423#L545-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~7; 1501#L546-1 start_simulation_#t~ret17 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret17;havoc start_simulation_#t~ret17; 1532#L1062 assume !(0 == start_simulation_~tmp~3); 1533#L1062-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret16, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~7;havoc exists_runnable_thread_~__retres1~7; 1535#L508-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7 := 1; 1425#L545-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~7; 1507#L546-2 stop_simulation_#t~ret16 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret16;havoc stop_simulation_#t~ret16; 1381#L1017 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 1382#L1024 stop_simulation_#res := stop_simulation_~__retres2~0; 1653#L1025 start_simulation_#t~ret18 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret18;havoc start_simulation_#t~ret18; 1654#L1075 assume !(0 != start_simulation_~tmp___0~1); 1936#L1043-1 [2018-11-23 14:59:44,670 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 14:59:44,670 INFO L82 PathProgramCache]: Analyzing trace with hash 453702758, now seen corresponding path program 1 times [2018-11-23 14:59:44,670 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 14:59:44,670 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 14:59:44,671 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 14:59:44,671 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 14:59:44,671 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 14:59:44,681 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 14:59:44,707 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 14:59:44,707 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 14:59:44,708 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-23 14:59:44,709 INFO L799 eck$LassoCheckResult]: stem already infeasible [2018-11-23 14:59:44,709 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 14:59:44,709 INFO L82 PathProgramCache]: Analyzing trace with hash 551788720, now seen corresponding path program 1 times [2018-11-23 14:59:44,709 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 14:59:44,709 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 14:59:44,712 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 14:59:44,712 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 14:59:44,712 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 14:59:44,731 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 14:59:44,775 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 14:59:44,775 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 14:59:44,775 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-23 14:59:44,776 INFO L811 eck$LassoCheckResult]: loop already infeasible [2018-11-23 14:59:44,776 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-23 14:59:44,776 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-23 14:59:44,776 INFO L87 Difference]: Start difference. First operand 660 states and 998 transitions. cyclomatic complexity: 339 Second operand 3 states. [2018-11-23 14:59:44,789 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 14:59:44,789 INFO L93 Difference]: Finished difference Result 660 states and 997 transitions. [2018-11-23 14:59:44,790 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-23 14:59:44,791 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 660 states and 997 transitions. [2018-11-23 14:59:44,795 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 573 [2018-11-23 14:59:44,799 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 660 states to 660 states and 997 transitions. [2018-11-23 14:59:44,799 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 660 [2018-11-23 14:59:44,800 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 660 [2018-11-23 14:59:44,800 INFO L73 IsDeterministic]: Start isDeterministic. Operand 660 states and 997 transitions. [2018-11-23 14:59:44,801 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-23 14:59:44,801 INFO L705 BuchiCegarLoop]: Abstraction has 660 states and 997 transitions. [2018-11-23 14:59:44,802 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 660 states and 997 transitions. [2018-11-23 14:59:44,813 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 660 to 660. [2018-11-23 14:59:44,813 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 660 states. [2018-11-23 14:59:44,815 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 660 states to 660 states and 997 transitions. [2018-11-23 14:59:44,815 INFO L728 BuchiCegarLoop]: Abstraction has 660 states and 997 transitions. [2018-11-23 14:59:44,815 INFO L608 BuchiCegarLoop]: Abstraction has 660 states and 997 transitions. [2018-11-23 14:59:44,816 INFO L442 BuchiCegarLoop]: ======== Iteration 3============ [2018-11-23 14:59:44,816 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 660 states and 997 transitions. [2018-11-23 14:59:44,819 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 573 [2018-11-23 14:59:44,819 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-23 14:59:44,820 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-23 14:59:44,821 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 14:59:44,821 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 14:59:44,822 INFO L794 eck$LassoCheckResult]: Stem: 3226#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0; 3122#L-1 havoc main_#res;havoc main_~__retres1~8;havoc main_~__retres1~8;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 2710#L1006 havoc start_simulation_#t~ret17, start_simulation_#t~ret18, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 2711#L458 assume 1 == ~m_i~0;~m_st~0 := 0; 3060#L465-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 3061#L470-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 2945#L475-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 2946#L480-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 2990#L485-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 2804#L490-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 2805#L495-1 assume !(0 == ~M_E~0); 3073#L674-1 assume !(0 == ~T1_E~0); 3074#L679-1 assume 0 == ~T2_E~0;~T2_E~0 := 1; 2963#L684-1 assume !(0 == ~T3_E~0); 2964#L689-1 assume !(0 == ~T4_E~0); 3205#L694-1 assume !(0 == ~T5_E~0); 2840#L699-1 assume !(0 == ~T6_E~0); 2841#L704-1 assume !(0 == ~E_M~0); 2666#L709-1 assume !(0 == ~E_1~0); 2667#L714-1 assume !(0 == ~E_2~0); 2758#L719-1 assume 0 == ~E_3~0;~E_3~0 := 1; 2759#L724-1 assume !(0 == ~E_4~0); 3066#L729-1 assume !(0 == ~E_5~0); 3067#L734-1 assume !(0 == ~E_6~0); 2956#L739-1 havoc activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 2863#L324 assume !(1 == ~m_pc~0); 2813#L324-2 is_master_triggered_~__retres1~0 := 0; 2812#L335 is_master_triggered_#res := is_master_triggered_~__retres1~0; 2809#L336 activate_threads_#t~ret9 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 2810#L839 assume !(0 != activate_threads_~tmp~1); 3079#L839-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 2900#L343 assume 1 == ~t1_pc~0; 2901#L344 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 2898#L354 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 2899#L355 activate_threads_#t~ret10 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 3035#L847 assume !(0 != activate_threads_~tmp___0~0); 3248#L847-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 3186#L362 assume 1 == ~t2_pc~0; 3187#L363 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 3132#L373 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 3182#L374 activate_threads_#t~ret11 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 3243#L855 assume !(0 != activate_threads_~tmp___1~0); 3254#L855-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 3259#L381 assume !(1 == ~t3_pc~0); 3294#L381-2 is_transmit3_triggered_~__retres1~3 := 0; 3291#L392 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 3292#L393 activate_threads_#t~ret12 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 2723#L863 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 2693#L863-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 2694#L400 assume 1 == ~t4_pc~0; 2754#L401 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 2738#L411 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 2753#L412 activate_threads_#t~ret13 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 2876#L871 assume !(0 != activate_threads_~tmp___3~0); 2970#L871-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 2974#L419 assume !(1 == ~t5_pc~0); 2883#L419-2 is_transmit5_triggered_~__retres1~5 := 0; 2884#L430 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 2947#L431 activate_threads_#t~ret14 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 2948#L879 assume !(0 != activate_threads_~tmp___4~0); 3197#L879-2 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 3198#L438 assume 1 == ~t6_pc~0; 3171#L439 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6 := 1; 3172#L449 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 3169#L450 activate_threads_#t~ret15 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 3170#L887 assume !(0 != activate_threads_~tmp___5~0); 3307#L887-2 assume !(1 == ~M_E~0); 2771#L752-1 assume !(1 == ~T1_E~0); 2772#L757-1 assume !(1 == ~T2_E~0); 3063#L762-1 assume !(1 == ~T3_E~0); 3064#L767-1 assume !(1 == ~T4_E~0); 2953#L772-1 assume !(1 == ~T5_E~0); 2954#L777-1 assume 1 == ~T6_E~0;~T6_E~0 := 2; 3203#L782-1 assume !(1 == ~E_M~0); 2835#L787-1 assume !(1 == ~E_1~0); 2836#L792-1 assume !(1 == ~E_2~0); 2695#L797-1 assume !(1 == ~E_3~0); 2696#L802-1 assume !(1 == ~E_4~0); 2769#L807-1 assume !(1 == ~E_5~0); 2770#L812-1 assume !(1 == ~E_6~0); 3263#L1043-1 [2018-11-23 14:59:44,822 INFO L796 eck$LassoCheckResult]: Loop: 3263#L1043-1 assume !false; 3201#L1044 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret1, eval_#t~nondet2, eval_~tmp_ndt_1~0, eval_#t~nondet3, eval_~tmp_ndt_2~0, eval_#t~nondet4, eval_~tmp_ndt_3~0, eval_#t~nondet5, eval_~tmp_ndt_4~0, eval_#t~nondet6, eval_~tmp_ndt_5~0, eval_#t~nondet7, eval_~tmp_ndt_6~0, eval_#t~nondet8, eval_~tmp_ndt_7~0, eval_~tmp~0;havoc eval_~tmp~0; 3054#L649 assume !false; 2822#L556 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~7;havoc exists_runnable_thread_~__retres1~7; 2823#L508 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7 := 1; 2748#L545 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~7; 2827#L546 eval_#t~ret1 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret1;havoc eval_#t~ret1; 3194#L560 assume !(0 != eval_~tmp~0); 2760#L664 start_simulation_~kernel_st~0 := 2; 2761#L458-1 start_simulation_~kernel_st~0 := 3; 3077#L674-2 assume 0 == ~M_E~0;~M_E~0 := 1; 3049#L674-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 3050#L679-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 2932#L684-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 2933#L689-3 assume !(0 == ~T4_E~0); 2991#L694-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 2818#L699-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 2819#L704-3 assume 0 == ~E_M~0;~E_M~0 := 1; 2681#L709-3 assume 0 == ~E_1~0;~E_1~0 := 1; 2682#L714-3 assume 0 == ~E_2~0;~E_2~0 := 1; 2764#L719-3 assume 0 == ~E_3~0;~E_3~0 := 1; 2765#L724-3 assume 0 == ~E_4~0;~E_4~0 := 1; 3075#L729-3 assume !(0 == ~E_5~0); 3076#L734-3 assume 0 == ~E_6~0;~E_6~0 := 1; 2965#L739-3 havoc activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 2824#L324-24 assume !(1 == ~m_pc~0); 2825#L324-26 is_master_triggered_~__retres1~0 := 0; 2831#L335-8 is_master_triggered_#res := is_master_triggered_~__retres1~0; 2855#L336-8 activate_threads_#t~ret9 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 3029#L839-24 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 2992#L839-26 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 2993#L343-24 assume 1 == ~t1_pc~0; 3024#L344-8 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 3025#L354-8 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 3021#L355-8 activate_threads_#t~ret10 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 3022#L847-24 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 3220#L847-26 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 3221#L362-24 assume 1 == ~t2_pc~0; 3213#L363-8 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 3105#L373-8 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 3106#L374-8 activate_threads_#t~ret11 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 3212#L855-24 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 3308#L855-26 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 3309#L381-24 assume 1 == ~t3_pc~0; 3316#L382-8 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 3285#L392-8 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 3286#L393-8 activate_threads_#t~ret12 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 2856#L863-24 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 2857#L863-26 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 2672#L400-24 assume !(1 == ~t4_pc~0); 2673#L400-26 is_transmit4_triggered_~__retres1~4 := 0; 2686#L411-8 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 2727#L412-8 activate_threads_#t~ret13 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 2850#L871-24 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 3080#L871-26 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 2961#L419-24 assume 1 == ~t5_pc~0; 2962#L420-8 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 2936#L430-8 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 2984#L431-8 activate_threads_#t~ret14 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 3087#L879-24 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 3109#L879-26 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 3115#L438-24 assume 1 == ~t6_pc~0; 3163#L439-8 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6 := 1; 3164#L449-8 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 3159#L450-8 activate_threads_#t~ret15 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 3160#L887-24 assume 0 != activate_threads_~tmp___5~0;~t6_st~0 := 0; 3264#L887-26 assume !(1 == ~M_E~0); 2762#L752-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 2763#L757-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 3069#L762-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 3070#L767-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 2959#L772-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 2960#L777-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 3204#L782-3 assume 1 == ~E_M~0;~E_M~0 := 2; 2838#L787-3 assume !(1 == ~E_1~0); 2839#L792-3 assume 1 == ~E_2~0;~E_2~0 := 2; 2703#L797-3 assume 1 == ~E_3~0;~E_3~0 := 2; 2704#L802-3 assume 1 == ~E_4~0;~E_4~0 := 2; 2756#L807-3 assume 1 == ~E_5~0;~E_5~0 := 2; 2757#L812-3 assume 1 == ~E_6~0;~E_6~0 := 2; 3065#L817-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~7;havoc exists_runnable_thread_~__retres1~7; 2944#L508-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7 := 1; 2750#L545-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~7; 2830#L546-1 start_simulation_#t~ret17 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret17;havoc start_simulation_#t~ret17; 2859#L1062 assume !(0 == start_simulation_~tmp~3); 2860#L1062-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret16, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~7;havoc exists_runnable_thread_~__retres1~7; 2862#L508-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7 := 1; 2752#L545-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~7; 2834#L546-2 stop_simulation_#t~ret16 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret16;havoc stop_simulation_#t~ret16; 2708#L1017 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 2709#L1024 stop_simulation_#res := stop_simulation_~__retres2~0; 2980#L1025 start_simulation_#t~ret18 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret18;havoc start_simulation_#t~ret18; 2981#L1075 assume !(0 != start_simulation_~tmp___0~1); 3263#L1043-1 [2018-11-23 14:59:44,822 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 14:59:44,822 INFO L82 PathProgramCache]: Analyzing trace with hash -1280401692, now seen corresponding path program 1 times [2018-11-23 14:59:44,823 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 14:59:44,823 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 14:59:44,823 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 14:59:44,824 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 14:59:44,824 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 14:59:44,834 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 14:59:44,858 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 14:59:44,858 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 14:59:44,858 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-23 14:59:44,858 INFO L799 eck$LassoCheckResult]: stem already infeasible [2018-11-23 14:59:44,858 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 14:59:44,859 INFO L82 PathProgramCache]: Analyzing trace with hash 551788720, now seen corresponding path program 2 times [2018-11-23 14:59:44,859 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 14:59:44,859 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 14:59:44,859 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 14:59:44,859 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 14:59:44,860 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 14:59:44,885 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 14:59:44,915 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 14:59:44,915 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 14:59:44,916 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-23 14:59:44,916 INFO L811 eck$LassoCheckResult]: loop already infeasible [2018-11-23 14:59:44,916 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-23 14:59:44,916 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-23 14:59:44,916 INFO L87 Difference]: Start difference. First operand 660 states and 997 transitions. cyclomatic complexity: 338 Second operand 3 states. [2018-11-23 14:59:44,928 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 14:59:44,928 INFO L93 Difference]: Finished difference Result 660 states and 996 transitions. [2018-11-23 14:59:44,928 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-23 14:59:44,929 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 660 states and 996 transitions. [2018-11-23 14:59:44,931 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 573 [2018-11-23 14:59:44,932 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 660 states to 660 states and 996 transitions. [2018-11-23 14:59:44,933 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 660 [2018-11-23 14:59:44,933 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 660 [2018-11-23 14:59:44,933 INFO L73 IsDeterministic]: Start isDeterministic. Operand 660 states and 996 transitions. [2018-11-23 14:59:44,934 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-23 14:59:44,934 INFO L705 BuchiCegarLoop]: Abstraction has 660 states and 996 transitions. [2018-11-23 14:59:44,935 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 660 states and 996 transitions. [2018-11-23 14:59:44,939 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 660 to 660. [2018-11-23 14:59:44,939 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 660 states. [2018-11-23 14:59:44,940 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 660 states to 660 states and 996 transitions. [2018-11-23 14:59:44,940 INFO L728 BuchiCegarLoop]: Abstraction has 660 states and 996 transitions. [2018-11-23 14:59:44,940 INFO L608 BuchiCegarLoop]: Abstraction has 660 states and 996 transitions. [2018-11-23 14:59:44,940 INFO L442 BuchiCegarLoop]: ======== Iteration 4============ [2018-11-23 14:59:44,940 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 660 states and 996 transitions. [2018-11-23 14:59:44,942 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 573 [2018-11-23 14:59:44,942 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-23 14:59:44,942 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-23 14:59:44,943 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 14:59:44,943 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 14:59:44,944 INFO L794 eck$LassoCheckResult]: Stem: 4552#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0; 4444#L-1 havoc main_#res;havoc main_~__retres1~8;havoc main_~__retres1~8;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 4037#L1006 havoc start_simulation_#t~ret17, start_simulation_#t~ret18, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 4038#L458 assume 1 == ~m_i~0;~m_st~0 := 0; 4387#L465-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 4388#L470-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 4272#L475-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 4273#L480-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 4317#L485-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 4128#L490-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 4129#L495-1 assume !(0 == ~M_E~0); 4399#L674-1 assume !(0 == ~T1_E~0); 4400#L679-1 assume 0 == ~T2_E~0;~T2_E~0 := 1; 4288#L684-1 assume !(0 == ~T3_E~0); 4289#L689-1 assume !(0 == ~T4_E~0); 4532#L694-1 assume !(0 == ~T5_E~0); 4167#L699-1 assume !(0 == ~T6_E~0); 4168#L704-1 assume !(0 == ~E_M~0); 3993#L709-1 assume !(0 == ~E_1~0); 3994#L714-1 assume !(0 == ~E_2~0); 4085#L719-1 assume 0 == ~E_3~0;~E_3~0 := 1; 4086#L724-1 assume !(0 == ~E_4~0); 4393#L729-1 assume !(0 == ~E_5~0); 4394#L734-1 assume !(0 == ~E_6~0); 4282#L739-1 havoc activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 4190#L324 assume !(1 == ~m_pc~0); 4140#L324-2 is_master_triggered_~__retres1~0 := 0; 4139#L335 is_master_triggered_#res := is_master_triggered_~__retres1~0; 4136#L336 activate_threads_#t~ret9 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 4137#L839 assume !(0 != activate_threads_~tmp~1); 4406#L839-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 4227#L343 assume 1 == ~t1_pc~0; 4228#L344 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 4222#L354 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 4223#L355 activate_threads_#t~ret10 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 4362#L847 assume !(0 != activate_threads_~tmp___0~0); 4575#L847-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 4513#L362 assume 1 == ~t2_pc~0; 4514#L363 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 4459#L373 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 4509#L374 activate_threads_#t~ret11 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 4570#L855 assume !(0 != activate_threads_~tmp___1~0); 4581#L855-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 4586#L381 assume !(1 == ~t3_pc~0); 4621#L381-2 is_transmit3_triggered_~__retres1~3 := 0; 4618#L392 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 4619#L393 activate_threads_#t~ret12 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 4050#L863 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 4020#L863-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 4021#L400 assume 1 == ~t4_pc~0; 4081#L401 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 4065#L411 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 4080#L412 activate_threads_#t~ret13 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 4203#L871 assume !(0 != activate_threads_~tmp___3~0); 4297#L871-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 4301#L419 assume !(1 == ~t5_pc~0); 4210#L419-2 is_transmit5_triggered_~__retres1~5 := 0; 4211#L430 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 4274#L431 activate_threads_#t~ret14 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 4275#L879 assume !(0 != activate_threads_~tmp___4~0); 4524#L879-2 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 4525#L438 assume 1 == ~t6_pc~0; 4498#L439 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6 := 1; 4499#L449 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 4496#L450 activate_threads_#t~ret15 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 4497#L887 assume !(0 != activate_threads_~tmp___5~0); 4634#L887-2 assume !(1 == ~M_E~0); 4098#L752-1 assume !(1 == ~T1_E~0); 4099#L757-1 assume !(1 == ~T2_E~0); 4390#L762-1 assume !(1 == ~T3_E~0); 4391#L767-1 assume !(1 == ~T4_E~0); 4280#L772-1 assume !(1 == ~T5_E~0); 4281#L777-1 assume 1 == ~T6_E~0;~T6_E~0 := 2; 4530#L782-1 assume !(1 == ~E_M~0); 4162#L787-1 assume !(1 == ~E_1~0); 4163#L792-1 assume !(1 == ~E_2~0); 4022#L797-1 assume !(1 == ~E_3~0); 4023#L802-1 assume !(1 == ~E_4~0); 4096#L807-1 assume !(1 == ~E_5~0); 4097#L812-1 assume !(1 == ~E_6~0); 4590#L1043-1 [2018-11-23 14:59:44,944 INFO L796 eck$LassoCheckResult]: Loop: 4590#L1043-1 assume !false; 4528#L1044 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret1, eval_#t~nondet2, eval_~tmp_ndt_1~0, eval_#t~nondet3, eval_~tmp_ndt_2~0, eval_#t~nondet4, eval_~tmp_ndt_3~0, eval_#t~nondet5, eval_~tmp_ndt_4~0, eval_#t~nondet6, eval_~tmp_ndt_5~0, eval_#t~nondet7, eval_~tmp_ndt_6~0, eval_#t~nondet8, eval_~tmp_ndt_7~0, eval_~tmp~0;havoc eval_~tmp~0; 4381#L649 assume !false; 4149#L556 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~7;havoc exists_runnable_thread_~__retres1~7; 4150#L508 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7 := 1; 4075#L545 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~7; 4154#L546 eval_#t~ret1 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret1;havoc eval_#t~ret1; 4521#L560 assume !(0 != eval_~tmp~0); 4087#L664 start_simulation_~kernel_st~0 := 2; 4088#L458-1 start_simulation_~kernel_st~0 := 3; 4404#L674-2 assume 0 == ~M_E~0;~M_E~0 := 1; 4376#L674-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 4377#L679-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 4259#L684-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 4260#L689-3 assume !(0 == ~T4_E~0); 4318#L694-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 4145#L699-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 4146#L704-3 assume 0 == ~E_M~0;~E_M~0 := 1; 4008#L709-3 assume 0 == ~E_1~0;~E_1~0 := 1; 4009#L714-3 assume 0 == ~E_2~0;~E_2~0 := 1; 4091#L719-3 assume 0 == ~E_3~0;~E_3~0 := 1; 4092#L724-3 assume 0 == ~E_4~0;~E_4~0 := 1; 4402#L729-3 assume !(0 == ~E_5~0); 4403#L734-3 assume 0 == ~E_6~0;~E_6~0 := 1; 4292#L739-3 havoc activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 4151#L324-24 assume !(1 == ~m_pc~0); 4152#L324-26 is_master_triggered_~__retres1~0 := 0; 4158#L335-8 is_master_triggered_#res := is_master_triggered_~__retres1~0; 4182#L336-8 activate_threads_#t~ret9 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 4356#L839-24 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 4319#L839-26 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 4320#L343-24 assume !(1 == ~t1_pc~0); 4353#L343-26 is_transmit1_triggered_~__retres1~1 := 0; 4352#L354-8 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 4348#L355-8 activate_threads_#t~ret10 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 4349#L847-24 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 4547#L847-26 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 4548#L362-24 assume 1 == ~t2_pc~0; 4540#L363-8 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 4432#L373-8 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 4433#L374-8 activate_threads_#t~ret11 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 4539#L855-24 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 4635#L855-26 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 4636#L381-24 assume 1 == ~t3_pc~0; 4643#L382-8 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 4612#L392-8 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 4613#L393-8 activate_threads_#t~ret12 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 4183#L863-24 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 4184#L863-26 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 3999#L400-24 assume !(1 == ~t4_pc~0); 4000#L400-26 is_transmit4_triggered_~__retres1~4 := 0; 4013#L411-8 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 4054#L412-8 activate_threads_#t~ret13 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 4177#L871-24 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 4407#L871-26 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 4290#L419-24 assume 1 == ~t5_pc~0; 4291#L420-8 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 4263#L430-8 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 4311#L431-8 activate_threads_#t~ret14 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 4414#L879-24 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 4436#L879-26 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 4442#L438-24 assume 1 == ~t6_pc~0; 4490#L439-8 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6 := 1; 4491#L449-8 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 4486#L450-8 activate_threads_#t~ret15 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 4487#L887-24 assume 0 != activate_threads_~tmp___5~0;~t6_st~0 := 0; 4591#L887-26 assume !(1 == ~M_E~0); 4089#L752-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 4090#L757-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 4396#L762-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 4397#L767-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 4286#L772-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 4287#L777-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 4531#L782-3 assume 1 == ~E_M~0;~E_M~0 := 2; 4165#L787-3 assume !(1 == ~E_1~0); 4166#L792-3 assume 1 == ~E_2~0;~E_2~0 := 2; 4030#L797-3 assume 1 == ~E_3~0;~E_3~0 := 2; 4031#L802-3 assume 1 == ~E_4~0;~E_4~0 := 2; 4083#L807-3 assume 1 == ~E_5~0;~E_5~0 := 2; 4084#L812-3 assume 1 == ~E_6~0;~E_6~0 := 2; 4392#L817-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~7;havoc exists_runnable_thread_~__retres1~7; 4271#L508-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7 := 1; 4077#L545-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~7; 4157#L546-1 start_simulation_#t~ret17 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret17;havoc start_simulation_#t~ret17; 4186#L1062 assume !(0 == start_simulation_~tmp~3); 4187#L1062-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret16, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~7;havoc exists_runnable_thread_~__retres1~7; 4189#L508-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7 := 1; 4079#L545-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~7; 4161#L546-2 stop_simulation_#t~ret16 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret16;havoc stop_simulation_#t~ret16; 4035#L1017 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 4036#L1024 stop_simulation_#res := stop_simulation_~__retres2~0; 4307#L1025 start_simulation_#t~ret18 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret18;havoc start_simulation_#t~ret18; 4308#L1075 assume !(0 != start_simulation_~tmp___0~1); 4590#L1043-1 [2018-11-23 14:59:44,944 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 14:59:44,944 INFO L82 PathProgramCache]: Analyzing trace with hash 2127342758, now seen corresponding path program 1 times [2018-11-23 14:59:44,944 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 14:59:44,944 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 14:59:44,945 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 14:59:44,945 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-23 14:59:44,945 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 14:59:44,949 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 14:59:44,974 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 14:59:44,974 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 14:59:44,974 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-23 14:59:44,974 INFO L799 eck$LassoCheckResult]: stem already infeasible [2018-11-23 14:59:44,975 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 14:59:44,975 INFO L82 PathProgramCache]: Analyzing trace with hash -1923452657, now seen corresponding path program 1 times [2018-11-23 14:59:44,975 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 14:59:44,975 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 14:59:44,975 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 14:59:44,976 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 14:59:44,976 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 14:59:44,985 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 14:59:45,015 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 14:59:45,015 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 14:59:45,015 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-23 14:59:45,016 INFO L811 eck$LassoCheckResult]: loop already infeasible [2018-11-23 14:59:45,016 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-23 14:59:45,016 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-23 14:59:45,016 INFO L87 Difference]: Start difference. First operand 660 states and 996 transitions. cyclomatic complexity: 337 Second operand 3 states. [2018-11-23 14:59:45,028 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 14:59:45,028 INFO L93 Difference]: Finished difference Result 660 states and 995 transitions. [2018-11-23 14:59:45,028 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-23 14:59:45,029 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 660 states and 995 transitions. [2018-11-23 14:59:45,031 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 573 [2018-11-23 14:59:45,032 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 660 states to 660 states and 995 transitions. [2018-11-23 14:59:45,032 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 660 [2018-11-23 14:59:45,033 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 660 [2018-11-23 14:59:45,033 INFO L73 IsDeterministic]: Start isDeterministic. Operand 660 states and 995 transitions. [2018-11-23 14:59:45,034 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-23 14:59:45,034 INFO L705 BuchiCegarLoop]: Abstraction has 660 states and 995 transitions. [2018-11-23 14:59:45,034 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 660 states and 995 transitions. [2018-11-23 14:59:45,038 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 660 to 660. [2018-11-23 14:59:45,038 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 660 states. [2018-11-23 14:59:45,040 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 660 states to 660 states and 995 transitions. [2018-11-23 14:59:45,040 INFO L728 BuchiCegarLoop]: Abstraction has 660 states and 995 transitions. [2018-11-23 14:59:45,040 INFO L608 BuchiCegarLoop]: Abstraction has 660 states and 995 transitions. [2018-11-23 14:59:45,040 INFO L442 BuchiCegarLoop]: ======== Iteration 5============ [2018-11-23 14:59:45,040 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 660 states and 995 transitions. [2018-11-23 14:59:45,042 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 573 [2018-11-23 14:59:45,042 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-23 14:59:45,042 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-23 14:59:45,043 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 14:59:45,043 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 14:59:45,044 INFO L794 eck$LassoCheckResult]: Stem: 5879#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0; 5774#L-1 havoc main_#res;havoc main_~__retres1~8;havoc main_~__retres1~8;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 5364#L1006 havoc start_simulation_#t~ret17, start_simulation_#t~ret18, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 5365#L458 assume 1 == ~m_i~0;~m_st~0 := 0; 5714#L465-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 5715#L470-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 5599#L475-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 5600#L480-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 5644#L485-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 5458#L490-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 5459#L495-1 assume !(0 == ~M_E~0); 5726#L674-1 assume !(0 == ~T1_E~0); 5727#L679-1 assume 0 == ~T2_E~0;~T2_E~0 := 1; 5617#L684-1 assume !(0 == ~T3_E~0); 5618#L689-1 assume !(0 == ~T4_E~0); 5859#L694-1 assume !(0 == ~T5_E~0); 5494#L699-1 assume !(0 == ~T6_E~0); 5495#L704-1 assume !(0 == ~E_M~0); 5320#L709-1 assume !(0 == ~E_1~0); 5321#L714-1 assume !(0 == ~E_2~0); 5412#L719-1 assume 0 == ~E_3~0;~E_3~0 := 1; 5413#L724-1 assume !(0 == ~E_4~0); 5720#L729-1 assume !(0 == ~E_5~0); 5721#L734-1 assume !(0 == ~E_6~0); 5609#L739-1 havoc activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 5517#L324 assume !(1 == ~m_pc~0); 5467#L324-2 is_master_triggered_~__retres1~0 := 0; 5466#L335 is_master_triggered_#res := is_master_triggered_~__retres1~0; 5463#L336 activate_threads_#t~ret9 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 5464#L839 assume !(0 != activate_threads_~tmp~1); 5733#L839-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 5554#L343 assume 1 == ~t1_pc~0; 5555#L344 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 5549#L354 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 5550#L355 activate_threads_#t~ret10 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 5689#L847 assume !(0 != activate_threads_~tmp___0~0); 5902#L847-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 5840#L362 assume 1 == ~t2_pc~0; 5841#L363 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 5786#L373 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 5839#L374 activate_threads_#t~ret11 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 5897#L855 assume !(0 != activate_threads_~tmp___1~0); 5908#L855-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 5913#L381 assume !(1 == ~t3_pc~0); 5948#L381-2 is_transmit3_triggered_~__retres1~3 := 0; 5946#L392 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 5947#L393 activate_threads_#t~ret12 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 5377#L863 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 5347#L863-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 5348#L400 assume 1 == ~t4_pc~0; 5408#L401 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 5392#L411 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 5407#L412 activate_threads_#t~ret13 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 5530#L871 assume !(0 != activate_threads_~tmp___3~0); 5624#L871-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 5628#L419 assume !(1 == ~t5_pc~0); 5537#L419-2 is_transmit5_triggered_~__retres1~5 := 0; 5538#L430 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 5601#L431 activate_threads_#t~ret14 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 5602#L879 assume !(0 != activate_threads_~tmp___4~0); 5851#L879-2 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 5852#L438 assume 1 == ~t6_pc~0; 5825#L439 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6 := 1; 5826#L449 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 5823#L450 activate_threads_#t~ret15 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 5824#L887 assume !(0 != activate_threads_~tmp___5~0); 5961#L887-2 assume !(1 == ~M_E~0); 5425#L752-1 assume !(1 == ~T1_E~0); 5426#L757-1 assume !(1 == ~T2_E~0); 5717#L762-1 assume !(1 == ~T3_E~0); 5718#L767-1 assume !(1 == ~T4_E~0); 5607#L772-1 assume !(1 == ~T5_E~0); 5608#L777-1 assume 1 == ~T6_E~0;~T6_E~0 := 2; 5857#L782-1 assume !(1 == ~E_M~0); 5489#L787-1 assume !(1 == ~E_1~0); 5490#L792-1 assume !(1 == ~E_2~0); 5349#L797-1 assume !(1 == ~E_3~0); 5350#L802-1 assume !(1 == ~E_4~0); 5423#L807-1 assume !(1 == ~E_5~0); 5424#L812-1 assume !(1 == ~E_6~0); 5917#L1043-1 [2018-11-23 14:59:45,044 INFO L796 eck$LassoCheckResult]: Loop: 5917#L1043-1 assume !false; 5855#L1044 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret1, eval_#t~nondet2, eval_~tmp_ndt_1~0, eval_#t~nondet3, eval_~tmp_ndt_2~0, eval_#t~nondet4, eval_~tmp_ndt_3~0, eval_#t~nondet5, eval_~tmp_ndt_4~0, eval_#t~nondet6, eval_~tmp_ndt_5~0, eval_#t~nondet7, eval_~tmp_ndt_6~0, eval_#t~nondet8, eval_~tmp_ndt_7~0, eval_~tmp~0;havoc eval_~tmp~0; 5710#L649 assume !false; 5476#L556 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~7;havoc exists_runnable_thread_~__retres1~7; 5477#L508 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7 := 1; 5402#L545 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~7; 5481#L546 eval_#t~ret1 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret1;havoc eval_#t~ret1; 5848#L560 assume !(0 != eval_~tmp~0); 5414#L664 start_simulation_~kernel_st~0 := 2; 5415#L458-1 start_simulation_~kernel_st~0 := 3; 5731#L674-2 assume 0 == ~M_E~0;~M_E~0 := 1; 5703#L674-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 5704#L679-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 5588#L684-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 5589#L689-3 assume !(0 == ~T4_E~0); 5645#L694-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 5472#L699-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 5473#L704-3 assume 0 == ~E_M~0;~E_M~0 := 1; 5335#L709-3 assume 0 == ~E_1~0;~E_1~0 := 1; 5336#L714-3 assume 0 == ~E_2~0;~E_2~0 := 1; 5418#L719-3 assume 0 == ~E_3~0;~E_3~0 := 1; 5419#L724-3 assume 0 == ~E_4~0;~E_4~0 := 1; 5729#L729-3 assume !(0 == ~E_5~0); 5730#L734-3 assume 0 == ~E_6~0;~E_6~0 := 1; 5619#L739-3 havoc activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 5478#L324-24 assume !(1 == ~m_pc~0); 5479#L324-26 is_master_triggered_~__retres1~0 := 0; 5485#L335-8 is_master_triggered_#res := is_master_triggered_~__retres1~0; 5509#L336-8 activate_threads_#t~ret9 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 5686#L839-24 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 5646#L839-26 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 5647#L343-24 assume !(1 == ~t1_pc~0); 5680#L343-26 is_transmit1_triggered_~__retres1~1 := 0; 5679#L354-8 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 5675#L355-8 activate_threads_#t~ret10 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 5676#L847-24 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 5874#L847-26 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 5875#L362-24 assume 1 == ~t2_pc~0; 5867#L363-8 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 5759#L373-8 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 5760#L374-8 activate_threads_#t~ret11 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 5866#L855-24 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 5962#L855-26 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 5963#L381-24 assume 1 == ~t3_pc~0; 5970#L382-8 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 5939#L392-8 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 5940#L393-8 activate_threads_#t~ret12 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 5510#L863-24 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 5511#L863-26 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 5326#L400-24 assume 1 == ~t4_pc~0; 5328#L401-8 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 5338#L411-8 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 5381#L412-8 activate_threads_#t~ret13 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 5504#L871-24 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 5734#L871-26 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 5615#L419-24 assume 1 == ~t5_pc~0; 5616#L420-8 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 5587#L430-8 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 5638#L431-8 activate_threads_#t~ret14 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 5741#L879-24 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 5762#L879-26 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 5769#L438-24 assume 1 == ~t6_pc~0; 5815#L439-8 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6 := 1; 5816#L449-8 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 5813#L450-8 activate_threads_#t~ret15 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 5814#L887-24 assume 0 != activate_threads_~tmp___5~0;~t6_st~0 := 0; 5918#L887-26 assume !(1 == ~M_E~0); 5416#L752-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 5417#L757-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 5723#L762-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 5724#L767-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 5612#L772-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 5613#L777-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 5858#L782-3 assume 1 == ~E_M~0;~E_M~0 := 2; 5492#L787-3 assume !(1 == ~E_1~0); 5493#L792-3 assume 1 == ~E_2~0;~E_2~0 := 2; 5356#L797-3 assume 1 == ~E_3~0;~E_3~0 := 2; 5357#L802-3 assume 1 == ~E_4~0;~E_4~0 := 2; 5410#L807-3 assume 1 == ~E_5~0;~E_5~0 := 2; 5411#L812-3 assume 1 == ~E_6~0;~E_6~0 := 2; 5719#L817-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~7;havoc exists_runnable_thread_~__retres1~7; 5598#L508-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7 := 1; 5404#L545-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~7; 5482#L546-1 start_simulation_#t~ret17 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret17;havoc start_simulation_#t~ret17; 5513#L1062 assume !(0 == start_simulation_~tmp~3); 5514#L1062-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret16, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~7;havoc exists_runnable_thread_~__retres1~7; 5516#L508-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7 := 1; 5406#L545-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~7; 5488#L546-2 stop_simulation_#t~ret16 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret16;havoc stop_simulation_#t~ret16; 5359#L1017 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 5360#L1024 stop_simulation_#res := stop_simulation_~__retres2~0; 5634#L1025 start_simulation_#t~ret18 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret18;havoc start_simulation_#t~ret18; 5635#L1075 assume !(0 != start_simulation_~tmp___0~1); 5917#L1043-1 [2018-11-23 14:59:45,044 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 14:59:45,044 INFO L82 PathProgramCache]: Analyzing trace with hash -256581980, now seen corresponding path program 1 times [2018-11-23 14:59:45,044 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 14:59:45,044 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 14:59:45,045 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 14:59:45,045 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 14:59:45,045 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 14:59:45,050 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 14:59:45,074 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 14:59:45,074 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 14:59:45,075 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-23 14:59:45,075 INFO L799 eck$LassoCheckResult]: stem already infeasible [2018-11-23 14:59:45,075 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 14:59:45,075 INFO L82 PathProgramCache]: Analyzing trace with hash -648349968, now seen corresponding path program 1 times [2018-11-23 14:59:45,075 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 14:59:45,075 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 14:59:45,076 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 14:59:45,076 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 14:59:45,076 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 14:59:45,083 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 14:59:45,114 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 14:59:45,114 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 14:59:45,114 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-23 14:59:45,114 INFO L811 eck$LassoCheckResult]: loop already infeasible [2018-11-23 14:59:45,115 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-23 14:59:45,115 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-23 14:59:45,115 INFO L87 Difference]: Start difference. First operand 660 states and 995 transitions. cyclomatic complexity: 336 Second operand 3 states. [2018-11-23 14:59:45,130 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 14:59:45,130 INFO L93 Difference]: Finished difference Result 660 states and 994 transitions. [2018-11-23 14:59:45,131 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-23 14:59:45,131 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 660 states and 994 transitions. [2018-11-23 14:59:45,134 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 573 [2018-11-23 14:59:45,136 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 660 states to 660 states and 994 transitions. [2018-11-23 14:59:45,136 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 660 [2018-11-23 14:59:45,137 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 660 [2018-11-23 14:59:45,137 INFO L73 IsDeterministic]: Start isDeterministic. Operand 660 states and 994 transitions. [2018-11-23 14:59:45,138 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-23 14:59:45,138 INFO L705 BuchiCegarLoop]: Abstraction has 660 states and 994 transitions. [2018-11-23 14:59:45,139 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 660 states and 994 transitions. [2018-11-23 14:59:45,145 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 660 to 660. [2018-11-23 14:59:45,145 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 660 states. [2018-11-23 14:59:45,147 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 660 states to 660 states and 994 transitions. [2018-11-23 14:59:45,147 INFO L728 BuchiCegarLoop]: Abstraction has 660 states and 994 transitions. [2018-11-23 14:59:45,147 INFO L608 BuchiCegarLoop]: Abstraction has 660 states and 994 transitions. [2018-11-23 14:59:45,147 INFO L442 BuchiCegarLoop]: ======== Iteration 6============ [2018-11-23 14:59:45,147 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 660 states and 994 transitions. [2018-11-23 14:59:45,149 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 573 [2018-11-23 14:59:45,149 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-23 14:59:45,150 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-23 14:59:45,151 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 14:59:45,151 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 14:59:45,151 INFO L794 eck$LassoCheckResult]: Stem: 7207#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0; 7103#L-1 havoc main_#res;havoc main_~__retres1~8;havoc main_~__retres1~8;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 6691#L1006 havoc start_simulation_#t~ret17, start_simulation_#t~ret18, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 6692#L458 assume 1 == ~m_i~0;~m_st~0 := 0; 7041#L465-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 7042#L470-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 6926#L475-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 6927#L480-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 6971#L485-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 6785#L490-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 6786#L495-1 assume !(0 == ~M_E~0); 7054#L674-1 assume !(0 == ~T1_E~0); 7055#L679-1 assume 0 == ~T2_E~0;~T2_E~0 := 1; 6944#L684-1 assume !(0 == ~T3_E~0); 6945#L689-1 assume !(0 == ~T4_E~0); 7186#L694-1 assume !(0 == ~T5_E~0); 6821#L699-1 assume !(0 == ~T6_E~0); 6822#L704-1 assume !(0 == ~E_M~0); 6647#L709-1 assume !(0 == ~E_1~0); 6648#L714-1 assume !(0 == ~E_2~0); 6739#L719-1 assume 0 == ~E_3~0;~E_3~0 := 1; 6740#L724-1 assume !(0 == ~E_4~0); 7047#L729-1 assume !(0 == ~E_5~0); 7048#L734-1 assume !(0 == ~E_6~0); 6937#L739-1 havoc activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 6844#L324 assume !(1 == ~m_pc~0); 6794#L324-2 is_master_triggered_~__retres1~0 := 0; 6793#L335 is_master_triggered_#res := is_master_triggered_~__retres1~0; 6790#L336 activate_threads_#t~ret9 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 6791#L839 assume !(0 != activate_threads_~tmp~1); 7060#L839-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 6881#L343 assume 1 == ~t1_pc~0; 6882#L344 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 6879#L354 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 6880#L355 activate_threads_#t~ret10 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 7016#L847 assume !(0 != activate_threads_~tmp___0~0); 7229#L847-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 7167#L362 assume 1 == ~t2_pc~0; 7168#L363 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 7113#L373 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 7166#L374 activate_threads_#t~ret11 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 7224#L855 assume !(0 != activate_threads_~tmp___1~0); 7235#L855-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 7240#L381 assume !(1 == ~t3_pc~0); 7275#L381-2 is_transmit3_triggered_~__retres1~3 := 0; 7273#L392 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 7274#L393 activate_threads_#t~ret12 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 6705#L863 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 6674#L863-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 6675#L400 assume 1 == ~t4_pc~0; 6735#L401 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 6719#L411 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 6734#L412 activate_threads_#t~ret13 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 6857#L871 assume !(0 != activate_threads_~tmp___3~0); 6951#L871-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 6955#L419 assume !(1 == ~t5_pc~0); 6864#L419-2 is_transmit5_triggered_~__retres1~5 := 0; 6865#L430 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 6928#L431 activate_threads_#t~ret14 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 6929#L879 assume !(0 != activate_threads_~tmp___4~0); 7178#L879-2 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 7179#L438 assume 1 == ~t6_pc~0; 7152#L439 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6 := 1; 7153#L449 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 7150#L450 activate_threads_#t~ret15 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 7151#L887 assume !(0 != activate_threads_~tmp___5~0); 7288#L887-2 assume !(1 == ~M_E~0); 6752#L752-1 assume !(1 == ~T1_E~0); 6753#L757-1 assume !(1 == ~T2_E~0); 7044#L762-1 assume !(1 == ~T3_E~0); 7045#L767-1 assume !(1 == ~T4_E~0); 6934#L772-1 assume !(1 == ~T5_E~0); 6935#L777-1 assume 1 == ~T6_E~0;~T6_E~0 := 2; 7184#L782-1 assume !(1 == ~E_M~0); 6817#L787-1 assume !(1 == ~E_1~0); 6818#L792-1 assume !(1 == ~E_2~0); 6679#L797-1 assume !(1 == ~E_3~0); 6680#L802-1 assume !(1 == ~E_4~0); 6750#L807-1 assume !(1 == ~E_5~0); 6751#L812-1 assume !(1 == ~E_6~0); 7244#L1043-1 [2018-11-23 14:59:45,151 INFO L796 eck$LassoCheckResult]: Loop: 7244#L1043-1 assume !false; 7182#L1044 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret1, eval_#t~nondet2, eval_~tmp_ndt_1~0, eval_#t~nondet3, eval_~tmp_ndt_2~0, eval_#t~nondet4, eval_~tmp_ndt_3~0, eval_#t~nondet5, eval_~tmp_ndt_4~0, eval_#t~nondet6, eval_~tmp_ndt_5~0, eval_#t~nondet7, eval_~tmp_ndt_6~0, eval_#t~nondet8, eval_~tmp_ndt_7~0, eval_~tmp~0;havoc eval_~tmp~0; 7035#L649 assume !false; 6806#L556 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~7;havoc exists_runnable_thread_~__retres1~7; 6807#L508 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7 := 1; 6729#L545 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~7; 6808#L546 eval_#t~ret1 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret1;havoc eval_#t~ret1; 7175#L560 assume !(0 != eval_~tmp~0); 6741#L664 start_simulation_~kernel_st~0 := 2; 6742#L458-1 start_simulation_~kernel_st~0 := 3; 7058#L674-2 assume 0 == ~M_E~0;~M_E~0 := 1; 7031#L674-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 7032#L679-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 6916#L684-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 6917#L689-3 assume !(0 == ~T4_E~0); 6972#L694-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 6799#L699-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 6800#L704-3 assume 0 == ~E_M~0;~E_M~0 := 1; 6659#L709-3 assume 0 == ~E_1~0;~E_1~0 := 1; 6660#L714-3 assume 0 == ~E_2~0;~E_2~0 := 1; 6745#L719-3 assume 0 == ~E_3~0;~E_3~0 := 1; 6746#L724-3 assume 0 == ~E_4~0;~E_4~0 := 1; 7056#L729-3 assume !(0 == ~E_5~0); 7057#L734-3 assume 0 == ~E_6~0;~E_6~0 := 1; 6946#L739-3 havoc activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 6803#L324-24 assume !(1 == ~m_pc~0); 6804#L324-26 is_master_triggered_~__retres1~0 := 0; 6812#L335-8 is_master_triggered_#res := is_master_triggered_~__retres1~0; 6836#L336-8 activate_threads_#t~ret9 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 7010#L839-24 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 6973#L839-26 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 6974#L343-24 assume 1 == ~t1_pc~0; 7005#L344-8 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 7006#L354-8 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 7002#L355-8 activate_threads_#t~ret10 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 7003#L847-24 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 7201#L847-26 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 7202#L362-24 assume 1 == ~t2_pc~0; 7194#L363-8 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 7086#L373-8 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 7087#L374-8 activate_threads_#t~ret11 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 7193#L855-24 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 7289#L855-26 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 7290#L381-24 assume 1 == ~t3_pc~0; 7297#L382-8 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 7266#L392-8 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 7267#L393-8 activate_threads_#t~ret12 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 6837#L863-24 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 6838#L863-26 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 6653#L400-24 assume !(1 == ~t4_pc~0); 6654#L400-26 is_transmit4_triggered_~__retres1~4 := 0; 6667#L411-8 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 6708#L412-8 activate_threads_#t~ret13 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 6831#L871-24 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 7061#L871-26 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 6942#L419-24 assume !(1 == ~t5_pc~0); 6914#L419-26 is_transmit5_triggered_~__retres1~5 := 0; 6915#L430-8 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 6965#L431-8 activate_threads_#t~ret14 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 7068#L879-24 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 7089#L879-26 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 7096#L438-24 assume 1 == ~t6_pc~0; 7144#L439-8 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6 := 1; 7145#L449-8 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 7140#L450-8 activate_threads_#t~ret15 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 7141#L887-24 assume 0 != activate_threads_~tmp___5~0;~t6_st~0 := 0; 7245#L887-26 assume !(1 == ~M_E~0); 6743#L752-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 6744#L757-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 7050#L762-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 7051#L767-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 6940#L772-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 6941#L777-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 7185#L782-3 assume 1 == ~E_M~0;~E_M~0 := 2; 6819#L787-3 assume !(1 == ~E_1~0); 6820#L792-3 assume 1 == ~E_2~0;~E_2~0 := 2; 6684#L797-3 assume 1 == ~E_3~0;~E_3~0 := 2; 6685#L802-3 assume 1 == ~E_4~0;~E_4~0 := 2; 6737#L807-3 assume 1 == ~E_5~0;~E_5~0 := 2; 6738#L812-3 assume 1 == ~E_6~0;~E_6~0 := 2; 7046#L817-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~7;havoc exists_runnable_thread_~__retres1~7; 6925#L508-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7 := 1; 6731#L545-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~7; 6809#L546-1 start_simulation_#t~ret17 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret17;havoc start_simulation_#t~ret17; 6840#L1062 assume !(0 == start_simulation_~tmp~3); 6841#L1062-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret16, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~7;havoc exists_runnable_thread_~__retres1~7; 6843#L508-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7 := 1; 6733#L545-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~7; 6815#L546-2 stop_simulation_#t~ret16 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret16;havoc stop_simulation_#t~ret16; 6689#L1017 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 6690#L1024 stop_simulation_#res := stop_simulation_~__retres2~0; 6961#L1025 start_simulation_#t~ret18 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret18;havoc start_simulation_#t~ret18; 6962#L1075 assume !(0 != start_simulation_~tmp___0~1); 7244#L1043-1 [2018-11-23 14:59:45,151 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 14:59:45,151 INFO L82 PathProgramCache]: Analyzing trace with hash -333482778, now seen corresponding path program 1 times [2018-11-23 14:59:45,152 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 14:59:45,152 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 14:59:45,152 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 14:59:45,152 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 14:59:45,152 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 14:59:45,156 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 14:59:45,178 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 14:59:45,179 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 14:59:45,179 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-23 14:59:45,179 INFO L799 eck$LassoCheckResult]: stem already infeasible [2018-11-23 14:59:45,179 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 14:59:45,179 INFO L82 PathProgramCache]: Analyzing trace with hash 1075109391, now seen corresponding path program 1 times [2018-11-23 14:59:45,179 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 14:59:45,179 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 14:59:45,180 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 14:59:45,180 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 14:59:45,180 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 14:59:45,186 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 14:59:45,221 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 14:59:45,221 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 14:59:45,221 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-23 14:59:45,221 INFO L811 eck$LassoCheckResult]: loop already infeasible [2018-11-23 14:59:45,221 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-23 14:59:45,222 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-23 14:59:45,222 INFO L87 Difference]: Start difference. First operand 660 states and 994 transitions. cyclomatic complexity: 335 Second operand 3 states. [2018-11-23 14:59:45,231 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 14:59:45,231 INFO L93 Difference]: Finished difference Result 660 states and 993 transitions. [2018-11-23 14:59:45,232 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-23 14:59:45,232 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 660 states and 993 transitions. [2018-11-23 14:59:45,235 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 573 [2018-11-23 14:59:45,237 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 660 states to 660 states and 993 transitions. [2018-11-23 14:59:45,237 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 660 [2018-11-23 14:59:45,238 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 660 [2018-11-23 14:59:45,238 INFO L73 IsDeterministic]: Start isDeterministic. Operand 660 states and 993 transitions. [2018-11-23 14:59:45,239 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-23 14:59:45,239 INFO L705 BuchiCegarLoop]: Abstraction has 660 states and 993 transitions. [2018-11-23 14:59:45,240 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 660 states and 993 transitions. [2018-11-23 14:59:45,246 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 660 to 660. [2018-11-23 14:59:45,246 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 660 states. [2018-11-23 14:59:45,248 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 660 states to 660 states and 993 transitions. [2018-11-23 14:59:45,248 INFO L728 BuchiCegarLoop]: Abstraction has 660 states and 993 transitions. [2018-11-23 14:59:45,248 INFO L608 BuchiCegarLoop]: Abstraction has 660 states and 993 transitions. [2018-11-23 14:59:45,248 INFO L442 BuchiCegarLoop]: ======== Iteration 7============ [2018-11-23 14:59:45,248 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 660 states and 993 transitions. [2018-11-23 14:59:45,250 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 573 [2018-11-23 14:59:45,250 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-23 14:59:45,251 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-23 14:59:45,252 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 14:59:45,252 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 14:59:45,252 INFO L794 eck$LassoCheckResult]: Stem: 8533#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0; 8425#L-1 havoc main_#res;havoc main_~__retres1~8;havoc main_~__retres1~8;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 8018#L1006 havoc start_simulation_#t~ret17, start_simulation_#t~ret18, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 8019#L458 assume 1 == ~m_i~0;~m_st~0 := 0; 8368#L465-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 8369#L470-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 8253#L475-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 8254#L480-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 8298#L485-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 8109#L490-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 8110#L495-1 assume !(0 == ~M_E~0); 8380#L674-1 assume !(0 == ~T1_E~0); 8381#L679-1 assume 0 == ~T2_E~0;~T2_E~0 := 1; 8269#L684-1 assume !(0 == ~T3_E~0); 8270#L689-1 assume !(0 == ~T4_E~0); 8513#L694-1 assume !(0 == ~T5_E~0); 8148#L699-1 assume !(0 == ~T6_E~0); 8149#L704-1 assume !(0 == ~E_M~0); 7974#L709-1 assume !(0 == ~E_1~0); 7975#L714-1 assume !(0 == ~E_2~0); 8066#L719-1 assume 0 == ~E_3~0;~E_3~0 := 1; 8067#L724-1 assume !(0 == ~E_4~0); 8374#L729-1 assume !(0 == ~E_5~0); 8375#L734-1 assume !(0 == ~E_6~0); 8263#L739-1 havoc activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 8171#L324 assume !(1 == ~m_pc~0); 8121#L324-2 is_master_triggered_~__retres1~0 := 0; 8120#L335 is_master_triggered_#res := is_master_triggered_~__retres1~0; 8117#L336 activate_threads_#t~ret9 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 8118#L839 assume !(0 != activate_threads_~tmp~1); 8387#L839-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 8208#L343 assume 1 == ~t1_pc~0; 8209#L344 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 8203#L354 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 8204#L355 activate_threads_#t~ret10 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 8343#L847 assume !(0 != activate_threads_~tmp___0~0); 8556#L847-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 8494#L362 assume 1 == ~t2_pc~0; 8495#L363 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 8440#L373 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 8490#L374 activate_threads_#t~ret11 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 8551#L855 assume !(0 != activate_threads_~tmp___1~0); 8562#L855-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 8567#L381 assume !(1 == ~t3_pc~0); 8602#L381-2 is_transmit3_triggered_~__retres1~3 := 0; 8599#L392 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 8600#L393 activate_threads_#t~ret12 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 8031#L863 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 8001#L863-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 8002#L400 assume 1 == ~t4_pc~0; 8062#L401 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 8046#L411 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 8061#L412 activate_threads_#t~ret13 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 8184#L871 assume !(0 != activate_threads_~tmp___3~0); 8278#L871-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 8282#L419 assume !(1 == ~t5_pc~0); 8191#L419-2 is_transmit5_triggered_~__retres1~5 := 0; 8192#L430 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 8255#L431 activate_threads_#t~ret14 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 8256#L879 assume !(0 != activate_threads_~tmp___4~0); 8505#L879-2 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 8506#L438 assume 1 == ~t6_pc~0; 8479#L439 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6 := 1; 8480#L449 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 8477#L450 activate_threads_#t~ret15 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 8478#L887 assume !(0 != activate_threads_~tmp___5~0); 8615#L887-2 assume !(1 == ~M_E~0); 8079#L752-1 assume !(1 == ~T1_E~0); 8080#L757-1 assume !(1 == ~T2_E~0); 8371#L762-1 assume !(1 == ~T3_E~0); 8372#L767-1 assume !(1 == ~T4_E~0); 8261#L772-1 assume !(1 == ~T5_E~0); 8262#L777-1 assume 1 == ~T6_E~0;~T6_E~0 := 2; 8511#L782-1 assume !(1 == ~E_M~0); 8143#L787-1 assume !(1 == ~E_1~0); 8144#L792-1 assume !(1 == ~E_2~0); 8003#L797-1 assume !(1 == ~E_3~0); 8004#L802-1 assume !(1 == ~E_4~0); 8077#L807-1 assume !(1 == ~E_5~0); 8078#L812-1 assume !(1 == ~E_6~0); 8571#L1043-1 [2018-11-23 14:59:45,252 INFO L796 eck$LassoCheckResult]: Loop: 8571#L1043-1 assume !false; 8509#L1044 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret1, eval_#t~nondet2, eval_~tmp_ndt_1~0, eval_#t~nondet3, eval_~tmp_ndt_2~0, eval_#t~nondet4, eval_~tmp_ndt_3~0, eval_#t~nondet5, eval_~tmp_ndt_4~0, eval_#t~nondet6, eval_~tmp_ndt_5~0, eval_#t~nondet7, eval_~tmp_ndt_6~0, eval_#t~nondet8, eval_~tmp_ndt_7~0, eval_~tmp~0;havoc eval_~tmp~0; 8362#L649 assume !false; 8130#L556 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~7;havoc exists_runnable_thread_~__retres1~7; 8131#L508 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7 := 1; 8056#L545 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~7; 8135#L546 eval_#t~ret1 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret1;havoc eval_#t~ret1; 8502#L560 assume !(0 != eval_~tmp~0); 8068#L664 start_simulation_~kernel_st~0 := 2; 8069#L458-1 start_simulation_~kernel_st~0 := 3; 8385#L674-2 assume 0 == ~M_E~0;~M_E~0 := 1; 8357#L674-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 8358#L679-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 8240#L684-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 8241#L689-3 assume !(0 == ~T4_E~0); 8299#L694-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 8126#L699-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 8127#L704-3 assume 0 == ~E_M~0;~E_M~0 := 1; 7989#L709-3 assume 0 == ~E_1~0;~E_1~0 := 1; 7990#L714-3 assume 0 == ~E_2~0;~E_2~0 := 1; 8072#L719-3 assume 0 == ~E_3~0;~E_3~0 := 1; 8073#L724-3 assume 0 == ~E_4~0;~E_4~0 := 1; 8383#L729-3 assume !(0 == ~E_5~0); 8384#L734-3 assume 0 == ~E_6~0;~E_6~0 := 1; 8273#L739-3 havoc activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 8132#L324-24 assume !(1 == ~m_pc~0); 8133#L324-26 is_master_triggered_~__retres1~0 := 0; 8139#L335-8 is_master_triggered_#res := is_master_triggered_~__retres1~0; 8163#L336-8 activate_threads_#t~ret9 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 8337#L839-24 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 8300#L839-26 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 8301#L343-24 assume 1 == ~t1_pc~0; 8332#L344-8 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 8333#L354-8 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 8329#L355-8 activate_threads_#t~ret10 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 8330#L847-24 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 8528#L847-26 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 8529#L362-24 assume 1 == ~t2_pc~0; 8521#L363-8 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 8413#L373-8 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 8414#L374-8 activate_threads_#t~ret11 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 8520#L855-24 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 8616#L855-26 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 8617#L381-24 assume 1 == ~t3_pc~0; 8624#L382-8 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 8593#L392-8 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 8594#L393-8 activate_threads_#t~ret12 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 8164#L863-24 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 8165#L863-26 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 7980#L400-24 assume !(1 == ~t4_pc~0); 7981#L400-26 is_transmit4_triggered_~__retres1~4 := 0; 7994#L411-8 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 8035#L412-8 activate_threads_#t~ret13 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 8158#L871-24 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 8388#L871-26 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 8271#L419-24 assume 1 == ~t5_pc~0; 8272#L420-8 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 8244#L430-8 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 8292#L431-8 activate_threads_#t~ret14 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 8395#L879-24 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 8417#L879-26 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 8423#L438-24 assume 1 == ~t6_pc~0; 8471#L439-8 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6 := 1; 8472#L449-8 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 8467#L450-8 activate_threads_#t~ret15 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 8468#L887-24 assume 0 != activate_threads_~tmp___5~0;~t6_st~0 := 0; 8572#L887-26 assume !(1 == ~M_E~0); 8070#L752-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 8071#L757-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 8377#L762-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 8378#L767-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 8267#L772-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 8268#L777-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 8512#L782-3 assume 1 == ~E_M~0;~E_M~0 := 2; 8146#L787-3 assume !(1 == ~E_1~0); 8147#L792-3 assume 1 == ~E_2~0;~E_2~0 := 2; 8011#L797-3 assume 1 == ~E_3~0;~E_3~0 := 2; 8012#L802-3 assume 1 == ~E_4~0;~E_4~0 := 2; 8064#L807-3 assume 1 == ~E_5~0;~E_5~0 := 2; 8065#L812-3 assume 1 == ~E_6~0;~E_6~0 := 2; 8373#L817-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~7;havoc exists_runnable_thread_~__retres1~7; 8252#L508-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7 := 1; 8058#L545-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~7; 8138#L546-1 start_simulation_#t~ret17 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret17;havoc start_simulation_#t~ret17; 8167#L1062 assume !(0 == start_simulation_~tmp~3); 8168#L1062-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret16, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~7;havoc exists_runnable_thread_~__retres1~7; 8170#L508-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7 := 1; 8060#L545-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~7; 8142#L546-2 stop_simulation_#t~ret16 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret16;havoc stop_simulation_#t~ret16; 8016#L1017 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 8017#L1024 stop_simulation_#res := stop_simulation_~__retres2~0; 8288#L1025 start_simulation_#t~ret18 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret18;havoc start_simulation_#t~ret18; 8289#L1075 assume !(0 != start_simulation_~tmp___0~1); 8571#L1043-1 [2018-11-23 14:59:45,252 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 14:59:45,252 INFO L82 PathProgramCache]: Analyzing trace with hash 633867876, now seen corresponding path program 1 times [2018-11-23 14:59:45,252 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 14:59:45,253 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 14:59:45,253 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 14:59:45,253 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 14:59:45,253 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 14:59:45,258 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 14:59:45,291 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 14:59:45,291 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 14:59:45,291 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2018-11-23 14:59:45,291 INFO L799 eck$LassoCheckResult]: stem already infeasible [2018-11-23 14:59:45,292 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 14:59:45,292 INFO L82 PathProgramCache]: Analyzing trace with hash 551788720, now seen corresponding path program 3 times [2018-11-23 14:59:45,292 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 14:59:45,292 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 14:59:45,292 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 14:59:45,293 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 14:59:45,293 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 14:59:45,298 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 14:59:45,337 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 14:59:45,337 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 14:59:45,337 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-23 14:59:45,337 INFO L811 eck$LassoCheckResult]: loop already infeasible [2018-11-23 14:59:45,338 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-23 14:59:45,338 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-23 14:59:45,338 INFO L87 Difference]: Start difference. First operand 660 states and 993 transitions. cyclomatic complexity: 334 Second operand 3 states. [2018-11-23 14:59:45,354 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 14:59:45,354 INFO L93 Difference]: Finished difference Result 660 states and 988 transitions. [2018-11-23 14:59:45,354 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-23 14:59:45,355 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 660 states and 988 transitions. [2018-11-23 14:59:45,357 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 573 [2018-11-23 14:59:45,360 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 660 states to 660 states and 988 transitions. [2018-11-23 14:59:45,360 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 660 [2018-11-23 14:59:45,360 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 660 [2018-11-23 14:59:45,361 INFO L73 IsDeterministic]: Start isDeterministic. Operand 660 states and 988 transitions. [2018-11-23 14:59:45,362 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-23 14:59:45,362 INFO L705 BuchiCegarLoop]: Abstraction has 660 states and 988 transitions. [2018-11-23 14:59:45,363 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 660 states and 988 transitions. [2018-11-23 14:59:45,369 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 660 to 660. [2018-11-23 14:59:45,369 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 660 states. [2018-11-23 14:59:45,370 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 660 states to 660 states and 988 transitions. [2018-11-23 14:59:45,370 INFO L728 BuchiCegarLoop]: Abstraction has 660 states and 988 transitions. [2018-11-23 14:59:45,371 INFO L608 BuchiCegarLoop]: Abstraction has 660 states and 988 transitions. [2018-11-23 14:59:45,371 INFO L442 BuchiCegarLoop]: ======== Iteration 8============ [2018-11-23 14:59:45,371 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 660 states and 988 transitions. [2018-11-23 14:59:45,373 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 573 [2018-11-23 14:59:45,373 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-23 14:59:45,373 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-23 14:59:45,374 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 14:59:45,374 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 14:59:45,374 INFO L794 eck$LassoCheckResult]: Stem: 9860#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0; 9752#L-1 havoc main_#res;havoc main_~__retres1~8;havoc main_~__retres1~8;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 9345#L1006 havoc start_simulation_#t~ret17, start_simulation_#t~ret18, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 9346#L458 assume 1 == ~m_i~0;~m_st~0 := 0; 9695#L465-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 9696#L470-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 9580#L475-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 9581#L480-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 9625#L485-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 9439#L490-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 9440#L495-1 assume !(0 == ~M_E~0); 9707#L674-1 assume !(0 == ~T1_E~0); 9708#L679-1 assume !(0 == ~T2_E~0); 9596#L684-1 assume !(0 == ~T3_E~0); 9597#L689-1 assume !(0 == ~T4_E~0); 9840#L694-1 assume !(0 == ~T5_E~0); 9475#L699-1 assume !(0 == ~T6_E~0); 9476#L704-1 assume !(0 == ~E_M~0); 9301#L709-1 assume !(0 == ~E_1~0); 9302#L714-1 assume !(0 == ~E_2~0); 9393#L719-1 assume 0 == ~E_3~0;~E_3~0 := 1; 9394#L724-1 assume !(0 == ~E_4~0); 9701#L729-1 assume !(0 == ~E_5~0); 9702#L734-1 assume !(0 == ~E_6~0); 9590#L739-1 havoc activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 9498#L324 assume !(1 == ~m_pc~0); 9448#L324-2 is_master_triggered_~__retres1~0 := 0; 9447#L335 is_master_triggered_#res := is_master_triggered_~__retres1~0; 9444#L336 activate_threads_#t~ret9 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 9445#L839 assume !(0 != activate_threads_~tmp~1); 9714#L839-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 9535#L343 assume 1 == ~t1_pc~0; 9536#L344 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 9530#L354 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 9531#L355 activate_threads_#t~ret10 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 9670#L847 assume !(0 != activate_threads_~tmp___0~0); 9883#L847-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 9821#L362 assume 1 == ~t2_pc~0; 9822#L363 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 9767#L373 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 9817#L374 activate_threads_#t~ret11 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 9878#L855 assume !(0 != activate_threads_~tmp___1~0); 9889#L855-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 9894#L381 assume !(1 == ~t3_pc~0); 9929#L381-2 is_transmit3_triggered_~__retres1~3 := 0; 9926#L392 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 9927#L393 activate_threads_#t~ret12 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 9358#L863 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 9328#L863-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 9329#L400 assume 1 == ~t4_pc~0; 9389#L401 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 9373#L411 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 9388#L412 activate_threads_#t~ret13 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 9511#L871 assume !(0 != activate_threads_~tmp___3~0); 9605#L871-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 9609#L419 assume !(1 == ~t5_pc~0); 9518#L419-2 is_transmit5_triggered_~__retres1~5 := 0; 9519#L430 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 9582#L431 activate_threads_#t~ret14 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 9583#L879 assume !(0 != activate_threads_~tmp___4~0); 9832#L879-2 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 9833#L438 assume 1 == ~t6_pc~0; 9806#L439 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6 := 1; 9807#L449 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 9804#L450 activate_threads_#t~ret15 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 9805#L887 assume !(0 != activate_threads_~tmp___5~0); 9942#L887-2 assume !(1 == ~M_E~0); 9406#L752-1 assume !(1 == ~T1_E~0); 9407#L757-1 assume !(1 == ~T2_E~0); 9698#L762-1 assume !(1 == ~T3_E~0); 9699#L767-1 assume !(1 == ~T4_E~0); 9588#L772-1 assume !(1 == ~T5_E~0); 9589#L777-1 assume 1 == ~T6_E~0;~T6_E~0 := 2; 9838#L782-1 assume !(1 == ~E_M~0); 9470#L787-1 assume !(1 == ~E_1~0); 9471#L792-1 assume !(1 == ~E_2~0); 9330#L797-1 assume !(1 == ~E_3~0); 9331#L802-1 assume !(1 == ~E_4~0); 9404#L807-1 assume !(1 == ~E_5~0); 9405#L812-1 assume !(1 == ~E_6~0); 9898#L1043-1 [2018-11-23 14:59:45,375 INFO L796 eck$LassoCheckResult]: Loop: 9898#L1043-1 assume !false; 9836#L1044 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret1, eval_#t~nondet2, eval_~tmp_ndt_1~0, eval_#t~nondet3, eval_~tmp_ndt_2~0, eval_#t~nondet4, eval_~tmp_ndt_3~0, eval_#t~nondet5, eval_~tmp_ndt_4~0, eval_#t~nondet6, eval_~tmp_ndt_5~0, eval_#t~nondet7, eval_~tmp_ndt_6~0, eval_#t~nondet8, eval_~tmp_ndt_7~0, eval_~tmp~0;havoc eval_~tmp~0; 9691#L649 assume !false; 9457#L556 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~7;havoc exists_runnable_thread_~__retres1~7; 9458#L508 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7 := 1; 9383#L545 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~7; 9462#L546 eval_#t~ret1 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret1;havoc eval_#t~ret1; 9829#L560 assume !(0 != eval_~tmp~0); 9395#L664 start_simulation_~kernel_st~0 := 2; 9396#L458-1 start_simulation_~kernel_st~0 := 3; 9712#L674-2 assume 0 == ~M_E~0;~M_E~0 := 1; 9684#L674-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 9685#L679-3 assume !(0 == ~T2_E~0); 9567#L684-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 9568#L689-3 assume !(0 == ~T4_E~0); 9626#L694-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 9453#L699-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 9454#L704-3 assume 0 == ~E_M~0;~E_M~0 := 1; 9316#L709-3 assume 0 == ~E_1~0;~E_1~0 := 1; 9317#L714-3 assume 0 == ~E_2~0;~E_2~0 := 1; 9399#L719-3 assume 0 == ~E_3~0;~E_3~0 := 1; 9400#L724-3 assume 0 == ~E_4~0;~E_4~0 := 1; 9710#L729-3 assume !(0 == ~E_5~0); 9711#L734-3 assume 0 == ~E_6~0;~E_6~0 := 1; 9600#L739-3 havoc activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 9459#L324-24 assume !(1 == ~m_pc~0); 9460#L324-26 is_master_triggered_~__retres1~0 := 0; 9466#L335-8 is_master_triggered_#res := is_master_triggered_~__retres1~0; 9490#L336-8 activate_threads_#t~ret9 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 9667#L839-24 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 9627#L839-26 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 9628#L343-24 assume 1 == ~t1_pc~0; 9659#L344-8 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 9660#L354-8 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 9656#L355-8 activate_threads_#t~ret10 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 9657#L847-24 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 9855#L847-26 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 9856#L362-24 assume 1 == ~t2_pc~0; 9848#L363-8 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 9740#L373-8 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 9741#L374-8 activate_threads_#t~ret11 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 9847#L855-24 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 9943#L855-26 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 9944#L381-24 assume !(1 == ~t3_pc~0); 9952#L381-26 is_transmit3_triggered_~__retres1~3 := 0; 9920#L392-8 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 9921#L393-8 activate_threads_#t~ret12 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 9491#L863-24 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 9492#L863-26 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 9307#L400-24 assume !(1 == ~t4_pc~0); 9308#L400-26 is_transmit4_triggered_~__retres1~4 := 0; 9321#L411-8 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 9362#L412-8 activate_threads_#t~ret13 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 9485#L871-24 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 9715#L871-26 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 9598#L419-24 assume !(1 == ~t5_pc~0); 9570#L419-26 is_transmit5_triggered_~__retres1~5 := 0; 9571#L430-8 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 9619#L431-8 activate_threads_#t~ret14 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 9722#L879-24 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 9744#L879-26 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 9750#L438-24 assume 1 == ~t6_pc~0; 9798#L439-8 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6 := 1; 9799#L449-8 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 9794#L450-8 activate_threads_#t~ret15 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 9795#L887-24 assume 0 != activate_threads_~tmp___5~0;~t6_st~0 := 0; 9899#L887-26 assume !(1 == ~M_E~0); 9397#L752-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 9398#L757-3 assume !(1 == ~T2_E~0); 9704#L762-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 9705#L767-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 9594#L772-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 9595#L777-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 9839#L782-3 assume 1 == ~E_M~0;~E_M~0 := 2; 9473#L787-3 assume !(1 == ~E_1~0); 9474#L792-3 assume 1 == ~E_2~0;~E_2~0 := 2; 9338#L797-3 assume 1 == ~E_3~0;~E_3~0 := 2; 9339#L802-3 assume 1 == ~E_4~0;~E_4~0 := 2; 9391#L807-3 assume 1 == ~E_5~0;~E_5~0 := 2; 9392#L812-3 assume 1 == ~E_6~0;~E_6~0 := 2; 9700#L817-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~7;havoc exists_runnable_thread_~__retres1~7; 9579#L508-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7 := 1; 9385#L545-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~7; 9465#L546-1 start_simulation_#t~ret17 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret17;havoc start_simulation_#t~ret17; 9494#L1062 assume !(0 == start_simulation_~tmp~3); 9495#L1062-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret16, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~7;havoc exists_runnable_thread_~__retres1~7; 9497#L508-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7 := 1; 9387#L545-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~7; 9469#L546-2 stop_simulation_#t~ret16 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret16;havoc stop_simulation_#t~ret16; 9340#L1017 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 9341#L1024 stop_simulation_#res := stop_simulation_~__retres2~0; 9615#L1025 start_simulation_#t~ret18 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret18;havoc start_simulation_#t~ret18; 9616#L1075 assume !(0 != start_simulation_~tmp___0~1); 9898#L1043-1 [2018-11-23 14:59:45,375 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 14:59:45,375 INFO L82 PathProgramCache]: Analyzing trace with hash 1587808034, now seen corresponding path program 1 times [2018-11-23 14:59:45,375 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 14:59:45,375 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 14:59:45,376 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 14:59:45,376 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-23 14:59:45,376 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 14:59:45,379 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 14:59:45,407 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 14:59:45,408 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 14:59:45,408 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2018-11-23 14:59:45,408 INFO L799 eck$LassoCheckResult]: stem already infeasible [2018-11-23 14:59:45,408 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 14:59:45,408 INFO L82 PathProgramCache]: Analyzing trace with hash -1572517134, now seen corresponding path program 1 times [2018-11-23 14:59:45,408 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 14:59:45,408 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 14:59:45,409 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 14:59:45,409 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 14:59:45,409 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 14:59:45,415 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 14:59:45,434 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 14:59:45,434 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 14:59:45,435 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-23 14:59:45,435 INFO L811 eck$LassoCheckResult]: loop already infeasible [2018-11-23 14:59:45,435 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-23 14:59:45,435 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-23 14:59:45,435 INFO L87 Difference]: Start difference. First operand 660 states and 988 transitions. cyclomatic complexity: 329 Second operand 3 states. [2018-11-23 14:59:45,502 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 14:59:45,502 INFO L93 Difference]: Finished difference Result 660 states and 974 transitions. [2018-11-23 14:59:45,502 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-23 14:59:45,502 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 660 states and 974 transitions. [2018-11-23 14:59:45,505 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 573 [2018-11-23 14:59:45,507 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 660 states to 660 states and 974 transitions. [2018-11-23 14:59:45,508 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 660 [2018-11-23 14:59:45,508 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 660 [2018-11-23 14:59:45,508 INFO L73 IsDeterministic]: Start isDeterministic. Operand 660 states and 974 transitions. [2018-11-23 14:59:45,509 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-23 14:59:45,509 INFO L705 BuchiCegarLoop]: Abstraction has 660 states and 974 transitions. [2018-11-23 14:59:45,510 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 660 states and 974 transitions. [2018-11-23 14:59:45,516 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 660 to 660. [2018-11-23 14:59:45,516 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 660 states. [2018-11-23 14:59:45,517 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 660 states to 660 states and 974 transitions. [2018-11-23 14:59:45,517 INFO L728 BuchiCegarLoop]: Abstraction has 660 states and 974 transitions. [2018-11-23 14:59:45,517 INFO L608 BuchiCegarLoop]: Abstraction has 660 states and 974 transitions. [2018-11-23 14:59:45,517 INFO L442 BuchiCegarLoop]: ======== Iteration 9============ [2018-11-23 14:59:45,518 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 660 states and 974 transitions. [2018-11-23 14:59:45,519 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 573 [2018-11-23 14:59:45,520 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-23 14:59:45,520 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-23 14:59:45,521 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 14:59:45,521 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 14:59:45,521 INFO L794 eck$LassoCheckResult]: Stem: 11188#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0; 11082#L-1 havoc main_#res;havoc main_~__retres1~8;havoc main_~__retres1~8;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 10672#L1006 havoc start_simulation_#t~ret17, start_simulation_#t~ret18, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 10673#L458 assume 1 == ~m_i~0;~m_st~0 := 0; 11022#L465-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 11023#L470-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 10907#L475-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 10908#L480-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 10952#L485-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 10766#L490-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 10767#L495-1 assume !(0 == ~M_E~0); 11034#L674-1 assume !(0 == ~T1_E~0); 11035#L679-1 assume !(0 == ~T2_E~0); 10925#L684-1 assume !(0 == ~T3_E~0); 10926#L689-1 assume !(0 == ~T4_E~0); 11167#L694-1 assume !(0 == ~T5_E~0); 10802#L699-1 assume !(0 == ~T6_E~0); 10803#L704-1 assume !(0 == ~E_M~0); 10628#L709-1 assume !(0 == ~E_1~0); 10629#L714-1 assume !(0 == ~E_2~0); 10720#L719-1 assume !(0 == ~E_3~0); 10721#L724-1 assume !(0 == ~E_4~0); 11028#L729-1 assume !(0 == ~E_5~0); 11029#L734-1 assume !(0 == ~E_6~0); 10918#L739-1 havoc activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 10825#L324 assume !(1 == ~m_pc~0); 10775#L324-2 is_master_triggered_~__retres1~0 := 0; 10774#L335 is_master_triggered_#res := is_master_triggered_~__retres1~0; 10771#L336 activate_threads_#t~ret9 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 10772#L839 assume !(0 != activate_threads_~tmp~1); 11041#L839-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 10862#L343 assume 1 == ~t1_pc~0; 10863#L344 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 10860#L354 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 10861#L355 activate_threads_#t~ret10 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 10997#L847 assume !(0 != activate_threads_~tmp___0~0); 11210#L847-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 11148#L362 assume 1 == ~t2_pc~0; 11149#L363 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 11094#L373 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 11147#L374 activate_threads_#t~ret11 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 11205#L855 assume !(0 != activate_threads_~tmp___1~0); 11216#L855-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 11221#L381 assume !(1 == ~t3_pc~0); 11256#L381-2 is_transmit3_triggered_~__retres1~3 := 0; 11254#L392 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 11255#L393 activate_threads_#t~ret12 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 10686#L863 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 10655#L863-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 10656#L400 assume 1 == ~t4_pc~0; 10716#L401 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 10700#L411 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 10715#L412 activate_threads_#t~ret13 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 10838#L871 assume !(0 != activate_threads_~tmp___3~0); 10932#L871-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 10936#L419 assume !(1 == ~t5_pc~0); 10845#L419-2 is_transmit5_triggered_~__retres1~5 := 0; 10846#L430 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 10909#L431 activate_threads_#t~ret14 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 10910#L879 assume !(0 != activate_threads_~tmp___4~0); 11159#L879-2 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 11160#L438 assume 1 == ~t6_pc~0; 11133#L439 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6 := 1; 11134#L449 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 11131#L450 activate_threads_#t~ret15 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 11132#L887 assume !(0 != activate_threads_~tmp___5~0); 11269#L887-2 assume !(1 == ~M_E~0); 10733#L752-1 assume !(1 == ~T1_E~0); 10734#L757-1 assume !(1 == ~T2_E~0); 11025#L762-1 assume !(1 == ~T3_E~0); 11026#L767-1 assume !(1 == ~T4_E~0); 10915#L772-1 assume !(1 == ~T5_E~0); 10916#L777-1 assume 1 == ~T6_E~0;~T6_E~0 := 2; 11165#L782-1 assume !(1 == ~E_M~0); 10797#L787-1 assume !(1 == ~E_1~0); 10798#L792-1 assume !(1 == ~E_2~0); 10660#L797-1 assume !(1 == ~E_3~0); 10661#L802-1 assume !(1 == ~E_4~0); 10731#L807-1 assume !(1 == ~E_5~0); 10732#L812-1 assume !(1 == ~E_6~0); 11225#L1043-1 [2018-11-23 14:59:45,521 INFO L796 eck$LassoCheckResult]: Loop: 11225#L1043-1 assume !false; 11163#L1044 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret1, eval_#t~nondet2, eval_~tmp_ndt_1~0, eval_#t~nondet3, eval_~tmp_ndt_2~0, eval_#t~nondet4, eval_~tmp_ndt_3~0, eval_#t~nondet5, eval_~tmp_ndt_4~0, eval_#t~nondet6, eval_~tmp_ndt_5~0, eval_#t~nondet7, eval_~tmp_ndt_6~0, eval_#t~nondet8, eval_~tmp_ndt_7~0, eval_~tmp~0;havoc eval_~tmp~0; 11018#L649 assume !false; 10784#L556 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~7;havoc exists_runnable_thread_~__retres1~7; 10785#L508 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7 := 1; 10710#L545 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~7; 10789#L546 eval_#t~ret1 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret1;havoc eval_#t~ret1; 11156#L560 assume !(0 != eval_~tmp~0); 10722#L664 start_simulation_~kernel_st~0 := 2; 10723#L458-1 start_simulation_~kernel_st~0 := 3; 11039#L674-2 assume 0 == ~M_E~0;~M_E~0 := 1; 11011#L674-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 11012#L679-3 assume !(0 == ~T2_E~0); 10896#L684-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 10897#L689-3 assume !(0 == ~T4_E~0); 10953#L694-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 10780#L699-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 10781#L704-3 assume 0 == ~E_M~0;~E_M~0 := 1; 10643#L709-3 assume 0 == ~E_1~0;~E_1~0 := 1; 10644#L714-3 assume 0 == ~E_2~0;~E_2~0 := 1; 10726#L719-3 assume !(0 == ~E_3~0); 10727#L724-3 assume 0 == ~E_4~0;~E_4~0 := 1; 11037#L729-3 assume !(0 == ~E_5~0); 11038#L734-3 assume 0 == ~E_6~0;~E_6~0 := 1; 10927#L739-3 havoc activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 10786#L324-24 assume !(1 == ~m_pc~0); 10787#L324-26 is_master_triggered_~__retres1~0 := 0; 10793#L335-8 is_master_triggered_#res := is_master_triggered_~__retres1~0; 10819#L336-8 activate_threads_#t~ret9 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 10991#L839-24 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 10954#L839-26 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 10955#L343-24 assume 1 == ~t1_pc~0; 10985#L344-8 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 10986#L354-8 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 10983#L355-8 activate_threads_#t~ret10 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 10984#L847-24 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 11182#L847-26 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 11183#L362-24 assume 1 == ~t2_pc~0; 11175#L363-8 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 11066#L373-8 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 11067#L374-8 activate_threads_#t~ret11 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 11174#L855-24 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 11270#L855-26 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 11271#L381-24 assume !(1 == ~t3_pc~0); 11279#L381-26 is_transmit3_triggered_~__retres1~3 := 0; 11247#L392-8 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 11248#L393-8 activate_threads_#t~ret12 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 10817#L863-24 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 10818#L863-26 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 10634#L400-24 assume !(1 == ~t4_pc~0); 10635#L400-26 is_transmit4_triggered_~__retres1~4 := 0; 10648#L411-8 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 10689#L412-8 activate_threads_#t~ret13 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 10812#L871-24 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 11042#L871-26 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 10923#L419-24 assume 1 == ~t5_pc~0; 10924#L420-8 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 10895#L430-8 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 10946#L431-8 activate_threads_#t~ret14 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 11049#L879-24 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 11070#L879-26 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 11077#L438-24 assume 1 == ~t6_pc~0; 11125#L439-8 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6 := 1; 11126#L449-8 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 11121#L450-8 activate_threads_#t~ret15 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 11122#L887-24 assume 0 != activate_threads_~tmp___5~0;~t6_st~0 := 0; 11226#L887-26 assume !(1 == ~M_E~0); 10724#L752-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 10725#L757-3 assume !(1 == ~T2_E~0); 11031#L762-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 11032#L767-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 10921#L772-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 10922#L777-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 11166#L782-3 assume 1 == ~E_M~0;~E_M~0 := 2; 10800#L787-3 assume !(1 == ~E_1~0); 10801#L792-3 assume 1 == ~E_2~0;~E_2~0 := 2; 10665#L797-3 assume !(1 == ~E_3~0); 10666#L802-3 assume 1 == ~E_4~0;~E_4~0 := 2; 10718#L807-3 assume 1 == ~E_5~0;~E_5~0 := 2; 10719#L812-3 assume 1 == ~E_6~0;~E_6~0 := 2; 11027#L817-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~7;havoc exists_runnable_thread_~__retres1~7; 10906#L508-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7 := 1; 10712#L545-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~7; 10790#L546-1 start_simulation_#t~ret17 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret17;havoc start_simulation_#t~ret17; 10821#L1062 assume !(0 == start_simulation_~tmp~3); 10822#L1062-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret16, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~7;havoc exists_runnable_thread_~__retres1~7; 10824#L508-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7 := 1; 10714#L545-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~7; 10796#L546-2 stop_simulation_#t~ret16 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret16;havoc stop_simulation_#t~ret16; 10670#L1017 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 10671#L1024 stop_simulation_#res := stop_simulation_~__retres2~0; 10942#L1025 start_simulation_#t~ret18 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret18;havoc start_simulation_#t~ret18; 10943#L1075 assume !(0 != start_simulation_~tmp___0~1); 11225#L1043-1 [2018-11-23 14:59:45,521 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 14:59:45,521 INFO L82 PathProgramCache]: Analyzing trace with hash 1789631968, now seen corresponding path program 1 times [2018-11-23 14:59:45,522 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 14:59:45,522 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 14:59:45,522 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 14:59:45,522 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 14:59:45,522 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 14:59:45,526 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 14:59:45,551 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 14:59:45,551 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 14:59:45,551 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2018-11-23 14:59:45,552 INFO L799 eck$LassoCheckResult]: stem already infeasible [2018-11-23 14:59:45,552 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 14:59:45,552 INFO L82 PathProgramCache]: Analyzing trace with hash -1300260969, now seen corresponding path program 1 times [2018-11-23 14:59:45,552 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 14:59:45,552 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 14:59:45,553 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 14:59:45,553 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 14:59:45,553 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 14:59:45,557 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 14:59:45,573 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 14:59:45,573 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 14:59:45,573 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-23 14:59:45,573 INFO L811 eck$LassoCheckResult]: loop already infeasible [2018-11-23 14:59:45,574 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-23 14:59:45,574 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-23 14:59:45,574 INFO L87 Difference]: Start difference. First operand 660 states and 974 transitions. cyclomatic complexity: 315 Second operand 3 states. [2018-11-23 14:59:45,690 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 14:59:45,691 INFO L93 Difference]: Finished difference Result 1174 states and 1718 transitions. [2018-11-23 14:59:45,692 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-23 14:59:45,692 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1174 states and 1718 transitions. [2018-11-23 14:59:45,697 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 1086 [2018-11-23 14:59:45,702 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1174 states to 1174 states and 1718 transitions. [2018-11-23 14:59:45,702 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1174 [2018-11-23 14:59:45,703 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1174 [2018-11-23 14:59:45,703 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1174 states and 1718 transitions. [2018-11-23 14:59:45,704 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-23 14:59:45,705 INFO L705 BuchiCegarLoop]: Abstraction has 1174 states and 1718 transitions. [2018-11-23 14:59:45,706 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1174 states and 1718 transitions. [2018-11-23 14:59:45,717 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1174 to 1172. [2018-11-23 14:59:45,717 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1172 states. [2018-11-23 14:59:45,719 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1172 states to 1172 states and 1716 transitions. [2018-11-23 14:59:45,720 INFO L728 BuchiCegarLoop]: Abstraction has 1172 states and 1716 transitions. [2018-11-23 14:59:45,720 INFO L608 BuchiCegarLoop]: Abstraction has 1172 states and 1716 transitions. [2018-11-23 14:59:45,720 INFO L442 BuchiCegarLoop]: ======== Iteration 10============ [2018-11-23 14:59:45,720 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1172 states and 1716 transitions. [2018-11-23 14:59:45,723 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 1084 [2018-11-23 14:59:45,724 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-23 14:59:45,724 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-23 14:59:45,725 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 14:59:45,725 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 14:59:45,725 INFO L794 eck$LassoCheckResult]: Stem: 13050#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0; 12940#L-1 havoc main_#res;havoc main_~__retres1~8;havoc main_~__retres1~8;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 12513#L1006 havoc start_simulation_#t~ret17, start_simulation_#t~ret18, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 12514#L458 assume 1 == ~m_i~0;~m_st~0 := 0; 12866#L465-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 12867#L470-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 12749#L475-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 12750#L480-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 12793#L485-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 12607#L490-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 12608#L495-1 assume !(0 == ~M_E~0); 12882#L674-1 assume !(0 == ~T1_E~0); 12883#L679-1 assume !(0 == ~T2_E~0); 12765#L684-1 assume !(0 == ~T3_E~0); 12766#L689-1 assume !(0 == ~T4_E~0); 13030#L694-1 assume !(0 == ~T5_E~0); 12643#L699-1 assume !(0 == ~T6_E~0); 12644#L704-1 assume !(0 == ~E_M~0); 12469#L709-1 assume !(0 == ~E_1~0); 12470#L714-1 assume !(0 == ~E_2~0); 12561#L719-1 assume !(0 == ~E_3~0); 12562#L724-1 assume !(0 == ~E_4~0); 12875#L729-1 assume !(0 == ~E_5~0); 12876#L734-1 assume !(0 == ~E_6~0); 12759#L739-1 havoc activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 12667#L324 assume !(1 == ~m_pc~0); 12616#L324-2 is_master_triggered_~__retres1~0 := 0; 12615#L335 is_master_triggered_#res := is_master_triggered_~__retres1~0; 12612#L336 activate_threads_#t~ret9 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 12613#L839 assume !(0 != activate_threads_~tmp~1); 12895#L839-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 12705#L343 assume !(1 == ~t1_pc~0); 12706#L343-2 is_transmit1_triggered_~__retres1~1 := 0; 12700#L354 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 12701#L355 activate_threads_#t~ret10 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 12838#L847 assume !(0 != activate_threads_~tmp___0~0); 13073#L847-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 13010#L362 assume 1 == ~t2_pc~0; 13011#L363 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 12955#L373 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 13006#L374 activate_threads_#t~ret11 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 13068#L855 assume !(0 != activate_threads_~tmp___1~0); 13079#L855-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 13084#L381 assume !(1 == ~t3_pc~0); 13120#L381-2 is_transmit3_triggered_~__retres1~3 := 0; 13116#L392 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 13117#L393 activate_threads_#t~ret12 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 12526#L863 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 12496#L863-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 12497#L400 assume 1 == ~t4_pc~0; 12557#L401 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 12541#L411 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 12556#L412 activate_threads_#t~ret13 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 12680#L871 assume !(0 != activate_threads_~tmp___3~0); 12774#L871-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 12778#L419 assume !(1 == ~t5_pc~0); 12687#L419-2 is_transmit5_triggered_~__retres1~5 := 0; 12688#L430 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 12751#L431 activate_threads_#t~ret14 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 12752#L879 assume !(0 != activate_threads_~tmp___4~0); 13022#L879-2 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 13023#L438 assume 1 == ~t6_pc~0; 12995#L439 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6 := 1; 12996#L449 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 12993#L450 activate_threads_#t~ret15 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 12994#L887 assume !(0 != activate_threads_~tmp___5~0); 13134#L887-2 assume !(1 == ~M_E~0); 12574#L752-1 assume !(1 == ~T1_E~0); 12575#L757-1 assume !(1 == ~T2_E~0); 12870#L762-1 assume !(1 == ~T3_E~0); 12871#L767-1 assume !(1 == ~T4_E~0); 12757#L772-1 assume !(1 == ~T5_E~0); 12758#L777-1 assume 1 == ~T6_E~0;~T6_E~0 := 2; 13028#L782-1 assume !(1 == ~E_M~0); 12638#L787-1 assume !(1 == ~E_1~0); 12639#L792-1 assume !(1 == ~E_2~0); 12498#L797-1 assume !(1 == ~E_3~0); 12499#L802-1 assume !(1 == ~E_4~0); 12572#L807-1 assume !(1 == ~E_5~0); 12573#L812-1 assume !(1 == ~E_6~0); 13088#L1043-1 [2018-11-23 14:59:45,725 INFO L796 eck$LassoCheckResult]: Loop: 13088#L1043-1 assume !false; 13026#L1044 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret1, eval_#t~nondet2, eval_~tmp_ndt_1~0, eval_#t~nondet3, eval_~tmp_ndt_2~0, eval_#t~nondet4, eval_~tmp_ndt_3~0, eval_#t~nondet5, eval_~tmp_ndt_4~0, eval_#t~nondet6, eval_~tmp_ndt_5~0, eval_#t~nondet7, eval_~tmp_ndt_6~0, eval_#t~nondet8, eval_~tmp_ndt_7~0, eval_~tmp~0;havoc eval_~tmp~0; 12861#L649 assume !false; 12625#L556 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~7;havoc exists_runnable_thread_~__retres1~7; 12626#L508 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7 := 1; 12551#L545 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~7; 12630#L546 eval_#t~ret1 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret1;havoc eval_#t~ret1; 13018#L560 assume !(0 != eval_~tmp~0); 13020#L664 start_simulation_~kernel_st~0 := 2; 13346#L458-1 start_simulation_~kernel_st~0 := 3; 13344#L674-2 assume 0 == ~M_E~0;~M_E~0 := 1; 13342#L674-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 13340#L679-3 assume !(0 == ~T2_E~0); 13338#L684-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 13337#L689-3 assume !(0 == ~T4_E~0); 13303#L694-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 13296#L699-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 13292#L704-3 assume 0 == ~E_M~0;~E_M~0 := 1; 13287#L709-3 assume 0 == ~E_1~0;~E_1~0 := 1; 13281#L714-3 assume 0 == ~E_2~0;~E_2~0 := 1; 13275#L719-3 assume !(0 == ~E_3~0); 13269#L724-3 assume 0 == ~E_4~0;~E_4~0 := 1; 13264#L729-3 assume !(0 == ~E_5~0); 13212#L734-3 assume 0 == ~E_6~0;~E_6~0 := 1; 13198#L739-3 havoc activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 13193#L324-24 assume 1 == ~m_pc~0; 13181#L325-8 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 13176#L335-8 is_master_triggered_#res := is_master_triggered_~__retres1~0; 13172#L336-8 activate_threads_#t~ret9 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 13168#L839-24 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 13162#L839-26 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 12889#L343-24 assume !(1 == ~t1_pc~0); 12890#L343-26 is_transmit1_triggered_~__retres1~1 := 0; 13579#L354-8 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 13578#L355-8 activate_threads_#t~ret10 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 13576#L847-24 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 13569#L847-26 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 13568#L362-24 assume !(1 == ~t2_pc~0); 13566#L362-26 is_transmit2_triggered_~__retres1~2 := 0; 13565#L373-8 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 13564#L374-8 activate_threads_#t~ret11 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 13563#L855-24 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 13562#L855-26 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 13561#L381-24 assume !(1 == ~t3_pc~0); 13559#L381-26 is_transmit3_triggered_~__retres1~3 := 0; 13558#L392-8 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 13557#L393-8 activate_threads_#t~ret12 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 13556#L863-24 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 13555#L863-26 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 13554#L400-24 assume !(1 == ~t4_pc~0); 13552#L400-26 is_transmit4_triggered_~__retres1~4 := 0; 13551#L411-8 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 13550#L412-8 activate_threads_#t~ret13 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 12911#L871-24 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 12900#L871-26 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 12767#L419-24 assume 1 == ~t5_pc~0; 12768#L420-8 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 12740#L430-8 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 12787#L431-8 activate_threads_#t~ret14 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 12909#L879-24 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 12932#L879-26 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 12938#L438-24 assume 1 == ~t6_pc~0; 12987#L439-8 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6 := 1; 12988#L449-8 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 12983#L450-8 activate_threads_#t~ret15 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 12984#L887-24 assume 0 != activate_threads_~tmp___5~0;~t6_st~0 := 0; 13089#L887-26 assume !(1 == ~M_E~0); 12565#L752-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 12566#L757-3 assume !(1 == ~T2_E~0); 12879#L762-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 12880#L767-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 12762#L772-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 12763#L777-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 13029#L782-3 assume 1 == ~E_M~0;~E_M~0 := 2; 12641#L787-3 assume !(1 == ~E_1~0); 12642#L792-3 assume 1 == ~E_2~0;~E_2~0 := 2; 12505#L797-3 assume !(1 == ~E_3~0); 12506#L802-3 assume 1 == ~E_4~0;~E_4~0 := 2; 12559#L807-3 assume 1 == ~E_5~0;~E_5~0 := 2; 12560#L812-3 assume 1 == ~E_6~0;~E_6~0 := 2; 12872#L817-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~7;havoc exists_runnable_thread_~__retres1~7; 12748#L508-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7 := 1; 12553#L545-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~7; 12631#L546-1 start_simulation_#t~ret17 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret17;havoc start_simulation_#t~ret17; 12663#L1062 assume !(0 == start_simulation_~tmp~3); 12664#L1062-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret16, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~7;havoc exists_runnable_thread_~__retres1~7; 12666#L508-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7 := 1; 12555#L545-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~7; 12635#L546-2 stop_simulation_#t~ret16 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret16;havoc stop_simulation_#t~ret16; 12508#L1017 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 12509#L1024 stop_simulation_#res := stop_simulation_~__retres2~0; 12783#L1025 start_simulation_#t~ret18 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret18;havoc start_simulation_#t~ret18; 12784#L1075 assume !(0 != start_simulation_~tmp___0~1); 13088#L1043-1 [2018-11-23 14:59:45,725 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 14:59:45,725 INFO L82 PathProgramCache]: Analyzing trace with hash -1037131999, now seen corresponding path program 1 times [2018-11-23 14:59:45,726 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 14:59:45,726 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 14:59:45,726 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 14:59:45,726 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 14:59:45,726 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 14:59:45,730 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 14:59:45,748 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 14:59:45,748 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 14:59:45,748 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2018-11-23 14:59:45,749 INFO L799 eck$LassoCheckResult]: stem already infeasible [2018-11-23 14:59:45,749 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 14:59:45,749 INFO L82 PathProgramCache]: Analyzing trace with hash -1310597514, now seen corresponding path program 1 times [2018-11-23 14:59:45,749 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 14:59:45,749 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 14:59:45,750 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 14:59:45,750 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 14:59:45,750 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 14:59:45,754 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 14:59:45,770 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 14:59:45,770 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 14:59:45,770 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-23 14:59:45,771 INFO L811 eck$LassoCheckResult]: loop already infeasible [2018-11-23 14:59:45,771 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-23 14:59:45,771 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-23 14:59:45,771 INFO L87 Difference]: Start difference. First operand 1172 states and 1716 transitions. cyclomatic complexity: 546 Second operand 3 states. [2018-11-23 14:59:45,828 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 14:59:45,828 INFO L93 Difference]: Finished difference Result 2143 states and 3114 transitions. [2018-11-23 14:59:45,829 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-23 14:59:45,829 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2143 states and 3114 transitions. [2018-11-23 14:59:45,837 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 2050 [2018-11-23 14:59:45,845 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2143 states to 2143 states and 3114 transitions. [2018-11-23 14:59:45,846 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2143 [2018-11-23 14:59:45,847 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2143 [2018-11-23 14:59:45,847 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2143 states and 3114 transitions. [2018-11-23 14:59:45,850 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-23 14:59:45,850 INFO L705 BuchiCegarLoop]: Abstraction has 2143 states and 3114 transitions. [2018-11-23 14:59:45,852 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2143 states and 3114 transitions. [2018-11-23 14:59:45,872 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2143 to 2139. [2018-11-23 14:59:45,872 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2139 states. [2018-11-23 14:59:45,876 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2139 states to 2139 states and 3110 transitions. [2018-11-23 14:59:45,877 INFO L728 BuchiCegarLoop]: Abstraction has 2139 states and 3110 transitions. [2018-11-23 14:59:45,877 INFO L608 BuchiCegarLoop]: Abstraction has 2139 states and 3110 transitions. [2018-11-23 14:59:45,877 INFO L442 BuchiCegarLoop]: ======== Iteration 11============ [2018-11-23 14:59:45,877 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2139 states and 3110 transitions. [2018-11-23 14:59:45,883 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 2046 [2018-11-23 14:59:45,884 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-23 14:59:45,884 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-23 14:59:45,885 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 14:59:45,885 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 14:59:45,885 INFO L794 eck$LassoCheckResult]: Stem: 16379#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0; 16267#L-1 havoc main_#res;havoc main_~__retres1~8;havoc main_~__retres1~8;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 15835#L1006 havoc start_simulation_#t~ret17, start_simulation_#t~ret18, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 15836#L458 assume 1 == ~m_i~0;~m_st~0 := 0; 16194#L465-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 16195#L470-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 16075#L475-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 16076#L480-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 16119#L485-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 15926#L490-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 15927#L495-1 assume !(0 == ~M_E~0); 16210#L674-1 assume !(0 == ~T1_E~0); 16211#L679-1 assume !(0 == ~T2_E~0); 16091#L684-1 assume !(0 == ~T3_E~0); 16092#L689-1 assume !(0 == ~T4_E~0); 16357#L694-1 assume !(0 == ~T5_E~0); 15966#L699-1 assume !(0 == ~T6_E~0); 15967#L704-1 assume !(0 == ~E_M~0); 15791#L709-1 assume !(0 == ~E_1~0); 15792#L714-1 assume !(0 == ~E_2~0); 15883#L719-1 assume !(0 == ~E_3~0); 15884#L724-1 assume !(0 == ~E_4~0); 16203#L729-1 assume !(0 == ~E_5~0); 16204#L734-1 assume !(0 == ~E_6~0); 16085#L739-1 havoc activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 15992#L324 assume !(1 == ~m_pc~0); 15938#L324-2 is_master_triggered_~__retres1~0 := 0; 15937#L335 is_master_triggered_#res := is_master_triggered_~__retres1~0; 15934#L336 activate_threads_#t~ret9 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 15935#L839 assume !(0 != activate_threads_~tmp~1); 16220#L839-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 16031#L343 assume !(1 == ~t1_pc~0); 16032#L343-2 is_transmit1_triggered_~__retres1~1 := 0; 16026#L354 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 16027#L355 activate_threads_#t~ret10 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 16164#L847 assume !(0 != activate_threads_~tmp___0~0); 16411#L847-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 16336#L362 assume !(1 == ~t2_pc~0); 16281#L362-2 is_transmit2_triggered_~__retres1~2 := 0; 16282#L373 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 16332#L374 activate_threads_#t~ret11 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 16401#L855 assume !(0 != activate_threads_~tmp___1~0); 16419#L855-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 16424#L381 assume !(1 == ~t3_pc~0); 16461#L381-2 is_transmit3_triggered_~__retres1~3 := 0; 16458#L392 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 16459#L393 activate_threads_#t~ret12 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 15847#L863 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 15818#L863-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 15819#L400 assume 1 == ~t4_pc~0; 15879#L401 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 15862#L411 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 15878#L412 activate_threads_#t~ret13 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 16007#L871 assume !(0 != activate_threads_~tmp___3~0); 16100#L871-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 16104#L419 assume !(1 == ~t5_pc~0); 16014#L419-2 is_transmit5_triggered_~__retres1~5 := 0; 16015#L430 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 16077#L431 activate_threads_#t~ret14 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 16078#L879 assume !(0 != activate_threads_~tmp___4~0); 16347#L879-2 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 16348#L438 assume 1 == ~t6_pc~0; 16321#L439 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6 := 1; 16322#L449 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 16319#L450 activate_threads_#t~ret15 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 16320#L887 assume !(0 != activate_threads_~tmp___5~0); 16475#L887-2 assume !(1 == ~M_E~0); 15896#L752-1 assume !(1 == ~T1_E~0); 15897#L757-1 assume !(1 == ~T2_E~0); 16198#L762-1 assume !(1 == ~T3_E~0); 16199#L767-1 assume !(1 == ~T4_E~0); 16083#L772-1 assume !(1 == ~T5_E~0); 16084#L777-1 assume 1 == ~T6_E~0;~T6_E~0 := 2; 16355#L782-1 assume !(1 == ~E_M~0); 15961#L787-1 assume !(1 == ~E_1~0); 15962#L792-1 assume !(1 == ~E_2~0); 15820#L797-1 assume !(1 == ~E_3~0); 15821#L802-1 assume !(1 == ~E_4~0); 15894#L807-1 assume !(1 == ~E_5~0); 15895#L812-1 assume !(1 == ~E_6~0); 16428#L1043-1 [2018-11-23 14:59:45,885 INFO L796 eck$LassoCheckResult]: Loop: 16428#L1043-1 assume !false; 16479#L1044 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret1, eval_#t~nondet2, eval_~tmp_ndt_1~0, eval_#t~nondet3, eval_~tmp_ndt_2~0, eval_#t~nondet4, eval_~tmp_ndt_3~0, eval_#t~nondet5, eval_~tmp_ndt_4~0, eval_#t~nondet6, eval_~tmp_ndt_5~0, eval_#t~nondet7, eval_~tmp_ndt_6~0, eval_#t~nondet8, eval_~tmp_ndt_7~0, eval_~tmp~0;havoc eval_~tmp~0; 17639#L649 assume !false; 17472#L556 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~7;havoc exists_runnable_thread_~__retres1~7; 17401#L508 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7 := 1; 17392#L545 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~7; 17386#L546 eval_#t~ret1 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret1;havoc eval_#t~ret1; 17379#L560 assume !(0 != eval_~tmp~0); 15885#L664 start_simulation_~kernel_st~0 := 2; 15886#L458-1 start_simulation_~kernel_st~0 := 3; 17929#L674-2 assume 0 == ~M_E~0;~M_E~0 := 1; 17928#L674-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 17926#L679-3 assume !(0 == ~T2_E~0); 17924#L684-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 17922#L689-3 assume !(0 == ~T4_E~0); 17920#L694-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 17917#L699-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 17737#L704-3 assume 0 == ~E_M~0;~E_M~0 := 1; 15806#L709-3 assume 0 == ~E_1~0;~E_1~0 := 1; 15807#L714-3 assume 0 == ~E_2~0;~E_2~0 := 1; 15889#L719-3 assume !(0 == ~E_3~0); 15890#L724-3 assume 0 == ~E_4~0;~E_4~0 := 1; 16213#L729-3 assume !(0 == ~E_5~0); 16214#L734-3 assume 0 == ~E_6~0;~E_6~0 := 1; 16095#L739-3 havoc activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 15949#L324-24 assume !(1 == ~m_pc~0); 15950#L324-26 is_master_triggered_~__retres1~0 := 0; 15956#L335-8 is_master_triggered_#res := is_master_triggered_~__retres1~0; 15982#L336-8 activate_threads_#t~ret9 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 16158#L839-24 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 16121#L839-26 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 16122#L343-24 assume !(1 == ~t1_pc~0); 16185#L343-26 is_transmit1_triggered_~__retres1~1 := 0; 16186#L354-8 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 16150#L355-8 activate_threads_#t~ret10 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 16151#L847-24 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 16372#L847-26 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 16374#L362-24 assume !(1 == ~t2_pc~0); 16405#L362-26 is_transmit2_triggered_~__retres1~2 := 0; 17767#L373-8 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 17766#L374-8 activate_threads_#t~ret11 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 17765#L855-24 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 17764#L855-26 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 17763#L381-24 assume !(1 == ~t3_pc~0); 17761#L381-26 is_transmit3_triggered_~__retres1~3 := 0; 17760#L392-8 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 17759#L393-8 activate_threads_#t~ret12 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 17758#L863-24 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 17757#L863-26 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 17756#L400-24 assume !(1 == ~t4_pc~0); 17754#L400-26 is_transmit4_triggered_~__retres1~4 := 0; 17753#L411-8 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 17752#L412-8 activate_threads_#t~ret13 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 17751#L871-24 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 17750#L871-26 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 17749#L419-24 assume 1 == ~t5_pc~0; 17747#L420-8 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 17746#L430-8 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 17745#L431-8 activate_threads_#t~ret14 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 17744#L879-24 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 17743#L879-26 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 17742#L438-24 assume !(1 == ~t6_pc~0); 17740#L438-26 is_transmit6_triggered_~__retres1~6 := 0; 17739#L449-8 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 16309#L450-8 activate_threads_#t~ret15 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 16310#L887-24 assume 0 != activate_threads_~tmp___5~0;~t6_st~0 := 0; 16429#L887-26 assume !(1 == ~M_E~0); 15887#L752-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 15888#L757-3 assume !(1 == ~T2_E~0); 16207#L762-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 16208#L767-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 16089#L772-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 16090#L777-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 16356#L782-3 assume 1 == ~E_M~0;~E_M~0 := 2; 15964#L787-3 assume !(1 == ~E_1~0); 15965#L792-3 assume 1 == ~E_2~0;~E_2~0 := 2; 15828#L797-3 assume !(1 == ~E_3~0); 15829#L802-3 assume 1 == ~E_4~0;~E_4~0 := 2; 15881#L807-3 assume 1 == ~E_5~0;~E_5~0 := 2; 15882#L812-3 assume 1 == ~E_6~0;~E_6~0 := 2; 16200#L817-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~7;havoc exists_runnable_thread_~__retres1~7; 16074#L508-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7 := 1; 15875#L545-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~7; 15955#L546-1 start_simulation_#t~ret17 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret17;havoc start_simulation_#t~ret17; 15987#L1062 assume !(0 == start_simulation_~tmp~3); 15988#L1062-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret16, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~7;havoc exists_runnable_thread_~__retres1~7; 17801#L508-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7 := 1; 15959#L545-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~7; 15960#L546-2 stop_simulation_#t~ret16 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret16;havoc stop_simulation_#t~ret16; 15833#L1017 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 15834#L1024 stop_simulation_#res := stop_simulation_~__retres2~0; 16109#L1025 start_simulation_#t~ret18 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret18;havoc start_simulation_#t~ret18; 16110#L1075 assume !(0 != start_simulation_~tmp___0~1); 16428#L1043-1 [2018-11-23 14:59:45,885 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 14:59:45,885 INFO L82 PathProgramCache]: Analyzing trace with hash 861398306, now seen corresponding path program 1 times [2018-11-23 14:59:45,885 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 14:59:45,886 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 14:59:45,886 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 14:59:45,886 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 14:59:45,886 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 14:59:45,890 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 14:59:45,923 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 14:59:45,924 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 14:59:45,924 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2018-11-23 14:59:45,924 INFO L799 eck$LassoCheckResult]: stem already infeasible [2018-11-23 14:59:45,924 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 14:59:45,924 INFO L82 PathProgramCache]: Analyzing trace with hash 1446190132, now seen corresponding path program 1 times [2018-11-23 14:59:45,924 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 14:59:45,924 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 14:59:45,932 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 14:59:45,932 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 14:59:45,932 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 14:59:45,936 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 14:59:45,952 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 14:59:45,952 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 14:59:45,953 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-23 14:59:45,953 INFO L811 eck$LassoCheckResult]: loop already infeasible [2018-11-23 14:59:45,953 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-23 14:59:45,953 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-23 14:59:45,953 INFO L87 Difference]: Start difference. First operand 2139 states and 3110 transitions. cyclomatic complexity: 975 Second operand 3 states. [2018-11-23 14:59:46,011 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 14:59:46,011 INFO L93 Difference]: Finished difference Result 3968 states and 5735 transitions. [2018-11-23 14:59:46,012 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-23 14:59:46,012 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 3968 states and 5735 transitions. [2018-11-23 14:59:46,029 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 3860 [2018-11-23 14:59:46,044 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 3968 states to 3968 states and 5735 transitions. [2018-11-23 14:59:46,045 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 3968 [2018-11-23 14:59:46,049 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 3968 [2018-11-23 14:59:46,049 INFO L73 IsDeterministic]: Start isDeterministic. Operand 3968 states and 5735 transitions. [2018-11-23 14:59:46,055 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-23 14:59:46,055 INFO L705 BuchiCegarLoop]: Abstraction has 3968 states and 5735 transitions. [2018-11-23 14:59:46,058 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3968 states and 5735 transitions. [2018-11-23 14:59:46,099 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3968 to 3960. [2018-11-23 14:59:46,099 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3960 states. [2018-11-23 14:59:46,108 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3960 states to 3960 states and 5727 transitions. [2018-11-23 14:59:46,108 INFO L728 BuchiCegarLoop]: Abstraction has 3960 states and 5727 transitions. [2018-11-23 14:59:46,108 INFO L608 BuchiCegarLoop]: Abstraction has 3960 states and 5727 transitions. [2018-11-23 14:59:46,108 INFO L442 BuchiCegarLoop]: ======== Iteration 12============ [2018-11-23 14:59:46,108 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 3960 states and 5727 transitions. [2018-11-23 14:59:46,119 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 3852 [2018-11-23 14:59:46,120 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-23 14:59:46,120 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-23 14:59:46,121 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 14:59:46,121 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 14:59:46,121 INFO L794 eck$LassoCheckResult]: Stem: 22505#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0; 22389#L-1 havoc main_#res;havoc main_~__retres1~8;havoc main_~__retres1~8;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 21947#L1006 havoc start_simulation_#t~ret17, start_simulation_#t~ret18, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 21948#L458 assume 1 == ~m_i~0;~m_st~0 := 0; 22316#L465-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 22317#L470-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 22196#L475-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 22197#L480-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 22240#L485-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 22035#L490-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 22036#L495-1 assume !(0 == ~M_E~0); 22332#L674-1 assume !(0 == ~T1_E~0); 22333#L679-1 assume !(0 == ~T2_E~0); 22212#L684-1 assume !(0 == ~T3_E~0); 22213#L689-1 assume !(0 == ~T4_E~0); 22480#L694-1 assume !(0 == ~T5_E~0); 22074#L699-1 assume !(0 == ~T6_E~0); 22075#L704-1 assume !(0 == ~E_M~0); 21905#L709-1 assume !(0 == ~E_1~0); 21906#L714-1 assume !(0 == ~E_2~0); 21992#L719-1 assume !(0 == ~E_3~0); 21993#L724-1 assume !(0 == ~E_4~0); 22325#L729-1 assume !(0 == ~E_5~0); 22326#L734-1 assume !(0 == ~E_6~0); 22206#L739-1 havoc activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 22103#L324 assume !(1 == ~m_pc~0); 22047#L324-2 is_master_triggered_~__retres1~0 := 0; 22046#L335 is_master_triggered_#res := is_master_triggered_~__retres1~0; 22043#L336 activate_threads_#t~ret9 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 22044#L839 assume !(0 != activate_threads_~tmp~1); 22344#L839-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 22152#L343 assume !(1 == ~t1_pc~0); 22153#L343-2 is_transmit1_triggered_~__retres1~1 := 0; 22147#L354 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 22148#L355 activate_threads_#t~ret10 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 22286#L847 assume !(0 != activate_threads_~tmp___0~0); 22541#L847-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 22459#L362 assume !(1 == ~t2_pc~0); 22403#L362-2 is_transmit2_triggered_~__retres1~2 := 0; 22404#L373 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 22455#L374 activate_threads_#t~ret11 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 22526#L855 assume !(0 != activate_threads_~tmp___1~0); 22547#L855-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 22552#L381 assume !(1 == ~t3_pc~0); 22588#L381-2 is_transmit3_triggered_~__retres1~3 := 0; 22585#L392 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 22586#L393 activate_threads_#t~ret12 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 21960#L863 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 21930#L863-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 21931#L400 assume !(1 == ~t4_pc~0); 21973#L400-2 is_transmit4_triggered_~__retres1~4 := 0; 21974#L411 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 21988#L412 activate_threads_#t~ret13 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 22122#L871 assume !(0 != activate_threads_~tmp___3~0); 22221#L871-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 22225#L419 assume !(1 == ~t5_pc~0); 22135#L419-2 is_transmit5_triggered_~__retres1~5 := 0; 22136#L430 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 22198#L431 activate_threads_#t~ret14 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 22199#L879 assume !(0 != activate_threads_~tmp___4~0); 22470#L879-2 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 22471#L438 assume 1 == ~t6_pc~0; 22444#L439 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6 := 1; 22445#L449 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 22442#L450 activate_threads_#t~ret15 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 22443#L887 assume !(0 != activate_threads_~tmp___5~0); 22605#L887-2 assume !(1 == ~M_E~0); 22005#L752-1 assume !(1 == ~T1_E~0); 22006#L757-1 assume !(1 == ~T2_E~0); 22320#L762-1 assume !(1 == ~T3_E~0); 22321#L767-1 assume !(1 == ~T4_E~0); 22204#L772-1 assume !(1 == ~T5_E~0); 22205#L777-1 assume 1 == ~T6_E~0;~T6_E~0 := 2; 22478#L782-1 assume !(1 == ~E_M~0); 22069#L787-1 assume !(1 == ~E_1~0); 22070#L792-1 assume !(1 == ~E_2~0); 21932#L797-1 assume !(1 == ~E_3~0); 21933#L802-1 assume !(1 == ~E_4~0); 22003#L807-1 assume !(1 == ~E_5~0); 22004#L812-1 assume !(1 == ~E_6~0); 22606#L1043-1 [2018-11-23 14:59:46,121 INFO L796 eck$LassoCheckResult]: Loop: 22606#L1043-1 assume !false; 25015#L1044 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret1, eval_#t~nondet2, eval_~tmp_ndt_1~0, eval_#t~nondet3, eval_~tmp_ndt_2~0, eval_#t~nondet4, eval_~tmp_ndt_3~0, eval_#t~nondet5, eval_~tmp_ndt_4~0, eval_#t~nondet6, eval_~tmp_ndt_5~0, eval_#t~nondet7, eval_~tmp_ndt_6~0, eval_#t~nondet8, eval_~tmp_ndt_7~0, eval_~tmp~0;havoc eval_~tmp~0; 25012#L649 assume !false; 25009#L556 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~7;havoc exists_runnable_thread_~__retres1~7; 25001#L508 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7 := 1; 24995#L545 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~7; 22599#L546 eval_#t~ret1 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret1;havoc eval_#t~ret1; 22466#L560 assume !(0 != eval_~tmp~0); 22468#L664 start_simulation_~kernel_st~0 := 2; 25585#L458-1 start_simulation_~kernel_st~0 := 3; 25584#L674-2 assume 0 == ~M_E~0;~M_E~0 := 1; 25583#L674-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 25582#L679-3 assume !(0 == ~T2_E~0); 25581#L684-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 25580#L689-3 assume !(0 == ~T4_E~0); 25579#L694-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 25578#L699-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 25577#L704-3 assume 0 == ~E_M~0;~E_M~0 := 1; 25576#L709-3 assume 0 == ~E_1~0;~E_1~0 := 1; 25575#L714-3 assume 0 == ~E_2~0;~E_2~0 := 1; 25574#L719-3 assume !(0 == ~E_3~0); 25573#L724-3 assume 0 == ~E_4~0;~E_4~0 := 1; 25572#L729-3 assume !(0 == ~E_5~0); 25571#L734-3 assume 0 == ~E_6~0;~E_6~0 := 1; 25569#L739-3 havoc activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 25566#L324-24 assume 1 == ~m_pc~0; 25563#L325-8 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 25561#L335-8 is_master_triggered_#res := is_master_triggered_~__retres1~0; 25559#L336-8 activate_threads_#t~ret9 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 25557#L839-24 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 22242#L839-26 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 22243#L343-24 assume !(1 == ~t1_pc~0); 22307#L343-26 is_transmit1_triggered_~__retres1~1 := 0; 22308#L354-8 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 22271#L355-8 activate_threads_#t~ret10 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 22272#L847-24 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 22498#L847-26 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 22500#L362-24 assume !(1 == ~t2_pc~0); 22535#L362-26 is_transmit2_triggered_~__retres1~2 := 0; 22376#L373-8 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 22377#L374-8 activate_threads_#t~ret11 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 22488#L855-24 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 22607#L855-26 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 22608#L381-24 assume !(1 == ~t3_pc~0); 22616#L381-26 is_transmit3_triggered_~__retres1~3 := 0; 22579#L392-8 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 22580#L393-8 activate_threads_#t~ret12 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 22094#L863-24 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 22095#L863-26 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 21911#L400-24 assume !(1 == ~t4_pc~0); 21912#L400-26 is_transmit4_triggered_~__retres1~4 := 0; 21922#L411-8 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 21964#L412-8 activate_threads_#t~ret13 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 22085#L871-24 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 22348#L871-26 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 22214#L419-24 assume 1 == ~t5_pc~0; 22215#L420-8 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 22187#L430-8 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 22234#L431-8 activate_threads_#t~ret14 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 22358#L879-24 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 22381#L879-26 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 22387#L438-24 assume 1 == ~t6_pc~0; 22436#L439-8 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6 := 1; 22437#L449-8 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 22432#L450-8 activate_threads_#t~ret15 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 22433#L887-24 assume 0 != activate_threads_~tmp___5~0;~t6_st~0 := 0; 22557#L887-26 assume !(1 == ~M_E~0); 21996#L752-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 21997#L757-3 assume !(1 == ~T2_E~0); 22329#L762-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 22330#L767-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 22210#L772-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 22211#L777-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 22479#L782-3 assume 1 == ~E_M~0;~E_M~0 := 2; 22072#L787-3 assume !(1 == ~E_1~0); 22073#L792-3 assume 1 == ~E_2~0;~E_2~0 := 2; 21941#L797-3 assume !(1 == ~E_3~0); 21942#L802-3 assume 1 == ~E_4~0;~E_4~0 := 2; 21990#L807-3 assume 1 == ~E_5~0;~E_5~0 := 2; 21991#L812-3 assume 1 == ~E_6~0;~E_6~0 := 2; 22322#L817-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~7;havoc exists_runnable_thread_~__retres1~7; 22195#L508-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7 := 1; 21985#L545-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~7; 22064#L546-1 start_simulation_#t~ret17 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret17;havoc start_simulation_#t~ret17; 22099#L1062 assume !(0 == start_simulation_~tmp~3); 22100#L1062-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret16, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~7;havoc exists_runnable_thread_~__retres1~7; 22102#L508-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7 := 1; 21987#L545-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~7; 22068#L546-2 stop_simulation_#t~ret16 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret16;havoc stop_simulation_#t~ret16; 25043#L1017 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 25038#L1024 stop_simulation_#res := stop_simulation_~__retres2~0; 25031#L1025 start_simulation_#t~ret18 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret18;havoc start_simulation_#t~ret18; 25025#L1075 assume !(0 != start_simulation_~tmp___0~1); 22606#L1043-1 [2018-11-23 14:59:46,121 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 14:59:46,121 INFO L82 PathProgramCache]: Analyzing trace with hash -910072669, now seen corresponding path program 1 times [2018-11-23 14:59:46,122 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 14:59:46,122 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 14:59:46,122 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 14:59:46,122 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 14:59:46,122 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 14:59:46,127 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 14:59:46,148 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 14:59:46,149 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 14:59:46,149 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2018-11-23 14:59:46,149 INFO L799 eck$LassoCheckResult]: stem already infeasible [2018-11-23 14:59:46,149 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 14:59:46,149 INFO L82 PathProgramCache]: Analyzing trace with hash -1310597514, now seen corresponding path program 2 times [2018-11-23 14:59:46,149 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 14:59:46,149 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 14:59:46,152 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 14:59:46,152 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 14:59:46,152 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 14:59:46,156 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 14:59:46,182 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 14:59:46,182 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 14:59:46,182 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-23 14:59:46,182 INFO L811 eck$LassoCheckResult]: loop already infeasible [2018-11-23 14:59:46,185 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-23 14:59:46,185 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-23 14:59:46,185 INFO L87 Difference]: Start difference. First operand 3960 states and 5727 transitions. cyclomatic complexity: 1775 Second operand 3 states. [2018-11-23 14:59:46,288 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 14:59:46,288 INFO L93 Difference]: Finished difference Result 7395 states and 10640 transitions. [2018-11-23 14:59:46,289 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-23 14:59:46,289 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 7395 states and 10640 transitions. [2018-11-23 14:59:46,316 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 7248 [2018-11-23 14:59:46,344 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 7395 states to 7395 states and 10640 transitions. [2018-11-23 14:59:46,345 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 7395 [2018-11-23 14:59:46,351 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 7395 [2018-11-23 14:59:46,351 INFO L73 IsDeterministic]: Start isDeterministic. Operand 7395 states and 10640 transitions. [2018-11-23 14:59:46,361 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-23 14:59:46,361 INFO L705 BuchiCegarLoop]: Abstraction has 7395 states and 10640 transitions. [2018-11-23 14:59:46,366 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 7395 states and 10640 transitions. [2018-11-23 14:59:46,442 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 7395 to 7379. [2018-11-23 14:59:46,442 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 7379 states. [2018-11-23 14:59:46,455 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 7379 states to 7379 states and 10624 transitions. [2018-11-23 14:59:46,455 INFO L728 BuchiCegarLoop]: Abstraction has 7379 states and 10624 transitions. [2018-11-23 14:59:46,455 INFO L608 BuchiCegarLoop]: Abstraction has 7379 states and 10624 transitions. [2018-11-23 14:59:46,455 INFO L442 BuchiCegarLoop]: ======== Iteration 13============ [2018-11-23 14:59:46,455 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 7379 states and 10624 transitions. [2018-11-23 14:59:46,475 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 7232 [2018-11-23 14:59:46,476 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-23 14:59:46,476 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-23 14:59:46,477 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 14:59:46,477 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 14:59:46,477 INFO L794 eck$LassoCheckResult]: Stem: 33907#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0; 33769#L-1 havoc main_#res;havoc main_~__retres1~8;havoc main_~__retres1~8;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 33308#L1006 havoc start_simulation_#t~ret17, start_simulation_#t~ret18, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 33309#L458 assume 1 == ~m_i~0;~m_st~0 := 0; 33695#L465-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 33696#L470-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 33568#L475-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 33569#L480-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 33615#L485-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 33398#L490-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 33399#L495-1 assume !(0 == ~M_E~0); 33715#L674-1 assume !(0 == ~T1_E~0); 33716#L679-1 assume !(0 == ~T2_E~0); 33585#L684-1 assume !(0 == ~T3_E~0); 33586#L689-1 assume !(0 == ~T4_E~0); 33881#L694-1 assume !(0 == ~T5_E~0); 33437#L699-1 assume !(0 == ~T6_E~0); 33438#L704-1 assume !(0 == ~E_M~0); 33267#L709-1 assume !(0 == ~E_1~0); 33268#L714-1 assume !(0 == ~E_2~0); 33355#L719-1 assume !(0 == ~E_3~0); 33356#L724-1 assume !(0 == ~E_4~0); 33705#L729-1 assume !(0 == ~E_5~0); 33706#L734-1 assume !(0 == ~E_6~0); 33579#L739-1 havoc activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 33467#L324 assume !(1 == ~m_pc~0); 33410#L324-2 is_master_triggered_~__retres1~0 := 0; 33409#L335 is_master_triggered_#res := is_master_triggered_~__retres1~0; 33406#L336 activate_threads_#t~ret9 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 33407#L839 assume !(0 != activate_threads_~tmp~1); 33726#L839-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 33524#L343 assume !(1 == ~t1_pc~0); 33525#L343-2 is_transmit1_triggered_~__retres1~1 := 0; 33519#L354 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 33520#L355 activate_threads_#t~ret10 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 33662#L847 assume !(0 != activate_threads_~tmp___0~0); 33941#L847-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 33838#L362 assume !(1 == ~t2_pc~0); 33783#L362-2 is_transmit2_triggered_~__retres1~2 := 0; 33784#L373 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 33834#L374 activate_threads_#t~ret11 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 33930#L855 assume !(0 != activate_threads_~tmp___1~0); 33948#L855-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 33954#L381 assume !(1 == ~t3_pc~0); 33993#L381-2 is_transmit3_triggered_~__retres1~3 := 0; 33990#L392 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 33991#L393 activate_threads_#t~ret12 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 33320#L863 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 33292#L863-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 33293#L400 assume !(1 == ~t4_pc~0); 33334#L400-2 is_transmit4_triggered_~__retres1~4 := 0; 33335#L411 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 33350#L412 activate_threads_#t~ret13 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 33495#L871 assume !(0 != activate_threads_~tmp___3~0); 33595#L871-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 33599#L419 assume !(1 == ~t5_pc~0); 33506#L419-2 is_transmit5_triggered_~__retres1~5 := 0; 33507#L430 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 33570#L431 activate_threads_#t~ret14 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 33571#L879 assume !(0 != activate_threads_~tmp___4~0); 33852#L879-2 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 33853#L438 assume !(1 == ~t6_pc~0); 33870#L438-2 is_transmit6_triggered_~__retres1~6 := 0; 33871#L449 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 33824#L450 activate_threads_#t~ret15 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 33825#L887 assume !(0 != activate_threads_~tmp___5~0); 34014#L887-2 assume !(1 == ~M_E~0); 33368#L752-1 assume !(1 == ~T1_E~0); 33369#L757-1 assume !(1 == ~T2_E~0); 33700#L762-1 assume !(1 == ~T3_E~0); 33701#L767-1 assume !(1 == ~T4_E~0); 33577#L772-1 assume !(1 == ~T5_E~0); 33578#L777-1 assume 1 == ~T6_E~0;~T6_E~0 := 2; 33879#L782-1 assume !(1 == ~E_M~0); 33432#L787-1 assume !(1 == ~E_1~0); 33433#L792-1 assume !(1 == ~E_2~0); 33294#L797-1 assume !(1 == ~E_3~0); 33295#L802-1 assume !(1 == ~E_4~0); 33366#L807-1 assume !(1 == ~E_5~0); 33367#L812-1 assume !(1 == ~E_6~0); 34017#L1043-1 [2018-11-23 14:59:46,478 INFO L796 eck$LassoCheckResult]: Loop: 34017#L1043-1 assume !false; 39525#L1044 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret1, eval_#t~nondet2, eval_~tmp_ndt_1~0, eval_#t~nondet3, eval_~tmp_ndt_2~0, eval_#t~nondet4, eval_~tmp_ndt_3~0, eval_#t~nondet5, eval_~tmp_ndt_4~0, eval_#t~nondet6, eval_~tmp_ndt_5~0, eval_#t~nondet7, eval_~tmp_ndt_6~0, eval_#t~nondet8, eval_~tmp_ndt_7~0, eval_~tmp~0;havoc eval_~tmp~0; 39519#L649 assume !false; 39512#L556 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~7;havoc exists_runnable_thread_~__retres1~7; 39497#L508 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7 := 1; 39488#L545 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~7; 39481#L546 eval_#t~ret1 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret1;havoc eval_#t~ret1; 39011#L560 assume !(0 != eval_~tmp~0); 39012#L664 start_simulation_~kernel_st~0 := 2; 39852#L458-1 start_simulation_~kernel_st~0 := 3; 39848#L674-2 assume 0 == ~M_E~0;~M_E~0 := 1; 39844#L674-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 39840#L679-3 assume !(0 == ~T2_E~0); 39836#L684-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 39829#L689-3 assume !(0 == ~T4_E~0); 39795#L694-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 39794#L699-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 39793#L704-3 assume 0 == ~E_M~0;~E_M~0 := 1; 39792#L709-3 assume 0 == ~E_1~0;~E_1~0 := 1; 39791#L714-3 assume 0 == ~E_2~0;~E_2~0 := 1; 39790#L719-3 assume !(0 == ~E_3~0); 39789#L724-3 assume 0 == ~E_4~0;~E_4~0 := 1; 39788#L729-3 assume !(0 == ~E_5~0); 39787#L734-3 assume 0 == ~E_6~0;~E_6~0 := 1; 39785#L739-3 havoc activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 39782#L324-24 assume 1 == ~m_pc~0; 39779#L325-8 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 39777#L335-8 is_master_triggered_#res := is_master_triggered_~__retres1~0; 39775#L336-8 activate_threads_#t~ret9 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 39773#L839-24 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 39771#L839-26 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 39769#L343-24 assume !(1 == ~t1_pc~0); 39767#L343-26 is_transmit1_triggered_~__retres1~1 := 0; 39765#L354-8 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 39763#L355-8 activate_threads_#t~ret10 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 39761#L847-24 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 39759#L847-26 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 39757#L362-24 assume !(1 == ~t2_pc~0); 39755#L362-26 is_transmit2_triggered_~__retres1~2 := 0; 39753#L373-8 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 39751#L374-8 activate_threads_#t~ret11 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 39749#L855-24 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 39746#L855-26 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 39744#L381-24 assume !(1 == ~t3_pc~0); 39741#L381-26 is_transmit3_triggered_~__retres1~3 := 0; 39739#L392-8 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 39737#L393-8 activate_threads_#t~ret12 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 39735#L863-24 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 39733#L863-26 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 39731#L400-24 assume !(1 == ~t4_pc~0); 39729#L400-26 is_transmit4_triggered_~__retres1~4 := 0; 39727#L411-8 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 39725#L412-8 activate_threads_#t~ret13 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 39723#L871-24 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 39721#L871-26 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 39718#L419-24 assume 1 == ~t5_pc~0; 39715#L420-8 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 39713#L430-8 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 39711#L431-8 activate_threads_#t~ret14 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 39709#L879-24 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 39707#L879-26 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 39705#L438-24 assume !(1 == ~t6_pc~0); 39703#L438-26 is_transmit6_triggered_~__retres1~6 := 0; 39701#L449-8 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 39699#L450-8 activate_threads_#t~ret15 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 39697#L887-24 assume 0 != activate_threads_~tmp___5~0;~t6_st~0 := 0; 39695#L887-26 assume !(1 == ~M_E~0); 39693#L752-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 39691#L757-3 assume !(1 == ~T2_E~0); 39689#L762-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 39687#L767-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 39685#L772-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 39683#L777-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 39681#L782-3 assume 1 == ~E_M~0;~E_M~0 := 2; 39679#L787-3 assume !(1 == ~E_1~0); 39677#L792-3 assume 1 == ~E_2~0;~E_2~0 := 2; 39675#L797-3 assume !(1 == ~E_3~0); 39673#L802-3 assume 1 == ~E_4~0;~E_4~0 := 2; 39672#L807-3 assume 1 == ~E_5~0;~E_5~0 := 2; 39671#L812-3 assume 1 == ~E_6~0;~E_6~0 := 2; 39670#L817-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~7;havoc exists_runnable_thread_~__retres1~7; 39666#L508-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7 := 1; 39661#L545-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~7; 39658#L546-1 start_simulation_#t~ret17 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret17;havoc start_simulation_#t~ret17; 39655#L1062 assume !(0 == start_simulation_~tmp~3); 39652#L1062-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret16, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~7;havoc exists_runnable_thread_~__retres1~7; 39647#L508-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7 := 1; 39636#L545-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~7; 39630#L546-2 stop_simulation_#t~ret16 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret16;havoc stop_simulation_#t~ret16; 39623#L1017 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 39617#L1024 stop_simulation_#res := stop_simulation_~__retres2~0; 39553#L1025 start_simulation_#t~ret18 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret18;havoc start_simulation_#t~ret18; 39545#L1075 assume !(0 != start_simulation_~tmp___0~1); 34017#L1043-1 [2018-11-23 14:59:46,478 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 14:59:46,478 INFO L82 PathProgramCache]: Analyzing trace with hash 81092004, now seen corresponding path program 1 times [2018-11-23 14:59:46,478 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 14:59:46,478 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 14:59:46,479 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 14:59:46,479 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-23 14:59:46,479 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 14:59:46,484 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 14:59:46,508 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 14:59:46,508 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 14:59:46,508 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2018-11-23 14:59:46,509 INFO L799 eck$LassoCheckResult]: stem already infeasible [2018-11-23 14:59:46,509 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 14:59:46,509 INFO L82 PathProgramCache]: Analyzing trace with hash -391622891, now seen corresponding path program 1 times [2018-11-23 14:59:46,509 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 14:59:46,509 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 14:59:46,510 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 14:59:46,510 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 14:59:46,510 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 14:59:46,515 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 14:59:46,533 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 14:59:46,533 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 14:59:46,533 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-23 14:59:46,533 INFO L811 eck$LassoCheckResult]: loop already infeasible [2018-11-23 14:59:46,533 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-23 14:59:46,533 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-23 14:59:46,534 INFO L87 Difference]: Start difference. First operand 7379 states and 10624 transitions. cyclomatic complexity: 3261 Second operand 3 states. [2018-11-23 14:59:46,615 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 14:59:46,616 INFO L93 Difference]: Finished difference Result 7379 states and 10574 transitions. [2018-11-23 14:59:46,617 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-23 14:59:46,617 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 7379 states and 10574 transitions. [2018-11-23 14:59:46,642 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 7232 [2018-11-23 14:59:46,672 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 7379 states to 7379 states and 10574 transitions. [2018-11-23 14:59:46,672 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 7379 [2018-11-23 14:59:46,679 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 7379 [2018-11-23 14:59:46,679 INFO L73 IsDeterministic]: Start isDeterministic. Operand 7379 states and 10574 transitions. [2018-11-23 14:59:46,686 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-23 14:59:46,686 INFO L705 BuchiCegarLoop]: Abstraction has 7379 states and 10574 transitions. [2018-11-23 14:59:46,691 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 7379 states and 10574 transitions. [2018-11-23 14:59:46,756 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 7379 to 7379. [2018-11-23 14:59:46,756 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 7379 states. [2018-11-23 14:59:46,769 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 7379 states to 7379 states and 10574 transitions. [2018-11-23 14:59:46,769 INFO L728 BuchiCegarLoop]: Abstraction has 7379 states and 10574 transitions. [2018-11-23 14:59:46,770 INFO L608 BuchiCegarLoop]: Abstraction has 7379 states and 10574 transitions. [2018-11-23 14:59:46,770 INFO L442 BuchiCegarLoop]: ======== Iteration 14============ [2018-11-23 14:59:46,770 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 7379 states and 10574 transitions. [2018-11-23 14:59:46,787 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 7232 [2018-11-23 14:59:46,787 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-23 14:59:46,787 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-23 14:59:46,788 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 14:59:46,788 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 14:59:46,789 INFO L794 eck$LassoCheckResult]: Stem: 48639#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0; 48514#L-1 havoc main_#res;havoc main_~__retres1~8;havoc main_~__retres1~8;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 48071#L1006 havoc start_simulation_#t~ret17, start_simulation_#t~ret18, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 48072#L458 assume 1 == ~m_i~0;~m_st~0 := 0; 48449#L465-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 48450#L470-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 48328#L475-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 48329#L480-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 48374#L485-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 48158#L490-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 48159#L495-1 assume !(0 == ~M_E~0); 48462#L674-1 assume !(0 == ~T1_E~0); 48463#L679-1 assume !(0 == ~T2_E~0); 48344#L684-1 assume !(0 == ~T3_E~0); 48345#L689-1 assume !(0 == ~T4_E~0); 48618#L694-1 assume !(0 == ~T5_E~0); 48197#L699-1 assume !(0 == ~T6_E~0); 48198#L704-1 assume !(0 == ~E_M~0); 48032#L709-1 assume !(0 == ~E_1~0); 48033#L714-1 assume !(0 == ~E_2~0); 48115#L719-1 assume !(0 == ~E_3~0); 48116#L724-1 assume !(0 == ~E_4~0); 48455#L729-1 assume !(0 == ~E_5~0); 48456#L734-1 assume !(0 == ~E_6~0); 48338#L739-1 havoc activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 48230#L324 assume !(1 == ~m_pc~0); 48170#L324-2 is_master_triggered_~__retres1~0 := 0; 48169#L335 is_master_triggered_#res := is_master_triggered_~__retres1~0; 48166#L336 activate_threads_#t~ret9 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 48167#L839 assume !(0 != activate_threads_~tmp~1); 48470#L839-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 48283#L343 assume !(1 == ~t1_pc~0); 48284#L343-2 is_transmit1_triggered_~__retres1~1 := 0; 48278#L354 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 48279#L355 activate_threads_#t~ret10 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 48419#L847 assume !(0 != activate_threads_~tmp___0~0); 48662#L847-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 48582#L362 assume !(1 == ~t2_pc~0); 48528#L362-2 is_transmit2_triggered_~__retres1~2 := 0; 48529#L373 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 48578#L374 activate_threads_#t~ret11 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 48657#L855 assume !(0 != activate_threads_~tmp___1~0); 48670#L855-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 48675#L381 assume !(1 == ~t3_pc~0); 48710#L381-2 is_transmit3_triggered_~__retres1~3 := 0; 48707#L392 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 48708#L393 activate_threads_#t~ret12 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 48083#L863 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 48056#L863-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 48057#L400 assume !(1 == ~t4_pc~0); 48097#L400-2 is_transmit4_triggered_~__retres1~4 := 0; 48098#L411 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 48111#L412 activate_threads_#t~ret13 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 48253#L871 assume !(0 != activate_threads_~tmp___3~0); 48353#L871-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 48357#L419 assume !(1 == ~t5_pc~0); 48266#L419-2 is_transmit5_triggered_~__retres1~5 := 0; 48267#L430 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 48330#L431 activate_threads_#t~ret14 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 48331#L879 assume !(0 != activate_threads_~tmp___4~0); 48596#L879-2 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 48597#L438 assume !(1 == ~t6_pc~0); 48610#L438-2 is_transmit6_triggered_~__retres1~6 := 0; 48611#L449 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 48568#L450 activate_threads_#t~ret15 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 48569#L887 assume !(0 != activate_threads_~tmp___5~0); 48727#L887-2 assume !(1 == ~M_E~0); 48128#L752-1 assume !(1 == ~T1_E~0); 48129#L757-1 assume !(1 == ~T2_E~0); 48452#L762-1 assume !(1 == ~T3_E~0); 48453#L767-1 assume !(1 == ~T4_E~0); 48336#L772-1 assume !(1 == ~T5_E~0); 48337#L777-1 assume !(1 == ~T6_E~0); 48616#L782-1 assume !(1 == ~E_M~0); 48192#L787-1 assume !(1 == ~E_1~0); 48193#L792-1 assume !(1 == ~E_2~0); 48058#L797-1 assume !(1 == ~E_3~0); 48059#L802-1 assume !(1 == ~E_4~0); 48126#L807-1 assume !(1 == ~E_5~0); 48127#L812-1 assume !(1 == ~E_6~0); 48730#L1043-1 [2018-11-23 14:59:46,789 INFO L796 eck$LassoCheckResult]: Loop: 48730#L1043-1 assume !false; 51029#L1044 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret1, eval_#t~nondet2, eval_~tmp_ndt_1~0, eval_#t~nondet3, eval_~tmp_ndt_2~0, eval_#t~nondet4, eval_~tmp_ndt_3~0, eval_#t~nondet5, eval_~tmp_ndt_4~0, eval_#t~nondet6, eval_~tmp_ndt_5~0, eval_#t~nondet7, eval_~tmp_ndt_6~0, eval_#t~nondet8, eval_~tmp_ndt_7~0, eval_~tmp~0;havoc eval_~tmp~0; 50771#L649 assume !false; 51026#L556 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~7;havoc exists_runnable_thread_~__retres1~7; 51015#L508 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7 := 1; 51010#L545 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~7; 51008#L546 eval_#t~ret1 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret1;havoc eval_#t~ret1; 51005#L560 assume !(0 != eval_~tmp~0); 51006#L664 start_simulation_~kernel_st~0 := 2; 51220#L458-1 start_simulation_~kernel_st~0 := 3; 51219#L674-2 assume 0 == ~M_E~0;~M_E~0 := 1; 51218#L674-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 51216#L679-3 assume !(0 == ~T2_E~0); 51213#L684-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 51211#L689-3 assume !(0 == ~T4_E~0); 51209#L694-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 51207#L699-3 assume !(0 == ~T6_E~0); 51205#L704-3 assume 0 == ~E_M~0;~E_M~0 := 1; 51203#L709-3 assume 0 == ~E_1~0;~E_1~0 := 1; 51201#L714-3 assume 0 == ~E_2~0;~E_2~0 := 1; 51199#L719-3 assume !(0 == ~E_3~0); 51197#L724-3 assume 0 == ~E_4~0;~E_4~0 := 1; 51195#L729-3 assume !(0 == ~E_5~0); 51193#L734-3 assume 0 == ~E_6~0;~E_6~0 := 1; 51191#L739-3 havoc activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 51189#L324-24 assume 1 == ~m_pc~0; 51186#L325-8 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 51184#L335-8 is_master_triggered_#res := is_master_triggered_~__retres1~0; 51182#L336-8 activate_threads_#t~ret9 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 51180#L839-24 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 51177#L839-26 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 51175#L343-24 assume !(1 == ~t1_pc~0); 51173#L343-26 is_transmit1_triggered_~__retres1~1 := 0; 51171#L354-8 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 51169#L355-8 activate_threads_#t~ret10 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 51167#L847-24 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 51165#L847-26 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 51163#L362-24 assume !(1 == ~t2_pc~0); 51161#L362-26 is_transmit2_triggered_~__retres1~2 := 0; 51159#L373-8 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 51157#L374-8 activate_threads_#t~ret11 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 51155#L855-24 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 51153#L855-26 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 51150#L381-24 assume !(1 == ~t3_pc~0); 51147#L381-26 is_transmit3_triggered_~__retres1~3 := 0; 51145#L392-8 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 51143#L393-8 activate_threads_#t~ret12 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 51141#L863-24 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 51139#L863-26 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 51137#L400-24 assume !(1 == ~t4_pc~0); 51135#L400-26 is_transmit4_triggered_~__retres1~4 := 0; 51133#L411-8 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 51131#L412-8 activate_threads_#t~ret13 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 51129#L871-24 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 51127#L871-26 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 51125#L419-24 assume 1 == ~t5_pc~0; 51122#L420-8 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 51120#L430-8 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 51118#L431-8 activate_threads_#t~ret14 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 51116#L879-24 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 51114#L879-26 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 51112#L438-24 assume !(1 == ~t6_pc~0); 51110#L438-26 is_transmit6_triggered_~__retres1~6 := 0; 51108#L449-8 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 51106#L450-8 activate_threads_#t~ret15 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 51104#L887-24 assume 0 != activate_threads_~tmp___5~0;~t6_st~0 := 0; 51103#L887-26 assume !(1 == ~M_E~0); 51102#L752-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 51101#L757-3 assume !(1 == ~T2_E~0); 51100#L762-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 51099#L767-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 51098#L772-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 51095#L777-3 assume !(1 == ~T6_E~0); 51093#L782-3 assume 1 == ~E_M~0;~E_M~0 := 2; 51091#L787-3 assume !(1 == ~E_1~0); 51089#L792-3 assume 1 == ~E_2~0;~E_2~0 := 2; 51086#L797-3 assume !(1 == ~E_3~0); 51084#L802-3 assume 1 == ~E_4~0;~E_4~0 := 2; 51082#L807-3 assume 1 == ~E_5~0;~E_5~0 := 2; 51080#L812-3 assume 1 == ~E_6~0;~E_6~0 := 2; 51078#L817-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~7;havoc exists_runnable_thread_~__retres1~7; 51069#L508-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7 := 1; 51064#L545-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~7; 51062#L546-1 start_simulation_#t~ret17 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret17;havoc start_simulation_#t~ret17; 51059#L1062 assume !(0 == start_simulation_~tmp~3); 51056#L1062-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret16, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~7;havoc exists_runnable_thread_~__retres1~7; 51049#L508-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7 := 1; 51042#L545-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~7; 51040#L546-2 stop_simulation_#t~ret16 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret16;havoc stop_simulation_#t~ret16; 51038#L1017 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 51036#L1024 stop_simulation_#res := stop_simulation_~__retres2~0; 51034#L1025 start_simulation_#t~ret18 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret18;havoc start_simulation_#t~ret18; 51032#L1075 assume !(0 != start_simulation_~tmp___0~1); 48730#L1043-1 [2018-11-23 14:59:46,789 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 14:59:46,789 INFO L82 PathProgramCache]: Analyzing trace with hash -728254622, now seen corresponding path program 1 times [2018-11-23 14:59:46,789 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 14:59:46,789 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 14:59:46,790 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 14:59:46,790 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 14:59:46,790 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 14:59:46,796 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 14:59:46,839 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 14:59:46,839 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 14:59:46,840 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-11-23 14:59:46,840 INFO L799 eck$LassoCheckResult]: stem already infeasible [2018-11-23 14:59:46,840 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 14:59:46,840 INFO L82 PathProgramCache]: Analyzing trace with hash 58144537, now seen corresponding path program 1 times [2018-11-23 14:59:46,840 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 14:59:46,840 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 14:59:46,841 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 14:59:46,841 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 14:59:46,841 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 14:59:46,852 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 14:59:46,874 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 14:59:46,874 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 14:59:46,874 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-23 14:59:46,874 INFO L811 eck$LassoCheckResult]: loop already infeasible [2018-11-23 14:59:46,874 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-11-23 14:59:46,874 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-11-23 14:59:46,875 INFO L87 Difference]: Start difference. First operand 7379 states and 10574 transitions. cyclomatic complexity: 3211 Second operand 5 states. [2018-11-23 14:59:47,053 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 14:59:47,053 INFO L93 Difference]: Finished difference Result 9983 states and 14333 transitions. [2018-11-23 14:59:47,054 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2018-11-23 14:59:47,055 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 9983 states and 14333 transitions. [2018-11-23 14:59:47,084 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 9788 [2018-11-23 14:59:47,110 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 9983 states to 9983 states and 14333 transitions. [2018-11-23 14:59:47,110 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 9983 [2018-11-23 14:59:47,118 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 9983 [2018-11-23 14:59:47,118 INFO L73 IsDeterministic]: Start isDeterministic. Operand 9983 states and 14333 transitions. [2018-11-23 14:59:47,125 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-23 14:59:47,125 INFO L705 BuchiCegarLoop]: Abstraction has 9983 states and 14333 transitions. [2018-11-23 14:59:47,132 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 9983 states and 14333 transitions. [2018-11-23 14:59:47,202 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 9983 to 7403. [2018-11-23 14:59:47,203 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 7403 states. [2018-11-23 14:59:47,214 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 7403 states to 7403 states and 10493 transitions. [2018-11-23 14:59:47,214 INFO L728 BuchiCegarLoop]: Abstraction has 7403 states and 10493 transitions. [2018-11-23 14:59:47,214 INFO L608 BuchiCegarLoop]: Abstraction has 7403 states and 10493 transitions. [2018-11-23 14:59:47,214 INFO L442 BuchiCegarLoop]: ======== Iteration 15============ [2018-11-23 14:59:47,214 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 7403 states and 10493 transitions. [2018-11-23 14:59:47,230 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 7256 [2018-11-23 14:59:47,230 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-23 14:59:47,230 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-23 14:59:47,231 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 14:59:47,231 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 14:59:47,231 INFO L794 eck$LassoCheckResult]: Stem: 66070#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0; 65929#L-1 havoc main_#res;havoc main_~__retres1~8;havoc main_~__retres1~8;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 65448#L1006 havoc start_simulation_#t~ret17, start_simulation_#t~ret18, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 65449#L458 assume 1 == ~m_i~0;~m_st~0 := 0; 65855#L465-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 65856#L470-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 65727#L475-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 65728#L480-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 65778#L485-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 65543#L490-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 65544#L495-1 assume !(0 == ~M_E~0); 65873#L674-1 assume !(0 == ~T1_E~0); 65874#L679-1 assume !(0 == ~T2_E~0); 65745#L684-1 assume !(0 == ~T3_E~0); 65746#L689-1 assume !(0 == ~T4_E~0); 66045#L694-1 assume !(0 == ~T5_E~0); 65585#L699-1 assume !(0 == ~T6_E~0); 65586#L704-1 assume !(0 == ~E_M~0); 65407#L709-1 assume !(0 == ~E_1~0); 65408#L714-1 assume !(0 == ~E_2~0); 65500#L719-1 assume !(0 == ~E_3~0); 65501#L724-1 assume !(0 == ~E_4~0); 65864#L729-1 assume !(0 == ~E_5~0); 65865#L734-1 assume !(0 == ~E_6~0); 65738#L739-1 havoc activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 65617#L324 assume !(1 == ~m_pc~0); 65556#L324-2 is_master_triggered_~__retres1~0 := 0; 65555#L335 is_master_triggered_#res := is_master_triggered_~__retres1~0; 65552#L336 activate_threads_#t~ret9 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 65553#L839 assume !(0 != activate_threads_~tmp~1); 65882#L839-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 65681#L343 assume !(1 == ~t1_pc~0); 65682#L343-2 is_transmit1_triggered_~__retres1~1 := 0; 65676#L354 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 65677#L355 activate_threads_#t~ret10 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 65824#L847 assume !(0 != activate_threads_~tmp___0~0); 66098#L847-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 66000#L362 assume !(1 == ~t2_pc~0); 65943#L362-2 is_transmit2_triggered_~__retres1~2 := 0; 65944#L373 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 65996#L374 activate_threads_#t~ret11 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 66089#L855 assume !(0 != activate_threads_~tmp___1~0); 66110#L855-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 66116#L381 assume !(1 == ~t3_pc~0); 66157#L381-2 is_transmit3_triggered_~__retres1~3 := 0; 66154#L392 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 66155#L393 activate_threads_#t~ret12 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 65461#L863 assume !(0 != activate_threads_~tmp___2~0); 65433#L863-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 65434#L400 assume !(1 == ~t4_pc~0); 65478#L400-2 is_transmit4_triggered_~__retres1~4 := 0; 65479#L411 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 65496#L412 activate_threads_#t~ret13 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 65649#L871 assume !(0 != activate_threads_~tmp___3~0); 65755#L871-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 65759#L419 assume !(1 == ~t5_pc~0); 65664#L419-2 is_transmit5_triggered_~__retres1~5 := 0; 65665#L430 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 65730#L431 activate_threads_#t~ret14 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 65731#L879 assume !(0 != activate_threads_~tmp___4~0); 66018#L879-2 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 66019#L438 assume !(1 == ~t6_pc~0); 66037#L438-2 is_transmit6_triggered_~__retres1~6 := 0; 66038#L449 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 65986#L450 activate_threads_#t~ret15 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 65987#L887 assume !(0 != activate_threads_~tmp___5~0); 66176#L887-2 assume !(1 == ~M_E~0); 65513#L752-1 assume !(1 == ~T1_E~0); 65514#L757-1 assume !(1 == ~T2_E~0); 65859#L762-1 assume !(1 == ~T3_E~0); 65860#L767-1 assume !(1 == ~T4_E~0); 65736#L772-1 assume !(1 == ~T5_E~0); 65737#L777-1 assume !(1 == ~T6_E~0); 66043#L782-1 assume !(1 == ~E_M~0); 65580#L787-1 assume !(1 == ~E_1~0); 65581#L792-1 assume !(1 == ~E_2~0); 65435#L797-1 assume !(1 == ~E_3~0); 65436#L802-1 assume !(1 == ~E_4~0); 65511#L807-1 assume !(1 == ~E_5~0); 65512#L812-1 assume !(1 == ~E_6~0); 66181#L1043-1 [2018-11-23 14:59:47,232 INFO L796 eck$LassoCheckResult]: Loop: 66181#L1043-1 assume !false; 68188#L1044 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret1, eval_#t~nondet2, eval_~tmp_ndt_1~0, eval_#t~nondet3, eval_~tmp_ndt_2~0, eval_#t~nondet4, eval_~tmp_ndt_3~0, eval_#t~nondet5, eval_~tmp_ndt_4~0, eval_#t~nondet6, eval_~tmp_ndt_5~0, eval_#t~nondet7, eval_~tmp_ndt_6~0, eval_#t~nondet8, eval_~tmp_ndt_7~0, eval_~tmp~0;havoc eval_~tmp~0; 68186#L649 assume !false; 68183#L556 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~7;havoc exists_runnable_thread_~__retres1~7; 68174#L508 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7 := 1; 68169#L545 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~7; 68168#L546 eval_#t~ret1 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret1;havoc eval_#t~ret1; 68166#L560 assume !(0 != eval_~tmp~0); 68167#L664 start_simulation_~kernel_st~0 := 2; 69789#L458-1 start_simulation_~kernel_st~0 := 3; 69788#L674-2 assume 0 == ~M_E~0;~M_E~0 := 1; 69787#L674-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 69786#L679-3 assume !(0 == ~T2_E~0); 69785#L684-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 69784#L689-3 assume !(0 == ~T4_E~0); 69783#L694-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 69782#L699-3 assume !(0 == ~T6_E~0); 69781#L704-3 assume 0 == ~E_M~0;~E_M~0 := 1; 69780#L709-3 assume 0 == ~E_1~0;~E_1~0 := 1; 69779#L714-3 assume 0 == ~E_2~0;~E_2~0 := 1; 69778#L719-3 assume !(0 == ~E_3~0); 69777#L724-3 assume 0 == ~E_4~0;~E_4~0 := 1; 69776#L729-3 assume !(0 == ~E_5~0); 69775#L734-3 assume 0 == ~E_6~0;~E_6~0 := 1; 69774#L739-3 havoc activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 69773#L324-24 assume 1 == ~m_pc~0; 69771#L325-8 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 69770#L335-8 is_master_triggered_#res := is_master_triggered_~__retres1~0; 69769#L336-8 activate_threads_#t~ret9 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 69768#L839-24 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 69767#L839-26 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 69765#L343-24 assume !(1 == ~t1_pc~0); 69762#L343-26 is_transmit1_triggered_~__retres1~1 := 0; 69760#L354-8 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 69758#L355-8 activate_threads_#t~ret10 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 69756#L847-24 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 69754#L847-26 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 69752#L362-24 assume !(1 == ~t2_pc~0); 69750#L362-26 is_transmit2_triggered_~__retres1~2 := 0; 69748#L373-8 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 69746#L374-8 activate_threads_#t~ret11 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 69744#L855-24 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 69742#L855-26 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 69740#L381-24 assume !(1 == ~t3_pc~0); 69737#L381-26 is_transmit3_triggered_~__retres1~3 := 0; 69735#L392-8 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 69733#L393-8 activate_threads_#t~ret12 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 69731#L863-24 assume !(0 != activate_threads_~tmp___2~0); 69729#L863-26 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 69726#L400-24 assume !(1 == ~t4_pc~0); 69724#L400-26 is_transmit4_triggered_~__retres1~4 := 0; 69722#L411-8 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 69720#L412-8 activate_threads_#t~ret13 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 69718#L871-24 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 69716#L871-26 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 69714#L419-24 assume !(1 == ~t5_pc~0); 69712#L419-26 is_transmit5_triggered_~__retres1~5 := 0; 69709#L430-8 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 69707#L431-8 activate_threads_#t~ret14 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 69705#L879-24 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 69703#L879-26 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 69701#L438-24 assume !(1 == ~t6_pc~0); 69698#L438-26 is_transmit6_triggered_~__retres1~6 := 0; 69696#L449-8 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 69694#L450-8 activate_threads_#t~ret15 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 69692#L887-24 assume 0 != activate_threads_~tmp___5~0;~t6_st~0 := 0; 69690#L887-26 assume !(1 == ~M_E~0); 69688#L752-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 69686#L757-3 assume !(1 == ~T2_E~0); 69684#L762-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 69682#L767-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 69680#L772-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 69678#L777-3 assume !(1 == ~T6_E~0); 69676#L782-3 assume 1 == ~E_M~0;~E_M~0 := 2; 69674#L787-3 assume !(1 == ~E_1~0); 69671#L792-3 assume 1 == ~E_2~0;~E_2~0 := 2; 69667#L797-3 assume !(1 == ~E_3~0); 69664#L802-3 assume 1 == ~E_4~0;~E_4~0 := 2; 69661#L807-3 assume 1 == ~E_5~0;~E_5~0 := 2; 69658#L812-3 assume 1 == ~E_6~0;~E_6~0 := 2; 69655#L817-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~7;havoc exists_runnable_thread_~__retres1~7; 69633#L508-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7 := 1; 69625#L545-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~7; 69620#L546-1 start_simulation_#t~ret17 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret17;havoc start_simulation_#t~ret17; 69614#L1062 assume !(0 == start_simulation_~tmp~3); 69605#L1062-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret16, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~7;havoc exists_runnable_thread_~__retres1~7; 68645#L508-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7 := 1; 68639#L545-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~7; 68638#L546-2 stop_simulation_#t~ret16 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret16;havoc stop_simulation_#t~ret16; 68637#L1017 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 68635#L1024 stop_simulation_#res := stop_simulation_~__retres2~0; 68633#L1025 start_simulation_#t~ret18 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret18;havoc start_simulation_#t~ret18; 68631#L1075 assume !(0 != start_simulation_~tmp___0~1); 66181#L1043-1 [2018-11-23 14:59:47,232 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 14:59:47,232 INFO L82 PathProgramCache]: Analyzing trace with hash -800641180, now seen corresponding path program 1 times [2018-11-23 14:59:47,232 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 14:59:47,232 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 14:59:47,233 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 14:59:47,233 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 14:59:47,233 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 14:59:47,237 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-23 14:59:47,242 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-23 14:59:47,273 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 14:59:47,273 INFO L82 PathProgramCache]: Analyzing trace with hash -1785229386, now seen corresponding path program 1 times [2018-11-23 14:59:47,273 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 14:59:47,273 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 14:59:47,274 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 14:59:47,274 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 14:59:47,274 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 14:59:47,278 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 14:59:47,293 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 14:59:47,294 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 14:59:47,294 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-23 14:59:47,294 INFO L811 eck$LassoCheckResult]: loop already infeasible [2018-11-23 14:59:47,294 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-23 14:59:47,294 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-23 14:59:47,294 INFO L87 Difference]: Start difference. First operand 7403 states and 10493 transitions. cyclomatic complexity: 3106 Second operand 3 states. [2018-11-23 14:59:47,341 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 14:59:47,342 INFO L93 Difference]: Finished difference Result 8438 states and 11933 transitions. [2018-11-23 14:59:47,343 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-23 14:59:47,343 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 8438 states and 11933 transitions. [2018-11-23 14:59:47,369 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 8232 [2018-11-23 14:59:47,393 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 8438 states to 8438 states and 11933 transitions. [2018-11-23 14:59:47,393 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 8438 [2018-11-23 14:59:47,399 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 8438 [2018-11-23 14:59:47,399 INFO L73 IsDeterministic]: Start isDeterministic. Operand 8438 states and 11933 transitions. [2018-11-23 14:59:47,406 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-23 14:59:47,406 INFO L705 BuchiCegarLoop]: Abstraction has 8438 states and 11933 transitions. [2018-11-23 14:59:47,412 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 8438 states and 11933 transitions. [2018-11-23 14:59:47,472 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 8438 to 8438. [2018-11-23 14:59:47,473 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 8438 states. [2018-11-23 14:59:47,559 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 8438 states to 8438 states and 11933 transitions. [2018-11-23 14:59:47,559 INFO L728 BuchiCegarLoop]: Abstraction has 8438 states and 11933 transitions. [2018-11-23 14:59:47,559 INFO L608 BuchiCegarLoop]: Abstraction has 8438 states and 11933 transitions. [2018-11-23 14:59:47,559 INFO L442 BuchiCegarLoop]: ======== Iteration 16============ [2018-11-23 14:59:47,559 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 8438 states and 11933 transitions. [2018-11-23 14:59:47,575 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 8232 [2018-11-23 14:59:47,575 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-23 14:59:47,575 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-23 14:59:47,576 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 14:59:47,576 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 14:59:47,577 INFO L794 eck$LassoCheckResult]: Stem: 81860#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0; 81738#L-1 havoc main_#res;havoc main_~__retres1~8;havoc main_~__retres1~8;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 81298#L1006 havoc start_simulation_#t~ret17, start_simulation_#t~ret18, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 81299#L458 assume 1 == ~m_i~0;~m_st~0 := 0; 81666#L465-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 81667#L470-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 81545#L475-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 81546#L480-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 81594#L485-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 81386#L490-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 81387#L495-1 assume 0 == ~M_E~0;~M_E~0 := 1; 81680#L674-1 assume !(0 == ~T1_E~0); 81681#L679-1 assume !(0 == ~T2_E~0); 82034#L684-1 assume !(0 == ~T3_E~0); 81962#L689-1 assume !(0 == ~T4_E~0); 81833#L694-1 assume !(0 == ~T5_E~0); 81426#L699-1 assume !(0 == ~T6_E~0); 81427#L704-1 assume !(0 == ~E_M~0); 81254#L709-1 assume !(0 == ~E_1~0); 81255#L714-1 assume !(0 == ~E_2~0); 81343#L719-1 assume !(0 == ~E_3~0); 81344#L724-1 assume !(0 == ~E_4~0); 81673#L729-1 assume !(0 == ~E_5~0); 81674#L734-1 assume !(0 == ~E_6~0); 82027#L739-1 havoc activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 82026#L324 assume !(1 == ~m_pc~0); 81398#L324-2 is_master_triggered_~__retres1~0 := 0; 81397#L335 is_master_triggered_#res := is_master_triggered_~__retres1~0; 81394#L336 activate_threads_#t~ret9 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 81395#L839 assume !(0 != activate_threads_~tmp~1); 81694#L839-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 81695#L343 assume !(1 == ~t1_pc~0); 82025#L343-2 is_transmit1_triggered_~__retres1~1 := 0; 81495#L354 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 81496#L355 activate_threads_#t~ret10 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 81902#L847 assume !(0 != activate_threads_~tmp___0~0); 81897#L847-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 81804#L362 assume !(1 == ~t2_pc~0); 81752#L362-2 is_transmit2_triggered_~__retres1~2 := 0; 81753#L373 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 81800#L374 activate_threads_#t~ret11 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 81884#L855 assume !(0 != activate_threads_~tmp___1~0); 82019#L855-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 82018#L381 assume !(1 == ~t3_pc~0); 82016#L381-2 is_transmit3_triggered_~__retres1~3 := 0; 81944#L392 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 81945#L393 activate_threads_#t~ret12 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 81310#L863 assume !(0 != activate_threads_~tmp___2~0); 81281#L863-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 81282#L400 assume !(1 == ~t4_pc~0); 81323#L400-2 is_transmit4_triggered_~__retres1~4 := 0; 81324#L411 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 81339#L412 activate_threads_#t~ret13 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 81473#L871 assume !(0 != activate_threads_~tmp___3~0); 81571#L871-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 81575#L419 assume !(1 == ~t5_pc~0); 81483#L419-2 is_transmit5_triggered_~__retres1~5 := 0; 81484#L430 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 81547#L431 activate_threads_#t~ret14 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 81548#L879 assume !(0 != activate_threads_~tmp___4~0); 81818#L879-2 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 81819#L438 assume !(1 == ~t6_pc~0); 81828#L438-2 is_transmit6_triggered_~__retres1~6 := 0; 81829#L449 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 81790#L450 activate_threads_#t~ret15 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 81791#L887 assume !(0 != activate_threads_~tmp___5~0); 81964#L887-2 assume 1 == ~M_E~0;~M_E~0 := 2; 81356#L752-1 assume !(1 == ~T1_E~0); 81357#L757-1 assume !(1 == ~T2_E~0); 81670#L762-1 assume !(1 == ~T3_E~0); 81671#L767-1 assume !(1 == ~T4_E~0); 81553#L772-1 assume !(1 == ~T5_E~0); 81554#L777-1 assume !(1 == ~T6_E~0); 81831#L782-1 assume !(1 == ~E_M~0); 81421#L787-1 assume !(1 == ~E_1~0); 81422#L792-1 assume !(1 == ~E_2~0); 81283#L797-1 assume !(1 == ~E_3~0); 81284#L802-1 assume !(1 == ~E_4~0); 81354#L807-1 assume !(1 == ~E_5~0); 81355#L812-1 assume !(1 == ~E_6~0); 81967#L1043-1 [2018-11-23 14:59:47,577 INFO L796 eck$LassoCheckResult]: Loop: 81967#L1043-1 assume !false; 87077#L1044 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret1, eval_#t~nondet2, eval_~tmp_ndt_1~0, eval_#t~nondet3, eval_~tmp_ndt_2~0, eval_#t~nondet4, eval_~tmp_ndt_3~0, eval_#t~nondet5, eval_~tmp_ndt_4~0, eval_#t~nondet6, eval_~tmp_ndt_5~0, eval_#t~nondet7, eval_~tmp_ndt_6~0, eval_#t~nondet8, eval_~tmp_ndt_7~0, eval_~tmp~0;havoc eval_~tmp~0; 87072#L649 assume !false; 87069#L556 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~7;havoc exists_runnable_thread_~__retres1~7; 86929#L508 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7 := 1; 86923#L545 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~7; 86921#L546 eval_#t~ret1 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret1;havoc eval_#t~ret1; 86918#L560 assume !(0 != eval_~tmp~0); 86919#L664 start_simulation_~kernel_st~0 := 2; 87629#L458-1 start_simulation_~kernel_st~0 := 3; 87625#L674-2 assume 0 == ~M_E~0;~M_E~0 := 1; 87623#L674-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 87621#L679-3 assume !(0 == ~T2_E~0); 87619#L684-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 87617#L689-3 assume !(0 == ~T4_E~0); 87615#L694-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 87613#L699-3 assume !(0 == ~T6_E~0); 87611#L704-3 assume 0 == ~E_M~0;~E_M~0 := 1; 87609#L709-3 assume 0 == ~E_1~0;~E_1~0 := 1; 87607#L714-3 assume 0 == ~E_2~0;~E_2~0 := 1; 87606#L719-3 assume !(0 == ~E_3~0); 87605#L724-3 assume 0 == ~E_4~0;~E_4~0 := 1; 87604#L729-3 assume !(0 == ~E_5~0); 87603#L734-3 assume 0 == ~E_6~0;~E_6~0 := 1; 87602#L739-3 havoc activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 87601#L324-24 assume !(1 == ~m_pc~0); 87600#L324-26 is_master_triggered_~__retres1~0 := 0; 87597#L335-8 is_master_triggered_#res := is_master_triggered_~__retres1~0; 87594#L336-8 activate_threads_#t~ret9 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 87592#L839-24 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 87590#L839-26 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 87588#L343-24 assume !(1 == ~t1_pc~0); 87586#L343-26 is_transmit1_triggered_~__retres1~1 := 0; 87584#L354-8 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 87582#L355-8 activate_threads_#t~ret10 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 87580#L847-24 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 87578#L847-26 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 87576#L362-24 assume !(1 == ~t2_pc~0); 87574#L362-26 is_transmit2_triggered_~__retres1~2 := 0; 87572#L373-8 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 87569#L374-8 activate_threads_#t~ret11 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 87567#L855-24 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 87565#L855-26 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 87563#L381-24 assume !(1 == ~t3_pc~0); 87560#L381-26 is_transmit3_triggered_~__retres1~3 := 0; 87557#L392-8 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 87555#L393-8 activate_threads_#t~ret12 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 87553#L863-24 assume !(0 != activate_threads_~tmp___2~0); 87551#L863-26 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 87549#L400-24 assume !(1 == ~t4_pc~0); 87547#L400-26 is_transmit4_triggered_~__retres1~4 := 0; 87545#L411-8 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 87543#L412-8 activate_threads_#t~ret13 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 87541#L871-24 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 87539#L871-26 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 87537#L419-24 assume !(1 == ~t5_pc~0); 87535#L419-26 is_transmit5_triggered_~__retres1~5 := 0; 87532#L430-8 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 87529#L431-8 activate_threads_#t~ret14 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 87527#L879-24 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 87525#L879-26 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 87523#L438-24 assume !(1 == ~t6_pc~0); 87521#L438-26 is_transmit6_triggered_~__retres1~6 := 0; 87519#L449-8 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 87517#L450-8 activate_threads_#t~ret15 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 87515#L887-24 assume 0 != activate_threads_~tmp___5~0;~t6_st~0 := 0; 87513#L887-26 assume 1 == ~M_E~0;~M_E~0 := 2; 87510#L752-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 87508#L757-3 assume !(1 == ~T2_E~0); 87506#L762-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 87504#L767-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 87502#L772-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 87500#L777-3 assume !(1 == ~T6_E~0); 87498#L782-3 assume 1 == ~E_M~0;~E_M~0 := 2; 87496#L787-3 assume !(1 == ~E_1~0); 87460#L792-3 assume 1 == ~E_2~0;~E_2~0 := 2; 87454#L797-3 assume !(1 == ~E_3~0); 87448#L802-3 assume 1 == ~E_4~0;~E_4~0 := 2; 87440#L807-3 assume 1 == ~E_5~0;~E_5~0 := 2; 87431#L812-3 assume 1 == ~E_6~0;~E_6~0 := 2; 87422#L817-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~7;havoc exists_runnable_thread_~__retres1~7; 87414#L508-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7 := 1; 87406#L545-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~7; 87402#L546-1 start_simulation_#t~ret17 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret17;havoc start_simulation_#t~ret17; 87396#L1062 assume !(0 == start_simulation_~tmp~3); 87392#L1062-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret16, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~7;havoc exists_runnable_thread_~__retres1~7; 87171#L508-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7 := 1; 87158#L545-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~7; 87120#L546-2 stop_simulation_#t~ret16 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret16;havoc stop_simulation_#t~ret16; 87115#L1017 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 87107#L1024 stop_simulation_#res := stop_simulation_~__retres2~0; 87099#L1025 start_simulation_#t~ret18 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret18;havoc start_simulation_#t~ret18; 87092#L1075 assume !(0 != start_simulation_~tmp___0~1); 81967#L1043-1 [2018-11-23 14:59:47,577 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 14:59:47,577 INFO L82 PathProgramCache]: Analyzing trace with hash -1697981720, now seen corresponding path program 1 times [2018-11-23 14:59:47,577 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 14:59:47,577 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 14:59:47,578 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 14:59:47,578 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 14:59:47,578 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 14:59:47,581 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 14:59:47,600 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 14:59:47,600 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 14:59:47,600 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2018-11-23 14:59:47,600 INFO L799 eck$LassoCheckResult]: stem already infeasible [2018-11-23 14:59:47,600 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 14:59:47,600 INFO L82 PathProgramCache]: Analyzing trace with hash -1870644397, now seen corresponding path program 1 times [2018-11-23 14:59:47,601 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 14:59:47,601 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 14:59:47,601 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 14:59:47,601 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 14:59:47,601 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 14:59:47,606 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 14:59:47,641 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 14:59:47,641 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 14:59:47,641 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-23 14:59:47,642 INFO L811 eck$LassoCheckResult]: loop already infeasible [2018-11-23 14:59:47,642 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-23 14:59:47,642 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-23 14:59:47,642 INFO L87 Difference]: Start difference. First operand 8438 states and 11933 transitions. cyclomatic complexity: 3511 Second operand 3 states. [2018-11-23 14:59:47,675 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 14:59:47,676 INFO L93 Difference]: Finished difference Result 7403 states and 10443 transitions. [2018-11-23 14:59:47,677 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-23 14:59:47,677 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 7403 states and 10443 transitions. [2018-11-23 14:59:47,699 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 7256 [2018-11-23 14:59:47,718 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 7403 states to 7403 states and 10443 transitions. [2018-11-23 14:59:47,718 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 7403 [2018-11-23 14:59:47,722 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 7403 [2018-11-23 14:59:47,722 INFO L73 IsDeterministic]: Start isDeterministic. Operand 7403 states and 10443 transitions. [2018-11-23 14:59:47,727 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-23 14:59:47,727 INFO L705 BuchiCegarLoop]: Abstraction has 7403 states and 10443 transitions. [2018-11-23 14:59:47,732 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 7403 states and 10443 transitions. [2018-11-23 14:59:47,782 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 7403 to 7403. [2018-11-23 14:59:47,782 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 7403 states. [2018-11-23 14:59:47,792 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 7403 states to 7403 states and 10443 transitions. [2018-11-23 14:59:47,792 INFO L728 BuchiCegarLoop]: Abstraction has 7403 states and 10443 transitions. [2018-11-23 14:59:47,792 INFO L608 BuchiCegarLoop]: Abstraction has 7403 states and 10443 transitions. [2018-11-23 14:59:47,792 INFO L442 BuchiCegarLoop]: ======== Iteration 17============ [2018-11-23 14:59:47,792 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 7403 states and 10443 transitions. [2018-11-23 14:59:47,808 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 7256 [2018-11-23 14:59:47,808 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-23 14:59:47,808 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-23 14:59:47,809 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 14:59:47,809 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 14:59:47,810 INFO L794 eck$LassoCheckResult]: Stem: 97710#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0; 97586#L-1 havoc main_#res;havoc main_~__retres1~8;havoc main_~__retres1~8;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 97142#L1006 havoc start_simulation_#t~ret17, start_simulation_#t~ret18, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 97143#L458 assume 1 == ~m_i~0;~m_st~0 := 0; 97519#L465-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 97520#L470-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 97399#L475-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 97400#L480-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 97445#L485-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 97231#L490-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 97232#L495-1 assume !(0 == ~M_E~0); 97536#L674-1 assume !(0 == ~T1_E~0); 97537#L679-1 assume !(0 == ~T2_E~0); 97416#L684-1 assume !(0 == ~T3_E~0); 97417#L689-1 assume !(0 == ~T4_E~0); 97689#L694-1 assume !(0 == ~T5_E~0); 97270#L699-1 assume !(0 == ~T6_E~0); 97271#L704-1 assume !(0 == ~E_M~0); 97102#L709-1 assume !(0 == ~E_1~0); 97103#L714-1 assume !(0 == ~E_2~0); 97188#L719-1 assume !(0 == ~E_3~0); 97189#L724-1 assume !(0 == ~E_4~0); 97528#L729-1 assume !(0 == ~E_5~0); 97529#L734-1 assume !(0 == ~E_6~0); 97410#L739-1 havoc activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 97305#L324 assume !(1 == ~m_pc~0); 97243#L324-2 is_master_triggered_~__retres1~0 := 0; 97242#L335 is_master_triggered_#res := is_master_triggered_~__retres1~0; 97239#L336 activate_threads_#t~ret9 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 97240#L839 assume !(0 != activate_threads_~tmp~1); 97545#L839-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 97355#L343 assume !(1 == ~t1_pc~0); 97356#L343-2 is_transmit1_triggered_~__retres1~1 := 0; 97350#L354 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 97351#L355 activate_threads_#t~ret10 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 97490#L847 assume !(0 != activate_threads_~tmp___0~0); 97743#L847-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 97654#L362 assume !(1 == ~t2_pc~0); 97600#L362-2 is_transmit2_triggered_~__retres1~2 := 0; 97601#L373 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 97650#L374 activate_threads_#t~ret11 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 97733#L855 assume !(0 != activate_threads_~tmp___1~0); 97750#L855-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 97755#L381 assume !(1 == ~t3_pc~0); 97792#L381-2 is_transmit3_triggered_~__retres1~3 := 0; 97789#L392 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 97790#L393 activate_threads_#t~ret12 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 97154#L863 assume !(0 != activate_threads_~tmp___2~0); 97126#L863-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 97127#L400 assume !(1 == ~t4_pc~0); 97169#L400-2 is_transmit4_triggered_~__retres1~4 := 0; 97170#L411 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 97184#L412 activate_threads_#t~ret13 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 97327#L871 assume !(0 != activate_threads_~tmp___3~0); 97425#L871-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 97429#L419 assume !(1 == ~t5_pc~0); 97338#L419-2 is_transmit5_triggered_~__retres1~5 := 0; 97339#L430 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 97402#L431 activate_threads_#t~ret14 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 97403#L879 assume !(0 != activate_threads_~tmp___4~0); 97667#L879-2 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 97668#L438 assume !(1 == ~t6_pc~0); 97682#L438-2 is_transmit6_triggered_~__retres1~6 := 0; 97683#L449 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 97640#L450 activate_threads_#t~ret15 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 97641#L887 assume !(0 != activate_threads_~tmp___5~0); 97809#L887-2 assume !(1 == ~M_E~0); 97201#L752-1 assume !(1 == ~T1_E~0); 97202#L757-1 assume !(1 == ~T2_E~0); 97523#L762-1 assume !(1 == ~T3_E~0); 97524#L767-1 assume !(1 == ~T4_E~0); 97408#L772-1 assume !(1 == ~T5_E~0); 97409#L777-1 assume !(1 == ~T6_E~0); 97687#L782-1 assume !(1 == ~E_M~0); 97265#L787-1 assume !(1 == ~E_1~0); 97266#L792-1 assume !(1 == ~E_2~0); 97128#L797-1 assume !(1 == ~E_3~0); 97129#L802-1 assume !(1 == ~E_4~0); 97199#L807-1 assume !(1 == ~E_5~0); 97200#L812-1 assume !(1 == ~E_6~0); 97811#L1043-1 [2018-11-23 14:59:47,810 INFO L796 eck$LassoCheckResult]: Loop: 97811#L1043-1 assume !false; 100122#L1044 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret1, eval_#t~nondet2, eval_~tmp_ndt_1~0, eval_#t~nondet3, eval_~tmp_ndt_2~0, eval_#t~nondet4, eval_~tmp_ndt_3~0, eval_#t~nondet5, eval_~tmp_ndt_4~0, eval_#t~nondet6, eval_~tmp_ndt_5~0, eval_#t~nondet7, eval_~tmp_ndt_6~0, eval_#t~nondet8, eval_~tmp_ndt_7~0, eval_~tmp~0;havoc eval_~tmp~0; 99864#L649 assume !false; 100119#L556 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~7;havoc exists_runnable_thread_~__retres1~7; 100108#L508 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7 := 1; 100103#L545 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~7; 100101#L546 eval_#t~ret1 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret1;havoc eval_#t~ret1; 100098#L560 assume !(0 != eval_~tmp~0); 100099#L664 start_simulation_~kernel_st~0 := 2; 100313#L458-1 start_simulation_~kernel_st~0 := 3; 100312#L674-2 assume !(0 == ~M_E~0); 100311#L674-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 100309#L679-3 assume !(0 == ~T2_E~0); 100306#L684-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 100304#L689-3 assume !(0 == ~T4_E~0); 100302#L694-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 100300#L699-3 assume !(0 == ~T6_E~0); 100298#L704-3 assume 0 == ~E_M~0;~E_M~0 := 1; 100296#L709-3 assume 0 == ~E_1~0;~E_1~0 := 1; 100294#L714-3 assume 0 == ~E_2~0;~E_2~0 := 1; 100292#L719-3 assume !(0 == ~E_3~0); 100290#L724-3 assume 0 == ~E_4~0;~E_4~0 := 1; 100288#L729-3 assume !(0 == ~E_5~0); 100286#L734-3 assume 0 == ~E_6~0;~E_6~0 := 1; 100284#L739-3 havoc activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 100282#L324-24 assume 1 == ~m_pc~0; 100279#L325-8 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 100277#L335-8 is_master_triggered_#res := is_master_triggered_~__retres1~0; 100275#L336-8 activate_threads_#t~ret9 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 100273#L839-24 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 100270#L839-26 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 100268#L343-24 assume !(1 == ~t1_pc~0); 100266#L343-26 is_transmit1_triggered_~__retres1~1 := 0; 100264#L354-8 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 100262#L355-8 activate_threads_#t~ret10 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 100260#L847-24 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 100258#L847-26 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 100256#L362-24 assume !(1 == ~t2_pc~0); 100254#L362-26 is_transmit2_triggered_~__retres1~2 := 0; 100252#L373-8 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 100250#L374-8 activate_threads_#t~ret11 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 100248#L855-24 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 100246#L855-26 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 100243#L381-24 assume !(1 == ~t3_pc~0); 100240#L381-26 is_transmit3_triggered_~__retres1~3 := 0; 100238#L392-8 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 100236#L393-8 activate_threads_#t~ret12 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 100234#L863-24 assume !(0 != activate_threads_~tmp___2~0); 100232#L863-26 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 100230#L400-24 assume !(1 == ~t4_pc~0); 100228#L400-26 is_transmit4_triggered_~__retres1~4 := 0; 100226#L411-8 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 100224#L412-8 activate_threads_#t~ret13 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 100222#L871-24 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 100220#L871-26 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 100218#L419-24 assume 1 == ~t5_pc~0; 100215#L420-8 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 100213#L430-8 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 100211#L431-8 activate_threads_#t~ret14 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 100209#L879-24 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 100207#L879-26 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 100205#L438-24 assume !(1 == ~t6_pc~0); 100203#L438-26 is_transmit6_triggered_~__retres1~6 := 0; 100201#L449-8 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 100199#L450-8 activate_threads_#t~ret15 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 100197#L887-24 assume 0 != activate_threads_~tmp___5~0;~t6_st~0 := 0; 100196#L887-26 assume !(1 == ~M_E~0); 100195#L752-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 100194#L757-3 assume !(1 == ~T2_E~0); 100193#L762-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 100192#L767-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 100191#L772-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 100188#L777-3 assume !(1 == ~T6_E~0); 100186#L782-3 assume 1 == ~E_M~0;~E_M~0 := 2; 100184#L787-3 assume !(1 == ~E_1~0); 100182#L792-3 assume 1 == ~E_2~0;~E_2~0 := 2; 100179#L797-3 assume !(1 == ~E_3~0); 100177#L802-3 assume 1 == ~E_4~0;~E_4~0 := 2; 100175#L807-3 assume 1 == ~E_5~0;~E_5~0 := 2; 100173#L812-3 assume 1 == ~E_6~0;~E_6~0 := 2; 100171#L817-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~7;havoc exists_runnable_thread_~__retres1~7; 100162#L508-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7 := 1; 100157#L545-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~7; 100155#L546-1 start_simulation_#t~ret17 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret17;havoc start_simulation_#t~ret17; 100152#L1062 assume !(0 == start_simulation_~tmp~3); 100149#L1062-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret16, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~7;havoc exists_runnable_thread_~__retres1~7; 100142#L508-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7 := 1; 100135#L545-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~7; 100133#L546-2 stop_simulation_#t~ret16 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret16;havoc stop_simulation_#t~ret16; 100131#L1017 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 100129#L1024 stop_simulation_#res := stop_simulation_~__retres2~0; 100127#L1025 start_simulation_#t~ret18 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret18;havoc start_simulation_#t~ret18; 100125#L1075 assume !(0 != start_simulation_~tmp___0~1); 97811#L1043-1 [2018-11-23 14:59:47,810 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 14:59:47,810 INFO L82 PathProgramCache]: Analyzing trace with hash -800641180, now seen corresponding path program 2 times [2018-11-23 14:59:47,810 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 14:59:47,810 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 14:59:47,811 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 14:59:47,811 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 14:59:47,811 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 14:59:47,815 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-23 14:59:47,819 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-23 14:59:47,834 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 14:59:47,834 INFO L82 PathProgramCache]: Analyzing trace with hash -983693863, now seen corresponding path program 1 times [2018-11-23 14:59:47,834 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 14:59:47,835 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 14:59:47,835 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 14:59:47,835 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-23 14:59:47,835 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 14:59:47,840 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 14:59:47,856 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 14:59:47,856 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 14:59:47,856 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-23 14:59:47,856 INFO L811 eck$LassoCheckResult]: loop already infeasible [2018-11-23 14:59:47,856 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-23 14:59:47,857 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-23 14:59:47,857 INFO L87 Difference]: Start difference. First operand 7403 states and 10443 transitions. cyclomatic complexity: 3056 Second operand 3 states. [2018-11-23 14:59:47,933 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 14:59:47,933 INFO L93 Difference]: Finished difference Result 11070 states and 15502 transitions. [2018-11-23 14:59:47,935 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-23 14:59:47,935 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 11070 states and 15502 transitions. [2018-11-23 14:59:47,964 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 10840 [2018-11-23 14:59:47,990 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 11070 states to 11070 states and 15502 transitions. [2018-11-23 14:59:47,990 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 11070 [2018-11-23 14:59:47,998 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 11070 [2018-11-23 14:59:47,998 INFO L73 IsDeterministic]: Start isDeterministic. Operand 11070 states and 15502 transitions. [2018-11-23 14:59:48,004 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-23 14:59:48,005 INFO L705 BuchiCegarLoop]: Abstraction has 11070 states and 15502 transitions. [2018-11-23 14:59:48,011 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 11070 states and 15502 transitions. [2018-11-23 14:59:48,078 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 11070 to 11030. [2018-11-23 14:59:48,079 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 11030 states. [2018-11-23 14:59:48,091 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 11030 states to 11030 states and 15446 transitions. [2018-11-23 14:59:48,092 INFO L728 BuchiCegarLoop]: Abstraction has 11030 states and 15446 transitions. [2018-11-23 14:59:48,092 INFO L608 BuchiCegarLoop]: Abstraction has 11030 states and 15446 transitions. [2018-11-23 14:59:48,092 INFO L442 BuchiCegarLoop]: ======== Iteration 18============ [2018-11-23 14:59:48,092 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 11030 states and 15446 transitions. [2018-11-23 14:59:48,116 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 10800 [2018-11-23 14:59:48,116 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-23 14:59:48,116 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-23 14:59:48,117 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 14:59:48,117 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 14:59:48,118 INFO L794 eck$LassoCheckResult]: Stem: 116194#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0; 116079#L-1 havoc main_#res;havoc main_~__retres1~8;havoc main_~__retres1~8;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 115624#L1006 havoc start_simulation_#t~ret17, start_simulation_#t~ret18, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 115625#L458 assume 1 == ~m_i~0;~m_st~0 := 0; 116002#L465-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 116003#L470-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 115886#L475-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 115887#L480-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 115932#L485-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 115713#L490-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 115714#L495-1 assume !(0 == ~M_E~0); 116020#L674-1 assume !(0 == ~T1_E~0); 116021#L679-1 assume !(0 == ~T2_E~0); 115902#L684-1 assume !(0 == ~T3_E~0); 115903#L689-1 assume !(0 == ~T4_E~0); 116173#L694-1 assume !(0 == ~T5_E~0); 115752#L699-1 assume !(0 == ~T6_E~0); 115753#L704-1 assume !(0 == ~E_M~0); 115581#L709-1 assume 0 == ~E_1~0;~E_1~0 := 1; 115582#L714-1 assume !(0 == ~E_2~0); 116358#L719-1 assume !(0 == ~E_3~0); 116290#L724-1 assume !(0 == ~E_4~0); 116291#L729-1 assume !(0 == ~E_5~0); 116317#L734-1 assume !(0 == ~E_6~0); 116318#L739-1 havoc activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 116357#L324 assume !(1 == ~m_pc~0); 115725#L324-2 is_master_triggered_~__retres1~0 := 0; 115724#L335 is_master_triggered_#res := is_master_triggered_~__retres1~0; 115721#L336 activate_threads_#t~ret9 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 115722#L839 assume !(0 != activate_threads_~tmp~1); 116033#L839-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 116034#L343 assume !(1 == ~t1_pc~0); 116356#L343-2 is_transmit1_triggered_~__retres1~1 := 0; 115834#L354 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 115835#L355 activate_threads_#t~ret10 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 116226#L847 assume !(0 != activate_threads_~tmp___0~0); 116220#L847-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 116148#L362 assume !(1 == ~t2_pc~0); 116093#L362-2 is_transmit2_triggered_~__retres1~2 := 0; 116094#L373 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 116144#L374 activate_threads_#t~ret11 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 116213#L855 assume !(0 != activate_threads_~tmp___1~0); 116230#L855-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 116271#L381 assume !(1 == ~t3_pc~0); 116272#L381-2 is_transmit3_triggered_~__retres1~3 := 0; 116348#L392 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 116307#L393 activate_threads_#t~ret12 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 115636#L863 assume !(0 != activate_threads_~tmp___2~0); 115609#L863-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 115610#L400 assume !(1 == ~t4_pc~0); 115666#L400-2 is_transmit4_triggered_~__retres1~4 := 0; 116344#L411 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 115805#L412 activate_threads_#t~ret13 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 115806#L871 assume !(0 != activate_threads_~tmp___3~0); 115912#L871-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 115916#L419 assume !(1 == ~t5_pc~0); 115822#L419-2 is_transmit5_triggered_~__retres1~5 := 0; 115823#L430 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 115888#L431 activate_threads_#t~ret14 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 115889#L879 assume !(0 != activate_threads_~tmp___4~0); 116158#L879-2 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 116159#L438 assume !(1 == ~t6_pc~0); 116166#L438-2 is_transmit6_triggered_~__retres1~6 := 0; 116167#L449 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 116134#L450 activate_threads_#t~ret15 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 116135#L887 assume !(0 != activate_threads_~tmp___5~0); 116287#L887-2 assume !(1 == ~M_E~0); 115683#L752-1 assume !(1 == ~T1_E~0); 115684#L757-1 assume !(1 == ~T2_E~0); 116007#L762-1 assume !(1 == ~T3_E~0); 116008#L767-1 assume !(1 == ~T4_E~0); 115894#L772-1 assume !(1 == ~T5_E~0); 115895#L777-1 assume !(1 == ~T6_E~0); 116171#L782-1 assume !(1 == ~E_M~0); 115747#L787-1 assume 1 == ~E_1~0;~E_1~0 := 2; 115748#L792-1 assume !(1 == ~E_2~0); 115611#L797-1 assume !(1 == ~E_3~0); 115612#L802-1 assume !(1 == ~E_4~0); 115681#L807-1 assume !(1 == ~E_5~0); 115682#L812-1 assume !(1 == ~E_6~0); 116292#L1043-1 [2018-11-23 14:59:48,118 INFO L796 eck$LassoCheckResult]: Loop: 116292#L1043-1 assume !false; 120655#L1044 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret1, eval_#t~nondet2, eval_~tmp_ndt_1~0, eval_#t~nondet3, eval_~tmp_ndt_2~0, eval_#t~nondet4, eval_~tmp_ndt_3~0, eval_#t~nondet5, eval_~tmp_ndt_4~0, eval_#t~nondet6, eval_~tmp_ndt_5~0, eval_#t~nondet7, eval_~tmp_ndt_6~0, eval_#t~nondet8, eval_~tmp_ndt_7~0, eval_~tmp~0;havoc eval_~tmp~0; 120652#L649 assume !false; 120650#L556 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~7;havoc exists_runnable_thread_~__retres1~7; 120611#L508 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7 := 1; 120602#L545 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~7; 120596#L546 eval_#t~ret1 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret1;havoc eval_#t~ret1; 120588#L560 assume !(0 != eval_~tmp~0); 120589#L664 start_simulation_~kernel_st~0 := 2; 120953#L458-1 start_simulation_~kernel_st~0 := 3; 120951#L674-2 assume !(0 == ~M_E~0); 120949#L674-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 120947#L679-3 assume !(0 == ~T2_E~0); 120945#L684-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 120943#L689-3 assume !(0 == ~T4_E~0); 120941#L694-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 120939#L699-3 assume !(0 == ~T6_E~0); 120937#L704-3 assume 0 == ~E_M~0;~E_M~0 := 1; 120934#L709-3 assume 0 == ~E_1~0;~E_1~0 := 1; 120931#L714-3 assume 0 == ~E_2~0;~E_2~0 := 1; 120929#L719-3 assume !(0 == ~E_3~0); 120927#L724-3 assume 0 == ~E_4~0;~E_4~0 := 1; 120925#L729-3 assume !(0 == ~E_5~0); 120923#L734-3 assume 0 == ~E_6~0;~E_6~0 := 1; 120921#L739-3 havoc activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 120919#L324-24 assume !(1 == ~m_pc~0); 120917#L324-26 is_master_triggered_~__retres1~0 := 0; 120914#L335-8 is_master_triggered_#res := is_master_triggered_~__retres1~0; 120912#L336-8 activate_threads_#t~ret9 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 120910#L839-24 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 120908#L839-26 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 120906#L343-24 assume !(1 == ~t1_pc~0); 120904#L343-26 is_transmit1_triggered_~__retres1~1 := 0; 120902#L354-8 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 120900#L355-8 activate_threads_#t~ret10 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 120898#L847-24 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 120896#L847-26 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 120895#L362-24 assume !(1 == ~t2_pc~0); 120894#L362-26 is_transmit2_triggered_~__retres1~2 := 0; 120893#L373-8 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 120892#L374-8 activate_threads_#t~ret11 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 120891#L855-24 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 120890#L855-26 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 120889#L381-24 assume !(1 == ~t3_pc~0); 120886#L381-26 is_transmit3_triggered_~__retres1~3 := 0; 120883#L392-8 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 120881#L393-8 activate_threads_#t~ret12 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 120879#L863-24 assume !(0 != activate_threads_~tmp___2~0); 120877#L863-26 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 120875#L400-24 assume !(1 == ~t4_pc~0); 120871#L400-26 is_transmit4_triggered_~__retres1~4 := 0; 120869#L411-8 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 120867#L412-8 activate_threads_#t~ret13 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 120865#L871-24 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 120863#L871-26 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 120861#L419-24 assume !(1 == ~t5_pc~0); 120859#L419-26 is_transmit5_triggered_~__retres1~5 := 0; 120856#L430-8 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 120854#L431-8 activate_threads_#t~ret14 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 120852#L879-24 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 120850#L879-26 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 120848#L438-24 assume !(1 == ~t6_pc~0); 120845#L438-26 is_transmit6_triggered_~__retres1~6 := 0; 120843#L449-8 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 120841#L450-8 activate_threads_#t~ret15 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 120839#L887-24 assume 0 != activate_threads_~tmp___5~0;~t6_st~0 := 0; 120837#L887-26 assume !(1 == ~M_E~0); 120835#L752-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 120833#L757-3 assume !(1 == ~T2_E~0); 120831#L762-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 120829#L767-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 120827#L772-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 120825#L777-3 assume !(1 == ~T6_E~0); 120823#L782-3 assume 1 == ~E_M~0;~E_M~0 := 2; 120821#L787-3 assume 1 == ~E_1~0;~E_1~0 := 2; 120817#L792-3 assume 1 == ~E_2~0;~E_2~0 := 2; 120815#L797-3 assume !(1 == ~E_3~0); 120813#L802-3 assume 1 == ~E_4~0;~E_4~0 := 2; 120811#L807-3 assume 1 == ~E_5~0;~E_5~0 := 2; 120809#L812-3 assume 1 == ~E_6~0;~E_6~0 := 2; 120807#L817-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~7;havoc exists_runnable_thread_~__retres1~7; 120797#L508-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7 := 1; 120792#L545-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~7; 120790#L546-1 start_simulation_#t~ret17 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret17;havoc start_simulation_#t~ret17; 120787#L1062 assume !(0 == start_simulation_~tmp~3); 120784#L1062-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret16, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~7;havoc exists_runnable_thread_~__retres1~7; 120779#L508-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7 := 1; 120771#L545-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~7; 120769#L546-2 stop_simulation_#t~ret16 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret16;havoc stop_simulation_#t~ret16; 120719#L1017 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 120712#L1024 stop_simulation_#res := stop_simulation_~__retres2~0; 120705#L1025 start_simulation_#t~ret18 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret18;havoc start_simulation_#t~ret18; 120697#L1075 assume !(0 != start_simulation_~tmp___0~1); 116292#L1043-1 [2018-11-23 14:59:48,118 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 14:59:48,118 INFO L82 PathProgramCache]: Analyzing trace with hash -1537171736, now seen corresponding path program 1 times [2018-11-23 14:59:48,118 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 14:59:48,118 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 14:59:48,119 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 14:59:48,119 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 14:59:48,119 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 14:59:48,122 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 14:59:48,151 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 14:59:48,151 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 14:59:48,151 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2018-11-23 14:59:48,152 INFO L799 eck$LassoCheckResult]: stem already infeasible [2018-11-23 14:59:48,152 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 14:59:48,152 INFO L82 PathProgramCache]: Analyzing trace with hash -1228583723, now seen corresponding path program 1 times [2018-11-23 14:59:48,152 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 14:59:48,152 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 14:59:48,152 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 14:59:48,153 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 14:59:48,153 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 14:59:48,157 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 14:59:48,200 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 14:59:48,200 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 14:59:48,200 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-11-23 14:59:48,200 INFO L811 eck$LassoCheckResult]: loop already infeasible [2018-11-23 14:59:48,201 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-23 14:59:48,201 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-23 14:59:48,201 INFO L87 Difference]: Start difference. First operand 11030 states and 15446 transitions. cyclomatic complexity: 4432 Second operand 3 states. [2018-11-23 14:59:48,254 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 14:59:48,254 INFO L93 Difference]: Finished difference Result 7403 states and 10333 transitions. [2018-11-23 14:59:48,255 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-23 14:59:48,256 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 7403 states and 10333 transitions. [2018-11-23 14:59:48,276 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 7256 [2018-11-23 14:59:48,290 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 7403 states to 7403 states and 10333 transitions. [2018-11-23 14:59:48,290 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 7403 [2018-11-23 14:59:48,294 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 7403 [2018-11-23 14:59:48,294 INFO L73 IsDeterministic]: Start isDeterministic. Operand 7403 states and 10333 transitions. [2018-11-23 14:59:48,298 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-23 14:59:48,298 INFO L705 BuchiCegarLoop]: Abstraction has 7403 states and 10333 transitions. [2018-11-23 14:59:48,302 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 7403 states and 10333 transitions. [2018-11-23 14:59:48,348 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 7403 to 7403. [2018-11-23 14:59:48,348 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 7403 states. [2018-11-23 14:59:48,358 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 7403 states to 7403 states and 10333 transitions. [2018-11-23 14:59:48,358 INFO L728 BuchiCegarLoop]: Abstraction has 7403 states and 10333 transitions. [2018-11-23 14:59:48,358 INFO L608 BuchiCegarLoop]: Abstraction has 7403 states and 10333 transitions. [2018-11-23 14:59:48,358 INFO L442 BuchiCegarLoop]: ======== Iteration 19============ [2018-11-23 14:59:48,358 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 7403 states and 10333 transitions. [2018-11-23 14:59:48,374 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 7256 [2018-11-23 14:59:48,375 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-23 14:59:48,375 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-23 14:59:48,375 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 14:59:48,376 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 14:59:48,376 INFO L794 eck$LassoCheckResult]: Stem: 134622#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0; 134494#L-1 havoc main_#res;havoc main_~__retres1~8;havoc main_~__retres1~8;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 134067#L1006 havoc start_simulation_#t~ret17, start_simulation_#t~ret18, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 134068#L458 assume 1 == ~m_i~0;~m_st~0 := 0; 134419#L465-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 134420#L470-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 134303#L475-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 134304#L480-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 134350#L485-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 134159#L490-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 134160#L495-1 assume !(0 == ~M_E~0); 134435#L674-1 assume !(0 == ~T1_E~0); 134436#L679-1 assume !(0 == ~T2_E~0); 134322#L684-1 assume !(0 == ~T3_E~0); 134323#L689-1 assume !(0 == ~T4_E~0); 134595#L694-1 assume !(0 == ~T5_E~0); 134195#L699-1 assume !(0 == ~T6_E~0); 134196#L704-1 assume !(0 == ~E_M~0); 134023#L709-1 assume !(0 == ~E_1~0); 134024#L714-1 assume !(0 == ~E_2~0); 134113#L719-1 assume !(0 == ~E_3~0); 134114#L724-1 assume !(0 == ~E_4~0); 134428#L729-1 assume !(0 == ~E_5~0); 134429#L734-1 assume !(0 == ~E_6~0); 134314#L739-1 havoc activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 134220#L324 assume !(1 == ~m_pc~0); 134168#L324-2 is_master_triggered_~__retres1~0 := 0; 134167#L335 is_master_triggered_#res := is_master_triggered_~__retres1~0; 134164#L336 activate_threads_#t~ret9 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 134165#L839 assume !(0 != activate_threads_~tmp~1); 134446#L839-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 134259#L343 assume !(1 == ~t1_pc~0); 134260#L343-2 is_transmit1_triggered_~__retres1~1 := 0; 134257#L354 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 134258#L355 activate_threads_#t~ret10 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 134389#L847 assume !(0 != activate_threads_~tmp___0~0); 134652#L847-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 134561#L362 assume !(1 == ~t2_pc~0); 134505#L362-2 is_transmit2_triggered_~__retres1~2 := 0; 134506#L373 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 134560#L374 activate_threads_#t~ret11 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 134641#L855 assume !(0 != activate_threads_~tmp___1~0); 134658#L855-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 134663#L381 assume !(1 == ~t3_pc~0); 134698#L381-2 is_transmit3_triggered_~__retres1~3 := 0; 134696#L392 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 134697#L393 activate_threads_#t~ret12 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 134080#L863 assume !(0 != activate_threads_~tmp___2~0); 134050#L863-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 134051#L400 assume !(1 == ~t4_pc~0); 134093#L400-2 is_transmit4_triggered_~__retres1~4 := 0; 134094#L411 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 134109#L412 activate_threads_#t~ret13 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 134234#L871 assume !(0 != activate_threads_~tmp___3~0); 134329#L871-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 134333#L419 assume !(1 == ~t5_pc~0); 134242#L419-2 is_transmit5_triggered_~__retres1~5 := 0; 134243#L430 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 134305#L431 activate_threads_#t~ret14 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 134306#L879 assume !(0 != activate_threads_~tmp___4~0); 134576#L879-2 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 134577#L438 assume !(1 == ~t6_pc~0); 134587#L438-2 is_transmit6_triggered_~__retres1~6 := 0; 134588#L449 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 134547#L450 activate_threads_#t~ret15 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 134548#L887 assume !(0 != activate_threads_~tmp___5~0); 134714#L887-2 assume !(1 == ~M_E~0); 134126#L752-1 assume !(1 == ~T1_E~0); 134127#L757-1 assume !(1 == ~T2_E~0); 134423#L762-1 assume !(1 == ~T3_E~0); 134424#L767-1 assume !(1 == ~T4_E~0); 134311#L772-1 assume !(1 == ~T5_E~0); 134312#L777-1 assume !(1 == ~T6_E~0); 134593#L782-1 assume !(1 == ~E_M~0); 134190#L787-1 assume !(1 == ~E_1~0); 134191#L792-1 assume !(1 == ~E_2~0); 134053#L797-1 assume !(1 == ~E_3~0); 134054#L802-1 assume !(1 == ~E_4~0); 134124#L807-1 assume !(1 == ~E_5~0); 134125#L812-1 assume !(1 == ~E_6~0); 134715#L1043-1 [2018-11-23 14:59:48,376 INFO L796 eck$LassoCheckResult]: Loop: 134715#L1043-1 assume !false; 136455#L1044 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret1, eval_#t~nondet2, eval_~tmp_ndt_1~0, eval_#t~nondet3, eval_~tmp_ndt_2~0, eval_#t~nondet4, eval_~tmp_ndt_3~0, eval_#t~nondet5, eval_~tmp_ndt_4~0, eval_#t~nondet6, eval_~tmp_ndt_5~0, eval_#t~nondet7, eval_~tmp_ndt_6~0, eval_#t~nondet8, eval_~tmp_ndt_7~0, eval_~tmp~0;havoc eval_~tmp~0; 136454#L649 assume !false; 136453#L556 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~7;havoc exists_runnable_thread_~__retres1~7; 136446#L508 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7 := 1; 136441#L545 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~7; 136439#L546 eval_#t~ret1 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret1;havoc eval_#t~ret1; 136436#L560 assume !(0 != eval_~tmp~0); 136437#L664 start_simulation_~kernel_st~0 := 2; 137828#L458-1 start_simulation_~kernel_st~0 := 3; 137825#L674-2 assume !(0 == ~M_E~0); 137821#L674-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 137818#L679-3 assume !(0 == ~T2_E~0); 137814#L684-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 137811#L689-3 assume !(0 == ~T4_E~0); 137808#L694-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 137805#L699-3 assume !(0 == ~T6_E~0); 137802#L704-3 assume 0 == ~E_M~0;~E_M~0 := 1; 137797#L709-3 assume !(0 == ~E_1~0); 137794#L714-3 assume 0 == ~E_2~0;~E_2~0 := 1; 137791#L719-3 assume !(0 == ~E_3~0); 137788#L724-3 assume 0 == ~E_4~0;~E_4~0 := 1; 137785#L729-3 assume !(0 == ~E_5~0); 137781#L734-3 assume 0 == ~E_6~0;~E_6~0 := 1; 137778#L739-3 havoc activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 137774#L324-24 assume 1 == ~m_pc~0; 137768#L325-8 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 137764#L335-8 is_master_triggered_#res := is_master_triggered_~__retres1~0; 137760#L336-8 activate_threads_#t~ret9 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 137756#L839-24 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 137752#L839-26 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 137747#L343-24 assume !(1 == ~t1_pc~0); 137743#L343-26 is_transmit1_triggered_~__retres1~1 := 0; 137739#L354-8 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 137735#L355-8 activate_threads_#t~ret10 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 137731#L847-24 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 137726#L847-26 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 137722#L362-24 assume !(1 == ~t2_pc~0); 137718#L362-26 is_transmit2_triggered_~__retres1~2 := 0; 137714#L373-8 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 137710#L374-8 activate_threads_#t~ret11 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 137706#L855-24 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 137702#L855-26 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 137697#L381-24 assume !(1 == ~t3_pc~0); 137690#L381-26 is_transmit3_triggered_~__retres1~3 := 0; 137685#L392-8 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 137680#L393-8 activate_threads_#t~ret12 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 137675#L863-24 assume !(0 != activate_threads_~tmp___2~0); 137669#L863-26 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 137664#L400-24 assume !(1 == ~t4_pc~0); 137659#L400-26 is_transmit4_triggered_~__retres1~4 := 0; 137654#L411-8 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 137649#L412-8 activate_threads_#t~ret13 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 137644#L871-24 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 137639#L871-26 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 137636#L419-24 assume 1 == ~t5_pc~0; 137632#L420-8 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 137630#L430-8 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 137628#L431-8 activate_threads_#t~ret14 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 137626#L879-24 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 137624#L879-26 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 137622#L438-24 assume !(1 == ~t6_pc~0); 137620#L438-26 is_transmit6_triggered_~__retres1~6 := 0; 137618#L449-8 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 137616#L450-8 activate_threads_#t~ret15 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 137614#L887-24 assume 0 != activate_threads_~tmp___5~0;~t6_st~0 := 0; 137611#L887-26 assume !(1 == ~M_E~0); 137609#L752-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 137607#L757-3 assume !(1 == ~T2_E~0); 137604#L762-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 137602#L767-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 137600#L772-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 137589#L777-3 assume !(1 == ~T6_E~0); 137584#L782-3 assume 1 == ~E_M~0;~E_M~0 := 2; 137579#L787-3 assume !(1 == ~E_1~0); 137573#L792-3 assume 1 == ~E_2~0;~E_2~0 := 2; 137569#L797-3 assume !(1 == ~E_3~0); 137544#L802-3 assume 1 == ~E_4~0;~E_4~0 := 2; 137538#L807-3 assume 1 == ~E_5~0;~E_5~0 := 2; 137533#L812-3 assume 1 == ~E_6~0;~E_6~0 := 2; 137528#L817-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~7;havoc exists_runnable_thread_~__retres1~7; 137513#L508-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7 := 1; 137508#L545-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~7; 137484#L546-1 start_simulation_#t~ret17 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret17;havoc start_simulation_#t~ret17; 137477#L1062 assume !(0 == start_simulation_~tmp~3); 137471#L1062-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret16, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~7;havoc exists_runnable_thread_~__retres1~7; 136655#L508-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7 := 1; 136649#L545-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~7; 136647#L546-2 stop_simulation_#t~ret16 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret16;havoc stop_simulation_#t~ret16; 136644#L1017 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 136642#L1024 stop_simulation_#res := stop_simulation_~__retres2~0; 136583#L1025 start_simulation_#t~ret18 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret18;havoc start_simulation_#t~ret18; 136574#L1075 assume !(0 != start_simulation_~tmp___0~1); 134715#L1043-1 [2018-11-23 14:59:48,376 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 14:59:48,376 INFO L82 PathProgramCache]: Analyzing trace with hash -800641180, now seen corresponding path program 3 times [2018-11-23 14:59:48,376 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 14:59:48,376 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 14:59:48,377 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 14:59:48,377 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 14:59:48,377 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 14:59:48,381 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-23 14:59:48,386 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-23 14:59:48,402 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 14:59:48,403 INFO L82 PathProgramCache]: Analyzing trace with hash 750410587, now seen corresponding path program 1 times [2018-11-23 14:59:48,403 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 14:59:48,403 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 14:59:48,403 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 14:59:48,404 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-23 14:59:48,404 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 14:59:48,409 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 14:59:48,454 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 14:59:48,455 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 14:59:48,455 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-11-23 14:59:48,455 INFO L811 eck$LassoCheckResult]: loop already infeasible [2018-11-23 14:59:48,455 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-11-23 14:59:48,456 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-11-23 14:59:48,456 INFO L87 Difference]: Start difference. First operand 7403 states and 10333 transitions. cyclomatic complexity: 2946 Second operand 5 states. [2018-11-23 14:59:48,639 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 14:59:48,640 INFO L93 Difference]: Finished difference Result 13347 states and 18417 transitions. [2018-11-23 14:59:48,640 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2018-11-23 14:59:48,640 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 13347 states and 18417 transitions. [2018-11-23 14:59:48,667 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 13136 [2018-11-23 14:59:48,686 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 13347 states to 13347 states and 18417 transitions. [2018-11-23 14:59:48,686 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 13347 [2018-11-23 14:59:48,692 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 13347 [2018-11-23 14:59:48,692 INFO L73 IsDeterministic]: Start isDeterministic. Operand 13347 states and 18417 transitions. [2018-11-23 14:59:48,698 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-23 14:59:48,698 INFO L705 BuchiCegarLoop]: Abstraction has 13347 states and 18417 transitions. [2018-11-23 14:59:48,704 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 13347 states and 18417 transitions. [2018-11-23 14:59:48,749 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 13347 to 7451. [2018-11-23 14:59:48,750 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 7451 states. [2018-11-23 14:59:48,756 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 7451 states to 7451 states and 10381 transitions. [2018-11-23 14:59:48,756 INFO L728 BuchiCegarLoop]: Abstraction has 7451 states and 10381 transitions. [2018-11-23 14:59:48,756 INFO L608 BuchiCegarLoop]: Abstraction has 7451 states and 10381 transitions. [2018-11-23 14:59:48,756 INFO L442 BuchiCegarLoop]: ======== Iteration 20============ [2018-11-23 14:59:48,756 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 7451 states and 10381 transitions. [2018-11-23 14:59:48,768 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 7304 [2018-11-23 14:59:48,768 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-23 14:59:48,768 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-23 14:59:48,769 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 14:59:48,769 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 14:59:48,769 INFO L794 eck$LassoCheckResult]: Stem: 155400#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0; 155275#L-1 havoc main_#res;havoc main_~__retres1~8;havoc main_~__retres1~8;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 154831#L1006 havoc start_simulation_#t~ret17, start_simulation_#t~ret18, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 154832#L458 assume 1 == ~m_i~0;~m_st~0 := 0; 155198#L465-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 155199#L470-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 155082#L475-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 155083#L480-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 155129#L485-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 154922#L490-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 154923#L495-1 assume !(0 == ~M_E~0); 155214#L674-1 assume !(0 == ~T1_E~0); 155215#L679-1 assume !(0 == ~T2_E~0); 155098#L684-1 assume !(0 == ~T3_E~0); 155099#L689-1 assume !(0 == ~T4_E~0); 155376#L694-1 assume !(0 == ~T5_E~0); 154962#L699-1 assume !(0 == ~T6_E~0); 154963#L704-1 assume !(0 == ~E_M~0); 154789#L709-1 assume !(0 == ~E_1~0); 154790#L714-1 assume !(0 == ~E_2~0); 154879#L719-1 assume !(0 == ~E_3~0); 154880#L724-1 assume !(0 == ~E_4~0); 155206#L729-1 assume !(0 == ~E_5~0); 155207#L734-1 assume !(0 == ~E_6~0); 155092#L739-1 havoc activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 154989#L324 assume !(1 == ~m_pc~0); 154934#L324-2 is_master_triggered_~__retres1~0 := 0; 154933#L335 is_master_triggered_#res := is_master_triggered_~__retres1~0; 154930#L336 activate_threads_#t~ret9 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 154931#L839 assume !(0 != activate_threads_~tmp~1); 155225#L839-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 155037#L343 assume !(1 == ~t1_pc~0); 155038#L343-2 is_transmit1_triggered_~__retres1~1 := 0; 155032#L354 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 155033#L355 activate_threads_#t~ret10 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 155170#L847 assume !(0 != activate_threads_~tmp___0~0); 155435#L847-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 155342#L362 assume !(1 == ~t2_pc~0); 155289#L362-2 is_transmit2_triggered_~__retres1~2 := 0; 155290#L373 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 155338#L374 activate_threads_#t~ret11 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 155419#L855 assume !(0 != activate_threads_~tmp___1~0); 155442#L855-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 155447#L381 assume !(1 == ~t3_pc~0); 155484#L381-2 is_transmit3_triggered_~__retres1~3 := 0; 155481#L392 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 155482#L393 activate_threads_#t~ret12 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 154843#L863 assume !(0 != activate_threads_~tmp___2~0); 154816#L863-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 154817#L400 assume !(1 == ~t4_pc~0); 154857#L400-2 is_transmit4_triggered_~__retres1~4 := 0; 154858#L411 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 154875#L412 activate_threads_#t~ret13 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 155012#L871 assume !(0 != activate_threads_~tmp___3~0); 155109#L871-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 155113#L419 assume !(1 == ~t5_pc~0); 155020#L419-2 is_transmit5_triggered_~__retres1~5 := 0; 155021#L430 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 155084#L431 activate_threads_#t~ret14 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 155085#L879 assume !(0 != activate_threads_~tmp___4~0); 155354#L879-2 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 155355#L438 assume !(1 == ~t6_pc~0); 155368#L438-2 is_transmit6_triggered_~__retres1~6 := 0; 155369#L449 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 155328#L450 activate_threads_#t~ret15 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 155329#L887 assume !(0 != activate_threads_~tmp___5~0); 155499#L887-2 assume !(1 == ~M_E~0); 154892#L752-1 assume !(1 == ~T1_E~0); 154893#L757-1 assume !(1 == ~T2_E~0); 155202#L762-1 assume !(1 == ~T3_E~0); 155203#L767-1 assume !(1 == ~T4_E~0); 155090#L772-1 assume !(1 == ~T5_E~0); 155091#L777-1 assume !(1 == ~T6_E~0); 155374#L782-1 assume !(1 == ~E_M~0); 154957#L787-1 assume !(1 == ~E_1~0); 154958#L792-1 assume !(1 == ~E_2~0); 154818#L797-1 assume !(1 == ~E_3~0); 154819#L802-1 assume !(1 == ~E_4~0); 154890#L807-1 assume !(1 == ~E_5~0); 154891#L812-1 assume !(1 == ~E_6~0); 155500#L1043-1 [2018-11-23 14:59:48,769 INFO L796 eck$LassoCheckResult]: Loop: 155500#L1043-1 assume !false; 159866#L1044 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret1, eval_#t~nondet2, eval_~tmp_ndt_1~0, eval_#t~nondet3, eval_~tmp_ndt_2~0, eval_#t~nondet4, eval_~tmp_ndt_3~0, eval_#t~nondet5, eval_~tmp_ndt_4~0, eval_#t~nondet6, eval_~tmp_ndt_5~0, eval_#t~nondet7, eval_~tmp_ndt_6~0, eval_#t~nondet8, eval_~tmp_ndt_7~0, eval_~tmp~0;havoc eval_~tmp~0; 159864#L649 assume !false; 159709#L556 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~7;havoc exists_runnable_thread_~__retres1~7; 159662#L508 assume !(0 == ~m_st~0); 159663#L512 assume !(0 == ~t1_st~0); 159665#L516 assume !(0 == ~t2_st~0); 159660#L520 assume !(0 == ~t3_st~0); 159661#L524 assume !(0 == ~t4_st~0); 159664#L528 assume !(0 == ~t5_st~0); 159658#L532 assume !(0 == ~t6_st~0);exists_runnable_thread_~__retres1~7 := 0; 159659#L545 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~7; 157796#L546 eval_#t~ret1 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret1;havoc eval_#t~ret1; 157797#L560 assume !(0 != eval_~tmp~0); 160004#L664 start_simulation_~kernel_st~0 := 2; 160003#L458-1 start_simulation_~kernel_st~0 := 3; 160002#L674-2 assume !(0 == ~M_E~0); 160001#L674-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 160000#L679-3 assume !(0 == ~T2_E~0); 159999#L684-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 159998#L689-3 assume !(0 == ~T4_E~0); 159997#L694-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 159996#L699-3 assume !(0 == ~T6_E~0); 159995#L704-3 assume 0 == ~E_M~0;~E_M~0 := 1; 159994#L709-3 assume !(0 == ~E_1~0); 159993#L714-3 assume 0 == ~E_2~0;~E_2~0 := 1; 159992#L719-3 assume !(0 == ~E_3~0); 159991#L724-3 assume 0 == ~E_4~0;~E_4~0 := 1; 159990#L729-3 assume !(0 == ~E_5~0); 159989#L734-3 assume 0 == ~E_6~0;~E_6~0 := 1; 159988#L739-3 havoc activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 159987#L324-24 assume !(1 == ~m_pc~0); 159986#L324-26 is_master_triggered_~__retres1~0 := 0; 159984#L335-8 is_master_triggered_#res := is_master_triggered_~__retres1~0; 159983#L336-8 activate_threads_#t~ret9 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 159982#L839-24 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 159981#L839-26 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 159980#L343-24 assume !(1 == ~t1_pc~0); 159979#L343-26 is_transmit1_triggered_~__retres1~1 := 0; 159978#L354-8 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 159977#L355-8 activate_threads_#t~ret10 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 159976#L847-24 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 159975#L847-26 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 159974#L362-24 assume !(1 == ~t2_pc~0); 159973#L362-26 is_transmit2_triggered_~__retres1~2 := 0; 159972#L373-8 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 159971#L374-8 activate_threads_#t~ret11 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 159970#L855-24 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 159969#L855-26 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 159968#L381-24 assume !(1 == ~t3_pc~0); 159966#L381-26 is_transmit3_triggered_~__retres1~3 := 0; 159965#L392-8 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 159964#L393-8 activate_threads_#t~ret12 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 159963#L863-24 assume !(0 != activate_threads_~tmp___2~0); 159962#L863-26 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 159961#L400-24 assume !(1 == ~t4_pc~0); 159960#L400-26 is_transmit4_triggered_~__retres1~4 := 0; 159959#L411-8 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 159958#L412-8 activate_threads_#t~ret13 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 159957#L871-24 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 159956#L871-26 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 159955#L419-24 assume !(1 == ~t5_pc~0); 159954#L419-26 is_transmit5_triggered_~__retres1~5 := 0; 159952#L430-8 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 159951#L431-8 activate_threads_#t~ret14 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 159950#L879-24 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 159949#L879-26 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 159948#L438-24 assume !(1 == ~t6_pc~0); 159947#L438-26 is_transmit6_triggered_~__retres1~6 := 0; 159946#L449-8 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 159945#L450-8 activate_threads_#t~ret15 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 159944#L887-24 assume 0 != activate_threads_~tmp___5~0;~t6_st~0 := 0; 159943#L887-26 assume !(1 == ~M_E~0); 159942#L752-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 159941#L757-3 assume !(1 == ~T2_E~0); 159940#L762-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 159939#L767-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 159938#L772-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 159937#L777-3 assume !(1 == ~T6_E~0); 159936#L782-3 assume 1 == ~E_M~0;~E_M~0 := 2; 159935#L787-3 assume !(1 == ~E_1~0); 159934#L792-3 assume 1 == ~E_2~0;~E_2~0 := 2; 159933#L797-3 assume !(1 == ~E_3~0); 159932#L802-3 assume 1 == ~E_4~0;~E_4~0 := 2; 159931#L807-3 assume 1 == ~E_5~0;~E_5~0 := 2; 159930#L812-3 assume 1 == ~E_6~0;~E_6~0 := 2; 159929#L817-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~7;havoc exists_runnable_thread_~__retres1~7; 159925#L508-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7 := 1; 159919#L545-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~7; 159916#L546-1 start_simulation_#t~ret17 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret17;havoc start_simulation_#t~ret17; 159912#L1062 assume !(0 == start_simulation_~tmp~3); 159909#L1062-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret16, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~7;havoc exists_runnable_thread_~__retres1~7; 159907#L508-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7 := 1; 159900#L545-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~7; 159897#L546-2 stop_simulation_#t~ret16 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret16;havoc stop_simulation_#t~ret16; 159895#L1017 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 159893#L1024 stop_simulation_#res := stop_simulation_~__retres2~0; 159891#L1025 start_simulation_#t~ret18 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret18;havoc start_simulation_#t~ret18; 159889#L1075 assume !(0 != start_simulation_~tmp___0~1); 155500#L1043-1 [2018-11-23 14:59:48,770 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 14:59:48,770 INFO L82 PathProgramCache]: Analyzing trace with hash -800641180, now seen corresponding path program 4 times [2018-11-23 14:59:48,770 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 14:59:48,770 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 14:59:48,771 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 14:59:48,771 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 14:59:48,771 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 14:59:48,776 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-23 14:59:48,781 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-23 14:59:48,795 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 14:59:48,795 INFO L82 PathProgramCache]: Analyzing trace with hash -1583383574, now seen corresponding path program 1 times [2018-11-23 14:59:48,795 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 14:59:48,795 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 14:59:48,796 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 14:59:48,796 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-23 14:59:48,796 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 14:59:48,802 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 14:59:48,858 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 14:59:48,859 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 14:59:48,859 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-11-23 14:59:48,859 INFO L811 eck$LassoCheckResult]: loop already infeasible [2018-11-23 14:59:48,862 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-11-23 14:59:48,862 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-11-23 14:59:48,863 INFO L87 Difference]: Start difference. First operand 7451 states and 10381 transitions. cyclomatic complexity: 2946 Second operand 5 states. [2018-11-23 14:59:49,066 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 14:59:49,066 INFO L93 Difference]: Finished difference Result 21286 states and 29378 transitions. [2018-11-23 14:59:49,067 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2018-11-23 14:59:49,067 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 21286 states and 29378 transitions. [2018-11-23 14:59:49,112 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 20904 [2018-11-23 14:59:49,143 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 21286 states to 21286 states and 29378 transitions. [2018-11-23 14:59:49,143 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 21286 [2018-11-23 14:59:49,152 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 21286 [2018-11-23 14:59:49,152 INFO L73 IsDeterministic]: Start isDeterministic. Operand 21286 states and 29378 transitions. [2018-11-23 14:59:49,160 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-23 14:59:49,160 INFO L705 BuchiCegarLoop]: Abstraction has 21286 states and 29378 transitions. [2018-11-23 14:59:49,170 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 21286 states and 29378 transitions. [2018-11-23 14:59:49,229 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 21286 to 7790. [2018-11-23 14:59:49,229 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 7790 states. [2018-11-23 14:59:49,236 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 7790 states to 7790 states and 10720 transitions. [2018-11-23 14:59:49,236 INFO L728 BuchiCegarLoop]: Abstraction has 7790 states and 10720 transitions. [2018-11-23 14:59:49,236 INFO L608 BuchiCegarLoop]: Abstraction has 7790 states and 10720 transitions. [2018-11-23 14:59:49,236 INFO L442 BuchiCegarLoop]: ======== Iteration 21============ [2018-11-23 14:59:49,236 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 7790 states and 10720 transitions. [2018-11-23 14:59:49,248 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 7640 [2018-11-23 14:59:49,249 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-23 14:59:49,249 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-23 14:59:49,249 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 14:59:49,249 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 14:59:49,250 INFO L794 eck$LassoCheckResult]: Stem: 184195#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0; 184060#L-1 havoc main_#res;havoc main_~__retres1~8;havoc main_~__retres1~8;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 183580#L1006 havoc start_simulation_#t~ret17, start_simulation_#t~ret18, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 183581#L458 assume 1 == ~m_i~0;~m_st~0 := 0; 183972#L465-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 183973#L470-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 183855#L475-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 183856#L480-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 183903#L485-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 183671#L490-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 183672#L495-1 assume !(0 == ~M_E~0); 183993#L674-1 assume !(0 == ~T1_E~0); 183994#L679-1 assume !(0 == ~T2_E~0); 183873#L684-1 assume !(0 == ~T3_E~0); 183874#L689-1 assume !(0 == ~T4_E~0); 184164#L694-1 assume !(0 == ~T5_E~0); 183713#L699-1 assume !(0 == ~T6_E~0); 183714#L704-1 assume !(0 == ~E_M~0); 183539#L709-1 assume !(0 == ~E_1~0); 183540#L714-1 assume !(0 == ~E_2~0); 183625#L719-1 assume !(0 == ~E_3~0); 183626#L724-1 assume !(0 == ~E_4~0); 183981#L729-1 assume !(0 == ~E_5~0); 183982#L734-1 assume !(0 == ~E_6~0); 183866#L739-1 havoc activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 183755#L324 assume !(1 == ~m_pc~0); 183681#L324-2 is_master_triggered_~__retres1~0 := 0; 183766#L335 is_master_triggered_#res := is_master_triggered_~__retres1~0; 183792#L336 activate_threads_#t~ret9 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 184003#L839 assume !(0 != activate_threads_~tmp~1); 184004#L839-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 183811#L343 assume !(1 == ~t1_pc~0); 183812#L343-2 is_transmit1_triggered_~__retres1~1 := 0; 183809#L354 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 183810#L355 activate_threads_#t~ret10 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 183943#L847 assume !(0 != activate_threads_~tmp___0~0); 184229#L847-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 184125#L362 assume !(1 == ~t2_pc~0); 184069#L362-2 is_transmit2_triggered_~__retres1~2 := 0; 184070#L373 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 184124#L374 activate_threads_#t~ret11 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 184217#L855 assume !(0 != activate_threads_~tmp___1~0); 184240#L855-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 184245#L381 assume !(1 == ~t3_pc~0); 184282#L381-2 is_transmit3_triggered_~__retres1~3 := 0; 184280#L392 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 184281#L393 activate_threads_#t~ret12 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 183594#L863 assume !(0 != activate_threads_~tmp___2~0); 183564#L863-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 183565#L400 assume !(1 == ~t4_pc~0); 183606#L400-2 is_transmit4_triggered_~__retres1~4 := 0; 183607#L411 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 183621#L412 activate_threads_#t~ret13 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 183780#L871 assume !(0 != activate_threads_~tmp___3~0); 183882#L871-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 183886#L419 assume !(1 == ~t5_pc~0); 183794#L419-2 is_transmit5_triggered_~__retres1~5 := 0; 183795#L430 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 183857#L431 activate_threads_#t~ret14 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 183858#L879 assume !(0 != activate_threads_~tmp___4~0); 184139#L879-2 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 184140#L438 assume !(1 == ~t6_pc~0); 184155#L438-2 is_transmit6_triggered_~__retres1~6 := 0; 184156#L449 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 184110#L450 activate_threads_#t~ret15 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 184111#L887 assume !(0 != activate_threads_~tmp___5~0); 184298#L887-2 assume !(1 == ~M_E~0); 183638#L752-1 assume !(1 == ~T1_E~0); 183639#L757-1 assume !(1 == ~T2_E~0); 183977#L762-1 assume !(1 == ~T3_E~0); 183978#L767-1 assume !(1 == ~T4_E~0); 183863#L772-1 assume !(1 == ~T5_E~0); 183864#L777-1 assume !(1 == ~T6_E~0); 184162#L782-1 assume !(1 == ~E_M~0); 183708#L787-1 assume !(1 == ~E_1~0); 183709#L792-1 assume !(1 == ~E_2~0); 183570#L797-1 assume !(1 == ~E_3~0); 183571#L802-1 assume !(1 == ~E_4~0); 183636#L807-1 assume !(1 == ~E_5~0); 183637#L812-1 assume !(1 == ~E_6~0); 184309#L1043-1 [2018-11-23 14:59:49,250 INFO L796 eck$LassoCheckResult]: Loop: 184309#L1043-1 assume !false; 187662#L1044 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret1, eval_#t~nondet2, eval_~tmp_ndt_1~0, eval_#t~nondet3, eval_~tmp_ndt_2~0, eval_#t~nondet4, eval_~tmp_ndt_3~0, eval_#t~nondet5, eval_~tmp_ndt_4~0, eval_#t~nondet6, eval_~tmp_ndt_5~0, eval_#t~nondet7, eval_~tmp_ndt_6~0, eval_#t~nondet8, eval_~tmp_ndt_7~0, eval_~tmp~0;havoc eval_~tmp~0; 187659#L649 assume !false; 187656#L556 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~7;havoc exists_runnable_thread_~__retres1~7; 187633#L508 assume !(0 == ~m_st~0); 187634#L512 assume !(0 == ~t1_st~0); 187636#L516 assume !(0 == ~t2_st~0); 187631#L520 assume !(0 == ~t3_st~0); 187632#L524 assume !(0 == ~t4_st~0); 187635#L528 assume !(0 == ~t5_st~0); 187629#L532 assume !(0 == ~t6_st~0);exists_runnable_thread_~__retres1~7 := 0; 187630#L545 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~7; 187620#L546 eval_#t~ret1 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret1;havoc eval_#t~ret1; 187621#L560 assume !(0 != eval_~tmp~0); 187983#L664 start_simulation_~kernel_st~0 := 2; 187982#L458-1 start_simulation_~kernel_st~0 := 3; 187981#L674-2 assume !(0 == ~M_E~0); 187980#L674-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 187979#L679-3 assume !(0 == ~T2_E~0); 187978#L684-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 187977#L689-3 assume !(0 == ~T4_E~0); 187976#L694-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 187975#L699-3 assume !(0 == ~T6_E~0); 187974#L704-3 assume 0 == ~E_M~0;~E_M~0 := 1; 187973#L709-3 assume !(0 == ~E_1~0); 187972#L714-3 assume 0 == ~E_2~0;~E_2~0 := 1; 187971#L719-3 assume !(0 == ~E_3~0); 187970#L724-3 assume 0 == ~E_4~0;~E_4~0 := 1; 187969#L729-3 assume !(0 == ~E_5~0); 187968#L734-3 assume 0 == ~E_6~0;~E_6~0 := 1; 187967#L739-3 havoc activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 187966#L324-24 assume 1 == ~m_pc~0; 187964#L325-8 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 187962#L335-8 is_master_triggered_#res := is_master_triggered_~__retres1~0; 187960#L336-8 activate_threads_#t~ret9 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 187958#L839-24 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 187957#L839-26 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 187956#L343-24 assume !(1 == ~t1_pc~0); 187955#L343-26 is_transmit1_triggered_~__retres1~1 := 0; 187954#L354-8 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 187953#L355-8 activate_threads_#t~ret10 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 187943#L847-24 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 187941#L847-26 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 187939#L362-24 assume !(1 == ~t2_pc~0); 187937#L362-26 is_transmit2_triggered_~__retres1~2 := 0; 187935#L373-8 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 187933#L374-8 activate_threads_#t~ret11 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 187931#L855-24 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 187929#L855-26 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 187927#L381-24 assume !(1 == ~t3_pc~0); 187924#L381-26 is_transmit3_triggered_~__retres1~3 := 0; 187922#L392-8 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 187920#L393-8 activate_threads_#t~ret12 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 187918#L863-24 assume !(0 != activate_threads_~tmp___2~0); 187916#L863-26 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 187904#L400-24 assume !(1 == ~t4_pc~0); 187901#L400-26 is_transmit4_triggered_~__retres1~4 := 0; 187898#L411-8 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 187895#L412-8 activate_threads_#t~ret13 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 187892#L871-24 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 187889#L871-26 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 187886#L419-24 assume 1 == ~t5_pc~0; 187882#L420-8 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 187879#L430-8 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 187876#L431-8 activate_threads_#t~ret14 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 187864#L879-24 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 187860#L879-26 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 187856#L438-24 assume !(1 == ~t6_pc~0); 187851#L438-26 is_transmit6_triggered_~__retres1~6 := 0; 187846#L449-8 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 187842#L450-8 activate_threads_#t~ret15 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 187838#L887-24 assume 0 != activate_threads_~tmp___5~0;~t6_st~0 := 0; 187833#L887-26 assume !(1 == ~M_E~0); 187828#L752-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 187823#L757-3 assume !(1 == ~T2_E~0); 187818#L762-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 187813#L767-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 187808#L772-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 187803#L777-3 assume !(1 == ~T6_E~0); 187797#L782-3 assume 1 == ~E_M~0;~E_M~0 := 2; 187792#L787-3 assume !(1 == ~E_1~0); 187787#L792-3 assume 1 == ~E_2~0;~E_2~0 := 2; 187781#L797-3 assume !(1 == ~E_3~0); 187776#L802-3 assume 1 == ~E_4~0;~E_4~0 := 2; 187771#L807-3 assume 1 == ~E_5~0;~E_5~0 := 2; 187766#L812-3 assume 1 == ~E_6~0;~E_6~0 := 2; 187761#L817-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~7;havoc exists_runnable_thread_~__retres1~7; 187739#L508-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7 := 1; 187730#L545-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~7; 187724#L546-1 start_simulation_#t~ret17 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret17;havoc start_simulation_#t~ret17; 187718#L1062 assume !(0 == start_simulation_~tmp~3); 187711#L1062-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret16, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~7;havoc exists_runnable_thread_~__retres1~7; 187697#L508-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7 := 1; 187690#L545-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~7; 187689#L546-2 stop_simulation_#t~ret16 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret16;havoc stop_simulation_#t~ret16; 187685#L1017 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 187683#L1024 stop_simulation_#res := stop_simulation_~__retres2~0; 187682#L1025 start_simulation_#t~ret18 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret18;havoc start_simulation_#t~ret18; 187681#L1075 assume !(0 != start_simulation_~tmp___0~1); 184309#L1043-1 [2018-11-23 14:59:49,250 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 14:59:49,250 INFO L82 PathProgramCache]: Analyzing trace with hash -800641180, now seen corresponding path program 5 times [2018-11-23 14:59:49,251 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 14:59:49,251 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 14:59:49,251 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 14:59:49,251 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 14:59:49,252 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 14:59:49,256 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-23 14:59:49,261 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-23 14:59:49,275 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 14:59:49,276 INFO L82 PathProgramCache]: Analyzing trace with hash 350450028, now seen corresponding path program 1 times [2018-11-23 14:59:49,276 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 14:59:49,276 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 14:59:49,276 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 14:59:49,277 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-23 14:59:49,277 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 14:59:49,282 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 14:59:49,323 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 14:59:49,323 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 14:59:49,323 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-11-23 14:59:49,325 INFO L811 eck$LassoCheckResult]: loop already infeasible [2018-11-23 14:59:49,326 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-11-23 14:59:49,326 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-11-23 14:59:49,326 INFO L87 Difference]: Start difference. First operand 7790 states and 10720 transitions. cyclomatic complexity: 2946 Second operand 5 states. [2018-11-23 14:59:49,455 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 14:59:49,455 INFO L93 Difference]: Finished difference Result 10110 states and 13947 transitions. [2018-11-23 14:59:49,455 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2018-11-23 14:59:49,456 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 10110 states and 13947 transitions. [2018-11-23 14:59:49,478 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 9912 [2018-11-23 14:59:49,492 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 10110 states to 10110 states and 13947 transitions. [2018-11-23 14:59:49,493 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 10110 [2018-11-23 14:59:49,497 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 10110 [2018-11-23 14:59:49,498 INFO L73 IsDeterministic]: Start isDeterministic. Operand 10110 states and 13947 transitions. [2018-11-23 14:59:49,502 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-23 14:59:49,502 INFO L705 BuchiCegarLoop]: Abstraction has 10110 states and 13947 transitions. [2018-11-23 14:59:49,507 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 10110 states and 13947 transitions. [2018-11-23 14:59:49,585 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 10110 to 7814. [2018-11-23 14:59:49,586 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 7814 states. [2018-11-23 14:59:49,592 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 7814 states to 7814 states and 10639 transitions. [2018-11-23 14:59:49,592 INFO L728 BuchiCegarLoop]: Abstraction has 7814 states and 10639 transitions. [2018-11-23 14:59:49,592 INFO L608 BuchiCegarLoop]: Abstraction has 7814 states and 10639 transitions. [2018-11-23 14:59:49,593 INFO L442 BuchiCegarLoop]: ======== Iteration 22============ [2018-11-23 14:59:49,593 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 7814 states and 10639 transitions. [2018-11-23 14:59:49,606 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 7664 [2018-11-23 14:59:49,606 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-23 14:59:49,606 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-23 14:59:49,607 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 14:59:49,607 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 14:59:49,607 INFO L794 eck$LassoCheckResult]: Stem: 202139#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0; 202000#L-1 havoc main_#res;havoc main_~__retres1~8;havoc main_~__retres1~8;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 201493#L1006 havoc start_simulation_#t~ret17, start_simulation_#t~ret18, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 201494#L458 assume 1 == ~m_i~0;~m_st~0 := 0; 201905#L465-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 201906#L470-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 201778#L475-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 201779#L480-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 201832#L485-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 201588#L490-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 201589#L495-1 assume !(0 == ~M_E~0); 201926#L674-1 assume !(0 == ~T1_E~0); 201927#L679-1 assume !(0 == ~T2_E~0); 201796#L684-1 assume !(0 == ~T3_E~0); 201797#L689-1 assume !(0 == ~T4_E~0); 202108#L694-1 assume !(0 == ~T5_E~0); 201631#L699-1 assume !(0 == ~T6_E~0); 201632#L704-1 assume !(0 == ~E_M~0); 201453#L709-1 assume !(0 == ~E_1~0); 201454#L714-1 assume !(0 == ~E_2~0); 201542#L719-1 assume !(0 == ~E_3~0); 201543#L724-1 assume !(0 == ~E_4~0); 201915#L729-1 assume !(0 == ~E_5~0); 201916#L734-1 assume !(0 == ~E_6~0); 201789#L739-1 havoc activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 201668#L324 assume !(1 == ~m_pc~0); 201598#L324-2 is_master_triggered_~__retres1~0 := 0; 201679#L335 is_master_triggered_#res := is_master_triggered_~__retres1~0; 201594#L336 activate_threads_#t~ret9 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 201595#L839 assume !(0 != activate_threads_~tmp~1); 201938#L839-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 201731#L343 assume !(1 == ~t1_pc~0); 201732#L343-2 is_transmit1_triggered_~__retres1~1 := 0; 201729#L354 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 201730#L355 activate_threads_#t~ret10 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 201873#L847 assume !(0 != activate_threads_~tmp___0~0); 202185#L847-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 202065#L362 assume !(1 == ~t2_pc~0); 202011#L362-2 is_transmit2_triggered_~__retres1~2 := 0; 202012#L373 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 202064#L374 activate_threads_#t~ret11 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 202165#L855 assume !(0 != activate_threads_~tmp___1~0); 202198#L855-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 202203#L381 assume !(1 == ~t3_pc~0); 202246#L381-2 is_transmit3_triggered_~__retres1~3 := 0; 202244#L392 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 202245#L393 activate_threads_#t~ret12 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 201507#L863 assume !(0 != activate_threads_~tmp___2~0); 201478#L863-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 201479#L400 assume !(1 == ~t4_pc~0); 201519#L400-2 is_transmit4_triggered_~__retres1~4 := 0; 201520#L411 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 201538#L412 activate_threads_#t~ret13 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 201699#L871 assume !(0 != activate_threads_~tmp___3~0); 201806#L871-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 201810#L419 assume !(1 == ~t5_pc~0); 201713#L419-2 is_transmit5_triggered_~__retres1~5 := 0; 201714#L430 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 201780#L431 activate_threads_#t~ret14 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 201781#L879 assume !(0 != activate_threads_~tmp___4~0); 202079#L879-2 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 202080#L438 assume !(1 == ~t6_pc~0); 202098#L438-2 is_transmit6_triggered_~__retres1~6 := 0; 202099#L449 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 202051#L450 activate_threads_#t~ret15 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 202052#L887 assume !(0 != activate_threads_~tmp___5~0); 202271#L887-2 assume !(1 == ~M_E~0); 201555#L752-1 assume !(1 == ~T1_E~0); 201556#L757-1 assume !(1 == ~T2_E~0); 201910#L762-1 assume !(1 == ~T3_E~0); 201911#L767-1 assume !(1 == ~T4_E~0); 201786#L772-1 assume !(1 == ~T5_E~0); 201787#L777-1 assume !(1 == ~T6_E~0); 202105#L782-1 assume !(1 == ~E_M~0); 201625#L787-1 assume !(1 == ~E_1~0); 201626#L792-1 assume !(1 == ~E_2~0); 201481#L797-1 assume !(1 == ~E_3~0); 201482#L802-1 assume !(1 == ~E_4~0); 201553#L807-1 assume !(1 == ~E_5~0); 201554#L812-1 assume !(1 == ~E_6~0); 202279#L1043-1 [2018-11-23 14:59:49,608 INFO L796 eck$LassoCheckResult]: Loop: 202279#L1043-1 assume !false; 205072#L1044 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret1, eval_#t~nondet2, eval_~tmp_ndt_1~0, eval_#t~nondet3, eval_~tmp_ndt_2~0, eval_#t~nondet4, eval_~tmp_ndt_3~0, eval_#t~nondet5, eval_~tmp_ndt_4~0, eval_#t~nondet6, eval_~tmp_ndt_5~0, eval_#t~nondet7, eval_~tmp_ndt_6~0, eval_#t~nondet8, eval_~tmp_ndt_7~0, eval_~tmp~0;havoc eval_~tmp~0; 205071#L649 assume !false; 205070#L556 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~7;havoc exists_runnable_thread_~__retres1~7; 205066#L508 assume !(0 == ~m_st~0); 205067#L512 assume !(0 == ~t1_st~0); 205069#L516 assume !(0 == ~t2_st~0); 205064#L520 assume !(0 == ~t3_st~0); 205065#L524 assume !(0 == ~t4_st~0); 205068#L528 assume !(0 == ~t5_st~0); 205062#L532 assume !(0 == ~t6_st~0);exists_runnable_thread_~__retres1~7 := 0; 205063#L545 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~7; 204749#L546 eval_#t~ret1 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret1;havoc eval_#t~ret1; 204750#L560 assume !(0 != eval_~tmp~0); 205352#L664 start_simulation_~kernel_st~0 := 2; 205351#L458-1 start_simulation_~kernel_st~0 := 3; 205350#L674-2 assume !(0 == ~M_E~0); 205349#L674-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 205348#L679-3 assume !(0 == ~T2_E~0); 205347#L684-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 205346#L689-3 assume !(0 == ~T4_E~0); 205345#L694-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 205344#L699-3 assume !(0 == ~T6_E~0); 205343#L704-3 assume 0 == ~E_M~0;~E_M~0 := 1; 205342#L709-3 assume !(0 == ~E_1~0); 205341#L714-3 assume 0 == ~E_2~0;~E_2~0 := 1; 205340#L719-3 assume !(0 == ~E_3~0); 205339#L724-3 assume 0 == ~E_4~0;~E_4~0 := 1; 205338#L729-3 assume !(0 == ~E_5~0); 205337#L734-3 assume 0 == ~E_6~0;~E_6~0 := 1; 205336#L739-3 havoc activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 205335#L324-24 assume !(1 == ~m_pc~0); 205334#L324-26 is_master_triggered_~__retres1~0 := 0; 205332#L335-8 is_master_triggered_#res := is_master_triggered_~__retres1~0; 205330#L336-8 activate_threads_#t~ret9 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 205328#L839-24 assume !(0 != activate_threads_~tmp~1); 205325#L839-26 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 205322#L343-24 assume !(1 == ~t1_pc~0); 205319#L343-26 is_transmit1_triggered_~__retres1~1 := 0; 205316#L354-8 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 205313#L355-8 activate_threads_#t~ret10 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 205311#L847-24 assume !(0 != activate_threads_~tmp___0~0); 205309#L847-26 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 205307#L362-24 assume !(1 == ~t2_pc~0); 205305#L362-26 is_transmit2_triggered_~__retres1~2 := 0; 205303#L373-8 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 205301#L374-8 activate_threads_#t~ret11 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 205299#L855-24 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 205297#L855-26 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 205295#L381-24 assume !(1 == ~t3_pc~0); 205292#L381-26 is_transmit3_triggered_~__retres1~3 := 0; 205290#L392-8 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 205288#L393-8 activate_threads_#t~ret12 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 205286#L863-24 assume !(0 != activate_threads_~tmp___2~0); 205283#L863-26 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 205281#L400-24 assume !(1 == ~t4_pc~0); 205278#L400-26 is_transmit4_triggered_~__retres1~4 := 0; 205273#L411-8 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 205267#L412-8 activate_threads_#t~ret13 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 205261#L871-24 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 205255#L871-26 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 205250#L419-24 assume !(1 == ~t5_pc~0); 205246#L419-26 is_transmit5_triggered_~__retres1~5 := 0; 205241#L430-8 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 205237#L431-8 activate_threads_#t~ret14 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 205233#L879-24 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 205229#L879-26 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 205224#L438-24 assume !(1 == ~t6_pc~0); 205220#L438-26 is_transmit6_triggered_~__retres1~6 := 0; 205216#L449-8 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 205212#L450-8 activate_threads_#t~ret15 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 205208#L887-24 assume 0 != activate_threads_~tmp___5~0;~t6_st~0 := 0; 205204#L887-26 assume !(1 == ~M_E~0); 205200#L752-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 205195#L757-3 assume !(1 == ~T2_E~0); 205190#L762-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 205186#L767-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 205182#L772-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 205178#L777-3 assume !(1 == ~T6_E~0); 205174#L782-3 assume 1 == ~E_M~0;~E_M~0 := 2; 205170#L787-3 assume !(1 == ~E_1~0); 205166#L792-3 assume 1 == ~E_2~0;~E_2~0 := 2; 205162#L797-3 assume !(1 == ~E_3~0); 205158#L802-3 assume 1 == ~E_4~0;~E_4~0 := 2; 205154#L807-3 assume 1 == ~E_5~0;~E_5~0 := 2; 205150#L812-3 assume 1 == ~E_6~0;~E_6~0 := 2; 205148#L817-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~7;havoc exists_runnable_thread_~__retres1~7; 205135#L508-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7 := 1; 205128#L545-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~7; 205124#L546-1 start_simulation_#t~ret17 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret17;havoc start_simulation_#t~ret17; 205119#L1062 assume !(0 == start_simulation_~tmp~3); 205115#L1062-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret16, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~7;havoc exists_runnable_thread_~__retres1~7; 205111#L508-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7 := 1; 205103#L545-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~7; 205100#L546-2 stop_simulation_#t~ret16 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret16;havoc stop_simulation_#t~ret16; 205095#L1017 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 205092#L1024 stop_simulation_#res := stop_simulation_~__retres2~0; 205085#L1025 start_simulation_#t~ret18 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret18;havoc start_simulation_#t~ret18; 205080#L1075 assume !(0 != start_simulation_~tmp___0~1); 202279#L1043-1 [2018-11-23 14:59:49,608 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 14:59:49,608 INFO L82 PathProgramCache]: Analyzing trace with hash -800641180, now seen corresponding path program 6 times [2018-11-23 14:59:49,608 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 14:59:49,608 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 14:59:49,609 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 14:59:49,609 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 14:59:49,609 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 14:59:49,613 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-23 14:59:49,617 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-23 14:59:49,628 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 14:59:49,629 INFO L82 PathProgramCache]: Analyzing trace with hash -1204047386, now seen corresponding path program 1 times [2018-11-23 14:59:49,629 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 14:59:49,629 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 14:59:49,629 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 14:59:49,630 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-23 14:59:49,630 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 14:59:49,633 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 14:59:49,656 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 14:59:49,657 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 14:59:49,657 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-23 14:59:49,657 INFO L811 eck$LassoCheckResult]: loop already infeasible [2018-11-23 14:59:49,657 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-23 14:59:49,657 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-23 14:59:49,657 INFO L87 Difference]: Start difference. First operand 7814 states and 10639 transitions. cyclomatic complexity: 2841 Second operand 3 states. [2018-11-23 14:59:49,714 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 14:59:49,714 INFO L93 Difference]: Finished difference Result 14550 states and 19515 transitions. [2018-11-23 14:59:49,715 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-23 14:59:49,715 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 14550 states and 19515 transitions. [2018-11-23 14:59:49,747 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 14336 [2018-11-23 14:59:49,768 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 14550 states to 14550 states and 19515 transitions. [2018-11-23 14:59:49,768 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 14550 [2018-11-23 14:59:49,775 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 14550 [2018-11-23 14:59:49,775 INFO L73 IsDeterministic]: Start isDeterministic. Operand 14550 states and 19515 transitions. [2018-11-23 14:59:49,781 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-23 14:59:49,781 INFO L705 BuchiCegarLoop]: Abstraction has 14550 states and 19515 transitions. [2018-11-23 14:59:49,787 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 14550 states and 19515 transitions. [2018-11-23 14:59:49,849 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 14550 to 13870. [2018-11-23 14:59:49,849 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 13870 states. [2018-11-23 14:59:49,863 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 13870 states to 13870 states and 18659 transitions. [2018-11-23 14:59:49,864 INFO L728 BuchiCegarLoop]: Abstraction has 13870 states and 18659 transitions. [2018-11-23 14:59:49,864 INFO L608 BuchiCegarLoop]: Abstraction has 13870 states and 18659 transitions. [2018-11-23 14:59:49,864 INFO L442 BuchiCegarLoop]: ======== Iteration 23============ [2018-11-23 14:59:49,864 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 13870 states and 18659 transitions. [2018-11-23 14:59:49,888 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 13656 [2018-11-23 14:59:49,888 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-23 14:59:49,888 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-23 14:59:49,889 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 14:59:49,889 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 14:59:49,889 INFO L794 eck$LassoCheckResult]: Stem: 224459#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0; 224335#L-1 havoc main_#res;havoc main_~__retres1~8;havoc main_~__retres1~8;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 223863#L1006 havoc start_simulation_#t~ret17, start_simulation_#t~ret18, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 223864#L458 assume 1 == ~m_i~0;~m_st~0 := 0; 224258#L465-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 224259#L470-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 224136#L475-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 224137#L480-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 224186#L485-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 223951#L490-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 223952#L495-1 assume !(0 == ~M_E~0); 224276#L674-1 assume !(0 == ~T1_E~0); 224277#L679-1 assume !(0 == ~T2_E~0); 224154#L684-1 assume !(0 == ~T3_E~0); 224155#L689-1 assume !(0 == ~T4_E~0); 224431#L694-1 assume !(0 == ~T5_E~0); 223994#L699-1 assume !(0 == ~T6_E~0); 223995#L704-1 assume !(0 == ~E_M~0); 223823#L709-1 assume !(0 == ~E_1~0); 223824#L714-1 assume !(0 == ~E_2~0); 223908#L719-1 assume !(0 == ~E_3~0); 223909#L724-1 assume !(0 == ~E_4~0); 224267#L729-1 assume !(0 == ~E_5~0); 224268#L734-1 assume !(0 == ~E_6~0); 224147#L739-1 havoc activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 224031#L324 assume !(1 == ~m_pc~0); 223963#L324-2 is_master_triggered_~__retres1~0 := 0; 224041#L335 is_master_triggered_#res := is_master_triggered_~__retres1~0; 224069#L336 activate_threads_#t~ret9 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 224287#L839 assume !(0 != activate_threads_~tmp~1); 224288#L839-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 224091#L343 assume !(1 == ~t1_pc~0); 224092#L343-2 is_transmit1_triggered_~__retres1~1 := 0; 224086#L354 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 224087#L355 activate_threads_#t~ret10 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 224227#L847 assume !(0 != activate_threads_~tmp___0~0); 224493#L847-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 224403#L362 assume !(1 == ~t2_pc~0); 224349#L362-2 is_transmit2_triggered_~__retres1~2 := 0; 224350#L373 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 224399#L374 activate_threads_#t~ret11 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 224482#L855 assume !(0 != activate_threads_~tmp___1~0); 224504#L855-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 224509#L381 assume !(1 == ~t3_pc~0); 224545#L381-2 is_transmit3_triggered_~__retres1~3 := 0; 224542#L392 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 224543#L393 activate_threads_#t~ret12 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 223876#L863 assume !(0 != activate_threads_~tmp___2~0); 223848#L863-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 223849#L400 assume !(1 == ~t4_pc~0); 223889#L400-2 is_transmit4_triggered_~__retres1~4 := 0; 223890#L411 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 223904#L412 activate_threads_#t~ret13 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 224059#L871 assume !(0 != activate_threads_~tmp___3~0); 224164#L871-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 224168#L419 assume !(1 == ~t5_pc~0); 224074#L419-2 is_transmit5_triggered_~__retres1~5 := 0; 224075#L430 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 224139#L431 activate_threads_#t~ret14 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 224140#L879 assume !(0 != activate_threads_~tmp___4~0); 224416#L879-2 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 224417#L438 assume !(1 == ~t6_pc~0); 224425#L438-2 is_transmit6_triggered_~__retres1~6 := 0; 224426#L449 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 224389#L450 activate_threads_#t~ret15 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 224390#L887 assume !(0 != activate_threads_~tmp___5~0); 224561#L887-2 assume !(1 == ~M_E~0); 223921#L752-1 assume !(1 == ~T1_E~0); 223922#L757-1 assume !(1 == ~T2_E~0); 224263#L762-1 assume !(1 == ~T3_E~0); 224264#L767-1 assume !(1 == ~T4_E~0); 224145#L772-1 assume !(1 == ~T5_E~0); 224146#L777-1 assume !(1 == ~T6_E~0); 224429#L782-1 assume !(1 == ~E_M~0); 223987#L787-1 assume !(1 == ~E_1~0); 223988#L792-1 assume !(1 == ~E_2~0); 223850#L797-1 assume !(1 == ~E_3~0); 223851#L802-1 assume !(1 == ~E_4~0); 223919#L807-1 assume !(1 == ~E_5~0); 223920#L812-1 assume !(1 == ~E_6~0); 224569#L1043-1 [2018-11-23 14:59:49,889 INFO L796 eck$LassoCheckResult]: Loop: 224569#L1043-1 assume !false; 229303#L1044 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret1, eval_#t~nondet2, eval_~tmp_ndt_1~0, eval_#t~nondet3, eval_~tmp_ndt_2~0, eval_#t~nondet4, eval_~tmp_ndt_3~0, eval_#t~nondet5, eval_~tmp_ndt_4~0, eval_#t~nondet6, eval_~tmp_ndt_5~0, eval_#t~nondet7, eval_~tmp_ndt_6~0, eval_#t~nondet8, eval_~tmp_ndt_7~0, eval_~tmp~0;havoc eval_~tmp~0; 229295#L649 assume !false; 229289#L556 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~7;havoc exists_runnable_thread_~__retres1~7; 229282#L508 assume !(0 == ~m_st~0); 229283#L512 assume !(0 == ~t1_st~0); 230039#L516 assume !(0 == ~t2_st~0); 230037#L520 assume !(0 == ~t3_st~0); 230036#L524 assume !(0 == ~t4_st~0); 230033#L528 assume !(0 == ~t5_st~0); 230030#L532 assume !(0 == ~t6_st~0);exists_runnable_thread_~__retres1~7 := 0; 230028#L545 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~7; 230026#L546 eval_#t~ret1 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret1;havoc eval_#t~ret1; 230024#L560 assume !(0 != eval_~tmp~0); 230022#L664 start_simulation_~kernel_st~0 := 2; 230020#L458-1 start_simulation_~kernel_st~0 := 3; 230018#L674-2 assume !(0 == ~M_E~0); 230016#L674-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 230014#L679-3 assume !(0 == ~T2_E~0); 230012#L684-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 230010#L689-3 assume !(0 == ~T4_E~0); 230008#L694-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 230005#L699-3 assume !(0 == ~T6_E~0); 230003#L704-3 assume 0 == ~E_M~0;~E_M~0 := 1; 230001#L709-3 assume !(0 == ~E_1~0); 229999#L714-3 assume 0 == ~E_2~0;~E_2~0 := 1; 229997#L719-3 assume !(0 == ~E_3~0); 229995#L724-3 assume 0 == ~E_4~0;~E_4~0 := 1; 229992#L729-3 assume !(0 == ~E_5~0); 229990#L734-3 assume 0 == ~E_6~0;~E_6~0 := 1; 229988#L739-3 havoc activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 229986#L324-24 assume 1 == ~m_pc~0; 229983#L325-8 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 229982#L335-8 is_master_triggered_#res := is_master_triggered_~__retres1~0; 229980#L336-8 activate_threads_#t~ret9 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 229976#L839-24 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 229975#L839-26 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 229974#L343-24 assume !(1 == ~t1_pc~0); 229973#L343-26 is_transmit1_triggered_~__retres1~1 := 0; 229972#L354-8 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 229971#L355-8 activate_threads_#t~ret10 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 229970#L847-24 assume !(0 != activate_threads_~tmp___0~0); 229969#L847-26 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 229968#L362-24 assume !(1 == ~t2_pc~0); 229967#L362-26 is_transmit2_triggered_~__retres1~2 := 0; 229966#L373-8 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 229965#L374-8 activate_threads_#t~ret11 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 229964#L855-24 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 229963#L855-26 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 229962#L381-24 assume !(1 == ~t3_pc~0); 229960#L381-26 is_transmit3_triggered_~__retres1~3 := 0; 229959#L392-8 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 229958#L393-8 activate_threads_#t~ret12 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 229957#L863-24 assume !(0 != activate_threads_~tmp___2~0); 229956#L863-26 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 229955#L400-24 assume !(1 == ~t4_pc~0); 229954#L400-26 is_transmit4_triggered_~__retres1~4 := 0; 229952#L411-8 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 229950#L412-8 activate_threads_#t~ret13 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 229948#L871-24 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 229947#L871-26 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 229945#L419-24 assume !(1 == ~t5_pc~0); 229943#L419-26 is_transmit5_triggered_~__retres1~5 := 0; 229940#L430-8 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 229938#L431-8 activate_threads_#t~ret14 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 229936#L879-24 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 229934#L879-26 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 229932#L438-24 assume !(1 == ~t6_pc~0); 229929#L438-26 is_transmit6_triggered_~__retres1~6 := 0; 229927#L449-8 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 229925#L450-8 activate_threads_#t~ret15 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 229923#L887-24 assume 0 != activate_threads_~tmp___5~0;~t6_st~0 := 0; 229921#L887-26 assume !(1 == ~M_E~0); 229918#L752-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 229916#L757-3 assume !(1 == ~T2_E~0); 229914#L762-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 229912#L767-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 229910#L772-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 229908#L777-3 assume !(1 == ~T6_E~0); 229906#L782-3 assume 1 == ~E_M~0;~E_M~0 := 2; 229904#L787-3 assume !(1 == ~E_1~0); 229902#L792-3 assume 1 == ~E_2~0;~E_2~0 := 2; 229900#L797-3 assume !(1 == ~E_3~0); 229898#L802-3 assume 1 == ~E_4~0;~E_4~0 := 2; 229896#L807-3 assume 1 == ~E_5~0;~E_5~0 := 2; 229894#L812-3 assume 1 == ~E_6~0;~E_6~0 := 2; 229891#L817-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~7;havoc exists_runnable_thread_~__retres1~7; 229889#L508-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7 := 1; 229887#L545-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~7; 229885#L546-1 start_simulation_#t~ret17 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret17;havoc start_simulation_#t~ret17; 229340#L1062 assume !(0 == start_simulation_~tmp~3); 229337#L1062-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret16, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~7;havoc exists_runnable_thread_~__retres1~7; 229334#L508-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7 := 1; 229332#L545-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~7; 229330#L546-2 stop_simulation_#t~ret16 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret16;havoc stop_simulation_#t~ret16; 229328#L1017 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 229326#L1024 stop_simulation_#res := stop_simulation_~__retres2~0; 229324#L1025 start_simulation_#t~ret18 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret18;havoc start_simulation_#t~ret18; 229322#L1075 assume !(0 != start_simulation_~tmp___0~1); 224569#L1043-1 [2018-11-23 14:59:49,889 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 14:59:49,889 INFO L82 PathProgramCache]: Analyzing trace with hash -800641180, now seen corresponding path program 7 times [2018-11-23 14:59:49,889 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 14:59:49,889 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 14:59:49,890 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 14:59:49,890 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 14:59:49,890 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 14:59:49,894 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-23 14:59:49,899 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-23 14:59:49,913 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 14:59:49,913 INFO L82 PathProgramCache]: Analyzing trace with hash 1307499785, now seen corresponding path program 1 times [2018-11-23 14:59:49,914 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 14:59:49,914 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 14:59:49,914 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 14:59:49,914 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 14:59:49,914 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 14:59:49,919 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 14:59:49,972 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 14:59:49,972 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 14:59:49,972 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-11-23 14:59:49,972 INFO L811 eck$LassoCheckResult]: loop already infeasible [2018-11-23 14:59:49,972 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-11-23 14:59:49,972 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-11-23 14:59:49,973 INFO L87 Difference]: Start difference. First operand 13870 states and 18659 transitions. cyclomatic complexity: 4805 Second operand 5 states. [2018-11-23 14:59:50,205 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 14:59:50,206 INFO L93 Difference]: Finished difference Result 25854 states and 34730 transitions. [2018-11-23 14:59:50,206 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2018-11-23 14:59:50,206 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 25854 states and 34730 transitions. [2018-11-23 14:59:50,266 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 25544 [2018-11-23 14:59:50,306 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 25854 states to 25854 states and 34730 transitions. [2018-11-23 14:59:50,307 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 25854 [2018-11-23 14:59:50,317 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 25854 [2018-11-23 14:59:50,318 INFO L73 IsDeterministic]: Start isDeterministic. Operand 25854 states and 34730 transitions. [2018-11-23 14:59:50,327 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-23 14:59:50,327 INFO L705 BuchiCegarLoop]: Abstraction has 25854 states and 34730 transitions. [2018-11-23 14:59:50,336 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 25854 states and 34730 transitions. [2018-11-23 14:59:50,418 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 25854 to 14206. [2018-11-23 14:59:50,418 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 14206 states. [2018-11-23 14:59:50,433 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 14206 states to 14206 states and 18898 transitions. [2018-11-23 14:59:50,433 INFO L728 BuchiCegarLoop]: Abstraction has 14206 states and 18898 transitions. [2018-11-23 14:59:50,433 INFO L608 BuchiCegarLoop]: Abstraction has 14206 states and 18898 transitions. [2018-11-23 14:59:50,433 INFO L442 BuchiCegarLoop]: ======== Iteration 24============ [2018-11-23 14:59:50,433 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 14206 states and 18898 transitions. [2018-11-23 14:59:50,461 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 13992 [2018-11-23 14:59:50,461 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-23 14:59:50,461 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-23 14:59:50,462 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 14:59:50,462 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 14:59:50,462 INFO L794 eck$LassoCheckResult]: Stem: 264186#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0; 264058#L-1 havoc main_#res;havoc main_~__retres1~8;havoc main_~__retres1~8;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 263600#L1006 havoc start_simulation_#t~ret17, start_simulation_#t~ret18, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 263601#L458 assume 1 == ~m_i~0;~m_st~0 := 0; 263984#L465-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 263985#L470-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 263870#L475-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 263871#L480-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 263915#L485-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 263688#L490-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 263689#L495-1 assume !(0 == ~M_E~0); 264002#L674-1 assume !(0 == ~T1_E~0); 264003#L679-1 assume !(0 == ~T2_E~0); 263886#L684-1 assume !(0 == ~T3_E~0); 263887#L689-1 assume !(0 == ~T4_E~0); 264159#L694-1 assume !(0 == ~T5_E~0); 263730#L699-1 assume !(0 == ~T6_E~0); 263731#L704-1 assume !(0 == ~E_M~0); 263561#L709-1 assume !(0 == ~E_1~0); 263562#L714-1 assume !(0 == ~E_2~0); 263645#L719-1 assume !(0 == ~E_3~0); 263646#L724-1 assume !(0 == ~E_4~0); 263993#L729-1 assume !(0 == ~E_5~0); 263994#L734-1 assume !(0 == ~E_6~0); 263880#L739-1 havoc activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 263768#L324 assume !(1 == ~m_pc~0); 263700#L324-2 is_master_triggered_~__retres1~0 := 0; 263779#L335 is_master_triggered_#res := is_master_triggered_~__retres1~0; 263804#L336 activate_threads_#t~ret9 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 264013#L839 assume !(0 != activate_threads_~tmp~1); 264014#L839-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 263826#L343 assume !(1 == ~t1_pc~0); 263827#L343-2 is_transmit1_triggered_~__retres1~1 := 0; 263821#L354 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 263822#L355 activate_threads_#t~ret10 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 263954#L847 assume !(0 != activate_threads_~tmp___0~0); 264229#L847-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 264125#L362 assume !(1 == ~t2_pc~0); 264072#L362-2 is_transmit2_triggered_~__retres1~2 := 0; 264073#L373 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 264121#L374 activate_threads_#t~ret11 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 264213#L855 assume !(0 != activate_threads_~tmp___1~0); 264239#L855-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 264244#L381 assume !(1 == ~t3_pc~0); 264280#L381-2 is_transmit3_triggered_~__retres1~3 := 0; 264277#L392 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 264278#L393 activate_threads_#t~ret12 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 263613#L863 assume !(0 != activate_threads_~tmp___2~0); 263585#L863-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 263586#L400 assume !(1 == ~t4_pc~0); 263626#L400-2 is_transmit4_triggered_~__retres1~4 := 0; 263627#L411 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 263641#L412 activate_threads_#t~ret13 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 263794#L871 assume !(0 != activate_threads_~tmp___3~0); 263895#L871-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 263899#L419 assume !(1 == ~t5_pc~0); 263809#L419-2 is_transmit5_triggered_~__retres1~5 := 0; 263810#L430 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 263872#L431 activate_threads_#t~ret14 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 263873#L879 assume !(0 != activate_threads_~tmp___4~0); 264137#L879-2 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 264138#L438 assume !(1 == ~t6_pc~0); 264151#L438-2 is_transmit6_triggered_~__retres1~6 := 0; 264152#L449 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 264111#L450 activate_threads_#t~ret15 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 264112#L887 assume !(0 != activate_threads_~tmp___5~0); 264298#L887-2 assume !(1 == ~M_E~0); 263658#L752-1 assume !(1 == ~T1_E~0); 263659#L757-1 assume !(1 == ~T2_E~0); 263989#L762-1 assume !(1 == ~T3_E~0); 263990#L767-1 assume !(1 == ~T4_E~0); 263878#L772-1 assume !(1 == ~T5_E~0); 263879#L777-1 assume !(1 == ~T6_E~0); 264157#L782-1 assume !(1 == ~E_M~0); 263723#L787-1 assume !(1 == ~E_1~0); 263724#L792-1 assume !(1 == ~E_2~0); 263587#L797-1 assume !(1 == ~E_3~0); 263588#L802-1 assume !(1 == ~E_4~0); 263656#L807-1 assume !(1 == ~E_5~0); 263657#L812-1 assume !(1 == ~E_6~0); 264303#L1043-1 [2018-11-23 14:59:50,462 INFO L796 eck$LassoCheckResult]: Loop: 264303#L1043-1 assume !false; 265648#L1044 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret1, eval_#t~nondet2, eval_~tmp_ndt_1~0, eval_#t~nondet3, eval_~tmp_ndt_2~0, eval_#t~nondet4, eval_~tmp_ndt_3~0, eval_#t~nondet5, eval_~tmp_ndt_4~0, eval_#t~nondet6, eval_~tmp_ndt_5~0, eval_#t~nondet7, eval_~tmp_ndt_6~0, eval_#t~nondet8, eval_~tmp_ndt_7~0, eval_~tmp~0;havoc eval_~tmp~0; 265646#L649 assume !false; 265644#L556 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~7;havoc exists_runnable_thread_~__retres1~7; 265641#L508 assume !(0 == ~m_st~0); 265642#L512 assume !(0 == ~t1_st~0); 265924#L516 assume !(0 == ~t2_st~0); 265922#L520 assume !(0 == ~t3_st~0); 265920#L524 assume !(0 == ~t4_st~0); 265918#L528 assume !(0 == ~t5_st~0); 265915#L532 assume !(0 == ~t6_st~0);exists_runnable_thread_~__retres1~7 := 0; 265913#L545 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~7; 265911#L546 eval_#t~ret1 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret1;havoc eval_#t~ret1; 265909#L560 assume !(0 != eval_~tmp~0); 265907#L664 start_simulation_~kernel_st~0 := 2; 265905#L458-1 start_simulation_~kernel_st~0 := 3; 265903#L674-2 assume !(0 == ~M_E~0); 265901#L674-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 265899#L679-3 assume !(0 == ~T2_E~0); 265898#L684-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 265897#L689-3 assume !(0 == ~T4_E~0); 265891#L694-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 265889#L699-3 assume !(0 == ~T6_E~0); 265887#L704-3 assume 0 == ~E_M~0;~E_M~0 := 1; 265884#L709-3 assume !(0 == ~E_1~0); 265882#L714-3 assume 0 == ~E_2~0;~E_2~0 := 1; 265880#L719-3 assume !(0 == ~E_3~0); 265877#L724-3 assume 0 == ~E_4~0;~E_4~0 := 1; 265875#L729-3 assume !(0 == ~E_5~0); 265873#L734-3 assume 0 == ~E_6~0;~E_6~0 := 1; 265872#L739-3 havoc activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 265871#L324-24 assume 1 == ~m_pc~0; 265868#L325-8 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 265866#L335-8 is_master_triggered_#res := is_master_triggered_~__retres1~0; 265865#L336-8 activate_threads_#t~ret9 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 265863#L839-24 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 265861#L839-26 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 265858#L343-24 assume !(1 == ~t1_pc~0); 265856#L343-26 is_transmit1_triggered_~__retres1~1 := 0; 265854#L354-8 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 265849#L355-8 activate_threads_#t~ret10 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 265847#L847-24 assume !(0 != activate_threads_~tmp___0~0); 265845#L847-26 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 265843#L362-24 assume !(1 == ~t2_pc~0); 265841#L362-26 is_transmit2_triggered_~__retres1~2 := 0; 265839#L373-8 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 265837#L374-8 activate_threads_#t~ret11 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 265835#L855-24 assume !(0 != activate_threads_~tmp___1~0); 265833#L855-26 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 265831#L381-24 assume !(1 == ~t3_pc~0); 265828#L381-26 is_transmit3_triggered_~__retres1~3 := 0; 265826#L392-8 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 265824#L393-8 activate_threads_#t~ret12 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 265822#L863-24 assume !(0 != activate_threads_~tmp___2~0); 265819#L863-26 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 265817#L400-24 assume !(1 == ~t4_pc~0); 265815#L400-26 is_transmit4_triggered_~__retres1~4 := 0; 265813#L411-8 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 265811#L412-8 activate_threads_#t~ret13 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 265809#L871-24 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 265807#L871-26 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 265805#L419-24 assume 1 == ~t5_pc~0; 265802#L420-8 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 265800#L430-8 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 265798#L431-8 activate_threads_#t~ret14 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 265796#L879-24 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 265794#L879-26 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 265791#L438-24 assume !(1 == ~t6_pc~0); 265789#L438-26 is_transmit6_triggered_~__retres1~6 := 0; 265787#L449-8 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 265785#L450-8 activate_threads_#t~ret15 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 265783#L887-24 assume 0 != activate_threads_~tmp___5~0;~t6_st~0 := 0; 265781#L887-26 assume !(1 == ~M_E~0); 265779#L752-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 265777#L757-3 assume !(1 == ~T2_E~0); 265775#L762-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 265773#L767-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 265771#L772-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 265769#L777-3 assume !(1 == ~T6_E~0); 265767#L782-3 assume 1 == ~E_M~0;~E_M~0 := 2; 265765#L787-3 assume !(1 == ~E_1~0); 265763#L792-3 assume 1 == ~E_2~0;~E_2~0 := 2; 265761#L797-3 assume !(1 == ~E_3~0); 265759#L802-3 assume 1 == ~E_4~0;~E_4~0 := 2; 265757#L807-3 assume 1 == ~E_5~0;~E_5~0 := 2; 265755#L812-3 assume 1 == ~E_6~0;~E_6~0 := 2; 265753#L817-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~7;havoc exists_runnable_thread_~__retres1~7; 265750#L508-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7 := 1; 265748#L545-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~7; 265746#L546-1 start_simulation_#t~ret17 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret17;havoc start_simulation_#t~ret17; 265744#L1062 assume !(0 == start_simulation_~tmp~3); 265739#L1062-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret16, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~7;havoc exists_runnable_thread_~__retres1~7; 265736#L508-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7 := 1; 265734#L545-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~7; 265732#L546-2 stop_simulation_#t~ret16 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret16;havoc stop_simulation_#t~ret16; 265727#L1017 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 265725#L1024 stop_simulation_#res := stop_simulation_~__retres2~0; 265723#L1025 start_simulation_#t~ret18 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret18;havoc start_simulation_#t~ret18; 265721#L1075 assume !(0 != start_simulation_~tmp___0~1); 264303#L1043-1 [2018-11-23 14:59:50,463 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 14:59:50,463 INFO L82 PathProgramCache]: Analyzing trace with hash -800641180, now seen corresponding path program 8 times [2018-11-23 14:59:50,463 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 14:59:50,463 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 14:59:50,463 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 14:59:50,463 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 14:59:50,464 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 14:59:50,467 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-23 14:59:50,472 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-23 14:59:50,486 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 14:59:50,486 INFO L82 PathProgramCache]: Analyzing trace with hash -1972448152, now seen corresponding path program 1 times [2018-11-23 14:59:50,486 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 14:59:50,486 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 14:59:50,487 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 14:59:50,487 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-23 14:59:50,487 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 14:59:50,492 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 14:59:50,535 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 14:59:50,535 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 14:59:50,535 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-11-23 14:59:50,536 INFO L811 eck$LassoCheckResult]: loop already infeasible [2018-11-23 14:59:50,536 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-11-23 14:59:50,536 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-11-23 14:59:50,536 INFO L87 Difference]: Start difference. First operand 14206 states and 18898 transitions. cyclomatic complexity: 4708 Second operand 5 states. [2018-11-23 14:59:50,717 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 14:59:50,717 INFO L93 Difference]: Finished difference Result 24782 states and 33117 transitions. [2018-11-23 14:59:50,718 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2018-11-23 14:59:50,718 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 24782 states and 33117 transitions. [2018-11-23 14:59:50,787 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 24472 [2018-11-23 14:59:50,832 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 24782 states to 24782 states and 33117 transitions. [2018-11-23 14:59:50,832 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 24782 [2018-11-23 14:59:50,843 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 24782 [2018-11-23 14:59:50,844 INFO L73 IsDeterministic]: Start isDeterministic. Operand 24782 states and 33117 transitions. [2018-11-23 14:59:50,932 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-23 14:59:50,932 INFO L705 BuchiCegarLoop]: Abstraction has 24782 states and 33117 transitions. [2018-11-23 14:59:50,937 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 24782 states and 33117 transitions. [2018-11-23 14:59:51,004 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 24782 to 14542. [2018-11-23 14:59:51,004 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 14542 states. [2018-11-23 14:59:51,017 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 14542 states to 14542 states and 19137 transitions. [2018-11-23 14:59:51,017 INFO L728 BuchiCegarLoop]: Abstraction has 14542 states and 19137 transitions. [2018-11-23 14:59:51,017 INFO L608 BuchiCegarLoop]: Abstraction has 14542 states and 19137 transitions. [2018-11-23 14:59:51,017 INFO L442 BuchiCegarLoop]: ======== Iteration 25============ [2018-11-23 14:59:51,017 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 14542 states and 19137 transitions. [2018-11-23 14:59:51,042 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 14328 [2018-11-23 14:59:51,042 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-23 14:59:51,042 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-23 14:59:51,043 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 14:59:51,043 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 14:59:51,043 INFO L794 eck$LassoCheckResult]: Stem: 303193#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0; 303076#L-1 havoc main_#res;havoc main_~__retres1~8;havoc main_~__retres1~8;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 302610#L1006 havoc start_simulation_#t~ret17, start_simulation_#t~ret18, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 302611#L458 assume 1 == ~m_i~0;~m_st~0 := 0; 302998#L465-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 302999#L470-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 302883#L475-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 302884#L480-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 302929#L485-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 302703#L490-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 302704#L495-1 assume !(0 == ~M_E~0); 303013#L674-1 assume !(0 == ~T1_E~0); 303014#L679-1 assume !(0 == ~T2_E~0); 302900#L684-1 assume !(0 == ~T3_E~0); 302901#L689-1 assume !(0 == ~T4_E~0); 303165#L694-1 assume !(0 == ~T5_E~0); 302747#L699-1 assume !(0 == ~T6_E~0); 302748#L704-1 assume !(0 == ~E_M~0); 302563#L709-1 assume !(0 == ~E_1~0); 302564#L714-1 assume !(0 == ~E_2~0); 302660#L719-1 assume !(0 == ~E_3~0); 302661#L724-1 assume !(0 == ~E_4~0); 303006#L729-1 assume !(0 == ~E_5~0); 303007#L734-1 assume !(0 == ~E_6~0); 302893#L739-1 havoc activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 302782#L324 assume !(1 == ~m_pc~0); 302716#L324-2 is_master_triggered_~__retres1~0 := 0; 302793#L335 is_master_triggered_#res := is_master_triggered_~__retres1~0; 302818#L336 activate_threads_#t~ret9 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 303024#L839 assume !(0 != activate_threads_~tmp~1); 303025#L839-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 302838#L343 assume !(1 == ~t1_pc~0); 302839#L343-2 is_transmit1_triggered_~__retres1~1 := 0; 302833#L354 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 302834#L355 activate_threads_#t~ret10 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 302969#L847 assume !(0 != activate_threads_~tmp___0~0); 303229#L847-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 303142#L362 assume !(1 == ~t2_pc~0); 303090#L362-2 is_transmit2_triggered_~__retres1~2 := 0; 303091#L373 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 303138#L374 activate_threads_#t~ret11 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 303217#L855 assume !(0 != activate_threads_~tmp___1~0); 303238#L855-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 303243#L381 assume !(1 == ~t3_pc~0); 303279#L381-2 is_transmit3_triggered_~__retres1~3 := 0; 303276#L392 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 303277#L393 activate_threads_#t~ret12 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 302622#L863 assume !(0 != activate_threads_~tmp___2~0); 302591#L863-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 302592#L400 assume !(1 == ~t4_pc~0); 302638#L400-2 is_transmit4_triggered_~__retres1~4 := 0; 302639#L411 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 302656#L412 activate_threads_#t~ret13 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 302810#L871 assume !(0 != activate_threads_~tmp___3~0); 302909#L871-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 302913#L419 assume !(1 == ~t5_pc~0); 302821#L419-2 is_transmit5_triggered_~__retres1~5 := 0; 302822#L430 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 302885#L431 activate_threads_#t~ret14 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 302886#L879 assume !(0 != activate_threads_~tmp___4~0); 303153#L879-2 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 303154#L438 assume !(1 == ~t6_pc~0); 303159#L438-2 is_transmit6_triggered_~__retres1~6 := 0; 303160#L449 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 303128#L450 activate_threads_#t~ret15 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 303129#L887 assume !(0 != activate_threads_~tmp___5~0); 303294#L887-2 assume !(1 == ~M_E~0); 302673#L752-1 assume !(1 == ~T1_E~0); 302674#L757-1 assume !(1 == ~T2_E~0); 303002#L762-1 assume !(1 == ~T3_E~0); 303003#L767-1 assume !(1 == ~T4_E~0); 302891#L772-1 assume !(1 == ~T5_E~0); 302892#L777-1 assume !(1 == ~T6_E~0); 303163#L782-1 assume !(1 == ~E_M~0); 302740#L787-1 assume !(1 == ~E_1~0); 302741#L792-1 assume !(1 == ~E_2~0); 302593#L797-1 assume !(1 == ~E_3~0); 302594#L802-1 assume !(1 == ~E_4~0); 302671#L807-1 assume !(1 == ~E_5~0); 302672#L812-1 assume !(1 == ~E_6~0); 303303#L1043-1 [2018-11-23 14:59:51,043 INFO L796 eck$LassoCheckResult]: Loop: 303303#L1043-1 assume !false; 308362#L1044 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret1, eval_#t~nondet2, eval_~tmp_ndt_1~0, eval_#t~nondet3, eval_~tmp_ndt_2~0, eval_#t~nondet4, eval_~tmp_ndt_3~0, eval_#t~nondet5, eval_~tmp_ndt_4~0, eval_#t~nondet6, eval_~tmp_ndt_5~0, eval_#t~nondet7, eval_~tmp_ndt_6~0, eval_#t~nondet8, eval_~tmp_ndt_7~0, eval_~tmp~0;havoc eval_~tmp~0; 308360#L649 assume !false; 308358#L556 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~7;havoc exists_runnable_thread_~__retres1~7; 308355#L508 assume !(0 == ~m_st~0); 308356#L512 assume !(0 == ~t1_st~0); 308685#L516 assume !(0 == ~t2_st~0); 308683#L520 assume !(0 == ~t3_st~0); 308682#L524 assume !(0 == ~t4_st~0); 308681#L528 assume !(0 == ~t5_st~0); 308678#L532 assume !(0 == ~t6_st~0);exists_runnable_thread_~__retres1~7 := 0; 308677#L545 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~7; 308676#L546 eval_#t~ret1 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret1;havoc eval_#t~ret1; 308675#L560 assume !(0 != eval_~tmp~0); 308671#L664 start_simulation_~kernel_st~0 := 2; 308669#L458-1 start_simulation_~kernel_st~0 := 3; 308667#L674-2 assume !(0 == ~M_E~0); 308665#L674-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 308660#L679-3 assume !(0 == ~T2_E~0); 308658#L684-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 308656#L689-3 assume !(0 == ~T4_E~0); 308654#L694-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 308652#L699-3 assume !(0 == ~T6_E~0); 308650#L704-3 assume 0 == ~E_M~0;~E_M~0 := 1; 308648#L709-3 assume !(0 == ~E_1~0); 308646#L714-3 assume 0 == ~E_2~0;~E_2~0 := 1; 308644#L719-3 assume !(0 == ~E_3~0); 308642#L724-3 assume 0 == ~E_4~0;~E_4~0 := 1; 308640#L729-3 assume !(0 == ~E_5~0); 308638#L734-3 assume 0 == ~E_6~0;~E_6~0 := 1; 308636#L739-3 havoc activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 308634#L324-24 assume 1 == ~m_pc~0; 308630#L325-8 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 308628#L335-8 is_master_triggered_#res := is_master_triggered_~__retres1~0; 308626#L336-8 activate_threads_#t~ret9 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 308623#L839-24 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 308621#L839-26 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 308619#L343-24 assume !(1 == ~t1_pc~0); 308617#L343-26 is_transmit1_triggered_~__retres1~1 := 0; 308615#L354-8 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 308613#L355-8 activate_threads_#t~ret10 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 308611#L847-24 assume !(0 != activate_threads_~tmp___0~0); 308609#L847-26 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 308607#L362-24 assume !(1 == ~t2_pc~0); 308605#L362-26 is_transmit2_triggered_~__retres1~2 := 0; 308602#L373-8 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 308600#L374-8 activate_threads_#t~ret11 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 308598#L855-24 assume !(0 != activate_threads_~tmp___1~0); 308596#L855-26 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 308594#L381-24 assume !(1 == ~t3_pc~0); 308591#L381-26 is_transmit3_triggered_~__retres1~3 := 0; 308589#L392-8 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 308587#L393-8 activate_threads_#t~ret12 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 308585#L863-24 assume !(0 != activate_threads_~tmp___2~0); 308583#L863-26 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 308581#L400-24 assume !(1 == ~t4_pc~0); 308579#L400-26 is_transmit4_triggered_~__retres1~4 := 0; 308577#L411-8 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 308575#L412-8 activate_threads_#t~ret13 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 308573#L871-24 assume !(0 != activate_threads_~tmp___3~0); 308571#L871-26 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 308569#L419-24 assume 1 == ~t5_pc~0; 308566#L420-8 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 308564#L430-8 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 308562#L431-8 activate_threads_#t~ret14 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 308560#L879-24 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 308558#L879-26 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 308556#L438-24 assume !(1 == ~t6_pc~0); 308555#L438-26 is_transmit6_triggered_~__retres1~6 := 0; 308554#L449-8 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 308552#L450-8 activate_threads_#t~ret15 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 308550#L887-24 assume 0 != activate_threads_~tmp___5~0;~t6_st~0 := 0; 308547#L887-26 assume !(1 == ~M_E~0); 308545#L752-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 308543#L757-3 assume !(1 == ~T2_E~0); 308540#L762-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 308538#L767-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 308536#L772-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 308535#L777-3 assume !(1 == ~T6_E~0); 308534#L782-3 assume 1 == ~E_M~0;~E_M~0 := 2; 308532#L787-3 assume !(1 == ~E_1~0); 308531#L792-3 assume 1 == ~E_2~0;~E_2~0 := 2; 308530#L797-3 assume !(1 == ~E_3~0); 308529#L802-3 assume 1 == ~E_4~0;~E_4~0 := 2; 308525#L807-3 assume 1 == ~E_5~0;~E_5~0 := 2; 308523#L812-3 assume 1 == ~E_6~0;~E_6~0 := 2; 308521#L817-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~7;havoc exists_runnable_thread_~__retres1~7; 308518#L508-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7 := 1; 308513#L545-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~7; 308511#L546-1 start_simulation_#t~ret17 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret17;havoc start_simulation_#t~ret17; 308508#L1062 assume !(0 == start_simulation_~tmp~3); 308505#L1062-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret16, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~7;havoc exists_runnable_thread_~__retres1~7; 308502#L508-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7 := 1; 308500#L545-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~7; 308498#L546-2 stop_simulation_#t~ret16 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret16;havoc stop_simulation_#t~ret16; 308496#L1017 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 308494#L1024 stop_simulation_#res := stop_simulation_~__retres2~0; 308492#L1025 start_simulation_#t~ret18 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret18;havoc start_simulation_#t~ret18; 308490#L1075 assume !(0 != start_simulation_~tmp___0~1); 303303#L1043-1 [2018-11-23 14:59:51,043 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 14:59:51,043 INFO L82 PathProgramCache]: Analyzing trace with hash -800641180, now seen corresponding path program 9 times [2018-11-23 14:59:51,043 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 14:59:51,044 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 14:59:51,044 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 14:59:51,044 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 14:59:51,044 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 14:59:51,047 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-23 14:59:51,052 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-23 14:59:51,066 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 14:59:51,067 INFO L82 PathProgramCache]: Analyzing trace with hash 950711846, now seen corresponding path program 1 times [2018-11-23 14:59:51,067 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 14:59:51,067 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 14:59:51,067 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 14:59:51,068 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-23 14:59:51,068 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 14:59:51,075 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 14:59:51,130 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 14:59:51,130 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 14:59:51,130 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-11-23 14:59:51,130 INFO L811 eck$LassoCheckResult]: loop already infeasible [2018-11-23 14:59:51,130 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-11-23 14:59:51,130 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-11-23 14:59:51,131 INFO L87 Difference]: Start difference. First operand 14542 states and 19137 transitions. cyclomatic complexity: 4611 Second operand 5 states. [2018-11-23 14:59:51,282 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 14:59:51,282 INFO L93 Difference]: Finished difference Result 23782 states and 31400 transitions. [2018-11-23 14:59:51,283 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2018-11-23 14:59:51,284 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 23782 states and 31400 transitions. [2018-11-23 14:59:51,335 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 23472 [2018-11-23 14:59:51,370 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 23782 states to 23782 states and 31400 transitions. [2018-11-23 14:59:51,370 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 23782 [2018-11-23 14:59:51,381 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 23782 [2018-11-23 14:59:51,381 INFO L73 IsDeterministic]: Start isDeterministic. Operand 23782 states and 31400 transitions. [2018-11-23 14:59:51,391 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-23 14:59:51,391 INFO L705 BuchiCegarLoop]: Abstraction has 23782 states and 31400 transitions. [2018-11-23 14:59:51,400 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 23782 states and 31400 transitions. [2018-11-23 14:59:51,482 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 23782 to 14878. [2018-11-23 14:59:51,483 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 14878 states. [2018-11-23 14:59:51,497 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 14878 states to 14878 states and 19376 transitions. [2018-11-23 14:59:51,497 INFO L728 BuchiCegarLoop]: Abstraction has 14878 states and 19376 transitions. [2018-11-23 14:59:51,497 INFO L608 BuchiCegarLoop]: Abstraction has 14878 states and 19376 transitions. [2018-11-23 14:59:51,497 INFO L442 BuchiCegarLoop]: ======== Iteration 26============ [2018-11-23 14:59:51,497 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 14878 states and 19376 transitions. [2018-11-23 14:59:51,523 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 14664 [2018-11-23 14:59:51,523 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-23 14:59:51,523 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-23 14:59:51,524 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 14:59:51,524 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 14:59:51,525 INFO L794 eck$LassoCheckResult]: Stem: 341556#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0; 341410#L-1 havoc main_#res;havoc main_~__retres1~8;havoc main_~__retres1~8;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 340940#L1006 havoc start_simulation_#t~ret17, start_simulation_#t~ret18, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 340941#L458 assume 1 == ~m_i~0;~m_st~0 := 0; 341331#L465-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 341332#L470-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 341218#L475-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 341219#L480-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 341263#L485-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 341033#L490-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 341034#L495-1 assume !(0 == ~M_E~0); 341349#L674-1 assume !(0 == ~T1_E~0); 341350#L679-1 assume !(0 == ~T2_E~0); 341236#L684-1 assume !(0 == ~T3_E~0); 341237#L689-1 assume !(0 == ~T4_E~0); 341528#L694-1 assume !(0 == ~T5_E~0); 341073#L699-1 assume !(0 == ~T6_E~0); 341074#L704-1 assume !(0 == ~E_M~0); 340901#L709-1 assume !(0 == ~E_1~0); 340902#L714-1 assume !(0 == ~E_2~0); 340987#L719-1 assume !(0 == ~E_3~0); 340988#L724-1 assume !(0 == ~E_4~0); 341339#L729-1 assume !(0 == ~E_5~0); 341340#L734-1 assume !(0 == ~E_6~0); 341229#L739-1 havoc activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 341114#L324 assume !(1 == ~m_pc~0); 341043#L324-2 is_master_triggered_~__retres1~0 := 0; 341125#L335 is_master_triggered_#res := is_master_triggered_~__retres1~0; 341039#L336 activate_threads_#t~ret9 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 341040#L839 assume !(0 != activate_threads_~tmp~1); 341359#L839-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 341173#L343 assume !(1 == ~t1_pc~0); 341174#L343-2 is_transmit1_triggered_~__retres1~1 := 0; 341171#L354 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 341172#L355 activate_threads_#t~ret10 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 341303#L847 assume !(0 != activate_threads_~tmp___0~0); 341590#L847-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 341473#L362 assume !(1 == ~t2_pc~0); 341419#L362-2 is_transmit2_triggered_~__retres1~2 := 0; 341420#L373 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 341472#L374 activate_threads_#t~ret11 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 341578#L855 assume !(0 != activate_threads_~tmp___1~0); 341599#L855-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 341604#L381 assume !(1 == ~t3_pc~0); 341644#L381-2 is_transmit3_triggered_~__retres1~3 := 0; 341642#L392 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 341643#L393 activate_threads_#t~ret12 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 340954#L863 assume !(0 != activate_threads_~tmp___2~0); 340925#L863-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 340926#L400 assume !(1 == ~t4_pc~0); 340966#L400-2 is_transmit4_triggered_~__retres1~4 := 0; 340967#L411 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 340983#L412 activate_threads_#t~ret13 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 341143#L871 assume !(0 != activate_threads_~tmp___3~0); 341244#L871-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 341248#L419 assume !(1 == ~t5_pc~0); 341156#L419-2 is_transmit5_triggered_~__retres1~5 := 0; 341157#L430 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 341220#L431 activate_threads_#t~ret14 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 341221#L879 assume !(0 != activate_threads_~tmp___4~0); 341496#L879-2 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 341497#L438 assume !(1 == ~t6_pc~0); 341517#L438-2 is_transmit6_triggered_~__retres1~6 := 0; 341518#L449 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 341458#L450 activate_threads_#t~ret15 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 341459#L887 assume !(0 != activate_threads_~tmp___5~0); 341664#L887-2 assume !(1 == ~M_E~0); 341000#L752-1 assume !(1 == ~T1_E~0); 341001#L757-1 assume !(1 == ~T2_E~0); 341335#L762-1 assume !(1 == ~T3_E~0); 341336#L767-1 assume !(1 == ~T4_E~0); 341226#L772-1 assume !(1 == ~T5_E~0); 341227#L777-1 assume !(1 == ~T6_E~0); 341526#L782-1 assume !(1 == ~E_M~0); 341068#L787-1 assume !(1 == ~E_1~0); 341069#L792-1 assume !(1 == ~E_2~0); 340930#L797-1 assume !(1 == ~E_3~0); 340931#L802-1 assume !(1 == ~E_4~0); 340998#L807-1 assume !(1 == ~E_5~0); 340999#L812-1 assume !(1 == ~E_6~0); 341668#L1043-1 [2018-11-23 14:59:51,525 INFO L796 eck$LassoCheckResult]: Loop: 341668#L1043-1 assume !false; 346949#L1044 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret1, eval_#t~nondet2, eval_~tmp_ndt_1~0, eval_#t~nondet3, eval_~tmp_ndt_2~0, eval_#t~nondet4, eval_~tmp_ndt_3~0, eval_#t~nondet5, eval_~tmp_ndt_4~0, eval_#t~nondet6, eval_~tmp_ndt_5~0, eval_#t~nondet7, eval_~tmp_ndt_6~0, eval_#t~nondet8, eval_~tmp_ndt_7~0, eval_~tmp~0;havoc eval_~tmp~0; 346944#L649 assume !false; 346939#L556 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~7;havoc exists_runnable_thread_~__retres1~7; 346932#L508 assume !(0 == ~m_st~0); 346933#L512 assume !(0 == ~t1_st~0); 347657#L516 assume !(0 == ~t2_st~0); 347655#L520 assume !(0 == ~t3_st~0); 347653#L524 assume !(0 == ~t4_st~0); 347651#L528 assume !(0 == ~t5_st~0); 347648#L532 assume !(0 == ~t6_st~0);exists_runnable_thread_~__retres1~7 := 0; 347646#L545 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~7; 347644#L546 eval_#t~ret1 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret1;havoc eval_#t~ret1; 347642#L560 assume !(0 != eval_~tmp~0); 347635#L664 start_simulation_~kernel_st~0 := 2; 347630#L458-1 start_simulation_~kernel_st~0 := 3; 347625#L674-2 assume !(0 == ~M_E~0); 347620#L674-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 347615#L679-3 assume !(0 == ~T2_E~0); 347610#L684-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 347605#L689-3 assume !(0 == ~T4_E~0); 347601#L694-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 347596#L699-3 assume !(0 == ~T6_E~0); 347589#L704-3 assume 0 == ~E_M~0;~E_M~0 := 1; 347583#L709-3 assume !(0 == ~E_1~0); 347576#L714-3 assume 0 == ~E_2~0;~E_2~0 := 1; 347571#L719-3 assume !(0 == ~E_3~0); 347566#L724-3 assume 0 == ~E_4~0;~E_4~0 := 1; 347559#L729-3 assume !(0 == ~E_5~0); 347554#L734-3 assume 0 == ~E_6~0;~E_6~0 := 1; 347549#L739-3 havoc activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 347544#L324-24 assume 1 == ~m_pc~0; 347538#L325-8 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 347533#L335-8 is_master_triggered_#res := is_master_triggered_~__retres1~0; 347528#L336-8 activate_threads_#t~ret9 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 347521#L839-24 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 347515#L839-26 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 347508#L343-24 assume !(1 == ~t1_pc~0); 347502#L343-26 is_transmit1_triggered_~__retres1~1 := 0; 347497#L354-8 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 347492#L355-8 activate_threads_#t~ret10 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 347486#L847-24 assume !(0 != activate_threads_~tmp___0~0); 347481#L847-26 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 347476#L362-24 assume !(1 == ~t2_pc~0); 347470#L362-26 is_transmit2_triggered_~__retres1~2 := 0; 347464#L373-8 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 347458#L374-8 activate_threads_#t~ret11 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 347452#L855-24 assume !(0 != activate_threads_~tmp___1~0); 347446#L855-26 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 347440#L381-24 assume !(1 == ~t3_pc~0); 347431#L381-26 is_transmit3_triggered_~__retres1~3 := 0; 347425#L392-8 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 347419#L393-8 activate_threads_#t~ret12 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 347415#L863-24 assume !(0 != activate_threads_~tmp___2~0); 347412#L863-26 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 347410#L400-24 assume !(1 == ~t4_pc~0); 347407#L400-26 is_transmit4_triggered_~__retres1~4 := 0; 347404#L411-8 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 347398#L412-8 activate_threads_#t~ret13 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 347390#L871-24 assume !(0 != activate_threads_~tmp___3~0); 347214#L871-26 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 347211#L419-24 assume 1 == ~t5_pc~0; 347207#L420-8 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 347203#L430-8 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 347197#L431-8 activate_threads_#t~ret14 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 347193#L879-24 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 347189#L879-26 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 347186#L438-24 assume !(1 == ~t6_pc~0); 347185#L438-26 is_transmit6_triggered_~__retres1~6 := 0; 347176#L449-8 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 347167#L450-8 activate_threads_#t~ret15 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 347159#L887-24 assume !(0 != activate_threads_~tmp___5~0); 347151#L887-26 assume !(1 == ~M_E~0); 347141#L752-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 347134#L757-3 assume !(1 == ~T2_E~0); 347127#L762-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 347120#L767-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 347114#L772-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 347107#L777-3 assume !(1 == ~T6_E~0); 347101#L782-3 assume 1 == ~E_M~0;~E_M~0 := 2; 347095#L787-3 assume !(1 == ~E_1~0); 347088#L792-3 assume 1 == ~E_2~0;~E_2~0 := 2; 347082#L797-3 assume !(1 == ~E_3~0); 347076#L802-3 assume 1 == ~E_4~0;~E_4~0 := 2; 347069#L807-3 assume 1 == ~E_5~0;~E_5~0 := 2; 347062#L812-3 assume 1 == ~E_6~0;~E_6~0 := 2; 347055#L817-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~7;havoc exists_runnable_thread_~__retres1~7; 347046#L508-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7 := 1; 347037#L545-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~7; 347030#L546-1 start_simulation_#t~ret17 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret17;havoc start_simulation_#t~ret17; 346979#L1062 assume !(0 == start_simulation_~tmp~3); 346976#L1062-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret16, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~7;havoc exists_runnable_thread_~__retres1~7; 346973#L508-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7 := 1; 346971#L545-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~7; 346969#L546-2 stop_simulation_#t~ret16 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret16;havoc stop_simulation_#t~ret16; 346967#L1017 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 346965#L1024 stop_simulation_#res := stop_simulation_~__retres2~0; 346963#L1025 start_simulation_#t~ret18 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret18;havoc start_simulation_#t~ret18; 346961#L1075 assume !(0 != start_simulation_~tmp___0~1); 341668#L1043-1 [2018-11-23 14:59:51,525 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 14:59:51,525 INFO L82 PathProgramCache]: Analyzing trace with hash -800641180, now seen corresponding path program 10 times [2018-11-23 14:59:51,525 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 14:59:51,525 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 14:59:51,526 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 14:59:51,526 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 14:59:51,526 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 14:59:51,530 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-23 14:59:51,534 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-23 14:59:51,548 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 14:59:51,549 INFO L82 PathProgramCache]: Analyzing trace with hash 441238756, now seen corresponding path program 1 times [2018-11-23 14:59:51,549 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 14:59:51,549 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 14:59:51,549 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 14:59:51,549 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-23 14:59:51,550 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 14:59:51,553 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-23 14:59:51,558 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-23 14:59:51,568 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 14:59:51,568 INFO L82 PathProgramCache]: Analyzing trace with hash -630875487, now seen corresponding path program 1 times [2018-11-23 14:59:51,568 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 14:59:51,568 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 14:59:51,569 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 14:59:51,569 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 14:59:51,569 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 14:59:51,573 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 14:59:51,601 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 14:59:51,601 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 14:59:51,601 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-23 14:59:52,239 WARN L180 SmtUtils]: Spent 629.00 ms on a formula simplification. DAG size of input: 215 DAG size of output: 196 [2018-11-23 14:59:52,415 WARN L180 SmtUtils]: Spent 168.00 ms on a formula simplification that was a NOOP. DAG size: 170 [2018-11-23 14:59:52,423 INFO L216 LassoAnalysis]: Preferences: [2018-11-23 14:59:52,424 INFO L124 ssoRankerPreferences]: Compute integeral hull: false [2018-11-23 14:59:52,424 INFO L125 ssoRankerPreferences]: Enable LassoPartitioneer: true [2018-11-23 14:59:52,425 INFO L126 ssoRankerPreferences]: Term annotations enabled: false [2018-11-23 14:59:52,425 INFO L127 ssoRankerPreferences]: Use exernal solver: true [2018-11-23 14:59:52,425 INFO L128 ssoRankerPreferences]: SMT solver command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2018-11-23 14:59:52,425 INFO L129 ssoRankerPreferences]: Dump SMT script to file: false [2018-11-23 14:59:52,425 INFO L130 ssoRankerPreferences]: Path of dumped script: [2018-11-23 14:59:52,425 INFO L131 ssoRankerPreferences]: Filename of dumped script: token_ring.06_true-unreach-call_false-termination.cil.c_Iteration26_Loop [2018-11-23 14:59:52,425 INFO L132 ssoRankerPreferences]: MapElimAlgo: Frank [2018-11-23 14:59:52,425 INFO L282 LassoAnalysis]: Starting lasso preprocessing... [2018-11-23 14:59:52,447 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 14:59:52,457 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 14:59:52,460 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 14:59:52,467 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 14:59:52,470 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 14:59:52,480 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 14:59:52,482 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 14:59:52,486 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 14:59:52,488 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 14:59:52,489 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 14:59:52,490 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 14:59:52,491 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 14:59:52,492 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 14:59:52,493 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 14:59:52,495 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 14:59:52,496 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 14:59:52,497 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 14:59:52,500 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 14:59:52,501 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 14:59:52,504 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 14:59:52,505 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 14:59:52,508 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 14:59:52,510 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 14:59:52,513 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 14:59:52,515 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 14:59:52,517 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 14:59:52,520 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 14:59:52,522 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 14:59:52,524 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 14:59:52,526 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 14:59:52,527 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 14:59:52,530 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 14:59:52,534 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 14:59:52,535 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 14:59:52,536 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 14:59:52,541 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 14:59:52,542 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 14:59:52,547 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 14:59:52,554 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 14:59:52,556 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 14:59:52,557 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 14:59:52,560 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 14:59:52,562 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 14:59:52,564 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 14:59:52,566 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 14:59:52,567 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 14:59:52,569 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 14:59:52,570 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 14:59:52,572 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 14:59:52,574 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 14:59:52,577 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 14:59:52,581 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 14:59:52,585 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 14:59:52,586 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 14:59:52,589 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 14:59:52,590 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 14:59:52,592 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 14:59:52,595 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 14:59:52,598 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 14:59:52,599 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 14:59:52,601 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 14:59:52,601 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 14:59:52,604 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 14:59:52,606 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 14:59:52,608 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 14:59:52,610 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 14:59:52,612 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 14:59:52,995 INFO L300 LassoAnalysis]: Preprocessing complete. [2018-11-23 14:59:52,996 INFO L412 LassoAnalysis]: Checking for nontermination... No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_14a495c8-4465-4fa3-a7af-a201bd4dc887/bin-2019/uautomizer/z3 Starting monitored process 2 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 2 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2018-11-23 14:59:53,009 INFO L151 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2018-11-23 14:59:53,009 INFO L163 nArgumentSynthesizer]: Using integer mode. [2018-11-23 14:59:53,017 INFO L445 LassoAnalysis]: Proved nontermination for one component. [2018-11-23 14:59:53,017 INFO L448 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {ULTIMATE.start_eval_#t~ret1=0} Honda state: {ULTIMATE.start_eval_#t~ret1=0} Generalized eigenvectors: [] Lambdas: [] Nus: [] No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_14a495c8-4465-4fa3-a7af-a201bd4dc887/bin-2019/uautomizer/z3 Starting monitored process 3 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 3 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2018-11-23 14:59:53,036 INFO L151 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2018-11-23 14:59:53,036 INFO L163 nArgumentSynthesizer]: Using integer mode. [2018-11-23 14:59:53,038 INFO L445 LassoAnalysis]: Proved nontermination for one component. [2018-11-23 14:59:53,038 INFO L448 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {ULTIMATE.start_start_simulation_#t~ret18=0} Honda state: {ULTIMATE.start_start_simulation_#t~ret18=0} Generalized eigenvectors: [] Lambdas: [] Nus: [] No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_14a495c8-4465-4fa3-a7af-a201bd4dc887/bin-2019/uautomizer/z3 Starting monitored process 4 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 4 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2018-11-23 14:59:53,061 INFO L151 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2018-11-23 14:59:53,061 INFO L163 nArgumentSynthesizer]: Using integer mode. [2018-11-23 14:59:53,072 INFO L445 LassoAnalysis]: Proved nontermination for one component. [2018-11-23 14:59:53,072 INFO L448 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {ULTIMATE.start_is_transmit6_triggered_#res=0, ULTIMATE.start_is_transmit6_triggered_~__retres1~6=0, ULTIMATE.start_activate_threads_~tmp___5~0=0} Honda state: {ULTIMATE.start_is_transmit6_triggered_#res=0, ULTIMATE.start_is_transmit6_triggered_~__retres1~6=0, ULTIMATE.start_activate_threads_~tmp___5~0=0} Generalized eigenvectors: [] Lambdas: [] Nus: [] No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_14a495c8-4465-4fa3-a7af-a201bd4dc887/bin-2019/uautomizer/z3 Starting monitored process 5 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 5 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2018-11-23 14:59:53,097 INFO L151 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2018-11-23 14:59:53,097 INFO L163 nArgumentSynthesizer]: Using integer mode. [2018-11-23 14:59:53,099 INFO L445 LassoAnalysis]: Proved nontermination for one component. [2018-11-23 14:59:53,099 INFO L448 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {ULTIMATE.start_eval_~tmp_ndt_7~0=0} Honda state: {ULTIMATE.start_eval_~tmp_ndt_7~0=0} Generalized eigenvectors: [] Lambdas: [] Nus: [] No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_14a495c8-4465-4fa3-a7af-a201bd4dc887/bin-2019/uautomizer/z3 Starting monitored process 6 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 6 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2018-11-23 14:59:53,118 INFO L151 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2018-11-23 14:59:53,118 INFO L163 nArgumentSynthesizer]: Using integer mode. [2018-11-23 14:59:53,124 INFO L445 LassoAnalysis]: Proved nontermination for one component. [2018-11-23 14:59:53,124 INFO L448 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {ULTIMATE.start_stop_simulation_~__retres2~0=0, ULTIMATE.start_start_simulation_~tmp___0~1=0, ULTIMATE.start_stop_simulation_#res=0} Honda state: {ULTIMATE.start_stop_simulation_~__retres2~0=0, ULTIMATE.start_start_simulation_~tmp___0~1=0, ULTIMATE.start_stop_simulation_#res=0} Generalized eigenvectors: [] Lambdas: [] Nus: [] No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_14a495c8-4465-4fa3-a7af-a201bd4dc887/bin-2019/uautomizer/z3 Starting monitored process 7 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 7 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2018-11-23 14:59:53,141 INFO L151 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2018-11-23 14:59:53,141 INFO L163 nArgumentSynthesizer]: Using integer mode. [2018-11-23 14:59:53,144 INFO L445 LassoAnalysis]: Proved nontermination for one component. [2018-11-23 14:59:53,145 INFO L448 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {~t4_st~0=-1} Honda state: {~t4_st~0=-1} Generalized eigenvectors: [] Lambdas: [] Nus: [] No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_14a495c8-4465-4fa3-a7af-a201bd4dc887/bin-2019/uautomizer/z3 Starting monitored process 8 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 8 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2018-11-23 14:59:53,172 INFO L151 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2018-11-23 14:59:53,172 INFO L163 nArgumentSynthesizer]: Using integer mode. No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_14a495c8-4465-4fa3-a7af-a201bd4dc887/bin-2019/uautomizer/z3 Starting monitored process 9 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 9 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2018-11-23 14:59:53,197 INFO L151 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 3 Nilpotent components: true [2018-11-23 14:59:53,197 INFO L163 nArgumentSynthesizer]: Using integer mode. [2018-11-23 14:59:53,211 INFO L452 LassoAnalysis]: Proving nontermination failed: No geometric nontermination argument exists. [2018-11-23 14:59:53,226 INFO L216 LassoAnalysis]: Preferences: [2018-11-23 14:59:53,226 INFO L124 ssoRankerPreferences]: Compute integeral hull: false [2018-11-23 14:59:53,226 INFO L125 ssoRankerPreferences]: Enable LassoPartitioneer: true [2018-11-23 14:59:53,226 INFO L126 ssoRankerPreferences]: Term annotations enabled: false [2018-11-23 14:59:53,226 INFO L127 ssoRankerPreferences]: Use exernal solver: false [2018-11-23 14:59:53,226 INFO L128 ssoRankerPreferences]: SMT solver command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2018-11-23 14:59:53,226 INFO L129 ssoRankerPreferences]: Dump SMT script to file: false [2018-11-23 14:59:53,226 INFO L130 ssoRankerPreferences]: Path of dumped script: [2018-11-23 14:59:53,226 INFO L131 ssoRankerPreferences]: Filename of dumped script: token_ring.06_true-unreach-call_false-termination.cil.c_Iteration26_Loop [2018-11-23 14:59:53,226 INFO L132 ssoRankerPreferences]: MapElimAlgo: Frank [2018-11-23 14:59:53,226 INFO L282 LassoAnalysis]: Starting lasso preprocessing... [2018-11-23 14:59:53,233 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 14:59:53,240 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 14:59:53,243 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 14:59:53,245 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 14:59:53,252 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 14:59:53,260 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 14:59:53,266 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 14:59:53,271 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 14:59:53,274 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 14:59:53,276 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 14:59:53,278 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 14:59:53,284 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 14:59:53,286 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 14:59:53,288 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 14:59:53,291 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 14:59:53,293 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 14:59:53,297 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 14:59:53,299 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 14:59:53,303 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 14:59:53,310 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 14:59:53,312 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 14:59:53,321 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 14:59:53,324 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 14:59:53,327 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 14:59:53,333 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 14:59:53,335 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 14:59:53,338 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 14:59:53,342 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 14:59:53,345 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 14:59:53,349 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 14:59:53,352 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 14:59:53,354 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 14:59:53,357 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 14:59:53,359 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 14:59:53,363 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 14:59:53,367 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 14:59:53,370 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 14:59:53,372 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 14:59:53,376 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 14:59:53,380 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 14:59:53,382 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 14:59:53,386 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 14:59:53,389 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 14:59:53,391 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 14:59:53,394 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 14:59:53,396 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 14:59:53,398 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 14:59:53,401 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 14:59:53,403 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 14:59:53,406 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 14:59:53,409 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 14:59:53,414 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 14:59:53,418 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 14:59:53,420 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 14:59:53,425 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 14:59:53,428 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 14:59:53,430 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 14:59:53,432 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 14:59:53,436 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 14:59:53,439 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 14:59:53,441 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 14:59:53,448 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 14:59:53,459 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 14:59:53,461 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 14:59:53,465 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 14:59:53,466 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 14:59:53,483 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 14:59:53,882 INFO L300 LassoAnalysis]: Preprocessing complete. [2018-11-23 14:59:53,886 INFO L497 LassoAnalysis]: Using template 'affine'. [2018-11-23 14:59:53,888 INFO L122 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSES Number of strict supporting invariants: 0 Number of non-strict supporting invariants: 1 Consider only non-deceasing supporting invariants: true Simplify termination arguments: true Simplify supporting invariants: trueOverapproximate stem: false [2018-11-23 14:59:53,889 INFO L339 nArgumentSynthesizer]: Template has degree 0. [2018-11-23 14:59:53,889 INFO L352 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2018-11-23 14:59:53,890 INFO L205 nArgumentSynthesizer]: 1 stem disjuncts [2018-11-23 14:59:53,890 INFO L206 nArgumentSynthesizer]: 1 loop disjuncts [2018-11-23 14:59:53,890 INFO L207 nArgumentSynthesizer]: 2 template conjuncts. [2018-11-23 14:59:53,891 INFO L402 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2018-11-23 14:59:53,891 INFO L403 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2018-11-23 14:59:53,893 INFO L530 LassoAnalysis]: Proving termination failed for this template and these settings. [2018-11-23 14:59:53,893 INFO L122 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSES Number of strict supporting invariants: 0 Number of non-strict supporting invariants: 1 Consider only non-deceasing supporting invariants: true Simplify termination arguments: true Simplify supporting invariants: trueOverapproximate stem: false [2018-11-23 14:59:53,894 INFO L339 nArgumentSynthesizer]: Template has degree 0. [2018-11-23 14:59:53,894 INFO L352 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2018-11-23 14:59:53,894 INFO L205 nArgumentSynthesizer]: 1 stem disjuncts [2018-11-23 14:59:53,894 INFO L206 nArgumentSynthesizer]: 1 loop disjuncts [2018-11-23 14:59:53,894 INFO L207 nArgumentSynthesizer]: 2 template conjuncts. [2018-11-23 14:59:53,894 INFO L402 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2018-11-23 14:59:53,894 INFO L403 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2018-11-23 14:59:53,895 INFO L530 LassoAnalysis]: Proving termination failed for this template and these settings. [2018-11-23 14:59:53,895 INFO L122 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSES Number of strict supporting invariants: 0 Number of non-strict supporting invariants: 1 Consider only non-deceasing supporting invariants: true Simplify termination arguments: true Simplify supporting invariants: trueOverapproximate stem: false [2018-11-23 14:59:53,896 INFO L339 nArgumentSynthesizer]: Template has degree 0. [2018-11-23 14:59:53,896 INFO L352 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2018-11-23 14:59:53,896 INFO L205 nArgumentSynthesizer]: 1 stem disjuncts [2018-11-23 14:59:53,896 INFO L206 nArgumentSynthesizer]: 1 loop disjuncts [2018-11-23 14:59:53,896 INFO L207 nArgumentSynthesizer]: 2 template conjuncts. [2018-11-23 14:59:53,896 INFO L402 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2018-11-23 14:59:53,896 INFO L403 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2018-11-23 14:59:53,897 INFO L530 LassoAnalysis]: Proving termination failed for this template and these settings. [2018-11-23 14:59:53,897 INFO L122 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSES Number of strict supporting invariants: 0 Number of non-strict supporting invariants: 1 Consider only non-deceasing supporting invariants: true Simplify termination arguments: true Simplify supporting invariants: trueOverapproximate stem: false [2018-11-23 14:59:53,898 INFO L339 nArgumentSynthesizer]: Template has degree 0. [2018-11-23 14:59:53,898 INFO L352 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2018-11-23 14:59:53,898 INFO L205 nArgumentSynthesizer]: 1 stem disjuncts [2018-11-23 14:59:53,898 INFO L206 nArgumentSynthesizer]: 2 loop disjuncts [2018-11-23 14:59:53,898 INFO L207 nArgumentSynthesizer]: 2 template conjuncts. [2018-11-23 14:59:53,898 INFO L402 nArgumentSynthesizer]: We have 4 Motzkin's Theorem applications. [2018-11-23 14:59:53,899 INFO L403 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2018-11-23 14:59:53,899 INFO L530 LassoAnalysis]: Proving termination failed for this template and these settings. [2018-11-23 14:59:53,900 INFO L122 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSES Number of strict supporting invariants: 0 Number of non-strict supporting invariants: 1 Consider only non-deceasing supporting invariants: true Simplify termination arguments: true Simplify supporting invariants: trueOverapproximate stem: false [2018-11-23 14:59:53,900 INFO L339 nArgumentSynthesizer]: Template has degree 0. [2018-11-23 14:59:53,900 INFO L352 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2018-11-23 14:59:53,900 INFO L205 nArgumentSynthesizer]: 1 stem disjuncts [2018-11-23 14:59:53,900 INFO L206 nArgumentSynthesizer]: 1 loop disjuncts [2018-11-23 14:59:53,900 INFO L207 nArgumentSynthesizer]: 2 template conjuncts. [2018-11-23 14:59:53,901 INFO L402 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2018-11-23 14:59:53,901 INFO L403 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2018-11-23 14:59:53,904 INFO L421 nArgumentSynthesizer]: Found a termination argument, trying to simplify. [2018-11-23 14:59:53,906 INFO L443 ModelExtractionUtils]: Simplification made 3 calls to the SMT solver. [2018-11-23 14:59:53,906 INFO L444 ModelExtractionUtils]: 0 out of 3 variables were initially zero. Simplification set additionally 0 variables to zero. [2018-11-23 14:59:53,907 INFO L437 nArgumentSynthesizer]: Simplifying supporting invariants... [2018-11-23 14:59:53,907 INFO L440 nArgumentSynthesizer]: Removed 0 redundant supporting invariants from a total of 0. [2018-11-23 14:59:53,908 INFO L518 LassoAnalysis]: Proved termination. [2018-11-23 14:59:53,908 INFO L520 LassoAnalysis]: Termination argument consisting of: Ranking function f(~E_4~0) = -1*~E_4~0 + 1 Supporting invariants [] [2018-11-23 14:59:53,909 INFO L297 tatePredicateManager]: 0 out of 0 supporting invariants were superfluous and have been removed [2018-11-23 14:59:53,974 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 14:59:54,004 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 14:59:54,008 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-23 14:59:54,047 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 14:59:54,049 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-23 14:59:54,073 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 14:59:54,078 INFO L152 lantAutomatonBouncer]: Defining deterministic Buchi interpolant automaton with honda bouncer for stem and without honda bouncer for loop.1 stem predicates 3 loop predicates [2018-11-23 14:59:54,078 INFO L72 iDifferenceNCSBLazy3]: Start buchiDifferenceNCSBLazy3. First operand 14878 states and 19376 transitions. cyclomatic complexity: 4514 Second operand 5 states. [2018-11-23 14:59:54,547 INFO L76 iDifferenceNCSBLazy3]: Finished buchiDifferenceNCSBLazy3. First operand 14878 states and 19376 transitions. cyclomatic complexity: 4514. Second operand 5 states. Result 55928 states and 73283 transitions. Complement of second has 5 states. [2018-11-23 14:59:54,549 INFO L142 InterpolantAutomaton]: Switched to read-only mode: Buchi interpolant automaton has 3 states 1 stem states 1 non-accepting loop states 1 accepting loop states [2018-11-23 14:59:54,549 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 5 states. [2018-11-23 14:59:54,551 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3 states to 3 states and 1665 transitions. [2018-11-23 14:59:54,553 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 3 states and 1665 transitions. Stem has 80 letters. Loop has 99 letters. [2018-11-23 14:59:54,556 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2018-11-23 14:59:54,557 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 3 states and 1665 transitions. Stem has 179 letters. Loop has 99 letters. [2018-11-23 14:59:54,557 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2018-11-23 14:59:54,558 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 3 states and 1665 transitions. Stem has 80 letters. Loop has 198 letters. [2018-11-23 14:59:54,559 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2018-11-23 14:59:54,560 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 55928 states and 73283 transitions. [2018-11-23 14:59:54,791 INFO L131 ngComponentsAnalysis]: Automaton has 48 accepting balls. 42216 [2018-11-23 14:59:55,070 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 55928 states to 55896 states and 73251 transitions. [2018-11-23 14:59:55,070 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 42719 [2018-11-23 14:59:55,099 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 42800 [2018-11-23 14:59:55,099 INFO L73 IsDeterministic]: Start isDeterministic. Operand 55896 states and 73251 transitions. [2018-11-23 14:59:55,101 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2018-11-23 14:59:55,101 INFO L705 BuchiCegarLoop]: Abstraction has 55896 states and 73251 transitions. [2018-11-23 14:59:55,126 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 55896 states and 73251 transitions. [2018-11-23 14:59:55,572 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 55896 to 40991. [2018-11-23 14:59:55,572 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 40991 states. [2018-11-23 14:59:55,620 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 40991 states to 40991 states and 53794 transitions. [2018-11-23 14:59:55,620 INFO L728 BuchiCegarLoop]: Abstraction has 40991 states and 53794 transitions. [2018-11-23 14:59:55,621 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-23 14:59:55,621 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-23 14:59:55,621 INFO L87 Difference]: Start difference. First operand 40991 states and 53794 transitions. Second operand 3 states. [2018-11-23 14:59:55,818 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 14:59:55,818 INFO L93 Difference]: Finished difference Result 43247 states and 56314 transitions. [2018-11-23 14:59:55,819 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-23 14:59:55,819 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 43247 states and 56314 transitions. [2018-11-23 14:59:55,952 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 29056 [2018-11-23 14:59:56,057 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 43247 states to 43247 states and 56314 transitions. [2018-11-23 14:59:56,057 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 29399 [2018-11-23 14:59:56,073 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 29399 [2018-11-23 14:59:56,073 INFO L73 IsDeterministic]: Start isDeterministic. Operand 43247 states and 56314 transitions. [2018-11-23 14:59:56,083 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2018-11-23 14:59:56,083 INFO L705 BuchiCegarLoop]: Abstraction has 43247 states and 56314 transitions. [2018-11-23 14:59:56,102 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 43247 states and 56314 transitions. [2018-11-23 14:59:56,341 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 43247 to 40991. [2018-11-23 14:59:56,341 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 40991 states. [2018-11-23 14:59:56,379 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 40991 states to 40991 states and 53602 transitions. [2018-11-23 14:59:56,379 INFO L728 BuchiCegarLoop]: Abstraction has 40991 states and 53602 transitions. [2018-11-23 14:59:56,379 INFO L608 BuchiCegarLoop]: Abstraction has 40991 states and 53602 transitions. [2018-11-23 14:59:56,379 INFO L442 BuchiCegarLoop]: ======== Iteration 27============ [2018-11-23 14:59:56,379 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 40991 states and 53602 transitions. [2018-11-23 14:59:56,454 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 27552 [2018-11-23 14:59:56,454 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-23 14:59:56,454 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-23 14:59:56,455 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 14:59:56,455 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 14:59:56,455 INFO L794 eck$LassoCheckResult]: Stem: 497687#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0; 497443#L-1 havoc main_#res;havoc main_~__retres1~8;havoc main_~__retres1~8;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 496578#L1006 havoc start_simulation_#t~ret17, start_simulation_#t~ret18, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 496579#L458 assume 1 == ~m_i~0;~m_st~0 := 0; 497295#L465-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 497296#L470-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 497081#L475-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 497082#L480-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 497162#L485-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 496745#L490-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 496746#L495-1 assume !(0 == ~M_E~0); 497328#L674-1 assume !(0 == ~T1_E~0); 497329#L679-1 assume !(0 == ~T2_E~0); 497110#L684-1 assume !(0 == ~T3_E~0); 497111#L689-1 assume !(0 == ~T4_E~0); 497630#L694-1 assume !(0 == ~T5_E~0); 496822#L699-1 assume !(0 == ~T6_E~0); 496823#L704-1 assume !(0 == ~E_M~0); 496505#L709-1 assume !(0 == ~E_1~0); 496506#L714-1 assume !(0 == ~E_2~0); 496664#L719-1 assume !(0 == ~E_3~0); 496665#L724-1 assume !(0 == ~E_4~0); 497310#L729-1 assume !(0 == ~E_5~0); 497311#L734-1 assume !(0 == ~E_6~0); 497097#L739-1 havoc activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 496892#L324 assume !(1 == ~m_pc~0); 496758#L324-2 is_master_triggered_~__retres1~0 := 0; 496916#L335 is_master_triggered_#res := is_master_triggered_~__retres1~0; 496754#L336 activate_threads_#t~ret9 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 496755#L839 assume !(0 != activate_threads_~tmp~1); 497345#L839-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 496996#L343 assume !(1 == ~t1_pc~0); 496997#L343-2 is_transmit1_triggered_~__retres1~1 := 0; 496994#L354 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 496995#L355 activate_threads_#t~ret10 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 497240#L847 assume !(0 != activate_threads_~tmp___0~0); 497749#L847-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 497557#L362 assume !(1 == ~t2_pc~0); 497455#L362-2 is_transmit2_triggered_~__retres1~2 := 0; 497456#L373 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 497556#L374 activate_threads_#t~ret11 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 497725#L855 assume !(0 != activate_threads_~tmp___1~0); 497772#L855-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 497781#L381 assume !(1 == ~t3_pc~0); 497847#L381-2 is_transmit3_triggered_~__retres1~3 := 0; 497845#L392 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 497846#L393 activate_threads_#t~ret12 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 496604#L863 assume !(0 != activate_threads_~tmp___2~0); 496554#L863-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 496555#L400 assume !(1 == ~t4_pc~0); 496626#L400-2 is_transmit4_triggered_~__retres1~4 := 0; 496627#L411 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 496657#L412 activate_threads_#t~ret13 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 496944#L871 assume !(0 != activate_threads_~tmp___3~0); 497123#L871-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 497130#L419 assume !(1 == ~t5_pc~0); 496968#L419-2 is_transmit5_triggered_~__retres1~5 := 0; 496969#L430 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 497083#L431 activate_threads_#t~ret14 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 497084#L879 assume !(0 != activate_threads_~tmp___4~0); 497583#L879-2 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 497584#L438 assume !(1 == ~t6_pc~0); 497614#L438-2 is_transmit6_triggered_~__retres1~6 := 0; 497615#L449 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 497532#L450 activate_threads_#t~ret15 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 497533#L887 assume !(0 != activate_threads_~tmp___5~0); 497881#L887-2 assume !(1 == ~M_E~0); 496686#L752-1 assume !(1 == ~T1_E~0); 496687#L757-1 assume !(1 == ~T2_E~0); 497304#L762-1 assume !(1 == ~T3_E~0); 497305#L767-1 assume !(1 == ~T4_E~0); 497093#L772-1 assume !(1 == ~T5_E~0); 497094#L777-1 assume !(1 == ~T6_E~0); 497626#L782-1 assume !(1 == ~E_M~0); 496813#L787-1 assume !(1 == ~E_1~0); 496814#L792-1 assume !(1 == ~E_2~0); 496562#L797-1 assume !(1 == ~E_3~0); 496563#L802-1 assume !(1 == ~E_4~0); 496684#L807-1 assume !(1 == ~E_5~0); 496685#L812-1 assume 1 == ~E_6~0;~E_6~0 := 2; 497893#L1043-1 [2018-11-23 14:59:56,456 INFO L796 eck$LassoCheckResult]: Loop: 497893#L1043-1 assume !false; 514940#L1044 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret1, eval_#t~nondet2, eval_~tmp_ndt_1~0, eval_#t~nondet3, eval_~tmp_ndt_2~0, eval_#t~nondet4, eval_~tmp_ndt_3~0, eval_#t~nondet5, eval_~tmp_ndt_4~0, eval_#t~nondet6, eval_~tmp_ndt_5~0, eval_#t~nondet7, eval_~tmp_ndt_6~0, eval_#t~nondet8, eval_~tmp_ndt_7~0, eval_~tmp~0;havoc eval_~tmp~0; 514079#L649 assume !false; 514935#L556 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~7;havoc exists_runnable_thread_~__retres1~7; 514933#L508 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7 := 1; 514931#L545 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~7; 514929#L546 eval_#t~ret1 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret1;havoc eval_#t~ret1; 514927#L560 assume 0 != eval_~tmp~0; 514925#L560-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0;eval_~tmp_ndt_1~0 := eval_#t~nondet2;havoc eval_#t~nondet2; 514922#L568 assume 0 != eval_~tmp_ndt_1~0;~m_st~0 := 1;havoc master_#t~nondet0; 514918#L64 assume 0 == ~m_pc~0; 514915#L89 assume !false; 514913#L76 ~token~0 := master_#t~nondet0;havoc master_#t~nondet0;~local~0 := ~token~0;~E_1~0 := 1;havoc activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 514911#L324-3 assume 1 == ~m_pc~0; 514909#L325-1 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 514910#L335-1 is_master_triggered_#res := is_master_triggered_~__retres1~0; 514952#L336-1 activate_threads_#t~ret9 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 514899#L839-3 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 514897#L839-5 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 514895#L343-3 assume !(1 == ~t1_pc~0); 514893#L343-5 is_transmit1_triggered_~__retres1~1 := 0; 514891#L354-1 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 514889#L355-1 activate_threads_#t~ret10 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 514887#L847-3 assume !(0 != activate_threads_~tmp___0~0); 514885#L847-5 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 514883#L362-3 assume !(1 == ~t2_pc~0); 514881#L362-5 is_transmit2_triggered_~__retres1~2 := 0; 514879#L373-1 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 514877#L374-1 activate_threads_#t~ret11 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 514875#L855-3 assume !(0 != activate_threads_~tmp___1~0); 514872#L855-5 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 514870#L381-3 assume !(1 == ~t3_pc~0); 514867#L381-5 is_transmit3_triggered_~__retres1~3 := 0; 514865#L392-1 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 514863#L393-1 activate_threads_#t~ret12 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 514861#L863-3 assume !(0 != activate_threads_~tmp___2~0); 514859#L863-5 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 514857#L400-3 assume !(1 == ~t4_pc~0); 514855#L400-5 is_transmit4_triggered_~__retres1~4 := 0; 514853#L411-1 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 514849#L412-1 activate_threads_#t~ret13 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 514847#L871-3 assume !(0 != activate_threads_~tmp___3~0); 514846#L871-5 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 514841#L419-3 assume !(1 == ~t5_pc~0); 514838#L419-5 is_transmit5_triggered_~__retres1~5 := 0; 514836#L430-1 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 514834#L431-1 activate_threads_#t~ret14 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 514832#L879-3 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 514831#L879-5 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 514830#L438-3 assume !(1 == ~t6_pc~0); 514822#L438-5 is_transmit6_triggered_~__retres1~6 := 0; 514820#L449-1 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 514818#L450-1 activate_threads_#t~ret15 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 514816#L887-3 assume !(0 != activate_threads_~tmp___5~0); 514815#L887-5 ~E_1~0 := 2;~m_pc~0 := 1;~m_st~0 := 2; 514809#L565 assume !(0 == ~t1_st~0); 514805#L579 assume !(0 == ~t2_st~0); 514802#L593 assume !(0 == ~t3_st~0); 515142#L607 assume !(0 == ~t4_st~0); 514842#L621 assume !(0 == ~t5_st~0); 514840#L635 assume !(0 == ~t6_st~0); 514037#L649 assume !false; 514835#L556 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~7;havoc exists_runnable_thread_~__retres1~7; 514833#L508 assume !(0 == ~m_st~0); 514828#L512 assume !(0 == ~t1_st~0); 514829#L516 assume !(0 == ~t2_st~0); 514825#L520 assume !(0 == ~t3_st~0); 514826#L524 assume !(0 == ~t4_st~0); 514827#L528 assume !(0 == ~t5_st~0); 514823#L532 assume !(0 == ~t6_st~0);exists_runnable_thread_~__retres1~7 := 0; 514824#L545 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~7; 515122#L546 eval_#t~ret1 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret1;havoc eval_#t~ret1; 515120#L560 assume !(0 != eval_~tmp~0); 515118#L664 start_simulation_~kernel_st~0 := 2; 515116#L458-1 start_simulation_~kernel_st~0 := 3; 515114#L674-2 assume !(0 == ~M_E~0); 515112#L674-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 515110#L679-3 assume !(0 == ~T2_E~0); 515109#L684-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 515108#L689-3 assume !(0 == ~T4_E~0); 515101#L694-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 515099#L699-3 assume !(0 == ~T6_E~0); 515097#L704-3 assume 0 == ~E_M~0;~E_M~0 := 1; 515094#L709-3 assume !(0 == ~E_1~0); 515092#L714-3 assume 0 == ~E_2~0;~E_2~0 := 1; 515090#L719-3 assume !(0 == ~E_3~0); 515087#L724-3 assume 0 == ~E_4~0;~E_4~0 := 1; 515085#L729-3 assume !(0 == ~E_5~0); 515083#L734-3 assume 0 == ~E_6~0;~E_6~0 := 1; 515082#L739-3 havoc activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 515081#L324-24 assume 1 == ~m_pc~0; 515078#L325-8 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 515076#L335-8 is_master_triggered_#res := is_master_triggered_~__retres1~0; 515075#L336-8 activate_threads_#t~ret9 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 515073#L839-24 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 515071#L839-26 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 515068#L343-24 assume !(1 == ~t1_pc~0); 515066#L343-26 is_transmit1_triggered_~__retres1~1 := 0; 515064#L354-8 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 515059#L355-8 activate_threads_#t~ret10 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 515057#L847-24 assume !(0 != activate_threads_~tmp___0~0); 515055#L847-26 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 515053#L362-24 assume !(1 == ~t2_pc~0); 515051#L362-26 is_transmit2_triggered_~__retres1~2 := 0; 515049#L373-8 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 515047#L374-8 activate_threads_#t~ret11 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 515045#L855-24 assume !(0 != activate_threads_~tmp___1~0); 515043#L855-26 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 515041#L381-24 assume !(1 == ~t3_pc~0); 515038#L381-26 is_transmit3_triggered_~__retres1~3 := 0; 515036#L392-8 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 515034#L393-8 activate_threads_#t~ret12 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 515032#L863-24 assume !(0 != activate_threads_~tmp___2~0); 515029#L863-26 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 515027#L400-24 assume !(1 == ~t4_pc~0); 515025#L400-26 is_transmit4_triggered_~__retres1~4 := 0; 515023#L411-8 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 515021#L412-8 activate_threads_#t~ret13 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 515019#L871-24 assume !(0 != activate_threads_~tmp___3~0); 515017#L871-26 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 515015#L419-24 assume !(1 == ~t5_pc~0); 515013#L419-26 is_transmit5_triggered_~__retres1~5 := 0; 515010#L430-8 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 515008#L431-8 activate_threads_#t~ret14 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 515006#L879-24 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 515004#L879-26 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 515001#L438-24 assume !(1 == ~t6_pc~0); 514999#L438-26 is_transmit6_triggered_~__retres1~6 := 0; 514997#L449-8 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 514995#L450-8 activate_threads_#t~ret15 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 514993#L887-24 assume !(0 != activate_threads_~tmp___5~0); 514991#L887-26 assume !(1 == ~M_E~0); 514989#L752-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 514987#L757-3 assume !(1 == ~T2_E~0); 514985#L762-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 514983#L767-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 514981#L772-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 514979#L777-3 assume !(1 == ~T6_E~0); 514977#L782-3 assume 1 == ~E_M~0;~E_M~0 := 2; 514975#L787-3 assume !(1 == ~E_1~0); 514973#L792-3 assume 1 == ~E_2~0;~E_2~0 := 2; 514971#L797-3 assume !(1 == ~E_3~0); 514969#L802-3 assume 1 == ~E_4~0;~E_4~0 := 2; 514967#L807-3 assume 1 == ~E_5~0;~E_5~0 := 2; 514965#L812-3 assume 1 == ~E_6~0;~E_6~0 := 2; 514963#L817-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~7;havoc exists_runnable_thread_~__retres1~7; 514961#L508-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7 := 1; 514959#L545-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~7; 514957#L546-1 start_simulation_#t~ret17 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret17;havoc start_simulation_#t~ret17; 514955#L1062 assume !(0 == start_simulation_~tmp~3); 514953#L1062-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret16, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~7;havoc exists_runnable_thread_~__retres1~7; 514951#L508-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7 := 1; 514950#L545-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~7; 514949#L546-2 stop_simulation_#t~ret16 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret16;havoc stop_simulation_#t~ret16; 514948#L1017 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 514947#L1024 stop_simulation_#res := stop_simulation_~__retres2~0; 514946#L1025 start_simulation_#t~ret18 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret18;havoc start_simulation_#t~ret18; 514945#L1075 assume !(0 != start_simulation_~tmp___0~1); 497893#L1043-1 [2018-11-23 14:59:56,456 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 14:59:56,456 INFO L82 PathProgramCache]: Analyzing trace with hash -800641182, now seen corresponding path program 1 times [2018-11-23 14:59:56,456 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 14:59:56,456 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 14:59:56,456 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 14:59:56,457 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 14:59:56,457 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 14:59:56,461 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 14:59:56,492 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 14:59:56,492 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 14:59:56,493 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [1] imperfect sequences [] total 1 [2018-11-23 14:59:56,493 INFO L799 eck$LassoCheckResult]: stem already infeasible [2018-11-23 14:59:56,493 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 14:59:56,493 INFO L82 PathProgramCache]: Analyzing trace with hash 1455502842, now seen corresponding path program 1 times [2018-11-23 14:59:56,493 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 14:59:56,493 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 14:59:56,494 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 14:59:56,494 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 14:59:56,494 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 14:59:56,500 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 14:59:56,521 INFO L134 CoverageAnalysis]: Checked inductivity of 6 backedges. 6 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 14:59:56,521 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 14:59:56,521 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-23 14:59:56,522 INFO L811 eck$LassoCheckResult]: loop already infeasible [2018-11-23 14:59:56,522 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-23 14:59:56,522 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-23 14:59:56,522 INFO L87 Difference]: Start difference. First operand 40991 states and 53602 transitions. cyclomatic complexity: 12659 Second operand 3 states. [2018-11-23 14:59:56,690 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 14:59:56,690 INFO L93 Difference]: Finished difference Result 40223 states and 52080 transitions. [2018-11-23 14:59:56,691 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-23 14:59:56,691 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 40223 states and 52080 transitions. [2018-11-23 14:59:56,957 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 27024 [2018-11-23 14:59:57,003 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 40223 states to 40223 states and 52080 transitions. [2018-11-23 14:59:57,003 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 27367 [2018-11-23 14:59:57,012 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 27367 [2018-11-23 14:59:57,012 INFO L73 IsDeterministic]: Start isDeterministic. Operand 40223 states and 52080 transitions. [2018-11-23 14:59:57,012 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2018-11-23 14:59:57,012 INFO L705 BuchiCegarLoop]: Abstraction has 40223 states and 52080 transitions. [2018-11-23 14:59:57,024 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 40223 states and 52080 transitions. [2018-11-23 14:59:57,187 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 40223 to 40223. [2018-11-23 14:59:57,188 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 40223 states. [2018-11-23 14:59:57,225 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 40223 states to 40223 states and 52080 transitions. [2018-11-23 14:59:57,225 INFO L728 BuchiCegarLoop]: Abstraction has 40223 states and 52080 transitions. [2018-11-23 14:59:57,226 INFO L608 BuchiCegarLoop]: Abstraction has 40223 states and 52080 transitions. [2018-11-23 14:59:57,226 INFO L442 BuchiCegarLoop]: ======== Iteration 28============ [2018-11-23 14:59:57,226 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 40223 states and 52080 transitions. [2018-11-23 14:59:57,294 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 27024 [2018-11-23 14:59:57,294 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-23 14:59:57,294 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-23 14:59:57,296 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 14:59:57,296 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 14:59:57,296 INFO L794 eck$LassoCheckResult]: Stem: 578883#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0; 578648#L-1 havoc main_#res;havoc main_~__retres1~8;havoc main_~__retres1~8;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 577800#L1006 havoc start_simulation_#t~ret17, start_simulation_#t~ret18, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 577801#L458 assume 1 == ~m_i~0;~m_st~0 := 0; 578509#L465-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 578510#L470-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 578291#L475-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 578292#L480-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 578373#L485-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 577959#L490-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 577960#L495-1 assume !(0 == ~M_E~0); 578541#L674-1 assume !(0 == ~T1_E~0); 578542#L679-1 assume !(0 == ~T2_E~0); 578317#L684-1 assume !(0 == ~T3_E~0); 578318#L689-1 assume !(0 == ~T4_E~0); 578825#L694-1 assume !(0 == ~T5_E~0); 578041#L699-1 assume !(0 == ~T6_E~0); 578042#L704-1 assume !(0 == ~E_M~0); 577726#L709-1 assume !(0 == ~E_1~0); 577727#L714-1 assume !(0 == ~E_2~0); 577884#L719-1 assume !(0 == ~E_3~0); 577885#L724-1 assume !(0 == ~E_4~0); 578525#L729-1 assume !(0 == ~E_5~0); 578526#L734-1 assume !(0 == ~E_6~0); 578306#L739-1 havoc activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 578106#L324 assume !(1 == ~m_pc~0); 577979#L324-2 is_master_triggered_~__retres1~0 := 0; 578127#L335 is_master_triggered_#res := is_master_triggered_~__retres1~0; 577975#L336 activate_threads_#t~ret9 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 577976#L839 assume !(0 != activate_threads_~tmp~1); 578558#L839-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 578207#L343 assume !(1 == ~t1_pc~0); 578208#L343-2 is_transmit1_triggered_~__retres1~1 := 0; 578199#L354 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 578200#L355 activate_threads_#t~ret10 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 578450#L847 assume !(0 != activate_threads_~tmp___0~0); 578954#L847-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 578755#L362 assume !(1 == ~t2_pc~0); 578667#L362-2 is_transmit2_triggered_~__retres1~2 := 0; 578668#L373 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 578750#L374 activate_threads_#t~ret11 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 578925#L855 assume !(0 != activate_threads_~tmp___1~0); 578978#L855-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 578987#L381 assume !(1 == ~t3_pc~0); 579051#L381-2 is_transmit3_triggered_~__retres1~3 := 0; 579047#L392 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 579048#L393 activate_threads_#t~ret12 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 577821#L863 assume !(0 != activate_threads_~tmp___2~0); 577775#L863-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 577776#L400 assume !(1 == ~t4_pc~0); 577848#L400-2 is_transmit4_triggered_~__retres1~4 := 0; 577849#L411 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 577877#L412 activate_threads_#t~ret13 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 578155#L871 assume !(0 != activate_threads_~tmp___3~0); 578335#L871-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 578342#L419 assume !(1 == ~t5_pc~0); 578179#L419-2 is_transmit5_triggered_~__retres1~5 := 0; 578180#L430 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 578294#L431 activate_threads_#t~ret14 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 578295#L879 assume !(0 != activate_threads_~tmp___4~0); 578780#L879-2 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 578781#L438 assume !(1 == ~t6_pc~0); 578810#L438-2 is_transmit6_triggered_~__retres1~6 := 0; 578811#L449 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 578735#L450 activate_threads_#t~ret15 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 578736#L887 assume !(0 != activate_threads_~tmp___5~0); 579089#L887-2 assume !(1 == ~M_E~0); 577906#L752-1 assume !(1 == ~T1_E~0); 577907#L757-1 assume !(1 == ~T2_E~0); 578516#L762-1 assume !(1 == ~T3_E~0); 578517#L767-1 assume !(1 == ~T4_E~0); 578304#L772-1 assume !(1 == ~T5_E~0); 578305#L777-1 assume !(1 == ~T6_E~0); 578822#L782-1 assume !(1 == ~E_M~0); 578029#L787-1 assume !(1 == ~E_1~0); 578030#L792-1 assume !(1 == ~E_2~0); 577777#L797-1 assume !(1 == ~E_3~0); 577778#L802-1 assume !(1 == ~E_4~0); 577904#L807-1 assume !(1 == ~E_5~0); 577905#L812-1 assume !(1 == ~E_6~0); 579104#L1043-1 assume !false; 582897#L1044 [2018-11-23 14:59:57,296 INFO L796 eck$LassoCheckResult]: Loop: 582897#L1044 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret1, eval_#t~nondet2, eval_~tmp_ndt_1~0, eval_#t~nondet3, eval_~tmp_ndt_2~0, eval_#t~nondet4, eval_~tmp_ndt_3~0, eval_#t~nondet5, eval_~tmp_ndt_4~0, eval_#t~nondet6, eval_~tmp_ndt_5~0, eval_#t~nondet7, eval_~tmp_ndt_6~0, eval_#t~nondet8, eval_~tmp_ndt_7~0, eval_~tmp~0;havoc eval_~tmp~0; 598747#L649 assume !false; 600109#L556 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~7;havoc exists_runnable_thread_~__retres1~7; 600107#L508 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7 := 1; 600104#L545 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~7; 600102#L546 eval_#t~ret1 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret1;havoc eval_#t~ret1; 600100#L560 assume 0 != eval_~tmp~0; 600097#L560-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0;eval_~tmp_ndt_1~0 := eval_#t~nondet2;havoc eval_#t~nondet2; 600094#L568 assume 0 != eval_~tmp_ndt_1~0;~m_st~0 := 1;havoc master_#t~nondet0; 600095#L64 assume 0 == ~m_pc~0; 601066#L89 assume !false; 601064#L76 ~token~0 := master_#t~nondet0;havoc master_#t~nondet0;~local~0 := ~token~0;~E_1~0 := 1;havoc activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 601062#L324-3 assume 1 == ~m_pc~0; 601059#L325-1 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 601057#L335-1 is_master_triggered_#res := is_master_triggered_~__retres1~0; 601055#L336-1 activate_threads_#t~ret9 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 601042#L839-3 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 601040#L839-5 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 601038#L343-3 assume !(1 == ~t1_pc~0); 601036#L343-5 is_transmit1_triggered_~__retres1~1 := 0; 601034#L354-1 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 601032#L355-1 activate_threads_#t~ret10 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 601030#L847-3 assume !(0 != activate_threads_~tmp___0~0); 601028#L847-5 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 601026#L362-3 assume !(1 == ~t2_pc~0); 601022#L362-5 is_transmit2_triggered_~__retres1~2 := 0; 601020#L373-1 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 601019#L374-1 activate_threads_#t~ret11 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 601014#L855-3 assume !(0 != activate_threads_~tmp___1~0); 601013#L855-5 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 598954#L381-3 assume !(1 == ~t3_pc~0); 598951#L381-5 is_transmit3_triggered_~__retres1~3 := 0; 598949#L392-1 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 598947#L393-1 activate_threads_#t~ret12 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 598945#L863-3 assume !(0 != activate_threads_~tmp___2~0); 598943#L863-5 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 598941#L400-3 assume !(1 == ~t4_pc~0); 598939#L400-5 is_transmit4_triggered_~__retres1~4 := 0; 598937#L411-1 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 598935#L412-1 activate_threads_#t~ret13 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 598933#L871-3 assume !(0 != activate_threads_~tmp___3~0); 598931#L871-5 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 598929#L419-3 assume !(1 == ~t5_pc~0); 598927#L419-5 is_transmit5_triggered_~__retres1~5 := 0; 598924#L430-1 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 598922#L431-1 activate_threads_#t~ret14 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 598920#L879-3 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 598918#L879-5 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 598916#L438-3 assume !(1 == ~t6_pc~0); 598914#L438-5 is_transmit6_triggered_~__retres1~6 := 0; 598912#L449-1 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 598910#L450-1 activate_threads_#t~ret15 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 598908#L887-3 assume !(0 != activate_threads_~tmp___5~0); 598906#L887-5 ~E_1~0 := 2;~m_pc~0 := 1;~m_st~0 := 2; 598903#L565 assume !(0 == ~t1_st~0); 598899#L579 assume !(0 == ~t2_st~0); 598896#L593 assume !(0 == ~t3_st~0); 598891#L607 assume !(0 == ~t4_st~0); 598885#L621 assume !(0 == ~t5_st~0); 598883#L635 assume !(0 == ~t6_st~0); 604954#L649 assume !false; 604952#L556 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~7;havoc exists_runnable_thread_~__retres1~7; 604951#L508 assume !(0 == ~m_st~0); 598995#L512 assume !(0 == ~t1_st~0); 598996#L516 assume !(0 == ~t2_st~0); 598992#L520 assume !(0 == ~t3_st~0); 598993#L524 assume !(0 == ~t4_st~0); 598994#L528 assume !(0 == ~t5_st~0); 598990#L532 assume !(0 == ~t6_st~0);exists_runnable_thread_~__retres1~7 := 0; 598991#L545 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~7; 610570#L546 eval_#t~ret1 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret1;havoc eval_#t~ret1; 610569#L560 assume !(0 != eval_~tmp~0); 610567#L664 start_simulation_~kernel_st~0 := 2; 610566#L458-1 start_simulation_~kernel_st~0 := 3; 610565#L674-2 assume !(0 == ~M_E~0); 610564#L674-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 610562#L679-3 assume !(0 == ~T2_E~0); 610559#L684-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 610557#L689-3 assume !(0 == ~T4_E~0); 610555#L694-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 610554#L699-3 assume !(0 == ~T6_E~0); 610553#L704-3 assume 0 == ~E_M~0;~E_M~0 := 1; 610551#L709-3 assume !(0 == ~E_1~0); 610550#L714-3 assume 0 == ~E_2~0;~E_2~0 := 1; 610549#L719-3 assume !(0 == ~E_3~0); 610548#L724-3 assume !(0 == ~E_4~0); 610547#L729-3 assume !(0 == ~E_5~0); 610546#L734-3 assume !(0 == ~E_6~0); 610542#L739-3 havoc activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 610540#L324-24 assume 1 == ~m_pc~0; 610537#L325-8 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 610535#L335-8 is_master_triggered_#res := is_master_triggered_~__retres1~0; 610531#L336-8 activate_threads_#t~ret9 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 610529#L839-24 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 610527#L839-26 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 610525#L343-24 assume !(1 == ~t1_pc~0); 610523#L343-26 is_transmit1_triggered_~__retres1~1 := 0; 610521#L354-8 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 610519#L355-8 activate_threads_#t~ret10 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 610517#L847-24 assume !(0 != activate_threads_~tmp___0~0); 610513#L847-26 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 610511#L362-24 assume !(1 == ~t2_pc~0); 610509#L362-26 is_transmit2_triggered_~__retres1~2 := 0; 610507#L373-8 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 610504#L374-8 activate_threads_#t~ret11 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 610502#L855-24 assume !(0 != activate_threads_~tmp___1~0); 610499#L855-26 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 610497#L381-24 assume !(1 == ~t3_pc~0); 610494#L381-26 is_transmit3_triggered_~__retres1~3 := 0; 610492#L392-8 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 610490#L393-8 activate_threads_#t~ret12 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 610488#L863-24 assume !(0 != activate_threads_~tmp___2~0); 610484#L863-26 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 610482#L400-24 assume !(1 == ~t4_pc~0); 610480#L400-26 is_transmit4_triggered_~__retres1~4 := 0; 610478#L411-8 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 610475#L412-8 activate_threads_#t~ret13 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 610474#L871-24 assume !(0 != activate_threads_~tmp___3~0); 610473#L871-26 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 610472#L419-24 assume !(1 == ~t5_pc~0); 610471#L419-26 is_transmit5_triggered_~__retres1~5 := 0; 610469#L430-8 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 610468#L431-8 activate_threads_#t~ret14 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 610390#L879-24 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 610386#L879-26 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 610380#L438-24 assume !(1 == ~t6_pc~0); 610375#L438-26 is_transmit6_triggered_~__retres1~6 := 0; 610370#L449-8 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 610366#L450-8 activate_threads_#t~ret15 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 610361#L887-24 assume !(0 != activate_threads_~tmp___5~0); 610355#L887-26 assume !(1 == ~M_E~0); 610349#L752-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 610343#L757-3 assume !(1 == ~T2_E~0); 610337#L762-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 610332#L767-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 600168#L772-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 600163#L777-3 assume !(1 == ~T6_E~0); 600159#L782-3 assume 1 == ~E_M~0;~E_M~0 := 2; 600157#L787-3 assume !(1 == ~E_1~0); 600155#L792-3 assume 1 == ~E_2~0;~E_2~0 := 2; 600152#L797-3 assume !(1 == ~E_3~0); 600150#L802-3 assume !(1 == ~E_4~0); 600148#L807-3 assume 1 == ~E_5~0;~E_5~0 := 2; 600146#L812-3 assume !(1 == ~E_6~0); 600144#L817-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~7;havoc exists_runnable_thread_~__retres1~7; 600142#L508-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7 := 1; 600140#L545-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~7; 600138#L546-1 start_simulation_#t~ret17 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret17;havoc start_simulation_#t~ret17; 600135#L1062 assume !(0 == start_simulation_~tmp~3); 600132#L1062-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret16, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~7;havoc exists_runnable_thread_~__retres1~7; 600130#L508-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7 := 1; 600128#L545-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~7; 600125#L546-2 stop_simulation_#t~ret16 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret16;havoc stop_simulation_#t~ret16; 600123#L1017 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 600121#L1024 stop_simulation_#res := stop_simulation_~__retres2~0; 600119#L1025 start_simulation_#t~ret18 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret18;havoc start_simulation_#t~ret18; 600117#L1075 assume !(0 != start_simulation_~tmp___0~1); 600115#L1043-1 assume !false; 582897#L1044 [2018-11-23 14:59:57,297 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 14:59:57,297 INFO L82 PathProgramCache]: Analyzing trace with hash 949927585, now seen corresponding path program 1 times [2018-11-23 14:59:57,297 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 14:59:57,297 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 14:59:57,298 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 14:59:57,298 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 14:59:57,298 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 14:59:57,302 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-23 14:59:57,307 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-23 14:59:57,320 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 14:59:57,320 INFO L82 PathProgramCache]: Analyzing trace with hash 489209200, now seen corresponding path program 1 times [2018-11-23 14:59:57,320 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 14:59:57,320 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 14:59:57,321 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 14:59:57,321 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 14:59:57,321 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 14:59:57,324 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 14:59:57,353 INFO L134 CoverageAnalysis]: Checked inductivity of 6 backedges. 6 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 14:59:57,353 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 14:59:57,353 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-23 14:59:57,354 INFO L811 eck$LassoCheckResult]: loop already infeasible [2018-11-23 14:59:57,354 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-23 14:59:57,354 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-23 14:59:57,354 INFO L87 Difference]: Start difference. First operand 40223 states and 52080 transitions. cyclomatic complexity: 11905 Second operand 3 states. [2018-11-23 14:59:57,496 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 14:59:57,496 INFO L93 Difference]: Finished difference Result 52973 states and 67795 transitions. [2018-11-23 14:59:57,496 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-23 14:59:57,496 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 52973 states and 67795 transitions. [2018-11-23 14:59:57,620 INFO L131 ngComponentsAnalysis]: Automaton has 64 accepting balls. 35632 [2018-11-23 14:59:57,704 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 52973 states to 52973 states and 67795 transitions. [2018-11-23 14:59:57,704 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 36132 [2018-11-23 14:59:57,721 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 36132 [2018-11-23 14:59:57,721 INFO L73 IsDeterministic]: Start isDeterministic. Operand 52973 states and 67795 transitions. [2018-11-23 14:59:57,724 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2018-11-23 14:59:57,724 INFO L705 BuchiCegarLoop]: Abstraction has 52973 states and 67795 transitions. [2018-11-23 14:59:57,746 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 52973 states and 67795 transitions. [2018-11-23 14:59:57,985 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 52973 to 50597. [2018-11-23 14:59:57,985 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 50597 states. [2018-11-23 14:59:58,034 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 50597 states to 50597 states and 65011 transitions. [2018-11-23 14:59:58,034 INFO L728 BuchiCegarLoop]: Abstraction has 50597 states and 65011 transitions. [2018-11-23 14:59:58,034 INFO L608 BuchiCegarLoop]: Abstraction has 50597 states and 65011 transitions. [2018-11-23 14:59:58,034 INFO L442 BuchiCegarLoop]: ======== Iteration 29============ [2018-11-23 14:59:58,034 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 50597 states and 65011 transitions. [2018-11-23 14:59:58,118 INFO L131 ngComponentsAnalysis]: Automaton has 64 accepting balls. 34048 [2018-11-23 14:59:58,118 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-23 14:59:58,118 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-23 14:59:58,119 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 14:59:58,119 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 14:59:58,119 INFO L794 eck$LassoCheckResult]: Stem: 672100#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0; 671869#L-1 havoc main_#res;havoc main_~__retres1~8;havoc main_~__retres1~8;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 671002#L1006 havoc start_simulation_#t~ret17, start_simulation_#t~ret18, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 671003#L458 assume 1 == ~m_i~0;~m_st~0 := 0; 671722#L465-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 671723#L470-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 671504#L475-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 671505#L480-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 671591#L485-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 671171#L490-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 671172#L495-1 assume !(0 == ~M_E~0); 671749#L674-1 assume !(0 == ~T1_E~0); 671750#L679-1 assume !(0 == ~T2_E~0); 671534#L684-1 assume !(0 == ~T3_E~0); 671535#L689-1 assume !(0 == ~T4_E~0); 672046#L694-1 assume !(0 == ~T5_E~0); 671244#L699-1 assume !(0 == ~T6_E~0); 671245#L704-1 assume !(0 == ~E_M~0); 670928#L709-1 assume !(0 == ~E_1~0); 670929#L714-1 assume !(0 == ~E_2~0); 671090#L719-1 assume !(0 == ~E_3~0); 671091#L724-1 assume !(0 == ~E_4~0); 671735#L729-1 assume !(0 == ~E_5~0); 671736#L734-1 assume !(0 == ~E_6~0); 671520#L739-1 havoc activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 671315#L324 assume !(1 == ~m_pc~0); 671316#L324-2 is_master_triggered_~__retres1~0 := 0; 671332#L335 is_master_triggered_#res := is_master_triggered_~__retres1~0; 671179#L336 activate_threads_#t~ret9 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 671180#L839 assume !(0 != activate_threads_~tmp~1); 671766#L839-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 671415#L343 assume !(1 == ~t1_pc~0); 671416#L343-2 is_transmit1_triggered_~__retres1~1 := 0; 671413#L354 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 671414#L355 activate_threads_#t~ret10 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 671666#L847 assume !(0 != activate_threads_~tmp___0~0); 672173#L847-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 671976#L362 assume !(1 == ~t2_pc~0); 671880#L362-2 is_transmit2_triggered_~__retres1~2 := 0; 671881#L373 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 671975#L374 activate_threads_#t~ret11 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 672139#L855 assume !(0 != activate_threads_~tmp___1~0); 672200#L855-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 672209#L381 assume !(1 == ~t3_pc~0); 672272#L381-2 is_transmit3_triggered_~__retres1~3 := 0; 672270#L392 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 672271#L393 activate_threads_#t~ret12 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 671026#L863 assume !(0 != activate_threads_~tmp___2~0); 670978#L863-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 670979#L400 assume !(1 == ~t4_pc~0); 671052#L400-2 is_transmit4_triggered_~__retres1~4 := 0; 671053#L411 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 671083#L412 activate_threads_#t~ret13 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 671363#L871 assume !(0 != activate_threads_~tmp___3~0); 671549#L871-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 671556#L419 assume !(1 == ~t5_pc~0); 671387#L419-2 is_transmit5_triggered_~__retres1~5 := 0; 671388#L430 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 671506#L431 activate_threads_#t~ret14 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 671507#L879 assume !(0 != activate_threads_~tmp___4~0); 672000#L879-2 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 672001#L438 assume !(1 == ~t6_pc~0); 672032#L438-2 is_transmit6_triggered_~__retres1~6 := 0; 672033#L449 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 671956#L450 activate_threads_#t~ret15 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 671957#L887 assume !(0 != activate_threads_~tmp___5~0); 672310#L887-2 assume !(1 == ~M_E~0); 671112#L752-1 assume !(1 == ~T1_E~0); 671113#L757-1 assume !(1 == ~T2_E~0); 671729#L762-1 assume !(1 == ~T3_E~0); 671730#L767-1 assume !(1 == ~T4_E~0); 671516#L772-1 assume !(1 == ~T5_E~0); 671517#L777-1 assume !(1 == ~T6_E~0); 672043#L782-1 assume !(1 == ~E_M~0); 671230#L787-1 assume !(1 == ~E_1~0); 671231#L792-1 assume !(1 == ~E_2~0); 670986#L797-1 assume !(1 == ~E_3~0); 670987#L802-1 assume !(1 == ~E_4~0); 671110#L807-1 assume !(1 == ~E_5~0); 671111#L812-1 assume !(1 == ~E_6~0); 672326#L1043-1 assume !false; 679791#L1044 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret1, eval_#t~nondet2, eval_~tmp_ndt_1~0, eval_#t~nondet3, eval_~tmp_ndt_2~0, eval_#t~nondet4, eval_~tmp_ndt_3~0, eval_#t~nondet5, eval_~tmp_ndt_4~0, eval_#t~nondet6, eval_~tmp_ndt_5~0, eval_#t~nondet7, eval_~tmp_ndt_6~0, eval_#t~nondet8, eval_~tmp_ndt_7~0, eval_~tmp~0;havoc eval_~tmp~0; 694840#L649 [2018-11-23 14:59:58,120 INFO L796 eck$LassoCheckResult]: Loop: 694840#L649 assume !false; 694839#L556 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~7;havoc exists_runnable_thread_~__retres1~7; 694838#L508 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7 := 1; 694837#L545 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~7; 694836#L546 eval_#t~ret1 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret1;havoc eval_#t~ret1; 694835#L560 assume 0 != eval_~tmp~0; 694834#L560-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0;eval_~tmp_ndt_1~0 := eval_#t~nondet2;havoc eval_#t~nondet2; 694832#L568 assume !(0 != eval_~tmp_ndt_1~0); 694831#L565 assume !(0 == ~t1_st~0); 694829#L579 assume !(0 == ~t2_st~0); 694826#L593 assume !(0 == ~t3_st~0); 694825#L607 assume !(0 == ~t4_st~0); 694844#L621 assume !(0 == ~t5_st~0); 694843#L635 assume !(0 == ~t6_st~0); 694840#L649 [2018-11-23 14:59:58,120 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 14:59:58,120 INFO L82 PathProgramCache]: Analyzing trace with hash -617015546, now seen corresponding path program 1 times [2018-11-23 14:59:58,120 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 14:59:58,120 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 14:59:58,121 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 14:59:58,121 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 14:59:58,121 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 14:59:58,125 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-23 14:59:58,130 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-23 14:59:58,146 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 14:59:58,146 INFO L82 PathProgramCache]: Analyzing trace with hash -982153583, now seen corresponding path program 1 times [2018-11-23 14:59:58,146 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 14:59:58,146 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 14:59:58,147 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 14:59:58,147 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 14:59:58,147 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 14:59:58,148 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-23 14:59:58,149 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-23 14:59:58,151 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 14:59:58,151 INFO L82 PathProgramCache]: Analyzing trace with hash -2134675242, now seen corresponding path program 1 times [2018-11-23 14:59:58,151 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 14:59:58,151 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 14:59:58,152 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 14:59:58,152 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 14:59:58,152 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 14:59:58,156 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 14:59:58,185 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 14:59:58,186 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 14:59:58,186 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-23 14:59:58,257 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-23 14:59:58,257 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-23 14:59:58,257 INFO L87 Difference]: Start difference. First operand 50597 states and 65011 transitions. cyclomatic complexity: 14510 Second operand 3 states. [2018-11-23 14:59:58,445 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 14:59:58,445 INFO L93 Difference]: Finished difference Result 88289 states and 112592 transitions. [2018-11-23 14:59:58,445 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-23 14:59:58,446 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 88289 states and 112592 transitions. [2018-11-23 14:59:58,869 INFO L131 ngComponentsAnalysis]: Automaton has 96 accepting balls. 57272 [2018-11-23 14:59:58,973 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 88289 states to 88289 states and 112592 transitions. [2018-11-23 14:59:58,973 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 60523 [2018-11-23 14:59:58,991 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 60523 [2018-11-23 14:59:58,991 INFO L73 IsDeterministic]: Start isDeterministic. Operand 88289 states and 112592 transitions. [2018-11-23 14:59:58,992 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2018-11-23 14:59:58,992 INFO L705 BuchiCegarLoop]: Abstraction has 88289 states and 112592 transitions. [2018-11-23 14:59:59,020 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 88289 states and 112592 transitions. [2018-11-23 14:59:59,410 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 88289 to 88289. [2018-11-23 14:59:59,410 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 88289 states. [2018-11-23 14:59:59,495 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 88289 states to 88289 states and 112592 transitions. [2018-11-23 14:59:59,495 INFO L728 BuchiCegarLoop]: Abstraction has 88289 states and 112592 transitions. [2018-11-23 14:59:59,495 INFO L608 BuchiCegarLoop]: Abstraction has 88289 states and 112592 transitions. [2018-11-23 14:59:59,495 INFO L442 BuchiCegarLoop]: ======== Iteration 30============ [2018-11-23 14:59:59,495 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 88289 states and 112592 transitions. [2018-11-23 14:59:59,638 INFO L131 ngComponentsAnalysis]: Automaton has 96 accepting balls. 57272 [2018-11-23 14:59:59,638 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-23 14:59:59,638 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-23 14:59:59,639 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 14:59:59,639 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 14:59:59,639 INFO L794 eck$LassoCheckResult]: Stem: 811037#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0; 810781#L-1 havoc main_#res;havoc main_~__retres1~8;havoc main_~__retres1~8;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 809897#L1006 havoc start_simulation_#t~ret17, start_simulation_#t~ret18, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 809898#L458 assume 1 == ~m_i~0;~m_st~0 := 0; 810628#L465-1 assume !(1 == ~t1_i~0);~t1_st~0 := 2; 810629#L470-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 810397#L475-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 810398#L480-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 810489#L485-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 810490#L490-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 811070#L495-1 assume !(0 == ~M_E~0); 811071#L674-1 assume !(0 == ~T1_E~0); 811350#L679-1 assume !(0 == ~T2_E~0); 811351#L684-1 assume !(0 == ~T3_E~0); 811249#L689-1 assume !(0 == ~T4_E~0); 811250#L694-1 assume !(0 == ~T5_E~0); 810142#L699-1 assume !(0 == ~T6_E~0); 810143#L704-1 assume !(0 == ~E_M~0); 809822#L709-1 assume !(0 == ~E_1~0); 809823#L714-1 assume !(0 == ~E_2~0); 809988#L719-1 assume !(0 == ~E_3~0); 809989#L724-1 assume !(0 == ~E_4~0); 810646#L729-1 assume !(0 == ~E_5~0); 810647#L734-1 assume !(0 == ~E_6~0); 810411#L739-1 havoc activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 810412#L324 assume !(1 == ~m_pc~0); 810227#L324-2 is_master_triggered_~__retres1~0 := 0; 810228#L335 is_master_triggered_#res := is_master_triggered_~__retres1~0; 810077#L336 activate_threads_#t~ret9 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 810078#L839 assume !(0 != activate_threads_~tmp~1); 810686#L839-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 810687#L343 assume !(1 == ~t1_pc~0); 810340#L343-2 is_transmit1_triggered_~__retres1~1 := 0; 810341#L354 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 810570#L355 activate_threads_#t~ret10 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 810571#L847 assume !(0 != activate_threads_~tmp___0~0); 811101#L847-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 811102#L362 assume !(1 == ~t2_pc~0); 810796#L362-2 is_transmit2_triggered_~__retres1~2 := 0; 810797#L373 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 811077#L374 activate_threads_#t~ret11 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 811078#L855 assume !(0 != activate_threads_~tmp___1~0); 811139#L855-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 811140#L381 assume !(1 == ~t3_pc~0); 811216#L381-2 is_transmit3_triggered_~__retres1~3 := 0; 811217#L392 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 811322#L393 activate_threads_#t~ret12 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 811323#L863 assume !(0 != activate_threads_~tmp___2~0); 809869#L863-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 809870#L400 assume !(1 == ~t4_pc~0); 809948#L400-2 is_transmit4_triggered_~__retres1~4 := 0; 809949#L411 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 810255#L412 activate_threads_#t~ret13 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 810256#L871 assume !(0 != activate_threads_~tmp___3~0); 810452#L871-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 810453#L419 assume !(1 == ~t5_pc~0); 810281#L419-2 is_transmit5_triggered_~__retres1~5 := 0; 810282#L430 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 810399#L431 activate_threads_#t~ret14 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 810400#L879 assume !(0 != activate_threads_~tmp___4~0); 810923#L879-2 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 810924#L438 assume !(1 == ~t6_pc~0); 810955#L438-2 is_transmit6_triggered_~__retres1~6 := 0; 810956#L449 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 810872#L450 activate_threads_#t~ret15 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 810873#L887 assume !(0 != activate_threads_~tmp___5~0); 811257#L887-2 assume !(1 == ~M_E~0); 811258#L752-1 assume !(1 == ~T1_E~0); 811280#L757-1 assume !(1 == ~T2_E~0); 811281#L762-1 assume !(1 == ~T3_E~0); 811342#L767-1 assume !(1 == ~T4_E~0); 811343#L772-1 assume !(1 == ~T5_E~0); 811242#L777-1 assume !(1 == ~T6_E~0); 811243#L782-1 assume !(1 == ~E_M~0); 810130#L787-1 assume !(1 == ~E_1~0); 810131#L792-1 assume !(1 == ~E_2~0); 809873#L797-1 assume !(1 == ~E_3~0); 809874#L802-1 assume !(1 == ~E_4~0); 810006#L807-1 assume !(1 == ~E_5~0); 810007#L812-1 assume !(1 == ~E_6~0); 814734#L1043-1 assume !false; 814735#L1044 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret1, eval_#t~nondet2, eval_~tmp_ndt_1~0, eval_#t~nondet3, eval_~tmp_ndt_2~0, eval_#t~nondet4, eval_~tmp_ndt_3~0, eval_#t~nondet5, eval_~tmp_ndt_4~0, eval_#t~nondet6, eval_~tmp_ndt_5~0, eval_#t~nondet7, eval_~tmp_ndt_6~0, eval_#t~nondet8, eval_~tmp_ndt_7~0, eval_~tmp~0;havoc eval_~tmp~0; 840982#L649 [2018-11-23 14:59:59,639 INFO L796 eck$LassoCheckResult]: Loop: 840982#L649 assume !false; 848964#L556 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~7;havoc exists_runnable_thread_~__retres1~7; 848963#L508 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7 := 1; 848962#L545 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~7; 848961#L546 eval_#t~ret1 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret1;havoc eval_#t~ret1; 848960#L560 assume 0 != eval_~tmp~0; 848959#L560-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0;eval_~tmp_ndt_1~0 := eval_#t~nondet2;havoc eval_#t~nondet2; 848957#L568 assume !(0 != eval_~tmp_ndt_1~0); 848882#L565 assume !(0 == ~t1_st~0); 848883#L579 assume !(0 == ~t2_st~0); 849024#L593 assume !(0 == ~t3_st~0); 849020#L607 assume !(0 == ~t4_st~0); 848967#L621 assume !(0 == ~t5_st~0); 848966#L635 assume !(0 == ~t6_st~0); 840982#L649 [2018-11-23 14:59:59,639 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 14:59:59,639 INFO L82 PathProgramCache]: Analyzing trace with hash 222018116, now seen corresponding path program 1 times [2018-11-23 14:59:59,640 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 14:59:59,640 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 14:59:59,640 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 14:59:59,640 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 14:59:59,640 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 14:59:59,643 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 14:59:59,670 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 14:59:59,670 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 14:59:59,670 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-23 14:59:59,671 INFO L799 eck$LassoCheckResult]: stem already infeasible [2018-11-23 14:59:59,671 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 14:59:59,671 INFO L82 PathProgramCache]: Analyzing trace with hash -982153583, now seen corresponding path program 2 times [2018-11-23 14:59:59,671 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 14:59:59,671 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 14:59:59,672 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 14:59:59,672 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 14:59:59,672 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 14:59:59,673 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-23 14:59:59,674 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-23 14:59:59,734 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-23 14:59:59,734 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-23 14:59:59,734 INFO L87 Difference]: Start difference. First operand 88289 states and 112592 transitions. cyclomatic complexity: 24447 Second operand 3 states. [2018-11-23 14:59:59,832 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 14:59:59,833 INFO L93 Difference]: Finished difference Result 61809 states and 78706 transitions. [2018-11-23 14:59:59,833 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-23 14:59:59,833 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 61809 states and 78706 transitions. [2018-11-23 14:59:59,969 INFO L131 ngComponentsAnalysis]: Automaton has 64 accepting balls. 41804 [2018-11-23 15:00:00,061 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 61809 states to 61809 states and 78706 transitions. [2018-11-23 15:00:00,061 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 42464 [2018-11-23 15:00:00,079 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 42464 [2018-11-23 15:00:00,079 INFO L73 IsDeterministic]: Start isDeterministic. Operand 61809 states and 78706 transitions. [2018-11-23 15:00:00,080 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2018-11-23 15:00:00,080 INFO L705 BuchiCegarLoop]: Abstraction has 61809 states and 78706 transitions. [2018-11-23 15:00:00,104 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 61809 states and 78706 transitions. [2018-11-23 15:00:00,632 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 61809 to 61809. [2018-11-23 15:00:00,632 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 61809 states. [2018-11-23 15:00:00,690 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 61809 states to 61809 states and 78706 transitions. [2018-11-23 15:00:00,690 INFO L728 BuchiCegarLoop]: Abstraction has 61809 states and 78706 transitions. [2018-11-23 15:00:00,691 INFO L608 BuchiCegarLoop]: Abstraction has 61809 states and 78706 transitions. [2018-11-23 15:00:00,691 INFO L442 BuchiCegarLoop]: ======== Iteration 31============ [2018-11-23 15:00:00,691 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 61809 states and 78706 transitions. [2018-11-23 15:00:00,792 INFO L131 ngComponentsAnalysis]: Automaton has 64 accepting balls. 41804 [2018-11-23 15:00:00,792 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-23 15:00:00,792 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-23 15:00:00,793 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 15:00:00,793 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 15:00:00,793 INFO L794 eck$LassoCheckResult]: Stem: 961107#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0; 960863#L-1 havoc main_#res;havoc main_~__retres1~8;havoc main_~__retres1~8;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 960002#L1006 havoc start_simulation_#t~ret17, start_simulation_#t~ret18, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 960003#L458 assume 1 == ~m_i~0;~m_st~0 := 0; 960713#L465-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 960714#L470-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 960496#L475-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 960497#L480-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 960583#L485-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 960168#L490-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 960169#L495-1 assume !(0 == ~M_E~0); 960746#L674-1 assume !(0 == ~T1_E~0); 960747#L679-1 assume !(0 == ~T2_E~0); 960527#L684-1 assume !(0 == ~T3_E~0); 960528#L689-1 assume !(0 == ~T4_E~0); 961049#L694-1 assume !(0 == ~T5_E~0); 960241#L699-1 assume !(0 == ~T6_E~0); 960242#L704-1 assume !(0 == ~E_M~0); 959926#L709-1 assume !(0 == ~E_1~0); 959927#L714-1 assume !(0 == ~E_2~0); 960089#L719-1 assume !(0 == ~E_3~0); 960090#L724-1 assume !(0 == ~E_4~0); 960728#L729-1 assume !(0 == ~E_5~0); 960729#L734-1 assume !(0 == ~E_6~0); 960513#L739-1 havoc activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 960306#L324 assume !(1 == ~m_pc~0); 960307#L324-2 is_master_triggered_~__retres1~0 := 0; 960328#L335 is_master_triggered_#res := is_master_triggered_~__retres1~0; 960177#L336 activate_threads_#t~ret9 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 960178#L839 assume !(0 != activate_threads_~tmp~1); 960761#L839-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 960405#L343 assume !(1 == ~t1_pc~0); 960406#L343-2 is_transmit1_triggered_~__retres1~1 := 0; 960403#L354 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 960404#L355 activate_threads_#t~ret10 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 960659#L847 assume !(0 != activate_threads_~tmp___0~0); 961172#L847-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 960972#L362 assume !(1 == ~t2_pc~0); 960874#L362-2 is_transmit2_triggered_~__retres1~2 := 0; 960875#L373 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 960971#L374 activate_threads_#t~ret11 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 961149#L855 assume !(0 != activate_threads_~tmp___1~0); 961192#L855-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 961201#L381 assume !(1 == ~t3_pc~0); 961270#L381-2 is_transmit3_triggered_~__retres1~3 := 0; 961268#L392 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 961269#L393 activate_threads_#t~ret12 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 960027#L863 assume !(0 != activate_threads_~tmp___2~0); 959977#L863-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 959978#L400 assume !(1 == ~t4_pc~0); 960051#L400-2 is_transmit4_triggered_~__retres1~4 := 0; 960052#L411 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 960082#L412 activate_threads_#t~ret13 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 960356#L871 assume !(0 != activate_threads_~tmp___3~0); 960541#L871-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 960548#L419 assume !(1 == ~t5_pc~0); 960377#L419-2 is_transmit5_triggered_~__retres1~5 := 0; 960378#L430 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 960498#L431 activate_threads_#t~ret14 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 960499#L879 assume !(0 != activate_threads_~tmp___4~0); 961005#L879-2 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 961006#L438 assume !(1 == ~t6_pc~0); 961031#L438-2 is_transmit6_triggered_~__retres1~6 := 0; 961032#L449 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 960952#L450 activate_threads_#t~ret15 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 960953#L887 assume !(0 != activate_threads_~tmp___5~0); 961308#L887-2 assume !(1 == ~M_E~0); 960109#L752-1 assume !(1 == ~T1_E~0); 960110#L757-1 assume !(1 == ~T2_E~0); 960720#L762-1 assume !(1 == ~T3_E~0); 960721#L767-1 assume !(1 == ~T4_E~0); 960508#L772-1 assume !(1 == ~T5_E~0); 960509#L777-1 assume !(1 == ~T6_E~0); 961045#L782-1 assume !(1 == ~E_M~0); 960233#L787-1 assume !(1 == ~E_1~0); 960234#L792-1 assume !(1 == ~E_2~0); 959985#L797-1 assume !(1 == ~E_3~0); 959986#L802-1 assume !(1 == ~E_4~0); 960107#L807-1 assume !(1 == ~E_5~0); 960108#L812-1 assume !(1 == ~E_6~0); 961329#L1043-1 assume !false; 967168#L1044 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret1, eval_#t~nondet2, eval_~tmp_ndt_1~0, eval_#t~nondet3, eval_~tmp_ndt_2~0, eval_#t~nondet4, eval_~tmp_ndt_3~0, eval_#t~nondet5, eval_~tmp_ndt_4~0, eval_#t~nondet6, eval_~tmp_ndt_5~0, eval_#t~nondet7, eval_~tmp_ndt_6~0, eval_#t~nondet8, eval_~tmp_ndt_7~0, eval_~tmp~0;havoc eval_~tmp~0; 984206#L649 [2018-11-23 15:00:00,793 INFO L796 eck$LassoCheckResult]: Loop: 984206#L649 assume !false; 984204#L556 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~7;havoc exists_runnable_thread_~__retres1~7; 984202#L508 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7 := 1; 984200#L545 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~7; 984198#L546 eval_#t~ret1 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret1;havoc eval_#t~ret1; 984196#L560 assume 0 != eval_~tmp~0; 984194#L560-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0;eval_~tmp_ndt_1~0 := eval_#t~nondet2;havoc eval_#t~nondet2; 984190#L568 assume !(0 != eval_~tmp_ndt_1~0); 984188#L565 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0;eval_~tmp_ndt_2~0 := eval_#t~nondet3;havoc eval_#t~nondet3; 984184#L582 assume !(0 != eval_~tmp_ndt_2~0); 984183#L579 assume !(0 == ~t2_st~0); 984182#L593 assume !(0 == ~t3_st~0); 984217#L607 assume !(0 == ~t4_st~0); 984210#L621 assume !(0 == ~t5_st~0); 984209#L635 assume !(0 == ~t6_st~0); 984206#L649 [2018-11-23 15:00:00,793 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 15:00:00,793 INFO L82 PathProgramCache]: Analyzing trace with hash -617015546, now seen corresponding path program 2 times [2018-11-23 15:00:00,794 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 15:00:00,794 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 15:00:00,794 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 15:00:00,794 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-23 15:00:00,794 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 15:00:00,799 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-23 15:00:00,803 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-23 15:00:00,814 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 15:00:00,815 INFO L82 PathProgramCache]: Analyzing trace with hash -1780835902, now seen corresponding path program 1 times [2018-11-23 15:00:00,815 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 15:00:00,815 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 15:00:00,815 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 15:00:00,816 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-23 15:00:00,816 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 15:00:00,817 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-23 15:00:00,818 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-23 15:00:00,820 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 15:00:00,820 INFO L82 PathProgramCache]: Analyzing trace with hash 1145698333, now seen corresponding path program 1 times [2018-11-23 15:00:00,820 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 15:00:00,820 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 15:00:00,821 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 15:00:00,821 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 15:00:00,821 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 15:00:00,825 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 15:00:00,858 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 15:00:00,858 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 15:00:00,858 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-23 15:00:00,922 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-23 15:00:00,922 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-23 15:00:00,923 INFO L87 Difference]: Start difference. First operand 61809 states and 78706 transitions. cyclomatic complexity: 16993 Second operand 3 states. [2018-11-23 15:00:01,077 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 15:00:01,077 INFO L93 Difference]: Finished difference Result 87158 states and 110623 transitions. [2018-11-23 15:00:01,077 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-23 15:00:01,078 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 87158 states and 110623 transitions. [2018-11-23 15:00:01,263 INFO L131 ngComponentsAnalysis]: Automaton has 64 accepting balls. 59148 [2018-11-23 15:00:01,387 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 87158 states to 87158 states and 110623 transitions. [2018-11-23 15:00:01,388 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 60024 [2018-11-23 15:00:01,411 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 60024 [2018-11-23 15:00:01,412 INFO L73 IsDeterministic]: Start isDeterministic. Operand 87158 states and 110623 transitions. [2018-11-23 15:00:01,413 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2018-11-23 15:00:01,413 INFO L705 BuchiCegarLoop]: Abstraction has 87158 states and 110623 transitions. [2018-11-23 15:00:01,452 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 87158 states and 110623 transitions. [2018-11-23 15:00:01,818 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 87158 to 83432. [2018-11-23 15:00:01,818 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 83432 states. [2018-11-23 15:00:01,899 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 83432 states to 83432 states and 106033 transitions. [2018-11-23 15:00:01,899 INFO L728 BuchiCegarLoop]: Abstraction has 83432 states and 106033 transitions. [2018-11-23 15:00:01,899 INFO L608 BuchiCegarLoop]: Abstraction has 83432 states and 106033 transitions. [2018-11-23 15:00:01,899 INFO L442 BuchiCegarLoop]: ======== Iteration 32============ [2018-11-23 15:00:01,899 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 83432 states and 106033 transitions. [2018-11-23 15:00:02,034 INFO L131 ngComponentsAnalysis]: Automaton has 64 accepting balls. 56664 [2018-11-23 15:00:02,035 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-23 15:00:02,035 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-23 15:00:02,035 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 15:00:02,035 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 15:00:02,035 INFO L794 eck$LassoCheckResult]: Stem: 1110119#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0; 1109864#L-1 havoc main_#res;havoc main_~__retres1~8;havoc main_~__retres1~8;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 1108979#L1006 havoc start_simulation_#t~ret17, start_simulation_#t~ret18, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 1108980#L458 assume 1 == ~m_i~0;~m_st~0 := 0; 1109707#L465-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1109708#L470-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1109480#L475-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 1109481#L480-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 1109571#L485-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 1109148#L490-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 1109149#L495-1 assume !(0 == ~M_E~0); 1109738#L674-1 assume !(0 == ~T1_E~0); 1109739#L679-1 assume !(0 == ~T2_E~0); 1109510#L684-1 assume !(0 == ~T3_E~0); 1109511#L689-1 assume !(0 == ~T4_E~0); 1110060#L694-1 assume !(0 == ~T5_E~0); 1109224#L699-1 assume !(0 == ~T6_E~0); 1109225#L704-1 assume !(0 == ~E_M~0); 1108901#L709-1 assume !(0 == ~E_1~0); 1108902#L714-1 assume !(0 == ~E_2~0); 1109069#L719-1 assume !(0 == ~E_3~0); 1109070#L724-1 assume !(0 == ~E_4~0); 1109721#L729-1 assume !(0 == ~E_5~0); 1109722#L734-1 assume !(0 == ~E_6~0); 1109497#L739-1 havoc activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 1109298#L324 assume !(1 == ~m_pc~0); 1109299#L324-2 is_master_triggered_~__retres1~0 := 0; 1109320#L335 is_master_triggered_#res := is_master_triggered_~__retres1~0; 1109157#L336 activate_threads_#t~ret9 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 1109158#L839 assume !(0 != activate_threads_~tmp~1); 1109754#L839-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 1109395#L343 assume !(1 == ~t1_pc~0); 1109396#L343-2 is_transmit1_triggered_~__retres1~1 := 0; 1109393#L354 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 1109394#L355 activate_threads_#t~ret10 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 1109648#L847 assume !(0 != activate_threads_~tmp___0~0); 1110182#L847-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 1109981#L362 assume !(1 == ~t2_pc~0); 1109875#L362-2 is_transmit2_triggered_~__retres1~2 := 0; 1109876#L373 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 1109980#L374 activate_threads_#t~ret11 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 1110157#L855 assume !(0 != activate_threads_~tmp___1~0); 1110204#L855-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 1110214#L381 assume !(1 == ~t3_pc~0); 1110278#L381-2 is_transmit3_triggered_~__retres1~3 := 0; 1110276#L392 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 1110277#L393 activate_threads_#t~ret12 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 1109006#L863 assume !(0 != activate_threads_~tmp___2~0); 1108950#L863-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 1108951#L400 assume !(1 == ~t4_pc~0); 1109028#L400-2 is_transmit4_triggered_~__retres1~4 := 0; 1109029#L411 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 1109061#L412 activate_threads_#t~ret13 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 1109350#L871 assume !(0 != activate_threads_~tmp___3~0); 1109527#L871-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 1109534#L419 assume !(1 == ~t5_pc~0); 1109367#L419-2 is_transmit5_triggered_~__retres1~5 := 0; 1109368#L430 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 1109482#L431 activate_threads_#t~ret14 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 1109483#L879 assume !(0 != activate_threads_~tmp___4~0); 1110013#L879-2 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 1110014#L438 assume !(1 == ~t6_pc~0); 1110043#L438-2 is_transmit6_triggered_~__retres1~6 := 0; 1110044#L449 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 1109960#L450 activate_threads_#t~ret15 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 1109961#L887 assume !(0 != activate_threads_~tmp___5~0); 1110317#L887-2 assume !(1 == ~M_E~0); 1109089#L752-1 assume !(1 == ~T1_E~0); 1109090#L757-1 assume !(1 == ~T2_E~0); 1109714#L762-1 assume !(1 == ~T3_E~0); 1109715#L767-1 assume !(1 == ~T4_E~0); 1109492#L772-1 assume !(1 == ~T5_E~0); 1109493#L777-1 assume !(1 == ~T6_E~0); 1110056#L782-1 assume !(1 == ~E_M~0); 1109215#L787-1 assume !(1 == ~E_1~0); 1109216#L792-1 assume !(1 == ~E_2~0); 1108959#L797-1 assume !(1 == ~E_3~0); 1108960#L802-1 assume !(1 == ~E_4~0); 1109087#L807-1 assume !(1 == ~E_5~0); 1109088#L812-1 assume !(1 == ~E_6~0); 1110334#L1043-1 assume !false; 1120221#L1044 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret1, eval_#t~nondet2, eval_~tmp_ndt_1~0, eval_#t~nondet3, eval_~tmp_ndt_2~0, eval_#t~nondet4, eval_~tmp_ndt_3~0, eval_#t~nondet5, eval_~tmp_ndt_4~0, eval_#t~nondet6, eval_~tmp_ndt_5~0, eval_#t~nondet7, eval_~tmp_ndt_6~0, eval_#t~nondet8, eval_~tmp_ndt_7~0, eval_~tmp~0;havoc eval_~tmp~0; 1137539#L649 [2018-11-23 15:00:02,035 INFO L796 eck$LassoCheckResult]: Loop: 1137539#L649 assume !false; 1137537#L556 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~7;havoc exists_runnable_thread_~__retres1~7; 1137536#L508 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7 := 1; 1137535#L545 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~7; 1137533#L546 eval_#t~ret1 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret1;havoc eval_#t~ret1; 1137530#L560 assume 0 != eval_~tmp~0; 1137528#L560-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0;eval_~tmp_ndt_1~0 := eval_#t~nondet2;havoc eval_#t~nondet2; 1137525#L568 assume !(0 != eval_~tmp_ndt_1~0); 1137526#L565 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0;eval_~tmp_ndt_2~0 := eval_#t~nondet3;havoc eval_#t~nondet3; 1138048#L582 assume !(0 != eval_~tmp_ndt_2~0); 1138046#L579 assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0;eval_~tmp_ndt_3~0 := eval_#t~nondet4;havoc eval_#t~nondet4; 1138043#L596 assume !(0 != eval_~tmp_ndt_3~0); 1138041#L593 assume !(0 == ~t3_st~0); 1138034#L607 assume !(0 == ~t4_st~0); 1138027#L621 assume !(0 == ~t5_st~0); 1137543#L635 assume !(0 == ~t6_st~0); 1137539#L649 [2018-11-23 15:00:02,035 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 15:00:02,036 INFO L82 PathProgramCache]: Analyzing trace with hash -617015546, now seen corresponding path program 3 times [2018-11-23 15:00:02,036 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 15:00:02,036 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 15:00:02,036 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 15:00:02,036 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 15:00:02,036 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 15:00:02,040 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-23 15:00:02,045 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-23 15:00:02,057 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 15:00:02,057 INFO L82 PathProgramCache]: Analyzing trace with hash -940480819, now seen corresponding path program 1 times [2018-11-23 15:00:02,057 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 15:00:02,057 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 15:00:02,057 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 15:00:02,058 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-23 15:00:02,058 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 15:00:02,059 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-23 15:00:02,060 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-23 15:00:02,062 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 15:00:02,062 INFO L82 PathProgramCache]: Analyzing trace with hash -412232750, now seen corresponding path program 1 times [2018-11-23 15:00:02,062 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 15:00:02,062 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 15:00:02,063 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 15:00:02,063 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 15:00:02,063 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 15:00:02,067 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 15:00:02,107 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 15:00:02,107 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 15:00:02,107 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-23 15:00:02,173 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-23 15:00:02,173 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-23 15:00:02,173 INFO L87 Difference]: Start difference. First operand 83432 states and 106033 transitions. cyclomatic complexity: 22697 Second operand 3 states. [2018-11-23 15:00:02,468 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 15:00:02,468 INFO L93 Difference]: Finished difference Result 151929 states and 192382 transitions. [2018-11-23 15:00:02,471 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-23 15:00:02,471 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 151929 states and 192382 transitions. [2018-11-23 15:00:03,226 INFO L131 ngComponentsAnalysis]: Automaton has 64 accepting balls. 101526 [2018-11-23 15:00:03,418 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 151929 states to 151929 states and 192382 transitions. [2018-11-23 15:00:03,419 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 103194 [2018-11-23 15:00:03,453 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 103194 [2018-11-23 15:00:03,453 INFO L73 IsDeterministic]: Start isDeterministic. Operand 151929 states and 192382 transitions. [2018-11-23 15:00:03,458 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2018-11-23 15:00:03,458 INFO L705 BuchiCegarLoop]: Abstraction has 151929 states and 192382 transitions. [2018-11-23 15:00:03,511 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 151929 states and 192382 transitions. [2018-11-23 15:00:04,187 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 151929 to 151929. [2018-11-23 15:00:04,187 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 151929 states. [2018-11-23 15:00:04,351 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 151929 states to 151929 states and 192382 transitions. [2018-11-23 15:00:04,351 INFO L728 BuchiCegarLoop]: Abstraction has 151929 states and 192382 transitions. [2018-11-23 15:00:04,351 INFO L608 BuchiCegarLoop]: Abstraction has 151929 states and 192382 transitions. [2018-11-23 15:00:04,352 INFO L442 BuchiCegarLoop]: ======== Iteration 33============ [2018-11-23 15:00:04,352 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 151929 states and 192382 transitions. [2018-11-23 15:00:04,611 INFO L131 ngComponentsAnalysis]: Automaton has 64 accepting balls. 101526 [2018-11-23 15:00:04,611 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-23 15:00:04,611 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-23 15:00:04,612 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 15:00:04,612 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 15:00:04,612 INFO L794 eck$LassoCheckResult]: Stem: 1345517#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0; 1345257#L-1 havoc main_#res;havoc main_~__retres1~8;havoc main_~__retres1~8;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 1344346#L1006 havoc start_simulation_#t~ret17, start_simulation_#t~ret18, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 1344347#L458 assume 1 == ~m_i~0;~m_st~0 := 0; 1345106#L465-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1345107#L470-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1344874#L475-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 1344875#L480-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 1344964#L485-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 1344522#L490-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 1344523#L495-1 assume !(0 == ~M_E~0); 1345138#L674-1 assume !(0 == ~T1_E~0); 1345139#L679-1 assume !(0 == ~T2_E~0); 1344904#L684-1 assume !(0 == ~T3_E~0); 1344905#L689-1 assume !(0 == ~T4_E~0); 1345458#L694-1 assume !(0 == ~T5_E~0); 1344601#L699-1 assume !(0 == ~T6_E~0); 1344602#L704-1 assume !(0 == ~E_M~0); 1344270#L709-1 assume !(0 == ~E_1~0); 1344271#L714-1 assume !(0 == ~E_2~0); 1344443#L719-1 assume !(0 == ~E_3~0); 1344444#L724-1 assume !(0 == ~E_4~0); 1345119#L729-1 assume !(0 == ~E_5~0); 1345120#L734-1 assume !(0 == ~E_6~0); 1344889#L739-1 havoc activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 1344685#L324 assume !(1 == ~m_pc~0); 1344686#L324-2 is_master_triggered_~__retres1~0 := 0; 1344704#L335 is_master_triggered_#res := is_master_triggered_~__retres1~0; 1344533#L336 activate_threads_#t~ret9 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 1344534#L839 assume !(0 != activate_threads_~tmp~1); 1345154#L839-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 1344787#L343 assume !(1 == ~t1_pc~0); 1344788#L343-2 is_transmit1_triggered_~__retres1~1 := 0; 1344785#L354 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 1344786#L355 activate_threads_#t~ret10 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 1345047#L847 assume !(0 != activate_threads_~tmp___0~0); 1345590#L847-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 1345375#L362 assume !(1 == ~t2_pc~0); 1345273#L362-2 is_transmit2_triggered_~__retres1~2 := 0; 1345274#L373 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 1345374#L374 activate_threads_#t~ret11 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 1345562#L855 assume !(0 != activate_threads_~tmp___1~0); 1345615#L855-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 1345624#L381 assume !(1 == ~t3_pc~0); 1345690#L381-2 is_transmit3_triggered_~__retres1~3 := 0; 1345688#L392 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 1345689#L393 activate_threads_#t~ret12 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 1344370#L863 assume !(0 != activate_threads_~tmp___2~0); 1344319#L863-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 1344320#L400 assume !(1 == ~t4_pc~0); 1344398#L400-2 is_transmit4_triggered_~__retres1~4 := 0; 1344399#L411 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 1344435#L412 activate_threads_#t~ret13 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 1344741#L871 assume !(0 != activate_threads_~tmp___3~0); 1344919#L871-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 1344926#L419 assume !(1 == ~t5_pc~0); 1344758#L419-2 is_transmit5_triggered_~__retres1~5 := 0; 1344759#L430 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 1344876#L431 activate_threads_#t~ret14 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 1344877#L879 assume !(0 != activate_threads_~tmp___4~0); 1345410#L879-2 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 1345411#L438 assume !(1 == ~t6_pc~0); 1345442#L438-2 is_transmit6_triggered_~__retres1~6 := 0; 1345443#L449 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 1345353#L450 activate_threads_#t~ret15 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 1345354#L887 assume !(0 != activate_threads_~tmp___5~0); 1345742#L887-2 assume !(1 == ~M_E~0); 1344463#L752-1 assume !(1 == ~T1_E~0); 1344464#L757-1 assume !(1 == ~T2_E~0); 1345112#L762-1 assume !(1 == ~T3_E~0); 1345113#L767-1 assume !(1 == ~T4_E~0); 1344887#L772-1 assume !(1 == ~T5_E~0); 1344888#L777-1 assume !(1 == ~T6_E~0); 1345454#L782-1 assume !(1 == ~E_M~0); 1344592#L787-1 assume !(1 == ~E_1~0); 1344593#L792-1 assume !(1 == ~E_2~0); 1344323#L797-1 assume !(1 == ~E_3~0); 1344324#L802-1 assume !(1 == ~E_4~0); 1344461#L807-1 assume !(1 == ~E_5~0); 1344462#L812-1 assume !(1 == ~E_6~0); 1345761#L1043-1 assume !false; 1363761#L1044 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret1, eval_#t~nondet2, eval_~tmp_ndt_1~0, eval_#t~nondet3, eval_~tmp_ndt_2~0, eval_#t~nondet4, eval_~tmp_ndt_3~0, eval_#t~nondet5, eval_~tmp_ndt_4~0, eval_#t~nondet6, eval_~tmp_ndt_5~0, eval_#t~nondet7, eval_~tmp_ndt_6~0, eval_#t~nondet8, eval_~tmp_ndt_7~0, eval_~tmp~0;havoc eval_~tmp~0; 1439886#L649 [2018-11-23 15:00:04,612 INFO L796 eck$LassoCheckResult]: Loop: 1439886#L649 assume !false; 1439884#L556 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~7;havoc exists_runnable_thread_~__retres1~7; 1439882#L508 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7 := 1; 1439880#L545 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~7; 1439878#L546 eval_#t~ret1 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret1;havoc eval_#t~ret1; 1439876#L560 assume 0 != eval_~tmp~0; 1439874#L560-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0;eval_~tmp_ndt_1~0 := eval_#t~nondet2;havoc eval_#t~nondet2; 1439871#L568 assume !(0 != eval_~tmp_ndt_1~0); 1439868#L565 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0;eval_~tmp_ndt_2~0 := eval_#t~nondet3;havoc eval_#t~nondet3; 1439865#L582 assume !(0 != eval_~tmp_ndt_2~0); 1439866#L579 assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0;eval_~tmp_ndt_3~0 := eval_#t~nondet4;havoc eval_#t~nondet4; 1457101#L596 assume !(0 != eval_~tmp_ndt_3~0); 1414556#L593 assume 0 == ~t3_st~0;havoc eval_~tmp_ndt_4~0;eval_~tmp_ndt_4~0 := eval_#t~nondet5;havoc eval_#t~nondet5; 1414553#L610 assume !(0 != eval_~tmp_ndt_4~0); 1414554#L607 assume !(0 == ~t4_st~0); 1439892#L621 assume !(0 == ~t5_st~0); 1439890#L635 assume !(0 == ~t6_st~0); 1439886#L649 [2018-11-23 15:00:04,613 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 15:00:04,613 INFO L82 PathProgramCache]: Analyzing trace with hash -617015546, now seen corresponding path program 4 times [2018-11-23 15:00:04,613 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 15:00:04,613 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 15:00:04,614 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 15:00:04,614 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 15:00:04,614 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 15:00:04,618 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-23 15:00:04,622 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-23 15:00:04,640 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 15:00:04,640 INFO L82 PathProgramCache]: Analyzing trace with hash 720702854, now seen corresponding path program 1 times [2018-11-23 15:00:04,640 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 15:00:04,640 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 15:00:04,641 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 15:00:04,641 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-23 15:00:04,641 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 15:00:04,642 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-23 15:00:04,644 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-23 15:00:04,645 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 15:00:04,646 INFO L82 PathProgramCache]: Analyzing trace with hash -83476191, now seen corresponding path program 1 times [2018-11-23 15:00:04,646 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 15:00:04,646 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 15:00:04,646 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 15:00:04,646 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 15:00:04,646 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 15:00:04,651 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 15:00:04,683 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 15:00:04,683 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 15:00:04,684 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-23 15:00:04,756 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-23 15:00:04,756 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-23 15:00:04,756 INFO L87 Difference]: Start difference. First operand 151929 states and 192382 transitions. cyclomatic complexity: 40549 Second operand 3 states. [2018-11-23 15:00:05,498 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 15:00:05,498 INFO L93 Difference]: Finished difference Result 217126 states and 274666 transitions. [2018-11-23 15:00:05,498 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-23 15:00:05,498 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 217126 states and 274666 transitions. [2018-11-23 15:00:05,982 INFO L131 ngComponentsAnalysis]: Automaton has 64 accepting balls. 145415 [2018-11-23 15:00:06,286 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 217126 states to 217126 states and 274666 transitions. [2018-11-23 15:00:06,286 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 147659 [2018-11-23 15:00:06,339 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 147659 [2018-11-23 15:00:06,339 INFO L73 IsDeterministic]: Start isDeterministic. Operand 217126 states and 274666 transitions. [2018-11-23 15:00:06,341 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2018-11-23 15:00:06,342 INFO L705 BuchiCegarLoop]: Abstraction has 217126 states and 274666 transitions. [2018-11-23 15:00:06,416 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 217126 states and 274666 transitions. [2018-11-23 15:00:07,459 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 217126 to 211780. [2018-11-23 15:00:07,459 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 211780 states. [2018-11-23 15:00:07,697 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 211780 states to 211780 states and 268186 transitions. [2018-11-23 15:00:07,697 INFO L728 BuchiCegarLoop]: Abstraction has 211780 states and 268186 transitions. [2018-11-23 15:00:07,697 INFO L608 BuchiCegarLoop]: Abstraction has 211780 states and 268186 transitions. [2018-11-23 15:00:07,697 INFO L442 BuchiCegarLoop]: ======== Iteration 34============ [2018-11-23 15:00:07,698 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 211780 states and 268186 transitions. [2018-11-23 15:00:08,086 INFO L131 ngComponentsAnalysis]: Automaton has 64 accepting balls. 141851 [2018-11-23 15:00:08,086 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-23 15:00:08,086 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-23 15:00:08,087 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 15:00:08,087 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 15:00:08,087 INFO L794 eck$LassoCheckResult]: Stem: 1714615#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0; 1714348#L-1 havoc main_#res;havoc main_~__retres1~8;havoc main_~__retres1~8;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 1713418#L1006 havoc start_simulation_#t~ret17, start_simulation_#t~ret18, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 1713419#L458 assume 1 == ~m_i~0;~m_st~0 := 0; 1714188#L465-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1714189#L470-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1713954#L475-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 1713955#L480-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 1714047#L485-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 1713598#L490-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 1713599#L495-1 assume !(0 == ~M_E~0); 1714219#L674-1 assume !(0 == ~T1_E~0); 1714220#L679-1 assume !(0 == ~T2_E~0); 1713987#L684-1 assume !(0 == ~T3_E~0); 1713988#L689-1 assume !(0 == ~T4_E~0); 1714554#L694-1 assume !(0 == ~T5_E~0); 1713677#L699-1 assume !(0 == ~T6_E~0); 1713678#L704-1 assume !(0 == ~E_M~0); 1713333#L709-1 assume !(0 == ~E_1~0); 1713334#L714-1 assume !(0 == ~E_2~0); 1713519#L719-1 assume !(0 == ~E_3~0); 1713520#L724-1 assume !(0 == ~E_4~0); 1714201#L729-1 assume !(0 == ~E_5~0); 1714202#L734-1 assume !(0 == ~E_6~0); 1713971#L739-1 havoc activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 1713745#L324 assume !(1 == ~m_pc~0); 1713746#L324-2 is_master_triggered_~__retres1~0 := 0; 1713769#L335 is_master_triggered_#res := is_master_triggered_~__retres1~0; 1713608#L336 activate_threads_#t~ret9 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 1713609#L839 assume !(0 != activate_threads_~tmp~1); 1714237#L839-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 1713862#L343 assume !(1 == ~t1_pc~0); 1713863#L343-2 is_transmit1_triggered_~__retres1~1 := 0; 1713860#L354 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 1713861#L355 activate_threads_#t~ret10 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 1714129#L847 assume !(0 != activate_threads_~tmp___0~0); 1714687#L847-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 1714461#L362 assume !(1 == ~t2_pc~0); 1714359#L362-2 is_transmit2_triggered_~__retres1~2 := 0; 1714360#L373 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 1714460#L374 activate_threads_#t~ret11 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 1714655#L855 assume !(0 != activate_threads_~tmp___1~0); 1714717#L855-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 1714726#L381 assume !(1 == ~t3_pc~0); 1714799#L381-2 is_transmit3_triggered_~__retres1~3 := 0; 1714797#L392 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 1714798#L393 activate_threads_#t~ret12 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 1713449#L863 assume !(0 != activate_threads_~tmp___2~0); 1713388#L863-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 1713389#L400 assume !(1 == ~t4_pc~0); 1713474#L400-2 is_transmit4_triggered_~__retres1~4 := 0; 1713475#L411 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 1713511#L412 activate_threads_#t~ret13 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 1713806#L871 assume !(0 != activate_threads_~tmp___3~0); 1714003#L871-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 1714010#L419 assume !(1 == ~t5_pc~0); 1713832#L419-2 is_transmit5_triggered_~__retres1~5 := 0; 1713833#L430 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 1713956#L431 activate_threads_#t~ret14 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 1713957#L879 assume !(0 != activate_threads_~tmp___4~0); 1714495#L879-2 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 1714496#L438 assume !(1 == ~t6_pc~0); 1714530#L438-2 is_transmit6_triggered_~__retres1~6 := 0; 1714531#L449 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 1714441#L450 activate_threads_#t~ret15 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 1714442#L887 assume !(0 != activate_threads_~tmp___5~0); 1714851#L887-2 assume !(1 == ~M_E~0); 1713539#L752-1 assume !(1 == ~T1_E~0); 1713540#L757-1 assume !(1 == ~T2_E~0); 1714194#L762-1 assume !(1 == ~T3_E~0); 1714195#L767-1 assume !(1 == ~T4_E~0); 1713967#L772-1 assume !(1 == ~T5_E~0); 1713968#L777-1 assume !(1 == ~T6_E~0); 1714551#L782-1 assume !(1 == ~E_M~0); 1713667#L787-1 assume !(1 == ~E_1~0); 1713668#L792-1 assume !(1 == ~E_2~0); 1713398#L797-1 assume !(1 == ~E_3~0); 1713399#L802-1 assume !(1 == ~E_4~0); 1713537#L807-1 assume !(1 == ~E_5~0); 1713538#L812-1 assume !(1 == ~E_6~0); 1714872#L1043-1 assume !false; 1722683#L1044 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret1, eval_#t~nondet2, eval_~tmp_ndt_1~0, eval_#t~nondet3, eval_~tmp_ndt_2~0, eval_#t~nondet4, eval_~tmp_ndt_3~0, eval_#t~nondet5, eval_~tmp_ndt_4~0, eval_#t~nondet6, eval_~tmp_ndt_5~0, eval_#t~nondet7, eval_~tmp_ndt_6~0, eval_#t~nondet8, eval_~tmp_ndt_7~0, eval_~tmp~0;havoc eval_~tmp~0; 1814845#L649 [2018-11-23 15:00:08,087 INFO L796 eck$LassoCheckResult]: Loop: 1814845#L649 assume !false; 1815653#L556 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~7;havoc exists_runnable_thread_~__retres1~7; 1815645#L508 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7 := 1; 1815636#L545 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~7; 1815626#L546 eval_#t~ret1 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret1;havoc eval_#t~ret1; 1815617#L560 assume 0 != eval_~tmp~0; 1815616#L560-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0;eval_~tmp_ndt_1~0 := eval_#t~nondet2;havoc eval_#t~nondet2; 1815614#L568 assume !(0 != eval_~tmp_ndt_1~0); 1815612#L565 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0;eval_~tmp_ndt_2~0 := eval_#t~nondet3;havoc eval_#t~nondet3; 1815558#L582 assume !(0 != eval_~tmp_ndt_2~0); 1815551#L579 assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0;eval_~tmp_ndt_3~0 := eval_#t~nondet4;havoc eval_#t~nondet4; 1815543#L596 assume !(0 != eval_~tmp_ndt_3~0); 1814877#L593 assume 0 == ~t3_st~0;havoc eval_~tmp_ndt_4~0;eval_~tmp_ndt_4~0 := eval_#t~nondet5;havoc eval_#t~nondet5; 1814872#L610 assume !(0 != eval_~tmp_ndt_4~0); 1814866#L607 assume 0 == ~t4_st~0;havoc eval_~tmp_ndt_5~0;eval_~tmp_ndt_5~0 := eval_#t~nondet6;havoc eval_#t~nondet6; 1814861#L624 assume !(0 != eval_~tmp_ndt_5~0); 1814854#L621 assume !(0 == ~t5_st~0); 1814849#L635 assume !(0 == ~t6_st~0); 1814845#L649 [2018-11-23 15:00:08,087 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 15:00:08,088 INFO L82 PathProgramCache]: Analyzing trace with hash -617015546, now seen corresponding path program 5 times [2018-11-23 15:00:08,088 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 15:00:08,088 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 15:00:08,088 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 15:00:08,088 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 15:00:08,089 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 15:00:08,092 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-23 15:00:08,097 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-23 15:00:08,108 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 15:00:08,108 INFO L82 PathProgramCache]: Analyzing trace with hash 860851977, now seen corresponding path program 1 times [2018-11-23 15:00:08,108 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 15:00:08,108 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 15:00:08,109 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 15:00:08,109 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-23 15:00:08,109 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 15:00:08,111 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-23 15:00:08,112 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-23 15:00:08,114 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 15:00:08,114 INFO L82 PathProgramCache]: Analyzing trace with hash 1701105358, now seen corresponding path program 1 times [2018-11-23 15:00:08,114 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 15:00:08,114 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 15:00:08,115 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 15:00:08,115 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 15:00:08,115 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 15:00:08,119 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 15:00:08,152 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 15:00:08,152 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 15:00:08,152 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-23 15:00:08,255 WARN L180 SmtUtils]: Spent 102.00 ms on a formula simplification. DAG size of input: 47 DAG size of output: 45 [2018-11-23 15:00:08,280 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-23 15:00:08,280 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-23 15:00:08,280 INFO L87 Difference]: Start difference. First operand 211780 states and 268186 transitions. cyclomatic complexity: 56502 Second operand 3 states. [2018-11-23 15:00:09,325 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 15:00:09,325 INFO L93 Difference]: Finished difference Result 374057 states and 472192 transitions. [2018-11-23 15:00:09,326 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-23 15:00:09,326 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 374057 states and 472192 transitions. [2018-11-23 15:00:10,196 INFO L131 ngComponentsAnalysis]: Automaton has 64 accepting balls. 250758 [2018-11-23 15:00:10,767 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 374057 states to 374057 states and 472192 transitions. [2018-11-23 15:00:10,767 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 255162 [2018-11-23 15:00:10,863 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 255162 [2018-11-23 15:00:10,863 INFO L73 IsDeterministic]: Start isDeterministic. Operand 374057 states and 472192 transitions. [2018-11-23 15:00:10,921 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2018-11-23 15:00:10,922 INFO L705 BuchiCegarLoop]: Abstraction has 374057 states and 472192 transitions. [2018-11-23 15:00:11,062 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 374057 states and 472192 transitions. [2018-11-23 15:00:17,538 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 374057 to 363365. [2018-11-23 15:00:17,538 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 363365 states. [2018-11-23 15:00:17,968 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 363365 states to 363365 states and 460042 transitions. [2018-11-23 15:00:17,968 INFO L728 BuchiCegarLoop]: Abstraction has 363365 states and 460042 transitions. [2018-11-23 15:00:17,968 INFO L608 BuchiCegarLoop]: Abstraction has 363365 states and 460042 transitions. [2018-11-23 15:00:17,968 INFO L442 BuchiCegarLoop]: ======== Iteration 35============ [2018-11-23 15:00:17,968 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 363365 states and 460042 transitions. [2018-11-23 15:00:18,612 INFO L131 ngComponentsAnalysis]: Automaton has 64 accepting balls. 243630 [2018-11-23 15:00:18,612 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-23 15:00:18,612 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-23 15:00:18,613 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 15:00:18,613 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 15:00:18,613 INFO L794 eck$LassoCheckResult]: Stem: 2300496#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0; 2300222#L-1 havoc main_#res;havoc main_~__retres1~8;havoc main_~__retres1~8;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 2299256#L1006 havoc start_simulation_#t~ret17, start_simulation_#t~ret18, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 2299257#L458 assume 1 == ~m_i~0;~m_st~0 := 0; 2300046#L465-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 2300047#L470-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 2299812#L475-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 2299813#L480-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 2299907#L485-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 2299436#L490-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 2299437#L495-1 assume !(0 == ~M_E~0); 2300076#L674-1 assume !(0 == ~T1_E~0); 2300077#L679-1 assume !(0 == ~T2_E~0); 2299845#L684-1 assume !(0 == ~T3_E~0); 2299846#L689-1 assume !(0 == ~T4_E~0); 2300434#L694-1 assume !(0 == ~T5_E~0); 2299516#L699-1 assume !(0 == ~T6_E~0); 2299517#L704-1 assume !(0 == ~E_M~0); 2299178#L709-1 assume !(0 == ~E_1~0); 2299179#L714-1 assume !(0 == ~E_2~0); 2299357#L719-1 assume !(0 == ~E_3~0); 2299358#L724-1 assume !(0 == ~E_4~0); 2300059#L729-1 assume !(0 == ~E_5~0); 2300060#L734-1 assume !(0 == ~E_6~0); 2299831#L739-1 havoc activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 2299591#L324 assume !(1 == ~m_pc~0); 2299592#L324-2 is_master_triggered_~__retres1~0 := 0; 2299616#L335 is_master_triggered_#res := is_master_triggered_~__retres1~0; 2299447#L336 activate_threads_#t~ret9 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 2299448#L839 assume !(0 != activate_threads_~tmp~1); 2300094#L839-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 2299718#L343 assume !(1 == ~t1_pc~0); 2299719#L343-2 is_transmit1_triggered_~__retres1~1 := 0; 2299716#L354 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 2299717#L355 activate_threads_#t~ret10 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 2299986#L847 assume !(0 != activate_threads_~tmp___0~0); 2300587#L847-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 2300341#L362 assume !(1 == ~t2_pc~0); 2300233#L362-2 is_transmit2_triggered_~__retres1~2 := 0; 2300234#L373 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 2300340#L374 activate_threads_#t~ret11 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 2300542#L855 assume !(0 != activate_threads_~tmp___1~0); 2300616#L855-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 2300627#L381 assume !(1 == ~t3_pc~0); 2300696#L381-2 is_transmit3_triggered_~__retres1~3 := 0; 2300694#L392 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 2300695#L393 activate_threads_#t~ret12 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 2299287#L863 assume !(0 != activate_threads_~tmp___2~0); 2299228#L863-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 2299229#L400 assume !(1 == ~t4_pc~0); 2299314#L400-2 is_transmit4_triggered_~__retres1~4 := 0; 2299315#L411 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 2299348#L412 activate_threads_#t~ret13 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 2299660#L871 assume !(0 != activate_threads_~tmp___3~0); 2299859#L871-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 2299866#L419 assume !(1 == ~t5_pc~0); 2299689#L419-2 is_transmit5_triggered_~__retres1~5 := 0; 2299690#L430 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 2299814#L431 activate_threads_#t~ret14 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 2299815#L879 assume !(0 != activate_threads_~tmp___4~0); 2300378#L879-2 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 2300379#L438 assume !(1 == ~t6_pc~0); 2300415#L438-2 is_transmit6_triggered_~__retres1~6 := 0; 2300416#L449 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 2300320#L450 activate_threads_#t~ret15 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 2300321#L887 assume !(0 != activate_threads_~tmp___5~0); 2300753#L887-2 assume !(1 == ~M_E~0); 2299377#L752-1 assume !(1 == ~T1_E~0); 2299378#L757-1 assume !(1 == ~T2_E~0); 2300052#L762-1 assume !(1 == ~T3_E~0); 2300053#L767-1 assume !(1 == ~T4_E~0); 2299826#L772-1 assume !(1 == ~T5_E~0); 2299827#L777-1 assume !(1 == ~T6_E~0); 2300431#L782-1 assume !(1 == ~E_M~0); 2299507#L787-1 assume !(1 == ~E_1~0); 2299508#L792-1 assume !(1 == ~E_2~0); 2299237#L797-1 assume !(1 == ~E_3~0); 2299238#L802-1 assume !(1 == ~E_4~0); 2299375#L807-1 assume !(1 == ~E_5~0); 2299376#L812-1 assume !(1 == ~E_6~0); 2300770#L1043-1 assume !false; 2322097#L1044 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret1, eval_#t~nondet2, eval_~tmp_ndt_1~0, eval_#t~nondet3, eval_~tmp_ndt_2~0, eval_#t~nondet4, eval_~tmp_ndt_3~0, eval_#t~nondet5, eval_~tmp_ndt_4~0, eval_#t~nondet6, eval_~tmp_ndt_5~0, eval_#t~nondet7, eval_~tmp_ndt_6~0, eval_#t~nondet8, eval_~tmp_ndt_7~0, eval_~tmp~0;havoc eval_~tmp~0; 2445453#L649 [2018-11-23 15:00:18,613 INFO L796 eck$LassoCheckResult]: Loop: 2445453#L649 assume !false; 2445446#L556 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~7;havoc exists_runnable_thread_~__retres1~7; 2445440#L508 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7 := 1; 2445434#L545 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~7; 2445428#L546 eval_#t~ret1 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret1;havoc eval_#t~ret1; 2445422#L560 assume 0 != eval_~tmp~0; 2445415#L560-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0;eval_~tmp_ndt_1~0 := eval_#t~nondet2;havoc eval_#t~nondet2; 2445409#L568 assume !(0 != eval_~tmp_ndt_1~0); 2445405#L565 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0;eval_~tmp_ndt_2~0 := eval_#t~nondet3;havoc eval_#t~nondet3; 2445400#L582 assume !(0 != eval_~tmp_ndt_2~0); 2445401#L579 assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0;eval_~tmp_ndt_3~0 := eval_#t~nondet4;havoc eval_#t~nondet4; 2504286#L596 assume !(0 != eval_~tmp_ndt_3~0); 2446053#L593 assume 0 == ~t3_st~0;havoc eval_~tmp_ndt_4~0;eval_~tmp_ndt_4~0 := eval_#t~nondet5;havoc eval_#t~nondet5; 2446050#L610 assume !(0 != eval_~tmp_ndt_4~0); 2446048#L607 assume 0 == ~t4_st~0;havoc eval_~tmp_ndt_5~0;eval_~tmp_ndt_5~0 := eval_#t~nondet6;havoc eval_#t~nondet6; 2446044#L624 assume !(0 != eval_~tmp_ndt_5~0); 2445474#L621 assume 0 == ~t5_st~0;havoc eval_~tmp_ndt_6~0;eval_~tmp_ndt_6~0 := eval_#t~nondet7;havoc eval_#t~nondet7; 2445465#L638 assume !(0 != eval_~tmp_ndt_6~0); 2445460#L635 assume !(0 == ~t6_st~0); 2445453#L649 [2018-11-23 15:00:18,613 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 15:00:18,613 INFO L82 PathProgramCache]: Analyzing trace with hash -617015546, now seen corresponding path program 6 times [2018-11-23 15:00:18,614 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 15:00:18,614 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 15:00:18,614 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 15:00:18,614 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 15:00:18,614 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 15:00:18,618 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-23 15:00:18,621 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-23 15:00:18,632 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 15:00:18,632 INFO L82 PathProgramCache]: Analyzing trace with hash 916412746, now seen corresponding path program 1 times [2018-11-23 15:00:18,632 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 15:00:18,632 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 15:00:18,633 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 15:00:18,633 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-23 15:00:18,633 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 15:00:18,634 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-23 15:00:18,636 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-23 15:00:18,637 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 15:00:18,637 INFO L82 PathProgramCache]: Analyzing trace with hash 1194463781, now seen corresponding path program 1 times [2018-11-23 15:00:18,638 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 15:00:18,638 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 15:00:18,638 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 15:00:18,638 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 15:00:18,638 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 15:00:18,643 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 15:00:18,694 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 15:00:18,694 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 15:00:18,694 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2018-11-23 15:00:18,817 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-23 15:00:18,817 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-23 15:00:18,817 INFO L87 Difference]: Start difference. First operand 363365 states and 460042 transitions. cyclomatic complexity: 96773 Second operand 3 states. [2018-11-23 15:00:19,807 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 15:00:19,807 INFO L93 Difference]: Finished difference Result 492475 states and 621565 transitions. [2018-11-23 15:00:19,807 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-23 15:00:19,807 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 492475 states and 621565 transitions. [2018-11-23 15:00:21,943 INFO L131 ngComponentsAnalysis]: Automaton has 64 accepting balls. 331176 [2018-11-23 15:00:22,684 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 492475 states to 492475 states and 621565 transitions. [2018-11-23 15:00:22,684 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 337092 [2018-11-23 15:00:22,810 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 337092 [2018-11-23 15:00:22,810 INFO L73 IsDeterministic]: Start isDeterministic. Operand 492475 states and 621565 transitions. [2018-11-23 15:00:22,812 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2018-11-23 15:00:22,812 INFO L705 BuchiCegarLoop]: Abstraction has 492475 states and 621565 transitions. [2018-11-23 15:00:23,007 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 492475 states and 621565 transitions. [2018-11-23 15:00:32,052 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 492475 to 492475. [2018-11-23 15:00:32,052 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 492475 states. [2018-11-23 15:00:32,694 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 492475 states to 492475 states and 621565 transitions. [2018-11-23 15:00:32,694 INFO L728 BuchiCegarLoop]: Abstraction has 492475 states and 621565 transitions. [2018-11-23 15:00:32,694 INFO L608 BuchiCegarLoop]: Abstraction has 492475 states and 621565 transitions. [2018-11-23 15:00:32,694 INFO L442 BuchiCegarLoop]: ======== Iteration 36============ [2018-11-23 15:00:32,694 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 492475 states and 621565 transitions. [2018-11-23 15:00:33,617 INFO L131 ngComponentsAnalysis]: Automaton has 64 accepting balls. 331176 [2018-11-23 15:00:33,618 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-23 15:00:33,618 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-23 15:00:33,618 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 15:00:33,618 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 15:00:33,618 INFO L794 eck$LassoCheckResult]: Stem: 3156282#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0; 3156019#L-1 havoc main_#res;havoc main_~__retres1~8;havoc main_~__retres1~8;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 3155103#L1006 havoc start_simulation_#t~ret17, start_simulation_#t~ret18, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 3155104#L458 assume 1 == ~m_i~0;~m_st~0 := 0; 3155866#L465-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 3155867#L470-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 3155640#L475-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 3155641#L480-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 3155732#L485-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 3155276#L490-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 3155277#L495-1 assume !(0 == ~M_E~0); 3155897#L674-1 assume !(0 == ~T1_E~0); 3155898#L679-1 assume !(0 == ~T2_E~0); 3155669#L684-1 assume !(0 == ~T3_E~0); 3155670#L689-1 assume !(0 == ~T4_E~0); 3156224#L694-1 assume !(0 == ~T5_E~0); 3155355#L699-1 assume !(0 == ~T6_E~0); 3155356#L704-1 assume !(0 == ~E_M~0); 3155026#L709-1 assume !(0 == ~E_1~0); 3155027#L714-1 assume !(0 == ~E_2~0); 3155197#L719-1 assume !(0 == ~E_3~0); 3155198#L724-1 assume !(0 == ~E_4~0); 3155879#L729-1 assume !(0 == ~E_5~0); 3155880#L734-1 assume !(0 == ~E_6~0); 3155656#L739-1 havoc activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 3155436#L324 assume !(1 == ~m_pc~0); 3155437#L324-2 is_master_triggered_~__retres1~0 := 0; 3155457#L335 is_master_triggered_#res := is_master_triggered_~__retres1~0; 3155287#L336 activate_threads_#t~ret9 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 3155288#L839 assume !(0 != activate_threads_~tmp~1); 3155914#L839-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 3155552#L343 assume !(1 == ~t1_pc~0); 3155553#L343-2 is_transmit1_triggered_~__retres1~1 := 0; 3155544#L354 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 3155545#L355 activate_threads_#t~ret10 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 3155809#L847 assume !(0 != activate_threads_~tmp___0~0); 3156358#L847-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 3156138#L362 assume !(1 == ~t2_pc~0); 3156038#L362-2 is_transmit2_triggered_~__retres1~2 := 0; 3156039#L373 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 3156133#L374 activate_threads_#t~ret11 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 3156325#L855 assume !(0 != activate_threads_~tmp___1~0); 3156381#L855-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 3156390#L381 assume !(1 == ~t3_pc~0); 3156455#L381-2 is_transmit3_triggered_~__retres1~3 := 0; 3156451#L392 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 3156452#L393 activate_threads_#t~ret12 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 3155124#L863 assume !(0 != activate_threads_~tmp___2~0); 3155076#L863-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 3155077#L400 assume !(1 == ~t4_pc~0); 3155155#L400-2 is_transmit4_triggered_~__retres1~4 := 0; 3155156#L411 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 3155189#L412 activate_threads_#t~ret13 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 3155496#L871 assume !(0 != activate_threads_~tmp___3~0); 3155690#L871-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 3155697#L419 assume !(1 == ~t5_pc~0); 3155522#L419-2 is_transmit5_triggered_~__retres1~5 := 0; 3155523#L430 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 3155642#L431 activate_threads_#t~ret14 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 3155643#L879 assume !(0 != activate_threads_~tmp___4~0); 3156172#L879-2 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 3156173#L438 assume !(1 == ~t6_pc~0); 3156203#L438-2 is_transmit6_triggered_~__retres1~6 := 0; 3156204#L449 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 3156117#L450 activate_threads_#t~ret15 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 3156118#L887 assume !(0 != activate_threads_~tmp___5~0); 3156513#L887-2 assume !(1 == ~M_E~0); 3155217#L752-1 assume !(1 == ~T1_E~0); 3155218#L757-1 assume !(1 == ~T2_E~0); 3155872#L762-1 assume !(1 == ~T3_E~0); 3155873#L767-1 assume !(1 == ~T4_E~0); 3155654#L772-1 assume !(1 == ~T5_E~0); 3155655#L777-1 assume !(1 == ~T6_E~0); 3156221#L782-1 assume !(1 == ~E_M~0); 3155342#L787-1 assume !(1 == ~E_1~0); 3155343#L792-1 assume !(1 == ~E_2~0); 3155078#L797-1 assume !(1 == ~E_3~0); 3155079#L802-1 assume !(1 == ~E_4~0); 3155215#L807-1 assume !(1 == ~E_5~0); 3155216#L812-1 assume !(1 == ~E_6~0); 3156533#L1043-1 assume !false; 3284353#L1044 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret1, eval_#t~nondet2, eval_~tmp_ndt_1~0, eval_#t~nondet3, eval_~tmp_ndt_2~0, eval_#t~nondet4, eval_~tmp_ndt_3~0, eval_#t~nondet5, eval_~tmp_ndt_4~0, eval_#t~nondet6, eval_~tmp_ndt_5~0, eval_#t~nondet7, eval_~tmp_ndt_6~0, eval_#t~nondet8, eval_~tmp_ndt_7~0, eval_~tmp~0;havoc eval_~tmp~0; 3284351#L649 [2018-11-23 15:00:33,619 INFO L796 eck$LassoCheckResult]: Loop: 3284351#L649 assume !false; 3284349#L556 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~7;havoc exists_runnable_thread_~__retres1~7; 3284348#L508 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7 := 1; 3284346#L545 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~7; 3284344#L546 eval_#t~ret1 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret1;havoc eval_#t~ret1; 3284342#L560 assume 0 != eval_~tmp~0; 3284340#L560-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0;eval_~tmp_ndt_1~0 := eval_#t~nondet2;havoc eval_#t~nondet2; 3284337#L568 assume !(0 != eval_~tmp_ndt_1~0); 3284334#L565 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0;eval_~tmp_ndt_2~0 := eval_#t~nondet3;havoc eval_#t~nondet3; 3284332#L582 assume !(0 != eval_~tmp_ndt_2~0); 3284329#L579 assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0;eval_~tmp_ndt_3~0 := eval_#t~nondet4;havoc eval_#t~nondet4; 3284326#L596 assume !(0 != eval_~tmp_ndt_3~0); 3230773#L593 assume 0 == ~t3_st~0;havoc eval_~tmp_ndt_4~0;eval_~tmp_ndt_4~0 := eval_#t~nondet5;havoc eval_#t~nondet5; 3230770#L610 assume !(0 != eval_~tmp_ndt_4~0); 3230771#L607 assume 0 == ~t4_st~0;havoc eval_~tmp_ndt_5~0;eval_~tmp_ndt_5~0 := eval_#t~nondet6;havoc eval_#t~nondet6; 3282375#L624 assume !(0 != eval_~tmp_ndt_5~0); 3282373#L621 assume 0 == ~t5_st~0;havoc eval_~tmp_ndt_6~0;eval_~tmp_ndt_6~0 := eval_#t~nondet7;havoc eval_#t~nondet7; 3282060#L638 assume !(0 != eval_~tmp_ndt_6~0); 3282372#L635 assume 0 == ~t6_st~0;havoc eval_~tmp_ndt_7~0;eval_~tmp_ndt_7~0 := eval_#t~nondet8;havoc eval_#t~nondet8; 3284354#L652 assume !(0 != eval_~tmp_ndt_7~0); 3284351#L649 [2018-11-23 15:00:33,619 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 15:00:33,619 INFO L82 PathProgramCache]: Analyzing trace with hash -617015546, now seen corresponding path program 7 times [2018-11-23 15:00:33,619 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 15:00:33,619 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 15:00:33,619 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 15:00:33,620 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 15:00:33,620 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 15:00:33,623 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-23 15:00:33,627 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-23 15:00:33,638 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 15:00:33,638 INFO L82 PathProgramCache]: Analyzing trace with hash -1655980219, now seen corresponding path program 1 times [2018-11-23 15:00:33,638 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 15:00:33,638 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 15:00:33,639 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 15:00:33,639 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 15:00:33,639 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 15:00:33,640 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-23 15:00:33,642 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-23 15:00:33,644 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 15:00:33,644 INFO L82 PathProgramCache]: Analyzing trace with hash -1626332726, now seen corresponding path program 1 times [2018-11-23 15:00:33,644 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 15:00:33,644 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 15:00:33,645 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 15:00:33,645 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 15:00:33,645 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 15:00:33,649 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-23 15:00:33,654 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-23 15:00:34,176 WARN L180 SmtUtils]: Spent 385.00 ms on a formula simplification. DAG size of input: 229 DAG size of output: 152 ----- class de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder.RCFGBacktranslator [?] ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0; [?] havoc main_#res;havoc main_~__retres1~8;havoc main_~__retres1~8;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; [?] havoc start_simulation_#t~ret17, start_simulation_#t~ret18, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; [?] assume 1 == ~m_i~0;~m_st~0 := 0; [?] assume 1 == ~t1_i~0;~t1_st~0 := 0; [?] assume 1 == ~t2_i~0;~t2_st~0 := 0; [?] assume 1 == ~t3_i~0;~t3_st~0 := 0; [?] assume 1 == ~t4_i~0;~t4_st~0 := 0; [?] assume 1 == ~t5_i~0;~t5_st~0 := 0; [?] assume 1 == ~t6_i~0;~t6_st~0 := 0; [?] assume !(0 == ~M_E~0); [?] assume !(0 == ~T1_E~0); [?] assume !(0 == ~T2_E~0); [?] assume !(0 == ~T3_E~0); [?] assume !(0 == ~T4_E~0); [?] assume !(0 == ~T5_E~0); [?] assume !(0 == ~T6_E~0); [?] assume !(0 == ~E_M~0); [?] assume !(0 == ~E_1~0); [?] assume !(0 == ~E_2~0); [?] assume !(0 == ~E_3~0); [?] assume !(0 == ~E_4~0); [?] assume !(0 == ~E_5~0); [?] assume !(0 == ~E_6~0); [?] havoc activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; [?] assume !(1 == ~m_pc~0); [?] is_master_triggered_~__retres1~0 := 0; [?] is_master_triggered_#res := is_master_triggered_~__retres1~0; [?] activate_threads_#t~ret9 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; [?] assume !(0 != activate_threads_~tmp~1); [?] havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; [?] assume !(1 == ~t1_pc~0); [?] is_transmit1_triggered_~__retres1~1 := 0; [?] is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; [?] activate_threads_#t~ret10 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; [?] assume !(0 != activate_threads_~tmp___0~0); [?] havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; [?] assume !(1 == ~t2_pc~0); [?] is_transmit2_triggered_~__retres1~2 := 0; [?] is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; [?] activate_threads_#t~ret11 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; [?] assume !(0 != activate_threads_~tmp___1~0); [?] havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; [?] assume !(1 == ~t3_pc~0); [?] is_transmit3_triggered_~__retres1~3 := 0; [?] is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; [?] activate_threads_#t~ret12 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; [?] assume !(0 != activate_threads_~tmp___2~0); [?] havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; [?] assume !(1 == ~t4_pc~0); [?] is_transmit4_triggered_~__retres1~4 := 0; [?] is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; [?] activate_threads_#t~ret13 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; [?] assume !(0 != activate_threads_~tmp___3~0); [?] havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; [?] assume !(1 == ~t5_pc~0); [?] is_transmit5_triggered_~__retres1~5 := 0; [?] is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; [?] activate_threads_#t~ret14 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; [?] assume !(0 != activate_threads_~tmp___4~0); [?] havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; [?] assume !(1 == ~t6_pc~0); [?] is_transmit6_triggered_~__retres1~6 := 0; [?] is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; [?] activate_threads_#t~ret15 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; [?] assume !(0 != activate_threads_~tmp___5~0); [?] assume !(1 == ~M_E~0); [?] assume !(1 == ~T1_E~0); [?] assume !(1 == ~T2_E~0); [?] assume !(1 == ~T3_E~0); [?] assume !(1 == ~T4_E~0); [?] assume !(1 == ~T5_E~0); [?] assume !(1 == ~T6_E~0); [?] assume !(1 == ~E_M~0); [?] assume !(1 == ~E_1~0); [?] assume !(1 == ~E_2~0); [?] assume !(1 == ~E_3~0); [?] assume !(1 == ~E_4~0); [?] assume !(1 == ~E_5~0); [?] assume !(1 == ~E_6~0); [?] assume !false; [?] start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret1, eval_#t~nondet2, eval_~tmp_ndt_1~0, eval_#t~nondet3, eval_~tmp_ndt_2~0, eval_#t~nondet4, eval_~tmp_ndt_3~0, eval_#t~nondet5, eval_~tmp_ndt_4~0, eval_#t~nondet6, eval_~tmp_ndt_5~0, eval_#t~nondet7, eval_~tmp_ndt_6~0, eval_#t~nondet8, eval_~tmp_ndt_7~0, eval_~tmp~0;havoc eval_~tmp~0; [L14] ~m_pc~0 := 0; [L15] ~t1_pc~0 := 0; [L16] ~t2_pc~0 := 0; [L17] ~t3_pc~0 := 0; [L18] ~t4_pc~0 := 0; [L19] ~t5_pc~0 := 0; [L20] ~t6_pc~0 := 0; [L21] ~m_st~0 := 0; [L22] ~t1_st~0 := 0; [L23] ~t2_st~0 := 0; [L24] ~t3_st~0 := 0; [L25] ~t4_st~0 := 0; [L26] ~t5_st~0 := 0; [L27] ~t6_st~0 := 0; [L28] ~m_i~0 := 0; [L29] ~t1_i~0 := 0; [L30] ~t2_i~0 := 0; [L31] ~t3_i~0 := 0; [L32] ~t4_i~0 := 0; [L33] ~t5_i~0 := 0; [L34] ~t6_i~0 := 0; [L35] ~M_E~0 := 2; [L36] ~T1_E~0 := 2; [L37] ~T2_E~0 := 2; [L38] ~T3_E~0 := 2; [L39] ~T4_E~0 := 2; [L40] ~T5_E~0 := 2; [L41] ~T6_E~0 := 2; [L42] ~E_M~0 := 2; [L43] ~E_1~0 := 2; [L44] ~E_2~0 := 2; [L45] ~E_3~0 := 2; [L46] ~E_4~0 := 2; [L47] ~E_5~0 := 2; [L48] ~E_6~0 := 2; [L57] ~token~0 := 0; [L59] ~local~0 := 0; [?] havoc main_#res; [?] havoc main_~__retres1~8; [L1088] havoc main_~__retres1~8; [L998] ~m_i~0 := 1; [L999] ~t1_i~0 := 1; [L1000] ~t2_i~0 := 1; [L1001] ~t3_i~0 := 1; [L1002] ~t4_i~0 := 1; [L1003] ~t5_i~0 := 1; [L1004] ~t6_i~0 := 1; [L1093] havoc start_simulation_#t~ret17, start_simulation_#t~ret18, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1; [L1029] havoc start_simulation_~kernel_st~0; [L1030] havoc start_simulation_~tmp~3; [L1031] havoc start_simulation_~tmp___0~1; [L1035] start_simulation_~kernel_st~0 := 0; [L465-L469] assume 1 == ~m_i~0; [L466] ~m_st~0 := 0; [L470-L474] assume 1 == ~t1_i~0; [L471] ~t1_st~0 := 0; [L475-L479] assume 1 == ~t2_i~0; [L476] ~t2_st~0 := 0; [L480-L484] assume 1 == ~t3_i~0; [L481] ~t3_st~0 := 0; [L485-L489] assume 1 == ~t4_i~0; [L486] ~t4_st~0 := 0; [L490-L494] assume 1 == ~t5_i~0; [L491] ~t5_st~0 := 0; [L495-L499] assume 1 == ~t6_i~0; [L496] ~t6_st~0 := 0; [L674-L678] assume !(0 == ~M_E~0); [L679-L683] assume !(0 == ~T1_E~0); [L684-L688] assume !(0 == ~T2_E~0); [L689-L693] assume !(0 == ~T3_E~0); [L694-L698] assume !(0 == ~T4_E~0); [L699-L703] assume !(0 == ~T5_E~0); [L704-L708] assume !(0 == ~T6_E~0); [L709-L713] assume !(0 == ~E_M~0); [L714-L718] assume !(0 == ~E_1~0); [L719-L723] assume !(0 == ~E_2~0); [L724-L728] assume !(0 == ~E_3~0); [L729-L733] assume !(0 == ~E_4~0); [L734-L738] assume !(0 == ~E_5~0); [L739-L743] assume !(0 == ~E_6~0); [L1039] havoc activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0; [L827] havoc activate_threads_~tmp~1; [L828] havoc activate_threads_~tmp___0~0; [L829] havoc activate_threads_~tmp___1~0; [L830] havoc activate_threads_~tmp___2~0; [L831] havoc activate_threads_~tmp___3~0; [L832] havoc activate_threads_~tmp___4~0; [L833] havoc activate_threads_~tmp___5~0; [L837] havoc is_master_triggered_#res; [L837] havoc is_master_triggered_~__retres1~0; [L321] havoc is_master_triggered_~__retres1~0; [L324-L333] assume !(1 == ~m_pc~0); [L334] is_master_triggered_~__retres1~0 := 0; [L336] is_master_triggered_#res := is_master_triggered_~__retres1~0; [L837] activate_threads_#t~ret9 := is_master_triggered_#res; [L837] activate_threads_~tmp~1 := activate_threads_#t~ret9; [L837] havoc activate_threads_#t~ret9; [L839-L843] assume !(0 != activate_threads_~tmp~1); [L845] havoc is_transmit1_triggered_#res; [L845] havoc is_transmit1_triggered_~__retres1~1; [L340] havoc is_transmit1_triggered_~__retres1~1; [L343-L352] assume !(1 == ~t1_pc~0); [L353] is_transmit1_triggered_~__retres1~1 := 0; [L355] is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; [L845] activate_threads_#t~ret10 := is_transmit1_triggered_#res; [L845] activate_threads_~tmp___0~0 := activate_threads_#t~ret10; [L845] havoc activate_threads_#t~ret10; [L847-L851] assume !(0 != activate_threads_~tmp___0~0); [L853] havoc is_transmit2_triggered_#res; [L853] havoc is_transmit2_triggered_~__retres1~2; [L359] havoc is_transmit2_triggered_~__retres1~2; [L362-L371] assume !(1 == ~t2_pc~0); [L372] is_transmit2_triggered_~__retres1~2 := 0; [L374] is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; [L853] activate_threads_#t~ret11 := is_transmit2_triggered_#res; [L853] activate_threads_~tmp___1~0 := activate_threads_#t~ret11; [L853] havoc activate_threads_#t~ret11; [L855-L859] assume !(0 != activate_threads_~tmp___1~0); [L861] havoc is_transmit3_triggered_#res; [L861] havoc is_transmit3_triggered_~__retres1~3; [L378] havoc is_transmit3_triggered_~__retres1~3; [L381-L390] assume !(1 == ~t3_pc~0); [L391] is_transmit3_triggered_~__retres1~3 := 0; [L393] is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; [L861] activate_threads_#t~ret12 := is_transmit3_triggered_#res; [L861] activate_threads_~tmp___2~0 := activate_threads_#t~ret12; [L861] havoc activate_threads_#t~ret12; [L863-L867] assume !(0 != activate_threads_~tmp___2~0); [L869] havoc is_transmit4_triggered_#res; [L869] havoc is_transmit4_triggered_~__retres1~4; [L397] havoc is_transmit4_triggered_~__retres1~4; [L400-L409] assume !(1 == ~t4_pc~0); [L410] is_transmit4_triggered_~__retres1~4 := 0; [L412] is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; [L869] activate_threads_#t~ret13 := is_transmit4_triggered_#res; [L869] activate_threads_~tmp___3~0 := activate_threads_#t~ret13; [L869] havoc activate_threads_#t~ret13; [L871-L875] assume !(0 != activate_threads_~tmp___3~0); [L877] havoc is_transmit5_triggered_#res; [L877] havoc is_transmit5_triggered_~__retres1~5; [L416] havoc is_transmit5_triggered_~__retres1~5; [L419-L428] assume !(1 == ~t5_pc~0); [L429] is_transmit5_triggered_~__retres1~5 := 0; [L431] is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; [L877] activate_threads_#t~ret14 := is_transmit5_triggered_#res; [L877] activate_threads_~tmp___4~0 := activate_threads_#t~ret14; [L877] havoc activate_threads_#t~ret14; [L879-L883] assume !(0 != activate_threads_~tmp___4~0); [L885] havoc is_transmit6_triggered_#res; [L885] havoc is_transmit6_triggered_~__retres1~6; [L435] havoc is_transmit6_triggered_~__retres1~6; [L438-L447] assume !(1 == ~t6_pc~0); [L448] is_transmit6_triggered_~__retres1~6 := 0; [L450] is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; [L885] activate_threads_#t~ret15 := is_transmit6_triggered_#res; [L885] activate_threads_~tmp___5~0 := activate_threads_#t~ret15; [L885] havoc activate_threads_#t~ret15; [L887-L891] assume !(0 != activate_threads_~tmp___5~0); [L752-L756] assume !(1 == ~M_E~0); [L757-L761] assume !(1 == ~T1_E~0); [L762-L766] assume !(1 == ~T2_E~0); [L767-L771] assume !(1 == ~T3_E~0); [L772-L776] assume !(1 == ~T4_E~0); [L777-L781] assume !(1 == ~T5_E~0); [L782-L786] assume !(1 == ~T6_E~0); [L787-L791] assume !(1 == ~E_M~0); [L792-L796] assume !(1 == ~E_1~0); [L797-L801] assume !(1 == ~E_2~0); [L802-L806] assume !(1 == ~E_3~0); [L807-L811] assume !(1 == ~E_4~0); [L812-L816] assume !(1 == ~E_5~0); [L817-L821] assume !(1 == ~E_6~0); [L1043-L1080] assume !false; [L1046] start_simulation_~kernel_st~0 := 1; [L1047] havoc eval_#t~ret1, eval_#t~nondet2, eval_~tmp_ndt_1~0, eval_#t~nondet3, eval_~tmp_ndt_2~0, eval_#t~nondet4, eval_~tmp_ndt_3~0, eval_#t~nondet5, eval_~tmp_ndt_4~0, eval_#t~nondet6, eval_~tmp_ndt_5~0, eval_#t~nondet7, eval_~tmp_ndt_6~0, eval_#t~nondet8, eval_~tmp_ndt_7~0, eval_~tmp~0; [L551] havoc eval_~tmp~0; ----- ----- class de.uni_freiburg.informatik.ultimate.boogie.preprocessor.BoogiePreprocessorBacktranslator [L14] ~m_pc~0 := 0; [L15] ~t1_pc~0 := 0; [L16] ~t2_pc~0 := 0; [L17] ~t3_pc~0 := 0; [L18] ~t4_pc~0 := 0; [L19] ~t5_pc~0 := 0; [L20] ~t6_pc~0 := 0; [L21] ~m_st~0 := 0; [L22] ~t1_st~0 := 0; [L23] ~t2_st~0 := 0; [L24] ~t3_st~0 := 0; [L25] ~t4_st~0 := 0; [L26] ~t5_st~0 := 0; [L27] ~t6_st~0 := 0; [L28] ~m_i~0 := 0; [L29] ~t1_i~0 := 0; [L30] ~t2_i~0 := 0; [L31] ~t3_i~0 := 0; [L32] ~t4_i~0 := 0; [L33] ~t5_i~0 := 0; [L34] ~t6_i~0 := 0; [L35] ~M_E~0 := 2; [L36] ~T1_E~0 := 2; [L37] ~T2_E~0 := 2; [L38] ~T3_E~0 := 2; [L39] ~T4_E~0 := 2; [L40] ~T5_E~0 := 2; [L41] ~T6_E~0 := 2; [L42] ~E_M~0 := 2; [L43] ~E_1~0 := 2; [L44] ~E_2~0 := 2; [L45] ~E_3~0 := 2; [L46] ~E_4~0 := 2; [L47] ~E_5~0 := 2; [L48] ~E_6~0 := 2; [L57] ~token~0 := 0; [L59] ~local~0 := 0; [?] havoc main_#res; [?] havoc main_~__retres1~8; [L1088] havoc main_~__retres1~8; [L998] ~m_i~0 := 1; [L999] ~t1_i~0 := 1; [L1000] ~t2_i~0 := 1; [L1001] ~t3_i~0 := 1; [L1002] ~t4_i~0 := 1; [L1003] ~t5_i~0 := 1; [L1004] ~t6_i~0 := 1; [L1093] havoc start_simulation_#t~ret17, start_simulation_#t~ret18, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1; [L1029] havoc start_simulation_~kernel_st~0; [L1030] havoc start_simulation_~tmp~3; [L1031] havoc start_simulation_~tmp___0~1; [L1035] start_simulation_~kernel_st~0 := 0; [L465-L469] assume 1 == ~m_i~0; [L466] ~m_st~0 := 0; [L470-L474] assume 1 == ~t1_i~0; [L471] ~t1_st~0 := 0; [L475-L479] assume 1 == ~t2_i~0; [L476] ~t2_st~0 := 0; [L480-L484] assume 1 == ~t3_i~0; [L481] ~t3_st~0 := 0; [L485-L489] assume 1 == ~t4_i~0; [L486] ~t4_st~0 := 0; [L490-L494] assume 1 == ~t5_i~0; [L491] ~t5_st~0 := 0; [L495-L499] assume 1 == ~t6_i~0; [L496] ~t6_st~0 := 0; [L674-L678] assume !(0 == ~M_E~0); [L679-L683] assume !(0 == ~T1_E~0); [L684-L688] assume !(0 == ~T2_E~0); [L689-L693] assume !(0 == ~T3_E~0); [L694-L698] assume !(0 == ~T4_E~0); [L699-L703] assume !(0 == ~T5_E~0); [L704-L708] assume !(0 == ~T6_E~0); [L709-L713] assume !(0 == ~E_M~0); [L714-L718] assume !(0 == ~E_1~0); [L719-L723] assume !(0 == ~E_2~0); [L724-L728] assume !(0 == ~E_3~0); [L729-L733] assume !(0 == ~E_4~0); [L734-L738] assume !(0 == ~E_5~0); [L739-L743] assume !(0 == ~E_6~0); [L1039] havoc activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0; [L827] havoc activate_threads_~tmp~1; [L828] havoc activate_threads_~tmp___0~0; [L829] havoc activate_threads_~tmp___1~0; [L830] havoc activate_threads_~tmp___2~0; [L831] havoc activate_threads_~tmp___3~0; [L832] havoc activate_threads_~tmp___4~0; [L833] havoc activate_threads_~tmp___5~0; [L837] havoc is_master_triggered_#res; [L837] havoc is_master_triggered_~__retres1~0; [L321] havoc is_master_triggered_~__retres1~0; [L324-L333] assume !(1 == ~m_pc~0); [L334] is_master_triggered_~__retres1~0 := 0; [L336] is_master_triggered_#res := is_master_triggered_~__retres1~0; [L837] activate_threads_#t~ret9 := is_master_triggered_#res; [L837] activate_threads_~tmp~1 := activate_threads_#t~ret9; [L837] havoc activate_threads_#t~ret9; [L839-L843] assume !(0 != activate_threads_~tmp~1); [L845] havoc is_transmit1_triggered_#res; [L845] havoc is_transmit1_triggered_~__retres1~1; [L340] havoc is_transmit1_triggered_~__retres1~1; [L343-L352] assume !(1 == ~t1_pc~0); [L353] is_transmit1_triggered_~__retres1~1 := 0; [L355] is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; [L845] activate_threads_#t~ret10 := is_transmit1_triggered_#res; [L845] activate_threads_~tmp___0~0 := activate_threads_#t~ret10; [L845] havoc activate_threads_#t~ret10; [L847-L851] assume !(0 != activate_threads_~tmp___0~0); [L853] havoc is_transmit2_triggered_#res; [L853] havoc is_transmit2_triggered_~__retres1~2; [L359] havoc is_transmit2_triggered_~__retres1~2; [L362-L371] assume !(1 == ~t2_pc~0); [L372] is_transmit2_triggered_~__retres1~2 := 0; [L374] is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; [L853] activate_threads_#t~ret11 := is_transmit2_triggered_#res; [L853] activate_threads_~tmp___1~0 := activate_threads_#t~ret11; [L853] havoc activate_threads_#t~ret11; [L855-L859] assume !(0 != activate_threads_~tmp___1~0); [L861] havoc is_transmit3_triggered_#res; [L861] havoc is_transmit3_triggered_~__retres1~3; [L378] havoc is_transmit3_triggered_~__retres1~3; [L381-L390] assume !(1 == ~t3_pc~0); [L391] is_transmit3_triggered_~__retres1~3 := 0; [L393] is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; [L861] activate_threads_#t~ret12 := is_transmit3_triggered_#res; [L861] activate_threads_~tmp___2~0 := activate_threads_#t~ret12; [L861] havoc activate_threads_#t~ret12; [L863-L867] assume !(0 != activate_threads_~tmp___2~0); [L869] havoc is_transmit4_triggered_#res; [L869] havoc is_transmit4_triggered_~__retres1~4; [L397] havoc is_transmit4_triggered_~__retres1~4; [L400-L409] assume !(1 == ~t4_pc~0); [L410] is_transmit4_triggered_~__retres1~4 := 0; [L412] is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; [L869] activate_threads_#t~ret13 := is_transmit4_triggered_#res; [L869] activate_threads_~tmp___3~0 := activate_threads_#t~ret13; [L869] havoc activate_threads_#t~ret13; [L871-L875] assume !(0 != activate_threads_~tmp___3~0); [L877] havoc is_transmit5_triggered_#res; [L877] havoc is_transmit5_triggered_~__retres1~5; [L416] havoc is_transmit5_triggered_~__retres1~5; [L419-L428] assume !(1 == ~t5_pc~0); [L429] is_transmit5_triggered_~__retres1~5 := 0; [L431] is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; [L877] activate_threads_#t~ret14 := is_transmit5_triggered_#res; [L877] activate_threads_~tmp___4~0 := activate_threads_#t~ret14; [L877] havoc activate_threads_#t~ret14; [L879-L883] assume !(0 != activate_threads_~tmp___4~0); [L885] havoc is_transmit6_triggered_#res; [L885] havoc is_transmit6_triggered_~__retres1~6; [L435] havoc is_transmit6_triggered_~__retres1~6; [L438-L447] assume !(1 == ~t6_pc~0); [L448] is_transmit6_triggered_~__retres1~6 := 0; [L450] is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; [L885] activate_threads_#t~ret15 := is_transmit6_triggered_#res; [L885] activate_threads_~tmp___5~0 := activate_threads_#t~ret15; [L885] havoc activate_threads_#t~ret15; [L887-L891] assume !(0 != activate_threads_~tmp___5~0); [L752-L756] assume !(1 == ~M_E~0); [L757-L761] assume !(1 == ~T1_E~0); [L762-L766] assume !(1 == ~T2_E~0); [L767-L771] assume !(1 == ~T3_E~0); [L772-L776] assume !(1 == ~T4_E~0); [L777-L781] assume !(1 == ~T5_E~0); [L782-L786] assume !(1 == ~T6_E~0); [L787-L791] assume !(1 == ~E_M~0); [L792-L796] assume !(1 == ~E_1~0); [L797-L801] assume !(1 == ~E_2~0); [L802-L806] assume !(1 == ~E_3~0); [L807-L811] assume !(1 == ~E_4~0); [L812-L816] assume !(1 == ~E_5~0); [L817-L821] assume !(1 == ~E_6~0); [L1043-L1080] assume !false; [L1046] start_simulation_~kernel_st~0 := 1; [L1047] havoc eval_#t~ret1, eval_#t~nondet2, eval_~tmp_ndt_1~0, eval_#t~nondet3, eval_~tmp_ndt_2~0, eval_#t~nondet4, eval_~tmp_ndt_3~0, eval_#t~nondet5, eval_~tmp_ndt_4~0, eval_#t~nondet6, eval_~tmp_ndt_5~0, eval_#t~nondet7, eval_~tmp_ndt_6~0, eval_#t~nondet8, eval_~tmp_ndt_7~0, eval_~tmp~0; [L551] havoc eval_~tmp~0; [L14] ~m_pc~0 := 0; [L15] ~t1_pc~0 := 0; [L16] ~t2_pc~0 := 0; [L17] ~t3_pc~0 := 0; [L18] ~t4_pc~0 := 0; [L19] ~t5_pc~0 := 0; [L20] ~t6_pc~0 := 0; [L21] ~m_st~0 := 0; [L22] ~t1_st~0 := 0; [L23] ~t2_st~0 := 0; [L24] ~t3_st~0 := 0; [L25] ~t4_st~0 := 0; [L26] ~t5_st~0 := 0; [L27] ~t6_st~0 := 0; [L28] ~m_i~0 := 0; [L29] ~t1_i~0 := 0; [L30] ~t2_i~0 := 0; [L31] ~t3_i~0 := 0; [L32] ~t4_i~0 := 0; [L33] ~t5_i~0 := 0; [L34] ~t6_i~0 := 0; [L35] ~M_E~0 := 2; [L36] ~T1_E~0 := 2; [L37] ~T2_E~0 := 2; [L38] ~T3_E~0 := 2; [L39] ~T4_E~0 := 2; [L40] ~T5_E~0 := 2; [L41] ~T6_E~0 := 2; [L42] ~E_M~0 := 2; [L43] ~E_1~0 := 2; [L44] ~E_2~0 := 2; [L45] ~E_3~0 := 2; [L46] ~E_4~0 := 2; [L47] ~E_5~0 := 2; [L48] ~E_6~0 := 2; [L57] ~token~0 := 0; [L59] ~local~0 := 0; [?] havoc main_#res; [?] havoc main_~__retres1~8; [L1088] havoc main_~__retres1~8; [L998] ~m_i~0 := 1; [L999] ~t1_i~0 := 1; [L1000] ~t2_i~0 := 1; [L1001] ~t3_i~0 := 1; [L1002] ~t4_i~0 := 1; [L1003] ~t5_i~0 := 1; [L1004] ~t6_i~0 := 1; [L1093] havoc start_simulation_#t~ret17, start_simulation_#t~ret18, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1; [L1029] havoc start_simulation_~kernel_st~0; [L1030] havoc start_simulation_~tmp~3; [L1031] havoc start_simulation_~tmp___0~1; [L1035] start_simulation_~kernel_st~0 := 0; [L465] COND TRUE 1 == ~m_i~0 [L466] ~m_st~0 := 0; [L470] COND TRUE 1 == ~t1_i~0 [L471] ~t1_st~0 := 0; [L475] COND TRUE 1 == ~t2_i~0 [L476] ~t2_st~0 := 0; [L480] COND TRUE 1 == ~t3_i~0 [L481] ~t3_st~0 := 0; [L485] COND TRUE 1 == ~t4_i~0 [L486] ~t4_st~0 := 0; [L490] COND TRUE 1 == ~t5_i~0 [L491] ~t5_st~0 := 0; [L495] COND TRUE 1 == ~t6_i~0 [L496] ~t6_st~0 := 0; [L674] COND FALSE !(0 == ~M_E~0) [L679] COND FALSE !(0 == ~T1_E~0) [L684] COND FALSE !(0 == ~T2_E~0) [L689] COND FALSE !(0 == ~T3_E~0) [L694] COND FALSE !(0 == ~T4_E~0) [L699] COND FALSE !(0 == ~T5_E~0) [L704] COND FALSE !(0 == ~T6_E~0) [L709] COND FALSE !(0 == ~E_M~0) [L714] COND FALSE !(0 == ~E_1~0) [L719] COND FALSE !(0 == ~E_2~0) [L724] COND FALSE !(0 == ~E_3~0) [L729] COND FALSE !(0 == ~E_4~0) [L734] COND FALSE !(0 == ~E_5~0) [L739] COND FALSE !(0 == ~E_6~0) [L1039] havoc activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0; [L827] havoc activate_threads_~tmp~1; [L828] havoc activate_threads_~tmp___0~0; [L829] havoc activate_threads_~tmp___1~0; [L830] havoc activate_threads_~tmp___2~0; [L831] havoc activate_threads_~tmp___3~0; [L832] havoc activate_threads_~tmp___4~0; [L833] havoc activate_threads_~tmp___5~0; [L837] havoc is_master_triggered_#res; [L837] havoc is_master_triggered_~__retres1~0; [L321] havoc is_master_triggered_~__retres1~0; [L324] COND FALSE !(1 == ~m_pc~0) [L334] is_master_triggered_~__retres1~0 := 0; [L336] is_master_triggered_#res := is_master_triggered_~__retres1~0; [L837] activate_threads_#t~ret9 := is_master_triggered_#res; [L837] activate_threads_~tmp~1 := activate_threads_#t~ret9; [L837] havoc activate_threads_#t~ret9; [L839-L843] COND FALSE !(0 != activate_threads_~tmp~1) [L845] havoc is_transmit1_triggered_#res; [L845] havoc is_transmit1_triggered_~__retres1~1; [L340] havoc is_transmit1_triggered_~__retres1~1; [L343] COND FALSE !(1 == ~t1_pc~0) [L353] is_transmit1_triggered_~__retres1~1 := 0; [L355] is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; [L845] activate_threads_#t~ret10 := is_transmit1_triggered_#res; [L845] activate_threads_~tmp___0~0 := activate_threads_#t~ret10; [L845] havoc activate_threads_#t~ret10; [L847-L851] COND FALSE !(0 != activate_threads_~tmp___0~0) [L853] havoc is_transmit2_triggered_#res; [L853] havoc is_transmit2_triggered_~__retres1~2; [L359] havoc is_transmit2_triggered_~__retres1~2; [L362] COND FALSE !(1 == ~t2_pc~0) [L372] is_transmit2_triggered_~__retres1~2 := 0; [L374] is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; [L853] activate_threads_#t~ret11 := is_transmit2_triggered_#res; [L853] activate_threads_~tmp___1~0 := activate_threads_#t~ret11; [L853] havoc activate_threads_#t~ret11; [L855-L859] COND FALSE !(0 != activate_threads_~tmp___1~0) [L861] havoc is_transmit3_triggered_#res; [L861] havoc is_transmit3_triggered_~__retres1~3; [L378] havoc is_transmit3_triggered_~__retres1~3; [L381] COND FALSE !(1 == ~t3_pc~0) [L391] is_transmit3_triggered_~__retres1~3 := 0; [L393] is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; [L861] activate_threads_#t~ret12 := is_transmit3_triggered_#res; [L861] activate_threads_~tmp___2~0 := activate_threads_#t~ret12; [L861] havoc activate_threads_#t~ret12; [L863-L867] COND FALSE !(0 != activate_threads_~tmp___2~0) [L869] havoc is_transmit4_triggered_#res; [L869] havoc is_transmit4_triggered_~__retres1~4; [L397] havoc is_transmit4_triggered_~__retres1~4; [L400] COND FALSE !(1 == ~t4_pc~0) [L410] is_transmit4_triggered_~__retres1~4 := 0; [L412] is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; [L869] activate_threads_#t~ret13 := is_transmit4_triggered_#res; [L869] activate_threads_~tmp___3~0 := activate_threads_#t~ret13; [L869] havoc activate_threads_#t~ret13; [L871-L875] COND FALSE !(0 != activate_threads_~tmp___3~0) [L877] havoc is_transmit5_triggered_#res; [L877] havoc is_transmit5_triggered_~__retres1~5; [L416] havoc is_transmit5_triggered_~__retres1~5; [L419] COND FALSE !(1 == ~t5_pc~0) [L429] is_transmit5_triggered_~__retres1~5 := 0; [L431] is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; [L877] activate_threads_#t~ret14 := is_transmit5_triggered_#res; [L877] activate_threads_~tmp___4~0 := activate_threads_#t~ret14; [L877] havoc activate_threads_#t~ret14; [L879-L883] COND FALSE !(0 != activate_threads_~tmp___4~0) [L885] havoc is_transmit6_triggered_#res; [L885] havoc is_transmit6_triggered_~__retres1~6; [L435] havoc is_transmit6_triggered_~__retres1~6; [L438] COND FALSE !(1 == ~t6_pc~0) [L448] is_transmit6_triggered_~__retres1~6 := 0; [L450] is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; [L885] activate_threads_#t~ret15 := is_transmit6_triggered_#res; [L885] activate_threads_~tmp___5~0 := activate_threads_#t~ret15; [L885] havoc activate_threads_#t~ret15; [L887-L891] COND FALSE !(0 != activate_threads_~tmp___5~0) [L752] COND FALSE !(1 == ~M_E~0) [L757] COND FALSE !(1 == ~T1_E~0) [L762] COND FALSE !(1 == ~T2_E~0) [L767] COND FALSE !(1 == ~T3_E~0) [L772] COND FALSE !(1 == ~T4_E~0) [L777] COND FALSE !(1 == ~T5_E~0) [L782] COND FALSE !(1 == ~T6_E~0) [L787] COND FALSE !(1 == ~E_M~0) [L792] COND FALSE !(1 == ~E_1~0) [L797] COND FALSE !(1 == ~E_2~0) [L802] COND FALSE !(1 == ~E_3~0) [L807] COND FALSE !(1 == ~E_4~0) [L812] COND FALSE !(1 == ~E_5~0) [L817] COND FALSE !(1 == ~E_6~0) [L1043-L1080] COND FALSE !(false) [L1046] start_simulation_~kernel_st~0 := 1; [L1047] havoc eval_#t~ret1, eval_#t~nondet2, eval_~tmp_ndt_1~0, eval_#t~nondet3, eval_~tmp_ndt_2~0, eval_#t~nondet4, eval_~tmp_ndt_3~0, eval_#t~nondet5, eval_~tmp_ndt_4~0, eval_#t~nondet6, eval_~tmp_ndt_5~0, eval_#t~nondet7, eval_~tmp_ndt_6~0, eval_#t~nondet8, eval_~tmp_ndt_7~0, eval_~tmp~0; [L551] havoc eval_~tmp~0; ----- ----- class de.uni_freiburg.informatik.ultimate.boogie.procedureinliner.backtranslation.InlinerBacktranslator [L14] ~m_pc~0 := 0; [L15] ~t1_pc~0 := 0; [L16] ~t2_pc~0 := 0; [L17] ~t3_pc~0 := 0; [L18] ~t4_pc~0 := 0; [L19] ~t5_pc~0 := 0; [L20] ~t6_pc~0 := 0; [L21] ~m_st~0 := 0; [L22] ~t1_st~0 := 0; [L23] ~t2_st~0 := 0; [L24] ~t3_st~0 := 0; [L25] ~t4_st~0 := 0; [L26] ~t5_st~0 := 0; [L27] ~t6_st~0 := 0; [L28] ~m_i~0 := 0; [L29] ~t1_i~0 := 0; [L30] ~t2_i~0 := 0; [L31] ~t3_i~0 := 0; [L32] ~t4_i~0 := 0; [L33] ~t5_i~0 := 0; [L34] ~t6_i~0 := 0; [L35] ~M_E~0 := 2; [L36] ~T1_E~0 := 2; [L37] ~T2_E~0 := 2; [L38] ~T3_E~0 := 2; [L39] ~T4_E~0 := 2; [L40] ~T5_E~0 := 2; [L41] ~T6_E~0 := 2; [L42] ~E_M~0 := 2; [L43] ~E_1~0 := 2; [L44] ~E_2~0 := 2; [L45] ~E_3~0 := 2; [L46] ~E_4~0 := 2; [L47] ~E_5~0 := 2; [L48] ~E_6~0 := 2; [L57] ~token~0 := 0; [L59] ~local~0 := 0; [?] havoc main_#res; [?] havoc main_~__retres1~8; [L1088] havoc main_~__retres1~8; [L998] ~m_i~0 := 1; [L999] ~t1_i~0 := 1; [L1000] ~t2_i~0 := 1; [L1001] ~t3_i~0 := 1; [L1002] ~t4_i~0 := 1; [L1003] ~t5_i~0 := 1; [L1004] ~t6_i~0 := 1; [L1093] havoc start_simulation_#t~ret17, start_simulation_#t~ret18, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1; [L1029] havoc start_simulation_~kernel_st~0; [L1030] havoc start_simulation_~tmp~3; [L1031] havoc start_simulation_~tmp___0~1; [L1035] start_simulation_~kernel_st~0 := 0; [L465] COND TRUE 1 == ~m_i~0 [L466] ~m_st~0 := 0; [L470] COND TRUE 1 == ~t1_i~0 [L471] ~t1_st~0 := 0; [L475] COND TRUE 1 == ~t2_i~0 [L476] ~t2_st~0 := 0; [L480] COND TRUE 1 == ~t3_i~0 [L481] ~t3_st~0 := 0; [L485] COND TRUE 1 == ~t4_i~0 [L486] ~t4_st~0 := 0; [L490] COND TRUE 1 == ~t5_i~0 [L491] ~t5_st~0 := 0; [L495] COND TRUE 1 == ~t6_i~0 [L496] ~t6_st~0 := 0; [L674] COND FALSE !(0 == ~M_E~0) [L679] COND FALSE !(0 == ~T1_E~0) [L684] COND FALSE !(0 == ~T2_E~0) [L689] COND FALSE !(0 == ~T3_E~0) [L694] COND FALSE !(0 == ~T4_E~0) [L699] COND FALSE !(0 == ~T5_E~0) [L704] COND FALSE !(0 == ~T6_E~0) [L709] COND FALSE !(0 == ~E_M~0) [L714] COND FALSE !(0 == ~E_1~0) [L719] COND FALSE !(0 == ~E_2~0) [L724] COND FALSE !(0 == ~E_3~0) [L729] COND FALSE !(0 == ~E_4~0) [L734] COND FALSE !(0 == ~E_5~0) [L739] COND FALSE !(0 == ~E_6~0) [L1039] havoc activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0; [L827] havoc activate_threads_~tmp~1; [L828] havoc activate_threads_~tmp___0~0; [L829] havoc activate_threads_~tmp___1~0; [L830] havoc activate_threads_~tmp___2~0; [L831] havoc activate_threads_~tmp___3~0; [L832] havoc activate_threads_~tmp___4~0; [L833] havoc activate_threads_~tmp___5~0; [L837] havoc is_master_triggered_#res; [L837] havoc is_master_triggered_~__retres1~0; [L321] havoc is_master_triggered_~__retres1~0; [L324] COND FALSE !(1 == ~m_pc~0) [L334] is_master_triggered_~__retres1~0 := 0; [L336] is_master_triggered_#res := is_master_triggered_~__retres1~0; [L837] activate_threads_#t~ret9 := is_master_triggered_#res; [L837] activate_threads_~tmp~1 := activate_threads_#t~ret9; [L837] havoc activate_threads_#t~ret9; [L839-L843] COND FALSE !(0 != activate_threads_~tmp~1) [L845] havoc is_transmit1_triggered_#res; [L845] havoc is_transmit1_triggered_~__retres1~1; [L340] havoc is_transmit1_triggered_~__retres1~1; [L343] COND FALSE !(1 == ~t1_pc~0) [L353] is_transmit1_triggered_~__retres1~1 := 0; [L355] is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; [L845] activate_threads_#t~ret10 := is_transmit1_triggered_#res; [L845] activate_threads_~tmp___0~0 := activate_threads_#t~ret10; [L845] havoc activate_threads_#t~ret10; [L847-L851] COND FALSE !(0 != activate_threads_~tmp___0~0) [L853] havoc is_transmit2_triggered_#res; [L853] havoc is_transmit2_triggered_~__retres1~2; [L359] havoc is_transmit2_triggered_~__retres1~2; [L362] COND FALSE !(1 == ~t2_pc~0) [L372] is_transmit2_triggered_~__retres1~2 := 0; [L374] is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; [L853] activate_threads_#t~ret11 := is_transmit2_triggered_#res; [L853] activate_threads_~tmp___1~0 := activate_threads_#t~ret11; [L853] havoc activate_threads_#t~ret11; [L855-L859] COND FALSE !(0 != activate_threads_~tmp___1~0) [L861] havoc is_transmit3_triggered_#res; [L861] havoc is_transmit3_triggered_~__retres1~3; [L378] havoc is_transmit3_triggered_~__retres1~3; [L381] COND FALSE !(1 == ~t3_pc~0) [L391] is_transmit3_triggered_~__retres1~3 := 0; [L393] is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; [L861] activate_threads_#t~ret12 := is_transmit3_triggered_#res; [L861] activate_threads_~tmp___2~0 := activate_threads_#t~ret12; [L861] havoc activate_threads_#t~ret12; [L863-L867] COND FALSE !(0 != activate_threads_~tmp___2~0) [L869] havoc is_transmit4_triggered_#res; [L869] havoc is_transmit4_triggered_~__retres1~4; [L397] havoc is_transmit4_triggered_~__retres1~4; [L400] COND FALSE !(1 == ~t4_pc~0) [L410] is_transmit4_triggered_~__retres1~4 := 0; [L412] is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; [L869] activate_threads_#t~ret13 := is_transmit4_triggered_#res; [L869] activate_threads_~tmp___3~0 := activate_threads_#t~ret13; [L869] havoc activate_threads_#t~ret13; [L871-L875] COND FALSE !(0 != activate_threads_~tmp___3~0) [L877] havoc is_transmit5_triggered_#res; [L877] havoc is_transmit5_triggered_~__retres1~5; [L416] havoc is_transmit5_triggered_~__retres1~5; [L419] COND FALSE !(1 == ~t5_pc~0) [L429] is_transmit5_triggered_~__retres1~5 := 0; [L431] is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; [L877] activate_threads_#t~ret14 := is_transmit5_triggered_#res; [L877] activate_threads_~tmp___4~0 := activate_threads_#t~ret14; [L877] havoc activate_threads_#t~ret14; [L879-L883] COND FALSE !(0 != activate_threads_~tmp___4~0) [L885] havoc is_transmit6_triggered_#res; [L885] havoc is_transmit6_triggered_~__retres1~6; [L435] havoc is_transmit6_triggered_~__retres1~6; [L438] COND FALSE !(1 == ~t6_pc~0) [L448] is_transmit6_triggered_~__retres1~6 := 0; [L450] is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; [L885] activate_threads_#t~ret15 := is_transmit6_triggered_#res; [L885] activate_threads_~tmp___5~0 := activate_threads_#t~ret15; [L885] havoc activate_threads_#t~ret15; [L887-L891] COND FALSE !(0 != activate_threads_~tmp___5~0) [L752] COND FALSE !(1 == ~M_E~0) [L757] COND FALSE !(1 == ~T1_E~0) [L762] COND FALSE !(1 == ~T2_E~0) [L767] COND FALSE !(1 == ~T3_E~0) [L772] COND FALSE !(1 == ~T4_E~0) [L777] COND FALSE !(1 == ~T5_E~0) [L782] COND FALSE !(1 == ~T6_E~0) [L787] COND FALSE !(1 == ~E_M~0) [L792] COND FALSE !(1 == ~E_1~0) [L797] COND FALSE !(1 == ~E_2~0) [L802] COND FALSE !(1 == ~E_3~0) [L807] COND FALSE !(1 == ~E_4~0) [L812] COND FALSE !(1 == ~E_5~0) [L817] COND FALSE !(1 == ~E_6~0) [L1043-L1080] COND FALSE !(false) [L1046] start_simulation_~kernel_st~0 := 1; [L1047] havoc eval_#t~ret1, eval_#t~nondet2, eval_~tmp_ndt_1~0, eval_#t~nondet3, eval_~tmp_ndt_2~0, eval_#t~nondet4, eval_~tmp_ndt_3~0, eval_#t~nondet5, eval_~tmp_ndt_4~0, eval_#t~nondet6, eval_~tmp_ndt_5~0, eval_#t~nondet7, eval_~tmp_ndt_6~0, eval_#t~nondet8, eval_~tmp_ndt_7~0, eval_~tmp~0; [L551] havoc eval_~tmp~0; [L14] ~m_pc~0 := 0; [L15] ~t1_pc~0 := 0; [L16] ~t2_pc~0 := 0; [L17] ~t3_pc~0 := 0; [L18] ~t4_pc~0 := 0; [L19] ~t5_pc~0 := 0; [L20] ~t6_pc~0 := 0; [L21] ~m_st~0 := 0; [L22] ~t1_st~0 := 0; [L23] ~t2_st~0 := 0; [L24] ~t3_st~0 := 0; [L25] ~t4_st~0 := 0; [L26] ~t5_st~0 := 0; [L27] ~t6_st~0 := 0; [L28] ~m_i~0 := 0; [L29] ~t1_i~0 := 0; [L30] ~t2_i~0 := 0; [L31] ~t3_i~0 := 0; [L32] ~t4_i~0 := 0; [L33] ~t5_i~0 := 0; [L34] ~t6_i~0 := 0; [L35] ~M_E~0 := 2; [L36] ~T1_E~0 := 2; [L37] ~T2_E~0 := 2; [L38] ~T3_E~0 := 2; [L39] ~T4_E~0 := 2; [L40] ~T5_E~0 := 2; [L41] ~T6_E~0 := 2; [L42] ~E_M~0 := 2; [L43] ~E_1~0 := 2; [L44] ~E_2~0 := 2; [L45] ~E_3~0 := 2; [L46] ~E_4~0 := 2; [L47] ~E_5~0 := 2; [L48] ~E_6~0 := 2; [L57] ~token~0 := 0; [L59] ~local~0 := 0; [L1088] havoc ~__retres1~8; [L998] ~m_i~0 := 1; [L999] ~t1_i~0 := 1; [L1000] ~t2_i~0 := 1; [L1001] ~t3_i~0 := 1; [L1002] ~t4_i~0 := 1; [L1003] ~t5_i~0 := 1; [L1004] ~t6_i~0 := 1; [L1029] havoc ~kernel_st~0; [L1030] havoc ~tmp~3; [L1031] havoc ~tmp___0~1; [L1035] ~kernel_st~0 := 0; [L465] COND TRUE 1 == ~m_i~0 [L466] ~m_st~0 := 0; [L470] COND TRUE 1 == ~t1_i~0 [L471] ~t1_st~0 := 0; [L475] COND TRUE 1 == ~t2_i~0 [L476] ~t2_st~0 := 0; [L480] COND TRUE 1 == ~t3_i~0 [L481] ~t3_st~0 := 0; [L485] COND TRUE 1 == ~t4_i~0 [L486] ~t4_st~0 := 0; [L490] COND TRUE 1 == ~t5_i~0 [L491] ~t5_st~0 := 0; [L495] COND TRUE 1 == ~t6_i~0 [L496] ~t6_st~0 := 0; [L674] COND FALSE !(0 == ~M_E~0) [L679] COND FALSE !(0 == ~T1_E~0) [L684] COND FALSE !(0 == ~T2_E~0) [L689] COND FALSE !(0 == ~T3_E~0) [L694] COND FALSE !(0 == ~T4_E~0) [L699] COND FALSE !(0 == ~T5_E~0) [L704] COND FALSE !(0 == ~T6_E~0) [L709] COND FALSE !(0 == ~E_M~0) [L714] COND FALSE !(0 == ~E_1~0) [L719] COND FALSE !(0 == ~E_2~0) [L724] COND FALSE !(0 == ~E_3~0) [L729] COND FALSE !(0 == ~E_4~0) [L734] COND FALSE !(0 == ~E_5~0) [L739] COND FALSE !(0 == ~E_6~0) [L827] havoc ~tmp~1; [L828] havoc ~tmp___0~0; [L829] havoc ~tmp___1~0; [L830] havoc ~tmp___2~0; [L831] havoc ~tmp___3~0; [L832] havoc ~tmp___4~0; [L833] havoc ~tmp___5~0; [L321] havoc ~__retres1~0; [L324] COND FALSE !(1 == ~m_pc~0) [L334] ~__retres1~0 := 0; [L336] #res := ~__retres1~0; [L837] ~tmp~1 := #t~ret9; [L837] havoc #t~ret9; [L839-L843] COND FALSE !(0 != ~tmp~1) [L340] havoc ~__retres1~1; [L343] COND FALSE !(1 == ~t1_pc~0) [L353] ~__retres1~1 := 0; [L355] #res := ~__retres1~1; [L845] ~tmp___0~0 := #t~ret10; [L845] havoc #t~ret10; [L847-L851] COND FALSE !(0 != ~tmp___0~0) [L359] havoc ~__retres1~2; [L362] COND FALSE !(1 == ~t2_pc~0) [L372] ~__retres1~2 := 0; [L374] #res := ~__retres1~2; [L853] ~tmp___1~0 := #t~ret11; [L853] havoc #t~ret11; [L855-L859] COND FALSE !(0 != ~tmp___1~0) [L378] havoc ~__retres1~3; [L381] COND FALSE !(1 == ~t3_pc~0) [L391] ~__retres1~3 := 0; [L393] #res := ~__retres1~3; [L861] ~tmp___2~0 := #t~ret12; [L861] havoc #t~ret12; [L863-L867] COND FALSE !(0 != ~tmp___2~0) [L397] havoc ~__retres1~4; [L400] COND FALSE !(1 == ~t4_pc~0) [L410] ~__retres1~4 := 0; [L412] #res := ~__retres1~4; [L869] ~tmp___3~0 := #t~ret13; [L869] havoc #t~ret13; [L871-L875] COND FALSE !(0 != ~tmp___3~0) [L416] havoc ~__retres1~5; [L419] COND FALSE !(1 == ~t5_pc~0) [L429] ~__retres1~5 := 0; [L431] #res := ~__retres1~5; [L877] ~tmp___4~0 := #t~ret14; [L877] havoc #t~ret14; [L879-L883] COND FALSE !(0 != ~tmp___4~0) [L435] havoc ~__retres1~6; [L438] COND FALSE !(1 == ~t6_pc~0) [L448] ~__retres1~6 := 0; [L450] #res := ~__retres1~6; [L885] ~tmp___5~0 := #t~ret15; [L885] havoc #t~ret15; [L887-L891] COND FALSE !(0 != ~tmp___5~0) [L752] COND FALSE !(1 == ~M_E~0) [L757] COND FALSE !(1 == ~T1_E~0) [L762] COND FALSE !(1 == ~T2_E~0) [L767] COND FALSE !(1 == ~T3_E~0) [L772] COND FALSE !(1 == ~T4_E~0) [L777] COND FALSE !(1 == ~T5_E~0) [L782] COND FALSE !(1 == ~T6_E~0) [L787] COND FALSE !(1 == ~E_M~0) [L792] COND FALSE !(1 == ~E_1~0) [L797] COND FALSE !(1 == ~E_2~0) [L802] COND FALSE !(1 == ~E_3~0) [L807] COND FALSE !(1 == ~E_4~0) [L812] COND FALSE !(1 == ~E_5~0) [L817] COND FALSE !(1 == ~E_6~0) [L1043-L1080] COND FALSE !(false) [L1046] ~kernel_st~0 := 1; [L551] havoc ~tmp~0; ----- ----- class de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.CACSL2BoogieBacktranslator [L14] ~m_pc~0 := 0; [L15] ~t1_pc~0 := 0; [L16] ~t2_pc~0 := 0; [L17] ~t3_pc~0 := 0; [L18] ~t4_pc~0 := 0; [L19] ~t5_pc~0 := 0; [L20] ~t6_pc~0 := 0; [L21] ~m_st~0 := 0; [L22] ~t1_st~0 := 0; [L23] ~t2_st~0 := 0; [L24] ~t3_st~0 := 0; [L25] ~t4_st~0 := 0; [L26] ~t5_st~0 := 0; [L27] ~t6_st~0 := 0; [L28] ~m_i~0 := 0; [L29] ~t1_i~0 := 0; [L30] ~t2_i~0 := 0; [L31] ~t3_i~0 := 0; [L32] ~t4_i~0 := 0; [L33] ~t5_i~0 := 0; [L34] ~t6_i~0 := 0; [L35] ~M_E~0 := 2; [L36] ~T1_E~0 := 2; [L37] ~T2_E~0 := 2; [L38] ~T3_E~0 := 2; [L39] ~T4_E~0 := 2; [L40] ~T5_E~0 := 2; [L41] ~T6_E~0 := 2; [L42] ~E_M~0 := 2; [L43] ~E_1~0 := 2; [L44] ~E_2~0 := 2; [L45] ~E_3~0 := 2; [L46] ~E_4~0 := 2; [L47] ~E_5~0 := 2; [L48] ~E_6~0 := 2; [L57] ~token~0 := 0; [L59] ~local~0 := 0; [L1088] havoc ~__retres1~8; [L998] ~m_i~0 := 1; [L999] ~t1_i~0 := 1; [L1000] ~t2_i~0 := 1; [L1001] ~t3_i~0 := 1; [L1002] ~t4_i~0 := 1; [L1003] ~t5_i~0 := 1; [L1004] ~t6_i~0 := 1; [L1029] havoc ~kernel_st~0; [L1030] havoc ~tmp~3; [L1031] havoc ~tmp___0~1; [L1035] ~kernel_st~0 := 0; [L465] COND TRUE 1 == ~m_i~0 [L466] ~m_st~0 := 0; [L470] COND TRUE 1 == ~t1_i~0 [L471] ~t1_st~0 := 0; [L475] COND TRUE 1 == ~t2_i~0 [L476] ~t2_st~0 := 0; [L480] COND TRUE 1 == ~t3_i~0 [L481] ~t3_st~0 := 0; [L485] COND TRUE 1 == ~t4_i~0 [L486] ~t4_st~0 := 0; [L490] COND TRUE 1 == ~t5_i~0 [L491] ~t5_st~0 := 0; [L495] COND TRUE 1 == ~t6_i~0 [L496] ~t6_st~0 := 0; [L674] COND FALSE !(0 == ~M_E~0) [L679] COND FALSE !(0 == ~T1_E~0) [L684] COND FALSE !(0 == ~T2_E~0) [L689] COND FALSE !(0 == ~T3_E~0) [L694] COND FALSE !(0 == ~T4_E~0) [L699] COND FALSE !(0 == ~T5_E~0) [L704] COND FALSE !(0 == ~T6_E~0) [L709] COND FALSE !(0 == ~E_M~0) [L714] COND FALSE !(0 == ~E_1~0) [L719] COND FALSE !(0 == ~E_2~0) [L724] COND FALSE !(0 == ~E_3~0) [L729] COND FALSE !(0 == ~E_4~0) [L734] COND FALSE !(0 == ~E_5~0) [L739] COND FALSE !(0 == ~E_6~0) [L827] havoc ~tmp~1; [L828] havoc ~tmp___0~0; [L829] havoc ~tmp___1~0; [L830] havoc ~tmp___2~0; [L831] havoc ~tmp___3~0; [L832] havoc ~tmp___4~0; [L833] havoc ~tmp___5~0; [L321] havoc ~__retres1~0; [L324] COND FALSE !(1 == ~m_pc~0) [L334] ~__retres1~0 := 0; [L336] #res := ~__retres1~0; [L837] ~tmp~1 := #t~ret9; [L837] havoc #t~ret9; [L839-L843] COND FALSE !(0 != ~tmp~1) [L340] havoc ~__retres1~1; [L343] COND FALSE !(1 == ~t1_pc~0) [L353] ~__retres1~1 := 0; [L355] #res := ~__retres1~1; [L845] ~tmp___0~0 := #t~ret10; [L845] havoc #t~ret10; [L847-L851] COND FALSE !(0 != ~tmp___0~0) [L359] havoc ~__retres1~2; [L362] COND FALSE !(1 == ~t2_pc~0) [L372] ~__retres1~2 := 0; [L374] #res := ~__retres1~2; [L853] ~tmp___1~0 := #t~ret11; [L853] havoc #t~ret11; [L855-L859] COND FALSE !(0 != ~tmp___1~0) [L378] havoc ~__retres1~3; [L381] COND FALSE !(1 == ~t3_pc~0) [L391] ~__retres1~3 := 0; [L393] #res := ~__retres1~3; [L861] ~tmp___2~0 := #t~ret12; [L861] havoc #t~ret12; [L863-L867] COND FALSE !(0 != ~tmp___2~0) [L397] havoc ~__retres1~4; [L400] COND FALSE !(1 == ~t4_pc~0) [L410] ~__retres1~4 := 0; [L412] #res := ~__retres1~4; [L869] ~tmp___3~0 := #t~ret13; [L869] havoc #t~ret13; [L871-L875] COND FALSE !(0 != ~tmp___3~0) [L416] havoc ~__retres1~5; [L419] COND FALSE !(1 == ~t5_pc~0) [L429] ~__retres1~5 := 0; [L431] #res := ~__retres1~5; [L877] ~tmp___4~0 := #t~ret14; [L877] havoc #t~ret14; [L879-L883] COND FALSE !(0 != ~tmp___4~0) [L435] havoc ~__retres1~6; [L438] COND FALSE !(1 == ~t6_pc~0) [L448] ~__retres1~6 := 0; [L450] #res := ~__retres1~6; [L885] ~tmp___5~0 := #t~ret15; [L885] havoc #t~ret15; [L887-L891] COND FALSE !(0 != ~tmp___5~0) [L752] COND FALSE !(1 == ~M_E~0) [L757] COND FALSE !(1 == ~T1_E~0) [L762] COND FALSE !(1 == ~T2_E~0) [L767] COND FALSE !(1 == ~T3_E~0) [L772] COND FALSE !(1 == ~T4_E~0) [L777] COND FALSE !(1 == ~T5_E~0) [L782] COND FALSE !(1 == ~T6_E~0) [L787] COND FALSE !(1 == ~E_M~0) [L792] COND FALSE !(1 == ~E_1~0) [L797] COND FALSE !(1 == ~E_2~0) [L802] COND FALSE !(1 == ~E_3~0) [L807] COND FALSE !(1 == ~E_4~0) [L812] COND FALSE !(1 == ~E_5~0) [L817] COND FALSE !(1 == ~E_6~0) [L1043-L1080] COND FALSE !(false) [L1046] ~kernel_st~0 := 1; [L551] havoc ~tmp~0; [L14] int m_pc = 0; [L15] int t1_pc = 0; [L16] int t2_pc = 0; [L17] int t3_pc = 0; [L18] int t4_pc = 0; [L19] int t5_pc = 0; [L20] int t6_pc = 0; [L21] int m_st ; [L22] int t1_st ; [L23] int t2_st ; [L24] int t3_st ; [L25] int t4_st ; [L26] int t5_st ; [L27] int t6_st ; [L28] int m_i ; [L29] int t1_i ; [L30] int t2_i ; [L31] int t3_i ; [L32] int t4_i ; [L33] int t5_i ; [L34] int t6_i ; [L35] int M_E = 2; [L36] int T1_E = 2; [L37] int T2_E = 2; [L38] int T3_E = 2; [L39] int T4_E = 2; [L40] int T5_E = 2; [L41] int T6_E = 2; [L42] int E_M = 2; [L43] int E_1 = 2; [L44] int E_2 = 2; [L45] int E_3 = 2; [L46] int E_4 = 2; [L47] int E_5 = 2; [L48] int E_6 = 2; [L57] int token ; [L59] int local ; [L1088] int __retres1 ; [L998] m_i = 1 [L999] t1_i = 1 [L1000] t2_i = 1 [L1001] t3_i = 1 [L1002] t4_i = 1 [L1003] t5_i = 1 [L1004] t6_i = 1 [L1029] int kernel_st ; [L1030] int tmp ; [L1031] int tmp___0 ; [L1035] kernel_st = 0 [L465] COND TRUE m_i == 1 [L466] m_st = 0 [L470] COND TRUE t1_i == 1 [L471] t1_st = 0 [L475] COND TRUE t2_i == 1 [L476] t2_st = 0 [L480] COND TRUE t3_i == 1 [L481] t3_st = 0 [L485] COND TRUE t4_i == 1 [L486] t4_st = 0 [L490] COND TRUE t5_i == 1 [L491] t5_st = 0 [L495] COND TRUE t6_i == 1 [L496] t6_st = 0 [L674] COND FALSE !(M_E == 0) [L679] COND FALSE !(T1_E == 0) [L684] COND FALSE !(T2_E == 0) [L689] COND FALSE !(T3_E == 0) [L694] COND FALSE !(T4_E == 0) [L699] COND FALSE !(T5_E == 0) [L704] COND FALSE !(T6_E == 0) [L709] COND FALSE !(E_M == 0) [L714] COND FALSE !(E_1 == 0) [L719] COND FALSE !(E_2 == 0) [L724] COND FALSE !(E_3 == 0) [L729] COND FALSE !(E_4 == 0) [L734] COND FALSE !(E_5 == 0) [L739] COND FALSE !(E_6 == 0) [L827] int tmp ; [L828] int tmp___0 ; [L829] int tmp___1 ; [L830] int tmp___2 ; [L831] int tmp___3 ; [L832] int tmp___4 ; [L833] int tmp___5 ; [L321] int __retres1 ; [L324] COND FALSE !(m_pc == 1) [L334] __retres1 = 0 [L336] return (__retres1); [L837] tmp = is_master_triggered() [L839] COND FALSE !(\read(tmp)) [L340] int __retres1 ; [L343] COND FALSE !(t1_pc == 1) [L353] __retres1 = 0 [L355] return (__retres1); [L845] tmp___0 = is_transmit1_triggered() [L847] COND FALSE !(\read(tmp___0)) [L359] int __retres1 ; [L362] COND FALSE !(t2_pc == 1) [L372] __retres1 = 0 [L374] return (__retres1); [L853] tmp___1 = is_transmit2_triggered() [L855] COND FALSE !(\read(tmp___1)) [L378] int __retres1 ; [L381] COND FALSE !(t3_pc == 1) [L391] __retres1 = 0 [L393] return (__retres1); [L861] tmp___2 = is_transmit3_triggered() [L863] COND FALSE !(\read(tmp___2)) [L397] int __retres1 ; [L400] COND FALSE !(t4_pc == 1) [L410] __retres1 = 0 [L412] return (__retres1); [L869] tmp___3 = is_transmit4_triggered() [L871] COND FALSE !(\read(tmp___3)) [L416] int __retres1 ; [L419] COND FALSE !(t5_pc == 1) [L429] __retres1 = 0 [L431] return (__retres1); [L877] tmp___4 = is_transmit5_triggered() [L879] COND FALSE !(\read(tmp___4)) [L435] int __retres1 ; [L438] COND FALSE !(t6_pc == 1) [L448] __retres1 = 0 [L450] return (__retres1); [L885] tmp___5 = is_transmit6_triggered() [L887] COND FALSE !(\read(tmp___5)) [L752] COND FALSE !(M_E == 1) [L757] COND FALSE !(T1_E == 1) [L762] COND FALSE !(T2_E == 1) [L767] COND FALSE !(T3_E == 1) [L772] COND FALSE !(T4_E == 1) [L777] COND FALSE !(T5_E == 1) [L782] COND FALSE !(T6_E == 1) [L787] COND FALSE !(E_M == 1) [L792] COND FALSE !(E_1 == 1) [L797] COND FALSE !(E_2 == 1) [L802] COND FALSE !(E_3 == 1) [L807] COND FALSE !(E_4 == 1) [L812] COND FALSE !(E_5 == 1) [L817] COND FALSE !(E_6 == 1) [L1043] COND TRUE 1 [L1046] kernel_st = 1 [L551] int tmp ; ----- ----- class de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder.RCFGBacktranslator [?] assume !false; [?] havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~7;havoc exists_runnable_thread_~__retres1~7; [?] assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7 := 1; [?] exists_runnable_thread_#res := exists_runnable_thread_~__retres1~7; [?] eval_#t~ret1 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret1;havoc eval_#t~ret1; [?] assume 0 != eval_~tmp~0; [?] assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0;eval_~tmp_ndt_1~0 := eval_#t~nondet2;havoc eval_#t~nondet2; [?] assume !(0 != eval_~tmp_ndt_1~0); [?] assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0;eval_~tmp_ndt_2~0 := eval_#t~nondet3;havoc eval_#t~nondet3; [?] assume !(0 != eval_~tmp_ndt_2~0); [?] assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0;eval_~tmp_ndt_3~0 := eval_#t~nondet4;havoc eval_#t~nondet4; [?] assume !(0 != eval_~tmp_ndt_3~0); [?] assume 0 == ~t3_st~0;havoc eval_~tmp_ndt_4~0;eval_~tmp_ndt_4~0 := eval_#t~nondet5;havoc eval_#t~nondet5; [?] assume !(0 != eval_~tmp_ndt_4~0); [?] assume 0 == ~t4_st~0;havoc eval_~tmp_ndt_5~0;eval_~tmp_ndt_5~0 := eval_#t~nondet6;havoc eval_#t~nondet6; [?] assume !(0 != eval_~tmp_ndt_5~0); [?] assume 0 == ~t5_st~0;havoc eval_~tmp_ndt_6~0;eval_~tmp_ndt_6~0 := eval_#t~nondet7;havoc eval_#t~nondet7; [?] assume !(0 != eval_~tmp_ndt_6~0); [?] assume 0 == ~t6_st~0;havoc eval_~tmp_ndt_7~0;eval_~tmp_ndt_7~0 := eval_#t~nondet8;havoc eval_#t~nondet8; [?] assume !(0 != eval_~tmp_ndt_7~0); [L555-L663] assume !false; [L558] havoc exists_runnable_thread_#res; [L558] havoc exists_runnable_thread_~__retres1~7; [L505] havoc exists_runnable_thread_~__retres1~7; [L508-L543] assume 0 == ~m_st~0; [L509] exists_runnable_thread_~__retres1~7 := 1; [L546] exists_runnable_thread_#res := exists_runnable_thread_~__retres1~7; [L558] eval_#t~ret1 := exists_runnable_thread_#res; [L558] eval_~tmp~0 := eval_#t~ret1; [L558] havoc eval_#t~ret1; [L560-L564] assume 0 != eval_~tmp~0; [L565-L578] assume 0 == ~m_st~0; [L566] havoc eval_~tmp_ndt_1~0; [L567] eval_~tmp_ndt_1~0 := eval_#t~nondet2; [L567] havoc eval_#t~nondet2; [L568-L575] assume !(0 != eval_~tmp_ndt_1~0); [L579-L592] assume 0 == ~t1_st~0; [L580] havoc eval_~tmp_ndt_2~0; [L581] eval_~tmp_ndt_2~0 := eval_#t~nondet3; [L581] havoc eval_#t~nondet3; [L582-L589] assume !(0 != eval_~tmp_ndt_2~0); [L593-L606] assume 0 == ~t2_st~0; [L594] havoc eval_~tmp_ndt_3~0; [L595] eval_~tmp_ndt_3~0 := eval_#t~nondet4; [L595] havoc eval_#t~nondet4; [L596-L603] assume !(0 != eval_~tmp_ndt_3~0); [L607-L620] assume 0 == ~t3_st~0; [L608] havoc eval_~tmp_ndt_4~0; [L609] eval_~tmp_ndt_4~0 := eval_#t~nondet5; [L609] havoc eval_#t~nondet5; [L610-L617] assume !(0 != eval_~tmp_ndt_4~0); [L621-L634] assume 0 == ~t4_st~0; [L622] havoc eval_~tmp_ndt_5~0; [L623] eval_~tmp_ndt_5~0 := eval_#t~nondet6; [L623] havoc eval_#t~nondet6; [L624-L631] assume !(0 != eval_~tmp_ndt_5~0); [L635-L648] assume 0 == ~t5_st~0; [L636] havoc eval_~tmp_ndt_6~0; [L637] eval_~tmp_ndt_6~0 := eval_#t~nondet7; [L637] havoc eval_#t~nondet7; [L638-L645] assume !(0 != eval_~tmp_ndt_6~0); [L649-L662] assume 0 == ~t6_st~0; [L650] havoc eval_~tmp_ndt_7~0; [L651] eval_~tmp_ndt_7~0 := eval_#t~nondet8; [L651] havoc eval_#t~nondet8; [L652-L659] assume !(0 != eval_~tmp_ndt_7~0); ----- ----- class de.uni_freiburg.informatik.ultimate.boogie.preprocessor.BoogiePreprocessorBacktranslator [L555-L663] assume !false; [L558] havoc exists_runnable_thread_#res; [L558] havoc exists_runnable_thread_~__retres1~7; [L505] havoc exists_runnable_thread_~__retres1~7; [L508-L543] assume 0 == ~m_st~0; [L509] exists_runnable_thread_~__retres1~7 := 1; [L546] exists_runnable_thread_#res := exists_runnable_thread_~__retres1~7; [L558] eval_#t~ret1 := exists_runnable_thread_#res; [L558] eval_~tmp~0 := eval_#t~ret1; [L558] havoc eval_#t~ret1; [L560-L564] assume 0 != eval_~tmp~0; [L565-L578] assume 0 == ~m_st~0; [L566] havoc eval_~tmp_ndt_1~0; [L567] eval_~tmp_ndt_1~0 := eval_#t~nondet2; [L567] havoc eval_#t~nondet2; [L568-L575] assume !(0 != eval_~tmp_ndt_1~0); [L579-L592] assume 0 == ~t1_st~0; [L580] havoc eval_~tmp_ndt_2~0; [L581] eval_~tmp_ndt_2~0 := eval_#t~nondet3; [L581] havoc eval_#t~nondet3; [L582-L589] assume !(0 != eval_~tmp_ndt_2~0); [L593-L606] assume 0 == ~t2_st~0; [L594] havoc eval_~tmp_ndt_3~0; [L595] eval_~tmp_ndt_3~0 := eval_#t~nondet4; [L595] havoc eval_#t~nondet4; [L596-L603] assume !(0 != eval_~tmp_ndt_3~0); [L607-L620] assume 0 == ~t3_st~0; [L608] havoc eval_~tmp_ndt_4~0; [L609] eval_~tmp_ndt_4~0 := eval_#t~nondet5; [L609] havoc eval_#t~nondet5; [L610-L617] assume !(0 != eval_~tmp_ndt_4~0); [L621-L634] assume 0 == ~t4_st~0; [L622] havoc eval_~tmp_ndt_5~0; [L623] eval_~tmp_ndt_5~0 := eval_#t~nondet6; [L623] havoc eval_#t~nondet6; [L624-L631] assume !(0 != eval_~tmp_ndt_5~0); [L635-L648] assume 0 == ~t5_st~0; [L636] havoc eval_~tmp_ndt_6~0; [L637] eval_~tmp_ndt_6~0 := eval_#t~nondet7; [L637] havoc eval_#t~nondet7; [L638-L645] assume !(0 != eval_~tmp_ndt_6~0); [L649-L662] assume 0 == ~t6_st~0; [L650] havoc eval_~tmp_ndt_7~0; [L651] eval_~tmp_ndt_7~0 := eval_#t~nondet8; [L651] havoc eval_#t~nondet8; [L652-L659] assume !(0 != eval_~tmp_ndt_7~0); [L555-L663] COND FALSE !(false) [L558] havoc exists_runnable_thread_#res; [L558] havoc exists_runnable_thread_~__retres1~7; [L505] havoc exists_runnable_thread_~__retres1~7; [L508] COND TRUE 0 == ~m_st~0 [L509] exists_runnable_thread_~__retres1~7 := 1; [L546] exists_runnable_thread_#res := exists_runnable_thread_~__retres1~7; [L558] eval_#t~ret1 := exists_runnable_thread_#res; [L558] eval_~tmp~0 := eval_#t~ret1; [L558] havoc eval_#t~ret1; [L560-L564] COND TRUE 0 != eval_~tmp~0 [L565] COND TRUE 0 == ~m_st~0 [L566] havoc eval_~tmp_ndt_1~0; [L567] eval_~tmp_ndt_1~0 := eval_#t~nondet2; [L567] havoc eval_#t~nondet2; [L568-L575] COND FALSE !(0 != eval_~tmp_ndt_1~0) [L579] COND TRUE 0 == ~t1_st~0 [L580] havoc eval_~tmp_ndt_2~0; [L581] eval_~tmp_ndt_2~0 := eval_#t~nondet3; [L581] havoc eval_#t~nondet3; [L582-L589] COND FALSE !(0 != eval_~tmp_ndt_2~0) [L593] COND TRUE 0 == ~t2_st~0 [L594] havoc eval_~tmp_ndt_3~0; [L595] eval_~tmp_ndt_3~0 := eval_#t~nondet4; [L595] havoc eval_#t~nondet4; [L596-L603] COND FALSE !(0 != eval_~tmp_ndt_3~0) [L607] COND TRUE 0 == ~t3_st~0 [L608] havoc eval_~tmp_ndt_4~0; [L609] eval_~tmp_ndt_4~0 := eval_#t~nondet5; [L609] havoc eval_#t~nondet5; [L610-L617] COND FALSE !(0 != eval_~tmp_ndt_4~0) [L621] COND TRUE 0 == ~t4_st~0 [L622] havoc eval_~tmp_ndt_5~0; [L623] eval_~tmp_ndt_5~0 := eval_#t~nondet6; [L623] havoc eval_#t~nondet6; [L624-L631] COND FALSE !(0 != eval_~tmp_ndt_5~0) [L635] COND TRUE 0 == ~t5_st~0 [L636] havoc eval_~tmp_ndt_6~0; [L637] eval_~tmp_ndt_6~0 := eval_#t~nondet7; [L637] havoc eval_#t~nondet7; [L638-L645] COND FALSE !(0 != eval_~tmp_ndt_6~0) [L649] COND TRUE 0 == ~t6_st~0 [L650] havoc eval_~tmp_ndt_7~0; [L651] eval_~tmp_ndt_7~0 := eval_#t~nondet8; [L651] havoc eval_#t~nondet8; [L652-L659] COND FALSE !(0 != eval_~tmp_ndt_7~0) ----- ----- class de.uni_freiburg.informatik.ultimate.boogie.procedureinliner.backtranslation.InlinerBacktranslator [L555-L663] COND FALSE !(false) [L558] havoc exists_runnable_thread_#res; [L558] havoc exists_runnable_thread_~__retres1~7; [L505] havoc exists_runnable_thread_~__retres1~7; [L508] COND TRUE 0 == ~m_st~0 [L509] exists_runnable_thread_~__retres1~7 := 1; [L546] exists_runnable_thread_#res := exists_runnable_thread_~__retres1~7; [L558] eval_#t~ret1 := exists_runnable_thread_#res; [L558] eval_~tmp~0 := eval_#t~ret1; [L558] havoc eval_#t~ret1; [L560-L564] COND TRUE 0 != eval_~tmp~0 [L565] COND TRUE 0 == ~m_st~0 [L566] havoc eval_~tmp_ndt_1~0; [L567] eval_~tmp_ndt_1~0 := eval_#t~nondet2; [L567] havoc eval_#t~nondet2; [L568-L575] COND FALSE !(0 != eval_~tmp_ndt_1~0) [L579] COND TRUE 0 == ~t1_st~0 [L580] havoc eval_~tmp_ndt_2~0; [L581] eval_~tmp_ndt_2~0 := eval_#t~nondet3; [L581] havoc eval_#t~nondet3; [L582-L589] COND FALSE !(0 != eval_~tmp_ndt_2~0) [L593] COND TRUE 0 == ~t2_st~0 [L594] havoc eval_~tmp_ndt_3~0; [L595] eval_~tmp_ndt_3~0 := eval_#t~nondet4; [L595] havoc eval_#t~nondet4; [L596-L603] COND FALSE !(0 != eval_~tmp_ndt_3~0) [L607] COND TRUE 0 == ~t3_st~0 [L608] havoc eval_~tmp_ndt_4~0; [L609] eval_~tmp_ndt_4~0 := eval_#t~nondet5; [L609] havoc eval_#t~nondet5; [L610-L617] COND FALSE !(0 != eval_~tmp_ndt_4~0) [L621] COND TRUE 0 == ~t4_st~0 [L622] havoc eval_~tmp_ndt_5~0; [L623] eval_~tmp_ndt_5~0 := eval_#t~nondet6; [L623] havoc eval_#t~nondet6; [L624-L631] COND FALSE !(0 != eval_~tmp_ndt_5~0) [L635] COND TRUE 0 == ~t5_st~0 [L636] havoc eval_~tmp_ndt_6~0; [L637] eval_~tmp_ndt_6~0 := eval_#t~nondet7; [L637] havoc eval_#t~nondet7; [L638-L645] COND FALSE !(0 != eval_~tmp_ndt_6~0) [L649] COND TRUE 0 == ~t6_st~0 [L650] havoc eval_~tmp_ndt_7~0; [L651] eval_~tmp_ndt_7~0 := eval_#t~nondet8; [L651] havoc eval_#t~nondet8; [L652-L659] COND FALSE !(0 != eval_~tmp_ndt_7~0) [L555-L663] COND FALSE !(false) [L505] havoc ~__retres1~7; [L508] COND TRUE 0 == ~m_st~0 [L509] ~__retres1~7 := 1; [L546] #res := ~__retres1~7; [L558] ~tmp~0 := #t~ret1; [L558] havoc #t~ret1; [L560-L564] COND TRUE 0 != ~tmp~0 [L565] COND TRUE 0 == ~m_st~0 [L566] havoc ~tmp_ndt_1~0; [L567] ~tmp_ndt_1~0 := #t~nondet2; [L567] havoc #t~nondet2; [L568-L575] COND FALSE !(0 != ~tmp_ndt_1~0) [L579] COND TRUE 0 == ~t1_st~0 [L580] havoc ~tmp_ndt_2~0; [L581] ~tmp_ndt_2~0 := #t~nondet3; [L581] havoc #t~nondet3; [L582-L589] COND FALSE !(0 != ~tmp_ndt_2~0) [L593] COND TRUE 0 == ~t2_st~0 [L594] havoc ~tmp_ndt_3~0; [L595] ~tmp_ndt_3~0 := #t~nondet4; [L595] havoc #t~nondet4; [L596-L603] COND FALSE !(0 != ~tmp_ndt_3~0) [L607] COND TRUE 0 == ~t3_st~0 [L608] havoc ~tmp_ndt_4~0; [L609] ~tmp_ndt_4~0 := #t~nondet5; [L609] havoc #t~nondet5; [L610-L617] COND FALSE !(0 != ~tmp_ndt_4~0) [L621] COND TRUE 0 == ~t4_st~0 [L622] havoc ~tmp_ndt_5~0; [L623] ~tmp_ndt_5~0 := #t~nondet6; [L623] havoc #t~nondet6; [L624-L631] COND FALSE !(0 != ~tmp_ndt_5~0) [L635] COND TRUE 0 == ~t5_st~0 [L636] havoc ~tmp_ndt_6~0; [L637] ~tmp_ndt_6~0 := #t~nondet7; [L637] havoc #t~nondet7; [L638-L645] COND FALSE !(0 != ~tmp_ndt_6~0) [L649] COND TRUE 0 == ~t6_st~0 [L650] havoc ~tmp_ndt_7~0; [L651] ~tmp_ndt_7~0 := #t~nondet8; [L651] havoc #t~nondet8; [L652-L659] COND FALSE !(0 != ~tmp_ndt_7~0) ----- ----- class de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.CACSL2BoogieBacktranslator [L555-L663] COND FALSE !(false) [L505] havoc ~__retres1~7; [L508] COND TRUE 0 == ~m_st~0 [L509] ~__retres1~7 := 1; [L546] #res := ~__retres1~7; [L558] ~tmp~0 := #t~ret1; [L558] havoc #t~ret1; [L560-L564] COND TRUE 0 != ~tmp~0 [L565] COND TRUE 0 == ~m_st~0 [L566] havoc ~tmp_ndt_1~0; [L567] ~tmp_ndt_1~0 := #t~nondet2; [L567] havoc #t~nondet2; [L568-L575] COND FALSE !(0 != ~tmp_ndt_1~0) [L579] COND TRUE 0 == ~t1_st~0 [L580] havoc ~tmp_ndt_2~0; [L581] ~tmp_ndt_2~0 := #t~nondet3; [L581] havoc #t~nondet3; [L582-L589] COND FALSE !(0 != ~tmp_ndt_2~0) [L593] COND TRUE 0 == ~t2_st~0 [L594] havoc ~tmp_ndt_3~0; [L595] ~tmp_ndt_3~0 := #t~nondet4; [L595] havoc #t~nondet4; [L596-L603] COND FALSE !(0 != ~tmp_ndt_3~0) [L607] COND TRUE 0 == ~t3_st~0 [L608] havoc ~tmp_ndt_4~0; [L609] ~tmp_ndt_4~0 := #t~nondet5; [L609] havoc #t~nondet5; [L610-L617] COND FALSE !(0 != ~tmp_ndt_4~0) [L621] COND TRUE 0 == ~t4_st~0 [L622] havoc ~tmp_ndt_5~0; [L623] ~tmp_ndt_5~0 := #t~nondet6; [L623] havoc #t~nondet6; [L624-L631] COND FALSE !(0 != ~tmp_ndt_5~0) [L635] COND TRUE 0 == ~t5_st~0 [L636] havoc ~tmp_ndt_6~0; [L637] ~tmp_ndt_6~0 := #t~nondet7; [L637] havoc #t~nondet7; [L638-L645] COND FALSE !(0 != ~tmp_ndt_6~0) [L649] COND TRUE 0 == ~t6_st~0 [L650] havoc ~tmp_ndt_7~0; [L651] ~tmp_ndt_7~0 := #t~nondet8; [L651] havoc #t~nondet8; [L652-L659] COND FALSE !(0 != ~tmp_ndt_7~0) [L555] COND TRUE 1 [L505] int __retres1 ; [L508] COND TRUE m_st == 0 [L509] __retres1 = 1 [L546] return (__retres1); [L558] tmp = exists_runnable_thread() [L560] COND TRUE \read(tmp) [L565] COND TRUE m_st == 0 [L566] int tmp_ndt_1; [L567] tmp_ndt_1 = __VERIFIER_nondet_int() [L568] COND FALSE !(\read(tmp_ndt_1)) [L579] COND TRUE t1_st == 0 [L580] int tmp_ndt_2; [L581] tmp_ndt_2 = __VERIFIER_nondet_int() [L582] COND FALSE !(\read(tmp_ndt_2)) [L593] COND TRUE t2_st == 0 [L594] int tmp_ndt_3; [L595] tmp_ndt_3 = __VERIFIER_nondet_int() [L596] COND FALSE !(\read(tmp_ndt_3)) [L607] COND TRUE t3_st == 0 [L608] int tmp_ndt_4; [L609] tmp_ndt_4 = __VERIFIER_nondet_int() [L610] COND FALSE !(\read(tmp_ndt_4)) [L621] COND TRUE t4_st == 0 [L622] int tmp_ndt_5; [L623] tmp_ndt_5 = __VERIFIER_nondet_int() [L624] COND FALSE !(\read(tmp_ndt_5)) [L635] COND TRUE t5_st == 0 [L636] int tmp_ndt_6; [L637] tmp_ndt_6 = __VERIFIER_nondet_int() [L638] COND FALSE !(\read(tmp_ndt_6)) [L649] COND TRUE t6_st == 0 [L650] int tmp_ndt_7; [L651] tmp_ndt_7 = __VERIFIER_nondet_int() [L652] COND FALSE !(\read(tmp_ndt_7)) ----- [2018-11-23 15:00:34,820 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer CFG 23.11 03:00:34 BoogieIcfgContainer [2018-11-23 15:00:34,820 INFO L132 PluginConnector]: ------------------------ END BuchiAutomizer---------------------------- [2018-11-23 15:00:34,820 INFO L113 PluginConnector]: ------------------------Witness Printer---------------------------- [2018-11-23 15:00:34,820 INFO L271 PluginConnector]: Initializing Witness Printer... [2018-11-23 15:00:34,821 INFO L276 PluginConnector]: Witness Printer initialized [2018-11-23 15:00:34,821 INFO L185 PluginConnector]: Executing the observer RCFGCatcher from plugin Witness Printer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 23.11 02:59:44" (3/4) ... [2018-11-23 15:00:34,824 INFO L141 WitnessPrinter]: Generating witness for non-termination counterexample ----- class de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder.RCFGBacktranslator [?] ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0; [?] havoc main_#res;havoc main_~__retres1~8;havoc main_~__retres1~8;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; [?] havoc start_simulation_#t~ret17, start_simulation_#t~ret18, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; [?] assume 1 == ~m_i~0;~m_st~0 := 0; [?] assume 1 == ~t1_i~0;~t1_st~0 := 0; [?] assume 1 == ~t2_i~0;~t2_st~0 := 0; [?] assume 1 == ~t3_i~0;~t3_st~0 := 0; [?] assume 1 == ~t4_i~0;~t4_st~0 := 0; [?] assume 1 == ~t5_i~0;~t5_st~0 := 0; [?] assume 1 == ~t6_i~0;~t6_st~0 := 0; [?] assume !(0 == ~M_E~0); [?] assume !(0 == ~T1_E~0); [?] assume !(0 == ~T2_E~0); [?] assume !(0 == ~T3_E~0); [?] assume !(0 == ~T4_E~0); [?] assume !(0 == ~T5_E~0); [?] assume !(0 == ~T6_E~0); [?] assume !(0 == ~E_M~0); [?] assume !(0 == ~E_1~0); [?] assume !(0 == ~E_2~0); [?] assume !(0 == ~E_3~0); [?] assume !(0 == ~E_4~0); [?] assume !(0 == ~E_5~0); [?] assume !(0 == ~E_6~0); [?] havoc activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; [?] assume !(1 == ~m_pc~0); [?] is_master_triggered_~__retres1~0 := 0; [?] is_master_triggered_#res := is_master_triggered_~__retres1~0; [?] activate_threads_#t~ret9 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; [?] assume !(0 != activate_threads_~tmp~1); [?] havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; [?] assume !(1 == ~t1_pc~0); [?] is_transmit1_triggered_~__retres1~1 := 0; [?] is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; [?] activate_threads_#t~ret10 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; [?] assume !(0 != activate_threads_~tmp___0~0); [?] havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; [?] assume !(1 == ~t2_pc~0); [?] is_transmit2_triggered_~__retres1~2 := 0; [?] is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; [?] activate_threads_#t~ret11 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; [?] assume !(0 != activate_threads_~tmp___1~0); [?] havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; [?] assume !(1 == ~t3_pc~0); [?] is_transmit3_triggered_~__retres1~3 := 0; [?] is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; [?] activate_threads_#t~ret12 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; [?] assume !(0 != activate_threads_~tmp___2~0); [?] havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; [?] assume !(1 == ~t4_pc~0); [?] is_transmit4_triggered_~__retres1~4 := 0; [?] is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; [?] activate_threads_#t~ret13 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; [?] assume !(0 != activate_threads_~tmp___3~0); [?] havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; [?] assume !(1 == ~t5_pc~0); [?] is_transmit5_triggered_~__retres1~5 := 0; [?] is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; [?] activate_threads_#t~ret14 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; [?] assume !(0 != activate_threads_~tmp___4~0); [?] havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; [?] assume !(1 == ~t6_pc~0); [?] is_transmit6_triggered_~__retres1~6 := 0; [?] is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; [?] activate_threads_#t~ret15 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; [?] assume !(0 != activate_threads_~tmp___5~0); [?] assume !(1 == ~M_E~0); [?] assume !(1 == ~T1_E~0); [?] assume !(1 == ~T2_E~0); [?] assume !(1 == ~T3_E~0); [?] assume !(1 == ~T4_E~0); [?] assume !(1 == ~T5_E~0); [?] assume !(1 == ~T6_E~0); [?] assume !(1 == ~E_M~0); [?] assume !(1 == ~E_1~0); [?] assume !(1 == ~E_2~0); [?] assume !(1 == ~E_3~0); [?] assume !(1 == ~E_4~0); [?] assume !(1 == ~E_5~0); [?] assume !(1 == ~E_6~0); [?] assume !false; [?] start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret1, eval_#t~nondet2, eval_~tmp_ndt_1~0, eval_#t~nondet3, eval_~tmp_ndt_2~0, eval_#t~nondet4, eval_~tmp_ndt_3~0, eval_#t~nondet5, eval_~tmp_ndt_4~0, eval_#t~nondet6, eval_~tmp_ndt_5~0, eval_#t~nondet7, eval_~tmp_ndt_6~0, eval_#t~nondet8, eval_~tmp_ndt_7~0, eval_~tmp~0;havoc eval_~tmp~0; [L14] ~m_pc~0 := 0; [L15] ~t1_pc~0 := 0; [L16] ~t2_pc~0 := 0; [L17] ~t3_pc~0 := 0; [L18] ~t4_pc~0 := 0; [L19] ~t5_pc~0 := 0; [L20] ~t6_pc~0 := 0; [L21] ~m_st~0 := 0; [L22] ~t1_st~0 := 0; [L23] ~t2_st~0 := 0; [L24] ~t3_st~0 := 0; [L25] ~t4_st~0 := 0; [L26] ~t5_st~0 := 0; [L27] ~t6_st~0 := 0; [L28] ~m_i~0 := 0; [L29] ~t1_i~0 := 0; [L30] ~t2_i~0 := 0; [L31] ~t3_i~0 := 0; [L32] ~t4_i~0 := 0; [L33] ~t5_i~0 := 0; [L34] ~t6_i~0 := 0; [L35] ~M_E~0 := 2; [L36] ~T1_E~0 := 2; [L37] ~T2_E~0 := 2; [L38] ~T3_E~0 := 2; [L39] ~T4_E~0 := 2; [L40] ~T5_E~0 := 2; [L41] ~T6_E~0 := 2; [L42] ~E_M~0 := 2; [L43] ~E_1~0 := 2; [L44] ~E_2~0 := 2; [L45] ~E_3~0 := 2; [L46] ~E_4~0 := 2; [L47] ~E_5~0 := 2; [L48] ~E_6~0 := 2; [L57] ~token~0 := 0; [L59] ~local~0 := 0; [?] havoc main_#res; [?] havoc main_~__retres1~8; [L1088] havoc main_~__retres1~8; [L998] ~m_i~0 := 1; [L999] ~t1_i~0 := 1; [L1000] ~t2_i~0 := 1; [L1001] ~t3_i~0 := 1; [L1002] ~t4_i~0 := 1; [L1003] ~t5_i~0 := 1; [L1004] ~t6_i~0 := 1; [L1093] havoc start_simulation_#t~ret17, start_simulation_#t~ret18, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1; [L1029] havoc start_simulation_~kernel_st~0; [L1030] havoc start_simulation_~tmp~3; [L1031] havoc start_simulation_~tmp___0~1; [L1035] start_simulation_~kernel_st~0 := 0; [L465-L469] assume 1 == ~m_i~0; [L466] ~m_st~0 := 0; [L470-L474] assume 1 == ~t1_i~0; [L471] ~t1_st~0 := 0; [L475-L479] assume 1 == ~t2_i~0; [L476] ~t2_st~0 := 0; [L480-L484] assume 1 == ~t3_i~0; [L481] ~t3_st~0 := 0; [L485-L489] assume 1 == ~t4_i~0; [L486] ~t4_st~0 := 0; [L490-L494] assume 1 == ~t5_i~0; [L491] ~t5_st~0 := 0; [L495-L499] assume 1 == ~t6_i~0; [L496] ~t6_st~0 := 0; [L674-L678] assume !(0 == ~M_E~0); [L679-L683] assume !(0 == ~T1_E~0); [L684-L688] assume !(0 == ~T2_E~0); [L689-L693] assume !(0 == ~T3_E~0); [L694-L698] assume !(0 == ~T4_E~0); [L699-L703] assume !(0 == ~T5_E~0); [L704-L708] assume !(0 == ~T6_E~0); [L709-L713] assume !(0 == ~E_M~0); [L714-L718] assume !(0 == ~E_1~0); [L719-L723] assume !(0 == ~E_2~0); [L724-L728] assume !(0 == ~E_3~0); [L729-L733] assume !(0 == ~E_4~0); [L734-L738] assume !(0 == ~E_5~0); [L739-L743] assume !(0 == ~E_6~0); [L1039] havoc activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0; [L827] havoc activate_threads_~tmp~1; [L828] havoc activate_threads_~tmp___0~0; [L829] havoc activate_threads_~tmp___1~0; [L830] havoc activate_threads_~tmp___2~0; [L831] havoc activate_threads_~tmp___3~0; [L832] havoc activate_threads_~tmp___4~0; [L833] havoc activate_threads_~tmp___5~0; [L837] havoc is_master_triggered_#res; [L837] havoc is_master_triggered_~__retres1~0; [L321] havoc is_master_triggered_~__retres1~0; [L324-L333] assume !(1 == ~m_pc~0); [L334] is_master_triggered_~__retres1~0 := 0; [L336] is_master_triggered_#res := is_master_triggered_~__retres1~0; [L837] activate_threads_#t~ret9 := is_master_triggered_#res; [L837] activate_threads_~tmp~1 := activate_threads_#t~ret9; [L837] havoc activate_threads_#t~ret9; [L839-L843] assume !(0 != activate_threads_~tmp~1); [L845] havoc is_transmit1_triggered_#res; [L845] havoc is_transmit1_triggered_~__retres1~1; [L340] havoc is_transmit1_triggered_~__retres1~1; [L343-L352] assume !(1 == ~t1_pc~0); [L353] is_transmit1_triggered_~__retres1~1 := 0; [L355] is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; [L845] activate_threads_#t~ret10 := is_transmit1_triggered_#res; [L845] activate_threads_~tmp___0~0 := activate_threads_#t~ret10; [L845] havoc activate_threads_#t~ret10; [L847-L851] assume !(0 != activate_threads_~tmp___0~0); [L853] havoc is_transmit2_triggered_#res; [L853] havoc is_transmit2_triggered_~__retres1~2; [L359] havoc is_transmit2_triggered_~__retres1~2; [L362-L371] assume !(1 == ~t2_pc~0); [L372] is_transmit2_triggered_~__retres1~2 := 0; [L374] is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; [L853] activate_threads_#t~ret11 := is_transmit2_triggered_#res; [L853] activate_threads_~tmp___1~0 := activate_threads_#t~ret11; [L853] havoc activate_threads_#t~ret11; [L855-L859] assume !(0 != activate_threads_~tmp___1~0); [L861] havoc is_transmit3_triggered_#res; [L861] havoc is_transmit3_triggered_~__retres1~3; [L378] havoc is_transmit3_triggered_~__retres1~3; [L381-L390] assume !(1 == ~t3_pc~0); [L391] is_transmit3_triggered_~__retres1~3 := 0; [L393] is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; [L861] activate_threads_#t~ret12 := is_transmit3_triggered_#res; [L861] activate_threads_~tmp___2~0 := activate_threads_#t~ret12; [L861] havoc activate_threads_#t~ret12; [L863-L867] assume !(0 != activate_threads_~tmp___2~0); [L869] havoc is_transmit4_triggered_#res; [L869] havoc is_transmit4_triggered_~__retres1~4; [L397] havoc is_transmit4_triggered_~__retres1~4; [L400-L409] assume !(1 == ~t4_pc~0); [L410] is_transmit4_triggered_~__retres1~4 := 0; [L412] is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; [L869] activate_threads_#t~ret13 := is_transmit4_triggered_#res; [L869] activate_threads_~tmp___3~0 := activate_threads_#t~ret13; [L869] havoc activate_threads_#t~ret13; [L871-L875] assume !(0 != activate_threads_~tmp___3~0); [L877] havoc is_transmit5_triggered_#res; [L877] havoc is_transmit5_triggered_~__retres1~5; [L416] havoc is_transmit5_triggered_~__retres1~5; [L419-L428] assume !(1 == ~t5_pc~0); [L429] is_transmit5_triggered_~__retres1~5 := 0; [L431] is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; [L877] activate_threads_#t~ret14 := is_transmit5_triggered_#res; [L877] activate_threads_~tmp___4~0 := activate_threads_#t~ret14; [L877] havoc activate_threads_#t~ret14; [L879-L883] assume !(0 != activate_threads_~tmp___4~0); [L885] havoc is_transmit6_triggered_#res; [L885] havoc is_transmit6_triggered_~__retres1~6; [L435] havoc is_transmit6_triggered_~__retres1~6; [L438-L447] assume !(1 == ~t6_pc~0); [L448] is_transmit6_triggered_~__retres1~6 := 0; [L450] is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; [L885] activate_threads_#t~ret15 := is_transmit6_triggered_#res; [L885] activate_threads_~tmp___5~0 := activate_threads_#t~ret15; [L885] havoc activate_threads_#t~ret15; [L887-L891] assume !(0 != activate_threads_~tmp___5~0); [L752-L756] assume !(1 == ~M_E~0); [L757-L761] assume !(1 == ~T1_E~0); [L762-L766] assume !(1 == ~T2_E~0); [L767-L771] assume !(1 == ~T3_E~0); [L772-L776] assume !(1 == ~T4_E~0); [L777-L781] assume !(1 == ~T5_E~0); [L782-L786] assume !(1 == ~T6_E~0); [L787-L791] assume !(1 == ~E_M~0); [L792-L796] assume !(1 == ~E_1~0); [L797-L801] assume !(1 == ~E_2~0); [L802-L806] assume !(1 == ~E_3~0); [L807-L811] assume !(1 == ~E_4~0); [L812-L816] assume !(1 == ~E_5~0); [L817-L821] assume !(1 == ~E_6~0); [L1043-L1080] assume !false; [L1046] start_simulation_~kernel_st~0 := 1; [L1047] havoc eval_#t~ret1, eval_#t~nondet2, eval_~tmp_ndt_1~0, eval_#t~nondet3, eval_~tmp_ndt_2~0, eval_#t~nondet4, eval_~tmp_ndt_3~0, eval_#t~nondet5, eval_~tmp_ndt_4~0, eval_#t~nondet6, eval_~tmp_ndt_5~0, eval_#t~nondet7, eval_~tmp_ndt_6~0, eval_#t~nondet8, eval_~tmp_ndt_7~0, eval_~tmp~0; [L551] havoc eval_~tmp~0; ----- ----- class de.uni_freiburg.informatik.ultimate.boogie.preprocessor.BoogiePreprocessorBacktranslator [L14] ~m_pc~0 := 0; [L15] ~t1_pc~0 := 0; [L16] ~t2_pc~0 := 0; [L17] ~t3_pc~0 := 0; [L18] ~t4_pc~0 := 0; [L19] ~t5_pc~0 := 0; [L20] ~t6_pc~0 := 0; [L21] ~m_st~0 := 0; [L22] ~t1_st~0 := 0; [L23] ~t2_st~0 := 0; [L24] ~t3_st~0 := 0; [L25] ~t4_st~0 := 0; [L26] ~t5_st~0 := 0; [L27] ~t6_st~0 := 0; [L28] ~m_i~0 := 0; [L29] ~t1_i~0 := 0; [L30] ~t2_i~0 := 0; [L31] ~t3_i~0 := 0; [L32] ~t4_i~0 := 0; [L33] ~t5_i~0 := 0; [L34] ~t6_i~0 := 0; [L35] ~M_E~0 := 2; [L36] ~T1_E~0 := 2; [L37] ~T2_E~0 := 2; [L38] ~T3_E~0 := 2; [L39] ~T4_E~0 := 2; [L40] ~T5_E~0 := 2; [L41] ~T6_E~0 := 2; [L42] ~E_M~0 := 2; [L43] ~E_1~0 := 2; [L44] ~E_2~0 := 2; [L45] ~E_3~0 := 2; [L46] ~E_4~0 := 2; [L47] ~E_5~0 := 2; [L48] ~E_6~0 := 2; [L57] ~token~0 := 0; [L59] ~local~0 := 0; [?] havoc main_#res; [?] havoc main_~__retres1~8; [L1088] havoc main_~__retres1~8; [L998] ~m_i~0 := 1; [L999] ~t1_i~0 := 1; [L1000] ~t2_i~0 := 1; [L1001] ~t3_i~0 := 1; [L1002] ~t4_i~0 := 1; [L1003] ~t5_i~0 := 1; [L1004] ~t6_i~0 := 1; [L1093] havoc start_simulation_#t~ret17, start_simulation_#t~ret18, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1; [L1029] havoc start_simulation_~kernel_st~0; [L1030] havoc start_simulation_~tmp~3; [L1031] havoc start_simulation_~tmp___0~1; [L1035] start_simulation_~kernel_st~0 := 0; [L465-L469] assume 1 == ~m_i~0; [L466] ~m_st~0 := 0; [L470-L474] assume 1 == ~t1_i~0; [L471] ~t1_st~0 := 0; [L475-L479] assume 1 == ~t2_i~0; [L476] ~t2_st~0 := 0; [L480-L484] assume 1 == ~t3_i~0; [L481] ~t3_st~0 := 0; [L485-L489] assume 1 == ~t4_i~0; [L486] ~t4_st~0 := 0; [L490-L494] assume 1 == ~t5_i~0; [L491] ~t5_st~0 := 0; [L495-L499] assume 1 == ~t6_i~0; [L496] ~t6_st~0 := 0; [L674-L678] assume !(0 == ~M_E~0); [L679-L683] assume !(0 == ~T1_E~0); [L684-L688] assume !(0 == ~T2_E~0); [L689-L693] assume !(0 == ~T3_E~0); [L694-L698] assume !(0 == ~T4_E~0); [L699-L703] assume !(0 == ~T5_E~0); [L704-L708] assume !(0 == ~T6_E~0); [L709-L713] assume !(0 == ~E_M~0); [L714-L718] assume !(0 == ~E_1~0); [L719-L723] assume !(0 == ~E_2~0); [L724-L728] assume !(0 == ~E_3~0); [L729-L733] assume !(0 == ~E_4~0); [L734-L738] assume !(0 == ~E_5~0); [L739-L743] assume !(0 == ~E_6~0); [L1039] havoc activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0; [L827] havoc activate_threads_~tmp~1; [L828] havoc activate_threads_~tmp___0~0; [L829] havoc activate_threads_~tmp___1~0; [L830] havoc activate_threads_~tmp___2~0; [L831] havoc activate_threads_~tmp___3~0; [L832] havoc activate_threads_~tmp___4~0; [L833] havoc activate_threads_~tmp___5~0; [L837] havoc is_master_triggered_#res; [L837] havoc is_master_triggered_~__retres1~0; [L321] havoc is_master_triggered_~__retres1~0; [L324-L333] assume !(1 == ~m_pc~0); [L334] is_master_triggered_~__retres1~0 := 0; [L336] is_master_triggered_#res := is_master_triggered_~__retres1~0; [L837] activate_threads_#t~ret9 := is_master_triggered_#res; [L837] activate_threads_~tmp~1 := activate_threads_#t~ret9; [L837] havoc activate_threads_#t~ret9; [L839-L843] assume !(0 != activate_threads_~tmp~1); [L845] havoc is_transmit1_triggered_#res; [L845] havoc is_transmit1_triggered_~__retres1~1; [L340] havoc is_transmit1_triggered_~__retres1~1; [L343-L352] assume !(1 == ~t1_pc~0); [L353] is_transmit1_triggered_~__retres1~1 := 0; [L355] is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; [L845] activate_threads_#t~ret10 := is_transmit1_triggered_#res; [L845] activate_threads_~tmp___0~0 := activate_threads_#t~ret10; [L845] havoc activate_threads_#t~ret10; [L847-L851] assume !(0 != activate_threads_~tmp___0~0); [L853] havoc is_transmit2_triggered_#res; [L853] havoc is_transmit2_triggered_~__retres1~2; [L359] havoc is_transmit2_triggered_~__retres1~2; [L362-L371] assume !(1 == ~t2_pc~0); [L372] is_transmit2_triggered_~__retres1~2 := 0; [L374] is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; [L853] activate_threads_#t~ret11 := is_transmit2_triggered_#res; [L853] activate_threads_~tmp___1~0 := activate_threads_#t~ret11; [L853] havoc activate_threads_#t~ret11; [L855-L859] assume !(0 != activate_threads_~tmp___1~0); [L861] havoc is_transmit3_triggered_#res; [L861] havoc is_transmit3_triggered_~__retres1~3; [L378] havoc is_transmit3_triggered_~__retres1~3; [L381-L390] assume !(1 == ~t3_pc~0); [L391] is_transmit3_triggered_~__retres1~3 := 0; [L393] is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; [L861] activate_threads_#t~ret12 := is_transmit3_triggered_#res; [L861] activate_threads_~tmp___2~0 := activate_threads_#t~ret12; [L861] havoc activate_threads_#t~ret12; [L863-L867] assume !(0 != activate_threads_~tmp___2~0); [L869] havoc is_transmit4_triggered_#res; [L869] havoc is_transmit4_triggered_~__retres1~4; [L397] havoc is_transmit4_triggered_~__retres1~4; [L400-L409] assume !(1 == ~t4_pc~0); [L410] is_transmit4_triggered_~__retres1~4 := 0; [L412] is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; [L869] activate_threads_#t~ret13 := is_transmit4_triggered_#res; [L869] activate_threads_~tmp___3~0 := activate_threads_#t~ret13; [L869] havoc activate_threads_#t~ret13; [L871-L875] assume !(0 != activate_threads_~tmp___3~0); [L877] havoc is_transmit5_triggered_#res; [L877] havoc is_transmit5_triggered_~__retres1~5; [L416] havoc is_transmit5_triggered_~__retres1~5; [L419-L428] assume !(1 == ~t5_pc~0); [L429] is_transmit5_triggered_~__retres1~5 := 0; [L431] is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; [L877] activate_threads_#t~ret14 := is_transmit5_triggered_#res; [L877] activate_threads_~tmp___4~0 := activate_threads_#t~ret14; [L877] havoc activate_threads_#t~ret14; [L879-L883] assume !(0 != activate_threads_~tmp___4~0); [L885] havoc is_transmit6_triggered_#res; [L885] havoc is_transmit6_triggered_~__retres1~6; [L435] havoc is_transmit6_triggered_~__retres1~6; [L438-L447] assume !(1 == ~t6_pc~0); [L448] is_transmit6_triggered_~__retres1~6 := 0; [L450] is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; [L885] activate_threads_#t~ret15 := is_transmit6_triggered_#res; [L885] activate_threads_~tmp___5~0 := activate_threads_#t~ret15; [L885] havoc activate_threads_#t~ret15; [L887-L891] assume !(0 != activate_threads_~tmp___5~0); [L752-L756] assume !(1 == ~M_E~0); [L757-L761] assume !(1 == ~T1_E~0); [L762-L766] assume !(1 == ~T2_E~0); [L767-L771] assume !(1 == ~T3_E~0); [L772-L776] assume !(1 == ~T4_E~0); [L777-L781] assume !(1 == ~T5_E~0); [L782-L786] assume !(1 == ~T6_E~0); [L787-L791] assume !(1 == ~E_M~0); [L792-L796] assume !(1 == ~E_1~0); [L797-L801] assume !(1 == ~E_2~0); [L802-L806] assume !(1 == ~E_3~0); [L807-L811] assume !(1 == ~E_4~0); [L812-L816] assume !(1 == ~E_5~0); [L817-L821] assume !(1 == ~E_6~0); [L1043-L1080] assume !false; [L1046] start_simulation_~kernel_st~0 := 1; [L1047] havoc eval_#t~ret1, eval_#t~nondet2, eval_~tmp_ndt_1~0, eval_#t~nondet3, eval_~tmp_ndt_2~0, eval_#t~nondet4, eval_~tmp_ndt_3~0, eval_#t~nondet5, eval_~tmp_ndt_4~0, eval_#t~nondet6, eval_~tmp_ndt_5~0, eval_#t~nondet7, eval_~tmp_ndt_6~0, eval_#t~nondet8, eval_~tmp_ndt_7~0, eval_~tmp~0; [L551] havoc eval_~tmp~0; [L14] ~m_pc~0 := 0; [L15] ~t1_pc~0 := 0; [L16] ~t2_pc~0 := 0; [L17] ~t3_pc~0 := 0; [L18] ~t4_pc~0 := 0; [L19] ~t5_pc~0 := 0; [L20] ~t6_pc~0 := 0; [L21] ~m_st~0 := 0; [L22] ~t1_st~0 := 0; [L23] ~t2_st~0 := 0; [L24] ~t3_st~0 := 0; [L25] ~t4_st~0 := 0; [L26] ~t5_st~0 := 0; [L27] ~t6_st~0 := 0; [L28] ~m_i~0 := 0; [L29] ~t1_i~0 := 0; [L30] ~t2_i~0 := 0; [L31] ~t3_i~0 := 0; [L32] ~t4_i~0 := 0; [L33] ~t5_i~0 := 0; [L34] ~t6_i~0 := 0; [L35] ~M_E~0 := 2; [L36] ~T1_E~0 := 2; [L37] ~T2_E~0 := 2; [L38] ~T3_E~0 := 2; [L39] ~T4_E~0 := 2; [L40] ~T5_E~0 := 2; [L41] ~T6_E~0 := 2; [L42] ~E_M~0 := 2; [L43] ~E_1~0 := 2; [L44] ~E_2~0 := 2; [L45] ~E_3~0 := 2; [L46] ~E_4~0 := 2; [L47] ~E_5~0 := 2; [L48] ~E_6~0 := 2; [L57] ~token~0 := 0; [L59] ~local~0 := 0; [?] havoc main_#res; [?] havoc main_~__retres1~8; [L1088] havoc main_~__retres1~8; [L998] ~m_i~0 := 1; [L999] ~t1_i~0 := 1; [L1000] ~t2_i~0 := 1; [L1001] ~t3_i~0 := 1; [L1002] ~t4_i~0 := 1; [L1003] ~t5_i~0 := 1; [L1004] ~t6_i~0 := 1; [L1093] havoc start_simulation_#t~ret17, start_simulation_#t~ret18, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1; [L1029] havoc start_simulation_~kernel_st~0; [L1030] havoc start_simulation_~tmp~3; [L1031] havoc start_simulation_~tmp___0~1; [L1035] start_simulation_~kernel_st~0 := 0; [L465] COND TRUE 1 == ~m_i~0 [L466] ~m_st~0 := 0; [L470] COND TRUE 1 == ~t1_i~0 [L471] ~t1_st~0 := 0; [L475] COND TRUE 1 == ~t2_i~0 [L476] ~t2_st~0 := 0; [L480] COND TRUE 1 == ~t3_i~0 [L481] ~t3_st~0 := 0; [L485] COND TRUE 1 == ~t4_i~0 [L486] ~t4_st~0 := 0; [L490] COND TRUE 1 == ~t5_i~0 [L491] ~t5_st~0 := 0; [L495] COND TRUE 1 == ~t6_i~0 [L496] ~t6_st~0 := 0; [L674] COND FALSE !(0 == ~M_E~0) [L679] COND FALSE !(0 == ~T1_E~0) [L684] COND FALSE !(0 == ~T2_E~0) [L689] COND FALSE !(0 == ~T3_E~0) [L694] COND FALSE !(0 == ~T4_E~0) [L699] COND FALSE !(0 == ~T5_E~0) [L704] COND FALSE !(0 == ~T6_E~0) [L709] COND FALSE !(0 == ~E_M~0) [L714] COND FALSE !(0 == ~E_1~0) [L719] COND FALSE !(0 == ~E_2~0) [L724] COND FALSE !(0 == ~E_3~0) [L729] COND FALSE !(0 == ~E_4~0) [L734] COND FALSE !(0 == ~E_5~0) [L739] COND FALSE !(0 == ~E_6~0) [L1039] havoc activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0; [L827] havoc activate_threads_~tmp~1; [L828] havoc activate_threads_~tmp___0~0; [L829] havoc activate_threads_~tmp___1~0; [L830] havoc activate_threads_~tmp___2~0; [L831] havoc activate_threads_~tmp___3~0; [L832] havoc activate_threads_~tmp___4~0; [L833] havoc activate_threads_~tmp___5~0; [L837] havoc is_master_triggered_#res; [L837] havoc is_master_triggered_~__retres1~0; [L321] havoc is_master_triggered_~__retres1~0; [L324] COND FALSE !(1 == ~m_pc~0) [L334] is_master_triggered_~__retres1~0 := 0; [L336] is_master_triggered_#res := is_master_triggered_~__retres1~0; [L837] activate_threads_#t~ret9 := is_master_triggered_#res; [L837] activate_threads_~tmp~1 := activate_threads_#t~ret9; [L837] havoc activate_threads_#t~ret9; [L839-L843] COND FALSE !(0 != activate_threads_~tmp~1) [L845] havoc is_transmit1_triggered_#res; [L845] havoc is_transmit1_triggered_~__retres1~1; [L340] havoc is_transmit1_triggered_~__retres1~1; [L343] COND FALSE !(1 == ~t1_pc~0) [L353] is_transmit1_triggered_~__retres1~1 := 0; [L355] is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; [L845] activate_threads_#t~ret10 := is_transmit1_triggered_#res; [L845] activate_threads_~tmp___0~0 := activate_threads_#t~ret10; [L845] havoc activate_threads_#t~ret10; [L847-L851] COND FALSE !(0 != activate_threads_~tmp___0~0) [L853] havoc is_transmit2_triggered_#res; [L853] havoc is_transmit2_triggered_~__retres1~2; [L359] havoc is_transmit2_triggered_~__retres1~2; [L362] COND FALSE !(1 == ~t2_pc~0) [L372] is_transmit2_triggered_~__retres1~2 := 0; [L374] is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; [L853] activate_threads_#t~ret11 := is_transmit2_triggered_#res; [L853] activate_threads_~tmp___1~0 := activate_threads_#t~ret11; [L853] havoc activate_threads_#t~ret11; [L855-L859] COND FALSE !(0 != activate_threads_~tmp___1~0) [L861] havoc is_transmit3_triggered_#res; [L861] havoc is_transmit3_triggered_~__retres1~3; [L378] havoc is_transmit3_triggered_~__retres1~3; [L381] COND FALSE !(1 == ~t3_pc~0) [L391] is_transmit3_triggered_~__retres1~3 := 0; [L393] is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; [L861] activate_threads_#t~ret12 := is_transmit3_triggered_#res; [L861] activate_threads_~tmp___2~0 := activate_threads_#t~ret12; [L861] havoc activate_threads_#t~ret12; [L863-L867] COND FALSE !(0 != activate_threads_~tmp___2~0) [L869] havoc is_transmit4_triggered_#res; [L869] havoc is_transmit4_triggered_~__retres1~4; [L397] havoc is_transmit4_triggered_~__retres1~4; [L400] COND FALSE !(1 == ~t4_pc~0) [L410] is_transmit4_triggered_~__retres1~4 := 0; [L412] is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; [L869] activate_threads_#t~ret13 := is_transmit4_triggered_#res; [L869] activate_threads_~tmp___3~0 := activate_threads_#t~ret13; [L869] havoc activate_threads_#t~ret13; [L871-L875] COND FALSE !(0 != activate_threads_~tmp___3~0) [L877] havoc is_transmit5_triggered_#res; [L877] havoc is_transmit5_triggered_~__retres1~5; [L416] havoc is_transmit5_triggered_~__retres1~5; [L419] COND FALSE !(1 == ~t5_pc~0) [L429] is_transmit5_triggered_~__retres1~5 := 0; [L431] is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; [L877] activate_threads_#t~ret14 := is_transmit5_triggered_#res; [L877] activate_threads_~tmp___4~0 := activate_threads_#t~ret14; [L877] havoc activate_threads_#t~ret14; [L879-L883] COND FALSE !(0 != activate_threads_~tmp___4~0) [L885] havoc is_transmit6_triggered_#res; [L885] havoc is_transmit6_triggered_~__retres1~6; [L435] havoc is_transmit6_triggered_~__retres1~6; [L438] COND FALSE !(1 == ~t6_pc~0) [L448] is_transmit6_triggered_~__retres1~6 := 0; [L450] is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; [L885] activate_threads_#t~ret15 := is_transmit6_triggered_#res; [L885] activate_threads_~tmp___5~0 := activate_threads_#t~ret15; [L885] havoc activate_threads_#t~ret15; [L887-L891] COND FALSE !(0 != activate_threads_~tmp___5~0) [L752] COND FALSE !(1 == ~M_E~0) [L757] COND FALSE !(1 == ~T1_E~0) [L762] COND FALSE !(1 == ~T2_E~0) [L767] COND FALSE !(1 == ~T3_E~0) [L772] COND FALSE !(1 == ~T4_E~0) [L777] COND FALSE !(1 == ~T5_E~0) [L782] COND FALSE !(1 == ~T6_E~0) [L787] COND FALSE !(1 == ~E_M~0) [L792] COND FALSE !(1 == ~E_1~0) [L797] COND FALSE !(1 == ~E_2~0) [L802] COND FALSE !(1 == ~E_3~0) [L807] COND FALSE !(1 == ~E_4~0) [L812] COND FALSE !(1 == ~E_5~0) [L817] COND FALSE !(1 == ~E_6~0) [L1043-L1080] COND FALSE !(false) [L1046] start_simulation_~kernel_st~0 := 1; [L1047] havoc eval_#t~ret1, eval_#t~nondet2, eval_~tmp_ndt_1~0, eval_#t~nondet3, eval_~tmp_ndt_2~0, eval_#t~nondet4, eval_~tmp_ndt_3~0, eval_#t~nondet5, eval_~tmp_ndt_4~0, eval_#t~nondet6, eval_~tmp_ndt_5~0, eval_#t~nondet7, eval_~tmp_ndt_6~0, eval_#t~nondet8, eval_~tmp_ndt_7~0, eval_~tmp~0; [L551] havoc eval_~tmp~0; ----- ----- class de.uni_freiburg.informatik.ultimate.boogie.procedureinliner.backtranslation.InlinerBacktranslator [L14] ~m_pc~0 := 0; [L15] ~t1_pc~0 := 0; [L16] ~t2_pc~0 := 0; [L17] ~t3_pc~0 := 0; [L18] ~t4_pc~0 := 0; [L19] ~t5_pc~0 := 0; [L20] ~t6_pc~0 := 0; [L21] ~m_st~0 := 0; [L22] ~t1_st~0 := 0; [L23] ~t2_st~0 := 0; [L24] ~t3_st~0 := 0; [L25] ~t4_st~0 := 0; [L26] ~t5_st~0 := 0; [L27] ~t6_st~0 := 0; [L28] ~m_i~0 := 0; [L29] ~t1_i~0 := 0; [L30] ~t2_i~0 := 0; [L31] ~t3_i~0 := 0; [L32] ~t4_i~0 := 0; [L33] ~t5_i~0 := 0; [L34] ~t6_i~0 := 0; [L35] ~M_E~0 := 2; [L36] ~T1_E~0 := 2; [L37] ~T2_E~0 := 2; [L38] ~T3_E~0 := 2; [L39] ~T4_E~0 := 2; [L40] ~T5_E~0 := 2; [L41] ~T6_E~0 := 2; [L42] ~E_M~0 := 2; [L43] ~E_1~0 := 2; [L44] ~E_2~0 := 2; [L45] ~E_3~0 := 2; [L46] ~E_4~0 := 2; [L47] ~E_5~0 := 2; [L48] ~E_6~0 := 2; [L57] ~token~0 := 0; [L59] ~local~0 := 0; [?] havoc main_#res; [?] havoc main_~__retres1~8; [L1088] havoc main_~__retres1~8; [L998] ~m_i~0 := 1; [L999] ~t1_i~0 := 1; [L1000] ~t2_i~0 := 1; [L1001] ~t3_i~0 := 1; [L1002] ~t4_i~0 := 1; [L1003] ~t5_i~0 := 1; [L1004] ~t6_i~0 := 1; [L1093] havoc start_simulation_#t~ret17, start_simulation_#t~ret18, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1; [L1029] havoc start_simulation_~kernel_st~0; [L1030] havoc start_simulation_~tmp~3; [L1031] havoc start_simulation_~tmp___0~1; [L1035] start_simulation_~kernel_st~0 := 0; [L465] COND TRUE 1 == ~m_i~0 [L466] ~m_st~0 := 0; [L470] COND TRUE 1 == ~t1_i~0 [L471] ~t1_st~0 := 0; [L475] COND TRUE 1 == ~t2_i~0 [L476] ~t2_st~0 := 0; [L480] COND TRUE 1 == ~t3_i~0 [L481] ~t3_st~0 := 0; [L485] COND TRUE 1 == ~t4_i~0 [L486] ~t4_st~0 := 0; [L490] COND TRUE 1 == ~t5_i~0 [L491] ~t5_st~0 := 0; [L495] COND TRUE 1 == ~t6_i~0 [L496] ~t6_st~0 := 0; [L674] COND FALSE !(0 == ~M_E~0) [L679] COND FALSE !(0 == ~T1_E~0) [L684] COND FALSE !(0 == ~T2_E~0) [L689] COND FALSE !(0 == ~T3_E~0) [L694] COND FALSE !(0 == ~T4_E~0) [L699] COND FALSE !(0 == ~T5_E~0) [L704] COND FALSE !(0 == ~T6_E~0) [L709] COND FALSE !(0 == ~E_M~0) [L714] COND FALSE !(0 == ~E_1~0) [L719] COND FALSE !(0 == ~E_2~0) [L724] COND FALSE !(0 == ~E_3~0) [L729] COND FALSE !(0 == ~E_4~0) [L734] COND FALSE !(0 == ~E_5~0) [L739] COND FALSE !(0 == ~E_6~0) [L1039] havoc activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0; [L827] havoc activate_threads_~tmp~1; [L828] havoc activate_threads_~tmp___0~0; [L829] havoc activate_threads_~tmp___1~0; [L830] havoc activate_threads_~tmp___2~0; [L831] havoc activate_threads_~tmp___3~0; [L832] havoc activate_threads_~tmp___4~0; [L833] havoc activate_threads_~tmp___5~0; [L837] havoc is_master_triggered_#res; [L837] havoc is_master_triggered_~__retres1~0; [L321] havoc is_master_triggered_~__retres1~0; [L324] COND FALSE !(1 == ~m_pc~0) [L334] is_master_triggered_~__retres1~0 := 0; [L336] is_master_triggered_#res := is_master_triggered_~__retres1~0; [L837] activate_threads_#t~ret9 := is_master_triggered_#res; [L837] activate_threads_~tmp~1 := activate_threads_#t~ret9; [L837] havoc activate_threads_#t~ret9; [L839-L843] COND FALSE !(0 != activate_threads_~tmp~1) [L845] havoc is_transmit1_triggered_#res; [L845] havoc is_transmit1_triggered_~__retres1~1; [L340] havoc is_transmit1_triggered_~__retres1~1; [L343] COND FALSE !(1 == ~t1_pc~0) [L353] is_transmit1_triggered_~__retres1~1 := 0; [L355] is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; [L845] activate_threads_#t~ret10 := is_transmit1_triggered_#res; [L845] activate_threads_~tmp___0~0 := activate_threads_#t~ret10; [L845] havoc activate_threads_#t~ret10; [L847-L851] COND FALSE !(0 != activate_threads_~tmp___0~0) [L853] havoc is_transmit2_triggered_#res; [L853] havoc is_transmit2_triggered_~__retres1~2; [L359] havoc is_transmit2_triggered_~__retres1~2; [L362] COND FALSE !(1 == ~t2_pc~0) [L372] is_transmit2_triggered_~__retres1~2 := 0; [L374] is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; [L853] activate_threads_#t~ret11 := is_transmit2_triggered_#res; [L853] activate_threads_~tmp___1~0 := activate_threads_#t~ret11; [L853] havoc activate_threads_#t~ret11; [L855-L859] COND FALSE !(0 != activate_threads_~tmp___1~0) [L861] havoc is_transmit3_triggered_#res; [L861] havoc is_transmit3_triggered_~__retres1~3; [L378] havoc is_transmit3_triggered_~__retres1~3; [L381] COND FALSE !(1 == ~t3_pc~0) [L391] is_transmit3_triggered_~__retres1~3 := 0; [L393] is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; [L861] activate_threads_#t~ret12 := is_transmit3_triggered_#res; [L861] activate_threads_~tmp___2~0 := activate_threads_#t~ret12; [L861] havoc activate_threads_#t~ret12; [L863-L867] COND FALSE !(0 != activate_threads_~tmp___2~0) [L869] havoc is_transmit4_triggered_#res; [L869] havoc is_transmit4_triggered_~__retres1~4; [L397] havoc is_transmit4_triggered_~__retres1~4; [L400] COND FALSE !(1 == ~t4_pc~0) [L410] is_transmit4_triggered_~__retres1~4 := 0; [L412] is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; [L869] activate_threads_#t~ret13 := is_transmit4_triggered_#res; [L869] activate_threads_~tmp___3~0 := activate_threads_#t~ret13; [L869] havoc activate_threads_#t~ret13; [L871-L875] COND FALSE !(0 != activate_threads_~tmp___3~0) [L877] havoc is_transmit5_triggered_#res; [L877] havoc is_transmit5_triggered_~__retres1~5; [L416] havoc is_transmit5_triggered_~__retres1~5; [L419] COND FALSE !(1 == ~t5_pc~0) [L429] is_transmit5_triggered_~__retres1~5 := 0; [L431] is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; [L877] activate_threads_#t~ret14 := is_transmit5_triggered_#res; [L877] activate_threads_~tmp___4~0 := activate_threads_#t~ret14; [L877] havoc activate_threads_#t~ret14; [L879-L883] COND FALSE !(0 != activate_threads_~tmp___4~0) [L885] havoc is_transmit6_triggered_#res; [L885] havoc is_transmit6_triggered_~__retres1~6; [L435] havoc is_transmit6_triggered_~__retres1~6; [L438] COND FALSE !(1 == ~t6_pc~0) [L448] is_transmit6_triggered_~__retres1~6 := 0; [L450] is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; [L885] activate_threads_#t~ret15 := is_transmit6_triggered_#res; [L885] activate_threads_~tmp___5~0 := activate_threads_#t~ret15; [L885] havoc activate_threads_#t~ret15; [L887-L891] COND FALSE !(0 != activate_threads_~tmp___5~0) [L752] COND FALSE !(1 == ~M_E~0) [L757] COND FALSE !(1 == ~T1_E~0) [L762] COND FALSE !(1 == ~T2_E~0) [L767] COND FALSE !(1 == ~T3_E~0) [L772] COND FALSE !(1 == ~T4_E~0) [L777] COND FALSE !(1 == ~T5_E~0) [L782] COND FALSE !(1 == ~T6_E~0) [L787] COND FALSE !(1 == ~E_M~0) [L792] COND FALSE !(1 == ~E_1~0) [L797] COND FALSE !(1 == ~E_2~0) [L802] COND FALSE !(1 == ~E_3~0) [L807] COND FALSE !(1 == ~E_4~0) [L812] COND FALSE !(1 == ~E_5~0) [L817] COND FALSE !(1 == ~E_6~0) [L1043-L1080] COND FALSE !(false) [L1046] start_simulation_~kernel_st~0 := 1; [L1047] havoc eval_#t~ret1, eval_#t~nondet2, eval_~tmp_ndt_1~0, eval_#t~nondet3, eval_~tmp_ndt_2~0, eval_#t~nondet4, eval_~tmp_ndt_3~0, eval_#t~nondet5, eval_~tmp_ndt_4~0, eval_#t~nondet6, eval_~tmp_ndt_5~0, eval_#t~nondet7, eval_~tmp_ndt_6~0, eval_#t~nondet8, eval_~tmp_ndt_7~0, eval_~tmp~0; [L551] havoc eval_~tmp~0; [L14] ~m_pc~0 := 0; [L15] ~t1_pc~0 := 0; [L16] ~t2_pc~0 := 0; [L17] ~t3_pc~0 := 0; [L18] ~t4_pc~0 := 0; [L19] ~t5_pc~0 := 0; [L20] ~t6_pc~0 := 0; [L21] ~m_st~0 := 0; [L22] ~t1_st~0 := 0; [L23] ~t2_st~0 := 0; [L24] ~t3_st~0 := 0; [L25] ~t4_st~0 := 0; [L26] ~t5_st~0 := 0; [L27] ~t6_st~0 := 0; [L28] ~m_i~0 := 0; [L29] ~t1_i~0 := 0; [L30] ~t2_i~0 := 0; [L31] ~t3_i~0 := 0; [L32] ~t4_i~0 := 0; [L33] ~t5_i~0 := 0; [L34] ~t6_i~0 := 0; [L35] ~M_E~0 := 2; [L36] ~T1_E~0 := 2; [L37] ~T2_E~0 := 2; [L38] ~T3_E~0 := 2; [L39] ~T4_E~0 := 2; [L40] ~T5_E~0 := 2; [L41] ~T6_E~0 := 2; [L42] ~E_M~0 := 2; [L43] ~E_1~0 := 2; [L44] ~E_2~0 := 2; [L45] ~E_3~0 := 2; [L46] ~E_4~0 := 2; [L47] ~E_5~0 := 2; [L48] ~E_6~0 := 2; [L57] ~token~0 := 0; [L59] ~local~0 := 0; [L1088] havoc ~__retres1~8; [L998] ~m_i~0 := 1; [L999] ~t1_i~0 := 1; [L1000] ~t2_i~0 := 1; [L1001] ~t3_i~0 := 1; [L1002] ~t4_i~0 := 1; [L1003] ~t5_i~0 := 1; [L1004] ~t6_i~0 := 1; [L1029] havoc ~kernel_st~0; [L1030] havoc ~tmp~3; [L1031] havoc ~tmp___0~1; [L1035] ~kernel_st~0 := 0; [L465] COND TRUE 1 == ~m_i~0 [L466] ~m_st~0 := 0; [L470] COND TRUE 1 == ~t1_i~0 [L471] ~t1_st~0 := 0; [L475] COND TRUE 1 == ~t2_i~0 [L476] ~t2_st~0 := 0; [L480] COND TRUE 1 == ~t3_i~0 [L481] ~t3_st~0 := 0; [L485] COND TRUE 1 == ~t4_i~0 [L486] ~t4_st~0 := 0; [L490] COND TRUE 1 == ~t5_i~0 [L491] ~t5_st~0 := 0; [L495] COND TRUE 1 == ~t6_i~0 [L496] ~t6_st~0 := 0; [L674] COND FALSE !(0 == ~M_E~0) [L679] COND FALSE !(0 == ~T1_E~0) [L684] COND FALSE !(0 == ~T2_E~0) [L689] COND FALSE !(0 == ~T3_E~0) [L694] COND FALSE !(0 == ~T4_E~0) [L699] COND FALSE !(0 == ~T5_E~0) [L704] COND FALSE !(0 == ~T6_E~0) [L709] COND FALSE !(0 == ~E_M~0) [L714] COND FALSE !(0 == ~E_1~0) [L719] COND FALSE !(0 == ~E_2~0) [L724] COND FALSE !(0 == ~E_3~0) [L729] COND FALSE !(0 == ~E_4~0) [L734] COND FALSE !(0 == ~E_5~0) [L739] COND FALSE !(0 == ~E_6~0) [L827] havoc ~tmp~1; [L828] havoc ~tmp___0~0; [L829] havoc ~tmp___1~0; [L830] havoc ~tmp___2~0; [L831] havoc ~tmp___3~0; [L832] havoc ~tmp___4~0; [L833] havoc ~tmp___5~0; [L321] havoc ~__retres1~0; [L324] COND FALSE !(1 == ~m_pc~0) [L334] ~__retres1~0 := 0; [L336] #res := ~__retres1~0; [L837] ~tmp~1 := #t~ret9; [L837] havoc #t~ret9; [L839-L843] COND FALSE !(0 != ~tmp~1) [L340] havoc ~__retres1~1; [L343] COND FALSE !(1 == ~t1_pc~0) [L353] ~__retres1~1 := 0; [L355] #res := ~__retres1~1; [L845] ~tmp___0~0 := #t~ret10; [L845] havoc #t~ret10; [L847-L851] COND FALSE !(0 != ~tmp___0~0) [L359] havoc ~__retres1~2; [L362] COND FALSE !(1 == ~t2_pc~0) [L372] ~__retres1~2 := 0; [L374] #res := ~__retres1~2; [L853] ~tmp___1~0 := #t~ret11; [L853] havoc #t~ret11; [L855-L859] COND FALSE !(0 != ~tmp___1~0) [L378] havoc ~__retres1~3; [L381] COND FALSE !(1 == ~t3_pc~0) [L391] ~__retres1~3 := 0; [L393] #res := ~__retres1~3; [L861] ~tmp___2~0 := #t~ret12; [L861] havoc #t~ret12; [L863-L867] COND FALSE !(0 != ~tmp___2~0) [L397] havoc ~__retres1~4; [L400] COND FALSE !(1 == ~t4_pc~0) [L410] ~__retres1~4 := 0; [L412] #res := ~__retres1~4; [L869] ~tmp___3~0 := #t~ret13; [L869] havoc #t~ret13; [L871-L875] COND FALSE !(0 != ~tmp___3~0) [L416] havoc ~__retres1~5; [L419] COND FALSE !(1 == ~t5_pc~0) [L429] ~__retres1~5 := 0; [L431] #res := ~__retres1~5; [L877] ~tmp___4~0 := #t~ret14; [L877] havoc #t~ret14; [L879-L883] COND FALSE !(0 != ~tmp___4~0) [L435] havoc ~__retres1~6; [L438] COND FALSE !(1 == ~t6_pc~0) [L448] ~__retres1~6 := 0; [L450] #res := ~__retres1~6; [L885] ~tmp___5~0 := #t~ret15; [L885] havoc #t~ret15; [L887-L891] COND FALSE !(0 != ~tmp___5~0) [L752] COND FALSE !(1 == ~M_E~0) [L757] COND FALSE !(1 == ~T1_E~0) [L762] COND FALSE !(1 == ~T2_E~0) [L767] COND FALSE !(1 == ~T3_E~0) [L772] COND FALSE !(1 == ~T4_E~0) [L777] COND FALSE !(1 == ~T5_E~0) [L782] COND FALSE !(1 == ~T6_E~0) [L787] COND FALSE !(1 == ~E_M~0) [L792] COND FALSE !(1 == ~E_1~0) [L797] COND FALSE !(1 == ~E_2~0) [L802] COND FALSE !(1 == ~E_3~0) [L807] COND FALSE !(1 == ~E_4~0) [L812] COND FALSE !(1 == ~E_5~0) [L817] COND FALSE !(1 == ~E_6~0) [L1043-L1080] COND FALSE !(false) [L1046] ~kernel_st~0 := 1; [L551] havoc ~tmp~0; ----- ----- class de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.CACSL2BoogieBacktranslator [L14] ~m_pc~0 := 0; [L15] ~t1_pc~0 := 0; [L16] ~t2_pc~0 := 0; [L17] ~t3_pc~0 := 0; [L18] ~t4_pc~0 := 0; [L19] ~t5_pc~0 := 0; [L20] ~t6_pc~0 := 0; [L21] ~m_st~0 := 0; [L22] ~t1_st~0 := 0; [L23] ~t2_st~0 := 0; [L24] ~t3_st~0 := 0; [L25] ~t4_st~0 := 0; [L26] ~t5_st~0 := 0; [L27] ~t6_st~0 := 0; [L28] ~m_i~0 := 0; [L29] ~t1_i~0 := 0; [L30] ~t2_i~0 := 0; [L31] ~t3_i~0 := 0; [L32] ~t4_i~0 := 0; [L33] ~t5_i~0 := 0; [L34] ~t6_i~0 := 0; [L35] ~M_E~0 := 2; [L36] ~T1_E~0 := 2; [L37] ~T2_E~0 := 2; [L38] ~T3_E~0 := 2; [L39] ~T4_E~0 := 2; [L40] ~T5_E~0 := 2; [L41] ~T6_E~0 := 2; [L42] ~E_M~0 := 2; [L43] ~E_1~0 := 2; [L44] ~E_2~0 := 2; [L45] ~E_3~0 := 2; [L46] ~E_4~0 := 2; [L47] ~E_5~0 := 2; [L48] ~E_6~0 := 2; [L57] ~token~0 := 0; [L59] ~local~0 := 0; [L1088] havoc ~__retres1~8; [L998] ~m_i~0 := 1; [L999] ~t1_i~0 := 1; [L1000] ~t2_i~0 := 1; [L1001] ~t3_i~0 := 1; [L1002] ~t4_i~0 := 1; [L1003] ~t5_i~0 := 1; [L1004] ~t6_i~0 := 1; [L1029] havoc ~kernel_st~0; [L1030] havoc ~tmp~3; [L1031] havoc ~tmp___0~1; [L1035] ~kernel_st~0 := 0; [L465] COND TRUE 1 == ~m_i~0 [L466] ~m_st~0 := 0; [L470] COND TRUE 1 == ~t1_i~0 [L471] ~t1_st~0 := 0; [L475] COND TRUE 1 == ~t2_i~0 [L476] ~t2_st~0 := 0; [L480] COND TRUE 1 == ~t3_i~0 [L481] ~t3_st~0 := 0; [L485] COND TRUE 1 == ~t4_i~0 [L486] ~t4_st~0 := 0; [L490] COND TRUE 1 == ~t5_i~0 [L491] ~t5_st~0 := 0; [L495] COND TRUE 1 == ~t6_i~0 [L496] ~t6_st~0 := 0; [L674] COND FALSE !(0 == ~M_E~0) [L679] COND FALSE !(0 == ~T1_E~0) [L684] COND FALSE !(0 == ~T2_E~0) [L689] COND FALSE !(0 == ~T3_E~0) [L694] COND FALSE !(0 == ~T4_E~0) [L699] COND FALSE !(0 == ~T5_E~0) [L704] COND FALSE !(0 == ~T6_E~0) [L709] COND FALSE !(0 == ~E_M~0) [L714] COND FALSE !(0 == ~E_1~0) [L719] COND FALSE !(0 == ~E_2~0) [L724] COND FALSE !(0 == ~E_3~0) [L729] COND FALSE !(0 == ~E_4~0) [L734] COND FALSE !(0 == ~E_5~0) [L739] COND FALSE !(0 == ~E_6~0) [L827] havoc ~tmp~1; [L828] havoc ~tmp___0~0; [L829] havoc ~tmp___1~0; [L830] havoc ~tmp___2~0; [L831] havoc ~tmp___3~0; [L832] havoc ~tmp___4~0; [L833] havoc ~tmp___5~0; [L321] havoc ~__retres1~0; [L324] COND FALSE !(1 == ~m_pc~0) [L334] ~__retres1~0 := 0; [L336] #res := ~__retres1~0; [L837] ~tmp~1 := #t~ret9; [L837] havoc #t~ret9; [L839-L843] COND FALSE !(0 != ~tmp~1) [L340] havoc ~__retres1~1; [L343] COND FALSE !(1 == ~t1_pc~0) [L353] ~__retres1~1 := 0; [L355] #res := ~__retres1~1; [L845] ~tmp___0~0 := #t~ret10; [L845] havoc #t~ret10; [L847-L851] COND FALSE !(0 != ~tmp___0~0) [L359] havoc ~__retres1~2; [L362] COND FALSE !(1 == ~t2_pc~0) [L372] ~__retres1~2 := 0; [L374] #res := ~__retres1~2; [L853] ~tmp___1~0 := #t~ret11; [L853] havoc #t~ret11; [L855-L859] COND FALSE !(0 != ~tmp___1~0) [L378] havoc ~__retres1~3; [L381] COND FALSE !(1 == ~t3_pc~0) [L391] ~__retres1~3 := 0; [L393] #res := ~__retres1~3; [L861] ~tmp___2~0 := #t~ret12; [L861] havoc #t~ret12; [L863-L867] COND FALSE !(0 != ~tmp___2~0) [L397] havoc ~__retres1~4; [L400] COND FALSE !(1 == ~t4_pc~0) [L410] ~__retres1~4 := 0; [L412] #res := ~__retres1~4; [L869] ~tmp___3~0 := #t~ret13; [L869] havoc #t~ret13; [L871-L875] COND FALSE !(0 != ~tmp___3~0) [L416] havoc ~__retres1~5; [L419] COND FALSE !(1 == ~t5_pc~0) [L429] ~__retres1~5 := 0; [L431] #res := ~__retres1~5; [L877] ~tmp___4~0 := #t~ret14; [L877] havoc #t~ret14; [L879-L883] COND FALSE !(0 != ~tmp___4~0) [L435] havoc ~__retres1~6; [L438] COND FALSE !(1 == ~t6_pc~0) [L448] ~__retres1~6 := 0; [L450] #res := ~__retres1~6; [L885] ~tmp___5~0 := #t~ret15; [L885] havoc #t~ret15; [L887-L891] COND FALSE !(0 != ~tmp___5~0) [L752] COND FALSE !(1 == ~M_E~0) [L757] COND FALSE !(1 == ~T1_E~0) [L762] COND FALSE !(1 == ~T2_E~0) [L767] COND FALSE !(1 == ~T3_E~0) [L772] COND FALSE !(1 == ~T4_E~0) [L777] COND FALSE !(1 == ~T5_E~0) [L782] COND FALSE !(1 == ~T6_E~0) [L787] COND FALSE !(1 == ~E_M~0) [L792] COND FALSE !(1 == ~E_1~0) [L797] COND FALSE !(1 == ~E_2~0) [L802] COND FALSE !(1 == ~E_3~0) [L807] COND FALSE !(1 == ~E_4~0) [L812] COND FALSE !(1 == ~E_5~0) [L817] COND FALSE !(1 == ~E_6~0) [L1043-L1080] COND FALSE !(false) [L1046] ~kernel_st~0 := 1; [L551] havoc ~tmp~0; [L14] int m_pc = 0; [L15] int t1_pc = 0; [L16] int t2_pc = 0; [L17] int t3_pc = 0; [L18] int t4_pc = 0; [L19] int t5_pc = 0; [L20] int t6_pc = 0; [L21] int m_st ; [L22] int t1_st ; [L23] int t2_st ; [L24] int t3_st ; [L25] int t4_st ; [L26] int t5_st ; [L27] int t6_st ; [L28] int m_i ; [L29] int t1_i ; [L30] int t2_i ; [L31] int t3_i ; [L32] int t4_i ; [L33] int t5_i ; [L34] int t6_i ; [L35] int M_E = 2; [L36] int T1_E = 2; [L37] int T2_E = 2; [L38] int T3_E = 2; [L39] int T4_E = 2; [L40] int T5_E = 2; [L41] int T6_E = 2; [L42] int E_M = 2; [L43] int E_1 = 2; [L44] int E_2 = 2; [L45] int E_3 = 2; [L46] int E_4 = 2; [L47] int E_5 = 2; [L48] int E_6 = 2; [L57] int token ; [L59] int local ; [L1088] int __retres1 ; [L998] m_i = 1 [L999] t1_i = 1 [L1000] t2_i = 1 [L1001] t3_i = 1 [L1002] t4_i = 1 [L1003] t5_i = 1 [L1004] t6_i = 1 [L1029] int kernel_st ; [L1030] int tmp ; [L1031] int tmp___0 ; [L1035] kernel_st = 0 [L465] COND TRUE m_i == 1 [L466] m_st = 0 [L470] COND TRUE t1_i == 1 [L471] t1_st = 0 [L475] COND TRUE t2_i == 1 [L476] t2_st = 0 [L480] COND TRUE t3_i == 1 [L481] t3_st = 0 [L485] COND TRUE t4_i == 1 [L486] t4_st = 0 [L490] COND TRUE t5_i == 1 [L491] t5_st = 0 [L495] COND TRUE t6_i == 1 [L496] t6_st = 0 [L674] COND FALSE !(M_E == 0) [L679] COND FALSE !(T1_E == 0) [L684] COND FALSE !(T2_E == 0) [L689] COND FALSE !(T3_E == 0) [L694] COND FALSE !(T4_E == 0) [L699] COND FALSE !(T5_E == 0) [L704] COND FALSE !(T6_E == 0) [L709] COND FALSE !(E_M == 0) [L714] COND FALSE !(E_1 == 0) [L719] COND FALSE !(E_2 == 0) [L724] COND FALSE !(E_3 == 0) [L729] COND FALSE !(E_4 == 0) [L734] COND FALSE !(E_5 == 0) [L739] COND FALSE !(E_6 == 0) [L827] int tmp ; [L828] int tmp___0 ; [L829] int tmp___1 ; [L830] int tmp___2 ; [L831] int tmp___3 ; [L832] int tmp___4 ; [L833] int tmp___5 ; [L321] int __retres1 ; [L324] COND FALSE !(m_pc == 1) [L334] __retres1 = 0 [L336] return (__retres1); [L837] tmp = is_master_triggered() [L839] COND FALSE !(\read(tmp)) [L340] int __retres1 ; [L343] COND FALSE !(t1_pc == 1) [L353] __retres1 = 0 [L355] return (__retres1); [L845] tmp___0 = is_transmit1_triggered() [L847] COND FALSE !(\read(tmp___0)) [L359] int __retres1 ; [L362] COND FALSE !(t2_pc == 1) [L372] __retres1 = 0 [L374] return (__retres1); [L853] tmp___1 = is_transmit2_triggered() [L855] COND FALSE !(\read(tmp___1)) [L378] int __retres1 ; [L381] COND FALSE !(t3_pc == 1) [L391] __retres1 = 0 [L393] return (__retres1); [L861] tmp___2 = is_transmit3_triggered() [L863] COND FALSE !(\read(tmp___2)) [L397] int __retres1 ; [L400] COND FALSE !(t4_pc == 1) [L410] __retres1 = 0 [L412] return (__retres1); [L869] tmp___3 = is_transmit4_triggered() [L871] COND FALSE !(\read(tmp___3)) [L416] int __retres1 ; [L419] COND FALSE !(t5_pc == 1) [L429] __retres1 = 0 [L431] return (__retres1); [L877] tmp___4 = is_transmit5_triggered() [L879] COND FALSE !(\read(tmp___4)) [L435] int __retres1 ; [L438] COND FALSE !(t6_pc == 1) [L448] __retres1 = 0 [L450] return (__retres1); [L885] tmp___5 = is_transmit6_triggered() [L887] COND FALSE !(\read(tmp___5)) [L752] COND FALSE !(M_E == 1) [L757] COND FALSE !(T1_E == 1) [L762] COND FALSE !(T2_E == 1) [L767] COND FALSE !(T3_E == 1) [L772] COND FALSE !(T4_E == 1) [L777] COND FALSE !(T5_E == 1) [L782] COND FALSE !(T6_E == 1) [L787] COND FALSE !(E_M == 1) [L792] COND FALSE !(E_1 == 1) [L797] COND FALSE !(E_2 == 1) [L802] COND FALSE !(E_3 == 1) [L807] COND FALSE !(E_4 == 1) [L812] COND FALSE !(E_5 == 1) [L817] COND FALSE !(E_6 == 1) [L1043] COND TRUE 1 [L1046] kernel_st = 1 [L551] int tmp ; ----- ----- class de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder.RCFGBacktranslator [?] assume !false; [?] havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~7;havoc exists_runnable_thread_~__retres1~7; [?] assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7 := 1; [?] exists_runnable_thread_#res := exists_runnable_thread_~__retres1~7; [?] eval_#t~ret1 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret1;havoc eval_#t~ret1; [?] assume 0 != eval_~tmp~0; [?] assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0;eval_~tmp_ndt_1~0 := eval_#t~nondet2;havoc eval_#t~nondet2; [?] assume !(0 != eval_~tmp_ndt_1~0); [?] assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0;eval_~tmp_ndt_2~0 := eval_#t~nondet3;havoc eval_#t~nondet3; [?] assume !(0 != eval_~tmp_ndt_2~0); [?] assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0;eval_~tmp_ndt_3~0 := eval_#t~nondet4;havoc eval_#t~nondet4; [?] assume !(0 != eval_~tmp_ndt_3~0); [?] assume 0 == ~t3_st~0;havoc eval_~tmp_ndt_4~0;eval_~tmp_ndt_4~0 := eval_#t~nondet5;havoc eval_#t~nondet5; [?] assume !(0 != eval_~tmp_ndt_4~0); [?] assume 0 == ~t4_st~0;havoc eval_~tmp_ndt_5~0;eval_~tmp_ndt_5~0 := eval_#t~nondet6;havoc eval_#t~nondet6; [?] assume !(0 != eval_~tmp_ndt_5~0); [?] assume 0 == ~t5_st~0;havoc eval_~tmp_ndt_6~0;eval_~tmp_ndt_6~0 := eval_#t~nondet7;havoc eval_#t~nondet7; [?] assume !(0 != eval_~tmp_ndt_6~0); [?] assume 0 == ~t6_st~0;havoc eval_~tmp_ndt_7~0;eval_~tmp_ndt_7~0 := eval_#t~nondet8;havoc eval_#t~nondet8; [?] assume !(0 != eval_~tmp_ndt_7~0); [L555-L663] assume !false; [L558] havoc exists_runnable_thread_#res; [L558] havoc exists_runnable_thread_~__retres1~7; [L505] havoc exists_runnable_thread_~__retres1~7; [L508-L543] assume 0 == ~m_st~0; [L509] exists_runnable_thread_~__retres1~7 := 1; [L546] exists_runnable_thread_#res := exists_runnable_thread_~__retres1~7; [L558] eval_#t~ret1 := exists_runnable_thread_#res; [L558] eval_~tmp~0 := eval_#t~ret1; [L558] havoc eval_#t~ret1; [L560-L564] assume 0 != eval_~tmp~0; [L565-L578] assume 0 == ~m_st~0; [L566] havoc eval_~tmp_ndt_1~0; [L567] eval_~tmp_ndt_1~0 := eval_#t~nondet2; [L567] havoc eval_#t~nondet2; [L568-L575] assume !(0 != eval_~tmp_ndt_1~0); [L579-L592] assume 0 == ~t1_st~0; [L580] havoc eval_~tmp_ndt_2~0; [L581] eval_~tmp_ndt_2~0 := eval_#t~nondet3; [L581] havoc eval_#t~nondet3; [L582-L589] assume !(0 != eval_~tmp_ndt_2~0); [L593-L606] assume 0 == ~t2_st~0; [L594] havoc eval_~tmp_ndt_3~0; [L595] eval_~tmp_ndt_3~0 := eval_#t~nondet4; [L595] havoc eval_#t~nondet4; [L596-L603] assume !(0 != eval_~tmp_ndt_3~0); [L607-L620] assume 0 == ~t3_st~0; [L608] havoc eval_~tmp_ndt_4~0; [L609] eval_~tmp_ndt_4~0 := eval_#t~nondet5; [L609] havoc eval_#t~nondet5; [L610-L617] assume !(0 != eval_~tmp_ndt_4~0); [L621-L634] assume 0 == ~t4_st~0; [L622] havoc eval_~tmp_ndt_5~0; [L623] eval_~tmp_ndt_5~0 := eval_#t~nondet6; [L623] havoc eval_#t~nondet6; [L624-L631] assume !(0 != eval_~tmp_ndt_5~0); [L635-L648] assume 0 == ~t5_st~0; [L636] havoc eval_~tmp_ndt_6~0; [L637] eval_~tmp_ndt_6~0 := eval_#t~nondet7; [L637] havoc eval_#t~nondet7; [L638-L645] assume !(0 != eval_~tmp_ndt_6~0); [L649-L662] assume 0 == ~t6_st~0; [L650] havoc eval_~tmp_ndt_7~0; [L651] eval_~tmp_ndt_7~0 := eval_#t~nondet8; [L651] havoc eval_#t~nondet8; [L652-L659] assume !(0 != eval_~tmp_ndt_7~0); ----- ----- class de.uni_freiburg.informatik.ultimate.boogie.preprocessor.BoogiePreprocessorBacktranslator [L555-L663] assume !false; [L558] havoc exists_runnable_thread_#res; [L558] havoc exists_runnable_thread_~__retres1~7; [L505] havoc exists_runnable_thread_~__retres1~7; [L508-L543] assume 0 == ~m_st~0; [L509] exists_runnable_thread_~__retres1~7 := 1; [L546] exists_runnable_thread_#res := exists_runnable_thread_~__retres1~7; [L558] eval_#t~ret1 := exists_runnable_thread_#res; [L558] eval_~tmp~0 := eval_#t~ret1; [L558] havoc eval_#t~ret1; [L560-L564] assume 0 != eval_~tmp~0; [L565-L578] assume 0 == ~m_st~0; [L566] havoc eval_~tmp_ndt_1~0; [L567] eval_~tmp_ndt_1~0 := eval_#t~nondet2; [L567] havoc eval_#t~nondet2; [L568-L575] assume !(0 != eval_~tmp_ndt_1~0); [L579-L592] assume 0 == ~t1_st~0; [L580] havoc eval_~tmp_ndt_2~0; [L581] eval_~tmp_ndt_2~0 := eval_#t~nondet3; [L581] havoc eval_#t~nondet3; [L582-L589] assume !(0 != eval_~tmp_ndt_2~0); [L593-L606] assume 0 == ~t2_st~0; [L594] havoc eval_~tmp_ndt_3~0; [L595] eval_~tmp_ndt_3~0 := eval_#t~nondet4; [L595] havoc eval_#t~nondet4; [L596-L603] assume !(0 != eval_~tmp_ndt_3~0); [L607-L620] assume 0 == ~t3_st~0; [L608] havoc eval_~tmp_ndt_4~0; [L609] eval_~tmp_ndt_4~0 := eval_#t~nondet5; [L609] havoc eval_#t~nondet5; [L610-L617] assume !(0 != eval_~tmp_ndt_4~0); [L621-L634] assume 0 == ~t4_st~0; [L622] havoc eval_~tmp_ndt_5~0; [L623] eval_~tmp_ndt_5~0 := eval_#t~nondet6; [L623] havoc eval_#t~nondet6; [L624-L631] assume !(0 != eval_~tmp_ndt_5~0); [L635-L648] assume 0 == ~t5_st~0; [L636] havoc eval_~tmp_ndt_6~0; [L637] eval_~tmp_ndt_6~0 := eval_#t~nondet7; [L637] havoc eval_#t~nondet7; [L638-L645] assume !(0 != eval_~tmp_ndt_6~0); [L649-L662] assume 0 == ~t6_st~0; [L650] havoc eval_~tmp_ndt_7~0; [L651] eval_~tmp_ndt_7~0 := eval_#t~nondet8; [L651] havoc eval_#t~nondet8; [L652-L659] assume !(0 != eval_~tmp_ndt_7~0); [L555-L663] COND FALSE !(false) [L558] havoc exists_runnable_thread_#res; [L558] havoc exists_runnable_thread_~__retres1~7; [L505] havoc exists_runnable_thread_~__retres1~7; [L508] COND TRUE 0 == ~m_st~0 [L509] exists_runnable_thread_~__retres1~7 := 1; [L546] exists_runnable_thread_#res := exists_runnable_thread_~__retres1~7; [L558] eval_#t~ret1 := exists_runnable_thread_#res; [L558] eval_~tmp~0 := eval_#t~ret1; [L558] havoc eval_#t~ret1; [L560-L564] COND TRUE 0 != eval_~tmp~0 [L565] COND TRUE 0 == ~m_st~0 [L566] havoc eval_~tmp_ndt_1~0; [L567] eval_~tmp_ndt_1~0 := eval_#t~nondet2; [L567] havoc eval_#t~nondet2; [L568-L575] COND FALSE !(0 != eval_~tmp_ndt_1~0) [L579] COND TRUE 0 == ~t1_st~0 [L580] havoc eval_~tmp_ndt_2~0; [L581] eval_~tmp_ndt_2~0 := eval_#t~nondet3; [L581] havoc eval_#t~nondet3; [L582-L589] COND FALSE !(0 != eval_~tmp_ndt_2~0) [L593] COND TRUE 0 == ~t2_st~0 [L594] havoc eval_~tmp_ndt_3~0; [L595] eval_~tmp_ndt_3~0 := eval_#t~nondet4; [L595] havoc eval_#t~nondet4; [L596-L603] COND FALSE !(0 != eval_~tmp_ndt_3~0) [L607] COND TRUE 0 == ~t3_st~0 [L608] havoc eval_~tmp_ndt_4~0; [L609] eval_~tmp_ndt_4~0 := eval_#t~nondet5; [L609] havoc eval_#t~nondet5; [L610-L617] COND FALSE !(0 != eval_~tmp_ndt_4~0) [L621] COND TRUE 0 == ~t4_st~0 [L622] havoc eval_~tmp_ndt_5~0; [L623] eval_~tmp_ndt_5~0 := eval_#t~nondet6; [L623] havoc eval_#t~nondet6; [L624-L631] COND FALSE !(0 != eval_~tmp_ndt_5~0) [L635] COND TRUE 0 == ~t5_st~0 [L636] havoc eval_~tmp_ndt_6~0; [L637] eval_~tmp_ndt_6~0 := eval_#t~nondet7; [L637] havoc eval_#t~nondet7; [L638-L645] COND FALSE !(0 != eval_~tmp_ndt_6~0) [L649] COND TRUE 0 == ~t6_st~0 [L650] havoc eval_~tmp_ndt_7~0; [L651] eval_~tmp_ndt_7~0 := eval_#t~nondet8; [L651] havoc eval_#t~nondet8; [L652-L659] COND FALSE !(0 != eval_~tmp_ndt_7~0) ----- ----- class de.uni_freiburg.informatik.ultimate.boogie.procedureinliner.backtranslation.InlinerBacktranslator [L555-L663] COND FALSE !(false) [L558] havoc exists_runnable_thread_#res; [L558] havoc exists_runnable_thread_~__retres1~7; [L505] havoc exists_runnable_thread_~__retres1~7; [L508] COND TRUE 0 == ~m_st~0 [L509] exists_runnable_thread_~__retres1~7 := 1; [L546] exists_runnable_thread_#res := exists_runnable_thread_~__retres1~7; [L558] eval_#t~ret1 := exists_runnable_thread_#res; [L558] eval_~tmp~0 := eval_#t~ret1; [L558] havoc eval_#t~ret1; [L560-L564] COND TRUE 0 != eval_~tmp~0 [L565] COND TRUE 0 == ~m_st~0 [L566] havoc eval_~tmp_ndt_1~0; [L567] eval_~tmp_ndt_1~0 := eval_#t~nondet2; [L567] havoc eval_#t~nondet2; [L568-L575] COND FALSE !(0 != eval_~tmp_ndt_1~0) [L579] COND TRUE 0 == ~t1_st~0 [L580] havoc eval_~tmp_ndt_2~0; [L581] eval_~tmp_ndt_2~0 := eval_#t~nondet3; [L581] havoc eval_#t~nondet3; [L582-L589] COND FALSE !(0 != eval_~tmp_ndt_2~0) [L593] COND TRUE 0 == ~t2_st~0 [L594] havoc eval_~tmp_ndt_3~0; [L595] eval_~tmp_ndt_3~0 := eval_#t~nondet4; [L595] havoc eval_#t~nondet4; [L596-L603] COND FALSE !(0 != eval_~tmp_ndt_3~0) [L607] COND TRUE 0 == ~t3_st~0 [L608] havoc eval_~tmp_ndt_4~0; [L609] eval_~tmp_ndt_4~0 := eval_#t~nondet5; [L609] havoc eval_#t~nondet5; [L610-L617] COND FALSE !(0 != eval_~tmp_ndt_4~0) [L621] COND TRUE 0 == ~t4_st~0 [L622] havoc eval_~tmp_ndt_5~0; [L623] eval_~tmp_ndt_5~0 := eval_#t~nondet6; [L623] havoc eval_#t~nondet6; [L624-L631] COND FALSE !(0 != eval_~tmp_ndt_5~0) [L635] COND TRUE 0 == ~t5_st~0 [L636] havoc eval_~tmp_ndt_6~0; [L637] eval_~tmp_ndt_6~0 := eval_#t~nondet7; [L637] havoc eval_#t~nondet7; [L638-L645] COND FALSE !(0 != eval_~tmp_ndt_6~0) [L649] COND TRUE 0 == ~t6_st~0 [L650] havoc eval_~tmp_ndt_7~0; [L651] eval_~tmp_ndt_7~0 := eval_#t~nondet8; [L651] havoc eval_#t~nondet8; [L652-L659] COND FALSE !(0 != eval_~tmp_ndt_7~0) [L555-L663] COND FALSE !(false) [L505] havoc ~__retres1~7; [L508] COND TRUE 0 == ~m_st~0 [L509] ~__retres1~7 := 1; [L546] #res := ~__retres1~7; [L558] ~tmp~0 := #t~ret1; [L558] havoc #t~ret1; [L560-L564] COND TRUE 0 != ~tmp~0 [L565] COND TRUE 0 == ~m_st~0 [L566] havoc ~tmp_ndt_1~0; [L567] ~tmp_ndt_1~0 := #t~nondet2; [L567] havoc #t~nondet2; [L568-L575] COND FALSE !(0 != ~tmp_ndt_1~0) [L579] COND TRUE 0 == ~t1_st~0 [L580] havoc ~tmp_ndt_2~0; [L581] ~tmp_ndt_2~0 := #t~nondet3; [L581] havoc #t~nondet3; [L582-L589] COND FALSE !(0 != ~tmp_ndt_2~0) [L593] COND TRUE 0 == ~t2_st~0 [L594] havoc ~tmp_ndt_3~0; [L595] ~tmp_ndt_3~0 := #t~nondet4; [L595] havoc #t~nondet4; [L596-L603] COND FALSE !(0 != ~tmp_ndt_3~0) [L607] COND TRUE 0 == ~t3_st~0 [L608] havoc ~tmp_ndt_4~0; [L609] ~tmp_ndt_4~0 := #t~nondet5; [L609] havoc #t~nondet5; [L610-L617] COND FALSE !(0 != ~tmp_ndt_4~0) [L621] COND TRUE 0 == ~t4_st~0 [L622] havoc ~tmp_ndt_5~0; [L623] ~tmp_ndt_5~0 := #t~nondet6; [L623] havoc #t~nondet6; [L624-L631] COND FALSE !(0 != ~tmp_ndt_5~0) [L635] COND TRUE 0 == ~t5_st~0 [L636] havoc ~tmp_ndt_6~0; [L637] ~tmp_ndt_6~0 := #t~nondet7; [L637] havoc #t~nondet7; [L638-L645] COND FALSE !(0 != ~tmp_ndt_6~0) [L649] COND TRUE 0 == ~t6_st~0 [L650] havoc ~tmp_ndt_7~0; [L651] ~tmp_ndt_7~0 := #t~nondet8; [L651] havoc #t~nondet8; [L652-L659] COND FALSE !(0 != ~tmp_ndt_7~0) ----- ----- class de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.CACSL2BoogieBacktranslator [L555-L663] COND FALSE !(false) [L505] havoc ~__retres1~7; [L508] COND TRUE 0 == ~m_st~0 [L509] ~__retres1~7 := 1; [L546] #res := ~__retres1~7; [L558] ~tmp~0 := #t~ret1; [L558] havoc #t~ret1; [L560-L564] COND TRUE 0 != ~tmp~0 [L565] COND TRUE 0 == ~m_st~0 [L566] havoc ~tmp_ndt_1~0; [L567] ~tmp_ndt_1~0 := #t~nondet2; [L567] havoc #t~nondet2; [L568-L575] COND FALSE !(0 != ~tmp_ndt_1~0) [L579] COND TRUE 0 == ~t1_st~0 [L580] havoc ~tmp_ndt_2~0; [L581] ~tmp_ndt_2~0 := #t~nondet3; [L581] havoc #t~nondet3; [L582-L589] COND FALSE !(0 != ~tmp_ndt_2~0) [L593] COND TRUE 0 == ~t2_st~0 [L594] havoc ~tmp_ndt_3~0; [L595] ~tmp_ndt_3~0 := #t~nondet4; [L595] havoc #t~nondet4; [L596-L603] COND FALSE !(0 != ~tmp_ndt_3~0) [L607] COND TRUE 0 == ~t3_st~0 [L608] havoc ~tmp_ndt_4~0; [L609] ~tmp_ndt_4~0 := #t~nondet5; [L609] havoc #t~nondet5; [L610-L617] COND FALSE !(0 != ~tmp_ndt_4~0) [L621] COND TRUE 0 == ~t4_st~0 [L622] havoc ~tmp_ndt_5~0; [L623] ~tmp_ndt_5~0 := #t~nondet6; [L623] havoc #t~nondet6; [L624-L631] COND FALSE !(0 != ~tmp_ndt_5~0) [L635] COND TRUE 0 == ~t5_st~0 [L636] havoc ~tmp_ndt_6~0; [L637] ~tmp_ndt_6~0 := #t~nondet7; [L637] havoc #t~nondet7; [L638-L645] COND FALSE !(0 != ~tmp_ndt_6~0) [L649] COND TRUE 0 == ~t6_st~0 [L650] havoc ~tmp_ndt_7~0; [L651] ~tmp_ndt_7~0 := #t~nondet8; [L651] havoc #t~nondet8; [L652-L659] COND FALSE !(0 != ~tmp_ndt_7~0) [L555] COND TRUE 1 [L505] int __retres1 ; [L508] COND TRUE m_st == 0 [L509] __retres1 = 1 [L546] return (__retres1); [L558] tmp = exists_runnable_thread() [L560] COND TRUE \read(tmp) [L565] COND TRUE m_st == 0 [L566] int tmp_ndt_1; [L567] tmp_ndt_1 = __VERIFIER_nondet_int() [L568] COND FALSE !(\read(tmp_ndt_1)) [L579] COND TRUE t1_st == 0 [L580] int tmp_ndt_2; [L581] tmp_ndt_2 = __VERIFIER_nondet_int() [L582] COND FALSE !(\read(tmp_ndt_2)) [L593] COND TRUE t2_st == 0 [L594] int tmp_ndt_3; [L595] tmp_ndt_3 = __VERIFIER_nondet_int() [L596] COND FALSE !(\read(tmp_ndt_3)) [L607] COND TRUE t3_st == 0 [L608] int tmp_ndt_4; [L609] tmp_ndt_4 = __VERIFIER_nondet_int() [L610] COND FALSE !(\read(tmp_ndt_4)) [L621] COND TRUE t4_st == 0 [L622] int tmp_ndt_5; [L623] tmp_ndt_5 = __VERIFIER_nondet_int() [L624] COND FALSE !(\read(tmp_ndt_5)) [L635] COND TRUE t5_st == 0 [L636] int tmp_ndt_6; [L637] tmp_ndt_6 = __VERIFIER_nondet_int() [L638] COND FALSE !(\read(tmp_ndt_6)) [L649] COND TRUE t6_st == 0 [L650] int tmp_ndt_7; [L651] tmp_ndt_7 = __VERIFIER_nondet_int() [L652] COND FALSE !(\read(tmp_ndt_7)) ----- [2018-11-23 15:00:36,514 INFO L145 WitnessManager]: Wrote witness to /tmp/vcloud-vcloud-master/worker/working_dir_14a495c8-4465-4fa3-a7af-a201bd4dc887/bin-2019/uautomizer/witness.graphml [2018-11-23 15:00:36,514 INFO L132 PluginConnector]: ------------------------ END Witness Printer---------------------------- [2018-11-23 15:00:36,515 INFO L168 Benchmark]: Toolchain (without parser) took 53661.26 ms. Allocated memory was 1.0 GB in the beginning and 6.8 GB in the end (delta: 5.8 GB). Free memory was 963.0 MB in the beginning and 3.3 GB in the end (delta: -2.4 GB). Peak memory consumption was 3.4 GB. Max. memory is 11.5 GB. [2018-11-23 15:00:36,515 INFO L168 Benchmark]: CDTParser took 0.15 ms. Allocated memory is still 1.0 GB. Free memory is still 982.9 MB. There was no memory consumed. Max. memory is 11.5 GB. [2018-11-23 15:00:36,515 INFO L168 Benchmark]: CACSL2BoogieTranslator took 259.42 ms. Allocated memory is still 1.0 GB. Free memory was 963.0 MB in the beginning and 940.5 MB in the end (delta: 22.5 MB). Peak memory consumption was 22.5 MB. Max. memory is 11.5 GB. [2018-11-23 15:00:36,515 INFO L168 Benchmark]: Boogie Procedure Inliner took 97.81 ms. Allocated memory was 1.0 GB in the beginning and 1.2 GB in the end (delta: 148.9 MB). Free memory was 940.5 MB in the beginning and 1.1 GB in the end (delta: -197.5 MB). Peak memory consumption was 15.0 MB. Max. memory is 11.5 GB. [2018-11-23 15:00:36,516 INFO L168 Benchmark]: Boogie Preprocessor took 54.02 ms. Allocated memory is still 1.2 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 5.4 MB). Peak memory consumption was 5.4 MB. Max. memory is 11.5 GB. [2018-11-23 15:00:36,516 INFO L168 Benchmark]: RCFGBuilder took 991.58 ms. Allocated memory is still 1.2 GB. Free memory was 1.1 GB in the beginning and 993.7 MB in the end (delta: 138.8 MB). Peak memory consumption was 138.8 MB. Max. memory is 11.5 GB. [2018-11-23 15:00:36,516 INFO L168 Benchmark]: BuchiAutomizer took 50561.32 ms. Allocated memory was 1.2 GB in the beginning and 6.8 GB in the end (delta: 5.6 GB). Free memory was 993.7 MB in the beginning and 3.3 GB in the end (delta: -2.3 GB). Peak memory consumption was 3.3 GB. Max. memory is 11.5 GB. [2018-11-23 15:00:36,516 INFO L168 Benchmark]: Witness Printer took 1693.70 ms. Allocated memory is still 6.8 GB. Free memory was 3.3 GB in the beginning and 3.3 GB in the end (delta: 72 B). Peak memory consumption was 72 B. Max. memory is 11.5 GB. [2018-11-23 15:00:36,518 INFO L336 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.15 ms. Allocated memory is still 1.0 GB. Free memory is still 982.9 MB. There was no memory consumed. Max. memory is 11.5 GB. * CACSL2BoogieTranslator took 259.42 ms. Allocated memory is still 1.0 GB. Free memory was 963.0 MB in the beginning and 940.5 MB in the end (delta: 22.5 MB). Peak memory consumption was 22.5 MB. Max. memory is 11.5 GB. * Boogie Procedure Inliner took 97.81 ms. Allocated memory was 1.0 GB in the beginning and 1.2 GB in the end (delta: 148.9 MB). Free memory was 940.5 MB in the beginning and 1.1 GB in the end (delta: -197.5 MB). Peak memory consumption was 15.0 MB. Max. memory is 11.5 GB. * Boogie Preprocessor took 54.02 ms. Allocated memory is still 1.2 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 5.4 MB). Peak memory consumption was 5.4 MB. Max. memory is 11.5 GB. * RCFGBuilder took 991.58 ms. Allocated memory is still 1.2 GB. Free memory was 1.1 GB in the beginning and 993.7 MB in the end (delta: 138.8 MB). Peak memory consumption was 138.8 MB. Max. memory is 11.5 GB. * BuchiAutomizer took 50561.32 ms. Allocated memory was 1.2 GB in the beginning and 6.8 GB in the end (delta: 5.6 GB). Free memory was 993.7 MB in the beginning and 3.3 GB in the end (delta: -2.3 GB). Peak memory consumption was 3.3 GB. Max. memory is 11.5 GB. * Witness Printer took 1693.70 ms. Allocated memory is still 6.8 GB. Free memory was 3.3 GB in the beginning and 3.3 GB in the end (delta: 72 B). Peak memory consumption was 72 B. Max. memory is 11.5 GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - StatisticsResult: Constructed decomposition of program Your program was decomposed into 36 terminating modules (35 trivial, 1 deterministic, 0 nondeterministic) and one nonterminating remainder module.One deterministic module has affine ranking function -1 * E_4 + 1 and consists of 3 locations. 35 modules have a trivial ranking function, the largest among these consists of 5 locations. The remainder module has 492475 locations. - StatisticsResult: Timing statistics BüchiAutomizer plugin needed 49.9s and 36 iterations. TraceHistogramMax:2. Analysis of lassos took 6.1s. Construction of modules took 1.5s. Büchi inclusion checks took 5.2s. Highest rank in rank-based complementation 3. Minimization of det autom 25. Minimization of nondet autom 11. Automata minimization 23.5s AutomataMinimizationTime, 36 MinimizatonAttempts, 95111 StatesRemovedByMinimization, 19 NontrivialMinimizations. Non-live state removal took 9.3s Buchi closure took 0.5s. Biggest automaton had 492475 states and ocurred in iteration 35. Nontrivial modules had stage [1, 0, 0, 0, 0]. InterpolantCoveringCapabilityFinite: 0/0 InterpolantCoveringCapabilityBuchi: 0/0 HoareTripleCheckerStatistics: 37035 SDtfs, 40564 SDslu, 33475 SDs, 0 SdLazy, 1139 SolverSat, 520 SolverUnsat, 0 SolverUnknown, 0 SolverNotchecked, 1.5s Time LassoAnalysisResults: nont1 unkn0 SFLI10 SFLT0 conc6 concLT1 SILN1 SILU0 SILI17 SILT0 lasso0 LassoPreprocessingBenchmarks: Lassos: inital246 mio100 ax100 hnf100 lsp4 ukn100 mio100 lsp100 div100 bol100 ite100 ukn100 eq209 hnf86 smp100 dnf189 smp63 tf108 neg92 sie116 LassoTerminationAnalysisBenchmarks: ConstraintsSatisfiability: unsat Degree: 0 Time: 2ms VariablesStem: 0 VariablesLoop: 1 DisjunctsStem: 1 DisjunctsLoop: 2 SupportingInvariants: 0 MotzkinApplications: 4 LassoTerminationAnalysisBenchmarks: LassoNonterminationAnalysisSatFixpoint: 6 LassoNonterminationAnalysisSatUnbounded: 0 LassoNonterminationAnalysisUnsat: 1 LassoNonterminationAnalysisUnknown: 0 LassoNonterminationAnalysisTime: 0.1s - TerminationAnalysisResult: Nontermination possible Buchi Automizer proved that your program is nonterminating for some inputs - FixpointNonTerminationResult [Line: 555]: Nontermination argument in form of an infinite program execution. Nontermination argument in form of an infinite execution State at position 0 is {} State at position 1 is {__retres1=0, t3_st=0, token=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@162a70d3=0, tmp=1, t5_i=1, __retres1=0, kernel_st=1, \result=0, t2_st=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@2cb76587=0, t4_i=1, E_3=2, t4_pc=0, E_5=2, T6_E=2, \result=0, E_1=2, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@4638ea80=0, tmp_ndt_2=0, \result=0, __retres1=0, \result=0, tmp_ndt_4=0, tmp_ndt_6=0, m_st=0, t6_pc=0, tmp___2=0, tmp___0=0, t3_pc=0, tmp=0, __retres1=0, \result=0, t6_i=1, m_pc=0, tmp___4=0, \result=0, __retres1=0, t6_st=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@33d26d86=0, E_6=2, \result=0, __retres1=0, \result=0, T2_E=2, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@32edcda=0, tmp___0=0, t1_pc=0, __retres1=1, t5_st=0, E_2=2, E_4=2, T1_E=2, tmp_ndt_1=0, M_E=2, tmp=0, tmp_ndt_3=0, __retres1=0, T5_E=2, t2_i=1, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@4ebf963a=0, T4_E=2, t3_i=1, t4_st=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@6fc9b60c=0, m_i=1, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@2cbedf2b=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@41da4b23=0, t1_st=0, tmp_ndt_5=0, t5_pc=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@25e92ba8=0, __retres1=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@7328494=0, local=0, t2_pc=0, tmp_ndt_7=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@5d2f4f9d=0, tmp___3=0, E_M=2, tmp___1=0, T3_E=2, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@570f15c8=0, t1_i=1, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@5fd216e4=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@33c95ae8=0, \result=1, tmp___5=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@6de2b9f=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@4d32d59=0} - StatisticsResult: NonterminationArgumentStatistics Fixpoint - NonterminatingLassoResult [Line: 555]: Nonterminating execution ----- class de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder.RCFGBacktranslator [?] ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0; [?] havoc main_#res;havoc main_~__retres1~8;havoc main_~__retres1~8;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; [?] havoc start_simulation_#t~ret17, start_simulation_#t~ret18, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; [?] assume 1 == ~m_i~0;~m_st~0 := 0; [?] assume 1 == ~t1_i~0;~t1_st~0 := 0; [?] assume 1 == ~t2_i~0;~t2_st~0 := 0; [?] assume 1 == ~t3_i~0;~t3_st~0 := 0; [?] assume 1 == ~t4_i~0;~t4_st~0 := 0; [?] assume 1 == ~t5_i~0;~t5_st~0 := 0; [?] assume 1 == ~t6_i~0;~t6_st~0 := 0; [?] assume !(0 == ~M_E~0); [?] assume !(0 == ~T1_E~0); [?] assume !(0 == ~T2_E~0); [?] assume !(0 == ~T3_E~0); [?] assume !(0 == ~T4_E~0); [?] assume !(0 == ~T5_E~0); [?] assume !(0 == ~T6_E~0); [?] assume !(0 == ~E_M~0); [?] assume !(0 == ~E_1~0); [?] assume !(0 == ~E_2~0); [?] assume !(0 == ~E_3~0); [?] assume !(0 == ~E_4~0); [?] assume !(0 == ~E_5~0); [?] assume !(0 == ~E_6~0); [?] havoc activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; [?] assume !(1 == ~m_pc~0); [?] is_master_triggered_~__retres1~0 := 0; [?] is_master_triggered_#res := is_master_triggered_~__retres1~0; [?] activate_threads_#t~ret9 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; [?] assume !(0 != activate_threads_~tmp~1); [?] havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; [?] assume !(1 == ~t1_pc~0); [?] is_transmit1_triggered_~__retres1~1 := 0; [?] is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; [?] activate_threads_#t~ret10 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; [?] assume !(0 != activate_threads_~tmp___0~0); [?] havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; [?] assume !(1 == ~t2_pc~0); [?] is_transmit2_triggered_~__retres1~2 := 0; [?] is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; [?] activate_threads_#t~ret11 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; [?] assume !(0 != activate_threads_~tmp___1~0); [?] havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; [?] assume !(1 == ~t3_pc~0); [?] is_transmit3_triggered_~__retres1~3 := 0; [?] is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; [?] activate_threads_#t~ret12 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; [?] assume !(0 != activate_threads_~tmp___2~0); [?] havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; [?] assume !(1 == ~t4_pc~0); [?] is_transmit4_triggered_~__retres1~4 := 0; [?] is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; [?] activate_threads_#t~ret13 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; [?] assume !(0 != activate_threads_~tmp___3~0); [?] havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; [?] assume !(1 == ~t5_pc~0); [?] is_transmit5_triggered_~__retres1~5 := 0; [?] is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; [?] activate_threads_#t~ret14 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; [?] assume !(0 != activate_threads_~tmp___4~0); [?] havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; [?] assume !(1 == ~t6_pc~0); [?] is_transmit6_triggered_~__retres1~6 := 0; [?] is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; [?] activate_threads_#t~ret15 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; [?] assume !(0 != activate_threads_~tmp___5~0); [?] assume !(1 == ~M_E~0); [?] assume !(1 == ~T1_E~0); [?] assume !(1 == ~T2_E~0); [?] assume !(1 == ~T3_E~0); [?] assume !(1 == ~T4_E~0); [?] assume !(1 == ~T5_E~0); [?] assume !(1 == ~T6_E~0); [?] assume !(1 == ~E_M~0); [?] assume !(1 == ~E_1~0); [?] assume !(1 == ~E_2~0); [?] assume !(1 == ~E_3~0); [?] assume !(1 == ~E_4~0); [?] assume !(1 == ~E_5~0); [?] assume !(1 == ~E_6~0); [?] assume !false; [?] start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret1, eval_#t~nondet2, eval_~tmp_ndt_1~0, eval_#t~nondet3, eval_~tmp_ndt_2~0, eval_#t~nondet4, eval_~tmp_ndt_3~0, eval_#t~nondet5, eval_~tmp_ndt_4~0, eval_#t~nondet6, eval_~tmp_ndt_5~0, eval_#t~nondet7, eval_~tmp_ndt_6~0, eval_#t~nondet8, eval_~tmp_ndt_7~0, eval_~tmp~0;havoc eval_~tmp~0; [L14] ~m_pc~0 := 0; [L15] ~t1_pc~0 := 0; [L16] ~t2_pc~0 := 0; [L17] ~t3_pc~0 := 0; [L18] ~t4_pc~0 := 0; [L19] ~t5_pc~0 := 0; [L20] ~t6_pc~0 := 0; [L21] ~m_st~0 := 0; [L22] ~t1_st~0 := 0; [L23] ~t2_st~0 := 0; [L24] ~t3_st~0 := 0; [L25] ~t4_st~0 := 0; [L26] ~t5_st~0 := 0; [L27] ~t6_st~0 := 0; [L28] ~m_i~0 := 0; [L29] ~t1_i~0 := 0; [L30] ~t2_i~0 := 0; [L31] ~t3_i~0 := 0; [L32] ~t4_i~0 := 0; [L33] ~t5_i~0 := 0; [L34] ~t6_i~0 := 0; [L35] ~M_E~0 := 2; [L36] ~T1_E~0 := 2; [L37] ~T2_E~0 := 2; [L38] ~T3_E~0 := 2; [L39] ~T4_E~0 := 2; [L40] ~T5_E~0 := 2; [L41] ~T6_E~0 := 2; [L42] ~E_M~0 := 2; [L43] ~E_1~0 := 2; [L44] ~E_2~0 := 2; [L45] ~E_3~0 := 2; [L46] ~E_4~0 := 2; [L47] ~E_5~0 := 2; [L48] ~E_6~0 := 2; [L57] ~token~0 := 0; [L59] ~local~0 := 0; [?] havoc main_#res; [?] havoc main_~__retres1~8; [L1088] havoc main_~__retres1~8; [L998] ~m_i~0 := 1; [L999] ~t1_i~0 := 1; [L1000] ~t2_i~0 := 1; [L1001] ~t3_i~0 := 1; [L1002] ~t4_i~0 := 1; [L1003] ~t5_i~0 := 1; [L1004] ~t6_i~0 := 1; [L1093] havoc start_simulation_#t~ret17, start_simulation_#t~ret18, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1; [L1029] havoc start_simulation_~kernel_st~0; [L1030] havoc start_simulation_~tmp~3; [L1031] havoc start_simulation_~tmp___0~1; [L1035] start_simulation_~kernel_st~0 := 0; [L465-L469] assume 1 == ~m_i~0; [L466] ~m_st~0 := 0; [L470-L474] assume 1 == ~t1_i~0; [L471] ~t1_st~0 := 0; [L475-L479] assume 1 == ~t2_i~0; [L476] ~t2_st~0 := 0; [L480-L484] assume 1 == ~t3_i~0; [L481] ~t3_st~0 := 0; [L485-L489] assume 1 == ~t4_i~0; [L486] ~t4_st~0 := 0; [L490-L494] assume 1 == ~t5_i~0; [L491] ~t5_st~0 := 0; [L495-L499] assume 1 == ~t6_i~0; [L496] ~t6_st~0 := 0; [L674-L678] assume !(0 == ~M_E~0); [L679-L683] assume !(0 == ~T1_E~0); [L684-L688] assume !(0 == ~T2_E~0); [L689-L693] assume !(0 == ~T3_E~0); [L694-L698] assume !(0 == ~T4_E~0); [L699-L703] assume !(0 == ~T5_E~0); [L704-L708] assume !(0 == ~T6_E~0); [L709-L713] assume !(0 == ~E_M~0); [L714-L718] assume !(0 == ~E_1~0); [L719-L723] assume !(0 == ~E_2~0); [L724-L728] assume !(0 == ~E_3~0); [L729-L733] assume !(0 == ~E_4~0); [L734-L738] assume !(0 == ~E_5~0); [L739-L743] assume !(0 == ~E_6~0); [L1039] havoc activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0; [L827] havoc activate_threads_~tmp~1; [L828] havoc activate_threads_~tmp___0~0; [L829] havoc activate_threads_~tmp___1~0; [L830] havoc activate_threads_~tmp___2~0; [L831] havoc activate_threads_~tmp___3~0; [L832] havoc activate_threads_~tmp___4~0; [L833] havoc activate_threads_~tmp___5~0; [L837] havoc is_master_triggered_#res; [L837] havoc is_master_triggered_~__retres1~0; [L321] havoc is_master_triggered_~__retres1~0; [L324-L333] assume !(1 == ~m_pc~0); [L334] is_master_triggered_~__retres1~0 := 0; [L336] is_master_triggered_#res := is_master_triggered_~__retres1~0; [L837] activate_threads_#t~ret9 := is_master_triggered_#res; [L837] activate_threads_~tmp~1 := activate_threads_#t~ret9; [L837] havoc activate_threads_#t~ret9; [L839-L843] assume !(0 != activate_threads_~tmp~1); [L845] havoc is_transmit1_triggered_#res; [L845] havoc is_transmit1_triggered_~__retres1~1; [L340] havoc is_transmit1_triggered_~__retres1~1; [L343-L352] assume !(1 == ~t1_pc~0); [L353] is_transmit1_triggered_~__retres1~1 := 0; [L355] is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; [L845] activate_threads_#t~ret10 := is_transmit1_triggered_#res; [L845] activate_threads_~tmp___0~0 := activate_threads_#t~ret10; [L845] havoc activate_threads_#t~ret10; [L847-L851] assume !(0 != activate_threads_~tmp___0~0); [L853] havoc is_transmit2_triggered_#res; [L853] havoc is_transmit2_triggered_~__retres1~2; [L359] havoc is_transmit2_triggered_~__retres1~2; [L362-L371] assume !(1 == ~t2_pc~0); [L372] is_transmit2_triggered_~__retres1~2 := 0; [L374] is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; [L853] activate_threads_#t~ret11 := is_transmit2_triggered_#res; [L853] activate_threads_~tmp___1~0 := activate_threads_#t~ret11; [L853] havoc activate_threads_#t~ret11; [L855-L859] assume !(0 != activate_threads_~tmp___1~0); [L861] havoc is_transmit3_triggered_#res; [L861] havoc is_transmit3_triggered_~__retres1~3; [L378] havoc is_transmit3_triggered_~__retres1~3; [L381-L390] assume !(1 == ~t3_pc~0); [L391] is_transmit3_triggered_~__retres1~3 := 0; [L393] is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; [L861] activate_threads_#t~ret12 := is_transmit3_triggered_#res; [L861] activate_threads_~tmp___2~0 := activate_threads_#t~ret12; [L861] havoc activate_threads_#t~ret12; [L863-L867] assume !(0 != activate_threads_~tmp___2~0); [L869] havoc is_transmit4_triggered_#res; [L869] havoc is_transmit4_triggered_~__retres1~4; [L397] havoc is_transmit4_triggered_~__retres1~4; [L400-L409] assume !(1 == ~t4_pc~0); [L410] is_transmit4_triggered_~__retres1~4 := 0; [L412] is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; [L869] activate_threads_#t~ret13 := is_transmit4_triggered_#res; [L869] activate_threads_~tmp___3~0 := activate_threads_#t~ret13; [L869] havoc activate_threads_#t~ret13; [L871-L875] assume !(0 != activate_threads_~tmp___3~0); [L877] havoc is_transmit5_triggered_#res; [L877] havoc is_transmit5_triggered_~__retres1~5; [L416] havoc is_transmit5_triggered_~__retres1~5; [L419-L428] assume !(1 == ~t5_pc~0); [L429] is_transmit5_triggered_~__retres1~5 := 0; [L431] is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; [L877] activate_threads_#t~ret14 := is_transmit5_triggered_#res; [L877] activate_threads_~tmp___4~0 := activate_threads_#t~ret14; [L877] havoc activate_threads_#t~ret14; [L879-L883] assume !(0 != activate_threads_~tmp___4~0); [L885] havoc is_transmit6_triggered_#res; [L885] havoc is_transmit6_triggered_~__retres1~6; [L435] havoc is_transmit6_triggered_~__retres1~6; [L438-L447] assume !(1 == ~t6_pc~0); [L448] is_transmit6_triggered_~__retres1~6 := 0; [L450] is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; [L885] activate_threads_#t~ret15 := is_transmit6_triggered_#res; [L885] activate_threads_~tmp___5~0 := activate_threads_#t~ret15; [L885] havoc activate_threads_#t~ret15; [L887-L891] assume !(0 != activate_threads_~tmp___5~0); [L752-L756] assume !(1 == ~M_E~0); [L757-L761] assume !(1 == ~T1_E~0); [L762-L766] assume !(1 == ~T2_E~0); [L767-L771] assume !(1 == ~T3_E~0); [L772-L776] assume !(1 == ~T4_E~0); [L777-L781] assume !(1 == ~T5_E~0); [L782-L786] assume !(1 == ~T6_E~0); [L787-L791] assume !(1 == ~E_M~0); [L792-L796] assume !(1 == ~E_1~0); [L797-L801] assume !(1 == ~E_2~0); [L802-L806] assume !(1 == ~E_3~0); [L807-L811] assume !(1 == ~E_4~0); [L812-L816] assume !(1 == ~E_5~0); [L817-L821] assume !(1 == ~E_6~0); [L1043-L1080] assume !false; [L1046] start_simulation_~kernel_st~0 := 1; [L1047] havoc eval_#t~ret1, eval_#t~nondet2, eval_~tmp_ndt_1~0, eval_#t~nondet3, eval_~tmp_ndt_2~0, eval_#t~nondet4, eval_~tmp_ndt_3~0, eval_#t~nondet5, eval_~tmp_ndt_4~0, eval_#t~nondet6, eval_~tmp_ndt_5~0, eval_#t~nondet7, eval_~tmp_ndt_6~0, eval_#t~nondet8, eval_~tmp_ndt_7~0, eval_~tmp~0; [L551] havoc eval_~tmp~0; ----- ----- class de.uni_freiburg.informatik.ultimate.boogie.preprocessor.BoogiePreprocessorBacktranslator [L14] ~m_pc~0 := 0; [L15] ~t1_pc~0 := 0; [L16] ~t2_pc~0 := 0; [L17] ~t3_pc~0 := 0; [L18] ~t4_pc~0 := 0; [L19] ~t5_pc~0 := 0; [L20] ~t6_pc~0 := 0; [L21] ~m_st~0 := 0; [L22] ~t1_st~0 := 0; [L23] ~t2_st~0 := 0; [L24] ~t3_st~0 := 0; [L25] ~t4_st~0 := 0; [L26] ~t5_st~0 := 0; [L27] ~t6_st~0 := 0; [L28] ~m_i~0 := 0; [L29] ~t1_i~0 := 0; [L30] ~t2_i~0 := 0; [L31] ~t3_i~0 := 0; [L32] ~t4_i~0 := 0; [L33] ~t5_i~0 := 0; [L34] ~t6_i~0 := 0; [L35] ~M_E~0 := 2; [L36] ~T1_E~0 := 2; [L37] ~T2_E~0 := 2; [L38] ~T3_E~0 := 2; [L39] ~T4_E~0 := 2; [L40] ~T5_E~0 := 2; [L41] ~T6_E~0 := 2; [L42] ~E_M~0 := 2; [L43] ~E_1~0 := 2; [L44] ~E_2~0 := 2; [L45] ~E_3~0 := 2; [L46] ~E_4~0 := 2; [L47] ~E_5~0 := 2; [L48] ~E_6~0 := 2; [L57] ~token~0 := 0; [L59] ~local~0 := 0; [?] havoc main_#res; [?] havoc main_~__retres1~8; [L1088] havoc main_~__retres1~8; [L998] ~m_i~0 := 1; [L999] ~t1_i~0 := 1; [L1000] ~t2_i~0 := 1; [L1001] ~t3_i~0 := 1; [L1002] ~t4_i~0 := 1; [L1003] ~t5_i~0 := 1; [L1004] ~t6_i~0 := 1; [L1093] havoc start_simulation_#t~ret17, start_simulation_#t~ret18, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1; [L1029] havoc start_simulation_~kernel_st~0; [L1030] havoc start_simulation_~tmp~3; [L1031] havoc start_simulation_~tmp___0~1; [L1035] start_simulation_~kernel_st~0 := 0; [L465-L469] assume 1 == ~m_i~0; [L466] ~m_st~0 := 0; [L470-L474] assume 1 == ~t1_i~0; [L471] ~t1_st~0 := 0; [L475-L479] assume 1 == ~t2_i~0; [L476] ~t2_st~0 := 0; [L480-L484] assume 1 == ~t3_i~0; [L481] ~t3_st~0 := 0; [L485-L489] assume 1 == ~t4_i~0; [L486] ~t4_st~0 := 0; [L490-L494] assume 1 == ~t5_i~0; [L491] ~t5_st~0 := 0; [L495-L499] assume 1 == ~t6_i~0; [L496] ~t6_st~0 := 0; [L674-L678] assume !(0 == ~M_E~0); [L679-L683] assume !(0 == ~T1_E~0); [L684-L688] assume !(0 == ~T2_E~0); [L689-L693] assume !(0 == ~T3_E~0); [L694-L698] assume !(0 == ~T4_E~0); [L699-L703] assume !(0 == ~T5_E~0); [L704-L708] assume !(0 == ~T6_E~0); [L709-L713] assume !(0 == ~E_M~0); [L714-L718] assume !(0 == ~E_1~0); [L719-L723] assume !(0 == ~E_2~0); [L724-L728] assume !(0 == ~E_3~0); [L729-L733] assume !(0 == ~E_4~0); [L734-L738] assume !(0 == ~E_5~0); [L739-L743] assume !(0 == ~E_6~0); [L1039] havoc activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0; [L827] havoc activate_threads_~tmp~1; [L828] havoc activate_threads_~tmp___0~0; [L829] havoc activate_threads_~tmp___1~0; [L830] havoc activate_threads_~tmp___2~0; [L831] havoc activate_threads_~tmp___3~0; [L832] havoc activate_threads_~tmp___4~0; [L833] havoc activate_threads_~tmp___5~0; [L837] havoc is_master_triggered_#res; [L837] havoc is_master_triggered_~__retres1~0; [L321] havoc is_master_triggered_~__retres1~0; [L324-L333] assume !(1 == ~m_pc~0); [L334] is_master_triggered_~__retres1~0 := 0; [L336] is_master_triggered_#res := is_master_triggered_~__retres1~0; [L837] activate_threads_#t~ret9 := is_master_triggered_#res; [L837] activate_threads_~tmp~1 := activate_threads_#t~ret9; [L837] havoc activate_threads_#t~ret9; [L839-L843] assume !(0 != activate_threads_~tmp~1); [L845] havoc is_transmit1_triggered_#res; [L845] havoc is_transmit1_triggered_~__retres1~1; [L340] havoc is_transmit1_triggered_~__retres1~1; [L343-L352] assume !(1 == ~t1_pc~0); [L353] is_transmit1_triggered_~__retres1~1 := 0; [L355] is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; [L845] activate_threads_#t~ret10 := is_transmit1_triggered_#res; [L845] activate_threads_~tmp___0~0 := activate_threads_#t~ret10; [L845] havoc activate_threads_#t~ret10; [L847-L851] assume !(0 != activate_threads_~tmp___0~0); [L853] havoc is_transmit2_triggered_#res; [L853] havoc is_transmit2_triggered_~__retres1~2; [L359] havoc is_transmit2_triggered_~__retres1~2; [L362-L371] assume !(1 == ~t2_pc~0); [L372] is_transmit2_triggered_~__retres1~2 := 0; [L374] is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; [L853] activate_threads_#t~ret11 := is_transmit2_triggered_#res; [L853] activate_threads_~tmp___1~0 := activate_threads_#t~ret11; [L853] havoc activate_threads_#t~ret11; [L855-L859] assume !(0 != activate_threads_~tmp___1~0); [L861] havoc is_transmit3_triggered_#res; [L861] havoc is_transmit3_triggered_~__retres1~3; [L378] havoc is_transmit3_triggered_~__retres1~3; [L381-L390] assume !(1 == ~t3_pc~0); [L391] is_transmit3_triggered_~__retres1~3 := 0; [L393] is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; [L861] activate_threads_#t~ret12 := is_transmit3_triggered_#res; [L861] activate_threads_~tmp___2~0 := activate_threads_#t~ret12; [L861] havoc activate_threads_#t~ret12; [L863-L867] assume !(0 != activate_threads_~tmp___2~0); [L869] havoc is_transmit4_triggered_#res; [L869] havoc is_transmit4_triggered_~__retres1~4; [L397] havoc is_transmit4_triggered_~__retres1~4; [L400-L409] assume !(1 == ~t4_pc~0); [L410] is_transmit4_triggered_~__retres1~4 := 0; [L412] is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; [L869] activate_threads_#t~ret13 := is_transmit4_triggered_#res; [L869] activate_threads_~tmp___3~0 := activate_threads_#t~ret13; [L869] havoc activate_threads_#t~ret13; [L871-L875] assume !(0 != activate_threads_~tmp___3~0); [L877] havoc is_transmit5_triggered_#res; [L877] havoc is_transmit5_triggered_~__retres1~5; [L416] havoc is_transmit5_triggered_~__retres1~5; [L419-L428] assume !(1 == ~t5_pc~0); [L429] is_transmit5_triggered_~__retres1~5 := 0; [L431] is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; [L877] activate_threads_#t~ret14 := is_transmit5_triggered_#res; [L877] activate_threads_~tmp___4~0 := activate_threads_#t~ret14; [L877] havoc activate_threads_#t~ret14; [L879-L883] assume !(0 != activate_threads_~tmp___4~0); [L885] havoc is_transmit6_triggered_#res; [L885] havoc is_transmit6_triggered_~__retres1~6; [L435] havoc is_transmit6_triggered_~__retres1~6; [L438-L447] assume !(1 == ~t6_pc~0); [L448] is_transmit6_triggered_~__retres1~6 := 0; [L450] is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; [L885] activate_threads_#t~ret15 := is_transmit6_triggered_#res; [L885] activate_threads_~tmp___5~0 := activate_threads_#t~ret15; [L885] havoc activate_threads_#t~ret15; [L887-L891] assume !(0 != activate_threads_~tmp___5~0); [L752-L756] assume !(1 == ~M_E~0); [L757-L761] assume !(1 == ~T1_E~0); [L762-L766] assume !(1 == ~T2_E~0); [L767-L771] assume !(1 == ~T3_E~0); [L772-L776] assume !(1 == ~T4_E~0); [L777-L781] assume !(1 == ~T5_E~0); [L782-L786] assume !(1 == ~T6_E~0); [L787-L791] assume !(1 == ~E_M~0); [L792-L796] assume !(1 == ~E_1~0); [L797-L801] assume !(1 == ~E_2~0); [L802-L806] assume !(1 == ~E_3~0); [L807-L811] assume !(1 == ~E_4~0); [L812-L816] assume !(1 == ~E_5~0); [L817-L821] assume !(1 == ~E_6~0); [L1043-L1080] assume !false; [L1046] start_simulation_~kernel_st~0 := 1; [L1047] havoc eval_#t~ret1, eval_#t~nondet2, eval_~tmp_ndt_1~0, eval_#t~nondet3, eval_~tmp_ndt_2~0, eval_#t~nondet4, eval_~tmp_ndt_3~0, eval_#t~nondet5, eval_~tmp_ndt_4~0, eval_#t~nondet6, eval_~tmp_ndt_5~0, eval_#t~nondet7, eval_~tmp_ndt_6~0, eval_#t~nondet8, eval_~tmp_ndt_7~0, eval_~tmp~0; [L551] havoc eval_~tmp~0; [L14] ~m_pc~0 := 0; [L15] ~t1_pc~0 := 0; [L16] ~t2_pc~0 := 0; [L17] ~t3_pc~0 := 0; [L18] ~t4_pc~0 := 0; [L19] ~t5_pc~0 := 0; [L20] ~t6_pc~0 := 0; [L21] ~m_st~0 := 0; [L22] ~t1_st~0 := 0; [L23] ~t2_st~0 := 0; [L24] ~t3_st~0 := 0; [L25] ~t4_st~0 := 0; [L26] ~t5_st~0 := 0; [L27] ~t6_st~0 := 0; [L28] ~m_i~0 := 0; [L29] ~t1_i~0 := 0; [L30] ~t2_i~0 := 0; [L31] ~t3_i~0 := 0; [L32] ~t4_i~0 := 0; [L33] ~t5_i~0 := 0; [L34] ~t6_i~0 := 0; [L35] ~M_E~0 := 2; [L36] ~T1_E~0 := 2; [L37] ~T2_E~0 := 2; [L38] ~T3_E~0 := 2; [L39] ~T4_E~0 := 2; [L40] ~T5_E~0 := 2; [L41] ~T6_E~0 := 2; [L42] ~E_M~0 := 2; [L43] ~E_1~0 := 2; [L44] ~E_2~0 := 2; [L45] ~E_3~0 := 2; [L46] ~E_4~0 := 2; [L47] ~E_5~0 := 2; [L48] ~E_6~0 := 2; [L57] ~token~0 := 0; [L59] ~local~0 := 0; [?] havoc main_#res; [?] havoc main_~__retres1~8; [L1088] havoc main_~__retres1~8; [L998] ~m_i~0 := 1; [L999] ~t1_i~0 := 1; [L1000] ~t2_i~0 := 1; [L1001] ~t3_i~0 := 1; [L1002] ~t4_i~0 := 1; [L1003] ~t5_i~0 := 1; [L1004] ~t6_i~0 := 1; [L1093] havoc start_simulation_#t~ret17, start_simulation_#t~ret18, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1; [L1029] havoc start_simulation_~kernel_st~0; [L1030] havoc start_simulation_~tmp~3; [L1031] havoc start_simulation_~tmp___0~1; [L1035] start_simulation_~kernel_st~0 := 0; [L465] COND TRUE 1 == ~m_i~0 [L466] ~m_st~0 := 0; [L470] COND TRUE 1 == ~t1_i~0 [L471] ~t1_st~0 := 0; [L475] COND TRUE 1 == ~t2_i~0 [L476] ~t2_st~0 := 0; [L480] COND TRUE 1 == ~t3_i~0 [L481] ~t3_st~0 := 0; [L485] COND TRUE 1 == ~t4_i~0 [L486] ~t4_st~0 := 0; [L490] COND TRUE 1 == ~t5_i~0 [L491] ~t5_st~0 := 0; [L495] COND TRUE 1 == ~t6_i~0 [L496] ~t6_st~0 := 0; [L674] COND FALSE !(0 == ~M_E~0) [L679] COND FALSE !(0 == ~T1_E~0) [L684] COND FALSE !(0 == ~T2_E~0) [L689] COND FALSE !(0 == ~T3_E~0) [L694] COND FALSE !(0 == ~T4_E~0) [L699] COND FALSE !(0 == ~T5_E~0) [L704] COND FALSE !(0 == ~T6_E~0) [L709] COND FALSE !(0 == ~E_M~0) [L714] COND FALSE !(0 == ~E_1~0) [L719] COND FALSE !(0 == ~E_2~0) [L724] COND FALSE !(0 == ~E_3~0) [L729] COND FALSE !(0 == ~E_4~0) [L734] COND FALSE !(0 == ~E_5~0) [L739] COND FALSE !(0 == ~E_6~0) [L1039] havoc activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0; [L827] havoc activate_threads_~tmp~1; [L828] havoc activate_threads_~tmp___0~0; [L829] havoc activate_threads_~tmp___1~0; [L830] havoc activate_threads_~tmp___2~0; [L831] havoc activate_threads_~tmp___3~0; [L832] havoc activate_threads_~tmp___4~0; [L833] havoc activate_threads_~tmp___5~0; [L837] havoc is_master_triggered_#res; [L837] havoc is_master_triggered_~__retres1~0; [L321] havoc is_master_triggered_~__retres1~0; [L324] COND FALSE !(1 == ~m_pc~0) [L334] is_master_triggered_~__retres1~0 := 0; [L336] is_master_triggered_#res := is_master_triggered_~__retres1~0; [L837] activate_threads_#t~ret9 := is_master_triggered_#res; [L837] activate_threads_~tmp~1 := activate_threads_#t~ret9; [L837] havoc activate_threads_#t~ret9; [L839-L843] COND FALSE !(0 != activate_threads_~tmp~1) [L845] havoc is_transmit1_triggered_#res; [L845] havoc is_transmit1_triggered_~__retres1~1; [L340] havoc is_transmit1_triggered_~__retres1~1; [L343] COND FALSE !(1 == ~t1_pc~0) [L353] is_transmit1_triggered_~__retres1~1 := 0; [L355] is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; [L845] activate_threads_#t~ret10 := is_transmit1_triggered_#res; [L845] activate_threads_~tmp___0~0 := activate_threads_#t~ret10; [L845] havoc activate_threads_#t~ret10; [L847-L851] COND FALSE !(0 != activate_threads_~tmp___0~0) [L853] havoc is_transmit2_triggered_#res; [L853] havoc is_transmit2_triggered_~__retres1~2; [L359] havoc is_transmit2_triggered_~__retres1~2; [L362] COND FALSE !(1 == ~t2_pc~0) [L372] is_transmit2_triggered_~__retres1~2 := 0; [L374] is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; [L853] activate_threads_#t~ret11 := is_transmit2_triggered_#res; [L853] activate_threads_~tmp___1~0 := activate_threads_#t~ret11; [L853] havoc activate_threads_#t~ret11; [L855-L859] COND FALSE !(0 != activate_threads_~tmp___1~0) [L861] havoc is_transmit3_triggered_#res; [L861] havoc is_transmit3_triggered_~__retres1~3; [L378] havoc is_transmit3_triggered_~__retres1~3; [L381] COND FALSE !(1 == ~t3_pc~0) [L391] is_transmit3_triggered_~__retres1~3 := 0; [L393] is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; [L861] activate_threads_#t~ret12 := is_transmit3_triggered_#res; [L861] activate_threads_~tmp___2~0 := activate_threads_#t~ret12; [L861] havoc activate_threads_#t~ret12; [L863-L867] COND FALSE !(0 != activate_threads_~tmp___2~0) [L869] havoc is_transmit4_triggered_#res; [L869] havoc is_transmit4_triggered_~__retres1~4; [L397] havoc is_transmit4_triggered_~__retres1~4; [L400] COND FALSE !(1 == ~t4_pc~0) [L410] is_transmit4_triggered_~__retres1~4 := 0; [L412] is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; [L869] activate_threads_#t~ret13 := is_transmit4_triggered_#res; [L869] activate_threads_~tmp___3~0 := activate_threads_#t~ret13; [L869] havoc activate_threads_#t~ret13; [L871-L875] COND FALSE !(0 != activate_threads_~tmp___3~0) [L877] havoc is_transmit5_triggered_#res; [L877] havoc is_transmit5_triggered_~__retres1~5; [L416] havoc is_transmit5_triggered_~__retres1~5; [L419] COND FALSE !(1 == ~t5_pc~0) [L429] is_transmit5_triggered_~__retres1~5 := 0; [L431] is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; [L877] activate_threads_#t~ret14 := is_transmit5_triggered_#res; [L877] activate_threads_~tmp___4~0 := activate_threads_#t~ret14; [L877] havoc activate_threads_#t~ret14; [L879-L883] COND FALSE !(0 != activate_threads_~tmp___4~0) [L885] havoc is_transmit6_triggered_#res; [L885] havoc is_transmit6_triggered_~__retres1~6; [L435] havoc is_transmit6_triggered_~__retres1~6; [L438] COND FALSE !(1 == ~t6_pc~0) [L448] is_transmit6_triggered_~__retres1~6 := 0; [L450] is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; [L885] activate_threads_#t~ret15 := is_transmit6_triggered_#res; [L885] activate_threads_~tmp___5~0 := activate_threads_#t~ret15; [L885] havoc activate_threads_#t~ret15; [L887-L891] COND FALSE !(0 != activate_threads_~tmp___5~0) [L752] COND FALSE !(1 == ~M_E~0) [L757] COND FALSE !(1 == ~T1_E~0) [L762] COND FALSE !(1 == ~T2_E~0) [L767] COND FALSE !(1 == ~T3_E~0) [L772] COND FALSE !(1 == ~T4_E~0) [L777] COND FALSE !(1 == ~T5_E~0) [L782] COND FALSE !(1 == ~T6_E~0) [L787] COND FALSE !(1 == ~E_M~0) [L792] COND FALSE !(1 == ~E_1~0) [L797] COND FALSE !(1 == ~E_2~0) [L802] COND FALSE !(1 == ~E_3~0) [L807] COND FALSE !(1 == ~E_4~0) [L812] COND FALSE !(1 == ~E_5~0) [L817] COND FALSE !(1 == ~E_6~0) [L1043-L1080] COND FALSE !(false) [L1046] start_simulation_~kernel_st~0 := 1; [L1047] havoc eval_#t~ret1, eval_#t~nondet2, eval_~tmp_ndt_1~0, eval_#t~nondet3, eval_~tmp_ndt_2~0, eval_#t~nondet4, eval_~tmp_ndt_3~0, eval_#t~nondet5, eval_~tmp_ndt_4~0, eval_#t~nondet6, eval_~tmp_ndt_5~0, eval_#t~nondet7, eval_~tmp_ndt_6~0, eval_#t~nondet8, eval_~tmp_ndt_7~0, eval_~tmp~0; [L551] havoc eval_~tmp~0; ----- ----- class de.uni_freiburg.informatik.ultimate.boogie.procedureinliner.backtranslation.InlinerBacktranslator [L14] ~m_pc~0 := 0; [L15] ~t1_pc~0 := 0; [L16] ~t2_pc~0 := 0; [L17] ~t3_pc~0 := 0; [L18] ~t4_pc~0 := 0; [L19] ~t5_pc~0 := 0; [L20] ~t6_pc~0 := 0; [L21] ~m_st~0 := 0; [L22] ~t1_st~0 := 0; [L23] ~t2_st~0 := 0; [L24] ~t3_st~0 := 0; [L25] ~t4_st~0 := 0; [L26] ~t5_st~0 := 0; [L27] ~t6_st~0 := 0; [L28] ~m_i~0 := 0; [L29] ~t1_i~0 := 0; [L30] ~t2_i~0 := 0; [L31] ~t3_i~0 := 0; [L32] ~t4_i~0 := 0; [L33] ~t5_i~0 := 0; [L34] ~t6_i~0 := 0; [L35] ~M_E~0 := 2; [L36] ~T1_E~0 := 2; [L37] ~T2_E~0 := 2; [L38] ~T3_E~0 := 2; [L39] ~T4_E~0 := 2; [L40] ~T5_E~0 := 2; [L41] ~T6_E~0 := 2; [L42] ~E_M~0 := 2; [L43] ~E_1~0 := 2; [L44] ~E_2~0 := 2; [L45] ~E_3~0 := 2; [L46] ~E_4~0 := 2; [L47] ~E_5~0 := 2; [L48] ~E_6~0 := 2; [L57] ~token~0 := 0; [L59] ~local~0 := 0; [?] havoc main_#res; [?] havoc main_~__retres1~8; [L1088] havoc main_~__retres1~8; [L998] ~m_i~0 := 1; [L999] ~t1_i~0 := 1; [L1000] ~t2_i~0 := 1; [L1001] ~t3_i~0 := 1; [L1002] ~t4_i~0 := 1; [L1003] ~t5_i~0 := 1; [L1004] ~t6_i~0 := 1; [L1093] havoc start_simulation_#t~ret17, start_simulation_#t~ret18, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1; [L1029] havoc start_simulation_~kernel_st~0; [L1030] havoc start_simulation_~tmp~3; [L1031] havoc start_simulation_~tmp___0~1; [L1035] start_simulation_~kernel_st~0 := 0; [L465] COND TRUE 1 == ~m_i~0 [L466] ~m_st~0 := 0; [L470] COND TRUE 1 == ~t1_i~0 [L471] ~t1_st~0 := 0; [L475] COND TRUE 1 == ~t2_i~0 [L476] ~t2_st~0 := 0; [L480] COND TRUE 1 == ~t3_i~0 [L481] ~t3_st~0 := 0; [L485] COND TRUE 1 == ~t4_i~0 [L486] ~t4_st~0 := 0; [L490] COND TRUE 1 == ~t5_i~0 [L491] ~t5_st~0 := 0; [L495] COND TRUE 1 == ~t6_i~0 [L496] ~t6_st~0 := 0; [L674] COND FALSE !(0 == ~M_E~0) [L679] COND FALSE !(0 == ~T1_E~0) [L684] COND FALSE !(0 == ~T2_E~0) [L689] COND FALSE !(0 == ~T3_E~0) [L694] COND FALSE !(0 == ~T4_E~0) [L699] COND FALSE !(0 == ~T5_E~0) [L704] COND FALSE !(0 == ~T6_E~0) [L709] COND FALSE !(0 == ~E_M~0) [L714] COND FALSE !(0 == ~E_1~0) [L719] COND FALSE !(0 == ~E_2~0) [L724] COND FALSE !(0 == ~E_3~0) [L729] COND FALSE !(0 == ~E_4~0) [L734] COND FALSE !(0 == ~E_5~0) [L739] COND FALSE !(0 == ~E_6~0) [L1039] havoc activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0; [L827] havoc activate_threads_~tmp~1; [L828] havoc activate_threads_~tmp___0~0; [L829] havoc activate_threads_~tmp___1~0; [L830] havoc activate_threads_~tmp___2~0; [L831] havoc activate_threads_~tmp___3~0; [L832] havoc activate_threads_~tmp___4~0; [L833] havoc activate_threads_~tmp___5~0; [L837] havoc is_master_triggered_#res; [L837] havoc is_master_triggered_~__retres1~0; [L321] havoc is_master_triggered_~__retres1~0; [L324] COND FALSE !(1 == ~m_pc~0) [L334] is_master_triggered_~__retres1~0 := 0; [L336] is_master_triggered_#res := is_master_triggered_~__retres1~0; [L837] activate_threads_#t~ret9 := is_master_triggered_#res; [L837] activate_threads_~tmp~1 := activate_threads_#t~ret9; [L837] havoc activate_threads_#t~ret9; [L839-L843] COND FALSE !(0 != activate_threads_~tmp~1) [L845] havoc is_transmit1_triggered_#res; [L845] havoc is_transmit1_triggered_~__retres1~1; [L340] havoc is_transmit1_triggered_~__retres1~1; [L343] COND FALSE !(1 == ~t1_pc~0) [L353] is_transmit1_triggered_~__retres1~1 := 0; [L355] is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; [L845] activate_threads_#t~ret10 := is_transmit1_triggered_#res; [L845] activate_threads_~tmp___0~0 := activate_threads_#t~ret10; [L845] havoc activate_threads_#t~ret10; [L847-L851] COND FALSE !(0 != activate_threads_~tmp___0~0) [L853] havoc is_transmit2_triggered_#res; [L853] havoc is_transmit2_triggered_~__retres1~2; [L359] havoc is_transmit2_triggered_~__retres1~2; [L362] COND FALSE !(1 == ~t2_pc~0) [L372] is_transmit2_triggered_~__retres1~2 := 0; [L374] is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; [L853] activate_threads_#t~ret11 := is_transmit2_triggered_#res; [L853] activate_threads_~tmp___1~0 := activate_threads_#t~ret11; [L853] havoc activate_threads_#t~ret11; [L855-L859] COND FALSE !(0 != activate_threads_~tmp___1~0) [L861] havoc is_transmit3_triggered_#res; [L861] havoc is_transmit3_triggered_~__retres1~3; [L378] havoc is_transmit3_triggered_~__retres1~3; [L381] COND FALSE !(1 == ~t3_pc~0) [L391] is_transmit3_triggered_~__retres1~3 := 0; [L393] is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; [L861] activate_threads_#t~ret12 := is_transmit3_triggered_#res; [L861] activate_threads_~tmp___2~0 := activate_threads_#t~ret12; [L861] havoc activate_threads_#t~ret12; [L863-L867] COND FALSE !(0 != activate_threads_~tmp___2~0) [L869] havoc is_transmit4_triggered_#res; [L869] havoc is_transmit4_triggered_~__retres1~4; [L397] havoc is_transmit4_triggered_~__retres1~4; [L400] COND FALSE !(1 == ~t4_pc~0) [L410] is_transmit4_triggered_~__retres1~4 := 0; [L412] is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; [L869] activate_threads_#t~ret13 := is_transmit4_triggered_#res; [L869] activate_threads_~tmp___3~0 := activate_threads_#t~ret13; [L869] havoc activate_threads_#t~ret13; [L871-L875] COND FALSE !(0 != activate_threads_~tmp___3~0) [L877] havoc is_transmit5_triggered_#res; [L877] havoc is_transmit5_triggered_~__retres1~5; [L416] havoc is_transmit5_triggered_~__retres1~5; [L419] COND FALSE !(1 == ~t5_pc~0) [L429] is_transmit5_triggered_~__retres1~5 := 0; [L431] is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; [L877] activate_threads_#t~ret14 := is_transmit5_triggered_#res; [L877] activate_threads_~tmp___4~0 := activate_threads_#t~ret14; [L877] havoc activate_threads_#t~ret14; [L879-L883] COND FALSE !(0 != activate_threads_~tmp___4~0) [L885] havoc is_transmit6_triggered_#res; [L885] havoc is_transmit6_triggered_~__retres1~6; [L435] havoc is_transmit6_triggered_~__retres1~6; [L438] COND FALSE !(1 == ~t6_pc~0) [L448] is_transmit6_triggered_~__retres1~6 := 0; [L450] is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; [L885] activate_threads_#t~ret15 := is_transmit6_triggered_#res; [L885] activate_threads_~tmp___5~0 := activate_threads_#t~ret15; [L885] havoc activate_threads_#t~ret15; [L887-L891] COND FALSE !(0 != activate_threads_~tmp___5~0) [L752] COND FALSE !(1 == ~M_E~0) [L757] COND FALSE !(1 == ~T1_E~0) [L762] COND FALSE !(1 == ~T2_E~0) [L767] COND FALSE !(1 == ~T3_E~0) [L772] COND FALSE !(1 == ~T4_E~0) [L777] COND FALSE !(1 == ~T5_E~0) [L782] COND FALSE !(1 == ~T6_E~0) [L787] COND FALSE !(1 == ~E_M~0) [L792] COND FALSE !(1 == ~E_1~0) [L797] COND FALSE !(1 == ~E_2~0) [L802] COND FALSE !(1 == ~E_3~0) [L807] COND FALSE !(1 == ~E_4~0) [L812] COND FALSE !(1 == ~E_5~0) [L817] COND FALSE !(1 == ~E_6~0) [L1043-L1080] COND FALSE !(false) [L1046] start_simulation_~kernel_st~0 := 1; [L1047] havoc eval_#t~ret1, eval_#t~nondet2, eval_~tmp_ndt_1~0, eval_#t~nondet3, eval_~tmp_ndt_2~0, eval_#t~nondet4, eval_~tmp_ndt_3~0, eval_#t~nondet5, eval_~tmp_ndt_4~0, eval_#t~nondet6, eval_~tmp_ndt_5~0, eval_#t~nondet7, eval_~tmp_ndt_6~0, eval_#t~nondet8, eval_~tmp_ndt_7~0, eval_~tmp~0; [L551] havoc eval_~tmp~0; [L14] ~m_pc~0 := 0; [L15] ~t1_pc~0 := 0; [L16] ~t2_pc~0 := 0; [L17] ~t3_pc~0 := 0; [L18] ~t4_pc~0 := 0; [L19] ~t5_pc~0 := 0; [L20] ~t6_pc~0 := 0; [L21] ~m_st~0 := 0; [L22] ~t1_st~0 := 0; [L23] ~t2_st~0 := 0; [L24] ~t3_st~0 := 0; [L25] ~t4_st~0 := 0; [L26] ~t5_st~0 := 0; [L27] ~t6_st~0 := 0; [L28] ~m_i~0 := 0; [L29] ~t1_i~0 := 0; [L30] ~t2_i~0 := 0; [L31] ~t3_i~0 := 0; [L32] ~t4_i~0 := 0; [L33] ~t5_i~0 := 0; [L34] ~t6_i~0 := 0; [L35] ~M_E~0 := 2; [L36] ~T1_E~0 := 2; [L37] ~T2_E~0 := 2; [L38] ~T3_E~0 := 2; [L39] ~T4_E~0 := 2; [L40] ~T5_E~0 := 2; [L41] ~T6_E~0 := 2; [L42] ~E_M~0 := 2; [L43] ~E_1~0 := 2; [L44] ~E_2~0 := 2; [L45] ~E_3~0 := 2; [L46] ~E_4~0 := 2; [L47] ~E_5~0 := 2; [L48] ~E_6~0 := 2; [L57] ~token~0 := 0; [L59] ~local~0 := 0; [L1088] havoc ~__retres1~8; [L998] ~m_i~0 := 1; [L999] ~t1_i~0 := 1; [L1000] ~t2_i~0 := 1; [L1001] ~t3_i~0 := 1; [L1002] ~t4_i~0 := 1; [L1003] ~t5_i~0 := 1; [L1004] ~t6_i~0 := 1; [L1029] havoc ~kernel_st~0; [L1030] havoc ~tmp~3; [L1031] havoc ~tmp___0~1; [L1035] ~kernel_st~0 := 0; [L465] COND TRUE 1 == ~m_i~0 [L466] ~m_st~0 := 0; [L470] COND TRUE 1 == ~t1_i~0 [L471] ~t1_st~0 := 0; [L475] COND TRUE 1 == ~t2_i~0 [L476] ~t2_st~0 := 0; [L480] COND TRUE 1 == ~t3_i~0 [L481] ~t3_st~0 := 0; [L485] COND TRUE 1 == ~t4_i~0 [L486] ~t4_st~0 := 0; [L490] COND TRUE 1 == ~t5_i~0 [L491] ~t5_st~0 := 0; [L495] COND TRUE 1 == ~t6_i~0 [L496] ~t6_st~0 := 0; [L674] COND FALSE !(0 == ~M_E~0) [L679] COND FALSE !(0 == ~T1_E~0) [L684] COND FALSE !(0 == ~T2_E~0) [L689] COND FALSE !(0 == ~T3_E~0) [L694] COND FALSE !(0 == ~T4_E~0) [L699] COND FALSE !(0 == ~T5_E~0) [L704] COND FALSE !(0 == ~T6_E~0) [L709] COND FALSE !(0 == ~E_M~0) [L714] COND FALSE !(0 == ~E_1~0) [L719] COND FALSE !(0 == ~E_2~0) [L724] COND FALSE !(0 == ~E_3~0) [L729] COND FALSE !(0 == ~E_4~0) [L734] COND FALSE !(0 == ~E_5~0) [L739] COND FALSE !(0 == ~E_6~0) [L827] havoc ~tmp~1; [L828] havoc ~tmp___0~0; [L829] havoc ~tmp___1~0; [L830] havoc ~tmp___2~0; [L831] havoc ~tmp___3~0; [L832] havoc ~tmp___4~0; [L833] havoc ~tmp___5~0; [L321] havoc ~__retres1~0; [L324] COND FALSE !(1 == ~m_pc~0) [L334] ~__retres1~0 := 0; [L336] #res := ~__retres1~0; [L837] ~tmp~1 := #t~ret9; [L837] havoc #t~ret9; [L839-L843] COND FALSE !(0 != ~tmp~1) [L340] havoc ~__retres1~1; [L343] COND FALSE !(1 == ~t1_pc~0) [L353] ~__retres1~1 := 0; [L355] #res := ~__retres1~1; [L845] ~tmp___0~0 := #t~ret10; [L845] havoc #t~ret10; [L847-L851] COND FALSE !(0 != ~tmp___0~0) [L359] havoc ~__retres1~2; [L362] COND FALSE !(1 == ~t2_pc~0) [L372] ~__retres1~2 := 0; [L374] #res := ~__retres1~2; [L853] ~tmp___1~0 := #t~ret11; [L853] havoc #t~ret11; [L855-L859] COND FALSE !(0 != ~tmp___1~0) [L378] havoc ~__retres1~3; [L381] COND FALSE !(1 == ~t3_pc~0) [L391] ~__retres1~3 := 0; [L393] #res := ~__retres1~3; [L861] ~tmp___2~0 := #t~ret12; [L861] havoc #t~ret12; [L863-L867] COND FALSE !(0 != ~tmp___2~0) [L397] havoc ~__retres1~4; [L400] COND FALSE !(1 == ~t4_pc~0) [L410] ~__retres1~4 := 0; [L412] #res := ~__retres1~4; [L869] ~tmp___3~0 := #t~ret13; [L869] havoc #t~ret13; [L871-L875] COND FALSE !(0 != ~tmp___3~0) [L416] havoc ~__retres1~5; [L419] COND FALSE !(1 == ~t5_pc~0) [L429] ~__retres1~5 := 0; [L431] #res := ~__retres1~5; [L877] ~tmp___4~0 := #t~ret14; [L877] havoc #t~ret14; [L879-L883] COND FALSE !(0 != ~tmp___4~0) [L435] havoc ~__retres1~6; [L438] COND FALSE !(1 == ~t6_pc~0) [L448] ~__retres1~6 := 0; [L450] #res := ~__retres1~6; [L885] ~tmp___5~0 := #t~ret15; [L885] havoc #t~ret15; [L887-L891] COND FALSE !(0 != ~tmp___5~0) [L752] COND FALSE !(1 == ~M_E~0) [L757] COND FALSE !(1 == ~T1_E~0) [L762] COND FALSE !(1 == ~T2_E~0) [L767] COND FALSE !(1 == ~T3_E~0) [L772] COND FALSE !(1 == ~T4_E~0) [L777] COND FALSE !(1 == ~T5_E~0) [L782] COND FALSE !(1 == ~T6_E~0) [L787] COND FALSE !(1 == ~E_M~0) [L792] COND FALSE !(1 == ~E_1~0) [L797] COND FALSE !(1 == ~E_2~0) [L802] COND FALSE !(1 == ~E_3~0) [L807] COND FALSE !(1 == ~E_4~0) [L812] COND FALSE !(1 == ~E_5~0) [L817] COND FALSE !(1 == ~E_6~0) [L1043-L1080] COND FALSE !(false) [L1046] ~kernel_st~0 := 1; [L551] havoc ~tmp~0; ----- ----- class de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.CACSL2BoogieBacktranslator [L14] ~m_pc~0 := 0; [L15] ~t1_pc~0 := 0; [L16] ~t2_pc~0 := 0; [L17] ~t3_pc~0 := 0; [L18] ~t4_pc~0 := 0; [L19] ~t5_pc~0 := 0; [L20] ~t6_pc~0 := 0; [L21] ~m_st~0 := 0; [L22] ~t1_st~0 := 0; [L23] ~t2_st~0 := 0; [L24] ~t3_st~0 := 0; [L25] ~t4_st~0 := 0; [L26] ~t5_st~0 := 0; [L27] ~t6_st~0 := 0; [L28] ~m_i~0 := 0; [L29] ~t1_i~0 := 0; [L30] ~t2_i~0 := 0; [L31] ~t3_i~0 := 0; [L32] ~t4_i~0 := 0; [L33] ~t5_i~0 := 0; [L34] ~t6_i~0 := 0; [L35] ~M_E~0 := 2; [L36] ~T1_E~0 := 2; [L37] ~T2_E~0 := 2; [L38] ~T3_E~0 := 2; [L39] ~T4_E~0 := 2; [L40] ~T5_E~0 := 2; [L41] ~T6_E~0 := 2; [L42] ~E_M~0 := 2; [L43] ~E_1~0 := 2; [L44] ~E_2~0 := 2; [L45] ~E_3~0 := 2; [L46] ~E_4~0 := 2; [L47] ~E_5~0 := 2; [L48] ~E_6~0 := 2; [L57] ~token~0 := 0; [L59] ~local~0 := 0; [L1088] havoc ~__retres1~8; [L998] ~m_i~0 := 1; [L999] ~t1_i~0 := 1; [L1000] ~t2_i~0 := 1; [L1001] ~t3_i~0 := 1; [L1002] ~t4_i~0 := 1; [L1003] ~t5_i~0 := 1; [L1004] ~t6_i~0 := 1; [L1029] havoc ~kernel_st~0; [L1030] havoc ~tmp~3; [L1031] havoc ~tmp___0~1; [L1035] ~kernel_st~0 := 0; [L465] COND TRUE 1 == ~m_i~0 [L466] ~m_st~0 := 0; [L470] COND TRUE 1 == ~t1_i~0 [L471] ~t1_st~0 := 0; [L475] COND TRUE 1 == ~t2_i~0 [L476] ~t2_st~0 := 0; [L480] COND TRUE 1 == ~t3_i~0 [L481] ~t3_st~0 := 0; [L485] COND TRUE 1 == ~t4_i~0 [L486] ~t4_st~0 := 0; [L490] COND TRUE 1 == ~t5_i~0 [L491] ~t5_st~0 := 0; [L495] COND TRUE 1 == ~t6_i~0 [L496] ~t6_st~0 := 0; [L674] COND FALSE !(0 == ~M_E~0) [L679] COND FALSE !(0 == ~T1_E~0) [L684] COND FALSE !(0 == ~T2_E~0) [L689] COND FALSE !(0 == ~T3_E~0) [L694] COND FALSE !(0 == ~T4_E~0) [L699] COND FALSE !(0 == ~T5_E~0) [L704] COND FALSE !(0 == ~T6_E~0) [L709] COND FALSE !(0 == ~E_M~0) [L714] COND FALSE !(0 == ~E_1~0) [L719] COND FALSE !(0 == ~E_2~0) [L724] COND FALSE !(0 == ~E_3~0) [L729] COND FALSE !(0 == ~E_4~0) [L734] COND FALSE !(0 == ~E_5~0) [L739] COND FALSE !(0 == ~E_6~0) [L827] havoc ~tmp~1; [L828] havoc ~tmp___0~0; [L829] havoc ~tmp___1~0; [L830] havoc ~tmp___2~0; [L831] havoc ~tmp___3~0; [L832] havoc ~tmp___4~0; [L833] havoc ~tmp___5~0; [L321] havoc ~__retres1~0; [L324] COND FALSE !(1 == ~m_pc~0) [L334] ~__retres1~0 := 0; [L336] #res := ~__retres1~0; [L837] ~tmp~1 := #t~ret9; [L837] havoc #t~ret9; [L839-L843] COND FALSE !(0 != ~tmp~1) [L340] havoc ~__retres1~1; [L343] COND FALSE !(1 == ~t1_pc~0) [L353] ~__retres1~1 := 0; [L355] #res := ~__retres1~1; [L845] ~tmp___0~0 := #t~ret10; [L845] havoc #t~ret10; [L847-L851] COND FALSE !(0 != ~tmp___0~0) [L359] havoc ~__retres1~2; [L362] COND FALSE !(1 == ~t2_pc~0) [L372] ~__retres1~2 := 0; [L374] #res := ~__retres1~2; [L853] ~tmp___1~0 := #t~ret11; [L853] havoc #t~ret11; [L855-L859] COND FALSE !(0 != ~tmp___1~0) [L378] havoc ~__retres1~3; [L381] COND FALSE !(1 == ~t3_pc~0) [L391] ~__retres1~3 := 0; [L393] #res := ~__retres1~3; [L861] ~tmp___2~0 := #t~ret12; [L861] havoc #t~ret12; [L863-L867] COND FALSE !(0 != ~tmp___2~0) [L397] havoc ~__retres1~4; [L400] COND FALSE !(1 == ~t4_pc~0) [L410] ~__retres1~4 := 0; [L412] #res := ~__retres1~4; [L869] ~tmp___3~0 := #t~ret13; [L869] havoc #t~ret13; [L871-L875] COND FALSE !(0 != ~tmp___3~0) [L416] havoc ~__retres1~5; [L419] COND FALSE !(1 == ~t5_pc~0) [L429] ~__retres1~5 := 0; [L431] #res := ~__retres1~5; [L877] ~tmp___4~0 := #t~ret14; [L877] havoc #t~ret14; [L879-L883] COND FALSE !(0 != ~tmp___4~0) [L435] havoc ~__retres1~6; [L438] COND FALSE !(1 == ~t6_pc~0) [L448] ~__retres1~6 := 0; [L450] #res := ~__retres1~6; [L885] ~tmp___5~0 := #t~ret15; [L885] havoc #t~ret15; [L887-L891] COND FALSE !(0 != ~tmp___5~0) [L752] COND FALSE !(1 == ~M_E~0) [L757] COND FALSE !(1 == ~T1_E~0) [L762] COND FALSE !(1 == ~T2_E~0) [L767] COND FALSE !(1 == ~T3_E~0) [L772] COND FALSE !(1 == ~T4_E~0) [L777] COND FALSE !(1 == ~T5_E~0) [L782] COND FALSE !(1 == ~T6_E~0) [L787] COND FALSE !(1 == ~E_M~0) [L792] COND FALSE !(1 == ~E_1~0) [L797] COND FALSE !(1 == ~E_2~0) [L802] COND FALSE !(1 == ~E_3~0) [L807] COND FALSE !(1 == ~E_4~0) [L812] COND FALSE !(1 == ~E_5~0) [L817] COND FALSE !(1 == ~E_6~0) [L1043-L1080] COND FALSE !(false) [L1046] ~kernel_st~0 := 1; [L551] havoc ~tmp~0; [L14] int m_pc = 0; [L15] int t1_pc = 0; [L16] int t2_pc = 0; [L17] int t3_pc = 0; [L18] int t4_pc = 0; [L19] int t5_pc = 0; [L20] int t6_pc = 0; [L21] int m_st ; [L22] int t1_st ; [L23] int t2_st ; [L24] int t3_st ; [L25] int t4_st ; [L26] int t5_st ; [L27] int t6_st ; [L28] int m_i ; [L29] int t1_i ; [L30] int t2_i ; [L31] int t3_i ; [L32] int t4_i ; [L33] int t5_i ; [L34] int t6_i ; [L35] int M_E = 2; [L36] int T1_E = 2; [L37] int T2_E = 2; [L38] int T3_E = 2; [L39] int T4_E = 2; [L40] int T5_E = 2; [L41] int T6_E = 2; [L42] int E_M = 2; [L43] int E_1 = 2; [L44] int E_2 = 2; [L45] int E_3 = 2; [L46] int E_4 = 2; [L47] int E_5 = 2; [L48] int E_6 = 2; [L57] int token ; [L59] int local ; [L1088] int __retres1 ; [L998] m_i = 1 [L999] t1_i = 1 [L1000] t2_i = 1 [L1001] t3_i = 1 [L1002] t4_i = 1 [L1003] t5_i = 1 [L1004] t6_i = 1 [L1029] int kernel_st ; [L1030] int tmp ; [L1031] int tmp___0 ; [L1035] kernel_st = 0 [L465] COND TRUE m_i == 1 [L466] m_st = 0 [L470] COND TRUE t1_i == 1 [L471] t1_st = 0 [L475] COND TRUE t2_i == 1 [L476] t2_st = 0 [L480] COND TRUE t3_i == 1 [L481] t3_st = 0 [L485] COND TRUE t4_i == 1 [L486] t4_st = 0 [L490] COND TRUE t5_i == 1 [L491] t5_st = 0 [L495] COND TRUE t6_i == 1 [L496] t6_st = 0 [L674] COND FALSE !(M_E == 0) [L679] COND FALSE !(T1_E == 0) [L684] COND FALSE !(T2_E == 0) [L689] COND FALSE !(T3_E == 0) [L694] COND FALSE !(T4_E == 0) [L699] COND FALSE !(T5_E == 0) [L704] COND FALSE !(T6_E == 0) [L709] COND FALSE !(E_M == 0) [L714] COND FALSE !(E_1 == 0) [L719] COND FALSE !(E_2 == 0) [L724] COND FALSE !(E_3 == 0) [L729] COND FALSE !(E_4 == 0) [L734] COND FALSE !(E_5 == 0) [L739] COND FALSE !(E_6 == 0) [L827] int tmp ; [L828] int tmp___0 ; [L829] int tmp___1 ; [L830] int tmp___2 ; [L831] int tmp___3 ; [L832] int tmp___4 ; [L833] int tmp___5 ; [L321] int __retres1 ; [L324] COND FALSE !(m_pc == 1) [L334] __retres1 = 0 [L336] return (__retres1); [L837] tmp = is_master_triggered() [L839] COND FALSE !(\read(tmp)) [L340] int __retres1 ; [L343] COND FALSE !(t1_pc == 1) [L353] __retres1 = 0 [L355] return (__retres1); [L845] tmp___0 = is_transmit1_triggered() [L847] COND FALSE !(\read(tmp___0)) [L359] int __retres1 ; [L362] COND FALSE !(t2_pc == 1) [L372] __retres1 = 0 [L374] return (__retres1); [L853] tmp___1 = is_transmit2_triggered() [L855] COND FALSE !(\read(tmp___1)) [L378] int __retres1 ; [L381] COND FALSE !(t3_pc == 1) [L391] __retres1 = 0 [L393] return (__retres1); [L861] tmp___2 = is_transmit3_triggered() [L863] COND FALSE !(\read(tmp___2)) [L397] int __retres1 ; [L400] COND FALSE !(t4_pc == 1) [L410] __retres1 = 0 [L412] return (__retres1); [L869] tmp___3 = is_transmit4_triggered() [L871] COND FALSE !(\read(tmp___3)) [L416] int __retres1 ; [L419] COND FALSE !(t5_pc == 1) [L429] __retres1 = 0 [L431] return (__retres1); [L877] tmp___4 = is_transmit5_triggered() [L879] COND FALSE !(\read(tmp___4)) [L435] int __retres1 ; [L438] COND FALSE !(t6_pc == 1) [L448] __retres1 = 0 [L450] return (__retres1); [L885] tmp___5 = is_transmit6_triggered() [L887] COND FALSE !(\read(tmp___5)) [L752] COND FALSE !(M_E == 1) [L757] COND FALSE !(T1_E == 1) [L762] COND FALSE !(T2_E == 1) [L767] COND FALSE !(T3_E == 1) [L772] COND FALSE !(T4_E == 1) [L777] COND FALSE !(T5_E == 1) [L782] COND FALSE !(T6_E == 1) [L787] COND FALSE !(E_M == 1) [L792] COND FALSE !(E_1 == 1) [L797] COND FALSE !(E_2 == 1) [L802] COND FALSE !(E_3 == 1) [L807] COND FALSE !(E_4 == 1) [L812] COND FALSE !(E_5 == 1) [L817] COND FALSE !(E_6 == 1) [L1043] COND TRUE 1 [L1046] kernel_st = 1 [L551] int tmp ; ----- ----- class de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder.RCFGBacktranslator [?] assume !false; [?] havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~7;havoc exists_runnable_thread_~__retres1~7; [?] assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7 := 1; [?] exists_runnable_thread_#res := exists_runnable_thread_~__retres1~7; [?] eval_#t~ret1 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret1;havoc eval_#t~ret1; [?] assume 0 != eval_~tmp~0; [?] assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0;eval_~tmp_ndt_1~0 := eval_#t~nondet2;havoc eval_#t~nondet2; [?] assume !(0 != eval_~tmp_ndt_1~0); [?] assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0;eval_~tmp_ndt_2~0 := eval_#t~nondet3;havoc eval_#t~nondet3; [?] assume !(0 != eval_~tmp_ndt_2~0); [?] assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0;eval_~tmp_ndt_3~0 := eval_#t~nondet4;havoc eval_#t~nondet4; [?] assume !(0 != eval_~tmp_ndt_3~0); [?] assume 0 == ~t3_st~0;havoc eval_~tmp_ndt_4~0;eval_~tmp_ndt_4~0 := eval_#t~nondet5;havoc eval_#t~nondet5; [?] assume !(0 != eval_~tmp_ndt_4~0); [?] assume 0 == ~t4_st~0;havoc eval_~tmp_ndt_5~0;eval_~tmp_ndt_5~0 := eval_#t~nondet6;havoc eval_#t~nondet6; [?] assume !(0 != eval_~tmp_ndt_5~0); [?] assume 0 == ~t5_st~0;havoc eval_~tmp_ndt_6~0;eval_~tmp_ndt_6~0 := eval_#t~nondet7;havoc eval_#t~nondet7; [?] assume !(0 != eval_~tmp_ndt_6~0); [?] assume 0 == ~t6_st~0;havoc eval_~tmp_ndt_7~0;eval_~tmp_ndt_7~0 := eval_#t~nondet8;havoc eval_#t~nondet8; [?] assume !(0 != eval_~tmp_ndt_7~0); [L555-L663] assume !false; [L558] havoc exists_runnable_thread_#res; [L558] havoc exists_runnable_thread_~__retres1~7; [L505] havoc exists_runnable_thread_~__retres1~7; [L508-L543] assume 0 == ~m_st~0; [L509] exists_runnable_thread_~__retres1~7 := 1; [L546] exists_runnable_thread_#res := exists_runnable_thread_~__retres1~7; [L558] eval_#t~ret1 := exists_runnable_thread_#res; [L558] eval_~tmp~0 := eval_#t~ret1; [L558] havoc eval_#t~ret1; [L560-L564] assume 0 != eval_~tmp~0; [L565-L578] assume 0 == ~m_st~0; [L566] havoc eval_~tmp_ndt_1~0; [L567] eval_~tmp_ndt_1~0 := eval_#t~nondet2; [L567] havoc eval_#t~nondet2; [L568-L575] assume !(0 != eval_~tmp_ndt_1~0); [L579-L592] assume 0 == ~t1_st~0; [L580] havoc eval_~tmp_ndt_2~0; [L581] eval_~tmp_ndt_2~0 := eval_#t~nondet3; [L581] havoc eval_#t~nondet3; [L582-L589] assume !(0 != eval_~tmp_ndt_2~0); [L593-L606] assume 0 == ~t2_st~0; [L594] havoc eval_~tmp_ndt_3~0; [L595] eval_~tmp_ndt_3~0 := eval_#t~nondet4; [L595] havoc eval_#t~nondet4; [L596-L603] assume !(0 != eval_~tmp_ndt_3~0); [L607-L620] assume 0 == ~t3_st~0; [L608] havoc eval_~tmp_ndt_4~0; [L609] eval_~tmp_ndt_4~0 := eval_#t~nondet5; [L609] havoc eval_#t~nondet5; [L610-L617] assume !(0 != eval_~tmp_ndt_4~0); [L621-L634] assume 0 == ~t4_st~0; [L622] havoc eval_~tmp_ndt_5~0; [L623] eval_~tmp_ndt_5~0 := eval_#t~nondet6; [L623] havoc eval_#t~nondet6; [L624-L631] assume !(0 != eval_~tmp_ndt_5~0); [L635-L648] assume 0 == ~t5_st~0; [L636] havoc eval_~tmp_ndt_6~0; [L637] eval_~tmp_ndt_6~0 := eval_#t~nondet7; [L637] havoc eval_#t~nondet7; [L638-L645] assume !(0 != eval_~tmp_ndt_6~0); [L649-L662] assume 0 == ~t6_st~0; [L650] havoc eval_~tmp_ndt_7~0; [L651] eval_~tmp_ndt_7~0 := eval_#t~nondet8; [L651] havoc eval_#t~nondet8; [L652-L659] assume !(0 != eval_~tmp_ndt_7~0); ----- ----- class de.uni_freiburg.informatik.ultimate.boogie.preprocessor.BoogiePreprocessorBacktranslator [L555-L663] assume !false; [L558] havoc exists_runnable_thread_#res; [L558] havoc exists_runnable_thread_~__retres1~7; [L505] havoc exists_runnable_thread_~__retres1~7; [L508-L543] assume 0 == ~m_st~0; [L509] exists_runnable_thread_~__retres1~7 := 1; [L546] exists_runnable_thread_#res := exists_runnable_thread_~__retres1~7; [L558] eval_#t~ret1 := exists_runnable_thread_#res; [L558] eval_~tmp~0 := eval_#t~ret1; [L558] havoc eval_#t~ret1; [L560-L564] assume 0 != eval_~tmp~0; [L565-L578] assume 0 == ~m_st~0; [L566] havoc eval_~tmp_ndt_1~0; [L567] eval_~tmp_ndt_1~0 := eval_#t~nondet2; [L567] havoc eval_#t~nondet2; [L568-L575] assume !(0 != eval_~tmp_ndt_1~0); [L579-L592] assume 0 == ~t1_st~0; [L580] havoc eval_~tmp_ndt_2~0; [L581] eval_~tmp_ndt_2~0 := eval_#t~nondet3; [L581] havoc eval_#t~nondet3; [L582-L589] assume !(0 != eval_~tmp_ndt_2~0); [L593-L606] assume 0 == ~t2_st~0; [L594] havoc eval_~tmp_ndt_3~0; [L595] eval_~tmp_ndt_3~0 := eval_#t~nondet4; [L595] havoc eval_#t~nondet4; [L596-L603] assume !(0 != eval_~tmp_ndt_3~0); [L607-L620] assume 0 == ~t3_st~0; [L608] havoc eval_~tmp_ndt_4~0; [L609] eval_~tmp_ndt_4~0 := eval_#t~nondet5; [L609] havoc eval_#t~nondet5; [L610-L617] assume !(0 != eval_~tmp_ndt_4~0); [L621-L634] assume 0 == ~t4_st~0; [L622] havoc eval_~tmp_ndt_5~0; [L623] eval_~tmp_ndt_5~0 := eval_#t~nondet6; [L623] havoc eval_#t~nondet6; [L624-L631] assume !(0 != eval_~tmp_ndt_5~0); [L635-L648] assume 0 == ~t5_st~0; [L636] havoc eval_~tmp_ndt_6~0; [L637] eval_~tmp_ndt_6~0 := eval_#t~nondet7; [L637] havoc eval_#t~nondet7; [L638-L645] assume !(0 != eval_~tmp_ndt_6~0); [L649-L662] assume 0 == ~t6_st~0; [L650] havoc eval_~tmp_ndt_7~0; [L651] eval_~tmp_ndt_7~0 := eval_#t~nondet8; [L651] havoc eval_#t~nondet8; [L652-L659] assume !(0 != eval_~tmp_ndt_7~0); [L555-L663] COND FALSE !(false) [L558] havoc exists_runnable_thread_#res; [L558] havoc exists_runnable_thread_~__retres1~7; [L505] havoc exists_runnable_thread_~__retres1~7; [L508] COND TRUE 0 == ~m_st~0 [L509] exists_runnable_thread_~__retres1~7 := 1; [L546] exists_runnable_thread_#res := exists_runnable_thread_~__retres1~7; [L558] eval_#t~ret1 := exists_runnable_thread_#res; [L558] eval_~tmp~0 := eval_#t~ret1; [L558] havoc eval_#t~ret1; [L560-L564] COND TRUE 0 != eval_~tmp~0 [L565] COND TRUE 0 == ~m_st~0 [L566] havoc eval_~tmp_ndt_1~0; [L567] eval_~tmp_ndt_1~0 := eval_#t~nondet2; [L567] havoc eval_#t~nondet2; [L568-L575] COND FALSE !(0 != eval_~tmp_ndt_1~0) [L579] COND TRUE 0 == ~t1_st~0 [L580] havoc eval_~tmp_ndt_2~0; [L581] eval_~tmp_ndt_2~0 := eval_#t~nondet3; [L581] havoc eval_#t~nondet3; [L582-L589] COND FALSE !(0 != eval_~tmp_ndt_2~0) [L593] COND TRUE 0 == ~t2_st~0 [L594] havoc eval_~tmp_ndt_3~0; [L595] eval_~tmp_ndt_3~0 := eval_#t~nondet4; [L595] havoc eval_#t~nondet4; [L596-L603] COND FALSE !(0 != eval_~tmp_ndt_3~0) [L607] COND TRUE 0 == ~t3_st~0 [L608] havoc eval_~tmp_ndt_4~0; [L609] eval_~tmp_ndt_4~0 := eval_#t~nondet5; [L609] havoc eval_#t~nondet5; [L610-L617] COND FALSE !(0 != eval_~tmp_ndt_4~0) [L621] COND TRUE 0 == ~t4_st~0 [L622] havoc eval_~tmp_ndt_5~0; [L623] eval_~tmp_ndt_5~0 := eval_#t~nondet6; [L623] havoc eval_#t~nondet6; [L624-L631] COND FALSE !(0 != eval_~tmp_ndt_5~0) [L635] COND TRUE 0 == ~t5_st~0 [L636] havoc eval_~tmp_ndt_6~0; [L637] eval_~tmp_ndt_6~0 := eval_#t~nondet7; [L637] havoc eval_#t~nondet7; [L638-L645] COND FALSE !(0 != eval_~tmp_ndt_6~0) [L649] COND TRUE 0 == ~t6_st~0 [L650] havoc eval_~tmp_ndt_7~0; [L651] eval_~tmp_ndt_7~0 := eval_#t~nondet8; [L651] havoc eval_#t~nondet8; [L652-L659] COND FALSE !(0 != eval_~tmp_ndt_7~0) ----- ----- class de.uni_freiburg.informatik.ultimate.boogie.procedureinliner.backtranslation.InlinerBacktranslator [L555-L663] COND FALSE !(false) [L558] havoc exists_runnable_thread_#res; [L558] havoc exists_runnable_thread_~__retres1~7; [L505] havoc exists_runnable_thread_~__retres1~7; [L508] COND TRUE 0 == ~m_st~0 [L509] exists_runnable_thread_~__retres1~7 := 1; [L546] exists_runnable_thread_#res := exists_runnable_thread_~__retres1~7; [L558] eval_#t~ret1 := exists_runnable_thread_#res; [L558] eval_~tmp~0 := eval_#t~ret1; [L558] havoc eval_#t~ret1; [L560-L564] COND TRUE 0 != eval_~tmp~0 [L565] COND TRUE 0 == ~m_st~0 [L566] havoc eval_~tmp_ndt_1~0; [L567] eval_~tmp_ndt_1~0 := eval_#t~nondet2; [L567] havoc eval_#t~nondet2; [L568-L575] COND FALSE !(0 != eval_~tmp_ndt_1~0) [L579] COND TRUE 0 == ~t1_st~0 [L580] havoc eval_~tmp_ndt_2~0; [L581] eval_~tmp_ndt_2~0 := eval_#t~nondet3; [L581] havoc eval_#t~nondet3; [L582-L589] COND FALSE !(0 != eval_~tmp_ndt_2~0) [L593] COND TRUE 0 == ~t2_st~0 [L594] havoc eval_~tmp_ndt_3~0; [L595] eval_~tmp_ndt_3~0 := eval_#t~nondet4; [L595] havoc eval_#t~nondet4; [L596-L603] COND FALSE !(0 != eval_~tmp_ndt_3~0) [L607] COND TRUE 0 == ~t3_st~0 [L608] havoc eval_~tmp_ndt_4~0; [L609] eval_~tmp_ndt_4~0 := eval_#t~nondet5; [L609] havoc eval_#t~nondet5; [L610-L617] COND FALSE !(0 != eval_~tmp_ndt_4~0) [L621] COND TRUE 0 == ~t4_st~0 [L622] havoc eval_~tmp_ndt_5~0; [L623] eval_~tmp_ndt_5~0 := eval_#t~nondet6; [L623] havoc eval_#t~nondet6; [L624-L631] COND FALSE !(0 != eval_~tmp_ndt_5~0) [L635] COND TRUE 0 == ~t5_st~0 [L636] havoc eval_~tmp_ndt_6~0; [L637] eval_~tmp_ndt_6~0 := eval_#t~nondet7; [L637] havoc eval_#t~nondet7; [L638-L645] COND FALSE !(0 != eval_~tmp_ndt_6~0) [L649] COND TRUE 0 == ~t6_st~0 [L650] havoc eval_~tmp_ndt_7~0; [L651] eval_~tmp_ndt_7~0 := eval_#t~nondet8; [L651] havoc eval_#t~nondet8; [L652-L659] COND FALSE !(0 != eval_~tmp_ndt_7~0) [L555-L663] COND FALSE !(false) [L505] havoc ~__retres1~7; [L508] COND TRUE 0 == ~m_st~0 [L509] ~__retres1~7 := 1; [L546] #res := ~__retres1~7; [L558] ~tmp~0 := #t~ret1; [L558] havoc #t~ret1; [L560-L564] COND TRUE 0 != ~tmp~0 [L565] COND TRUE 0 == ~m_st~0 [L566] havoc ~tmp_ndt_1~0; [L567] ~tmp_ndt_1~0 := #t~nondet2; [L567] havoc #t~nondet2; [L568-L575] COND FALSE !(0 != ~tmp_ndt_1~0) [L579] COND TRUE 0 == ~t1_st~0 [L580] havoc ~tmp_ndt_2~0; [L581] ~tmp_ndt_2~0 := #t~nondet3; [L581] havoc #t~nondet3; [L582-L589] COND FALSE !(0 != ~tmp_ndt_2~0) [L593] COND TRUE 0 == ~t2_st~0 [L594] havoc ~tmp_ndt_3~0; [L595] ~tmp_ndt_3~0 := #t~nondet4; [L595] havoc #t~nondet4; [L596-L603] COND FALSE !(0 != ~tmp_ndt_3~0) [L607] COND TRUE 0 == ~t3_st~0 [L608] havoc ~tmp_ndt_4~0; [L609] ~tmp_ndt_4~0 := #t~nondet5; [L609] havoc #t~nondet5; [L610-L617] COND FALSE !(0 != ~tmp_ndt_4~0) [L621] COND TRUE 0 == ~t4_st~0 [L622] havoc ~tmp_ndt_5~0; [L623] ~tmp_ndt_5~0 := #t~nondet6; [L623] havoc #t~nondet6; [L624-L631] COND FALSE !(0 != ~tmp_ndt_5~0) [L635] COND TRUE 0 == ~t5_st~0 [L636] havoc ~tmp_ndt_6~0; [L637] ~tmp_ndt_6~0 := #t~nondet7; [L637] havoc #t~nondet7; [L638-L645] COND FALSE !(0 != ~tmp_ndt_6~0) [L649] COND TRUE 0 == ~t6_st~0 [L650] havoc ~tmp_ndt_7~0; [L651] ~tmp_ndt_7~0 := #t~nondet8; [L651] havoc #t~nondet8; [L652-L659] COND FALSE !(0 != ~tmp_ndt_7~0) ----- ----- class de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.CACSL2BoogieBacktranslator [L555-L663] COND FALSE !(false) [L505] havoc ~__retres1~7; [L508] COND TRUE 0 == ~m_st~0 [L509] ~__retres1~7 := 1; [L546] #res := ~__retres1~7; [L558] ~tmp~0 := #t~ret1; [L558] havoc #t~ret1; [L560-L564] COND TRUE 0 != ~tmp~0 [L565] COND TRUE 0 == ~m_st~0 [L566] havoc ~tmp_ndt_1~0; [L567] ~tmp_ndt_1~0 := #t~nondet2; [L567] havoc #t~nondet2; [L568-L575] COND FALSE !(0 != ~tmp_ndt_1~0) [L579] COND TRUE 0 == ~t1_st~0 [L580] havoc ~tmp_ndt_2~0; [L581] ~tmp_ndt_2~0 := #t~nondet3; [L581] havoc #t~nondet3; [L582-L589] COND FALSE !(0 != ~tmp_ndt_2~0) [L593] COND TRUE 0 == ~t2_st~0 [L594] havoc ~tmp_ndt_3~0; [L595] ~tmp_ndt_3~0 := #t~nondet4; [L595] havoc #t~nondet4; [L596-L603] COND FALSE !(0 != ~tmp_ndt_3~0) [L607] COND TRUE 0 == ~t3_st~0 [L608] havoc ~tmp_ndt_4~0; [L609] ~tmp_ndt_4~0 := #t~nondet5; [L609] havoc #t~nondet5; [L610-L617] COND FALSE !(0 != ~tmp_ndt_4~0) [L621] COND TRUE 0 == ~t4_st~0 [L622] havoc ~tmp_ndt_5~0; [L623] ~tmp_ndt_5~0 := #t~nondet6; [L623] havoc #t~nondet6; [L624-L631] COND FALSE !(0 != ~tmp_ndt_5~0) [L635] COND TRUE 0 == ~t5_st~0 [L636] havoc ~tmp_ndt_6~0; [L637] ~tmp_ndt_6~0 := #t~nondet7; [L637] havoc #t~nondet7; [L638-L645] COND FALSE !(0 != ~tmp_ndt_6~0) [L649] COND TRUE 0 == ~t6_st~0 [L650] havoc ~tmp_ndt_7~0; [L651] ~tmp_ndt_7~0 := #t~nondet8; [L651] havoc #t~nondet8; [L652-L659] COND FALSE !(0 != ~tmp_ndt_7~0) [L555] COND TRUE 1 [L505] int __retres1 ; [L508] COND TRUE m_st == 0 [L509] __retres1 = 1 [L546] return (__retres1); [L558] tmp = exists_runnable_thread() [L560] COND TRUE \read(tmp) [L565] COND TRUE m_st == 0 [L566] int tmp_ndt_1; [L567] tmp_ndt_1 = __VERIFIER_nondet_int() [L568] COND FALSE !(\read(tmp_ndt_1)) [L579] COND TRUE t1_st == 0 [L580] int tmp_ndt_2; [L581] tmp_ndt_2 = __VERIFIER_nondet_int() [L582] COND FALSE !(\read(tmp_ndt_2)) [L593] COND TRUE t2_st == 0 [L594] int tmp_ndt_3; [L595] tmp_ndt_3 = __VERIFIER_nondet_int() [L596] COND FALSE !(\read(tmp_ndt_3)) [L607] COND TRUE t3_st == 0 [L608] int tmp_ndt_4; [L609] tmp_ndt_4 = __VERIFIER_nondet_int() [L610] COND FALSE !(\read(tmp_ndt_4)) [L621] COND TRUE t4_st == 0 [L622] int tmp_ndt_5; [L623] tmp_ndt_5 = __VERIFIER_nondet_int() [L624] COND FALSE !(\read(tmp_ndt_5)) [L635] COND TRUE t5_st == 0 [L636] int tmp_ndt_6; [L637] tmp_ndt_6 = __VERIFIER_nondet_int() [L638] COND FALSE !(\read(tmp_ndt_6)) [L649] COND TRUE t6_st == 0 [L650] int tmp_ndt_7; [L651] tmp_ndt_7 = __VERIFIER_nondet_int() [L652] COND FALSE !(\read(tmp_ndt_7)) ----- ----- class de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder.RCFGBacktranslator [?] ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0; [?] havoc main_#res;havoc main_~__retres1~8;havoc main_~__retres1~8;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; [?] havoc start_simulation_#t~ret17, start_simulation_#t~ret18, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; [?] assume 1 == ~m_i~0;~m_st~0 := 0; [?] assume 1 == ~t1_i~0;~t1_st~0 := 0; [?] assume 1 == ~t2_i~0;~t2_st~0 := 0; [?] assume 1 == ~t3_i~0;~t3_st~0 := 0; [?] assume 1 == ~t4_i~0;~t4_st~0 := 0; [?] assume 1 == ~t5_i~0;~t5_st~0 := 0; [?] assume 1 == ~t6_i~0;~t6_st~0 := 0; [?] assume !(0 == ~M_E~0); [?] assume !(0 == ~T1_E~0); [?] assume !(0 == ~T2_E~0); [?] assume !(0 == ~T3_E~0); [?] assume !(0 == ~T4_E~0); [?] assume !(0 == ~T5_E~0); [?] assume !(0 == ~T6_E~0); [?] assume !(0 == ~E_M~0); [?] assume !(0 == ~E_1~0); [?] assume !(0 == ~E_2~0); [?] assume !(0 == ~E_3~0); [?] assume !(0 == ~E_4~0); [?] assume !(0 == ~E_5~0); [?] assume !(0 == ~E_6~0); [?] havoc activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; [?] assume !(1 == ~m_pc~0); [?] is_master_triggered_~__retres1~0 := 0; [?] is_master_triggered_#res := is_master_triggered_~__retres1~0; [?] activate_threads_#t~ret9 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; [?] assume !(0 != activate_threads_~tmp~1); [?] havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; [?] assume !(1 == ~t1_pc~0); [?] is_transmit1_triggered_~__retres1~1 := 0; [?] is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; [?] activate_threads_#t~ret10 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; [?] assume !(0 != activate_threads_~tmp___0~0); [?] havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; [?] assume !(1 == ~t2_pc~0); [?] is_transmit2_triggered_~__retres1~2 := 0; [?] is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; [?] activate_threads_#t~ret11 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; [?] assume !(0 != activate_threads_~tmp___1~0); [?] havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; [?] assume !(1 == ~t3_pc~0); [?] is_transmit3_triggered_~__retres1~3 := 0; [?] is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; [?] activate_threads_#t~ret12 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; [?] assume !(0 != activate_threads_~tmp___2~0); [?] havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; [?] assume !(1 == ~t4_pc~0); [?] is_transmit4_triggered_~__retres1~4 := 0; [?] is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; [?] activate_threads_#t~ret13 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; [?] assume !(0 != activate_threads_~tmp___3~0); [?] havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; [?] assume !(1 == ~t5_pc~0); [?] is_transmit5_triggered_~__retres1~5 := 0; [?] is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; [?] activate_threads_#t~ret14 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; [?] assume !(0 != activate_threads_~tmp___4~0); [?] havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; [?] assume !(1 == ~t6_pc~0); [?] is_transmit6_triggered_~__retres1~6 := 0; [?] is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; [?] activate_threads_#t~ret15 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; [?] assume !(0 != activate_threads_~tmp___5~0); [?] assume !(1 == ~M_E~0); [?] assume !(1 == ~T1_E~0); [?] assume !(1 == ~T2_E~0); [?] assume !(1 == ~T3_E~0); [?] assume !(1 == ~T4_E~0); [?] assume !(1 == ~T5_E~0); [?] assume !(1 == ~T6_E~0); [?] assume !(1 == ~E_M~0); [?] assume !(1 == ~E_1~0); [?] assume !(1 == ~E_2~0); [?] assume !(1 == ~E_3~0); [?] assume !(1 == ~E_4~0); [?] assume !(1 == ~E_5~0); [?] assume !(1 == ~E_6~0); [?] assume !false; [?] start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret1, eval_#t~nondet2, eval_~tmp_ndt_1~0, eval_#t~nondet3, eval_~tmp_ndt_2~0, eval_#t~nondet4, eval_~tmp_ndt_3~0, eval_#t~nondet5, eval_~tmp_ndt_4~0, eval_#t~nondet6, eval_~tmp_ndt_5~0, eval_#t~nondet7, eval_~tmp_ndt_6~0, eval_#t~nondet8, eval_~tmp_ndt_7~0, eval_~tmp~0;havoc eval_~tmp~0; [L14] ~m_pc~0 := 0; [L15] ~t1_pc~0 := 0; [L16] ~t2_pc~0 := 0; [L17] ~t3_pc~0 := 0; [L18] ~t4_pc~0 := 0; [L19] ~t5_pc~0 := 0; [L20] ~t6_pc~0 := 0; [L21] ~m_st~0 := 0; [L22] ~t1_st~0 := 0; [L23] ~t2_st~0 := 0; [L24] ~t3_st~0 := 0; [L25] ~t4_st~0 := 0; [L26] ~t5_st~0 := 0; [L27] ~t6_st~0 := 0; [L28] ~m_i~0 := 0; [L29] ~t1_i~0 := 0; [L30] ~t2_i~0 := 0; [L31] ~t3_i~0 := 0; [L32] ~t4_i~0 := 0; [L33] ~t5_i~0 := 0; [L34] ~t6_i~0 := 0; [L35] ~M_E~0 := 2; [L36] ~T1_E~0 := 2; [L37] ~T2_E~0 := 2; [L38] ~T3_E~0 := 2; [L39] ~T4_E~0 := 2; [L40] ~T5_E~0 := 2; [L41] ~T6_E~0 := 2; [L42] ~E_M~0 := 2; [L43] ~E_1~0 := 2; [L44] ~E_2~0 := 2; [L45] ~E_3~0 := 2; [L46] ~E_4~0 := 2; [L47] ~E_5~0 := 2; [L48] ~E_6~0 := 2; [L57] ~token~0 := 0; [L59] ~local~0 := 0; [?] havoc main_#res; [?] havoc main_~__retres1~8; [L1088] havoc main_~__retres1~8; [L998] ~m_i~0 := 1; [L999] ~t1_i~0 := 1; [L1000] ~t2_i~0 := 1; [L1001] ~t3_i~0 := 1; [L1002] ~t4_i~0 := 1; [L1003] ~t5_i~0 := 1; [L1004] ~t6_i~0 := 1; [L1093] havoc start_simulation_#t~ret17, start_simulation_#t~ret18, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1; [L1029] havoc start_simulation_~kernel_st~0; [L1030] havoc start_simulation_~tmp~3; [L1031] havoc start_simulation_~tmp___0~1; [L1035] start_simulation_~kernel_st~0 := 0; [L465-L469] assume 1 == ~m_i~0; [L466] ~m_st~0 := 0; [L470-L474] assume 1 == ~t1_i~0; [L471] ~t1_st~0 := 0; [L475-L479] assume 1 == ~t2_i~0; [L476] ~t2_st~0 := 0; [L480-L484] assume 1 == ~t3_i~0; [L481] ~t3_st~0 := 0; [L485-L489] assume 1 == ~t4_i~0; [L486] ~t4_st~0 := 0; [L490-L494] assume 1 == ~t5_i~0; [L491] ~t5_st~0 := 0; [L495-L499] assume 1 == ~t6_i~0; [L496] ~t6_st~0 := 0; [L674-L678] assume !(0 == ~M_E~0); [L679-L683] assume !(0 == ~T1_E~0); [L684-L688] assume !(0 == ~T2_E~0); [L689-L693] assume !(0 == ~T3_E~0); [L694-L698] assume !(0 == ~T4_E~0); [L699-L703] assume !(0 == ~T5_E~0); [L704-L708] assume !(0 == ~T6_E~0); [L709-L713] assume !(0 == ~E_M~0); [L714-L718] assume !(0 == ~E_1~0); [L719-L723] assume !(0 == ~E_2~0); [L724-L728] assume !(0 == ~E_3~0); [L729-L733] assume !(0 == ~E_4~0); [L734-L738] assume !(0 == ~E_5~0); [L739-L743] assume !(0 == ~E_6~0); [L1039] havoc activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0; [L827] havoc activate_threads_~tmp~1; [L828] havoc activate_threads_~tmp___0~0; [L829] havoc activate_threads_~tmp___1~0; [L830] havoc activate_threads_~tmp___2~0; [L831] havoc activate_threads_~tmp___3~0; [L832] havoc activate_threads_~tmp___4~0; [L833] havoc activate_threads_~tmp___5~0; [L837] havoc is_master_triggered_#res; [L837] havoc is_master_triggered_~__retres1~0; [L321] havoc is_master_triggered_~__retres1~0; [L324-L333] assume !(1 == ~m_pc~0); [L334] is_master_triggered_~__retres1~0 := 0; [L336] is_master_triggered_#res := is_master_triggered_~__retres1~0; [L837] activate_threads_#t~ret9 := is_master_triggered_#res; [L837] activate_threads_~tmp~1 := activate_threads_#t~ret9; [L837] havoc activate_threads_#t~ret9; [L839-L843] assume !(0 != activate_threads_~tmp~1); [L845] havoc is_transmit1_triggered_#res; [L845] havoc is_transmit1_triggered_~__retres1~1; [L340] havoc is_transmit1_triggered_~__retres1~1; [L343-L352] assume !(1 == ~t1_pc~0); [L353] is_transmit1_triggered_~__retres1~1 := 0; [L355] is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; [L845] activate_threads_#t~ret10 := is_transmit1_triggered_#res; [L845] activate_threads_~tmp___0~0 := activate_threads_#t~ret10; [L845] havoc activate_threads_#t~ret10; [L847-L851] assume !(0 != activate_threads_~tmp___0~0); [L853] havoc is_transmit2_triggered_#res; [L853] havoc is_transmit2_triggered_~__retres1~2; [L359] havoc is_transmit2_triggered_~__retres1~2; [L362-L371] assume !(1 == ~t2_pc~0); [L372] is_transmit2_triggered_~__retres1~2 := 0; [L374] is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; [L853] activate_threads_#t~ret11 := is_transmit2_triggered_#res; [L853] activate_threads_~tmp___1~0 := activate_threads_#t~ret11; [L853] havoc activate_threads_#t~ret11; [L855-L859] assume !(0 != activate_threads_~tmp___1~0); [L861] havoc is_transmit3_triggered_#res; [L861] havoc is_transmit3_triggered_~__retres1~3; [L378] havoc is_transmit3_triggered_~__retres1~3; [L381-L390] assume !(1 == ~t3_pc~0); [L391] is_transmit3_triggered_~__retres1~3 := 0; [L393] is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; [L861] activate_threads_#t~ret12 := is_transmit3_triggered_#res; [L861] activate_threads_~tmp___2~0 := activate_threads_#t~ret12; [L861] havoc activate_threads_#t~ret12; [L863-L867] assume !(0 != activate_threads_~tmp___2~0); [L869] havoc is_transmit4_triggered_#res; [L869] havoc is_transmit4_triggered_~__retres1~4; [L397] havoc is_transmit4_triggered_~__retres1~4; [L400-L409] assume !(1 == ~t4_pc~0); [L410] is_transmit4_triggered_~__retres1~4 := 0; [L412] is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; [L869] activate_threads_#t~ret13 := is_transmit4_triggered_#res; [L869] activate_threads_~tmp___3~0 := activate_threads_#t~ret13; [L869] havoc activate_threads_#t~ret13; [L871-L875] assume !(0 != activate_threads_~tmp___3~0); [L877] havoc is_transmit5_triggered_#res; [L877] havoc is_transmit5_triggered_~__retres1~5; [L416] havoc is_transmit5_triggered_~__retres1~5; [L419-L428] assume !(1 == ~t5_pc~0); [L429] is_transmit5_triggered_~__retres1~5 := 0; [L431] is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; [L877] activate_threads_#t~ret14 := is_transmit5_triggered_#res; [L877] activate_threads_~tmp___4~0 := activate_threads_#t~ret14; [L877] havoc activate_threads_#t~ret14; [L879-L883] assume !(0 != activate_threads_~tmp___4~0); [L885] havoc is_transmit6_triggered_#res; [L885] havoc is_transmit6_triggered_~__retres1~6; [L435] havoc is_transmit6_triggered_~__retres1~6; [L438-L447] assume !(1 == ~t6_pc~0); [L448] is_transmit6_triggered_~__retres1~6 := 0; [L450] is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; [L885] activate_threads_#t~ret15 := is_transmit6_triggered_#res; [L885] activate_threads_~tmp___5~0 := activate_threads_#t~ret15; [L885] havoc activate_threads_#t~ret15; [L887-L891] assume !(0 != activate_threads_~tmp___5~0); [L752-L756] assume !(1 == ~M_E~0); [L757-L761] assume !(1 == ~T1_E~0); [L762-L766] assume !(1 == ~T2_E~0); [L767-L771] assume !(1 == ~T3_E~0); [L772-L776] assume !(1 == ~T4_E~0); [L777-L781] assume !(1 == ~T5_E~0); [L782-L786] assume !(1 == ~T6_E~0); [L787-L791] assume !(1 == ~E_M~0); [L792-L796] assume !(1 == ~E_1~0); [L797-L801] assume !(1 == ~E_2~0); [L802-L806] assume !(1 == ~E_3~0); [L807-L811] assume !(1 == ~E_4~0); [L812-L816] assume !(1 == ~E_5~0); [L817-L821] assume !(1 == ~E_6~0); [L1043-L1080] assume !false; [L1046] start_simulation_~kernel_st~0 := 1; [L1047] havoc eval_#t~ret1, eval_#t~nondet2, eval_~tmp_ndt_1~0, eval_#t~nondet3, eval_~tmp_ndt_2~0, eval_#t~nondet4, eval_~tmp_ndt_3~0, eval_#t~nondet5, eval_~tmp_ndt_4~0, eval_#t~nondet6, eval_~tmp_ndt_5~0, eval_#t~nondet7, eval_~tmp_ndt_6~0, eval_#t~nondet8, eval_~tmp_ndt_7~0, eval_~tmp~0; [L551] havoc eval_~tmp~0; ----- ----- class de.uni_freiburg.informatik.ultimate.boogie.preprocessor.BoogiePreprocessorBacktranslator [L14] ~m_pc~0 := 0; [L15] ~t1_pc~0 := 0; [L16] ~t2_pc~0 := 0; [L17] ~t3_pc~0 := 0; [L18] ~t4_pc~0 := 0; [L19] ~t5_pc~0 := 0; [L20] ~t6_pc~0 := 0; [L21] ~m_st~0 := 0; [L22] ~t1_st~0 := 0; [L23] ~t2_st~0 := 0; [L24] ~t3_st~0 := 0; [L25] ~t4_st~0 := 0; [L26] ~t5_st~0 := 0; [L27] ~t6_st~0 := 0; [L28] ~m_i~0 := 0; [L29] ~t1_i~0 := 0; [L30] ~t2_i~0 := 0; [L31] ~t3_i~0 := 0; [L32] ~t4_i~0 := 0; [L33] ~t5_i~0 := 0; [L34] ~t6_i~0 := 0; [L35] ~M_E~0 := 2; [L36] ~T1_E~0 := 2; [L37] ~T2_E~0 := 2; [L38] ~T3_E~0 := 2; [L39] ~T4_E~0 := 2; [L40] ~T5_E~0 := 2; [L41] ~T6_E~0 := 2; [L42] ~E_M~0 := 2; [L43] ~E_1~0 := 2; [L44] ~E_2~0 := 2; [L45] ~E_3~0 := 2; [L46] ~E_4~0 := 2; [L47] ~E_5~0 := 2; [L48] ~E_6~0 := 2; [L57] ~token~0 := 0; [L59] ~local~0 := 0; [?] havoc main_#res; [?] havoc main_~__retres1~8; [L1088] havoc main_~__retres1~8; [L998] ~m_i~0 := 1; [L999] ~t1_i~0 := 1; [L1000] ~t2_i~0 := 1; [L1001] ~t3_i~0 := 1; [L1002] ~t4_i~0 := 1; [L1003] ~t5_i~0 := 1; [L1004] ~t6_i~0 := 1; [L1093] havoc start_simulation_#t~ret17, start_simulation_#t~ret18, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1; [L1029] havoc start_simulation_~kernel_st~0; [L1030] havoc start_simulation_~tmp~3; [L1031] havoc start_simulation_~tmp___0~1; [L1035] start_simulation_~kernel_st~0 := 0; [L465-L469] assume 1 == ~m_i~0; [L466] ~m_st~0 := 0; [L470-L474] assume 1 == ~t1_i~0; [L471] ~t1_st~0 := 0; [L475-L479] assume 1 == ~t2_i~0; [L476] ~t2_st~0 := 0; [L480-L484] assume 1 == ~t3_i~0; [L481] ~t3_st~0 := 0; [L485-L489] assume 1 == ~t4_i~0; [L486] ~t4_st~0 := 0; [L490-L494] assume 1 == ~t5_i~0; [L491] ~t5_st~0 := 0; [L495-L499] assume 1 == ~t6_i~0; [L496] ~t6_st~0 := 0; [L674-L678] assume !(0 == ~M_E~0); [L679-L683] assume !(0 == ~T1_E~0); [L684-L688] assume !(0 == ~T2_E~0); [L689-L693] assume !(0 == ~T3_E~0); [L694-L698] assume !(0 == ~T4_E~0); [L699-L703] assume !(0 == ~T5_E~0); [L704-L708] assume !(0 == ~T6_E~0); [L709-L713] assume !(0 == ~E_M~0); [L714-L718] assume !(0 == ~E_1~0); [L719-L723] assume !(0 == ~E_2~0); [L724-L728] assume !(0 == ~E_3~0); [L729-L733] assume !(0 == ~E_4~0); [L734-L738] assume !(0 == ~E_5~0); [L739-L743] assume !(0 == ~E_6~0); [L1039] havoc activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0; [L827] havoc activate_threads_~tmp~1; [L828] havoc activate_threads_~tmp___0~0; [L829] havoc activate_threads_~tmp___1~0; [L830] havoc activate_threads_~tmp___2~0; [L831] havoc activate_threads_~tmp___3~0; [L832] havoc activate_threads_~tmp___4~0; [L833] havoc activate_threads_~tmp___5~0; [L837] havoc is_master_triggered_#res; [L837] havoc is_master_triggered_~__retres1~0; [L321] havoc is_master_triggered_~__retres1~0; [L324-L333] assume !(1 == ~m_pc~0); [L334] is_master_triggered_~__retres1~0 := 0; [L336] is_master_triggered_#res := is_master_triggered_~__retres1~0; [L837] activate_threads_#t~ret9 := is_master_triggered_#res; [L837] activate_threads_~tmp~1 := activate_threads_#t~ret9; [L837] havoc activate_threads_#t~ret9; [L839-L843] assume !(0 != activate_threads_~tmp~1); [L845] havoc is_transmit1_triggered_#res; [L845] havoc is_transmit1_triggered_~__retres1~1; [L340] havoc is_transmit1_triggered_~__retres1~1; [L343-L352] assume !(1 == ~t1_pc~0); [L353] is_transmit1_triggered_~__retres1~1 := 0; [L355] is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; [L845] activate_threads_#t~ret10 := is_transmit1_triggered_#res; [L845] activate_threads_~tmp___0~0 := activate_threads_#t~ret10; [L845] havoc activate_threads_#t~ret10; [L847-L851] assume !(0 != activate_threads_~tmp___0~0); [L853] havoc is_transmit2_triggered_#res; [L853] havoc is_transmit2_triggered_~__retres1~2; [L359] havoc is_transmit2_triggered_~__retres1~2; [L362-L371] assume !(1 == ~t2_pc~0); [L372] is_transmit2_triggered_~__retres1~2 := 0; [L374] is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; [L853] activate_threads_#t~ret11 := is_transmit2_triggered_#res; [L853] activate_threads_~tmp___1~0 := activate_threads_#t~ret11; [L853] havoc activate_threads_#t~ret11; [L855-L859] assume !(0 != activate_threads_~tmp___1~0); [L861] havoc is_transmit3_triggered_#res; [L861] havoc is_transmit3_triggered_~__retres1~3; [L378] havoc is_transmit3_triggered_~__retres1~3; [L381-L390] assume !(1 == ~t3_pc~0); [L391] is_transmit3_triggered_~__retres1~3 := 0; [L393] is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; [L861] activate_threads_#t~ret12 := is_transmit3_triggered_#res; [L861] activate_threads_~tmp___2~0 := activate_threads_#t~ret12; [L861] havoc activate_threads_#t~ret12; [L863-L867] assume !(0 != activate_threads_~tmp___2~0); [L869] havoc is_transmit4_triggered_#res; [L869] havoc is_transmit4_triggered_~__retres1~4; [L397] havoc is_transmit4_triggered_~__retres1~4; [L400-L409] assume !(1 == ~t4_pc~0); [L410] is_transmit4_triggered_~__retres1~4 := 0; [L412] is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; [L869] activate_threads_#t~ret13 := is_transmit4_triggered_#res; [L869] activate_threads_~tmp___3~0 := activate_threads_#t~ret13; [L869] havoc activate_threads_#t~ret13; [L871-L875] assume !(0 != activate_threads_~tmp___3~0); [L877] havoc is_transmit5_triggered_#res; [L877] havoc is_transmit5_triggered_~__retres1~5; [L416] havoc is_transmit5_triggered_~__retres1~5; [L419-L428] assume !(1 == ~t5_pc~0); [L429] is_transmit5_triggered_~__retres1~5 := 0; [L431] is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; [L877] activate_threads_#t~ret14 := is_transmit5_triggered_#res; [L877] activate_threads_~tmp___4~0 := activate_threads_#t~ret14; [L877] havoc activate_threads_#t~ret14; [L879-L883] assume !(0 != activate_threads_~tmp___4~0); [L885] havoc is_transmit6_triggered_#res; [L885] havoc is_transmit6_triggered_~__retres1~6; [L435] havoc is_transmit6_triggered_~__retres1~6; [L438-L447] assume !(1 == ~t6_pc~0); [L448] is_transmit6_triggered_~__retres1~6 := 0; [L450] is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; [L885] activate_threads_#t~ret15 := is_transmit6_triggered_#res; [L885] activate_threads_~tmp___5~0 := activate_threads_#t~ret15; [L885] havoc activate_threads_#t~ret15; [L887-L891] assume !(0 != activate_threads_~tmp___5~0); [L752-L756] assume !(1 == ~M_E~0); [L757-L761] assume !(1 == ~T1_E~0); [L762-L766] assume !(1 == ~T2_E~0); [L767-L771] assume !(1 == ~T3_E~0); [L772-L776] assume !(1 == ~T4_E~0); [L777-L781] assume !(1 == ~T5_E~0); [L782-L786] assume !(1 == ~T6_E~0); [L787-L791] assume !(1 == ~E_M~0); [L792-L796] assume !(1 == ~E_1~0); [L797-L801] assume !(1 == ~E_2~0); [L802-L806] assume !(1 == ~E_3~0); [L807-L811] assume !(1 == ~E_4~0); [L812-L816] assume !(1 == ~E_5~0); [L817-L821] assume !(1 == ~E_6~0); [L1043-L1080] assume !false; [L1046] start_simulation_~kernel_st~0 := 1; [L1047] havoc eval_#t~ret1, eval_#t~nondet2, eval_~tmp_ndt_1~0, eval_#t~nondet3, eval_~tmp_ndt_2~0, eval_#t~nondet4, eval_~tmp_ndt_3~0, eval_#t~nondet5, eval_~tmp_ndt_4~0, eval_#t~nondet6, eval_~tmp_ndt_5~0, eval_#t~nondet7, eval_~tmp_ndt_6~0, eval_#t~nondet8, eval_~tmp_ndt_7~0, eval_~tmp~0; [L551] havoc eval_~tmp~0; [L14] ~m_pc~0 := 0; [L15] ~t1_pc~0 := 0; [L16] ~t2_pc~0 := 0; [L17] ~t3_pc~0 := 0; [L18] ~t4_pc~0 := 0; [L19] ~t5_pc~0 := 0; [L20] ~t6_pc~0 := 0; [L21] ~m_st~0 := 0; [L22] ~t1_st~0 := 0; [L23] ~t2_st~0 := 0; [L24] ~t3_st~0 := 0; [L25] ~t4_st~0 := 0; [L26] ~t5_st~0 := 0; [L27] ~t6_st~0 := 0; [L28] ~m_i~0 := 0; [L29] ~t1_i~0 := 0; [L30] ~t2_i~0 := 0; [L31] ~t3_i~0 := 0; [L32] ~t4_i~0 := 0; [L33] ~t5_i~0 := 0; [L34] ~t6_i~0 := 0; [L35] ~M_E~0 := 2; [L36] ~T1_E~0 := 2; [L37] ~T2_E~0 := 2; [L38] ~T3_E~0 := 2; [L39] ~T4_E~0 := 2; [L40] ~T5_E~0 := 2; [L41] ~T6_E~0 := 2; [L42] ~E_M~0 := 2; [L43] ~E_1~0 := 2; [L44] ~E_2~0 := 2; [L45] ~E_3~0 := 2; [L46] ~E_4~0 := 2; [L47] ~E_5~0 := 2; [L48] ~E_6~0 := 2; [L57] ~token~0 := 0; [L59] ~local~0 := 0; [?] havoc main_#res; [?] havoc main_~__retres1~8; [L1088] havoc main_~__retres1~8; [L998] ~m_i~0 := 1; [L999] ~t1_i~0 := 1; [L1000] ~t2_i~0 := 1; [L1001] ~t3_i~0 := 1; [L1002] ~t4_i~0 := 1; [L1003] ~t5_i~0 := 1; [L1004] ~t6_i~0 := 1; [L1093] havoc start_simulation_#t~ret17, start_simulation_#t~ret18, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1; [L1029] havoc start_simulation_~kernel_st~0; [L1030] havoc start_simulation_~tmp~3; [L1031] havoc start_simulation_~tmp___0~1; [L1035] start_simulation_~kernel_st~0 := 0; [L465] COND TRUE 1 == ~m_i~0 [L466] ~m_st~0 := 0; [L470] COND TRUE 1 == ~t1_i~0 [L471] ~t1_st~0 := 0; [L475] COND TRUE 1 == ~t2_i~0 [L476] ~t2_st~0 := 0; [L480] COND TRUE 1 == ~t3_i~0 [L481] ~t3_st~0 := 0; [L485] COND TRUE 1 == ~t4_i~0 [L486] ~t4_st~0 := 0; [L490] COND TRUE 1 == ~t5_i~0 [L491] ~t5_st~0 := 0; [L495] COND TRUE 1 == ~t6_i~0 [L496] ~t6_st~0 := 0; [L674] COND FALSE !(0 == ~M_E~0) [L679] COND FALSE !(0 == ~T1_E~0) [L684] COND FALSE !(0 == ~T2_E~0) [L689] COND FALSE !(0 == ~T3_E~0) [L694] COND FALSE !(0 == ~T4_E~0) [L699] COND FALSE !(0 == ~T5_E~0) [L704] COND FALSE !(0 == ~T6_E~0) [L709] COND FALSE !(0 == ~E_M~0) [L714] COND FALSE !(0 == ~E_1~0) [L719] COND FALSE !(0 == ~E_2~0) [L724] COND FALSE !(0 == ~E_3~0) [L729] COND FALSE !(0 == ~E_4~0) [L734] COND FALSE !(0 == ~E_5~0) [L739] COND FALSE !(0 == ~E_6~0) [L1039] havoc activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0; [L827] havoc activate_threads_~tmp~1; [L828] havoc activate_threads_~tmp___0~0; [L829] havoc activate_threads_~tmp___1~0; [L830] havoc activate_threads_~tmp___2~0; [L831] havoc activate_threads_~tmp___3~0; [L832] havoc activate_threads_~tmp___4~0; [L833] havoc activate_threads_~tmp___5~0; [L837] havoc is_master_triggered_#res; [L837] havoc is_master_triggered_~__retres1~0; [L321] havoc is_master_triggered_~__retres1~0; [L324] COND FALSE !(1 == ~m_pc~0) [L334] is_master_triggered_~__retres1~0 := 0; [L336] is_master_triggered_#res := is_master_triggered_~__retres1~0; [L837] activate_threads_#t~ret9 := is_master_triggered_#res; [L837] activate_threads_~tmp~1 := activate_threads_#t~ret9; [L837] havoc activate_threads_#t~ret9; [L839-L843] COND FALSE !(0 != activate_threads_~tmp~1) [L845] havoc is_transmit1_triggered_#res; [L845] havoc is_transmit1_triggered_~__retres1~1; [L340] havoc is_transmit1_triggered_~__retres1~1; [L343] COND FALSE !(1 == ~t1_pc~0) [L353] is_transmit1_triggered_~__retres1~1 := 0; [L355] is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; [L845] activate_threads_#t~ret10 := is_transmit1_triggered_#res; [L845] activate_threads_~tmp___0~0 := activate_threads_#t~ret10; [L845] havoc activate_threads_#t~ret10; [L847-L851] COND FALSE !(0 != activate_threads_~tmp___0~0) [L853] havoc is_transmit2_triggered_#res; [L853] havoc is_transmit2_triggered_~__retres1~2; [L359] havoc is_transmit2_triggered_~__retres1~2; [L362] COND FALSE !(1 == ~t2_pc~0) [L372] is_transmit2_triggered_~__retres1~2 := 0; [L374] is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; [L853] activate_threads_#t~ret11 := is_transmit2_triggered_#res; [L853] activate_threads_~tmp___1~0 := activate_threads_#t~ret11; [L853] havoc activate_threads_#t~ret11; [L855-L859] COND FALSE !(0 != activate_threads_~tmp___1~0) [L861] havoc is_transmit3_triggered_#res; [L861] havoc is_transmit3_triggered_~__retres1~3; [L378] havoc is_transmit3_triggered_~__retres1~3; [L381] COND FALSE !(1 == ~t3_pc~0) [L391] is_transmit3_triggered_~__retres1~3 := 0; [L393] is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; [L861] activate_threads_#t~ret12 := is_transmit3_triggered_#res; [L861] activate_threads_~tmp___2~0 := activate_threads_#t~ret12; [L861] havoc activate_threads_#t~ret12; [L863-L867] COND FALSE !(0 != activate_threads_~tmp___2~0) [L869] havoc is_transmit4_triggered_#res; [L869] havoc is_transmit4_triggered_~__retres1~4; [L397] havoc is_transmit4_triggered_~__retres1~4; [L400] COND FALSE !(1 == ~t4_pc~0) [L410] is_transmit4_triggered_~__retres1~4 := 0; [L412] is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; [L869] activate_threads_#t~ret13 := is_transmit4_triggered_#res; [L869] activate_threads_~tmp___3~0 := activate_threads_#t~ret13; [L869] havoc activate_threads_#t~ret13; [L871-L875] COND FALSE !(0 != activate_threads_~tmp___3~0) [L877] havoc is_transmit5_triggered_#res; [L877] havoc is_transmit5_triggered_~__retres1~5; [L416] havoc is_transmit5_triggered_~__retres1~5; [L419] COND FALSE !(1 == ~t5_pc~0) [L429] is_transmit5_triggered_~__retres1~5 := 0; [L431] is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; [L877] activate_threads_#t~ret14 := is_transmit5_triggered_#res; [L877] activate_threads_~tmp___4~0 := activate_threads_#t~ret14; [L877] havoc activate_threads_#t~ret14; [L879-L883] COND FALSE !(0 != activate_threads_~tmp___4~0) [L885] havoc is_transmit6_triggered_#res; [L885] havoc is_transmit6_triggered_~__retres1~6; [L435] havoc is_transmit6_triggered_~__retres1~6; [L438] COND FALSE !(1 == ~t6_pc~0) [L448] is_transmit6_triggered_~__retres1~6 := 0; [L450] is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; [L885] activate_threads_#t~ret15 := is_transmit6_triggered_#res; [L885] activate_threads_~tmp___5~0 := activate_threads_#t~ret15; [L885] havoc activate_threads_#t~ret15; [L887-L891] COND FALSE !(0 != activate_threads_~tmp___5~0) [L752] COND FALSE !(1 == ~M_E~0) [L757] COND FALSE !(1 == ~T1_E~0) [L762] COND FALSE !(1 == ~T2_E~0) [L767] COND FALSE !(1 == ~T3_E~0) [L772] COND FALSE !(1 == ~T4_E~0) [L777] COND FALSE !(1 == ~T5_E~0) [L782] COND FALSE !(1 == ~T6_E~0) [L787] COND FALSE !(1 == ~E_M~0) [L792] COND FALSE !(1 == ~E_1~0) [L797] COND FALSE !(1 == ~E_2~0) [L802] COND FALSE !(1 == ~E_3~0) [L807] COND FALSE !(1 == ~E_4~0) [L812] COND FALSE !(1 == ~E_5~0) [L817] COND FALSE !(1 == ~E_6~0) [L1043-L1080] COND FALSE !(false) [L1046] start_simulation_~kernel_st~0 := 1; [L1047] havoc eval_#t~ret1, eval_#t~nondet2, eval_~tmp_ndt_1~0, eval_#t~nondet3, eval_~tmp_ndt_2~0, eval_#t~nondet4, eval_~tmp_ndt_3~0, eval_#t~nondet5, eval_~tmp_ndt_4~0, eval_#t~nondet6, eval_~tmp_ndt_5~0, eval_#t~nondet7, eval_~tmp_ndt_6~0, eval_#t~nondet8, eval_~tmp_ndt_7~0, eval_~tmp~0; [L551] havoc eval_~tmp~0; ----- ----- class de.uni_freiburg.informatik.ultimate.boogie.procedureinliner.backtranslation.InlinerBacktranslator [L14] ~m_pc~0 := 0; [L15] ~t1_pc~0 := 0; [L16] ~t2_pc~0 := 0; [L17] ~t3_pc~0 := 0; [L18] ~t4_pc~0 := 0; [L19] ~t5_pc~0 := 0; [L20] ~t6_pc~0 := 0; [L21] ~m_st~0 := 0; [L22] ~t1_st~0 := 0; [L23] ~t2_st~0 := 0; [L24] ~t3_st~0 := 0; [L25] ~t4_st~0 := 0; [L26] ~t5_st~0 := 0; [L27] ~t6_st~0 := 0; [L28] ~m_i~0 := 0; [L29] ~t1_i~0 := 0; [L30] ~t2_i~0 := 0; [L31] ~t3_i~0 := 0; [L32] ~t4_i~0 := 0; [L33] ~t5_i~0 := 0; [L34] ~t6_i~0 := 0; [L35] ~M_E~0 := 2; [L36] ~T1_E~0 := 2; [L37] ~T2_E~0 := 2; [L38] ~T3_E~0 := 2; [L39] ~T4_E~0 := 2; [L40] ~T5_E~0 := 2; [L41] ~T6_E~0 := 2; [L42] ~E_M~0 := 2; [L43] ~E_1~0 := 2; [L44] ~E_2~0 := 2; [L45] ~E_3~0 := 2; [L46] ~E_4~0 := 2; [L47] ~E_5~0 := 2; [L48] ~E_6~0 := 2; [L57] ~token~0 := 0; [L59] ~local~0 := 0; [?] havoc main_#res; [?] havoc main_~__retres1~8; [L1088] havoc main_~__retres1~8; [L998] ~m_i~0 := 1; [L999] ~t1_i~0 := 1; [L1000] ~t2_i~0 := 1; [L1001] ~t3_i~0 := 1; [L1002] ~t4_i~0 := 1; [L1003] ~t5_i~0 := 1; [L1004] ~t6_i~0 := 1; [L1093] havoc start_simulation_#t~ret17, start_simulation_#t~ret18, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1; [L1029] havoc start_simulation_~kernel_st~0; [L1030] havoc start_simulation_~tmp~3; [L1031] havoc start_simulation_~tmp___0~1; [L1035] start_simulation_~kernel_st~0 := 0; [L465] COND TRUE 1 == ~m_i~0 [L466] ~m_st~0 := 0; [L470] COND TRUE 1 == ~t1_i~0 [L471] ~t1_st~0 := 0; [L475] COND TRUE 1 == ~t2_i~0 [L476] ~t2_st~0 := 0; [L480] COND TRUE 1 == ~t3_i~0 [L481] ~t3_st~0 := 0; [L485] COND TRUE 1 == ~t4_i~0 [L486] ~t4_st~0 := 0; [L490] COND TRUE 1 == ~t5_i~0 [L491] ~t5_st~0 := 0; [L495] COND TRUE 1 == ~t6_i~0 [L496] ~t6_st~0 := 0; [L674] COND FALSE !(0 == ~M_E~0) [L679] COND FALSE !(0 == ~T1_E~0) [L684] COND FALSE !(0 == ~T2_E~0) [L689] COND FALSE !(0 == ~T3_E~0) [L694] COND FALSE !(0 == ~T4_E~0) [L699] COND FALSE !(0 == ~T5_E~0) [L704] COND FALSE !(0 == ~T6_E~0) [L709] COND FALSE !(0 == ~E_M~0) [L714] COND FALSE !(0 == ~E_1~0) [L719] COND FALSE !(0 == ~E_2~0) [L724] COND FALSE !(0 == ~E_3~0) [L729] COND FALSE !(0 == ~E_4~0) [L734] COND FALSE !(0 == ~E_5~0) [L739] COND FALSE !(0 == ~E_6~0) [L1039] havoc activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0; [L827] havoc activate_threads_~tmp~1; [L828] havoc activate_threads_~tmp___0~0; [L829] havoc activate_threads_~tmp___1~0; [L830] havoc activate_threads_~tmp___2~0; [L831] havoc activate_threads_~tmp___3~0; [L832] havoc activate_threads_~tmp___4~0; [L833] havoc activate_threads_~tmp___5~0; [L837] havoc is_master_triggered_#res; [L837] havoc is_master_triggered_~__retres1~0; [L321] havoc is_master_triggered_~__retres1~0; [L324] COND FALSE !(1 == ~m_pc~0) [L334] is_master_triggered_~__retres1~0 := 0; [L336] is_master_triggered_#res := is_master_triggered_~__retres1~0; [L837] activate_threads_#t~ret9 := is_master_triggered_#res; [L837] activate_threads_~tmp~1 := activate_threads_#t~ret9; [L837] havoc activate_threads_#t~ret9; [L839-L843] COND FALSE !(0 != activate_threads_~tmp~1) [L845] havoc is_transmit1_triggered_#res; [L845] havoc is_transmit1_triggered_~__retres1~1; [L340] havoc is_transmit1_triggered_~__retres1~1; [L343] COND FALSE !(1 == ~t1_pc~0) [L353] is_transmit1_triggered_~__retres1~1 := 0; [L355] is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; [L845] activate_threads_#t~ret10 := is_transmit1_triggered_#res; [L845] activate_threads_~tmp___0~0 := activate_threads_#t~ret10; [L845] havoc activate_threads_#t~ret10; [L847-L851] COND FALSE !(0 != activate_threads_~tmp___0~0) [L853] havoc is_transmit2_triggered_#res; [L853] havoc is_transmit2_triggered_~__retres1~2; [L359] havoc is_transmit2_triggered_~__retres1~2; [L362] COND FALSE !(1 == ~t2_pc~0) [L372] is_transmit2_triggered_~__retres1~2 := 0; [L374] is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; [L853] activate_threads_#t~ret11 := is_transmit2_triggered_#res; [L853] activate_threads_~tmp___1~0 := activate_threads_#t~ret11; [L853] havoc activate_threads_#t~ret11; [L855-L859] COND FALSE !(0 != activate_threads_~tmp___1~0) [L861] havoc is_transmit3_triggered_#res; [L861] havoc is_transmit3_triggered_~__retres1~3; [L378] havoc is_transmit3_triggered_~__retres1~3; [L381] COND FALSE !(1 == ~t3_pc~0) [L391] is_transmit3_triggered_~__retres1~3 := 0; [L393] is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; [L861] activate_threads_#t~ret12 := is_transmit3_triggered_#res; [L861] activate_threads_~tmp___2~0 := activate_threads_#t~ret12; [L861] havoc activate_threads_#t~ret12; [L863-L867] COND FALSE !(0 != activate_threads_~tmp___2~0) [L869] havoc is_transmit4_triggered_#res; [L869] havoc is_transmit4_triggered_~__retres1~4; [L397] havoc is_transmit4_triggered_~__retres1~4; [L400] COND FALSE !(1 == ~t4_pc~0) [L410] is_transmit4_triggered_~__retres1~4 := 0; [L412] is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; [L869] activate_threads_#t~ret13 := is_transmit4_triggered_#res; [L869] activate_threads_~tmp___3~0 := activate_threads_#t~ret13; [L869] havoc activate_threads_#t~ret13; [L871-L875] COND FALSE !(0 != activate_threads_~tmp___3~0) [L877] havoc is_transmit5_triggered_#res; [L877] havoc is_transmit5_triggered_~__retres1~5; [L416] havoc is_transmit5_triggered_~__retres1~5; [L419] COND FALSE !(1 == ~t5_pc~0) [L429] is_transmit5_triggered_~__retres1~5 := 0; [L431] is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; [L877] activate_threads_#t~ret14 := is_transmit5_triggered_#res; [L877] activate_threads_~tmp___4~0 := activate_threads_#t~ret14; [L877] havoc activate_threads_#t~ret14; [L879-L883] COND FALSE !(0 != activate_threads_~tmp___4~0) [L885] havoc is_transmit6_triggered_#res; [L885] havoc is_transmit6_triggered_~__retres1~6; [L435] havoc is_transmit6_triggered_~__retres1~6; [L438] COND FALSE !(1 == ~t6_pc~0) [L448] is_transmit6_triggered_~__retres1~6 := 0; [L450] is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; [L885] activate_threads_#t~ret15 := is_transmit6_triggered_#res; [L885] activate_threads_~tmp___5~0 := activate_threads_#t~ret15; [L885] havoc activate_threads_#t~ret15; [L887-L891] COND FALSE !(0 != activate_threads_~tmp___5~0) [L752] COND FALSE !(1 == ~M_E~0) [L757] COND FALSE !(1 == ~T1_E~0) [L762] COND FALSE !(1 == ~T2_E~0) [L767] COND FALSE !(1 == ~T3_E~0) [L772] COND FALSE !(1 == ~T4_E~0) [L777] COND FALSE !(1 == ~T5_E~0) [L782] COND FALSE !(1 == ~T6_E~0) [L787] COND FALSE !(1 == ~E_M~0) [L792] COND FALSE !(1 == ~E_1~0) [L797] COND FALSE !(1 == ~E_2~0) [L802] COND FALSE !(1 == ~E_3~0) [L807] COND FALSE !(1 == ~E_4~0) [L812] COND FALSE !(1 == ~E_5~0) [L817] COND FALSE !(1 == ~E_6~0) [L1043-L1080] COND FALSE !(false) [L1046] start_simulation_~kernel_st~0 := 1; [L1047] havoc eval_#t~ret1, eval_#t~nondet2, eval_~tmp_ndt_1~0, eval_#t~nondet3, eval_~tmp_ndt_2~0, eval_#t~nondet4, eval_~tmp_ndt_3~0, eval_#t~nondet5, eval_~tmp_ndt_4~0, eval_#t~nondet6, eval_~tmp_ndt_5~0, eval_#t~nondet7, eval_~tmp_ndt_6~0, eval_#t~nondet8, eval_~tmp_ndt_7~0, eval_~tmp~0; [L551] havoc eval_~tmp~0; [L14] ~m_pc~0 := 0; [L15] ~t1_pc~0 := 0; [L16] ~t2_pc~0 := 0; [L17] ~t3_pc~0 := 0; [L18] ~t4_pc~0 := 0; [L19] ~t5_pc~0 := 0; [L20] ~t6_pc~0 := 0; [L21] ~m_st~0 := 0; [L22] ~t1_st~0 := 0; [L23] ~t2_st~0 := 0; [L24] ~t3_st~0 := 0; [L25] ~t4_st~0 := 0; [L26] ~t5_st~0 := 0; [L27] ~t6_st~0 := 0; [L28] ~m_i~0 := 0; [L29] ~t1_i~0 := 0; [L30] ~t2_i~0 := 0; [L31] ~t3_i~0 := 0; [L32] ~t4_i~0 := 0; [L33] ~t5_i~0 := 0; [L34] ~t6_i~0 := 0; [L35] ~M_E~0 := 2; [L36] ~T1_E~0 := 2; [L37] ~T2_E~0 := 2; [L38] ~T3_E~0 := 2; [L39] ~T4_E~0 := 2; [L40] ~T5_E~0 := 2; [L41] ~T6_E~0 := 2; [L42] ~E_M~0 := 2; [L43] ~E_1~0 := 2; [L44] ~E_2~0 := 2; [L45] ~E_3~0 := 2; [L46] ~E_4~0 := 2; [L47] ~E_5~0 := 2; [L48] ~E_6~0 := 2; [L57] ~token~0 := 0; [L59] ~local~0 := 0; [L1088] havoc ~__retres1~8; [L998] ~m_i~0 := 1; [L999] ~t1_i~0 := 1; [L1000] ~t2_i~0 := 1; [L1001] ~t3_i~0 := 1; [L1002] ~t4_i~0 := 1; [L1003] ~t5_i~0 := 1; [L1004] ~t6_i~0 := 1; [L1029] havoc ~kernel_st~0; [L1030] havoc ~tmp~3; [L1031] havoc ~tmp___0~1; [L1035] ~kernel_st~0 := 0; [L465] COND TRUE 1 == ~m_i~0 [L466] ~m_st~0 := 0; [L470] COND TRUE 1 == ~t1_i~0 [L471] ~t1_st~0 := 0; [L475] COND TRUE 1 == ~t2_i~0 [L476] ~t2_st~0 := 0; [L480] COND TRUE 1 == ~t3_i~0 [L481] ~t3_st~0 := 0; [L485] COND TRUE 1 == ~t4_i~0 [L486] ~t4_st~0 := 0; [L490] COND TRUE 1 == ~t5_i~0 [L491] ~t5_st~0 := 0; [L495] COND TRUE 1 == ~t6_i~0 [L496] ~t6_st~0 := 0; [L674] COND FALSE !(0 == ~M_E~0) [L679] COND FALSE !(0 == ~T1_E~0) [L684] COND FALSE !(0 == ~T2_E~0) [L689] COND FALSE !(0 == ~T3_E~0) [L694] COND FALSE !(0 == ~T4_E~0) [L699] COND FALSE !(0 == ~T5_E~0) [L704] COND FALSE !(0 == ~T6_E~0) [L709] COND FALSE !(0 == ~E_M~0) [L714] COND FALSE !(0 == ~E_1~0) [L719] COND FALSE !(0 == ~E_2~0) [L724] COND FALSE !(0 == ~E_3~0) [L729] COND FALSE !(0 == ~E_4~0) [L734] COND FALSE !(0 == ~E_5~0) [L739] COND FALSE !(0 == ~E_6~0) [L827] havoc ~tmp~1; [L828] havoc ~tmp___0~0; [L829] havoc ~tmp___1~0; [L830] havoc ~tmp___2~0; [L831] havoc ~tmp___3~0; [L832] havoc ~tmp___4~0; [L833] havoc ~tmp___5~0; [L321] havoc ~__retres1~0; [L324] COND FALSE !(1 == ~m_pc~0) [L334] ~__retres1~0 := 0; [L336] #res := ~__retres1~0; [L837] ~tmp~1 := #t~ret9; [L837] havoc #t~ret9; [L839-L843] COND FALSE !(0 != ~tmp~1) [L340] havoc ~__retres1~1; [L343] COND FALSE !(1 == ~t1_pc~0) [L353] ~__retres1~1 := 0; [L355] #res := ~__retres1~1; [L845] ~tmp___0~0 := #t~ret10; [L845] havoc #t~ret10; [L847-L851] COND FALSE !(0 != ~tmp___0~0) [L359] havoc ~__retres1~2; [L362] COND FALSE !(1 == ~t2_pc~0) [L372] ~__retres1~2 := 0; [L374] #res := ~__retres1~2; [L853] ~tmp___1~0 := #t~ret11; [L853] havoc #t~ret11; [L855-L859] COND FALSE !(0 != ~tmp___1~0) [L378] havoc ~__retres1~3; [L381] COND FALSE !(1 == ~t3_pc~0) [L391] ~__retres1~3 := 0; [L393] #res := ~__retres1~3; [L861] ~tmp___2~0 := #t~ret12; [L861] havoc #t~ret12; [L863-L867] COND FALSE !(0 != ~tmp___2~0) [L397] havoc ~__retres1~4; [L400] COND FALSE !(1 == ~t4_pc~0) [L410] ~__retres1~4 := 0; [L412] #res := ~__retres1~4; [L869] ~tmp___3~0 := #t~ret13; [L869] havoc #t~ret13; [L871-L875] COND FALSE !(0 != ~tmp___3~0) [L416] havoc ~__retres1~5; [L419] COND FALSE !(1 == ~t5_pc~0) [L429] ~__retres1~5 := 0; [L431] #res := ~__retres1~5; [L877] ~tmp___4~0 := #t~ret14; [L877] havoc #t~ret14; [L879-L883] COND FALSE !(0 != ~tmp___4~0) [L435] havoc ~__retres1~6; [L438] COND FALSE !(1 == ~t6_pc~0) [L448] ~__retres1~6 := 0; [L450] #res := ~__retres1~6; [L885] ~tmp___5~0 := #t~ret15; [L885] havoc #t~ret15; [L887-L891] COND FALSE !(0 != ~tmp___5~0) [L752] COND FALSE !(1 == ~M_E~0) [L757] COND FALSE !(1 == ~T1_E~0) [L762] COND FALSE !(1 == ~T2_E~0) [L767] COND FALSE !(1 == ~T3_E~0) [L772] COND FALSE !(1 == ~T4_E~0) [L777] COND FALSE !(1 == ~T5_E~0) [L782] COND FALSE !(1 == ~T6_E~0) [L787] COND FALSE !(1 == ~E_M~0) [L792] COND FALSE !(1 == ~E_1~0) [L797] COND FALSE !(1 == ~E_2~0) [L802] COND FALSE !(1 == ~E_3~0) [L807] COND FALSE !(1 == ~E_4~0) [L812] COND FALSE !(1 == ~E_5~0) [L817] COND FALSE !(1 == ~E_6~0) [L1043-L1080] COND FALSE !(false) [L1046] ~kernel_st~0 := 1; [L551] havoc ~tmp~0; ----- ----- class de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.CACSL2BoogieBacktranslator [L14] ~m_pc~0 := 0; [L15] ~t1_pc~0 := 0; [L16] ~t2_pc~0 := 0; [L17] ~t3_pc~0 := 0; [L18] ~t4_pc~0 := 0; [L19] ~t5_pc~0 := 0; [L20] ~t6_pc~0 := 0; [L21] ~m_st~0 := 0; [L22] ~t1_st~0 := 0; [L23] ~t2_st~0 := 0; [L24] ~t3_st~0 := 0; [L25] ~t4_st~0 := 0; [L26] ~t5_st~0 := 0; [L27] ~t6_st~0 := 0; [L28] ~m_i~0 := 0; [L29] ~t1_i~0 := 0; [L30] ~t2_i~0 := 0; [L31] ~t3_i~0 := 0; [L32] ~t4_i~0 := 0; [L33] ~t5_i~0 := 0; [L34] ~t6_i~0 := 0; [L35] ~M_E~0 := 2; [L36] ~T1_E~0 := 2; [L37] ~T2_E~0 := 2; [L38] ~T3_E~0 := 2; [L39] ~T4_E~0 := 2; [L40] ~T5_E~0 := 2; [L41] ~T6_E~0 := 2; [L42] ~E_M~0 := 2; [L43] ~E_1~0 := 2; [L44] ~E_2~0 := 2; [L45] ~E_3~0 := 2; [L46] ~E_4~0 := 2; [L47] ~E_5~0 := 2; [L48] ~E_6~0 := 2; [L57] ~token~0 := 0; [L59] ~local~0 := 0; [L1088] havoc ~__retres1~8; [L998] ~m_i~0 := 1; [L999] ~t1_i~0 := 1; [L1000] ~t2_i~0 := 1; [L1001] ~t3_i~0 := 1; [L1002] ~t4_i~0 := 1; [L1003] ~t5_i~0 := 1; [L1004] ~t6_i~0 := 1; [L1029] havoc ~kernel_st~0; [L1030] havoc ~tmp~3; [L1031] havoc ~tmp___0~1; [L1035] ~kernel_st~0 := 0; [L465] COND TRUE 1 == ~m_i~0 [L466] ~m_st~0 := 0; [L470] COND TRUE 1 == ~t1_i~0 [L471] ~t1_st~0 := 0; [L475] COND TRUE 1 == ~t2_i~0 [L476] ~t2_st~0 := 0; [L480] COND TRUE 1 == ~t3_i~0 [L481] ~t3_st~0 := 0; [L485] COND TRUE 1 == ~t4_i~0 [L486] ~t4_st~0 := 0; [L490] COND TRUE 1 == ~t5_i~0 [L491] ~t5_st~0 := 0; [L495] COND TRUE 1 == ~t6_i~0 [L496] ~t6_st~0 := 0; [L674] COND FALSE !(0 == ~M_E~0) [L679] COND FALSE !(0 == ~T1_E~0) [L684] COND FALSE !(0 == ~T2_E~0) [L689] COND FALSE !(0 == ~T3_E~0) [L694] COND FALSE !(0 == ~T4_E~0) [L699] COND FALSE !(0 == ~T5_E~0) [L704] COND FALSE !(0 == ~T6_E~0) [L709] COND FALSE !(0 == ~E_M~0) [L714] COND FALSE !(0 == ~E_1~0) [L719] COND FALSE !(0 == ~E_2~0) [L724] COND FALSE !(0 == ~E_3~0) [L729] COND FALSE !(0 == ~E_4~0) [L734] COND FALSE !(0 == ~E_5~0) [L739] COND FALSE !(0 == ~E_6~0) [L827] havoc ~tmp~1; [L828] havoc ~tmp___0~0; [L829] havoc ~tmp___1~0; [L830] havoc ~tmp___2~0; [L831] havoc ~tmp___3~0; [L832] havoc ~tmp___4~0; [L833] havoc ~tmp___5~0; [L321] havoc ~__retres1~0; [L324] COND FALSE !(1 == ~m_pc~0) [L334] ~__retres1~0 := 0; [L336] #res := ~__retres1~0; [L837] ~tmp~1 := #t~ret9; [L837] havoc #t~ret9; [L839-L843] COND FALSE !(0 != ~tmp~1) [L340] havoc ~__retres1~1; [L343] COND FALSE !(1 == ~t1_pc~0) [L353] ~__retres1~1 := 0; [L355] #res := ~__retres1~1; [L845] ~tmp___0~0 := #t~ret10; [L845] havoc #t~ret10; [L847-L851] COND FALSE !(0 != ~tmp___0~0) [L359] havoc ~__retres1~2; [L362] COND FALSE !(1 == ~t2_pc~0) [L372] ~__retres1~2 := 0; [L374] #res := ~__retres1~2; [L853] ~tmp___1~0 := #t~ret11; [L853] havoc #t~ret11; [L855-L859] COND FALSE !(0 != ~tmp___1~0) [L378] havoc ~__retres1~3; [L381] COND FALSE !(1 == ~t3_pc~0) [L391] ~__retres1~3 := 0; [L393] #res := ~__retres1~3; [L861] ~tmp___2~0 := #t~ret12; [L861] havoc #t~ret12; [L863-L867] COND FALSE !(0 != ~tmp___2~0) [L397] havoc ~__retres1~4; [L400] COND FALSE !(1 == ~t4_pc~0) [L410] ~__retres1~4 := 0; [L412] #res := ~__retres1~4; [L869] ~tmp___3~0 := #t~ret13; [L869] havoc #t~ret13; [L871-L875] COND FALSE !(0 != ~tmp___3~0) [L416] havoc ~__retres1~5; [L419] COND FALSE !(1 == ~t5_pc~0) [L429] ~__retres1~5 := 0; [L431] #res := ~__retres1~5; [L877] ~tmp___4~0 := #t~ret14; [L877] havoc #t~ret14; [L879-L883] COND FALSE !(0 != ~tmp___4~0) [L435] havoc ~__retres1~6; [L438] COND FALSE !(1 == ~t6_pc~0) [L448] ~__retres1~6 := 0; [L450] #res := ~__retres1~6; [L885] ~tmp___5~0 := #t~ret15; [L885] havoc #t~ret15; [L887-L891] COND FALSE !(0 != ~tmp___5~0) [L752] COND FALSE !(1 == ~M_E~0) [L757] COND FALSE !(1 == ~T1_E~0) [L762] COND FALSE !(1 == ~T2_E~0) [L767] COND FALSE !(1 == ~T3_E~0) [L772] COND FALSE !(1 == ~T4_E~0) [L777] COND FALSE !(1 == ~T5_E~0) [L782] COND FALSE !(1 == ~T6_E~0) [L787] COND FALSE !(1 == ~E_M~0) [L792] COND FALSE !(1 == ~E_1~0) [L797] COND FALSE !(1 == ~E_2~0) [L802] COND FALSE !(1 == ~E_3~0) [L807] COND FALSE !(1 == ~E_4~0) [L812] COND FALSE !(1 == ~E_5~0) [L817] COND FALSE !(1 == ~E_6~0) [L1043-L1080] COND FALSE !(false) [L1046] ~kernel_st~0 := 1; [L551] havoc ~tmp~0; [L14] int m_pc = 0; [L15] int t1_pc = 0; [L16] int t2_pc = 0; [L17] int t3_pc = 0; [L18] int t4_pc = 0; [L19] int t5_pc = 0; [L20] int t6_pc = 0; [L21] int m_st ; [L22] int t1_st ; [L23] int t2_st ; [L24] int t3_st ; [L25] int t4_st ; [L26] int t5_st ; [L27] int t6_st ; [L28] int m_i ; [L29] int t1_i ; [L30] int t2_i ; [L31] int t3_i ; [L32] int t4_i ; [L33] int t5_i ; [L34] int t6_i ; [L35] int M_E = 2; [L36] int T1_E = 2; [L37] int T2_E = 2; [L38] int T3_E = 2; [L39] int T4_E = 2; [L40] int T5_E = 2; [L41] int T6_E = 2; [L42] int E_M = 2; [L43] int E_1 = 2; [L44] int E_2 = 2; [L45] int E_3 = 2; [L46] int E_4 = 2; [L47] int E_5 = 2; [L48] int E_6 = 2; [L57] int token ; [L59] int local ; [L1088] int __retres1 ; [L998] m_i = 1 [L999] t1_i = 1 [L1000] t2_i = 1 [L1001] t3_i = 1 [L1002] t4_i = 1 [L1003] t5_i = 1 [L1004] t6_i = 1 [L1029] int kernel_st ; [L1030] int tmp ; [L1031] int tmp___0 ; [L1035] kernel_st = 0 [L465] COND TRUE m_i == 1 [L466] m_st = 0 [L470] COND TRUE t1_i == 1 [L471] t1_st = 0 [L475] COND TRUE t2_i == 1 [L476] t2_st = 0 [L480] COND TRUE t3_i == 1 [L481] t3_st = 0 [L485] COND TRUE t4_i == 1 [L486] t4_st = 0 [L490] COND TRUE t5_i == 1 [L491] t5_st = 0 [L495] COND TRUE t6_i == 1 [L496] t6_st = 0 [L674] COND FALSE !(M_E == 0) [L679] COND FALSE !(T1_E == 0) [L684] COND FALSE !(T2_E == 0) [L689] COND FALSE !(T3_E == 0) [L694] COND FALSE !(T4_E == 0) [L699] COND FALSE !(T5_E == 0) [L704] COND FALSE !(T6_E == 0) [L709] COND FALSE !(E_M == 0) [L714] COND FALSE !(E_1 == 0) [L719] COND FALSE !(E_2 == 0) [L724] COND FALSE !(E_3 == 0) [L729] COND FALSE !(E_4 == 0) [L734] COND FALSE !(E_5 == 0) [L739] COND FALSE !(E_6 == 0) [L827] int tmp ; [L828] int tmp___0 ; [L829] int tmp___1 ; [L830] int tmp___2 ; [L831] int tmp___3 ; [L832] int tmp___4 ; [L833] int tmp___5 ; [L321] int __retres1 ; [L324] COND FALSE !(m_pc == 1) [L334] __retres1 = 0 [L336] return (__retres1); [L837] tmp = is_master_triggered() [L839] COND FALSE !(\read(tmp)) [L340] int __retres1 ; [L343] COND FALSE !(t1_pc == 1) [L353] __retres1 = 0 [L355] return (__retres1); [L845] tmp___0 = is_transmit1_triggered() [L847] COND FALSE !(\read(tmp___0)) [L359] int __retres1 ; [L362] COND FALSE !(t2_pc == 1) [L372] __retres1 = 0 [L374] return (__retres1); [L853] tmp___1 = is_transmit2_triggered() [L855] COND FALSE !(\read(tmp___1)) [L378] int __retres1 ; [L381] COND FALSE !(t3_pc == 1) [L391] __retres1 = 0 [L393] return (__retres1); [L861] tmp___2 = is_transmit3_triggered() [L863] COND FALSE !(\read(tmp___2)) [L397] int __retres1 ; [L400] COND FALSE !(t4_pc == 1) [L410] __retres1 = 0 [L412] return (__retres1); [L869] tmp___3 = is_transmit4_triggered() [L871] COND FALSE !(\read(tmp___3)) [L416] int __retres1 ; [L419] COND FALSE !(t5_pc == 1) [L429] __retres1 = 0 [L431] return (__retres1); [L877] tmp___4 = is_transmit5_triggered() [L879] COND FALSE !(\read(tmp___4)) [L435] int __retres1 ; [L438] COND FALSE !(t6_pc == 1) [L448] __retres1 = 0 [L450] return (__retres1); [L885] tmp___5 = is_transmit6_triggered() [L887] COND FALSE !(\read(tmp___5)) [L752] COND FALSE !(M_E == 1) [L757] COND FALSE !(T1_E == 1) [L762] COND FALSE !(T2_E == 1) [L767] COND FALSE !(T3_E == 1) [L772] COND FALSE !(T4_E == 1) [L777] COND FALSE !(T5_E == 1) [L782] COND FALSE !(T6_E == 1) [L787] COND FALSE !(E_M == 1) [L792] COND FALSE !(E_1 == 1) [L797] COND FALSE !(E_2 == 1) [L802] COND FALSE !(E_3 == 1) [L807] COND FALSE !(E_4 == 1) [L812] COND FALSE !(E_5 == 1) [L817] COND FALSE !(E_6 == 1) [L1043] COND TRUE 1 [L1046] kernel_st = 1 [L551] int tmp ; ----- ----- class de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder.RCFGBacktranslator [?] assume !false; [?] havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~7;havoc exists_runnable_thread_~__retres1~7; [?] assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7 := 1; [?] exists_runnable_thread_#res := exists_runnable_thread_~__retres1~7; [?] eval_#t~ret1 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret1;havoc eval_#t~ret1; [?] assume 0 != eval_~tmp~0; [?] assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0;eval_~tmp_ndt_1~0 := eval_#t~nondet2;havoc eval_#t~nondet2; [?] assume !(0 != eval_~tmp_ndt_1~0); [?] assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0;eval_~tmp_ndt_2~0 := eval_#t~nondet3;havoc eval_#t~nondet3; [?] assume !(0 != eval_~tmp_ndt_2~0); [?] assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0;eval_~tmp_ndt_3~0 := eval_#t~nondet4;havoc eval_#t~nondet4; [?] assume !(0 != eval_~tmp_ndt_3~0); [?] assume 0 == ~t3_st~0;havoc eval_~tmp_ndt_4~0;eval_~tmp_ndt_4~0 := eval_#t~nondet5;havoc eval_#t~nondet5; [?] assume !(0 != eval_~tmp_ndt_4~0); [?] assume 0 == ~t4_st~0;havoc eval_~tmp_ndt_5~0;eval_~tmp_ndt_5~0 := eval_#t~nondet6;havoc eval_#t~nondet6; [?] assume !(0 != eval_~tmp_ndt_5~0); [?] assume 0 == ~t5_st~0;havoc eval_~tmp_ndt_6~0;eval_~tmp_ndt_6~0 := eval_#t~nondet7;havoc eval_#t~nondet7; [?] assume !(0 != eval_~tmp_ndt_6~0); [?] assume 0 == ~t6_st~0;havoc eval_~tmp_ndt_7~0;eval_~tmp_ndt_7~0 := eval_#t~nondet8;havoc eval_#t~nondet8; [?] assume !(0 != eval_~tmp_ndt_7~0); [L555-L663] assume !false; [L558] havoc exists_runnable_thread_#res; [L558] havoc exists_runnable_thread_~__retres1~7; [L505] havoc exists_runnable_thread_~__retres1~7; [L508-L543] assume 0 == ~m_st~0; [L509] exists_runnable_thread_~__retres1~7 := 1; [L546] exists_runnable_thread_#res := exists_runnable_thread_~__retres1~7; [L558] eval_#t~ret1 := exists_runnable_thread_#res; [L558] eval_~tmp~0 := eval_#t~ret1; [L558] havoc eval_#t~ret1; [L560-L564] assume 0 != eval_~tmp~0; [L565-L578] assume 0 == ~m_st~0; [L566] havoc eval_~tmp_ndt_1~0; [L567] eval_~tmp_ndt_1~0 := eval_#t~nondet2; [L567] havoc eval_#t~nondet2; [L568-L575] assume !(0 != eval_~tmp_ndt_1~0); [L579-L592] assume 0 == ~t1_st~0; [L580] havoc eval_~tmp_ndt_2~0; [L581] eval_~tmp_ndt_2~0 := eval_#t~nondet3; [L581] havoc eval_#t~nondet3; [L582-L589] assume !(0 != eval_~tmp_ndt_2~0); [L593-L606] assume 0 == ~t2_st~0; [L594] havoc eval_~tmp_ndt_3~0; [L595] eval_~tmp_ndt_3~0 := eval_#t~nondet4; [L595] havoc eval_#t~nondet4; [L596-L603] assume !(0 != eval_~tmp_ndt_3~0); [L607-L620] assume 0 == ~t3_st~0; [L608] havoc eval_~tmp_ndt_4~0; [L609] eval_~tmp_ndt_4~0 := eval_#t~nondet5; [L609] havoc eval_#t~nondet5; [L610-L617] assume !(0 != eval_~tmp_ndt_4~0); [L621-L634] assume 0 == ~t4_st~0; [L622] havoc eval_~tmp_ndt_5~0; [L623] eval_~tmp_ndt_5~0 := eval_#t~nondet6; [L623] havoc eval_#t~nondet6; [L624-L631] assume !(0 != eval_~tmp_ndt_5~0); [L635-L648] assume 0 == ~t5_st~0; [L636] havoc eval_~tmp_ndt_6~0; [L637] eval_~tmp_ndt_6~0 := eval_#t~nondet7; [L637] havoc eval_#t~nondet7; [L638-L645] assume !(0 != eval_~tmp_ndt_6~0); [L649-L662] assume 0 == ~t6_st~0; [L650] havoc eval_~tmp_ndt_7~0; [L651] eval_~tmp_ndt_7~0 := eval_#t~nondet8; [L651] havoc eval_#t~nondet8; [L652-L659] assume !(0 != eval_~tmp_ndt_7~0); ----- ----- class de.uni_freiburg.informatik.ultimate.boogie.preprocessor.BoogiePreprocessorBacktranslator [L555-L663] assume !false; [L558] havoc exists_runnable_thread_#res; [L558] havoc exists_runnable_thread_~__retres1~7; [L505] havoc exists_runnable_thread_~__retres1~7; [L508-L543] assume 0 == ~m_st~0; [L509] exists_runnable_thread_~__retres1~7 := 1; [L546] exists_runnable_thread_#res := exists_runnable_thread_~__retres1~7; [L558] eval_#t~ret1 := exists_runnable_thread_#res; [L558] eval_~tmp~0 := eval_#t~ret1; [L558] havoc eval_#t~ret1; [L560-L564] assume 0 != eval_~tmp~0; [L565-L578] assume 0 == ~m_st~0; [L566] havoc eval_~tmp_ndt_1~0; [L567] eval_~tmp_ndt_1~0 := eval_#t~nondet2; [L567] havoc eval_#t~nondet2; [L568-L575] assume !(0 != eval_~tmp_ndt_1~0); [L579-L592] assume 0 == ~t1_st~0; [L580] havoc eval_~tmp_ndt_2~0; [L581] eval_~tmp_ndt_2~0 := eval_#t~nondet3; [L581] havoc eval_#t~nondet3; [L582-L589] assume !(0 != eval_~tmp_ndt_2~0); [L593-L606] assume 0 == ~t2_st~0; [L594] havoc eval_~tmp_ndt_3~0; [L595] eval_~tmp_ndt_3~0 := eval_#t~nondet4; [L595] havoc eval_#t~nondet4; [L596-L603] assume !(0 != eval_~tmp_ndt_3~0); [L607-L620] assume 0 == ~t3_st~0; [L608] havoc eval_~tmp_ndt_4~0; [L609] eval_~tmp_ndt_4~0 := eval_#t~nondet5; [L609] havoc eval_#t~nondet5; [L610-L617] assume !(0 != eval_~tmp_ndt_4~0); [L621-L634] assume 0 == ~t4_st~0; [L622] havoc eval_~tmp_ndt_5~0; [L623] eval_~tmp_ndt_5~0 := eval_#t~nondet6; [L623] havoc eval_#t~nondet6; [L624-L631] assume !(0 != eval_~tmp_ndt_5~0); [L635-L648] assume 0 == ~t5_st~0; [L636] havoc eval_~tmp_ndt_6~0; [L637] eval_~tmp_ndt_6~0 := eval_#t~nondet7; [L637] havoc eval_#t~nondet7; [L638-L645] assume !(0 != eval_~tmp_ndt_6~0); [L649-L662] assume 0 == ~t6_st~0; [L650] havoc eval_~tmp_ndt_7~0; [L651] eval_~tmp_ndt_7~0 := eval_#t~nondet8; [L651] havoc eval_#t~nondet8; [L652-L659] assume !(0 != eval_~tmp_ndt_7~0); [L555-L663] COND FALSE !(false) [L558] havoc exists_runnable_thread_#res; [L558] havoc exists_runnable_thread_~__retres1~7; [L505] havoc exists_runnable_thread_~__retres1~7; [L508] COND TRUE 0 == ~m_st~0 [L509] exists_runnable_thread_~__retres1~7 := 1; [L546] exists_runnable_thread_#res := exists_runnable_thread_~__retres1~7; [L558] eval_#t~ret1 := exists_runnable_thread_#res; [L558] eval_~tmp~0 := eval_#t~ret1; [L558] havoc eval_#t~ret1; [L560-L564] COND TRUE 0 != eval_~tmp~0 [L565] COND TRUE 0 == ~m_st~0 [L566] havoc eval_~tmp_ndt_1~0; [L567] eval_~tmp_ndt_1~0 := eval_#t~nondet2; [L567] havoc eval_#t~nondet2; [L568-L575] COND FALSE !(0 != eval_~tmp_ndt_1~0) [L579] COND TRUE 0 == ~t1_st~0 [L580] havoc eval_~tmp_ndt_2~0; [L581] eval_~tmp_ndt_2~0 := eval_#t~nondet3; [L581] havoc eval_#t~nondet3; [L582-L589] COND FALSE !(0 != eval_~tmp_ndt_2~0) [L593] COND TRUE 0 == ~t2_st~0 [L594] havoc eval_~tmp_ndt_3~0; [L595] eval_~tmp_ndt_3~0 := eval_#t~nondet4; [L595] havoc eval_#t~nondet4; [L596-L603] COND FALSE !(0 != eval_~tmp_ndt_3~0) [L607] COND TRUE 0 == ~t3_st~0 [L608] havoc eval_~tmp_ndt_4~0; [L609] eval_~tmp_ndt_4~0 := eval_#t~nondet5; [L609] havoc eval_#t~nondet5; [L610-L617] COND FALSE !(0 != eval_~tmp_ndt_4~0) [L621] COND TRUE 0 == ~t4_st~0 [L622] havoc eval_~tmp_ndt_5~0; [L623] eval_~tmp_ndt_5~0 := eval_#t~nondet6; [L623] havoc eval_#t~nondet6; [L624-L631] COND FALSE !(0 != eval_~tmp_ndt_5~0) [L635] COND TRUE 0 == ~t5_st~0 [L636] havoc eval_~tmp_ndt_6~0; [L637] eval_~tmp_ndt_6~0 := eval_#t~nondet7; [L637] havoc eval_#t~nondet7; [L638-L645] COND FALSE !(0 != eval_~tmp_ndt_6~0) [L649] COND TRUE 0 == ~t6_st~0 [L650] havoc eval_~tmp_ndt_7~0; [L651] eval_~tmp_ndt_7~0 := eval_#t~nondet8; [L651] havoc eval_#t~nondet8; [L652-L659] COND FALSE !(0 != eval_~tmp_ndt_7~0) ----- ----- class de.uni_freiburg.informatik.ultimate.boogie.procedureinliner.backtranslation.InlinerBacktranslator [L555-L663] COND FALSE !(false) [L558] havoc exists_runnable_thread_#res; [L558] havoc exists_runnable_thread_~__retres1~7; [L505] havoc exists_runnable_thread_~__retres1~7; [L508] COND TRUE 0 == ~m_st~0 [L509] exists_runnable_thread_~__retres1~7 := 1; [L546] exists_runnable_thread_#res := exists_runnable_thread_~__retres1~7; [L558] eval_#t~ret1 := exists_runnable_thread_#res; [L558] eval_~tmp~0 := eval_#t~ret1; [L558] havoc eval_#t~ret1; [L560-L564] COND TRUE 0 != eval_~tmp~0 [L565] COND TRUE 0 == ~m_st~0 [L566] havoc eval_~tmp_ndt_1~0; [L567] eval_~tmp_ndt_1~0 := eval_#t~nondet2; [L567] havoc eval_#t~nondet2; [L568-L575] COND FALSE !(0 != eval_~tmp_ndt_1~0) [L579] COND TRUE 0 == ~t1_st~0 [L580] havoc eval_~tmp_ndt_2~0; [L581] eval_~tmp_ndt_2~0 := eval_#t~nondet3; [L581] havoc eval_#t~nondet3; [L582-L589] COND FALSE !(0 != eval_~tmp_ndt_2~0) [L593] COND TRUE 0 == ~t2_st~0 [L594] havoc eval_~tmp_ndt_3~0; [L595] eval_~tmp_ndt_3~0 := eval_#t~nondet4; [L595] havoc eval_#t~nondet4; [L596-L603] COND FALSE !(0 != eval_~tmp_ndt_3~0) [L607] COND TRUE 0 == ~t3_st~0 [L608] havoc eval_~tmp_ndt_4~0; [L609] eval_~tmp_ndt_4~0 := eval_#t~nondet5; [L609] havoc eval_#t~nondet5; [L610-L617] COND FALSE !(0 != eval_~tmp_ndt_4~0) [L621] COND TRUE 0 == ~t4_st~0 [L622] havoc eval_~tmp_ndt_5~0; [L623] eval_~tmp_ndt_5~0 := eval_#t~nondet6; [L623] havoc eval_#t~nondet6; [L624-L631] COND FALSE !(0 != eval_~tmp_ndt_5~0) [L635] COND TRUE 0 == ~t5_st~0 [L636] havoc eval_~tmp_ndt_6~0; [L637] eval_~tmp_ndt_6~0 := eval_#t~nondet7; [L637] havoc eval_#t~nondet7; [L638-L645] COND FALSE !(0 != eval_~tmp_ndt_6~0) [L649] COND TRUE 0 == ~t6_st~0 [L650] havoc eval_~tmp_ndt_7~0; [L651] eval_~tmp_ndt_7~0 := eval_#t~nondet8; [L651] havoc eval_#t~nondet8; [L652-L659] COND FALSE !(0 != eval_~tmp_ndt_7~0) [L555-L663] COND FALSE !(false) [L505] havoc ~__retres1~7; [L508] COND TRUE 0 == ~m_st~0 [L509] ~__retres1~7 := 1; [L546] #res := ~__retres1~7; [L558] ~tmp~0 := #t~ret1; [L558] havoc #t~ret1; [L560-L564] COND TRUE 0 != ~tmp~0 [L565] COND TRUE 0 == ~m_st~0 [L566] havoc ~tmp_ndt_1~0; [L567] ~tmp_ndt_1~0 := #t~nondet2; [L567] havoc #t~nondet2; [L568-L575] COND FALSE !(0 != ~tmp_ndt_1~0) [L579] COND TRUE 0 == ~t1_st~0 [L580] havoc ~tmp_ndt_2~0; [L581] ~tmp_ndt_2~0 := #t~nondet3; [L581] havoc #t~nondet3; [L582-L589] COND FALSE !(0 != ~tmp_ndt_2~0) [L593] COND TRUE 0 == ~t2_st~0 [L594] havoc ~tmp_ndt_3~0; [L595] ~tmp_ndt_3~0 := #t~nondet4; [L595] havoc #t~nondet4; [L596-L603] COND FALSE !(0 != ~tmp_ndt_3~0) [L607] COND TRUE 0 == ~t3_st~0 [L608] havoc ~tmp_ndt_4~0; [L609] ~tmp_ndt_4~0 := #t~nondet5; [L609] havoc #t~nondet5; [L610-L617] COND FALSE !(0 != ~tmp_ndt_4~0) [L621] COND TRUE 0 == ~t4_st~0 [L622] havoc ~tmp_ndt_5~0; [L623] ~tmp_ndt_5~0 := #t~nondet6; [L623] havoc #t~nondet6; [L624-L631] COND FALSE !(0 != ~tmp_ndt_5~0) [L635] COND TRUE 0 == ~t5_st~0 [L636] havoc ~tmp_ndt_6~0; [L637] ~tmp_ndt_6~0 := #t~nondet7; [L637] havoc #t~nondet7; [L638-L645] COND FALSE !(0 != ~tmp_ndt_6~0) [L649] COND TRUE 0 == ~t6_st~0 [L650] havoc ~tmp_ndt_7~0; [L651] ~tmp_ndt_7~0 := #t~nondet8; [L651] havoc #t~nondet8; [L652-L659] COND FALSE !(0 != ~tmp_ndt_7~0) ----- ----- class de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.CACSL2BoogieBacktranslator [L555-L663] COND FALSE !(false) [L505] havoc ~__retres1~7; [L508] COND TRUE 0 == ~m_st~0 [L509] ~__retres1~7 := 1; [L546] #res := ~__retres1~7; [L558] ~tmp~0 := #t~ret1; [L558] havoc #t~ret1; [L560-L564] COND TRUE 0 != ~tmp~0 [L565] COND TRUE 0 == ~m_st~0 [L566] havoc ~tmp_ndt_1~0; [L567] ~tmp_ndt_1~0 := #t~nondet2; [L567] havoc #t~nondet2; [L568-L575] COND FALSE !(0 != ~tmp_ndt_1~0) [L579] COND TRUE 0 == ~t1_st~0 [L580] havoc ~tmp_ndt_2~0; [L581] ~tmp_ndt_2~0 := #t~nondet3; [L581] havoc #t~nondet3; [L582-L589] COND FALSE !(0 != ~tmp_ndt_2~0) [L593] COND TRUE 0 == ~t2_st~0 [L594] havoc ~tmp_ndt_3~0; [L595] ~tmp_ndt_3~0 := #t~nondet4; [L595] havoc #t~nondet4; [L596-L603] COND FALSE !(0 != ~tmp_ndt_3~0) [L607] COND TRUE 0 == ~t3_st~0 [L608] havoc ~tmp_ndt_4~0; [L609] ~tmp_ndt_4~0 := #t~nondet5; [L609] havoc #t~nondet5; [L610-L617] COND FALSE !(0 != ~tmp_ndt_4~0) [L621] COND TRUE 0 == ~t4_st~0 [L622] havoc ~tmp_ndt_5~0; [L623] ~tmp_ndt_5~0 := #t~nondet6; [L623] havoc #t~nondet6; [L624-L631] COND FALSE !(0 != ~tmp_ndt_5~0) [L635] COND TRUE 0 == ~t5_st~0 [L636] havoc ~tmp_ndt_6~0; [L637] ~tmp_ndt_6~0 := #t~nondet7; [L637] havoc #t~nondet7; [L638-L645] COND FALSE !(0 != ~tmp_ndt_6~0) [L649] COND TRUE 0 == ~t6_st~0 [L650] havoc ~tmp_ndt_7~0; [L651] ~tmp_ndt_7~0 := #t~nondet8; [L651] havoc #t~nondet8; [L652-L659] COND FALSE !(0 != ~tmp_ndt_7~0) [L555] COND TRUE 1 [L505] int __retres1 ; [L508] COND TRUE m_st == 0 [L509] __retres1 = 1 [L546] return (__retres1); [L558] tmp = exists_runnable_thread() [L560] COND TRUE \read(tmp) [L565] COND TRUE m_st == 0 [L566] int tmp_ndt_1; [L567] tmp_ndt_1 = __VERIFIER_nondet_int() [L568] COND FALSE !(\read(tmp_ndt_1)) [L579] COND TRUE t1_st == 0 [L580] int tmp_ndt_2; [L581] tmp_ndt_2 = __VERIFIER_nondet_int() [L582] COND FALSE !(\read(tmp_ndt_2)) [L593] COND TRUE t2_st == 0 [L594] int tmp_ndt_3; [L595] tmp_ndt_3 = __VERIFIER_nondet_int() [L596] COND FALSE !(\read(tmp_ndt_3)) [L607] COND TRUE t3_st == 0 [L608] int tmp_ndt_4; [L609] tmp_ndt_4 = __VERIFIER_nondet_int() [L610] COND FALSE !(\read(tmp_ndt_4)) [L621] COND TRUE t4_st == 0 [L622] int tmp_ndt_5; [L623] tmp_ndt_5 = __VERIFIER_nondet_int() [L624] COND FALSE !(\read(tmp_ndt_5)) [L635] COND TRUE t5_st == 0 [L636] int tmp_ndt_6; [L637] tmp_ndt_6 = __VERIFIER_nondet_int() [L638] COND FALSE !(\read(tmp_ndt_6)) [L649] COND TRUE t6_st == 0 [L650] int tmp_ndt_7; [L651] tmp_ndt_7 = __VERIFIER_nondet_int() [L652] COND FALSE !(\read(tmp_ndt_7)) ----- Found a nonterminating execution for the following lasso shaped sequence of statements. Stem: [L14] int m_pc = 0; [L15] int t1_pc = 0; [L16] int t2_pc = 0; [L17] int t3_pc = 0; [L18] int t4_pc = 0; [L19] int t5_pc = 0; [L20] int t6_pc = 0; [L21] int m_st ; [L22] int t1_st ; [L23] int t2_st ; [L24] int t3_st ; [L25] int t4_st ; [L26] int t5_st ; [L27] int t6_st ; [L28] int m_i ; [L29] int t1_i ; [L30] int t2_i ; [L31] int t3_i ; [L32] int t4_i ; [L33] int t5_i ; [L34] int t6_i ; [L35] int M_E = 2; [L36] int T1_E = 2; [L37] int T2_E = 2; [L38] int T3_E = 2; [L39] int T4_E = 2; [L40] int T5_E = 2; [L41] int T6_E = 2; [L42] int E_M = 2; [L43] int E_1 = 2; [L44] int E_2 = 2; [L45] int E_3 = 2; [L46] int E_4 = 2; [L47] int E_5 = 2; [L48] int E_6 = 2; [L57] int token ; [L59] int local ; [L1088] int __retres1 ; [L998] m_i = 1 [L999] t1_i = 1 [L1000] t2_i = 1 [L1001] t3_i = 1 [L1002] t4_i = 1 [L1003] t5_i = 1 [L1004] t6_i = 1 [L1029] int kernel_st ; [L1030] int tmp ; [L1031] int tmp___0 ; [L1035] kernel_st = 0 [L465] COND TRUE m_i == 1 [L466] m_st = 0 [L470] COND TRUE t1_i == 1 [L471] t1_st = 0 [L475] COND TRUE t2_i == 1 [L476] t2_st = 0 [L480] COND TRUE t3_i == 1 [L481] t3_st = 0 [L485] COND TRUE t4_i == 1 [L486] t4_st = 0 [L490] COND TRUE t5_i == 1 [L491] t5_st = 0 [L495] COND TRUE t6_i == 1 [L496] t6_st = 0 [L674] COND FALSE !(M_E == 0) [L679] COND FALSE !(T1_E == 0) [L684] COND FALSE !(T2_E == 0) [L689] COND FALSE !(T3_E == 0) [L694] COND FALSE !(T4_E == 0) [L699] COND FALSE !(T5_E == 0) [L704] COND FALSE !(T6_E == 0) [L709] COND FALSE !(E_M == 0) [L714] COND FALSE !(E_1 == 0) [L719] COND FALSE !(E_2 == 0) [L724] COND FALSE !(E_3 == 0) [L729] COND FALSE !(E_4 == 0) [L734] COND FALSE !(E_5 == 0) [L739] COND FALSE !(E_6 == 0) [L827] int tmp ; [L828] int tmp___0 ; [L829] int tmp___1 ; [L830] int tmp___2 ; [L831] int tmp___3 ; [L832] int tmp___4 ; [L833] int tmp___5 ; [L321] int __retres1 ; [L324] COND FALSE !(m_pc == 1) [L334] __retres1 = 0 [L336] return (__retres1); [L837] tmp = is_master_triggered() [L839] COND FALSE !(\read(tmp)) [L340] int __retres1 ; [L343] COND FALSE !(t1_pc == 1) [L353] __retres1 = 0 [L355] return (__retres1); [L845] tmp___0 = is_transmit1_triggered() [L847] COND FALSE !(\read(tmp___0)) [L359] int __retres1 ; [L362] COND FALSE !(t2_pc == 1) [L372] __retres1 = 0 [L374] return (__retres1); [L853] tmp___1 = is_transmit2_triggered() [L855] COND FALSE !(\read(tmp___1)) [L378] int __retres1 ; [L381] COND FALSE !(t3_pc == 1) [L391] __retres1 = 0 [L393] return (__retres1); [L861] tmp___2 = is_transmit3_triggered() [L863] COND FALSE !(\read(tmp___2)) [L397] int __retres1 ; [L400] COND FALSE !(t4_pc == 1) [L410] __retres1 = 0 [L412] return (__retres1); [L869] tmp___3 = is_transmit4_triggered() [L871] COND FALSE !(\read(tmp___3)) [L416] int __retres1 ; [L419] COND FALSE !(t5_pc == 1) [L429] __retres1 = 0 [L431] return (__retres1); [L877] tmp___4 = is_transmit5_triggered() [L879] COND FALSE !(\read(tmp___4)) [L435] int __retres1 ; [L438] COND FALSE !(t6_pc == 1) [L448] __retres1 = 0 [L450] return (__retres1); [L885] tmp___5 = is_transmit6_triggered() [L887] COND FALSE !(\read(tmp___5)) [L752] COND FALSE !(M_E == 1) [L757] COND FALSE !(T1_E == 1) [L762] COND FALSE !(T2_E == 1) [L767] COND FALSE !(T3_E == 1) [L772] COND FALSE !(T4_E == 1) [L777] COND FALSE !(T5_E == 1) [L782] COND FALSE !(T6_E == 1) [L787] COND FALSE !(E_M == 1) [L792] COND FALSE !(E_1 == 1) [L797] COND FALSE !(E_2 == 1) [L802] COND FALSE !(E_3 == 1) [L807] COND FALSE !(E_4 == 1) [L812] COND FALSE !(E_5 == 1) [L817] COND FALSE !(E_6 == 1) [L1043] COND TRUE 1 [L1046] kernel_st = 1 [L551] int tmp ; Loop: [L555] COND TRUE 1 [L505] int __retres1 ; [L508] COND TRUE m_st == 0 [L509] __retres1 = 1 [L546] return (__retres1); [L558] tmp = exists_runnable_thread() [L560] COND TRUE \read(tmp) [L565] COND TRUE m_st == 0 [L566] int tmp_ndt_1; [L567] tmp_ndt_1 = __VERIFIER_nondet_int() [L568] COND FALSE !(\read(tmp_ndt_1)) [L579] COND TRUE t1_st == 0 [L580] int tmp_ndt_2; [L581] tmp_ndt_2 = __VERIFIER_nondet_int() [L582] COND FALSE !(\read(tmp_ndt_2)) [L593] COND TRUE t2_st == 0 [L594] int tmp_ndt_3; [L595] tmp_ndt_3 = __VERIFIER_nondet_int() [L596] COND FALSE !(\read(tmp_ndt_3)) [L607] COND TRUE t3_st == 0 [L608] int tmp_ndt_4; [L609] tmp_ndt_4 = __VERIFIER_nondet_int() [L610] COND FALSE !(\read(tmp_ndt_4)) [L621] COND TRUE t4_st == 0 [L622] int tmp_ndt_5; [L623] tmp_ndt_5 = __VERIFIER_nondet_int() [L624] COND FALSE !(\read(tmp_ndt_5)) [L635] COND TRUE t5_st == 0 [L636] int tmp_ndt_6; [L637] tmp_ndt_6 = __VERIFIER_nondet_int() [L638] COND FALSE !(\read(tmp_ndt_6)) [L649] COND TRUE t6_st == 0 [L650] int tmp_ndt_7; [L651] tmp_ndt_7 = __VERIFIER_nondet_int() [L652] COND FALSE !(\read(tmp_ndt_7)) End of lasso representation. RESULT: Ultimate proved your program to be incorrect! Received shutdown request...