./Ultimate.py --spec ../../sv-benchmarks/c/properties/termination.prp --file ../../sv-benchmarks/c/systemc/token_ring.07_false-unreach-call_false-termination.cil.c --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for termination Using default analysis Version aa418289 Calling Ultimate with: java -Dosgi.configuration.area=/tmp/vcloud-vcloud-master/worker/working_dir_0fe0e757-a0d1-4897-81ed-84240e247463/bin-2019/uautomizer/data/config -Xmx12G -Xms1G -jar /tmp/vcloud-vcloud-master/worker/working_dir_0fe0e757-a0d1-4897-81ed-84240e247463/bin-2019/uautomizer/plugins/org.eclipse.equinox.launcher_1.3.100.v20150511-1540.jar -data @noDefault -ultimatedata /tmp/vcloud-vcloud-master/worker/working_dir_0fe0e757-a0d1-4897-81ed-84240e247463/bin-2019/uautomizer/data -tc /tmp/vcloud-vcloud-master/worker/working_dir_0fe0e757-a0d1-4897-81ed-84240e247463/bin-2019/uautomizer/config/AutomizerTermination.xml -i ../../sv-benchmarks/c/systemc/token_ring.07_false-unreach-call_false-termination.cil.c -s /tmp/vcloud-vcloud-master/worker/working_dir_0fe0e757-a0d1-4897-81ed-84240e247463/bin-2019/uautomizer/config/svcomp-Termination-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud-vcloud-master/worker/working_dir_0fe0e757-a0d1-4897-81ed-84240e247463/bin-2019/uautomizer --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash 7fd2d1a9f96a95d1ad5fce6dcab48c9b2b66f4e4 ................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................... Execution finished normally Writing output log to file Ultimate.log Writing human readable error path to file UltimateCounterExample.errorpath Result: FALSE(TERM) --- Real Ultimate output --- This is Ultimate 0.1.23-aa41828 [2018-11-23 16:06:09,792 INFO L170 SettingsManager]: Resetting all preferences to default values... [2018-11-23 16:06:09,793 INFO L174 SettingsManager]: Resetting UltimateCore preferences to default values [2018-11-23 16:06:09,800 INFO L177 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2018-11-23 16:06:09,801 INFO L174 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2018-11-23 16:06:09,801 INFO L174 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2018-11-23 16:06:09,802 INFO L174 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2018-11-23 16:06:09,803 INFO L174 SettingsManager]: Resetting LassoRanker preferences to default values [2018-11-23 16:06:09,804 INFO L174 SettingsManager]: Resetting Reaching Definitions preferences to default values [2018-11-23 16:06:09,805 INFO L174 SettingsManager]: Resetting SyntaxChecker preferences to default values [2018-11-23 16:06:09,805 INFO L177 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2018-11-23 16:06:09,805 INFO L174 SettingsManager]: Resetting LTL2Aut preferences to default values [2018-11-23 16:06:09,806 INFO L174 SettingsManager]: Resetting PEA to Boogie preferences to default values [2018-11-23 16:06:09,806 INFO L174 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2018-11-23 16:06:09,807 INFO L174 SettingsManager]: Resetting ChcToBoogie preferences to default values [2018-11-23 16:06:09,808 INFO L174 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2018-11-23 16:06:09,808 INFO L174 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2018-11-23 16:06:09,810 INFO L174 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2018-11-23 16:06:09,811 INFO L174 SettingsManager]: Resetting CodeCheck preferences to default values [2018-11-23 16:06:09,812 INFO L174 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2018-11-23 16:06:09,813 INFO L174 SettingsManager]: Resetting RCFGBuilder preferences to default values [2018-11-23 16:06:09,813 INFO L174 SettingsManager]: Resetting TraceAbstraction preferences to default values [2018-11-23 16:06:09,815 INFO L177 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2018-11-23 16:06:09,815 INFO L177 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2018-11-23 16:06:09,815 INFO L174 SettingsManager]: Resetting TreeAutomizer preferences to default values [2018-11-23 16:06:09,816 INFO L174 SettingsManager]: Resetting IcfgTransformer preferences to default values [2018-11-23 16:06:09,817 INFO L174 SettingsManager]: Resetting Boogie Printer preferences to default values [2018-11-23 16:06:09,817 INFO L174 SettingsManager]: Resetting ReqPrinter preferences to default values [2018-11-23 16:06:09,818 INFO L174 SettingsManager]: Resetting Witness Printer preferences to default values [2018-11-23 16:06:09,819 INFO L177 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2018-11-23 16:06:09,819 INFO L174 SettingsManager]: Resetting CDTParser preferences to default values [2018-11-23 16:06:09,819 INFO L177 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2018-11-23 16:06:09,819 INFO L177 SettingsManager]: ReqParser provides no preferences, ignoring... [2018-11-23 16:06:09,820 INFO L174 SettingsManager]: Resetting SmtParser preferences to default values [2018-11-23 16:06:09,820 INFO L174 SettingsManager]: Resetting Witness Parser preferences to default values [2018-11-23 16:06:09,821 INFO L181 SettingsManager]: Finished resetting all preferences to default values... [2018-11-23 16:06:09,821 INFO L98 SettingsManager]: Beginning loading settings from /tmp/vcloud-vcloud-master/worker/working_dir_0fe0e757-a0d1-4897-81ed-84240e247463/bin-2019/uautomizer/config/svcomp-Termination-32bit-Automizer_Default.epf [2018-11-23 16:06:09,831 INFO L110 SettingsManager]: Loading preferences was successful [2018-11-23 16:06:09,831 INFO L112 SettingsManager]: Preferences different from defaults after loading the file: [2018-11-23 16:06:09,832 INFO L131 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2018-11-23 16:06:09,832 INFO L133 SettingsManager]: * Create parallel compositions if possible=false [2018-11-23 16:06:09,832 INFO L133 SettingsManager]: * Use SBE=true [2018-11-23 16:06:09,833 INFO L131 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: [2018-11-23 16:06:09,833 INFO L133 SettingsManager]: * NCSB implementation=INTSET_LAZY3 [2018-11-23 16:06:09,833 INFO L133 SettingsManager]: * Use old map elimination=false [2018-11-23 16:06:09,833 INFO L133 SettingsManager]: * Use external solver (rank synthesis)=false [2018-11-23 16:06:09,833 INFO L133 SettingsManager]: * Use only trivial implications for array writes=true [2018-11-23 16:06:09,833 INFO L133 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES [2018-11-23 16:06:09,833 INFO L131 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2018-11-23 16:06:09,834 INFO L133 SettingsManager]: * sizeof long=4 [2018-11-23 16:06:09,834 INFO L133 SettingsManager]: * Check unreachability of error function in SV-COMP mode=false [2018-11-23 16:06:09,834 INFO L133 SettingsManager]: * Overapproximate operations on floating types=true [2018-11-23 16:06:09,834 INFO L133 SettingsManager]: * sizeof POINTER=4 [2018-11-23 16:06:09,834 INFO L133 SettingsManager]: * Check division by zero=IGNORE [2018-11-23 16:06:09,834 INFO L133 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME [2018-11-23 16:06:09,834 INFO L133 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME [2018-11-23 16:06:09,834 INFO L133 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME [2018-11-23 16:06:09,835 INFO L133 SettingsManager]: * sizeof long double=12 [2018-11-23 16:06:09,835 INFO L133 SettingsManager]: * Check if freed pointer was valid=false [2018-11-23 16:06:09,835 INFO L133 SettingsManager]: * Assume nondeterminstic values are in range=false [2018-11-23 16:06:09,835 INFO L133 SettingsManager]: * Use constant arrays=true [2018-11-23 16:06:09,835 INFO L133 SettingsManager]: * Pointer base address is valid at dereference=ASSUME [2018-11-23 16:06:09,835 INFO L131 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2018-11-23 16:06:09,835 INFO L133 SettingsManager]: * Size of a code block=SequenceOfStatements [2018-11-23 16:06:09,835 INFO L133 SettingsManager]: * To the following directory=/home/matthias/ultimate/dump [2018-11-23 16:06:09,835 INFO L131 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2018-11-23 16:06:09,836 INFO L133 SettingsManager]: * Trace refinement strategy=CAMEL [2018-11-23 16:06:09,836 INFO L133 SettingsManager]: * Dump automata to the following directory=/home/matthias/ultimate/dump/auto [2018-11-23 16:06:09,836 INFO L131 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2018-11-23 16:06:09,837 INFO L133 SettingsManager]: * TransformationType=MODULO_NEIGHBOR Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud-vcloud-master/worker/working_dir_0fe0e757-a0d1-4897-81ed-84240e247463/bin-2019/uautomizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> 7fd2d1a9f96a95d1ad5fce6dcab48c9b2b66f4e4 [2018-11-23 16:06:09,858 INFO L81 nceAwareModelManager]: Repository-Root is: /tmp [2018-11-23 16:06:09,866 INFO L258 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2018-11-23 16:06:09,868 INFO L214 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2018-11-23 16:06:09,869 INFO L271 PluginConnector]: Initializing CDTParser... [2018-11-23 16:06:09,869 INFO L276 PluginConnector]: CDTParser initialized [2018-11-23 16:06:09,869 INFO L418 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud-vcloud-master/worker/working_dir_0fe0e757-a0d1-4897-81ed-84240e247463/bin-2019/uautomizer/../../sv-benchmarks/c/systemc/token_ring.07_false-unreach-call_false-termination.cil.c [2018-11-23 16:06:09,905 INFO L221 CDTParser]: Created temporary CDT project at /tmp/vcloud-vcloud-master/worker/working_dir_0fe0e757-a0d1-4897-81ed-84240e247463/bin-2019/uautomizer/data/13db2e137/291252d96f334ff2bda31c102831a8b5/FLAGcd9463af3 [2018-11-23 16:06:10,325 INFO L307 CDTParser]: Found 1 translation units. [2018-11-23 16:06:10,325 INFO L161 CDTParser]: Scanning /tmp/vcloud-vcloud-master/worker/working_dir_0fe0e757-a0d1-4897-81ed-84240e247463/sv-benchmarks/c/systemc/token_ring.07_false-unreach-call_false-termination.cil.c [2018-11-23 16:06:10,334 INFO L355 CDTParser]: About to delete temporary CDT project at /tmp/vcloud-vcloud-master/worker/working_dir_0fe0e757-a0d1-4897-81ed-84240e247463/bin-2019/uautomizer/data/13db2e137/291252d96f334ff2bda31c102831a8b5/FLAGcd9463af3 [2018-11-23 16:06:10,342 INFO L363 CDTParser]: Successfully deleted /tmp/vcloud-vcloud-master/worker/working_dir_0fe0e757-a0d1-4897-81ed-84240e247463/bin-2019/uautomizer/data/13db2e137/291252d96f334ff2bda31c102831a8b5 [2018-11-23 16:06:10,344 INFO L296 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2018-11-23 16:06:10,345 INFO L131 ToolchainWalker]: Walking toolchain with 6 elements. [2018-11-23 16:06:10,346 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2018-11-23 16:06:10,346 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2018-11-23 16:06:10,349 INFO L276 PluginConnector]: CACSL2BoogieTranslator initialized [2018-11-23 16:06:10,350 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 23.11 04:06:10" (1/1) ... [2018-11-23 16:06:10,352 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@57f3324f and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 04:06:10, skipping insertion in model container [2018-11-23 16:06:10,352 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 23.11 04:06:10" (1/1) ... [2018-11-23 16:06:10,361 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2018-11-23 16:06:10,393 INFO L176 MainTranslator]: Built tables and reachable declarations [2018-11-23 16:06:10,558 INFO L201 PostProcessor]: Analyzing one entry point: main [2018-11-23 16:06:10,561 INFO L191 MainTranslator]: Completed pre-run [2018-11-23 16:06:10,601 INFO L201 PostProcessor]: Analyzing one entry point: main [2018-11-23 16:06:10,618 INFO L195 MainTranslator]: Completed translation [2018-11-23 16:06:10,618 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 04:06:10 WrapperNode [2018-11-23 16:06:10,619 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2018-11-23 16:06:10,619 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2018-11-23 16:06:10,619 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2018-11-23 16:06:10,619 INFO L276 PluginConnector]: Boogie Procedure Inliner initialized [2018-11-23 16:06:10,667 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 04:06:10" (1/1) ... [2018-11-23 16:06:10,674 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 04:06:10" (1/1) ... [2018-11-23 16:06:10,721 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2018-11-23 16:06:10,722 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2018-11-23 16:06:10,722 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2018-11-23 16:06:10,722 INFO L276 PluginConnector]: Boogie Preprocessor initialized [2018-11-23 16:06:10,728 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 04:06:10" (1/1) ... [2018-11-23 16:06:10,728 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 04:06:10" (1/1) ... [2018-11-23 16:06:10,732 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 04:06:10" (1/1) ... [2018-11-23 16:06:10,732 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 04:06:10" (1/1) ... [2018-11-23 16:06:10,748 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 04:06:10" (1/1) ... [2018-11-23 16:06:10,767 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 04:06:10" (1/1) ... [2018-11-23 16:06:10,771 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 04:06:10" (1/1) ... [2018-11-23 16:06:10,777 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2018-11-23 16:06:10,778 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2018-11-23 16:06:10,778 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2018-11-23 16:06:10,778 INFO L276 PluginConnector]: RCFGBuilder initialized [2018-11-23 16:06:10,779 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 04:06:10" (1/1) ... No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_0fe0e757-a0d1-4897-81ed-84240e247463/bin-2019/uautomizer/z3 Starting monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2018-11-23 16:06:10,826 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2018-11-23 16:06:10,826 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2018-11-23 16:06:12,021 INFO L275 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2018-11-23 16:06:12,022 INFO L280 CfgBuilder]: Removed 280 assue(true) statements. [2018-11-23 16:06:12,022 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 23.11 04:06:12 BoogieIcfgContainer [2018-11-23 16:06:12,022 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2018-11-23 16:06:12,023 INFO L113 PluginConnector]: ------------------------BuchiAutomizer---------------------------- [2018-11-23 16:06:12,023 INFO L271 PluginConnector]: Initializing BuchiAutomizer... [2018-11-23 16:06:12,026 INFO L276 PluginConnector]: BuchiAutomizer initialized [2018-11-23 16:06:12,027 INFO L102 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2018-11-23 16:06:12,027 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 23.11 04:06:10" (1/3) ... [2018-11-23 16:06:12,028 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@45049972 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 23.11 04:06:12, skipping insertion in model container [2018-11-23 16:06:12,028 INFO L102 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2018-11-23 16:06:12,028 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 04:06:10" (2/3) ... [2018-11-23 16:06:12,028 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@45049972 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 23.11 04:06:12, skipping insertion in model container [2018-11-23 16:06:12,029 INFO L102 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2018-11-23 16:06:12,029 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 23.11 04:06:12" (3/3) ... [2018-11-23 16:06:12,030 INFO L375 chiAutomizerObserver]: Analyzing ICFG token_ring.07_false-unreach-call_false-termination.cil.c [2018-11-23 16:06:12,075 INFO L133 ementStrategyFactory]: Using default assertion order modulation [2018-11-23 16:06:12,075 INFO L374 BuchiCegarLoop]: Interprodecural is true [2018-11-23 16:06:12,075 INFO L375 BuchiCegarLoop]: Hoare is false [2018-11-23 16:06:12,075 INFO L376 BuchiCegarLoop]: Compute interpolants for ForwardPredicates [2018-11-23 16:06:12,076 INFO L377 BuchiCegarLoop]: Backedges is STRAIGHT_LINE [2018-11-23 16:06:12,076 INFO L378 BuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2018-11-23 16:06:12,076 INFO L379 BuchiCegarLoop]: Difference is false [2018-11-23 16:06:12,076 INFO L380 BuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2018-11-23 16:06:12,076 INFO L383 BuchiCegarLoop]: ======== Iteration 0==of CEGAR loop == BuchiCegarLoop======== [2018-11-23 16:06:12,100 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 818 states. [2018-11-23 16:06:12,139 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 715 [2018-11-23 16:06:12,139 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-23 16:06:12,140 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-23 16:06:12,149 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 16:06:12,149 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 16:06:12,149 INFO L442 BuchiCegarLoop]: ======== Iteration 1============ [2018-11-23 16:06:12,149 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 818 states. [2018-11-23 16:06:12,158 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 715 [2018-11-23 16:06:12,159 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-23 16:06:12,159 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-23 16:06:12,161 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 16:06:12,162 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 16:06:12,169 INFO L794 eck$LassoCheckResult]: Stem: 316#ULTIMATE.startENTRYtrue ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; 235#L-1true havoc main_#res;havoc main_~__retres1~9;havoc main_~__retres1~9;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 281#L1143true havoc start_simulation_#t~ret20, start_simulation_#t~ret21, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 213#L531true assume !(1 == ~m_i~0);~m_st~0 := 2; 658#L538-1true assume 1 == ~t1_i~0;~t1_st~0 := 0; 463#L543-1true assume !(1 == ~t2_i~0);~t2_st~0 := 2; 380#L548-1true assume !(1 == ~t3_i~0);~t3_st~0 := 2; 214#L553-1true assume !(1 == ~t4_i~0);~t4_st~0 := 2; 816#L558-1true assume !(1 == ~t5_i~0);~t5_st~0 := 2; 551#L563-1true assume !(1 == ~t6_i~0);~t6_st~0 := 2; 364#L568-1true assume !(1 == ~t7_i~0);~t7_st~0 := 2; 200#L573-1true assume !(0 == ~M_E~0); 301#L771-1true assume 0 == ~T1_E~0;~T1_E~0 := 1; 92#L776-1true assume !(0 == ~T2_E~0); 731#L781-1true assume !(0 == ~T3_E~0); 431#L786-1true assume !(0 == ~T4_E~0); 269#L791-1true assume !(0 == ~T5_E~0); 62#L796-1true assume !(0 == ~T6_E~0); 798#L801-1true assume !(0 == ~T7_E~0); 628#L806-1true assume !(0 == ~E_M~0); 342#L811-1true assume 0 == ~E_1~0;~E_1~0 := 1; 163#L816-1true assume !(0 == ~E_2~0); 767#L821-1true assume !(0 == ~E_3~0); 687#L826-1true assume !(0 == ~E_4~0); 509#L831-1true assume !(0 == ~E_5~0); 332#L836-1true assume !(0 == ~E_6~0); 17#L841-1true assume !(0 == ~E_7~0); 664#L846-1true havoc activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 55#L378true assume !(1 == ~m_pc~0); 42#L378-2true is_master_triggered_~__retres1~0 := 0; 471#L389true is_master_triggered_#res := is_master_triggered_~__retres1~0; 534#L390true activate_threads_#t~ret11 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 736#L957true assume !(0 != activate_threads_~tmp~1); 737#L957-2true havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 187#L397true assume 1 == ~t1_pc~0; 140#L398true assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 584#L408true is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 540#L409true activate_threads_#t~ret12 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 344#L965true assume !(0 != activate_threads_~tmp___0~0); 337#L965-2true havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 384#L416true assume !(1 == ~t2_pc~0); 285#L416-2true is_transmit2_triggered_~__retres1~2 := 0; 784#L427true is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 659#L428true activate_threads_#t~ret13 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 27#L973true assume !(0 != activate_threads_~tmp___1~0); 30#L973-2true havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 497#L435true assume 1 == ~t3_pc~0; 351#L436true assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 73#L446true is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 766#L447true activate_threads_#t~ret14 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 568#L981true assume !(0 != activate_threads_~tmp___2~0); 560#L981-2true havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 622#L454true assume 1 == ~t4_pc~0; 466#L455true assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 216#L465true is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 52#L466true activate_threads_#t~ret15 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 273#L989true assume !(0 != activate_threads_~tmp___3~0); 276#L989-2true havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 717#L473true assume !(1 == ~t5_pc~0); 719#L473-2true is_transmit5_triggered_~__retres1~5 := 0; 322#L484true is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 202#L485true activate_threads_#t~ret16 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 779#L997true assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 772#L997-2true havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 817#L492true assume 1 == ~t6_pc~0; 781#L493true assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6 := 1; 414#L503true is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 381#L504true activate_threads_#t~ret17 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 605#L1005true assume !(0 != activate_threads_~tmp___5~0); 607#L1005-2true havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 12#L511true assume !(1 == ~t7_pc~0); 130#L511-2true is_transmit7_triggered_~__retres1~7 := 0; 428#L522true is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 506#L523true activate_threads_#t~ret18 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 314#L1013true assume !(0 != activate_threads_~tmp___6~0); 307#L1013-2true assume !(1 == ~M_E~0); 310#L859-1true assume !(1 == ~T1_E~0); 103#L864-1true assume 1 == ~T2_E~0;~T2_E~0 := 2; 727#L869-1true assume !(1 == ~T3_E~0); 429#L874-1true assume !(1 == ~T4_E~0); 263#L879-1true assume !(1 == ~T5_E~0); 60#L884-1true assume !(1 == ~T6_E~0); 794#L889-1true assume !(1 == ~T7_E~0); 626#L894-1true assume !(1 == ~E_M~0); 338#L899-1true assume !(1 == ~E_1~0); 159#L904-1true assume 1 == ~E_2~0;~E_2~0 := 2; 774#L909-1true assume !(1 == ~E_3~0); 695#L914-1true assume !(1 == ~E_4~0); 513#L919-1true assume !(1 == ~E_5~0); 336#L924-1true assume !(1 == ~E_6~0); 32#L929-1true assume !(1 == ~E_7~0); 639#L1180-1true [2018-11-23 16:06:12,171 INFO L796 eck$LassoCheckResult]: Loop: 639#L1180-1true assume !false; 611#L1181true start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret2, eval_#t~nondet3, eval_~tmp_ndt_1~0, eval_#t~nondet4, eval_~tmp_ndt_2~0, eval_#t~nondet5, eval_~tmp_ndt_3~0, eval_#t~nondet6, eval_~tmp_ndt_4~0, eval_#t~nondet7, eval_~tmp_ndt_5~0, eval_#t~nondet8, eval_~tmp_ndt_6~0, eval_#t~nondet9, eval_~tmp_ndt_7~0, eval_#t~nondet10, eval_~tmp_ndt_8~0, eval_~tmp~0;havoc eval_~tmp~0; 389#L746true assume false; 554#L761true start_simulation_~kernel_st~0 := 2; 215#L531-1true start_simulation_~kernel_st~0 := 3; 302#L771-2true assume 0 == ~M_E~0;~M_E~0 := 1; 305#L771-4true assume 0 == ~T1_E~0;~T1_E~0 := 1; 95#L776-3true assume !(0 == ~T2_E~0); 734#L781-3true assume 0 == ~T3_E~0;~T3_E~0 := 1; 432#L786-3true assume 0 == ~T4_E~0;~T4_E~0 := 1; 254#L791-3true assume 0 == ~T5_E~0;~T5_E~0 := 1; 57#L796-3true assume 0 == ~T6_E~0;~T6_E~0 := 1; 789#L801-3true assume 0 == ~T7_E~0;~T7_E~0 := 1; 624#L806-3true assume 0 == ~E_M~0;~E_M~0 := 1; 419#L811-3true assume 0 == ~E_1~0;~E_1~0 := 1; 154#L816-3true assume !(0 == ~E_2~0); 769#L821-3true assume 0 == ~E_3~0;~E_3~0 := 1; 689#L826-3true assume 0 == ~E_4~0;~E_4~0 := 1; 510#L831-3true assume 0 == ~E_5~0;~E_5~0 := 1; 333#L836-3true assume 0 == ~E_6~0;~E_6~0 := 1; 22#L841-3true assume 0 == ~E_7~0;~E_7~0 := 1; 665#L846-3true havoc activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 13#L378-27true assume !(1 == ~m_pc~0); 131#L378-29true is_master_triggered_~__retres1~0 := 0; 440#L389-9true is_master_triggered_#res := is_master_triggered_~__retres1~0; 517#L390-9true activate_threads_#t~ret11 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 703#L957-27true assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 705#L957-29true havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 149#L397-27true assume 1 == ~t1_pc~0; 226#L398-9true assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 581#L408-9true is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 641#L409-9true activate_threads_#t~ret12 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 399#L965-27true assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 391#L965-29true havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 261#L416-27true assume 1 == ~t2_pc~0; 229#L417-9true assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 672#L427-9true is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 645#L428-9true activate_threads_#t~ret13 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 110#L973-27true assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 114#L973-29true havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 362#L435-27true assume 1 == ~t3_pc~0; 349#L436-9true assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 71#L446-9true is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 750#L447-9true activate_threads_#t~ret14 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 642#L981-27true assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 630#L981-29true havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 478#L454-27true assume 1 == ~t4_pc~0; 435#L455-9true assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 206#L465-9true is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 35#L466-9true activate_threads_#t~ret15 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 230#L989-27true assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 232#L989-29true havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 595#L473-27true assume 1 == ~t5_pc~0; 576#L474-9true assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 320#L484-9true is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 177#L485-9true activate_threads_#t~ret16 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 753#L997-27true assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 740#L997-29true havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 791#L492-27true assume !(1 == ~t6_pc~0); 793#L492-29true is_transmit6_triggered_~__retres1~6 := 0; 395#L503-9true is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 297#L504-9true activate_threads_#t~ret17 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 439#L1005-27true assume !(0 != activate_threads_~tmp___5~0); 443#L1005-29true havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 84#L511-27true assume 1 == ~t7_pc~0; 68#L512-9true assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7 := 1; 527#L522-9true is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 491#L523-9true activate_threads_#t~ret18 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 182#L1013-27true assume 0 != activate_threads_~tmp___6~0;~t7_st~0 := 0; 165#L1013-29true assume 1 == ~M_E~0;~M_E~0 := 2; 299#L859-3true assume 1 == ~T1_E~0;~T1_E~0 := 2; 91#L864-3true assume 1 == ~T2_E~0;~T2_E~0 := 2; 729#L869-3true assume !(1 == ~T3_E~0); 430#L874-3true assume 1 == ~T4_E~0;~T4_E~0 := 2; 268#L879-3true assume 1 == ~T5_E~0;~T5_E~0 := 2; 61#L884-3true assume 1 == ~T6_E~0;~T6_E~0 := 2; 797#L889-3true assume 1 == ~T7_E~0;~T7_E~0 := 2; 627#L894-3true assume 1 == ~E_M~0;~E_M~0 := 2; 341#L899-3true assume 1 == ~E_1~0;~E_1~0 := 2; 162#L904-3true assume 1 == ~E_2~0;~E_2~0 := 2; 776#L909-3true assume !(1 == ~E_3~0); 697#L914-3true assume 1 == ~E_4~0;~E_4~0 := 2; 508#L919-3true assume 1 == ~E_5~0;~E_5~0 := 2; 331#L924-3true assume 1 == ~E_6~0;~E_6~0 := 2; 16#L929-3true assume 1 == ~E_7~0;~E_7~0 := 2; 663#L934-3true havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~8;havoc exists_runnable_thread_~__retres1~8; 620#L586-1true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8 := 1; 596#L628-1true exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; 548#L629-1true start_simulation_#t~ret20 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret20;havoc start_simulation_#t~ret20; 657#L1199true assume !(0 == start_simulation_~tmp~3); 646#L1199-1true havoc stop_simulation_#res;havoc stop_simulation_#t~ret19, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~8;havoc exists_runnable_thread_~__retres1~8; 621#L586-2true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8 := 1; 598#L628-2true exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; 550#L629-2true stop_simulation_#t~ret19 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret19;havoc stop_simulation_#t~ret19; 673#L1154true assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 515#L1161true stop_simulation_#res := stop_simulation_~__retres2~0; 495#L1162true start_simulation_#t~ret21 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret21;havoc start_simulation_#t~ret21; 178#L1212true assume !(0 != start_simulation_~tmp___0~1); 639#L1180-1true [2018-11-23 16:06:12,175 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 16:06:12,175 INFO L82 PathProgramCache]: Analyzing trace with hash -1537628007, now seen corresponding path program 1 times [2018-11-23 16:06:12,176 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 16:06:12,177 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 16:06:12,206 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 16:06:12,206 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 16:06:12,206 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 16:06:12,237 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 16:06:12,302 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 16:06:12,303 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 16:06:12,304 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-23 16:06:12,307 INFO L799 eck$LassoCheckResult]: stem already infeasible [2018-11-23 16:06:12,307 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 16:06:12,307 INFO L82 PathProgramCache]: Analyzing trace with hash 1636718763, now seen corresponding path program 1 times [2018-11-23 16:06:12,307 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 16:06:12,308 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 16:06:12,308 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 16:06:12,308 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 16:06:12,309 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 16:06:12,314 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 16:06:12,329 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 16:06:12,329 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 16:06:12,330 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2018-11-23 16:06:12,331 INFO L811 eck$LassoCheckResult]: loop already infeasible [2018-11-23 16:06:12,341 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-23 16:06:12,341 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-23 16:06:12,343 INFO L87 Difference]: Start difference. First operand 818 states. Second operand 3 states. [2018-11-23 16:06:12,390 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 16:06:12,391 INFO L93 Difference]: Finished difference Result 818 states and 1232 transitions. [2018-11-23 16:06:12,392 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-23 16:06:12,393 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 818 states and 1232 transitions. [2018-11-23 16:06:12,398 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 713 [2018-11-23 16:06:12,406 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 818 states to 812 states and 1226 transitions. [2018-11-23 16:06:12,407 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 812 [2018-11-23 16:06:12,408 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 812 [2018-11-23 16:06:12,409 INFO L73 IsDeterministic]: Start isDeterministic. Operand 812 states and 1226 transitions. [2018-11-23 16:06:12,412 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-23 16:06:12,413 INFO L705 BuchiCegarLoop]: Abstraction has 812 states and 1226 transitions. [2018-11-23 16:06:12,426 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 812 states and 1226 transitions. [2018-11-23 16:06:12,454 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 812 to 812. [2018-11-23 16:06:12,455 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 812 states. [2018-11-23 16:06:12,457 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 812 states to 812 states and 1226 transitions. [2018-11-23 16:06:12,458 INFO L728 BuchiCegarLoop]: Abstraction has 812 states and 1226 transitions. [2018-11-23 16:06:12,458 INFO L608 BuchiCegarLoop]: Abstraction has 812 states and 1226 transitions. [2018-11-23 16:06:12,458 INFO L442 BuchiCegarLoop]: ======== Iteration 2============ [2018-11-23 16:06:12,458 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 812 states and 1226 transitions. [2018-11-23 16:06:12,461 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 713 [2018-11-23 16:06:12,461 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-23 16:06:12,461 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-23 16:06:12,463 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 16:06:12,463 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 16:06:12,464 INFO L794 eck$LassoCheckResult]: Stem: 2098#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; 2007#L-1 havoc main_#res;havoc main_~__retres1~9;havoc main_~__retres1~9;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 2008#L1143 havoc start_simulation_#t~ret20, start_simulation_#t~ret21, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 1979#L531 assume 1 == ~m_i~0;~m_st~0 := 0; 1980#L538-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 2249#L543-1 assume !(1 == ~t2_i~0);~t2_st~0 := 2; 2161#L548-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 1981#L553-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 1982#L558-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 2313#L563-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 2157#L568-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 1965#L573-1 assume !(0 == ~M_E~0); 1966#L771-1 assume 0 == ~T1_E~0;~T1_E~0 := 1; 1826#L776-1 assume !(0 == ~T2_E~0); 1827#L781-1 assume !(0 == ~T3_E~0); 2212#L786-1 assume !(0 == ~T4_E~0); 2053#L791-1 assume !(0 == ~T5_E~0); 1765#L796-1 assume !(0 == ~T6_E~0); 1766#L801-1 assume !(0 == ~T7_E~0); 2375#L806-1 assume !(0 == ~E_M~0); 2125#L811-1 assume 0 == ~E_1~0;~E_1~0 := 1; 1917#L816-1 assume !(0 == ~E_2~0); 1918#L821-1 assume !(0 == ~E_3~0); 2409#L826-1 assume !(0 == ~E_4~0); 2280#L831-1 assume !(0 == ~E_5~0); 2113#L836-1 assume !(0 == ~E_6~0); 1675#L841-1 assume !(0 == ~E_7~0); 1676#L846-1 havoc activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 1749#L378 assume !(1 == ~m_pc~0); 1723#L378-2 is_master_triggered_~__retres1~0 := 0; 1724#L389 is_master_triggered_#res := is_master_triggered_~__retres1~0; 2256#L390 activate_threads_#t~ret11 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 2294#L957 assume !(0 != activate_threads_~tmp~1); 2424#L957-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 1950#L397 assume 1 == ~t1_pc~0; 1868#L398 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 1869#L408 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 2298#L409 activate_threads_#t~ret12 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 2128#L965 assume !(0 != activate_threads_~tmp___0~0); 2119#L965-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 2120#L416 assume !(1 == ~t2_pc~0); 2033#L416-2 is_transmit2_triggered_~__retres1~2 := 0; 2032#L427 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 2392#L428 activate_threads_#t~ret13 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 1695#L973 assume !(0 != activate_threads_~tmp___1~0); 1696#L973-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 1701#L435 assume 1 == ~t3_pc~0; 2141#L436 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 1790#L446 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 1791#L447 activate_threads_#t~ret14 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 2332#L981 assume !(0 != activate_threads_~tmp___2~0); 2322#L981-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 2323#L454 assume 1 == ~t4_pc~0; 2252#L455 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 1985#L465 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 1743#L466 activate_threads_#t~ret15 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 1744#L989 assume !(0 != activate_threads_~tmp___3~0); 2057#L989-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 2059#L473 assume !(1 == ~t5_pc~0); 2365#L473-2 is_transmit5_triggered_~__retres1~5 := 0; 2103#L484 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 1968#L485 activate_threads_#t~ret16 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 1969#L997 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 2445#L997-2 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 2446#L492 assume 1 == ~t6_pc~0; 2449#L493 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6 := 1; 2196#L503 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 2162#L504 activate_threads_#t~ret17 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 2163#L1005 assume !(0 != activate_threads_~tmp___5~0); 2367#L1005-2 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 1664#L511 assume !(1 == ~t7_pc~0); 1665#L511-2 is_transmit7_triggered_~__retres1~7 := 0; 1820#L522 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 2209#L523 activate_threads_#t~ret18 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 2096#L1013 assume !(0 != activate_threads_~tmp___6~0); 2089#L1013-2 assume !(1 == ~M_E~0); 2090#L859-1 assume !(1 == ~T1_E~0); 1839#L864-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 1840#L869-1 assume !(1 == ~T3_E~0); 2210#L874-1 assume !(1 == ~T4_E~0); 2047#L879-1 assume !(1 == ~T5_E~0); 1761#L884-1 assume !(1 == ~T6_E~0); 1762#L889-1 assume !(1 == ~T7_E~0); 2373#L894-1 assume !(1 == ~E_M~0); 2121#L899-1 assume !(1 == ~E_1~0); 1910#L904-1 assume 1 == ~E_2~0;~E_2~0 := 2; 1911#L909-1 assume !(1 == ~E_3~0); 2412#L914-1 assume !(1 == ~E_4~0); 2282#L919-1 assume !(1 == ~E_5~0); 2118#L924-1 assume !(1 == ~E_6~0); 1704#L929-1 assume !(1 == ~E_7~0); 1705#L1180-1 [2018-11-23 16:06:12,464 INFO L796 eck$LassoCheckResult]: Loop: 1705#L1180-1 assume !false; 2368#L1181 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret2, eval_#t~nondet3, eval_~tmp_ndt_1~0, eval_#t~nondet4, eval_~tmp_ndt_2~0, eval_#t~nondet5, eval_~tmp_ndt_3~0, eval_#t~nondet6, eval_~tmp_ndt_4~0, eval_#t~nondet7, eval_~tmp_ndt_5~0, eval_#t~nondet8, eval_~tmp_ndt_6~0, eval_#t~nondet9, eval_~tmp_ndt_7~0, eval_#t~nondet10, eval_~tmp_ndt_8~0, eval_~tmp~0;havoc eval_~tmp~0; 1830#L746 assume !false; 2086#L639 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~8;havoc exists_runnable_thread_~__retres1~8; 2087#L586 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8 := 1; 1756#L628 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; 2320#L629 eval_#t~ret2 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret2;havoc eval_#t~ret2; 1650#L643 assume !(0 != eval_~tmp~0); 1652#L761 start_simulation_~kernel_st~0 := 2; 1983#L531-1 start_simulation_~kernel_st~0 := 3; 1984#L771-2 assume 0 == ~M_E~0;~M_E~0 := 1; 2083#L771-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 1832#L776-3 assume !(0 == ~T2_E~0); 1833#L781-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 2213#L786-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 2040#L791-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 1753#L796-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 1754#L801-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 2372#L806-3 assume 0 == ~E_M~0;~E_M~0 := 1; 2200#L811-3 assume 0 == ~E_1~0;~E_1~0 := 1; 1900#L816-3 assume !(0 == ~E_2~0); 1901#L821-3 assume 0 == ~E_3~0;~E_3~0 := 1; 2410#L826-3 assume 0 == ~E_4~0;~E_4~0 := 1; 2281#L831-3 assume 0 == ~E_5~0;~E_5~0 := 1; 2114#L836-3 assume 0 == ~E_6~0;~E_6~0 := 1; 1685#L841-3 assume 0 == ~E_7~0;~E_7~0 := 1; 1686#L846-3 havoc activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 1667#L378-27 assume 1 == ~m_pc~0; 1668#L379-9 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 1844#L389-9 is_master_triggered_#res := is_master_triggered_~__retres1~0; 2223#L390-9 activate_threads_#t~ret11 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 2285#L957-27 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 2416#L957-29 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 1889#L397-27 assume !(1 == ~t1_pc~0); 1890#L397-29 is_transmit1_triggered_~__retres1~1 := 0; 1892#L408-9 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 2350#L409-9 activate_threads_#t~ret12 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 2181#L965-27 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 2173#L965-29 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 2045#L416-27 assume 1 == ~t2_pc~0; 1997#L417-9 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 1998#L427-9 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 2383#L428-9 activate_threads_#t~ret13 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 1845#L973-27 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 1846#L973-29 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 1852#L435-27 assume 1 == ~t3_pc~0; 2136#L436-9 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 1787#L446-9 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 1788#L447-9 activate_threads_#t~ret14 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 2381#L981-27 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 2376#L981-29 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 2262#L454-27 assume 1 == ~t4_pc~0; 2216#L455-9 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 1972#L465-9 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 1710#L466-9 activate_threads_#t~ret15 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 1711#L989-27 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 2000#L989-29 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 2004#L473-27 assume 1 == ~t5_pc~0; 2342#L474-9 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 2101#L484-9 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 1935#L485-9 activate_threads_#t~ret16 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 1936#L997-27 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 2426#L997-29 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 2427#L492-27 assume 1 == ~t6_pc~0; 2395#L493-9 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6 := 1; 2177#L503-9 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 2079#L504-9 activate_threads_#t~ret17 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 2080#L1005-27 assume !(0 != activate_threads_~tmp___5~0); 2222#L1005-29 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 1818#L511-27 assume 1 == ~t7_pc~0; 1779#L512-9 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7 := 1; 1780#L522-9 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 2269#L523-9 activate_threads_#t~ret18 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 1941#L1013-27 assume 0 != activate_threads_~tmp___6~0;~t7_st~0 := 0; 1920#L1013-29 assume 1 == ~M_E~0;~M_E~0 := 2; 1921#L859-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 1824#L864-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 1825#L869-3 assume !(1 == ~T3_E~0); 2211#L874-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 2052#L879-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 1763#L884-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 1764#L889-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 2374#L894-3 assume 1 == ~E_M~0;~E_M~0 := 2; 2124#L899-3 assume 1 == ~E_1~0;~E_1~0 := 2; 1915#L904-3 assume 1 == ~E_2~0;~E_2~0 := 2; 1916#L909-3 assume !(1 == ~E_3~0); 2413#L914-3 assume 1 == ~E_4~0;~E_4~0 := 2; 2279#L919-3 assume 1 == ~E_5~0;~E_5~0 := 2; 2112#L924-3 assume 1 == ~E_6~0;~E_6~0 := 2; 1673#L929-3 assume 1 == ~E_7~0;~E_7~0 := 2; 1674#L934-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~8;havoc exists_runnable_thread_~__retres1~8; 2369#L586-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8 := 1; 1760#L628-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; 2307#L629-1 start_simulation_#t~ret20 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret20;havoc start_simulation_#t~ret20; 2308#L1199 assume !(0 == start_simulation_~tmp~3); 2225#L1199-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret19, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~8;havoc exists_runnable_thread_~__retres1~8; 2370#L586-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8 := 1; 1738#L628-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; 2311#L629-2 stop_simulation_#t~ret19 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret19;havoc stop_simulation_#t~ret19; 2312#L1154 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 2283#L1161 stop_simulation_#res := stop_simulation_~__retres2~0; 2271#L1162 start_simulation_#t~ret21 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret21;havoc start_simulation_#t~ret21; 1937#L1212 assume !(0 != start_simulation_~tmp___0~1); 1705#L1180-1 [2018-11-23 16:06:12,465 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 16:06:12,465 INFO L82 PathProgramCache]: Analyzing trace with hash -542934309, now seen corresponding path program 1 times [2018-11-23 16:06:12,465 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 16:06:12,465 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 16:06:12,466 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 16:06:12,466 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 16:06:12,466 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 16:06:12,476 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 16:06:12,521 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 16:06:12,521 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 16:06:12,521 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-23 16:06:12,522 INFO L799 eck$LassoCheckResult]: stem already infeasible [2018-11-23 16:06:12,522 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 16:06:12,522 INFO L82 PathProgramCache]: Analyzing trace with hash 2056175835, now seen corresponding path program 1 times [2018-11-23 16:06:12,522 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 16:06:12,522 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 16:06:12,523 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 16:06:12,523 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 16:06:12,523 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 16:06:12,543 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 16:06:12,609 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 16:06:12,609 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 16:06:12,609 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-23 16:06:12,610 INFO L811 eck$LassoCheckResult]: loop already infeasible [2018-11-23 16:06:12,610 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-23 16:06:12,610 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-23 16:06:12,610 INFO L87 Difference]: Start difference. First operand 812 states and 1226 transitions. cyclomatic complexity: 415 Second operand 3 states. [2018-11-23 16:06:12,624 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 16:06:12,625 INFO L93 Difference]: Finished difference Result 812 states and 1225 transitions. [2018-11-23 16:06:12,625 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-23 16:06:12,626 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 812 states and 1225 transitions. [2018-11-23 16:06:12,631 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 713 [2018-11-23 16:06:12,634 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 812 states to 812 states and 1225 transitions. [2018-11-23 16:06:12,635 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 812 [2018-11-23 16:06:12,635 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 812 [2018-11-23 16:06:12,636 INFO L73 IsDeterministic]: Start isDeterministic. Operand 812 states and 1225 transitions. [2018-11-23 16:06:12,637 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-23 16:06:12,637 INFO L705 BuchiCegarLoop]: Abstraction has 812 states and 1225 transitions. [2018-11-23 16:06:12,638 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 812 states and 1225 transitions. [2018-11-23 16:06:12,648 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 812 to 812. [2018-11-23 16:06:12,648 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 812 states. [2018-11-23 16:06:12,650 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 812 states to 812 states and 1225 transitions. [2018-11-23 16:06:12,651 INFO L728 BuchiCegarLoop]: Abstraction has 812 states and 1225 transitions. [2018-11-23 16:06:12,651 INFO L608 BuchiCegarLoop]: Abstraction has 812 states and 1225 transitions. [2018-11-23 16:06:12,651 INFO L442 BuchiCegarLoop]: ======== Iteration 3============ [2018-11-23 16:06:12,651 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 812 states and 1225 transitions. [2018-11-23 16:06:12,654 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 713 [2018-11-23 16:06:12,654 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-23 16:06:12,655 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-23 16:06:12,656 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 16:06:12,656 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 16:06:12,657 INFO L794 eck$LassoCheckResult]: Stem: 3729#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; 3638#L-1 havoc main_#res;havoc main_~__retres1~9;havoc main_~__retres1~9;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 3639#L1143 havoc start_simulation_#t~ret20, start_simulation_#t~ret21, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 3610#L531 assume 1 == ~m_i~0;~m_st~0 := 0; 3611#L538-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 3880#L543-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 3792#L548-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 3612#L553-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 3613#L558-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 3944#L563-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 3788#L568-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 3596#L573-1 assume !(0 == ~M_E~0); 3597#L771-1 assume 0 == ~T1_E~0;~T1_E~0 := 1; 3457#L776-1 assume !(0 == ~T2_E~0); 3458#L781-1 assume !(0 == ~T3_E~0); 3843#L786-1 assume !(0 == ~T4_E~0); 3684#L791-1 assume !(0 == ~T5_E~0); 3396#L796-1 assume !(0 == ~T6_E~0); 3397#L801-1 assume !(0 == ~T7_E~0); 4006#L806-1 assume !(0 == ~E_M~0); 3756#L811-1 assume 0 == ~E_1~0;~E_1~0 := 1; 3548#L816-1 assume !(0 == ~E_2~0); 3549#L821-1 assume !(0 == ~E_3~0); 4040#L826-1 assume !(0 == ~E_4~0); 3911#L831-1 assume !(0 == ~E_5~0); 3744#L836-1 assume !(0 == ~E_6~0); 3306#L841-1 assume !(0 == ~E_7~0); 3307#L846-1 havoc activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 3380#L378 assume !(1 == ~m_pc~0); 3354#L378-2 is_master_triggered_~__retres1~0 := 0; 3355#L389 is_master_triggered_#res := is_master_triggered_~__retres1~0; 3887#L390 activate_threads_#t~ret11 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 3925#L957 assume !(0 != activate_threads_~tmp~1); 4055#L957-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 3581#L397 assume 1 == ~t1_pc~0; 3499#L398 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 3500#L408 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 3929#L409 activate_threads_#t~ret12 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 3759#L965 assume !(0 != activate_threads_~tmp___0~0); 3750#L965-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 3751#L416 assume !(1 == ~t2_pc~0); 3664#L416-2 is_transmit2_triggered_~__retres1~2 := 0; 3663#L427 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 4023#L428 activate_threads_#t~ret13 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 3326#L973 assume !(0 != activate_threads_~tmp___1~0); 3327#L973-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 3332#L435 assume 1 == ~t3_pc~0; 3772#L436 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 3421#L446 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 3422#L447 activate_threads_#t~ret14 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 3963#L981 assume !(0 != activate_threads_~tmp___2~0); 3953#L981-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 3954#L454 assume 1 == ~t4_pc~0; 3883#L455 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 3616#L465 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 3374#L466 activate_threads_#t~ret15 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 3375#L989 assume !(0 != activate_threads_~tmp___3~0); 3688#L989-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 3690#L473 assume !(1 == ~t5_pc~0); 3996#L473-2 is_transmit5_triggered_~__retres1~5 := 0; 3734#L484 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 3599#L485 activate_threads_#t~ret16 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 3600#L997 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 4076#L997-2 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 4077#L492 assume 1 == ~t6_pc~0; 4080#L493 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6 := 1; 3827#L503 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 3793#L504 activate_threads_#t~ret17 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 3794#L1005 assume !(0 != activate_threads_~tmp___5~0); 3998#L1005-2 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 3295#L511 assume !(1 == ~t7_pc~0); 3296#L511-2 is_transmit7_triggered_~__retres1~7 := 0; 3451#L522 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 3840#L523 activate_threads_#t~ret18 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 3727#L1013 assume !(0 != activate_threads_~tmp___6~0); 3720#L1013-2 assume !(1 == ~M_E~0); 3721#L859-1 assume !(1 == ~T1_E~0); 3470#L864-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 3471#L869-1 assume !(1 == ~T3_E~0); 3841#L874-1 assume !(1 == ~T4_E~0); 3678#L879-1 assume !(1 == ~T5_E~0); 3392#L884-1 assume !(1 == ~T6_E~0); 3393#L889-1 assume !(1 == ~T7_E~0); 4004#L894-1 assume !(1 == ~E_M~0); 3752#L899-1 assume !(1 == ~E_1~0); 3541#L904-1 assume 1 == ~E_2~0;~E_2~0 := 2; 3542#L909-1 assume !(1 == ~E_3~0); 4043#L914-1 assume !(1 == ~E_4~0); 3913#L919-1 assume !(1 == ~E_5~0); 3749#L924-1 assume !(1 == ~E_6~0); 3335#L929-1 assume !(1 == ~E_7~0); 3336#L1180-1 [2018-11-23 16:06:12,657 INFO L796 eck$LassoCheckResult]: Loop: 3336#L1180-1 assume !false; 3999#L1181 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret2, eval_#t~nondet3, eval_~tmp_ndt_1~0, eval_#t~nondet4, eval_~tmp_ndt_2~0, eval_#t~nondet5, eval_~tmp_ndt_3~0, eval_#t~nondet6, eval_~tmp_ndt_4~0, eval_#t~nondet7, eval_~tmp_ndt_5~0, eval_#t~nondet8, eval_~tmp_ndt_6~0, eval_#t~nondet9, eval_~tmp_ndt_7~0, eval_#t~nondet10, eval_~tmp_ndt_8~0, eval_~tmp~0;havoc eval_~tmp~0; 3461#L746 assume !false; 3717#L639 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~8;havoc exists_runnable_thread_~__retres1~8; 3718#L586 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8 := 1; 3387#L628 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; 3951#L629 eval_#t~ret2 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret2;havoc eval_#t~ret2; 3281#L643 assume !(0 != eval_~tmp~0); 3283#L761 start_simulation_~kernel_st~0 := 2; 3614#L531-1 start_simulation_~kernel_st~0 := 3; 3615#L771-2 assume 0 == ~M_E~0;~M_E~0 := 1; 3714#L771-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 3463#L776-3 assume !(0 == ~T2_E~0); 3464#L781-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 3844#L786-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 3671#L791-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 3384#L796-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 3385#L801-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 4003#L806-3 assume 0 == ~E_M~0;~E_M~0 := 1; 3831#L811-3 assume 0 == ~E_1~0;~E_1~0 := 1; 3531#L816-3 assume !(0 == ~E_2~0); 3532#L821-3 assume 0 == ~E_3~0;~E_3~0 := 1; 4041#L826-3 assume 0 == ~E_4~0;~E_4~0 := 1; 3912#L831-3 assume 0 == ~E_5~0;~E_5~0 := 1; 3745#L836-3 assume 0 == ~E_6~0;~E_6~0 := 1; 3316#L841-3 assume 0 == ~E_7~0;~E_7~0 := 1; 3317#L846-3 havoc activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 3298#L378-27 assume 1 == ~m_pc~0; 3299#L379-9 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 3475#L389-9 is_master_triggered_#res := is_master_triggered_~__retres1~0; 3854#L390-9 activate_threads_#t~ret11 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 3916#L957-27 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 4047#L957-29 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 3520#L397-27 assume !(1 == ~t1_pc~0); 3521#L397-29 is_transmit1_triggered_~__retres1~1 := 0; 3523#L408-9 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 3981#L409-9 activate_threads_#t~ret12 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 3812#L965-27 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 3804#L965-29 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 3676#L416-27 assume 1 == ~t2_pc~0; 3628#L417-9 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 3629#L427-9 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 4014#L428-9 activate_threads_#t~ret13 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 3476#L973-27 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 3477#L973-29 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 3483#L435-27 assume 1 == ~t3_pc~0; 3767#L436-9 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 3418#L446-9 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 3419#L447-9 activate_threads_#t~ret14 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 4012#L981-27 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 4007#L981-29 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 3893#L454-27 assume 1 == ~t4_pc~0; 3847#L455-9 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 3603#L465-9 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 3341#L466-9 activate_threads_#t~ret15 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 3342#L989-27 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 3631#L989-29 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 3635#L473-27 assume 1 == ~t5_pc~0; 3973#L474-9 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 3732#L484-9 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 3566#L485-9 activate_threads_#t~ret16 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 3567#L997-27 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 4057#L997-29 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 4058#L492-27 assume 1 == ~t6_pc~0; 4026#L493-9 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6 := 1; 3808#L503-9 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 3710#L504-9 activate_threads_#t~ret17 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 3711#L1005-27 assume !(0 != activate_threads_~tmp___5~0); 3853#L1005-29 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 3449#L511-27 assume 1 == ~t7_pc~0; 3410#L512-9 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7 := 1; 3411#L522-9 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 3900#L523-9 activate_threads_#t~ret18 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 3572#L1013-27 assume 0 != activate_threads_~tmp___6~0;~t7_st~0 := 0; 3551#L1013-29 assume 1 == ~M_E~0;~M_E~0 := 2; 3552#L859-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 3455#L864-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 3456#L869-3 assume !(1 == ~T3_E~0); 3842#L874-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 3683#L879-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 3394#L884-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 3395#L889-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 4005#L894-3 assume 1 == ~E_M~0;~E_M~0 := 2; 3755#L899-3 assume 1 == ~E_1~0;~E_1~0 := 2; 3546#L904-3 assume 1 == ~E_2~0;~E_2~0 := 2; 3547#L909-3 assume !(1 == ~E_3~0); 4044#L914-3 assume 1 == ~E_4~0;~E_4~0 := 2; 3910#L919-3 assume 1 == ~E_5~0;~E_5~0 := 2; 3743#L924-3 assume 1 == ~E_6~0;~E_6~0 := 2; 3304#L929-3 assume 1 == ~E_7~0;~E_7~0 := 2; 3305#L934-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~8;havoc exists_runnable_thread_~__retres1~8; 4000#L586-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8 := 1; 3391#L628-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; 3938#L629-1 start_simulation_#t~ret20 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret20;havoc start_simulation_#t~ret20; 3939#L1199 assume !(0 == start_simulation_~tmp~3); 3856#L1199-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret19, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~8;havoc exists_runnable_thread_~__retres1~8; 4001#L586-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8 := 1; 3369#L628-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; 3942#L629-2 stop_simulation_#t~ret19 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret19;havoc stop_simulation_#t~ret19; 3943#L1154 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 3914#L1161 stop_simulation_#res := stop_simulation_~__retres2~0; 3902#L1162 start_simulation_#t~ret21 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret21;havoc start_simulation_#t~ret21; 3568#L1212 assume !(0 != start_simulation_~tmp___0~1); 3336#L1180-1 [2018-11-23 16:06:12,657 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 16:06:12,657 INFO L82 PathProgramCache]: Analyzing trace with hash 1415640477, now seen corresponding path program 1 times [2018-11-23 16:06:12,657 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 16:06:12,657 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 16:06:12,658 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 16:06:12,658 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 16:06:12,658 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 16:06:12,666 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 16:06:12,701 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 16:06:12,701 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 16:06:12,701 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-23 16:06:12,701 INFO L799 eck$LassoCheckResult]: stem already infeasible [2018-11-23 16:06:12,702 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 16:06:12,702 INFO L82 PathProgramCache]: Analyzing trace with hash 2056175835, now seen corresponding path program 2 times [2018-11-23 16:06:12,702 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 16:06:12,702 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 16:06:12,703 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 16:06:12,703 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 16:06:12,703 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 16:06:12,715 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 16:06:12,768 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 16:06:12,768 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 16:06:12,768 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-23 16:06:12,769 INFO L811 eck$LassoCheckResult]: loop already infeasible [2018-11-23 16:06:12,769 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-23 16:06:12,769 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-23 16:06:12,769 INFO L87 Difference]: Start difference. First operand 812 states and 1225 transitions. cyclomatic complexity: 414 Second operand 3 states. [2018-11-23 16:06:12,784 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 16:06:12,784 INFO L93 Difference]: Finished difference Result 812 states and 1224 transitions. [2018-11-23 16:06:12,785 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-23 16:06:12,785 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 812 states and 1224 transitions. [2018-11-23 16:06:12,787 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 713 [2018-11-23 16:06:12,789 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 812 states to 812 states and 1224 transitions. [2018-11-23 16:06:12,789 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 812 [2018-11-23 16:06:12,790 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 812 [2018-11-23 16:06:12,790 INFO L73 IsDeterministic]: Start isDeterministic. Operand 812 states and 1224 transitions. [2018-11-23 16:06:12,791 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-23 16:06:12,791 INFO L705 BuchiCegarLoop]: Abstraction has 812 states and 1224 transitions. [2018-11-23 16:06:12,792 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 812 states and 1224 transitions. [2018-11-23 16:06:12,796 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 812 to 812. [2018-11-23 16:06:12,797 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 812 states. [2018-11-23 16:06:12,798 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 812 states to 812 states and 1224 transitions. [2018-11-23 16:06:12,798 INFO L728 BuchiCegarLoop]: Abstraction has 812 states and 1224 transitions. [2018-11-23 16:06:12,798 INFO L608 BuchiCegarLoop]: Abstraction has 812 states and 1224 transitions. [2018-11-23 16:06:12,798 INFO L442 BuchiCegarLoop]: ======== Iteration 4============ [2018-11-23 16:06:12,798 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 812 states and 1224 transitions. [2018-11-23 16:06:12,800 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 713 [2018-11-23 16:06:12,800 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-23 16:06:12,800 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-23 16:06:12,802 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 16:06:12,802 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 16:06:12,802 INFO L794 eck$LassoCheckResult]: Stem: 5360#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; 5269#L-1 havoc main_#res;havoc main_~__retres1~9;havoc main_~__retres1~9;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 5270#L1143 havoc start_simulation_#t~ret20, start_simulation_#t~ret21, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 5241#L531 assume 1 == ~m_i~0;~m_st~0 := 0; 5242#L538-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 5511#L543-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 5423#L548-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 5243#L553-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 5244#L558-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 5575#L563-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 5419#L568-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 5227#L573-1 assume !(0 == ~M_E~0); 5228#L771-1 assume 0 == ~T1_E~0;~T1_E~0 := 1; 5088#L776-1 assume !(0 == ~T2_E~0); 5089#L781-1 assume !(0 == ~T3_E~0); 5474#L786-1 assume !(0 == ~T4_E~0); 5315#L791-1 assume !(0 == ~T5_E~0); 5027#L796-1 assume !(0 == ~T6_E~0); 5028#L801-1 assume !(0 == ~T7_E~0); 5637#L806-1 assume !(0 == ~E_M~0); 5387#L811-1 assume 0 == ~E_1~0;~E_1~0 := 1; 5179#L816-1 assume !(0 == ~E_2~0); 5180#L821-1 assume !(0 == ~E_3~0); 5671#L826-1 assume !(0 == ~E_4~0); 5542#L831-1 assume !(0 == ~E_5~0); 5375#L836-1 assume !(0 == ~E_6~0); 4937#L841-1 assume !(0 == ~E_7~0); 4938#L846-1 havoc activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 5011#L378 assume !(1 == ~m_pc~0); 4985#L378-2 is_master_triggered_~__retres1~0 := 0; 4986#L389 is_master_triggered_#res := is_master_triggered_~__retres1~0; 5518#L390 activate_threads_#t~ret11 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 5556#L957 assume !(0 != activate_threads_~tmp~1); 5686#L957-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 5212#L397 assume 1 == ~t1_pc~0; 5130#L398 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 5131#L408 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 5560#L409 activate_threads_#t~ret12 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 5390#L965 assume !(0 != activate_threads_~tmp___0~0); 5381#L965-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 5382#L416 assume !(1 == ~t2_pc~0); 5295#L416-2 is_transmit2_triggered_~__retres1~2 := 0; 5294#L427 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 5654#L428 activate_threads_#t~ret13 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 4957#L973 assume !(0 != activate_threads_~tmp___1~0); 4958#L973-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 4963#L435 assume 1 == ~t3_pc~0; 5403#L436 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 5052#L446 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 5053#L447 activate_threads_#t~ret14 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 5594#L981 assume !(0 != activate_threads_~tmp___2~0); 5584#L981-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 5585#L454 assume 1 == ~t4_pc~0; 5514#L455 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 5247#L465 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 5005#L466 activate_threads_#t~ret15 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 5006#L989 assume !(0 != activate_threads_~tmp___3~0); 5319#L989-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 5321#L473 assume !(1 == ~t5_pc~0); 5627#L473-2 is_transmit5_triggered_~__retres1~5 := 0; 5365#L484 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 5230#L485 activate_threads_#t~ret16 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 5231#L997 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 5707#L997-2 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 5708#L492 assume 1 == ~t6_pc~0; 5711#L493 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6 := 1; 5458#L503 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 5424#L504 activate_threads_#t~ret17 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 5425#L1005 assume !(0 != activate_threads_~tmp___5~0); 5629#L1005-2 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 4926#L511 assume !(1 == ~t7_pc~0); 4927#L511-2 is_transmit7_triggered_~__retres1~7 := 0; 5082#L522 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 5471#L523 activate_threads_#t~ret18 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 5358#L1013 assume !(0 != activate_threads_~tmp___6~0); 5351#L1013-2 assume !(1 == ~M_E~0); 5352#L859-1 assume !(1 == ~T1_E~0); 5101#L864-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 5102#L869-1 assume !(1 == ~T3_E~0); 5472#L874-1 assume !(1 == ~T4_E~0); 5309#L879-1 assume !(1 == ~T5_E~0); 5023#L884-1 assume !(1 == ~T6_E~0); 5024#L889-1 assume !(1 == ~T7_E~0); 5635#L894-1 assume !(1 == ~E_M~0); 5383#L899-1 assume !(1 == ~E_1~0); 5172#L904-1 assume 1 == ~E_2~0;~E_2~0 := 2; 5173#L909-1 assume !(1 == ~E_3~0); 5674#L914-1 assume !(1 == ~E_4~0); 5544#L919-1 assume !(1 == ~E_5~0); 5380#L924-1 assume !(1 == ~E_6~0); 4966#L929-1 assume !(1 == ~E_7~0); 4967#L1180-1 [2018-11-23 16:06:12,806 INFO L796 eck$LassoCheckResult]: Loop: 4967#L1180-1 assume !false; 5630#L1181 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret2, eval_#t~nondet3, eval_~tmp_ndt_1~0, eval_#t~nondet4, eval_~tmp_ndt_2~0, eval_#t~nondet5, eval_~tmp_ndt_3~0, eval_#t~nondet6, eval_~tmp_ndt_4~0, eval_#t~nondet7, eval_~tmp_ndt_5~0, eval_#t~nondet8, eval_~tmp_ndt_6~0, eval_#t~nondet9, eval_~tmp_ndt_7~0, eval_#t~nondet10, eval_~tmp_ndt_8~0, eval_~tmp~0;havoc eval_~tmp~0; 5092#L746 assume !false; 5348#L639 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~8;havoc exists_runnable_thread_~__retres1~8; 5349#L586 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8 := 1; 5018#L628 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; 5582#L629 eval_#t~ret2 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret2;havoc eval_#t~ret2; 4912#L643 assume !(0 != eval_~tmp~0); 4914#L761 start_simulation_~kernel_st~0 := 2; 5245#L531-1 start_simulation_~kernel_st~0 := 3; 5246#L771-2 assume 0 == ~M_E~0;~M_E~0 := 1; 5345#L771-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 5094#L776-3 assume !(0 == ~T2_E~0); 5095#L781-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 5475#L786-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 5302#L791-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 5015#L796-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 5016#L801-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 5634#L806-3 assume 0 == ~E_M~0;~E_M~0 := 1; 5462#L811-3 assume 0 == ~E_1~0;~E_1~0 := 1; 5162#L816-3 assume !(0 == ~E_2~0); 5163#L821-3 assume 0 == ~E_3~0;~E_3~0 := 1; 5672#L826-3 assume 0 == ~E_4~0;~E_4~0 := 1; 5543#L831-3 assume 0 == ~E_5~0;~E_5~0 := 1; 5376#L836-3 assume 0 == ~E_6~0;~E_6~0 := 1; 4947#L841-3 assume 0 == ~E_7~0;~E_7~0 := 1; 4948#L846-3 havoc activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 4929#L378-27 assume 1 == ~m_pc~0; 4930#L379-9 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 5106#L389-9 is_master_triggered_#res := is_master_triggered_~__retres1~0; 5485#L390-9 activate_threads_#t~ret11 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 5547#L957-27 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 5678#L957-29 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 5151#L397-27 assume !(1 == ~t1_pc~0); 5152#L397-29 is_transmit1_triggered_~__retres1~1 := 0; 5154#L408-9 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 5612#L409-9 activate_threads_#t~ret12 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 5443#L965-27 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 5435#L965-29 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 5307#L416-27 assume 1 == ~t2_pc~0; 5259#L417-9 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 5260#L427-9 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 5645#L428-9 activate_threads_#t~ret13 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 5107#L973-27 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 5108#L973-29 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 5114#L435-27 assume 1 == ~t3_pc~0; 5398#L436-9 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 5049#L446-9 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 5050#L447-9 activate_threads_#t~ret14 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 5643#L981-27 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 5638#L981-29 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 5524#L454-27 assume 1 == ~t4_pc~0; 5478#L455-9 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 5234#L465-9 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 4972#L466-9 activate_threads_#t~ret15 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 4973#L989-27 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 5262#L989-29 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 5266#L473-27 assume 1 == ~t5_pc~0; 5604#L474-9 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 5363#L484-9 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 5197#L485-9 activate_threads_#t~ret16 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 5198#L997-27 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 5688#L997-29 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 5689#L492-27 assume 1 == ~t6_pc~0; 5657#L493-9 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6 := 1; 5439#L503-9 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 5341#L504-9 activate_threads_#t~ret17 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 5342#L1005-27 assume !(0 != activate_threads_~tmp___5~0); 5484#L1005-29 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 5080#L511-27 assume 1 == ~t7_pc~0; 5041#L512-9 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7 := 1; 5042#L522-9 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 5531#L523-9 activate_threads_#t~ret18 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 5203#L1013-27 assume 0 != activate_threads_~tmp___6~0;~t7_st~0 := 0; 5182#L1013-29 assume 1 == ~M_E~0;~M_E~0 := 2; 5183#L859-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 5086#L864-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 5087#L869-3 assume !(1 == ~T3_E~0); 5473#L874-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 5314#L879-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 5025#L884-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 5026#L889-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 5636#L894-3 assume 1 == ~E_M~0;~E_M~0 := 2; 5386#L899-3 assume 1 == ~E_1~0;~E_1~0 := 2; 5177#L904-3 assume 1 == ~E_2~0;~E_2~0 := 2; 5178#L909-3 assume !(1 == ~E_3~0); 5675#L914-3 assume 1 == ~E_4~0;~E_4~0 := 2; 5541#L919-3 assume 1 == ~E_5~0;~E_5~0 := 2; 5374#L924-3 assume 1 == ~E_6~0;~E_6~0 := 2; 4935#L929-3 assume 1 == ~E_7~0;~E_7~0 := 2; 4936#L934-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~8;havoc exists_runnable_thread_~__retres1~8; 5631#L586-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8 := 1; 5022#L628-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; 5569#L629-1 start_simulation_#t~ret20 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret20;havoc start_simulation_#t~ret20; 5570#L1199 assume !(0 == start_simulation_~tmp~3); 5487#L1199-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret19, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~8;havoc exists_runnable_thread_~__retres1~8; 5632#L586-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8 := 1; 5000#L628-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; 5573#L629-2 stop_simulation_#t~ret19 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret19;havoc stop_simulation_#t~ret19; 5574#L1154 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 5545#L1161 stop_simulation_#res := stop_simulation_~__retres2~0; 5533#L1162 start_simulation_#t~ret21 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret21;havoc start_simulation_#t~ret21; 5199#L1212 assume !(0 != start_simulation_~tmp___0~1); 4967#L1180-1 [2018-11-23 16:06:12,807 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 16:06:12,807 INFO L82 PathProgramCache]: Analyzing trace with hash -460842341, now seen corresponding path program 1 times [2018-11-23 16:06:12,807 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 16:06:12,807 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 16:06:12,808 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 16:06:12,808 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-23 16:06:12,808 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 16:06:12,813 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 16:06:12,833 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 16:06:12,833 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 16:06:12,833 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-23 16:06:12,833 INFO L799 eck$LassoCheckResult]: stem already infeasible [2018-11-23 16:06:12,834 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 16:06:12,834 INFO L82 PathProgramCache]: Analyzing trace with hash 2056175835, now seen corresponding path program 3 times [2018-11-23 16:06:12,834 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 16:06:12,834 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 16:06:12,835 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 16:06:12,835 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 16:06:12,835 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 16:06:12,842 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 16:06:12,874 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 16:06:12,875 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 16:06:12,875 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-23 16:06:12,875 INFO L811 eck$LassoCheckResult]: loop already infeasible [2018-11-23 16:06:12,875 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-23 16:06:12,875 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-23 16:06:12,875 INFO L87 Difference]: Start difference. First operand 812 states and 1224 transitions. cyclomatic complexity: 413 Second operand 3 states. [2018-11-23 16:06:12,887 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 16:06:12,888 INFO L93 Difference]: Finished difference Result 812 states and 1223 transitions. [2018-11-23 16:06:12,888 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-23 16:06:12,888 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 812 states and 1223 transitions. [2018-11-23 16:06:12,891 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 713 [2018-11-23 16:06:12,893 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 812 states to 812 states and 1223 transitions. [2018-11-23 16:06:12,893 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 812 [2018-11-23 16:06:12,893 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 812 [2018-11-23 16:06:12,894 INFO L73 IsDeterministic]: Start isDeterministic. Operand 812 states and 1223 transitions. [2018-11-23 16:06:12,894 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-23 16:06:12,894 INFO L705 BuchiCegarLoop]: Abstraction has 812 states and 1223 transitions. [2018-11-23 16:06:12,895 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 812 states and 1223 transitions. [2018-11-23 16:06:12,900 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 812 to 812. [2018-11-23 16:06:12,900 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 812 states. [2018-11-23 16:06:12,902 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 812 states to 812 states and 1223 transitions. [2018-11-23 16:06:12,902 INFO L728 BuchiCegarLoop]: Abstraction has 812 states and 1223 transitions. [2018-11-23 16:06:12,902 INFO L608 BuchiCegarLoop]: Abstraction has 812 states and 1223 transitions. [2018-11-23 16:06:12,902 INFO L442 BuchiCegarLoop]: ======== Iteration 5============ [2018-11-23 16:06:12,902 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 812 states and 1223 transitions. [2018-11-23 16:06:12,904 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 713 [2018-11-23 16:06:12,904 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-23 16:06:12,904 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-23 16:06:12,905 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 16:06:12,905 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 16:06:12,905 INFO L794 eck$LassoCheckResult]: Stem: 6991#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; 6900#L-1 havoc main_#res;havoc main_~__retres1~9;havoc main_~__retres1~9;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 6901#L1143 havoc start_simulation_#t~ret20, start_simulation_#t~ret21, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 6872#L531 assume 1 == ~m_i~0;~m_st~0 := 0; 6873#L538-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 7143#L543-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 7054#L548-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 6874#L553-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 6875#L558-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 7206#L563-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 7050#L568-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 6858#L573-1 assume !(0 == ~M_E~0); 6859#L771-1 assume 0 == ~T1_E~0;~T1_E~0 := 1; 6720#L776-1 assume !(0 == ~T2_E~0); 6721#L781-1 assume !(0 == ~T3_E~0); 7105#L786-1 assume !(0 == ~T4_E~0); 6946#L791-1 assume !(0 == ~T5_E~0); 6658#L796-1 assume !(0 == ~T6_E~0); 6659#L801-1 assume !(0 == ~T7_E~0); 7268#L806-1 assume !(0 == ~E_M~0); 7018#L811-1 assume 0 == ~E_1~0;~E_1~0 := 1; 6810#L816-1 assume !(0 == ~E_2~0); 6811#L821-1 assume !(0 == ~E_3~0); 7302#L826-1 assume !(0 == ~E_4~0); 7173#L831-1 assume !(0 == ~E_5~0); 7006#L836-1 assume !(0 == ~E_6~0); 6568#L841-1 assume !(0 == ~E_7~0); 6569#L846-1 havoc activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 6642#L378 assume !(1 == ~m_pc~0); 6616#L378-2 is_master_triggered_~__retres1~0 := 0; 6617#L389 is_master_triggered_#res := is_master_triggered_~__retres1~0; 7151#L390 activate_threads_#t~ret11 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 7187#L957 assume !(0 != activate_threads_~tmp~1); 7317#L957-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 6843#L397 assume 1 == ~t1_pc~0; 6761#L398 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 6762#L408 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 7191#L409 activate_threads_#t~ret12 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 7021#L965 assume !(0 != activate_threads_~tmp___0~0); 7012#L965-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 7013#L416 assume !(1 == ~t2_pc~0); 6926#L416-2 is_transmit2_triggered_~__retres1~2 := 0; 6925#L427 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 7285#L428 activate_threads_#t~ret13 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 6588#L973 assume !(0 != activate_threads_~tmp___1~0); 6589#L973-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 6594#L435 assume 1 == ~t3_pc~0; 7034#L436 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 6686#L446 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 6687#L447 activate_threads_#t~ret14 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 7225#L981 assume !(0 != activate_threads_~tmp___2~0); 7215#L981-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 7216#L454 assume 1 == ~t4_pc~0; 7145#L455 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 6878#L465 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 6636#L466 activate_threads_#t~ret15 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 6637#L989 assume !(0 != activate_threads_~tmp___3~0); 6950#L989-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 6952#L473 assume !(1 == ~t5_pc~0); 7258#L473-2 is_transmit5_triggered_~__retres1~5 := 0; 6996#L484 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 6861#L485 activate_threads_#t~ret16 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 6862#L997 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 7338#L997-2 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 7339#L492 assume 1 == ~t6_pc~0; 7342#L493 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6 := 1; 7089#L503 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 7055#L504 activate_threads_#t~ret17 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 7056#L1005 assume !(0 != activate_threads_~tmp___5~0); 7260#L1005-2 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 6557#L511 assume !(1 == ~t7_pc~0); 6558#L511-2 is_transmit7_triggered_~__retres1~7 := 0; 6713#L522 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 7102#L523 activate_threads_#t~ret18 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 6989#L1013 assume !(0 != activate_threads_~tmp___6~0); 6982#L1013-2 assume !(1 == ~M_E~0); 6983#L859-1 assume !(1 == ~T1_E~0); 6732#L864-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 6733#L869-1 assume !(1 == ~T3_E~0); 7103#L874-1 assume !(1 == ~T4_E~0); 6940#L879-1 assume !(1 == ~T5_E~0); 6654#L884-1 assume !(1 == ~T6_E~0); 6655#L889-1 assume !(1 == ~T7_E~0); 7266#L894-1 assume !(1 == ~E_M~0); 7014#L899-1 assume !(1 == ~E_1~0); 6803#L904-1 assume 1 == ~E_2~0;~E_2~0 := 2; 6804#L909-1 assume !(1 == ~E_3~0); 7305#L914-1 assume !(1 == ~E_4~0); 7175#L919-1 assume !(1 == ~E_5~0); 7011#L924-1 assume !(1 == ~E_6~0); 6597#L929-1 assume !(1 == ~E_7~0); 6598#L1180-1 [2018-11-23 16:06:12,906 INFO L796 eck$LassoCheckResult]: Loop: 6598#L1180-1 assume !false; 7261#L1181 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret2, eval_#t~nondet3, eval_~tmp_ndt_1~0, eval_#t~nondet4, eval_~tmp_ndt_2~0, eval_#t~nondet5, eval_~tmp_ndt_3~0, eval_#t~nondet6, eval_~tmp_ndt_4~0, eval_#t~nondet7, eval_~tmp_ndt_5~0, eval_#t~nondet8, eval_~tmp_ndt_6~0, eval_#t~nondet9, eval_~tmp_ndt_7~0, eval_#t~nondet10, eval_~tmp_ndt_8~0, eval_~tmp~0;havoc eval_~tmp~0; 6723#L746 assume !false; 6980#L639 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~8;havoc exists_runnable_thread_~__retres1~8; 6981#L586 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8 := 1; 6649#L628 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; 7213#L629 eval_#t~ret2 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret2;havoc eval_#t~ret2; 6543#L643 assume !(0 != eval_~tmp~0); 6545#L761 start_simulation_~kernel_st~0 := 2; 6876#L531-1 start_simulation_~kernel_st~0 := 3; 6877#L771-2 assume 0 == ~M_E~0;~M_E~0 := 1; 6978#L771-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 6725#L776-3 assume !(0 == ~T2_E~0); 6726#L781-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 7106#L786-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 6934#L791-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 6646#L796-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 6647#L801-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 7265#L806-3 assume 0 == ~E_M~0;~E_M~0 := 1; 7093#L811-3 assume 0 == ~E_1~0;~E_1~0 := 1; 6793#L816-3 assume !(0 == ~E_2~0); 6794#L821-3 assume 0 == ~E_3~0;~E_3~0 := 1; 7303#L826-3 assume 0 == ~E_4~0;~E_4~0 := 1; 7174#L831-3 assume 0 == ~E_5~0;~E_5~0 := 1; 7007#L836-3 assume 0 == ~E_6~0;~E_6~0 := 1; 6578#L841-3 assume 0 == ~E_7~0;~E_7~0 := 1; 6579#L846-3 havoc activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 6560#L378-27 assume 1 == ~m_pc~0; 6561#L379-9 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 6739#L389-9 is_master_triggered_#res := is_master_triggered_~__retres1~0; 7116#L390-9 activate_threads_#t~ret11 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 7178#L957-27 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 7309#L957-29 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 6782#L397-27 assume 1 == ~t1_pc~0; 6784#L398-9 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 6785#L408-9 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 7243#L409-9 activate_threads_#t~ret12 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 7074#L965-27 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 7066#L965-29 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 6938#L416-27 assume 1 == ~t2_pc~0; 6890#L417-9 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 6891#L427-9 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 7276#L428-9 activate_threads_#t~ret13 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 6737#L973-27 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 6738#L973-29 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 6745#L435-27 assume 1 == ~t3_pc~0; 7029#L436-9 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 6680#L446-9 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 6681#L447-9 activate_threads_#t~ret14 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 7274#L981-27 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 7269#L981-29 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 7155#L454-27 assume 1 == ~t4_pc~0; 7108#L455-9 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 6865#L465-9 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 6603#L466-9 activate_threads_#t~ret15 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 6604#L989-27 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 6893#L989-29 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 6897#L473-27 assume 1 == ~t5_pc~0; 7234#L474-9 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 6994#L484-9 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 6828#L485-9 activate_threads_#t~ret16 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 6829#L997-27 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 7319#L997-29 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 7320#L492-27 assume 1 == ~t6_pc~0; 7288#L493-9 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6 := 1; 7069#L503-9 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 6972#L504-9 activate_threads_#t~ret17 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 6973#L1005-27 assume !(0 != activate_threads_~tmp___5~0); 7115#L1005-29 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 6711#L511-27 assume 1 == ~t7_pc~0; 6672#L512-9 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7 := 1; 6673#L522-9 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 7162#L523-9 activate_threads_#t~ret18 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 6834#L1013-27 assume 0 != activate_threads_~tmp___6~0;~t7_st~0 := 0; 6813#L1013-29 assume 1 == ~M_E~0;~M_E~0 := 2; 6814#L859-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 6717#L864-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 6718#L869-3 assume !(1 == ~T3_E~0); 7104#L874-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 6945#L879-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 6656#L884-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 6657#L889-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 7267#L894-3 assume 1 == ~E_M~0;~E_M~0 := 2; 7017#L899-3 assume 1 == ~E_1~0;~E_1~0 := 2; 6808#L904-3 assume 1 == ~E_2~0;~E_2~0 := 2; 6809#L909-3 assume !(1 == ~E_3~0); 7306#L914-3 assume 1 == ~E_4~0;~E_4~0 := 2; 7172#L919-3 assume 1 == ~E_5~0;~E_5~0 := 2; 7005#L924-3 assume 1 == ~E_6~0;~E_6~0 := 2; 6566#L929-3 assume 1 == ~E_7~0;~E_7~0 := 2; 6567#L934-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~8;havoc exists_runnable_thread_~__retres1~8; 7262#L586-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8 := 1; 6653#L628-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; 7200#L629-1 start_simulation_#t~ret20 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret20;havoc start_simulation_#t~ret20; 7201#L1199 assume !(0 == start_simulation_~tmp~3); 7118#L1199-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret19, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~8;havoc exists_runnable_thread_~__retres1~8; 7263#L586-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8 := 1; 6631#L628-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; 7204#L629-2 stop_simulation_#t~ret19 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret19;havoc stop_simulation_#t~ret19; 7205#L1154 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 7176#L1161 stop_simulation_#res := stop_simulation_~__retres2~0; 7164#L1162 start_simulation_#t~ret21 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret21;havoc start_simulation_#t~ret21; 6830#L1212 assume !(0 != start_simulation_~tmp___0~1); 6598#L1180-1 [2018-11-23 16:06:12,906 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 16:06:12,906 INFO L82 PathProgramCache]: Analyzing trace with hash 1418288605, now seen corresponding path program 1 times [2018-11-23 16:06:12,906 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 16:06:12,906 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 16:06:12,907 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 16:06:12,907 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-23 16:06:12,907 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 16:06:12,911 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 16:06:12,938 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 16:06:12,938 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 16:06:12,938 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-23 16:06:12,938 INFO L799 eck$LassoCheckResult]: stem already infeasible [2018-11-23 16:06:12,938 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 16:06:12,939 INFO L82 PathProgramCache]: Analyzing trace with hash 1149419388, now seen corresponding path program 1 times [2018-11-23 16:06:12,939 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 16:06:12,939 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 16:06:12,939 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 16:06:12,939 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 16:06:12,939 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 16:06:12,948 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 16:06:12,974 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 16:06:12,974 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 16:06:12,975 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-23 16:06:12,975 INFO L811 eck$LassoCheckResult]: loop already infeasible [2018-11-23 16:06:12,975 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-23 16:06:12,975 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-23 16:06:12,975 INFO L87 Difference]: Start difference. First operand 812 states and 1223 transitions. cyclomatic complexity: 412 Second operand 3 states. [2018-11-23 16:06:12,990 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 16:06:12,991 INFO L93 Difference]: Finished difference Result 812 states and 1222 transitions. [2018-11-23 16:06:12,991 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-23 16:06:12,991 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 812 states and 1222 transitions. [2018-11-23 16:06:12,994 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 713 [2018-11-23 16:06:12,995 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 812 states to 812 states and 1222 transitions. [2018-11-23 16:06:12,995 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 812 [2018-11-23 16:06:12,996 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 812 [2018-11-23 16:06:12,996 INFO L73 IsDeterministic]: Start isDeterministic. Operand 812 states and 1222 transitions. [2018-11-23 16:06:12,997 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-23 16:06:12,997 INFO L705 BuchiCegarLoop]: Abstraction has 812 states and 1222 transitions. [2018-11-23 16:06:12,998 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 812 states and 1222 transitions. [2018-11-23 16:06:13,003 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 812 to 812. [2018-11-23 16:06:13,003 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 812 states. [2018-11-23 16:06:13,004 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 812 states to 812 states and 1222 transitions. [2018-11-23 16:06:13,004 INFO L728 BuchiCegarLoop]: Abstraction has 812 states and 1222 transitions. [2018-11-23 16:06:13,004 INFO L608 BuchiCegarLoop]: Abstraction has 812 states and 1222 transitions. [2018-11-23 16:06:13,005 INFO L442 BuchiCegarLoop]: ======== Iteration 6============ [2018-11-23 16:06:13,005 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 812 states and 1222 transitions. [2018-11-23 16:06:13,007 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 713 [2018-11-23 16:06:13,007 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-23 16:06:13,007 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-23 16:06:13,008 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 16:06:13,008 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 16:06:13,008 INFO L794 eck$LassoCheckResult]: Stem: 8622#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; 8531#L-1 havoc main_#res;havoc main_~__retres1~9;havoc main_~__retres1~9;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 8532#L1143 havoc start_simulation_#t~ret20, start_simulation_#t~ret21, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 8503#L531 assume 1 == ~m_i~0;~m_st~0 := 0; 8504#L538-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 8773#L543-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 8685#L548-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 8505#L553-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 8506#L558-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 8837#L563-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 8681#L568-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 8489#L573-1 assume !(0 == ~M_E~0); 8490#L771-1 assume 0 == ~T1_E~0;~T1_E~0 := 1; 8350#L776-1 assume !(0 == ~T2_E~0); 8351#L781-1 assume !(0 == ~T3_E~0); 8736#L786-1 assume !(0 == ~T4_E~0); 8577#L791-1 assume !(0 == ~T5_E~0); 8289#L796-1 assume !(0 == ~T6_E~0); 8290#L801-1 assume !(0 == ~T7_E~0); 8899#L806-1 assume !(0 == ~E_M~0); 8649#L811-1 assume 0 == ~E_1~0;~E_1~0 := 1; 8441#L816-1 assume !(0 == ~E_2~0); 8442#L821-1 assume !(0 == ~E_3~0); 8933#L826-1 assume !(0 == ~E_4~0); 8804#L831-1 assume !(0 == ~E_5~0); 8637#L836-1 assume !(0 == ~E_6~0); 8199#L841-1 assume !(0 == ~E_7~0); 8200#L846-1 havoc activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 8273#L378 assume !(1 == ~m_pc~0); 8247#L378-2 is_master_triggered_~__retres1~0 := 0; 8248#L389 is_master_triggered_#res := is_master_triggered_~__retres1~0; 8780#L390 activate_threads_#t~ret11 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 8818#L957 assume !(0 != activate_threads_~tmp~1); 8948#L957-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 8474#L397 assume 1 == ~t1_pc~0; 8392#L398 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 8393#L408 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 8822#L409 activate_threads_#t~ret12 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 8652#L965 assume !(0 != activate_threads_~tmp___0~0); 8643#L965-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 8644#L416 assume !(1 == ~t2_pc~0); 8557#L416-2 is_transmit2_triggered_~__retres1~2 := 0; 8556#L427 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 8916#L428 activate_threads_#t~ret13 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 8219#L973 assume !(0 != activate_threads_~tmp___1~0); 8220#L973-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 8225#L435 assume 1 == ~t3_pc~0; 8665#L436 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 8314#L446 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 8315#L447 activate_threads_#t~ret14 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 8856#L981 assume !(0 != activate_threads_~tmp___2~0); 8846#L981-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 8847#L454 assume 1 == ~t4_pc~0; 8776#L455 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 8509#L465 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 8267#L466 activate_threads_#t~ret15 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 8268#L989 assume !(0 != activate_threads_~tmp___3~0); 8581#L989-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 8583#L473 assume !(1 == ~t5_pc~0); 8889#L473-2 is_transmit5_triggered_~__retres1~5 := 0; 8627#L484 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 8492#L485 activate_threads_#t~ret16 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 8493#L997 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 8969#L997-2 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 8970#L492 assume 1 == ~t6_pc~0; 8973#L493 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6 := 1; 8720#L503 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 8686#L504 activate_threads_#t~ret17 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 8687#L1005 assume !(0 != activate_threads_~tmp___5~0); 8891#L1005-2 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 8188#L511 assume !(1 == ~t7_pc~0); 8189#L511-2 is_transmit7_triggered_~__retres1~7 := 0; 8344#L522 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 8733#L523 activate_threads_#t~ret18 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 8620#L1013 assume !(0 != activate_threads_~tmp___6~0); 8613#L1013-2 assume !(1 == ~M_E~0); 8614#L859-1 assume !(1 == ~T1_E~0); 8363#L864-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 8364#L869-1 assume !(1 == ~T3_E~0); 8734#L874-1 assume !(1 == ~T4_E~0); 8571#L879-1 assume !(1 == ~T5_E~0); 8285#L884-1 assume !(1 == ~T6_E~0); 8286#L889-1 assume !(1 == ~T7_E~0); 8897#L894-1 assume !(1 == ~E_M~0); 8645#L899-1 assume !(1 == ~E_1~0); 8434#L904-1 assume 1 == ~E_2~0;~E_2~0 := 2; 8435#L909-1 assume !(1 == ~E_3~0); 8936#L914-1 assume !(1 == ~E_4~0); 8806#L919-1 assume !(1 == ~E_5~0); 8642#L924-1 assume !(1 == ~E_6~0); 8228#L929-1 assume !(1 == ~E_7~0); 8229#L1180-1 [2018-11-23 16:06:13,008 INFO L796 eck$LassoCheckResult]: Loop: 8229#L1180-1 assume !false; 8892#L1181 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret2, eval_#t~nondet3, eval_~tmp_ndt_1~0, eval_#t~nondet4, eval_~tmp_ndt_2~0, eval_#t~nondet5, eval_~tmp_ndt_3~0, eval_#t~nondet6, eval_~tmp_ndt_4~0, eval_#t~nondet7, eval_~tmp_ndt_5~0, eval_#t~nondet8, eval_~tmp_ndt_6~0, eval_#t~nondet9, eval_~tmp_ndt_7~0, eval_#t~nondet10, eval_~tmp_ndt_8~0, eval_~tmp~0;havoc eval_~tmp~0; 8354#L746 assume !false; 8610#L639 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~8;havoc exists_runnable_thread_~__retres1~8; 8611#L586 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8 := 1; 8280#L628 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; 8844#L629 eval_#t~ret2 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret2;havoc eval_#t~ret2; 8174#L643 assume !(0 != eval_~tmp~0); 8176#L761 start_simulation_~kernel_st~0 := 2; 8507#L531-1 start_simulation_~kernel_st~0 := 3; 8508#L771-2 assume 0 == ~M_E~0;~M_E~0 := 1; 8607#L771-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 8356#L776-3 assume !(0 == ~T2_E~0); 8357#L781-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 8737#L786-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 8564#L791-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 8277#L796-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 8278#L801-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 8896#L806-3 assume 0 == ~E_M~0;~E_M~0 := 1; 8724#L811-3 assume 0 == ~E_1~0;~E_1~0 := 1; 8424#L816-3 assume !(0 == ~E_2~0); 8425#L821-3 assume 0 == ~E_3~0;~E_3~0 := 1; 8934#L826-3 assume 0 == ~E_4~0;~E_4~0 := 1; 8805#L831-3 assume 0 == ~E_5~0;~E_5~0 := 1; 8638#L836-3 assume 0 == ~E_6~0;~E_6~0 := 1; 8209#L841-3 assume 0 == ~E_7~0;~E_7~0 := 1; 8210#L846-3 havoc activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 8191#L378-27 assume 1 == ~m_pc~0; 8192#L379-9 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 8368#L389-9 is_master_triggered_#res := is_master_triggered_~__retres1~0; 8747#L390-9 activate_threads_#t~ret11 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 8809#L957-27 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 8940#L957-29 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 8413#L397-27 assume !(1 == ~t1_pc~0); 8414#L397-29 is_transmit1_triggered_~__retres1~1 := 0; 8416#L408-9 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 8874#L409-9 activate_threads_#t~ret12 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 8705#L965-27 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 8697#L965-29 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 8569#L416-27 assume 1 == ~t2_pc~0; 8521#L417-9 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 8522#L427-9 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 8907#L428-9 activate_threads_#t~ret13 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 8369#L973-27 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 8370#L973-29 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 8376#L435-27 assume 1 == ~t3_pc~0; 8660#L436-9 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 8311#L446-9 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 8312#L447-9 activate_threads_#t~ret14 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 8905#L981-27 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 8900#L981-29 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 8786#L454-27 assume 1 == ~t4_pc~0; 8740#L455-9 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 8496#L465-9 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 8234#L466-9 activate_threads_#t~ret15 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 8235#L989-27 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 8524#L989-29 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 8528#L473-27 assume 1 == ~t5_pc~0; 8866#L474-9 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 8625#L484-9 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 8459#L485-9 activate_threads_#t~ret16 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 8460#L997-27 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 8950#L997-29 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 8951#L492-27 assume 1 == ~t6_pc~0; 8919#L493-9 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6 := 1; 8701#L503-9 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 8603#L504-9 activate_threads_#t~ret17 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 8604#L1005-27 assume !(0 != activate_threads_~tmp___5~0); 8746#L1005-29 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 8342#L511-27 assume !(1 == ~t7_pc~0); 8305#L511-29 is_transmit7_triggered_~__retres1~7 := 0; 8304#L522-9 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 8793#L523-9 activate_threads_#t~ret18 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 8465#L1013-27 assume 0 != activate_threads_~tmp___6~0;~t7_st~0 := 0; 8444#L1013-29 assume 1 == ~M_E~0;~M_E~0 := 2; 8445#L859-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 8348#L864-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 8349#L869-3 assume !(1 == ~T3_E~0); 8735#L874-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 8576#L879-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 8287#L884-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 8288#L889-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 8898#L894-3 assume 1 == ~E_M~0;~E_M~0 := 2; 8648#L899-3 assume 1 == ~E_1~0;~E_1~0 := 2; 8439#L904-3 assume 1 == ~E_2~0;~E_2~0 := 2; 8440#L909-3 assume !(1 == ~E_3~0); 8937#L914-3 assume 1 == ~E_4~0;~E_4~0 := 2; 8803#L919-3 assume 1 == ~E_5~0;~E_5~0 := 2; 8636#L924-3 assume 1 == ~E_6~0;~E_6~0 := 2; 8197#L929-3 assume 1 == ~E_7~0;~E_7~0 := 2; 8198#L934-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~8;havoc exists_runnable_thread_~__retres1~8; 8893#L586-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8 := 1; 8284#L628-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; 8831#L629-1 start_simulation_#t~ret20 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret20;havoc start_simulation_#t~ret20; 8832#L1199 assume !(0 == start_simulation_~tmp~3); 8749#L1199-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret19, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~8;havoc exists_runnable_thread_~__retres1~8; 8894#L586-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8 := 1; 8262#L628-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; 8835#L629-2 stop_simulation_#t~ret19 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret19;havoc stop_simulation_#t~ret19; 8836#L1154 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 8807#L1161 stop_simulation_#res := stop_simulation_~__retres2~0; 8795#L1162 start_simulation_#t~ret21 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret21;havoc start_simulation_#t~ret21; 8461#L1212 assume !(0 != start_simulation_~tmp___0~1); 8229#L1180-1 [2018-11-23 16:06:13,009 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 16:06:13,009 INFO L82 PathProgramCache]: Analyzing trace with hash 93432411, now seen corresponding path program 1 times [2018-11-23 16:06:13,009 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 16:06:13,009 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 16:06:13,010 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 16:06:13,010 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 16:06:13,010 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 16:06:13,014 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 16:06:13,034 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 16:06:13,034 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 16:06:13,034 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-23 16:06:13,034 INFO L799 eck$LassoCheckResult]: stem already infeasible [2018-11-23 16:06:13,034 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 16:06:13,035 INFO L82 PathProgramCache]: Analyzing trace with hash 427525562, now seen corresponding path program 1 times [2018-11-23 16:06:13,035 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 16:06:13,035 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 16:06:13,035 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 16:06:13,036 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 16:06:13,036 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 16:06:13,042 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 16:06:13,073 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 16:06:13,073 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 16:06:13,073 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-23 16:06:13,074 INFO L811 eck$LassoCheckResult]: loop already infeasible [2018-11-23 16:06:13,074 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-23 16:06:13,074 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-23 16:06:13,074 INFO L87 Difference]: Start difference. First operand 812 states and 1222 transitions. cyclomatic complexity: 411 Second operand 3 states. [2018-11-23 16:06:13,085 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 16:06:13,085 INFO L93 Difference]: Finished difference Result 812 states and 1221 transitions. [2018-11-23 16:06:13,086 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-23 16:06:13,086 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 812 states and 1221 transitions. [2018-11-23 16:06:13,089 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 713 [2018-11-23 16:06:13,092 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 812 states to 812 states and 1221 transitions. [2018-11-23 16:06:13,092 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 812 [2018-11-23 16:06:13,093 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 812 [2018-11-23 16:06:13,093 INFO L73 IsDeterministic]: Start isDeterministic. Operand 812 states and 1221 transitions. [2018-11-23 16:06:13,094 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-23 16:06:13,094 INFO L705 BuchiCegarLoop]: Abstraction has 812 states and 1221 transitions. [2018-11-23 16:06:13,095 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 812 states and 1221 transitions. [2018-11-23 16:06:13,103 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 812 to 812. [2018-11-23 16:06:13,103 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 812 states. [2018-11-23 16:06:13,105 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 812 states to 812 states and 1221 transitions. [2018-11-23 16:06:13,105 INFO L728 BuchiCegarLoop]: Abstraction has 812 states and 1221 transitions. [2018-11-23 16:06:13,105 INFO L608 BuchiCegarLoop]: Abstraction has 812 states and 1221 transitions. [2018-11-23 16:06:13,105 INFO L442 BuchiCegarLoop]: ======== Iteration 7============ [2018-11-23 16:06:13,105 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 812 states and 1221 transitions. [2018-11-23 16:06:13,108 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 713 [2018-11-23 16:06:13,108 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-23 16:06:13,108 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-23 16:06:13,109 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 16:06:13,110 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 16:06:13,110 INFO L794 eck$LassoCheckResult]: Stem: 10253#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; 10162#L-1 havoc main_#res;havoc main_~__retres1~9;havoc main_~__retres1~9;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 10163#L1143 havoc start_simulation_#t~ret20, start_simulation_#t~ret21, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 10134#L531 assume 1 == ~m_i~0;~m_st~0 := 0; 10135#L538-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 10404#L543-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 10316#L548-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 10136#L553-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 10137#L558-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 10468#L563-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 10312#L568-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 10120#L573-1 assume !(0 == ~M_E~0); 10121#L771-1 assume 0 == ~T1_E~0;~T1_E~0 := 1; 9981#L776-1 assume !(0 == ~T2_E~0); 9982#L781-1 assume !(0 == ~T3_E~0); 10367#L786-1 assume !(0 == ~T4_E~0); 10208#L791-1 assume !(0 == ~T5_E~0); 9920#L796-1 assume !(0 == ~T6_E~0); 9921#L801-1 assume !(0 == ~T7_E~0); 10530#L806-1 assume !(0 == ~E_M~0); 10280#L811-1 assume 0 == ~E_1~0;~E_1~0 := 1; 10072#L816-1 assume !(0 == ~E_2~0); 10073#L821-1 assume !(0 == ~E_3~0); 10564#L826-1 assume !(0 == ~E_4~0); 10435#L831-1 assume !(0 == ~E_5~0); 10268#L836-1 assume !(0 == ~E_6~0); 9830#L841-1 assume !(0 == ~E_7~0); 9831#L846-1 havoc activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 9904#L378 assume !(1 == ~m_pc~0); 9878#L378-2 is_master_triggered_~__retres1~0 := 0; 9879#L389 is_master_triggered_#res := is_master_triggered_~__retres1~0; 10411#L390 activate_threads_#t~ret11 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 10449#L957 assume !(0 != activate_threads_~tmp~1); 10579#L957-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 10105#L397 assume 1 == ~t1_pc~0; 10023#L398 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 10024#L408 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 10453#L409 activate_threads_#t~ret12 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 10283#L965 assume !(0 != activate_threads_~tmp___0~0); 10274#L965-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 10275#L416 assume !(1 == ~t2_pc~0); 10188#L416-2 is_transmit2_triggered_~__retres1~2 := 0; 10187#L427 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 10547#L428 activate_threads_#t~ret13 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 9850#L973 assume !(0 != activate_threads_~tmp___1~0); 9851#L973-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 9856#L435 assume 1 == ~t3_pc~0; 10296#L436 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 9945#L446 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 9946#L447 activate_threads_#t~ret14 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 10487#L981 assume !(0 != activate_threads_~tmp___2~0); 10477#L981-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 10478#L454 assume 1 == ~t4_pc~0; 10407#L455 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 10140#L465 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 9898#L466 activate_threads_#t~ret15 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 9899#L989 assume !(0 != activate_threads_~tmp___3~0); 10212#L989-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 10214#L473 assume !(1 == ~t5_pc~0); 10520#L473-2 is_transmit5_triggered_~__retres1~5 := 0; 10258#L484 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 10123#L485 activate_threads_#t~ret16 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 10124#L997 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 10600#L997-2 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 10601#L492 assume 1 == ~t6_pc~0; 10604#L493 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6 := 1; 10351#L503 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 10317#L504 activate_threads_#t~ret17 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 10318#L1005 assume !(0 != activate_threads_~tmp___5~0); 10522#L1005-2 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 9819#L511 assume !(1 == ~t7_pc~0); 9820#L511-2 is_transmit7_triggered_~__retres1~7 := 0; 9975#L522 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 10364#L523 activate_threads_#t~ret18 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 10251#L1013 assume !(0 != activate_threads_~tmp___6~0); 10244#L1013-2 assume !(1 == ~M_E~0); 10245#L859-1 assume !(1 == ~T1_E~0); 9994#L864-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 9995#L869-1 assume !(1 == ~T3_E~0); 10365#L874-1 assume !(1 == ~T4_E~0); 10202#L879-1 assume !(1 == ~T5_E~0); 9916#L884-1 assume !(1 == ~T6_E~0); 9917#L889-1 assume !(1 == ~T7_E~0); 10528#L894-1 assume !(1 == ~E_M~0); 10276#L899-1 assume !(1 == ~E_1~0); 10065#L904-1 assume 1 == ~E_2~0;~E_2~0 := 2; 10066#L909-1 assume !(1 == ~E_3~0); 10567#L914-1 assume !(1 == ~E_4~0); 10437#L919-1 assume !(1 == ~E_5~0); 10273#L924-1 assume !(1 == ~E_6~0); 9859#L929-1 assume !(1 == ~E_7~0); 9860#L1180-1 [2018-11-23 16:06:13,110 INFO L796 eck$LassoCheckResult]: Loop: 9860#L1180-1 assume !false; 10523#L1181 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret2, eval_#t~nondet3, eval_~tmp_ndt_1~0, eval_#t~nondet4, eval_~tmp_ndt_2~0, eval_#t~nondet5, eval_~tmp_ndt_3~0, eval_#t~nondet6, eval_~tmp_ndt_4~0, eval_#t~nondet7, eval_~tmp_ndt_5~0, eval_#t~nondet8, eval_~tmp_ndt_6~0, eval_#t~nondet9, eval_~tmp_ndt_7~0, eval_#t~nondet10, eval_~tmp_ndt_8~0, eval_~tmp~0;havoc eval_~tmp~0; 9985#L746 assume !false; 10241#L639 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~8;havoc exists_runnable_thread_~__retres1~8; 10242#L586 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8 := 1; 9911#L628 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; 10475#L629 eval_#t~ret2 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret2;havoc eval_#t~ret2; 9805#L643 assume !(0 != eval_~tmp~0); 9807#L761 start_simulation_~kernel_st~0 := 2; 10138#L531-1 start_simulation_~kernel_st~0 := 3; 10139#L771-2 assume 0 == ~M_E~0;~M_E~0 := 1; 10238#L771-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 9987#L776-3 assume !(0 == ~T2_E~0); 9988#L781-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 10368#L786-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 10195#L791-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 9908#L796-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 9909#L801-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 10527#L806-3 assume 0 == ~E_M~0;~E_M~0 := 1; 10355#L811-3 assume 0 == ~E_1~0;~E_1~0 := 1; 10055#L816-3 assume !(0 == ~E_2~0); 10056#L821-3 assume 0 == ~E_3~0;~E_3~0 := 1; 10565#L826-3 assume 0 == ~E_4~0;~E_4~0 := 1; 10436#L831-3 assume 0 == ~E_5~0;~E_5~0 := 1; 10269#L836-3 assume 0 == ~E_6~0;~E_6~0 := 1; 9840#L841-3 assume 0 == ~E_7~0;~E_7~0 := 1; 9841#L846-3 havoc activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 9822#L378-27 assume !(1 == ~m_pc~0); 9824#L378-29 is_master_triggered_~__retres1~0 := 0; 9999#L389-9 is_master_triggered_#res := is_master_triggered_~__retres1~0; 10378#L390-9 activate_threads_#t~ret11 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 10440#L957-27 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 10571#L957-29 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 10044#L397-27 assume !(1 == ~t1_pc~0); 10045#L397-29 is_transmit1_triggered_~__retres1~1 := 0; 10047#L408-9 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 10505#L409-9 activate_threads_#t~ret12 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 10336#L965-27 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 10328#L965-29 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 10200#L416-27 assume 1 == ~t2_pc~0; 10152#L417-9 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 10153#L427-9 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 10538#L428-9 activate_threads_#t~ret13 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 10000#L973-27 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 10001#L973-29 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 10007#L435-27 assume 1 == ~t3_pc~0; 10291#L436-9 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 9942#L446-9 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 9943#L447-9 activate_threads_#t~ret14 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 10536#L981-27 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 10531#L981-29 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 10417#L454-27 assume 1 == ~t4_pc~0; 10371#L455-9 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 10127#L465-9 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 9865#L466-9 activate_threads_#t~ret15 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 9866#L989-27 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 10155#L989-29 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 10159#L473-27 assume 1 == ~t5_pc~0; 10497#L474-9 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 10256#L484-9 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 10090#L485-9 activate_threads_#t~ret16 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 10091#L997-27 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 10581#L997-29 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 10582#L492-27 assume 1 == ~t6_pc~0; 10550#L493-9 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6 := 1; 10332#L503-9 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 10234#L504-9 activate_threads_#t~ret17 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 10235#L1005-27 assume !(0 != activate_threads_~tmp___5~0); 10377#L1005-29 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 9973#L511-27 assume !(1 == ~t7_pc~0); 9936#L511-29 is_transmit7_triggered_~__retres1~7 := 0; 9935#L522-9 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 10424#L523-9 activate_threads_#t~ret18 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 10096#L1013-27 assume 0 != activate_threads_~tmp___6~0;~t7_st~0 := 0; 10075#L1013-29 assume 1 == ~M_E~0;~M_E~0 := 2; 10076#L859-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 9979#L864-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 9980#L869-3 assume !(1 == ~T3_E~0); 10366#L874-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 10207#L879-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 9918#L884-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 9919#L889-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 10529#L894-3 assume 1 == ~E_M~0;~E_M~0 := 2; 10279#L899-3 assume 1 == ~E_1~0;~E_1~0 := 2; 10070#L904-3 assume 1 == ~E_2~0;~E_2~0 := 2; 10071#L909-3 assume !(1 == ~E_3~0); 10568#L914-3 assume 1 == ~E_4~0;~E_4~0 := 2; 10434#L919-3 assume 1 == ~E_5~0;~E_5~0 := 2; 10267#L924-3 assume 1 == ~E_6~0;~E_6~0 := 2; 9828#L929-3 assume 1 == ~E_7~0;~E_7~0 := 2; 9829#L934-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~8;havoc exists_runnable_thread_~__retres1~8; 10524#L586-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8 := 1; 9915#L628-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; 10462#L629-1 start_simulation_#t~ret20 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret20;havoc start_simulation_#t~ret20; 10463#L1199 assume !(0 == start_simulation_~tmp~3); 10380#L1199-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret19, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~8;havoc exists_runnable_thread_~__retres1~8; 10525#L586-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8 := 1; 9893#L628-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; 10466#L629-2 stop_simulation_#t~ret19 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret19;havoc stop_simulation_#t~ret19; 10467#L1154 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 10438#L1161 stop_simulation_#res := stop_simulation_~__retres2~0; 10426#L1162 start_simulation_#t~ret21 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret21;havoc start_simulation_#t~ret21; 10092#L1212 assume !(0 != start_simulation_~tmp___0~1); 9860#L1180-1 [2018-11-23 16:06:13,110 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 16:06:13,110 INFO L82 PathProgramCache]: Analyzing trace with hash -1473325539, now seen corresponding path program 1 times [2018-11-23 16:06:13,110 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 16:06:13,111 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 16:06:13,111 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 16:06:13,111 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 16:06:13,111 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 16:06:13,115 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 16:06:13,140 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 16:06:13,140 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 16:06:13,140 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-23 16:06:13,140 INFO L799 eck$LassoCheckResult]: stem already infeasible [2018-11-23 16:06:13,140 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 16:06:13,141 INFO L82 PathProgramCache]: Analyzing trace with hash 506643417, now seen corresponding path program 1 times [2018-11-23 16:06:13,141 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 16:06:13,141 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 16:06:13,141 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 16:06:13,141 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 16:06:13,142 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 16:06:13,148 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 16:06:13,176 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 16:06:13,177 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 16:06:13,177 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-23 16:06:13,177 INFO L811 eck$LassoCheckResult]: loop already infeasible [2018-11-23 16:06:13,177 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-23 16:06:13,177 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-23 16:06:13,178 INFO L87 Difference]: Start difference. First operand 812 states and 1221 transitions. cyclomatic complexity: 410 Second operand 3 states. [2018-11-23 16:06:13,188 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 16:06:13,189 INFO L93 Difference]: Finished difference Result 812 states and 1220 transitions. [2018-11-23 16:06:13,189 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-23 16:06:13,190 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 812 states and 1220 transitions. [2018-11-23 16:06:13,193 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 713 [2018-11-23 16:06:13,196 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 812 states to 812 states and 1220 transitions. [2018-11-23 16:06:13,196 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 812 [2018-11-23 16:06:13,197 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 812 [2018-11-23 16:06:13,197 INFO L73 IsDeterministic]: Start isDeterministic. Operand 812 states and 1220 transitions. [2018-11-23 16:06:13,198 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-23 16:06:13,198 INFO L705 BuchiCegarLoop]: Abstraction has 812 states and 1220 transitions. [2018-11-23 16:06:13,199 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 812 states and 1220 transitions. [2018-11-23 16:06:13,219 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 812 to 812. [2018-11-23 16:06:13,219 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 812 states. [2018-11-23 16:06:13,221 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 812 states to 812 states and 1220 transitions. [2018-11-23 16:06:13,221 INFO L728 BuchiCegarLoop]: Abstraction has 812 states and 1220 transitions. [2018-11-23 16:06:13,221 INFO L608 BuchiCegarLoop]: Abstraction has 812 states and 1220 transitions. [2018-11-23 16:06:13,221 INFO L442 BuchiCegarLoop]: ======== Iteration 8============ [2018-11-23 16:06:13,221 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 812 states and 1220 transitions. [2018-11-23 16:06:13,224 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 713 [2018-11-23 16:06:13,224 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-23 16:06:13,224 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-23 16:06:13,225 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 16:06:13,225 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 16:06:13,226 INFO L794 eck$LassoCheckResult]: Stem: 11884#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; 11793#L-1 havoc main_#res;havoc main_~__retres1~9;havoc main_~__retres1~9;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 11794#L1143 havoc start_simulation_#t~ret20, start_simulation_#t~ret21, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 11765#L531 assume 1 == ~m_i~0;~m_st~0 := 0; 11766#L538-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 12035#L543-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 11947#L548-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 11767#L553-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 11768#L558-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 12099#L563-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 11943#L568-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 11751#L573-1 assume !(0 == ~M_E~0); 11752#L771-1 assume 0 == ~T1_E~0;~T1_E~0 := 1; 11612#L776-1 assume !(0 == ~T2_E~0); 11613#L781-1 assume !(0 == ~T3_E~0); 11998#L786-1 assume !(0 == ~T4_E~0); 11839#L791-1 assume !(0 == ~T5_E~0); 11551#L796-1 assume !(0 == ~T6_E~0); 11552#L801-1 assume !(0 == ~T7_E~0); 12161#L806-1 assume !(0 == ~E_M~0); 11911#L811-1 assume 0 == ~E_1~0;~E_1~0 := 1; 11703#L816-1 assume !(0 == ~E_2~0); 11704#L821-1 assume !(0 == ~E_3~0); 12195#L826-1 assume !(0 == ~E_4~0); 12066#L831-1 assume !(0 == ~E_5~0); 11899#L836-1 assume !(0 == ~E_6~0); 11461#L841-1 assume !(0 == ~E_7~0); 11462#L846-1 havoc activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 11535#L378 assume !(1 == ~m_pc~0); 11509#L378-2 is_master_triggered_~__retres1~0 := 0; 11510#L389 is_master_triggered_#res := is_master_triggered_~__retres1~0; 12042#L390 activate_threads_#t~ret11 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 12080#L957 assume !(0 != activate_threads_~tmp~1); 12210#L957-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 11736#L397 assume 1 == ~t1_pc~0; 11654#L398 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 11655#L408 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 12084#L409 activate_threads_#t~ret12 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 11914#L965 assume !(0 != activate_threads_~tmp___0~0); 11905#L965-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 11906#L416 assume !(1 == ~t2_pc~0); 11819#L416-2 is_transmit2_triggered_~__retres1~2 := 0; 11818#L427 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 12178#L428 activate_threads_#t~ret13 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 11481#L973 assume !(0 != activate_threads_~tmp___1~0); 11482#L973-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 11487#L435 assume 1 == ~t3_pc~0; 11927#L436 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 11576#L446 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 11577#L447 activate_threads_#t~ret14 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 12118#L981 assume !(0 != activate_threads_~tmp___2~0); 12108#L981-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 12109#L454 assume 1 == ~t4_pc~0; 12038#L455 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 11771#L465 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 11529#L466 activate_threads_#t~ret15 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 11530#L989 assume !(0 != activate_threads_~tmp___3~0); 11843#L989-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 11845#L473 assume !(1 == ~t5_pc~0); 12151#L473-2 is_transmit5_triggered_~__retres1~5 := 0; 11889#L484 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 11754#L485 activate_threads_#t~ret16 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 11755#L997 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 12231#L997-2 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 12232#L492 assume 1 == ~t6_pc~0; 12235#L493 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6 := 1; 11982#L503 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 11948#L504 activate_threads_#t~ret17 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 11949#L1005 assume !(0 != activate_threads_~tmp___5~0); 12153#L1005-2 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 11450#L511 assume !(1 == ~t7_pc~0); 11451#L511-2 is_transmit7_triggered_~__retres1~7 := 0; 11606#L522 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 11995#L523 activate_threads_#t~ret18 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 11882#L1013 assume !(0 != activate_threads_~tmp___6~0); 11875#L1013-2 assume !(1 == ~M_E~0); 11876#L859-1 assume !(1 == ~T1_E~0); 11625#L864-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 11626#L869-1 assume !(1 == ~T3_E~0); 11996#L874-1 assume !(1 == ~T4_E~0); 11833#L879-1 assume !(1 == ~T5_E~0); 11547#L884-1 assume !(1 == ~T6_E~0); 11548#L889-1 assume !(1 == ~T7_E~0); 12159#L894-1 assume !(1 == ~E_M~0); 11907#L899-1 assume !(1 == ~E_1~0); 11696#L904-1 assume 1 == ~E_2~0;~E_2~0 := 2; 11697#L909-1 assume !(1 == ~E_3~0); 12198#L914-1 assume !(1 == ~E_4~0); 12068#L919-1 assume !(1 == ~E_5~0); 11904#L924-1 assume !(1 == ~E_6~0); 11490#L929-1 assume !(1 == ~E_7~0); 11491#L1180-1 [2018-11-23 16:06:13,226 INFO L796 eck$LassoCheckResult]: Loop: 11491#L1180-1 assume !false; 12154#L1181 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret2, eval_#t~nondet3, eval_~tmp_ndt_1~0, eval_#t~nondet4, eval_~tmp_ndt_2~0, eval_#t~nondet5, eval_~tmp_ndt_3~0, eval_#t~nondet6, eval_~tmp_ndt_4~0, eval_#t~nondet7, eval_~tmp_ndt_5~0, eval_#t~nondet8, eval_~tmp_ndt_6~0, eval_#t~nondet9, eval_~tmp_ndt_7~0, eval_#t~nondet10, eval_~tmp_ndt_8~0, eval_~tmp~0;havoc eval_~tmp~0; 11616#L746 assume !false; 11872#L639 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~8;havoc exists_runnable_thread_~__retres1~8; 11873#L586 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8 := 1; 11542#L628 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; 12106#L629 eval_#t~ret2 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret2;havoc eval_#t~ret2; 11436#L643 assume !(0 != eval_~tmp~0); 11438#L761 start_simulation_~kernel_st~0 := 2; 11769#L531-1 start_simulation_~kernel_st~0 := 3; 11770#L771-2 assume 0 == ~M_E~0;~M_E~0 := 1; 11869#L771-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 11618#L776-3 assume !(0 == ~T2_E~0); 11619#L781-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 11999#L786-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 11826#L791-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 11539#L796-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 11540#L801-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 12158#L806-3 assume 0 == ~E_M~0;~E_M~0 := 1; 11986#L811-3 assume 0 == ~E_1~0;~E_1~0 := 1; 11686#L816-3 assume !(0 == ~E_2~0); 11687#L821-3 assume 0 == ~E_3~0;~E_3~0 := 1; 12196#L826-3 assume 0 == ~E_4~0;~E_4~0 := 1; 12067#L831-3 assume 0 == ~E_5~0;~E_5~0 := 1; 11900#L836-3 assume 0 == ~E_6~0;~E_6~0 := 1; 11471#L841-3 assume 0 == ~E_7~0;~E_7~0 := 1; 11472#L846-3 havoc activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 11453#L378-27 assume 1 == ~m_pc~0; 11454#L379-9 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 11630#L389-9 is_master_triggered_#res := is_master_triggered_~__retres1~0; 12009#L390-9 activate_threads_#t~ret11 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 12071#L957-27 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 12202#L957-29 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 11675#L397-27 assume !(1 == ~t1_pc~0); 11676#L397-29 is_transmit1_triggered_~__retres1~1 := 0; 11678#L408-9 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 12136#L409-9 activate_threads_#t~ret12 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 11967#L965-27 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 11959#L965-29 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 11831#L416-27 assume 1 == ~t2_pc~0; 11783#L417-9 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 11784#L427-9 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 12169#L428-9 activate_threads_#t~ret13 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 11631#L973-27 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 11632#L973-29 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 11638#L435-27 assume 1 == ~t3_pc~0; 11922#L436-9 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 11573#L446-9 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 11574#L447-9 activate_threads_#t~ret14 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 12167#L981-27 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 12162#L981-29 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 12048#L454-27 assume 1 == ~t4_pc~0; 12002#L455-9 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 11758#L465-9 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 11496#L466-9 activate_threads_#t~ret15 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 11497#L989-27 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 11786#L989-29 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 11790#L473-27 assume 1 == ~t5_pc~0; 12128#L474-9 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 11887#L484-9 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 11721#L485-9 activate_threads_#t~ret16 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 11722#L997-27 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 12212#L997-29 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 12213#L492-27 assume 1 == ~t6_pc~0; 12181#L493-9 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6 := 1; 11963#L503-9 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 11865#L504-9 activate_threads_#t~ret17 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 11866#L1005-27 assume !(0 != activate_threads_~tmp___5~0); 12008#L1005-29 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 11604#L511-27 assume 1 == ~t7_pc~0; 11565#L512-9 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7 := 1; 11566#L522-9 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 12055#L523-9 activate_threads_#t~ret18 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 11727#L1013-27 assume 0 != activate_threads_~tmp___6~0;~t7_st~0 := 0; 11706#L1013-29 assume 1 == ~M_E~0;~M_E~0 := 2; 11707#L859-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 11610#L864-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 11611#L869-3 assume !(1 == ~T3_E~0); 11997#L874-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 11838#L879-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 11549#L884-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 11550#L889-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 12160#L894-3 assume 1 == ~E_M~0;~E_M~0 := 2; 11910#L899-3 assume 1 == ~E_1~0;~E_1~0 := 2; 11701#L904-3 assume 1 == ~E_2~0;~E_2~0 := 2; 11702#L909-3 assume !(1 == ~E_3~0); 12199#L914-3 assume 1 == ~E_4~0;~E_4~0 := 2; 12065#L919-3 assume 1 == ~E_5~0;~E_5~0 := 2; 11898#L924-3 assume 1 == ~E_6~0;~E_6~0 := 2; 11459#L929-3 assume 1 == ~E_7~0;~E_7~0 := 2; 11460#L934-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~8;havoc exists_runnable_thread_~__retres1~8; 12155#L586-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8 := 1; 11546#L628-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; 12093#L629-1 start_simulation_#t~ret20 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret20;havoc start_simulation_#t~ret20; 12094#L1199 assume !(0 == start_simulation_~tmp~3); 12011#L1199-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret19, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~8;havoc exists_runnable_thread_~__retres1~8; 12156#L586-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8 := 1; 11524#L628-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; 12097#L629-2 stop_simulation_#t~ret19 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret19;havoc stop_simulation_#t~ret19; 12098#L1154 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 12069#L1161 stop_simulation_#res := stop_simulation_~__retres2~0; 12057#L1162 start_simulation_#t~ret21 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret21;havoc start_simulation_#t~ret21; 11723#L1212 assume !(0 != start_simulation_~tmp___0~1); 11491#L1180-1 [2018-11-23 16:06:13,226 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 16:06:13,226 INFO L82 PathProgramCache]: Analyzing trace with hash -415487461, now seen corresponding path program 1 times [2018-11-23 16:06:13,226 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 16:06:13,226 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 16:06:13,227 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 16:06:13,227 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 16:06:13,227 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 16:06:13,231 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 16:06:13,270 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 16:06:13,271 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 16:06:13,271 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2018-11-23 16:06:13,271 INFO L799 eck$LassoCheckResult]: stem already infeasible [2018-11-23 16:06:13,271 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 16:06:13,271 INFO L82 PathProgramCache]: Analyzing trace with hash 2056175835, now seen corresponding path program 4 times [2018-11-23 16:06:13,271 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 16:06:13,271 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 16:06:13,272 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 16:06:13,272 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 16:06:13,272 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 16:06:13,279 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 16:06:13,313 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 16:06:13,313 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 16:06:13,313 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-23 16:06:13,314 INFO L811 eck$LassoCheckResult]: loop already infeasible [2018-11-23 16:06:13,314 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-23 16:06:13,314 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-23 16:06:13,314 INFO L87 Difference]: Start difference. First operand 812 states and 1220 transitions. cyclomatic complexity: 409 Second operand 3 states. [2018-11-23 16:06:13,349 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 16:06:13,349 INFO L93 Difference]: Finished difference Result 812 states and 1215 transitions. [2018-11-23 16:06:13,350 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-23 16:06:13,350 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 812 states and 1215 transitions. [2018-11-23 16:06:13,354 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 713 [2018-11-23 16:06:13,358 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 812 states to 812 states and 1215 transitions. [2018-11-23 16:06:13,358 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 812 [2018-11-23 16:06:13,359 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 812 [2018-11-23 16:06:13,359 INFO L73 IsDeterministic]: Start isDeterministic. Operand 812 states and 1215 transitions. [2018-11-23 16:06:13,360 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-23 16:06:13,360 INFO L705 BuchiCegarLoop]: Abstraction has 812 states and 1215 transitions. [2018-11-23 16:06:13,361 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 812 states and 1215 transitions. [2018-11-23 16:06:13,368 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 812 to 812. [2018-11-23 16:06:13,368 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 812 states. [2018-11-23 16:06:13,370 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 812 states to 812 states and 1215 transitions. [2018-11-23 16:06:13,370 INFO L728 BuchiCegarLoop]: Abstraction has 812 states and 1215 transitions. [2018-11-23 16:06:13,370 INFO L608 BuchiCegarLoop]: Abstraction has 812 states and 1215 transitions. [2018-11-23 16:06:13,370 INFO L442 BuchiCegarLoop]: ======== Iteration 9============ [2018-11-23 16:06:13,370 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 812 states and 1215 transitions. [2018-11-23 16:06:13,373 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 713 [2018-11-23 16:06:13,373 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-23 16:06:13,373 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-23 16:06:13,374 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 16:06:13,374 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 16:06:13,374 INFO L794 eck$LassoCheckResult]: Stem: 13515#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; 13424#L-1 havoc main_#res;havoc main_~__retres1~9;havoc main_~__retres1~9;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 13425#L1143 havoc start_simulation_#t~ret20, start_simulation_#t~ret21, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 13396#L531 assume 1 == ~m_i~0;~m_st~0 := 0; 13397#L538-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 13667#L543-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 13578#L548-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 13398#L553-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 13399#L558-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 13730#L563-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 13574#L568-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 13382#L573-1 assume !(0 == ~M_E~0); 13383#L771-1 assume !(0 == ~T1_E~0); 13244#L776-1 assume !(0 == ~T2_E~0); 13245#L781-1 assume !(0 == ~T3_E~0); 13629#L786-1 assume !(0 == ~T4_E~0); 13470#L791-1 assume !(0 == ~T5_E~0); 13182#L796-1 assume !(0 == ~T6_E~0); 13183#L801-1 assume !(0 == ~T7_E~0); 13792#L806-1 assume !(0 == ~E_M~0); 13542#L811-1 assume 0 == ~E_1~0;~E_1~0 := 1; 13334#L816-1 assume !(0 == ~E_2~0); 13335#L821-1 assume !(0 == ~E_3~0); 13826#L826-1 assume !(0 == ~E_4~0); 13697#L831-1 assume !(0 == ~E_5~0); 13530#L836-1 assume !(0 == ~E_6~0); 13097#L841-1 assume !(0 == ~E_7~0); 13098#L846-1 havoc activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 13166#L378 assume !(1 == ~m_pc~0); 13140#L378-2 is_master_triggered_~__retres1~0 := 0; 13141#L389 is_master_triggered_#res := is_master_triggered_~__retres1~0; 13675#L390 activate_threads_#t~ret11 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 13711#L957 assume !(0 != activate_threads_~tmp~1); 13841#L957-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 13367#L397 assume 1 == ~t1_pc~0; 13285#L398 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 13286#L408 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 13715#L409 activate_threads_#t~ret12 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 13545#L965 assume !(0 != activate_threads_~tmp___0~0); 13536#L965-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 13537#L416 assume !(1 == ~t2_pc~0); 13450#L416-2 is_transmit2_triggered_~__retres1~2 := 0; 13449#L427 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 13809#L428 activate_threads_#t~ret13 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 13112#L973 assume !(0 != activate_threads_~tmp___1~0); 13113#L973-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 13118#L435 assume 1 == ~t3_pc~0; 13558#L436 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 13207#L446 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 13208#L447 activate_threads_#t~ret14 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 13749#L981 assume !(0 != activate_threads_~tmp___2~0); 13739#L981-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 13740#L454 assume 1 == ~t4_pc~0; 13669#L455 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 13402#L465 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 13160#L466 activate_threads_#t~ret15 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 13161#L989 assume !(0 != activate_threads_~tmp___3~0); 13474#L989-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 13476#L473 assume !(1 == ~t5_pc~0); 13782#L473-2 is_transmit5_triggered_~__retres1~5 := 0; 13520#L484 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 13385#L485 activate_threads_#t~ret16 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 13386#L997 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 13862#L997-2 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 13863#L492 assume 1 == ~t6_pc~0; 13866#L493 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6 := 1; 13613#L503 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 13579#L504 activate_threads_#t~ret17 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 13580#L1005 assume !(0 != activate_threads_~tmp___5~0); 13784#L1005-2 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 13081#L511 assume !(1 == ~t7_pc~0); 13082#L511-2 is_transmit7_triggered_~__retres1~7 := 0; 13237#L522 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 13626#L523 activate_threads_#t~ret18 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 13513#L1013 assume !(0 != activate_threads_~tmp___6~0); 13506#L1013-2 assume !(1 == ~M_E~0); 13507#L859-1 assume !(1 == ~T1_E~0); 13256#L864-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 13257#L869-1 assume !(1 == ~T3_E~0); 13627#L874-1 assume !(1 == ~T4_E~0); 13464#L879-1 assume !(1 == ~T5_E~0); 13178#L884-1 assume !(1 == ~T6_E~0); 13179#L889-1 assume !(1 == ~T7_E~0); 13790#L894-1 assume !(1 == ~E_M~0); 13538#L899-1 assume !(1 == ~E_1~0); 13327#L904-1 assume 1 == ~E_2~0;~E_2~0 := 2; 13328#L909-1 assume !(1 == ~E_3~0); 13829#L914-1 assume !(1 == ~E_4~0); 13699#L919-1 assume !(1 == ~E_5~0); 13535#L924-1 assume !(1 == ~E_6~0); 13121#L929-1 assume !(1 == ~E_7~0); 13122#L1180-1 [2018-11-23 16:06:13,375 INFO L796 eck$LassoCheckResult]: Loop: 13122#L1180-1 assume !false; 13785#L1181 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret2, eval_#t~nondet3, eval_~tmp_ndt_1~0, eval_#t~nondet4, eval_~tmp_ndt_2~0, eval_#t~nondet5, eval_~tmp_ndt_3~0, eval_#t~nondet6, eval_~tmp_ndt_4~0, eval_#t~nondet7, eval_~tmp_ndt_5~0, eval_#t~nondet8, eval_~tmp_ndt_6~0, eval_#t~nondet9, eval_~tmp_ndt_7~0, eval_#t~nondet10, eval_~tmp_ndt_8~0, eval_~tmp~0;havoc eval_~tmp~0; 13247#L746 assume !false; 13503#L639 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~8;havoc exists_runnable_thread_~__retres1~8; 13504#L586 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8 := 1; 13173#L628 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; 13737#L629 eval_#t~ret2 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret2;havoc eval_#t~ret2; 13067#L643 assume !(0 != eval_~tmp~0); 13069#L761 start_simulation_~kernel_st~0 := 2; 13400#L531-1 start_simulation_~kernel_st~0 := 3; 13401#L771-2 assume 0 == ~M_E~0;~M_E~0 := 1; 13500#L771-4 assume !(0 == ~T1_E~0); 13249#L776-3 assume !(0 == ~T2_E~0); 13250#L781-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 13630#L786-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 13457#L791-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 13170#L796-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 13171#L801-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 13789#L806-3 assume 0 == ~E_M~0;~E_M~0 := 1; 13617#L811-3 assume 0 == ~E_1~0;~E_1~0 := 1; 13317#L816-3 assume !(0 == ~E_2~0); 13318#L821-3 assume 0 == ~E_3~0;~E_3~0 := 1; 13827#L826-3 assume 0 == ~E_4~0;~E_4~0 := 1; 13698#L831-3 assume 0 == ~E_5~0;~E_5~0 := 1; 13531#L836-3 assume 0 == ~E_6~0;~E_6~0 := 1; 13102#L841-3 assume 0 == ~E_7~0;~E_7~0 := 1; 13103#L846-3 havoc activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 13084#L378-27 assume 1 == ~m_pc~0; 13085#L379-9 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 13261#L389-9 is_master_triggered_#res := is_master_triggered_~__retres1~0; 13640#L390-9 activate_threads_#t~ret11 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 13702#L957-27 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 13833#L957-29 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 13306#L397-27 assume !(1 == ~t1_pc~0); 13307#L397-29 is_transmit1_triggered_~__retres1~1 := 0; 13309#L408-9 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 13767#L409-9 activate_threads_#t~ret12 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 13598#L965-27 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 13590#L965-29 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 13462#L416-27 assume 1 == ~t2_pc~0; 13414#L417-9 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 13415#L427-9 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 13800#L428-9 activate_threads_#t~ret13 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 13262#L973-27 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 13263#L973-29 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 13269#L435-27 assume 1 == ~t3_pc~0; 13553#L436-9 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 13204#L446-9 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 13205#L447-9 activate_threads_#t~ret14 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 13798#L981-27 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 13793#L981-29 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 13679#L454-27 assume 1 == ~t4_pc~0; 13633#L455-9 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 13389#L465-9 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 13127#L466-9 activate_threads_#t~ret15 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 13128#L989-27 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 13417#L989-29 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 13421#L473-27 assume !(1 == ~t5_pc~0); 13760#L473-29 is_transmit5_triggered_~__retres1~5 := 0; 13518#L484-9 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 13352#L485-9 activate_threads_#t~ret16 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 13353#L997-27 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 13843#L997-29 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 13844#L492-27 assume 1 == ~t6_pc~0; 13812#L493-9 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6 := 1; 13594#L503-9 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 13496#L504-9 activate_threads_#t~ret17 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 13497#L1005-27 assume !(0 != activate_threads_~tmp___5~0); 13639#L1005-29 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 13235#L511-27 assume 1 == ~t7_pc~0; 13196#L512-9 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7 := 1; 13197#L522-9 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 13686#L523-9 activate_threads_#t~ret18 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 13358#L1013-27 assume 0 != activate_threads_~tmp___6~0;~t7_st~0 := 0; 13337#L1013-29 assume 1 == ~M_E~0;~M_E~0 := 2; 13338#L859-3 assume !(1 == ~T1_E~0); 13241#L864-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 13242#L869-3 assume !(1 == ~T3_E~0); 13628#L874-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 13469#L879-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 13180#L884-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 13181#L889-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 13791#L894-3 assume 1 == ~E_M~0;~E_M~0 := 2; 13541#L899-3 assume 1 == ~E_1~0;~E_1~0 := 2; 13332#L904-3 assume 1 == ~E_2~0;~E_2~0 := 2; 13333#L909-3 assume !(1 == ~E_3~0); 13830#L914-3 assume 1 == ~E_4~0;~E_4~0 := 2; 13696#L919-3 assume 1 == ~E_5~0;~E_5~0 := 2; 13529#L924-3 assume 1 == ~E_6~0;~E_6~0 := 2; 13090#L929-3 assume 1 == ~E_7~0;~E_7~0 := 2; 13091#L934-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~8;havoc exists_runnable_thread_~__retres1~8; 13786#L586-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8 := 1; 13177#L628-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; 13724#L629-1 start_simulation_#t~ret20 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret20;havoc start_simulation_#t~ret20; 13725#L1199 assume !(0 == start_simulation_~tmp~3); 13642#L1199-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret19, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~8;havoc exists_runnable_thread_~__retres1~8; 13787#L586-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8 := 1; 13155#L628-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; 13728#L629-2 stop_simulation_#t~ret19 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret19;havoc stop_simulation_#t~ret19; 13729#L1154 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 13700#L1161 stop_simulation_#res := stop_simulation_~__retres2~0; 13688#L1162 start_simulation_#t~ret21 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret21;havoc start_simulation_#t~ret21; 13354#L1212 assume !(0 != start_simulation_~tmp___0~1); 13122#L1180-1 [2018-11-23 16:06:13,375 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 16:06:13,375 INFO L82 PathProgramCache]: Analyzing trace with hash -175247715, now seen corresponding path program 1 times [2018-11-23 16:06:13,375 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 16:06:13,375 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 16:06:13,376 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 16:06:13,376 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-23 16:06:13,376 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 16:06:13,380 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 16:06:13,396 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 16:06:13,396 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 16:06:13,396 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2018-11-23 16:06:13,396 INFO L799 eck$LassoCheckResult]: stem already infeasible [2018-11-23 16:06:13,396 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 16:06:13,397 INFO L82 PathProgramCache]: Analyzing trace with hash 210197686, now seen corresponding path program 1 times [2018-11-23 16:06:13,397 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 16:06:13,397 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 16:06:13,397 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 16:06:13,397 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 16:06:13,398 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 16:06:13,403 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 16:06:13,427 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 16:06:13,427 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 16:06:13,427 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-23 16:06:13,427 INFO L811 eck$LassoCheckResult]: loop already infeasible [2018-11-23 16:06:13,427 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-23 16:06:13,428 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-23 16:06:13,428 INFO L87 Difference]: Start difference. First operand 812 states and 1215 transitions. cyclomatic complexity: 404 Second operand 3 states. [2018-11-23 16:06:13,502 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 16:06:13,502 INFO L93 Difference]: Finished difference Result 812 states and 1200 transitions. [2018-11-23 16:06:13,502 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-23 16:06:13,503 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 812 states and 1200 transitions. [2018-11-23 16:06:13,506 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 713 [2018-11-23 16:06:13,509 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 812 states to 812 states and 1200 transitions. [2018-11-23 16:06:13,509 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 812 [2018-11-23 16:06:13,509 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 812 [2018-11-23 16:06:13,510 INFO L73 IsDeterministic]: Start isDeterministic. Operand 812 states and 1200 transitions. [2018-11-23 16:06:13,511 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-23 16:06:13,511 INFO L705 BuchiCegarLoop]: Abstraction has 812 states and 1200 transitions. [2018-11-23 16:06:13,512 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 812 states and 1200 transitions. [2018-11-23 16:06:13,519 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 812 to 812. [2018-11-23 16:06:13,519 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 812 states. [2018-11-23 16:06:13,521 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 812 states to 812 states and 1200 transitions. [2018-11-23 16:06:13,521 INFO L728 BuchiCegarLoop]: Abstraction has 812 states and 1200 transitions. [2018-11-23 16:06:13,521 INFO L608 BuchiCegarLoop]: Abstraction has 812 states and 1200 transitions. [2018-11-23 16:06:13,521 INFO L442 BuchiCegarLoop]: ======== Iteration 10============ [2018-11-23 16:06:13,521 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 812 states and 1200 transitions. [2018-11-23 16:06:13,524 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 713 [2018-11-23 16:06:13,524 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-23 16:06:13,524 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-23 16:06:13,525 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 16:06:13,525 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 16:06:13,525 INFO L794 eck$LassoCheckResult]: Stem: 15146#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; 15055#L-1 havoc main_#res;havoc main_~__retres1~9;havoc main_~__retres1~9;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 15056#L1143 havoc start_simulation_#t~ret20, start_simulation_#t~ret21, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 15027#L531 assume 1 == ~m_i~0;~m_st~0 := 0; 15028#L538-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 15298#L543-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 15209#L548-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 15029#L553-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 15030#L558-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 15361#L563-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 15205#L568-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 15013#L573-1 assume !(0 == ~M_E~0); 15014#L771-1 assume !(0 == ~T1_E~0); 14875#L776-1 assume !(0 == ~T2_E~0); 14876#L781-1 assume !(0 == ~T3_E~0); 15260#L786-1 assume !(0 == ~T4_E~0); 15101#L791-1 assume !(0 == ~T5_E~0); 14813#L796-1 assume !(0 == ~T6_E~0); 14814#L801-1 assume !(0 == ~T7_E~0); 15423#L806-1 assume !(0 == ~E_M~0); 15173#L811-1 assume !(0 == ~E_1~0); 14961#L816-1 assume !(0 == ~E_2~0); 14962#L821-1 assume !(0 == ~E_3~0); 15457#L826-1 assume !(0 == ~E_4~0); 15328#L831-1 assume !(0 == ~E_5~0); 15161#L836-1 assume !(0 == ~E_6~0); 14723#L841-1 assume !(0 == ~E_7~0); 14724#L846-1 havoc activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 14797#L378 assume !(1 == ~m_pc~0); 14771#L378-2 is_master_triggered_~__retres1~0 := 0; 14772#L389 is_master_triggered_#res := is_master_triggered_~__retres1~0; 15304#L390 activate_threads_#t~ret11 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 15342#L957 assume !(0 != activate_threads_~tmp~1); 15472#L957-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 14997#L397 assume !(1 == ~t1_pc~0); 14917#L397-2 is_transmit1_triggered_~__retres1~1 := 0; 15002#L408 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 15346#L409 activate_threads_#t~ret12 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 15176#L965 assume !(0 != activate_threads_~tmp___0~0); 15167#L965-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 15168#L416 assume !(1 == ~t2_pc~0); 15081#L416-2 is_transmit2_triggered_~__retres1~2 := 0; 15080#L427 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 15440#L428 activate_threads_#t~ret13 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 14743#L973 assume !(0 != activate_threads_~tmp___1~0); 14744#L973-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 14749#L435 assume 1 == ~t3_pc~0; 15189#L436 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 14841#L446 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 14842#L447 activate_threads_#t~ret14 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 15380#L981 assume !(0 != activate_threads_~tmp___2~0); 15370#L981-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 15371#L454 assume 1 == ~t4_pc~0; 15300#L455 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 15033#L465 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 14791#L466 activate_threads_#t~ret15 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 14792#L989 assume !(0 != activate_threads_~tmp___3~0); 15105#L989-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 15107#L473 assume !(1 == ~t5_pc~0); 15413#L473-2 is_transmit5_triggered_~__retres1~5 := 0; 15151#L484 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 15016#L485 activate_threads_#t~ret16 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 15017#L997 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 15493#L997-2 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 15494#L492 assume 1 == ~t6_pc~0; 15497#L493 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6 := 1; 15244#L503 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 15210#L504 activate_threads_#t~ret17 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 15211#L1005 assume !(0 != activate_threads_~tmp___5~0); 15415#L1005-2 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 14712#L511 assume !(1 == ~t7_pc~0); 14713#L511-2 is_transmit7_triggered_~__retres1~7 := 0; 14868#L522 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 15257#L523 activate_threads_#t~ret18 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 15144#L1013 assume !(0 != activate_threads_~tmp___6~0); 15137#L1013-2 assume !(1 == ~M_E~0); 15138#L859-1 assume !(1 == ~T1_E~0); 14887#L864-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 14888#L869-1 assume !(1 == ~T3_E~0); 15258#L874-1 assume !(1 == ~T4_E~0); 15095#L879-1 assume !(1 == ~T5_E~0); 14809#L884-1 assume !(1 == ~T6_E~0); 14810#L889-1 assume !(1 == ~T7_E~0); 15421#L894-1 assume !(1 == ~E_M~0); 15169#L899-1 assume !(1 == ~E_1~0); 14954#L904-1 assume 1 == ~E_2~0;~E_2~0 := 2; 14955#L909-1 assume !(1 == ~E_3~0); 15460#L914-1 assume !(1 == ~E_4~0); 15330#L919-1 assume !(1 == ~E_5~0); 15166#L924-1 assume !(1 == ~E_6~0); 14752#L929-1 assume !(1 == ~E_7~0); 14753#L1180-1 [2018-11-23 16:06:13,525 INFO L796 eck$LassoCheckResult]: Loop: 14753#L1180-1 assume !false; 15416#L1181 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret2, eval_#t~nondet3, eval_~tmp_ndt_1~0, eval_#t~nondet4, eval_~tmp_ndt_2~0, eval_#t~nondet5, eval_~tmp_ndt_3~0, eval_#t~nondet6, eval_~tmp_ndt_4~0, eval_#t~nondet7, eval_~tmp_ndt_5~0, eval_#t~nondet8, eval_~tmp_ndt_6~0, eval_#t~nondet9, eval_~tmp_ndt_7~0, eval_#t~nondet10, eval_~tmp_ndt_8~0, eval_~tmp~0;havoc eval_~tmp~0; 14878#L746 assume !false; 15135#L639 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~8;havoc exists_runnable_thread_~__retres1~8; 15136#L586 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8 := 1; 14804#L628 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; 15368#L629 eval_#t~ret2 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret2;havoc eval_#t~ret2; 14698#L643 assume !(0 != eval_~tmp~0); 14700#L761 start_simulation_~kernel_st~0 := 2; 15031#L531-1 start_simulation_~kernel_st~0 := 3; 15032#L771-2 assume 0 == ~M_E~0;~M_E~0 := 1; 15133#L771-4 assume !(0 == ~T1_E~0); 14880#L776-3 assume !(0 == ~T2_E~0); 14881#L781-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 15261#L786-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 15089#L791-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 14801#L796-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 14802#L801-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 15420#L806-3 assume 0 == ~E_M~0;~E_M~0 := 1; 15248#L811-3 assume !(0 == ~E_1~0); 14944#L816-3 assume !(0 == ~E_2~0); 14945#L821-3 assume 0 == ~E_3~0;~E_3~0 := 1; 15458#L826-3 assume 0 == ~E_4~0;~E_4~0 := 1; 15329#L831-3 assume 0 == ~E_5~0;~E_5~0 := 1; 15162#L836-3 assume 0 == ~E_6~0;~E_6~0 := 1; 14733#L841-3 assume 0 == ~E_7~0;~E_7~0 := 1; 14734#L846-3 havoc activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 14715#L378-27 assume 1 == ~m_pc~0; 14716#L379-9 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 14894#L389-9 is_master_triggered_#res := is_master_triggered_~__retres1~0; 15271#L390-9 activate_threads_#t~ret11 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 15333#L957-27 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 15464#L957-29 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 14933#L397-27 assume !(1 == ~t1_pc~0); 14934#L397-29 is_transmit1_triggered_~__retres1~1 := 0; 14936#L408-9 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 15398#L409-9 activate_threads_#t~ret12 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 15229#L965-27 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 15221#L965-29 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 15093#L416-27 assume 1 == ~t2_pc~0; 15045#L417-9 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 15046#L427-9 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 15431#L428-9 activate_threads_#t~ret13 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 14892#L973-27 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 14893#L973-29 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 14900#L435-27 assume 1 == ~t3_pc~0; 15184#L436-9 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 14835#L446-9 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 14836#L447-9 activate_threads_#t~ret14 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 15429#L981-27 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 15424#L981-29 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 15310#L454-27 assume !(1 == ~t4_pc~0); 15264#L454-29 is_transmit4_triggered_~__retres1~4 := 0; 15020#L465-9 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 14758#L466-9 activate_threads_#t~ret15 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 14759#L989-27 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 15048#L989-29 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 15052#L473-27 assume 1 == ~t5_pc~0; 15389#L474-9 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 15149#L484-9 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 14981#L485-9 activate_threads_#t~ret16 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 14982#L997-27 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 15474#L997-29 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 15475#L492-27 assume 1 == ~t6_pc~0; 15443#L493-9 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6 := 1; 15224#L503-9 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 15127#L504-9 activate_threads_#t~ret17 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 15128#L1005-27 assume !(0 != activate_threads_~tmp___5~0); 15270#L1005-29 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 14866#L511-27 assume 1 == ~t7_pc~0; 14825#L512-9 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7 := 1; 14826#L522-9 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 15317#L523-9 activate_threads_#t~ret18 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 14988#L1013-27 assume 0 != activate_threads_~tmp___6~0;~t7_st~0 := 0; 14964#L1013-29 assume 1 == ~M_E~0;~M_E~0 := 2; 14965#L859-3 assume !(1 == ~T1_E~0); 14872#L864-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 14873#L869-3 assume !(1 == ~T3_E~0); 15259#L874-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 15100#L879-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 14811#L884-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 14812#L889-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 15422#L894-3 assume 1 == ~E_M~0;~E_M~0 := 2; 15172#L899-3 assume !(1 == ~E_1~0); 14959#L904-3 assume 1 == ~E_2~0;~E_2~0 := 2; 14960#L909-3 assume !(1 == ~E_3~0); 15461#L914-3 assume 1 == ~E_4~0;~E_4~0 := 2; 15327#L919-3 assume 1 == ~E_5~0;~E_5~0 := 2; 15160#L924-3 assume 1 == ~E_6~0;~E_6~0 := 2; 14721#L929-3 assume 1 == ~E_7~0;~E_7~0 := 2; 14722#L934-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~8;havoc exists_runnable_thread_~__retres1~8; 15417#L586-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8 := 1; 14808#L628-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; 15355#L629-1 start_simulation_#t~ret20 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret20;havoc start_simulation_#t~ret20; 15356#L1199 assume !(0 == start_simulation_~tmp~3); 15273#L1199-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret19, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~8;havoc exists_runnable_thread_~__retres1~8; 15418#L586-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8 := 1; 14786#L628-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; 15359#L629-2 stop_simulation_#t~ret19 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret19;havoc stop_simulation_#t~ret19; 15360#L1154 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 15331#L1161 stop_simulation_#res := stop_simulation_~__retres2~0; 15319#L1162 start_simulation_#t~ret21 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret21;havoc start_simulation_#t~ret21; 14983#L1212 assume !(0 != start_simulation_~tmp___0~1); 14753#L1180-1 [2018-11-23 16:06:13,526 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 16:06:13,526 INFO L82 PathProgramCache]: Analyzing trace with hash -902331040, now seen corresponding path program 1 times [2018-11-23 16:06:13,526 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 16:06:13,526 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 16:06:13,526 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 16:06:13,527 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 16:06:13,527 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 16:06:13,531 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 16:06:13,548 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 16:06:13,548 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 16:06:13,548 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2018-11-23 16:06:13,549 INFO L799 eck$LassoCheckResult]: stem already infeasible [2018-11-23 16:06:13,549 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 16:06:13,549 INFO L82 PathProgramCache]: Analyzing trace with hash -1880145166, now seen corresponding path program 1 times [2018-11-23 16:06:13,549 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 16:06:13,549 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 16:06:13,550 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 16:06:13,550 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 16:06:13,550 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 16:06:13,555 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 16:06:13,572 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 16:06:13,572 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 16:06:13,572 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-23 16:06:13,572 INFO L811 eck$LassoCheckResult]: loop already infeasible [2018-11-23 16:06:13,572 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-23 16:06:13,572 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-23 16:06:13,573 INFO L87 Difference]: Start difference. First operand 812 states and 1200 transitions. cyclomatic complexity: 389 Second operand 3 states. [2018-11-23 16:06:13,673 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 16:06:13,673 INFO L93 Difference]: Finished difference Result 1458 states and 2138 transitions. [2018-11-23 16:06:13,673 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-23 16:06:13,673 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1458 states and 2138 transitions. [2018-11-23 16:06:13,678 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 1358 [2018-11-23 16:06:13,683 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1458 states to 1458 states and 2138 transitions. [2018-11-23 16:06:13,683 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1458 [2018-11-23 16:06:13,684 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1458 [2018-11-23 16:06:13,684 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1458 states and 2138 transitions. [2018-11-23 16:06:13,686 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-23 16:06:13,686 INFO L705 BuchiCegarLoop]: Abstraction has 1458 states and 2138 transitions. [2018-11-23 16:06:13,688 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1458 states and 2138 transitions. [2018-11-23 16:06:13,701 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1458 to 1456. [2018-11-23 16:06:13,701 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1456 states. [2018-11-23 16:06:13,704 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1456 states to 1456 states and 2136 transitions. [2018-11-23 16:06:13,704 INFO L728 BuchiCegarLoop]: Abstraction has 1456 states and 2136 transitions. [2018-11-23 16:06:13,704 INFO L608 BuchiCegarLoop]: Abstraction has 1456 states and 2136 transitions. [2018-11-23 16:06:13,704 INFO L442 BuchiCegarLoop]: ======== Iteration 11============ [2018-11-23 16:06:13,704 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1456 states and 2136 transitions. [2018-11-23 16:06:13,708 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 1356 [2018-11-23 16:06:13,708 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-23 16:06:13,708 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-23 16:06:13,709 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 16:06:13,710 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 16:06:13,710 INFO L794 eck$LassoCheckResult]: Stem: 17425#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; 17334#L-1 havoc main_#res;havoc main_~__retres1~9;havoc main_~__retres1~9;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 17335#L1143 havoc start_simulation_#t~ret20, start_simulation_#t~ret21, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 17306#L531 assume 1 == ~m_i~0;~m_st~0 := 0; 17307#L538-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 17591#L543-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 17502#L548-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 17308#L553-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 17309#L558-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 17659#L563-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 17493#L568-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 17292#L573-1 assume !(0 == ~M_E~0); 17293#L771-1 assume !(0 == ~T1_E~0); 17152#L776-1 assume !(0 == ~T2_E~0); 17153#L781-1 assume !(0 == ~T3_E~0); 17553#L786-1 assume !(0 == ~T4_E~0); 17380#L791-1 assume !(0 == ~T5_E~0); 17090#L796-1 assume !(0 == ~T6_E~0); 17091#L801-1 assume !(0 == ~T7_E~0); 17723#L806-1 assume !(0 == ~E_M~0); 17452#L811-1 assume !(0 == ~E_1~0); 17239#L816-1 assume !(0 == ~E_2~0); 17240#L821-1 assume !(0 == ~E_3~0); 17762#L826-1 assume !(0 == ~E_4~0); 17625#L831-1 assume !(0 == ~E_5~0); 17440#L836-1 assume !(0 == ~E_6~0); 17000#L841-1 assume !(0 == ~E_7~0); 17001#L846-1 havoc activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 17074#L378 assume !(1 == ~m_pc~0); 17048#L378-2 is_master_triggered_~__retres1~0 := 0; 17049#L389 is_master_triggered_#res := is_master_triggered_~__retres1~0; 17599#L390 activate_threads_#t~ret11 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 17640#L957 assume !(0 != activate_threads_~tmp~1); 17778#L957-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 17276#L397 assume !(1 == ~t1_pc~0); 17195#L397-2 is_transmit1_triggered_~__retres1~1 := 0; 17281#L408 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 17644#L409 activate_threads_#t~ret12 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 17455#L965 assume !(0 != activate_threads_~tmp___0~0); 17446#L965-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 17447#L416 assume !(1 == ~t2_pc~0); 17360#L416-2 is_transmit2_triggered_~__retres1~2 := 0; 17359#L427 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 17744#L428 activate_threads_#t~ret13 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 17020#L973 assume !(0 != activate_threads_~tmp___1~0); 17021#L973-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 17026#L435 assume !(1 == ~t3_pc~0); 17617#L435-2 is_transmit3_triggered_~__retres1~3 := 0; 17118#L446 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 17119#L447 activate_threads_#t~ret14 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 17679#L981 assume !(0 != activate_threads_~tmp___2~0); 17668#L981-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 17669#L454 assume 1 == ~t4_pc~0; 17593#L455 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 17312#L465 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 17068#L466 activate_threads_#t~ret15 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 17069#L989 assume !(0 != activate_threads_~tmp___3~0); 17384#L989-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 17386#L473 assume !(1 == ~t5_pc~0); 17713#L473-2 is_transmit5_triggered_~__retres1~5 := 0; 17430#L484 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 17295#L485 activate_threads_#t~ret16 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 17296#L997 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 17800#L997-2 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 17801#L492 assume 1 == ~t6_pc~0; 17804#L493 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6 := 1; 17537#L503 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 17503#L504 activate_threads_#t~ret17 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 17504#L1005 assume !(0 != activate_threads_~tmp___5~0); 17715#L1005-2 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 16989#L511 assume !(1 == ~t7_pc~0); 16990#L511-2 is_transmit7_triggered_~__retres1~7 := 0; 17145#L522 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 17550#L523 activate_threads_#t~ret18 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 17423#L1013 assume !(0 != activate_threads_~tmp___6~0); 17416#L1013-2 assume !(1 == ~M_E~0); 17417#L859-1 assume !(1 == ~T1_E~0); 17164#L864-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 17165#L869-1 assume !(1 == ~T3_E~0); 17551#L874-1 assume !(1 == ~T4_E~0); 17374#L879-1 assume !(1 == ~T5_E~0); 17086#L884-1 assume !(1 == ~T6_E~0); 17087#L889-1 assume !(1 == ~T7_E~0); 17721#L894-1 assume !(1 == ~E_M~0); 17448#L899-1 assume !(1 == ~E_1~0); 17232#L904-1 assume 1 == ~E_2~0;~E_2~0 := 2; 17233#L909-1 assume !(1 == ~E_3~0); 17765#L914-1 assume !(1 == ~E_4~0); 17628#L919-1 assume !(1 == ~E_5~0); 17445#L924-1 assume !(1 == ~E_6~0); 17029#L929-1 assume !(1 == ~E_7~0); 17030#L1180-1 [2018-11-23 16:06:13,710 INFO L796 eck$LassoCheckResult]: Loop: 17030#L1180-1 assume !false; 17716#L1181 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret2, eval_#t~nondet3, eval_~tmp_ndt_1~0, eval_#t~nondet4, eval_~tmp_ndt_2~0, eval_#t~nondet5, eval_~tmp_ndt_3~0, eval_#t~nondet6, eval_~tmp_ndt_4~0, eval_#t~nondet7, eval_~tmp_ndt_5~0, eval_#t~nondet8, eval_~tmp_ndt_6~0, eval_#t~nondet9, eval_~tmp_ndt_7~0, eval_#t~nondet10, eval_~tmp_ndt_8~0, eval_~tmp~0;havoc eval_~tmp~0; 17155#L746 assume !false; 17414#L639 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~8;havoc exists_runnable_thread_~__retres1~8; 17415#L586 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8 := 1; 17081#L628 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; 17666#L629 eval_#t~ret2 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret2;havoc eval_#t~ret2; 16975#L643 assume !(0 != eval_~tmp~0); 16977#L761 start_simulation_~kernel_st~0 := 2; 17310#L531-1 start_simulation_~kernel_st~0 := 3; 17311#L771-2 assume 0 == ~M_E~0;~M_E~0 := 1; 17412#L771-4 assume !(0 == ~T1_E~0); 17157#L776-3 assume !(0 == ~T2_E~0); 17158#L781-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 17777#L786-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 18375#L791-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 18374#L796-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 18373#L801-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 18372#L806-3 assume 0 == ~E_M~0;~E_M~0 := 1; 18371#L811-3 assume !(0 == ~E_1~0); 18370#L816-3 assume !(0 == ~E_2~0); 18369#L821-3 assume 0 == ~E_3~0;~E_3~0 := 1; 18368#L826-3 assume 0 == ~E_4~0;~E_4~0 := 1; 18367#L831-3 assume 0 == ~E_5~0;~E_5~0 := 1; 17441#L836-3 assume 0 == ~E_6~0;~E_6~0 := 1; 17010#L841-3 assume 0 == ~E_7~0;~E_7~0 := 1; 17011#L846-3 havoc activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 16992#L378-27 assume 1 == ~m_pc~0; 16993#L379-9 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 17171#L389-9 is_master_triggered_#res := is_master_triggered_~__retres1~0; 17564#L390-9 activate_threads_#t~ret11 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 17631#L957-27 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 17769#L957-29 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 17211#L397-27 assume !(1 == ~t1_pc~0); 17212#L397-29 is_transmit1_triggered_~__retres1~1 := 0; 17214#L408-9 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 17698#L409-9 activate_threads_#t~ret12 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 17522#L965-27 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 17514#L965-29 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 17372#L416-27 assume 1 == ~t2_pc~0; 17324#L417-9 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 17325#L427-9 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 17734#L428-9 activate_threads_#t~ret13 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 17169#L973-27 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 17170#L973-29 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 17178#L435-27 assume !(1 == ~t3_pc~0); 17491#L435-29 is_transmit3_triggered_~__retres1~3 := 0; 17112#L446-9 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 17113#L447-9 activate_threads_#t~ret14 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 17732#L981-27 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 17724#L981-29 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 17603#L454-27 assume 1 == ~t4_pc~0; 17556#L455-9 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 17299#L465-9 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 17035#L466-9 activate_threads_#t~ret15 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 17036#L989-27 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 17327#L989-29 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 17331#L473-27 assume 1 == ~t5_pc~0; 17688#L474-9 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 17428#L484-9 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 17259#L485-9 activate_threads_#t~ret16 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 17260#L997-27 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 17780#L997-29 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 17781#L492-27 assume 1 == ~t6_pc~0; 17747#L493-9 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6 := 1; 17517#L503-9 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 17406#L504-9 activate_threads_#t~ret17 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 17407#L1005-27 assume !(0 != activate_threads_~tmp___5~0); 17563#L1005-29 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 17143#L511-27 assume !(1 == ~t7_pc~0); 17104#L511-29 is_transmit7_triggered_~__retres1~7 := 0; 17103#L522-9 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 17612#L523-9 activate_threads_#t~ret18 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 17267#L1013-27 assume 0 != activate_threads_~tmp___6~0;~t7_st~0 := 0; 17242#L1013-29 assume 1 == ~M_E~0;~M_E~0 := 2; 17243#L859-3 assume !(1 == ~T1_E~0); 17149#L864-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 17150#L869-3 assume !(1 == ~T3_E~0); 17552#L874-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 17379#L879-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 17088#L884-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 17089#L889-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 17722#L894-3 assume 1 == ~E_M~0;~E_M~0 := 2; 17451#L899-3 assume !(1 == ~E_1~0); 17237#L904-3 assume 1 == ~E_2~0;~E_2~0 := 2; 17238#L909-3 assume !(1 == ~E_3~0); 17766#L914-3 assume 1 == ~E_4~0;~E_4~0 := 2; 17624#L919-3 assume 1 == ~E_5~0;~E_5~0 := 2; 17439#L924-3 assume 1 == ~E_6~0;~E_6~0 := 2; 16998#L929-3 assume 1 == ~E_7~0;~E_7~0 := 2; 16999#L934-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~8;havoc exists_runnable_thread_~__retres1~8; 17717#L586-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8 := 1; 17085#L628-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; 17653#L629-1 start_simulation_#t~ret20 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret20;havoc start_simulation_#t~ret20; 17654#L1199 assume !(0 == start_simulation_~tmp~3); 17743#L1199-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret19, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~8;havoc exists_runnable_thread_~__retres1~8; 18254#L586-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8 := 1; 18244#L628-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; 18242#L629-2 stop_simulation_#t~ret19 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret19;havoc stop_simulation_#t~ret19; 18240#L1154 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 18238#L1161 stop_simulation_#res := stop_simulation_~__retres2~0; 18236#L1162 start_simulation_#t~ret21 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret21;havoc start_simulation_#t~ret21; 18235#L1212 assume !(0 != start_simulation_~tmp___0~1); 17030#L1180-1 [2018-11-23 16:06:13,710 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 16:06:13,710 INFO L82 PathProgramCache]: Analyzing trace with hash -1775808735, now seen corresponding path program 1 times [2018-11-23 16:06:13,710 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 16:06:13,710 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 16:06:13,711 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 16:06:13,711 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 16:06:13,711 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 16:06:13,715 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 16:06:13,736 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 16:06:13,736 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 16:06:13,736 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2018-11-23 16:06:13,736 INFO L799 eck$LassoCheckResult]: stem already infeasible [2018-11-23 16:06:13,736 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 16:06:13,737 INFO L82 PathProgramCache]: Analyzing trace with hash 346092689, now seen corresponding path program 1 times [2018-11-23 16:06:13,737 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 16:06:13,737 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 16:06:13,737 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 16:06:13,737 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 16:06:13,738 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 16:06:13,742 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 16:06:13,761 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 16:06:13,761 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 16:06:13,761 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-23 16:06:13,761 INFO L811 eck$LassoCheckResult]: loop already infeasible [2018-11-23 16:06:13,761 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-23 16:06:13,761 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-23 16:06:13,762 INFO L87 Difference]: Start difference. First operand 1456 states and 2136 transitions. cyclomatic complexity: 682 Second operand 3 states. [2018-11-23 16:06:13,823 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 16:06:13,823 INFO L93 Difference]: Finished difference Result 2683 states and 3911 transitions. [2018-11-23 16:06:13,824 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-23 16:06:13,824 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2683 states and 3911 transitions. [2018-11-23 16:06:13,832 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 2578 [2018-11-23 16:06:13,842 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2683 states to 2683 states and 3911 transitions. [2018-11-23 16:06:13,842 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2683 [2018-11-23 16:06:13,844 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2683 [2018-11-23 16:06:13,844 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2683 states and 3911 transitions. [2018-11-23 16:06:13,847 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-23 16:06:13,847 INFO L705 BuchiCegarLoop]: Abstraction has 2683 states and 3911 transitions. [2018-11-23 16:06:13,849 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2683 states and 3911 transitions. [2018-11-23 16:06:13,874 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2683 to 2679. [2018-11-23 16:06:13,875 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2679 states. [2018-11-23 16:06:13,880 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2679 states to 2679 states and 3907 transitions. [2018-11-23 16:06:13,880 INFO L728 BuchiCegarLoop]: Abstraction has 2679 states and 3907 transitions. [2018-11-23 16:06:13,880 INFO L608 BuchiCegarLoop]: Abstraction has 2679 states and 3907 transitions. [2018-11-23 16:06:13,880 INFO L442 BuchiCegarLoop]: ======== Iteration 12============ [2018-11-23 16:06:13,880 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2679 states and 3907 transitions. [2018-11-23 16:06:13,886 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 2574 [2018-11-23 16:06:13,886 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-23 16:06:13,886 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-23 16:06:13,887 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 16:06:13,887 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 16:06:13,887 INFO L794 eck$LassoCheckResult]: Stem: 21573#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; 21482#L-1 havoc main_#res;havoc main_~__retres1~9;havoc main_~__retres1~9;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 21483#L1143 havoc start_simulation_#t~ret20, start_simulation_#t~ret21, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 21453#L531 assume 1 == ~m_i~0;~m_st~0 := 0; 21454#L538-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 21748#L543-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 21652#L548-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 21455#L553-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 21456#L558-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 21819#L563-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 21642#L568-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 21438#L573-1 assume !(0 == ~M_E~0); 21439#L771-1 assume !(0 == ~T1_E~0); 21297#L776-1 assume !(0 == ~T2_E~0); 21298#L781-1 assume !(0 == ~T3_E~0); 21704#L786-1 assume !(0 == ~T4_E~0); 21528#L791-1 assume !(0 == ~T5_E~0); 21236#L796-1 assume !(0 == ~T6_E~0); 21237#L801-1 assume !(0 == ~T7_E~0); 21890#L806-1 assume !(0 == ~E_M~0); 21600#L811-1 assume !(0 == ~E_1~0); 21385#L816-1 assume !(0 == ~E_2~0); 21386#L821-1 assume !(0 == ~E_3~0); 21929#L826-1 assume !(0 == ~E_4~0); 21785#L831-1 assume !(0 == ~E_5~0); 21588#L836-1 assume !(0 == ~E_6~0); 21146#L841-1 assume !(0 == ~E_7~0); 21147#L846-1 havoc activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 21220#L378 assume !(1 == ~m_pc~0); 21194#L378-2 is_master_triggered_~__retres1~0 := 0; 21195#L389 is_master_triggered_#res := is_master_triggered_~__retres1~0; 21754#L390 activate_threads_#t~ret11 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 21800#L957 assume !(0 != activate_threads_~tmp~1); 21947#L957-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 21422#L397 assume !(1 == ~t1_pc~0); 21340#L397-2 is_transmit1_triggered_~__retres1~1 := 0; 21427#L408 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 21804#L409 activate_threads_#t~ret12 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 21603#L965 assume !(0 != activate_threads_~tmp___0~0); 21594#L965-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 21595#L416 assume !(1 == ~t2_pc~0); 21508#L416-2 is_transmit2_triggered_~__retres1~2 := 0; 21507#L427 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 21910#L428 activate_threads_#t~ret13 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 21166#L973 assume !(0 != activate_threads_~tmp___1~0); 21167#L973-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 21172#L435 assume !(1 == ~t3_pc~0); 21777#L435-2 is_transmit3_triggered_~__retres1~3 := 0; 21264#L446 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 21265#L447 activate_threads_#t~ret14 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 21840#L981 assume !(0 != activate_threads_~tmp___2~0); 21829#L981-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 21830#L454 assume !(1 == ~t4_pc~0); 21882#L454-2 is_transmit4_triggered_~__retres1~4 := 0; 21459#L465 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 21214#L466 activate_threads_#t~ret15 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 21215#L989 assume !(0 != activate_threads_~tmp___3~0); 21532#L989-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 21534#L473 assume !(1 == ~t5_pc~0); 21874#L473-2 is_transmit5_triggered_~__retres1~5 := 0; 21578#L484 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 21441#L485 activate_threads_#t~ret16 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 21442#L997 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 21968#L997-2 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 21969#L492 assume 1 == ~t6_pc~0; 21972#L493 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6 := 1; 21688#L503 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 21653#L504 activate_threads_#t~ret17 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 21654#L1005 assume !(0 != activate_threads_~tmp___5~0); 21876#L1005-2 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 21135#L511 assume !(1 == ~t7_pc~0); 21136#L511-2 is_transmit7_triggered_~__retres1~7 := 0; 21291#L522 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 21701#L523 activate_threads_#t~ret18 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 21571#L1013 assume !(0 != activate_threads_~tmp___6~0); 21564#L1013-2 assume !(1 == ~M_E~0); 21565#L859-1 assume !(1 == ~T1_E~0); 21310#L864-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 21311#L869-1 assume !(1 == ~T3_E~0); 21702#L874-1 assume !(1 == ~T4_E~0); 21522#L879-1 assume !(1 == ~T5_E~0); 21232#L884-1 assume !(1 == ~T6_E~0); 21233#L889-1 assume !(1 == ~T7_E~0); 21888#L894-1 assume !(1 == ~E_M~0); 21596#L899-1 assume !(1 == ~E_1~0); 21378#L904-1 assume 1 == ~E_2~0;~E_2~0 := 2; 21379#L909-1 assume !(1 == ~E_3~0); 21932#L914-1 assume !(1 == ~E_4~0); 21787#L919-1 assume !(1 == ~E_5~0); 21593#L924-1 assume !(1 == ~E_6~0); 21175#L929-1 assume !(1 == ~E_7~0); 21176#L1180-1 [2018-11-23 16:06:13,888 INFO L796 eck$LassoCheckResult]: Loop: 21176#L1180-1 assume !false; 21878#L1181 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret2, eval_#t~nondet3, eval_~tmp_ndt_1~0, eval_#t~nondet4, eval_~tmp_ndt_2~0, eval_#t~nondet5, eval_~tmp_ndt_3~0, eval_#t~nondet6, eval_~tmp_ndt_4~0, eval_#t~nondet7, eval_~tmp_ndt_5~0, eval_#t~nondet8, eval_~tmp_ndt_6~0, eval_#t~nondet9, eval_~tmp_ndt_7~0, eval_#t~nondet10, eval_~tmp_ndt_8~0, eval_~tmp~0;havoc eval_~tmp~0; 21301#L746 assume !false; 21562#L639 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~8;havoc exists_runnable_thread_~__retres1~8; 21563#L586 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8 := 1; 21227#L628 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; 21827#L629 eval_#t~ret2 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret2;havoc eval_#t~ret2; 21121#L643 assume !(0 != eval_~tmp~0); 21123#L761 start_simulation_~kernel_st~0 := 2; 23712#L531-1 start_simulation_~kernel_st~0 := 3; 23711#L771-2 assume 0 == ~M_E~0;~M_E~0 := 1; 23710#L771-4 assume !(0 == ~T1_E~0); 23709#L776-3 assume !(0 == ~T2_E~0); 23708#L781-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 23707#L786-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 23706#L791-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 23705#L796-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 23704#L801-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 23703#L806-3 assume 0 == ~E_M~0;~E_M~0 := 1; 23702#L811-3 assume !(0 == ~E_1~0); 23701#L816-3 assume !(0 == ~E_2~0); 23700#L821-3 assume 0 == ~E_3~0;~E_3~0 := 1; 23699#L826-3 assume 0 == ~E_4~0;~E_4~0 := 1; 23626#L831-3 assume 0 == ~E_5~0;~E_5~0 := 1; 23625#L836-3 assume 0 == ~E_6~0;~E_6~0 := 1; 23624#L841-3 assume 0 == ~E_7~0;~E_7~0 := 1; 23623#L846-3 havoc activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 23622#L378-27 assume 1 == ~m_pc~0; 23620#L379-9 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 23619#L389-9 is_master_triggered_#res := is_master_triggered_~__retres1~0; 21790#L390-9 activate_threads_#t~ret11 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 21791#L957-27 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 21938#L957-29 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 21356#L397-27 assume !(1 == ~t1_pc~0); 21357#L397-29 is_transmit1_triggered_~__retres1~1 := 0; 21359#L408-9 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 21859#L409-9 activate_threads_#t~ret12 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 21673#L965-27 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 21664#L965-29 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 21520#L416-27 assume 1 == ~t2_pc~0; 21472#L417-9 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 21473#L427-9 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 21900#L428-9 activate_threads_#t~ret13 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 21316#L973-27 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 21317#L973-29 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 21324#L435-27 assume !(1 == ~t3_pc~0); 21640#L435-29 is_transmit3_triggered_~__retres1~3 := 0; 21258#L446-9 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 21259#L447-9 activate_threads_#t~ret14 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 21898#L981-27 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 21891#L981-29 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 21762#L454-27 assume !(1 == ~t4_pc~0); 21746#L454-29 is_transmit4_triggered_~__retres1~4 := 0; 21446#L465-9 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 21181#L466-9 activate_threads_#t~ret15 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 21182#L989-27 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 21475#L989-29 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 21479#L473-27 assume 1 == ~t5_pc~0; 21850#L474-9 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 21576#L484-9 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 21406#L485-9 activate_threads_#t~ret16 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 21407#L997-27 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 21949#L997-29 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 21950#L492-27 assume 1 == ~t6_pc~0; 21913#L493-9 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6 := 1; 21667#L503-9 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 21554#L504-9 activate_threads_#t~ret17 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 21555#L1005-27 assume !(0 != activate_threads_~tmp___5~0); 21715#L1005-29 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 21289#L511-27 assume 1 == ~t7_pc~0; 21248#L512-9 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7 := 1; 21249#L522-9 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 21773#L523-9 activate_threads_#t~ret18 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 21413#L1013-27 assume 0 != activate_threads_~tmp___6~0;~t7_st~0 := 0; 21388#L1013-29 assume 1 == ~M_E~0;~M_E~0 := 2; 21389#L859-3 assume !(1 == ~T1_E~0); 21295#L864-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 21296#L869-3 assume !(1 == ~T3_E~0); 21703#L874-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 21527#L879-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 21234#L884-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 21235#L889-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 21889#L894-3 assume 1 == ~E_M~0;~E_M~0 := 2; 21599#L899-3 assume !(1 == ~E_1~0); 21383#L904-3 assume 1 == ~E_2~0;~E_2~0 := 2; 21384#L909-3 assume !(1 == ~E_3~0); 21933#L914-3 assume 1 == ~E_4~0;~E_4~0 := 2; 21784#L919-3 assume 1 == ~E_5~0;~E_5~0 := 2; 21587#L924-3 assume 1 == ~E_6~0;~E_6~0 := 2; 21144#L929-3 assume 1 == ~E_7~0;~E_7~0 := 2; 21145#L934-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~8;havoc exists_runnable_thread_~__retres1~8; 21884#L586-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8 := 1; 21231#L628-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; 21813#L629-1 start_simulation_#t~ret20 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret20;havoc start_simulation_#t~ret20; 21814#L1199 assume !(0 == start_simulation_~tmp~3); 21718#L1199-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret19, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~8;havoc exists_runnable_thread_~__retres1~8; 21885#L586-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8 := 1; 21209#L628-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; 21817#L629-2 stop_simulation_#t~ret19 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret19;havoc stop_simulation_#t~ret19; 21818#L1154 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 21788#L1161 stop_simulation_#res := stop_simulation_~__retres2~0; 21775#L1162 start_simulation_#t~ret21 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret21;havoc start_simulation_#t~ret21; 21408#L1212 assume !(0 != start_simulation_~tmp___0~1); 21176#L1180-1 [2018-11-23 16:06:13,888 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 16:06:13,888 INFO L82 PathProgramCache]: Analyzing trace with hash 1562230178, now seen corresponding path program 1 times [2018-11-23 16:06:13,888 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 16:06:13,888 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 16:06:13,889 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 16:06:13,889 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 16:06:13,889 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 16:06:13,893 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 16:06:13,939 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 16:06:13,940 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 16:06:13,940 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2018-11-23 16:06:13,940 INFO L799 eck$LassoCheckResult]: stem already infeasible [2018-11-23 16:06:13,940 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 16:06:13,940 INFO L82 PathProgramCache]: Analyzing trace with hash 1273174737, now seen corresponding path program 1 times [2018-11-23 16:06:13,940 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 16:06:13,940 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 16:06:13,941 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 16:06:13,941 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 16:06:13,941 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 16:06:13,946 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 16:06:13,981 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 16:06:13,981 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 16:06:13,981 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-23 16:06:13,981 INFO L811 eck$LassoCheckResult]: loop already infeasible [2018-11-23 16:06:13,984 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-23 16:06:13,984 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-23 16:06:13,984 INFO L87 Difference]: Start difference. First operand 2679 states and 3907 transitions. cyclomatic complexity: 1232 Second operand 3 states. [2018-11-23 16:06:14,091 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 16:06:14,091 INFO L93 Difference]: Finished difference Result 5004 states and 7258 transitions. [2018-11-23 16:06:14,091 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-23 16:06:14,091 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 5004 states and 7258 transitions. [2018-11-23 16:06:14,111 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 4884 [2018-11-23 16:06:14,130 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 5004 states to 5004 states and 7258 transitions. [2018-11-23 16:06:14,130 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 5004 [2018-11-23 16:06:14,134 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 5004 [2018-11-23 16:06:14,134 INFO L73 IsDeterministic]: Start isDeterministic. Operand 5004 states and 7258 transitions. [2018-11-23 16:06:14,141 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-23 16:06:14,141 INFO L705 BuchiCegarLoop]: Abstraction has 5004 states and 7258 transitions. [2018-11-23 16:06:14,144 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 5004 states and 7258 transitions. [2018-11-23 16:06:14,221 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 5004 to 4996. [2018-11-23 16:06:14,221 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 4996 states. [2018-11-23 16:06:14,229 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 4996 states to 4996 states and 7250 transitions. [2018-11-23 16:06:14,230 INFO L728 BuchiCegarLoop]: Abstraction has 4996 states and 7250 transitions. [2018-11-23 16:06:14,230 INFO L608 BuchiCegarLoop]: Abstraction has 4996 states and 7250 transitions. [2018-11-23 16:06:14,230 INFO L442 BuchiCegarLoop]: ======== Iteration 13============ [2018-11-23 16:06:14,230 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 4996 states and 7250 transitions. [2018-11-23 16:06:14,242 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 4876 [2018-11-23 16:06:14,242 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-23 16:06:14,242 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-23 16:06:14,243 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 16:06:14,243 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 16:06:14,243 INFO L794 eck$LassoCheckResult]: Stem: 29273#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; 29177#L-1 havoc main_#res;havoc main_~__retres1~9;havoc main_~__retres1~9;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 29178#L1143 havoc start_simulation_#t~ret20, start_simulation_#t~ret21, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 29147#L531 assume 1 == ~m_i~0;~m_st~0 := 0; 29148#L538-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 29450#L543-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 29352#L548-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 29149#L553-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 29150#L558-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 29522#L563-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 29342#L568-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 29133#L573-1 assume !(0 == ~M_E~0); 29134#L771-1 assume !(0 == ~T1_E~0); 28989#L776-1 assume !(0 == ~T2_E~0); 28990#L781-1 assume !(0 == ~T3_E~0); 29403#L786-1 assume !(0 == ~T4_E~0); 29226#L791-1 assume !(0 == ~T5_E~0); 28927#L796-1 assume !(0 == ~T6_E~0); 28928#L801-1 assume !(0 == ~T7_E~0); 29589#L806-1 assume !(0 == ~E_M~0); 29301#L811-1 assume !(0 == ~E_1~0); 29080#L816-1 assume !(0 == ~E_2~0); 29081#L821-1 assume !(0 == ~E_3~0); 29638#L826-1 assume !(0 == ~E_4~0); 29487#L831-1 assume !(0 == ~E_5~0); 29288#L836-1 assume !(0 == ~E_6~0); 28842#L841-1 assume !(0 == ~E_7~0); 28843#L846-1 havoc activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 28911#L378 assume !(1 == ~m_pc~0); 28885#L378-2 is_master_triggered_~__retres1~0 := 0; 28886#L389 is_master_triggered_#res := is_master_triggered_~__retres1~0; 29459#L390 activate_threads_#t~ret11 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 29503#L957 assume !(0 != activate_threads_~tmp~1); 29657#L957-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 29117#L397 assume !(1 == ~t1_pc~0); 29035#L397-2 is_transmit1_triggered_~__retres1~1 := 0; 29122#L408 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 29507#L409 activate_threads_#t~ret12 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 29304#L965 assume !(0 != activate_threads_~tmp___0~0); 29295#L965-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 29296#L416 assume !(1 == ~t2_pc~0); 29205#L416-2 is_transmit2_triggered_~__retres1~2 := 0; 29204#L427 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 29613#L428 activate_threads_#t~ret13 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 28860#L973 assume !(0 != activate_threads_~tmp___1~0); 28861#L973-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 28865#L435 assume !(1 == ~t3_pc~0); 29479#L435-2 is_transmit3_triggered_~__retres1~3 := 0; 28955#L446 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 28956#L447 activate_threads_#t~ret14 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 29542#L981 assume !(0 != activate_threads_~tmp___2~0); 29531#L981-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 29532#L454 assume !(1 == ~t4_pc~0); 29581#L454-2 is_transmit4_triggered_~__retres1~4 := 0; 29153#L465 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 28905#L466 activate_threads_#t~ret15 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 28906#L989 assume !(0 != activate_threads_~tmp___3~0); 29232#L989-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 29234#L473 assume !(1 == ~t5_pc~0); 29575#L473-2 is_transmit5_triggered_~__retres1~5 := 0; 29278#L484 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 29136#L485 activate_threads_#t~ret16 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 29137#L997 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 29681#L997-2 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 29682#L492 assume !(1 == ~t6_pc~0); 29701#L492-2 is_transmit6_triggered_~__retres1~6 := 0; 29387#L503 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 29353#L504 activate_threads_#t~ret17 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 29354#L1005 assume !(0 != activate_threads_~tmp___5~0); 29578#L1005-2 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 28830#L511 assume !(1 == ~t7_pc~0); 28831#L511-2 is_transmit7_triggered_~__retres1~7 := 0; 28982#L522 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 29400#L523 activate_threads_#t~ret18 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 29271#L1013 assume !(0 != activate_threads_~tmp___6~0); 29264#L1013-2 assume !(1 == ~M_E~0); 29265#L859-1 assume !(1 == ~T1_E~0); 29003#L864-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 29004#L869-1 assume !(1 == ~T3_E~0); 29401#L874-1 assume !(1 == ~T4_E~0); 29221#L879-1 assume !(1 == ~T5_E~0); 28923#L884-1 assume !(1 == ~T6_E~0); 28924#L889-1 assume !(1 == ~T7_E~0); 29587#L894-1 assume !(1 == ~E_M~0); 29299#L899-1 assume !(1 == ~E_1~0); 29073#L904-1 assume 1 == ~E_2~0;~E_2~0 := 2; 29074#L909-1 assume !(1 == ~E_3~0); 29641#L914-1 assume !(1 == ~E_4~0); 29489#L919-1 assume !(1 == ~E_5~0); 29294#L924-1 assume !(1 == ~E_6~0); 28866#L929-1 assume !(1 == ~E_7~0); 28867#L1180-1 [2018-11-23 16:06:14,243 INFO L796 eck$LassoCheckResult]: Loop: 28867#L1180-1 assume !false; 30685#L1181 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret2, eval_#t~nondet3, eval_~tmp_ndt_1~0, eval_#t~nondet4, eval_~tmp_ndt_2~0, eval_#t~nondet5, eval_~tmp_ndt_3~0, eval_#t~nondet6, eval_~tmp_ndt_4~0, eval_#t~nondet7, eval_~tmp_ndt_5~0, eval_#t~nondet8, eval_~tmp_ndt_6~0, eval_#t~nondet9, eval_~tmp_ndt_7~0, eval_#t~nondet10, eval_~tmp_ndt_8~0, eval_~tmp~0;havoc eval_~tmp~0; 30680#L746 assume !false; 30679#L639 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~8;havoc exists_runnable_thread_~__retres1~8; 30677#L586 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8 := 1; 30670#L628 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; 30669#L629 eval_#t~ret2 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret2;havoc eval_#t~ret2; 30667#L643 assume !(0 != eval_~tmp~0); 30668#L761 start_simulation_~kernel_st~0 := 2; 31661#L531-1 start_simulation_~kernel_st~0 := 3; 31659#L771-2 assume 0 == ~M_E~0;~M_E~0 := 1; 31654#L771-4 assume !(0 == ~T1_E~0); 31653#L776-3 assume !(0 == ~T2_E~0); 31652#L781-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 31651#L786-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 31650#L791-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 31649#L796-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 31648#L801-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 31647#L806-3 assume 0 == ~E_M~0;~E_M~0 := 1; 31646#L811-3 assume !(0 == ~E_1~0); 31645#L816-3 assume !(0 == ~E_2~0); 31643#L821-3 assume 0 == ~E_3~0;~E_3~0 := 1; 31640#L826-3 assume 0 == ~E_4~0;~E_4~0 := 1; 31638#L831-3 assume 0 == ~E_5~0;~E_5~0 := 1; 31636#L836-3 assume 0 == ~E_6~0;~E_6~0 := 1; 31634#L841-3 assume 0 == ~E_7~0;~E_7~0 := 1; 31632#L846-3 havoc activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 31629#L378-27 assume 1 == ~m_pc~0; 31626#L379-9 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 31624#L389-9 is_master_triggered_#res := is_master_triggered_~__retres1~0; 31622#L390-9 activate_threads_#t~ret11 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 31620#L957-27 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 31618#L957-29 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 31616#L397-27 assume !(1 == ~t1_pc~0); 31612#L397-29 is_transmit1_triggered_~__retres1~1 := 0; 31610#L408-9 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 31608#L409-9 activate_threads_#t~ret12 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 31606#L965-27 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 31604#L965-29 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 31602#L416-27 assume !(1 == ~t2_pc~0); 31600#L416-29 is_transmit2_triggered_~__retres1~2 := 0; 31597#L427-9 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 31595#L428-9 activate_threads_#t~ret13 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 31593#L973-27 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 31591#L973-29 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 31590#L435-27 assume !(1 == ~t3_pc~0); 31589#L435-29 is_transmit3_triggered_~__retres1~3 := 0; 31588#L446-9 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 31587#L447-9 activate_threads_#t~ret14 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 31585#L981-27 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 31583#L981-29 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 31581#L454-27 assume !(1 == ~t4_pc~0); 31579#L454-29 is_transmit4_triggered_~__retres1~4 := 0; 31576#L465-9 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 31574#L466-9 activate_threads_#t~ret15 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 31572#L989-27 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 31570#L989-29 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 31569#L473-27 assume !(1 == ~t5_pc~0); 31565#L473-29 is_transmit5_triggered_~__retres1~5 := 0; 31563#L484-9 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 31558#L485-9 activate_threads_#t~ret16 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 31556#L997-27 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 31553#L997-29 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 31552#L492-27 assume !(1 == ~t6_pc~0); 31551#L492-29 is_transmit6_triggered_~__retres1~6 := 0; 31550#L503-9 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 31549#L504-9 activate_threads_#t~ret17 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 31548#L1005-27 assume !(0 != activate_threads_~tmp___5~0); 31547#L1005-29 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 31546#L511-27 assume 1 == ~t7_pc~0; 31544#L512-9 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7 := 1; 31543#L522-9 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 31542#L523-9 activate_threads_#t~ret18 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 31541#L1013-27 assume 0 != activate_threads_~tmp___6~0;~t7_st~0 := 0; 31540#L1013-29 assume 1 == ~M_E~0;~M_E~0 := 2; 31539#L859-3 assume !(1 == ~T1_E~0); 31537#L864-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 31534#L869-3 assume !(1 == ~T3_E~0); 31532#L874-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 31530#L879-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 31528#L884-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 31526#L889-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 31525#L894-3 assume 1 == ~E_M~0;~E_M~0 := 2; 31522#L899-3 assume !(1 == ~E_1~0); 31520#L904-3 assume 1 == ~E_2~0;~E_2~0 := 2; 31518#L909-3 assume !(1 == ~E_3~0); 31516#L914-3 assume 1 == ~E_4~0;~E_4~0 := 2; 31514#L919-3 assume 1 == ~E_5~0;~E_5~0 := 2; 31512#L924-3 assume 1 == ~E_6~0;~E_6~0 := 2; 31510#L929-3 assume 1 == ~E_7~0;~E_7~0 := 2; 31507#L934-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~8;havoc exists_runnable_thread_~__retres1~8; 31505#L586-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8 := 1; 31496#L628-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; 31494#L629-1 start_simulation_#t~ret20 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret20;havoc start_simulation_#t~ret20; 30714#L1199 assume !(0 == start_simulation_~tmp~3); 30711#L1199-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret19, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~8;havoc exists_runnable_thread_~__retres1~8; 30709#L586-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8 := 1; 30701#L628-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; 30697#L629-2 stop_simulation_#t~ret19 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret19;havoc stop_simulation_#t~ret19; 30695#L1154 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 30694#L1161 stop_simulation_#res := stop_simulation_~__retres2~0; 30693#L1162 start_simulation_#t~ret21 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret21;havoc start_simulation_#t~ret21; 30689#L1212 assume !(0 != start_simulation_~tmp___0~1); 28867#L1180-1 [2018-11-23 16:06:14,244 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 16:06:14,244 INFO L82 PathProgramCache]: Analyzing trace with hash -110287453, now seen corresponding path program 1 times [2018-11-23 16:06:14,244 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 16:06:14,244 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 16:06:14,244 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 16:06:14,245 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 16:06:14,245 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 16:06:14,249 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 16:06:14,280 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 16:06:14,280 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 16:06:14,280 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2018-11-23 16:06:14,280 INFO L799 eck$LassoCheckResult]: stem already infeasible [2018-11-23 16:06:14,280 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 16:06:14,281 INFO L82 PathProgramCache]: Analyzing trace with hash 1070079854, now seen corresponding path program 1 times [2018-11-23 16:06:14,281 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 16:06:14,281 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 16:06:14,281 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 16:06:14,281 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 16:06:14,281 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 16:06:14,286 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 16:06:14,317 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 16:06:14,317 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 16:06:14,317 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-23 16:06:14,317 INFO L811 eck$LassoCheckResult]: loop already infeasible [2018-11-23 16:06:14,317 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-23 16:06:14,317 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-23 16:06:14,318 INFO L87 Difference]: Start difference. First operand 4996 states and 7250 transitions. cyclomatic complexity: 2262 Second operand 3 states. [2018-11-23 16:06:14,354 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 16:06:14,354 INFO L93 Difference]: Finished difference Result 4996 states and 7224 transitions. [2018-11-23 16:06:14,354 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-23 16:06:14,354 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 4996 states and 7224 transitions. [2018-11-23 16:06:14,370 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 4876 [2018-11-23 16:06:14,389 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 4996 states to 4996 states and 7224 transitions. [2018-11-23 16:06:14,389 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 4996 [2018-11-23 16:06:14,392 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 4996 [2018-11-23 16:06:14,392 INFO L73 IsDeterministic]: Start isDeterministic. Operand 4996 states and 7224 transitions. [2018-11-23 16:06:14,397 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-23 16:06:14,397 INFO L705 BuchiCegarLoop]: Abstraction has 4996 states and 7224 transitions. [2018-11-23 16:06:14,401 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 4996 states and 7224 transitions. [2018-11-23 16:06:14,442 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 4996 to 4996. [2018-11-23 16:06:14,443 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 4996 states. [2018-11-23 16:06:14,452 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 4996 states to 4996 states and 7224 transitions. [2018-11-23 16:06:14,452 INFO L728 BuchiCegarLoop]: Abstraction has 4996 states and 7224 transitions. [2018-11-23 16:06:14,452 INFO L608 BuchiCegarLoop]: Abstraction has 4996 states and 7224 transitions. [2018-11-23 16:06:14,452 INFO L442 BuchiCegarLoop]: ======== Iteration 14============ [2018-11-23 16:06:14,452 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 4996 states and 7224 transitions. [2018-11-23 16:06:14,464 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 4876 [2018-11-23 16:06:14,464 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-23 16:06:14,465 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-23 16:06:14,465 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 16:06:14,466 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 16:06:14,466 INFO L794 eck$LassoCheckResult]: Stem: 39272#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; 39176#L-1 havoc main_#res;havoc main_~__retres1~9;havoc main_~__retres1~9;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 39177#L1143 havoc start_simulation_#t~ret20, start_simulation_#t~ret21, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 39147#L531 assume 1 == ~m_i~0;~m_st~0 := 0; 39148#L538-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 39441#L543-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 39344#L548-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 39149#L553-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 39150#L558-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 39516#L563-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 39336#L568-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 39132#L573-1 assume !(0 == ~M_E~0); 39133#L771-1 assume !(0 == ~T1_E~0); 38987#L776-1 assume !(0 == ~T2_E~0); 38988#L781-1 assume !(0 == ~T3_E~0); 39399#L786-1 assume !(0 == ~T4_E~0); 39224#L791-1 assume !(0 == ~T5_E~0); 38926#L796-1 assume !(0 == ~T6_E~0); 38927#L801-1 assume !(0 == ~T7_E~0); 39594#L806-1 assume !(0 == ~E_M~0); 39302#L811-1 assume !(0 == ~E_1~0); 39077#L816-1 assume !(0 == ~E_2~0); 39078#L821-1 assume !(0 == ~E_3~0); 39638#L826-1 assume !(0 == ~E_4~0); 39479#L831-1 assume !(0 == ~E_5~0); 39288#L836-1 assume !(0 == ~E_6~0); 38835#L841-1 assume !(0 == ~E_7~0); 38836#L846-1 havoc activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 38910#L378 assume !(1 == ~m_pc~0); 38884#L378-2 is_master_triggered_~__retres1~0 := 0; 38885#L389 is_master_triggered_#res := is_master_triggered_~__retres1~0; 39446#L390 activate_threads_#t~ret11 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 39495#L957 assume !(0 != activate_threads_~tmp~1); 39661#L957-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 39114#L397 assume !(1 == ~t1_pc~0); 39032#L397-2 is_transmit1_triggered_~__retres1~1 := 0; 39119#L408 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 39500#L409 activate_threads_#t~ret12 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 39305#L965 assume !(0 != activate_threads_~tmp___0~0); 39294#L965-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 39295#L416 assume !(1 == ~t2_pc~0); 39202#L416-2 is_transmit2_triggered_~__retres1~2 := 0; 39201#L427 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 39613#L428 activate_threads_#t~ret13 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 38855#L973 assume !(0 != activate_threads_~tmp___1~0); 38856#L973-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 38861#L435 assume !(1 == ~t3_pc~0); 39469#L435-2 is_transmit3_triggered_~__retres1~3 := 0; 38951#L446 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 38952#L447 activate_threads_#t~ret14 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 39538#L981 assume !(0 != activate_threads_~tmp___2~0); 39528#L981-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 39529#L454 assume !(1 == ~t4_pc~0); 39584#L454-2 is_transmit4_triggered_~__retres1~4 := 0; 39153#L465 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 38904#L466 activate_threads_#t~ret15 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 38905#L989 assume !(0 != activate_threads_~tmp___3~0); 39228#L989-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 39230#L473 assume !(1 == ~t5_pc~0); 39578#L473-2 is_transmit5_triggered_~__retres1~5 := 0; 39277#L484 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 39135#L485 activate_threads_#t~ret16 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 39136#L997 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 39687#L997-2 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 39688#L492 assume !(1 == ~t6_pc~0); 39717#L492-2 is_transmit6_triggered_~__retres1~6 := 0; 39382#L503 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 39345#L504 activate_threads_#t~ret17 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 39346#L1005 assume !(0 != activate_threads_~tmp___5~0); 39581#L1005-2 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 38824#L511 assume !(1 == ~t7_pc~0); 38825#L511-2 is_transmit7_triggered_~__retres1~7 := 0; 38981#L522 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 39396#L523 activate_threads_#t~ret18 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 39270#L1013 assume !(0 != activate_threads_~tmp___6~0); 39262#L1013-2 assume !(1 == ~M_E~0); 39263#L859-1 assume !(1 == ~T1_E~0); 39000#L864-1 assume !(1 == ~T2_E~0); 39001#L869-1 assume !(1 == ~T3_E~0); 39397#L874-1 assume !(1 == ~T4_E~0); 39218#L879-1 assume !(1 == ~T5_E~0); 38922#L884-1 assume !(1 == ~T6_E~0); 38923#L889-1 assume !(1 == ~T7_E~0); 39592#L894-1 assume !(1 == ~E_M~0); 39296#L899-1 assume !(1 == ~E_1~0); 39069#L904-1 assume 1 == ~E_2~0;~E_2~0 := 2; 39070#L909-1 assume !(1 == ~E_3~0); 39641#L914-1 assume !(1 == ~E_4~0); 39481#L919-1 assume !(1 == ~E_5~0); 39293#L924-1 assume !(1 == ~E_6~0); 38864#L929-1 assume !(1 == ~E_7~0); 38865#L1180-1 [2018-11-23 16:06:14,466 INFO L796 eck$LassoCheckResult]: Loop: 38865#L1180-1 assume !false; 40881#L1181 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret2, eval_#t~nondet3, eval_~tmp_ndt_1~0, eval_#t~nondet4, eval_~tmp_ndt_2~0, eval_#t~nondet5, eval_~tmp_ndt_3~0, eval_#t~nondet6, eval_~tmp_ndt_4~0, eval_#t~nondet7, eval_~tmp_ndt_5~0, eval_#t~nondet8, eval_~tmp_ndt_6~0, eval_#t~nondet9, eval_~tmp_ndt_7~0, eval_#t~nondet10, eval_~tmp_ndt_8~0, eval_~tmp~0;havoc eval_~tmp~0; 40875#L746 assume !false; 40873#L639 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~8;havoc exists_runnable_thread_~__retres1~8; 40867#L586 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8 := 1; 40859#L628 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; 40856#L629 eval_#t~ret2 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret2;havoc eval_#t~ret2; 40853#L643 assume !(0 != eval_~tmp~0); 40854#L761 start_simulation_~kernel_st~0 := 2; 42025#L531-1 start_simulation_~kernel_st~0 := 3; 42023#L771-2 assume 0 == ~M_E~0;~M_E~0 := 1; 42021#L771-4 assume !(0 == ~T1_E~0); 42019#L776-3 assume !(0 == ~T2_E~0); 42017#L781-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 42015#L786-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 42013#L791-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 42011#L796-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 42009#L801-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 42007#L806-3 assume 0 == ~E_M~0;~E_M~0 := 1; 42005#L811-3 assume !(0 == ~E_1~0); 42003#L816-3 assume !(0 == ~E_2~0); 42001#L821-3 assume 0 == ~E_3~0;~E_3~0 := 1; 42000#L826-3 assume 0 == ~E_4~0;~E_4~0 := 1; 41999#L831-3 assume 0 == ~E_5~0;~E_5~0 := 1; 41997#L836-3 assume 0 == ~E_6~0;~E_6~0 := 1; 41996#L841-3 assume 0 == ~E_7~0;~E_7~0 := 1; 41995#L846-3 havoc activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 41994#L378-27 assume 1 == ~m_pc~0; 41992#L379-9 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 41991#L389-9 is_master_triggered_#res := is_master_triggered_~__retres1~0; 41990#L390-9 activate_threads_#t~ret11 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 41989#L957-27 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 41988#L957-29 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 41987#L397-27 assume !(1 == ~t1_pc~0); 41985#L397-29 is_transmit1_triggered_~__retres1~1 := 0; 41984#L408-9 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 41983#L409-9 activate_threads_#t~ret12 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 41982#L965-27 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 41981#L965-29 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 41980#L416-27 assume 1 == ~t2_pc~0; 41978#L417-9 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 41976#L427-9 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 41973#L428-9 activate_threads_#t~ret13 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 41971#L973-27 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 41969#L973-29 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 41967#L435-27 assume !(1 == ~t3_pc~0); 41965#L435-29 is_transmit3_triggered_~__retres1~3 := 0; 41962#L446-9 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 41960#L447-9 activate_threads_#t~ret14 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 41958#L981-27 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 41956#L981-29 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 41954#L454-27 assume !(1 == ~t4_pc~0); 41952#L454-29 is_transmit4_triggered_~__retres1~4 := 0; 41950#L465-9 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 41947#L466-9 activate_threads_#t~ret15 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 41945#L989-27 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 41943#L989-29 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 41941#L473-27 assume !(1 == ~t5_pc~0); 41938#L473-29 is_transmit5_triggered_~__retres1~5 := 0; 41936#L484-9 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 41933#L485-9 activate_threads_#t~ret16 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 41931#L997-27 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 41929#L997-29 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 41927#L492-27 assume !(1 == ~t6_pc~0); 41925#L492-29 is_transmit6_triggered_~__retres1~6 := 0; 41923#L503-9 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 41920#L504-9 activate_threads_#t~ret17 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 41918#L1005-27 assume !(0 != activate_threads_~tmp___5~0); 41916#L1005-29 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 41914#L511-27 assume 1 == ~t7_pc~0; 41911#L512-9 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7 := 1; 41909#L522-9 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 41906#L523-9 activate_threads_#t~ret18 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 41904#L1013-27 assume 0 != activate_threads_~tmp___6~0;~t7_st~0 := 0; 41902#L1013-29 assume 1 == ~M_E~0;~M_E~0 := 2; 41900#L859-3 assume !(1 == ~T1_E~0); 41898#L864-3 assume !(1 == ~T2_E~0); 41896#L869-3 assume !(1 == ~T3_E~0); 41894#L874-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 41892#L879-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 41890#L884-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 41888#L889-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 41886#L894-3 assume 1 == ~E_M~0;~E_M~0 := 2; 41884#L899-3 assume !(1 == ~E_1~0); 41881#L904-3 assume 1 == ~E_2~0;~E_2~0 := 2; 41879#L909-3 assume !(1 == ~E_3~0); 41877#L914-3 assume 1 == ~E_4~0;~E_4~0 := 2; 41876#L919-3 assume 1 == ~E_5~0;~E_5~0 := 2; 41875#L924-3 assume 1 == ~E_6~0;~E_6~0 := 2; 41874#L929-3 assume 1 == ~E_7~0;~E_7~0 := 2; 41873#L934-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~8;havoc exists_runnable_thread_~__retres1~8; 41872#L586-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8 := 1; 41862#L628-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; 41860#L629-1 start_simulation_#t~ret20 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret20;havoc start_simulation_#t~ret20; 41858#L1199 assume !(0 == start_simulation_~tmp~3); 41855#L1199-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret19, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~8;havoc exists_runnable_thread_~__retres1~8; 40903#L586-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8 := 1; 40894#L628-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; 40892#L629-2 stop_simulation_#t~ret19 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret19;havoc stop_simulation_#t~ret19; 40890#L1154 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 40888#L1161 stop_simulation_#res := stop_simulation_~__retres2~0; 40886#L1162 start_simulation_#t~ret21 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret21;havoc start_simulation_#t~ret21; 40884#L1212 assume !(0 != start_simulation_~tmp___0~1); 38865#L1180-1 [2018-11-23 16:06:14,466 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 16:06:14,466 INFO L82 PathProgramCache]: Analyzing trace with hash -1121404703, now seen corresponding path program 1 times [2018-11-23 16:06:14,466 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 16:06:14,467 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 16:06:14,467 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 16:06:14,467 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 16:06:14,467 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 16:06:14,472 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 16:06:14,496 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 16:06:14,497 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 16:06:14,497 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2018-11-23 16:06:14,497 INFO L799 eck$LassoCheckResult]: stem already infeasible [2018-11-23 16:06:14,497 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 16:06:14,497 INFO L82 PathProgramCache]: Analyzing trace with hash -2006578095, now seen corresponding path program 1 times [2018-11-23 16:06:14,497 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 16:06:14,497 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 16:06:14,498 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 16:06:14,498 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 16:06:14,498 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 16:06:14,502 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 16:06:14,529 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 16:06:14,529 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 16:06:14,529 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-23 16:06:14,530 INFO L811 eck$LassoCheckResult]: loop already infeasible [2018-11-23 16:06:14,530 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-23 16:06:14,530 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-23 16:06:14,530 INFO L87 Difference]: Start difference. First operand 4996 states and 7224 transitions. cyclomatic complexity: 2236 Second operand 3 states. [2018-11-23 16:06:14,618 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 16:06:14,618 INFO L93 Difference]: Finished difference Result 4996 states and 7137 transitions. [2018-11-23 16:06:14,619 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-23 16:06:14,619 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 4996 states and 7137 transitions. [2018-11-23 16:06:14,635 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 4876 [2018-11-23 16:06:14,651 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 4996 states to 4996 states and 7137 transitions. [2018-11-23 16:06:14,651 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 4996 [2018-11-23 16:06:14,654 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 4996 [2018-11-23 16:06:14,654 INFO L73 IsDeterministic]: Start isDeterministic. Operand 4996 states and 7137 transitions. [2018-11-23 16:06:14,658 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-23 16:06:14,659 INFO L705 BuchiCegarLoop]: Abstraction has 4996 states and 7137 transitions. [2018-11-23 16:06:14,662 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 4996 states and 7137 transitions. [2018-11-23 16:06:14,702 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 4996 to 4996. [2018-11-23 16:06:14,702 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 4996 states. [2018-11-23 16:06:14,711 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 4996 states to 4996 states and 7137 transitions. [2018-11-23 16:06:14,711 INFO L728 BuchiCegarLoop]: Abstraction has 4996 states and 7137 transitions. [2018-11-23 16:06:14,712 INFO L608 BuchiCegarLoop]: Abstraction has 4996 states and 7137 transitions. [2018-11-23 16:06:14,712 INFO L442 BuchiCegarLoop]: ======== Iteration 15============ [2018-11-23 16:06:14,712 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 4996 states and 7137 transitions. [2018-11-23 16:06:14,724 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 4876 [2018-11-23 16:06:14,724 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-23 16:06:14,724 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-23 16:06:14,725 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 16:06:14,725 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 16:06:14,725 INFO L794 eck$LassoCheckResult]: Stem: 49264#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; 49166#L-1 havoc main_#res;havoc main_~__retres1~9;havoc main_~__retres1~9;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 49167#L1143 havoc start_simulation_#t~ret20, start_simulation_#t~ret21, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 49140#L531 assume 1 == ~m_i~0;~m_st~0 := 0; 49141#L538-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 49438#L543-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 49340#L548-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 49142#L553-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 49143#L558-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 49514#L563-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 49331#L568-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 49126#L573-1 assume !(0 == ~M_E~0); 49127#L771-1 assume !(0 == ~T1_E~0); 48985#L776-1 assume !(0 == ~T2_E~0); 48986#L781-1 assume !(0 == ~T3_E~0); 49393#L786-1 assume !(0 == ~T4_E~0); 49211#L791-1 assume !(0 == ~T5_E~0); 48924#L796-1 assume !(0 == ~T6_E~0); 48925#L801-1 assume !(0 == ~T7_E~0); 49587#L806-1 assume !(0 == ~E_M~0); 49292#L811-1 assume !(0 == ~E_1~0); 49073#L816-1 assume !(0 == ~E_2~0); 49074#L821-1 assume !(0 == ~E_3~0); 49631#L826-1 assume !(0 == ~E_4~0); 49477#L831-1 assume !(0 == ~E_5~0); 49280#L836-1 assume !(0 == ~E_6~0); 48834#L841-1 assume !(0 == ~E_7~0); 48835#L846-1 havoc activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 48908#L378 assume !(1 == ~m_pc~0); 48882#L378-2 is_master_triggered_~__retres1~0 := 0; 48883#L389 is_master_triggered_#res := is_master_triggered_~__retres1~0; 49444#L390 activate_threads_#t~ret11 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 49493#L957 assume !(0 != activate_threads_~tmp~1); 49649#L957-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 49110#L397 assume !(1 == ~t1_pc~0); 49029#L397-2 is_transmit1_triggered_~__retres1~1 := 0; 49115#L408 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 49498#L409 activate_threads_#t~ret12 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 49295#L965 assume !(0 != activate_threads_~tmp___0~0); 49286#L965-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 49287#L416 assume !(1 == ~t2_pc~0); 49187#L416-2 is_transmit2_triggered_~__retres1~2 := 0; 49228#L427 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 49610#L428 activate_threads_#t~ret13 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 48854#L973 assume !(0 != activate_threads_~tmp___1~0); 48855#L973-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 48860#L435 assume !(1 == ~t3_pc~0); 49469#L435-2 is_transmit3_triggered_~__retres1~3 := 0; 48949#L446 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 48950#L447 activate_threads_#t~ret14 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 49537#L981 assume !(0 != activate_threads_~tmp___2~0); 49525#L981-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 49526#L454 assume !(1 == ~t4_pc~0); 49576#L454-2 is_transmit4_triggered_~__retres1~4 := 0; 49146#L465 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 48902#L466 activate_threads_#t~ret15 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 48903#L989 assume !(0 != activate_threads_~tmp___3~0); 49215#L989-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 49218#L473 assume !(1 == ~t5_pc~0); 49570#L473-2 is_transmit5_triggered_~__retres1~5 := 0; 49270#L484 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 49129#L485 activate_threads_#t~ret16 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 49130#L997 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 49673#L997-2 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 49674#L492 assume !(1 == ~t6_pc~0); 49690#L492-2 is_transmit6_triggered_~__retres1~6 := 0; 49377#L503 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 49341#L504 activate_threads_#t~ret17 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 49342#L1005 assume !(0 != activate_threads_~tmp___5~0); 49572#L1005-2 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 48823#L511 assume !(1 == ~t7_pc~0); 48824#L511-2 is_transmit7_triggered_~__retres1~7 := 0; 48979#L522 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 49390#L523 activate_threads_#t~ret18 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 49262#L1013 assume !(0 != activate_threads_~tmp___6~0); 49255#L1013-2 assume !(1 == ~M_E~0); 49256#L859-1 assume !(1 == ~T1_E~0); 48998#L864-1 assume !(1 == ~T2_E~0); 48999#L869-1 assume !(1 == ~T3_E~0); 49391#L874-1 assume !(1 == ~T4_E~0); 49204#L879-1 assume !(1 == ~T5_E~0); 48920#L884-1 assume !(1 == ~T6_E~0); 48921#L889-1 assume !(1 == ~T7_E~0); 49585#L894-1 assume !(1 == ~E_M~0); 49288#L899-1 assume !(1 == ~E_1~0); 49066#L904-1 assume !(1 == ~E_2~0); 49067#L909-1 assume !(1 == ~E_3~0); 49634#L914-1 assume !(1 == ~E_4~0); 49479#L919-1 assume !(1 == ~E_5~0); 49285#L924-1 assume !(1 == ~E_6~0); 48863#L929-1 assume !(1 == ~E_7~0); 48864#L1180-1 [2018-11-23 16:06:14,725 INFO L796 eck$LassoCheckResult]: Loop: 48864#L1180-1 assume !false; 50739#L1181 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret2, eval_#t~nondet3, eval_~tmp_ndt_1~0, eval_#t~nondet4, eval_~tmp_ndt_2~0, eval_#t~nondet5, eval_~tmp_ndt_3~0, eval_#t~nondet6, eval_~tmp_ndt_4~0, eval_#t~nondet7, eval_~tmp_ndt_5~0, eval_#t~nondet8, eval_~tmp_ndt_6~0, eval_#t~nondet9, eval_~tmp_ndt_7~0, eval_#t~nondet10, eval_~tmp_ndt_8~0, eval_~tmp~0;havoc eval_~tmp~0; 50733#L746 assume !false; 50731#L639 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~8;havoc exists_runnable_thread_~__retres1~8; 50723#L586 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8 := 1; 50715#L628 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; 50714#L629 eval_#t~ret2 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret2;havoc eval_#t~ret2; 50712#L643 assume !(0 != eval_~tmp~0); 50713#L761 start_simulation_~kernel_st~0 := 2; 53745#L531-1 start_simulation_~kernel_st~0 := 3; 53744#L771-2 assume 0 == ~M_E~0;~M_E~0 := 1; 53743#L771-4 assume !(0 == ~T1_E~0); 48991#L776-3 assume !(0 == ~T2_E~0); 48992#L781-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 53667#L786-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 53653#L791-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 53649#L796-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 53646#L801-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 53643#L806-3 assume 0 == ~E_M~0;~E_M~0 := 1; 53635#L811-3 assume !(0 == ~E_1~0); 53630#L816-3 assume !(0 == ~E_2~0); 53628#L821-3 assume 0 == ~E_3~0;~E_3~0 := 1; 53625#L826-3 assume 0 == ~E_4~0;~E_4~0 := 1; 53622#L831-3 assume 0 == ~E_5~0;~E_5~0 := 1; 53620#L836-3 assume 0 == ~E_6~0;~E_6~0 := 1; 53618#L841-3 assume 0 == ~E_7~0;~E_7~0 := 1; 53616#L846-3 havoc activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 53613#L378-27 assume 1 == ~m_pc~0; 53610#L379-9 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 53608#L389-9 is_master_triggered_#res := is_master_triggered_~__retres1~0; 53606#L390-9 activate_threads_#t~ret11 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 53604#L957-27 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 53602#L957-29 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 53599#L397-27 assume !(1 == ~t1_pc~0); 53596#L397-29 is_transmit1_triggered_~__retres1~1 := 0; 53595#L408-9 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 53594#L409-9 activate_threads_#t~ret12 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 53593#L965-27 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 53591#L965-29 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 53589#L416-27 assume !(1 == ~t2_pc~0); 53586#L416-29 is_transmit2_triggered_~__retres1~2 := 0; 53584#L427-9 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 53558#L428-9 activate_threads_#t~ret13 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 53557#L973-27 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 49011#L973-29 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 49012#L435-27 assume !(1 == ~t3_pc~0); 49329#L435-29 is_transmit3_triggered_~__retres1~3 := 0; 53592#L446-9 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 53590#L447-9 activate_threads_#t~ret14 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 53587#L981-27 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 53585#L981-29 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 53583#L454-27 assume !(1 == ~t4_pc~0); 53580#L454-29 is_transmit4_triggered_~__retres1~4 := 0; 49133#L465-9 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 48869#L466-9 activate_threads_#t~ret15 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 48870#L989-27 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 49160#L989-29 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 49163#L473-27 assume 1 == ~t5_pc~0; 49547#L474-9 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 49267#L484-9 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 49268#L485-9 activate_threads_#t~ret16 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 53553#L997-27 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 53552#L997-29 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 53551#L492-27 assume !(1 == ~t6_pc~0); 53550#L492-29 is_transmit6_triggered_~__retres1~6 := 0; 53549#L503-9 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 53548#L504-9 activate_threads_#t~ret17 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 53547#L1005-27 assume !(0 != activate_threads_~tmp___5~0); 53546#L1005-29 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 53545#L511-27 assume 1 == ~t7_pc~0; 53543#L512-9 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7 := 1; 53542#L522-9 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 53541#L523-9 activate_threads_#t~ret18 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 53540#L1013-27 assume 0 != activate_threads_~tmp___6~0;~t7_st~0 := 0; 53539#L1013-29 assume 1 == ~M_E~0;~M_E~0 := 2; 53538#L859-3 assume !(1 == ~T1_E~0); 53537#L864-3 assume !(1 == ~T2_E~0); 53536#L869-3 assume !(1 == ~T3_E~0); 53535#L874-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 53534#L879-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 53532#L884-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 53529#L889-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 53527#L894-3 assume 1 == ~E_M~0;~E_M~0 := 2; 53525#L899-3 assume !(1 == ~E_1~0); 53523#L904-3 assume !(1 == ~E_2~0); 53521#L909-3 assume !(1 == ~E_3~0); 52921#L914-3 assume 1 == ~E_4~0;~E_4~0 := 2; 52920#L919-3 assume 1 == ~E_5~0;~E_5~0 := 2; 52919#L924-3 assume 1 == ~E_6~0;~E_6~0 := 2; 52832#L929-3 assume 1 == ~E_7~0;~E_7~0 := 2; 50783#L934-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~8;havoc exists_runnable_thread_~__retres1~8; 50780#L586-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8 := 1; 50771#L628-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; 50769#L629-1 start_simulation_#t~ret20 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret20;havoc start_simulation_#t~ret20; 50766#L1199 assume !(0 == start_simulation_~tmp~3); 50764#L1199-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret19, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~8;havoc exists_runnable_thread_~__retres1~8; 50760#L586-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8 := 1; 50751#L628-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; 50750#L629-2 stop_simulation_#t~ret19 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret19;havoc stop_simulation_#t~ret19; 50749#L1154 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 50745#L1161 stop_simulation_#res := stop_simulation_~__retres2~0; 50742#L1162 start_simulation_#t~ret21 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret21;havoc start_simulation_#t~ret21; 50741#L1212 assume !(0 != start_simulation_~tmp___0~1); 48864#L1180-1 [2018-11-23 16:06:14,726 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 16:06:14,726 INFO L82 PathProgramCache]: Analyzing trace with hash -1064146401, now seen corresponding path program 1 times [2018-11-23 16:06:14,726 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 16:06:14,726 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 16:06:14,726 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 16:06:14,727 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 16:06:14,727 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 16:06:14,733 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 16:06:14,812 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 16:06:14,812 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 16:06:14,812 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-11-23 16:06:14,812 INFO L799 eck$LassoCheckResult]: stem already infeasible [2018-11-23 16:06:14,812 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 16:06:14,812 INFO L82 PathProgramCache]: Analyzing trace with hash -1682598381, now seen corresponding path program 1 times [2018-11-23 16:06:14,813 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 16:06:14,813 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 16:06:14,813 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 16:06:14,813 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 16:06:14,813 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 16:06:14,818 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 16:06:14,836 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 16:06:14,836 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 16:06:14,836 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-23 16:06:14,836 INFO L811 eck$LassoCheckResult]: loop already infeasible [2018-11-23 16:06:14,837 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-11-23 16:06:14,837 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-11-23 16:06:14,837 INFO L87 Difference]: Start difference. First operand 4996 states and 7137 transitions. cyclomatic complexity: 2149 Second operand 5 states. [2018-11-23 16:06:15,296 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 16:06:15,297 INFO L93 Difference]: Finished difference Result 11929 states and 17122 transitions. [2018-11-23 16:06:15,298 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2018-11-23 16:06:15,298 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 11929 states and 17122 transitions. [2018-11-23 16:06:15,335 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 11700 [2018-11-23 16:06:15,410 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 11929 states to 11929 states and 17122 transitions. [2018-11-23 16:06:15,410 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 11929 [2018-11-23 16:06:15,415 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 11929 [2018-11-23 16:06:15,415 INFO L73 IsDeterministic]: Start isDeterministic. Operand 11929 states and 17122 transitions. [2018-11-23 16:06:15,423 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-23 16:06:15,423 INFO L705 BuchiCegarLoop]: Abstraction has 11929 states and 17122 transitions. [2018-11-23 16:06:15,430 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 11929 states and 17122 transitions. [2018-11-23 16:06:15,489 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 11929 to 5203. [2018-11-23 16:06:15,490 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 5203 states. [2018-11-23 16:06:15,498 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 5203 states to 5203 states and 7344 transitions. [2018-11-23 16:06:15,498 INFO L728 BuchiCegarLoop]: Abstraction has 5203 states and 7344 transitions. [2018-11-23 16:06:15,498 INFO L608 BuchiCegarLoop]: Abstraction has 5203 states and 7344 transitions. [2018-11-23 16:06:15,498 INFO L442 BuchiCegarLoop]: ======== Iteration 16============ [2018-11-23 16:06:15,498 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 5203 states and 7344 transitions. [2018-11-23 16:06:15,510 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 5080 [2018-11-23 16:06:15,510 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-23 16:06:15,510 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-23 16:06:15,511 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 16:06:15,512 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 16:06:15,512 INFO L794 eck$LassoCheckResult]: Stem: 66201#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; 66106#L-1 havoc main_#res;havoc main_~__retres1~9;havoc main_~__retres1~9;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 66107#L1143 havoc start_simulation_#t~ret20, start_simulation_#t~ret21, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 66080#L531 assume 1 == ~m_i~0;~m_st~0 := 0; 66081#L538-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 66387#L543-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 66290#L548-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 66082#L553-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 66083#L558-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 66458#L563-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 66276#L568-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 66065#L573-1 assume !(0 == ~M_E~0); 66066#L771-1 assume !(0 == ~T1_E~0); 65923#L776-1 assume !(0 == ~T2_E~0); 65924#L781-1 assume !(0 == ~T3_E~0); 66344#L786-1 assume !(0 == ~T4_E~0); 66151#L791-1 assume !(0 == ~T5_E~0); 65862#L796-1 assume !(0 == ~T6_E~0); 65863#L801-1 assume !(0 == ~T7_E~0); 66545#L806-1 assume !(0 == ~E_M~0); 66234#L811-1 assume !(0 == ~E_1~0); 66011#L816-1 assume !(0 == ~E_2~0); 66012#L821-1 assume !(0 == ~E_3~0); 66588#L826-1 assume !(0 == ~E_4~0); 66424#L831-1 assume !(0 == ~E_5~0); 66222#L836-1 assume !(0 == ~E_6~0); 65772#L841-1 assume !(0 == ~E_7~0); 65773#L846-1 havoc activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 65846#L378 assume !(1 == ~m_pc~0); 65820#L378-2 is_master_triggered_~__retres1~0 := 0; 65821#L389 is_master_triggered_#res := is_master_triggered_~__retres1~0; 66394#L390 activate_threads_#t~ret11 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 66439#L957 assume !(0 != activate_threads_~tmp~1); 66626#L957-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 66049#L397 assume !(1 == ~t1_pc~0); 65966#L397-2 is_transmit1_triggered_~__retres1~1 := 0; 66054#L408 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 66443#L409 activate_threads_#t~ret12 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 66237#L965 assume !(0 != activate_threads_~tmp___0~0); 66228#L965-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 66229#L416 assume !(1 == ~t2_pc~0); 66127#L416-2 is_transmit2_triggered_~__retres1~2 := 0; 66166#L427 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 66562#L428 activate_threads_#t~ret13 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 65792#L973 assume !(0 != activate_threads_~tmp___1~0); 65793#L973-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 65798#L435 assume !(1 == ~t3_pc~0); 66416#L435-2 is_transmit3_triggered_~__retres1~3 := 0; 65887#L446 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 65888#L447 activate_threads_#t~ret14 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 66479#L981 assume !(0 != activate_threads_~tmp___2~0); 66468#L981-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 66469#L454 assume !(1 == ~t4_pc~0); 66532#L454-2 is_transmit4_triggered_~__retres1~4 := 0; 66086#L465 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 65840#L466 activate_threads_#t~ret15 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 65841#L989 assume !(0 != activate_threads_~tmp___3~0); 66155#L989-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 66158#L473 assume !(1 == ~t5_pc~0); 66526#L473-2 is_transmit5_triggered_~__retres1~5 := 0; 66207#L484 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 66208#L485 activate_threads_#t~ret16 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 66663#L997 assume !(0 != activate_threads_~tmp___4~0); 66656#L997-2 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 66657#L492 assume !(1 == ~t6_pc~0); 66683#L492-2 is_transmit6_triggered_~__retres1~6 := 0; 66326#L503 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 66291#L504 activate_threads_#t~ret17 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 66292#L1005 assume !(0 != activate_threads_~tmp___5~0); 66529#L1005-2 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 65761#L511 assume !(1 == ~t7_pc~0); 65762#L511-2 is_transmit7_triggered_~__retres1~7 := 0; 65917#L522 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 66341#L523 activate_threads_#t~ret18 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 66199#L1013 assume !(0 != activate_threads_~tmp___6~0); 66192#L1013-2 assume !(1 == ~M_E~0); 66193#L859-1 assume !(1 == ~T1_E~0); 65936#L864-1 assume !(1 == ~T2_E~0); 65937#L869-1 assume !(1 == ~T3_E~0); 66342#L874-1 assume !(1 == ~T4_E~0); 66144#L879-1 assume !(1 == ~T5_E~0); 65858#L884-1 assume !(1 == ~T6_E~0); 65859#L889-1 assume !(1 == ~T7_E~0); 66542#L894-1 assume !(1 == ~E_M~0); 66230#L899-1 assume !(1 == ~E_1~0); 66004#L904-1 assume !(1 == ~E_2~0); 66005#L909-1 assume !(1 == ~E_3~0); 66600#L914-1 assume !(1 == ~E_4~0); 66426#L919-1 assume !(1 == ~E_5~0); 66227#L924-1 assume !(1 == ~E_6~0); 65801#L929-1 assume !(1 == ~E_7~0); 65802#L1180-1 [2018-11-23 16:06:15,512 INFO L796 eck$LassoCheckResult]: Loop: 65802#L1180-1 assume !false; 70604#L1181 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret2, eval_#t~nondet3, eval_~tmp_ndt_1~0, eval_#t~nondet4, eval_~tmp_ndt_2~0, eval_#t~nondet5, eval_~tmp_ndt_3~0, eval_#t~nondet6, eval_~tmp_ndt_4~0, eval_#t~nondet7, eval_~tmp_ndt_5~0, eval_#t~nondet8, eval_~tmp_ndt_6~0, eval_#t~nondet9, eval_~tmp_ndt_7~0, eval_#t~nondet10, eval_~tmp_ndt_8~0, eval_~tmp~0;havoc eval_~tmp~0; 70600#L746 assume !false; 70599#L639 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~8;havoc exists_runnable_thread_~__retres1~8; 66541#L586 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8 := 1; 65853#L628 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; 66466#L629 eval_#t~ret2 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret2;havoc eval_#t~ret2; 65747#L643 assume !(0 != eval_~tmp~0); 65749#L761 start_simulation_~kernel_st~0 := 2; 70845#L531-1 start_simulation_~kernel_st~0 := 3; 70844#L771-2 assume 0 == ~M_E~0;~M_E~0 := 1; 70843#L771-4 assume !(0 == ~T1_E~0); 70842#L776-3 assume !(0 == ~T2_E~0); 70841#L781-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 70840#L786-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 70839#L791-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 70838#L796-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 70837#L801-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 70836#L806-3 assume 0 == ~E_M~0;~E_M~0 := 1; 70835#L811-3 assume !(0 == ~E_1~0); 70833#L816-3 assume !(0 == ~E_2~0); 70831#L821-3 assume 0 == ~E_3~0;~E_3~0 := 1; 70824#L826-3 assume 0 == ~E_4~0;~E_4~0 := 1; 70823#L831-3 assume 0 == ~E_5~0;~E_5~0 := 1; 70822#L836-3 assume 0 == ~E_6~0;~E_6~0 := 1; 70821#L841-3 assume 0 == ~E_7~0;~E_7~0 := 1; 70820#L846-3 havoc activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 70819#L378-27 assume 1 == ~m_pc~0; 70817#L379-9 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 70816#L389-9 is_master_triggered_#res := is_master_triggered_~__retres1~0; 70815#L390-9 activate_threads_#t~ret11 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 70814#L957-27 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 70813#L957-29 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 70812#L397-27 assume !(1 == ~t1_pc~0); 70810#L397-29 is_transmit1_triggered_~__retres1~1 := 0; 70809#L408-9 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 70808#L409-9 activate_threads_#t~ret12 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 70807#L965-27 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 70806#L965-29 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 70805#L416-27 assume !(1 == ~t2_pc~0); 70803#L416-29 is_transmit2_triggered_~__retres1~2 := 0; 70802#L427-9 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 70801#L428-9 activate_threads_#t~ret13 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 70800#L973-27 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 70799#L973-29 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 70798#L435-27 assume !(1 == ~t3_pc~0); 70797#L435-29 is_transmit3_triggered_~__retres1~3 := 0; 70796#L446-9 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 70795#L447-9 activate_threads_#t~ret14 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 70794#L981-27 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 70793#L981-29 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 70792#L454-27 assume !(1 == ~t4_pc~0); 70791#L454-29 is_transmit4_triggered_~__retres1~4 := 0; 70790#L465-9 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 70789#L466-9 activate_threads_#t~ret15 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 70788#L989-27 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 70787#L989-29 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 70786#L473-27 assume !(1 == ~t5_pc~0); 70785#L473-29 is_transmit5_triggered_~__retres1~5 := 0; 70783#L484-9 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 70781#L485-9 activate_threads_#t~ret16 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 70779#L997-27 assume !(0 != activate_threads_~tmp___4~0); 70777#L997-29 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 70776#L492-27 assume !(1 == ~t6_pc~0); 70775#L492-29 is_transmit6_triggered_~__retres1~6 := 0; 70774#L503-9 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 70773#L504-9 activate_threads_#t~ret17 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 70772#L1005-27 assume !(0 != activate_threads_~tmp___5~0); 70771#L1005-29 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 70770#L511-27 assume !(1 == ~t7_pc~0); 70729#L511-29 is_transmit7_triggered_~__retres1~7 := 0; 70726#L522-9 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 70724#L523-9 activate_threads_#t~ret18 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 70722#L1013-27 assume 0 != activate_threads_~tmp___6~0;~t7_st~0 := 0; 70720#L1013-29 assume 1 == ~M_E~0;~M_E~0 := 2; 70717#L859-3 assume !(1 == ~T1_E~0); 70715#L864-3 assume !(1 == ~T2_E~0); 70713#L869-3 assume !(1 == ~T3_E~0); 70711#L874-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 70709#L879-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 70707#L884-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 70705#L889-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 70703#L894-3 assume 1 == ~E_M~0;~E_M~0 := 2; 70701#L899-3 assume !(1 == ~E_1~0); 70699#L904-3 assume !(1 == ~E_2~0); 70697#L909-3 assume !(1 == ~E_3~0); 70695#L914-3 assume 1 == ~E_4~0;~E_4~0 := 2; 70693#L919-3 assume 1 == ~E_5~0;~E_5~0 := 2; 70691#L924-3 assume 1 == ~E_6~0;~E_6~0 := 2; 70689#L929-3 assume 1 == ~E_7~0;~E_7~0 := 2; 70687#L934-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~8;havoc exists_runnable_thread_~__retres1~8; 70685#L586-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8 := 1; 70676#L628-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; 70674#L629-1 start_simulation_#t~ret20 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret20;havoc start_simulation_#t~ret20; 70672#L1199 assume !(0 == start_simulation_~tmp~3); 70671#L1199-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret19, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~8;havoc exists_runnable_thread_~__retres1~8; 70667#L586-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8 := 1; 70658#L628-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; 70656#L629-2 stop_simulation_#t~ret19 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret19;havoc stop_simulation_#t~ret19; 70653#L1154 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 70630#L1161 stop_simulation_#res := stop_simulation_~__retres2~0; 70613#L1162 start_simulation_#t~ret21 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret21;havoc start_simulation_#t~ret21; 70610#L1212 assume !(0 != start_simulation_~tmp___0~1); 65802#L1180-1 [2018-11-23 16:06:15,512 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 16:06:15,512 INFO L82 PathProgramCache]: Analyzing trace with hash 322056993, now seen corresponding path program 1 times [2018-11-23 16:06:15,512 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 16:06:15,513 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 16:06:15,513 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 16:06:15,513 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 16:06:15,513 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 16:06:15,518 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-23 16:06:15,523 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-23 16:06:15,560 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 16:06:15,560 INFO L82 PathProgramCache]: Analyzing trace with hash -76139633, now seen corresponding path program 1 times [2018-11-23 16:06:15,561 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 16:06:15,561 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 16:06:15,561 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 16:06:15,561 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 16:06:15,561 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 16:06:15,565 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 16:06:15,584 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 16:06:15,584 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 16:06:15,584 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-23 16:06:15,585 INFO L811 eck$LassoCheckResult]: loop already infeasible [2018-11-23 16:06:15,585 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-23 16:06:15,585 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-23 16:06:15,585 INFO L87 Difference]: Start difference. First operand 5203 states and 7344 transitions. cyclomatic complexity: 2149 Second operand 3 states. [2018-11-23 16:06:15,619 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 16:06:15,619 INFO L93 Difference]: Finished difference Result 5863 states and 8271 transitions. [2018-11-23 16:06:15,619 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-23 16:06:15,620 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 5863 states and 8271 transitions. [2018-11-23 16:06:15,636 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 5668 [2018-11-23 16:06:15,652 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 5863 states to 5863 states and 8271 transitions. [2018-11-23 16:06:15,652 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 5863 [2018-11-23 16:06:15,655 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 5863 [2018-11-23 16:06:15,655 INFO L73 IsDeterministic]: Start isDeterministic. Operand 5863 states and 8271 transitions. [2018-11-23 16:06:15,659 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-23 16:06:15,659 INFO L705 BuchiCegarLoop]: Abstraction has 5863 states and 8271 transitions. [2018-11-23 16:06:15,663 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 5863 states and 8271 transitions. [2018-11-23 16:06:15,702 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 5863 to 5863. [2018-11-23 16:06:15,702 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 5863 states. [2018-11-23 16:06:15,710 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 5863 states to 5863 states and 8271 transitions. [2018-11-23 16:06:15,711 INFO L728 BuchiCegarLoop]: Abstraction has 5863 states and 8271 transitions. [2018-11-23 16:06:15,711 INFO L608 BuchiCegarLoop]: Abstraction has 5863 states and 8271 transitions. [2018-11-23 16:06:15,711 INFO L442 BuchiCegarLoop]: ======== Iteration 17============ [2018-11-23 16:06:15,711 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 5863 states and 8271 transitions. [2018-11-23 16:06:15,723 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 5668 [2018-11-23 16:06:15,723 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-23 16:06:15,723 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-23 16:06:15,724 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 16:06:15,724 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 16:06:15,724 INFO L794 eck$LassoCheckResult]: Stem: 77290#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; 77187#L-1 havoc main_#res;havoc main_~__retres1~9;havoc main_~__retres1~9;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 77188#L1143 havoc start_simulation_#t~ret20, start_simulation_#t~ret21, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 77160#L531 assume 1 == ~m_i~0;~m_st~0 := 0; 77161#L538-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 77465#L543-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 77363#L548-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 77162#L553-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 77163#L558-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 77542#L563-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 77354#L568-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 77146#L573-1 assume !(0 == ~M_E~0); 77147#L771-1 assume !(0 == ~T1_E~0); 77001#L776-1 assume !(0 == ~T2_E~0); 77002#L781-1 assume 0 == ~T3_E~0;~T3_E~0 := 1; 77421#L786-1 assume !(0 == ~T4_E~0); 77422#L791-1 assume !(0 == ~T5_E~0); 77818#L796-1 assume !(0 == ~T6_E~0); 77817#L801-1 assume !(0 == ~T7_E~0); 77816#L806-1 assume !(0 == ~E_M~0); 77319#L811-1 assume !(0 == ~E_1~0); 77320#L816-1 assume !(0 == ~E_2~0); 77745#L821-1 assume !(0 == ~E_3~0); 77746#L826-1 assume !(0 == ~E_4~0); 77815#L831-1 assume !(0 == ~E_5~0); 77814#L836-1 assume !(0 == ~E_6~0); 77813#L841-1 assume !(0 == ~E_7~0); 77666#L846-1 havoc activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 76921#L378 assume !(1 == ~m_pc~0); 76895#L378-2 is_master_triggered_~__retres1~0 := 0; 76896#L389 is_master_triggered_#res := is_master_triggered_~__retres1~0; 77473#L390 activate_threads_#t~ret11 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 77716#L957 assume !(0 != activate_threads_~tmp~1); 77717#L957-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 77808#L397 assume !(1 == ~t1_pc~0); 77806#L397-2 is_transmit1_triggered_~__retres1~1 := 0; 77595#L408 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 77596#L409 activate_threads_#t~ret12 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 77323#L965 assume !(0 != activate_threads_~tmp___0~0); 77324#L965-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 77370#L416 assume !(1 == ~t2_pc~0); 77208#L416-2 is_transmit2_triggered_~__retres1~2 := 0; 77804#L427 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 77662#L428 activate_threads_#t~ret13 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 76866#L973 assume !(0 != activate_threads_~tmp___1~0); 76867#L973-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 76872#L435 assume !(1 == ~t3_pc~0); 77492#L435-2 is_transmit3_triggered_~__retres1~3 := 0; 77495#L446 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 77743#L447 activate_threads_#t~ret14 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 77744#L981 assume !(0 != activate_threads_~tmp___2~0); 77554#L981-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 77555#L454 assume !(1 == ~t4_pc~0); 77622#L454-2 is_transmit4_triggered_~__retres1~4 := 0; 77166#L465 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 76915#L466 activate_threads_#t~ret15 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 76916#L989 assume !(0 != activate_threads_~tmp___3~0); 77241#L989-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 77242#L473 assume !(1 == ~t5_pc~0); 77614#L473-2 is_transmit5_triggered_~__retres1~5 := 0; 77295#L484 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 77296#L485 activate_threads_#t~ret16 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 77790#L997 assume !(0 != activate_threads_~tmp___4~0); 77752#L997-2 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 77753#L492 assume !(1 == ~t6_pc~0); 77772#L492-2 is_transmit6_triggered_~__retres1~6 := 0; 77402#L503 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 77403#L504 activate_threads_#t~ret17 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 77616#L1005 assume !(0 != activate_threads_~tmp___5~0); 77617#L1005-2 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 77778#L511 assume !(1 == ~t7_pc~0); 76993#L511-2 is_transmit7_triggered_~__retres1~7 := 0; 76994#L522 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 77418#L523 activate_threads_#t~ret18 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 77499#L1013 assume !(0 != activate_threads_~tmp___6~0); 77775#L1013-2 assume !(1 == ~M_E~0); 77285#L859-1 assume !(1 == ~T1_E~0); 77013#L864-1 assume !(1 == ~T2_E~0); 77014#L869-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 77419#L874-1 assume !(1 == ~T4_E~0); 77224#L879-1 assume !(1 == ~T5_E~0); 76933#L884-1 assume !(1 == ~T6_E~0); 76934#L889-1 assume !(1 == ~T7_E~0); 77635#L894-1 assume !(1 == ~E_M~0); 77315#L899-1 assume !(1 == ~E_1~0); 77085#L904-1 assume !(1 == ~E_2~0); 77086#L909-1 assume !(1 == ~E_3~0); 77690#L914-1 assume !(1 == ~E_4~0); 77504#L919-1 assume !(1 == ~E_5~0); 77312#L924-1 assume !(1 == ~E_6~0); 76875#L929-1 assume !(1 == ~E_7~0); 76876#L1180-1 [2018-11-23 16:06:15,725 INFO L796 eck$LassoCheckResult]: Loop: 76876#L1180-1 assume !false; 79857#L1181 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret2, eval_#t~nondet3, eval_~tmp_ndt_1~0, eval_#t~nondet4, eval_~tmp_ndt_2~0, eval_#t~nondet5, eval_~tmp_ndt_3~0, eval_#t~nondet6, eval_~tmp_ndt_4~0, eval_#t~nondet7, eval_~tmp_ndt_5~0, eval_#t~nondet8, eval_~tmp_ndt_6~0, eval_#t~nondet9, eval_~tmp_ndt_7~0, eval_#t~nondet10, eval_~tmp_ndt_8~0, eval_~tmp~0;havoc eval_~tmp~0; 79852#L746 assume !false; 79850#L639 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~8;havoc exists_runnable_thread_~__retres1~8; 79836#L586 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8 := 1; 79828#L628 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; 79826#L629 eval_#t~ret2 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret2;havoc eval_#t~ret2; 79823#L643 assume !(0 != eval_~tmp~0); 79824#L761 start_simulation_~kernel_st~0 := 2; 80078#L531-1 start_simulation_~kernel_st~0 := 3; 80076#L771-2 assume 0 == ~M_E~0;~M_E~0 := 1; 80074#L771-4 assume !(0 == ~T1_E~0); 80072#L776-3 assume !(0 == ~T2_E~0); 80069#L781-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 80067#L786-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 80065#L791-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 80063#L796-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 80061#L801-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 80058#L806-3 assume 0 == ~E_M~0;~E_M~0 := 1; 80056#L811-3 assume !(0 == ~E_1~0); 80054#L816-3 assume !(0 == ~E_2~0); 80052#L821-3 assume 0 == ~E_3~0;~E_3~0 := 1; 80050#L826-3 assume 0 == ~E_4~0;~E_4~0 := 1; 80047#L831-3 assume 0 == ~E_5~0;~E_5~0 := 1; 80045#L836-3 assume 0 == ~E_6~0;~E_6~0 := 1; 80043#L841-3 assume 0 == ~E_7~0;~E_7~0 := 1; 80041#L846-3 havoc activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 80039#L378-27 assume !(1 == ~m_pc~0); 80037#L378-29 is_master_triggered_~__retres1~0 := 0; 80033#L389-9 is_master_triggered_#res := is_master_triggered_~__retres1~0; 80031#L390-9 activate_threads_#t~ret11 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 80029#L957-27 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 80027#L957-29 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 80025#L397-27 assume !(1 == ~t1_pc~0); 80022#L397-29 is_transmit1_triggered_~__retres1~1 := 0; 80020#L408-9 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 80018#L409-9 activate_threads_#t~ret12 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 80016#L965-27 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 80014#L965-29 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 80012#L416-27 assume !(1 == ~t2_pc~0); 80009#L416-29 is_transmit2_triggered_~__retres1~2 := 0; 80007#L427-9 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 80005#L428-9 activate_threads_#t~ret13 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 80003#L973-27 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 80001#L973-29 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 79999#L435-27 assume !(1 == ~t3_pc~0); 79997#L435-29 is_transmit3_triggered_~__retres1~3 := 0; 79993#L446-9 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 79991#L447-9 activate_threads_#t~ret14 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 79989#L981-27 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 79987#L981-29 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 79984#L454-27 assume !(1 == ~t4_pc~0); 79982#L454-29 is_transmit4_triggered_~__retres1~4 := 0; 79980#L465-9 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 79978#L466-9 activate_threads_#t~ret15 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 79976#L989-27 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 79974#L989-29 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 79972#L473-27 assume !(1 == ~t5_pc~0); 79968#L473-29 is_transmit5_triggered_~__retres1~5 := 0; 79966#L484-9 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 79963#L485-9 activate_threads_#t~ret16 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 79961#L997-27 assume !(0 != activate_threads_~tmp___4~0); 79958#L997-29 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 79956#L492-27 assume !(1 == ~t6_pc~0); 79954#L492-29 is_transmit6_triggered_~__retres1~6 := 0; 79952#L503-9 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 79950#L504-9 activate_threads_#t~ret17 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 79949#L1005-27 assume !(0 != activate_threads_~tmp___5~0); 79948#L1005-29 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 79947#L511-27 assume 1 == ~t7_pc~0; 79945#L512-9 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7 := 1; 79944#L522-9 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 79943#L523-9 activate_threads_#t~ret18 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 79942#L1013-27 assume 0 != activate_threads_~tmp___6~0;~t7_st~0 := 0; 79939#L1013-29 assume 1 == ~M_E~0;~M_E~0 := 2; 79938#L859-3 assume !(1 == ~T1_E~0); 79932#L864-3 assume !(1 == ~T2_E~0); 79930#L869-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 79927#L874-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 79925#L879-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 79922#L884-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 79920#L889-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 79918#L894-3 assume 1 == ~E_M~0;~E_M~0 := 2; 79916#L899-3 assume !(1 == ~E_1~0); 79914#L904-3 assume !(1 == ~E_2~0); 79912#L909-3 assume !(1 == ~E_3~0); 79909#L914-3 assume 1 == ~E_4~0;~E_4~0 := 2; 79907#L919-3 assume 1 == ~E_5~0;~E_5~0 := 2; 79905#L924-3 assume 1 == ~E_6~0;~E_6~0 := 2; 79903#L929-3 assume 1 == ~E_7~0;~E_7~0 := 2; 79901#L934-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~8;havoc exists_runnable_thread_~__retres1~8; 79898#L586-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8 := 1; 79889#L628-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; 79887#L629-1 start_simulation_#t~ret20 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret20;havoc start_simulation_#t~ret20; 79884#L1199 assume !(0 == start_simulation_~tmp~3); 79881#L1199-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret19, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~8;havoc exists_runnable_thread_~__retres1~8; 79879#L586-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8 := 1; 79870#L628-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; 79868#L629-2 stop_simulation_#t~ret19 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret19;havoc stop_simulation_#t~ret19; 79866#L1154 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 79864#L1161 stop_simulation_#res := stop_simulation_~__retres2~0; 79862#L1162 start_simulation_#t~ret21 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret21;havoc start_simulation_#t~ret21; 79860#L1212 assume !(0 != start_simulation_~tmp___0~1); 76876#L1180-1 [2018-11-23 16:06:15,725 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 16:06:15,725 INFO L82 PathProgramCache]: Analyzing trace with hash 881797405, now seen corresponding path program 1 times [2018-11-23 16:06:15,725 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 16:06:15,725 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 16:06:15,726 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 16:06:15,726 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 16:06:15,726 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 16:06:15,729 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 16:06:15,766 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 16:06:15,766 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 16:06:15,767 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2018-11-23 16:06:15,767 INFO L799 eck$LassoCheckResult]: stem already infeasible [2018-11-23 16:06:15,767 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 16:06:15,767 INFO L82 PathProgramCache]: Analyzing trace with hash 1569588881, now seen corresponding path program 1 times [2018-11-23 16:06:15,767 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 16:06:15,767 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 16:06:15,768 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 16:06:15,768 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 16:06:15,768 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 16:06:15,772 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 16:06:15,795 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 16:06:15,795 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 16:06:15,795 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-23 16:06:15,795 INFO L811 eck$LassoCheckResult]: loop already infeasible [2018-11-23 16:06:15,796 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-23 16:06:15,796 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-23 16:06:15,796 INFO L87 Difference]: Start difference. First operand 5863 states and 8271 transitions. cyclomatic complexity: 2416 Second operand 3 states. [2018-11-23 16:06:15,815 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 16:06:15,816 INFO L93 Difference]: Finished difference Result 5203 states and 7318 transitions. [2018-11-23 16:06:15,817 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-23 16:06:15,817 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 5203 states and 7318 transitions. [2018-11-23 16:06:15,827 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 5080 [2018-11-23 16:06:15,835 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 5203 states to 5203 states and 7318 transitions. [2018-11-23 16:06:15,835 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 5203 [2018-11-23 16:06:15,837 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 5203 [2018-11-23 16:06:15,837 INFO L73 IsDeterministic]: Start isDeterministic. Operand 5203 states and 7318 transitions. [2018-11-23 16:06:15,840 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-23 16:06:15,840 INFO L705 BuchiCegarLoop]: Abstraction has 5203 states and 7318 transitions. [2018-11-23 16:06:15,843 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 5203 states and 7318 transitions. [2018-11-23 16:06:15,866 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 5203 to 5203. [2018-11-23 16:06:15,866 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 5203 states. [2018-11-23 16:06:15,871 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 5203 states to 5203 states and 7318 transitions. [2018-11-23 16:06:15,871 INFO L728 BuchiCegarLoop]: Abstraction has 5203 states and 7318 transitions. [2018-11-23 16:06:15,871 INFO L608 BuchiCegarLoop]: Abstraction has 5203 states and 7318 transitions. [2018-11-23 16:06:15,871 INFO L442 BuchiCegarLoop]: ======== Iteration 18============ [2018-11-23 16:06:15,871 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 5203 states and 7318 transitions. [2018-11-23 16:06:15,880 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 5080 [2018-11-23 16:06:15,880 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-23 16:06:15,880 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-23 16:06:15,881 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 16:06:15,881 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 16:06:15,881 INFO L794 eck$LassoCheckResult]: Stem: 88349#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; 88250#L-1 havoc main_#res;havoc main_~__retres1~9;havoc main_~__retres1~9;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 88251#L1143 havoc start_simulation_#t~ret20, start_simulation_#t~ret21, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 88224#L531 assume 1 == ~m_i~0;~m_st~0 := 0; 88225#L538-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 88522#L543-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 88425#L548-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 88226#L553-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 88227#L558-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 88595#L563-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 88417#L568-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 88209#L573-1 assume !(0 == ~M_E~0); 88210#L771-1 assume !(0 == ~T1_E~0); 88069#L776-1 assume !(0 == ~T2_E~0); 88070#L781-1 assume !(0 == ~T3_E~0); 88481#L786-1 assume !(0 == ~T4_E~0); 88298#L791-1 assume !(0 == ~T5_E~0); 88008#L796-1 assume !(0 == ~T6_E~0); 88009#L801-1 assume !(0 == ~T7_E~0); 88682#L806-1 assume !(0 == ~E_M~0); 88376#L811-1 assume !(0 == ~E_1~0); 88157#L816-1 assume !(0 == ~E_2~0); 88158#L821-1 assume !(0 == ~E_3~0); 88727#L826-1 assume !(0 == ~E_4~0); 88560#L831-1 assume !(0 == ~E_5~0); 88364#L836-1 assume !(0 == ~E_6~0); 87918#L841-1 assume !(0 == ~E_7~0); 87919#L846-1 havoc activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 87992#L378 assume !(1 == ~m_pc~0); 87966#L378-2 is_master_triggered_~__retres1~0 := 0; 87967#L389 is_master_triggered_#res := is_master_triggered_~__retres1~0; 88529#L390 activate_threads_#t~ret11 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 88575#L957 assume !(0 != activate_threads_~tmp~1); 88749#L957-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 88193#L397 assume !(1 == ~t1_pc~0); 88112#L397-2 is_transmit1_triggered_~__retres1~1 := 0; 88198#L408 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 88579#L409 activate_threads_#t~ret12 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 88379#L965 assume !(0 != activate_threads_~tmp___0~0); 88370#L965-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 88371#L416 assume !(1 == ~t2_pc~0); 88271#L416-2 is_transmit2_triggered_~__retres1~2 := 0; 88314#L427 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 88703#L428 activate_threads_#t~ret13 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 87938#L973 assume !(0 != activate_threads_~tmp___1~0); 87939#L973-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 87944#L435 assume !(1 == ~t3_pc~0); 88551#L435-2 is_transmit3_triggered_~__retres1~3 := 0; 88033#L446 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 88034#L447 activate_threads_#t~ret14 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 88620#L981 assume !(0 != activate_threads_~tmp___2~0); 88607#L981-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 88608#L454 assume !(1 == ~t4_pc~0); 88673#L454-2 is_transmit4_triggered_~__retres1~4 := 0; 88230#L465 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 87986#L466 activate_threads_#t~ret15 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 87987#L989 assume !(0 != activate_threads_~tmp___3~0); 88302#L989-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 88305#L473 assume !(1 == ~t5_pc~0); 88666#L473-2 is_transmit5_triggered_~__retres1~5 := 0; 88354#L484 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 88212#L485 activate_threads_#t~ret16 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 88213#L997 assume !(0 != activate_threads_~tmp___4~0); 88774#L997-2 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 88775#L492 assume !(1 == ~t6_pc~0); 88798#L492-2 is_transmit6_triggered_~__retres1~6 := 0; 88464#L503 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 88426#L504 activate_threads_#t~ret17 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 88427#L1005 assume !(0 != activate_threads_~tmp___5~0); 88668#L1005-2 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 87907#L511 assume !(1 == ~t7_pc~0); 87908#L511-2 is_transmit7_triggered_~__retres1~7 := 0; 88063#L522 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 88478#L523 activate_threads_#t~ret18 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 88347#L1013 assume !(0 != activate_threads_~tmp___6~0); 88340#L1013-2 assume !(1 == ~M_E~0); 88341#L859-1 assume !(1 == ~T1_E~0); 88082#L864-1 assume !(1 == ~T2_E~0); 88083#L869-1 assume !(1 == ~T3_E~0); 88479#L874-1 assume !(1 == ~T4_E~0); 88291#L879-1 assume !(1 == ~T5_E~0); 88004#L884-1 assume !(1 == ~T6_E~0); 88005#L889-1 assume !(1 == ~T7_E~0); 88679#L894-1 assume !(1 == ~E_M~0); 88372#L899-1 assume !(1 == ~E_1~0); 88149#L904-1 assume !(1 == ~E_2~0); 88150#L909-1 assume !(1 == ~E_3~0); 88731#L914-1 assume !(1 == ~E_4~0); 88562#L919-1 assume !(1 == ~E_5~0); 88369#L924-1 assume !(1 == ~E_6~0); 87947#L929-1 assume !(1 == ~E_7~0); 87948#L1180-1 [2018-11-23 16:06:15,881 INFO L796 eck$LassoCheckResult]: Loop: 87948#L1180-1 assume !false; 88670#L1181 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret2, eval_#t~nondet3, eval_~tmp_ndt_1~0, eval_#t~nondet4, eval_~tmp_ndt_2~0, eval_#t~nondet5, eval_~tmp_ndt_3~0, eval_#t~nondet6, eval_~tmp_ndt_4~0, eval_#t~nondet7, eval_~tmp_ndt_5~0, eval_#t~nondet8, eval_~tmp_ndt_6~0, eval_#t~nondet9, eval_~tmp_ndt_7~0, eval_#t~nondet10, eval_~tmp_ndt_8~0, eval_~tmp~0;havoc eval_~tmp~0; 88073#L746 assume !false; 88337#L639 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~8;havoc exists_runnable_thread_~__retres1~8; 88338#L586 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8 := 1; 87999#L628 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; 88604#L629 eval_#t~ret2 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret2;havoc eval_#t~ret2; 87892#L643 assume !(0 != eval_~tmp~0); 87894#L761 start_simulation_~kernel_st~0 := 2; 92940#L531-1 start_simulation_~kernel_st~0 := 3; 92939#L771-2 assume 0 == ~M_E~0;~M_E~0 := 1; 92938#L771-4 assume !(0 == ~T1_E~0); 92937#L776-3 assume !(0 == ~T2_E~0); 92936#L781-3 assume !(0 == ~T3_E~0); 92934#L786-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 92933#L791-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 92932#L796-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 92931#L801-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 92930#L806-3 assume 0 == ~E_M~0;~E_M~0 := 1; 92873#L811-3 assume !(0 == ~E_1~0); 88139#L816-3 assume !(0 == ~E_2~0); 88140#L821-3 assume 0 == ~E_3~0;~E_3~0 := 1; 88728#L826-3 assume 0 == ~E_4~0;~E_4~0 := 1; 88561#L831-3 assume 0 == ~E_5~0;~E_5~0 := 1; 88365#L836-3 assume 0 == ~E_6~0;~E_6~0 := 1; 87928#L841-3 assume 0 == ~E_7~0;~E_7~0 := 1; 87929#L846-3 havoc activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 87910#L378-27 assume 1 == ~m_pc~0; 87911#L379-9 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 88087#L389-9 is_master_triggered_#res := is_master_triggered_~__retres1~0; 88493#L390-9 activate_threads_#t~ret11 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 88565#L957-27 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 88736#L957-29 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 88128#L397-27 assume !(1 == ~t1_pc~0); 88129#L397-29 is_transmit1_triggered_~__retres1~1 := 0; 88131#L408-9 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 92706#L409-9 activate_threads_#t~ret12 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 92705#L965-27 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 92704#L965-29 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 88289#L416-27 assume !(1 == ~t2_pc~0); 88243#L416-29 is_transmit2_triggered_~__retres1~2 := 0; 88267#L427-9 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 88692#L428-9 activate_threads_#t~ret13 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 88088#L973-27 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 88089#L973-29 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 88095#L435-27 assume !(1 == ~t3_pc~0); 88415#L435-29 is_transmit3_triggered_~__retres1~3 := 0; 92992#L446-9 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 92990#L447-9 activate_threads_#t~ret14 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 92987#L981-27 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 92986#L981-29 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 92985#L454-27 assume !(1 == ~t4_pc~0); 92984#L454-29 is_transmit4_triggered_~__retres1~4 := 0; 92983#L465-9 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 92982#L466-9 activate_threads_#t~ret15 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 92981#L989-27 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 92980#L989-29 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 92979#L473-27 assume !(1 == ~t5_pc~0); 92977#L473-29 is_transmit5_triggered_~__retres1~5 := 0; 92975#L484-9 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 92973#L485-9 activate_threads_#t~ret16 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 92972#L997-27 assume !(0 != activate_threads_~tmp___4~0); 92970#L997-29 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 92969#L492-27 assume !(1 == ~t6_pc~0); 92968#L492-29 is_transmit6_triggered_~__retres1~6 := 0; 92966#L503-9 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 92964#L504-9 activate_threads_#t~ret17 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 92962#L1005-27 assume !(0 != activate_threads_~tmp___5~0); 92960#L1005-29 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 92957#L511-27 assume !(1 == ~t7_pc~0); 92955#L511-29 is_transmit7_triggered_~__retres1~7 := 0; 92953#L522-9 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 92952#L523-9 activate_threads_#t~ret18 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 92951#L1013-27 assume 0 != activate_threads_~tmp___6~0;~t7_st~0 := 0; 92950#L1013-29 assume 1 == ~M_E~0;~M_E~0 := 2; 92949#L859-3 assume !(1 == ~T1_E~0); 92947#L864-3 assume !(1 == ~T2_E~0); 92944#L869-3 assume !(1 == ~T3_E~0); 92943#L874-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 92942#L879-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 92941#L884-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 88791#L889-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 88680#L894-3 assume 1 == ~E_M~0;~E_M~0 := 2; 88681#L899-3 assume !(1 == ~E_1~0); 92678#L904-3 assume !(1 == ~E_2~0); 92677#L909-3 assume !(1 == ~E_3~0); 92676#L914-3 assume 1 == ~E_4~0;~E_4~0 := 2; 92621#L919-3 assume 1 == ~E_5~0;~E_5~0 := 2; 88363#L924-3 assume 1 == ~E_6~0;~E_6~0 := 2; 87916#L929-3 assume 1 == ~E_7~0;~E_7~0 := 2; 87917#L934-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~8;havoc exists_runnable_thread_~__retres1~8; 88675#L586-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8 := 1; 88003#L628-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; 88589#L629-1 start_simulation_#t~ret20 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret20;havoc start_simulation_#t~ret20; 88590#L1199 assume !(0 == start_simulation_~tmp~3); 88495#L1199-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret19, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~8;havoc exists_runnable_thread_~__retres1~8; 88676#L586-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8 := 1; 87981#L628-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; 88593#L629-2 stop_simulation_#t~ret19 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret19;havoc stop_simulation_#t~ret19; 88594#L1154 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 88563#L1161 stop_simulation_#res := stop_simulation_~__retres2~0; 88549#L1162 start_simulation_#t~ret21 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret21;havoc start_simulation_#t~ret21; 88179#L1212 assume !(0 != start_simulation_~tmp___0~1); 87948#L1180-1 [2018-11-23 16:06:15,881 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 16:06:15,882 INFO L82 PathProgramCache]: Analyzing trace with hash 322056993, now seen corresponding path program 2 times [2018-11-23 16:06:15,882 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 16:06:15,882 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 16:06:15,882 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 16:06:15,882 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 16:06:15,882 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 16:06:15,887 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-23 16:06:15,891 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-23 16:06:15,910 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 16:06:15,910 INFO L82 PathProgramCache]: Analyzing trace with hash 1800923597, now seen corresponding path program 1 times [2018-11-23 16:06:15,910 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 16:06:15,910 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 16:06:15,911 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 16:06:15,911 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-23 16:06:15,911 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 16:06:15,915 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 16:06:15,938 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 16:06:15,938 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 16:06:15,939 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-23 16:06:15,939 INFO L811 eck$LassoCheckResult]: loop already infeasible [2018-11-23 16:06:15,939 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-23 16:06:15,939 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-23 16:06:15,939 INFO L87 Difference]: Start difference. First operand 5203 states and 7318 transitions. cyclomatic complexity: 2123 Second operand 3 states. [2018-11-23 16:06:16,000 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 16:06:16,000 INFO L93 Difference]: Finished difference Result 7777 states and 10878 transitions. [2018-11-23 16:06:16,001 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-23 16:06:16,001 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 7777 states and 10878 transitions. [2018-11-23 16:06:16,017 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 7574 [2018-11-23 16:06:16,029 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 7777 states to 7777 states and 10878 transitions. [2018-11-23 16:06:16,029 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 7777 [2018-11-23 16:06:16,033 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 7777 [2018-11-23 16:06:16,033 INFO L73 IsDeterministic]: Start isDeterministic. Operand 7777 states and 10878 transitions. [2018-11-23 16:06:16,036 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-23 16:06:16,036 INFO L705 BuchiCegarLoop]: Abstraction has 7777 states and 10878 transitions. [2018-11-23 16:06:16,040 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 7777 states and 10878 transitions. [2018-11-23 16:06:16,076 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 7777 to 7773. [2018-11-23 16:06:16,076 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 7773 states. [2018-11-23 16:06:16,083 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 7773 states to 7773 states and 10874 transitions. [2018-11-23 16:06:16,083 INFO L728 BuchiCegarLoop]: Abstraction has 7773 states and 10874 transitions. [2018-11-23 16:06:16,083 INFO L608 BuchiCegarLoop]: Abstraction has 7773 states and 10874 transitions. [2018-11-23 16:06:16,083 INFO L442 BuchiCegarLoop]: ======== Iteration 19============ [2018-11-23 16:06:16,083 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 7773 states and 10874 transitions. [2018-11-23 16:06:16,096 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 7570 [2018-11-23 16:06:16,096 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-23 16:06:16,096 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-23 16:06:16,097 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 16:06:16,097 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 16:06:16,097 INFO L794 eck$LassoCheckResult]: Stem: 101344#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; 101244#L-1 havoc main_#res;havoc main_~__retres1~9;havoc main_~__retres1~9;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 101245#L1143 havoc start_simulation_#t~ret20, start_simulation_#t~ret21, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 101218#L531 assume 1 == ~m_i~0;~m_st~0 := 0; 101219#L538-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 101524#L543-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 101421#L548-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 101220#L553-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 101221#L558-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 101604#L563-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 101403#L568-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 101203#L573-1 assume !(0 == ~M_E~0); 101204#L771-1 assume !(0 == ~T1_E~0); 101060#L776-1 assume !(0 == ~T2_E~0); 101061#L781-1 assume !(0 == ~T3_E~0); 101477#L786-1 assume !(0 == ~T4_E~0); 101288#L791-1 assume !(0 == ~T5_E~0); 100997#L796-1 assume !(0 == ~T6_E~0); 100998#L801-1 assume !(0 == ~T7_E~0); 101692#L806-1 assume !(0 == ~E_M~0); 101373#L811-1 assume !(0 == ~E_1~0); 101149#L816-1 assume !(0 == ~E_2~0); 101150#L821-1 assume 0 == ~E_3~0;~E_3~0 := 1; 101788#L826-1 assume !(0 == ~E_4~0); 101852#L831-1 assume !(0 == ~E_5~0); 101360#L836-1 assume !(0 == ~E_6~0); 101361#L841-1 assume !(0 == ~E_7~0); 101715#L846-1 havoc activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 100980#L378 assume !(1 == ~m_pc~0); 100981#L378-2 is_master_triggered_~__retres1~0 := 0; 101850#L389 is_master_triggered_#res := is_master_triggered_~__retres1~0; 101583#L390 activate_threads_#t~ret11 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 101584#L957 assume !(0 != activate_threads_~tmp~1); 101766#L957-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 101767#L397 assume !(1 == ~t1_pc~0); 101191#L397-2 is_transmit1_triggered_~__retres1~1 := 0; 101192#L408 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 101588#L409 activate_threads_#t~ret12 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 101589#L965 assume !(0 != activate_threads_~tmp___0~0); 101367#L965-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 101368#L416 assume !(1 == ~t2_pc~0); 101305#L416-2 is_transmit2_triggered_~__retres1~2 := 0; 101306#L427 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 101711#L428 activate_threads_#t~ret13 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 100928#L973 assume !(0 != activate_threads_~tmp___1~0); 100929#L973-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 100933#L435 assume !(1 == ~t3_pc~0); 101555#L435-2 is_transmit3_triggered_~__retres1~3 := 0; 101558#L446 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 101786#L447 activate_threads_#t~ret14 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 101787#L981 assume !(0 != activate_threads_~tmp___2~0); 101614#L981-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 101615#L454 assume !(1 == ~t4_pc~0); 101682#L454-2 is_transmit4_triggered_~__retres1~4 := 0; 101224#L465 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 100974#L466 activate_threads_#t~ret15 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 100975#L989 assume !(0 != activate_threads_~tmp___3~0); 101296#L989-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 101297#L473 assume !(1 == ~t5_pc~0); 101673#L473-2 is_transmit5_triggered_~__retres1~5 := 0; 101841#L484 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 101838#L485 activate_threads_#t~ret16 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 101835#L997 assume !(0 != activate_threads_~tmp___4~0); 101794#L997-2 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 101795#L492 assume !(1 == ~t6_pc~0); 101820#L492-2 is_transmit6_triggered_~__retres1~6 := 0; 101459#L503 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 101460#L504 activate_threads_#t~ret17 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 101676#L1005 assume !(0 != activate_threads_~tmp___5~0); 101677#L1005-2 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 101831#L511 assume !(1 == ~t7_pc~0); 101053#L511-2 is_transmit7_triggered_~__retres1~7 := 0; 101054#L522 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 101473#L523 activate_threads_#t~ret18 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 101563#L1013 assume !(0 != activate_threads_~tmp___6~0); 101333#L1013-2 assume !(1 == ~M_E~0); 101334#L859-1 assume !(1 == ~T1_E~0); 101828#L864-1 assume !(1 == ~T2_E~0); 101760#L869-1 assume !(1 == ~T3_E~0); 101474#L874-1 assume !(1 == ~T4_E~0); 101475#L879-1 assume !(1 == ~T5_E~0); 101826#L884-1 assume !(1 == ~T6_E~0); 101812#L889-1 assume !(1 == ~T7_E~0); 101690#L894-1 assume !(1 == ~E_M~0); 101371#L899-1 assume !(1 == ~E_1~0); 101142#L904-1 assume !(1 == ~E_2~0); 101143#L909-1 assume 1 == ~E_3~0;~E_3~0 := 2; 101744#L914-1 assume !(1 == ~E_4~0); 101569#L919-1 assume !(1 == ~E_5~0); 101366#L924-1 assume !(1 == ~E_6~0); 100934#L929-1 assume !(1 == ~E_7~0); 100935#L1180-1 [2018-11-23 16:06:16,098 INFO L796 eck$LassoCheckResult]: Loop: 100935#L1180-1 assume !false; 103841#L1181 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret2, eval_#t~nondet3, eval_~tmp_ndt_1~0, eval_#t~nondet4, eval_~tmp_ndt_2~0, eval_#t~nondet5, eval_~tmp_ndt_3~0, eval_#t~nondet6, eval_~tmp_ndt_4~0, eval_#t~nondet7, eval_~tmp_ndt_5~0, eval_#t~nondet8, eval_~tmp_ndt_6~0, eval_#t~nondet9, eval_~tmp_ndt_7~0, eval_#t~nondet10, eval_~tmp_ndt_8~0, eval_~tmp~0;havoc eval_~tmp~0; 103836#L746 assume !false; 103833#L639 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~8;havoc exists_runnable_thread_~__retres1~8; 103825#L586 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8 := 1; 103818#L628 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; 103817#L629 eval_#t~ret2 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret2;havoc eval_#t~ret2; 103815#L643 assume !(0 != eval_~tmp~0); 103816#L761 start_simulation_~kernel_st~0 := 2; 106446#L531-1 start_simulation_~kernel_st~0 := 3; 106444#L771-2 assume 0 == ~M_E~0;~M_E~0 := 1; 106442#L771-4 assume !(0 == ~T1_E~0); 106440#L776-3 assume !(0 == ~T2_E~0); 106438#L781-3 assume !(0 == ~T3_E~0); 106435#L786-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 106433#L791-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 106431#L796-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 106429#L801-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 106427#L806-3 assume 0 == ~E_M~0;~E_M~0 := 1; 106424#L811-3 assume !(0 == ~E_1~0); 106422#L816-3 assume !(0 == ~E_2~0); 106419#L821-3 assume 0 == ~E_3~0;~E_3~0 := 1; 106417#L826-3 assume 0 == ~E_4~0;~E_4~0 := 1; 106415#L831-3 assume 0 == ~E_5~0;~E_5~0 := 1; 106413#L836-3 assume 0 == ~E_6~0;~E_6~0 := 1; 106410#L841-3 assume 0 == ~E_7~0;~E_7~0 := 1; 106408#L846-3 havoc activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 106406#L378-27 assume 1 == ~m_pc~0; 106403#L379-9 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 106401#L389-9 is_master_triggered_#res := is_master_triggered_~__retres1~0; 106399#L390-9 activate_threads_#t~ret11 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 106397#L957-27 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 106395#L957-29 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 106393#L397-27 assume !(1 == ~t1_pc~0); 106390#L397-29 is_transmit1_triggered_~__retres1~1 := 0; 106388#L408-9 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 106386#L409-9 activate_threads_#t~ret12 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 106384#L965-27 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 106382#L965-29 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 103996#L416-27 assume !(1 == ~t2_pc~0); 103993#L416-29 is_transmit2_triggered_~__retres1~2 := 0; 103991#L427-9 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 103989#L428-9 activate_threads_#t~ret13 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 103985#L973-27 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 103983#L973-29 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 103981#L435-27 assume !(1 == ~t3_pc~0); 103979#L435-29 is_transmit3_triggered_~__retres1~3 := 0; 103976#L446-9 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 103974#L447-9 activate_threads_#t~ret14 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 103972#L981-27 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 103970#L981-29 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 103968#L454-27 assume !(1 == ~t4_pc~0); 103966#L454-29 is_transmit4_triggered_~__retres1~4 := 0; 103964#L465-9 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 103962#L466-9 activate_threads_#t~ret15 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 103960#L989-27 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 103959#L989-29 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 103956#L473-27 assume !(1 == ~t5_pc~0); 103952#L473-29 is_transmit5_triggered_~__retres1~5 := 0; 103950#L484-9 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 103948#L485-9 activate_threads_#t~ret16 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 103946#L997-27 assume !(0 != activate_threads_~tmp___4~0); 103943#L997-29 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 103941#L492-27 assume !(1 == ~t6_pc~0); 103939#L492-29 is_transmit6_triggered_~__retres1~6 := 0; 103937#L503-9 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 103935#L504-9 activate_threads_#t~ret17 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 103933#L1005-27 assume !(0 != activate_threads_~tmp___5~0); 103931#L1005-29 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 103929#L511-27 assume !(1 == ~t7_pc~0); 103927#L511-29 is_transmit7_triggered_~__retres1~7 := 0; 103924#L522-9 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 103923#L523-9 activate_threads_#t~ret18 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 103922#L1013-27 assume 0 != activate_threads_~tmp___6~0;~t7_st~0 := 0; 103919#L1013-29 assume 1 == ~M_E~0;~M_E~0 := 2; 103917#L859-3 assume !(1 == ~T1_E~0); 103915#L864-3 assume !(1 == ~T2_E~0); 103913#L869-3 assume !(1 == ~T3_E~0); 103911#L874-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 103909#L879-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 103907#L884-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 103905#L889-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 103903#L894-3 assume 1 == ~E_M~0;~E_M~0 := 2; 103901#L899-3 assume !(1 == ~E_1~0); 103899#L904-3 assume !(1 == ~E_2~0); 103897#L909-3 assume 1 == ~E_3~0;~E_3~0 := 2; 103894#L914-3 assume 1 == ~E_4~0;~E_4~0 := 2; 103892#L919-3 assume 1 == ~E_5~0;~E_5~0 := 2; 103890#L924-3 assume 1 == ~E_6~0;~E_6~0 := 2; 103888#L929-3 assume 1 == ~E_7~0;~E_7~0 := 2; 103886#L934-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~8;havoc exists_runnable_thread_~__retres1~8; 103884#L586-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8 := 1; 103876#L628-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; 103872#L629-1 start_simulation_#t~ret20 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret20;havoc start_simulation_#t~ret20; 103869#L1199 assume !(0 == start_simulation_~tmp~3); 103866#L1199-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret19, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~8;havoc exists_runnable_thread_~__retres1~8; 103864#L586-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8 := 1; 103854#L628-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; 103852#L629-2 stop_simulation_#t~ret19 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret19;havoc stop_simulation_#t~ret19; 103850#L1154 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 103848#L1161 stop_simulation_#res := stop_simulation_~__retres2~0; 103846#L1162 start_simulation_#t~ret21 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret21;havoc start_simulation_#t~ret21; 103844#L1212 assume !(0 != start_simulation_~tmp___0~1); 100935#L1180-1 [2018-11-23 16:06:16,098 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 16:06:16,098 INFO L82 PathProgramCache]: Analyzing trace with hash 812836125, now seen corresponding path program 1 times [2018-11-23 16:06:16,098 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 16:06:16,098 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 16:06:16,099 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 16:06:16,099 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 16:06:16,099 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 16:06:16,103 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 16:06:16,124 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 16:06:16,124 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 16:06:16,124 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2018-11-23 16:06:16,124 INFO L799 eck$LassoCheckResult]: stem already infeasible [2018-11-23 16:06:16,125 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 16:06:16,125 INFO L82 PathProgramCache]: Analyzing trace with hash -499898993, now seen corresponding path program 1 times [2018-11-23 16:06:16,125 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 16:06:16,125 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 16:06:16,126 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 16:06:16,126 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 16:06:16,126 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 16:06:16,131 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 16:06:16,157 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 16:06:16,157 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 16:06:16,158 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-11-23 16:06:16,158 INFO L811 eck$LassoCheckResult]: loop already infeasible [2018-11-23 16:06:16,158 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-23 16:06:16,158 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-23 16:06:16,158 INFO L87 Difference]: Start difference. First operand 7773 states and 10874 transitions. cyclomatic complexity: 3109 Second operand 3 states. [2018-11-23 16:06:16,199 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 16:06:16,200 INFO L93 Difference]: Finished difference Result 5203 states and 7256 transitions. [2018-11-23 16:06:16,201 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-23 16:06:16,201 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 5203 states and 7256 transitions. [2018-11-23 16:06:16,213 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 5080 [2018-11-23 16:06:16,222 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 5203 states to 5203 states and 7256 transitions. [2018-11-23 16:06:16,222 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 5203 [2018-11-23 16:06:16,225 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 5203 [2018-11-23 16:06:16,225 INFO L73 IsDeterministic]: Start isDeterministic. Operand 5203 states and 7256 transitions. [2018-11-23 16:06:16,229 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-23 16:06:16,230 INFO L705 BuchiCegarLoop]: Abstraction has 5203 states and 7256 transitions. [2018-11-23 16:06:16,232 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 5203 states and 7256 transitions. [2018-11-23 16:06:16,298 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 5203 to 5203. [2018-11-23 16:06:16,298 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 5203 states. [2018-11-23 16:06:16,303 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 5203 states to 5203 states and 7256 transitions. [2018-11-23 16:06:16,303 INFO L728 BuchiCegarLoop]: Abstraction has 5203 states and 7256 transitions. [2018-11-23 16:06:16,303 INFO L608 BuchiCegarLoop]: Abstraction has 5203 states and 7256 transitions. [2018-11-23 16:06:16,303 INFO L442 BuchiCegarLoop]: ======== Iteration 20============ [2018-11-23 16:06:16,304 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 5203 states and 7256 transitions. [2018-11-23 16:06:16,312 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 5080 [2018-11-23 16:06:16,312 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-23 16:06:16,312 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-23 16:06:16,313 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 16:06:16,313 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 16:06:16,313 INFO L794 eck$LassoCheckResult]: Stem: 114320#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; 114225#L-1 havoc main_#res;havoc main_~__retres1~9;havoc main_~__retres1~9;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 114226#L1143 havoc start_simulation_#t~ret20, start_simulation_#t~ret21, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 114199#L531 assume 1 == ~m_i~0;~m_st~0 := 0; 114200#L538-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 114482#L543-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 114387#L548-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 114201#L553-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 114202#L558-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 114552#L563-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 114380#L568-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 114183#L573-1 assume !(0 == ~M_E~0); 114184#L771-1 assume !(0 == ~T1_E~0); 114039#L776-1 assume !(0 == ~T2_E~0); 114040#L781-1 assume !(0 == ~T3_E~0); 114439#L786-1 assume !(0 == ~T4_E~0); 114270#L791-1 assume !(0 == ~T5_E~0); 113978#L796-1 assume !(0 == ~T6_E~0); 113979#L801-1 assume !(0 == ~T7_E~0); 114632#L806-1 assume !(0 == ~E_M~0); 114348#L811-1 assume !(0 == ~E_1~0); 114130#L816-1 assume !(0 == ~E_2~0); 114131#L821-1 assume !(0 == ~E_3~0); 114676#L826-1 assume !(0 == ~E_4~0); 114517#L831-1 assume !(0 == ~E_5~0); 114335#L836-1 assume !(0 == ~E_6~0); 113888#L841-1 assume !(0 == ~E_7~0); 113889#L846-1 havoc activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 113962#L378 assume !(1 == ~m_pc~0); 113936#L378-2 is_master_triggered_~__retres1~0 := 0; 113937#L389 is_master_triggered_#res := is_master_triggered_~__retres1~0; 114487#L390 activate_threads_#t~ret11 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 114533#L957 assume !(0 != activate_threads_~tmp~1); 114700#L957-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 114167#L397 assume !(1 == ~t1_pc~0); 114085#L397-2 is_transmit1_triggered_~__retres1~1 := 0; 114172#L408 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 114537#L409 activate_threads_#t~ret12 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 114351#L965 assume !(0 != activate_threads_~tmp___0~0); 114342#L965-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 114343#L416 assume !(1 == ~t2_pc~0); 114246#L416-2 is_transmit2_triggered_~__retres1~2 := 0; 114285#L427 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 114651#L428 activate_threads_#t~ret13 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 113908#L973 assume !(0 != activate_threads_~tmp___1~0); 113909#L973-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 113914#L435 assume !(1 == ~t3_pc~0); 114509#L435-2 is_transmit3_triggered_~__retres1~3 := 0; 114003#L446 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 114004#L447 activate_threads_#t~ret14 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 114572#L981 assume !(0 != activate_threads_~tmp___2~0); 114562#L981-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 114563#L454 assume !(1 == ~t4_pc~0); 114624#L454-2 is_transmit4_triggered_~__retres1~4 := 0; 114205#L465 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 113956#L466 activate_threads_#t~ret15 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 113957#L989 assume !(0 != activate_threads_~tmp___3~0); 114274#L989-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 114277#L473 assume !(1 == ~t5_pc~0); 114616#L473-2 is_transmit5_triggered_~__retres1~5 := 0; 114325#L484 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 114186#L485 activate_threads_#t~ret16 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 114187#L997 assume !(0 != activate_threads_~tmp___4~0); 114725#L997-2 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 114726#L492 assume !(1 == ~t6_pc~0); 114751#L492-2 is_transmit6_triggered_~__retres1~6 := 0; 114423#L503 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 114388#L504 activate_threads_#t~ret17 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 114389#L1005 assume !(0 != activate_threads_~tmp___5~0); 114618#L1005-2 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 113877#L511 assume !(1 == ~t7_pc~0); 113878#L511-2 is_transmit7_triggered_~__retres1~7 := 0; 114033#L522 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 114436#L523 activate_threads_#t~ret18 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 114318#L1013 assume !(0 != activate_threads_~tmp___6~0); 114311#L1013-2 assume !(1 == ~M_E~0); 114312#L859-1 assume !(1 == ~T1_E~0); 114053#L864-1 assume !(1 == ~T2_E~0); 114054#L869-1 assume !(1 == ~T3_E~0); 114437#L874-1 assume !(1 == ~T4_E~0); 114263#L879-1 assume !(1 == ~T5_E~0); 113974#L884-1 assume !(1 == ~T6_E~0); 113975#L889-1 assume !(1 == ~T7_E~0); 114630#L894-1 assume !(1 == ~E_M~0); 114344#L899-1 assume !(1 == ~E_1~0); 114123#L904-1 assume !(1 == ~E_2~0); 114124#L909-1 assume !(1 == ~E_3~0); 114680#L914-1 assume !(1 == ~E_4~0); 114519#L919-1 assume !(1 == ~E_5~0); 114341#L924-1 assume !(1 == ~E_6~0); 113917#L929-1 assume !(1 == ~E_7~0); 113918#L1180-1 [2018-11-23 16:06:16,313 INFO L796 eck$LassoCheckResult]: Loop: 113918#L1180-1 assume !false; 116029#L1181 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret2, eval_#t~nondet3, eval_~tmp_ndt_1~0, eval_#t~nondet4, eval_~tmp_ndt_2~0, eval_#t~nondet5, eval_~tmp_ndt_3~0, eval_#t~nondet6, eval_~tmp_ndt_4~0, eval_#t~nondet7, eval_~tmp_ndt_5~0, eval_#t~nondet8, eval_~tmp_ndt_6~0, eval_#t~nondet9, eval_~tmp_ndt_7~0, eval_#t~nondet10, eval_~tmp_ndt_8~0, eval_~tmp~0;havoc eval_~tmp~0; 116024#L746 assume !false; 116023#L639 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~8;havoc exists_runnable_thread_~__retres1~8; 116018#L586 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8 := 1; 116009#L628 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; 116007#L629 eval_#t~ret2 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret2;havoc eval_#t~ret2; 116004#L643 assume !(0 != eval_~tmp~0); 116005#L761 start_simulation_~kernel_st~0 := 2; 116227#L531-1 start_simulation_~kernel_st~0 := 3; 116225#L771-2 assume 0 == ~M_E~0;~M_E~0 := 1; 116223#L771-4 assume !(0 == ~T1_E~0); 116221#L776-3 assume !(0 == ~T2_E~0); 116219#L781-3 assume !(0 == ~T3_E~0); 116217#L786-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 116215#L791-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 116213#L796-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 116211#L801-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 116209#L806-3 assume 0 == ~E_M~0;~E_M~0 := 1; 116207#L811-3 assume !(0 == ~E_1~0); 116205#L816-3 assume !(0 == ~E_2~0); 116203#L821-3 assume !(0 == ~E_3~0); 116201#L826-3 assume 0 == ~E_4~0;~E_4~0 := 1; 116199#L831-3 assume 0 == ~E_5~0;~E_5~0 := 1; 116197#L836-3 assume 0 == ~E_6~0;~E_6~0 := 1; 116196#L841-3 assume 0 == ~E_7~0;~E_7~0 := 1; 116195#L846-3 havoc activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 116194#L378-27 assume !(1 == ~m_pc~0); 116193#L378-29 is_master_triggered_~__retres1~0 := 0; 116191#L389-9 is_master_triggered_#res := is_master_triggered_~__retres1~0; 116190#L390-9 activate_threads_#t~ret11 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 116189#L957-27 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 116188#L957-29 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 116187#L397-27 assume !(1 == ~t1_pc~0); 116185#L397-29 is_transmit1_triggered_~__retres1~1 := 0; 116184#L408-9 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 116183#L409-9 activate_threads_#t~ret12 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 116181#L965-27 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 116180#L965-29 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 116179#L416-27 assume !(1 == ~t2_pc~0); 116177#L416-29 is_transmit2_triggered_~__retres1~2 := 0; 116176#L427-9 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 116174#L428-9 activate_threads_#t~ret13 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 116173#L973-27 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 116172#L973-29 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 116171#L435-27 assume !(1 == ~t3_pc~0); 116170#L435-29 is_transmit3_triggered_~__retres1~3 := 0; 116169#L446-9 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 116168#L447-9 activate_threads_#t~ret14 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 116166#L981-27 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 116163#L981-29 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 116161#L454-27 assume !(1 == ~t4_pc~0); 116159#L454-29 is_transmit4_triggered_~__retres1~4 := 0; 116157#L465-9 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 116155#L466-9 activate_threads_#t~ret15 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 116152#L989-27 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 116150#L989-29 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 116148#L473-27 assume !(1 == ~t5_pc~0); 116144#L473-29 is_transmit5_triggered_~__retres1~5 := 0; 116142#L484-9 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 116140#L485-9 activate_threads_#t~ret16 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 116137#L997-27 assume !(0 != activate_threads_~tmp___4~0); 116134#L997-29 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 116132#L492-27 assume !(1 == ~t6_pc~0); 116130#L492-29 is_transmit6_triggered_~__retres1~6 := 0; 116128#L503-9 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 116126#L504-9 activate_threads_#t~ret17 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 116124#L1005-27 assume !(0 != activate_threads_~tmp___5~0); 116122#L1005-29 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 116120#L511-27 assume 1 == ~t7_pc~0; 116117#L512-9 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7 := 1; 116115#L522-9 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 116113#L523-9 activate_threads_#t~ret18 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 116111#L1013-27 assume 0 != activate_threads_~tmp___6~0;~t7_st~0 := 0; 116109#L1013-29 assume 1 == ~M_E~0;~M_E~0 := 2; 116107#L859-3 assume !(1 == ~T1_E~0); 116105#L864-3 assume !(1 == ~T2_E~0); 116103#L869-3 assume !(1 == ~T3_E~0); 116101#L874-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 116100#L879-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 116096#L884-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 116094#L889-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 116092#L894-3 assume 1 == ~E_M~0;~E_M~0 := 2; 116090#L899-3 assume !(1 == ~E_1~0); 116087#L904-3 assume !(1 == ~E_2~0); 116085#L909-3 assume !(1 == ~E_3~0); 116083#L914-3 assume 1 == ~E_4~0;~E_4~0 := 2; 116081#L919-3 assume 1 == ~E_5~0;~E_5~0 := 2; 116079#L924-3 assume 1 == ~E_6~0;~E_6~0 := 2; 116077#L929-3 assume 1 == ~E_7~0;~E_7~0 := 2; 116075#L934-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~8;havoc exists_runnable_thread_~__retres1~8; 116073#L586-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8 := 1; 116064#L628-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; 116061#L629-1 start_simulation_#t~ret20 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret20;havoc start_simulation_#t~ret20; 116058#L1199 assume !(0 == start_simulation_~tmp~3); 116055#L1199-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret19, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~8;havoc exists_runnable_thread_~__retres1~8; 116053#L586-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8 := 1; 116045#L628-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; 116041#L629-2 stop_simulation_#t~ret19 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret19;havoc stop_simulation_#t~ret19; 116039#L1154 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 116038#L1161 stop_simulation_#res := stop_simulation_~__retres2~0; 116037#L1162 start_simulation_#t~ret21 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret21;havoc start_simulation_#t~ret21; 116033#L1212 assume !(0 != start_simulation_~tmp___0~1); 113918#L1180-1 [2018-11-23 16:06:16,314 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 16:06:16,314 INFO L82 PathProgramCache]: Analyzing trace with hash 322056993, now seen corresponding path program 3 times [2018-11-23 16:06:16,314 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 16:06:16,314 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 16:06:16,314 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 16:06:16,314 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 16:06:16,315 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 16:06:16,319 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-23 16:06:16,323 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-23 16:06:16,340 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 16:06:16,340 INFO L82 PathProgramCache]: Analyzing trace with hash 780482379, now seen corresponding path program 1 times [2018-11-23 16:06:16,341 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 16:06:16,341 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 16:06:16,341 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 16:06:16,341 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-23 16:06:16,341 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 16:06:16,346 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 16:06:16,373 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 16:06:16,373 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 16:06:16,373 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-11-23 16:06:16,374 INFO L811 eck$LassoCheckResult]: loop already infeasible [2018-11-23 16:06:16,374 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-11-23 16:06:16,374 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-11-23 16:06:16,374 INFO L87 Difference]: Start difference. First operand 5203 states and 7256 transitions. cyclomatic complexity: 2061 Second operand 5 states. [2018-11-23 16:06:16,455 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 16:06:16,455 INFO L93 Difference]: Finished difference Result 9487 states and 13112 transitions. [2018-11-23 16:06:16,457 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2018-11-23 16:06:16,457 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 9487 states and 13112 transitions. [2018-11-23 16:06:16,476 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 9340 [2018-11-23 16:06:16,489 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 9487 states to 9487 states and 13112 transitions. [2018-11-23 16:06:16,489 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 9487 [2018-11-23 16:06:16,494 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 9487 [2018-11-23 16:06:16,494 INFO L73 IsDeterministic]: Start isDeterministic. Operand 9487 states and 13112 transitions. [2018-11-23 16:06:16,498 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-23 16:06:16,498 INFO L705 BuchiCegarLoop]: Abstraction has 9487 states and 13112 transitions. [2018-11-23 16:06:16,502 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 9487 states and 13112 transitions. [2018-11-23 16:06:16,533 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 9487 to 5227. [2018-11-23 16:06:16,533 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 5227 states. [2018-11-23 16:06:16,538 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 5227 states to 5227 states and 7280 transitions. [2018-11-23 16:06:16,538 INFO L728 BuchiCegarLoop]: Abstraction has 5227 states and 7280 transitions. [2018-11-23 16:06:16,538 INFO L608 BuchiCegarLoop]: Abstraction has 5227 states and 7280 transitions. [2018-11-23 16:06:16,538 INFO L442 BuchiCegarLoop]: ======== Iteration 21============ [2018-11-23 16:06:16,538 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 5227 states and 7280 transitions. [2018-11-23 16:06:16,546 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 5104 [2018-11-23 16:06:16,546 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-23 16:06:16,546 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-23 16:06:16,547 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 16:06:16,547 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 16:06:16,547 INFO L794 eck$LassoCheckResult]: Stem: 129026#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; 128930#L-1 havoc main_#res;havoc main_~__retres1~9;havoc main_~__retres1~9;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 128931#L1143 havoc start_simulation_#t~ret20, start_simulation_#t~ret21, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 128905#L531 assume 1 == ~m_i~0;~m_st~0 := 0; 128906#L538-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 129198#L543-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 129097#L548-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 128907#L553-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 128908#L558-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 129271#L563-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 129087#L568-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 128890#L573-1 assume !(0 == ~M_E~0); 128891#L771-1 assume !(0 == ~T1_E~0); 128745#L776-1 assume !(0 == ~T2_E~0); 128746#L781-1 assume !(0 == ~T3_E~0); 129154#L786-1 assume !(0 == ~T4_E~0); 128975#L791-1 assume !(0 == ~T5_E~0); 128684#L796-1 assume !(0 == ~T6_E~0); 128685#L801-1 assume !(0 == ~T7_E~0); 129356#L806-1 assume !(0 == ~E_M~0); 129054#L811-1 assume !(0 == ~E_1~0); 128836#L816-1 assume !(0 == ~E_2~0); 128837#L821-1 assume !(0 == ~E_3~0); 129403#L826-1 assume !(0 == ~E_4~0); 129236#L831-1 assume !(0 == ~E_5~0); 129041#L836-1 assume !(0 == ~E_6~0); 128593#L841-1 assume !(0 == ~E_7~0); 128594#L846-1 havoc activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 128668#L378 assume !(1 == ~m_pc~0); 128642#L378-2 is_master_triggered_~__retres1~0 := 0; 128643#L389 is_master_triggered_#res := is_master_triggered_~__retres1~0; 129205#L390 activate_threads_#t~ret11 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 129252#L957 assume !(0 != activate_threads_~tmp~1); 129426#L957-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 128873#L397 assume !(1 == ~t1_pc~0); 128790#L397-2 is_transmit1_triggered_~__retres1~1 := 0; 128878#L408 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 129256#L409 activate_threads_#t~ret12 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 129057#L965 assume !(0 != activate_threads_~tmp___0~0); 129048#L965-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 129049#L416 assume !(1 == ~t2_pc~0); 128951#L416-2 is_transmit2_triggered_~__retres1~2 := 0; 128990#L427 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 129381#L428 activate_threads_#t~ret13 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 128614#L973 assume !(0 != activate_threads_~tmp___1~0); 128615#L973-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 128620#L435 assume !(1 == ~t3_pc~0); 129227#L435-2 is_transmit3_triggered_~__retres1~3 := 0; 128709#L446 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 128710#L447 activate_threads_#t~ret14 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 129293#L981 assume !(0 != activate_threads_~tmp___2~0); 129281#L981-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 129282#L454 assume !(1 == ~t4_pc~0); 129347#L454-2 is_transmit4_triggered_~__retres1~4 := 0; 128911#L465 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 128662#L466 activate_threads_#t~ret15 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 128663#L989 assume !(0 != activate_threads_~tmp___3~0); 128979#L989-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 128982#L473 assume !(1 == ~t5_pc~0); 129340#L473-2 is_transmit5_triggered_~__retres1~5 := 0; 129031#L484 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 128893#L485 activate_threads_#t~ret16 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 128894#L997 assume !(0 != activate_threads_~tmp___4~0); 129454#L997-2 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 129455#L492 assume !(1 == ~t6_pc~0); 129477#L492-2 is_transmit6_triggered_~__retres1~6 := 0; 129138#L503 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 129098#L504 activate_threads_#t~ret17 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 129099#L1005 assume !(0 != activate_threads_~tmp___5~0); 129342#L1005-2 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 128582#L511 assume !(1 == ~t7_pc~0); 128583#L511-2 is_transmit7_triggered_~__retres1~7 := 0; 128739#L522 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 129151#L523 activate_threads_#t~ret18 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 129024#L1013 assume !(0 != activate_threads_~tmp___6~0); 129017#L1013-2 assume !(1 == ~M_E~0); 129018#L859-1 assume !(1 == ~T1_E~0); 128758#L864-1 assume !(1 == ~T2_E~0); 128759#L869-1 assume !(1 == ~T3_E~0); 129152#L874-1 assume !(1 == ~T4_E~0); 128968#L879-1 assume !(1 == ~T5_E~0); 128680#L884-1 assume !(1 == ~T6_E~0); 128681#L889-1 assume !(1 == ~T7_E~0); 129354#L894-1 assume !(1 == ~E_M~0); 129050#L899-1 assume !(1 == ~E_1~0); 128828#L904-1 assume !(1 == ~E_2~0); 128829#L909-1 assume !(1 == ~E_3~0); 129406#L914-1 assume !(1 == ~E_4~0); 129240#L919-1 assume !(1 == ~E_5~0); 129047#L924-1 assume !(1 == ~E_6~0); 128623#L929-1 assume !(1 == ~E_7~0); 128624#L1180-1 [2018-11-23 16:06:16,548 INFO L796 eck$LassoCheckResult]: Loop: 128624#L1180-1 assume !false; 129344#L1181 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret2, eval_#t~nondet3, eval_~tmp_ndt_1~0, eval_#t~nondet4, eval_~tmp_ndt_2~0, eval_#t~nondet5, eval_~tmp_ndt_3~0, eval_#t~nondet6, eval_~tmp_ndt_4~0, eval_#t~nondet7, eval_~tmp_ndt_5~0, eval_#t~nondet8, eval_~tmp_ndt_6~0, eval_#t~nondet9, eval_~tmp_ndt_7~0, eval_#t~nondet10, eval_~tmp_ndt_8~0, eval_~tmp~0;havoc eval_~tmp~0; 128749#L746 assume !false; 129109#L639 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~8;havoc exists_runnable_thread_~__retres1~8; 132963#L586 assume !(0 == ~m_st~0); 132964#L590 assume !(0 == ~t1_st~0); 132959#L594 assume !(0 == ~t2_st~0); 132960#L598 assume !(0 == ~t3_st~0); 132962#L602 assume !(0 == ~t4_st~0); 132957#L606 assume !(0 == ~t5_st~0); 132958#L610 assume !(0 == ~t6_st~0); 132961#L614 assume !(0 == ~t7_st~0);exists_runnable_thread_~__retres1~8 := 0; 132965#L628 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; 131650#L629 eval_#t~ret2 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret2;havoc eval_#t~ret2; 131651#L643 assume !(0 != eval_~tmp~0); 132938#L761 start_simulation_~kernel_st~0 := 2; 132937#L531-1 start_simulation_~kernel_st~0 := 3; 132935#L771-2 assume 0 == ~M_E~0;~M_E~0 := 1; 132934#L771-4 assume !(0 == ~T1_E~0); 128751#L776-3 assume !(0 == ~T2_E~0); 128752#L781-3 assume !(0 == ~T3_E~0); 130373#L786-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 130374#L791-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 130367#L796-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 130368#L801-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 130361#L806-3 assume 0 == ~E_M~0;~E_M~0 := 1; 130362#L811-3 assume !(0 == ~E_1~0); 130355#L816-3 assume !(0 == ~E_2~0); 130356#L821-3 assume !(0 == ~E_3~0); 130349#L826-3 assume 0 == ~E_4~0;~E_4~0 := 1; 130350#L831-3 assume 0 == ~E_5~0;~E_5~0 := 1; 130342#L836-3 assume 0 == ~E_6~0;~E_6~0 := 1; 130343#L841-3 assume 0 == ~E_7~0;~E_7~0 := 1; 129604#L846-3 havoc activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 129605#L378-27 assume 1 == ~m_pc~0; 132928#L379-9 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 132927#L389-9 is_master_triggered_#res := is_master_triggered_~__retres1~0; 132926#L390-9 activate_threads_#t~ret11 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 129410#L957-27 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 129411#L957-29 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 128806#L397-27 assume !(1 == ~t1_pc~0); 128807#L397-29 is_transmit1_triggered_~__retres1~1 := 0; 128809#L408-9 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 129316#L409-9 activate_threads_#t~ret12 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 129363#L965-27 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 129112#L965-29 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 129113#L416-27 assume !(1 == ~t2_pc~0); 132686#L416-29 is_transmit2_triggered_~__retres1~2 := 0; 132685#L427-9 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 132684#L428-9 activate_threads_#t~ret13 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 128766#L973-27 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 128767#L973-29 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 128773#L435-27 assume !(1 == ~t3_pc~0); 132682#L435-29 is_transmit3_triggered_~__retres1~3 := 0; 132681#L446-9 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 132680#L447-9 activate_threads_#t~ret14 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 132679#L981-27 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 132678#L981-29 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 132677#L454-27 assume !(1 == ~t4_pc~0); 132676#L454-29 is_transmit4_triggered_~__retres1~4 := 0; 132675#L465-9 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 132674#L466-9 activate_threads_#t~ret15 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 132673#L989-27 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 132672#L989-29 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 132671#L473-27 assume !(1 == ~t5_pc~0); 132670#L473-29 is_transmit5_triggered_~__retres1~5 := 0; 132668#L484-9 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 132667#L485-9 activate_threads_#t~ret16 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 129440#L997-27 assume !(0 != activate_threads_~tmp___4~0); 129441#L997-29 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 129470#L492-27 assume !(1 == ~t6_pc~0); 129471#L492-29 is_transmit6_triggered_~__retres1~6 := 0; 133604#L503-9 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 133603#L504-9 activate_threads_#t~ret17 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 133602#L1005-27 assume !(0 != activate_threads_~tmp___5~0); 133601#L1005-29 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 133600#L511-27 assume 1 == ~t7_pc~0; 133598#L512-9 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7 := 1; 133597#L522-9 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 133596#L523-9 activate_threads_#t~ret18 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 133595#L1013-27 assume 0 != activate_threads_~tmp___6~0;~t7_st~0 := 0; 133594#L1013-29 assume 1 == ~M_E~0;~M_E~0 := 2; 133593#L859-3 assume !(1 == ~T1_E~0); 133592#L864-3 assume !(1 == ~T2_E~0); 133591#L869-3 assume !(1 == ~T3_E~0); 133590#L874-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 133589#L879-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 133588#L884-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 133587#L889-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 133586#L894-3 assume 1 == ~E_M~0;~E_M~0 := 2; 133585#L899-3 assume !(1 == ~E_1~0); 133584#L904-3 assume !(1 == ~E_2~0); 133583#L909-3 assume !(1 == ~E_3~0); 133582#L914-3 assume 1 == ~E_4~0;~E_4~0 := 2; 133581#L919-3 assume 1 == ~E_5~0;~E_5~0 := 2; 133580#L924-3 assume 1 == ~E_6~0;~E_6~0 := 2; 133579#L929-3 assume 1 == ~E_7~0;~E_7~0 := 2; 133578#L934-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~8;havoc exists_runnable_thread_~__retres1~8; 133425#L586-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8 := 1; 133417#L628-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; 133416#L629-1 start_simulation_#t~ret20 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret20;havoc start_simulation_#t~ret20; 133414#L1199 assume !(0 == start_simulation_~tmp~3); 133412#L1199-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret19, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~8;havoc exists_runnable_thread_~__retres1~8; 129351#L586-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8 := 1; 128657#L628-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; 129269#L629-2 stop_simulation_#t~ret19 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret19;havoc stop_simulation_#t~ret19; 129270#L1154 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 129241#L1161 stop_simulation_#res := stop_simulation_~__retres2~0; 129225#L1162 start_simulation_#t~ret21 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret21;havoc start_simulation_#t~ret21; 128858#L1212 assume !(0 != start_simulation_~tmp___0~1); 128624#L1180-1 [2018-11-23 16:06:16,548 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 16:06:16,548 INFO L82 PathProgramCache]: Analyzing trace with hash 322056993, now seen corresponding path program 4 times [2018-11-23 16:06:16,548 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 16:06:16,548 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 16:06:16,549 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 16:06:16,549 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 16:06:16,549 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 16:06:16,553 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-23 16:06:16,558 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-23 16:06:16,575 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 16:06:16,576 INFO L82 PathProgramCache]: Analyzing trace with hash 711279776, now seen corresponding path program 1 times [2018-11-23 16:06:16,576 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 16:06:16,576 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 16:06:16,576 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 16:06:16,576 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-23 16:06:16,577 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 16:06:16,582 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 16:06:16,656 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 16:06:16,656 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 16:06:16,656 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-11-23 16:06:16,657 INFO L811 eck$LassoCheckResult]: loop already infeasible [2018-11-23 16:06:16,657 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-11-23 16:06:16,657 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-11-23 16:06:16,657 INFO L87 Difference]: Start difference. First operand 5227 states and 7280 transitions. cyclomatic complexity: 2061 Second operand 5 states. [2018-11-23 16:06:16,770 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 16:06:16,770 INFO L93 Difference]: Finished difference Result 7847 states and 11091 transitions. [2018-11-23 16:06:16,770 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2018-11-23 16:06:16,770 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 7847 states and 11091 transitions. [2018-11-23 16:06:16,787 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 7676 [2018-11-23 16:06:16,798 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 7847 states to 7847 states and 11091 transitions. [2018-11-23 16:06:16,798 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 7847 [2018-11-23 16:06:16,802 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 7847 [2018-11-23 16:06:16,802 INFO L73 IsDeterministic]: Start isDeterministic. Operand 7847 states and 11091 transitions. [2018-11-23 16:06:16,806 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-23 16:06:16,806 INFO L705 BuchiCegarLoop]: Abstraction has 7847 states and 11091 transitions. [2018-11-23 16:06:16,809 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 7847 states and 11091 transitions. [2018-11-23 16:06:16,836 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 7847 to 5251. [2018-11-23 16:06:16,836 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 5251 states. [2018-11-23 16:06:16,840 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 5251 states to 5251 states and 7243 transitions. [2018-11-23 16:06:16,841 INFO L728 BuchiCegarLoop]: Abstraction has 5251 states and 7243 transitions. [2018-11-23 16:06:16,841 INFO L608 BuchiCegarLoop]: Abstraction has 5251 states and 7243 transitions. [2018-11-23 16:06:16,841 INFO L442 BuchiCegarLoop]: ======== Iteration 22============ [2018-11-23 16:06:16,841 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 5251 states and 7243 transitions. [2018-11-23 16:06:16,849 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 5128 [2018-11-23 16:06:16,849 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-23 16:06:16,850 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-23 16:06:16,850 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 16:06:16,850 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 16:06:16,851 INFO L794 eck$LassoCheckResult]: Stem: 142140#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; 142039#L-1 havoc main_#res;havoc main_~__retres1~9;havoc main_~__retres1~9;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 142040#L1143 havoc start_simulation_#t~ret20, start_simulation_#t~ret21, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 142013#L531 assume 1 == ~m_i~0;~m_st~0 := 0; 142014#L538-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 142332#L543-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 142217#L548-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 142015#L553-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 142016#L558-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 142417#L563-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 142205#L568-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 141994#L573-1 assume !(0 == ~M_E~0); 141995#L771-1 assume !(0 == ~T1_E~0); 141834#L776-1 assume !(0 == ~T2_E~0); 141835#L781-1 assume !(0 == ~T3_E~0); 142281#L786-1 assume !(0 == ~T4_E~0); 142088#L791-1 assume !(0 == ~T5_E~0); 141773#L796-1 assume !(0 == ~T6_E~0); 141774#L801-1 assume !(0 == ~T7_E~0); 142506#L806-1 assume !(0 == ~E_M~0); 142170#L811-1 assume !(0 == ~E_1~0); 141933#L816-1 assume !(0 == ~E_2~0); 141934#L821-1 assume !(0 == ~E_3~0); 142564#L826-1 assume !(0 == ~E_4~0); 142375#L831-1 assume !(0 == ~E_5~0); 142158#L836-1 assume !(0 == ~E_6~0); 141681#L841-1 assume !(0 == ~E_7~0); 141682#L846-1 havoc activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 141757#L378 assume !(1 == ~m_pc~0); 141731#L378-2 is_master_triggered_~__retres1~0 := 0; 141732#L389 is_master_triggered_#res := is_master_triggered_~__retres1~0; 142341#L390 activate_threads_#t~ret11 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 142393#L957 assume !(0 != activate_threads_~tmp~1); 142595#L957-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 141973#L397 assume !(1 == ~t1_pc~0); 141886#L397-2 is_transmit1_triggered_~__retres1~1 := 0; 141980#L408 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 142399#L409 activate_threads_#t~ret12 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 142173#L965 assume !(0 != activate_threads_~tmp___0~0); 142164#L965-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 142165#L416 assume !(1 == ~t2_pc~0); 142062#L416-2 is_transmit2_triggered_~__retres1~2 := 0; 142103#L427 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 142532#L428 activate_threads_#t~ret13 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 141702#L973 assume !(0 != activate_threads_~tmp___1~0); 141703#L973-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 141708#L435 assume !(1 == ~t3_pc~0); 142367#L435-2 is_transmit3_triggered_~__retres1~3 := 0; 141798#L446 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 141799#L447 activate_threads_#t~ret14 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 142442#L981 assume !(0 != activate_threads_~tmp___2~0); 142430#L981-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 142431#L454 assume !(1 == ~t4_pc~0); 142496#L454-2 is_transmit4_triggered_~__retres1~4 := 0; 142019#L465 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 141751#L466 activate_threads_#t~ret15 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 141752#L989 assume !(0 != activate_threads_~tmp___3~0); 142092#L989-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 142095#L473 assume !(1 == ~t5_pc~0); 142489#L473-2 is_transmit5_triggered_~__retres1~5 := 0; 142145#L484 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 141997#L485 activate_threads_#t~ret16 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 141998#L997 assume !(0 != activate_threads_~tmp___4~0); 142626#L997-2 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 142627#L492 assume !(1 == ~t6_pc~0); 142659#L492-2 is_transmit6_triggered_~__retres1~6 := 0; 142264#L503 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 142218#L504 activate_threads_#t~ret17 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 142219#L1005 assume !(0 != activate_threads_~tmp___5~0); 142492#L1005-2 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 141670#L511 assume !(1 == ~t7_pc~0); 141671#L511-2 is_transmit7_triggered_~__retres1~7 := 0; 141828#L522 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 142278#L523 activate_threads_#t~ret18 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 142137#L1013 assume !(0 != activate_threads_~tmp___6~0); 142129#L1013-2 assume !(1 == ~M_E~0); 142130#L859-1 assume !(1 == ~T1_E~0); 141853#L864-1 assume !(1 == ~T2_E~0); 141854#L869-1 assume !(1 == ~T3_E~0); 142279#L874-1 assume !(1 == ~T4_E~0); 142080#L879-1 assume !(1 == ~T5_E~0); 141769#L884-1 assume !(1 == ~T6_E~0); 141770#L889-1 assume !(1 == ~T7_E~0); 142504#L894-1 assume !(1 == ~E_M~0); 142166#L899-1 assume !(1 == ~E_1~0); 141926#L904-1 assume !(1 == ~E_2~0); 141927#L909-1 assume !(1 == ~E_3~0); 142574#L914-1 assume !(1 == ~E_4~0); 142378#L919-1 assume !(1 == ~E_5~0); 142163#L924-1 assume !(1 == ~E_6~0); 141711#L929-1 assume !(1 == ~E_7~0); 141712#L1180-1 [2018-11-23 16:06:16,851 INFO L796 eck$LassoCheckResult]: Loop: 141712#L1180-1 assume !false; 146591#L1181 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret2, eval_#t~nondet3, eval_~tmp_ndt_1~0, eval_#t~nondet4, eval_~tmp_ndt_2~0, eval_#t~nondet5, eval_~tmp_ndt_3~0, eval_#t~nondet6, eval_~tmp_ndt_4~0, eval_#t~nondet7, eval_~tmp_ndt_5~0, eval_#t~nondet8, eval_~tmp_ndt_6~0, eval_#t~nondet9, eval_~tmp_ndt_7~0, eval_#t~nondet10, eval_~tmp_ndt_8~0, eval_~tmp~0;havoc eval_~tmp~0; 145935#L746 assume !false; 146714#L639 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~8;havoc exists_runnable_thread_~__retres1~8; 146711#L586 assume !(0 == ~m_st~0); 146709#L590 assume !(0 == ~t1_st~0); 146707#L594 assume !(0 == ~t2_st~0); 146705#L598 assume !(0 == ~t3_st~0); 146703#L602 assume !(0 == ~t4_st~0); 146702#L606 assume !(0 == ~t5_st~0); 146701#L610 assume !(0 == ~t6_st~0); 146678#L614 assume !(0 == ~t7_st~0);exists_runnable_thread_~__retres1~8 := 0; 146622#L628 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; 146539#L629 eval_#t~ret2 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret2;havoc eval_#t~ret2; 146538#L643 assume !(0 != eval_~tmp~0); 146536#L761 start_simulation_~kernel_st~0 := 2; 146534#L531-1 start_simulation_~kernel_st~0 := 3; 146532#L771-2 assume 0 == ~M_E~0;~M_E~0 := 1; 146530#L771-4 assume !(0 == ~T1_E~0); 146528#L776-3 assume !(0 == ~T2_E~0); 146526#L781-3 assume !(0 == ~T3_E~0); 146524#L786-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 146522#L791-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 146519#L796-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 146517#L801-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 146515#L806-3 assume 0 == ~E_M~0;~E_M~0 := 1; 146513#L811-3 assume !(0 == ~E_1~0); 146511#L816-3 assume !(0 == ~E_2~0); 146509#L821-3 assume !(0 == ~E_3~0); 146507#L826-3 assume 0 == ~E_4~0;~E_4~0 := 1; 146505#L831-3 assume 0 == ~E_5~0;~E_5~0 := 1; 142159#L836-3 assume 0 == ~E_6~0;~E_6~0 := 1; 141691#L841-3 assume 0 == ~E_7~0;~E_7~0 := 1; 141692#L846-3 havoc activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 141673#L378-27 assume 1 == ~m_pc~0; 141674#L379-9 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 141858#L389-9 is_master_triggered_#res := is_master_triggered_~__retres1~0; 142294#L390-9 activate_threads_#t~ret11 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 142381#L957-27 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 142579#L957-29 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 141904#L397-27 assume !(1 == ~t1_pc~0); 141905#L397-29 is_transmit1_triggered_~__retres1~1 := 0; 141907#L408-9 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 142462#L409-9 activate_threads_#t~ret12 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 142243#L965-27 assume !(0 != activate_threads_~tmp___0~0); 142230#L965-29 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 142077#L416-27 assume !(1 == ~t2_pc~0); 142032#L416-29 is_transmit2_triggered_~__retres1~2 := 0; 142058#L427-9 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 142521#L428-9 activate_threads_#t~ret13 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 141859#L973-27 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 141860#L973-29 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 141866#L435-27 assume !(1 == ~t3_pc~0); 142203#L435-29 is_transmit3_triggered_~__retres1~3 := 0; 141795#L446-9 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 141796#L447-9 activate_threads_#t~ret14 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 146105#L981-27 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 142507#L981-29 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 142508#L454-27 assume !(1 == ~t4_pc~0); 146102#L454-29 is_transmit4_triggered_~__retres1~4 := 0; 142001#L465-9 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 142002#L466-9 activate_threads_#t~ret15 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 146098#L989-27 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 146096#L989-29 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 142482#L473-27 assume 1 == ~t5_pc~0; 142483#L474-9 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 146091#L484-9 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 146088#L485-9 activate_threads_#t~ret16 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 146085#L997-27 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 146083#L997-29 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 142643#L492-27 assume !(1 == ~t6_pc~0); 142644#L492-29 is_transmit6_triggered_~__retres1~6 := 0; 146491#L503-9 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 146490#L504-9 activate_threads_#t~ret17 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 146489#L1005-27 assume !(0 != activate_threads_~tmp___5~0); 146488#L1005-29 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 146487#L511-27 assume !(1 == ~t7_pc~0); 146486#L511-29 is_transmit7_triggered_~__retres1~7 := 0; 146484#L522-9 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 146483#L523-9 activate_threads_#t~ret18 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 146482#L1013-27 assume 0 != activate_threads_~tmp___6~0;~t7_st~0 := 0; 146481#L1013-29 assume 1 == ~M_E~0;~M_E~0 := 2; 146480#L859-3 assume !(1 == ~T1_E~0); 146479#L864-3 assume !(1 == ~T2_E~0); 146478#L869-3 assume !(1 == ~T3_E~0); 146477#L874-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 146476#L879-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 146475#L884-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 146474#L889-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 146473#L894-3 assume 1 == ~E_M~0;~E_M~0 := 2; 146472#L899-3 assume !(1 == ~E_1~0); 146471#L904-3 assume !(1 == ~E_2~0); 146470#L909-3 assume !(1 == ~E_3~0); 146469#L914-3 assume 1 == ~E_4~0;~E_4~0 := 2; 146468#L919-3 assume 1 == ~E_5~0;~E_5~0 := 2; 146374#L924-3 assume 1 == ~E_6~0;~E_6~0 := 2; 146373#L929-3 assume 1 == ~E_7~0;~E_7~0 := 2; 146371#L934-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~8;havoc exists_runnable_thread_~__retres1~8; 146372#L586-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8 := 1; 146358#L628-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; 146359#L629-1 start_simulation_#t~ret20 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret20;havoc start_simulation_#t~ret20; 146350#L1199 assume !(0 == start_simulation_~tmp~3); 146351#L1199-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret19, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~8;havoc exists_runnable_thread_~__retres1~8; 146620#L586-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8 := 1; 146612#L628-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; 146610#L629-2 stop_simulation_#t~ret19 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret19;havoc stop_simulation_#t~ret19; 146609#L1154 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 146608#L1161 stop_simulation_#res := stop_simulation_~__retres2~0; 146606#L1162 start_simulation_#t~ret21 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret21;havoc start_simulation_#t~ret21; 146607#L1212 assume !(0 != start_simulation_~tmp___0~1); 141712#L1180-1 [2018-11-23 16:06:16,851 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 16:06:16,851 INFO L82 PathProgramCache]: Analyzing trace with hash 322056993, now seen corresponding path program 5 times [2018-11-23 16:06:16,851 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 16:06:16,851 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 16:06:16,852 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 16:06:16,852 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 16:06:16,852 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 16:06:16,857 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-23 16:06:16,862 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-23 16:06:16,878 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 16:06:16,879 INFO L82 PathProgramCache]: Analyzing trace with hash -589479648, now seen corresponding path program 1 times [2018-11-23 16:06:16,879 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 16:06:16,879 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 16:06:16,879 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 16:06:16,879 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-23 16:06:16,880 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 16:06:16,885 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 16:06:16,937 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 16:06:16,937 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 16:06:16,937 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-11-23 16:06:16,938 INFO L811 eck$LassoCheckResult]: loop already infeasible [2018-11-23 16:06:16,938 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-11-23 16:06:16,938 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-11-23 16:06:16,941 INFO L87 Difference]: Start difference. First operand 5251 states and 7243 transitions. cyclomatic complexity: 2000 Second operand 5 states. [2018-11-23 16:06:17,039 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 16:06:17,039 INFO L93 Difference]: Finished difference Result 8203 states and 11430 transitions. [2018-11-23 16:06:17,039 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2018-11-23 16:06:17,040 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 8203 states and 11430 transitions. [2018-11-23 16:06:17,056 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 8032 [2018-11-23 16:06:17,067 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 8203 states to 8203 states and 11430 transitions. [2018-11-23 16:06:17,067 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 8203 [2018-11-23 16:06:17,070 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 8203 [2018-11-23 16:06:17,070 INFO L73 IsDeterministic]: Start isDeterministic. Operand 8203 states and 11430 transitions. [2018-11-23 16:06:17,075 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-23 16:06:17,075 INFO L705 BuchiCegarLoop]: Abstraction has 8203 states and 11430 transitions. [2018-11-23 16:06:17,079 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 8203 states and 11430 transitions. [2018-11-23 16:06:17,105 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 8203 to 5275. [2018-11-23 16:06:17,105 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 5275 states. [2018-11-23 16:06:17,110 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 5275 states to 5275 states and 7206 transitions. [2018-11-23 16:06:17,110 INFO L728 BuchiCegarLoop]: Abstraction has 5275 states and 7206 transitions. [2018-11-23 16:06:17,110 INFO L608 BuchiCegarLoop]: Abstraction has 5275 states and 7206 transitions. [2018-11-23 16:06:17,110 INFO L442 BuchiCegarLoop]: ======== Iteration 23============ [2018-11-23 16:06:17,110 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 5275 states and 7206 transitions. [2018-11-23 16:06:17,119 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 5152 [2018-11-23 16:06:17,119 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-23 16:06:17,119 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-23 16:06:17,120 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 16:06:17,120 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 16:06:17,120 INFO L794 eck$LassoCheckResult]: Stem: 155607#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; 155501#L-1 havoc main_#res;havoc main_~__retres1~9;havoc main_~__retres1~9;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 155502#L1143 havoc start_simulation_#t~ret20, start_simulation_#t~ret21, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 155474#L531 assume 1 == ~m_i~0;~m_st~0 := 0; 155475#L538-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 155801#L543-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 155685#L548-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 155476#L553-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 155477#L558-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 155895#L563-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 155673#L568-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 155458#L573-1 assume !(0 == ~M_E~0); 155459#L771-1 assume !(0 == ~T1_E~0); 155305#L776-1 assume !(0 == ~T2_E~0); 155306#L781-1 assume !(0 == ~T3_E~0); 155747#L786-1 assume !(0 == ~T4_E~0); 155553#L791-1 assume !(0 == ~T5_E~0); 155239#L796-1 assume !(0 == ~T6_E~0); 155240#L801-1 assume !(0 == ~T7_E~0); 155994#L806-1 assume !(0 == ~E_M~0); 155639#L811-1 assume !(0 == ~E_1~0); 155399#L816-1 assume !(0 == ~E_2~0); 155400#L821-1 assume !(0 == ~E_3~0); 156062#L826-1 assume !(0 == ~E_4~0); 155850#L831-1 assume !(0 == ~E_5~0); 155625#L836-1 assume !(0 == ~E_6~0); 155154#L841-1 assume !(0 == ~E_7~0); 155155#L846-1 havoc activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 155223#L378 assume !(1 == ~m_pc~0); 155197#L378-2 is_master_triggered_~__retres1~0 := 0; 155198#L389 is_master_triggered_#res := is_master_triggered_~__retres1~0; 155811#L390 activate_threads_#t~ret11 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 155874#L957 assume !(0 != activate_threads_~tmp~1); 156097#L957-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 155440#L397 assume !(1 == ~t1_pc~0); 155354#L397-2 is_transmit1_triggered_~__retres1~1 := 0; 155446#L408 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 155879#L409 activate_threads_#t~ret12 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 155642#L965 assume !(0 != activate_threads_~tmp___0~0); 155632#L965-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 155633#L416 assume !(1 == ~t2_pc~0); 155526#L416-2 is_transmit2_triggered_~__retres1~2 := 0; 155571#L427 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 156027#L428 activate_threads_#t~ret13 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 155172#L973 assume !(0 != activate_threads_~tmp___1~0); 155173#L973-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 155177#L435 assume !(1 == ~t3_pc~0); 155838#L435-2 is_transmit3_triggered_~__retres1~3 := 0; 155267#L446 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 155268#L447 activate_threads_#t~ret14 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 155917#L981 assume !(0 != activate_threads_~tmp___2~0); 155906#L981-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 155907#L454 assume !(1 == ~t4_pc~0); 155985#L454-2 is_transmit4_triggered_~__retres1~4 := 0; 155480#L465 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 155217#L466 activate_threads_#t~ret15 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 155218#L989 assume !(0 != activate_threads_~tmp___3~0); 155557#L989-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 155561#L473 assume !(1 == ~t5_pc~0); 155973#L473-2 is_transmit5_triggered_~__retres1~5 := 0; 155615#L484 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 155461#L485 activate_threads_#t~ret16 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 155462#L997 assume !(0 != activate_threads_~tmp___4~0); 156132#L997-2 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 156133#L492 assume !(1 == ~t6_pc~0); 156169#L492-2 is_transmit6_triggered_~__retres1~6 := 0; 155730#L503 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 155686#L504 activate_threads_#t~ret17 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 155687#L1005 assume !(0 != activate_threads_~tmp___5~0); 155975#L1005-2 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 155142#L511 assume !(1 == ~t7_pc~0); 155143#L511-2 is_transmit7_triggered_~__retres1~7 := 0; 155296#L522 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 155744#L523 activate_threads_#t~ret18 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 155605#L1013 assume !(0 != activate_threads_~tmp___6~0); 155598#L1013-2 assume !(1 == ~M_E~0); 155599#L859-1 assume !(1 == ~T1_E~0); 155319#L864-1 assume !(1 == ~T2_E~0); 155320#L869-1 assume !(1 == ~T3_E~0); 155745#L874-1 assume !(1 == ~T4_E~0); 155546#L879-1 assume !(1 == ~T5_E~0); 155235#L884-1 assume !(1 == ~T6_E~0); 155236#L889-1 assume !(1 == ~T7_E~0); 155992#L894-1 assume !(1 == ~E_M~0); 155636#L899-1 assume !(1 == ~E_1~0); 155392#L904-1 assume !(1 == ~E_2~0); 155393#L909-1 assume !(1 == ~E_3~0); 156070#L914-1 assume !(1 == ~E_4~0); 155852#L919-1 assume !(1 == ~E_5~0); 155631#L924-1 assume !(1 == ~E_6~0); 155178#L929-1 assume !(1 == ~E_7~0); 155179#L1180-1 [2018-11-23 16:06:17,120 INFO L796 eck$LassoCheckResult]: Loop: 155179#L1180-1 assume !false; 156005#L1181 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret2, eval_#t~nondet3, eval_~tmp_ndt_1~0, eval_#t~nondet4, eval_~tmp_ndt_2~0, eval_#t~nondet5, eval_~tmp_ndt_3~0, eval_#t~nondet6, eval_~tmp_ndt_4~0, eval_#t~nondet7, eval_~tmp_ndt_5~0, eval_#t~nondet8, eval_~tmp_ndt_6~0, eval_#t~nondet9, eval_~tmp_ndt_7~0, eval_#t~nondet10, eval_~tmp_ndt_8~0, eval_~tmp~0;havoc eval_~tmp~0; 155308#L746 assume !false; 160367#L639 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~8;havoc exists_runnable_thread_~__retres1~8; 160365#L586 assume !(0 == ~m_st~0); 160364#L590 assume !(0 == ~t1_st~0); 160190#L594 assume !(0 == ~t2_st~0); 160188#L598 assume !(0 == ~t3_st~0); 160185#L602 assume !(0 == ~t4_st~0); 160182#L606 assume !(0 == ~t5_st~0); 160179#L610 assume !(0 == ~t6_st~0); 160175#L614 assume !(0 == ~t7_st~0);exists_runnable_thread_~__retres1~8 := 0; 160172#L628 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; 160169#L629 eval_#t~ret2 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret2;havoc eval_#t~ret2; 160166#L643 assume !(0 != eval_~tmp~0); 160163#L761 start_simulation_~kernel_st~0 := 2; 160159#L531-1 start_simulation_~kernel_st~0 := 3; 160156#L771-2 assume 0 == ~M_E~0;~M_E~0 := 1; 160153#L771-4 assume !(0 == ~T1_E~0); 160150#L776-3 assume !(0 == ~T2_E~0); 160147#L781-3 assume !(0 == ~T3_E~0); 160144#L786-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 160141#L791-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 160138#L796-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 160135#L801-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 160132#L806-3 assume 0 == ~E_M~0;~E_M~0 := 1; 160064#L811-3 assume !(0 == ~E_1~0); 160063#L816-3 assume !(0 == ~E_2~0); 160062#L821-3 assume !(0 == ~E_3~0); 160060#L826-3 assume 0 == ~E_4~0;~E_4~0 := 1; 160059#L831-3 assume 0 == ~E_5~0;~E_5~0 := 1; 160058#L836-3 assume 0 == ~E_6~0;~E_6~0 := 1; 160057#L841-3 assume 0 == ~E_7~0;~E_7~0 := 1; 156031#L846-3 havoc activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 155138#L378-27 assume 1 == ~m_pc~0; 155139#L379-9 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 155326#L389-9 is_master_triggered_#res := is_master_triggered_~__retres1~0; 155762#L390-9 activate_threads_#t~ret11 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 155856#L957-27 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 159724#L957-29 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 159723#L397-27 assume !(1 == ~t1_pc~0); 159721#L397-29 is_transmit1_triggered_~__retres1~1 := 0; 159720#L408-9 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 159618#L409-9 activate_threads_#t~ret12 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 159543#L965-27 assume !(0 != activate_threads_~tmp___0~0); 159358#L965-29 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 159356#L416-27 assume !(1 == ~t2_pc~0); 159353#L416-29 is_transmit2_triggered_~__retres1~2 := 0; 159351#L427-9 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 159349#L428-9 activate_threads_#t~ret13 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 159347#L973-27 assume !(0 != activate_threads_~tmp___1~0); 159345#L973-29 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 159343#L435-27 assume !(1 == ~t3_pc~0); 159341#L435-29 is_transmit3_triggered_~__retres1~3 := 0; 159337#L446-9 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 156112#L447-9 activate_threads_#t~ret14 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 156009#L981-27 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 155995#L981-29 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 155817#L454-27 assume !(1 == ~t4_pc~0); 155799#L454-29 is_transmit4_triggered_~__retres1~4 := 0; 155466#L465-9 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 155184#L466-9 activate_threads_#t~ret15 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 155185#L989-27 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 155494#L989-29 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 155497#L473-27 assume 1 == ~t5_pc~0; 155931#L474-9 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 155932#L484-9 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 159253#L485-9 activate_threads_#t~ret16 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 159247#L997-27 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 156117#L997-29 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 159416#L492-27 assume !(1 == ~t6_pc~0); 159414#L492-29 is_transmit6_triggered_~__retres1~6 := 0; 159412#L503-9 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 159410#L504-9 activate_threads_#t~ret17 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 159408#L1005-27 assume !(0 != activate_threads_~tmp___5~0); 159406#L1005-29 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 159400#L511-27 assume 1 == ~t7_pc~0; 159398#L512-9 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7 := 1; 159389#L522-9 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 159386#L523-9 activate_threads_#t~ret18 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 159384#L1013-27 assume 0 != activate_threads_~tmp___6~0;~t7_st~0 := 0; 159381#L1013-29 assume 1 == ~M_E~0;~M_E~0 := 2; 159379#L859-3 assume !(1 == ~T1_E~0); 159377#L864-3 assume !(1 == ~T2_E~0); 159373#L869-3 assume !(1 == ~T3_E~0); 159360#L874-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 159359#L879-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 159357#L884-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 159354#L889-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 159352#L894-3 assume 1 == ~E_M~0;~E_M~0 := 2; 159350#L899-3 assume !(1 == ~E_1~0); 159348#L904-3 assume !(1 == ~E_2~0); 159346#L909-3 assume !(1 == ~E_3~0); 159344#L914-3 assume 1 == ~E_4~0;~E_4~0 := 2; 159342#L919-3 assume 1 == ~E_5~0;~E_5~0 := 2; 159340#L924-3 assume 1 == ~E_6~0;~E_6~0 := 2; 159339#L929-3 assume 1 == ~E_7~0;~E_7~0 := 2; 159338#L934-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~8;havoc exists_runnable_thread_~__retres1~8; 159328#L586-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8 := 1; 159320#L628-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; 159317#L629-1 start_simulation_#t~ret20 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret20;havoc start_simulation_#t~ret20; 159315#L1199 assume !(0 == start_simulation_~tmp~3); 156014#L1199-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret19, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~8;havoc exists_runnable_thread_~__retres1~8; 156015#L586-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8 := 1; 155964#L628-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; 155965#L629-2 stop_simulation_#t~ret19 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret19;havoc stop_simulation_#t~ret19; 156039#L1154 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 156040#L1161 stop_simulation_#res := stop_simulation_~__retres2~0; 155835#L1162 start_simulation_#t~ret21 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret21;havoc start_simulation_#t~ret21; 155836#L1212 assume !(0 != start_simulation_~tmp___0~1); 155179#L1180-1 [2018-11-23 16:06:17,120 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 16:06:17,120 INFO L82 PathProgramCache]: Analyzing trace with hash 322056993, now seen corresponding path program 6 times [2018-11-23 16:06:17,121 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 16:06:17,121 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 16:06:17,121 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 16:06:17,121 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 16:06:17,121 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 16:06:17,126 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-23 16:06:17,130 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-23 16:06:17,146 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 16:06:17,146 INFO L82 PathProgramCache]: Analyzing trace with hash 1240994559, now seen corresponding path program 1 times [2018-11-23 16:06:17,146 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 16:06:17,146 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 16:06:17,147 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 16:06:17,147 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-23 16:06:17,147 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 16:06:17,152 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 16:06:17,216 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 16:06:17,216 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 16:06:17,216 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-11-23 16:06:17,217 INFO L811 eck$LassoCheckResult]: loop already infeasible [2018-11-23 16:06:17,217 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-11-23 16:06:17,217 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-11-23 16:06:17,217 INFO L87 Difference]: Start difference. First operand 5275 states and 7206 transitions. cyclomatic complexity: 1939 Second operand 5 states. [2018-11-23 16:06:17,441 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 16:06:17,441 INFO L93 Difference]: Finished difference Result 6975 states and 9529 transitions. [2018-11-23 16:06:17,442 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2018-11-23 16:06:17,443 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 6975 states and 9529 transitions. [2018-11-23 16:06:17,456 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 6836 [2018-11-23 16:06:17,463 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 6975 states to 6975 states and 9529 transitions. [2018-11-23 16:06:17,463 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 6975 [2018-11-23 16:06:17,466 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 6975 [2018-11-23 16:06:17,466 INFO L73 IsDeterministic]: Start isDeterministic. Operand 6975 states and 9529 transitions. [2018-11-23 16:06:17,469 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-23 16:06:17,469 INFO L705 BuchiCegarLoop]: Abstraction has 6975 states and 9529 transitions. [2018-11-23 16:06:17,472 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 6975 states and 9529 transitions. [2018-11-23 16:06:17,493 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 6975 to 5287. [2018-11-23 16:06:17,494 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 5287 states. [2018-11-23 16:06:17,498 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 5287 states to 5287 states and 7153 transitions. [2018-11-23 16:06:17,498 INFO L728 BuchiCegarLoop]: Abstraction has 5287 states and 7153 transitions. [2018-11-23 16:06:17,498 INFO L608 BuchiCegarLoop]: Abstraction has 5287 states and 7153 transitions. [2018-11-23 16:06:17,498 INFO L442 BuchiCegarLoop]: ======== Iteration 24============ [2018-11-23 16:06:17,498 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 5287 states and 7153 transitions. [2018-11-23 16:06:17,506 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 5164 [2018-11-23 16:06:17,506 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-23 16:06:17,506 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-23 16:06:17,507 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 16:06:17,507 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 16:06:17,507 INFO L794 eck$LassoCheckResult]: Stem: 167885#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; 167778#L-1 havoc main_#res;havoc main_~__retres1~9;havoc main_~__retres1~9;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 167779#L1143 havoc start_simulation_#t~ret20, start_simulation_#t~ret21, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 167751#L531 assume 1 == ~m_i~0;~m_st~0 := 0; 167752#L538-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 168074#L543-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 167960#L548-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 167753#L553-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 167754#L558-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 168169#L563-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 167950#L568-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 167731#L573-1 assume !(0 == ~M_E~0); 167732#L771-1 assume !(0 == ~T1_E~0); 167572#L776-1 assume !(0 == ~T2_E~0); 167573#L781-1 assume !(0 == ~T3_E~0); 168026#L786-1 assume !(0 == ~T4_E~0); 167830#L791-1 assume !(0 == ~T5_E~0); 167505#L796-1 assume !(0 == ~T6_E~0); 167506#L801-1 assume !(0 == ~T7_E~0); 168262#L806-1 assume !(0 == ~E_M~0); 167916#L811-1 assume !(0 == ~E_1~0); 167672#L816-1 assume !(0 == ~E_2~0); 167673#L821-1 assume !(0 == ~E_3~0); 168324#L826-1 assume !(0 == ~E_4~0); 168123#L831-1 assume !(0 == ~E_5~0); 167903#L836-1 assume !(0 == ~E_6~0); 167420#L841-1 assume !(0 == ~E_7~0); 167421#L846-1 havoc activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 167489#L378 assume !(1 == ~m_pc~0); 167463#L378-2 is_master_triggered_~__retres1~0 := 0; 167464#L389 is_master_triggered_#res := is_master_triggered_~__retres1~0; 168082#L390 activate_threads_#t~ret11 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 168149#L957 assume !(0 != activate_threads_~tmp~1); 168364#L957-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 167712#L397 assume !(1 == ~t1_pc~0); 167626#L397-2 is_transmit1_triggered_~__retres1~1 := 0; 167719#L408 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 168154#L409 activate_threads_#t~ret12 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 167919#L965 assume !(0 != activate_threads_~tmp___0~0); 167910#L965-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 167911#L416 assume !(1 == ~t2_pc~0); 167803#L416-2 is_transmit2_triggered_~__retres1~2 := 0; 167847#L427 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 168292#L428 activate_threads_#t~ret13 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 167438#L973 assume !(0 != activate_threads_~tmp___1~0); 167439#L973-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 167443#L435 assume !(1 == ~t3_pc~0); 168113#L435-2 is_transmit3_triggered_~__retres1~3 := 0; 167534#L446 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 167535#L447 activate_threads_#t~ret14 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 168192#L981 assume !(0 != activate_threads_~tmp___2~0); 168181#L981-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 168182#L454 assume !(1 == ~t4_pc~0); 168249#L454-2 is_transmit4_triggered_~__retres1~4 := 0; 167757#L465 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 167483#L466 activate_threads_#t~ret15 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 167484#L989 assume !(0 != activate_threads_~tmp___3~0); 167835#L989-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 167838#L473 assume !(1 == ~t5_pc~0); 168244#L473-2 is_transmit5_triggered_~__retres1~5 := 0; 167892#L484 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 167735#L485 activate_threads_#t~ret16 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 167736#L997 assume !(0 != activate_threads_~tmp___4~0); 168398#L997-2 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 168399#L492 assume !(1 == ~t6_pc~0); 168437#L492-2 is_transmit6_triggered_~__retres1~6 := 0; 168009#L503 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 167961#L504 activate_threads_#t~ret17 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 167962#L1005 assume !(0 != activate_threads_~tmp___5~0); 168246#L1005-2 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 167408#L511 assume !(1 == ~t7_pc~0); 167409#L511-2 is_transmit7_triggered_~__retres1~7 := 0; 167563#L522 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 168022#L523 activate_threads_#t~ret18 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 167883#L1013 assume !(0 != activate_threads_~tmp___6~0); 167875#L1013-2 assume !(1 == ~M_E~0); 167876#L859-1 assume !(1 == ~T1_E~0); 167586#L864-1 assume !(1 == ~T2_E~0); 167587#L869-1 assume !(1 == ~T3_E~0); 168023#L874-1 assume !(1 == ~T4_E~0); 167822#L879-1 assume !(1 == ~T5_E~0); 167501#L884-1 assume !(1 == ~T6_E~0); 167502#L889-1 assume !(1 == ~T7_E~0); 168259#L894-1 assume !(1 == ~E_M~0); 167914#L899-1 assume !(1 == ~E_1~0); 167664#L904-1 assume !(1 == ~E_2~0); 167665#L909-1 assume !(1 == ~E_3~0); 168333#L914-1 assume !(1 == ~E_4~0); 168126#L919-1 assume !(1 == ~E_5~0); 167909#L924-1 assume !(1 == ~E_6~0); 167444#L929-1 assume !(1 == ~E_7~0); 167445#L1180-1 [2018-11-23 16:06:17,508 INFO L796 eck$LassoCheckResult]: Loop: 167445#L1180-1 assume !false; 170573#L1181 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret2, eval_#t~nondet3, eval_~tmp_ndt_1~0, eval_#t~nondet4, eval_~tmp_ndt_2~0, eval_#t~nondet5, eval_~tmp_ndt_3~0, eval_#t~nondet6, eval_~tmp_ndt_4~0, eval_#t~nondet7, eval_~tmp_ndt_5~0, eval_#t~nondet8, eval_~tmp_ndt_6~0, eval_#t~nondet9, eval_~tmp_ndt_7~0, eval_#t~nondet10, eval_~tmp_ndt_8~0, eval_~tmp~0;havoc eval_~tmp~0; 170568#L746 assume !false; 170566#L639 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~8;havoc exists_runnable_thread_~__retres1~8; 170562#L586 assume !(0 == ~m_st~0); 170563#L590 assume !(0 == ~t1_st~0); 170558#L594 assume !(0 == ~t2_st~0); 170559#L598 assume !(0 == ~t3_st~0); 170561#L602 assume !(0 == ~t4_st~0); 170556#L606 assume !(0 == ~t5_st~0); 170557#L610 assume !(0 == ~t6_st~0); 170560#L614 assume !(0 == ~t7_st~0);exists_runnable_thread_~__retres1~8 := 0; 170564#L628 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; 170550#L629 eval_#t~ret2 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret2;havoc eval_#t~ret2; 170551#L643 assume !(0 != eval_~tmp~0); 170825#L761 start_simulation_~kernel_st~0 := 2; 170824#L531-1 start_simulation_~kernel_st~0 := 3; 170823#L771-2 assume 0 == ~M_E~0;~M_E~0 := 1; 170822#L771-4 assume !(0 == ~T1_E~0); 170821#L776-3 assume !(0 == ~T2_E~0); 170820#L781-3 assume !(0 == ~T3_E~0); 170819#L786-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 170818#L791-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 170817#L796-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 170816#L801-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 170815#L806-3 assume 0 == ~E_M~0;~E_M~0 := 1; 170814#L811-3 assume !(0 == ~E_1~0); 170813#L816-3 assume !(0 == ~E_2~0); 170812#L821-3 assume !(0 == ~E_3~0); 170811#L826-3 assume 0 == ~E_4~0;~E_4~0 := 1; 170810#L831-3 assume 0 == ~E_5~0;~E_5~0 := 1; 170809#L836-3 assume 0 == ~E_6~0;~E_6~0 := 1; 170808#L841-3 assume 0 == ~E_7~0;~E_7~0 := 1; 170807#L846-3 havoc activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 170806#L378-27 assume 1 == ~m_pc~0; 170804#L379-9 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 170803#L389-9 is_master_triggered_#res := is_master_triggered_~__retres1~0; 170802#L390-9 activate_threads_#t~ret11 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 170801#L957-27 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 170800#L957-29 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 170799#L397-27 assume !(1 == ~t1_pc~0); 170796#L397-29 is_transmit1_triggered_~__retres1~1 := 0; 170793#L408-9 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 170791#L409-9 activate_threads_#t~ret12 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 170789#L965-27 assume !(0 != activate_threads_~tmp___0~0); 170787#L965-29 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 170785#L416-27 assume !(1 == ~t2_pc~0); 170781#L416-29 is_transmit2_triggered_~__retres1~2 := 0; 170779#L427-9 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 170777#L428-9 activate_threads_#t~ret13 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 170775#L973-27 assume !(0 != activate_threads_~tmp___1~0); 170773#L973-29 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 170771#L435-27 assume !(1 == ~t3_pc~0); 170768#L435-29 is_transmit3_triggered_~__retres1~3 := 0; 170766#L446-9 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 170764#L447-9 activate_threads_#t~ret14 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 170762#L981-27 assume !(0 != activate_threads_~tmp___2~0); 170760#L981-29 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 170758#L454-27 assume !(1 == ~t4_pc~0); 170756#L454-29 is_transmit4_triggered_~__retres1~4 := 0; 170754#L465-9 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 170752#L466-9 activate_threads_#t~ret15 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 170750#L989-27 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 170747#L989-29 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 170743#L473-27 assume 1 == ~t5_pc~0; 170739#L474-9 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 170735#L484-9 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 170731#L485-9 activate_threads_#t~ret16 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 170727#L997-27 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 170723#L997-29 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 170720#L492-27 assume !(1 == ~t6_pc~0); 170717#L492-29 is_transmit6_triggered_~__retres1~6 := 0; 170713#L503-9 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 170709#L504-9 activate_threads_#t~ret17 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 170705#L1005-27 assume !(0 != activate_threads_~tmp___5~0); 170700#L1005-29 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 170697#L511-27 assume !(1 == ~t7_pc~0); 170694#L511-29 is_transmit7_triggered_~__retres1~7 := 0; 170690#L522-9 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 170687#L523-9 activate_threads_#t~ret18 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 170684#L1013-27 assume 0 != activate_threads_~tmp___6~0;~t7_st~0 := 0; 170681#L1013-29 assume 1 == ~M_E~0;~M_E~0 := 2; 170678#L859-3 assume !(1 == ~T1_E~0); 170675#L864-3 assume !(1 == ~T2_E~0); 170671#L869-3 assume !(1 == ~T3_E~0); 170668#L874-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 170665#L879-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 170662#L884-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 170659#L889-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 170656#L894-3 assume 1 == ~E_M~0;~E_M~0 := 2; 170653#L899-3 assume !(1 == ~E_1~0); 170650#L904-3 assume !(1 == ~E_2~0); 170647#L909-3 assume !(1 == ~E_3~0); 170644#L914-3 assume 1 == ~E_4~0;~E_4~0 := 2; 170640#L919-3 assume 1 == ~E_5~0;~E_5~0 := 2; 170636#L924-3 assume 1 == ~E_6~0;~E_6~0 := 2; 170632#L929-3 assume 1 == ~E_7~0;~E_7~0 := 2; 170628#L934-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~8;havoc exists_runnable_thread_~__retres1~8; 170624#L586-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8 := 1; 170614#L628-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; 170611#L629-1 start_simulation_#t~ret20 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret20;havoc start_simulation_#t~ret20; 170607#L1199 assume !(0 == start_simulation_~tmp~3); 170604#L1199-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret19, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~8;havoc exists_runnable_thread_~__retres1~8; 170602#L586-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8 := 1; 170593#L628-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; 170591#L629-2 stop_simulation_#t~ret19 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret19;havoc stop_simulation_#t~ret19; 170588#L1154 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 170586#L1161 stop_simulation_#res := stop_simulation_~__retres2~0; 170584#L1162 start_simulation_#t~ret21 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret21;havoc start_simulation_#t~ret21; 170581#L1212 assume !(0 != start_simulation_~tmp___0~1); 167445#L1180-1 [2018-11-23 16:06:17,508 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 16:06:17,508 INFO L82 PathProgramCache]: Analyzing trace with hash 322056993, now seen corresponding path program 7 times [2018-11-23 16:06:17,508 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 16:06:17,508 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 16:06:17,509 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 16:06:17,509 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 16:06:17,509 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 16:06:17,513 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-23 16:06:17,517 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-23 16:06:17,535 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 16:06:17,536 INFO L82 PathProgramCache]: Analyzing trace with hash 488363292, now seen corresponding path program 1 times [2018-11-23 16:06:17,536 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 16:06:17,536 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 16:06:17,536 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 16:06:17,536 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 16:06:17,537 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 16:06:17,541 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 16:06:17,591 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 16:06:17,591 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 16:06:17,591 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-11-23 16:06:17,592 INFO L811 eck$LassoCheckResult]: loop already infeasible [2018-11-23 16:06:17,592 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-11-23 16:06:17,592 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-11-23 16:06:17,592 INFO L87 Difference]: Start difference. First operand 5287 states and 7153 transitions. cyclomatic complexity: 1874 Second operand 5 states. [2018-11-23 16:06:17,728 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 16:06:17,728 INFO L93 Difference]: Finished difference Result 9406 states and 12772 transitions. [2018-11-23 16:06:17,729 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2018-11-23 16:06:17,729 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 9406 states and 12772 transitions. [2018-11-23 16:06:17,749 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 9267 [2018-11-23 16:06:17,761 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 9406 states to 9406 states and 12772 transitions. [2018-11-23 16:06:17,762 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 9406 [2018-11-23 16:06:17,766 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 9406 [2018-11-23 16:06:17,766 INFO L73 IsDeterministic]: Start isDeterministic. Operand 9406 states and 12772 transitions. [2018-11-23 16:06:17,770 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-23 16:06:17,770 INFO L705 BuchiCegarLoop]: Abstraction has 9406 states and 12772 transitions. [2018-11-23 16:06:17,774 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 9406 states and 12772 transitions. [2018-11-23 16:06:17,802 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 9406 to 5395. [2018-11-23 16:06:17,802 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 5395 states. [2018-11-23 16:06:17,806 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 5395 states to 5395 states and 7228 transitions. [2018-11-23 16:06:17,807 INFO L728 BuchiCegarLoop]: Abstraction has 5395 states and 7228 transitions. [2018-11-23 16:06:17,807 INFO L608 BuchiCegarLoop]: Abstraction has 5395 states and 7228 transitions. [2018-11-23 16:06:17,807 INFO L442 BuchiCegarLoop]: ======== Iteration 25============ [2018-11-23 16:06:17,807 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 5395 states and 7228 transitions. [2018-11-23 16:06:17,816 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 5272 [2018-11-23 16:06:17,816 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-23 16:06:17,816 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-23 16:06:17,817 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 16:06:17,817 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 16:06:17,817 INFO L794 eck$LassoCheckResult]: Stem: 182576#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; 182469#L-1 havoc main_#res;havoc main_~__retres1~9;havoc main_~__retres1~9;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 182470#L1143 havoc start_simulation_#t~ret20, start_simulation_#t~ret21, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 182440#L531 assume 1 == ~m_i~0;~m_st~0 := 0; 182441#L538-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 182756#L543-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 182651#L548-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 182442#L553-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 182443#L558-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 182836#L563-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 182638#L568-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 182421#L573-1 assume !(0 == ~M_E~0); 182422#L771-1 assume !(0 == ~T1_E~0); 182272#L776-1 assume !(0 == ~T2_E~0); 182273#L781-1 assume !(0 == ~T3_E~0); 182711#L786-1 assume !(0 == ~T4_E~0); 182521#L791-1 assume !(0 == ~T5_E~0); 182211#L796-1 assume !(0 == ~T6_E~0); 182212#L801-1 assume !(0 == ~T7_E~0); 182933#L806-1 assume !(0 == ~E_M~0); 182603#L811-1 assume !(0 == ~E_1~0); 182366#L816-1 assume !(0 == ~E_2~0); 182367#L821-1 assume !(0 == ~E_3~0); 182989#L826-1 assume !(0 == ~E_4~0); 182798#L831-1 assume !(0 == ~E_5~0); 182591#L836-1 assume !(0 == ~E_6~0); 182123#L841-1 assume !(0 == ~E_7~0); 182124#L846-1 havoc activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 182195#L378 assume !(1 == ~m_pc~0); 182169#L378-2 is_master_triggered_~__retres1~0 := 0; 182170#L389 is_master_triggered_#res := is_master_triggered_~__retres1~0; 182764#L390 activate_threads_#t~ret11 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 182816#L957 assume !(0 != activate_threads_~tmp~1); 183011#L957-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 182404#L397 assume !(1 == ~t1_pc~0); 182321#L397-2 is_transmit1_triggered_~__retres1~1 := 0; 182409#L408 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 182820#L409 activate_threads_#t~ret12 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 182606#L965 assume !(0 != activate_threads_~tmp___0~0); 182597#L965-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 182598#L416 assume !(1 == ~t2_pc~0); 182492#L416-2 is_transmit2_triggered_~__retres1~2 := 0; 182539#L427 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 182961#L428 activate_threads_#t~ret13 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 182141#L973 assume !(0 != activate_threads_~tmp___1~0); 182142#L973-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 182147#L435 assume !(1 == ~t3_pc~0); 182788#L435-2 is_transmit3_triggered_~__retres1~3 := 0; 182236#L446 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 182237#L447 activate_threads_#t~ret14 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 182862#L981 assume !(0 != activate_threads_~tmp___2~0); 182848#L981-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 182849#L454 assume !(1 == ~t4_pc~0); 182920#L454-2 is_transmit4_triggered_~__retres1~4 := 0; 182446#L465 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 182189#L466 activate_threads_#t~ret15 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 182190#L989 assume !(0 != activate_threads_~tmp___3~0); 182526#L989-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 182529#L473 assume !(1 == ~t5_pc~0); 182908#L473-2 is_transmit5_triggered_~__retres1~5 := 0; 182581#L484 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 182424#L485 activate_threads_#t~ret16 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 182425#L997 assume !(0 != activate_threads_~tmp___4~0); 183043#L997-2 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 183044#L492 assume !(1 == ~t6_pc~0); 183068#L492-2 is_transmit6_triggered_~__retres1~6 := 0; 182694#L503 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 182652#L504 activate_threads_#t~ret17 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 182653#L1005 assume !(0 != activate_threads_~tmp___5~0); 182910#L1005-2 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 182114#L511 assume !(1 == ~t7_pc~0); 182115#L511-2 is_transmit7_triggered_~__retres1~7 := 0; 182266#L522 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 182708#L523 activate_threads_#t~ret18 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 182574#L1013 assume !(0 != activate_threads_~tmp___6~0); 182567#L1013-2 assume !(1 == ~M_E~0); 182568#L859-1 assume !(1 == ~T1_E~0); 182285#L864-1 assume !(1 == ~T2_E~0); 182286#L869-1 assume !(1 == ~T3_E~0); 182709#L874-1 assume !(1 == ~T4_E~0); 182512#L879-1 assume !(1 == ~T5_E~0); 182207#L884-1 assume !(1 == ~T6_E~0); 182208#L889-1 assume !(1 == ~T7_E~0); 182931#L894-1 assume !(1 == ~E_M~0); 182599#L899-1 assume !(1 == ~E_1~0); 182359#L904-1 assume !(1 == ~E_2~0); 182360#L909-1 assume !(1 == ~E_3~0); 182995#L914-1 assume !(1 == ~E_4~0); 182800#L919-1 assume !(1 == ~E_5~0); 182596#L924-1 assume !(1 == ~E_6~0); 182150#L929-1 assume !(1 == ~E_7~0); 182151#L1180-1 [2018-11-23 16:06:17,818 INFO L796 eck$LassoCheckResult]: Loop: 182151#L1180-1 assume !false; 185255#L1181 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret2, eval_#t~nondet3, eval_~tmp_ndt_1~0, eval_#t~nondet4, eval_~tmp_ndt_2~0, eval_#t~nondet5, eval_~tmp_ndt_3~0, eval_#t~nondet6, eval_~tmp_ndt_4~0, eval_#t~nondet7, eval_~tmp_ndt_5~0, eval_#t~nondet8, eval_~tmp_ndt_6~0, eval_#t~nondet9, eval_~tmp_ndt_7~0, eval_#t~nondet10, eval_~tmp_ndt_8~0, eval_~tmp~0;havoc eval_~tmp~0; 185116#L746 assume !false; 185253#L639 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~8;havoc exists_runnable_thread_~__retres1~8; 185250#L586 assume !(0 == ~m_st~0); 185251#L590 assume !(0 == ~t1_st~0); 185246#L594 assume !(0 == ~t2_st~0); 185247#L598 assume !(0 == ~t3_st~0); 185249#L602 assume !(0 == ~t4_st~0); 185244#L606 assume !(0 == ~t5_st~0); 185245#L610 assume !(0 == ~t6_st~0); 185248#L614 assume !(0 == ~t7_st~0);exists_runnable_thread_~__retres1~8 := 0; 185252#L628 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; 184913#L629 eval_#t~ret2 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret2;havoc eval_#t~ret2; 184914#L643 assume !(0 != eval_~tmp~0); 186328#L761 start_simulation_~kernel_st~0 := 2; 186327#L531-1 start_simulation_~kernel_st~0 := 3; 186326#L771-2 assume 0 == ~M_E~0;~M_E~0 := 1; 186325#L771-4 assume !(0 == ~T1_E~0); 186324#L776-3 assume !(0 == ~T2_E~0); 186323#L781-3 assume !(0 == ~T3_E~0); 186322#L786-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 186321#L791-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 186320#L796-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 186319#L801-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 186318#L806-3 assume 0 == ~E_M~0;~E_M~0 := 1; 186317#L811-3 assume !(0 == ~E_1~0); 186316#L816-3 assume !(0 == ~E_2~0); 186315#L821-3 assume !(0 == ~E_3~0); 186314#L826-3 assume 0 == ~E_4~0;~E_4~0 := 1; 186313#L831-3 assume 0 == ~E_5~0;~E_5~0 := 1; 186312#L836-3 assume 0 == ~E_6~0;~E_6~0 := 1; 186311#L841-3 assume 0 == ~E_7~0;~E_7~0 := 1; 186310#L846-3 havoc activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 186309#L378-27 assume 1 == ~m_pc~0; 186307#L379-9 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 186306#L389-9 is_master_triggered_#res := is_master_triggered_~__retres1~0; 186305#L390-9 activate_threads_#t~ret11 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 186304#L957-27 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 186303#L957-29 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 186302#L397-27 assume !(1 == ~t1_pc~0); 186300#L397-29 is_transmit1_triggered_~__retres1~1 := 0; 186299#L408-9 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 186298#L409-9 activate_threads_#t~ret12 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 186297#L965-27 assume !(0 != activate_threads_~tmp___0~0); 186296#L965-29 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 186295#L416-27 assume !(1 == ~t2_pc~0); 186292#L416-29 is_transmit2_triggered_~__retres1~2 := 0; 186289#L427-9 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 186287#L428-9 activate_threads_#t~ret13 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 186285#L973-27 assume !(0 != activate_threads_~tmp___1~0); 186283#L973-29 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 186281#L435-27 assume !(1 == ~t3_pc~0); 186278#L435-29 is_transmit3_triggered_~__retres1~3 := 0; 186276#L446-9 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 186274#L447-9 activate_threads_#t~ret14 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 186272#L981-27 assume !(0 != activate_threads_~tmp___2~0); 182934#L981-29 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 182772#L454-27 assume !(1 == ~t4_pc~0); 182773#L454-29 is_transmit4_triggered_~__retres1~4 := 0; 185243#L465-9 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 185242#L466-9 activate_threads_#t~ret15 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 185241#L989-27 assume !(0 != activate_threads_~tmp___3~0); 185240#L989-29 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 185239#L473-27 assume !(1 == ~t5_pc~0); 185238#L473-29 is_transmit5_triggered_~__retres1~5 := 0; 185236#L484-9 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 185234#L485-9 activate_threads_#t~ret16 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 185232#L997-27 assume !(0 != activate_threads_~tmp___4~0); 185230#L997-29 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 185229#L492-27 assume !(1 == ~t6_pc~0); 185228#L492-29 is_transmit6_triggered_~__retres1~6 := 0; 185227#L503-9 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 185226#L504-9 activate_threads_#t~ret17 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 185225#L1005-27 assume !(0 != activate_threads_~tmp___5~0); 185224#L1005-29 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 185223#L511-27 assume !(1 == ~t7_pc~0); 185222#L511-29 is_transmit7_triggered_~__retres1~7 := 0; 185220#L522-9 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 185218#L523-9 activate_threads_#t~ret18 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 185216#L1013-27 assume 0 != activate_threads_~tmp___6~0;~t7_st~0 := 0; 185214#L1013-29 assume 1 == ~M_E~0;~M_E~0 := 2; 185212#L859-3 assume !(1 == ~T1_E~0); 185210#L864-3 assume !(1 == ~T2_E~0); 185208#L869-3 assume !(1 == ~T3_E~0); 185206#L874-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 185204#L879-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 185202#L884-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 185200#L889-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 185198#L894-3 assume 1 == ~E_M~0;~E_M~0 := 2; 185196#L899-3 assume !(1 == ~E_1~0); 185194#L904-3 assume !(1 == ~E_2~0); 185192#L909-3 assume !(1 == ~E_3~0); 185190#L914-3 assume 1 == ~E_4~0;~E_4~0 := 2; 185188#L919-3 assume 1 == ~E_5~0;~E_5~0 := 2; 185186#L924-3 assume 1 == ~E_6~0;~E_6~0 := 2; 185184#L929-3 assume 1 == ~E_7~0;~E_7~0 := 2; 185182#L934-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~8;havoc exists_runnable_thread_~__retres1~8; 185180#L586-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8 := 1; 185170#L628-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; 185168#L629-1 start_simulation_#t~ret20 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret20;havoc start_simulation_#t~ret20; 185165#L1199 assume !(0 == start_simulation_~tmp~3); 185166#L1199-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret19, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~8;havoc exists_runnable_thread_~__retres1~8; 185277#L586-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8 := 1; 185268#L628-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; 185266#L629-2 stop_simulation_#t~ret19 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret19;havoc stop_simulation_#t~ret19; 185263#L1154 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 185261#L1161 stop_simulation_#res := stop_simulation_~__retres2~0; 185259#L1162 start_simulation_#t~ret21 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret21;havoc start_simulation_#t~ret21; 185257#L1212 assume !(0 != start_simulation_~tmp___0~1); 182151#L1180-1 [2018-11-23 16:06:17,818 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 16:06:17,818 INFO L82 PathProgramCache]: Analyzing trace with hash 322056993, now seen corresponding path program 8 times [2018-11-23 16:06:17,818 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 16:06:17,818 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 16:06:17,819 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 16:06:17,819 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 16:06:17,819 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 16:06:17,823 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-23 16:06:17,828 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-23 16:06:17,846 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 16:06:17,847 INFO L82 PathProgramCache]: Analyzing trace with hash 1367667063, now seen corresponding path program 1 times [2018-11-23 16:06:17,847 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 16:06:17,847 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 16:06:17,847 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 16:06:17,847 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-23 16:06:17,847 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 16:06:17,853 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 16:06:17,905 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 16:06:17,905 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 16:06:17,906 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-11-23 16:06:17,906 INFO L811 eck$LassoCheckResult]: loop already infeasible [2018-11-23 16:06:17,906 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-11-23 16:06:17,906 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-11-23 16:06:17,906 INFO L87 Difference]: Start difference. First operand 5395 states and 7228 transitions. cyclomatic complexity: 1841 Second operand 5 states. [2018-11-23 16:06:18,044 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 16:06:18,044 INFO L93 Difference]: Finished difference Result 11802 states and 15983 transitions. [2018-11-23 16:06:18,046 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2018-11-23 16:06:18,046 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 11802 states and 15983 transitions. [2018-11-23 16:06:18,070 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 11596 [2018-11-23 16:06:18,086 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 11802 states to 11802 states and 15983 transitions. [2018-11-23 16:06:18,087 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 11802 [2018-11-23 16:06:18,092 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 11802 [2018-11-23 16:06:18,092 INFO L73 IsDeterministic]: Start isDeterministic. Operand 11802 states and 15983 transitions. [2018-11-23 16:06:18,097 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-23 16:06:18,097 INFO L705 BuchiCegarLoop]: Abstraction has 11802 states and 15983 transitions. [2018-11-23 16:06:18,102 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 11802 states and 15983 transitions. [2018-11-23 16:06:18,133 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 11802 to 5602. [2018-11-23 16:06:18,133 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 5602 states. [2018-11-23 16:06:18,138 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 5602 states to 5602 states and 7435 transitions. [2018-11-23 16:06:18,138 INFO L728 BuchiCegarLoop]: Abstraction has 5602 states and 7435 transitions. [2018-11-23 16:06:18,138 INFO L608 BuchiCegarLoop]: Abstraction has 5602 states and 7435 transitions. [2018-11-23 16:06:18,138 INFO L442 BuchiCegarLoop]: ======== Iteration 26============ [2018-11-23 16:06:18,138 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 5602 states and 7435 transitions. [2018-11-23 16:06:18,148 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 5476 [2018-11-23 16:06:18,148 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-23 16:06:18,148 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-23 16:06:18,149 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 16:06:18,149 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 16:06:18,150 INFO L794 eck$LassoCheckResult]: Stem: 199795#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; 199698#L-1 havoc main_#res;havoc main_~__retres1~9;havoc main_~__retres1~9;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 199699#L1143 havoc start_simulation_#t~ret20, start_simulation_#t~ret21, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 199672#L531 assume 1 == ~m_i~0;~m_st~0 := 0; 199673#L538-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 199978#L543-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 199869#L548-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 199674#L553-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 199675#L558-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 200073#L563-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 199858#L568-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 199658#L573-1 assume !(0 == ~M_E~0); 199659#L771-1 assume !(0 == ~T1_E~0); 199490#L776-1 assume !(0 == ~T2_E~0); 199491#L781-1 assume !(0 == ~T3_E~0); 199927#L786-1 assume !(0 == ~T4_E~0); 199743#L791-1 assume !(0 == ~T5_E~0); 199421#L796-1 assume !(0 == ~T6_E~0); 199422#L801-1 assume !(0 == ~T7_E~0); 200152#L806-1 assume !(0 == ~E_M~0); 199826#L811-1 assume !(0 == ~E_1~0); 199603#L816-1 assume !(0 == ~E_2~0); 199604#L821-1 assume !(0 == ~E_3~0); 200197#L826-1 assume !(0 == ~E_4~0); 200035#L831-1 assume !(0 == ~E_5~0); 199813#L836-1 assume !(0 == ~E_6~0); 199331#L841-1 assume !(0 == ~E_7~0); 199332#L846-1 havoc activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 199405#L378 assume !(1 == ~m_pc~0); 199379#L378-2 is_master_triggered_~__retres1~0 := 0; 199380#L389 is_master_triggered_#res := is_master_triggered_~__retres1~0; 199988#L390 activate_threads_#t~ret11 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 200052#L957 assume !(0 != activate_threads_~tmp~1); 200226#L957-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 199642#L397 assume !(1 == ~t1_pc~0); 199559#L397-2 is_transmit1_triggered_~__retres1~1 := 0; 199647#L408 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 200058#L409 activate_threads_#t~ret12 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 199829#L965 assume !(0 != activate_threads_~tmp___0~0); 199820#L965-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 199821#L416 assume !(1 == ~t2_pc~0); 199719#L416-2 is_transmit2_triggered_~__retres1~2 := 0; 199759#L427 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 200174#L428 activate_threads_#t~ret13 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 199351#L973 assume !(0 != activate_threads_~tmp___1~0); 199352#L973-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 199357#L435 assume !(1 == ~t3_pc~0); 200021#L435-2 is_transmit3_triggered_~__retres1~3 := 0; 199447#L446 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 199448#L447 activate_threads_#t~ret14 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 200095#L981 assume !(0 != activate_threads_~tmp___2~0); 200084#L981-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 200085#L454 assume !(1 == ~t4_pc~0); 200145#L454-2 is_transmit4_triggered_~__retres1~4 := 0; 199678#L465 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 199399#L466 activate_threads_#t~ret15 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 199400#L989 assume !(0 != activate_threads_~tmp___3~0); 199747#L989-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 199750#L473 assume !(1 == ~t5_pc~0); 200138#L473-2 is_transmit5_triggered_~__retres1~5 := 0; 199800#L484 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 199661#L485 activate_threads_#t~ret16 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 199662#L997 assume !(0 != activate_threads_~tmp___4~0); 200250#L997-2 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 200251#L492 assume !(1 == ~t6_pc~0); 200272#L492-2 is_transmit6_triggered_~__retres1~6 := 0; 199910#L503 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 199870#L504 activate_threads_#t~ret17 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 199871#L1005 assume !(0 != activate_threads_~tmp___5~0); 200141#L1005-2 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 199320#L511 assume !(1 == ~t7_pc~0); 199321#L511-2 is_transmit7_triggered_~__retres1~7 := 0; 199548#L522 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 199924#L523 activate_threads_#t~ret18 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 199792#L1013 assume !(0 != activate_threads_~tmp___6~0); 199785#L1013-2 assume !(1 == ~M_E~0); 199786#L859-1 assume !(1 == ~T1_E~0); 199512#L864-1 assume !(1 == ~T2_E~0); 199513#L869-1 assume !(1 == ~T3_E~0); 199925#L874-1 assume !(1 == ~T4_E~0); 199736#L879-1 assume !(1 == ~T5_E~0); 199417#L884-1 assume !(1 == ~T6_E~0); 199418#L889-1 assume !(1 == ~T7_E~0); 200150#L894-1 assume !(1 == ~E_M~0); 199822#L899-1 assume !(1 == ~E_1~0); 199596#L904-1 assume !(1 == ~E_2~0); 199597#L909-1 assume !(1 == ~E_3~0); 200200#L914-1 assume !(1 == ~E_4~0); 200038#L919-1 assume !(1 == ~E_5~0); 199819#L924-1 assume !(1 == ~E_6~0); 199360#L929-1 assume !(1 == ~E_7~0); 199361#L1180-1 [2018-11-23 16:06:18,150 INFO L796 eck$LassoCheckResult]: Loop: 199361#L1180-1 assume !false; 200143#L1181 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret2, eval_#t~nondet3, eval_~tmp_ndt_1~0, eval_#t~nondet4, eval_~tmp_ndt_2~0, eval_#t~nondet5, eval_~tmp_ndt_3~0, eval_#t~nondet6, eval_~tmp_ndt_4~0, eval_#t~nondet7, eval_~tmp_ndt_5~0, eval_#t~nondet8, eval_~tmp_ndt_6~0, eval_#t~nondet9, eval_~tmp_ndt_7~0, eval_#t~nondet10, eval_~tmp_ndt_8~0, eval_~tmp~0;havoc eval_~tmp~0; 199496#L746 assume !false; 199783#L639 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~8;havoc exists_runnable_thread_~__retres1~8; 199784#L586 assume !(0 == ~m_st~0); 199855#L590 assume !(0 == ~t1_st~0); 199809#L594 assume !(0 == ~t2_st~0); 199411#L598 assume !(0 == ~t3_st~0); 199413#L602 assume !(0 == ~t4_st~0); 200133#L606 assume !(0 == ~t5_st~0); 199921#L610 assume !(0 == ~t6_st~0); 199878#L614 assume !(0 == ~t7_st~0);exists_runnable_thread_~__retres1~8 := 0; 199879#L628 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; 204858#L629 eval_#t~ret2 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret2;havoc eval_#t~ret2; 204764#L643 assume !(0 != eval_~tmp~0); 200076#L761 start_simulation_~kernel_st~0 := 2; 199676#L531-1 start_simulation_~kernel_st~0 := 3; 199677#L771-2 assume 0 == ~M_E~0;~M_E~0 := 1; 199781#L771-4 assume !(0 == ~T1_E~0); 199498#L776-3 assume !(0 == ~T2_E~0); 199499#L781-3 assume !(0 == ~T3_E~0); 199928#L786-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 199727#L791-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 199409#L796-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 199410#L801-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 200149#L806-3 assume 0 == ~E_M~0;~E_M~0 := 1; 199915#L811-3 assume !(0 == ~E_1~0); 199586#L816-3 assume !(0 == ~E_2~0); 199587#L821-3 assume !(0 == ~E_3~0); 200198#L826-3 assume 0 == ~E_4~0;~E_4~0 := 1; 200036#L831-3 assume 0 == ~E_5~0;~E_5~0 := 1; 199814#L836-3 assume 0 == ~E_6~0;~E_6~0 := 1; 199341#L841-3 assume 0 == ~E_7~0;~E_7~0 := 1; 199342#L846-3 havoc activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 199323#L378-27 assume !(1 == ~m_pc~0); 199325#L378-29 is_master_triggered_~__retres1~0 := 0; 199520#L389-9 is_master_triggered_#res := is_master_triggered_~__retres1~0; 199941#L390-9 activate_threads_#t~ret11 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 200041#L957-27 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 204153#L957-29 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 204152#L397-27 assume !(1 == ~t1_pc~0); 204149#L397-29 is_transmit1_triggered_~__retres1~1 := 0; 204148#L408-9 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 204147#L409-9 activate_threads_#t~ret12 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 204144#L965-27 assume !(0 != activate_threads_~tmp___0~0); 199882#L965-29 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 199883#L416-27 assume !(1 == ~t2_pc~0); 204138#L416-29 is_transmit2_triggered_~__retres1~2 := 0; 204137#L427-9 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 204136#L428-9 activate_threads_#t~ret13 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 199521#L973-27 assume !(0 != activate_threads_~tmp___1~0); 199522#L973-29 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 199529#L435-27 assume !(1 == ~t3_pc~0); 199856#L435-29 is_transmit3_triggered_~__retres1~3 := 0; 199443#L446-9 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 199444#L447-9 activate_threads_#t~ret14 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 200159#L981-27 assume !(0 != activate_threads_~tmp___2~0); 200160#L981-29 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 204128#L454-27 assume !(1 == ~t4_pc~0); 204126#L454-29 is_transmit4_triggered_~__retres1~4 := 0; 204124#L465-9 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 204123#L466-9 activate_threads_#t~ret15 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 204121#L989-27 assume !(0 != activate_threads_~tmp___3~0); 204119#L989-29 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 204118#L473-27 assume 1 == ~t5_pc~0; 204115#L474-9 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 204111#L484-9 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 204107#L485-9 activate_threads_#t~ret16 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 204105#L997-27 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 204104#L997-29 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 200264#L492-27 assume !(1 == ~t6_pc~0); 200265#L492-29 is_transmit6_triggered_~__retres1~6 := 0; 199886#L503-9 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 199775#L504-9 activate_threads_#t~ret17 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 199776#L1005-27 assume !(0 != activate_threads_~tmp___5~0); 199940#L1005-29 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 199946#L511-27 assume !(1 == ~t7_pc~0); 199435#L511-29 is_transmit7_triggered_~__retres1~7 := 0; 199478#L522-9 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 200047#L523-9 activate_threads_#t~ret18 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 199633#L1013-27 assume !(0 != activate_threads_~tmp___6~0); 199606#L1013-29 assume 1 == ~M_E~0;~M_E~0 := 2; 199607#L859-3 assume !(1 == ~T1_E~0); 199488#L864-3 assume !(1 == ~T2_E~0); 199489#L869-3 assume !(1 == ~T3_E~0); 199926#L874-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 199741#L879-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 199419#L884-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 199420#L889-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 200151#L894-3 assume 1 == ~E_M~0;~E_M~0 := 2; 199825#L899-3 assume !(1 == ~E_1~0); 199601#L904-3 assume !(1 == ~E_2~0); 199602#L909-3 assume !(1 == ~E_3~0); 200201#L914-3 assume 1 == ~E_4~0;~E_4~0 := 2; 200034#L919-3 assume 1 == ~E_5~0;~E_5~0 := 2; 199812#L924-3 assume 1 == ~E_6~0;~E_6~0 := 2; 199329#L929-3 assume 1 == ~E_7~0;~E_7~0 := 2; 199330#L934-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~8;havoc exists_runnable_thread_~__retres1~8; 200146#L586-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8 := 1; 199416#L628-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; 200067#L629-1 start_simulation_#t~ret20 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret20;havoc start_simulation_#t~ret20; 200068#L1199 assume !(0 == start_simulation_~tmp~3); 199943#L1199-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret19, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~8;havoc exists_runnable_thread_~__retres1~8; 200147#L586-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8 := 1; 199394#L628-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; 200071#L629-2 stop_simulation_#t~ret19 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret19;havoc stop_simulation_#t~ret19; 200072#L1154 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 200039#L1161 stop_simulation_#res := stop_simulation_~__retres2~0; 200018#L1162 start_simulation_#t~ret21 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret21;havoc start_simulation_#t~ret21; 199627#L1212 assume !(0 != start_simulation_~tmp___0~1); 199361#L1180-1 [2018-11-23 16:06:18,150 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 16:06:18,150 INFO L82 PathProgramCache]: Analyzing trace with hash 322056993, now seen corresponding path program 9 times [2018-11-23 16:06:18,150 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 16:06:18,150 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 16:06:18,151 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 16:06:18,151 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 16:06:18,151 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 16:06:18,155 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-23 16:06:18,160 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-23 16:06:18,176 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 16:06:18,176 INFO L82 PathProgramCache]: Analyzing trace with hash -1765691849, now seen corresponding path program 1 times [2018-11-23 16:06:18,177 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 16:06:18,177 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 16:06:18,177 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 16:06:18,177 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-23 16:06:18,177 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 16:06:18,182 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 16:06:18,238 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 16:06:18,238 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 16:06:18,238 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-11-23 16:06:18,239 INFO L811 eck$LassoCheckResult]: loop already infeasible [2018-11-23 16:06:18,239 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-11-23 16:06:18,239 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-11-23 16:06:18,239 INFO L87 Difference]: Start difference. First operand 5602 states and 7435 transitions. cyclomatic complexity: 1841 Second operand 5 states. [2018-11-23 16:06:18,386 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 16:06:18,387 INFO L93 Difference]: Finished difference Result 16129 states and 21192 transitions. [2018-11-23 16:06:18,389 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2018-11-23 16:06:18,389 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 16129 states and 21192 transitions. [2018-11-23 16:06:18,422 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 15816 [2018-11-23 16:06:18,443 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 16129 states to 16129 states and 21192 transitions. [2018-11-23 16:06:18,444 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 16129 [2018-11-23 16:06:18,450 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 16129 [2018-11-23 16:06:18,450 INFO L73 IsDeterministic]: Start isDeterministic. Operand 16129 states and 21192 transitions. [2018-11-23 16:06:18,456 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-23 16:06:18,456 INFO L705 BuchiCegarLoop]: Abstraction has 16129 states and 21192 transitions. [2018-11-23 16:06:18,462 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 16129 states and 21192 transitions. [2018-11-23 16:06:18,507 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 16129 to 5809. [2018-11-23 16:06:18,507 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 5809 states. [2018-11-23 16:06:18,514 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 5809 states to 5809 states and 7642 transitions. [2018-11-23 16:06:18,514 INFO L728 BuchiCegarLoop]: Abstraction has 5809 states and 7642 transitions. [2018-11-23 16:06:18,514 INFO L608 BuchiCegarLoop]: Abstraction has 5809 states and 7642 transitions. [2018-11-23 16:06:18,514 INFO L442 BuchiCegarLoop]: ======== Iteration 27============ [2018-11-23 16:06:18,514 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 5809 states and 7642 transitions. [2018-11-23 16:06:18,525 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 5680 [2018-11-23 16:06:18,525 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-23 16:06:18,525 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-23 16:06:18,526 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 16:06:18,526 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 16:06:18,527 INFO L794 eck$LassoCheckResult]: Stem: 221553#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; 221454#L-1 havoc main_#res;havoc main_~__retres1~9;havoc main_~__retres1~9;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 221455#L1143 havoc start_simulation_#t~ret20, start_simulation_#t~ret21, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 221428#L531 assume 1 == ~m_i~0;~m_st~0 := 0; 221429#L538-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 221727#L543-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 221624#L548-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 221430#L553-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 221431#L558-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 221814#L563-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 221616#L568-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 221412#L573-1 assume !(0 == ~M_E~0); 221413#L771-1 assume !(0 == ~T1_E~0); 221238#L776-1 assume !(0 == ~T2_E~0); 221239#L781-1 assume !(0 == ~T3_E~0); 221679#L786-1 assume !(0 == ~T4_E~0); 221500#L791-1 assume !(0 == ~T5_E~0); 221172#L796-1 assume !(0 == ~T6_E~0); 221173#L801-1 assume !(0 == ~T7_E~0); 221901#L806-1 assume !(0 == ~E_M~0); 221581#L811-1 assume !(0 == ~E_1~0); 221358#L816-1 assume !(0 == ~E_2~0); 221359#L821-1 assume !(0 == ~E_3~0); 221954#L826-1 assume !(0 == ~E_4~0); 221767#L831-1 assume !(0 == ~E_5~0); 221569#L836-1 assume !(0 == ~E_6~0); 221076#L841-1 assume !(0 == ~E_7~0); 221077#L846-1 havoc activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 221156#L378 assume !(1 == ~m_pc~0); 221128#L378-2 is_master_triggered_~__retres1~0 := 0; 221129#L389 is_master_triggered_#res := is_master_triggered_~__retres1~0; 221734#L390 activate_threads_#t~ret11 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 221983#L957 assume !(0 != activate_threads_~tmp~1); 221984#L957-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 221396#L397 assume !(1 == ~t1_pc~0); 221313#L397-2 is_transmit1_triggered_~__retres1~1 := 0; 221401#L408 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 221798#L409 activate_threads_#t~ret12 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 221584#L965 assume !(0 != activate_threads_~tmp___0~0); 221575#L965-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 221576#L416 assume !(1 == ~t2_pc~0); 221475#L416-2 is_transmit2_triggered_~__retres1~2 := 0; 221516#L427 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 221923#L428 activate_threads_#t~ret13 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 221098#L973 assume !(0 != activate_threads_~tmp___1~0); 221099#L973-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 221105#L435 assume !(1 == ~t3_pc~0); 221759#L435-2 is_transmit3_triggered_~__retres1~3 := 0; 221197#L446 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 221198#L447 activate_threads_#t~ret14 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 221838#L981 assume !(0 != activate_threads_~tmp___2~0); 221826#L981-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 221827#L454 assume !(1 == ~t4_pc~0); 221891#L454-2 is_transmit4_triggered_~__retres1~4 := 0; 221434#L465 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 221150#L466 activate_threads_#t~ret15 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 221151#L989 assume !(0 != activate_threads_~tmp___3~0); 221504#L989-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 221507#L473 assume !(1 == ~t5_pc~0); 221884#L473-2 is_transmit5_triggered_~__retres1~5 := 0; 221559#L484 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 221415#L485 activate_threads_#t~ret16 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 221416#L997 assume !(0 != activate_threads_~tmp___4~0); 222011#L997-2 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 222012#L492 assume !(1 == ~t6_pc~0); 222033#L492-2 is_transmit6_triggered_~__retres1~6 := 0; 221662#L503 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 221625#L504 activate_threads_#t~ret17 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 221626#L1005 assume !(0 != activate_threads_~tmp___5~0); 221886#L1005-2 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 221065#L511 assume !(1 == ~t7_pc~0); 221066#L511-2 is_transmit7_triggered_~__retres1~7 := 0; 221299#L522 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 221675#L523 activate_threads_#t~ret18 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 221551#L1013 assume !(0 != activate_threads_~tmp___6~0); 221544#L1013-2 assume !(1 == ~M_E~0); 221545#L859-1 assume !(1 == ~T1_E~0); 221254#L864-1 assume !(1 == ~T2_E~0); 221255#L869-1 assume !(1 == ~T3_E~0); 221676#L874-1 assume !(1 == ~T4_E~0); 221492#L879-1 assume !(1 == ~T5_E~0); 221168#L884-1 assume !(1 == ~T6_E~0); 221169#L889-1 assume !(1 == ~T7_E~0); 221899#L894-1 assume !(1 == ~E_M~0); 221577#L899-1 assume !(1 == ~E_1~0); 221351#L904-1 assume !(1 == ~E_2~0); 221352#L909-1 assume !(1 == ~E_3~0); 221957#L914-1 assume !(1 == ~E_4~0); 221770#L919-1 assume !(1 == ~E_5~0); 221574#L924-1 assume !(1 == ~E_6~0); 221109#L929-1 assume !(1 == ~E_7~0); 221110#L1180-1 [2018-11-23 16:06:18,527 INFO L796 eck$LassoCheckResult]: Loop: 221110#L1180-1 assume !false; 221888#L1181 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret2, eval_#t~nondet3, eval_~tmp_ndt_1~0, eval_#t~nondet4, eval_~tmp_ndt_2~0, eval_#t~nondet5, eval_~tmp_ndt_3~0, eval_#t~nondet6, eval_~tmp_ndt_4~0, eval_#t~nondet7, eval_~tmp_ndt_5~0, eval_#t~nondet8, eval_~tmp_ndt_6~0, eval_#t~nondet9, eval_~tmp_ndt_7~0, eval_#t~nondet10, eval_~tmp_ndt_8~0, eval_~tmp~0;havoc eval_~tmp~0; 221242#L746 assume !false; 221541#L639 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~8;havoc exists_runnable_thread_~__retres1~8; 221542#L586 assume !(0 == ~m_st~0); 221613#L590 assume !(0 == ~t1_st~0); 221565#L594 assume !(0 == ~t2_st~0); 221162#L598 assume !(0 == ~t3_st~0); 221164#L602 assume !(0 == ~t4_st~0); 221876#L606 assume !(0 == ~t5_st~0); 221672#L610 assume !(0 == ~t6_st~0); 221633#L614 assume !(0 == ~t7_st~0);exists_runnable_thread_~__retres1~8 := 0; 221634#L628 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; 226835#L629 eval_#t~ret2 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret2;havoc eval_#t~ret2; 226834#L643 assume !(0 != eval_~tmp~0); 221817#L761 start_simulation_~kernel_st~0 := 2; 221432#L531-1 start_simulation_~kernel_st~0 := 3; 221433#L771-2 assume 0 == ~M_E~0;~M_E~0 := 1; 221538#L771-4 assume !(0 == ~T1_E~0); 221244#L776-3 assume !(0 == ~T2_E~0); 221245#L781-3 assume !(0 == ~T3_E~0); 221680#L786-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 221681#L791-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 226739#L796-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 222025#L801-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 221897#L806-3 assume 0 == ~E_M~0;~E_M~0 := 1; 221898#L811-3 assume !(0 == ~E_1~0); 226737#L816-3 assume !(0 == ~E_2~0); 222007#L821-3 assume !(0 == ~E_3~0); 221955#L826-3 assume 0 == ~E_4~0;~E_4~0 := 1; 221768#L831-3 assume 0 == ~E_5~0;~E_5~0 := 1; 221570#L836-3 assume 0 == ~E_6~0;~E_6~0 := 1; 221087#L841-3 assume 0 == ~E_7~0;~E_7~0 := 1; 221088#L846-3 havoc activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 221068#L378-27 assume !(1 == ~m_pc~0); 221070#L378-29 is_master_triggered_~__retres1~0 := 0; 221694#L389-9 is_master_triggered_#res := is_master_triggered_~__retres1~0; 221695#L390-9 activate_threads_#t~ret11 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 221962#L957-27 assume !(0 != activate_threads_~tmp~1); 221963#L957-29 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 226732#L397-27 assume !(1 == ~t1_pc~0); 226730#L397-29 is_transmit1_triggered_~__retres1~1 := 0; 226729#L408-9 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 226728#L409-9 activate_threads_#t~ret12 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 226727#L965-27 assume !(0 != activate_threads_~tmp___0~0); 226726#L965-29 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 226725#L416-27 assume !(1 == ~t2_pc~0); 226723#L416-29 is_transmit2_triggered_~__retres1~2 := 0; 226722#L427-9 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 226721#L428-9 activate_threads_#t~ret13 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 226720#L973-27 assume !(0 != activate_threads_~tmp___1~0); 221276#L973-29 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 221277#L435-27 assume !(1 == ~t3_pc~0); 221614#L435-29 is_transmit3_triggered_~__retres1~3 := 0; 221194#L446-9 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 221195#L447-9 activate_threads_#t~ret14 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 221908#L981-27 assume !(0 != activate_threads_~tmp___2~0); 221902#L981-29 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 221742#L454-27 assume !(1 == ~t4_pc~0); 221726#L454-29 is_transmit4_triggered_~__retres1~4 := 0; 221419#L465-9 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 221115#L466-9 activate_threads_#t~ret15 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 221116#L989-27 assume !(0 != activate_threads_~tmp___3~0); 221448#L989-29 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 221451#L473-27 assume 1 == ~t5_pc~0; 221851#L474-9 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 221852#L484-9 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 226592#L485-9 activate_threads_#t~ret16 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 226593#L997-27 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 221987#L997-29 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 221988#L492-27 assume !(1 == ~t6_pc~0); 222028#L492-29 is_transmit6_triggered_~__retres1~6 := 0; 221642#L503-9 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 221643#L504-9 activate_threads_#t~ret17 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 221692#L1005-27 assume !(0 != activate_threads_~tmp___5~0); 221693#L1005-29 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 221225#L511-27 assume 1 == ~t7_pc~0; 221186#L512-9 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7 := 1; 221187#L522-9 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 226784#L523-9 activate_threads_#t~ret18 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 226783#L1013-27 assume 0 != activate_threads_~tmp___6~0;~t7_st~0 := 0; 221361#L1013-29 assume 1 == ~M_E~0;~M_E~0 := 2; 221362#L859-3 assume !(1 == ~T1_E~0); 221236#L864-3 assume !(1 == ~T2_E~0); 221237#L869-3 assume !(1 == ~T3_E~0); 221677#L874-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 221678#L879-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 226685#L884-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 226684#L889-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 226683#L894-3 assume 1 == ~E_M~0;~E_M~0 := 2; 226681#L899-3 assume !(1 == ~E_1~0); 226680#L904-3 assume !(1 == ~E_2~0); 226679#L909-3 assume !(1 == ~E_3~0); 226678#L914-3 assume 1 == ~E_4~0;~E_4~0 := 2; 226677#L919-3 assume 1 == ~E_5~0;~E_5~0 := 2; 226676#L924-3 assume 1 == ~E_6~0;~E_6~0 := 2; 226675#L929-3 assume 1 == ~E_7~0;~E_7~0 := 2; 226674#L934-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~8;havoc exists_runnable_thread_~__retres1~8; 226673#L586-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8 := 1; 226665#L628-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; 226664#L629-1 start_simulation_#t~ret20 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret20;havoc start_simulation_#t~ret20; 226662#L1199 assume !(0 == start_simulation_~tmp~3); 226663#L1199-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret19, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~8;havoc exists_runnable_thread_~__retres1~8; 226779#L586-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8 := 1; 226770#L628-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; 221812#L629-2 stop_simulation_#t~ret19 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret19;havoc stop_simulation_#t~ret19; 221813#L1154 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 221771#L1161 stop_simulation_#res := stop_simulation_~__retres2~0; 221757#L1162 start_simulation_#t~ret21 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret21;havoc start_simulation_#t~ret21; 221382#L1212 assume !(0 != start_simulation_~tmp___0~1); 221110#L1180-1 [2018-11-23 16:06:18,527 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 16:06:18,527 INFO L82 PathProgramCache]: Analyzing trace with hash 322056993, now seen corresponding path program 10 times [2018-11-23 16:06:18,527 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 16:06:18,528 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 16:06:18,528 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 16:06:18,528 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 16:06:18,528 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 16:06:18,533 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-23 16:06:18,538 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-23 16:06:18,554 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 16:06:18,554 INFO L82 PathProgramCache]: Analyzing trace with hash -82773032, now seen corresponding path program 1 times [2018-11-23 16:06:18,554 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 16:06:18,554 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 16:06:18,555 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 16:06:18,555 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-23 16:06:18,555 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 16:06:18,560 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 16:06:18,598 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 16:06:18,598 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 16:06:18,598 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-23 16:06:18,598 INFO L811 eck$LassoCheckResult]: loop already infeasible [2018-11-23 16:06:18,599 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-23 16:06:18,599 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-23 16:06:18,599 INFO L87 Difference]: Start difference. First operand 5809 states and 7642 transitions. cyclomatic complexity: 1841 Second operand 3 states. [2018-11-23 16:06:18,660 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 16:06:18,660 INFO L93 Difference]: Finished difference Result 10937 states and 14178 transitions. [2018-11-23 16:06:18,661 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-23 16:06:18,662 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 10937 states and 14178 transitions. [2018-11-23 16:06:18,687 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 10784 [2018-11-23 16:06:18,703 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 10937 states to 10937 states and 14178 transitions. [2018-11-23 16:06:18,703 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 10937 [2018-11-23 16:06:18,708 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 10937 [2018-11-23 16:06:18,708 INFO L73 IsDeterministic]: Start isDeterministic. Operand 10937 states and 14178 transitions. [2018-11-23 16:06:18,713 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-23 16:06:18,713 INFO L705 BuchiCegarLoop]: Abstraction has 10937 states and 14178 transitions. [2018-11-23 16:06:18,718 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 10937 states and 14178 transitions. [2018-11-23 16:06:18,813 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 10937 to 10465. [2018-11-23 16:06:18,813 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 10465 states. [2018-11-23 16:06:18,821 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 10465 states to 10465 states and 13594 transitions. [2018-11-23 16:06:18,821 INFO L728 BuchiCegarLoop]: Abstraction has 10465 states and 13594 transitions. [2018-11-23 16:06:18,821 INFO L608 BuchiCegarLoop]: Abstraction has 10465 states and 13594 transitions. [2018-11-23 16:06:18,821 INFO L442 BuchiCegarLoop]: ======== Iteration 28============ [2018-11-23 16:06:18,821 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 10465 states and 13594 transitions. [2018-11-23 16:06:18,838 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 10312 [2018-11-23 16:06:18,838 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-23 16:06:18,838 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-23 16:06:18,839 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 16:06:18,839 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 16:06:18,839 INFO L794 eck$LassoCheckResult]: Stem: 238292#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; 238194#L-1 havoc main_#res;havoc main_~__retres1~9;havoc main_~__retres1~9;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 238195#L1143 havoc start_simulation_#t~ret20, start_simulation_#t~ret21, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 238168#L531 assume 1 == ~m_i~0;~m_st~0 := 0; 238169#L538-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 238469#L543-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 238363#L548-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 238170#L553-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 238171#L558-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 238550#L563-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 238353#L568-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 238153#L573-1 assume !(0 == ~M_E~0); 238154#L771-1 assume !(0 == ~T1_E~0); 237986#L776-1 assume !(0 == ~T2_E~0); 237987#L781-1 assume !(0 == ~T3_E~0); 238422#L786-1 assume !(0 == ~T4_E~0); 238238#L791-1 assume !(0 == ~T5_E~0); 237921#L796-1 assume !(0 == ~T6_E~0); 237922#L801-1 assume !(0 == ~T7_E~0); 238634#L806-1 assume !(0 == ~E_M~0); 238322#L811-1 assume !(0 == ~E_1~0); 238098#L816-1 assume !(0 == ~E_2~0); 238099#L821-1 assume !(0 == ~E_3~0); 238671#L826-1 assume !(0 == ~E_4~0); 238511#L831-1 assume !(0 == ~E_5~0); 238310#L836-1 assume !(0 == ~E_6~0); 237832#L841-1 assume !(0 == ~E_7~0); 237833#L846-1 havoc activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 237905#L378 assume !(1 == ~m_pc~0); 237879#L378-2 is_master_triggered_~__retres1~0 := 0; 237880#L389 is_master_triggered_#res := is_master_triggered_~__retres1~0; 238478#L390 activate_threads_#t~ret11 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 238702#L957 assume !(0 != activate_threads_~tmp~1); 238703#L957-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 238136#L397 assume !(1 == ~t1_pc~0); 238054#L397-2 is_transmit1_triggered_~__retres1~1 := 0; 238142#L408 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 238535#L409 activate_threads_#t~ret12 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 238325#L965 assume !(0 != activate_threads_~tmp___0~0); 238316#L965-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 238317#L416 assume !(1 == ~t2_pc~0); 238215#L416-2 is_transmit2_triggered_~__retres1~2 := 0; 238254#L427 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 238652#L428 activate_threads_#t~ret13 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 237849#L973 assume !(0 != activate_threads_~tmp___1~0); 237850#L973-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 237857#L435 assume !(1 == ~t3_pc~0); 238497#L435-2 is_transmit3_triggered_~__retres1~3 := 0; 237949#L446 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 237950#L447 activate_threads_#t~ret14 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 238574#L981 assume !(0 != activate_threads_~tmp___2~0); 238564#L981-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 238565#L454 assume !(1 == ~t4_pc~0); 238625#L454-2 is_transmit4_triggered_~__retres1~4 := 0; 238174#L465 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 237899#L466 activate_threads_#t~ret15 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 237900#L989 assume !(0 != activate_threads_~tmp___3~0); 238242#L989-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 238245#L473 assume !(1 == ~t5_pc~0); 238618#L473-2 is_transmit5_triggered_~__retres1~5 := 0; 238297#L484 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 238156#L485 activate_threads_#t~ret16 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 238157#L997 assume !(0 != activate_threads_~tmp___4~0); 238730#L997-2 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 238731#L492 assume !(1 == ~t6_pc~0); 238747#L492-2 is_transmit6_triggered_~__retres1~6 := 0; 238401#L503 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 238364#L504 activate_threads_#t~ret17 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 238365#L1005 assume !(0 != activate_threads_~tmp___5~0); 238621#L1005-2 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 237820#L511 assume !(1 == ~t7_pc~0); 237821#L511-2 is_transmit7_triggered_~__retres1~7 := 0; 238043#L522 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 238748#L523 activate_threads_#t~ret18 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 238289#L1013 assume !(0 != activate_threads_~tmp___6~0); 238281#L1013-2 assume !(1 == ~M_E~0); 238282#L859-1 assume !(1 == ~T1_E~0); 238001#L864-1 assume !(1 == ~T2_E~0); 238002#L869-1 assume !(1 == ~T3_E~0); 238420#L874-1 assume !(1 == ~T4_E~0); 238232#L879-1 assume !(1 == ~T5_E~0); 237917#L884-1 assume !(1 == ~T6_E~0); 237918#L889-1 assume !(1 == ~T7_E~0); 238632#L894-1 assume !(1 == ~E_M~0); 238320#L899-1 assume !(1 == ~E_1~0); 238091#L904-1 assume !(1 == ~E_2~0); 238092#L909-1 assume !(1 == ~E_3~0); 238675#L914-1 assume !(1 == ~E_4~0); 238513#L919-1 assume !(1 == ~E_5~0); 238315#L924-1 assume !(1 == ~E_6~0); 237858#L929-1 assume !(1 == ~E_7~0); 237859#L1180-1 [2018-11-23 16:06:18,839 INFO L796 eck$LassoCheckResult]: Loop: 237859#L1180-1 assume !false; 243680#L1181 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret2, eval_#t~nondet3, eval_~tmp_ndt_1~0, eval_#t~nondet4, eval_~tmp_ndt_2~0, eval_#t~nondet5, eval_~tmp_ndt_3~0, eval_#t~nondet6, eval_~tmp_ndt_4~0, eval_#t~nondet7, eval_~tmp_ndt_5~0, eval_#t~nondet8, eval_~tmp_ndt_6~0, eval_#t~nondet9, eval_~tmp_ndt_7~0, eval_#t~nondet10, eval_~tmp_ndt_8~0, eval_~tmp~0;havoc eval_~tmp~0; 243674#L746 assume !false; 243672#L639 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~8;havoc exists_runnable_thread_~__retres1~8; 243669#L586 assume !(0 == ~m_st~0); 243670#L590 assume !(0 == ~t1_st~0); 244499#L594 assume !(0 == ~t2_st~0); 244497#L598 assume !(0 == ~t3_st~0); 244495#L602 assume !(0 == ~t4_st~0); 244493#L606 assume !(0 == ~t5_st~0); 244490#L610 assume !(0 == ~t6_st~0); 244475#L614 assume !(0 == ~t7_st~0);exists_runnable_thread_~__retres1~8 := 0; 244465#L628 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; 244456#L629 eval_#t~ret2 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret2;havoc eval_#t~ret2; 244452#L643 assume !(0 != eval_~tmp~0); 244448#L761 start_simulation_~kernel_st~0 := 2; 244442#L531-1 start_simulation_~kernel_st~0 := 3; 244438#L771-2 assume 0 == ~M_E~0;~M_E~0 := 1; 244434#L771-4 assume !(0 == ~T1_E~0); 244430#L776-3 assume !(0 == ~T2_E~0); 244427#L781-3 assume !(0 == ~T3_E~0); 244424#L786-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 244420#L791-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 244416#L796-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 244412#L801-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 244408#L806-3 assume 0 == ~E_M~0;~E_M~0 := 1; 244403#L811-3 assume !(0 == ~E_1~0); 244399#L816-3 assume !(0 == ~E_2~0); 244395#L821-3 assume !(0 == ~E_3~0); 244390#L826-3 assume 0 == ~E_4~0;~E_4~0 := 1; 243871#L831-3 assume 0 == ~E_5~0;~E_5~0 := 1; 243868#L836-3 assume 0 == ~E_6~0;~E_6~0 := 1; 243866#L841-3 assume 0 == ~E_7~0;~E_7~0 := 1; 243864#L846-3 havoc activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 243862#L378-27 assume 1 == ~m_pc~0; 243859#L379-9 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 243857#L389-9 is_master_triggered_#res := is_master_triggered_~__retres1~0; 243853#L390-9 activate_threads_#t~ret11 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 243850#L957-27 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 243848#L957-29 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 243846#L397-27 assume !(1 == ~t1_pc~0); 243842#L397-29 is_transmit1_triggered_~__retres1~1 := 0; 243840#L408-9 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 243838#L409-9 activate_threads_#t~ret12 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 243836#L965-27 assume !(0 != activate_threads_~tmp___0~0); 243834#L965-29 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 243832#L416-27 assume !(1 == ~t2_pc~0); 243829#L416-29 is_transmit2_triggered_~__retres1~2 := 0; 243827#L427-9 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 243825#L428-9 activate_threads_#t~ret13 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 243823#L973-27 assume !(0 != activate_threads_~tmp___1~0); 243821#L973-29 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 243819#L435-27 assume !(1 == ~t3_pc~0); 243817#L435-29 is_transmit3_triggered_~__retres1~3 := 0; 243815#L446-9 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 243811#L447-9 activate_threads_#t~ret14 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 243809#L981-27 assume !(0 != activate_threads_~tmp___2~0); 243807#L981-29 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 243805#L454-27 assume !(1 == ~t4_pc~0); 243802#L454-29 is_transmit4_triggered_~__retres1~4 := 0; 243800#L465-9 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 243798#L466-9 activate_threads_#t~ret15 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 243796#L989-27 assume !(0 != activate_threads_~tmp___3~0); 243794#L989-29 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 243792#L473-27 assume 1 == ~t5_pc~0; 243790#L474-9 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 243791#L484-9 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 244018#L485-9 activate_threads_#t~ret16 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 243779#L997-27 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 243777#L997-29 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 243775#L492-27 assume !(1 == ~t6_pc~0); 243772#L492-29 is_transmit6_triggered_~__retres1~6 := 0; 243771#L503-9 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 243767#L504-9 activate_threads_#t~ret17 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 243765#L1005-27 assume !(0 != activate_threads_~tmp___5~0); 243764#L1005-29 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 243760#L511-27 assume 1 == ~t7_pc~0; 243758#L512-9 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7 := 1; 243759#L522-9 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 244206#L523-9 activate_threads_#t~ret18 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 243747#L1013-27 assume 0 != activate_threads_~tmp___6~0;~t7_st~0 := 0; 243745#L1013-29 assume 1 == ~M_E~0;~M_E~0 := 2; 243743#L859-3 assume !(1 == ~T1_E~0); 243740#L864-3 assume !(1 == ~T2_E~0); 243738#L869-3 assume !(1 == ~T3_E~0); 243736#L874-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 243735#L879-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 243734#L884-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 243732#L889-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 243731#L894-3 assume 1 == ~E_M~0;~E_M~0 := 2; 243730#L899-3 assume !(1 == ~E_1~0); 243729#L904-3 assume !(1 == ~E_2~0); 243725#L909-3 assume !(1 == ~E_3~0); 243723#L914-3 assume 1 == ~E_4~0;~E_4~0 := 2; 243721#L919-3 assume 1 == ~E_5~0;~E_5~0 := 2; 243719#L924-3 assume 1 == ~E_6~0;~E_6~0 := 2; 243714#L929-3 assume 1 == ~E_7~0;~E_7~0 := 2; 243712#L934-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~8;havoc exists_runnable_thread_~__retres1~8; 243710#L586-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8 := 1; 243707#L628-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; 243705#L629-1 start_simulation_#t~ret20 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret20;havoc start_simulation_#t~ret20; 243702#L1199 assume !(0 == start_simulation_~tmp~3); 243699#L1199-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret19, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~8;havoc exists_runnable_thread_~__retres1~8; 243696#L586-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8 := 1; 243694#L628-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; 243691#L629-2 stop_simulation_#t~ret19 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret19;havoc stop_simulation_#t~ret19; 243689#L1154 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 243687#L1161 stop_simulation_#res := stop_simulation_~__retres2~0; 243685#L1162 start_simulation_#t~ret21 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret21;havoc start_simulation_#t~ret21; 243683#L1212 assume !(0 != start_simulation_~tmp___0~1); 237859#L1180-1 [2018-11-23 16:06:18,839 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 16:06:18,840 INFO L82 PathProgramCache]: Analyzing trace with hash 322056993, now seen corresponding path program 11 times [2018-11-23 16:06:18,840 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 16:06:18,840 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 16:06:18,840 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 16:06:18,840 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 16:06:18,840 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 16:06:18,844 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-23 16:06:18,849 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-23 16:06:18,866 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 16:06:18,866 INFO L82 PathProgramCache]: Analyzing trace with hash -238791685, now seen corresponding path program 1 times [2018-11-23 16:06:18,866 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 16:06:18,866 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 16:06:18,866 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 16:06:18,867 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-23 16:06:18,867 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 16:06:18,871 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-23 16:06:18,876 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-23 16:06:18,892 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 16:06:18,892 INFO L82 PathProgramCache]: Analyzing trace with hash -1359933669, now seen corresponding path program 1 times [2018-11-23 16:06:18,892 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 16:06:18,892 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 16:06:18,892 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 16:06:18,892 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 16:06:18,893 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 16:06:18,898 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 16:06:18,943 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 16:06:18,943 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 16:06:18,943 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-23 16:06:19,568 WARN L180 SmtUtils]: Spent 617.00 ms on a formula simplification. DAG size of input: 241 DAG size of output: 224 [2018-11-23 16:06:19,768 WARN L180 SmtUtils]: Spent 192.00 ms on a formula simplification that was a NOOP. DAG size: 192 [2018-11-23 16:06:19,776 INFO L216 LassoAnalysis]: Preferences: [2018-11-23 16:06:19,777 INFO L124 ssoRankerPreferences]: Compute integeral hull: false [2018-11-23 16:06:19,777 INFO L125 ssoRankerPreferences]: Enable LassoPartitioneer: true [2018-11-23 16:06:19,777 INFO L126 ssoRankerPreferences]: Term annotations enabled: false [2018-11-23 16:06:19,777 INFO L127 ssoRankerPreferences]: Use exernal solver: true [2018-11-23 16:06:19,777 INFO L128 ssoRankerPreferences]: SMT solver command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2018-11-23 16:06:19,777 INFO L129 ssoRankerPreferences]: Dump SMT script to file: false [2018-11-23 16:06:19,777 INFO L130 ssoRankerPreferences]: Path of dumped script: [2018-11-23 16:06:19,777 INFO L131 ssoRankerPreferences]: Filename of dumped script: token_ring.07_false-unreach-call_false-termination.cil.c_Iteration28_Loop [2018-11-23 16:06:19,777 INFO L132 ssoRankerPreferences]: MapElimAlgo: Frank [2018-11-23 16:06:19,778 INFO L282 LassoAnalysis]: Starting lasso preprocessing... [2018-11-23 16:06:19,797 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 16:06:19,807 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 16:06:19,808 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 16:06:19,810 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 16:06:19,815 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 16:06:19,818 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 16:06:19,820 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 16:06:19,823 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 16:06:19,824 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 16:06:19,826 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 16:06:19,828 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 16:06:19,830 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 16:06:19,833 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 16:06:19,835 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 16:06:19,838 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 16:06:19,842 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 16:06:19,846 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 16:06:19,848 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 16:06:19,850 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 16:06:19,853 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 16:06:19,855 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 16:06:19,856 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 16:06:19,857 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 16:06:19,861 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 16:06:19,865 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 16:06:19,869 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 16:06:19,896 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 16:06:19,901 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 16:06:19,903 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 16:06:19,906 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 16:06:19,909 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 16:06:19,913 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 16:06:19,914 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 16:06:19,915 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 16:06:19,917 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 16:06:19,921 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 16:06:19,922 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 16:06:19,924 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 16:06:19,925 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 16:06:19,927 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 16:06:19,937 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 16:06:19,938 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 16:06:19,940 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 16:06:19,945 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 16:06:19,947 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 16:06:19,949 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 16:06:19,950 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 16:06:19,959 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 16:06:19,960 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 16:06:19,963 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 16:06:19,965 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 16:06:19,985 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 16:06:19,987 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 16:06:19,990 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 16:06:19,991 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 16:06:19,995 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 16:06:19,998 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 16:06:20,001 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 16:06:20,005 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 16:06:20,007 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 16:06:20,012 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 16:06:20,015 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 16:06:20,017 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 16:06:20,021 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 16:06:20,023 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 16:06:20,027 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 16:06:20,032 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 16:06:20,034 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 16:06:20,039 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 16:06:20,041 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 16:06:20,055 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 16:06:20,058 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 16:06:20,072 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 16:06:20,081 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 16:06:20,083 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 16:06:20,539 INFO L300 LassoAnalysis]: Preprocessing complete. [2018-11-23 16:06:20,540 INFO L412 LassoAnalysis]: Checking for nontermination... No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_0fe0e757-a0d1-4897-81ed-84240e247463/bin-2019/uautomizer/z3 Starting monitored process 2 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 2 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2018-11-23 16:06:20,555 INFO L151 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2018-11-23 16:06:20,555 INFO L163 nArgumentSynthesizer]: Using integer mode. [2018-11-23 16:06:20,566 INFO L445 LassoAnalysis]: Proved nontermination for one component. [2018-11-23 16:06:20,566 INFO L448 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {ULTIMATE.start_stop_simulation_~tmp~2=1, ULTIMATE.start_exists_runnable_thread_#res=1, ULTIMATE.start_exists_runnable_thread_~__retres1~8=1} Honda state: {ULTIMATE.start_stop_simulation_~tmp~2=1, ULTIMATE.start_exists_runnable_thread_#res=1, ULTIMATE.start_exists_runnable_thread_~__retres1~8=1} Generalized eigenvectors: [] Lambdas: [] Nus: [] No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_0fe0e757-a0d1-4897-81ed-84240e247463/bin-2019/uautomizer/z3 Starting monitored process 3 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 3 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2018-11-23 16:06:20,588 INFO L151 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2018-11-23 16:06:20,588 INFO L163 nArgumentSynthesizer]: Using integer mode. [2018-11-23 16:06:20,590 INFO L445 LassoAnalysis]: Proved nontermination for one component. [2018-11-23 16:06:20,591 INFO L448 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {ULTIMATE.start_eval_~tmp_ndt_7~0=0} Honda state: {ULTIMATE.start_eval_~tmp_ndt_7~0=0} Generalized eigenvectors: [] Lambdas: [] Nus: [] No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_0fe0e757-a0d1-4897-81ed-84240e247463/bin-2019/uautomizer/z3 Starting monitored process 4 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 4 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2018-11-23 16:06:20,607 INFO L151 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2018-11-23 16:06:20,607 INFO L163 nArgumentSynthesizer]: Using integer mode. [2018-11-23 16:06:20,610 INFO L445 LassoAnalysis]: Proved nontermination for one component. [2018-11-23 16:06:20,610 INFO L448 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {~t4_st~0=-1} Honda state: {~t4_st~0=-1} Generalized eigenvectors: [] Lambdas: [] Nus: [] No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_0fe0e757-a0d1-4897-81ed-84240e247463/bin-2019/uautomizer/z3 Starting monitored process 5 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 5 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2018-11-23 16:06:20,636 INFO L151 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2018-11-23 16:06:20,636 INFO L163 nArgumentSynthesizer]: Using integer mode. [2018-11-23 16:06:20,643 INFO L445 LassoAnalysis]: Proved nontermination for one component. [2018-11-23 16:06:20,643 INFO L448 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {ULTIMATE.start_stop_simulation_~__retres2~0=0, ULTIMATE.start_start_simulation_~tmp___0~1=0, ULTIMATE.start_stop_simulation_#res=0} Honda state: {ULTIMATE.start_stop_simulation_~__retres2~0=0, ULTIMATE.start_start_simulation_~tmp___0~1=0, ULTIMATE.start_stop_simulation_#res=0} Generalized eigenvectors: [] Lambdas: [] Nus: [] No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_0fe0e757-a0d1-4897-81ed-84240e247463/bin-2019/uautomizer/z3 Starting monitored process 6 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 6 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2018-11-23 16:06:20,664 INFO L151 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2018-11-23 16:06:20,664 INFO L163 nArgumentSynthesizer]: Using integer mode. [2018-11-23 16:06:20,667 INFO L445 LassoAnalysis]: Proved nontermination for one component. [2018-11-23 16:06:20,667 INFO L448 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {ULTIMATE.start_stop_simulation_#t~ret19=0} Honda state: {ULTIMATE.start_stop_simulation_#t~ret19=0} Generalized eigenvectors: [] Lambdas: [] Nus: [] No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_0fe0e757-a0d1-4897-81ed-84240e247463/bin-2019/uautomizer/z3 Starting monitored process 7 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 7 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2018-11-23 16:06:20,699 INFO L151 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2018-11-23 16:06:20,699 INFO L163 nArgumentSynthesizer]: Using integer mode. [2018-11-23 16:06:20,703 INFO L445 LassoAnalysis]: Proved nontermination for one component. [2018-11-23 16:06:20,703 INFO L448 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {~m_pc~0=1} Honda state: {~m_pc~0=1} Generalized eigenvectors: [] Lambdas: [] Nus: [] No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_0fe0e757-a0d1-4897-81ed-84240e247463/bin-2019/uautomizer/z3 Starting monitored process 8 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 8 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2018-11-23 16:06:20,732 INFO L151 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2018-11-23 16:06:20,732 INFO L163 nArgumentSynthesizer]: Using integer mode. [2018-11-23 16:06:20,738 INFO L445 LassoAnalysis]: Proved nontermination for one component. [2018-11-23 16:06:20,739 INFO L448 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {~E_3~0=-5} Honda state: {~E_3~0=-5} Generalized eigenvectors: [] Lambdas: [] Nus: [] No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_0fe0e757-a0d1-4897-81ed-84240e247463/bin-2019/uautomizer/z3 Starting monitored process 9 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 9 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2018-11-23 16:06:20,765 INFO L151 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2018-11-23 16:06:20,765 INFO L163 nArgumentSynthesizer]: Using integer mode. [2018-11-23 16:06:20,775 INFO L445 LassoAnalysis]: Proved nontermination for one component. [2018-11-23 16:06:20,775 INFO L448 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {ULTIMATE.start_activate_threads_#t~ret14=0} Honda state: {ULTIMATE.start_activate_threads_#t~ret14=0} Generalized eigenvectors: [] Lambdas: [] Nus: [] No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_0fe0e757-a0d1-4897-81ed-84240e247463/bin-2019/uautomizer/z3 Starting monitored process 10 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 10 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2018-11-23 16:06:20,802 INFO L151 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2018-11-23 16:06:20,803 INFO L163 nArgumentSynthesizer]: Using integer mode. [2018-11-23 16:06:20,807 INFO L445 LassoAnalysis]: Proved nontermination for one component. [2018-11-23 16:06:20,807 INFO L448 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {ULTIMATE.start_activate_threads_~tmp___1~0=0} Honda state: {ULTIMATE.start_activate_threads_~tmp___1~0=0} Generalized eigenvectors: [] Lambdas: [] Nus: [] No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_0fe0e757-a0d1-4897-81ed-84240e247463/bin-2019/uautomizer/z3 Starting monitored process 11 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 11 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2018-11-23 16:06:20,823 INFO L151 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2018-11-23 16:06:20,823 INFO L163 nArgumentSynthesizer]: Using integer mode. [2018-11-23 16:06:20,825 INFO L445 LassoAnalysis]: Proved nontermination for one component. [2018-11-23 16:06:20,825 INFO L448 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {~t7_pc~0=1} Honda state: {~t7_pc~0=1} Generalized eigenvectors: [] Lambdas: [] Nus: [] No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_0fe0e757-a0d1-4897-81ed-84240e247463/bin-2019/uautomizer/z3 Starting monitored process 12 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 12 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2018-11-23 16:06:20,841 INFO L151 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2018-11-23 16:06:20,841 INFO L163 nArgumentSynthesizer]: Using integer mode. [2018-11-23 16:06:20,844 INFO L445 LassoAnalysis]: Proved nontermination for one component. [2018-11-23 16:06:20,844 INFO L448 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {ULTIMATE.start_eval_~tmp_ndt_8~0=0} Honda state: {ULTIMATE.start_eval_~tmp_ndt_8~0=0} Generalized eigenvectors: [] Lambdas: [] Nus: [] No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_0fe0e757-a0d1-4897-81ed-84240e247463/bin-2019/uautomizer/z3 Starting monitored process 13 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 13 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2018-11-23 16:06:20,860 INFO L151 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2018-11-23 16:06:20,860 INFO L163 nArgumentSynthesizer]: Using integer mode. [2018-11-23 16:06:20,863 INFO L445 LassoAnalysis]: Proved nontermination for one component. [2018-11-23 16:06:20,863 INFO L448 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {ULTIMATE.start_activate_threads_~tmp___0~0=0, ULTIMATE.start_is_transmit1_triggered_~__retres1~1=0, ULTIMATE.start_is_transmit1_triggered_#res=0} Honda state: {ULTIMATE.start_activate_threads_~tmp___0~0=0, ULTIMATE.start_is_transmit1_triggered_~__retres1~1=0, ULTIMATE.start_is_transmit1_triggered_#res=0} Generalized eigenvectors: [] Lambdas: [] Nus: [] No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_0fe0e757-a0d1-4897-81ed-84240e247463/bin-2019/uautomizer/z3 Starting monitored process 14 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 14 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2018-11-23 16:06:20,879 INFO L151 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2018-11-23 16:06:20,879 INFO L163 nArgumentSynthesizer]: Using integer mode. [2018-11-23 16:06:20,881 INFO L445 LassoAnalysis]: Proved nontermination for one component. [2018-11-23 16:06:20,882 INFO L448 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {ULTIMATE.start_eval_#t~nondet9=0} Honda state: {ULTIMATE.start_eval_#t~nondet9=0} Generalized eigenvectors: [] Lambdas: [] Nus: [] No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_0fe0e757-a0d1-4897-81ed-84240e247463/bin-2019/uautomizer/z3 Starting monitored process 15 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 15 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2018-11-23 16:06:20,898 INFO L151 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2018-11-23 16:06:20,899 INFO L163 nArgumentSynthesizer]: Using integer mode. [2018-11-23 16:06:20,901 INFO L445 LassoAnalysis]: Proved nontermination for one component. [2018-11-23 16:06:20,901 INFO L448 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {~t3_pc~0=4} Honda state: {~t3_pc~0=4} Generalized eigenvectors: [] Lambdas: [] Nus: [] No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_0fe0e757-a0d1-4897-81ed-84240e247463/bin-2019/uautomizer/z3 Starting monitored process 16 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 16 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2018-11-23 16:06:20,916 INFO L151 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2018-11-23 16:06:20,917 INFO L163 nArgumentSynthesizer]: Using integer mode. No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_0fe0e757-a0d1-4897-81ed-84240e247463/bin-2019/uautomizer/z3 Starting monitored process 17 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 17 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2018-11-23 16:06:20,935 INFO L151 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 3 Nilpotent components: true [2018-11-23 16:06:20,935 INFO L163 nArgumentSynthesizer]: Using integer mode. [2018-11-23 16:06:20,938 INFO L452 LassoAnalysis]: Proving nontermination failed: No geometric nontermination argument exists. [2018-11-23 16:06:20,952 INFO L216 LassoAnalysis]: Preferences: [2018-11-23 16:06:20,952 INFO L124 ssoRankerPreferences]: Compute integeral hull: false [2018-11-23 16:06:20,952 INFO L125 ssoRankerPreferences]: Enable LassoPartitioneer: true [2018-11-23 16:06:20,952 INFO L126 ssoRankerPreferences]: Term annotations enabled: false [2018-11-23 16:06:20,952 INFO L127 ssoRankerPreferences]: Use exernal solver: false [2018-11-23 16:06:20,952 INFO L128 ssoRankerPreferences]: SMT solver command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2018-11-23 16:06:20,952 INFO L129 ssoRankerPreferences]: Dump SMT script to file: false [2018-11-23 16:06:20,952 INFO L130 ssoRankerPreferences]: Path of dumped script: [2018-11-23 16:06:20,952 INFO L131 ssoRankerPreferences]: Filename of dumped script: token_ring.07_false-unreach-call_false-termination.cil.c_Iteration28_Loop [2018-11-23 16:06:20,952 INFO L132 ssoRankerPreferences]: MapElimAlgo: Frank [2018-11-23 16:06:20,952 INFO L282 LassoAnalysis]: Starting lasso preprocessing... [2018-11-23 16:06:20,954 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 16:06:20,963 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 16:06:20,964 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 16:06:20,965 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 16:06:20,966 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 16:06:20,968 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 16:06:20,971 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 16:06:20,976 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 16:06:20,978 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 16:06:20,998 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 16:06:21,001 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 16:06:21,008 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 16:06:21,011 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 16:06:21,015 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 16:06:21,017 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 16:06:21,021 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 16:06:21,022 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 16:06:21,026 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 16:06:21,030 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 16:06:21,032 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 16:06:21,035 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 16:06:21,038 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 16:06:21,040 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 16:06:21,044 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 16:06:21,047 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 16:06:21,057 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 16:06:21,060 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 16:06:21,064 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 16:06:21,066 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 16:06:21,068 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 16:06:21,071 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 16:06:21,072 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 16:06:21,075 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 16:06:21,080 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 16:06:21,083 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 16:06:21,085 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 16:06:21,089 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 16:06:21,092 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 16:06:21,093 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 16:06:21,095 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 16:06:21,096 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 16:06:21,099 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 16:06:21,107 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 16:06:21,110 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 16:06:21,112 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 16:06:21,113 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 16:06:21,115 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 16:06:21,121 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 16:06:21,122 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 16:06:21,124 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 16:06:21,127 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 16:06:21,135 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 16:06:21,136 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 16:06:21,150 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 16:06:21,161 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 16:06:21,163 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 16:06:21,171 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 16:06:21,177 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 16:06:21,180 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 16:06:21,183 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 16:06:21,184 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 16:06:21,185 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 16:06:21,187 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 16:06:21,189 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 16:06:21,191 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 16:06:21,193 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 16:06:21,197 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 16:06:21,211 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 16:06:21,215 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 16:06:21,227 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 16:06:21,231 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 16:06:21,233 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 16:06:21,251 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 16:06:21,255 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 16:06:21,259 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 16:06:21,675 INFO L300 LassoAnalysis]: Preprocessing complete. [2018-11-23 16:06:21,678 INFO L497 LassoAnalysis]: Using template 'affine'. [2018-11-23 16:06:21,680 INFO L122 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSES Number of strict supporting invariants: 0 Number of non-strict supporting invariants: 1 Consider only non-deceasing supporting invariants: true Simplify termination arguments: true Simplify supporting invariants: trueOverapproximate stem: false [2018-11-23 16:06:21,681 INFO L339 nArgumentSynthesizer]: Template has degree 0. [2018-11-23 16:06:21,681 INFO L352 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2018-11-23 16:06:21,682 INFO L205 nArgumentSynthesizer]: 1 stem disjuncts [2018-11-23 16:06:21,682 INFO L206 nArgumentSynthesizer]: 1 loop disjuncts [2018-11-23 16:06:21,682 INFO L207 nArgumentSynthesizer]: 2 template conjuncts. [2018-11-23 16:06:21,684 INFO L402 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2018-11-23 16:06:21,684 INFO L403 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2018-11-23 16:06:21,688 INFO L530 LassoAnalysis]: Proving termination failed for this template and these settings. [2018-11-23 16:06:21,688 INFO L122 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSES Number of strict supporting invariants: 0 Number of non-strict supporting invariants: 1 Consider only non-deceasing supporting invariants: true Simplify termination arguments: true Simplify supporting invariants: trueOverapproximate stem: false [2018-11-23 16:06:21,688 INFO L339 nArgumentSynthesizer]: Template has degree 0. [2018-11-23 16:06:21,688 INFO L352 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2018-11-23 16:06:21,689 INFO L205 nArgumentSynthesizer]: 1 stem disjuncts [2018-11-23 16:06:21,689 INFO L206 nArgumentSynthesizer]: 1 loop disjuncts [2018-11-23 16:06:21,689 INFO L207 nArgumentSynthesizer]: 2 template conjuncts. [2018-11-23 16:06:21,689 INFO L402 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2018-11-23 16:06:21,689 INFO L403 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2018-11-23 16:06:21,690 INFO L530 LassoAnalysis]: Proving termination failed for this template and these settings. [2018-11-23 16:06:21,690 INFO L122 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSES Number of strict supporting invariants: 0 Number of non-strict supporting invariants: 1 Consider only non-deceasing supporting invariants: true Simplify termination arguments: true Simplify supporting invariants: trueOverapproximate stem: false [2018-11-23 16:06:21,690 INFO L339 nArgumentSynthesizer]: Template has degree 0. [2018-11-23 16:06:21,690 INFO L352 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2018-11-23 16:06:21,690 INFO L205 nArgumentSynthesizer]: 1 stem disjuncts [2018-11-23 16:06:21,691 INFO L206 nArgumentSynthesizer]: 1 loop disjuncts [2018-11-23 16:06:21,691 INFO L207 nArgumentSynthesizer]: 2 template conjuncts. [2018-11-23 16:06:21,691 INFO L402 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2018-11-23 16:06:21,691 INFO L403 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2018-11-23 16:06:21,692 INFO L530 LassoAnalysis]: Proving termination failed for this template and these settings. [2018-11-23 16:06:21,692 INFO L122 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSES Number of strict supporting invariants: 0 Number of non-strict supporting invariants: 1 Consider only non-deceasing supporting invariants: true Simplify termination arguments: true Simplify supporting invariants: trueOverapproximate stem: false [2018-11-23 16:06:21,692 INFO L339 nArgumentSynthesizer]: Template has degree 0. [2018-11-23 16:06:21,692 INFO L352 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2018-11-23 16:06:21,692 INFO L205 nArgumentSynthesizer]: 1 stem disjuncts [2018-11-23 16:06:21,692 INFO L206 nArgumentSynthesizer]: 2 loop disjuncts [2018-11-23 16:06:21,692 INFO L207 nArgumentSynthesizer]: 2 template conjuncts. [2018-11-23 16:06:21,693 INFO L402 nArgumentSynthesizer]: We have 4 Motzkin's Theorem applications. [2018-11-23 16:06:21,693 INFO L403 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2018-11-23 16:06:21,694 INFO L530 LassoAnalysis]: Proving termination failed for this template and these settings. [2018-11-23 16:06:21,694 INFO L122 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSES Number of strict supporting invariants: 0 Number of non-strict supporting invariants: 1 Consider only non-deceasing supporting invariants: true Simplify termination arguments: true Simplify supporting invariants: trueOverapproximate stem: false [2018-11-23 16:06:21,694 INFO L339 nArgumentSynthesizer]: Template has degree 0. [2018-11-23 16:06:21,694 INFO L352 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2018-11-23 16:06:21,694 INFO L205 nArgumentSynthesizer]: 1 stem disjuncts [2018-11-23 16:06:21,695 INFO L206 nArgumentSynthesizer]: 1 loop disjuncts [2018-11-23 16:06:21,695 INFO L207 nArgumentSynthesizer]: 2 template conjuncts. [2018-11-23 16:06:21,695 INFO L402 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2018-11-23 16:06:21,695 INFO L403 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2018-11-23 16:06:21,696 INFO L530 LassoAnalysis]: Proving termination failed for this template and these settings. [2018-11-23 16:06:21,696 INFO L122 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSES Number of strict supporting invariants: 0 Number of non-strict supporting invariants: 1 Consider only non-deceasing supporting invariants: true Simplify termination arguments: true Simplify supporting invariants: trueOverapproximate stem: false [2018-11-23 16:06:21,697 INFO L339 nArgumentSynthesizer]: Template has degree 0. [2018-11-23 16:06:21,697 INFO L352 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2018-11-23 16:06:21,697 INFO L205 nArgumentSynthesizer]: 1 stem disjuncts [2018-11-23 16:06:21,697 INFO L206 nArgumentSynthesizer]: 2 loop disjuncts [2018-11-23 16:06:21,697 INFO L207 nArgumentSynthesizer]: 2 template conjuncts. [2018-11-23 16:06:21,697 INFO L402 nArgumentSynthesizer]: We have 4 Motzkin's Theorem applications. [2018-11-23 16:06:21,698 INFO L403 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2018-11-23 16:06:21,699 INFO L530 LassoAnalysis]: Proving termination failed for this template and these settings. [2018-11-23 16:06:21,699 INFO L122 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSES Number of strict supporting invariants: 0 Number of non-strict supporting invariants: 1 Consider only non-deceasing supporting invariants: true Simplify termination arguments: true Simplify supporting invariants: trueOverapproximate stem: false [2018-11-23 16:06:21,699 INFO L339 nArgumentSynthesizer]: Template has degree 0. [2018-11-23 16:06:21,699 INFO L352 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2018-11-23 16:06:21,700 INFO L205 nArgumentSynthesizer]: 1 stem disjuncts [2018-11-23 16:06:21,700 INFO L206 nArgumentSynthesizer]: 1 loop disjuncts [2018-11-23 16:06:21,700 INFO L207 nArgumentSynthesizer]: 2 template conjuncts. [2018-11-23 16:06:21,700 INFO L402 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2018-11-23 16:06:21,700 INFO L403 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2018-11-23 16:06:21,702 INFO L530 LassoAnalysis]: Proving termination failed for this template and these settings. [2018-11-23 16:06:21,702 INFO L122 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSES Number of strict supporting invariants: 0 Number of non-strict supporting invariants: 1 Consider only non-deceasing supporting invariants: true Simplify termination arguments: true Simplify supporting invariants: trueOverapproximate stem: false [2018-11-23 16:06:21,702 INFO L339 nArgumentSynthesizer]: Template has degree 0. [2018-11-23 16:06:21,702 INFO L352 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2018-11-23 16:06:21,703 INFO L205 nArgumentSynthesizer]: 1 stem disjuncts [2018-11-23 16:06:21,703 INFO L206 nArgumentSynthesizer]: 1 loop disjuncts [2018-11-23 16:06:21,703 INFO L207 nArgumentSynthesizer]: 2 template conjuncts. [2018-11-23 16:06:21,703 INFO L402 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2018-11-23 16:06:21,703 INFO L403 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2018-11-23 16:06:21,704 INFO L530 LassoAnalysis]: Proving termination failed for this template and these settings. [2018-11-23 16:06:21,704 INFO L122 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSES Number of strict supporting invariants: 0 Number of non-strict supporting invariants: 1 Consider only non-deceasing supporting invariants: true Simplify termination arguments: true Simplify supporting invariants: trueOverapproximate stem: false [2018-11-23 16:06:21,704 INFO L339 nArgumentSynthesizer]: Template has degree 0. [2018-11-23 16:06:21,704 INFO L352 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2018-11-23 16:06:21,704 INFO L205 nArgumentSynthesizer]: 1 stem disjuncts [2018-11-23 16:06:21,705 INFO L206 nArgumentSynthesizer]: 1 loop disjuncts [2018-11-23 16:06:21,705 INFO L207 nArgumentSynthesizer]: 2 template conjuncts. [2018-11-23 16:06:21,705 INFO L402 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2018-11-23 16:06:21,705 INFO L403 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2018-11-23 16:06:21,705 INFO L530 LassoAnalysis]: Proving termination failed for this template and these settings. [2018-11-23 16:06:21,706 INFO L122 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSES Number of strict supporting invariants: 0 Number of non-strict supporting invariants: 1 Consider only non-deceasing supporting invariants: true Simplify termination arguments: true Simplify supporting invariants: trueOverapproximate stem: false [2018-11-23 16:06:21,706 INFO L339 nArgumentSynthesizer]: Template has degree 0. [2018-11-23 16:06:21,706 INFO L352 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2018-11-23 16:06:21,706 INFO L205 nArgumentSynthesizer]: 1 stem disjuncts [2018-11-23 16:06:21,706 INFO L206 nArgumentSynthesizer]: 1 loop disjuncts [2018-11-23 16:06:21,707 INFO L207 nArgumentSynthesizer]: 2 template conjuncts. [2018-11-23 16:06:21,707 INFO L402 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2018-11-23 16:06:21,707 INFO L403 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2018-11-23 16:06:21,708 INFO L530 LassoAnalysis]: Proving termination failed for this template and these settings. [2018-11-23 16:06:21,708 INFO L122 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSES Number of strict supporting invariants: 0 Number of non-strict supporting invariants: 1 Consider only non-deceasing supporting invariants: true Simplify termination arguments: true Simplify supporting invariants: trueOverapproximate stem: false [2018-11-23 16:06:21,709 INFO L339 nArgumentSynthesizer]: Template has degree 0. [2018-11-23 16:06:21,709 INFO L352 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2018-11-23 16:06:21,709 INFO L205 nArgumentSynthesizer]: 1 stem disjuncts [2018-11-23 16:06:21,709 INFO L206 nArgumentSynthesizer]: 1 loop disjuncts [2018-11-23 16:06:21,709 INFO L207 nArgumentSynthesizer]: 2 template conjuncts. [2018-11-23 16:06:21,709 INFO L402 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2018-11-23 16:06:21,710 INFO L403 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2018-11-23 16:06:21,711 INFO L530 LassoAnalysis]: Proving termination failed for this template and these settings. [2018-11-23 16:06:21,712 INFO L122 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSES Number of strict supporting invariants: 0 Number of non-strict supporting invariants: 1 Consider only non-deceasing supporting invariants: true Simplify termination arguments: true Simplify supporting invariants: trueOverapproximate stem: false [2018-11-23 16:06:21,712 INFO L339 nArgumentSynthesizer]: Template has degree 0. [2018-11-23 16:06:21,712 INFO L352 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2018-11-23 16:06:21,712 INFO L205 nArgumentSynthesizer]: 1 stem disjuncts [2018-11-23 16:06:21,712 INFO L206 nArgumentSynthesizer]: 1 loop disjuncts [2018-11-23 16:06:21,712 INFO L207 nArgumentSynthesizer]: 2 template conjuncts. [2018-11-23 16:06:21,713 INFO L402 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2018-11-23 16:06:21,713 INFO L403 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2018-11-23 16:06:21,714 INFO L530 LassoAnalysis]: Proving termination failed for this template and these settings. [2018-11-23 16:06:21,714 INFO L122 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSES Number of strict supporting invariants: 0 Number of non-strict supporting invariants: 1 Consider only non-deceasing supporting invariants: true Simplify termination arguments: true Simplify supporting invariants: trueOverapproximate stem: false [2018-11-23 16:06:21,714 INFO L339 nArgumentSynthesizer]: Template has degree 0. [2018-11-23 16:06:21,714 INFO L352 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2018-11-23 16:06:21,715 INFO L205 nArgumentSynthesizer]: 1 stem disjuncts [2018-11-23 16:06:21,715 INFO L206 nArgumentSynthesizer]: 2 loop disjuncts [2018-11-23 16:06:21,715 INFO L207 nArgumentSynthesizer]: 2 template conjuncts. [2018-11-23 16:06:21,715 INFO L402 nArgumentSynthesizer]: We have 4 Motzkin's Theorem applications. [2018-11-23 16:06:21,715 INFO L403 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2018-11-23 16:06:21,716 INFO L530 LassoAnalysis]: Proving termination failed for this template and these settings. [2018-11-23 16:06:21,716 INFO L122 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSES Number of strict supporting invariants: 0 Number of non-strict supporting invariants: 1 Consider only non-deceasing supporting invariants: true Simplify termination arguments: true Simplify supporting invariants: trueOverapproximate stem: false [2018-11-23 16:06:21,716 INFO L339 nArgumentSynthesizer]: Template has degree 0. [2018-11-23 16:06:21,717 INFO L352 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2018-11-23 16:06:21,717 INFO L205 nArgumentSynthesizer]: 1 stem disjuncts [2018-11-23 16:06:21,717 INFO L206 nArgumentSynthesizer]: 1 loop disjuncts [2018-11-23 16:06:21,717 INFO L207 nArgumentSynthesizer]: 2 template conjuncts. [2018-11-23 16:06:21,717 INFO L402 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2018-11-23 16:06:21,717 INFO L403 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2018-11-23 16:06:21,718 INFO L530 LassoAnalysis]: Proving termination failed for this template and these settings. [2018-11-23 16:06:21,718 INFO L122 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSES Number of strict supporting invariants: 0 Number of non-strict supporting invariants: 1 Consider only non-deceasing supporting invariants: true Simplify termination arguments: true Simplify supporting invariants: trueOverapproximate stem: false [2018-11-23 16:06:21,718 INFO L339 nArgumentSynthesizer]: Template has degree 0. [2018-11-23 16:06:21,718 INFO L352 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2018-11-23 16:06:21,718 INFO L205 nArgumentSynthesizer]: 1 stem disjuncts [2018-11-23 16:06:21,719 INFO L206 nArgumentSynthesizer]: 1 loop disjuncts [2018-11-23 16:06:21,719 INFO L207 nArgumentSynthesizer]: 2 template conjuncts. [2018-11-23 16:06:21,719 INFO L402 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2018-11-23 16:06:21,719 INFO L403 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2018-11-23 16:06:21,721 INFO L421 nArgumentSynthesizer]: Found a termination argument, trying to simplify. [2018-11-23 16:06:21,723 INFO L443 ModelExtractionUtils]: Simplification made 3 calls to the SMT solver. [2018-11-23 16:06:21,723 INFO L444 ModelExtractionUtils]: 0 out of 3 variables were initially zero. Simplification set additionally 0 variables to zero. [2018-11-23 16:06:21,725 INFO L437 nArgumentSynthesizer]: Simplifying supporting invariants... [2018-11-23 16:06:21,725 INFO L440 nArgumentSynthesizer]: Removed 0 redundant supporting invariants from a total of 0. [2018-11-23 16:06:21,725 INFO L518 LassoAnalysis]: Proved termination. [2018-11-23 16:06:21,725 INFO L520 LassoAnalysis]: Termination argument consisting of: Ranking function f(~E_5~0) = -1*~E_5~0 + 1 Supporting invariants [] [2018-11-23 16:06:21,726 INFO L297 tatePredicateManager]: 0 out of 0 supporting invariants were superfluous and have been removed [2018-11-23 16:06:21,871 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 16:06:21,906 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 16:06:21,910 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-23 16:06:21,966 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 16:06:21,969 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-23 16:06:21,996 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 16:06:22,001 INFO L152 lantAutomatonBouncer]: Defining deterministic Buchi interpolant automaton with honda bouncer for stem and without honda bouncer for loop.1 stem predicates 3 loop predicates [2018-11-23 16:06:22,002 INFO L72 iDifferenceNCSBLazy3]: Start buchiDifferenceNCSBLazy3. First operand 10465 states and 13594 transitions. cyclomatic complexity: 3137 Second operand 5 states. [2018-11-23 16:06:22,306 INFO L76 iDifferenceNCSBLazy3]: Finished buchiDifferenceNCSBLazy3. First operand 10465 states and 13594 transitions. cyclomatic complexity: 3137. Second operand 5 states. Result 35775 states and 46653 transitions. Complement of second has 5 states. [2018-11-23 16:06:22,308 INFO L142 InterpolantAutomaton]: Switched to read-only mode: Buchi interpolant automaton has 3 states 1 stem states 1 non-accepting loop states 1 accepting loop states [2018-11-23 16:06:22,308 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 5 states. [2018-11-23 16:06:22,310 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3 states to 3 states and 2043 transitions. [2018-11-23 16:06:22,312 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 3 states and 2043 transitions. Stem has 91 letters. Loop has 110 letters. [2018-11-23 16:06:22,314 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2018-11-23 16:06:22,315 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 3 states and 2043 transitions. Stem has 201 letters. Loop has 110 letters. [2018-11-23 16:06:22,316 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2018-11-23 16:06:22,316 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 3 states and 2043 transitions. Stem has 91 letters. Loop has 220 letters. [2018-11-23 16:06:22,318 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2018-11-23 16:06:22,318 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 35775 states and 46653 transitions. [2018-11-23 16:06:22,451 INFO L131 ngComponentsAnalysis]: Automaton has 20 accepting balls. 25644 [2018-11-23 16:06:22,556 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 35775 states to 35767 states and 46645 transitions. [2018-11-23 16:06:22,556 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 25870 [2018-11-23 16:06:22,576 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 25911 [2018-11-23 16:06:22,576 INFO L73 IsDeterministic]: Start isDeterministic. Operand 35767 states and 46645 transitions. [2018-11-23 16:06:22,590 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2018-11-23 16:06:22,590 INFO L705 BuchiCegarLoop]: Abstraction has 35767 states and 46645 transitions. [2018-11-23 16:06:22,609 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 35767 states and 46645 transitions. [2018-11-23 16:06:23,026 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 35767 to 30122. [2018-11-23 16:06:23,026 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 30122 states. [2018-11-23 16:06:23,061 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 30122 states to 30122 states and 39244 transitions. [2018-11-23 16:06:23,061 INFO L728 BuchiCegarLoop]: Abstraction has 30122 states and 39244 transitions. [2018-11-23 16:06:23,061 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-23 16:06:23,062 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-23 16:06:23,062 INFO L87 Difference]: Start difference. First operand 30122 states and 39244 transitions. Second operand 3 states. [2018-11-23 16:06:23,254 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 16:06:23,254 INFO L93 Difference]: Finished difference Result 31538 states and 40900 transitions. [2018-11-23 16:06:23,257 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-23 16:06:23,257 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 31538 states and 40900 transitions. [2018-11-23 16:06:23,356 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 21024 [2018-11-23 16:06:23,424 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 31538 states to 31538 states and 40900 transitions. [2018-11-23 16:06:23,424 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 21226 [2018-11-23 16:06:23,439 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 21226 [2018-11-23 16:06:23,439 INFO L73 IsDeterministic]: Start isDeterministic. Operand 31538 states and 40900 transitions. [2018-11-23 16:06:23,445 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2018-11-23 16:06:23,445 INFO L705 BuchiCegarLoop]: Abstraction has 31538 states and 40900 transitions. [2018-11-23 16:06:23,460 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 31538 states and 40900 transitions. [2018-11-23 16:06:23,665 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 31538 to 30122. [2018-11-23 16:06:23,665 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 30122 states. [2018-11-23 16:06:23,702 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 30122 states to 30122 states and 39148 transitions. [2018-11-23 16:06:23,703 INFO L728 BuchiCegarLoop]: Abstraction has 30122 states and 39148 transitions. [2018-11-23 16:06:23,703 INFO L608 BuchiCegarLoop]: Abstraction has 30122 states and 39148 transitions. [2018-11-23 16:06:23,703 INFO L442 BuchiCegarLoop]: ======== Iteration 29============ [2018-11-23 16:06:23,703 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 30122 states and 39148 transitions. [2018-11-23 16:06:23,765 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 20080 [2018-11-23 16:06:23,766 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-23 16:06:23,766 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-23 16:06:23,767 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 16:06:23,767 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 16:06:23,767 INFO L794 eck$LassoCheckResult]: Stem: 347218#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; 347039#L-1 havoc main_#res;havoc main_~__retres1~9;havoc main_~__retres1~9;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 347040#L1143 havoc start_simulation_#t~ret20, start_simulation_#t~ret21, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 346992#L531 assume 1 == ~m_i~0;~m_st~0 := 0; 346993#L538-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 347533#L543-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 347348#L548-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 346994#L553-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 346995#L558-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 347675#L563-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 347330#L568-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 346964#L573-1 assume !(0 == ~M_E~0); 346965#L771-1 assume !(0 == ~T1_E~0); 346661#L776-1 assume !(0 == ~T2_E~0); 346662#L781-1 assume !(0 == ~T3_E~0); 347444#L786-1 assume !(0 == ~T4_E~0); 347121#L791-1 assume !(0 == ~T5_E~0); 346541#L796-1 assume !(0 == ~T6_E~0); 346542#L801-1 assume !(0 == ~T7_E~0); 347839#L806-1 assume !(0 == ~E_M~0); 347271#L811-1 assume !(0 == ~E_1~0); 346861#L816-1 assume !(0 == ~E_2~0); 346862#L821-1 assume !(0 == ~E_3~0); 347921#L826-1 assume !(0 == ~E_4~0); 347607#L831-1 assume !(0 == ~E_5~0); 347251#L836-1 assume !(0 == ~E_6~0); 346382#L841-1 assume !(0 == ~E_7~0); 346383#L846-1 havoc activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 346513#L378 assume !(1 == ~m_pc~0); 346467#L378-2 is_master_triggered_~__retres1~0 := 0; 346468#L389 is_master_triggered_#res := is_master_triggered_~__retres1~0; 348067#L390 activate_threads_#t~ret11 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 347966#L957 assume !(0 != activate_threads_~tmp~1); 347967#L957-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 346933#L397 assume !(1 == ~t1_pc~0); 346777#L397-2 is_transmit1_triggered_~__retres1~1 := 0; 346944#L408 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 347646#L409 activate_threads_#t~ret12 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 347276#L965 assume !(0 != activate_threads_~tmp___0~0); 347262#L965-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 347263#L416 assume !(1 == ~t2_pc~0); 347076#L416-2 is_transmit2_triggered_~__retres1~2 := 0; 347151#L427 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 347879#L428 activate_threads_#t~ret13 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 346414#L973 assume !(0 != activate_threads_~tmp___1~0); 346415#L973-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 346427#L435 assume !(1 == ~t3_pc~0); 347588#L435-2 is_transmit3_triggered_~__retres1~3 := 0; 346593#L446 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 346594#L447 activate_threads_#t~ret14 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 347718#L981 assume !(0 != activate_threads_~tmp___2~0); 347698#L981-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 347699#L454 assume !(1 == ~t4_pc~0); 347821#L454-2 is_transmit4_triggered_~__retres1~4 := 0; 347000#L465 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 346503#L466 activate_threads_#t~ret15 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 346504#L989 assume !(0 != activate_threads_~tmp___3~0); 347129#L989-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 347133#L473 assume !(1 == ~t5_pc~0); 347806#L473-2 is_transmit5_triggered_~__retres1~5 := 0; 347952#L484 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 348068#L485 activate_threads_#t~ret16 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 348026#L997 assume !(0 != activate_threads_~tmp___4~0); 348018#L997-2 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 348019#L492 assume !(1 == ~t6_pc~0); 348063#L492-2 is_transmit6_triggered_~__retres1~6 := 0; 347415#L503 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 347349#L504 activate_threads_#t~ret17 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 347350#L1005 assume !(0 != activate_threads_~tmp___5~0); 347811#L1005-2 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 346367#L511 assume !(1 == ~t7_pc~0); 346368#L511-2 is_transmit7_triggered_~__retres1~7 := 0; 346762#L522 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 348066#L523 activate_threads_#t~ret18 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 347215#L1013 assume !(0 != activate_threads_~tmp___6~0); 347200#L1013-2 assume !(1 == ~M_E~0); 347201#L859-1 assume !(1 == ~T1_E~0); 346689#L864-1 assume !(1 == ~T2_E~0); 346690#L869-1 assume !(1 == ~T3_E~0); 347440#L874-1 assume !(1 == ~T4_E~0); 347110#L879-1 assume !(1 == ~T5_E~0); 346535#L884-1 assume !(1 == ~T6_E~0); 346536#L889-1 assume !(1 == ~T7_E~0); 347836#L894-1 assume !(1 == ~E_M~0); 347264#L899-1 assume !(1 == ~E_1~0); 346849#L904-1 assume !(1 == ~E_2~0); 346850#L909-1 assume !(1 == ~E_3~0); 347929#L914-1 assume !(1 == ~E_4~0); 347612#L919-1 assume !(1 == ~E_5~0); 347261#L924-1 assume !(1 == ~E_6~0); 346428#L929-1 assume 1 == ~E_7~0;~E_7~0 := 2; 346429#L1180-1 [2018-11-23 16:06:23,768 INFO L796 eck$LassoCheckResult]: Loop: 346429#L1180-1 assume !false; 360236#L1181 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret2, eval_#t~nondet3, eval_~tmp_ndt_1~0, eval_#t~nondet4, eval_~tmp_ndt_2~0, eval_#t~nondet5, eval_~tmp_ndt_3~0, eval_#t~nondet6, eval_~tmp_ndt_4~0, eval_#t~nondet7, eval_~tmp_ndt_5~0, eval_#t~nondet8, eval_~tmp_ndt_6~0, eval_#t~nondet9, eval_~tmp_ndt_7~0, eval_#t~nondet10, eval_~tmp_ndt_8~0, eval_~tmp~0;havoc eval_~tmp~0; 360230#L746 assume !false; 360228#L639 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~8;havoc exists_runnable_thread_~__retres1~8; 360224#L586 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8 := 1; 360222#L628 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; 360220#L629 eval_#t~ret2 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret2;havoc eval_#t~ret2; 360218#L643 assume 0 != eval_~tmp~0; 360215#L643-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0;eval_~tmp_ndt_1~0 := eval_#t~nondet3;havoc eval_#t~nondet3; 360213#L651 assume 0 != eval_~tmp_ndt_1~0;~m_st~0 := 1;havoc master_#t~nondet0, master_#t~nondet1, master_~tmp_var~0;master_~tmp_var~0 := master_#t~nondet0;havoc master_#t~nondet0; 360214#L70 assume 0 == ~m_pc~0; 361696#L106 assume !false; 361695#L82 ~token~0 := master_#t~nondet1;havoc master_#t~nondet1;~local~0 := ~token~0;~E_1~0 := 1;havoc activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 361694#L378-3 assume 1 == ~m_pc~0; 361693#L379-1 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 361691#L389-1 is_master_triggered_#res := is_master_triggered_~__retres1~0; 361689#L390-1 activate_threads_#t~ret11 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 361686#L957-3 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 361685#L957-5 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 361684#L397-3 assume !(1 == ~t1_pc~0); 361683#L397-5 is_transmit1_triggered_~__retres1~1 := 0; 361681#L408-1 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 361679#L409-1 activate_threads_#t~ret12 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 361676#L965-3 assume !(0 != activate_threads_~tmp___0~0); 361675#L965-5 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 361674#L416-3 assume !(1 == ~t2_pc~0); 361671#L416-5 is_transmit2_triggered_~__retres1~2 := 0; 361670#L427-1 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 361669#L428-1 activate_threads_#t~ret13 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 361668#L973-3 assume !(0 != activate_threads_~tmp___1~0); 361667#L973-5 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 361663#L435-3 assume !(1 == ~t3_pc~0); 361661#L435-5 is_transmit3_triggered_~__retres1~3 := 0; 361659#L446-1 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 361657#L447-1 activate_threads_#t~ret14 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 361654#L981-3 assume !(0 != activate_threads_~tmp___2~0); 361653#L981-5 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 361650#L454-3 assume !(1 == ~t4_pc~0); 361648#L454-5 is_transmit4_triggered_~__retres1~4 := 0; 361646#L465-1 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 361644#L466-1 activate_threads_#t~ret15 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 361642#L989-3 assume !(0 != activate_threads_~tmp___3~0); 361640#L989-5 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 361632#L473-3 assume 1 == ~t5_pc~0; 361633#L474-1 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 361634#L484-1 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 361706#L485-1 activate_threads_#t~ret16 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 361623#L997-3 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 361621#L997-5 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 361619#L492-3 assume !(1 == ~t6_pc~0); 361617#L492-5 is_transmit6_triggered_~__retres1~6 := 0; 361615#L503-1 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 361611#L504-1 activate_threads_#t~ret17 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 361609#L1005-3 assume 0 != activate_threads_~tmp___5~0;~t6_st~0 := 0; 361607#L1005-5 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 361605#L511-3 assume 1 == ~t7_pc~0; 361601#L512-1 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7 := 1; 361599#L522-1 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 361595#L523-1 activate_threads_#t~ret18 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 361590#L1013-3 assume 0 != activate_threads_~tmp___6~0;~t7_st~0 := 0; 360370#L1013-5 ~E_1~0 := 2;~m_pc~0 := 1;~m_st~0 := 2; 360367#L648 assume !(0 == ~t1_st~0); 359668#L662 assume !(0 == ~t2_st~0); 359664#L676 assume !(0 == ~t3_st~0); 359660#L690 assume !(0 == ~t4_st~0); 359657#L704 assume !(0 == ~t5_st~0); 360458#L718 assume !(0 == ~t6_st~0); 360453#L732 assume !(0 == ~t7_st~0); 360449#L746 assume !false; 360448#L639 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~8;havoc exists_runnable_thread_~__retres1~8; 360447#L586 assume !(0 == ~m_st~0); 360446#L590 assume !(0 == ~t1_st~0); 360441#L594 assume !(0 == ~t2_st~0); 360442#L598 assume !(0 == ~t3_st~0); 360444#L602 assume !(0 == ~t4_st~0); 360439#L606 assume !(0 == ~t5_st~0); 360440#L610 assume !(0 == ~t6_st~0); 360443#L614 assume !(0 == ~t7_st~0);exists_runnable_thread_~__retres1~8 := 0; 360445#L628 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; 366057#L629 eval_#t~ret2 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret2;havoc eval_#t~ret2; 366056#L643 assume !(0 != eval_~tmp~0); 366054#L761 start_simulation_~kernel_st~0 := 2; 366053#L531-1 start_simulation_~kernel_st~0 := 3; 366052#L771-2 assume 0 == ~M_E~0;~M_E~0 := 1; 366050#L771-4 assume !(0 == ~T1_E~0); 366049#L776-3 assume !(0 == ~T2_E~0); 366048#L781-3 assume !(0 == ~T3_E~0); 366047#L786-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 366043#L791-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 366041#L796-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 366039#L801-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 366037#L806-3 assume 0 == ~E_M~0;~E_M~0 := 1; 366033#L811-3 assume !(0 == ~E_1~0); 366031#L816-3 assume !(0 == ~E_2~0); 360421#L821-3 assume !(0 == ~E_3~0); 360420#L826-3 assume 0 == ~E_4~0;~E_4~0 := 1; 360418#L831-3 assume 0 == ~E_5~0;~E_5~0 := 1; 360416#L836-3 assume 0 == ~E_6~0;~E_6~0 := 1; 360415#L841-3 assume 0 == ~E_7~0;~E_7~0 := 1; 360414#L846-3 havoc activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 360411#L378-27 assume 1 == ~m_pc~0; 360408#L379-9 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 360405#L389-9 is_master_triggered_#res := is_master_triggered_~__retres1~0; 360404#L390-9 activate_threads_#t~ret11 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 360399#L957-27 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 360397#L957-29 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 360395#L397-27 assume !(1 == ~t1_pc~0); 360392#L397-29 is_transmit1_triggered_~__retres1~1 := 0; 360389#L408-9 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 360388#L409-9 activate_threads_#t~ret12 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 360385#L965-27 assume !(0 != activate_threads_~tmp___0~0); 360383#L965-29 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 360381#L416-27 assume !(1 == ~t2_pc~0); 360378#L416-29 is_transmit2_triggered_~__retres1~2 := 0; 360376#L427-9 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 360374#L428-9 activate_threads_#t~ret13 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 360371#L973-27 assume !(0 != activate_threads_~tmp___1~0); 360368#L973-29 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 360366#L435-27 assume !(1 == ~t3_pc~0); 360364#L435-29 is_transmit3_triggered_~__retres1~3 := 0; 360362#L446-9 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 360359#L447-9 activate_threads_#t~ret14 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 360357#L981-27 assume !(0 != activate_threads_~tmp___2~0); 360355#L981-29 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 360352#L454-27 assume !(1 == ~t4_pc~0); 360350#L454-29 is_transmit4_triggered_~__retres1~4 := 0; 360348#L465-9 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 360347#L466-9 activate_threads_#t~ret15 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 360346#L989-27 assume !(0 != activate_threads_~tmp___3~0); 360344#L989-29 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 360343#L473-27 assume !(1 == ~t5_pc~0); 360341#L473-29 is_transmit5_triggered_~__retres1~5 := 0; 360339#L484-9 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 360337#L485-9 activate_threads_#t~ret16 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 360336#L997-27 assume !(0 != activate_threads_~tmp___4~0); 360334#L997-29 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 360333#L492-27 assume !(1 == ~t6_pc~0); 360329#L492-29 is_transmit6_triggered_~__retres1~6 := 0; 360327#L503-9 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 360325#L504-9 activate_threads_#t~ret17 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 360323#L1005-27 assume !(0 != activate_threads_~tmp___5~0); 360318#L1005-29 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 360316#L511-27 assume !(1 == ~t7_pc~0); 360313#L511-29 is_transmit7_triggered_~__retres1~7 := 0; 360310#L522-9 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 360308#L523-9 activate_threads_#t~ret18 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 360306#L1013-27 assume !(0 != activate_threads_~tmp___6~0); 360303#L1013-29 assume 1 == ~M_E~0;~M_E~0 := 2; 360301#L859-3 assume !(1 == ~T1_E~0); 360299#L864-3 assume !(1 == ~T2_E~0); 360295#L869-3 assume !(1 == ~T3_E~0); 360293#L874-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 360291#L879-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 360289#L884-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 360286#L889-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 360284#L894-3 assume 1 == ~E_M~0;~E_M~0 := 2; 360282#L899-3 assume !(1 == ~E_1~0); 360280#L904-3 assume !(1 == ~E_2~0); 360278#L909-3 assume !(1 == ~E_3~0); 360276#L914-3 assume 1 == ~E_4~0;~E_4~0 := 2; 360274#L919-3 assume 1 == ~E_5~0;~E_5~0 := 2; 360272#L924-3 assume 1 == ~E_6~0;~E_6~0 := 2; 360270#L929-3 assume 1 == ~E_7~0;~E_7~0 := 2; 360268#L934-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~8;havoc exists_runnable_thread_~__retres1~8; 360266#L586-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8 := 1; 360264#L628-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; 360262#L629-1 start_simulation_#t~ret20 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret20;havoc start_simulation_#t~ret20; 360259#L1199 assume !(0 == start_simulation_~tmp~3); 360254#L1199-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret19, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~8;havoc exists_runnable_thread_~__retres1~8; 360252#L586-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8 := 1; 360250#L628-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; 360248#L629-2 stop_simulation_#t~ret19 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret19;havoc stop_simulation_#t~ret19; 360245#L1154 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 360243#L1161 stop_simulation_#res := stop_simulation_~__retres2~0; 360241#L1162 start_simulation_#t~ret21 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret21;havoc start_simulation_#t~ret21; 360239#L1212 assume !(0 != start_simulation_~tmp___0~1); 346429#L1180-1 [2018-11-23 16:06:23,768 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 16:06:23,768 INFO L82 PathProgramCache]: Analyzing trace with hash 322056991, now seen corresponding path program 1 times [2018-11-23 16:06:23,768 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 16:06:23,768 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 16:06:23,769 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 16:06:23,769 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 16:06:23,769 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 16:06:23,774 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 16:06:23,833 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 16:06:23,833 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 16:06:23,833 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [1] imperfect sequences [] total 1 [2018-11-23 16:06:23,833 INFO L799 eck$LassoCheckResult]: stem already infeasible [2018-11-23 16:06:23,833 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 16:06:23,834 INFO L82 PathProgramCache]: Analyzing trace with hash 470910536, now seen corresponding path program 1 times [2018-11-23 16:06:23,834 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 16:06:23,834 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 16:06:23,834 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 16:06:23,834 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 16:06:23,834 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 16:06:23,840 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 16:06:23,876 INFO L134 CoverageAnalysis]: Checked inductivity of 6 backedges. 6 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 16:06:23,876 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 16:06:23,876 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-23 16:06:23,876 INFO L811 eck$LassoCheckResult]: loop already infeasible [2018-11-23 16:06:23,877 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-23 16:06:23,877 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-23 16:06:23,877 INFO L87 Difference]: Start difference. First operand 30122 states and 39148 transitions. cyclomatic complexity: 9050 Second operand 3 states. [2018-11-23 16:06:24,009 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 16:06:24,009 INFO L93 Difference]: Finished difference Result 24475 states and 31449 transitions. [2018-11-23 16:06:24,010 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-23 16:06:24,011 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 24475 states and 31449 transitions. [2018-11-23 16:06:24,079 INFO L131 ngComponentsAnalysis]: Automaton has 12 accepting balls. 14804 [2018-11-23 16:06:24,130 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 24475 states to 24475 states and 31449 transitions. [2018-11-23 16:06:24,130 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 14971 [2018-11-23 16:06:24,138 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 14971 [2018-11-23 16:06:24,139 INFO L73 IsDeterministic]: Start isDeterministic. Operand 24475 states and 31449 transitions. [2018-11-23 16:06:24,141 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2018-11-23 16:06:24,141 INFO L705 BuchiCegarLoop]: Abstraction has 24475 states and 31449 transitions. [2018-11-23 16:06:24,153 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 24475 states and 31449 transitions. [2018-11-23 16:06:24,293 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 24475 to 24475. [2018-11-23 16:06:24,293 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 24475 states. [2018-11-23 16:06:24,322 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 24475 states to 24475 states and 31449 transitions. [2018-11-23 16:06:24,322 INFO L728 BuchiCegarLoop]: Abstraction has 24475 states and 31449 transitions. [2018-11-23 16:06:24,322 INFO L608 BuchiCegarLoop]: Abstraction has 24475 states and 31449 transitions. [2018-11-23 16:06:24,322 INFO L442 BuchiCegarLoop]: ======== Iteration 30============ [2018-11-23 16:06:24,322 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 24475 states and 31449 transitions. [2018-11-23 16:06:24,369 INFO L131 ngComponentsAnalysis]: Automaton has 12 accepting balls. 14804 [2018-11-23 16:06:24,369 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-23 16:06:24,369 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-23 16:06:24,370 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 16:06:24,371 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 16:06:24,371 INFO L794 eck$LassoCheckResult]: Stem: 401798#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; 401623#L-1 havoc main_#res;havoc main_~__retres1~9;havoc main_~__retres1~9;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 401624#L1143 havoc start_simulation_#t~ret20, start_simulation_#t~ret21, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 401573#L531 assume 1 == ~m_i~0;~m_st~0 := 0; 401574#L538-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 402112#L543-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 401921#L548-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 401575#L553-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 401576#L558-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 402251#L563-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 401905#L568-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 401548#L573-1 assume !(0 == ~M_E~0); 401549#L771-1 assume !(0 == ~T1_E~0); 401250#L776-1 assume !(0 == ~T2_E~0); 401251#L781-1 assume !(0 == ~T3_E~0); 402019#L786-1 assume !(0 == ~T4_E~0); 401702#L791-1 assume !(0 == ~T5_E~0); 401147#L796-1 assume !(0 == ~T6_E~0); 401148#L801-1 assume !(0 == ~T7_E~0); 402413#L806-1 assume !(0 == ~E_M~0); 401848#L811-1 assume !(0 == ~E_1~0); 401446#L816-1 assume !(0 == ~E_2~0); 401447#L821-1 assume !(0 == ~E_3~0); 402489#L826-1 assume !(0 == ~E_4~0); 402183#L831-1 assume !(0 == ~E_5~0); 401827#L836-1 assume !(0 == ~E_6~0); 400987#L841-1 assume !(0 == ~E_7~0); 400988#L846-1 havoc activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 401119#L378 assume !(1 == ~m_pc~0); 401073#L378-2 is_master_triggered_~__retres1~0 := 0; 401074#L389 is_master_triggered_#res := is_master_triggered_~__retres1~0; 402611#L390 activate_threads_#t~ret11 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 402529#L957 assume !(0 != activate_threads_~tmp~1); 402530#L957-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 401519#L397 assume !(1 == ~t1_pc~0); 401364#L397-2 is_transmit1_triggered_~__retres1~1 := 0; 401529#L408 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 402222#L409 activate_threads_#t~ret12 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 401853#L965 assume !(0 != activate_threads_~tmp___0~0); 401839#L965-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 401840#L416 assume !(1 == ~t2_pc~0); 401658#L416-2 is_transmit2_triggered_~__retres1~2 := 0; 401729#L427 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 402451#L428 activate_threads_#t~ret13 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 401020#L973 assume !(0 != activate_threads_~tmp___1~0); 401021#L973-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 401031#L435 assume !(1 == ~t3_pc~0); 402166#L435-2 is_transmit3_triggered_~__retres1~3 := 0; 401191#L446 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 401192#L447 activate_threads_#t~ret14 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 402292#L981 assume !(0 != activate_threads_~tmp___2~0); 402273#L981-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 402274#L454 assume !(1 == ~t4_pc~0); 402395#L454-2 is_transmit4_triggered_~__retres1~4 := 0; 401581#L465 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 401109#L466 activate_threads_#t~ret15 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 401110#L989 assume !(0 != activate_threads_~tmp___3~0); 401709#L989-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 401713#L473 assume !(1 == ~t5_pc~0); 402379#L473-2 is_transmit5_triggered_~__retres1~5 := 0; 402512#L484 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 402612#L485 activate_threads_#t~ret16 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 402580#L997 assume !(0 != activate_threads_~tmp___4~0); 402574#L997-2 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 402575#L492 assume !(1 == ~t6_pc~0); 402610#L492-2 is_transmit6_triggered_~__retres1~6 := 0; 401990#L503 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 401922#L504 activate_threads_#t~ret17 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 401923#L1005 assume !(0 != activate_threads_~tmp___5~0); 402384#L1005-2 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 400972#L511 assume !(1 == ~t7_pc~0); 400973#L511-2 is_transmit7_triggered_~__retres1~7 := 0; 401349#L522 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 402015#L523 activate_threads_#t~ret18 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 401795#L1013 assume !(0 != activate_threads_~tmp___6~0); 401780#L1013-2 assume !(1 == ~M_E~0); 401781#L859-1 assume !(1 == ~T1_E~0); 401277#L864-1 assume !(1 == ~T2_E~0); 401278#L869-1 assume !(1 == ~T3_E~0); 402016#L874-1 assume !(1 == ~T4_E~0); 401691#L879-1 assume !(1 == ~T5_E~0); 401141#L884-1 assume !(1 == ~T6_E~0); 401142#L889-1 assume !(1 == ~T7_E~0); 402410#L894-1 assume !(1 == ~E_M~0); 401841#L899-1 assume !(1 == ~E_1~0); 401434#L904-1 assume !(1 == ~E_2~0); 401435#L909-1 assume !(1 == ~E_3~0); 402494#L914-1 assume !(1 == ~E_4~0); 402187#L919-1 assume !(1 == ~E_5~0); 401838#L924-1 assume !(1 == ~E_6~0); 401034#L929-1 assume !(1 == ~E_7~0); 401035#L1180-1 assume !false; 405496#L1181 [2018-11-23 16:06:24,371 INFO L796 eck$LassoCheckResult]: Loop: 405496#L1181 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret2, eval_#t~nondet3, eval_~tmp_ndt_1~0, eval_#t~nondet4, eval_~tmp_ndt_2~0, eval_#t~nondet5, eval_~tmp_ndt_3~0, eval_#t~nondet6, eval_~tmp_ndt_4~0, eval_#t~nondet7, eval_~tmp_ndt_5~0, eval_#t~nondet8, eval_~tmp_ndt_6~0, eval_#t~nondet9, eval_~tmp_ndt_7~0, eval_#t~nondet10, eval_~tmp_ndt_8~0, eval_~tmp~0;havoc eval_~tmp~0; 414824#L746 assume !false; 414816#L639 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~8;havoc exists_runnable_thread_~__retres1~8; 414807#L586 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8 := 1; 414800#L628 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; 414792#L629 eval_#t~ret2 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret2;havoc eval_#t~ret2; 414776#L643 assume 0 != eval_~tmp~0; 414765#L643-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0;eval_~tmp_ndt_1~0 := eval_#t~nondet3;havoc eval_#t~nondet3; 414756#L651 assume 0 != eval_~tmp_ndt_1~0;~m_st~0 := 1;havoc master_#t~nondet0, master_#t~nondet1, master_~tmp_var~0;master_~tmp_var~0 := master_#t~nondet0;havoc master_#t~nondet0; 414757#L70 assume 0 == ~m_pc~0; 415128#L106 assume !false; 415127#L82 ~token~0 := master_#t~nondet1;havoc master_#t~nondet1;~local~0 := ~token~0;~E_1~0 := 1;havoc activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 415126#L378-3 assume !(1 == ~m_pc~0); 415124#L378-5 is_master_triggered_~__retres1~0 := 0; 415122#L389-1 is_master_triggered_#res := is_master_triggered_~__retres1~0; 415120#L390-1 activate_threads_#t~ret11 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 415119#L957-3 assume !(0 != activate_threads_~tmp~1); 415117#L957-5 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 415116#L397-3 assume !(1 == ~t1_pc~0); 415114#L397-5 is_transmit1_triggered_~__retres1~1 := 0; 415115#L408-1 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 415112#L409-1 activate_threads_#t~ret12 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 415108#L965-3 assume !(0 != activate_threads_~tmp___0~0); 415106#L965-5 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 415104#L416-3 assume !(1 == ~t2_pc~0); 415101#L416-5 is_transmit2_triggered_~__retres1~2 := 0; 415100#L427-1 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 415099#L428-1 activate_threads_#t~ret13 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 415098#L973-3 assume !(0 != activate_threads_~tmp___1~0); 415096#L973-5 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 415095#L435-3 assume !(1 == ~t3_pc~0); 415094#L435-5 is_transmit3_triggered_~__retres1~3 := 0; 415092#L446-1 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 415091#L447-1 activate_threads_#t~ret14 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 415090#L981-3 assume !(0 != activate_threads_~tmp___2~0); 415089#L981-5 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 415087#L454-3 assume !(1 == ~t4_pc~0); 415085#L454-5 is_transmit4_triggered_~__retres1~4 := 0; 415083#L465-1 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 415082#L466-1 activate_threads_#t~ret15 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 415081#L989-3 assume !(0 != activate_threads_~tmp___3~0); 415078#L989-5 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 415073#L473-3 assume 1 == ~t5_pc~0; 415074#L474-1 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 415075#L484-1 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 415093#L485-1 activate_threads_#t~ret16 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 415062#L997-3 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 415060#L997-5 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 415058#L492-3 assume !(1 == ~t6_pc~0); 415056#L492-5 is_transmit6_triggered_~__retres1~6 := 0; 415053#L503-1 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 415051#L504-1 activate_threads_#t~ret17 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 415049#L1005-3 assume 0 != activate_threads_~tmp___5~0;~t6_st~0 := 0; 415047#L1005-5 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 415045#L511-3 assume !(1 == ~t7_pc~0); 415042#L511-5 is_transmit7_triggered_~__retres1~7 := 0; 415040#L522-1 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 415038#L523-1 activate_threads_#t~ret18 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 415036#L1013-3 assume !(0 != activate_threads_~tmp___6~0); 415034#L1013-5 ~E_1~0 := 2;~m_pc~0 := 1;~m_st~0 := 2; 414980#L648 assume !(0 == ~t1_st~0); 414978#L662 assume !(0 == ~t2_st~0); 414976#L676 assume !(0 == ~t3_st~0); 415855#L690 assume !(0 == ~t4_st~0); 415851#L704 assume !(0 == ~t5_st~0); 415845#L718 assume !(0 == ~t6_st~0); 415841#L732 assume !(0 == ~t7_st~0); 415839#L746 assume !false; 416550#L639 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~8;havoc exists_runnable_thread_~__retres1~8; 416544#L586 assume !(0 == ~m_st~0); 416537#L590 assume !(0 == ~t1_st~0); 416532#L594 assume !(0 == ~t2_st~0); 416527#L598 assume !(0 == ~t3_st~0); 416520#L602 assume !(0 == ~t4_st~0); 416513#L606 assume !(0 == ~t5_st~0); 416504#L610 assume !(0 == ~t6_st~0); 416496#L614 assume !(0 == ~t7_st~0);exists_runnable_thread_~__retres1~8 := 0; 416487#L628 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; 416477#L629 eval_#t~ret2 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret2;havoc eval_#t~ret2; 416469#L643 assume !(0 != eval_~tmp~0); 416463#L761 start_simulation_~kernel_st~0 := 2; 416455#L531-1 start_simulation_~kernel_st~0 := 3; 416446#L771-2 assume 0 == ~M_E~0;~M_E~0 := 1; 416436#L771-4 assume !(0 == ~T1_E~0); 416427#L776-3 assume !(0 == ~T2_E~0); 416420#L781-3 assume !(0 == ~T3_E~0); 416414#L786-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 416408#L791-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 416402#L796-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 416395#L801-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 416389#L806-3 assume 0 == ~E_M~0;~E_M~0 := 1; 416383#L811-3 assume !(0 == ~E_1~0); 416374#L816-3 assume !(0 == ~E_2~0); 416366#L821-3 assume !(0 == ~E_3~0); 416359#L826-3 assume 0 == ~E_4~0;~E_4~0 := 1; 416308#L831-3 assume !(0 == ~E_5~0); 416301#L836-3 assume 0 == ~E_6~0;~E_6~0 := 1; 416297#L841-3 assume !(0 == ~E_7~0); 416295#L846-3 havoc activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 416292#L378-27 assume 1 == ~m_pc~0; 416289#L379-9 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 416286#L389-9 is_master_triggered_#res := is_master_triggered_~__retres1~0; 416285#L390-9 activate_threads_#t~ret11 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 416283#L957-27 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 416280#L957-29 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 416278#L397-27 assume !(1 == ~t1_pc~0); 416275#L397-29 is_transmit1_triggered_~__retres1~1 := 0; 416272#L408-9 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 416270#L409-9 activate_threads_#t~ret12 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 416251#L965-27 assume !(0 != activate_threads_~tmp___0~0); 416246#L965-29 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 416241#L416-27 assume !(1 == ~t2_pc~0); 416236#L416-29 is_transmit2_triggered_~__retres1~2 := 0; 416232#L427-9 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 416227#L428-9 activate_threads_#t~ret13 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 416226#L973-27 assume !(0 != activate_threads_~tmp___1~0); 416225#L973-29 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 416224#L435-27 assume !(1 == ~t3_pc~0); 416223#L435-29 is_transmit3_triggered_~__retres1~3 := 0; 416221#L446-9 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 416219#L447-9 activate_threads_#t~ret14 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 416217#L981-27 assume !(0 != activate_threads_~tmp___2~0); 416216#L981-29 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 416215#L454-27 assume !(1 == ~t4_pc~0); 416212#L454-29 is_transmit4_triggered_~__retres1~4 := 0; 416210#L465-9 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 416208#L466-9 activate_threads_#t~ret15 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 416206#L989-27 assume !(0 != activate_threads_~tmp___3~0); 416204#L989-29 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 416202#L473-27 assume 1 == ~t5_pc~0; 416180#L474-9 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 416172#L484-9 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 416165#L485-9 activate_threads_#t~ret16 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 416157#L997-27 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 416149#L997-29 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 416142#L492-27 assume !(1 == ~t6_pc~0); 416136#L492-29 is_transmit6_triggered_~__retres1~6 := 0; 416130#L503-9 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 416123#L504-9 activate_threads_#t~ret17 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 416103#L1005-27 assume !(0 != activate_threads_~tmp___5~0); 416093#L1005-29 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 415918#L511-27 assume !(1 == ~t7_pc~0); 415915#L511-29 is_transmit7_triggered_~__retres1~7 := 0; 415912#L522-9 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 415910#L523-9 activate_threads_#t~ret18 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 415908#L1013-27 assume !(0 != activate_threads_~tmp___6~0); 415647#L1013-29 assume 1 == ~M_E~0;~M_E~0 := 2; 415637#L859-3 assume !(1 == ~T1_E~0); 415628#L864-3 assume !(1 == ~T2_E~0); 415621#L869-3 assume !(1 == ~T3_E~0); 415615#L874-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 415608#L879-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 415601#L884-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 415540#L889-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 415532#L894-3 assume 1 == ~E_M~0;~E_M~0 := 2; 415267#L899-3 assume !(1 == ~E_1~0); 415264#L904-3 assume !(1 == ~E_2~0); 415262#L909-3 assume !(1 == ~E_3~0); 415260#L914-3 assume 1 == ~E_4~0;~E_4~0 := 2; 415258#L919-3 assume !(1 == ~E_5~0); 415244#L924-3 assume 1 == ~E_6~0;~E_6~0 := 2; 415242#L929-3 assume !(1 == ~E_7~0); 415239#L934-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~8;havoc exists_runnable_thread_~__retres1~8; 415237#L586-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8 := 1; 415235#L628-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; 415229#L629-1 start_simulation_#t~ret20 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret20;havoc start_simulation_#t~ret20; 415164#L1199 assume !(0 == start_simulation_~tmp~3); 415161#L1199-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret19, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~8;havoc exists_runnable_thread_~__retres1~8; 415159#L586-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8 := 1; 415157#L628-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; 415155#L629-2 stop_simulation_#t~ret19 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret19;havoc stop_simulation_#t~ret19; 415153#L1154 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 415151#L1161 stop_simulation_#res := stop_simulation_~__retres2~0; 415147#L1162 start_simulation_#t~ret21 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret21;havoc start_simulation_#t~ret21; 415145#L1212 assume !(0 != start_simulation_~tmp___0~1); 415143#L1180-1 assume !false; 405496#L1181 [2018-11-23 16:06:24,371 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 16:06:24,371 INFO L82 PathProgramCache]: Analyzing trace with hash 1393832633, now seen corresponding path program 1 times [2018-11-23 16:06:24,372 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 16:06:24,372 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 16:06:24,372 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 16:06:24,372 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 16:06:24,372 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 16:06:24,377 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-23 16:06:24,381 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-23 16:06:24,399 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 16:06:24,399 INFO L82 PathProgramCache]: Analyzing trace with hash -767508839, now seen corresponding path program 1 times [2018-11-23 16:06:24,399 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 16:06:24,399 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 16:06:24,399 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 16:06:24,399 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 16:06:24,400 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 16:06:24,403 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 16:06:24,484 INFO L134 CoverageAnalysis]: Checked inductivity of 6 backedges. 6 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 16:06:24,485 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 16:06:24,485 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-11-23 16:06:24,485 INFO L811 eck$LassoCheckResult]: loop already infeasible [2018-11-23 16:06:24,485 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-11-23 16:06:24,485 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-11-23 16:06:24,485 INFO L87 Difference]: Start difference. First operand 24475 states and 31449 transitions. cyclomatic complexity: 6994 Second operand 5 states. [2018-11-23 16:06:24,786 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 16:06:24,787 INFO L93 Difference]: Finished difference Result 40832 states and 52516 transitions. [2018-11-23 16:06:24,789 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2018-11-23 16:06:24,789 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 40832 states and 52516 transitions. [2018-11-23 16:06:24,975 INFO L131 ngComponentsAnalysis]: Automaton has 12 accepting balls. 24707 [2018-11-23 16:06:25,024 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 40832 states to 40832 states and 52516 transitions. [2018-11-23 16:06:25,024 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 24914 [2018-11-23 16:06:25,032 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 24914 [2018-11-23 16:06:25,032 INFO L73 IsDeterministic]: Start isDeterministic. Operand 40832 states and 52516 transitions. [2018-11-23 16:06:25,035 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2018-11-23 16:06:25,035 INFO L705 BuchiCegarLoop]: Abstraction has 40832 states and 52516 transitions. [2018-11-23 16:06:25,046 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 40832 states and 52516 transitions. [2018-11-23 16:06:25,200 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 40832 to 24967. [2018-11-23 16:06:25,200 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 24967 states. [2018-11-23 16:06:25,224 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 24967 states to 24967 states and 31796 transitions. [2018-11-23 16:06:25,224 INFO L728 BuchiCegarLoop]: Abstraction has 24967 states and 31796 transitions. [2018-11-23 16:06:25,225 INFO L608 BuchiCegarLoop]: Abstraction has 24967 states and 31796 transitions. [2018-11-23 16:06:25,225 INFO L442 BuchiCegarLoop]: ======== Iteration 31============ [2018-11-23 16:06:25,225 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 24967 states and 31796 transitions. [2018-11-23 16:06:25,265 INFO L131 ngComponentsAnalysis]: Automaton has 12 accepting balls. 15104 [2018-11-23 16:06:25,265 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-23 16:06:25,265 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-23 16:06:25,267 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 16:06:25,267 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 16:06:25,267 INFO L794 eck$LassoCheckResult]: Stem: 467136#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; 466956#L-1 havoc main_#res;havoc main_~__retres1~9;havoc main_~__retres1~9;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 466957#L1143 havoc start_simulation_#t~ret20, start_simulation_#t~ret21, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 466908#L531 assume 1 == ~m_i~0;~m_st~0 := 0; 466909#L538-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 467482#L543-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 467272#L548-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 466910#L553-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 466911#L558-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 467633#L563-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 467246#L568-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 466879#L573-1 assume !(0 == ~M_E~0); 466880#L771-1 assume !(0 == ~T1_E~0); 466574#L776-1 assume !(0 == ~T2_E~0); 466575#L781-1 assume !(0 == ~T3_E~0); 467385#L786-1 assume !(0 == ~T4_E~0); 467038#L791-1 assume !(0 == ~T5_E~0); 466471#L796-1 assume !(0 == ~T6_E~0); 466472#L801-1 assume !(0 == ~T7_E~0); 467799#L806-1 assume !(0 == ~E_M~0); 467186#L811-1 assume !(0 == ~E_1~0); 466777#L816-1 assume !(0 == ~E_2~0); 466778#L821-1 assume !(0 == ~E_3~0); 467903#L826-1 assume !(0 == ~E_4~0); 467566#L831-1 assume !(0 == ~E_5~0); 467164#L836-1 assume !(0 == ~E_6~0); 466303#L841-1 assume !(0 == ~E_7~0); 466304#L846-1 havoc activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 466443#L378 assume !(1 == ~m_pc~0); 466397#L378-2 is_master_triggered_~__retres1~0 := 0; 466398#L389 is_master_triggered_#res := is_master_triggered_~__retres1~0; 468082#L390 activate_threads_#t~ret11 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 467962#L957 assume !(0 != activate_threads_~tmp~1); 467963#L957-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 466850#L397 assume !(1 == ~t1_pc~0); 466692#L397-2 is_transmit1_triggered_~__retres1~1 := 0; 466860#L408 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 467604#L409 activate_threads_#t~ret12 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 467191#L965 assume !(0 != activate_threads_~tmp___0~0); 467175#L965-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 467176#L416 assume !(1 == ~t2_pc~0); 466992#L416-2 is_transmit2_triggered_~__retres1~2 := 0; 467067#L427 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 467852#L428 activate_threads_#t~ret13 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 466344#L973 assume !(0 != activate_threads_~tmp___1~0); 466345#L973-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 466356#L435 assume !(1 == ~t3_pc~0); 467545#L435-2 is_transmit3_triggered_~__retres1~3 := 0; 466515#L446 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 466516#L447 activate_threads_#t~ret14 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 467677#L981 assume !(0 != activate_threads_~tmp___2~0); 467656#L981-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 467657#L454 assume !(1 == ~t4_pc~0); 467782#L454-2 is_transmit4_triggered_~__retres1~4 := 0; 466916#L465 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 466433#L466 activate_threads_#t~ret15 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 466434#L989 assume !(0 != activate_threads_~tmp___3~0); 467045#L989-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 467049#L473 assume !(1 == ~t5_pc~0); 467771#L473-2 is_transmit5_triggered_~__retres1~5 := 0; 467943#L484 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 468083#L485 activate_threads_#t~ret16 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 468027#L997 assume !(0 != activate_threads_~tmp___4~0); 468016#L997-2 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 468017#L492 assume !(1 == ~t6_pc~0); 468081#L492-2 is_transmit6_triggered_~__retres1~6 := 0; 467352#L503 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 467273#L504 activate_threads_#t~ret17 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 467274#L1005 assume !(0 != activate_threads_~tmp___5~0); 467775#L1005-2 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 466294#L511 assume !(1 == ~t7_pc~0); 466295#L511-2 is_transmit7_triggered_~__retres1~7 := 0; 466677#L522 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 467380#L523 activate_threads_#t~ret18 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 467133#L1013 assume !(0 != activate_threads_~tmp___6~0); 467118#L1013-2 assume !(1 == ~M_E~0); 467119#L859-1 assume !(1 == ~T1_E~0); 466602#L864-1 assume !(1 == ~T2_E~0); 466603#L869-1 assume !(1 == ~T3_E~0); 467381#L874-1 assume !(1 == ~T4_E~0); 467025#L879-1 assume !(1 == ~T5_E~0); 466465#L884-1 assume !(1 == ~T6_E~0); 466466#L889-1 assume !(1 == ~T7_E~0); 467796#L894-1 assume !(1 == ~E_M~0); 467177#L899-1 assume !(1 == ~E_1~0); 466765#L904-1 assume !(1 == ~E_2~0); 466766#L909-1 assume !(1 == ~E_3~0); 467912#L914-1 assume !(1 == ~E_4~0); 467572#L919-1 assume !(1 == ~E_5~0); 467174#L924-1 assume !(1 == ~E_6~0); 466360#L929-1 assume !(1 == ~E_7~0); 466361#L1180-1 assume !false; 469721#L1181 [2018-11-23 16:06:25,268 INFO L796 eck$LassoCheckResult]: Loop: 469721#L1181 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret2, eval_#t~nondet3, eval_~tmp_ndt_1~0, eval_#t~nondet4, eval_~tmp_ndt_2~0, eval_#t~nondet5, eval_~tmp_ndt_3~0, eval_#t~nondet6, eval_~tmp_ndt_4~0, eval_#t~nondet7, eval_~tmp_ndt_5~0, eval_#t~nondet8, eval_~tmp_ndt_6~0, eval_#t~nondet9, eval_~tmp_ndt_7~0, eval_#t~nondet10, eval_~tmp_ndt_8~0, eval_~tmp~0;havoc eval_~tmp~0; 477461#L746 assume !false; 477457#L639 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~8;havoc exists_runnable_thread_~__retres1~8; 477449#L586 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8 := 1; 477444#L628 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; 477439#L629 eval_#t~ret2 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret2;havoc eval_#t~ret2; 477434#L643 assume 0 != eval_~tmp~0; 477430#L643-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0;eval_~tmp_ndt_1~0 := eval_#t~nondet3;havoc eval_#t~nondet3; 477425#L651 assume 0 != eval_~tmp_ndt_1~0;~m_st~0 := 1;havoc master_#t~nondet0, master_#t~nondet1, master_~tmp_var~0;master_~tmp_var~0 := master_#t~nondet0;havoc master_#t~nondet0; 477409#L70 assume 0 == ~m_pc~0; 477404#L106 assume !false; 477398#L82 ~token~0 := master_#t~nondet1;havoc master_#t~nondet1;~local~0 := ~token~0;~E_1~0 := 1;havoc activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 477394#L378-3 assume !(1 == ~m_pc~0); 477390#L378-5 is_master_triggered_~__retres1~0 := 0; 477384#L389-1 is_master_triggered_#res := is_master_triggered_~__retres1~0; 477377#L390-1 activate_threads_#t~ret11 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 477370#L957-3 assume !(0 != activate_threads_~tmp~1); 477363#L957-5 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 477358#L397-3 assume 1 == ~t1_pc~0; 477351#L398-1 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 477344#L408-1 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 477338#L409-1 activate_threads_#t~ret12 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 477334#L965-3 assume !(0 != activate_threads_~tmp___0~0); 477330#L965-5 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 477326#L416-3 assume !(1 == ~t2_pc~0); 477320#L416-5 is_transmit2_triggered_~__retres1~2 := 0; 477315#L427-1 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 477310#L428-1 activate_threads_#t~ret13 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 477304#L973-3 assume !(0 != activate_threads_~tmp___1~0); 477298#L973-5 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 477293#L435-3 assume !(1 == ~t3_pc~0); 477087#L435-5 is_transmit3_triggered_~__retres1~3 := 0; 477085#L446-1 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 477083#L447-1 activate_threads_#t~ret14 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 477079#L981-3 assume !(0 != activate_threads_~tmp___2~0); 477077#L981-5 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 477075#L454-3 assume !(1 == ~t4_pc~0); 477073#L454-5 is_transmit4_triggered_~__retres1~4 := 0; 477070#L465-1 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 477068#L466-1 activate_threads_#t~ret15 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 477066#L989-3 assume !(0 != activate_threads_~tmp___3~0); 477064#L989-5 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 477059#L473-3 assume 1 == ~t5_pc~0; 477060#L474-1 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 477061#L484-1 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 477286#L485-1 activate_threads_#t~ret16 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 477050#L997-3 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 477048#L997-5 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 477046#L492-3 assume !(1 == ~t6_pc~0); 477044#L492-5 is_transmit6_triggered_~__retres1~6 := 0; 477042#L503-1 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 477038#L504-1 activate_threads_#t~ret17 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 477036#L1005-3 assume !(0 != activate_threads_~tmp___5~0); 477034#L1005-5 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 477032#L511-3 assume !(1 == ~t7_pc~0); 477028#L511-5 is_transmit7_triggered_~__retres1~7 := 0; 477026#L522-1 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 477024#L523-1 activate_threads_#t~ret18 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 477022#L1013-3 assume !(0 != activate_threads_~tmp___6~0); 477020#L1013-5 ~E_1~0 := 2;~m_pc~0 := 1;~m_st~0 := 2; 476995#L648 assume !(0 == ~t1_st~0); 476683#L662 assume !(0 == ~t2_st~0); 476679#L676 assume !(0 == ~t3_st~0); 476677#L690 assume !(0 == ~t4_st~0); 477731#L704 assume !(0 == ~t5_st~0); 477726#L718 assume !(0 == ~t6_st~0); 477722#L732 assume !(0 == ~t7_st~0); 477719#L746 assume !false; 478161#L639 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~8;havoc exists_runnable_thread_~__retres1~8; 478159#L586 assume !(0 == ~m_st~0); 478157#L590 assume !(0 == ~t1_st~0); 478155#L594 assume !(0 == ~t2_st~0); 478153#L598 assume !(0 == ~t3_st~0); 478151#L602 assume !(0 == ~t4_st~0); 478149#L606 assume !(0 == ~t5_st~0); 478147#L610 assume !(0 == ~t6_st~0); 478144#L614 assume !(0 == ~t7_st~0);exists_runnable_thread_~__retres1~8 := 0; 478142#L628 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; 478140#L629 eval_#t~ret2 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret2;havoc eval_#t~ret2; 478138#L643 assume !(0 != eval_~tmp~0); 478136#L761 start_simulation_~kernel_st~0 := 2; 478134#L531-1 start_simulation_~kernel_st~0 := 3; 478132#L771-2 assume 0 == ~M_E~0;~M_E~0 := 1; 478129#L771-4 assume !(0 == ~T1_E~0); 478126#L776-3 assume !(0 == ~T2_E~0); 478123#L781-3 assume !(0 == ~T3_E~0); 478120#L786-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 478118#L791-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 478116#L796-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 478114#L801-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 478112#L806-3 assume 0 == ~E_M~0;~E_M~0 := 1; 478110#L811-3 assume !(0 == ~E_1~0); 478108#L816-3 assume !(0 == ~E_2~0); 478106#L821-3 assume !(0 == ~E_3~0); 478103#L826-3 assume 0 == ~E_4~0;~E_4~0 := 1; 478101#L831-3 assume !(0 == ~E_5~0); 478099#L836-3 assume 0 == ~E_6~0;~E_6~0 := 1; 478097#L841-3 assume !(0 == ~E_7~0); 478095#L846-3 havoc activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 478093#L378-27 assume 1 == ~m_pc~0; 478090#L379-9 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 478088#L389-9 is_master_triggered_#res := is_master_triggered_~__retres1~0; 478086#L390-9 activate_threads_#t~ret11 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 478083#L957-27 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 478081#L957-29 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 478079#L397-27 assume !(1 == ~t1_pc~0); 478076#L397-29 is_transmit1_triggered_~__retres1~1 := 0; 478074#L408-9 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 478072#L409-9 activate_threads_#t~ret12 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 478070#L965-27 assume !(0 != activate_threads_~tmp___0~0); 478068#L965-29 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 478066#L416-27 assume !(1 == ~t2_pc~0); 478063#L416-29 is_transmit2_triggered_~__retres1~2 := 0; 478061#L427-9 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 478059#L428-9 activate_threads_#t~ret13 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 478057#L973-27 assume !(0 != activate_threads_~tmp___1~0); 478055#L973-29 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 478047#L435-27 assume !(1 == ~t3_pc~0); 478045#L435-29 is_transmit3_triggered_~__retres1~3 := 0; 478043#L446-9 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 478040#L447-9 activate_threads_#t~ret14 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 478038#L981-27 assume !(0 != activate_threads_~tmp___2~0); 478036#L981-29 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 478033#L454-27 assume !(1 == ~t4_pc~0); 478031#L454-29 is_transmit4_triggered_~__retres1~4 := 0; 478029#L465-9 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 478027#L466-9 activate_threads_#t~ret15 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 478024#L989-27 assume !(0 != activate_threads_~tmp___3~0); 478021#L989-29 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 478018#L473-27 assume !(1 == ~t5_pc~0); 478013#L473-29 is_transmit5_triggered_~__retres1~5 := 0; 478010#L484-9 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 478006#L485-9 activate_threads_#t~ret16 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 478003#L997-27 assume !(0 != activate_threads_~tmp___4~0); 478000#L997-29 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 477998#L492-27 assume !(1 == ~t6_pc~0); 477996#L492-29 is_transmit6_triggered_~__retres1~6 := 0; 477993#L503-9 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 477989#L504-9 activate_threads_#t~ret17 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 477986#L1005-27 assume !(0 != activate_threads_~tmp___5~0); 477984#L1005-29 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 477980#L511-27 assume !(1 == ~t7_pc~0); 477976#L511-29 is_transmit7_triggered_~__retres1~7 := 0; 477973#L522-9 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 477968#L523-9 activate_threads_#t~ret18 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 477961#L1013-27 assume !(0 != activate_threads_~tmp___6~0); 477953#L1013-29 assume 1 == ~M_E~0;~M_E~0 := 2; 477942#L859-3 assume !(1 == ~T1_E~0); 477933#L864-3 assume !(1 == ~T2_E~0); 477926#L869-3 assume !(1 == ~T3_E~0); 477918#L874-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 477913#L879-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 477907#L884-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 477902#L889-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 477897#L894-3 assume 1 == ~E_M~0;~E_M~0 := 2; 477892#L899-3 assume !(1 == ~E_1~0); 477886#L904-3 assume !(1 == ~E_2~0); 477733#L909-3 assume !(1 == ~E_3~0); 477622#L914-3 assume 1 == ~E_4~0;~E_4~0 := 2; 477616#L919-3 assume !(1 == ~E_5~0); 477596#L924-3 assume 1 == ~E_6~0;~E_6~0 := 2; 477588#L929-3 assume !(1 == ~E_7~0); 477580#L934-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~8;havoc exists_runnable_thread_~__retres1~8; 477573#L586-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8 := 1; 477565#L628-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; 477557#L629-1 start_simulation_#t~ret20 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret20;havoc start_simulation_#t~ret20; 477548#L1199 assume !(0 == start_simulation_~tmp~3); 477541#L1199-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret19, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~8;havoc exists_runnable_thread_~__retres1~8; 477534#L586-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8 := 1; 477526#L628-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; 477517#L629-2 stop_simulation_#t~ret19 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret19;havoc stop_simulation_#t~ret19; 477509#L1154 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 477501#L1161 stop_simulation_#res := stop_simulation_~__retres2~0; 477493#L1162 start_simulation_#t~ret21 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret21;havoc start_simulation_#t~ret21; 477486#L1212 assume !(0 != start_simulation_~tmp___0~1); 477476#L1180-1 assume !false; 469721#L1181 [2018-11-23 16:06:25,268 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 16:06:25,268 INFO L82 PathProgramCache]: Analyzing trace with hash 1393832633, now seen corresponding path program 2 times [2018-11-23 16:06:25,268 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 16:06:25,268 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 16:06:25,269 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 16:06:25,269 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 16:06:25,269 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 16:06:25,273 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-23 16:06:25,278 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-23 16:06:25,295 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 16:06:25,295 INFO L82 PathProgramCache]: Analyzing trace with hash 1890026491, now seen corresponding path program 1 times [2018-11-23 16:06:25,295 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 16:06:25,295 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 16:06:25,296 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 16:06:25,296 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-23 16:06:25,296 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 16:06:25,299 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 16:06:25,342 INFO L134 CoverageAnalysis]: Checked inductivity of 6 backedges. 6 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 16:06:25,342 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 16:06:25,343 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2018-11-23 16:06:25,343 INFO L811 eck$LassoCheckResult]: loop already infeasible [2018-11-23 16:06:25,343 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2018-11-23 16:06:25,343 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=21, Unknown=0, NotChecked=0, Total=30 [2018-11-23 16:06:25,343 INFO L87 Difference]: Start difference. First operand 24967 states and 31796 transitions. cyclomatic complexity: 6849 Second operand 6 states. [2018-11-23 16:06:25,543 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 16:06:25,543 INFO L93 Difference]: Finished difference Result 38592 states and 48876 transitions. [2018-11-23 16:06:25,543 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2018-11-23 16:06:25,543 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 38592 states and 48876 transitions. [2018-11-23 16:06:25,612 INFO L131 ngComponentsAnalysis]: Automaton has 24 accepting balls. 23357 [2018-11-23 16:06:25,661 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 38592 states to 38592 states and 48876 transitions. [2018-11-23 16:06:25,661 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 23597 [2018-11-23 16:06:25,672 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 23597 [2018-11-23 16:06:25,672 INFO L73 IsDeterministic]: Start isDeterministic. Operand 38592 states and 48876 transitions. [2018-11-23 16:06:25,675 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2018-11-23 16:06:25,675 INFO L705 BuchiCegarLoop]: Abstraction has 38592 states and 48876 transitions. [2018-11-23 16:06:25,690 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 38592 states and 48876 transitions. [2018-11-23 16:06:25,833 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 38592 to 32466. [2018-11-23 16:06:25,834 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 32466 states. [2018-11-23 16:06:25,858 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 32466 states to 32466 states and 40930 transitions. [2018-11-23 16:06:25,859 INFO L728 BuchiCegarLoop]: Abstraction has 32466 states and 40930 transitions. [2018-11-23 16:06:25,859 INFO L608 BuchiCegarLoop]: Abstraction has 32466 states and 40930 transitions. [2018-11-23 16:06:25,859 INFO L442 BuchiCegarLoop]: ======== Iteration 32============ [2018-11-23 16:06:25,859 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 32466 states and 40930 transitions. [2018-11-23 16:06:25,901 INFO L131 ngComponentsAnalysis]: Automaton has 24 accepting balls. 19683 [2018-11-23 16:06:25,901 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-23 16:06:25,902 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-23 16:06:25,902 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 16:06:25,902 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 16:06:25,903 INFO L794 eck$LassoCheckResult]: Stem: 530719#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; 530535#L-1 havoc main_#res;havoc main_~__retres1~9;havoc main_~__retres1~9;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 530536#L1143 havoc start_simulation_#t~ret20, start_simulation_#t~ret21, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 530487#L531 assume 1 == ~m_i~0;~m_st~0 := 0; 530488#L538-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 531041#L543-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 530842#L548-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 530489#L553-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 530490#L558-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 531202#L563-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 530826#L568-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 530461#L573-1 assume !(0 == ~M_E~0); 530462#L771-1 assume !(0 == ~T1_E~0); 530148#L776-1 assume !(0 == ~T2_E~0); 530149#L781-1 assume !(0 == ~T3_E~0); 530952#L786-1 assume !(0 == ~T4_E~0); 530619#L791-1 assume !(0 == ~T5_E~0); 530045#L796-1 assume !(0 == ~T6_E~0); 530046#L801-1 assume !(0 == ~T7_E~0); 531369#L806-1 assume !(0 == ~E_M~0); 530769#L811-1 assume !(0 == ~E_1~0); 530356#L816-1 assume !(0 == ~E_2~0); 530357#L821-1 assume !(0 == ~E_3~0); 531456#L826-1 assume !(0 == ~E_4~0); 531123#L831-1 assume !(0 == ~E_5~0); 530750#L836-1 assume !(0 == ~E_6~0); 529882#L841-1 assume !(0 == ~E_7~0); 529883#L846-1 havoc activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 530018#L378 assume !(1 == ~m_pc~0); 529972#L378-2 is_master_triggered_~__retres1~0 := 0; 529973#L389 is_master_triggered_#res := is_master_triggered_~__retres1~0; 531060#L390 activate_threads_#t~ret11 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 531162#L957 assume !(0 != activate_threads_~tmp~1); 531510#L957-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 530431#L397 assume !(1 == ~t1_pc~0); 530273#L397-2 is_transmit1_triggered_~__retres1~1 := 0; 530440#L408 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 531170#L409 activate_threads_#t~ret12 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 530774#L965 assume !(0 != activate_threads_~tmp___0~0); 530760#L965-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 530761#L416 assume !(1 == ~t2_pc~0); 530572#L416-2 is_transmit2_triggered_~__retres1~2 := 0; 530647#L427 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 531410#L428 activate_threads_#t~ret13 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 529921#L973 assume !(0 != activate_threads_~tmp___1~0); 529922#L973-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 529931#L435 assume !(1 == ~t3_pc~0); 531103#L435-2 is_transmit3_triggered_~__retres1~3 := 0; 530090#L446 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 530091#L447 activate_threads_#t~ret14 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 531247#L981 assume !(0 != activate_threads_~tmp___2~0); 531225#L981-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 531226#L454 assume !(1 == ~t4_pc~0); 531348#L454-2 is_transmit4_triggered_~__retres1~4 := 0; 530495#L465 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 530008#L466 activate_threads_#t~ret15 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 530009#L989 assume !(0 != activate_threads_~tmp___3~0); 530627#L989-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 530631#L473 assume !(1 == ~t5_pc~0); 531333#L473-2 is_transmit5_triggered_~__retres1~5 := 0; 531490#L484 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 531619#L485 activate_threads_#t~ret16 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 531574#L997 assume !(0 != activate_threads_~tmp___4~0); 531564#L997-2 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 531565#L492 assume !(1 == ~t6_pc~0); 531618#L492-2 is_transmit6_triggered_~__retres1~6 := 0; 530920#L503 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 530843#L504 activate_threads_#t~ret17 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 530844#L1005 assume !(0 != activate_threads_~tmp___5~0); 531340#L1005-2 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 529873#L511 assume !(1 == ~t7_pc~0); 529874#L511-2 is_transmit7_triggered_~__retres1~7 := 0; 530256#L522 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 530948#L523 activate_threads_#t~ret18 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 530716#L1013 assume !(0 != activate_threads_~tmp___6~0); 530701#L1013-2 assume !(1 == ~M_E~0); 530702#L859-1 assume !(1 == ~T1_E~0); 530175#L864-1 assume !(1 == ~T2_E~0); 530176#L869-1 assume !(1 == ~T3_E~0); 530949#L874-1 assume !(1 == ~T4_E~0); 530605#L879-1 assume !(1 == ~T5_E~0); 530039#L884-1 assume !(1 == ~T6_E~0); 530040#L889-1 assume !(1 == ~T7_E~0); 531366#L894-1 assume !(1 == ~E_M~0); 530762#L899-1 assume !(1 == ~E_1~0); 530345#L904-1 assume !(1 == ~E_2~0); 530346#L909-1 assume !(1 == ~E_3~0); 531461#L914-1 assume !(1 == ~E_4~0); 531132#L919-1 assume !(1 == ~E_5~0); 530759#L924-1 assume !(1 == ~E_6~0); 529934#L929-1 assume !(1 == ~E_7~0); 529935#L1180-1 assume !false; 532677#L1181 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret2, eval_#t~nondet3, eval_~tmp_ndt_1~0, eval_#t~nondet4, eval_~tmp_ndt_2~0, eval_#t~nondet5, eval_~tmp_ndt_3~0, eval_#t~nondet6, eval_~tmp_ndt_4~0, eval_#t~nondet7, eval_~tmp_ndt_5~0, eval_#t~nondet8, eval_~tmp_ndt_6~0, eval_#t~nondet9, eval_~tmp_ndt_7~0, eval_#t~nondet10, eval_~tmp_ndt_8~0, eval_~tmp~0;havoc eval_~tmp~0; 532670#L746 [2018-11-23 16:06:25,903 INFO L796 eck$LassoCheckResult]: Loop: 532670#L746 assume !false; 532665#L639 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~8;havoc exists_runnable_thread_~__retres1~8; 532660#L586 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8 := 1; 532656#L628 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; 532652#L629 eval_#t~ret2 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret2;havoc eval_#t~ret2; 532648#L643 assume 0 != eval_~tmp~0; 532641#L643-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0;eval_~tmp_ndt_1~0 := eval_#t~nondet3;havoc eval_#t~nondet3; 532634#L651 assume !(0 != eval_~tmp_ndt_1~0); 532628#L648 assume !(0 == ~t1_st~0); 532625#L662 assume !(0 == ~t2_st~0); 532621#L676 assume !(0 == ~t3_st~0); 532615#L690 assume !(0 == ~t4_st~0); 532611#L704 assume !(0 == ~t5_st~0); 532607#L718 assume !(0 == ~t6_st~0); 532606#L732 assume !(0 == ~t7_st~0); 532670#L746 [2018-11-23 16:06:25,903 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 16:06:25,903 INFO L82 PathProgramCache]: Analyzing trace with hash 259139107, now seen corresponding path program 1 times [2018-11-23 16:06:25,903 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 16:06:25,903 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 16:06:25,904 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 16:06:25,904 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 16:06:25,904 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 16:06:25,908 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-23 16:06:25,913 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-23 16:06:25,929 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 16:06:25,929 INFO L82 PathProgramCache]: Analyzing trace with hash 542398742, now seen corresponding path program 1 times [2018-11-23 16:06:25,930 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 16:06:25,930 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 16:06:25,930 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 16:06:25,930 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 16:06:25,930 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 16:06:25,932 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-23 16:06:25,933 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-23 16:06:25,934 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 16:06:25,934 INFO L82 PathProgramCache]: Analyzing trace with hash -1695487308, now seen corresponding path program 1 times [2018-11-23 16:06:25,934 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 16:06:25,935 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 16:06:25,935 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 16:06:25,935 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 16:06:25,935 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 16:06:25,940 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 16:06:25,971 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 16:06:25,971 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 16:06:25,971 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-23 16:06:26,038 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-23 16:06:26,038 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-23 16:06:26,039 INFO L87 Difference]: Start difference. First operand 32466 states and 40930 transitions. cyclomatic complexity: 8504 Second operand 3 states. [2018-11-23 16:06:26,133 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 16:06:26,133 INFO L93 Difference]: Finished difference Result 56473 states and 70772 transitions. [2018-11-23 16:06:26,135 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-23 16:06:26,135 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 56473 states and 70772 transitions. [2018-11-23 16:06:26,243 INFO L131 ngComponentsAnalysis]: Automaton has 24 accepting balls. 34292 [2018-11-23 16:06:26,320 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 56473 states to 56473 states and 70772 transitions. [2018-11-23 16:06:26,320 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 34703 [2018-11-23 16:06:26,333 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 34703 [2018-11-23 16:06:26,333 INFO L73 IsDeterministic]: Start isDeterministic. Operand 56473 states and 70772 transitions. [2018-11-23 16:06:26,333 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2018-11-23 16:06:26,333 INFO L705 BuchiCegarLoop]: Abstraction has 56473 states and 70772 transitions. [2018-11-23 16:06:26,360 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 56473 states and 70772 transitions. [2018-11-23 16:06:26,796 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 56473 to 56413. [2018-11-23 16:06:26,797 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 56413 states. [2018-11-23 16:06:26,841 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 56413 states to 56413 states and 70712 transitions. [2018-11-23 16:06:26,842 INFO L728 BuchiCegarLoop]: Abstraction has 56413 states and 70712 transitions. [2018-11-23 16:06:26,842 INFO L608 BuchiCegarLoop]: Abstraction has 56413 states and 70712 transitions. [2018-11-23 16:06:26,842 INFO L442 BuchiCegarLoop]: ======== Iteration 33============ [2018-11-23 16:06:26,842 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 56413 states and 70712 transitions. [2018-11-23 16:06:26,921 INFO L131 ngComponentsAnalysis]: Automaton has 24 accepting balls. 34256 [2018-11-23 16:06:26,921 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-23 16:06:26,921 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-23 16:06:26,922 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 16:06:26,922 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 16:06:26,922 INFO L794 eck$LassoCheckResult]: Stem: 619674#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; 619486#L-1 havoc main_#res;havoc main_~__retres1~9;havoc main_~__retres1~9;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 619487#L1143 havoc start_simulation_#t~ret20, start_simulation_#t~ret21, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 619439#L531 assume 1 == ~m_i~0;~m_st~0 := 0; 619440#L538-1 assume !(1 == ~t1_i~0);~t1_st~0 := 2; 620012#L543-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 619809#L548-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 619441#L553-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 619442#L558-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 620170#L563-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 619792#L568-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 619411#L573-1 assume !(0 == ~M_E~0); 619412#L771-1 assume !(0 == ~T1_E~0); 619084#L776-1 assume !(0 == ~T2_E~0); 619085#L781-1 assume !(0 == ~T3_E~0); 619919#L786-1 assume !(0 == ~T4_E~0); 619572#L791-1 assume !(0 == ~T5_E~0); 618981#L796-1 assume !(0 == ~T6_E~0); 618982#L801-1 assume !(0 == ~T7_E~0); 620340#L806-1 assume !(0 == ~E_M~0); 619728#L811-1 assume !(0 == ~E_1~0); 619306#L816-1 assume !(0 == ~E_2~0); 619307#L821-1 assume !(0 == ~E_3~0); 620439#L826-1 assume !(0 == ~E_4~0); 620096#L831-1 assume !(0 == ~E_5~0); 619707#L836-1 assume !(0 == ~E_6~0); 618826#L841-1 assume !(0 == ~E_7~0); 618827#L846-1 havoc activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 618954#L378 assume !(1 == ~m_pc~0); 618910#L378-2 is_master_triggered_~__retres1~0 := 0; 618911#L389 is_master_triggered_#res := is_master_triggered_~__retres1~0; 620023#L390 activate_threads_#t~ret11 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 620134#L957 assume !(0 != activate_threads_~tmp~1); 625360#L957-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 619379#L397 assume !(1 == ~t1_pc~0); 619222#L397-2 is_transmit1_triggered_~__retres1~1 := 0; 620271#L408 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 620140#L409 activate_threads_#t~ret12 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 619733#L965 assume !(0 != activate_threads_~tmp___0~0); 619719#L965-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 619720#L416 assume !(1 == ~t2_pc~0); 619525#L416-2 is_transmit2_triggered_~__retres1~2 := 0; 619599#L427 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 620383#L428 activate_threads_#t~ret13 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 618862#L973 assume !(0 != activate_threads_~tmp___1~0); 618863#L973-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 618871#L435 assume !(1 == ~t3_pc~0); 620075#L435-2 is_transmit3_triggered_~__retres1~3 := 0; 619023#L446 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 619024#L447 activate_threads_#t~ret14 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 620217#L981 assume !(0 != activate_threads_~tmp___2~0); 620194#L981-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 620195#L454 assume !(1 == ~t4_pc~0); 620320#L454-2 is_transmit4_triggered_~__retres1~4 := 0; 619447#L465 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 618944#L466 activate_threads_#t~ret15 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 618945#L989 assume !(0 != activate_threads_~tmp___3~0); 619579#L989-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 619583#L473 assume !(1 == ~t5_pc~0); 625315#L473-2 is_transmit5_triggered_~__retres1~5 := 0; 625314#L484 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 625313#L485 activate_threads_#t~ret16 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 625311#L997 assume !(0 != activate_threads_~tmp___4~0); 625310#L997-2 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 625309#L492 assume !(1 == ~t6_pc~0); 625308#L492-2 is_transmit6_triggered_~__retres1~6 := 0; 625307#L503 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 625306#L504 activate_threads_#t~ret17 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 625305#L1005 assume !(0 != activate_threads_~tmp___5~0); 625304#L1005-2 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 618809#L511 assume !(1 == ~t7_pc~0); 618810#L511-2 is_transmit7_triggered_~__retres1~7 := 0; 619201#L522 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 619915#L523 activate_threads_#t~ret18 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 619670#L1013 assume !(0 != activate_threads_~tmp___6~0); 619656#L1013-2 assume !(1 == ~M_E~0); 619657#L859-1 assume !(1 == ~T1_E~0); 619115#L864-1 assume !(1 == ~T2_E~0); 619116#L869-1 assume !(1 == ~T3_E~0); 619916#L874-1 assume !(1 == ~T4_E~0); 619559#L879-1 assume !(1 == ~T5_E~0); 618975#L884-1 assume !(1 == ~T6_E~0); 618976#L889-1 assume !(1 == ~T7_E~0); 620337#L894-1 assume !(1 == ~E_M~0); 619721#L899-1 assume !(1 == ~E_1~0); 619295#L904-1 assume !(1 == ~E_2~0); 619296#L909-1 assume !(1 == ~E_3~0); 620446#L914-1 assume !(1 == ~E_4~0); 620101#L919-1 assume !(1 == ~E_5~0); 619718#L924-1 assume !(1 == ~E_6~0); 618874#L929-1 assume !(1 == ~E_7~0); 618875#L1180-1 assume !false; 627165#L1181 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret2, eval_#t~nondet3, eval_~tmp_ndt_1~0, eval_#t~nondet4, eval_~tmp_ndt_2~0, eval_#t~nondet5, eval_~tmp_ndt_3~0, eval_#t~nondet6, eval_~tmp_ndt_4~0, eval_#t~nondet7, eval_~tmp_ndt_5~0, eval_#t~nondet8, eval_~tmp_ndt_6~0, eval_#t~nondet9, eval_~tmp_ndt_7~0, eval_#t~nondet10, eval_~tmp_ndt_8~0, eval_~tmp~0;havoc eval_~tmp~0; 647914#L746 [2018-11-23 16:06:26,922 INFO L796 eck$LassoCheckResult]: Loop: 647914#L746 assume !false; 647912#L639 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~8;havoc exists_runnable_thread_~__retres1~8; 647910#L586 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8 := 1; 647909#L628 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; 647906#L629 eval_#t~ret2 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret2;havoc eval_#t~ret2; 647904#L643 assume 0 != eval_~tmp~0; 647902#L643-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0;eval_~tmp_ndt_1~0 := eval_#t~nondet3;havoc eval_#t~nondet3; 647899#L651 assume !(0 != eval_~tmp_ndt_1~0); 647399#L648 assume !(0 == ~t1_st~0); 647396#L662 assume !(0 == ~t2_st~0); 647393#L676 assume !(0 == ~t3_st~0); 647390#L690 assume !(0 == ~t4_st~0); 647389#L704 assume !(0 == ~t5_st~0); 649181#L718 assume !(0 == ~t6_st~0); 647919#L732 assume !(0 == ~t7_st~0); 647914#L746 [2018-11-23 16:06:26,922 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 16:06:26,922 INFO L82 PathProgramCache]: Analyzing trace with hash -511594459, now seen corresponding path program 1 times [2018-11-23 16:06:26,922 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 16:06:26,923 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 16:06:26,923 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 16:06:26,923 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 16:06:26,923 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 16:06:26,926 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 16:06:26,951 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 16:06:26,951 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 16:06:26,951 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-23 16:06:26,952 INFO L799 eck$LassoCheckResult]: stem already infeasible [2018-11-23 16:06:26,952 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 16:06:26,952 INFO L82 PathProgramCache]: Analyzing trace with hash 542398742, now seen corresponding path program 2 times [2018-11-23 16:06:26,952 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 16:06:26,952 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 16:06:26,952 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 16:06:26,953 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 16:06:26,953 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 16:06:26,954 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-23 16:06:26,955 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-23 16:06:27,024 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-23 16:06:27,024 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-23 16:06:27,024 INFO L87 Difference]: Start difference. First operand 56413 states and 70712 transitions. cyclomatic complexity: 14339 Second operand 3 states. [2018-11-23 16:06:27,115 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 16:06:27,115 INFO L93 Difference]: Finished difference Result 56317 states and 70590 transitions. [2018-11-23 16:06:27,115 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-23 16:06:27,115 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 56317 states and 70590 transitions. [2018-11-23 16:06:27,219 INFO L131 ngComponentsAnalysis]: Automaton has 24 accepting balls. 34256 [2018-11-23 16:06:27,291 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 56317 states to 56317 states and 70590 transitions. [2018-11-23 16:06:27,291 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 34572 [2018-11-23 16:06:27,305 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 34572 [2018-11-23 16:06:27,305 INFO L73 IsDeterministic]: Start isDeterministic. Operand 56317 states and 70590 transitions. [2018-11-23 16:06:27,305 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2018-11-23 16:06:27,305 INFO L705 BuchiCegarLoop]: Abstraction has 56317 states and 70590 transitions. [2018-11-23 16:06:27,325 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 56317 states and 70590 transitions. [2018-11-23 16:06:27,535 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 56317 to 56317. [2018-11-23 16:06:27,535 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 56317 states. [2018-11-23 16:06:27,581 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 56317 states to 56317 states and 70590 transitions. [2018-11-23 16:06:27,581 INFO L728 BuchiCegarLoop]: Abstraction has 56317 states and 70590 transitions. [2018-11-23 16:06:27,581 INFO L608 BuchiCegarLoop]: Abstraction has 56317 states and 70590 transitions. [2018-11-23 16:06:27,581 INFO L442 BuchiCegarLoop]: ======== Iteration 34============ [2018-11-23 16:06:27,581 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 56317 states and 70590 transitions. [2018-11-23 16:06:27,661 INFO L131 ngComponentsAnalysis]: Automaton has 24 accepting balls. 34256 [2018-11-23 16:06:27,662 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-23 16:06:27,662 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-23 16:06:27,662 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 16:06:27,662 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 16:06:27,662 INFO L794 eck$LassoCheckResult]: Stem: 732397#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; 732210#L-1 havoc main_#res;havoc main_~__retres1~9;havoc main_~__retres1~9;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 732211#L1143 havoc start_simulation_#t~ret20, start_simulation_#t~ret21, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 732162#L531 assume 1 == ~m_i~0;~m_st~0 := 0; 732163#L538-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 732729#L543-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 732530#L548-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 732164#L553-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 732165#L558-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 732870#L563-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 732514#L568-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 732136#L573-1 assume !(0 == ~M_E~0); 732137#L771-1 assume !(0 == ~T1_E~0); 731820#L776-1 assume !(0 == ~T2_E~0); 731821#L781-1 assume !(0 == ~T3_E~0); 732637#L786-1 assume !(0 == ~T4_E~0); 732299#L791-1 assume !(0 == ~T5_E~0); 731717#L796-1 assume !(0 == ~T6_E~0); 731718#L801-1 assume !(0 == ~T7_E~0); 733026#L806-1 assume !(0 == ~E_M~0); 732448#L811-1 assume !(0 == ~E_1~0); 732033#L816-1 assume !(0 == ~E_2~0); 732034#L821-1 assume !(0 == ~E_3~0); 733118#L826-1 assume !(0 == ~E_4~0); 732804#L831-1 assume !(0 == ~E_5~0); 732428#L836-1 assume !(0 == ~E_6~0); 731562#L841-1 assume !(0 == ~E_7~0); 731563#L846-1 havoc activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 731690#L378 assume !(1 == ~m_pc~0); 731646#L378-2 is_master_triggered_~__retres1~0 := 0; 731647#L389 is_master_triggered_#res := is_master_triggered_~__retres1~0; 732742#L390 activate_threads_#t~ret11 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 732834#L957 assume !(0 != activate_threads_~tmp~1); 733168#L957-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 732107#L397 assume !(1 == ~t1_pc~0); 731949#L397-2 is_transmit1_triggered_~__retres1~1 := 0; 732116#L408 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 732839#L409 activate_threads_#t~ret12 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 732453#L965 assume !(0 != activate_threads_~tmp___0~0); 732439#L965-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 732440#L416 assume !(1 == ~t2_pc~0); 732249#L416-2 is_transmit2_triggered_~__retres1~2 := 0; 732326#L427 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 733066#L428 activate_threads_#t~ret13 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 731600#L973 assume !(0 != activate_threads_~tmp___1~0); 731601#L973-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 731608#L435 assume !(1 == ~t3_pc~0); 732786#L435-2 is_transmit3_triggered_~__retres1~3 := 0; 731759#L446 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 731760#L447 activate_threads_#t~ret14 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 732912#L981 assume !(0 != activate_threads_~tmp___2~0); 732893#L981-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 732894#L454 assume !(1 == ~t4_pc~0); 733007#L454-2 is_transmit4_triggered_~__retres1~4 := 0; 732170#L465 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 731680#L466 activate_threads_#t~ret15 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 731681#L989 assume !(0 != activate_threads_~tmp___3~0); 732306#L989-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 732310#L473 assume !(1 == ~t5_pc~0); 732998#L473-2 is_transmit5_triggered_~__retres1~5 := 0; 733151#L484 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 733266#L485 activate_threads_#t~ret16 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 733226#L997 assume !(0 != activate_threads_~tmp___4~0); 733217#L997-2 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 733218#L492 assume !(1 == ~t6_pc~0); 733265#L492-2 is_transmit6_triggered_~__retres1~6 := 0; 732607#L503 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 732531#L504 activate_threads_#t~ret17 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 732532#L1005 assume !(0 != activate_threads_~tmp___5~0); 733001#L1005-2 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 731545#L511 assume !(1 == ~t7_pc~0); 731546#L511-2 is_transmit7_triggered_~__retres1~7 := 0; 731931#L522 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 732633#L523 activate_threads_#t~ret18 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 732394#L1013 assume !(0 != activate_threads_~tmp___6~0); 732379#L1013-2 assume !(1 == ~M_E~0); 732380#L859-1 assume !(1 == ~T1_E~0); 731850#L864-1 assume !(1 == ~T2_E~0); 731851#L869-1 assume !(1 == ~T3_E~0); 732634#L874-1 assume !(1 == ~T4_E~0); 732286#L879-1 assume !(1 == ~T5_E~0); 731711#L884-1 assume !(1 == ~T6_E~0); 731712#L889-1 assume !(1 == ~T7_E~0); 733023#L894-1 assume !(1 == ~E_M~0); 732441#L899-1 assume !(1 == ~E_1~0); 732021#L904-1 assume !(1 == ~E_2~0); 732022#L909-1 assume !(1 == ~E_3~0); 733127#L914-1 assume !(1 == ~E_4~0); 732808#L919-1 assume !(1 == ~E_5~0); 732438#L924-1 assume !(1 == ~E_6~0); 731611#L929-1 assume !(1 == ~E_7~0); 731612#L1180-1 assume !false; 738351#L1181 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret2, eval_#t~nondet3, eval_~tmp_ndt_1~0, eval_#t~nondet4, eval_~tmp_ndt_2~0, eval_#t~nondet5, eval_~tmp_ndt_3~0, eval_#t~nondet6, eval_~tmp_ndt_4~0, eval_#t~nondet7, eval_~tmp_ndt_5~0, eval_#t~nondet8, eval_~tmp_ndt_6~0, eval_#t~nondet9, eval_~tmp_ndt_7~0, eval_#t~nondet10, eval_~tmp_ndt_8~0, eval_~tmp~0;havoc eval_~tmp~0; 766079#L746 [2018-11-23 16:06:27,663 INFO L796 eck$LassoCheckResult]: Loop: 766079#L746 assume !false; 766076#L639 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~8;havoc exists_runnable_thread_~__retres1~8; 766074#L586 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8 := 1; 766071#L628 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; 766069#L629 eval_#t~ret2 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret2;havoc eval_#t~ret2; 766067#L643 assume 0 != eval_~tmp~0; 766065#L643-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0;eval_~tmp_ndt_1~0 := eval_#t~nondet3;havoc eval_#t~nondet3; 766062#L651 assume !(0 != eval_~tmp_ndt_1~0); 766063#L648 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0;eval_~tmp_ndt_2~0 := eval_#t~nondet4;havoc eval_#t~nondet4; 760267#L665 assume !(0 != eval_~tmp_ndt_2~0); 766153#L662 assume !(0 == ~t2_st~0); 766149#L676 assume !(0 == ~t3_st~0); 766145#L690 assume !(0 == ~t4_st~0); 766144#L704 assume !(0 == ~t5_st~0); 775524#L718 assume !(0 == ~t6_st~0); 775523#L732 assume !(0 == ~t7_st~0); 766079#L746 [2018-11-23 16:06:27,663 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 16:06:27,663 INFO L82 PathProgramCache]: Analyzing trace with hash 259139107, now seen corresponding path program 2 times [2018-11-23 16:06:27,663 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 16:06:27,663 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 16:06:27,663 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 16:06:27,664 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-23 16:06:27,664 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 16:06:27,672 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-23 16:06:27,676 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-23 16:06:27,694 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 16:06:27,694 INFO L82 PathProgramCache]: Analyzing trace with hash -1828219668, now seen corresponding path program 1 times [2018-11-23 16:06:27,694 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 16:06:27,694 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 16:06:27,695 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 16:06:27,695 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-23 16:06:27,695 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 16:06:27,696 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-23 16:06:27,697 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-23 16:06:27,698 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 16:06:27,699 INFO L82 PathProgramCache]: Analyzing trace with hash 1811756814, now seen corresponding path program 1 times [2018-11-23 16:06:27,699 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 16:06:27,699 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 16:06:27,699 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 16:06:27,699 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 16:06:27,699 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 16:06:27,704 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 16:06:27,726 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 16:06:27,727 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 16:06:27,727 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-23 16:06:27,803 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-23 16:06:27,803 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-23 16:06:27,803 INFO L87 Difference]: Start difference. First operand 56317 states and 70590 transitions. cyclomatic complexity: 14313 Second operand 3 states. [2018-11-23 16:06:28,002 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 16:06:28,002 INFO L93 Difference]: Finished difference Result 96673 states and 120834 transitions. [2018-11-23 16:06:28,002 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-23 16:06:28,002 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 96673 states and 120834 transitions. [2018-11-23 16:06:28,183 INFO L131 ngComponentsAnalysis]: Automaton has 24 accepting balls. 58988 [2018-11-23 16:06:28,606 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 96673 states to 96673 states and 120834 transitions. [2018-11-23 16:06:28,606 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 59520 [2018-11-23 16:06:28,618 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 59520 [2018-11-23 16:06:28,618 INFO L73 IsDeterministic]: Start isDeterministic. Operand 96673 states and 120834 transitions. [2018-11-23 16:06:28,618 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2018-11-23 16:06:28,618 INFO L705 BuchiCegarLoop]: Abstraction has 96673 states and 120834 transitions. [2018-11-23 16:06:28,641 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 96673 states and 120834 transitions. [2018-11-23 16:06:28,974 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 96673 to 96673. [2018-11-23 16:06:28,974 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 96673 states. [2018-11-23 16:06:29,051 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 96673 states to 96673 states and 120834 transitions. [2018-11-23 16:06:29,051 INFO L728 BuchiCegarLoop]: Abstraction has 96673 states and 120834 transitions. [2018-11-23 16:06:29,051 INFO L608 BuchiCegarLoop]: Abstraction has 96673 states and 120834 transitions. [2018-11-23 16:06:29,051 INFO L442 BuchiCegarLoop]: ======== Iteration 35============ [2018-11-23 16:06:29,051 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 96673 states and 120834 transitions. [2018-11-23 16:06:29,190 INFO L131 ngComponentsAnalysis]: Automaton has 24 accepting balls. 58988 [2018-11-23 16:06:29,191 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-23 16:06:29,191 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-23 16:06:29,191 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 16:06:29,191 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 16:06:29,191 INFO L794 eck$LassoCheckResult]: Stem: 885396#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; 885214#L-1 havoc main_#res;havoc main_~__retres1~9;havoc main_~__retres1~9;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 885215#L1143 havoc start_simulation_#t~ret20, start_simulation_#t~ret21, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 885166#L531 assume 1 == ~m_i~0;~m_st~0 := 0; 885167#L538-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 885737#L543-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 885536#L548-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 885168#L553-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 885169#L558-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 885892#L563-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 885520#L568-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 885143#L573-1 assume !(0 == ~M_E~0); 885144#L771-1 assume !(0 == ~T1_E~0); 884817#L776-1 assume !(0 == ~T2_E~0); 884818#L781-1 assume !(0 == ~T3_E~0); 885646#L786-1 assume !(0 == ~T4_E~0); 885296#L791-1 assume !(0 == ~T5_E~0); 884714#L796-1 assume !(0 == ~T6_E~0); 884715#L801-1 assume !(0 == ~T7_E~0); 886063#L806-1 assume !(0 == ~E_M~0); 885455#L811-1 assume !(0 == ~E_1~0); 885036#L816-1 assume !(0 == ~E_2~0); 885037#L821-1 assume !(0 == ~E_3~0); 886163#L826-1 assume !(0 == ~E_4~0); 885816#L831-1 assume !(0 == ~E_5~0); 885435#L836-1 assume !(0 == ~E_6~0); 884560#L841-1 assume !(0 == ~E_7~0); 884561#L846-1 havoc activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 884687#L378 assume !(1 == ~m_pc~0); 884643#L378-2 is_master_triggered_~__retres1~0 := 0; 884644#L389 is_master_triggered_#res := is_master_triggered_~__retres1~0; 885751#L390 activate_threads_#t~ret11 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 885855#L957 assume !(0 != activate_threads_~tmp~1); 886221#L957-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 885113#L397 assume !(1 == ~t1_pc~0); 884954#L397-2 is_transmit1_triggered_~__retres1~1 := 0; 885124#L408 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 885862#L409 activate_threads_#t~ret12 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 885460#L965 assume !(0 != activate_threads_~tmp___0~0); 885446#L965-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 885447#L416 assume !(1 == ~t2_pc~0); 885249#L416-2 is_transmit2_triggered_~__retres1~2 := 0; 885326#L427 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 886109#L428 activate_threads_#t~ret13 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 884595#L973 assume !(0 != activate_threads_~tmp___1~0); 884596#L973-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 884605#L435 assume !(1 == ~t3_pc~0); 885799#L435-2 is_transmit3_triggered_~__retres1~3 := 0; 884756#L446 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 884757#L447 activate_threads_#t~ret14 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 885934#L981 assume !(0 != activate_threads_~tmp___2~0); 885915#L981-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 885916#L454 assume !(1 == ~t4_pc~0); 886041#L454-2 is_transmit4_triggered_~__retres1~4 := 0; 885174#L465 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 884677#L466 activate_threads_#t~ret15 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 884678#L989 assume !(0 != activate_threads_~tmp___3~0); 885303#L989-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 885307#L473 assume !(1 == ~t5_pc~0); 886025#L473-2 is_transmit5_triggered_~__retres1~5 := 0; 886203#L484 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 886331#L485 activate_threads_#t~ret16 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 886284#L997 assume !(0 != activate_threads_~tmp___4~0); 886277#L997-2 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 886278#L492 assume !(1 == ~t6_pc~0); 886330#L492-2 is_transmit6_triggered_~__retres1~6 := 0; 885608#L503 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 885537#L504 activate_threads_#t~ret17 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 885538#L1005 assume !(0 != activate_threads_~tmp___5~0); 886030#L1005-2 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 884542#L511 assume !(1 == ~t7_pc~0); 884543#L511-2 is_transmit7_triggered_~__retres1~7 := 0; 884936#L522 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 885642#L523 activate_threads_#t~ret18 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 885393#L1013 assume !(0 != activate_threads_~tmp___6~0); 885379#L1013-2 assume !(1 == ~M_E~0); 885380#L859-1 assume !(1 == ~T1_E~0); 884847#L864-1 assume !(1 == ~T2_E~0); 884848#L869-1 assume !(1 == ~T3_E~0); 885643#L874-1 assume !(1 == ~T4_E~0); 885283#L879-1 assume !(1 == ~T5_E~0); 884708#L884-1 assume !(1 == ~T6_E~0); 884709#L889-1 assume !(1 == ~T7_E~0); 886060#L894-1 assume !(1 == ~E_M~0); 885448#L899-1 assume !(1 == ~E_1~0); 885025#L904-1 assume !(1 == ~E_2~0); 885026#L909-1 assume !(1 == ~E_3~0); 886171#L914-1 assume !(1 == ~E_4~0); 885823#L919-1 assume !(1 == ~E_5~0); 885445#L924-1 assume !(1 == ~E_6~0); 884607#L929-1 assume !(1 == ~E_7~0); 884608#L1180-1 assume !false; 891084#L1181 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret2, eval_#t~nondet3, eval_~tmp_ndt_1~0, eval_#t~nondet4, eval_~tmp_ndt_2~0, eval_#t~nondet5, eval_~tmp_ndt_3~0, eval_#t~nondet6, eval_~tmp_ndt_4~0, eval_#t~nondet7, eval_~tmp_ndt_5~0, eval_#t~nondet8, eval_~tmp_ndt_6~0, eval_#t~nondet9, eval_~tmp_ndt_7~0, eval_#t~nondet10, eval_~tmp_ndt_8~0, eval_~tmp~0;havoc eval_~tmp~0; 962763#L746 [2018-11-23 16:06:29,191 INFO L796 eck$LassoCheckResult]: Loop: 962763#L746 assume !false; 962754#L639 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~8;havoc exists_runnable_thread_~__retres1~8; 962747#L586 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8 := 1; 962740#L628 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; 962730#L629 eval_#t~ret2 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret2;havoc eval_#t~ret2; 962723#L643 assume 0 != eval_~tmp~0; 962722#L643-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0;eval_~tmp_ndt_1~0 := eval_#t~nondet3;havoc eval_#t~nondet3; 962711#L651 assume !(0 != eval_~tmp_ndt_1~0); 961415#L648 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0;eval_~tmp_ndt_2~0 := eval_#t~nondet4;havoc eval_#t~nondet4; 961409#L665 assume !(0 != eval_~tmp_ndt_2~0); 953393#L662 assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0;eval_~tmp_ndt_3~0 := eval_#t~nondet5;havoc eval_#t~nondet5; 953390#L679 assume !(0 != eval_~tmp_ndt_3~0); 953388#L676 assume !(0 == ~t3_st~0); 953386#L690 assume !(0 == ~t4_st~0); 962981#L704 assume !(0 == ~t5_st~0); 962977#L718 assume !(0 == ~t6_st~0); 962776#L732 assume !(0 == ~t7_st~0); 962763#L746 [2018-11-23 16:06:29,191 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 16:06:29,192 INFO L82 PathProgramCache]: Analyzing trace with hash 259139107, now seen corresponding path program 3 times [2018-11-23 16:06:29,192 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 16:06:29,192 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 16:06:29,192 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 16:06:29,192 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 16:06:29,193 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 16:06:29,197 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-23 16:06:29,202 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-23 16:06:29,221 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 16:06:29,221 INFO L82 PathProgramCache]: Analyzing trace with hash -1857247933, now seen corresponding path program 1 times [2018-11-23 16:06:29,221 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 16:06:29,221 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 16:06:29,221 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 16:06:29,222 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-23 16:06:29,222 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 16:06:29,223 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-23 16:06:29,224 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-23 16:06:29,226 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 16:06:29,226 INFO L82 PathProgramCache]: Analyzing trace with hash -687126687, now seen corresponding path program 1 times [2018-11-23 16:06:29,226 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 16:06:29,226 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 16:06:29,227 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 16:06:29,227 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 16:06:29,227 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 16:06:29,231 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 16:06:29,258 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 16:06:29,259 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 16:06:29,259 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-23 16:06:29,366 WARN L180 SmtUtils]: Spent 106.00 ms on a formula simplification. DAG size of input: 44 DAG size of output: 42 [2018-11-23 16:06:29,386 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-23 16:06:29,386 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-23 16:06:29,386 INFO L87 Difference]: Start difference. First operand 96673 states and 120834 transitions. cyclomatic complexity: 24201 Second operand 3 states. [2018-11-23 16:06:29,590 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 16:06:29,590 INFO L93 Difference]: Finished difference Result 128167 states and 159660 transitions. [2018-11-23 16:06:29,591 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-23 16:06:29,591 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 128167 states and 159660 transitions. [2018-11-23 16:06:29,839 INFO L131 ngComponentsAnalysis]: Automaton has 24 accepting balls. 78490 [2018-11-23 16:06:30,005 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 128167 states to 128167 states and 159660 transitions. [2018-11-23 16:06:30,005 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 79166 [2018-11-23 16:06:30,034 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 79166 [2018-11-23 16:06:30,034 INFO L73 IsDeterministic]: Start isDeterministic. Operand 128167 states and 159660 transitions. [2018-11-23 16:06:30,052 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2018-11-23 16:06:30,052 INFO L705 BuchiCegarLoop]: Abstraction has 128167 states and 159660 transitions. [2018-11-23 16:06:30,097 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 128167 states and 159660 transitions. [2018-11-23 16:06:32,634 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 128167 to 128167. [2018-11-23 16:06:32,635 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 128167 states. [2018-11-23 16:06:32,743 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 128167 states to 128167 states and 159660 transitions. [2018-11-23 16:06:32,743 INFO L728 BuchiCegarLoop]: Abstraction has 128167 states and 159660 transitions. [2018-11-23 16:06:32,743 INFO L608 BuchiCegarLoop]: Abstraction has 128167 states and 159660 transitions. [2018-11-23 16:06:32,743 INFO L442 BuchiCegarLoop]: ======== Iteration 36============ [2018-11-23 16:06:32,743 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 128167 states and 159660 transitions. [2018-11-23 16:06:32,938 INFO L131 ngComponentsAnalysis]: Automaton has 24 accepting balls. 78490 [2018-11-23 16:06:32,938 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-23 16:06:32,938 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-23 16:06:32,938 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 16:06:32,938 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 16:06:32,938 INFO L794 eck$LassoCheckResult]: Stem: 1110242#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; 1110056#L-1 havoc main_#res;havoc main_~__retres1~9;havoc main_~__retres1~9;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 1110057#L1143 havoc start_simulation_#t~ret20, start_simulation_#t~ret21, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 1110006#L531 assume 1 == ~m_i~0;~m_st~0 := 0; 1110007#L538-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1110579#L543-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1110381#L548-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 1110008#L553-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 1110009#L558-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 1110727#L563-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 1110364#L568-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 1109979#L573-1 assume !(0 == ~M_E~0); 1109980#L771-1 assume !(0 == ~T1_E~0); 1109659#L776-1 assume !(0 == ~T2_E~0); 1109660#L781-1 assume !(0 == ~T3_E~0); 1110488#L786-1 assume !(0 == ~T4_E~0); 1110138#L791-1 assume !(0 == ~T5_E~0); 1109555#L796-1 assume !(0 == ~T6_E~0); 1109556#L801-1 assume !(0 == ~T7_E~0); 1110885#L806-1 assume !(0 == ~E_M~0); 1110305#L811-1 assume !(0 == ~E_1~0); 1109876#L816-1 assume !(0 == ~E_2~0); 1109877#L821-1 assume !(0 == ~E_3~0); 1110973#L826-1 assume !(0 == ~E_4~0); 1110654#L831-1 assume !(0 == ~E_5~0); 1110282#L836-1 assume !(0 == ~E_6~0); 1109416#L841-1 assume !(0 == ~E_7~0); 1109417#L846-1 havoc activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 1109530#L378 assume !(1 == ~m_pc~0); 1109488#L378-2 is_master_triggered_~__retres1~0 := 0; 1109489#L389 is_master_triggered_#res := is_master_triggered_~__retres1~0; 1110595#L390 activate_threads_#t~ret11 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 1110691#L957 assume !(0 != activate_threads_~tmp~1); 1111029#L957-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 1109949#L397 assume !(1 == ~t1_pc~0); 1109796#L397-2 is_transmit1_triggered_~__retres1~1 := 0; 1109958#L408 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 1110698#L409 activate_threads_#t~ret12 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 1110310#L965 assume !(0 != activate_threads_~tmp___0~0); 1110296#L965-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 1110297#L416 assume !(1 == ~t2_pc~0); 1110091#L416-2 is_transmit2_triggered_~__retres1~2 := 0; 1110166#L427 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 1110926#L428 activate_threads_#t~ret13 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 1109446#L973 assume !(0 != activate_threads_~tmp___1~0); 1109447#L973-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 1109453#L435 assume !(1 == ~t3_pc~0); 1110637#L435-2 is_transmit3_triggered_~__retres1~3 := 0; 1109601#L446 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 1109602#L447 activate_threads_#t~ret14 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 1110772#L981 assume !(0 != activate_threads_~tmp___2~0); 1110750#L981-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 1110751#L454 assume !(1 == ~t4_pc~0); 1110867#L454-2 is_transmit4_triggered_~__retres1~4 := 0; 1110014#L465 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 1109520#L466 activate_threads_#t~ret15 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 1109521#L989 assume !(0 != activate_threads_~tmp___3~0); 1110145#L989-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 1110149#L473 assume !(1 == ~t5_pc~0); 1110853#L473-2 is_transmit5_triggered_~__retres1~5 := 0; 1111010#L484 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 1111137#L485 activate_threads_#t~ret16 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 1111093#L997 assume !(0 != activate_threads_~tmp___4~0); 1111086#L997-2 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 1111087#L492 assume !(1 == ~t6_pc~0); 1111131#L492-2 is_transmit6_triggered_~__retres1~6 := 0; 1110455#L503 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 1110382#L504 activate_threads_#t~ret17 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 1110383#L1005 assume !(0 != activate_threads_~tmp___5~0); 1110857#L1005-2 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 1109399#L511 assume !(1 == ~t7_pc~0); 1109400#L511-2 is_transmit7_triggered_~__retres1~7 := 0; 1109780#L522 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 1110483#L523 activate_threads_#t~ret18 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 1110239#L1013 assume !(0 != activate_threads_~tmp___6~0); 1110225#L1013-2 assume !(1 == ~M_E~0); 1110226#L859-1 assume !(1 == ~T1_E~0); 1109686#L864-1 assume !(1 == ~T2_E~0); 1109687#L869-1 assume !(1 == ~T3_E~0); 1110484#L874-1 assume !(1 == ~T4_E~0); 1110127#L879-1 assume !(1 == ~T5_E~0); 1109549#L884-1 assume !(1 == ~T6_E~0); 1109550#L889-1 assume !(1 == ~T7_E~0); 1110882#L894-1 assume !(1 == ~E_M~0); 1110302#L899-1 assume !(1 == ~E_1~0); 1109865#L904-1 assume !(1 == ~E_2~0); 1109866#L909-1 assume !(1 == ~E_3~0); 1110985#L914-1 assume !(1 == ~E_4~0); 1110661#L919-1 assume !(1 == ~E_5~0); 1110295#L924-1 assume !(1 == ~E_6~0); 1109454#L929-1 assume !(1 == ~E_7~0); 1109455#L1180-1 assume !false; 1125552#L1181 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret2, eval_#t~nondet3, eval_~tmp_ndt_1~0, eval_#t~nondet4, eval_~tmp_ndt_2~0, eval_#t~nondet5, eval_~tmp_ndt_3~0, eval_#t~nondet6, eval_~tmp_ndt_4~0, eval_#t~nondet7, eval_~tmp_ndt_5~0, eval_#t~nondet8, eval_~tmp_ndt_6~0, eval_#t~nondet9, eval_~tmp_ndt_7~0, eval_#t~nondet10, eval_~tmp_ndt_8~0, eval_~tmp~0;havoc eval_~tmp~0; 1161940#L746 [2018-11-23 16:06:32,939 INFO L796 eck$LassoCheckResult]: Loop: 1161940#L746 assume !false; 1161939#L639 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~8;havoc exists_runnable_thread_~__retres1~8; 1161938#L586 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8 := 1; 1161937#L628 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; 1161935#L629 eval_#t~ret2 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret2;havoc eval_#t~ret2; 1161933#L643 assume 0 != eval_~tmp~0; 1161932#L643-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0;eval_~tmp_ndt_1~0 := eval_#t~nondet3;havoc eval_#t~nondet3; 1161930#L651 assume !(0 != eval_~tmp_ndt_1~0); 1161931#L648 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0;eval_~tmp_ndt_2~0 := eval_#t~nondet4;havoc eval_#t~nondet4; 1166052#L665 assume !(0 != eval_~tmp_ndt_2~0); 1171914#L662 assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0;eval_~tmp_ndt_3~0 := eval_#t~nondet5;havoc eval_#t~nondet5; 1177851#L679 assume !(0 != eval_~tmp_ndt_3~0); 1177845#L676 assume 0 == ~t3_st~0;havoc eval_~tmp_ndt_4~0;eval_~tmp_ndt_4~0 := eval_#t~nondet6;havoc eval_#t~nondet6; 1177841#L693 assume !(0 != eval_~tmp_ndt_4~0); 1177842#L690 assume !(0 == ~t4_st~0); 1202412#L704 assume !(0 == ~t5_st~0); 1202408#L718 assume !(0 == ~t6_st~0); 1161944#L732 assume !(0 == ~t7_st~0); 1161940#L746 [2018-11-23 16:06:32,939 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 16:06:32,939 INFO L82 PathProgramCache]: Analyzing trace with hash 259139107, now seen corresponding path program 4 times [2018-11-23 16:06:32,939 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 16:06:32,939 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 16:06:32,940 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 16:06:32,940 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 16:06:32,940 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 16:06:32,944 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-23 16:06:32,948 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-23 16:06:32,966 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 16:06:32,966 INFO L82 PathProgramCache]: Analyzing trace with hash 305294527, now seen corresponding path program 1 times [2018-11-23 16:06:32,966 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 16:06:32,966 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 16:06:32,969 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 16:06:32,970 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-23 16:06:32,970 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 16:06:32,971 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-23 16:06:32,972 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-23 16:06:32,974 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 16:06:32,974 INFO L82 PathProgramCache]: Analyzing trace with hash -2075652511, now seen corresponding path program 1 times [2018-11-23 16:06:32,974 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 16:06:32,974 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 16:06:32,977 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 16:06:32,977 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 16:06:32,977 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 16:06:32,981 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 16:06:33,009 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 16:06:33,009 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 16:06:33,009 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-23 16:06:33,116 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-23 16:06:33,116 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-23 16:06:33,116 INFO L87 Difference]: Start difference. First operand 128167 states and 159660 transitions. cyclomatic complexity: 31533 Second operand 3 states. [2018-11-23 16:06:33,463 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 16:06:33,463 INFO L93 Difference]: Finished difference Result 200647 states and 249926 transitions. [2018-11-23 16:06:33,463 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-23 16:06:33,463 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 200647 states and 249926 transitions. [2018-11-23 16:06:33,895 INFO L131 ngComponentsAnalysis]: Automaton has 24 accepting balls. 127800 [2018-11-23 16:06:34,176 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 200647 states to 200647 states and 249926 transitions. [2018-11-23 16:06:34,176 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 128764 [2018-11-23 16:06:34,228 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 128764 [2018-11-23 16:06:34,228 INFO L73 IsDeterministic]: Start isDeterministic. Operand 200647 states and 249926 transitions. [2018-11-23 16:06:34,228 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2018-11-23 16:06:34,228 INFO L705 BuchiCegarLoop]: Abstraction has 200647 states and 249926 transitions. [2018-11-23 16:06:34,304 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 200647 states and 249926 transitions. [2018-11-23 16:06:35,505 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 200647 to 198631. [2018-11-23 16:06:35,505 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 198631 states. [2018-11-23 16:06:35,695 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 198631 states to 198631 states and 247514 transitions. [2018-11-23 16:06:35,695 INFO L728 BuchiCegarLoop]: Abstraction has 198631 states and 247514 transitions. [2018-11-23 16:06:35,695 INFO L608 BuchiCegarLoop]: Abstraction has 198631 states and 247514 transitions. [2018-11-23 16:06:35,695 INFO L442 BuchiCegarLoop]: ======== Iteration 37============ [2018-11-23 16:06:35,695 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 198631 states and 247514 transitions. [2018-11-23 16:06:36,016 INFO L131 ngComponentsAnalysis]: Automaton has 24 accepting balls. 125784 [2018-11-23 16:06:36,016 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-23 16:06:36,016 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-23 16:06:36,016 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 16:06:36,016 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 16:06:36,017 INFO L794 eck$LassoCheckResult]: Stem: 1439090#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; 1438898#L-1 havoc main_#res;havoc main_~__retres1~9;havoc main_~__retres1~9;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 1438899#L1143 havoc start_simulation_#t~ret20, start_simulation_#t~ret21, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 1438846#L531 assume 1 == ~m_i~0;~m_st~0 := 0; 1438847#L538-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1439452#L543-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1439243#L548-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 1438848#L553-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 1438849#L558-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 1439612#L563-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 1439217#L568-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 1438818#L573-1 assume !(0 == ~M_E~0); 1438819#L771-1 assume !(0 == ~T1_E~0); 1438493#L776-1 assume !(0 == ~T2_E~0); 1438494#L781-1 assume !(0 == ~T3_E~0); 1439360#L786-1 assume !(0 == ~T4_E~0); 1438986#L791-1 assume !(0 == ~T5_E~0); 1438390#L796-1 assume !(0 == ~T6_E~0); 1438391#L801-1 assume !(0 == ~T7_E~0); 1439800#L806-1 assume !(0 == ~E_M~0); 1439152#L811-1 assume !(0 == ~E_1~0); 1438711#L816-1 assume !(0 == ~E_2~0); 1438712#L821-1 assume !(0 == ~E_3~0); 1439902#L826-1 assume !(0 == ~E_4~0); 1439536#L831-1 assume !(0 == ~E_5~0); 1439129#L836-1 assume !(0 == ~E_6~0); 1438232#L841-1 assume !(0 == ~E_7~0); 1438233#L846-1 havoc activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 1438365#L378 assume !(1 == ~m_pc~0); 1438322#L378-2 is_master_triggered_~__retres1~0 := 0; 1438323#L389 is_master_triggered_#res := is_master_triggered_~__retres1~0; 1439465#L390 activate_threads_#t~ret11 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 1439571#L957 assume !(0 != activate_threads_~tmp~1); 1439966#L957-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 1438785#L397 assume !(1 == ~t1_pc~0); 1438627#L397-2 is_transmit1_triggered_~__retres1~1 := 0; 1438797#L408 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 1439582#L409 activate_threads_#t~ret12 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 1439157#L965 assume !(0 != activate_threads_~tmp___0~0); 1439143#L965-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 1439144#L416 assume !(1 == ~t2_pc~0); 1438936#L416-2 is_transmit2_triggered_~__retres1~2 := 0; 1439017#L427 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 1439848#L428 activate_threads_#t~ret13 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 1438272#L973 assume !(0 != activate_threads_~tmp___1~0); 1438273#L973-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 1438282#L435 assume !(1 == ~t3_pc~0); 1439517#L435-2 is_transmit3_triggered_~__retres1~3 := 0; 1438432#L446 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 1438433#L447 activate_threads_#t~ret14 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 1439661#L981 assume !(0 != activate_threads_~tmp___2~0); 1439641#L981-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 1439642#L454 assume !(1 == ~t4_pc~0); 1439774#L454-2 is_transmit4_triggered_~__retres1~4 := 0; 1438854#L465 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 1438355#L466 activate_threads_#t~ret15 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 1438356#L989 assume !(0 != activate_threads_~tmp___3~0); 1438993#L989-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 1438998#L473 assume !(1 == ~t5_pc~0); 1439753#L473-2 is_transmit5_triggered_~__retres1~5 := 0; 1439100#L484 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 1438822#L485 activate_threads_#t~ret16 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 1438823#L997 assume !(0 != activate_threads_~tmp___4~0); 1440021#L997-2 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 1440022#L492 assume !(1 == ~t6_pc~0); 1440084#L492-2 is_transmit6_triggered_~__retres1~6 := 0; 1439324#L503 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 1439244#L504 activate_threads_#t~ret17 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 1439245#L1005 assume !(0 != activate_threads_~tmp___5~0); 1439758#L1005-2 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 1438214#L511 assume !(1 == ~t7_pc~0); 1438215#L511-2 is_transmit7_triggered_~__retres1~7 := 0; 1438605#L522 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 1439356#L523 activate_threads_#t~ret18 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 1439086#L1013 assume !(0 != activate_threads_~tmp___6~0); 1439073#L1013-2 assume !(1 == ~M_E~0); 1439074#L859-1 assume !(1 == ~T1_E~0); 1438523#L864-1 assume !(1 == ~T2_E~0); 1438524#L869-1 assume !(1 == ~T3_E~0); 1439357#L874-1 assume !(1 == ~T4_E~0); 1438970#L879-1 assume !(1 == ~T5_E~0); 1438384#L884-1 assume !(1 == ~T6_E~0); 1438385#L889-1 assume !(1 == ~T7_E~0); 1439797#L894-1 assume !(1 == ~E_M~0); 1439145#L899-1 assume !(1 == ~E_1~0); 1438699#L904-1 assume !(1 == ~E_2~0); 1438700#L909-1 assume !(1 == ~E_3~0); 1439909#L914-1 assume !(1 == ~E_4~0); 1439543#L919-1 assume !(1 == ~E_5~0); 1439142#L924-1 assume !(1 == ~E_6~0); 1438285#L929-1 assume !(1 == ~E_7~0); 1438286#L1180-1 assume !false; 1469820#L1181 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret2, eval_#t~nondet3, eval_~tmp_ndt_1~0, eval_#t~nondet4, eval_~tmp_ndt_2~0, eval_#t~nondet5, eval_~tmp_ndt_3~0, eval_#t~nondet6, eval_~tmp_ndt_4~0, eval_#t~nondet7, eval_~tmp_ndt_5~0, eval_#t~nondet8, eval_~tmp_ndt_6~0, eval_#t~nondet9, eval_~tmp_ndt_7~0, eval_#t~nondet10, eval_~tmp_ndt_8~0, eval_~tmp~0;havoc eval_~tmp~0; 1519739#L746 [2018-11-23 16:06:36,017 INFO L796 eck$LassoCheckResult]: Loop: 1519739#L746 assume !false; 1519731#L639 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~8;havoc exists_runnable_thread_~__retres1~8; 1519726#L586 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8 := 1; 1519721#L628 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; 1519715#L629 eval_#t~ret2 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret2;havoc eval_#t~ret2; 1519709#L643 assume 0 != eval_~tmp~0; 1519703#L643-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0;eval_~tmp_ndt_1~0 := eval_#t~nondet3;havoc eval_#t~nondet3; 1519698#L651 assume !(0 != eval_~tmp_ndt_1~0); 1515717#L648 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0;eval_~tmp_ndt_2~0 := eval_#t~nondet4;havoc eval_#t~nondet4; 1515714#L665 assume !(0 != eval_~tmp_ndt_2~0); 1515712#L662 assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0;eval_~tmp_ndt_3~0 := eval_#t~nondet5;havoc eval_#t~nondet5; 1515700#L679 assume !(0 != eval_~tmp_ndt_3~0); 1515710#L676 assume 0 == ~t3_st~0;havoc eval_~tmp_ndt_4~0;eval_~tmp_ndt_4~0 := eval_#t~nondet6;havoc eval_#t~nondet6; 1519694#L693 assume !(0 != eval_~tmp_ndt_4~0); 1519695#L690 assume 0 == ~t4_st~0;havoc eval_~tmp_ndt_5~0;eval_~tmp_ndt_5~0 := eval_#t~nondet7;havoc eval_#t~nondet7; 1519799#L707 assume !(0 != eval_~tmp_ndt_5~0); 1519770#L704 assume !(0 == ~t5_st~0); 1519758#L718 assume !(0 == ~t6_st~0); 1519748#L732 assume !(0 == ~t7_st~0); 1519739#L746 [2018-11-23 16:06:36,017 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 16:06:36,017 INFO L82 PathProgramCache]: Analyzing trace with hash 259139107, now seen corresponding path program 5 times [2018-11-23 16:06:36,017 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 16:06:36,017 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 16:06:36,017 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 16:06:36,018 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 16:06:36,018 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 16:06:36,022 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-23 16:06:36,026 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-23 16:06:36,044 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 16:06:36,044 INFO L82 PathProgramCache]: Analyzing trace with hash 663084400, now seen corresponding path program 1 times [2018-11-23 16:06:36,044 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 16:06:36,044 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 16:06:36,045 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 16:06:36,045 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-23 16:06:36,045 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 16:06:36,046 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-23 16:06:36,047 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-23 16:06:36,049 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 16:06:36,049 INFO L82 PathProgramCache]: Analyzing trace with hash -131829746, now seen corresponding path program 1 times [2018-11-23 16:06:36,049 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 16:06:36,049 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 16:06:36,050 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 16:06:36,050 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 16:06:36,050 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 16:06:36,053 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 16:06:36,084 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 16:06:36,084 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 16:06:36,084 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-23 16:06:36,180 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-23 16:06:36,180 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-23 16:06:36,180 INFO L87 Difference]: Start difference. First operand 198631 states and 247514 transitions. cyclomatic complexity: 48923 Second operand 3 states. [2018-11-23 16:06:36,756 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 16:06:36,756 INFO L93 Difference]: Finished difference Result 366757 states and 456202 transitions. [2018-11-23 16:06:36,756 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-23 16:06:36,756 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 366757 states and 456202 transitions. [2018-11-23 16:06:37,556 INFO L131 ngComponentsAnalysis]: Automaton has 24 accepting balls. 232460 [2018-11-23 16:06:38,875 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 366757 states to 366757 states and 456202 transitions. [2018-11-23 16:06:38,875 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 234288 [2018-11-23 16:06:38,938 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 234288 [2018-11-23 16:06:38,938 INFO L73 IsDeterministic]: Start isDeterministic. Operand 366757 states and 456202 transitions. [2018-11-23 16:06:38,939 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2018-11-23 16:06:38,939 INFO L705 BuchiCegarLoop]: Abstraction has 366757 states and 456202 transitions. [2018-11-23 16:06:39,060 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 366757 states and 456202 transitions. [2018-11-23 16:06:40,521 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 366757 to 356389. [2018-11-23 16:06:40,521 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 356389 states. [2018-11-23 16:06:46,627 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 356389 states to 356389 states and 444394 transitions. [2018-11-23 16:06:46,627 INFO L728 BuchiCegarLoop]: Abstraction has 356389 states and 444394 transitions. [2018-11-23 16:06:46,627 INFO L608 BuchiCegarLoop]: Abstraction has 356389 states and 444394 transitions. [2018-11-23 16:06:46,627 INFO L442 BuchiCegarLoop]: ======== Iteration 38============ [2018-11-23 16:06:46,627 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 356389 states and 444394 transitions. [2018-11-23 16:06:47,014 INFO L131 ngComponentsAnalysis]: Automaton has 24 accepting balls. 225980 [2018-11-23 16:06:47,015 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-23 16:06:47,015 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-23 16:06:47,015 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 16:06:47,015 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 16:06:47,016 INFO L794 eck$LassoCheckResult]: Stem: 2004494#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; 2004301#L-1 havoc main_#res;havoc main_~__retres1~9;havoc main_~__retres1~9;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 2004302#L1143 havoc start_simulation_#t~ret20, start_simulation_#t~ret21, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 2004247#L531 assume 1 == ~m_i~0;~m_st~0 := 0; 2004248#L538-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 2004860#L543-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 2004639#L548-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 2004249#L553-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 2004250#L558-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 2005032#L563-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 2004618#L568-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 2004219#L573-1 assume !(0 == ~M_E~0); 2004220#L771-1 assume !(0 == ~T1_E~0); 2003887#L776-1 assume !(0 == ~T2_E~0); 2003888#L781-1 assume !(0 == ~T3_E~0); 2004761#L786-1 assume !(0 == ~T4_E~0); 2004386#L791-1 assume !(0 == ~T5_E~0); 2003783#L796-1 assume !(0 == ~T6_E~0); 2003784#L801-1 assume !(0 == ~T7_E~0); 2005221#L806-1 assume !(0 == ~E_M~0); 2004556#L811-1 assume !(0 == ~E_1~0); 2004110#L816-1 assume !(0 == ~E_2~0); 2004111#L821-1 assume !(0 == ~E_3~0); 2005318#L826-1 assume !(0 == ~E_4~0); 2004947#L831-1 assume !(0 == ~E_5~0); 2004534#L836-1 assume !(0 == ~E_6~0); 2003627#L841-1 assume !(0 == ~E_7~0); 2003628#L846-1 havoc activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 2003758#L378 assume !(1 == ~m_pc~0); 2003715#L378-2 is_master_triggered_~__retres1~0 := 0; 2003716#L389 is_master_triggered_#res := is_master_triggered_~__retres1~0; 2004874#L390 activate_threads_#t~ret11 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 2004992#L957 assume !(0 != activate_threads_~tmp~1); 2005394#L957-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 2004184#L397 assume !(1 == ~t1_pc~0); 2004024#L397-2 is_transmit1_triggered_~__retres1~1 := 0; 2004195#L408 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 2005001#L409 activate_threads_#t~ret12 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 2004561#L965 assume !(0 != activate_threads_~tmp___0~0); 2004545#L965-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 2004546#L416 assume !(1 == ~t2_pc~0); 2004337#L416-2 is_transmit2_triggered_~__retres1~2 := 0; 2004417#L427 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 2005269#L428 activate_threads_#t~ret13 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 2003666#L973 assume !(0 != activate_threads_~tmp___1~0); 2003667#L973-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 2003676#L435 assume !(1 == ~t3_pc~0); 2004926#L435-2 is_transmit3_triggered_~__retres1~3 := 0; 2003825#L446 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 2003826#L447 activate_threads_#t~ret14 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 2005078#L981 assume !(0 != activate_threads_~tmp___2~0); 2005057#L981-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 2005058#L454 assume !(1 == ~t4_pc~0); 2005198#L454-2 is_transmit4_triggered_~__retres1~4 := 0; 2004255#L465 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 2003748#L466 activate_threads_#t~ret15 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 2003749#L989 assume !(0 != activate_threads_~tmp___3~0); 2004393#L989-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 2004397#L473 assume !(1 == ~t5_pc~0); 2005180#L473-2 is_transmit5_triggered_~__retres1~5 := 0; 2004506#L484 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 2004223#L485 activate_threads_#t~ret16 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 2004224#L997 assume !(0 != activate_threads_~tmp___4~0); 2005453#L997-2 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 2005454#L492 assume !(1 == ~t6_pc~0); 2005520#L492-2 is_transmit6_triggered_~__retres1~6 := 0; 2004725#L503 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 2004640#L504 activate_threads_#t~ret17 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 2004641#L1005 assume !(0 != activate_threads_~tmp___5~0); 2005186#L1005-2 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 2003610#L511 assume !(1 == ~t7_pc~0); 2003611#L511-2 is_transmit7_triggered_~__retres1~7 := 0; 2004004#L522 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 2004757#L523 activate_threads_#t~ret18 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 2004489#L1013 assume !(0 != activate_threads_~tmp___6~0); 2004474#L1013-2 assume !(1 == ~M_E~0); 2004475#L859-1 assume !(1 == ~T1_E~0); 2003919#L864-1 assume !(1 == ~T2_E~0); 2003920#L869-1 assume !(1 == ~T3_E~0); 2004758#L874-1 assume !(1 == ~T4_E~0); 2004373#L879-1 assume !(1 == ~T5_E~0); 2003777#L884-1 assume !(1 == ~T6_E~0); 2003778#L889-1 assume !(1 == ~T7_E~0); 2005218#L894-1 assume !(1 == ~E_M~0); 2004547#L899-1 assume !(1 == ~E_1~0); 2004097#L904-1 assume !(1 == ~E_2~0); 2004098#L909-1 assume !(1 == ~E_3~0); 2005328#L914-1 assume !(1 == ~E_4~0); 2004957#L919-1 assume !(1 == ~E_5~0); 2004544#L924-1 assume !(1 == ~E_6~0); 2003678#L929-1 assume !(1 == ~E_7~0); 2003679#L1180-1 assume !false; 2127965#L1181 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret2, eval_#t~nondet3, eval_~tmp_ndt_1~0, eval_#t~nondet4, eval_~tmp_ndt_2~0, eval_#t~nondet5, eval_~tmp_ndt_3~0, eval_#t~nondet6, eval_~tmp_ndt_4~0, eval_#t~nondet7, eval_~tmp_ndt_5~0, eval_#t~nondet8, eval_~tmp_ndt_6~0, eval_#t~nondet9, eval_~tmp_ndt_7~0, eval_#t~nondet10, eval_~tmp_ndt_8~0, eval_~tmp~0;havoc eval_~tmp~0; 2353082#L746 [2018-11-23 16:06:47,016 INFO L796 eck$LassoCheckResult]: Loop: 2353082#L746 assume !false; 2353081#L639 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~8;havoc exists_runnable_thread_~__retres1~8; 2353080#L586 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8 := 1; 2353078#L628 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; 2353076#L629 eval_#t~ret2 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret2;havoc eval_#t~ret2; 2333843#L643 assume 0 != eval_~tmp~0; 2333842#L643-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0;eval_~tmp_ndt_1~0 := eval_#t~nondet3;havoc eval_#t~nondet3; 2333840#L651 assume !(0 != eval_~tmp_ndt_1~0); 2190759#L648 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0;eval_~tmp_ndt_2~0 := eval_#t~nondet4;havoc eval_#t~nondet4; 2190755#L665 assume !(0 != eval_~tmp_ndt_2~0); 2190753#L662 assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0;eval_~tmp_ndt_3~0 := eval_#t~nondet5;havoc eval_#t~nondet5; 2190741#L679 assume !(0 != eval_~tmp_ndt_3~0); 2190751#L676 assume 0 == ~t3_st~0;havoc eval_~tmp_ndt_4~0;eval_~tmp_ndt_4~0 := eval_#t~nondet6;havoc eval_#t~nondet6; 2221830#L693 assume !(0 != eval_~tmp_ndt_4~0); 2221829#L690 assume 0 == ~t4_st~0;havoc eval_~tmp_ndt_5~0;eval_~tmp_ndt_5~0 := eval_#t~nondet7;havoc eval_#t~nondet7; 2221827#L707 assume !(0 != eval_~tmp_ndt_5~0); 2221828#L704 assume 0 == ~t5_st~0;havoc eval_~tmp_ndt_6~0;eval_~tmp_ndt_6~0 := eval_#t~nondet8;havoc eval_#t~nondet8; 2184679#L721 assume !(0 != eval_~tmp_ndt_6~0); 2283186#L718 assume !(0 == ~t6_st~0); 2283067#L732 assume !(0 == ~t7_st~0); 2353082#L746 [2018-11-23 16:06:47,016 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 16:06:47,016 INFO L82 PathProgramCache]: Analyzing trace with hash 259139107, now seen corresponding path program 6 times [2018-11-23 16:06:47,016 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 16:06:47,016 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 16:06:47,017 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 16:06:47,017 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 16:06:47,017 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 16:06:47,020 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-23 16:06:47,024 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-23 16:06:47,044 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 16:06:47,044 INFO L82 PathProgramCache]: Analyzing trace with hash -926027630, now seen corresponding path program 1 times [2018-11-23 16:06:47,044 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 16:06:47,044 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 16:06:47,045 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 16:06:47,045 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-23 16:06:47,045 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 16:06:47,046 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-23 16:06:47,048 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-23 16:06:47,049 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 16:06:47,050 INFO L82 PathProgramCache]: Analyzing trace with hash 201437620, now seen corresponding path program 1 times [2018-11-23 16:06:47,050 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 16:06:47,050 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 16:06:47,050 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 16:06:47,050 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 16:06:47,050 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 16:06:47,054 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 16:06:47,099 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 16:06:47,100 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 16:06:47,100 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-23 16:06:47,189 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-23 16:06:47,189 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-23 16:06:47,189 INFO L87 Difference]: Start difference. First operand 356389 states and 444394 transitions. cyclomatic complexity: 88045 Second operand 3 states. [2018-11-23 16:06:48,001 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 16:06:48,001 INFO L93 Difference]: Finished difference Result 513005 states and 639600 transitions. [2018-11-23 16:06:48,002 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-23 16:06:48,002 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 513005 states and 639600 transitions. [2018-11-23 16:06:49,187 INFO L131 ngComponentsAnalysis]: Automaton has 24 accepting balls. 325482 [2018-11-23 16:06:49,949 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 513005 states to 513005 states and 639600 transitions. [2018-11-23 16:06:49,949 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 327814 [2018-11-23 16:06:50,082 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 327814 [2018-11-23 16:06:50,082 INFO L73 IsDeterministic]: Start isDeterministic. Operand 513005 states and 639600 transitions. [2018-11-23 16:06:50,083 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2018-11-23 16:06:50,083 INFO L705 BuchiCegarLoop]: Abstraction has 513005 states and 639600 transitions. [2018-11-23 16:06:50,286 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 513005 states and 639600 transitions. [2018-11-23 16:06:53,141 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 513005 to 505517. [2018-11-23 16:06:53,141 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 505517 states. [2018-11-23 16:06:53,681 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 505517 states to 505517 states and 630384 transitions. [2018-11-23 16:06:53,682 INFO L728 BuchiCegarLoop]: Abstraction has 505517 states and 630384 transitions. [2018-11-23 16:06:53,682 INFO L608 BuchiCegarLoop]: Abstraction has 505517 states and 630384 transitions. [2018-11-23 16:06:53,682 INFO L442 BuchiCegarLoop]: ======== Iteration 39============ [2018-11-23 16:06:53,682 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 505517 states and 630384 transitions. [2018-11-23 16:06:54,797 INFO L131 ngComponentsAnalysis]: Automaton has 24 accepting balls. 320802 [2018-11-23 16:06:54,797 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-23 16:06:54,797 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-23 16:06:54,798 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 16:06:54,798 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 16:06:54,798 INFO L794 eck$LassoCheckResult]: Stem: 2873891#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; 2873695#L-1 havoc main_#res;havoc main_~__retres1~9;havoc main_~__retres1~9;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 2873696#L1143 havoc start_simulation_#t~ret20, start_simulation_#t~ret21, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 2873642#L531 assume 1 == ~m_i~0;~m_st~0 := 0; 2873643#L538-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 2874258#L543-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 2874037#L548-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 2873644#L553-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 2873645#L558-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 2874441#L563-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 2874013#L568-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 2873613#L573-1 assume !(0 == ~M_E~0); 2873614#L771-1 assume !(0 == ~T1_E~0); 2873286#L776-1 assume !(0 == ~T2_E~0); 2873287#L781-1 assume !(0 == ~T3_E~0); 2874165#L786-1 assume !(0 == ~T4_E~0); 2873783#L791-1 assume !(0 == ~T5_E~0); 2873184#L796-1 assume !(0 == ~T6_E~0); 2873185#L801-1 assume !(0 == ~T7_E~0); 2874637#L806-1 assume !(0 == ~E_M~0); 2873949#L811-1 assume !(0 == ~E_1~0); 2873509#L816-1 assume !(0 == ~E_2~0); 2873510#L821-1 assume !(0 == ~E_3~0); 2874738#L826-1 assume !(0 == ~E_4~0); 2874361#L831-1 assume !(0 == ~E_5~0); 2873927#L836-1 assume !(0 == ~E_6~0); 2873030#L841-1 assume !(0 == ~E_7~0); 2873031#L846-1 havoc activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 2873159#L378 assume !(1 == ~m_pc~0); 2873117#L378-2 is_master_triggered_~__retres1~0 := 0; 2873118#L389 is_master_triggered_#res := is_master_triggered_~__retres1~0; 2874276#L390 activate_threads_#t~ret11 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 2874403#L957 assume !(0 != activate_threads_~tmp~1); 2874806#L957-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 2873582#L397 assume !(1 == ~t1_pc~0); 2873425#L397-2 is_transmit1_triggered_~__retres1~1 := 0; 2873592#L408 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 2874411#L409 activate_threads_#t~ret12 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 2873954#L965 assume !(0 != activate_threads_~tmp___0~0); 2873938#L965-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 2873939#L416 assume !(1 == ~t2_pc~0); 2873735#L416-2 is_transmit2_triggered_~__retres1~2 := 0; 2873816#L427 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 2874684#L428 activate_threads_#t~ret13 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 2873070#L973 assume !(0 != activate_threads_~tmp___1~0); 2873071#L973-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 2873078#L435 assume !(1 == ~t3_pc~0); 2874335#L435-2 is_transmit3_triggered_~__retres1~3 := 0; 2873226#L446 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 2873227#L447 activate_threads_#t~ret14 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 2874491#L981 assume !(0 != activate_threads_~tmp___2~0); 2874467#L981-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 2874468#L454 assume !(1 == ~t4_pc~0); 2874610#L454-2 is_transmit4_triggered_~__retres1~4 := 0; 2873650#L465 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 2873149#L466 activate_threads_#t~ret15 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 2873150#L989 assume !(0 != activate_threads_~tmp___3~0); 2873790#L989-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 2873795#L473 assume !(1 == ~t5_pc~0); 2874593#L473-2 is_transmit5_triggered_~__retres1~5 := 0; 2873902#L484 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 2873616#L485 activate_threads_#t~ret16 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 2873617#L997 assume !(0 != activate_threads_~tmp___4~0); 2874867#L997-2 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 2874868#L492 assume !(1 == ~t6_pc~0); 2874947#L492-2 is_transmit6_triggered_~__retres1~6 := 0; 2874124#L503 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 2874038#L504 activate_threads_#t~ret17 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 2874039#L1005 assume !(0 != activate_threads_~tmp___5~0); 2874597#L1005-2 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 2873013#L511 assume !(1 == ~t7_pc~0); 2873014#L511-2 is_transmit7_triggered_~__retres1~7 := 0; 2873403#L522 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 2874161#L523 activate_threads_#t~ret18 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 2873888#L1013 assume !(0 != activate_threads_~tmp___6~0); 2873871#L1013-2 assume !(1 == ~M_E~0); 2873872#L859-1 assume !(1 == ~T1_E~0); 2873320#L864-1 assume !(1 == ~T2_E~0); 2873321#L869-1 assume !(1 == ~T3_E~0); 2874162#L874-1 assume !(1 == ~T4_E~0); 2873770#L879-1 assume !(1 == ~T5_E~0); 2873178#L884-1 assume !(1 == ~T6_E~0); 2873179#L889-1 assume !(1 == ~T7_E~0); 2874634#L894-1 assume !(1 == ~E_M~0); 2873940#L899-1 assume !(1 == ~E_1~0); 2873498#L904-1 assume !(1 == ~E_2~0); 2873499#L909-1 assume !(1 == ~E_3~0); 2874753#L914-1 assume !(1 == ~E_4~0); 2874372#L919-1 assume !(1 == ~E_5~0); 2873937#L924-1 assume !(1 == ~E_6~0); 2873081#L929-1 assume !(1 == ~E_7~0); 2873082#L1180-1 assume !false; 3057266#L1181 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret2, eval_#t~nondet3, eval_~tmp_ndt_1~0, eval_#t~nondet4, eval_~tmp_ndt_2~0, eval_#t~nondet5, eval_~tmp_ndt_3~0, eval_#t~nondet6, eval_~tmp_ndt_4~0, eval_#t~nondet7, eval_~tmp_ndt_5~0, eval_#t~nondet8, eval_~tmp_ndt_6~0, eval_#t~nondet9, eval_~tmp_ndt_7~0, eval_#t~nondet10, eval_~tmp_ndt_8~0, eval_~tmp~0;havoc eval_~tmp~0; 3057267#L746 [2018-11-23 16:06:54,798 INFO L796 eck$LassoCheckResult]: Loop: 3057267#L746 assume !false; 3272468#L639 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~8;havoc exists_runnable_thread_~__retres1~8; 3272467#L586 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8 := 1; 3272466#L628 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; 3272465#L629 eval_#t~ret2 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret2;havoc eval_#t~ret2; 3272464#L643 assume 0 != eval_~tmp~0; 3272463#L643-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0;eval_~tmp_ndt_1~0 := eval_#t~nondet3;havoc eval_#t~nondet3; 3272462#L651 assume !(0 != eval_~tmp_ndt_1~0); 2980706#L648 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0;eval_~tmp_ndt_2~0 := eval_#t~nondet4;havoc eval_#t~nondet4; 2980702#L665 assume !(0 != eval_~tmp_ndt_2~0); 2980452#L662 assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0;eval_~tmp_ndt_3~0 := eval_#t~nondet5;havoc eval_#t~nondet5; 2980450#L679 assume !(0 != eval_~tmp_ndt_3~0); 2980449#L676 assume 0 == ~t3_st~0;havoc eval_~tmp_ndt_4~0;eval_~tmp_ndt_4~0 := eval_#t~nondet6;havoc eval_#t~nondet6; 2980447#L693 assume !(0 != eval_~tmp_ndt_4~0); 2980446#L690 assume 0 == ~t4_st~0;havoc eval_~tmp_ndt_5~0;eval_~tmp_ndt_5~0 := eval_#t~nondet7;havoc eval_#t~nondet7; 2980444#L707 assume !(0 != eval_~tmp_ndt_5~0); 2980445#L704 assume 0 == ~t5_st~0;havoc eval_~tmp_ndt_6~0;eval_~tmp_ndt_6~0 := eval_#t~nondet8;havoc eval_#t~nondet8; 3051734#L721 assume !(0 != eval_~tmp_ndt_6~0); 3051733#L718 assume 0 == ~t6_st~0;havoc eval_~tmp_ndt_7~0;eval_~tmp_ndt_7~0 := eval_#t~nondet9;havoc eval_#t~nondet9; 2992766#L735 assume !(0 != eval_~tmp_ndt_7~0); 2992767#L732 assume !(0 == ~t7_st~0); 3057267#L746 [2018-11-23 16:06:54,798 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 16:06:54,798 INFO L82 PathProgramCache]: Analyzing trace with hash 259139107, now seen corresponding path program 7 times [2018-11-23 16:06:54,799 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 16:06:54,799 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 16:06:54,799 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 16:06:54,799 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 16:06:54,799 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 16:06:54,801 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-23 16:06:54,804 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-23 16:06:54,819 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 16:06:54,819 INFO L82 PathProgramCache]: Analyzing trace with hash 1357697437, now seen corresponding path program 1 times [2018-11-23 16:06:54,819 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 16:06:54,819 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 16:06:54,819 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 16:06:54,820 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 16:06:54,820 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 16:06:54,821 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-23 16:06:54,822 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-23 16:06:54,824 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 16:06:54,824 INFO L82 PathProgramCache]: Analyzing trace with hash 1949381819, now seen corresponding path program 1 times [2018-11-23 16:06:54,824 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 16:06:54,824 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 16:06:54,825 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 16:06:54,825 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 16:06:54,825 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 16:06:54,828 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 16:06:54,859 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 16:06:54,860 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 16:06:54,860 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2018-11-23 16:06:54,970 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-23 16:06:54,970 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-23 16:06:54,971 INFO L87 Difference]: Start difference. First operand 505517 states and 630384 transitions. cyclomatic complexity: 124907 Second operand 3 states. [2018-11-23 16:06:56,556 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 16:06:56,556 INFO L93 Difference]: Finished difference Result 872280 states and 1087578 transitions. [2018-11-23 16:06:56,556 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-23 16:06:56,556 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 872280 states and 1087578 transitions. [2018-11-23 16:06:59,533 INFO L131 ngComponentsAnalysis]: Automaton has 24 accepting balls. 554036 [2018-11-23 16:07:00,643 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 872280 states to 872280 states and 1087578 transitions. [2018-11-23 16:07:00,643 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 558600 [2018-11-23 16:07:00,780 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 558600 [2018-11-23 16:07:00,781 INFO L73 IsDeterministic]: Start isDeterministic. Operand 872280 states and 1087578 transitions. [2018-11-23 16:07:00,793 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2018-11-23 16:07:00,793 INFO L705 BuchiCegarLoop]: Abstraction has 872280 states and 1087578 transitions. [2018-11-23 16:07:01,085 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 872280 states and 1087578 transitions. [2018-11-23 16:07:13,395 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 872280 to 872280. [2018-11-23 16:07:13,395 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 872280 states. [2018-11-23 16:07:15,092 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 872280 states to 872280 states and 1087578 transitions. [2018-11-23 16:07:15,092 INFO L728 BuchiCegarLoop]: Abstraction has 872280 states and 1087578 transitions. [2018-11-23 16:07:15,092 INFO L608 BuchiCegarLoop]: Abstraction has 872280 states and 1087578 transitions. [2018-11-23 16:07:15,092 INFO L442 BuchiCegarLoop]: ======== Iteration 40============ [2018-11-23 16:07:15,092 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 872280 states and 1087578 transitions. [2018-11-23 16:07:21,545 INFO L131 ngComponentsAnalysis]: Automaton has 24 accepting balls. 554036 [2018-11-23 16:07:21,546 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-23 16:07:21,546 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-23 16:07:21,546 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 16:07:21,546 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 16:07:21,546 INFO L794 eck$LassoCheckResult]: Stem: 4251685#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; 4251496#L-1 havoc main_#res;havoc main_~__retres1~9;havoc main_~__retres1~9;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 4251497#L1143 havoc start_simulation_#t~ret20, start_simulation_#t~ret21, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 4251442#L531 assume 1 == ~m_i~0;~m_st~0 := 0; 4251443#L538-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 4252043#L543-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 4251826#L548-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 4251444#L553-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 4251445#L558-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 4252210#L563-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 4251807#L568-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 4251415#L573-1 assume !(0 == ~M_E~0); 4251416#L771-1 assume !(0 == ~T1_E~0); 4251092#L776-1 assume !(0 == ~T2_E~0); 4251093#L781-1 assume !(0 == ~T3_E~0); 4251945#L786-1 assume !(0 == ~T4_E~0); 4251582#L791-1 assume !(0 == ~T5_E~0); 4250986#L796-1 assume !(0 == ~T6_E~0); 4250987#L801-1 assume !(0 == ~T7_E~0); 4252392#L806-1 assume !(0 == ~E_M~0); 4251742#L811-1 assume !(0 == ~E_1~0); 4251311#L816-1 assume !(0 == ~E_2~0); 4251312#L821-1 assume !(0 == ~E_3~0); 4252505#L826-1 assume !(0 == ~E_4~0); 4252133#L831-1 assume !(0 == ~E_5~0); 4251723#L836-1 assume !(0 == ~E_6~0); 4250833#L841-1 assume !(0 == ~E_7~0); 4250834#L846-1 havoc activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 4250961#L378 assume !(1 == ~m_pc~0); 4250919#L378-2 is_master_triggered_~__retres1~0 := 0; 4250920#L389 is_master_triggered_#res := is_master_triggered_~__retres1~0; 4252064#L390 activate_threads_#t~ret11 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 4252174#L957 assume !(0 != activate_threads_~tmp~1); 4252566#L957-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 4251384#L397 assume !(1 == ~t1_pc~0); 4251227#L397-2 is_transmit1_triggered_~__retres1~1 := 0; 4251395#L408 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 4252181#L409 activate_threads_#t~ret12 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 4251747#L965 assume !(0 != activate_threads_~tmp___0~0); 4251733#L965-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 4251734#L416 assume !(1 == ~t2_pc~0); 4251532#L416-2 is_transmit2_triggered_~__retres1~2 := 0; 4251610#L427 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 4252442#L428 activate_threads_#t~ret13 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 4250871#L973 assume !(0 != activate_threads_~tmp___1~0); 4250872#L973-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 4250881#L435 assume !(1 == ~t3_pc~0); 4252113#L435-2 is_transmit3_triggered_~__retres1~3 := 0; 4251032#L446 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 4251033#L447 activate_threads_#t~ret14 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 4252255#L981 assume !(0 != activate_threads_~tmp___2~0); 4252234#L981-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 4252235#L454 assume !(1 == ~t4_pc~0); 4252370#L454-2 is_transmit4_triggered_~__retres1~4 := 0; 4251450#L465 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 4250951#L466 activate_threads_#t~ret15 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 4250952#L989 assume !(0 != activate_threads_~tmp___3~0); 4251589#L989-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 4251593#L473 assume !(1 == ~t5_pc~0); 4252355#L473-2 is_transmit5_triggered_~__retres1~5 := 0; 4252548#L484 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 4253090#L485 activate_threads_#t~ret16 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 4252632#L997 assume !(0 != activate_threads_~tmp___4~0); 4252622#L997-2 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 4252623#L492 assume !(1 == ~t6_pc~0); 4252687#L492-2 is_transmit6_triggered_~__retres1~6 := 0; 4251904#L503 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 4251827#L504 activate_threads_#t~ret17 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 4251828#L1005 assume !(0 != activate_threads_~tmp___5~0); 4252360#L1005-2 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 4250816#L511 assume !(1 == ~t7_pc~0); 4250817#L511-2 is_transmit7_triggered_~__retres1~7 := 0; 4251205#L522 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 4251941#L523 activate_threads_#t~ret18 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 4251682#L1013 assume !(0 != activate_threads_~tmp___6~0); 4251669#L1013-2 assume !(1 == ~M_E~0); 4251670#L859-1 assume !(1 == ~T1_E~0); 4251119#L864-1 assume !(1 == ~T2_E~0); 4251120#L869-1 assume !(1 == ~T3_E~0); 4251942#L874-1 assume !(1 == ~T4_E~0); 4251566#L879-1 assume !(1 == ~T5_E~0); 4250980#L884-1 assume !(1 == ~T6_E~0); 4250981#L889-1 assume !(1 == ~T7_E~0); 4252389#L894-1 assume !(1 == ~E_M~0); 4251735#L899-1 assume !(1 == ~E_1~0); 4251300#L904-1 assume !(1 == ~E_2~0); 4251301#L909-1 assume !(1 == ~E_3~0); 4252514#L914-1 assume !(1 == ~E_4~0); 4252144#L919-1 assume !(1 == ~E_5~0); 4251732#L924-1 assume !(1 == ~E_6~0); 4250883#L929-1 assume !(1 == ~E_7~0); 4250884#L1180-1 assume !false; 4491861#L1181 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret2, eval_#t~nondet3, eval_~tmp_ndt_1~0, eval_#t~nondet4, eval_~tmp_ndt_2~0, eval_#t~nondet5, eval_~tmp_ndt_3~0, eval_#t~nondet6, eval_~tmp_ndt_4~0, eval_#t~nondet7, eval_~tmp_ndt_5~0, eval_#t~nondet8, eval_~tmp_ndt_6~0, eval_#t~nondet9, eval_~tmp_ndt_7~0, eval_#t~nondet10, eval_~tmp_ndt_8~0, eval_~tmp~0;havoc eval_~tmp~0; 4395027#L746 [2018-11-23 16:07:21,547 INFO L796 eck$LassoCheckResult]: Loop: 4395027#L746 assume !false; 4491856#L639 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~8;havoc exists_runnable_thread_~__retres1~8; 4491854#L586 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8 := 1; 4491851#L628 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; 4491849#L629 eval_#t~ret2 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret2;havoc eval_#t~ret2; 4491847#L643 assume 0 != eval_~tmp~0; 4491845#L643-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0;eval_~tmp_ndt_1~0 := eval_#t~nondet3;havoc eval_#t~nondet3; 4491842#L651 assume !(0 != eval_~tmp_ndt_1~0); 4431164#L648 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0;eval_~tmp_ndt_2~0 := eval_#t~nondet4;havoc eval_#t~nondet4; 4431162#L665 assume !(0 != eval_~tmp_ndt_2~0); 4431161#L662 assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0;eval_~tmp_ndt_3~0 := eval_#t~nondet5;havoc eval_#t~nondet5; 4393310#L679 assume !(0 != eval_~tmp_ndt_3~0); 4431160#L676 assume 0 == ~t3_st~0;havoc eval_~tmp_ndt_4~0;eval_~tmp_ndt_4~0 := eval_#t~nondet6;havoc eval_#t~nondet6; 4574401#L693 assume !(0 != eval_~tmp_ndt_4~0); 4574400#L690 assume 0 == ~t4_st~0;havoc eval_~tmp_ndt_5~0;eval_~tmp_ndt_5~0 := eval_#t~nondet7;havoc eval_#t~nondet7; 4574395#L707 assume !(0 != eval_~tmp_ndt_5~0); 4395039#L704 assume 0 == ~t5_st~0;havoc eval_~tmp_ndt_6~0;eval_~tmp_ndt_6~0 := eval_#t~nondet8;havoc eval_#t~nondet8; 4395036#L721 assume !(0 != eval_~tmp_ndt_6~0); 4395035#L718 assume 0 == ~t6_st~0;havoc eval_~tmp_ndt_7~0;eval_~tmp_ndt_7~0 := eval_#t~nondet9;havoc eval_#t~nondet9; 4395031#L735 assume !(0 != eval_~tmp_ndt_7~0); 4395029#L732 assume 0 == ~t7_st~0;havoc eval_~tmp_ndt_8~0;eval_~tmp_ndt_8~0 := eval_#t~nondet10;havoc eval_#t~nondet10; 4384841#L749 assume !(0 != eval_~tmp_ndt_8~0); 4395027#L746 [2018-11-23 16:07:21,547 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 16:07:21,547 INFO L82 PathProgramCache]: Analyzing trace with hash 259139107, now seen corresponding path program 8 times [2018-11-23 16:07:21,547 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 16:07:21,547 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 16:07:21,547 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 16:07:21,547 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 16:07:21,548 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 16:07:21,550 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-23 16:07:21,553 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-23 16:07:21,565 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 16:07:21,565 INFO L82 PathProgramCache]: Analyzing trace with hash -861056923, now seen corresponding path program 1 times [2018-11-23 16:07:21,565 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 16:07:21,565 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 16:07:21,566 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 16:07:21,566 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-23 16:07:21,566 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 16:07:21,567 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-23 16:07:21,568 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-23 16:07:21,570 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 16:07:21,570 INFO L82 PathProgramCache]: Analyzing trace with hash 301289735, now seen corresponding path program 1 times [2018-11-23 16:07:21,570 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 16:07:21,570 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 16:07:21,571 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 16:07:21,571 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 16:07:21,571 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 16:07:21,574 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-23 16:07:21,578 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-23 16:07:22,198 WARN L180 SmtUtils]: Spent 480.00 ms on a formula simplification. DAG size of input: 260 DAG size of output: 172 [2018-11-23 16:07:22,315 WARN L180 SmtUtils]: Spent 114.00 ms on a formula simplification that was a NOOP. DAG size: 138 ----- class de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder.RCFGBacktranslator [?] ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; [?] havoc main_#res;havoc main_~__retres1~9;havoc main_~__retres1~9;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; [?] havoc start_simulation_#t~ret20, start_simulation_#t~ret21, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; [?] assume 1 == ~m_i~0;~m_st~0 := 0; [?] assume 1 == ~t1_i~0;~t1_st~0 := 0; [?] assume 1 == ~t2_i~0;~t2_st~0 := 0; [?] assume 1 == ~t3_i~0;~t3_st~0 := 0; [?] assume 1 == ~t4_i~0;~t4_st~0 := 0; [?] assume 1 == ~t5_i~0;~t5_st~0 := 0; [?] assume 1 == ~t6_i~0;~t6_st~0 := 0; [?] assume 1 == ~t7_i~0;~t7_st~0 := 0; [?] assume !(0 == ~M_E~0); [?] assume !(0 == ~T1_E~0); [?] assume !(0 == ~T2_E~0); [?] assume !(0 == ~T3_E~0); [?] assume !(0 == ~T4_E~0); [?] assume !(0 == ~T5_E~0); [?] assume !(0 == ~T6_E~0); [?] assume !(0 == ~T7_E~0); [?] assume !(0 == ~E_M~0); [?] assume !(0 == ~E_1~0); [?] assume !(0 == ~E_2~0); [?] assume !(0 == ~E_3~0); [?] assume !(0 == ~E_4~0); [?] assume !(0 == ~E_5~0); [?] assume !(0 == ~E_6~0); [?] assume !(0 == ~E_7~0); [?] havoc activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; [?] assume !(1 == ~m_pc~0); [?] is_master_triggered_~__retres1~0 := 0; [?] is_master_triggered_#res := is_master_triggered_~__retres1~0; [?] activate_threads_#t~ret11 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; [?] assume !(0 != activate_threads_~tmp~1); [?] havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; [?] assume !(1 == ~t1_pc~0); [?] is_transmit1_triggered_~__retres1~1 := 0; [?] is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; [?] activate_threads_#t~ret12 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; [?] assume !(0 != activate_threads_~tmp___0~0); [?] havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; [?] assume !(1 == ~t2_pc~0); [?] is_transmit2_triggered_~__retres1~2 := 0; [?] is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; [?] activate_threads_#t~ret13 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; [?] assume !(0 != activate_threads_~tmp___1~0); [?] havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; [?] assume !(1 == ~t3_pc~0); [?] is_transmit3_triggered_~__retres1~3 := 0; [?] is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; [?] activate_threads_#t~ret14 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; [?] assume !(0 != activate_threads_~tmp___2~0); [?] havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; [?] assume !(1 == ~t4_pc~0); [?] is_transmit4_triggered_~__retres1~4 := 0; [?] is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; [?] activate_threads_#t~ret15 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; [?] assume !(0 != activate_threads_~tmp___3~0); [?] havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; [?] assume !(1 == ~t5_pc~0); [?] is_transmit5_triggered_~__retres1~5 := 0; [?] is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; [?] activate_threads_#t~ret16 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; [?] assume !(0 != activate_threads_~tmp___4~0); [?] havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; [?] assume !(1 == ~t6_pc~0); [?] is_transmit6_triggered_~__retres1~6 := 0; [?] is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; [?] activate_threads_#t~ret17 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; [?] assume !(0 != activate_threads_~tmp___5~0); [?] havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; [?] assume !(1 == ~t7_pc~0); [?] is_transmit7_triggered_~__retres1~7 := 0; [?] is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; [?] activate_threads_#t~ret18 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; [?] assume !(0 != activate_threads_~tmp___6~0); [?] assume !(1 == ~M_E~0); [?] assume !(1 == ~T1_E~0); [?] assume !(1 == ~T2_E~0); [?] assume !(1 == ~T3_E~0); [?] assume !(1 == ~T4_E~0); [?] assume !(1 == ~T5_E~0); [?] assume !(1 == ~T6_E~0); [?] assume !(1 == ~T7_E~0); [?] assume !(1 == ~E_M~0); [?] assume !(1 == ~E_1~0); [?] assume !(1 == ~E_2~0); [?] assume !(1 == ~E_3~0); [?] assume !(1 == ~E_4~0); [?] assume !(1 == ~E_5~0); [?] assume !(1 == ~E_6~0); [?] assume !(1 == ~E_7~0); [?] assume !false; [?] start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret2, eval_#t~nondet3, eval_~tmp_ndt_1~0, eval_#t~nondet4, eval_~tmp_ndt_2~0, eval_#t~nondet5, eval_~tmp_ndt_3~0, eval_#t~nondet6, eval_~tmp_ndt_4~0, eval_#t~nondet7, eval_~tmp_ndt_5~0, eval_#t~nondet8, eval_~tmp_ndt_6~0, eval_#t~nondet9, eval_~tmp_ndt_7~0, eval_#t~nondet10, eval_~tmp_ndt_8~0, eval_~tmp~0;havoc eval_~tmp~0; [L14] ~m_pc~0 := 0; [L15] ~t1_pc~0 := 0; [L16] ~t2_pc~0 := 0; [L17] ~t3_pc~0 := 0; [L18] ~t4_pc~0 := 0; [L19] ~t5_pc~0 := 0; [L20] ~t6_pc~0 := 0; [L21] ~t7_pc~0 := 0; [L22] ~m_st~0 := 0; [L23] ~t1_st~0 := 0; [L24] ~t2_st~0 := 0; [L25] ~t3_st~0 := 0; [L26] ~t4_st~0 := 0; [L27] ~t5_st~0 := 0; [L28] ~t6_st~0 := 0; [L29] ~t7_st~0 := 0; [L30] ~m_i~0 := 0; [L31] ~t1_i~0 := 0; [L32] ~t2_i~0 := 0; [L33] ~t3_i~0 := 0; [L34] ~t4_i~0 := 0; [L35] ~t5_i~0 := 0; [L36] ~t6_i~0 := 0; [L37] ~t7_i~0 := 0; [L38] ~M_E~0 := 2; [L39] ~T1_E~0 := 2; [L40] ~T2_E~0 := 2; [L41] ~T3_E~0 := 2; [L42] ~T4_E~0 := 2; [L43] ~T5_E~0 := 2; [L44] ~T6_E~0 := 2; [L45] ~T7_E~0 := 2; [L46] ~E_M~0 := 2; [L47] ~E_1~0 := 2; [L48] ~E_2~0 := 2; [L49] ~E_3~0 := 2; [L50] ~E_4~0 := 2; [L51] ~E_5~0 := 2; [L52] ~E_6~0 := 2; [L53] ~E_7~0 := 2; [L63] ~token~0 := 0; [L65] ~local~0 := 0; [?] havoc main_#res; [?] havoc main_~__retres1~9; [L1225] havoc main_~__retres1~9; [L1134] ~m_i~0 := 1; [L1135] ~t1_i~0 := 1; [L1136] ~t2_i~0 := 1; [L1137] ~t3_i~0 := 1; [L1138] ~t4_i~0 := 1; [L1139] ~t5_i~0 := 1; [L1140] ~t6_i~0 := 1; [L1141] ~t7_i~0 := 1; [L1230] havoc start_simulation_#t~ret20, start_simulation_#t~ret21, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1; [L1166] havoc start_simulation_~kernel_st~0; [L1167] havoc start_simulation_~tmp~3; [L1168] havoc start_simulation_~tmp___0~1; [L1172] start_simulation_~kernel_st~0 := 0; [L538-L542] assume 1 == ~m_i~0; [L539] ~m_st~0 := 0; [L543-L547] assume 1 == ~t1_i~0; [L544] ~t1_st~0 := 0; [L548-L552] assume 1 == ~t2_i~0; [L549] ~t2_st~0 := 0; [L553-L557] assume 1 == ~t3_i~0; [L554] ~t3_st~0 := 0; [L558-L562] assume 1 == ~t4_i~0; [L559] ~t4_st~0 := 0; [L563-L567] assume 1 == ~t5_i~0; [L564] ~t5_st~0 := 0; [L568-L572] assume 1 == ~t6_i~0; [L569] ~t6_st~0 := 0; [L573-L577] assume 1 == ~t7_i~0; [L574] ~t7_st~0 := 0; [L771-L775] assume !(0 == ~M_E~0); [L776-L780] assume !(0 == ~T1_E~0); [L781-L785] assume !(0 == ~T2_E~0); [L786-L790] assume !(0 == ~T3_E~0); [L791-L795] assume !(0 == ~T4_E~0); [L796-L800] assume !(0 == ~T5_E~0); [L801-L805] assume !(0 == ~T6_E~0); [L806-L810] assume !(0 == ~T7_E~0); [L811-L815] assume !(0 == ~E_M~0); [L816-L820] assume !(0 == ~E_1~0); [L821-L825] assume !(0 == ~E_2~0); [L826-L830] assume !(0 == ~E_3~0); [L831-L835] assume !(0 == ~E_4~0); [L836-L840] assume !(0 == ~E_5~0); [L841-L845] assume !(0 == ~E_6~0); [L846-L850] assume !(0 == ~E_7~0); [L1176] havoc activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0; [L944] havoc activate_threads_~tmp~1; [L945] havoc activate_threads_~tmp___0~0; [L946] havoc activate_threads_~tmp___1~0; [L947] havoc activate_threads_~tmp___2~0; [L948] havoc activate_threads_~tmp___3~0; [L949] havoc activate_threads_~tmp___4~0; [L950] havoc activate_threads_~tmp___5~0; [L951] havoc activate_threads_~tmp___6~0; [L955] havoc is_master_triggered_#res; [L955] havoc is_master_triggered_~__retres1~0; [L375] havoc is_master_triggered_~__retres1~0; [L378-L387] assume !(1 == ~m_pc~0); [L388] is_master_triggered_~__retres1~0 := 0; [L390] is_master_triggered_#res := is_master_triggered_~__retres1~0; [L955] activate_threads_#t~ret11 := is_master_triggered_#res; [L955] activate_threads_~tmp~1 := activate_threads_#t~ret11; [L955] havoc activate_threads_#t~ret11; [L957-L961] assume !(0 != activate_threads_~tmp~1); [L963] havoc is_transmit1_triggered_#res; [L963] havoc is_transmit1_triggered_~__retres1~1; [L394] havoc is_transmit1_triggered_~__retres1~1; [L397-L406] assume !(1 == ~t1_pc~0); [L407] is_transmit1_triggered_~__retres1~1 := 0; [L409] is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; [L963] activate_threads_#t~ret12 := is_transmit1_triggered_#res; [L963] activate_threads_~tmp___0~0 := activate_threads_#t~ret12; [L963] havoc activate_threads_#t~ret12; [L965-L969] assume !(0 != activate_threads_~tmp___0~0); [L971] havoc is_transmit2_triggered_#res; [L971] havoc is_transmit2_triggered_~__retres1~2; [L413] havoc is_transmit2_triggered_~__retres1~2; [L416-L425] assume !(1 == ~t2_pc~0); [L426] is_transmit2_triggered_~__retres1~2 := 0; [L428] is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; [L971] activate_threads_#t~ret13 := is_transmit2_triggered_#res; [L971] activate_threads_~tmp___1~0 := activate_threads_#t~ret13; [L971] havoc activate_threads_#t~ret13; [L973-L977] assume !(0 != activate_threads_~tmp___1~0); [L979] havoc is_transmit3_triggered_#res; [L979] havoc is_transmit3_triggered_~__retres1~3; [L432] havoc is_transmit3_triggered_~__retres1~3; [L435-L444] assume !(1 == ~t3_pc~0); [L445] is_transmit3_triggered_~__retres1~3 := 0; [L447] is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; [L979] activate_threads_#t~ret14 := is_transmit3_triggered_#res; [L979] activate_threads_~tmp___2~0 := activate_threads_#t~ret14; [L979] havoc activate_threads_#t~ret14; [L981-L985] assume !(0 != activate_threads_~tmp___2~0); [L987] havoc is_transmit4_triggered_#res; [L987] havoc is_transmit4_triggered_~__retres1~4; [L451] havoc is_transmit4_triggered_~__retres1~4; [L454-L463] assume !(1 == ~t4_pc~0); [L464] is_transmit4_triggered_~__retres1~4 := 0; [L466] is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; [L987] activate_threads_#t~ret15 := is_transmit4_triggered_#res; [L987] activate_threads_~tmp___3~0 := activate_threads_#t~ret15; [L987] havoc activate_threads_#t~ret15; [L989-L993] assume !(0 != activate_threads_~tmp___3~0); [L995] havoc is_transmit5_triggered_#res; [L995] havoc is_transmit5_triggered_~__retres1~5; [L470] havoc is_transmit5_triggered_~__retres1~5; [L473-L482] assume !(1 == ~t5_pc~0); [L483] is_transmit5_triggered_~__retres1~5 := 0; [L485] is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; [L995] activate_threads_#t~ret16 := is_transmit5_triggered_#res; [L995] activate_threads_~tmp___4~0 := activate_threads_#t~ret16; [L995] havoc activate_threads_#t~ret16; [L997-L1001] assume !(0 != activate_threads_~tmp___4~0); [L1003] havoc is_transmit6_triggered_#res; [L1003] havoc is_transmit6_triggered_~__retres1~6; [L489] havoc is_transmit6_triggered_~__retres1~6; [L492-L501] assume !(1 == ~t6_pc~0); [L502] is_transmit6_triggered_~__retres1~6 := 0; [L504] is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; [L1003] activate_threads_#t~ret17 := is_transmit6_triggered_#res; [L1003] activate_threads_~tmp___5~0 := activate_threads_#t~ret17; [L1003] havoc activate_threads_#t~ret17; [L1005-L1009] assume !(0 != activate_threads_~tmp___5~0); [L1011] havoc is_transmit7_triggered_#res; [L1011] havoc is_transmit7_triggered_~__retres1~7; [L508] havoc is_transmit7_triggered_~__retres1~7; [L511-L520] assume !(1 == ~t7_pc~0); [L521] is_transmit7_triggered_~__retres1~7 := 0; [L523] is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; [L1011] activate_threads_#t~ret18 := is_transmit7_triggered_#res; [L1011] activate_threads_~tmp___6~0 := activate_threads_#t~ret18; [L1011] havoc activate_threads_#t~ret18; [L1013-L1017] assume !(0 != activate_threads_~tmp___6~0); [L859-L863] assume !(1 == ~M_E~0); [L864-L868] assume !(1 == ~T1_E~0); [L869-L873] assume !(1 == ~T2_E~0); [L874-L878] assume !(1 == ~T3_E~0); [L879-L883] assume !(1 == ~T4_E~0); [L884-L888] assume !(1 == ~T5_E~0); [L889-L893] assume !(1 == ~T6_E~0); [L894-L898] assume !(1 == ~T7_E~0); [L899-L903] assume !(1 == ~E_M~0); [L904-L908] assume !(1 == ~E_1~0); [L909-L913] assume !(1 == ~E_2~0); [L914-L918] assume !(1 == ~E_3~0); [L919-L923] assume !(1 == ~E_4~0); [L924-L928] assume !(1 == ~E_5~0); [L929-L933] assume !(1 == ~E_6~0); [L934-L938] assume !(1 == ~E_7~0); [L1180-L1217] assume !false; [L1183] start_simulation_~kernel_st~0 := 1; [L1184] havoc eval_#t~ret2, eval_#t~nondet3, eval_~tmp_ndt_1~0, eval_#t~nondet4, eval_~tmp_ndt_2~0, eval_#t~nondet5, eval_~tmp_ndt_3~0, eval_#t~nondet6, eval_~tmp_ndt_4~0, eval_#t~nondet7, eval_~tmp_ndt_5~0, eval_#t~nondet8, eval_~tmp_ndt_6~0, eval_#t~nondet9, eval_~tmp_ndt_7~0, eval_#t~nondet10, eval_~tmp_ndt_8~0, eval_~tmp~0; [L634] havoc eval_~tmp~0; ----- ----- class de.uni_freiburg.informatik.ultimate.boogie.preprocessor.BoogiePreprocessorBacktranslator [L14] ~m_pc~0 := 0; [L15] ~t1_pc~0 := 0; [L16] ~t2_pc~0 := 0; [L17] ~t3_pc~0 := 0; [L18] ~t4_pc~0 := 0; [L19] ~t5_pc~0 := 0; [L20] ~t6_pc~0 := 0; [L21] ~t7_pc~0 := 0; [L22] ~m_st~0 := 0; [L23] ~t1_st~0 := 0; [L24] ~t2_st~0 := 0; [L25] ~t3_st~0 := 0; [L26] ~t4_st~0 := 0; [L27] ~t5_st~0 := 0; [L28] ~t6_st~0 := 0; [L29] ~t7_st~0 := 0; [L30] ~m_i~0 := 0; [L31] ~t1_i~0 := 0; [L32] ~t2_i~0 := 0; [L33] ~t3_i~0 := 0; [L34] ~t4_i~0 := 0; [L35] ~t5_i~0 := 0; [L36] ~t6_i~0 := 0; [L37] ~t7_i~0 := 0; [L38] ~M_E~0 := 2; [L39] ~T1_E~0 := 2; [L40] ~T2_E~0 := 2; [L41] ~T3_E~0 := 2; [L42] ~T4_E~0 := 2; [L43] ~T5_E~0 := 2; [L44] ~T6_E~0 := 2; [L45] ~T7_E~0 := 2; [L46] ~E_M~0 := 2; [L47] ~E_1~0 := 2; [L48] ~E_2~0 := 2; [L49] ~E_3~0 := 2; [L50] ~E_4~0 := 2; [L51] ~E_5~0 := 2; [L52] ~E_6~0 := 2; [L53] ~E_7~0 := 2; [L63] ~token~0 := 0; [L65] ~local~0 := 0; [?] havoc main_#res; [?] havoc main_~__retres1~9; [L1225] havoc main_~__retres1~9; [L1134] ~m_i~0 := 1; [L1135] ~t1_i~0 := 1; [L1136] ~t2_i~0 := 1; [L1137] ~t3_i~0 := 1; [L1138] ~t4_i~0 := 1; [L1139] ~t5_i~0 := 1; [L1140] ~t6_i~0 := 1; [L1141] ~t7_i~0 := 1; [L1230] havoc start_simulation_#t~ret20, start_simulation_#t~ret21, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1; [L1166] havoc start_simulation_~kernel_st~0; [L1167] havoc start_simulation_~tmp~3; [L1168] havoc start_simulation_~tmp___0~1; [L1172] start_simulation_~kernel_st~0 := 0; [L538-L542] assume 1 == ~m_i~0; [L539] ~m_st~0 := 0; [L543-L547] assume 1 == ~t1_i~0; [L544] ~t1_st~0 := 0; [L548-L552] assume 1 == ~t2_i~0; [L549] ~t2_st~0 := 0; [L553-L557] assume 1 == ~t3_i~0; [L554] ~t3_st~0 := 0; [L558-L562] assume 1 == ~t4_i~0; [L559] ~t4_st~0 := 0; [L563-L567] assume 1 == ~t5_i~0; [L564] ~t5_st~0 := 0; [L568-L572] assume 1 == ~t6_i~0; [L569] ~t6_st~0 := 0; [L573-L577] assume 1 == ~t7_i~0; [L574] ~t7_st~0 := 0; [L771-L775] assume !(0 == ~M_E~0); [L776-L780] assume !(0 == ~T1_E~0); [L781-L785] assume !(0 == ~T2_E~0); [L786-L790] assume !(0 == ~T3_E~0); [L791-L795] assume !(0 == ~T4_E~0); [L796-L800] assume !(0 == ~T5_E~0); [L801-L805] assume !(0 == ~T6_E~0); [L806-L810] assume !(0 == ~T7_E~0); [L811-L815] assume !(0 == ~E_M~0); [L816-L820] assume !(0 == ~E_1~0); [L821-L825] assume !(0 == ~E_2~0); [L826-L830] assume !(0 == ~E_3~0); [L831-L835] assume !(0 == ~E_4~0); [L836-L840] assume !(0 == ~E_5~0); [L841-L845] assume !(0 == ~E_6~0); [L846-L850] assume !(0 == ~E_7~0); [L1176] havoc activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0; [L944] havoc activate_threads_~tmp~1; [L945] havoc activate_threads_~tmp___0~0; [L946] havoc activate_threads_~tmp___1~0; [L947] havoc activate_threads_~tmp___2~0; [L948] havoc activate_threads_~tmp___3~0; [L949] havoc activate_threads_~tmp___4~0; [L950] havoc activate_threads_~tmp___5~0; [L951] havoc activate_threads_~tmp___6~0; [L955] havoc is_master_triggered_#res; [L955] havoc is_master_triggered_~__retres1~0; [L375] havoc is_master_triggered_~__retres1~0; [L378-L387] assume !(1 == ~m_pc~0); [L388] is_master_triggered_~__retres1~0 := 0; [L390] is_master_triggered_#res := is_master_triggered_~__retres1~0; [L955] activate_threads_#t~ret11 := is_master_triggered_#res; [L955] activate_threads_~tmp~1 := activate_threads_#t~ret11; [L955] havoc activate_threads_#t~ret11; [L957-L961] assume !(0 != activate_threads_~tmp~1); [L963] havoc is_transmit1_triggered_#res; [L963] havoc is_transmit1_triggered_~__retres1~1; [L394] havoc is_transmit1_triggered_~__retres1~1; [L397-L406] assume !(1 == ~t1_pc~0); [L407] is_transmit1_triggered_~__retres1~1 := 0; [L409] is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; [L963] activate_threads_#t~ret12 := is_transmit1_triggered_#res; [L963] activate_threads_~tmp___0~0 := activate_threads_#t~ret12; [L963] havoc activate_threads_#t~ret12; [L965-L969] assume !(0 != activate_threads_~tmp___0~0); [L971] havoc is_transmit2_triggered_#res; [L971] havoc is_transmit2_triggered_~__retres1~2; [L413] havoc is_transmit2_triggered_~__retres1~2; [L416-L425] assume !(1 == ~t2_pc~0); [L426] is_transmit2_triggered_~__retres1~2 := 0; [L428] is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; [L971] activate_threads_#t~ret13 := is_transmit2_triggered_#res; [L971] activate_threads_~tmp___1~0 := activate_threads_#t~ret13; [L971] havoc activate_threads_#t~ret13; [L973-L977] assume !(0 != activate_threads_~tmp___1~0); [L979] havoc is_transmit3_triggered_#res; [L979] havoc is_transmit3_triggered_~__retres1~3; [L432] havoc is_transmit3_triggered_~__retres1~3; [L435-L444] assume !(1 == ~t3_pc~0); [L445] is_transmit3_triggered_~__retres1~3 := 0; [L447] is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; [L979] activate_threads_#t~ret14 := is_transmit3_triggered_#res; [L979] activate_threads_~tmp___2~0 := activate_threads_#t~ret14; [L979] havoc activate_threads_#t~ret14; [L981-L985] assume !(0 != activate_threads_~tmp___2~0); [L987] havoc is_transmit4_triggered_#res; [L987] havoc is_transmit4_triggered_~__retres1~4; [L451] havoc is_transmit4_triggered_~__retres1~4; [L454-L463] assume !(1 == ~t4_pc~0); [L464] is_transmit4_triggered_~__retres1~4 := 0; [L466] is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; [L987] activate_threads_#t~ret15 := is_transmit4_triggered_#res; [L987] activate_threads_~tmp___3~0 := activate_threads_#t~ret15; [L987] havoc activate_threads_#t~ret15; [L989-L993] assume !(0 != activate_threads_~tmp___3~0); [L995] havoc is_transmit5_triggered_#res; [L995] havoc is_transmit5_triggered_~__retres1~5; [L470] havoc is_transmit5_triggered_~__retres1~5; [L473-L482] assume !(1 == ~t5_pc~0); [L483] is_transmit5_triggered_~__retres1~5 := 0; [L485] is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; [L995] activate_threads_#t~ret16 := is_transmit5_triggered_#res; [L995] activate_threads_~tmp___4~0 := activate_threads_#t~ret16; [L995] havoc activate_threads_#t~ret16; [L997-L1001] assume !(0 != activate_threads_~tmp___4~0); [L1003] havoc is_transmit6_triggered_#res; [L1003] havoc is_transmit6_triggered_~__retres1~6; [L489] havoc is_transmit6_triggered_~__retres1~6; [L492-L501] assume !(1 == ~t6_pc~0); [L502] is_transmit6_triggered_~__retres1~6 := 0; [L504] is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; [L1003] activate_threads_#t~ret17 := is_transmit6_triggered_#res; [L1003] activate_threads_~tmp___5~0 := activate_threads_#t~ret17; [L1003] havoc activate_threads_#t~ret17; [L1005-L1009] assume !(0 != activate_threads_~tmp___5~0); [L1011] havoc is_transmit7_triggered_#res; [L1011] havoc is_transmit7_triggered_~__retres1~7; [L508] havoc is_transmit7_triggered_~__retres1~7; [L511-L520] assume !(1 == ~t7_pc~0); [L521] is_transmit7_triggered_~__retres1~7 := 0; [L523] is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; [L1011] activate_threads_#t~ret18 := is_transmit7_triggered_#res; [L1011] activate_threads_~tmp___6~0 := activate_threads_#t~ret18; [L1011] havoc activate_threads_#t~ret18; [L1013-L1017] assume !(0 != activate_threads_~tmp___6~0); [L859-L863] assume !(1 == ~M_E~0); [L864-L868] assume !(1 == ~T1_E~0); [L869-L873] assume !(1 == ~T2_E~0); [L874-L878] assume !(1 == ~T3_E~0); [L879-L883] assume !(1 == ~T4_E~0); [L884-L888] assume !(1 == ~T5_E~0); [L889-L893] assume !(1 == ~T6_E~0); [L894-L898] assume !(1 == ~T7_E~0); [L899-L903] assume !(1 == ~E_M~0); [L904-L908] assume !(1 == ~E_1~0); [L909-L913] assume !(1 == ~E_2~0); [L914-L918] assume !(1 == ~E_3~0); [L919-L923] assume !(1 == ~E_4~0); [L924-L928] assume !(1 == ~E_5~0); [L929-L933] assume !(1 == ~E_6~0); [L934-L938] assume !(1 == ~E_7~0); [L1180-L1217] assume !false; [L1183] start_simulation_~kernel_st~0 := 1; [L1184] havoc eval_#t~ret2, eval_#t~nondet3, eval_~tmp_ndt_1~0, eval_#t~nondet4, eval_~tmp_ndt_2~0, eval_#t~nondet5, eval_~tmp_ndt_3~0, eval_#t~nondet6, eval_~tmp_ndt_4~0, eval_#t~nondet7, eval_~tmp_ndt_5~0, eval_#t~nondet8, eval_~tmp_ndt_6~0, eval_#t~nondet9, eval_~tmp_ndt_7~0, eval_#t~nondet10, eval_~tmp_ndt_8~0, eval_~tmp~0; [L634] havoc eval_~tmp~0; [L14] ~m_pc~0 := 0; [L15] ~t1_pc~0 := 0; [L16] ~t2_pc~0 := 0; [L17] ~t3_pc~0 := 0; [L18] ~t4_pc~0 := 0; [L19] ~t5_pc~0 := 0; [L20] ~t6_pc~0 := 0; [L21] ~t7_pc~0 := 0; [L22] ~m_st~0 := 0; [L23] ~t1_st~0 := 0; [L24] ~t2_st~0 := 0; [L25] ~t3_st~0 := 0; [L26] ~t4_st~0 := 0; [L27] ~t5_st~0 := 0; [L28] ~t6_st~0 := 0; [L29] ~t7_st~0 := 0; [L30] ~m_i~0 := 0; [L31] ~t1_i~0 := 0; [L32] ~t2_i~0 := 0; [L33] ~t3_i~0 := 0; [L34] ~t4_i~0 := 0; [L35] ~t5_i~0 := 0; [L36] ~t6_i~0 := 0; [L37] ~t7_i~0 := 0; [L38] ~M_E~0 := 2; [L39] ~T1_E~0 := 2; [L40] ~T2_E~0 := 2; [L41] ~T3_E~0 := 2; [L42] ~T4_E~0 := 2; [L43] ~T5_E~0 := 2; [L44] ~T6_E~0 := 2; [L45] ~T7_E~0 := 2; [L46] ~E_M~0 := 2; [L47] ~E_1~0 := 2; [L48] ~E_2~0 := 2; [L49] ~E_3~0 := 2; [L50] ~E_4~0 := 2; [L51] ~E_5~0 := 2; [L52] ~E_6~0 := 2; [L53] ~E_7~0 := 2; [L63] ~token~0 := 0; [L65] ~local~0 := 0; [?] havoc main_#res; [?] havoc main_~__retres1~9; [L1225] havoc main_~__retres1~9; [L1134] ~m_i~0 := 1; [L1135] ~t1_i~0 := 1; [L1136] ~t2_i~0 := 1; [L1137] ~t3_i~0 := 1; [L1138] ~t4_i~0 := 1; [L1139] ~t5_i~0 := 1; [L1140] ~t6_i~0 := 1; [L1141] ~t7_i~0 := 1; [L1230] havoc start_simulation_#t~ret20, start_simulation_#t~ret21, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1; [L1166] havoc start_simulation_~kernel_st~0; [L1167] havoc start_simulation_~tmp~3; [L1168] havoc start_simulation_~tmp___0~1; [L1172] start_simulation_~kernel_st~0 := 0; [L538] COND TRUE 1 == ~m_i~0 [L539] ~m_st~0 := 0; [L543] COND TRUE 1 == ~t1_i~0 [L544] ~t1_st~0 := 0; [L548] COND TRUE 1 == ~t2_i~0 [L549] ~t2_st~0 := 0; [L553] COND TRUE 1 == ~t3_i~0 [L554] ~t3_st~0 := 0; [L558] COND TRUE 1 == ~t4_i~0 [L559] ~t4_st~0 := 0; [L563] COND TRUE 1 == ~t5_i~0 [L564] ~t5_st~0 := 0; [L568] COND TRUE 1 == ~t6_i~0 [L569] ~t6_st~0 := 0; [L573] COND TRUE 1 == ~t7_i~0 [L574] ~t7_st~0 := 0; [L771] COND FALSE !(0 == ~M_E~0) [L776] COND FALSE !(0 == ~T1_E~0) [L781] COND FALSE !(0 == ~T2_E~0) [L786] COND FALSE !(0 == ~T3_E~0) [L791] COND FALSE !(0 == ~T4_E~0) [L796] COND FALSE !(0 == ~T5_E~0) [L801] COND FALSE !(0 == ~T6_E~0) [L806] COND FALSE !(0 == ~T7_E~0) [L811] COND FALSE !(0 == ~E_M~0) [L816] COND FALSE !(0 == ~E_1~0) [L821] COND FALSE !(0 == ~E_2~0) [L826] COND FALSE !(0 == ~E_3~0) [L831] COND FALSE !(0 == ~E_4~0) [L836] COND FALSE !(0 == ~E_5~0) [L841] COND FALSE !(0 == ~E_6~0) [L846] COND FALSE !(0 == ~E_7~0) [L1176] havoc activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0; [L944] havoc activate_threads_~tmp~1; [L945] havoc activate_threads_~tmp___0~0; [L946] havoc activate_threads_~tmp___1~0; [L947] havoc activate_threads_~tmp___2~0; [L948] havoc activate_threads_~tmp___3~0; [L949] havoc activate_threads_~tmp___4~0; [L950] havoc activate_threads_~tmp___5~0; [L951] havoc activate_threads_~tmp___6~0; [L955] havoc is_master_triggered_#res; [L955] havoc is_master_triggered_~__retres1~0; [L375] havoc is_master_triggered_~__retres1~0; [L378] COND FALSE !(1 == ~m_pc~0) [L388] is_master_triggered_~__retres1~0 := 0; [L390] is_master_triggered_#res := is_master_triggered_~__retres1~0; [L955] activate_threads_#t~ret11 := is_master_triggered_#res; [L955] activate_threads_~tmp~1 := activate_threads_#t~ret11; [L955] havoc activate_threads_#t~ret11; [L957-L961] COND FALSE !(0 != activate_threads_~tmp~1) [L963] havoc is_transmit1_triggered_#res; [L963] havoc is_transmit1_triggered_~__retres1~1; [L394] havoc is_transmit1_triggered_~__retres1~1; [L397] COND FALSE !(1 == ~t1_pc~0) [L407] is_transmit1_triggered_~__retres1~1 := 0; [L409] is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; [L963] activate_threads_#t~ret12 := is_transmit1_triggered_#res; [L963] activate_threads_~tmp___0~0 := activate_threads_#t~ret12; [L963] havoc activate_threads_#t~ret12; [L965-L969] COND FALSE !(0 != activate_threads_~tmp___0~0) [L971] havoc is_transmit2_triggered_#res; [L971] havoc is_transmit2_triggered_~__retres1~2; [L413] havoc is_transmit2_triggered_~__retres1~2; [L416] COND FALSE !(1 == ~t2_pc~0) [L426] is_transmit2_triggered_~__retres1~2 := 0; [L428] is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; [L971] activate_threads_#t~ret13 := is_transmit2_triggered_#res; [L971] activate_threads_~tmp___1~0 := activate_threads_#t~ret13; [L971] havoc activate_threads_#t~ret13; [L973-L977] COND FALSE !(0 != activate_threads_~tmp___1~0) [L979] havoc is_transmit3_triggered_#res; [L979] havoc is_transmit3_triggered_~__retres1~3; [L432] havoc is_transmit3_triggered_~__retres1~3; [L435] COND FALSE !(1 == ~t3_pc~0) [L445] is_transmit3_triggered_~__retres1~3 := 0; [L447] is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; [L979] activate_threads_#t~ret14 := is_transmit3_triggered_#res; [L979] activate_threads_~tmp___2~0 := activate_threads_#t~ret14; [L979] havoc activate_threads_#t~ret14; [L981-L985] COND FALSE !(0 != activate_threads_~tmp___2~0) [L987] havoc is_transmit4_triggered_#res; [L987] havoc is_transmit4_triggered_~__retres1~4; [L451] havoc is_transmit4_triggered_~__retres1~4; [L454] COND FALSE !(1 == ~t4_pc~0) [L464] is_transmit4_triggered_~__retres1~4 := 0; [L466] is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; [L987] activate_threads_#t~ret15 := is_transmit4_triggered_#res; [L987] activate_threads_~tmp___3~0 := activate_threads_#t~ret15; [L987] havoc activate_threads_#t~ret15; [L989-L993] COND FALSE !(0 != activate_threads_~tmp___3~0) [L995] havoc is_transmit5_triggered_#res; [L995] havoc is_transmit5_triggered_~__retres1~5; [L470] havoc is_transmit5_triggered_~__retres1~5; [L473] COND FALSE !(1 == ~t5_pc~0) [L483] is_transmit5_triggered_~__retres1~5 := 0; [L485] is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; [L995] activate_threads_#t~ret16 := is_transmit5_triggered_#res; [L995] activate_threads_~tmp___4~0 := activate_threads_#t~ret16; [L995] havoc activate_threads_#t~ret16; [L997-L1001] COND FALSE !(0 != activate_threads_~tmp___4~0) [L1003] havoc is_transmit6_triggered_#res; [L1003] havoc is_transmit6_triggered_~__retres1~6; [L489] havoc is_transmit6_triggered_~__retres1~6; [L492] COND FALSE !(1 == ~t6_pc~0) [L502] is_transmit6_triggered_~__retres1~6 := 0; [L504] is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; [L1003] activate_threads_#t~ret17 := is_transmit6_triggered_#res; [L1003] activate_threads_~tmp___5~0 := activate_threads_#t~ret17; [L1003] havoc activate_threads_#t~ret17; [L1005-L1009] COND FALSE !(0 != activate_threads_~tmp___5~0) [L1011] havoc is_transmit7_triggered_#res; [L1011] havoc is_transmit7_triggered_~__retres1~7; [L508] havoc is_transmit7_triggered_~__retres1~7; [L511] COND FALSE !(1 == ~t7_pc~0) [L521] is_transmit7_triggered_~__retres1~7 := 0; [L523] is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; [L1011] activate_threads_#t~ret18 := is_transmit7_triggered_#res; [L1011] activate_threads_~tmp___6~0 := activate_threads_#t~ret18; [L1011] havoc activate_threads_#t~ret18; [L1013-L1017] COND FALSE !(0 != activate_threads_~tmp___6~0) [L859] COND FALSE !(1 == ~M_E~0) [L864] COND FALSE !(1 == ~T1_E~0) [L869] COND FALSE !(1 == ~T2_E~0) [L874] COND FALSE !(1 == ~T3_E~0) [L879] COND FALSE !(1 == ~T4_E~0) [L884] COND FALSE !(1 == ~T5_E~0) [L889] COND FALSE !(1 == ~T6_E~0) [L894] COND FALSE !(1 == ~T7_E~0) [L899] COND FALSE !(1 == ~E_M~0) [L904] COND FALSE !(1 == ~E_1~0) [L909] COND FALSE !(1 == ~E_2~0) [L914] COND FALSE !(1 == ~E_3~0) [L919] COND FALSE !(1 == ~E_4~0) [L924] COND FALSE !(1 == ~E_5~0) [L929] COND FALSE !(1 == ~E_6~0) [L934] COND FALSE !(1 == ~E_7~0) [L1180-L1217] COND FALSE !(false) [L1183] start_simulation_~kernel_st~0 := 1; [L1184] havoc eval_#t~ret2, eval_#t~nondet3, eval_~tmp_ndt_1~0, eval_#t~nondet4, eval_~tmp_ndt_2~0, eval_#t~nondet5, eval_~tmp_ndt_3~0, eval_#t~nondet6, eval_~tmp_ndt_4~0, eval_#t~nondet7, eval_~tmp_ndt_5~0, eval_#t~nondet8, eval_~tmp_ndt_6~0, eval_#t~nondet9, eval_~tmp_ndt_7~0, eval_#t~nondet10, eval_~tmp_ndt_8~0, eval_~tmp~0; [L634] havoc eval_~tmp~0; ----- ----- class de.uni_freiburg.informatik.ultimate.boogie.procedureinliner.backtranslation.InlinerBacktranslator [L14] ~m_pc~0 := 0; [L15] ~t1_pc~0 := 0; [L16] ~t2_pc~0 := 0; [L17] ~t3_pc~0 := 0; [L18] ~t4_pc~0 := 0; [L19] ~t5_pc~0 := 0; [L20] ~t6_pc~0 := 0; [L21] ~t7_pc~0 := 0; [L22] ~m_st~0 := 0; [L23] ~t1_st~0 := 0; [L24] ~t2_st~0 := 0; [L25] ~t3_st~0 := 0; [L26] ~t4_st~0 := 0; [L27] ~t5_st~0 := 0; [L28] ~t6_st~0 := 0; [L29] ~t7_st~0 := 0; [L30] ~m_i~0 := 0; [L31] ~t1_i~0 := 0; [L32] ~t2_i~0 := 0; [L33] ~t3_i~0 := 0; [L34] ~t4_i~0 := 0; [L35] ~t5_i~0 := 0; [L36] ~t6_i~0 := 0; [L37] ~t7_i~0 := 0; [L38] ~M_E~0 := 2; [L39] ~T1_E~0 := 2; [L40] ~T2_E~0 := 2; [L41] ~T3_E~0 := 2; [L42] ~T4_E~0 := 2; [L43] ~T5_E~0 := 2; [L44] ~T6_E~0 := 2; [L45] ~T7_E~0 := 2; [L46] ~E_M~0 := 2; [L47] ~E_1~0 := 2; [L48] ~E_2~0 := 2; [L49] ~E_3~0 := 2; [L50] ~E_4~0 := 2; [L51] ~E_5~0 := 2; [L52] ~E_6~0 := 2; [L53] ~E_7~0 := 2; [L63] ~token~0 := 0; [L65] ~local~0 := 0; [?] havoc main_#res; [?] havoc main_~__retres1~9; [L1225] havoc main_~__retres1~9; [L1134] ~m_i~0 := 1; [L1135] ~t1_i~0 := 1; [L1136] ~t2_i~0 := 1; [L1137] ~t3_i~0 := 1; [L1138] ~t4_i~0 := 1; [L1139] ~t5_i~0 := 1; [L1140] ~t6_i~0 := 1; [L1141] ~t7_i~0 := 1; [L1230] havoc start_simulation_#t~ret20, start_simulation_#t~ret21, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1; [L1166] havoc start_simulation_~kernel_st~0; [L1167] havoc start_simulation_~tmp~3; [L1168] havoc start_simulation_~tmp___0~1; [L1172] start_simulation_~kernel_st~0 := 0; [L538] COND TRUE 1 == ~m_i~0 [L539] ~m_st~0 := 0; [L543] COND TRUE 1 == ~t1_i~0 [L544] ~t1_st~0 := 0; [L548] COND TRUE 1 == ~t2_i~0 [L549] ~t2_st~0 := 0; [L553] COND TRUE 1 == ~t3_i~0 [L554] ~t3_st~0 := 0; [L558] COND TRUE 1 == ~t4_i~0 [L559] ~t4_st~0 := 0; [L563] COND TRUE 1 == ~t5_i~0 [L564] ~t5_st~0 := 0; [L568] COND TRUE 1 == ~t6_i~0 [L569] ~t6_st~0 := 0; [L573] COND TRUE 1 == ~t7_i~0 [L574] ~t7_st~0 := 0; [L771] COND FALSE !(0 == ~M_E~0) [L776] COND FALSE !(0 == ~T1_E~0) [L781] COND FALSE !(0 == ~T2_E~0) [L786] COND FALSE !(0 == ~T3_E~0) [L791] COND FALSE !(0 == ~T4_E~0) [L796] COND FALSE !(0 == ~T5_E~0) [L801] COND FALSE !(0 == ~T6_E~0) [L806] COND FALSE !(0 == ~T7_E~0) [L811] COND FALSE !(0 == ~E_M~0) [L816] COND FALSE !(0 == ~E_1~0) [L821] COND FALSE !(0 == ~E_2~0) [L826] COND FALSE !(0 == ~E_3~0) [L831] COND FALSE !(0 == ~E_4~0) [L836] COND FALSE !(0 == ~E_5~0) [L841] COND FALSE !(0 == ~E_6~0) [L846] COND FALSE !(0 == ~E_7~0) [L1176] havoc activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0; [L944] havoc activate_threads_~tmp~1; [L945] havoc activate_threads_~tmp___0~0; [L946] havoc activate_threads_~tmp___1~0; [L947] havoc activate_threads_~tmp___2~0; [L948] havoc activate_threads_~tmp___3~0; [L949] havoc activate_threads_~tmp___4~0; [L950] havoc activate_threads_~tmp___5~0; [L951] havoc activate_threads_~tmp___6~0; [L955] havoc is_master_triggered_#res; [L955] havoc is_master_triggered_~__retres1~0; [L375] havoc is_master_triggered_~__retres1~0; [L378] COND FALSE !(1 == ~m_pc~0) [L388] is_master_triggered_~__retres1~0 := 0; [L390] is_master_triggered_#res := is_master_triggered_~__retres1~0; [L955] activate_threads_#t~ret11 := is_master_triggered_#res; [L955] activate_threads_~tmp~1 := activate_threads_#t~ret11; [L955] havoc activate_threads_#t~ret11; [L957-L961] COND FALSE !(0 != activate_threads_~tmp~1) [L963] havoc is_transmit1_triggered_#res; [L963] havoc is_transmit1_triggered_~__retres1~1; [L394] havoc is_transmit1_triggered_~__retres1~1; [L397] COND FALSE !(1 == ~t1_pc~0) [L407] is_transmit1_triggered_~__retres1~1 := 0; [L409] is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; [L963] activate_threads_#t~ret12 := is_transmit1_triggered_#res; [L963] activate_threads_~tmp___0~0 := activate_threads_#t~ret12; [L963] havoc activate_threads_#t~ret12; [L965-L969] COND FALSE !(0 != activate_threads_~tmp___0~0) [L971] havoc is_transmit2_triggered_#res; [L971] havoc is_transmit2_triggered_~__retres1~2; [L413] havoc is_transmit2_triggered_~__retres1~2; [L416] COND FALSE !(1 == ~t2_pc~0) [L426] is_transmit2_triggered_~__retres1~2 := 0; [L428] is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; [L971] activate_threads_#t~ret13 := is_transmit2_triggered_#res; [L971] activate_threads_~tmp___1~0 := activate_threads_#t~ret13; [L971] havoc activate_threads_#t~ret13; [L973-L977] COND FALSE !(0 != activate_threads_~tmp___1~0) [L979] havoc is_transmit3_triggered_#res; [L979] havoc is_transmit3_triggered_~__retres1~3; [L432] havoc is_transmit3_triggered_~__retres1~3; [L435] COND FALSE !(1 == ~t3_pc~0) [L445] is_transmit3_triggered_~__retres1~3 := 0; [L447] is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; [L979] activate_threads_#t~ret14 := is_transmit3_triggered_#res; [L979] activate_threads_~tmp___2~0 := activate_threads_#t~ret14; [L979] havoc activate_threads_#t~ret14; [L981-L985] COND FALSE !(0 != activate_threads_~tmp___2~0) [L987] havoc is_transmit4_triggered_#res; [L987] havoc is_transmit4_triggered_~__retres1~4; [L451] havoc is_transmit4_triggered_~__retres1~4; [L454] COND FALSE !(1 == ~t4_pc~0) [L464] is_transmit4_triggered_~__retres1~4 := 0; [L466] is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; [L987] activate_threads_#t~ret15 := is_transmit4_triggered_#res; [L987] activate_threads_~tmp___3~0 := activate_threads_#t~ret15; [L987] havoc activate_threads_#t~ret15; [L989-L993] COND FALSE !(0 != activate_threads_~tmp___3~0) [L995] havoc is_transmit5_triggered_#res; [L995] havoc is_transmit5_triggered_~__retres1~5; [L470] havoc is_transmit5_triggered_~__retres1~5; [L473] COND FALSE !(1 == ~t5_pc~0) [L483] is_transmit5_triggered_~__retres1~5 := 0; [L485] is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; [L995] activate_threads_#t~ret16 := is_transmit5_triggered_#res; [L995] activate_threads_~tmp___4~0 := activate_threads_#t~ret16; [L995] havoc activate_threads_#t~ret16; [L997-L1001] COND FALSE !(0 != activate_threads_~tmp___4~0) [L1003] havoc is_transmit6_triggered_#res; [L1003] havoc is_transmit6_triggered_~__retres1~6; [L489] havoc is_transmit6_triggered_~__retres1~6; [L492] COND FALSE !(1 == ~t6_pc~0) [L502] is_transmit6_triggered_~__retres1~6 := 0; [L504] is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; [L1003] activate_threads_#t~ret17 := is_transmit6_triggered_#res; [L1003] activate_threads_~tmp___5~0 := activate_threads_#t~ret17; [L1003] havoc activate_threads_#t~ret17; [L1005-L1009] COND FALSE !(0 != activate_threads_~tmp___5~0) [L1011] havoc is_transmit7_triggered_#res; [L1011] havoc is_transmit7_triggered_~__retres1~7; [L508] havoc is_transmit7_triggered_~__retres1~7; [L511] COND FALSE !(1 == ~t7_pc~0) [L521] is_transmit7_triggered_~__retres1~7 := 0; [L523] is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; [L1011] activate_threads_#t~ret18 := is_transmit7_triggered_#res; [L1011] activate_threads_~tmp___6~0 := activate_threads_#t~ret18; [L1011] havoc activate_threads_#t~ret18; [L1013-L1017] COND FALSE !(0 != activate_threads_~tmp___6~0) [L859] COND FALSE !(1 == ~M_E~0) [L864] COND FALSE !(1 == ~T1_E~0) [L869] COND FALSE !(1 == ~T2_E~0) [L874] COND FALSE !(1 == ~T3_E~0) [L879] COND FALSE !(1 == ~T4_E~0) [L884] COND FALSE !(1 == ~T5_E~0) [L889] COND FALSE !(1 == ~T6_E~0) [L894] COND FALSE !(1 == ~T7_E~0) [L899] COND FALSE !(1 == ~E_M~0) [L904] COND FALSE !(1 == ~E_1~0) [L909] COND FALSE !(1 == ~E_2~0) [L914] COND FALSE !(1 == ~E_3~0) [L919] COND FALSE !(1 == ~E_4~0) [L924] COND FALSE !(1 == ~E_5~0) [L929] COND FALSE !(1 == ~E_6~0) [L934] COND FALSE !(1 == ~E_7~0) [L1180-L1217] COND FALSE !(false) [L1183] start_simulation_~kernel_st~0 := 1; [L1184] havoc eval_#t~ret2, eval_#t~nondet3, eval_~tmp_ndt_1~0, eval_#t~nondet4, eval_~tmp_ndt_2~0, eval_#t~nondet5, eval_~tmp_ndt_3~0, eval_#t~nondet6, eval_~tmp_ndt_4~0, eval_#t~nondet7, eval_~tmp_ndt_5~0, eval_#t~nondet8, eval_~tmp_ndt_6~0, eval_#t~nondet9, eval_~tmp_ndt_7~0, eval_#t~nondet10, eval_~tmp_ndt_8~0, eval_~tmp~0; [L634] havoc eval_~tmp~0; [L14] ~m_pc~0 := 0; [L15] ~t1_pc~0 := 0; [L16] ~t2_pc~0 := 0; [L17] ~t3_pc~0 := 0; [L18] ~t4_pc~0 := 0; [L19] ~t5_pc~0 := 0; [L20] ~t6_pc~0 := 0; [L21] ~t7_pc~0 := 0; [L22] ~m_st~0 := 0; [L23] ~t1_st~0 := 0; [L24] ~t2_st~0 := 0; [L25] ~t3_st~0 := 0; [L26] ~t4_st~0 := 0; [L27] ~t5_st~0 := 0; [L28] ~t6_st~0 := 0; [L29] ~t7_st~0 := 0; [L30] ~m_i~0 := 0; [L31] ~t1_i~0 := 0; [L32] ~t2_i~0 := 0; [L33] ~t3_i~0 := 0; [L34] ~t4_i~0 := 0; [L35] ~t5_i~0 := 0; [L36] ~t6_i~0 := 0; [L37] ~t7_i~0 := 0; [L38] ~M_E~0 := 2; [L39] ~T1_E~0 := 2; [L40] ~T2_E~0 := 2; [L41] ~T3_E~0 := 2; [L42] ~T4_E~0 := 2; [L43] ~T5_E~0 := 2; [L44] ~T6_E~0 := 2; [L45] ~T7_E~0 := 2; [L46] ~E_M~0 := 2; [L47] ~E_1~0 := 2; [L48] ~E_2~0 := 2; [L49] ~E_3~0 := 2; [L50] ~E_4~0 := 2; [L51] ~E_5~0 := 2; [L52] ~E_6~0 := 2; [L53] ~E_7~0 := 2; [L63] ~token~0 := 0; [L65] ~local~0 := 0; [L1225] havoc ~__retres1~9; [L1134] ~m_i~0 := 1; [L1135] ~t1_i~0 := 1; [L1136] ~t2_i~0 := 1; [L1137] ~t3_i~0 := 1; [L1138] ~t4_i~0 := 1; [L1139] ~t5_i~0 := 1; [L1140] ~t6_i~0 := 1; [L1141] ~t7_i~0 := 1; [L1166] havoc ~kernel_st~0; [L1167] havoc ~tmp~3; [L1168] havoc ~tmp___0~1; [L1172] ~kernel_st~0 := 0; [L538] COND TRUE 1 == ~m_i~0 [L539] ~m_st~0 := 0; [L543] COND TRUE 1 == ~t1_i~0 [L544] ~t1_st~0 := 0; [L548] COND TRUE 1 == ~t2_i~0 [L549] ~t2_st~0 := 0; [L553] COND TRUE 1 == ~t3_i~0 [L554] ~t3_st~0 := 0; [L558] COND TRUE 1 == ~t4_i~0 [L559] ~t4_st~0 := 0; [L563] COND TRUE 1 == ~t5_i~0 [L564] ~t5_st~0 := 0; [L568] COND TRUE 1 == ~t6_i~0 [L569] ~t6_st~0 := 0; [L573] COND TRUE 1 == ~t7_i~0 [L574] ~t7_st~0 := 0; [L771] COND FALSE !(0 == ~M_E~0) [L776] COND FALSE !(0 == ~T1_E~0) [L781] COND FALSE !(0 == ~T2_E~0) [L786] COND FALSE !(0 == ~T3_E~0) [L791] COND FALSE !(0 == ~T4_E~0) [L796] COND FALSE !(0 == ~T5_E~0) [L801] COND FALSE !(0 == ~T6_E~0) [L806] COND FALSE !(0 == ~T7_E~0) [L811] COND FALSE !(0 == ~E_M~0) [L816] COND FALSE !(0 == ~E_1~0) [L821] COND FALSE !(0 == ~E_2~0) [L826] COND FALSE !(0 == ~E_3~0) [L831] COND FALSE !(0 == ~E_4~0) [L836] COND FALSE !(0 == ~E_5~0) [L841] COND FALSE !(0 == ~E_6~0) [L846] COND FALSE !(0 == ~E_7~0) [L944] havoc ~tmp~1; [L945] havoc ~tmp___0~0; [L946] havoc ~tmp___1~0; [L947] havoc ~tmp___2~0; [L948] havoc ~tmp___3~0; [L949] havoc ~tmp___4~0; [L950] havoc ~tmp___5~0; [L951] havoc ~tmp___6~0; [L375] havoc ~__retres1~0; [L378] COND FALSE !(1 == ~m_pc~0) [L388] ~__retres1~0 := 0; [L390] #res := ~__retres1~0; [L955] ~tmp~1 := #t~ret11; [L955] havoc #t~ret11; [L957-L961] COND FALSE !(0 != ~tmp~1) [L394] havoc ~__retres1~1; [L397] COND FALSE !(1 == ~t1_pc~0) [L407] ~__retres1~1 := 0; [L409] #res := ~__retres1~1; [L963] ~tmp___0~0 := #t~ret12; [L963] havoc #t~ret12; [L965-L969] COND FALSE !(0 != ~tmp___0~0) [L413] havoc ~__retres1~2; [L416] COND FALSE !(1 == ~t2_pc~0) [L426] ~__retres1~2 := 0; [L428] #res := ~__retres1~2; [L971] ~tmp___1~0 := #t~ret13; [L971] havoc #t~ret13; [L973-L977] COND FALSE !(0 != ~tmp___1~0) [L432] havoc ~__retres1~3; [L435] COND FALSE !(1 == ~t3_pc~0) [L445] ~__retres1~3 := 0; [L447] #res := ~__retres1~3; [L979] ~tmp___2~0 := #t~ret14; [L979] havoc #t~ret14; [L981-L985] COND FALSE !(0 != ~tmp___2~0) [L451] havoc ~__retres1~4; [L454] COND FALSE !(1 == ~t4_pc~0) [L464] ~__retres1~4 := 0; [L466] #res := ~__retres1~4; [L987] ~tmp___3~0 := #t~ret15; [L987] havoc #t~ret15; [L989-L993] COND FALSE !(0 != ~tmp___3~0) [L470] havoc ~__retres1~5; [L473] COND FALSE !(1 == ~t5_pc~0) [L483] ~__retres1~5 := 0; [L485] #res := ~__retres1~5; [L995] ~tmp___4~0 := #t~ret16; [L995] havoc #t~ret16; [L997-L1001] COND FALSE !(0 != ~tmp___4~0) [L489] havoc ~__retres1~6; [L492] COND FALSE !(1 == ~t6_pc~0) [L502] ~__retres1~6 := 0; [L504] #res := ~__retres1~6; [L1003] ~tmp___5~0 := #t~ret17; [L1003] havoc #t~ret17; [L1005-L1009] COND FALSE !(0 != ~tmp___5~0) [L508] havoc ~__retres1~7; [L511] COND FALSE !(1 == ~t7_pc~0) [L521] ~__retres1~7 := 0; [L523] #res := ~__retres1~7; [L1011] ~tmp___6~0 := #t~ret18; [L1011] havoc #t~ret18; [L1013-L1017] COND FALSE !(0 != ~tmp___6~0) [L859] COND FALSE !(1 == ~M_E~0) [L864] COND FALSE !(1 == ~T1_E~0) [L869] COND FALSE !(1 == ~T2_E~0) [L874] COND FALSE !(1 == ~T3_E~0) [L879] COND FALSE !(1 == ~T4_E~0) [L884] COND FALSE !(1 == ~T5_E~0) [L889] COND FALSE !(1 == ~T6_E~0) [L894] COND FALSE !(1 == ~T7_E~0) [L899] COND FALSE !(1 == ~E_M~0) [L904] COND FALSE !(1 == ~E_1~0) [L909] COND FALSE !(1 == ~E_2~0) [L914] COND FALSE !(1 == ~E_3~0) [L919] COND FALSE !(1 == ~E_4~0) [L924] COND FALSE !(1 == ~E_5~0) [L929] COND FALSE !(1 == ~E_6~0) [L934] COND FALSE !(1 == ~E_7~0) [L1180-L1217] COND FALSE !(false) [L1183] ~kernel_st~0 := 1; [L634] havoc ~tmp~0; ----- ----- class de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.CACSL2BoogieBacktranslator [L14] ~m_pc~0 := 0; [L15] ~t1_pc~0 := 0; [L16] ~t2_pc~0 := 0; [L17] ~t3_pc~0 := 0; [L18] ~t4_pc~0 := 0; [L19] ~t5_pc~0 := 0; [L20] ~t6_pc~0 := 0; [L21] ~t7_pc~0 := 0; [L22] ~m_st~0 := 0; [L23] ~t1_st~0 := 0; [L24] ~t2_st~0 := 0; [L25] ~t3_st~0 := 0; [L26] ~t4_st~0 := 0; [L27] ~t5_st~0 := 0; [L28] ~t6_st~0 := 0; [L29] ~t7_st~0 := 0; [L30] ~m_i~0 := 0; [L31] ~t1_i~0 := 0; [L32] ~t2_i~0 := 0; [L33] ~t3_i~0 := 0; [L34] ~t4_i~0 := 0; [L35] ~t5_i~0 := 0; [L36] ~t6_i~0 := 0; [L37] ~t7_i~0 := 0; [L38] ~M_E~0 := 2; [L39] ~T1_E~0 := 2; [L40] ~T2_E~0 := 2; [L41] ~T3_E~0 := 2; [L42] ~T4_E~0 := 2; [L43] ~T5_E~0 := 2; [L44] ~T6_E~0 := 2; [L45] ~T7_E~0 := 2; [L46] ~E_M~0 := 2; [L47] ~E_1~0 := 2; [L48] ~E_2~0 := 2; [L49] ~E_3~0 := 2; [L50] ~E_4~0 := 2; [L51] ~E_5~0 := 2; [L52] ~E_6~0 := 2; [L53] ~E_7~0 := 2; [L63] ~token~0 := 0; [L65] ~local~0 := 0; [L1225] havoc ~__retres1~9; [L1134] ~m_i~0 := 1; [L1135] ~t1_i~0 := 1; [L1136] ~t2_i~0 := 1; [L1137] ~t3_i~0 := 1; [L1138] ~t4_i~0 := 1; [L1139] ~t5_i~0 := 1; [L1140] ~t6_i~0 := 1; [L1141] ~t7_i~0 := 1; [L1166] havoc ~kernel_st~0; [L1167] havoc ~tmp~3; [L1168] havoc ~tmp___0~1; [L1172] ~kernel_st~0 := 0; [L538] COND TRUE 1 == ~m_i~0 [L539] ~m_st~0 := 0; [L543] COND TRUE 1 == ~t1_i~0 [L544] ~t1_st~0 := 0; [L548] COND TRUE 1 == ~t2_i~0 [L549] ~t2_st~0 := 0; [L553] COND TRUE 1 == ~t3_i~0 [L554] ~t3_st~0 := 0; [L558] COND TRUE 1 == ~t4_i~0 [L559] ~t4_st~0 := 0; [L563] COND TRUE 1 == ~t5_i~0 [L564] ~t5_st~0 := 0; [L568] COND TRUE 1 == ~t6_i~0 [L569] ~t6_st~0 := 0; [L573] COND TRUE 1 == ~t7_i~0 [L574] ~t7_st~0 := 0; [L771] COND FALSE !(0 == ~M_E~0) [L776] COND FALSE !(0 == ~T1_E~0) [L781] COND FALSE !(0 == ~T2_E~0) [L786] COND FALSE !(0 == ~T3_E~0) [L791] COND FALSE !(0 == ~T4_E~0) [L796] COND FALSE !(0 == ~T5_E~0) [L801] COND FALSE !(0 == ~T6_E~0) [L806] COND FALSE !(0 == ~T7_E~0) [L811] COND FALSE !(0 == ~E_M~0) [L816] COND FALSE !(0 == ~E_1~0) [L821] COND FALSE !(0 == ~E_2~0) [L826] COND FALSE !(0 == ~E_3~0) [L831] COND FALSE !(0 == ~E_4~0) [L836] COND FALSE !(0 == ~E_5~0) [L841] COND FALSE !(0 == ~E_6~0) [L846] COND FALSE !(0 == ~E_7~0) [L944] havoc ~tmp~1; [L945] havoc ~tmp___0~0; [L946] havoc ~tmp___1~0; [L947] havoc ~tmp___2~0; [L948] havoc ~tmp___3~0; [L949] havoc ~tmp___4~0; [L950] havoc ~tmp___5~0; [L951] havoc ~tmp___6~0; [L375] havoc ~__retres1~0; [L378] COND FALSE !(1 == ~m_pc~0) [L388] ~__retres1~0 := 0; [L390] #res := ~__retres1~0; [L955] ~tmp~1 := #t~ret11; [L955] havoc #t~ret11; [L957-L961] COND FALSE !(0 != ~tmp~1) [L394] havoc ~__retres1~1; [L397] COND FALSE !(1 == ~t1_pc~0) [L407] ~__retres1~1 := 0; [L409] #res := ~__retres1~1; [L963] ~tmp___0~0 := #t~ret12; [L963] havoc #t~ret12; [L965-L969] COND FALSE !(0 != ~tmp___0~0) [L413] havoc ~__retres1~2; [L416] COND FALSE !(1 == ~t2_pc~0) [L426] ~__retres1~2 := 0; [L428] #res := ~__retres1~2; [L971] ~tmp___1~0 := #t~ret13; [L971] havoc #t~ret13; [L973-L977] COND FALSE !(0 != ~tmp___1~0) [L432] havoc ~__retres1~3; [L435] COND FALSE !(1 == ~t3_pc~0) [L445] ~__retres1~3 := 0; [L447] #res := ~__retres1~3; [L979] ~tmp___2~0 := #t~ret14; [L979] havoc #t~ret14; [L981-L985] COND FALSE !(0 != ~tmp___2~0) [L451] havoc ~__retres1~4; [L454] COND FALSE !(1 == ~t4_pc~0) [L464] ~__retres1~4 := 0; [L466] #res := ~__retres1~4; [L987] ~tmp___3~0 := #t~ret15; [L987] havoc #t~ret15; [L989-L993] COND FALSE !(0 != ~tmp___3~0) [L470] havoc ~__retres1~5; [L473] COND FALSE !(1 == ~t5_pc~0) [L483] ~__retres1~5 := 0; [L485] #res := ~__retres1~5; [L995] ~tmp___4~0 := #t~ret16; [L995] havoc #t~ret16; [L997-L1001] COND FALSE !(0 != ~tmp___4~0) [L489] havoc ~__retres1~6; [L492] COND FALSE !(1 == ~t6_pc~0) [L502] ~__retres1~6 := 0; [L504] #res := ~__retres1~6; [L1003] ~tmp___5~0 := #t~ret17; [L1003] havoc #t~ret17; [L1005-L1009] COND FALSE !(0 != ~tmp___5~0) [L508] havoc ~__retres1~7; [L511] COND FALSE !(1 == ~t7_pc~0) [L521] ~__retres1~7 := 0; [L523] #res := ~__retres1~7; [L1011] ~tmp___6~0 := #t~ret18; [L1011] havoc #t~ret18; [L1013-L1017] COND FALSE !(0 != ~tmp___6~0) [L859] COND FALSE !(1 == ~M_E~0) [L864] COND FALSE !(1 == ~T1_E~0) [L869] COND FALSE !(1 == ~T2_E~0) [L874] COND FALSE !(1 == ~T3_E~0) [L879] COND FALSE !(1 == ~T4_E~0) [L884] COND FALSE !(1 == ~T5_E~0) [L889] COND FALSE !(1 == ~T6_E~0) [L894] COND FALSE !(1 == ~T7_E~0) [L899] COND FALSE !(1 == ~E_M~0) [L904] COND FALSE !(1 == ~E_1~0) [L909] COND FALSE !(1 == ~E_2~0) [L914] COND FALSE !(1 == ~E_3~0) [L919] COND FALSE !(1 == ~E_4~0) [L924] COND FALSE !(1 == ~E_5~0) [L929] COND FALSE !(1 == ~E_6~0) [L934] COND FALSE !(1 == ~E_7~0) [L1180-L1217] COND FALSE !(false) [L1183] ~kernel_st~0 := 1; [L634] havoc ~tmp~0; [L14] int m_pc = 0; [L15] int t1_pc = 0; [L16] int t2_pc = 0; [L17] int t3_pc = 0; [L18] int t4_pc = 0; [L19] int t5_pc = 0; [L20] int t6_pc = 0; [L21] int t7_pc = 0; [L22] int m_st ; [L23] int t1_st ; [L24] int t2_st ; [L25] int t3_st ; [L26] int t4_st ; [L27] int t5_st ; [L28] int t6_st ; [L29] int t7_st ; [L30] int m_i ; [L31] int t1_i ; [L32] int t2_i ; [L33] int t3_i ; [L34] int t4_i ; [L35] int t5_i ; [L36] int t6_i ; [L37] int t7_i ; [L38] int M_E = 2; [L39] int T1_E = 2; [L40] int T2_E = 2; [L41] int T3_E = 2; [L42] int T4_E = 2; [L43] int T5_E = 2; [L44] int T6_E = 2; [L45] int T7_E = 2; [L46] int E_M = 2; [L47] int E_1 = 2; [L48] int E_2 = 2; [L49] int E_3 = 2; [L50] int E_4 = 2; [L51] int E_5 = 2; [L52] int E_6 = 2; [L53] int E_7 = 2; [L63] int token ; [L65] int local ; [L1225] int __retres1 ; [L1134] m_i = 1 [L1135] t1_i = 1 [L1136] t2_i = 1 [L1137] t3_i = 1 [L1138] t4_i = 1 [L1139] t5_i = 1 [L1140] t6_i = 1 [L1141] t7_i = 1 [L1166] int kernel_st ; [L1167] int tmp ; [L1168] int tmp___0 ; [L1172] kernel_st = 0 [L538] COND TRUE m_i == 1 [L539] m_st = 0 [L543] COND TRUE t1_i == 1 [L544] t1_st = 0 [L548] COND TRUE t2_i == 1 [L549] t2_st = 0 [L553] COND TRUE t3_i == 1 [L554] t3_st = 0 [L558] COND TRUE t4_i == 1 [L559] t4_st = 0 [L563] COND TRUE t5_i == 1 [L564] t5_st = 0 [L568] COND TRUE t6_i == 1 [L569] t6_st = 0 [L573] COND TRUE t7_i == 1 [L574] t7_st = 0 [L771] COND FALSE !(M_E == 0) [L776] COND FALSE !(T1_E == 0) [L781] COND FALSE !(T2_E == 0) [L786] COND FALSE !(T3_E == 0) [L791] COND FALSE !(T4_E == 0) [L796] COND FALSE !(T5_E == 0) [L801] COND FALSE !(T6_E == 0) [L806] COND FALSE !(T7_E == 0) [L811] COND FALSE !(E_M == 0) [L816] COND FALSE !(E_1 == 0) [L821] COND FALSE !(E_2 == 0) [L826] COND FALSE !(E_3 == 0) [L831] COND FALSE !(E_4 == 0) [L836] COND FALSE !(E_5 == 0) [L841] COND FALSE !(E_6 == 0) [L846] COND FALSE !(E_7 == 0) [L944] int tmp ; [L945] int tmp___0 ; [L946] int tmp___1 ; [L947] int tmp___2 ; [L948] int tmp___3 ; [L949] int tmp___4 ; [L950] int tmp___5 ; [L951] int tmp___6 ; [L375] int __retres1 ; [L378] COND FALSE !(m_pc == 1) [L388] __retres1 = 0 [L390] return (__retres1); [L955] tmp = is_master_triggered() [L957] COND FALSE !(\read(tmp)) [L394] int __retres1 ; [L397] COND FALSE !(t1_pc == 1) [L407] __retres1 = 0 [L409] return (__retres1); [L963] tmp___0 = is_transmit1_triggered() [L965] COND FALSE !(\read(tmp___0)) [L413] int __retres1 ; [L416] COND FALSE !(t2_pc == 1) [L426] __retres1 = 0 [L428] return (__retres1); [L971] tmp___1 = is_transmit2_triggered() [L973] COND FALSE !(\read(tmp___1)) [L432] int __retres1 ; [L435] COND FALSE !(t3_pc == 1) [L445] __retres1 = 0 [L447] return (__retres1); [L979] tmp___2 = is_transmit3_triggered() [L981] COND FALSE !(\read(tmp___2)) [L451] int __retres1 ; [L454] COND FALSE !(t4_pc == 1) [L464] __retres1 = 0 [L466] return (__retres1); [L987] tmp___3 = is_transmit4_triggered() [L989] COND FALSE !(\read(tmp___3)) [L470] int __retres1 ; [L473] COND FALSE !(t5_pc == 1) [L483] __retres1 = 0 [L485] return (__retres1); [L995] tmp___4 = is_transmit5_triggered() [L997] COND FALSE !(\read(tmp___4)) [L489] int __retres1 ; [L492] COND FALSE !(t6_pc == 1) [L502] __retres1 = 0 [L504] return (__retres1); [L1003] tmp___5 = is_transmit6_triggered() [L1005] COND FALSE !(\read(tmp___5)) [L508] int __retres1 ; [L511] COND FALSE !(t7_pc == 1) [L521] __retres1 = 0 [L523] return (__retres1); [L1011] tmp___6 = is_transmit7_triggered() [L1013] COND FALSE !(\read(tmp___6)) [L859] COND FALSE !(M_E == 1) [L864] COND FALSE !(T1_E == 1) [L869] COND FALSE !(T2_E == 1) [L874] COND FALSE !(T3_E == 1) [L879] COND FALSE !(T4_E == 1) [L884] COND FALSE !(T5_E == 1) [L889] COND FALSE !(T6_E == 1) [L894] COND FALSE !(T7_E == 1) [L899] COND FALSE !(E_M == 1) [L904] COND FALSE !(E_1 == 1) [L909] COND FALSE !(E_2 == 1) [L914] COND FALSE !(E_3 == 1) [L919] COND FALSE !(E_4 == 1) [L924] COND FALSE !(E_5 == 1) [L929] COND FALSE !(E_6 == 1) [L934] COND FALSE !(E_7 == 1) [L1180] COND TRUE 1 [L1183] kernel_st = 1 [L634] int tmp ; ----- ----- class de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder.RCFGBacktranslator [?] assume !false; [?] havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~8;havoc exists_runnable_thread_~__retres1~8; [?] assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8 := 1; [?] exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; [?] eval_#t~ret2 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret2;havoc eval_#t~ret2; [?] assume 0 != eval_~tmp~0; [?] assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0;eval_~tmp_ndt_1~0 := eval_#t~nondet3;havoc eval_#t~nondet3; [?] assume !(0 != eval_~tmp_ndt_1~0); [?] assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0;eval_~tmp_ndt_2~0 := eval_#t~nondet4;havoc eval_#t~nondet4; [?] assume !(0 != eval_~tmp_ndt_2~0); [?] assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0;eval_~tmp_ndt_3~0 := eval_#t~nondet5;havoc eval_#t~nondet5; [?] assume !(0 != eval_~tmp_ndt_3~0); [?] assume 0 == ~t3_st~0;havoc eval_~tmp_ndt_4~0;eval_~tmp_ndt_4~0 := eval_#t~nondet6;havoc eval_#t~nondet6; [?] assume !(0 != eval_~tmp_ndt_4~0); [?] assume 0 == ~t4_st~0;havoc eval_~tmp_ndt_5~0;eval_~tmp_ndt_5~0 := eval_#t~nondet7;havoc eval_#t~nondet7; [?] assume !(0 != eval_~tmp_ndt_5~0); [?] assume 0 == ~t5_st~0;havoc eval_~tmp_ndt_6~0;eval_~tmp_ndt_6~0 := eval_#t~nondet8;havoc eval_#t~nondet8; [?] assume !(0 != eval_~tmp_ndt_6~0); [?] assume 0 == ~t6_st~0;havoc eval_~tmp_ndt_7~0;eval_~tmp_ndt_7~0 := eval_#t~nondet9;havoc eval_#t~nondet9; [?] assume !(0 != eval_~tmp_ndt_7~0); [?] assume 0 == ~t7_st~0;havoc eval_~tmp_ndt_8~0;eval_~tmp_ndt_8~0 := eval_#t~nondet10;havoc eval_#t~nondet10; [?] assume !(0 != eval_~tmp_ndt_8~0); [L638-L760] assume !false; [L641] havoc exists_runnable_thread_#res; [L641] havoc exists_runnable_thread_~__retres1~8; [L583] havoc exists_runnable_thread_~__retres1~8; [L586-L626] assume 0 == ~m_st~0; [L587] exists_runnable_thread_~__retres1~8 := 1; [L629] exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; [L641] eval_#t~ret2 := exists_runnable_thread_#res; [L641] eval_~tmp~0 := eval_#t~ret2; [L641] havoc eval_#t~ret2; [L643-L647] assume 0 != eval_~tmp~0; [L648-L661] assume 0 == ~m_st~0; [L649] havoc eval_~tmp_ndt_1~0; [L650] eval_~tmp_ndt_1~0 := eval_#t~nondet3; [L650] havoc eval_#t~nondet3; [L651-L658] assume !(0 != eval_~tmp_ndt_1~0); [L662-L675] assume 0 == ~t1_st~0; [L663] havoc eval_~tmp_ndt_2~0; [L664] eval_~tmp_ndt_2~0 := eval_#t~nondet4; [L664] havoc eval_#t~nondet4; [L665-L672] assume !(0 != eval_~tmp_ndt_2~0); [L676-L689] assume 0 == ~t2_st~0; [L677] havoc eval_~tmp_ndt_3~0; [L678] eval_~tmp_ndt_3~0 := eval_#t~nondet5; [L678] havoc eval_#t~nondet5; [L679-L686] assume !(0 != eval_~tmp_ndt_3~0); [L690-L703] assume 0 == ~t3_st~0; [L691] havoc eval_~tmp_ndt_4~0; [L692] eval_~tmp_ndt_4~0 := eval_#t~nondet6; [L692] havoc eval_#t~nondet6; [L693-L700] assume !(0 != eval_~tmp_ndt_4~0); [L704-L717] assume 0 == ~t4_st~0; [L705] havoc eval_~tmp_ndt_5~0; [L706] eval_~tmp_ndt_5~0 := eval_#t~nondet7; [L706] havoc eval_#t~nondet7; [L707-L714] assume !(0 != eval_~tmp_ndt_5~0); [L718-L731] assume 0 == ~t5_st~0; [L719] havoc eval_~tmp_ndt_6~0; [L720] eval_~tmp_ndt_6~0 := eval_#t~nondet8; [L720] havoc eval_#t~nondet8; [L721-L728] assume !(0 != eval_~tmp_ndt_6~0); [L732-L745] assume 0 == ~t6_st~0; [L733] havoc eval_~tmp_ndt_7~0; [L734] eval_~tmp_ndt_7~0 := eval_#t~nondet9; [L734] havoc eval_#t~nondet9; [L735-L742] assume !(0 != eval_~tmp_ndt_7~0); [L746-L759] assume 0 == ~t7_st~0; [L747] havoc eval_~tmp_ndt_8~0; [L748] eval_~tmp_ndt_8~0 := eval_#t~nondet10; [L748] havoc eval_#t~nondet10; [L749-L756] assume !(0 != eval_~tmp_ndt_8~0); ----- ----- class de.uni_freiburg.informatik.ultimate.boogie.preprocessor.BoogiePreprocessorBacktranslator [L638-L760] assume !false; [L641] havoc exists_runnable_thread_#res; [L641] havoc exists_runnable_thread_~__retres1~8; [L583] havoc exists_runnable_thread_~__retres1~8; [L586-L626] assume 0 == ~m_st~0; [L587] exists_runnable_thread_~__retres1~8 := 1; [L629] exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; [L641] eval_#t~ret2 := exists_runnable_thread_#res; [L641] eval_~tmp~0 := eval_#t~ret2; [L641] havoc eval_#t~ret2; [L643-L647] assume 0 != eval_~tmp~0; [L648-L661] assume 0 == ~m_st~0; [L649] havoc eval_~tmp_ndt_1~0; [L650] eval_~tmp_ndt_1~0 := eval_#t~nondet3; [L650] havoc eval_#t~nondet3; [L651-L658] assume !(0 != eval_~tmp_ndt_1~0); [L662-L675] assume 0 == ~t1_st~0; [L663] havoc eval_~tmp_ndt_2~0; [L664] eval_~tmp_ndt_2~0 := eval_#t~nondet4; [L664] havoc eval_#t~nondet4; [L665-L672] assume !(0 != eval_~tmp_ndt_2~0); [L676-L689] assume 0 == ~t2_st~0; [L677] havoc eval_~tmp_ndt_3~0; [L678] eval_~tmp_ndt_3~0 := eval_#t~nondet5; [L678] havoc eval_#t~nondet5; [L679-L686] assume !(0 != eval_~tmp_ndt_3~0); [L690-L703] assume 0 == ~t3_st~0; [L691] havoc eval_~tmp_ndt_4~0; [L692] eval_~tmp_ndt_4~0 := eval_#t~nondet6; [L692] havoc eval_#t~nondet6; [L693-L700] assume !(0 != eval_~tmp_ndt_4~0); [L704-L717] assume 0 == ~t4_st~0; [L705] havoc eval_~tmp_ndt_5~0; [L706] eval_~tmp_ndt_5~0 := eval_#t~nondet7; [L706] havoc eval_#t~nondet7; [L707-L714] assume !(0 != eval_~tmp_ndt_5~0); [L718-L731] assume 0 == ~t5_st~0; [L719] havoc eval_~tmp_ndt_6~0; [L720] eval_~tmp_ndt_6~0 := eval_#t~nondet8; [L720] havoc eval_#t~nondet8; [L721-L728] assume !(0 != eval_~tmp_ndt_6~0); [L732-L745] assume 0 == ~t6_st~0; [L733] havoc eval_~tmp_ndt_7~0; [L734] eval_~tmp_ndt_7~0 := eval_#t~nondet9; [L734] havoc eval_#t~nondet9; [L735-L742] assume !(0 != eval_~tmp_ndt_7~0); [L746-L759] assume 0 == ~t7_st~0; [L747] havoc eval_~tmp_ndt_8~0; [L748] eval_~tmp_ndt_8~0 := eval_#t~nondet10; [L748] havoc eval_#t~nondet10; [L749-L756] assume !(0 != eval_~tmp_ndt_8~0); [L638-L760] COND FALSE !(false) [L641] havoc exists_runnable_thread_#res; [L641] havoc exists_runnable_thread_~__retres1~8; [L583] havoc exists_runnable_thread_~__retres1~8; [L586] COND TRUE 0 == ~m_st~0 [L587] exists_runnable_thread_~__retres1~8 := 1; [L629] exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; [L641] eval_#t~ret2 := exists_runnable_thread_#res; [L641] eval_~tmp~0 := eval_#t~ret2; [L641] havoc eval_#t~ret2; [L643-L647] COND TRUE 0 != eval_~tmp~0 [L648] COND TRUE 0 == ~m_st~0 [L649] havoc eval_~tmp_ndt_1~0; [L650] eval_~tmp_ndt_1~0 := eval_#t~nondet3; [L650] havoc eval_#t~nondet3; [L651-L658] COND FALSE !(0 != eval_~tmp_ndt_1~0) [L662] COND TRUE 0 == ~t1_st~0 [L663] havoc eval_~tmp_ndt_2~0; [L664] eval_~tmp_ndt_2~0 := eval_#t~nondet4; [L664] havoc eval_#t~nondet4; [L665-L672] COND FALSE !(0 != eval_~tmp_ndt_2~0) [L676] COND TRUE 0 == ~t2_st~0 [L677] havoc eval_~tmp_ndt_3~0; [L678] eval_~tmp_ndt_3~0 := eval_#t~nondet5; [L678] havoc eval_#t~nondet5; [L679-L686] COND FALSE !(0 != eval_~tmp_ndt_3~0) [L690] COND TRUE 0 == ~t3_st~0 [L691] havoc eval_~tmp_ndt_4~0; [L692] eval_~tmp_ndt_4~0 := eval_#t~nondet6; [L692] havoc eval_#t~nondet6; [L693-L700] COND FALSE !(0 != eval_~tmp_ndt_4~0) [L704] COND TRUE 0 == ~t4_st~0 [L705] havoc eval_~tmp_ndt_5~0; [L706] eval_~tmp_ndt_5~0 := eval_#t~nondet7; [L706] havoc eval_#t~nondet7; [L707-L714] COND FALSE !(0 != eval_~tmp_ndt_5~0) [L718] COND TRUE 0 == ~t5_st~0 [L719] havoc eval_~tmp_ndt_6~0; [L720] eval_~tmp_ndt_6~0 := eval_#t~nondet8; [L720] havoc eval_#t~nondet8; [L721-L728] COND FALSE !(0 != eval_~tmp_ndt_6~0) [L732] COND TRUE 0 == ~t6_st~0 [L733] havoc eval_~tmp_ndt_7~0; [L734] eval_~tmp_ndt_7~0 := eval_#t~nondet9; [L734] havoc eval_#t~nondet9; [L735-L742] COND FALSE !(0 != eval_~tmp_ndt_7~0) [L746] COND TRUE 0 == ~t7_st~0 [L747] havoc eval_~tmp_ndt_8~0; [L748] eval_~tmp_ndt_8~0 := eval_#t~nondet10; [L748] havoc eval_#t~nondet10; [L749-L756] COND FALSE !(0 != eval_~tmp_ndt_8~0) ----- ----- class de.uni_freiburg.informatik.ultimate.boogie.procedureinliner.backtranslation.InlinerBacktranslator [L638-L760] COND FALSE !(false) [L641] havoc exists_runnable_thread_#res; [L641] havoc exists_runnable_thread_~__retres1~8; [L583] havoc exists_runnable_thread_~__retres1~8; [L586] COND TRUE 0 == ~m_st~0 [L587] exists_runnable_thread_~__retres1~8 := 1; [L629] exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; [L641] eval_#t~ret2 := exists_runnable_thread_#res; [L641] eval_~tmp~0 := eval_#t~ret2; [L641] havoc eval_#t~ret2; [L643-L647] COND TRUE 0 != eval_~tmp~0 [L648] COND TRUE 0 == ~m_st~0 [L649] havoc eval_~tmp_ndt_1~0; [L650] eval_~tmp_ndt_1~0 := eval_#t~nondet3; [L650] havoc eval_#t~nondet3; [L651-L658] COND FALSE !(0 != eval_~tmp_ndt_1~0) [L662] COND TRUE 0 == ~t1_st~0 [L663] havoc eval_~tmp_ndt_2~0; [L664] eval_~tmp_ndt_2~0 := eval_#t~nondet4; [L664] havoc eval_#t~nondet4; [L665-L672] COND FALSE !(0 != eval_~tmp_ndt_2~0) [L676] COND TRUE 0 == ~t2_st~0 [L677] havoc eval_~tmp_ndt_3~0; [L678] eval_~tmp_ndt_3~0 := eval_#t~nondet5; [L678] havoc eval_#t~nondet5; [L679-L686] COND FALSE !(0 != eval_~tmp_ndt_3~0) [L690] COND TRUE 0 == ~t3_st~0 [L691] havoc eval_~tmp_ndt_4~0; [L692] eval_~tmp_ndt_4~0 := eval_#t~nondet6; [L692] havoc eval_#t~nondet6; [L693-L700] COND FALSE !(0 != eval_~tmp_ndt_4~0) [L704] COND TRUE 0 == ~t4_st~0 [L705] havoc eval_~tmp_ndt_5~0; [L706] eval_~tmp_ndt_5~0 := eval_#t~nondet7; [L706] havoc eval_#t~nondet7; [L707-L714] COND FALSE !(0 != eval_~tmp_ndt_5~0) [L718] COND TRUE 0 == ~t5_st~0 [L719] havoc eval_~tmp_ndt_6~0; [L720] eval_~tmp_ndt_6~0 := eval_#t~nondet8; [L720] havoc eval_#t~nondet8; [L721-L728] COND FALSE !(0 != eval_~tmp_ndt_6~0) [L732] COND TRUE 0 == ~t6_st~0 [L733] havoc eval_~tmp_ndt_7~0; [L734] eval_~tmp_ndt_7~0 := eval_#t~nondet9; [L734] havoc eval_#t~nondet9; [L735-L742] COND FALSE !(0 != eval_~tmp_ndt_7~0) [L746] COND TRUE 0 == ~t7_st~0 [L747] havoc eval_~tmp_ndt_8~0; [L748] eval_~tmp_ndt_8~0 := eval_#t~nondet10; [L748] havoc eval_#t~nondet10; [L749-L756] COND FALSE !(0 != eval_~tmp_ndt_8~0) [L638-L760] COND FALSE !(false) [L583] havoc ~__retres1~8; [L586] COND TRUE 0 == ~m_st~0 [L587] ~__retres1~8 := 1; [L629] #res := ~__retres1~8; [L641] ~tmp~0 := #t~ret2; [L641] havoc #t~ret2; [L643-L647] COND TRUE 0 != ~tmp~0 [L648] COND TRUE 0 == ~m_st~0 [L649] havoc ~tmp_ndt_1~0; [L650] ~tmp_ndt_1~0 := #t~nondet3; [L650] havoc #t~nondet3; [L651-L658] COND FALSE !(0 != ~tmp_ndt_1~0) [L662] COND TRUE 0 == ~t1_st~0 [L663] havoc ~tmp_ndt_2~0; [L664] ~tmp_ndt_2~0 := #t~nondet4; [L664] havoc #t~nondet4; [L665-L672] COND FALSE !(0 != ~tmp_ndt_2~0) [L676] COND TRUE 0 == ~t2_st~0 [L677] havoc ~tmp_ndt_3~0; [L678] ~tmp_ndt_3~0 := #t~nondet5; [L678] havoc #t~nondet5; [L679-L686] COND FALSE !(0 != ~tmp_ndt_3~0) [L690] COND TRUE 0 == ~t3_st~0 [L691] havoc ~tmp_ndt_4~0; [L692] ~tmp_ndt_4~0 := #t~nondet6; [L692] havoc #t~nondet6; [L693-L700] COND FALSE !(0 != ~tmp_ndt_4~0) [L704] COND TRUE 0 == ~t4_st~0 [L705] havoc ~tmp_ndt_5~0; [L706] ~tmp_ndt_5~0 := #t~nondet7; [L706] havoc #t~nondet7; [L707-L714] COND FALSE !(0 != ~tmp_ndt_5~0) [L718] COND TRUE 0 == ~t5_st~0 [L719] havoc ~tmp_ndt_6~0; [L720] ~tmp_ndt_6~0 := #t~nondet8; [L720] havoc #t~nondet8; [L721-L728] COND FALSE !(0 != ~tmp_ndt_6~0) [L732] COND TRUE 0 == ~t6_st~0 [L733] havoc ~tmp_ndt_7~0; [L734] ~tmp_ndt_7~0 := #t~nondet9; [L734] havoc #t~nondet9; [L735-L742] COND FALSE !(0 != ~tmp_ndt_7~0) [L746] COND TRUE 0 == ~t7_st~0 [L747] havoc ~tmp_ndt_8~0; [L748] ~tmp_ndt_8~0 := #t~nondet10; [L748] havoc #t~nondet10; [L749-L756] COND FALSE !(0 != ~tmp_ndt_8~0) ----- ----- class de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.CACSL2BoogieBacktranslator [L638-L760] COND FALSE !(false) [L583] havoc ~__retres1~8; [L586] COND TRUE 0 == ~m_st~0 [L587] ~__retres1~8 := 1; [L629] #res := ~__retres1~8; [L641] ~tmp~0 := #t~ret2; [L641] havoc #t~ret2; [L643-L647] COND TRUE 0 != ~tmp~0 [L648] COND TRUE 0 == ~m_st~0 [L649] havoc ~tmp_ndt_1~0; [L650] ~tmp_ndt_1~0 := #t~nondet3; [L650] havoc #t~nondet3; [L651-L658] COND FALSE !(0 != ~tmp_ndt_1~0) [L662] COND TRUE 0 == ~t1_st~0 [L663] havoc ~tmp_ndt_2~0; [L664] ~tmp_ndt_2~0 := #t~nondet4; [L664] havoc #t~nondet4; [L665-L672] COND FALSE !(0 != ~tmp_ndt_2~0) [L676] COND TRUE 0 == ~t2_st~0 [L677] havoc ~tmp_ndt_3~0; [L678] ~tmp_ndt_3~0 := #t~nondet5; [L678] havoc #t~nondet5; [L679-L686] COND FALSE !(0 != ~tmp_ndt_3~0) [L690] COND TRUE 0 == ~t3_st~0 [L691] havoc ~tmp_ndt_4~0; [L692] ~tmp_ndt_4~0 := #t~nondet6; [L692] havoc #t~nondet6; [L693-L700] COND FALSE !(0 != ~tmp_ndt_4~0) [L704] COND TRUE 0 == ~t4_st~0 [L705] havoc ~tmp_ndt_5~0; [L706] ~tmp_ndt_5~0 := #t~nondet7; [L706] havoc #t~nondet7; [L707-L714] COND FALSE !(0 != ~tmp_ndt_5~0) [L718] COND TRUE 0 == ~t5_st~0 [L719] havoc ~tmp_ndt_6~0; [L720] ~tmp_ndt_6~0 := #t~nondet8; [L720] havoc #t~nondet8; [L721-L728] COND FALSE !(0 != ~tmp_ndt_6~0) [L732] COND TRUE 0 == ~t6_st~0 [L733] havoc ~tmp_ndt_7~0; [L734] ~tmp_ndt_7~0 := #t~nondet9; [L734] havoc #t~nondet9; [L735-L742] COND FALSE !(0 != ~tmp_ndt_7~0) [L746] COND TRUE 0 == ~t7_st~0 [L747] havoc ~tmp_ndt_8~0; [L748] ~tmp_ndt_8~0 := #t~nondet10; [L748] havoc #t~nondet10; [L749-L756] COND FALSE !(0 != ~tmp_ndt_8~0) [L638] COND TRUE 1 [L583] int __retres1 ; [L586] COND TRUE m_st == 0 [L587] __retres1 = 1 [L629] return (__retres1); [L641] tmp = exists_runnable_thread() [L643] COND TRUE \read(tmp) [L648] COND TRUE m_st == 0 [L649] int tmp_ndt_1; [L650] tmp_ndt_1 = __VERIFIER_nondet_int() [L651] COND FALSE !(\read(tmp_ndt_1)) [L662] COND TRUE t1_st == 0 [L663] int tmp_ndt_2; [L664] tmp_ndt_2 = __VERIFIER_nondet_int() [L665] COND FALSE !(\read(tmp_ndt_2)) [L676] COND TRUE t2_st == 0 [L677] int tmp_ndt_3; [L678] tmp_ndt_3 = __VERIFIER_nondet_int() [L679] COND FALSE !(\read(tmp_ndt_3)) [L690] COND TRUE t3_st == 0 [L691] int tmp_ndt_4; [L692] tmp_ndt_4 = __VERIFIER_nondet_int() [L693] COND FALSE !(\read(tmp_ndt_4)) [L704] COND TRUE t4_st == 0 [L705] int tmp_ndt_5; [L706] tmp_ndt_5 = __VERIFIER_nondet_int() [L707] COND FALSE !(\read(tmp_ndt_5)) [L718] COND TRUE t5_st == 0 [L719] int tmp_ndt_6; [L720] tmp_ndt_6 = __VERIFIER_nondet_int() [L721] COND FALSE !(\read(tmp_ndt_6)) [L732] COND TRUE t6_st == 0 [L733] int tmp_ndt_7; [L734] tmp_ndt_7 = __VERIFIER_nondet_int() [L735] COND FALSE !(\read(tmp_ndt_7)) [L746] COND TRUE t7_st == 0 [L747] int tmp_ndt_8; [L748] tmp_ndt_8 = __VERIFIER_nondet_int() [L749] COND FALSE !(\read(tmp_ndt_8)) ----- [2018-11-23 16:07:23,066 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer CFG 23.11 04:07:23 BoogieIcfgContainer [2018-11-23 16:07:23,066 INFO L132 PluginConnector]: ------------------------ END BuchiAutomizer---------------------------- [2018-11-23 16:07:23,067 INFO L113 PluginConnector]: ------------------------Witness Printer---------------------------- [2018-11-23 16:07:23,131 INFO L271 PluginConnector]: Initializing Witness Printer... [2018-11-23 16:07:23,131 INFO L276 PluginConnector]: Witness Printer initialized [2018-11-23 16:07:23,132 INFO L185 PluginConnector]: Executing the observer RCFGCatcher from plugin Witness Printer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 23.11 04:06:12" (3/4) ... [2018-11-23 16:07:23,134 INFO L141 WitnessPrinter]: Generating witness for non-termination counterexample ----- class de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder.RCFGBacktranslator [?] ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; [?] havoc main_#res;havoc main_~__retres1~9;havoc main_~__retres1~9;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; [?] havoc start_simulation_#t~ret20, start_simulation_#t~ret21, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; [?] assume 1 == ~m_i~0;~m_st~0 := 0; [?] assume 1 == ~t1_i~0;~t1_st~0 := 0; [?] assume 1 == ~t2_i~0;~t2_st~0 := 0; [?] assume 1 == ~t3_i~0;~t3_st~0 := 0; [?] assume 1 == ~t4_i~0;~t4_st~0 := 0; [?] assume 1 == ~t5_i~0;~t5_st~0 := 0; [?] assume 1 == ~t6_i~0;~t6_st~0 := 0; [?] assume 1 == ~t7_i~0;~t7_st~0 := 0; [?] assume !(0 == ~M_E~0); [?] assume !(0 == ~T1_E~0); [?] assume !(0 == ~T2_E~0); [?] assume !(0 == ~T3_E~0); [?] assume !(0 == ~T4_E~0); [?] assume !(0 == ~T5_E~0); [?] assume !(0 == ~T6_E~0); [?] assume !(0 == ~T7_E~0); [?] assume !(0 == ~E_M~0); [?] assume !(0 == ~E_1~0); [?] assume !(0 == ~E_2~0); [?] assume !(0 == ~E_3~0); [?] assume !(0 == ~E_4~0); [?] assume !(0 == ~E_5~0); [?] assume !(0 == ~E_6~0); [?] assume !(0 == ~E_7~0); [?] havoc activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; [?] assume !(1 == ~m_pc~0); [?] is_master_triggered_~__retres1~0 := 0; [?] is_master_triggered_#res := is_master_triggered_~__retres1~0; [?] activate_threads_#t~ret11 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; [?] assume !(0 != activate_threads_~tmp~1); [?] havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; [?] assume !(1 == ~t1_pc~0); [?] is_transmit1_triggered_~__retres1~1 := 0; [?] is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; [?] activate_threads_#t~ret12 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; [?] assume !(0 != activate_threads_~tmp___0~0); [?] havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; [?] assume !(1 == ~t2_pc~0); [?] is_transmit2_triggered_~__retres1~2 := 0; [?] is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; [?] activate_threads_#t~ret13 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; [?] assume !(0 != activate_threads_~tmp___1~0); [?] havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; [?] assume !(1 == ~t3_pc~0); [?] is_transmit3_triggered_~__retres1~3 := 0; [?] is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; [?] activate_threads_#t~ret14 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; [?] assume !(0 != activate_threads_~tmp___2~0); [?] havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; [?] assume !(1 == ~t4_pc~0); [?] is_transmit4_triggered_~__retres1~4 := 0; [?] is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; [?] activate_threads_#t~ret15 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; [?] assume !(0 != activate_threads_~tmp___3~0); [?] havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; [?] assume !(1 == ~t5_pc~0); [?] is_transmit5_triggered_~__retres1~5 := 0; [?] is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; [?] activate_threads_#t~ret16 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; [?] assume !(0 != activate_threads_~tmp___4~0); [?] havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; [?] assume !(1 == ~t6_pc~0); [?] is_transmit6_triggered_~__retres1~6 := 0; [?] is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; [?] activate_threads_#t~ret17 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; [?] assume !(0 != activate_threads_~tmp___5~0); [?] havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; [?] assume !(1 == ~t7_pc~0); [?] is_transmit7_triggered_~__retres1~7 := 0; [?] is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; [?] activate_threads_#t~ret18 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; [?] assume !(0 != activate_threads_~tmp___6~0); [?] assume !(1 == ~M_E~0); [?] assume !(1 == ~T1_E~0); [?] assume !(1 == ~T2_E~0); [?] assume !(1 == ~T3_E~0); [?] assume !(1 == ~T4_E~0); [?] assume !(1 == ~T5_E~0); [?] assume !(1 == ~T6_E~0); [?] assume !(1 == ~T7_E~0); [?] assume !(1 == ~E_M~0); [?] assume !(1 == ~E_1~0); [?] assume !(1 == ~E_2~0); [?] assume !(1 == ~E_3~0); [?] assume !(1 == ~E_4~0); [?] assume !(1 == ~E_5~0); [?] assume !(1 == ~E_6~0); [?] assume !(1 == ~E_7~0); [?] assume !false; [?] start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret2, eval_#t~nondet3, eval_~tmp_ndt_1~0, eval_#t~nondet4, eval_~tmp_ndt_2~0, eval_#t~nondet5, eval_~tmp_ndt_3~0, eval_#t~nondet6, eval_~tmp_ndt_4~0, eval_#t~nondet7, eval_~tmp_ndt_5~0, eval_#t~nondet8, eval_~tmp_ndt_6~0, eval_#t~nondet9, eval_~tmp_ndt_7~0, eval_#t~nondet10, eval_~tmp_ndt_8~0, eval_~tmp~0;havoc eval_~tmp~0; [L14] ~m_pc~0 := 0; [L15] ~t1_pc~0 := 0; [L16] ~t2_pc~0 := 0; [L17] ~t3_pc~0 := 0; [L18] ~t4_pc~0 := 0; [L19] ~t5_pc~0 := 0; [L20] ~t6_pc~0 := 0; [L21] ~t7_pc~0 := 0; [L22] ~m_st~0 := 0; [L23] ~t1_st~0 := 0; [L24] ~t2_st~0 := 0; [L25] ~t3_st~0 := 0; [L26] ~t4_st~0 := 0; [L27] ~t5_st~0 := 0; [L28] ~t6_st~0 := 0; [L29] ~t7_st~0 := 0; [L30] ~m_i~0 := 0; [L31] ~t1_i~0 := 0; [L32] ~t2_i~0 := 0; [L33] ~t3_i~0 := 0; [L34] ~t4_i~0 := 0; [L35] ~t5_i~0 := 0; [L36] ~t6_i~0 := 0; [L37] ~t7_i~0 := 0; [L38] ~M_E~0 := 2; [L39] ~T1_E~0 := 2; [L40] ~T2_E~0 := 2; [L41] ~T3_E~0 := 2; [L42] ~T4_E~0 := 2; [L43] ~T5_E~0 := 2; [L44] ~T6_E~0 := 2; [L45] ~T7_E~0 := 2; [L46] ~E_M~0 := 2; [L47] ~E_1~0 := 2; [L48] ~E_2~0 := 2; [L49] ~E_3~0 := 2; [L50] ~E_4~0 := 2; [L51] ~E_5~0 := 2; [L52] ~E_6~0 := 2; [L53] ~E_7~0 := 2; [L63] ~token~0 := 0; [L65] ~local~0 := 0; [?] havoc main_#res; [?] havoc main_~__retres1~9; [L1225] havoc main_~__retres1~9; [L1134] ~m_i~0 := 1; [L1135] ~t1_i~0 := 1; [L1136] ~t2_i~0 := 1; [L1137] ~t3_i~0 := 1; [L1138] ~t4_i~0 := 1; [L1139] ~t5_i~0 := 1; [L1140] ~t6_i~0 := 1; [L1141] ~t7_i~0 := 1; [L1230] havoc start_simulation_#t~ret20, start_simulation_#t~ret21, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1; [L1166] havoc start_simulation_~kernel_st~0; [L1167] havoc start_simulation_~tmp~3; [L1168] havoc start_simulation_~tmp___0~1; [L1172] start_simulation_~kernel_st~0 := 0; [L538-L542] assume 1 == ~m_i~0; [L539] ~m_st~0 := 0; [L543-L547] assume 1 == ~t1_i~0; [L544] ~t1_st~0 := 0; [L548-L552] assume 1 == ~t2_i~0; [L549] ~t2_st~0 := 0; [L553-L557] assume 1 == ~t3_i~0; [L554] ~t3_st~0 := 0; [L558-L562] assume 1 == ~t4_i~0; [L559] ~t4_st~0 := 0; [L563-L567] assume 1 == ~t5_i~0; [L564] ~t5_st~0 := 0; [L568-L572] assume 1 == ~t6_i~0; [L569] ~t6_st~0 := 0; [L573-L577] assume 1 == ~t7_i~0; [L574] ~t7_st~0 := 0; [L771-L775] assume !(0 == ~M_E~0); [L776-L780] assume !(0 == ~T1_E~0); [L781-L785] assume !(0 == ~T2_E~0); [L786-L790] assume !(0 == ~T3_E~0); [L791-L795] assume !(0 == ~T4_E~0); [L796-L800] assume !(0 == ~T5_E~0); [L801-L805] assume !(0 == ~T6_E~0); [L806-L810] assume !(0 == ~T7_E~0); [L811-L815] assume !(0 == ~E_M~0); [L816-L820] assume !(0 == ~E_1~0); [L821-L825] assume !(0 == ~E_2~0); [L826-L830] assume !(0 == ~E_3~0); [L831-L835] assume !(0 == ~E_4~0); [L836-L840] assume !(0 == ~E_5~0); [L841-L845] assume !(0 == ~E_6~0); [L846-L850] assume !(0 == ~E_7~0); [L1176] havoc activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0; [L944] havoc activate_threads_~tmp~1; [L945] havoc activate_threads_~tmp___0~0; [L946] havoc activate_threads_~tmp___1~0; [L947] havoc activate_threads_~tmp___2~0; [L948] havoc activate_threads_~tmp___3~0; [L949] havoc activate_threads_~tmp___4~0; [L950] havoc activate_threads_~tmp___5~0; [L951] havoc activate_threads_~tmp___6~0; [L955] havoc is_master_triggered_#res; [L955] havoc is_master_triggered_~__retres1~0; [L375] havoc is_master_triggered_~__retres1~0; [L378-L387] assume !(1 == ~m_pc~0); [L388] is_master_triggered_~__retres1~0 := 0; [L390] is_master_triggered_#res := is_master_triggered_~__retres1~0; [L955] activate_threads_#t~ret11 := is_master_triggered_#res; [L955] activate_threads_~tmp~1 := activate_threads_#t~ret11; [L955] havoc activate_threads_#t~ret11; [L957-L961] assume !(0 != activate_threads_~tmp~1); [L963] havoc is_transmit1_triggered_#res; [L963] havoc is_transmit1_triggered_~__retres1~1; [L394] havoc is_transmit1_triggered_~__retres1~1; [L397-L406] assume !(1 == ~t1_pc~0); [L407] is_transmit1_triggered_~__retres1~1 := 0; [L409] is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; [L963] activate_threads_#t~ret12 := is_transmit1_triggered_#res; [L963] activate_threads_~tmp___0~0 := activate_threads_#t~ret12; [L963] havoc activate_threads_#t~ret12; [L965-L969] assume !(0 != activate_threads_~tmp___0~0); [L971] havoc is_transmit2_triggered_#res; [L971] havoc is_transmit2_triggered_~__retres1~2; [L413] havoc is_transmit2_triggered_~__retres1~2; [L416-L425] assume !(1 == ~t2_pc~0); [L426] is_transmit2_triggered_~__retres1~2 := 0; [L428] is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; [L971] activate_threads_#t~ret13 := is_transmit2_triggered_#res; [L971] activate_threads_~tmp___1~0 := activate_threads_#t~ret13; [L971] havoc activate_threads_#t~ret13; [L973-L977] assume !(0 != activate_threads_~tmp___1~0); [L979] havoc is_transmit3_triggered_#res; [L979] havoc is_transmit3_triggered_~__retres1~3; [L432] havoc is_transmit3_triggered_~__retres1~3; [L435-L444] assume !(1 == ~t3_pc~0); [L445] is_transmit3_triggered_~__retres1~3 := 0; [L447] is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; [L979] activate_threads_#t~ret14 := is_transmit3_triggered_#res; [L979] activate_threads_~tmp___2~0 := activate_threads_#t~ret14; [L979] havoc activate_threads_#t~ret14; [L981-L985] assume !(0 != activate_threads_~tmp___2~0); [L987] havoc is_transmit4_triggered_#res; [L987] havoc is_transmit4_triggered_~__retres1~4; [L451] havoc is_transmit4_triggered_~__retres1~4; [L454-L463] assume !(1 == ~t4_pc~0); [L464] is_transmit4_triggered_~__retres1~4 := 0; [L466] is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; [L987] activate_threads_#t~ret15 := is_transmit4_triggered_#res; [L987] activate_threads_~tmp___3~0 := activate_threads_#t~ret15; [L987] havoc activate_threads_#t~ret15; [L989-L993] assume !(0 != activate_threads_~tmp___3~0); [L995] havoc is_transmit5_triggered_#res; [L995] havoc is_transmit5_triggered_~__retres1~5; [L470] havoc is_transmit5_triggered_~__retres1~5; [L473-L482] assume !(1 == ~t5_pc~0); [L483] is_transmit5_triggered_~__retres1~5 := 0; [L485] is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; [L995] activate_threads_#t~ret16 := is_transmit5_triggered_#res; [L995] activate_threads_~tmp___4~0 := activate_threads_#t~ret16; [L995] havoc activate_threads_#t~ret16; [L997-L1001] assume !(0 != activate_threads_~tmp___4~0); [L1003] havoc is_transmit6_triggered_#res; [L1003] havoc is_transmit6_triggered_~__retres1~6; [L489] havoc is_transmit6_triggered_~__retres1~6; [L492-L501] assume !(1 == ~t6_pc~0); [L502] is_transmit6_triggered_~__retres1~6 := 0; [L504] is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; [L1003] activate_threads_#t~ret17 := is_transmit6_triggered_#res; [L1003] activate_threads_~tmp___5~0 := activate_threads_#t~ret17; [L1003] havoc activate_threads_#t~ret17; [L1005-L1009] assume !(0 != activate_threads_~tmp___5~0); [L1011] havoc is_transmit7_triggered_#res; [L1011] havoc is_transmit7_triggered_~__retres1~7; [L508] havoc is_transmit7_triggered_~__retres1~7; [L511-L520] assume !(1 == ~t7_pc~0); [L521] is_transmit7_triggered_~__retres1~7 := 0; [L523] is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; [L1011] activate_threads_#t~ret18 := is_transmit7_triggered_#res; [L1011] activate_threads_~tmp___6~0 := activate_threads_#t~ret18; [L1011] havoc activate_threads_#t~ret18; [L1013-L1017] assume !(0 != activate_threads_~tmp___6~0); [L859-L863] assume !(1 == ~M_E~0); [L864-L868] assume !(1 == ~T1_E~0); [L869-L873] assume !(1 == ~T2_E~0); [L874-L878] assume !(1 == ~T3_E~0); [L879-L883] assume !(1 == ~T4_E~0); [L884-L888] assume !(1 == ~T5_E~0); [L889-L893] assume !(1 == ~T6_E~0); [L894-L898] assume !(1 == ~T7_E~0); [L899-L903] assume !(1 == ~E_M~0); [L904-L908] assume !(1 == ~E_1~0); [L909-L913] assume !(1 == ~E_2~0); [L914-L918] assume !(1 == ~E_3~0); [L919-L923] assume !(1 == ~E_4~0); [L924-L928] assume !(1 == ~E_5~0); [L929-L933] assume !(1 == ~E_6~0); [L934-L938] assume !(1 == ~E_7~0); [L1180-L1217] assume !false; [L1183] start_simulation_~kernel_st~0 := 1; [L1184] havoc eval_#t~ret2, eval_#t~nondet3, eval_~tmp_ndt_1~0, eval_#t~nondet4, eval_~tmp_ndt_2~0, eval_#t~nondet5, eval_~tmp_ndt_3~0, eval_#t~nondet6, eval_~tmp_ndt_4~0, eval_#t~nondet7, eval_~tmp_ndt_5~0, eval_#t~nondet8, eval_~tmp_ndt_6~0, eval_#t~nondet9, eval_~tmp_ndt_7~0, eval_#t~nondet10, eval_~tmp_ndt_8~0, eval_~tmp~0; [L634] havoc eval_~tmp~0; ----- ----- class de.uni_freiburg.informatik.ultimate.boogie.preprocessor.BoogiePreprocessorBacktranslator [L14] ~m_pc~0 := 0; [L15] ~t1_pc~0 := 0; [L16] ~t2_pc~0 := 0; [L17] ~t3_pc~0 := 0; [L18] ~t4_pc~0 := 0; [L19] ~t5_pc~0 := 0; [L20] ~t6_pc~0 := 0; [L21] ~t7_pc~0 := 0; [L22] ~m_st~0 := 0; [L23] ~t1_st~0 := 0; [L24] ~t2_st~0 := 0; [L25] ~t3_st~0 := 0; [L26] ~t4_st~0 := 0; [L27] ~t5_st~0 := 0; [L28] ~t6_st~0 := 0; [L29] ~t7_st~0 := 0; [L30] ~m_i~0 := 0; [L31] ~t1_i~0 := 0; [L32] ~t2_i~0 := 0; [L33] ~t3_i~0 := 0; [L34] ~t4_i~0 := 0; [L35] ~t5_i~0 := 0; [L36] ~t6_i~0 := 0; [L37] ~t7_i~0 := 0; [L38] ~M_E~0 := 2; [L39] ~T1_E~0 := 2; [L40] ~T2_E~0 := 2; [L41] ~T3_E~0 := 2; [L42] ~T4_E~0 := 2; [L43] ~T5_E~0 := 2; [L44] ~T6_E~0 := 2; [L45] ~T7_E~0 := 2; [L46] ~E_M~0 := 2; [L47] ~E_1~0 := 2; [L48] ~E_2~0 := 2; [L49] ~E_3~0 := 2; [L50] ~E_4~0 := 2; [L51] ~E_5~0 := 2; [L52] ~E_6~0 := 2; [L53] ~E_7~0 := 2; [L63] ~token~0 := 0; [L65] ~local~0 := 0; [?] havoc main_#res; [?] havoc main_~__retres1~9; [L1225] havoc main_~__retres1~9; [L1134] ~m_i~0 := 1; [L1135] ~t1_i~0 := 1; [L1136] ~t2_i~0 := 1; [L1137] ~t3_i~0 := 1; [L1138] ~t4_i~0 := 1; [L1139] ~t5_i~0 := 1; [L1140] ~t6_i~0 := 1; [L1141] ~t7_i~0 := 1; [L1230] havoc start_simulation_#t~ret20, start_simulation_#t~ret21, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1; [L1166] havoc start_simulation_~kernel_st~0; [L1167] havoc start_simulation_~tmp~3; [L1168] havoc start_simulation_~tmp___0~1; [L1172] start_simulation_~kernel_st~0 := 0; [L538-L542] assume 1 == ~m_i~0; [L539] ~m_st~0 := 0; [L543-L547] assume 1 == ~t1_i~0; [L544] ~t1_st~0 := 0; [L548-L552] assume 1 == ~t2_i~0; [L549] ~t2_st~0 := 0; [L553-L557] assume 1 == ~t3_i~0; [L554] ~t3_st~0 := 0; [L558-L562] assume 1 == ~t4_i~0; [L559] ~t4_st~0 := 0; [L563-L567] assume 1 == ~t5_i~0; [L564] ~t5_st~0 := 0; [L568-L572] assume 1 == ~t6_i~0; [L569] ~t6_st~0 := 0; [L573-L577] assume 1 == ~t7_i~0; [L574] ~t7_st~0 := 0; [L771-L775] assume !(0 == ~M_E~0); [L776-L780] assume !(0 == ~T1_E~0); [L781-L785] assume !(0 == ~T2_E~0); [L786-L790] assume !(0 == ~T3_E~0); [L791-L795] assume !(0 == ~T4_E~0); [L796-L800] assume !(0 == ~T5_E~0); [L801-L805] assume !(0 == ~T6_E~0); [L806-L810] assume !(0 == ~T7_E~0); [L811-L815] assume !(0 == ~E_M~0); [L816-L820] assume !(0 == ~E_1~0); [L821-L825] assume !(0 == ~E_2~0); [L826-L830] assume !(0 == ~E_3~0); [L831-L835] assume !(0 == ~E_4~0); [L836-L840] assume !(0 == ~E_5~0); [L841-L845] assume !(0 == ~E_6~0); [L846-L850] assume !(0 == ~E_7~0); [L1176] havoc activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0; [L944] havoc activate_threads_~tmp~1; [L945] havoc activate_threads_~tmp___0~0; [L946] havoc activate_threads_~tmp___1~0; [L947] havoc activate_threads_~tmp___2~0; [L948] havoc activate_threads_~tmp___3~0; [L949] havoc activate_threads_~tmp___4~0; [L950] havoc activate_threads_~tmp___5~0; [L951] havoc activate_threads_~tmp___6~0; [L955] havoc is_master_triggered_#res; [L955] havoc is_master_triggered_~__retres1~0; [L375] havoc is_master_triggered_~__retres1~0; [L378-L387] assume !(1 == ~m_pc~0); [L388] is_master_triggered_~__retres1~0 := 0; [L390] is_master_triggered_#res := is_master_triggered_~__retres1~0; [L955] activate_threads_#t~ret11 := is_master_triggered_#res; [L955] activate_threads_~tmp~1 := activate_threads_#t~ret11; [L955] havoc activate_threads_#t~ret11; [L957-L961] assume !(0 != activate_threads_~tmp~1); [L963] havoc is_transmit1_triggered_#res; [L963] havoc is_transmit1_triggered_~__retres1~1; [L394] havoc is_transmit1_triggered_~__retres1~1; [L397-L406] assume !(1 == ~t1_pc~0); [L407] is_transmit1_triggered_~__retres1~1 := 0; [L409] is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; [L963] activate_threads_#t~ret12 := is_transmit1_triggered_#res; [L963] activate_threads_~tmp___0~0 := activate_threads_#t~ret12; [L963] havoc activate_threads_#t~ret12; [L965-L969] assume !(0 != activate_threads_~tmp___0~0); [L971] havoc is_transmit2_triggered_#res; [L971] havoc is_transmit2_triggered_~__retres1~2; [L413] havoc is_transmit2_triggered_~__retres1~2; [L416-L425] assume !(1 == ~t2_pc~0); [L426] is_transmit2_triggered_~__retres1~2 := 0; [L428] is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; [L971] activate_threads_#t~ret13 := is_transmit2_triggered_#res; [L971] activate_threads_~tmp___1~0 := activate_threads_#t~ret13; [L971] havoc activate_threads_#t~ret13; [L973-L977] assume !(0 != activate_threads_~tmp___1~0); [L979] havoc is_transmit3_triggered_#res; [L979] havoc is_transmit3_triggered_~__retres1~3; [L432] havoc is_transmit3_triggered_~__retres1~3; [L435-L444] assume !(1 == ~t3_pc~0); [L445] is_transmit3_triggered_~__retres1~3 := 0; [L447] is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; [L979] activate_threads_#t~ret14 := is_transmit3_triggered_#res; [L979] activate_threads_~tmp___2~0 := activate_threads_#t~ret14; [L979] havoc activate_threads_#t~ret14; [L981-L985] assume !(0 != activate_threads_~tmp___2~0); [L987] havoc is_transmit4_triggered_#res; [L987] havoc is_transmit4_triggered_~__retres1~4; [L451] havoc is_transmit4_triggered_~__retres1~4; [L454-L463] assume !(1 == ~t4_pc~0); [L464] is_transmit4_triggered_~__retres1~4 := 0; [L466] is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; [L987] activate_threads_#t~ret15 := is_transmit4_triggered_#res; [L987] activate_threads_~tmp___3~0 := activate_threads_#t~ret15; [L987] havoc activate_threads_#t~ret15; [L989-L993] assume !(0 != activate_threads_~tmp___3~0); [L995] havoc is_transmit5_triggered_#res; [L995] havoc is_transmit5_triggered_~__retres1~5; [L470] havoc is_transmit5_triggered_~__retres1~5; [L473-L482] assume !(1 == ~t5_pc~0); [L483] is_transmit5_triggered_~__retres1~5 := 0; [L485] is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; [L995] activate_threads_#t~ret16 := is_transmit5_triggered_#res; [L995] activate_threads_~tmp___4~0 := activate_threads_#t~ret16; [L995] havoc activate_threads_#t~ret16; [L997-L1001] assume !(0 != activate_threads_~tmp___4~0); [L1003] havoc is_transmit6_triggered_#res; [L1003] havoc is_transmit6_triggered_~__retres1~6; [L489] havoc is_transmit6_triggered_~__retres1~6; [L492-L501] assume !(1 == ~t6_pc~0); [L502] is_transmit6_triggered_~__retres1~6 := 0; [L504] is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; [L1003] activate_threads_#t~ret17 := is_transmit6_triggered_#res; [L1003] activate_threads_~tmp___5~0 := activate_threads_#t~ret17; [L1003] havoc activate_threads_#t~ret17; [L1005-L1009] assume !(0 != activate_threads_~tmp___5~0); [L1011] havoc is_transmit7_triggered_#res; [L1011] havoc is_transmit7_triggered_~__retres1~7; [L508] havoc is_transmit7_triggered_~__retres1~7; [L511-L520] assume !(1 == ~t7_pc~0); [L521] is_transmit7_triggered_~__retres1~7 := 0; [L523] is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; [L1011] activate_threads_#t~ret18 := is_transmit7_triggered_#res; [L1011] activate_threads_~tmp___6~0 := activate_threads_#t~ret18; [L1011] havoc activate_threads_#t~ret18; [L1013-L1017] assume !(0 != activate_threads_~tmp___6~0); [L859-L863] assume !(1 == ~M_E~0); [L864-L868] assume !(1 == ~T1_E~0); [L869-L873] assume !(1 == ~T2_E~0); [L874-L878] assume !(1 == ~T3_E~0); [L879-L883] assume !(1 == ~T4_E~0); [L884-L888] assume !(1 == ~T5_E~0); [L889-L893] assume !(1 == ~T6_E~0); [L894-L898] assume !(1 == ~T7_E~0); [L899-L903] assume !(1 == ~E_M~0); [L904-L908] assume !(1 == ~E_1~0); [L909-L913] assume !(1 == ~E_2~0); [L914-L918] assume !(1 == ~E_3~0); [L919-L923] assume !(1 == ~E_4~0); [L924-L928] assume !(1 == ~E_5~0); [L929-L933] assume !(1 == ~E_6~0); [L934-L938] assume !(1 == ~E_7~0); [L1180-L1217] assume !false; [L1183] start_simulation_~kernel_st~0 := 1; [L1184] havoc eval_#t~ret2, eval_#t~nondet3, eval_~tmp_ndt_1~0, eval_#t~nondet4, eval_~tmp_ndt_2~0, eval_#t~nondet5, eval_~tmp_ndt_3~0, eval_#t~nondet6, eval_~tmp_ndt_4~0, eval_#t~nondet7, eval_~tmp_ndt_5~0, eval_#t~nondet8, eval_~tmp_ndt_6~0, eval_#t~nondet9, eval_~tmp_ndt_7~0, eval_#t~nondet10, eval_~tmp_ndt_8~0, eval_~tmp~0; [L634] havoc eval_~tmp~0; [L14] ~m_pc~0 := 0; [L15] ~t1_pc~0 := 0; [L16] ~t2_pc~0 := 0; [L17] ~t3_pc~0 := 0; [L18] ~t4_pc~0 := 0; [L19] ~t5_pc~0 := 0; [L20] ~t6_pc~0 := 0; [L21] ~t7_pc~0 := 0; [L22] ~m_st~0 := 0; [L23] ~t1_st~0 := 0; [L24] ~t2_st~0 := 0; [L25] ~t3_st~0 := 0; [L26] ~t4_st~0 := 0; [L27] ~t5_st~0 := 0; [L28] ~t6_st~0 := 0; [L29] ~t7_st~0 := 0; [L30] ~m_i~0 := 0; [L31] ~t1_i~0 := 0; [L32] ~t2_i~0 := 0; [L33] ~t3_i~0 := 0; [L34] ~t4_i~0 := 0; [L35] ~t5_i~0 := 0; [L36] ~t6_i~0 := 0; [L37] ~t7_i~0 := 0; [L38] ~M_E~0 := 2; [L39] ~T1_E~0 := 2; [L40] ~T2_E~0 := 2; [L41] ~T3_E~0 := 2; [L42] ~T4_E~0 := 2; [L43] ~T5_E~0 := 2; [L44] ~T6_E~0 := 2; [L45] ~T7_E~0 := 2; [L46] ~E_M~0 := 2; [L47] ~E_1~0 := 2; [L48] ~E_2~0 := 2; [L49] ~E_3~0 := 2; [L50] ~E_4~0 := 2; [L51] ~E_5~0 := 2; [L52] ~E_6~0 := 2; [L53] ~E_7~0 := 2; [L63] ~token~0 := 0; [L65] ~local~0 := 0; [?] havoc main_#res; [?] havoc main_~__retres1~9; [L1225] havoc main_~__retres1~9; [L1134] ~m_i~0 := 1; [L1135] ~t1_i~0 := 1; [L1136] ~t2_i~0 := 1; [L1137] ~t3_i~0 := 1; [L1138] ~t4_i~0 := 1; [L1139] ~t5_i~0 := 1; [L1140] ~t6_i~0 := 1; [L1141] ~t7_i~0 := 1; [L1230] havoc start_simulation_#t~ret20, start_simulation_#t~ret21, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1; [L1166] havoc start_simulation_~kernel_st~0; [L1167] havoc start_simulation_~tmp~3; [L1168] havoc start_simulation_~tmp___0~1; [L1172] start_simulation_~kernel_st~0 := 0; [L538] COND TRUE 1 == ~m_i~0 [L539] ~m_st~0 := 0; [L543] COND TRUE 1 == ~t1_i~0 [L544] ~t1_st~0 := 0; [L548] COND TRUE 1 == ~t2_i~0 [L549] ~t2_st~0 := 0; [L553] COND TRUE 1 == ~t3_i~0 [L554] ~t3_st~0 := 0; [L558] COND TRUE 1 == ~t4_i~0 [L559] ~t4_st~0 := 0; [L563] COND TRUE 1 == ~t5_i~0 [L564] ~t5_st~0 := 0; [L568] COND TRUE 1 == ~t6_i~0 [L569] ~t6_st~0 := 0; [L573] COND TRUE 1 == ~t7_i~0 [L574] ~t7_st~0 := 0; [L771] COND FALSE !(0 == ~M_E~0) [L776] COND FALSE !(0 == ~T1_E~0) [L781] COND FALSE !(0 == ~T2_E~0) [L786] COND FALSE !(0 == ~T3_E~0) [L791] COND FALSE !(0 == ~T4_E~0) [L796] COND FALSE !(0 == ~T5_E~0) [L801] COND FALSE !(0 == ~T6_E~0) [L806] COND FALSE !(0 == ~T7_E~0) [L811] COND FALSE !(0 == ~E_M~0) [L816] COND FALSE !(0 == ~E_1~0) [L821] COND FALSE !(0 == ~E_2~0) [L826] COND FALSE !(0 == ~E_3~0) [L831] COND FALSE !(0 == ~E_4~0) [L836] COND FALSE !(0 == ~E_5~0) [L841] COND FALSE !(0 == ~E_6~0) [L846] COND FALSE !(0 == ~E_7~0) [L1176] havoc activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0; [L944] havoc activate_threads_~tmp~1; [L945] havoc activate_threads_~tmp___0~0; [L946] havoc activate_threads_~tmp___1~0; [L947] havoc activate_threads_~tmp___2~0; [L948] havoc activate_threads_~tmp___3~0; [L949] havoc activate_threads_~tmp___4~0; [L950] havoc activate_threads_~tmp___5~0; [L951] havoc activate_threads_~tmp___6~0; [L955] havoc is_master_triggered_#res; [L955] havoc is_master_triggered_~__retres1~0; [L375] havoc is_master_triggered_~__retres1~0; [L378] COND FALSE !(1 == ~m_pc~0) [L388] is_master_triggered_~__retres1~0 := 0; [L390] is_master_triggered_#res := is_master_triggered_~__retres1~0; [L955] activate_threads_#t~ret11 := is_master_triggered_#res; [L955] activate_threads_~tmp~1 := activate_threads_#t~ret11; [L955] havoc activate_threads_#t~ret11; [L957-L961] COND FALSE !(0 != activate_threads_~tmp~1) [L963] havoc is_transmit1_triggered_#res; [L963] havoc is_transmit1_triggered_~__retres1~1; [L394] havoc is_transmit1_triggered_~__retres1~1; [L397] COND FALSE !(1 == ~t1_pc~0) [L407] is_transmit1_triggered_~__retres1~1 := 0; [L409] is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; [L963] activate_threads_#t~ret12 := is_transmit1_triggered_#res; [L963] activate_threads_~tmp___0~0 := activate_threads_#t~ret12; [L963] havoc activate_threads_#t~ret12; [L965-L969] COND FALSE !(0 != activate_threads_~tmp___0~0) [L971] havoc is_transmit2_triggered_#res; [L971] havoc is_transmit2_triggered_~__retres1~2; [L413] havoc is_transmit2_triggered_~__retres1~2; [L416] COND FALSE !(1 == ~t2_pc~0) [L426] is_transmit2_triggered_~__retres1~2 := 0; [L428] is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; [L971] activate_threads_#t~ret13 := is_transmit2_triggered_#res; [L971] activate_threads_~tmp___1~0 := activate_threads_#t~ret13; [L971] havoc activate_threads_#t~ret13; [L973-L977] COND FALSE !(0 != activate_threads_~tmp___1~0) [L979] havoc is_transmit3_triggered_#res; [L979] havoc is_transmit3_triggered_~__retres1~3; [L432] havoc is_transmit3_triggered_~__retres1~3; [L435] COND FALSE !(1 == ~t3_pc~0) [L445] is_transmit3_triggered_~__retres1~3 := 0; [L447] is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; [L979] activate_threads_#t~ret14 := is_transmit3_triggered_#res; [L979] activate_threads_~tmp___2~0 := activate_threads_#t~ret14; [L979] havoc activate_threads_#t~ret14; [L981-L985] COND FALSE !(0 != activate_threads_~tmp___2~0) [L987] havoc is_transmit4_triggered_#res; [L987] havoc is_transmit4_triggered_~__retres1~4; [L451] havoc is_transmit4_triggered_~__retres1~4; [L454] COND FALSE !(1 == ~t4_pc~0) [L464] is_transmit4_triggered_~__retres1~4 := 0; [L466] is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; [L987] activate_threads_#t~ret15 := is_transmit4_triggered_#res; [L987] activate_threads_~tmp___3~0 := activate_threads_#t~ret15; [L987] havoc activate_threads_#t~ret15; [L989-L993] COND FALSE !(0 != activate_threads_~tmp___3~0) [L995] havoc is_transmit5_triggered_#res; [L995] havoc is_transmit5_triggered_~__retres1~5; [L470] havoc is_transmit5_triggered_~__retres1~5; [L473] COND FALSE !(1 == ~t5_pc~0) [L483] is_transmit5_triggered_~__retres1~5 := 0; [L485] is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; [L995] activate_threads_#t~ret16 := is_transmit5_triggered_#res; [L995] activate_threads_~tmp___4~0 := activate_threads_#t~ret16; [L995] havoc activate_threads_#t~ret16; [L997-L1001] COND FALSE !(0 != activate_threads_~tmp___4~0) [L1003] havoc is_transmit6_triggered_#res; [L1003] havoc is_transmit6_triggered_~__retres1~6; [L489] havoc is_transmit6_triggered_~__retres1~6; [L492] COND FALSE !(1 == ~t6_pc~0) [L502] is_transmit6_triggered_~__retres1~6 := 0; [L504] is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; [L1003] activate_threads_#t~ret17 := is_transmit6_triggered_#res; [L1003] activate_threads_~tmp___5~0 := activate_threads_#t~ret17; [L1003] havoc activate_threads_#t~ret17; [L1005-L1009] COND FALSE !(0 != activate_threads_~tmp___5~0) [L1011] havoc is_transmit7_triggered_#res; [L1011] havoc is_transmit7_triggered_~__retres1~7; [L508] havoc is_transmit7_triggered_~__retres1~7; [L511] COND FALSE !(1 == ~t7_pc~0) [L521] is_transmit7_triggered_~__retres1~7 := 0; [L523] is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; [L1011] activate_threads_#t~ret18 := is_transmit7_triggered_#res; [L1011] activate_threads_~tmp___6~0 := activate_threads_#t~ret18; [L1011] havoc activate_threads_#t~ret18; [L1013-L1017] COND FALSE !(0 != activate_threads_~tmp___6~0) [L859] COND FALSE !(1 == ~M_E~0) [L864] COND FALSE !(1 == ~T1_E~0) [L869] COND FALSE !(1 == ~T2_E~0) [L874] COND FALSE !(1 == ~T3_E~0) [L879] COND FALSE !(1 == ~T4_E~0) [L884] COND FALSE !(1 == ~T5_E~0) [L889] COND FALSE !(1 == ~T6_E~0) [L894] COND FALSE !(1 == ~T7_E~0) [L899] COND FALSE !(1 == ~E_M~0) [L904] COND FALSE !(1 == ~E_1~0) [L909] COND FALSE !(1 == ~E_2~0) [L914] COND FALSE !(1 == ~E_3~0) [L919] COND FALSE !(1 == ~E_4~0) [L924] COND FALSE !(1 == ~E_5~0) [L929] COND FALSE !(1 == ~E_6~0) [L934] COND FALSE !(1 == ~E_7~0) [L1180-L1217] COND FALSE !(false) [L1183] start_simulation_~kernel_st~0 := 1; [L1184] havoc eval_#t~ret2, eval_#t~nondet3, eval_~tmp_ndt_1~0, eval_#t~nondet4, eval_~tmp_ndt_2~0, eval_#t~nondet5, eval_~tmp_ndt_3~0, eval_#t~nondet6, eval_~tmp_ndt_4~0, eval_#t~nondet7, eval_~tmp_ndt_5~0, eval_#t~nondet8, eval_~tmp_ndt_6~0, eval_#t~nondet9, eval_~tmp_ndt_7~0, eval_#t~nondet10, eval_~tmp_ndt_8~0, eval_~tmp~0; [L634] havoc eval_~tmp~0; ----- ----- class de.uni_freiburg.informatik.ultimate.boogie.procedureinliner.backtranslation.InlinerBacktranslator [L14] ~m_pc~0 := 0; [L15] ~t1_pc~0 := 0; [L16] ~t2_pc~0 := 0; [L17] ~t3_pc~0 := 0; [L18] ~t4_pc~0 := 0; [L19] ~t5_pc~0 := 0; [L20] ~t6_pc~0 := 0; [L21] ~t7_pc~0 := 0; [L22] ~m_st~0 := 0; [L23] ~t1_st~0 := 0; [L24] ~t2_st~0 := 0; [L25] ~t3_st~0 := 0; [L26] ~t4_st~0 := 0; [L27] ~t5_st~0 := 0; [L28] ~t6_st~0 := 0; [L29] ~t7_st~0 := 0; [L30] ~m_i~0 := 0; [L31] ~t1_i~0 := 0; [L32] ~t2_i~0 := 0; [L33] ~t3_i~0 := 0; [L34] ~t4_i~0 := 0; [L35] ~t5_i~0 := 0; [L36] ~t6_i~0 := 0; [L37] ~t7_i~0 := 0; [L38] ~M_E~0 := 2; [L39] ~T1_E~0 := 2; [L40] ~T2_E~0 := 2; [L41] ~T3_E~0 := 2; [L42] ~T4_E~0 := 2; [L43] ~T5_E~0 := 2; [L44] ~T6_E~0 := 2; [L45] ~T7_E~0 := 2; [L46] ~E_M~0 := 2; [L47] ~E_1~0 := 2; [L48] ~E_2~0 := 2; [L49] ~E_3~0 := 2; [L50] ~E_4~0 := 2; [L51] ~E_5~0 := 2; [L52] ~E_6~0 := 2; [L53] ~E_7~0 := 2; [L63] ~token~0 := 0; [L65] ~local~0 := 0; [?] havoc main_#res; [?] havoc main_~__retres1~9; [L1225] havoc main_~__retres1~9; [L1134] ~m_i~0 := 1; [L1135] ~t1_i~0 := 1; [L1136] ~t2_i~0 := 1; [L1137] ~t3_i~0 := 1; [L1138] ~t4_i~0 := 1; [L1139] ~t5_i~0 := 1; [L1140] ~t6_i~0 := 1; [L1141] ~t7_i~0 := 1; [L1230] havoc start_simulation_#t~ret20, start_simulation_#t~ret21, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1; [L1166] havoc start_simulation_~kernel_st~0; [L1167] havoc start_simulation_~tmp~3; [L1168] havoc start_simulation_~tmp___0~1; [L1172] start_simulation_~kernel_st~0 := 0; [L538] COND TRUE 1 == ~m_i~0 [L539] ~m_st~0 := 0; [L543] COND TRUE 1 == ~t1_i~0 [L544] ~t1_st~0 := 0; [L548] COND TRUE 1 == ~t2_i~0 [L549] ~t2_st~0 := 0; [L553] COND TRUE 1 == ~t3_i~0 [L554] ~t3_st~0 := 0; [L558] COND TRUE 1 == ~t4_i~0 [L559] ~t4_st~0 := 0; [L563] COND TRUE 1 == ~t5_i~0 [L564] ~t5_st~0 := 0; [L568] COND TRUE 1 == ~t6_i~0 [L569] ~t6_st~0 := 0; [L573] COND TRUE 1 == ~t7_i~0 [L574] ~t7_st~0 := 0; [L771] COND FALSE !(0 == ~M_E~0) [L776] COND FALSE !(0 == ~T1_E~0) [L781] COND FALSE !(0 == ~T2_E~0) [L786] COND FALSE !(0 == ~T3_E~0) [L791] COND FALSE !(0 == ~T4_E~0) [L796] COND FALSE !(0 == ~T5_E~0) [L801] COND FALSE !(0 == ~T6_E~0) [L806] COND FALSE !(0 == ~T7_E~0) [L811] COND FALSE !(0 == ~E_M~0) [L816] COND FALSE !(0 == ~E_1~0) [L821] COND FALSE !(0 == ~E_2~0) [L826] COND FALSE !(0 == ~E_3~0) [L831] COND FALSE !(0 == ~E_4~0) [L836] COND FALSE !(0 == ~E_5~0) [L841] COND FALSE !(0 == ~E_6~0) [L846] COND FALSE !(0 == ~E_7~0) [L1176] havoc activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0; [L944] havoc activate_threads_~tmp~1; [L945] havoc activate_threads_~tmp___0~0; [L946] havoc activate_threads_~tmp___1~0; [L947] havoc activate_threads_~tmp___2~0; [L948] havoc activate_threads_~tmp___3~0; [L949] havoc activate_threads_~tmp___4~0; [L950] havoc activate_threads_~tmp___5~0; [L951] havoc activate_threads_~tmp___6~0; [L955] havoc is_master_triggered_#res; [L955] havoc is_master_triggered_~__retres1~0; [L375] havoc is_master_triggered_~__retres1~0; [L378] COND FALSE !(1 == ~m_pc~0) [L388] is_master_triggered_~__retres1~0 := 0; [L390] is_master_triggered_#res := is_master_triggered_~__retres1~0; [L955] activate_threads_#t~ret11 := is_master_triggered_#res; [L955] activate_threads_~tmp~1 := activate_threads_#t~ret11; [L955] havoc activate_threads_#t~ret11; [L957-L961] COND FALSE !(0 != activate_threads_~tmp~1) [L963] havoc is_transmit1_triggered_#res; [L963] havoc is_transmit1_triggered_~__retres1~1; [L394] havoc is_transmit1_triggered_~__retres1~1; [L397] COND FALSE !(1 == ~t1_pc~0) [L407] is_transmit1_triggered_~__retres1~1 := 0; [L409] is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; [L963] activate_threads_#t~ret12 := is_transmit1_triggered_#res; [L963] activate_threads_~tmp___0~0 := activate_threads_#t~ret12; [L963] havoc activate_threads_#t~ret12; [L965-L969] COND FALSE !(0 != activate_threads_~tmp___0~0) [L971] havoc is_transmit2_triggered_#res; [L971] havoc is_transmit2_triggered_~__retres1~2; [L413] havoc is_transmit2_triggered_~__retres1~2; [L416] COND FALSE !(1 == ~t2_pc~0) [L426] is_transmit2_triggered_~__retres1~2 := 0; [L428] is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; [L971] activate_threads_#t~ret13 := is_transmit2_triggered_#res; [L971] activate_threads_~tmp___1~0 := activate_threads_#t~ret13; [L971] havoc activate_threads_#t~ret13; [L973-L977] COND FALSE !(0 != activate_threads_~tmp___1~0) [L979] havoc is_transmit3_triggered_#res; [L979] havoc is_transmit3_triggered_~__retres1~3; [L432] havoc is_transmit3_triggered_~__retres1~3; [L435] COND FALSE !(1 == ~t3_pc~0) [L445] is_transmit3_triggered_~__retres1~3 := 0; [L447] is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; [L979] activate_threads_#t~ret14 := is_transmit3_triggered_#res; [L979] activate_threads_~tmp___2~0 := activate_threads_#t~ret14; [L979] havoc activate_threads_#t~ret14; [L981-L985] COND FALSE !(0 != activate_threads_~tmp___2~0) [L987] havoc is_transmit4_triggered_#res; [L987] havoc is_transmit4_triggered_~__retres1~4; [L451] havoc is_transmit4_triggered_~__retres1~4; [L454] COND FALSE !(1 == ~t4_pc~0) [L464] is_transmit4_triggered_~__retres1~4 := 0; [L466] is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; [L987] activate_threads_#t~ret15 := is_transmit4_triggered_#res; [L987] activate_threads_~tmp___3~0 := activate_threads_#t~ret15; [L987] havoc activate_threads_#t~ret15; [L989-L993] COND FALSE !(0 != activate_threads_~tmp___3~0) [L995] havoc is_transmit5_triggered_#res; [L995] havoc is_transmit5_triggered_~__retres1~5; [L470] havoc is_transmit5_triggered_~__retres1~5; [L473] COND FALSE !(1 == ~t5_pc~0) [L483] is_transmit5_triggered_~__retres1~5 := 0; [L485] is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; [L995] activate_threads_#t~ret16 := is_transmit5_triggered_#res; [L995] activate_threads_~tmp___4~0 := activate_threads_#t~ret16; [L995] havoc activate_threads_#t~ret16; [L997-L1001] COND FALSE !(0 != activate_threads_~tmp___4~0) [L1003] havoc is_transmit6_triggered_#res; [L1003] havoc is_transmit6_triggered_~__retres1~6; [L489] havoc is_transmit6_triggered_~__retres1~6; [L492] COND FALSE !(1 == ~t6_pc~0) [L502] is_transmit6_triggered_~__retres1~6 := 0; [L504] is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; [L1003] activate_threads_#t~ret17 := is_transmit6_triggered_#res; [L1003] activate_threads_~tmp___5~0 := activate_threads_#t~ret17; [L1003] havoc activate_threads_#t~ret17; [L1005-L1009] COND FALSE !(0 != activate_threads_~tmp___5~0) [L1011] havoc is_transmit7_triggered_#res; [L1011] havoc is_transmit7_triggered_~__retres1~7; [L508] havoc is_transmit7_triggered_~__retres1~7; [L511] COND FALSE !(1 == ~t7_pc~0) [L521] is_transmit7_triggered_~__retres1~7 := 0; [L523] is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; [L1011] activate_threads_#t~ret18 := is_transmit7_triggered_#res; [L1011] activate_threads_~tmp___6~0 := activate_threads_#t~ret18; [L1011] havoc activate_threads_#t~ret18; [L1013-L1017] COND FALSE !(0 != activate_threads_~tmp___6~0) [L859] COND FALSE !(1 == ~M_E~0) [L864] COND FALSE !(1 == ~T1_E~0) [L869] COND FALSE !(1 == ~T2_E~0) [L874] COND FALSE !(1 == ~T3_E~0) [L879] COND FALSE !(1 == ~T4_E~0) [L884] COND FALSE !(1 == ~T5_E~0) [L889] COND FALSE !(1 == ~T6_E~0) [L894] COND FALSE !(1 == ~T7_E~0) [L899] COND FALSE !(1 == ~E_M~0) [L904] COND FALSE !(1 == ~E_1~0) [L909] COND FALSE !(1 == ~E_2~0) [L914] COND FALSE !(1 == ~E_3~0) [L919] COND FALSE !(1 == ~E_4~0) [L924] COND FALSE !(1 == ~E_5~0) [L929] COND FALSE !(1 == ~E_6~0) [L934] COND FALSE !(1 == ~E_7~0) [L1180-L1217] COND FALSE !(false) [L1183] start_simulation_~kernel_st~0 := 1; [L1184] havoc eval_#t~ret2, eval_#t~nondet3, eval_~tmp_ndt_1~0, eval_#t~nondet4, eval_~tmp_ndt_2~0, eval_#t~nondet5, eval_~tmp_ndt_3~0, eval_#t~nondet6, eval_~tmp_ndt_4~0, eval_#t~nondet7, eval_~tmp_ndt_5~0, eval_#t~nondet8, eval_~tmp_ndt_6~0, eval_#t~nondet9, eval_~tmp_ndt_7~0, eval_#t~nondet10, eval_~tmp_ndt_8~0, eval_~tmp~0; [L634] havoc eval_~tmp~0; [L14] ~m_pc~0 := 0; [L15] ~t1_pc~0 := 0; [L16] ~t2_pc~0 := 0; [L17] ~t3_pc~0 := 0; [L18] ~t4_pc~0 := 0; [L19] ~t5_pc~0 := 0; [L20] ~t6_pc~0 := 0; [L21] ~t7_pc~0 := 0; [L22] ~m_st~0 := 0; [L23] ~t1_st~0 := 0; [L24] ~t2_st~0 := 0; [L25] ~t3_st~0 := 0; [L26] ~t4_st~0 := 0; [L27] ~t5_st~0 := 0; [L28] ~t6_st~0 := 0; [L29] ~t7_st~0 := 0; [L30] ~m_i~0 := 0; [L31] ~t1_i~0 := 0; [L32] ~t2_i~0 := 0; [L33] ~t3_i~0 := 0; [L34] ~t4_i~0 := 0; [L35] ~t5_i~0 := 0; [L36] ~t6_i~0 := 0; [L37] ~t7_i~0 := 0; [L38] ~M_E~0 := 2; [L39] ~T1_E~0 := 2; [L40] ~T2_E~0 := 2; [L41] ~T3_E~0 := 2; [L42] ~T4_E~0 := 2; [L43] ~T5_E~0 := 2; [L44] ~T6_E~0 := 2; [L45] ~T7_E~0 := 2; [L46] ~E_M~0 := 2; [L47] ~E_1~0 := 2; [L48] ~E_2~0 := 2; [L49] ~E_3~0 := 2; [L50] ~E_4~0 := 2; [L51] ~E_5~0 := 2; [L52] ~E_6~0 := 2; [L53] ~E_7~0 := 2; [L63] ~token~0 := 0; [L65] ~local~0 := 0; [L1225] havoc ~__retres1~9; [L1134] ~m_i~0 := 1; [L1135] ~t1_i~0 := 1; [L1136] ~t2_i~0 := 1; [L1137] ~t3_i~0 := 1; [L1138] ~t4_i~0 := 1; [L1139] ~t5_i~0 := 1; [L1140] ~t6_i~0 := 1; [L1141] ~t7_i~0 := 1; [L1166] havoc ~kernel_st~0; [L1167] havoc ~tmp~3; [L1168] havoc ~tmp___0~1; [L1172] ~kernel_st~0 := 0; [L538] COND TRUE 1 == ~m_i~0 [L539] ~m_st~0 := 0; [L543] COND TRUE 1 == ~t1_i~0 [L544] ~t1_st~0 := 0; [L548] COND TRUE 1 == ~t2_i~0 [L549] ~t2_st~0 := 0; [L553] COND TRUE 1 == ~t3_i~0 [L554] ~t3_st~0 := 0; [L558] COND TRUE 1 == ~t4_i~0 [L559] ~t4_st~0 := 0; [L563] COND TRUE 1 == ~t5_i~0 [L564] ~t5_st~0 := 0; [L568] COND TRUE 1 == ~t6_i~0 [L569] ~t6_st~0 := 0; [L573] COND TRUE 1 == ~t7_i~0 [L574] ~t7_st~0 := 0; [L771] COND FALSE !(0 == ~M_E~0) [L776] COND FALSE !(0 == ~T1_E~0) [L781] COND FALSE !(0 == ~T2_E~0) [L786] COND FALSE !(0 == ~T3_E~0) [L791] COND FALSE !(0 == ~T4_E~0) [L796] COND FALSE !(0 == ~T5_E~0) [L801] COND FALSE !(0 == ~T6_E~0) [L806] COND FALSE !(0 == ~T7_E~0) [L811] COND FALSE !(0 == ~E_M~0) [L816] COND FALSE !(0 == ~E_1~0) [L821] COND FALSE !(0 == ~E_2~0) [L826] COND FALSE !(0 == ~E_3~0) [L831] COND FALSE !(0 == ~E_4~0) [L836] COND FALSE !(0 == ~E_5~0) [L841] COND FALSE !(0 == ~E_6~0) [L846] COND FALSE !(0 == ~E_7~0) [L944] havoc ~tmp~1; [L945] havoc ~tmp___0~0; [L946] havoc ~tmp___1~0; [L947] havoc ~tmp___2~0; [L948] havoc ~tmp___3~0; [L949] havoc ~tmp___4~0; [L950] havoc ~tmp___5~0; [L951] havoc ~tmp___6~0; [L375] havoc ~__retres1~0; [L378] COND FALSE !(1 == ~m_pc~0) [L388] ~__retres1~0 := 0; [L390] #res := ~__retres1~0; [L955] ~tmp~1 := #t~ret11; [L955] havoc #t~ret11; [L957-L961] COND FALSE !(0 != ~tmp~1) [L394] havoc ~__retres1~1; [L397] COND FALSE !(1 == ~t1_pc~0) [L407] ~__retres1~1 := 0; [L409] #res := ~__retres1~1; [L963] ~tmp___0~0 := #t~ret12; [L963] havoc #t~ret12; [L965-L969] COND FALSE !(0 != ~tmp___0~0) [L413] havoc ~__retres1~2; [L416] COND FALSE !(1 == ~t2_pc~0) [L426] ~__retres1~2 := 0; [L428] #res := ~__retres1~2; [L971] ~tmp___1~0 := #t~ret13; [L971] havoc #t~ret13; [L973-L977] COND FALSE !(0 != ~tmp___1~0) [L432] havoc ~__retres1~3; [L435] COND FALSE !(1 == ~t3_pc~0) [L445] ~__retres1~3 := 0; [L447] #res := ~__retres1~3; [L979] ~tmp___2~0 := #t~ret14; [L979] havoc #t~ret14; [L981-L985] COND FALSE !(0 != ~tmp___2~0) [L451] havoc ~__retres1~4; [L454] COND FALSE !(1 == ~t4_pc~0) [L464] ~__retres1~4 := 0; [L466] #res := ~__retres1~4; [L987] ~tmp___3~0 := #t~ret15; [L987] havoc #t~ret15; [L989-L993] COND FALSE !(0 != ~tmp___3~0) [L470] havoc ~__retres1~5; [L473] COND FALSE !(1 == ~t5_pc~0) [L483] ~__retres1~5 := 0; [L485] #res := ~__retres1~5; [L995] ~tmp___4~0 := #t~ret16; [L995] havoc #t~ret16; [L997-L1001] COND FALSE !(0 != ~tmp___4~0) [L489] havoc ~__retres1~6; [L492] COND FALSE !(1 == ~t6_pc~0) [L502] ~__retres1~6 := 0; [L504] #res := ~__retres1~6; [L1003] ~tmp___5~0 := #t~ret17; [L1003] havoc #t~ret17; [L1005-L1009] COND FALSE !(0 != ~tmp___5~0) [L508] havoc ~__retres1~7; [L511] COND FALSE !(1 == ~t7_pc~0) [L521] ~__retres1~7 := 0; [L523] #res := ~__retres1~7; [L1011] ~tmp___6~0 := #t~ret18; [L1011] havoc #t~ret18; [L1013-L1017] COND FALSE !(0 != ~tmp___6~0) [L859] COND FALSE !(1 == ~M_E~0) [L864] COND FALSE !(1 == ~T1_E~0) [L869] COND FALSE !(1 == ~T2_E~0) [L874] COND FALSE !(1 == ~T3_E~0) [L879] COND FALSE !(1 == ~T4_E~0) [L884] COND FALSE !(1 == ~T5_E~0) [L889] COND FALSE !(1 == ~T6_E~0) [L894] COND FALSE !(1 == ~T7_E~0) [L899] COND FALSE !(1 == ~E_M~0) [L904] COND FALSE !(1 == ~E_1~0) [L909] COND FALSE !(1 == ~E_2~0) [L914] COND FALSE !(1 == ~E_3~0) [L919] COND FALSE !(1 == ~E_4~0) [L924] COND FALSE !(1 == ~E_5~0) [L929] COND FALSE !(1 == ~E_6~0) [L934] COND FALSE !(1 == ~E_7~0) [L1180-L1217] COND FALSE !(false) [L1183] ~kernel_st~0 := 1; [L634] havoc ~tmp~0; ----- ----- class de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.CACSL2BoogieBacktranslator [L14] ~m_pc~0 := 0; [L15] ~t1_pc~0 := 0; [L16] ~t2_pc~0 := 0; [L17] ~t3_pc~0 := 0; [L18] ~t4_pc~0 := 0; [L19] ~t5_pc~0 := 0; [L20] ~t6_pc~0 := 0; [L21] ~t7_pc~0 := 0; [L22] ~m_st~0 := 0; [L23] ~t1_st~0 := 0; [L24] ~t2_st~0 := 0; [L25] ~t3_st~0 := 0; [L26] ~t4_st~0 := 0; [L27] ~t5_st~0 := 0; [L28] ~t6_st~0 := 0; [L29] ~t7_st~0 := 0; [L30] ~m_i~0 := 0; [L31] ~t1_i~0 := 0; [L32] ~t2_i~0 := 0; [L33] ~t3_i~0 := 0; [L34] ~t4_i~0 := 0; [L35] ~t5_i~0 := 0; [L36] ~t6_i~0 := 0; [L37] ~t7_i~0 := 0; [L38] ~M_E~0 := 2; [L39] ~T1_E~0 := 2; [L40] ~T2_E~0 := 2; [L41] ~T3_E~0 := 2; [L42] ~T4_E~0 := 2; [L43] ~T5_E~0 := 2; [L44] ~T6_E~0 := 2; [L45] ~T7_E~0 := 2; [L46] ~E_M~0 := 2; [L47] ~E_1~0 := 2; [L48] ~E_2~0 := 2; [L49] ~E_3~0 := 2; [L50] ~E_4~0 := 2; [L51] ~E_5~0 := 2; [L52] ~E_6~0 := 2; [L53] ~E_7~0 := 2; [L63] ~token~0 := 0; [L65] ~local~0 := 0; [L1225] havoc ~__retres1~9; [L1134] ~m_i~0 := 1; [L1135] ~t1_i~0 := 1; [L1136] ~t2_i~0 := 1; [L1137] ~t3_i~0 := 1; [L1138] ~t4_i~0 := 1; [L1139] ~t5_i~0 := 1; [L1140] ~t6_i~0 := 1; [L1141] ~t7_i~0 := 1; [L1166] havoc ~kernel_st~0; [L1167] havoc ~tmp~3; [L1168] havoc ~tmp___0~1; [L1172] ~kernel_st~0 := 0; [L538] COND TRUE 1 == ~m_i~0 [L539] ~m_st~0 := 0; [L543] COND TRUE 1 == ~t1_i~0 [L544] ~t1_st~0 := 0; [L548] COND TRUE 1 == ~t2_i~0 [L549] ~t2_st~0 := 0; [L553] COND TRUE 1 == ~t3_i~0 [L554] ~t3_st~0 := 0; [L558] COND TRUE 1 == ~t4_i~0 [L559] ~t4_st~0 := 0; [L563] COND TRUE 1 == ~t5_i~0 [L564] ~t5_st~0 := 0; [L568] COND TRUE 1 == ~t6_i~0 [L569] ~t6_st~0 := 0; [L573] COND TRUE 1 == ~t7_i~0 [L574] ~t7_st~0 := 0; [L771] COND FALSE !(0 == ~M_E~0) [L776] COND FALSE !(0 == ~T1_E~0) [L781] COND FALSE !(0 == ~T2_E~0) [L786] COND FALSE !(0 == ~T3_E~0) [L791] COND FALSE !(0 == ~T4_E~0) [L796] COND FALSE !(0 == ~T5_E~0) [L801] COND FALSE !(0 == ~T6_E~0) [L806] COND FALSE !(0 == ~T7_E~0) [L811] COND FALSE !(0 == ~E_M~0) [L816] COND FALSE !(0 == ~E_1~0) [L821] COND FALSE !(0 == ~E_2~0) [L826] COND FALSE !(0 == ~E_3~0) [L831] COND FALSE !(0 == ~E_4~0) [L836] COND FALSE !(0 == ~E_5~0) [L841] COND FALSE !(0 == ~E_6~0) [L846] COND FALSE !(0 == ~E_7~0) [L944] havoc ~tmp~1; [L945] havoc ~tmp___0~0; [L946] havoc ~tmp___1~0; [L947] havoc ~tmp___2~0; [L948] havoc ~tmp___3~0; [L949] havoc ~tmp___4~0; [L950] havoc ~tmp___5~0; [L951] havoc ~tmp___6~0; [L375] havoc ~__retres1~0; [L378] COND FALSE !(1 == ~m_pc~0) [L388] ~__retres1~0 := 0; [L390] #res := ~__retres1~0; [L955] ~tmp~1 := #t~ret11; [L955] havoc #t~ret11; [L957-L961] COND FALSE !(0 != ~tmp~1) [L394] havoc ~__retres1~1; [L397] COND FALSE !(1 == ~t1_pc~0) [L407] ~__retres1~1 := 0; [L409] #res := ~__retres1~1; [L963] ~tmp___0~0 := #t~ret12; [L963] havoc #t~ret12; [L965-L969] COND FALSE !(0 != ~tmp___0~0) [L413] havoc ~__retres1~2; [L416] COND FALSE !(1 == ~t2_pc~0) [L426] ~__retres1~2 := 0; [L428] #res := ~__retres1~2; [L971] ~tmp___1~0 := #t~ret13; [L971] havoc #t~ret13; [L973-L977] COND FALSE !(0 != ~tmp___1~0) [L432] havoc ~__retres1~3; [L435] COND FALSE !(1 == ~t3_pc~0) [L445] ~__retres1~3 := 0; [L447] #res := ~__retres1~3; [L979] ~tmp___2~0 := #t~ret14; [L979] havoc #t~ret14; [L981-L985] COND FALSE !(0 != ~tmp___2~0) [L451] havoc ~__retres1~4; [L454] COND FALSE !(1 == ~t4_pc~0) [L464] ~__retres1~4 := 0; [L466] #res := ~__retres1~4; [L987] ~tmp___3~0 := #t~ret15; [L987] havoc #t~ret15; [L989-L993] COND FALSE !(0 != ~tmp___3~0) [L470] havoc ~__retres1~5; [L473] COND FALSE !(1 == ~t5_pc~0) [L483] ~__retres1~5 := 0; [L485] #res := ~__retres1~5; [L995] ~tmp___4~0 := #t~ret16; [L995] havoc #t~ret16; [L997-L1001] COND FALSE !(0 != ~tmp___4~0) [L489] havoc ~__retres1~6; [L492] COND FALSE !(1 == ~t6_pc~0) [L502] ~__retres1~6 := 0; [L504] #res := ~__retres1~6; [L1003] ~tmp___5~0 := #t~ret17; [L1003] havoc #t~ret17; [L1005-L1009] COND FALSE !(0 != ~tmp___5~0) [L508] havoc ~__retres1~7; [L511] COND FALSE !(1 == ~t7_pc~0) [L521] ~__retres1~7 := 0; [L523] #res := ~__retres1~7; [L1011] ~tmp___6~0 := #t~ret18; [L1011] havoc #t~ret18; [L1013-L1017] COND FALSE !(0 != ~tmp___6~0) [L859] COND FALSE !(1 == ~M_E~0) [L864] COND FALSE !(1 == ~T1_E~0) [L869] COND FALSE !(1 == ~T2_E~0) [L874] COND FALSE !(1 == ~T3_E~0) [L879] COND FALSE !(1 == ~T4_E~0) [L884] COND FALSE !(1 == ~T5_E~0) [L889] COND FALSE !(1 == ~T6_E~0) [L894] COND FALSE !(1 == ~T7_E~0) [L899] COND FALSE !(1 == ~E_M~0) [L904] COND FALSE !(1 == ~E_1~0) [L909] COND FALSE !(1 == ~E_2~0) [L914] COND FALSE !(1 == ~E_3~0) [L919] COND FALSE !(1 == ~E_4~0) [L924] COND FALSE !(1 == ~E_5~0) [L929] COND FALSE !(1 == ~E_6~0) [L934] COND FALSE !(1 == ~E_7~0) [L1180-L1217] COND FALSE !(false) [L1183] ~kernel_st~0 := 1; [L634] havoc ~tmp~0; [L14] int m_pc = 0; [L15] int t1_pc = 0; [L16] int t2_pc = 0; [L17] int t3_pc = 0; [L18] int t4_pc = 0; [L19] int t5_pc = 0; [L20] int t6_pc = 0; [L21] int t7_pc = 0; [L22] int m_st ; [L23] int t1_st ; [L24] int t2_st ; [L25] int t3_st ; [L26] int t4_st ; [L27] int t5_st ; [L28] int t6_st ; [L29] int t7_st ; [L30] int m_i ; [L31] int t1_i ; [L32] int t2_i ; [L33] int t3_i ; [L34] int t4_i ; [L35] int t5_i ; [L36] int t6_i ; [L37] int t7_i ; [L38] int M_E = 2; [L39] int T1_E = 2; [L40] int T2_E = 2; [L41] int T3_E = 2; [L42] int T4_E = 2; [L43] int T5_E = 2; [L44] int T6_E = 2; [L45] int T7_E = 2; [L46] int E_M = 2; [L47] int E_1 = 2; [L48] int E_2 = 2; [L49] int E_3 = 2; [L50] int E_4 = 2; [L51] int E_5 = 2; [L52] int E_6 = 2; [L53] int E_7 = 2; [L63] int token ; [L65] int local ; [L1225] int __retres1 ; [L1134] m_i = 1 [L1135] t1_i = 1 [L1136] t2_i = 1 [L1137] t3_i = 1 [L1138] t4_i = 1 [L1139] t5_i = 1 [L1140] t6_i = 1 [L1141] t7_i = 1 [L1166] int kernel_st ; [L1167] int tmp ; [L1168] int tmp___0 ; [L1172] kernel_st = 0 [L538] COND TRUE m_i == 1 [L539] m_st = 0 [L543] COND TRUE t1_i == 1 [L544] t1_st = 0 [L548] COND TRUE t2_i == 1 [L549] t2_st = 0 [L553] COND TRUE t3_i == 1 [L554] t3_st = 0 [L558] COND TRUE t4_i == 1 [L559] t4_st = 0 [L563] COND TRUE t5_i == 1 [L564] t5_st = 0 [L568] COND TRUE t6_i == 1 [L569] t6_st = 0 [L573] COND TRUE t7_i == 1 [L574] t7_st = 0 [L771] COND FALSE !(M_E == 0) [L776] COND FALSE !(T1_E == 0) [L781] COND FALSE !(T2_E == 0) [L786] COND FALSE !(T3_E == 0) [L791] COND FALSE !(T4_E == 0) [L796] COND FALSE !(T5_E == 0) [L801] COND FALSE !(T6_E == 0) [L806] COND FALSE !(T7_E == 0) [L811] COND FALSE !(E_M == 0) [L816] COND FALSE !(E_1 == 0) [L821] COND FALSE !(E_2 == 0) [L826] COND FALSE !(E_3 == 0) [L831] COND FALSE !(E_4 == 0) [L836] COND FALSE !(E_5 == 0) [L841] COND FALSE !(E_6 == 0) [L846] COND FALSE !(E_7 == 0) [L944] int tmp ; [L945] int tmp___0 ; [L946] int tmp___1 ; [L947] int tmp___2 ; [L948] int tmp___3 ; [L949] int tmp___4 ; [L950] int tmp___5 ; [L951] int tmp___6 ; [L375] int __retres1 ; [L378] COND FALSE !(m_pc == 1) [L388] __retres1 = 0 [L390] return (__retres1); [L955] tmp = is_master_triggered() [L957] COND FALSE !(\read(tmp)) [L394] int __retres1 ; [L397] COND FALSE !(t1_pc == 1) [L407] __retres1 = 0 [L409] return (__retres1); [L963] tmp___0 = is_transmit1_triggered() [L965] COND FALSE !(\read(tmp___0)) [L413] int __retres1 ; [L416] COND FALSE !(t2_pc == 1) [L426] __retres1 = 0 [L428] return (__retres1); [L971] tmp___1 = is_transmit2_triggered() [L973] COND FALSE !(\read(tmp___1)) [L432] int __retres1 ; [L435] COND FALSE !(t3_pc == 1) [L445] __retres1 = 0 [L447] return (__retres1); [L979] tmp___2 = is_transmit3_triggered() [L981] COND FALSE !(\read(tmp___2)) [L451] int __retres1 ; [L454] COND FALSE !(t4_pc == 1) [L464] __retres1 = 0 [L466] return (__retres1); [L987] tmp___3 = is_transmit4_triggered() [L989] COND FALSE !(\read(tmp___3)) [L470] int __retres1 ; [L473] COND FALSE !(t5_pc == 1) [L483] __retres1 = 0 [L485] return (__retres1); [L995] tmp___4 = is_transmit5_triggered() [L997] COND FALSE !(\read(tmp___4)) [L489] int __retres1 ; [L492] COND FALSE !(t6_pc == 1) [L502] __retres1 = 0 [L504] return (__retres1); [L1003] tmp___5 = is_transmit6_triggered() [L1005] COND FALSE !(\read(tmp___5)) [L508] int __retres1 ; [L511] COND FALSE !(t7_pc == 1) [L521] __retres1 = 0 [L523] return (__retres1); [L1011] tmp___6 = is_transmit7_triggered() [L1013] COND FALSE !(\read(tmp___6)) [L859] COND FALSE !(M_E == 1) [L864] COND FALSE !(T1_E == 1) [L869] COND FALSE !(T2_E == 1) [L874] COND FALSE !(T3_E == 1) [L879] COND FALSE !(T4_E == 1) [L884] COND FALSE !(T5_E == 1) [L889] COND FALSE !(T6_E == 1) [L894] COND FALSE !(T7_E == 1) [L899] COND FALSE !(E_M == 1) [L904] COND FALSE !(E_1 == 1) [L909] COND FALSE !(E_2 == 1) [L914] COND FALSE !(E_3 == 1) [L919] COND FALSE !(E_4 == 1) [L924] COND FALSE !(E_5 == 1) [L929] COND FALSE !(E_6 == 1) [L934] COND FALSE !(E_7 == 1) [L1180] COND TRUE 1 [L1183] kernel_st = 1 [L634] int tmp ; ----- ----- class de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder.RCFGBacktranslator [?] assume !false; [?] havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~8;havoc exists_runnable_thread_~__retres1~8; [?] assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8 := 1; [?] exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; [?] eval_#t~ret2 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret2;havoc eval_#t~ret2; [?] assume 0 != eval_~tmp~0; [?] assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0;eval_~tmp_ndt_1~0 := eval_#t~nondet3;havoc eval_#t~nondet3; [?] assume !(0 != eval_~tmp_ndt_1~0); [?] assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0;eval_~tmp_ndt_2~0 := eval_#t~nondet4;havoc eval_#t~nondet4; [?] assume !(0 != eval_~tmp_ndt_2~0); [?] assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0;eval_~tmp_ndt_3~0 := eval_#t~nondet5;havoc eval_#t~nondet5; [?] assume !(0 != eval_~tmp_ndt_3~0); [?] assume 0 == ~t3_st~0;havoc eval_~tmp_ndt_4~0;eval_~tmp_ndt_4~0 := eval_#t~nondet6;havoc eval_#t~nondet6; [?] assume !(0 != eval_~tmp_ndt_4~0); [?] assume 0 == ~t4_st~0;havoc eval_~tmp_ndt_5~0;eval_~tmp_ndt_5~0 := eval_#t~nondet7;havoc eval_#t~nondet7; [?] assume !(0 != eval_~tmp_ndt_5~0); [?] assume 0 == ~t5_st~0;havoc eval_~tmp_ndt_6~0;eval_~tmp_ndt_6~0 := eval_#t~nondet8;havoc eval_#t~nondet8; [?] assume !(0 != eval_~tmp_ndt_6~0); [?] assume 0 == ~t6_st~0;havoc eval_~tmp_ndt_7~0;eval_~tmp_ndt_7~0 := eval_#t~nondet9;havoc eval_#t~nondet9; [?] assume !(0 != eval_~tmp_ndt_7~0); [?] assume 0 == ~t7_st~0;havoc eval_~tmp_ndt_8~0;eval_~tmp_ndt_8~0 := eval_#t~nondet10;havoc eval_#t~nondet10; [?] assume !(0 != eval_~tmp_ndt_8~0); [L638-L760] assume !false; [L641] havoc exists_runnable_thread_#res; [L641] havoc exists_runnable_thread_~__retres1~8; [L583] havoc exists_runnable_thread_~__retres1~8; [L586-L626] assume 0 == ~m_st~0; [L587] exists_runnable_thread_~__retres1~8 := 1; [L629] exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; [L641] eval_#t~ret2 := exists_runnable_thread_#res; [L641] eval_~tmp~0 := eval_#t~ret2; [L641] havoc eval_#t~ret2; [L643-L647] assume 0 != eval_~tmp~0; [L648-L661] assume 0 == ~m_st~0; [L649] havoc eval_~tmp_ndt_1~0; [L650] eval_~tmp_ndt_1~0 := eval_#t~nondet3; [L650] havoc eval_#t~nondet3; [L651-L658] assume !(0 != eval_~tmp_ndt_1~0); [L662-L675] assume 0 == ~t1_st~0; [L663] havoc eval_~tmp_ndt_2~0; [L664] eval_~tmp_ndt_2~0 := eval_#t~nondet4; [L664] havoc eval_#t~nondet4; [L665-L672] assume !(0 != eval_~tmp_ndt_2~0); [L676-L689] assume 0 == ~t2_st~0; [L677] havoc eval_~tmp_ndt_3~0; [L678] eval_~tmp_ndt_3~0 := eval_#t~nondet5; [L678] havoc eval_#t~nondet5; [L679-L686] assume !(0 != eval_~tmp_ndt_3~0); [L690-L703] assume 0 == ~t3_st~0; [L691] havoc eval_~tmp_ndt_4~0; [L692] eval_~tmp_ndt_4~0 := eval_#t~nondet6; [L692] havoc eval_#t~nondet6; [L693-L700] assume !(0 != eval_~tmp_ndt_4~0); [L704-L717] assume 0 == ~t4_st~0; [L705] havoc eval_~tmp_ndt_5~0; [L706] eval_~tmp_ndt_5~0 := eval_#t~nondet7; [L706] havoc eval_#t~nondet7; [L707-L714] assume !(0 != eval_~tmp_ndt_5~0); [L718-L731] assume 0 == ~t5_st~0; [L719] havoc eval_~tmp_ndt_6~0; [L720] eval_~tmp_ndt_6~0 := eval_#t~nondet8; [L720] havoc eval_#t~nondet8; [L721-L728] assume !(0 != eval_~tmp_ndt_6~0); [L732-L745] assume 0 == ~t6_st~0; [L733] havoc eval_~tmp_ndt_7~0; [L734] eval_~tmp_ndt_7~0 := eval_#t~nondet9; [L734] havoc eval_#t~nondet9; [L735-L742] assume !(0 != eval_~tmp_ndt_7~0); [L746-L759] assume 0 == ~t7_st~0; [L747] havoc eval_~tmp_ndt_8~0; [L748] eval_~tmp_ndt_8~0 := eval_#t~nondet10; [L748] havoc eval_#t~nondet10; [L749-L756] assume !(0 != eval_~tmp_ndt_8~0); ----- ----- class de.uni_freiburg.informatik.ultimate.boogie.preprocessor.BoogiePreprocessorBacktranslator [L638-L760] assume !false; [L641] havoc exists_runnable_thread_#res; [L641] havoc exists_runnable_thread_~__retres1~8; [L583] havoc exists_runnable_thread_~__retres1~8; [L586-L626] assume 0 == ~m_st~0; [L587] exists_runnable_thread_~__retres1~8 := 1; [L629] exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; [L641] eval_#t~ret2 := exists_runnable_thread_#res; [L641] eval_~tmp~0 := eval_#t~ret2; [L641] havoc eval_#t~ret2; [L643-L647] assume 0 != eval_~tmp~0; [L648-L661] assume 0 == ~m_st~0; [L649] havoc eval_~tmp_ndt_1~0; [L650] eval_~tmp_ndt_1~0 := eval_#t~nondet3; [L650] havoc eval_#t~nondet3; [L651-L658] assume !(0 != eval_~tmp_ndt_1~0); [L662-L675] assume 0 == ~t1_st~0; [L663] havoc eval_~tmp_ndt_2~0; [L664] eval_~tmp_ndt_2~0 := eval_#t~nondet4; [L664] havoc eval_#t~nondet4; [L665-L672] assume !(0 != eval_~tmp_ndt_2~0); [L676-L689] assume 0 == ~t2_st~0; [L677] havoc eval_~tmp_ndt_3~0; [L678] eval_~tmp_ndt_3~0 := eval_#t~nondet5; [L678] havoc eval_#t~nondet5; [L679-L686] assume !(0 != eval_~tmp_ndt_3~0); [L690-L703] assume 0 == ~t3_st~0; [L691] havoc eval_~tmp_ndt_4~0; [L692] eval_~tmp_ndt_4~0 := eval_#t~nondet6; [L692] havoc eval_#t~nondet6; [L693-L700] assume !(0 != eval_~tmp_ndt_4~0); [L704-L717] assume 0 == ~t4_st~0; [L705] havoc eval_~tmp_ndt_5~0; [L706] eval_~tmp_ndt_5~0 := eval_#t~nondet7; [L706] havoc eval_#t~nondet7; [L707-L714] assume !(0 != eval_~tmp_ndt_5~0); [L718-L731] assume 0 == ~t5_st~0; [L719] havoc eval_~tmp_ndt_6~0; [L720] eval_~tmp_ndt_6~0 := eval_#t~nondet8; [L720] havoc eval_#t~nondet8; [L721-L728] assume !(0 != eval_~tmp_ndt_6~0); [L732-L745] assume 0 == ~t6_st~0; [L733] havoc eval_~tmp_ndt_7~0; [L734] eval_~tmp_ndt_7~0 := eval_#t~nondet9; [L734] havoc eval_#t~nondet9; [L735-L742] assume !(0 != eval_~tmp_ndt_7~0); [L746-L759] assume 0 == ~t7_st~0; [L747] havoc eval_~tmp_ndt_8~0; [L748] eval_~tmp_ndt_8~0 := eval_#t~nondet10; [L748] havoc eval_#t~nondet10; [L749-L756] assume !(0 != eval_~tmp_ndt_8~0); [L638-L760] COND FALSE !(false) [L641] havoc exists_runnable_thread_#res; [L641] havoc exists_runnable_thread_~__retres1~8; [L583] havoc exists_runnable_thread_~__retres1~8; [L586] COND TRUE 0 == ~m_st~0 [L587] exists_runnable_thread_~__retres1~8 := 1; [L629] exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; [L641] eval_#t~ret2 := exists_runnable_thread_#res; [L641] eval_~tmp~0 := eval_#t~ret2; [L641] havoc eval_#t~ret2; [L643-L647] COND TRUE 0 != eval_~tmp~0 [L648] COND TRUE 0 == ~m_st~0 [L649] havoc eval_~tmp_ndt_1~0; [L650] eval_~tmp_ndt_1~0 := eval_#t~nondet3; [L650] havoc eval_#t~nondet3; [L651-L658] COND FALSE !(0 != eval_~tmp_ndt_1~0) [L662] COND TRUE 0 == ~t1_st~0 [L663] havoc eval_~tmp_ndt_2~0; [L664] eval_~tmp_ndt_2~0 := eval_#t~nondet4; [L664] havoc eval_#t~nondet4; [L665-L672] COND FALSE !(0 != eval_~tmp_ndt_2~0) [L676] COND TRUE 0 == ~t2_st~0 [L677] havoc eval_~tmp_ndt_3~0; [L678] eval_~tmp_ndt_3~0 := eval_#t~nondet5; [L678] havoc eval_#t~nondet5; [L679-L686] COND FALSE !(0 != eval_~tmp_ndt_3~0) [L690] COND TRUE 0 == ~t3_st~0 [L691] havoc eval_~tmp_ndt_4~0; [L692] eval_~tmp_ndt_4~0 := eval_#t~nondet6; [L692] havoc eval_#t~nondet6; [L693-L700] COND FALSE !(0 != eval_~tmp_ndt_4~0) [L704] COND TRUE 0 == ~t4_st~0 [L705] havoc eval_~tmp_ndt_5~0; [L706] eval_~tmp_ndt_5~0 := eval_#t~nondet7; [L706] havoc eval_#t~nondet7; [L707-L714] COND FALSE !(0 != eval_~tmp_ndt_5~0) [L718] COND TRUE 0 == ~t5_st~0 [L719] havoc eval_~tmp_ndt_6~0; [L720] eval_~tmp_ndt_6~0 := eval_#t~nondet8; [L720] havoc eval_#t~nondet8; [L721-L728] COND FALSE !(0 != eval_~tmp_ndt_6~0) [L732] COND TRUE 0 == ~t6_st~0 [L733] havoc eval_~tmp_ndt_7~0; [L734] eval_~tmp_ndt_7~0 := eval_#t~nondet9; [L734] havoc eval_#t~nondet9; [L735-L742] COND FALSE !(0 != eval_~tmp_ndt_7~0) [L746] COND TRUE 0 == ~t7_st~0 [L747] havoc eval_~tmp_ndt_8~0; [L748] eval_~tmp_ndt_8~0 := eval_#t~nondet10; [L748] havoc eval_#t~nondet10; [L749-L756] COND FALSE !(0 != eval_~tmp_ndt_8~0) ----- ----- class de.uni_freiburg.informatik.ultimate.boogie.procedureinliner.backtranslation.InlinerBacktranslator [L638-L760] COND FALSE !(false) [L641] havoc exists_runnable_thread_#res; [L641] havoc exists_runnable_thread_~__retres1~8; [L583] havoc exists_runnable_thread_~__retres1~8; [L586] COND TRUE 0 == ~m_st~0 [L587] exists_runnable_thread_~__retres1~8 := 1; [L629] exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; [L641] eval_#t~ret2 := exists_runnable_thread_#res; [L641] eval_~tmp~0 := eval_#t~ret2; [L641] havoc eval_#t~ret2; [L643-L647] COND TRUE 0 != eval_~tmp~0 [L648] COND TRUE 0 == ~m_st~0 [L649] havoc eval_~tmp_ndt_1~0; [L650] eval_~tmp_ndt_1~0 := eval_#t~nondet3; [L650] havoc eval_#t~nondet3; [L651-L658] COND FALSE !(0 != eval_~tmp_ndt_1~0) [L662] COND TRUE 0 == ~t1_st~0 [L663] havoc eval_~tmp_ndt_2~0; [L664] eval_~tmp_ndt_2~0 := eval_#t~nondet4; [L664] havoc eval_#t~nondet4; [L665-L672] COND FALSE !(0 != eval_~tmp_ndt_2~0) [L676] COND TRUE 0 == ~t2_st~0 [L677] havoc eval_~tmp_ndt_3~0; [L678] eval_~tmp_ndt_3~0 := eval_#t~nondet5; [L678] havoc eval_#t~nondet5; [L679-L686] COND FALSE !(0 != eval_~tmp_ndt_3~0) [L690] COND TRUE 0 == ~t3_st~0 [L691] havoc eval_~tmp_ndt_4~0; [L692] eval_~tmp_ndt_4~0 := eval_#t~nondet6; [L692] havoc eval_#t~nondet6; [L693-L700] COND FALSE !(0 != eval_~tmp_ndt_4~0) [L704] COND TRUE 0 == ~t4_st~0 [L705] havoc eval_~tmp_ndt_5~0; [L706] eval_~tmp_ndt_5~0 := eval_#t~nondet7; [L706] havoc eval_#t~nondet7; [L707-L714] COND FALSE !(0 != eval_~tmp_ndt_5~0) [L718] COND TRUE 0 == ~t5_st~0 [L719] havoc eval_~tmp_ndt_6~0; [L720] eval_~tmp_ndt_6~0 := eval_#t~nondet8; [L720] havoc eval_#t~nondet8; [L721-L728] COND FALSE !(0 != eval_~tmp_ndt_6~0) [L732] COND TRUE 0 == ~t6_st~0 [L733] havoc eval_~tmp_ndt_7~0; [L734] eval_~tmp_ndt_7~0 := eval_#t~nondet9; [L734] havoc eval_#t~nondet9; [L735-L742] COND FALSE !(0 != eval_~tmp_ndt_7~0) [L746] COND TRUE 0 == ~t7_st~0 [L747] havoc eval_~tmp_ndt_8~0; [L748] eval_~tmp_ndt_8~0 := eval_#t~nondet10; [L748] havoc eval_#t~nondet10; [L749-L756] COND FALSE !(0 != eval_~tmp_ndt_8~0) [L638-L760] COND FALSE !(false) [L583] havoc ~__retres1~8; [L586] COND TRUE 0 == ~m_st~0 [L587] ~__retres1~8 := 1; [L629] #res := ~__retres1~8; [L641] ~tmp~0 := #t~ret2; [L641] havoc #t~ret2; [L643-L647] COND TRUE 0 != ~tmp~0 [L648] COND TRUE 0 == ~m_st~0 [L649] havoc ~tmp_ndt_1~0; [L650] ~tmp_ndt_1~0 := #t~nondet3; [L650] havoc #t~nondet3; [L651-L658] COND FALSE !(0 != ~tmp_ndt_1~0) [L662] COND TRUE 0 == ~t1_st~0 [L663] havoc ~tmp_ndt_2~0; [L664] ~tmp_ndt_2~0 := #t~nondet4; [L664] havoc #t~nondet4; [L665-L672] COND FALSE !(0 != ~tmp_ndt_2~0) [L676] COND TRUE 0 == ~t2_st~0 [L677] havoc ~tmp_ndt_3~0; [L678] ~tmp_ndt_3~0 := #t~nondet5; [L678] havoc #t~nondet5; [L679-L686] COND FALSE !(0 != ~tmp_ndt_3~0) [L690] COND TRUE 0 == ~t3_st~0 [L691] havoc ~tmp_ndt_4~0; [L692] ~tmp_ndt_4~0 := #t~nondet6; [L692] havoc #t~nondet6; [L693-L700] COND FALSE !(0 != ~tmp_ndt_4~0) [L704] COND TRUE 0 == ~t4_st~0 [L705] havoc ~tmp_ndt_5~0; [L706] ~tmp_ndt_5~0 := #t~nondet7; [L706] havoc #t~nondet7; [L707-L714] COND FALSE !(0 != ~tmp_ndt_5~0) [L718] COND TRUE 0 == ~t5_st~0 [L719] havoc ~tmp_ndt_6~0; [L720] ~tmp_ndt_6~0 := #t~nondet8; [L720] havoc #t~nondet8; [L721-L728] COND FALSE !(0 != ~tmp_ndt_6~0) [L732] COND TRUE 0 == ~t6_st~0 [L733] havoc ~tmp_ndt_7~0; [L734] ~tmp_ndt_7~0 := #t~nondet9; [L734] havoc #t~nondet9; [L735-L742] COND FALSE !(0 != ~tmp_ndt_7~0) [L746] COND TRUE 0 == ~t7_st~0 [L747] havoc ~tmp_ndt_8~0; [L748] ~tmp_ndt_8~0 := #t~nondet10; [L748] havoc #t~nondet10; [L749-L756] COND FALSE !(0 != ~tmp_ndt_8~0) ----- ----- class de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.CACSL2BoogieBacktranslator [L638-L760] COND FALSE !(false) [L583] havoc ~__retres1~8; [L586] COND TRUE 0 == ~m_st~0 [L587] ~__retres1~8 := 1; [L629] #res := ~__retres1~8; [L641] ~tmp~0 := #t~ret2; [L641] havoc #t~ret2; [L643-L647] COND TRUE 0 != ~tmp~0 [L648] COND TRUE 0 == ~m_st~0 [L649] havoc ~tmp_ndt_1~0; [L650] ~tmp_ndt_1~0 := #t~nondet3; [L650] havoc #t~nondet3; [L651-L658] COND FALSE !(0 != ~tmp_ndt_1~0) [L662] COND TRUE 0 == ~t1_st~0 [L663] havoc ~tmp_ndt_2~0; [L664] ~tmp_ndt_2~0 := #t~nondet4; [L664] havoc #t~nondet4; [L665-L672] COND FALSE !(0 != ~tmp_ndt_2~0) [L676] COND TRUE 0 == ~t2_st~0 [L677] havoc ~tmp_ndt_3~0; [L678] ~tmp_ndt_3~0 := #t~nondet5; [L678] havoc #t~nondet5; [L679-L686] COND FALSE !(0 != ~tmp_ndt_3~0) [L690] COND TRUE 0 == ~t3_st~0 [L691] havoc ~tmp_ndt_4~0; [L692] ~tmp_ndt_4~0 := #t~nondet6; [L692] havoc #t~nondet6; [L693-L700] COND FALSE !(0 != ~tmp_ndt_4~0) [L704] COND TRUE 0 == ~t4_st~0 [L705] havoc ~tmp_ndt_5~0; [L706] ~tmp_ndt_5~0 := #t~nondet7; [L706] havoc #t~nondet7; [L707-L714] COND FALSE !(0 != ~tmp_ndt_5~0) [L718] COND TRUE 0 == ~t5_st~0 [L719] havoc ~tmp_ndt_6~0; [L720] ~tmp_ndt_6~0 := #t~nondet8; [L720] havoc #t~nondet8; [L721-L728] COND FALSE !(0 != ~tmp_ndt_6~0) [L732] COND TRUE 0 == ~t6_st~0 [L733] havoc ~tmp_ndt_7~0; [L734] ~tmp_ndt_7~0 := #t~nondet9; [L734] havoc #t~nondet9; [L735-L742] COND FALSE !(0 != ~tmp_ndt_7~0) [L746] COND TRUE 0 == ~t7_st~0 [L747] havoc ~tmp_ndt_8~0; [L748] ~tmp_ndt_8~0 := #t~nondet10; [L748] havoc #t~nondet10; [L749-L756] COND FALSE !(0 != ~tmp_ndt_8~0) [L638] COND TRUE 1 [L583] int __retres1 ; [L586] COND TRUE m_st == 0 [L587] __retres1 = 1 [L629] return (__retres1); [L641] tmp = exists_runnable_thread() [L643] COND TRUE \read(tmp) [L648] COND TRUE m_st == 0 [L649] int tmp_ndt_1; [L650] tmp_ndt_1 = __VERIFIER_nondet_int() [L651] COND FALSE !(\read(tmp_ndt_1)) [L662] COND TRUE t1_st == 0 [L663] int tmp_ndt_2; [L664] tmp_ndt_2 = __VERIFIER_nondet_int() [L665] COND FALSE !(\read(tmp_ndt_2)) [L676] COND TRUE t2_st == 0 [L677] int tmp_ndt_3; [L678] tmp_ndt_3 = __VERIFIER_nondet_int() [L679] COND FALSE !(\read(tmp_ndt_3)) [L690] COND TRUE t3_st == 0 [L691] int tmp_ndt_4; [L692] tmp_ndt_4 = __VERIFIER_nondet_int() [L693] COND FALSE !(\read(tmp_ndt_4)) [L704] COND TRUE t4_st == 0 [L705] int tmp_ndt_5; [L706] tmp_ndt_5 = __VERIFIER_nondet_int() [L707] COND FALSE !(\read(tmp_ndt_5)) [L718] COND TRUE t5_st == 0 [L719] int tmp_ndt_6; [L720] tmp_ndt_6 = __VERIFIER_nondet_int() [L721] COND FALSE !(\read(tmp_ndt_6)) [L732] COND TRUE t6_st == 0 [L733] int tmp_ndt_7; [L734] tmp_ndt_7 = __VERIFIER_nondet_int() [L735] COND FALSE !(\read(tmp_ndt_7)) [L746] COND TRUE t7_st == 0 [L747] int tmp_ndt_8; [L748] tmp_ndt_8 = __VERIFIER_nondet_int() [L749] COND FALSE !(\read(tmp_ndt_8)) ----- [2018-11-23 16:07:25,283 INFO L145 WitnessManager]: Wrote witness to /tmp/vcloud-vcloud-master/worker/working_dir_0fe0e757-a0d1-4897-81ed-84240e247463/bin-2019/uautomizer/witness.graphml [2018-11-23 16:07:25,283 INFO L132 PluginConnector]: ------------------------ END Witness Printer---------------------------- [2018-11-23 16:07:25,284 INFO L168 Benchmark]: Toolchain (without parser) took 74939.17 ms. Allocated memory was 1.0 GB in the beginning and 7.2 GB in the end (delta: 6.2 GB). Free memory was 959.2 MB in the beginning and 5.3 GB in the end (delta: -4.3 GB). Peak memory consumption was 1.9 GB. Max. memory is 11.5 GB. [2018-11-23 16:07:25,320 INFO L168 Benchmark]: CDTParser took 0.12 ms. Allocated memory is still 1.0 GB. Free memory is still 985.5 MB. There was no memory consumed. Max. memory is 11.5 GB. [2018-11-23 16:07:25,320 INFO L168 Benchmark]: CACSL2BoogieTranslator took 273.01 ms. Allocated memory is still 1.0 GB. Free memory was 959.2 MB in the beginning and 935.1 MB in the end (delta: 24.2 MB). Peak memory consumption was 24.2 MB. Max. memory is 11.5 GB. [2018-11-23 16:07:25,320 INFO L168 Benchmark]: Boogie Procedure Inliner took 102.40 ms. Allocated memory was 1.0 GB in the beginning and 1.2 GB in the end (delta: 132.1 MB). Free memory was 935.1 MB in the beginning and 1.1 GB in the end (delta: -188.7 MB). Peak memory consumption was 15.2 MB. Max. memory is 11.5 GB. [2018-11-23 16:07:25,321 INFO L168 Benchmark]: Boogie Preprocessor took 55.49 ms. Allocated memory is still 1.2 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 5.4 MB). Peak memory consumption was 5.4 MB. Max. memory is 11.5 GB. [2018-11-23 16:07:25,321 INFO L168 Benchmark]: RCFGBuilder took 1244.81 ms. Allocated memory is still 1.2 GB. Free memory was 1.1 GB in the beginning and 949.0 MB in the end (delta: 169.4 MB). Peak memory consumption was 169.4 MB. Max. memory is 11.5 GB. [2018-11-23 16:07:25,321 INFO L168 Benchmark]: BuchiAutomizer took 71043.66 ms. Allocated memory was 1.2 GB in the beginning and 7.2 GB in the end (delta: 6.1 GB). Free memory was 949.0 MB in the beginning and 5.3 GB in the end (delta: -4.3 GB). Peak memory consumption was 1.7 GB. Max. memory is 11.5 GB. [2018-11-23 16:07:25,321 INFO L168 Benchmark]: Witness Printer took 2216.63 ms. Allocated memory is still 7.2 GB. Free memory was 5.3 GB in the beginning and 5.3 GB in the end (delta: 96 B). Peak memory consumption was 96 B. Max. memory is 11.5 GB. [2018-11-23 16:07:25,323 INFO L336 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.12 ms. Allocated memory is still 1.0 GB. Free memory is still 985.5 MB. There was no memory consumed. Max. memory is 11.5 GB. * CACSL2BoogieTranslator took 273.01 ms. Allocated memory is still 1.0 GB. Free memory was 959.2 MB in the beginning and 935.1 MB in the end (delta: 24.2 MB). Peak memory consumption was 24.2 MB. Max. memory is 11.5 GB. * Boogie Procedure Inliner took 102.40 ms. Allocated memory was 1.0 GB in the beginning and 1.2 GB in the end (delta: 132.1 MB). Free memory was 935.1 MB in the beginning and 1.1 GB in the end (delta: -188.7 MB). Peak memory consumption was 15.2 MB. Max. memory is 11.5 GB. * Boogie Preprocessor took 55.49 ms. Allocated memory is still 1.2 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 5.4 MB). Peak memory consumption was 5.4 MB. Max. memory is 11.5 GB. * RCFGBuilder took 1244.81 ms. Allocated memory is still 1.2 GB. Free memory was 1.1 GB in the beginning and 949.0 MB in the end (delta: 169.4 MB). Peak memory consumption was 169.4 MB. Max. memory is 11.5 GB. * BuchiAutomizer took 71043.66 ms. Allocated memory was 1.2 GB in the beginning and 7.2 GB in the end (delta: 6.1 GB). Free memory was 949.0 MB in the beginning and 5.3 GB in the end (delta: -4.3 GB). Peak memory consumption was 1.7 GB. Max. memory is 11.5 GB. * Witness Printer took 2216.63 ms. Allocated memory is still 7.2 GB. Free memory was 5.3 GB in the beginning and 5.3 GB in the end (delta: 96 B). Peak memory consumption was 96 B. Max. memory is 11.5 GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - StatisticsResult: Constructed decomposition of program Your program was decomposed into 40 terminating modules (39 trivial, 1 deterministic, 0 nondeterministic) and one nonterminating remainder module.One deterministic module has affine ranking function -1 * E_5 + 1 and consists of 3 locations. 39 modules have a trivial ranking function, the largest among these consists of 6 locations. The remainder module has 872280 locations. - StatisticsResult: Timing statistics BüchiAutomizer plugin needed 70.2s and 40 iterations. TraceHistogramMax:2. Analysis of lassos took 7.4s. Construction of modules took 1.8s. Büchi inclusion checks took 5.7s. Highest rank in rank-based complementation 3. Minimization of det autom 27. Minimization of nondet autom 13. Automata minimization 33.2s AutomataMinimizationTime, 40 MinimizatonAttempts, 88203 StatesRemovedByMinimization, 21 NontrivialMinimizations. Non-live state removal took 11.8s Buchi closure took 0.5s. Biggest automaton had 872280 states and ocurred in iteration 39. Nontrivial modules had stage [1, 0, 0, 0, 0]. InterpolantCoveringCapabilityFinite: 0/0 InterpolantCoveringCapabilityBuchi: 0/0 HoareTripleCheckerStatistics: 52191 SDtfs, 57572 SDslu, 49524 SDs, 0 SdLazy, 1647 SolverSat, 673 SolverUnsat, 0 SolverUnknown, 0 SolverNotchecked, 1.8s Time LassoAnalysisResults: nont1 unkn0 SFLI12 SFLT0 conc7 concLT1 SILN1 SILU0 SILI18 SILT0 lasso0 LassoPreprocessingBenchmarks: Lassos: inital279 mio100 ax100 hnf100 lsp3 ukn100 mio100 lsp100 div100 bol100 ite100 ukn100 eq209 hnf86 smp100 dnf189 smp63 tf108 neg92 sie116 LassoTerminationAnalysisBenchmarks: ConstraintsSatisfiability: unsat Degree: 0 Time: 1ms VariablesStem: 0 VariablesLoop: 1 DisjunctsStem: 1 DisjunctsLoop: 2 SupportingInvariants: 0 MotzkinApplications: 4 LassoTerminationAnalysisBenchmarks: LassoNonterminationAnalysisSatFixpoint: 14 LassoNonterminationAnalysisSatUnbounded: 0 LassoNonterminationAnalysisUnsat: 1 LassoNonterminationAnalysisUnknown: 0 LassoNonterminationAnalysisTime: 0.1s - TerminationAnalysisResult: Nontermination possible Buchi Automizer proved that your program is nonterminating for some inputs - FixpointNonTerminationResult [Line: 638]: Nontermination argument in form of an infinite program execution. Nontermination argument in form of an infinite execution State at position 0 is {} State at position 1 is {E_7=2, t3_st=0, __retres1=0, t5_i=1, __retres1=0, kernel_st=1, \result=0, E_3=2, T6_E=2, t7_i=1, tmp_ndt_8=0, tmp_ndt_4=0, \result=0, m_st=0, t6_pc=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@1aac9ca2=0, tmp___2=0, __retres1=0, t3_pc=0, \result=0, m_pc=0, tmp___6=0, t6_st=0, E_6=2, __retres1=0, \result=0, T2_E=2, t5_st=0, __retres1=1, E_2=2, t7_pc=0, tmp=0, M_E=2, tmp_ndt_3=0, __retres1=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@7fad5622=0, T4_E=2, t4_st=0, t3_i=1, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@159daf8b=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@38354d63=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@4de0fa82=0, t5_pc=0, t7_st=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@58e9bbfb=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@2070b989=0, \result=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@323ca4f8=0, tmp_ndt_7=0, tmp___3=0, t1_i=1, __retres1=0, token=0, T7_E=2, tmp=1, t2_st=0, t4_i=1, t4_pc=0, E_5=2, \result=0, E_1=2, tmp_ndt_2=0, \result=0, __retres1=0, tmp_ndt_6=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@42de6072=0, tmp___0=0, tmp=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@c0285a8=0, t6_i=1, tmp___4=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@3b209689=0, \result=0, __retres1=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@24c147a0=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@1aa750ad=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@1bbd6e6f=0, \result=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@3bc6d4e4=0, tmp___0=0, t1_pc=0, E_4=2, T1_E=2, tmp_ndt_1=0, T5_E=2, t2_i=1, m_i=1, t1_st=0, tmp_ndt_5=0, local=0, __retres1=0, t2_pc=0, E_M=2, tmp___1=0, T3_E=2, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@45e31189=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@496276f0=0, \result=1, tmp___5=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@697b1765=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@6fa02d59=0} - StatisticsResult: NonterminationArgumentStatistics Fixpoint - NonterminatingLassoResult [Line: 638]: Nonterminating execution ----- class de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder.RCFGBacktranslator [?] ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; [?] havoc main_#res;havoc main_~__retres1~9;havoc main_~__retres1~9;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; [?] havoc start_simulation_#t~ret20, start_simulation_#t~ret21, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; [?] assume 1 == ~m_i~0;~m_st~0 := 0; [?] assume 1 == ~t1_i~0;~t1_st~0 := 0; [?] assume 1 == ~t2_i~0;~t2_st~0 := 0; [?] assume 1 == ~t3_i~0;~t3_st~0 := 0; [?] assume 1 == ~t4_i~0;~t4_st~0 := 0; [?] assume 1 == ~t5_i~0;~t5_st~0 := 0; [?] assume 1 == ~t6_i~0;~t6_st~0 := 0; [?] assume 1 == ~t7_i~0;~t7_st~0 := 0; [?] assume !(0 == ~M_E~0); [?] assume !(0 == ~T1_E~0); [?] assume !(0 == ~T2_E~0); [?] assume !(0 == ~T3_E~0); [?] assume !(0 == ~T4_E~0); [?] assume !(0 == ~T5_E~0); [?] assume !(0 == ~T6_E~0); [?] assume !(0 == ~T7_E~0); [?] assume !(0 == ~E_M~0); [?] assume !(0 == ~E_1~0); [?] assume !(0 == ~E_2~0); [?] assume !(0 == ~E_3~0); [?] assume !(0 == ~E_4~0); [?] assume !(0 == ~E_5~0); [?] assume !(0 == ~E_6~0); [?] assume !(0 == ~E_7~0); [?] havoc activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; [?] assume !(1 == ~m_pc~0); [?] is_master_triggered_~__retres1~0 := 0; [?] is_master_triggered_#res := is_master_triggered_~__retres1~0; [?] activate_threads_#t~ret11 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; [?] assume !(0 != activate_threads_~tmp~1); [?] havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; [?] assume !(1 == ~t1_pc~0); [?] is_transmit1_triggered_~__retres1~1 := 0; [?] is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; [?] activate_threads_#t~ret12 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; [?] assume !(0 != activate_threads_~tmp___0~0); [?] havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; [?] assume !(1 == ~t2_pc~0); [?] is_transmit2_triggered_~__retres1~2 := 0; [?] is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; [?] activate_threads_#t~ret13 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; [?] assume !(0 != activate_threads_~tmp___1~0); [?] havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; [?] assume !(1 == ~t3_pc~0); [?] is_transmit3_triggered_~__retres1~3 := 0; [?] is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; [?] activate_threads_#t~ret14 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; [?] assume !(0 != activate_threads_~tmp___2~0); [?] havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; [?] assume !(1 == ~t4_pc~0); [?] is_transmit4_triggered_~__retres1~4 := 0; [?] is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; [?] activate_threads_#t~ret15 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; [?] assume !(0 != activate_threads_~tmp___3~0); [?] havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; [?] assume !(1 == ~t5_pc~0); [?] is_transmit5_triggered_~__retres1~5 := 0; [?] is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; [?] activate_threads_#t~ret16 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; [?] assume !(0 != activate_threads_~tmp___4~0); [?] havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; [?] assume !(1 == ~t6_pc~0); [?] is_transmit6_triggered_~__retres1~6 := 0; [?] is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; [?] activate_threads_#t~ret17 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; [?] assume !(0 != activate_threads_~tmp___5~0); [?] havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; [?] assume !(1 == ~t7_pc~0); [?] is_transmit7_triggered_~__retres1~7 := 0; [?] is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; [?] activate_threads_#t~ret18 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; [?] assume !(0 != activate_threads_~tmp___6~0); [?] assume !(1 == ~M_E~0); [?] assume !(1 == ~T1_E~0); [?] assume !(1 == ~T2_E~0); [?] assume !(1 == ~T3_E~0); [?] assume !(1 == ~T4_E~0); [?] assume !(1 == ~T5_E~0); [?] assume !(1 == ~T6_E~0); [?] assume !(1 == ~T7_E~0); [?] assume !(1 == ~E_M~0); [?] assume !(1 == ~E_1~0); [?] assume !(1 == ~E_2~0); [?] assume !(1 == ~E_3~0); [?] assume !(1 == ~E_4~0); [?] assume !(1 == ~E_5~0); [?] assume !(1 == ~E_6~0); [?] assume !(1 == ~E_7~0); [?] assume !false; [?] start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret2, eval_#t~nondet3, eval_~tmp_ndt_1~0, eval_#t~nondet4, eval_~tmp_ndt_2~0, eval_#t~nondet5, eval_~tmp_ndt_3~0, eval_#t~nondet6, eval_~tmp_ndt_4~0, eval_#t~nondet7, eval_~tmp_ndt_5~0, eval_#t~nondet8, eval_~tmp_ndt_6~0, eval_#t~nondet9, eval_~tmp_ndt_7~0, eval_#t~nondet10, eval_~tmp_ndt_8~0, eval_~tmp~0;havoc eval_~tmp~0; [L14] ~m_pc~0 := 0; [L15] ~t1_pc~0 := 0; [L16] ~t2_pc~0 := 0; [L17] ~t3_pc~0 := 0; [L18] ~t4_pc~0 := 0; [L19] ~t5_pc~0 := 0; [L20] ~t6_pc~0 := 0; [L21] ~t7_pc~0 := 0; [L22] ~m_st~0 := 0; [L23] ~t1_st~0 := 0; [L24] ~t2_st~0 := 0; [L25] ~t3_st~0 := 0; [L26] ~t4_st~0 := 0; [L27] ~t5_st~0 := 0; [L28] ~t6_st~0 := 0; [L29] ~t7_st~0 := 0; [L30] ~m_i~0 := 0; [L31] ~t1_i~0 := 0; [L32] ~t2_i~0 := 0; [L33] ~t3_i~0 := 0; [L34] ~t4_i~0 := 0; [L35] ~t5_i~0 := 0; [L36] ~t6_i~0 := 0; [L37] ~t7_i~0 := 0; [L38] ~M_E~0 := 2; [L39] ~T1_E~0 := 2; [L40] ~T2_E~0 := 2; [L41] ~T3_E~0 := 2; [L42] ~T4_E~0 := 2; [L43] ~T5_E~0 := 2; [L44] ~T6_E~0 := 2; [L45] ~T7_E~0 := 2; [L46] ~E_M~0 := 2; [L47] ~E_1~0 := 2; [L48] ~E_2~0 := 2; [L49] ~E_3~0 := 2; [L50] ~E_4~0 := 2; [L51] ~E_5~0 := 2; [L52] ~E_6~0 := 2; [L53] ~E_7~0 := 2; [L63] ~token~0 := 0; [L65] ~local~0 := 0; [?] havoc main_#res; [?] havoc main_~__retres1~9; [L1225] havoc main_~__retres1~9; [L1134] ~m_i~0 := 1; [L1135] ~t1_i~0 := 1; [L1136] ~t2_i~0 := 1; [L1137] ~t3_i~0 := 1; [L1138] ~t4_i~0 := 1; [L1139] ~t5_i~0 := 1; [L1140] ~t6_i~0 := 1; [L1141] ~t7_i~0 := 1; [L1230] havoc start_simulation_#t~ret20, start_simulation_#t~ret21, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1; [L1166] havoc start_simulation_~kernel_st~0; [L1167] havoc start_simulation_~tmp~3; [L1168] havoc start_simulation_~tmp___0~1; [L1172] start_simulation_~kernel_st~0 := 0; [L538-L542] assume 1 == ~m_i~0; [L539] ~m_st~0 := 0; [L543-L547] assume 1 == ~t1_i~0; [L544] ~t1_st~0 := 0; [L548-L552] assume 1 == ~t2_i~0; [L549] ~t2_st~0 := 0; [L553-L557] assume 1 == ~t3_i~0; [L554] ~t3_st~0 := 0; [L558-L562] assume 1 == ~t4_i~0; [L559] ~t4_st~0 := 0; [L563-L567] assume 1 == ~t5_i~0; [L564] ~t5_st~0 := 0; [L568-L572] assume 1 == ~t6_i~0; [L569] ~t6_st~0 := 0; [L573-L577] assume 1 == ~t7_i~0; [L574] ~t7_st~0 := 0; [L771-L775] assume !(0 == ~M_E~0); [L776-L780] assume !(0 == ~T1_E~0); [L781-L785] assume !(0 == ~T2_E~0); [L786-L790] assume !(0 == ~T3_E~0); [L791-L795] assume !(0 == ~T4_E~0); [L796-L800] assume !(0 == ~T5_E~0); [L801-L805] assume !(0 == ~T6_E~0); [L806-L810] assume !(0 == ~T7_E~0); [L811-L815] assume !(0 == ~E_M~0); [L816-L820] assume !(0 == ~E_1~0); [L821-L825] assume !(0 == ~E_2~0); [L826-L830] assume !(0 == ~E_3~0); [L831-L835] assume !(0 == ~E_4~0); [L836-L840] assume !(0 == ~E_5~0); [L841-L845] assume !(0 == ~E_6~0); [L846-L850] assume !(0 == ~E_7~0); [L1176] havoc activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0; [L944] havoc activate_threads_~tmp~1; [L945] havoc activate_threads_~tmp___0~0; [L946] havoc activate_threads_~tmp___1~0; [L947] havoc activate_threads_~tmp___2~0; [L948] havoc activate_threads_~tmp___3~0; [L949] havoc activate_threads_~tmp___4~0; [L950] havoc activate_threads_~tmp___5~0; [L951] havoc activate_threads_~tmp___6~0; [L955] havoc is_master_triggered_#res; [L955] havoc is_master_triggered_~__retres1~0; [L375] havoc is_master_triggered_~__retres1~0; [L378-L387] assume !(1 == ~m_pc~0); [L388] is_master_triggered_~__retres1~0 := 0; [L390] is_master_triggered_#res := is_master_triggered_~__retres1~0; [L955] activate_threads_#t~ret11 := is_master_triggered_#res; [L955] activate_threads_~tmp~1 := activate_threads_#t~ret11; [L955] havoc activate_threads_#t~ret11; [L957-L961] assume !(0 != activate_threads_~tmp~1); [L963] havoc is_transmit1_triggered_#res; [L963] havoc is_transmit1_triggered_~__retres1~1; [L394] havoc is_transmit1_triggered_~__retres1~1; [L397-L406] assume !(1 == ~t1_pc~0); [L407] is_transmit1_triggered_~__retres1~1 := 0; [L409] is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; [L963] activate_threads_#t~ret12 := is_transmit1_triggered_#res; [L963] activate_threads_~tmp___0~0 := activate_threads_#t~ret12; [L963] havoc activate_threads_#t~ret12; [L965-L969] assume !(0 != activate_threads_~tmp___0~0); [L971] havoc is_transmit2_triggered_#res; [L971] havoc is_transmit2_triggered_~__retres1~2; [L413] havoc is_transmit2_triggered_~__retres1~2; [L416-L425] assume !(1 == ~t2_pc~0); [L426] is_transmit2_triggered_~__retres1~2 := 0; [L428] is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; [L971] activate_threads_#t~ret13 := is_transmit2_triggered_#res; [L971] activate_threads_~tmp___1~0 := activate_threads_#t~ret13; [L971] havoc activate_threads_#t~ret13; [L973-L977] assume !(0 != activate_threads_~tmp___1~0); [L979] havoc is_transmit3_triggered_#res; [L979] havoc is_transmit3_triggered_~__retres1~3; [L432] havoc is_transmit3_triggered_~__retres1~3; [L435-L444] assume !(1 == ~t3_pc~0); [L445] is_transmit3_triggered_~__retres1~3 := 0; [L447] is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; [L979] activate_threads_#t~ret14 := is_transmit3_triggered_#res; [L979] activate_threads_~tmp___2~0 := activate_threads_#t~ret14; [L979] havoc activate_threads_#t~ret14; [L981-L985] assume !(0 != activate_threads_~tmp___2~0); [L987] havoc is_transmit4_triggered_#res; [L987] havoc is_transmit4_triggered_~__retres1~4; [L451] havoc is_transmit4_triggered_~__retres1~4; [L454-L463] assume !(1 == ~t4_pc~0); [L464] is_transmit4_triggered_~__retres1~4 := 0; [L466] is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; [L987] activate_threads_#t~ret15 := is_transmit4_triggered_#res; [L987] activate_threads_~tmp___3~0 := activate_threads_#t~ret15; [L987] havoc activate_threads_#t~ret15; [L989-L993] assume !(0 != activate_threads_~tmp___3~0); [L995] havoc is_transmit5_triggered_#res; [L995] havoc is_transmit5_triggered_~__retres1~5; [L470] havoc is_transmit5_triggered_~__retres1~5; [L473-L482] assume !(1 == ~t5_pc~0); [L483] is_transmit5_triggered_~__retres1~5 := 0; [L485] is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; [L995] activate_threads_#t~ret16 := is_transmit5_triggered_#res; [L995] activate_threads_~tmp___4~0 := activate_threads_#t~ret16; [L995] havoc activate_threads_#t~ret16; [L997-L1001] assume !(0 != activate_threads_~tmp___4~0); [L1003] havoc is_transmit6_triggered_#res; [L1003] havoc is_transmit6_triggered_~__retres1~6; [L489] havoc is_transmit6_triggered_~__retres1~6; [L492-L501] assume !(1 == ~t6_pc~0); [L502] is_transmit6_triggered_~__retres1~6 := 0; [L504] is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; [L1003] activate_threads_#t~ret17 := is_transmit6_triggered_#res; [L1003] activate_threads_~tmp___5~0 := activate_threads_#t~ret17; [L1003] havoc activate_threads_#t~ret17; [L1005-L1009] assume !(0 != activate_threads_~tmp___5~0); [L1011] havoc is_transmit7_triggered_#res; [L1011] havoc is_transmit7_triggered_~__retres1~7; [L508] havoc is_transmit7_triggered_~__retres1~7; [L511-L520] assume !(1 == ~t7_pc~0); [L521] is_transmit7_triggered_~__retres1~7 := 0; [L523] is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; [L1011] activate_threads_#t~ret18 := is_transmit7_triggered_#res; [L1011] activate_threads_~tmp___6~0 := activate_threads_#t~ret18; [L1011] havoc activate_threads_#t~ret18; [L1013-L1017] assume !(0 != activate_threads_~tmp___6~0); [L859-L863] assume !(1 == ~M_E~0); [L864-L868] assume !(1 == ~T1_E~0); [L869-L873] assume !(1 == ~T2_E~0); [L874-L878] assume !(1 == ~T3_E~0); [L879-L883] assume !(1 == ~T4_E~0); [L884-L888] assume !(1 == ~T5_E~0); [L889-L893] assume !(1 == ~T6_E~0); [L894-L898] assume !(1 == ~T7_E~0); [L899-L903] assume !(1 == ~E_M~0); [L904-L908] assume !(1 == ~E_1~0); [L909-L913] assume !(1 == ~E_2~0); [L914-L918] assume !(1 == ~E_3~0); [L919-L923] assume !(1 == ~E_4~0); [L924-L928] assume !(1 == ~E_5~0); [L929-L933] assume !(1 == ~E_6~0); [L934-L938] assume !(1 == ~E_7~0); [L1180-L1217] assume !false; [L1183] start_simulation_~kernel_st~0 := 1; [L1184] havoc eval_#t~ret2, eval_#t~nondet3, eval_~tmp_ndt_1~0, eval_#t~nondet4, eval_~tmp_ndt_2~0, eval_#t~nondet5, eval_~tmp_ndt_3~0, eval_#t~nondet6, eval_~tmp_ndt_4~0, eval_#t~nondet7, eval_~tmp_ndt_5~0, eval_#t~nondet8, eval_~tmp_ndt_6~0, eval_#t~nondet9, eval_~tmp_ndt_7~0, eval_#t~nondet10, eval_~tmp_ndt_8~0, eval_~tmp~0; [L634] havoc eval_~tmp~0; ----- ----- class de.uni_freiburg.informatik.ultimate.boogie.preprocessor.BoogiePreprocessorBacktranslator [L14] ~m_pc~0 := 0; [L15] ~t1_pc~0 := 0; [L16] ~t2_pc~0 := 0; [L17] ~t3_pc~0 := 0; [L18] ~t4_pc~0 := 0; [L19] ~t5_pc~0 := 0; [L20] ~t6_pc~0 := 0; [L21] ~t7_pc~0 := 0; [L22] ~m_st~0 := 0; [L23] ~t1_st~0 := 0; [L24] ~t2_st~0 := 0; [L25] ~t3_st~0 := 0; [L26] ~t4_st~0 := 0; [L27] ~t5_st~0 := 0; [L28] ~t6_st~0 := 0; [L29] ~t7_st~0 := 0; [L30] ~m_i~0 := 0; [L31] ~t1_i~0 := 0; [L32] ~t2_i~0 := 0; [L33] ~t3_i~0 := 0; [L34] ~t4_i~0 := 0; [L35] ~t5_i~0 := 0; [L36] ~t6_i~0 := 0; [L37] ~t7_i~0 := 0; [L38] ~M_E~0 := 2; [L39] ~T1_E~0 := 2; [L40] ~T2_E~0 := 2; [L41] ~T3_E~0 := 2; [L42] ~T4_E~0 := 2; [L43] ~T5_E~0 := 2; [L44] ~T6_E~0 := 2; [L45] ~T7_E~0 := 2; [L46] ~E_M~0 := 2; [L47] ~E_1~0 := 2; [L48] ~E_2~0 := 2; [L49] ~E_3~0 := 2; [L50] ~E_4~0 := 2; [L51] ~E_5~0 := 2; [L52] ~E_6~0 := 2; [L53] ~E_7~0 := 2; [L63] ~token~0 := 0; [L65] ~local~0 := 0; [?] havoc main_#res; [?] havoc main_~__retres1~9; [L1225] havoc main_~__retres1~9; [L1134] ~m_i~0 := 1; [L1135] ~t1_i~0 := 1; [L1136] ~t2_i~0 := 1; [L1137] ~t3_i~0 := 1; [L1138] ~t4_i~0 := 1; [L1139] ~t5_i~0 := 1; [L1140] ~t6_i~0 := 1; [L1141] ~t7_i~0 := 1; [L1230] havoc start_simulation_#t~ret20, start_simulation_#t~ret21, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1; [L1166] havoc start_simulation_~kernel_st~0; [L1167] havoc start_simulation_~tmp~3; [L1168] havoc start_simulation_~tmp___0~1; [L1172] start_simulation_~kernel_st~0 := 0; [L538-L542] assume 1 == ~m_i~0; [L539] ~m_st~0 := 0; [L543-L547] assume 1 == ~t1_i~0; [L544] ~t1_st~0 := 0; [L548-L552] assume 1 == ~t2_i~0; [L549] ~t2_st~0 := 0; [L553-L557] assume 1 == ~t3_i~0; [L554] ~t3_st~0 := 0; [L558-L562] assume 1 == ~t4_i~0; [L559] ~t4_st~0 := 0; [L563-L567] assume 1 == ~t5_i~0; [L564] ~t5_st~0 := 0; [L568-L572] assume 1 == ~t6_i~0; [L569] ~t6_st~0 := 0; [L573-L577] assume 1 == ~t7_i~0; [L574] ~t7_st~0 := 0; [L771-L775] assume !(0 == ~M_E~0); [L776-L780] assume !(0 == ~T1_E~0); [L781-L785] assume !(0 == ~T2_E~0); [L786-L790] assume !(0 == ~T3_E~0); [L791-L795] assume !(0 == ~T4_E~0); [L796-L800] assume !(0 == ~T5_E~0); [L801-L805] assume !(0 == ~T6_E~0); [L806-L810] assume !(0 == ~T7_E~0); [L811-L815] assume !(0 == ~E_M~0); [L816-L820] assume !(0 == ~E_1~0); [L821-L825] assume !(0 == ~E_2~0); [L826-L830] assume !(0 == ~E_3~0); [L831-L835] assume !(0 == ~E_4~0); [L836-L840] assume !(0 == ~E_5~0); [L841-L845] assume !(0 == ~E_6~0); [L846-L850] assume !(0 == ~E_7~0); [L1176] havoc activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0; [L944] havoc activate_threads_~tmp~1; [L945] havoc activate_threads_~tmp___0~0; [L946] havoc activate_threads_~tmp___1~0; [L947] havoc activate_threads_~tmp___2~0; [L948] havoc activate_threads_~tmp___3~0; [L949] havoc activate_threads_~tmp___4~0; [L950] havoc activate_threads_~tmp___5~0; [L951] havoc activate_threads_~tmp___6~0; [L955] havoc is_master_triggered_#res; [L955] havoc is_master_triggered_~__retres1~0; [L375] havoc is_master_triggered_~__retres1~0; [L378-L387] assume !(1 == ~m_pc~0); [L388] is_master_triggered_~__retres1~0 := 0; [L390] is_master_triggered_#res := is_master_triggered_~__retres1~0; [L955] activate_threads_#t~ret11 := is_master_triggered_#res; [L955] activate_threads_~tmp~1 := activate_threads_#t~ret11; [L955] havoc activate_threads_#t~ret11; [L957-L961] assume !(0 != activate_threads_~tmp~1); [L963] havoc is_transmit1_triggered_#res; [L963] havoc is_transmit1_triggered_~__retres1~1; [L394] havoc is_transmit1_triggered_~__retres1~1; [L397-L406] assume !(1 == ~t1_pc~0); [L407] is_transmit1_triggered_~__retres1~1 := 0; [L409] is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; [L963] activate_threads_#t~ret12 := is_transmit1_triggered_#res; [L963] activate_threads_~tmp___0~0 := activate_threads_#t~ret12; [L963] havoc activate_threads_#t~ret12; [L965-L969] assume !(0 != activate_threads_~tmp___0~0); [L971] havoc is_transmit2_triggered_#res; [L971] havoc is_transmit2_triggered_~__retres1~2; [L413] havoc is_transmit2_triggered_~__retres1~2; [L416-L425] assume !(1 == ~t2_pc~0); [L426] is_transmit2_triggered_~__retres1~2 := 0; [L428] is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; [L971] activate_threads_#t~ret13 := is_transmit2_triggered_#res; [L971] activate_threads_~tmp___1~0 := activate_threads_#t~ret13; [L971] havoc activate_threads_#t~ret13; [L973-L977] assume !(0 != activate_threads_~tmp___1~0); [L979] havoc is_transmit3_triggered_#res; [L979] havoc is_transmit3_triggered_~__retres1~3; [L432] havoc is_transmit3_triggered_~__retres1~3; [L435-L444] assume !(1 == ~t3_pc~0); [L445] is_transmit3_triggered_~__retres1~3 := 0; [L447] is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; [L979] activate_threads_#t~ret14 := is_transmit3_triggered_#res; [L979] activate_threads_~tmp___2~0 := activate_threads_#t~ret14; [L979] havoc activate_threads_#t~ret14; [L981-L985] assume !(0 != activate_threads_~tmp___2~0); [L987] havoc is_transmit4_triggered_#res; [L987] havoc is_transmit4_triggered_~__retres1~4; [L451] havoc is_transmit4_triggered_~__retres1~4; [L454-L463] assume !(1 == ~t4_pc~0); [L464] is_transmit4_triggered_~__retres1~4 := 0; [L466] is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; [L987] activate_threads_#t~ret15 := is_transmit4_triggered_#res; [L987] activate_threads_~tmp___3~0 := activate_threads_#t~ret15; [L987] havoc activate_threads_#t~ret15; [L989-L993] assume !(0 != activate_threads_~tmp___3~0); [L995] havoc is_transmit5_triggered_#res; [L995] havoc is_transmit5_triggered_~__retres1~5; [L470] havoc is_transmit5_triggered_~__retres1~5; [L473-L482] assume !(1 == ~t5_pc~0); [L483] is_transmit5_triggered_~__retres1~5 := 0; [L485] is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; [L995] activate_threads_#t~ret16 := is_transmit5_triggered_#res; [L995] activate_threads_~tmp___4~0 := activate_threads_#t~ret16; [L995] havoc activate_threads_#t~ret16; [L997-L1001] assume !(0 != activate_threads_~tmp___4~0); [L1003] havoc is_transmit6_triggered_#res; [L1003] havoc is_transmit6_triggered_~__retres1~6; [L489] havoc is_transmit6_triggered_~__retres1~6; [L492-L501] assume !(1 == ~t6_pc~0); [L502] is_transmit6_triggered_~__retres1~6 := 0; [L504] is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; [L1003] activate_threads_#t~ret17 := is_transmit6_triggered_#res; [L1003] activate_threads_~tmp___5~0 := activate_threads_#t~ret17; [L1003] havoc activate_threads_#t~ret17; [L1005-L1009] assume !(0 != activate_threads_~tmp___5~0); [L1011] havoc is_transmit7_triggered_#res; [L1011] havoc is_transmit7_triggered_~__retres1~7; [L508] havoc is_transmit7_triggered_~__retres1~7; [L511-L520] assume !(1 == ~t7_pc~0); [L521] is_transmit7_triggered_~__retres1~7 := 0; [L523] is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; [L1011] activate_threads_#t~ret18 := is_transmit7_triggered_#res; [L1011] activate_threads_~tmp___6~0 := activate_threads_#t~ret18; [L1011] havoc activate_threads_#t~ret18; [L1013-L1017] assume !(0 != activate_threads_~tmp___6~0); [L859-L863] assume !(1 == ~M_E~0); [L864-L868] assume !(1 == ~T1_E~0); [L869-L873] assume !(1 == ~T2_E~0); [L874-L878] assume !(1 == ~T3_E~0); [L879-L883] assume !(1 == ~T4_E~0); [L884-L888] assume !(1 == ~T5_E~0); [L889-L893] assume !(1 == ~T6_E~0); [L894-L898] assume !(1 == ~T7_E~0); [L899-L903] assume !(1 == ~E_M~0); [L904-L908] assume !(1 == ~E_1~0); [L909-L913] assume !(1 == ~E_2~0); [L914-L918] assume !(1 == ~E_3~0); [L919-L923] assume !(1 == ~E_4~0); [L924-L928] assume !(1 == ~E_5~0); [L929-L933] assume !(1 == ~E_6~0); [L934-L938] assume !(1 == ~E_7~0); [L1180-L1217] assume !false; [L1183] start_simulation_~kernel_st~0 := 1; [L1184] havoc eval_#t~ret2, eval_#t~nondet3, eval_~tmp_ndt_1~0, eval_#t~nondet4, eval_~tmp_ndt_2~0, eval_#t~nondet5, eval_~tmp_ndt_3~0, eval_#t~nondet6, eval_~tmp_ndt_4~0, eval_#t~nondet7, eval_~tmp_ndt_5~0, eval_#t~nondet8, eval_~tmp_ndt_6~0, eval_#t~nondet9, eval_~tmp_ndt_7~0, eval_#t~nondet10, eval_~tmp_ndt_8~0, eval_~tmp~0; [L634] havoc eval_~tmp~0; [L14] ~m_pc~0 := 0; [L15] ~t1_pc~0 := 0; [L16] ~t2_pc~0 := 0; [L17] ~t3_pc~0 := 0; [L18] ~t4_pc~0 := 0; [L19] ~t5_pc~0 := 0; [L20] ~t6_pc~0 := 0; [L21] ~t7_pc~0 := 0; [L22] ~m_st~0 := 0; [L23] ~t1_st~0 := 0; [L24] ~t2_st~0 := 0; [L25] ~t3_st~0 := 0; [L26] ~t4_st~0 := 0; [L27] ~t5_st~0 := 0; [L28] ~t6_st~0 := 0; [L29] ~t7_st~0 := 0; [L30] ~m_i~0 := 0; [L31] ~t1_i~0 := 0; [L32] ~t2_i~0 := 0; [L33] ~t3_i~0 := 0; [L34] ~t4_i~0 := 0; [L35] ~t5_i~0 := 0; [L36] ~t6_i~0 := 0; [L37] ~t7_i~0 := 0; [L38] ~M_E~0 := 2; [L39] ~T1_E~0 := 2; [L40] ~T2_E~0 := 2; [L41] ~T3_E~0 := 2; [L42] ~T4_E~0 := 2; [L43] ~T5_E~0 := 2; [L44] ~T6_E~0 := 2; [L45] ~T7_E~0 := 2; [L46] ~E_M~0 := 2; [L47] ~E_1~0 := 2; [L48] ~E_2~0 := 2; [L49] ~E_3~0 := 2; [L50] ~E_4~0 := 2; [L51] ~E_5~0 := 2; [L52] ~E_6~0 := 2; [L53] ~E_7~0 := 2; [L63] ~token~0 := 0; [L65] ~local~0 := 0; [?] havoc main_#res; [?] havoc main_~__retres1~9; [L1225] havoc main_~__retres1~9; [L1134] ~m_i~0 := 1; [L1135] ~t1_i~0 := 1; [L1136] ~t2_i~0 := 1; [L1137] ~t3_i~0 := 1; [L1138] ~t4_i~0 := 1; [L1139] ~t5_i~0 := 1; [L1140] ~t6_i~0 := 1; [L1141] ~t7_i~0 := 1; [L1230] havoc start_simulation_#t~ret20, start_simulation_#t~ret21, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1; [L1166] havoc start_simulation_~kernel_st~0; [L1167] havoc start_simulation_~tmp~3; [L1168] havoc start_simulation_~tmp___0~1; [L1172] start_simulation_~kernel_st~0 := 0; [L538] COND TRUE 1 == ~m_i~0 [L539] ~m_st~0 := 0; [L543] COND TRUE 1 == ~t1_i~0 [L544] ~t1_st~0 := 0; [L548] COND TRUE 1 == ~t2_i~0 [L549] ~t2_st~0 := 0; [L553] COND TRUE 1 == ~t3_i~0 [L554] ~t3_st~0 := 0; [L558] COND TRUE 1 == ~t4_i~0 [L559] ~t4_st~0 := 0; [L563] COND TRUE 1 == ~t5_i~0 [L564] ~t5_st~0 := 0; [L568] COND TRUE 1 == ~t6_i~0 [L569] ~t6_st~0 := 0; [L573] COND TRUE 1 == ~t7_i~0 [L574] ~t7_st~0 := 0; [L771] COND FALSE !(0 == ~M_E~0) [L776] COND FALSE !(0 == ~T1_E~0) [L781] COND FALSE !(0 == ~T2_E~0) [L786] COND FALSE !(0 == ~T3_E~0) [L791] COND FALSE !(0 == ~T4_E~0) [L796] COND FALSE !(0 == ~T5_E~0) [L801] COND FALSE !(0 == ~T6_E~0) [L806] COND FALSE !(0 == ~T7_E~0) [L811] COND FALSE !(0 == ~E_M~0) [L816] COND FALSE !(0 == ~E_1~0) [L821] COND FALSE !(0 == ~E_2~0) [L826] COND FALSE !(0 == ~E_3~0) [L831] COND FALSE !(0 == ~E_4~0) [L836] COND FALSE !(0 == ~E_5~0) [L841] COND FALSE !(0 == ~E_6~0) [L846] COND FALSE !(0 == ~E_7~0) [L1176] havoc activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0; [L944] havoc activate_threads_~tmp~1; [L945] havoc activate_threads_~tmp___0~0; [L946] havoc activate_threads_~tmp___1~0; [L947] havoc activate_threads_~tmp___2~0; [L948] havoc activate_threads_~tmp___3~0; [L949] havoc activate_threads_~tmp___4~0; [L950] havoc activate_threads_~tmp___5~0; [L951] havoc activate_threads_~tmp___6~0; [L955] havoc is_master_triggered_#res; [L955] havoc is_master_triggered_~__retres1~0; [L375] havoc is_master_triggered_~__retres1~0; [L378] COND FALSE !(1 == ~m_pc~0) [L388] is_master_triggered_~__retres1~0 := 0; [L390] is_master_triggered_#res := is_master_triggered_~__retres1~0; [L955] activate_threads_#t~ret11 := is_master_triggered_#res; [L955] activate_threads_~tmp~1 := activate_threads_#t~ret11; [L955] havoc activate_threads_#t~ret11; [L957-L961] COND FALSE !(0 != activate_threads_~tmp~1) [L963] havoc is_transmit1_triggered_#res; [L963] havoc is_transmit1_triggered_~__retres1~1; [L394] havoc is_transmit1_triggered_~__retres1~1; [L397] COND FALSE !(1 == ~t1_pc~0) [L407] is_transmit1_triggered_~__retres1~1 := 0; [L409] is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; [L963] activate_threads_#t~ret12 := is_transmit1_triggered_#res; [L963] activate_threads_~tmp___0~0 := activate_threads_#t~ret12; [L963] havoc activate_threads_#t~ret12; [L965-L969] COND FALSE !(0 != activate_threads_~tmp___0~0) [L971] havoc is_transmit2_triggered_#res; [L971] havoc is_transmit2_triggered_~__retres1~2; [L413] havoc is_transmit2_triggered_~__retres1~2; [L416] COND FALSE !(1 == ~t2_pc~0) [L426] is_transmit2_triggered_~__retres1~2 := 0; [L428] is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; [L971] activate_threads_#t~ret13 := is_transmit2_triggered_#res; [L971] activate_threads_~tmp___1~0 := activate_threads_#t~ret13; [L971] havoc activate_threads_#t~ret13; [L973-L977] COND FALSE !(0 != activate_threads_~tmp___1~0) [L979] havoc is_transmit3_triggered_#res; [L979] havoc is_transmit3_triggered_~__retres1~3; [L432] havoc is_transmit3_triggered_~__retres1~3; [L435] COND FALSE !(1 == ~t3_pc~0) [L445] is_transmit3_triggered_~__retres1~3 := 0; [L447] is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; [L979] activate_threads_#t~ret14 := is_transmit3_triggered_#res; [L979] activate_threads_~tmp___2~0 := activate_threads_#t~ret14; [L979] havoc activate_threads_#t~ret14; [L981-L985] COND FALSE !(0 != activate_threads_~tmp___2~0) [L987] havoc is_transmit4_triggered_#res; [L987] havoc is_transmit4_triggered_~__retres1~4; [L451] havoc is_transmit4_triggered_~__retres1~4; [L454] COND FALSE !(1 == ~t4_pc~0) [L464] is_transmit4_triggered_~__retres1~4 := 0; [L466] is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; [L987] activate_threads_#t~ret15 := is_transmit4_triggered_#res; [L987] activate_threads_~tmp___3~0 := activate_threads_#t~ret15; [L987] havoc activate_threads_#t~ret15; [L989-L993] COND FALSE !(0 != activate_threads_~tmp___3~0) [L995] havoc is_transmit5_triggered_#res; [L995] havoc is_transmit5_triggered_~__retres1~5; [L470] havoc is_transmit5_triggered_~__retres1~5; [L473] COND FALSE !(1 == ~t5_pc~0) [L483] is_transmit5_triggered_~__retres1~5 := 0; [L485] is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; [L995] activate_threads_#t~ret16 := is_transmit5_triggered_#res; [L995] activate_threads_~tmp___4~0 := activate_threads_#t~ret16; [L995] havoc activate_threads_#t~ret16; [L997-L1001] COND FALSE !(0 != activate_threads_~tmp___4~0) [L1003] havoc is_transmit6_triggered_#res; [L1003] havoc is_transmit6_triggered_~__retres1~6; [L489] havoc is_transmit6_triggered_~__retres1~6; [L492] COND FALSE !(1 == ~t6_pc~0) [L502] is_transmit6_triggered_~__retres1~6 := 0; [L504] is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; [L1003] activate_threads_#t~ret17 := is_transmit6_triggered_#res; [L1003] activate_threads_~tmp___5~0 := activate_threads_#t~ret17; [L1003] havoc activate_threads_#t~ret17; [L1005-L1009] COND FALSE !(0 != activate_threads_~tmp___5~0) [L1011] havoc is_transmit7_triggered_#res; [L1011] havoc is_transmit7_triggered_~__retres1~7; [L508] havoc is_transmit7_triggered_~__retres1~7; [L511] COND FALSE !(1 == ~t7_pc~0) [L521] is_transmit7_triggered_~__retres1~7 := 0; [L523] is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; [L1011] activate_threads_#t~ret18 := is_transmit7_triggered_#res; [L1011] activate_threads_~tmp___6~0 := activate_threads_#t~ret18; [L1011] havoc activate_threads_#t~ret18; [L1013-L1017] COND FALSE !(0 != activate_threads_~tmp___6~0) [L859] COND FALSE !(1 == ~M_E~0) [L864] COND FALSE !(1 == ~T1_E~0) [L869] COND FALSE !(1 == ~T2_E~0) [L874] COND FALSE !(1 == ~T3_E~0) [L879] COND FALSE !(1 == ~T4_E~0) [L884] COND FALSE !(1 == ~T5_E~0) [L889] COND FALSE !(1 == ~T6_E~0) [L894] COND FALSE !(1 == ~T7_E~0) [L899] COND FALSE !(1 == ~E_M~0) [L904] COND FALSE !(1 == ~E_1~0) [L909] COND FALSE !(1 == ~E_2~0) [L914] COND FALSE !(1 == ~E_3~0) [L919] COND FALSE !(1 == ~E_4~0) [L924] COND FALSE !(1 == ~E_5~0) [L929] COND FALSE !(1 == ~E_6~0) [L934] COND FALSE !(1 == ~E_7~0) [L1180-L1217] COND FALSE !(false) [L1183] start_simulation_~kernel_st~0 := 1; [L1184] havoc eval_#t~ret2, eval_#t~nondet3, eval_~tmp_ndt_1~0, eval_#t~nondet4, eval_~tmp_ndt_2~0, eval_#t~nondet5, eval_~tmp_ndt_3~0, eval_#t~nondet6, eval_~tmp_ndt_4~0, eval_#t~nondet7, eval_~tmp_ndt_5~0, eval_#t~nondet8, eval_~tmp_ndt_6~0, eval_#t~nondet9, eval_~tmp_ndt_7~0, eval_#t~nondet10, eval_~tmp_ndt_8~0, eval_~tmp~0; [L634] havoc eval_~tmp~0; ----- ----- class de.uni_freiburg.informatik.ultimate.boogie.procedureinliner.backtranslation.InlinerBacktranslator [L14] ~m_pc~0 := 0; [L15] ~t1_pc~0 := 0; [L16] ~t2_pc~0 := 0; [L17] ~t3_pc~0 := 0; [L18] ~t4_pc~0 := 0; [L19] ~t5_pc~0 := 0; [L20] ~t6_pc~0 := 0; [L21] ~t7_pc~0 := 0; [L22] ~m_st~0 := 0; [L23] ~t1_st~0 := 0; [L24] ~t2_st~0 := 0; [L25] ~t3_st~0 := 0; [L26] ~t4_st~0 := 0; [L27] ~t5_st~0 := 0; [L28] ~t6_st~0 := 0; [L29] ~t7_st~0 := 0; [L30] ~m_i~0 := 0; [L31] ~t1_i~0 := 0; [L32] ~t2_i~0 := 0; [L33] ~t3_i~0 := 0; [L34] ~t4_i~0 := 0; [L35] ~t5_i~0 := 0; [L36] ~t6_i~0 := 0; [L37] ~t7_i~0 := 0; [L38] ~M_E~0 := 2; [L39] ~T1_E~0 := 2; [L40] ~T2_E~0 := 2; [L41] ~T3_E~0 := 2; [L42] ~T4_E~0 := 2; [L43] ~T5_E~0 := 2; [L44] ~T6_E~0 := 2; [L45] ~T7_E~0 := 2; [L46] ~E_M~0 := 2; [L47] ~E_1~0 := 2; [L48] ~E_2~0 := 2; [L49] ~E_3~0 := 2; [L50] ~E_4~0 := 2; [L51] ~E_5~0 := 2; [L52] ~E_6~0 := 2; [L53] ~E_7~0 := 2; [L63] ~token~0 := 0; [L65] ~local~0 := 0; [?] havoc main_#res; [?] havoc main_~__retres1~9; [L1225] havoc main_~__retres1~9; [L1134] ~m_i~0 := 1; [L1135] ~t1_i~0 := 1; [L1136] ~t2_i~0 := 1; [L1137] ~t3_i~0 := 1; [L1138] ~t4_i~0 := 1; [L1139] ~t5_i~0 := 1; [L1140] ~t6_i~0 := 1; [L1141] ~t7_i~0 := 1; [L1230] havoc start_simulation_#t~ret20, start_simulation_#t~ret21, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1; [L1166] havoc start_simulation_~kernel_st~0; [L1167] havoc start_simulation_~tmp~3; [L1168] havoc start_simulation_~tmp___0~1; [L1172] start_simulation_~kernel_st~0 := 0; [L538] COND TRUE 1 == ~m_i~0 [L539] ~m_st~0 := 0; [L543] COND TRUE 1 == ~t1_i~0 [L544] ~t1_st~0 := 0; [L548] COND TRUE 1 == ~t2_i~0 [L549] ~t2_st~0 := 0; [L553] COND TRUE 1 == ~t3_i~0 [L554] ~t3_st~0 := 0; [L558] COND TRUE 1 == ~t4_i~0 [L559] ~t4_st~0 := 0; [L563] COND TRUE 1 == ~t5_i~0 [L564] ~t5_st~0 := 0; [L568] COND TRUE 1 == ~t6_i~0 [L569] ~t6_st~0 := 0; [L573] COND TRUE 1 == ~t7_i~0 [L574] ~t7_st~0 := 0; [L771] COND FALSE !(0 == ~M_E~0) [L776] COND FALSE !(0 == ~T1_E~0) [L781] COND FALSE !(0 == ~T2_E~0) [L786] COND FALSE !(0 == ~T3_E~0) [L791] COND FALSE !(0 == ~T4_E~0) [L796] COND FALSE !(0 == ~T5_E~0) [L801] COND FALSE !(0 == ~T6_E~0) [L806] COND FALSE !(0 == ~T7_E~0) [L811] COND FALSE !(0 == ~E_M~0) [L816] COND FALSE !(0 == ~E_1~0) [L821] COND FALSE !(0 == ~E_2~0) [L826] COND FALSE !(0 == ~E_3~0) [L831] COND FALSE !(0 == ~E_4~0) [L836] COND FALSE !(0 == ~E_5~0) [L841] COND FALSE !(0 == ~E_6~0) [L846] COND FALSE !(0 == ~E_7~0) [L1176] havoc activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0; [L944] havoc activate_threads_~tmp~1; [L945] havoc activate_threads_~tmp___0~0; [L946] havoc activate_threads_~tmp___1~0; [L947] havoc activate_threads_~tmp___2~0; [L948] havoc activate_threads_~tmp___3~0; [L949] havoc activate_threads_~tmp___4~0; [L950] havoc activate_threads_~tmp___5~0; [L951] havoc activate_threads_~tmp___6~0; [L955] havoc is_master_triggered_#res; [L955] havoc is_master_triggered_~__retres1~0; [L375] havoc is_master_triggered_~__retres1~0; [L378] COND FALSE !(1 == ~m_pc~0) [L388] is_master_triggered_~__retres1~0 := 0; [L390] is_master_triggered_#res := is_master_triggered_~__retres1~0; [L955] activate_threads_#t~ret11 := is_master_triggered_#res; [L955] activate_threads_~tmp~1 := activate_threads_#t~ret11; [L955] havoc activate_threads_#t~ret11; [L957-L961] COND FALSE !(0 != activate_threads_~tmp~1) [L963] havoc is_transmit1_triggered_#res; [L963] havoc is_transmit1_triggered_~__retres1~1; [L394] havoc is_transmit1_triggered_~__retres1~1; [L397] COND FALSE !(1 == ~t1_pc~0) [L407] is_transmit1_triggered_~__retres1~1 := 0; [L409] is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; [L963] activate_threads_#t~ret12 := is_transmit1_triggered_#res; [L963] activate_threads_~tmp___0~0 := activate_threads_#t~ret12; [L963] havoc activate_threads_#t~ret12; [L965-L969] COND FALSE !(0 != activate_threads_~tmp___0~0) [L971] havoc is_transmit2_triggered_#res; [L971] havoc is_transmit2_triggered_~__retres1~2; [L413] havoc is_transmit2_triggered_~__retres1~2; [L416] COND FALSE !(1 == ~t2_pc~0) [L426] is_transmit2_triggered_~__retres1~2 := 0; [L428] is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; [L971] activate_threads_#t~ret13 := is_transmit2_triggered_#res; [L971] activate_threads_~tmp___1~0 := activate_threads_#t~ret13; [L971] havoc activate_threads_#t~ret13; [L973-L977] COND FALSE !(0 != activate_threads_~tmp___1~0) [L979] havoc is_transmit3_triggered_#res; [L979] havoc is_transmit3_triggered_~__retres1~3; [L432] havoc is_transmit3_triggered_~__retres1~3; [L435] COND FALSE !(1 == ~t3_pc~0) [L445] is_transmit3_triggered_~__retres1~3 := 0; [L447] is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; [L979] activate_threads_#t~ret14 := is_transmit3_triggered_#res; [L979] activate_threads_~tmp___2~0 := activate_threads_#t~ret14; [L979] havoc activate_threads_#t~ret14; [L981-L985] COND FALSE !(0 != activate_threads_~tmp___2~0) [L987] havoc is_transmit4_triggered_#res; [L987] havoc is_transmit4_triggered_~__retres1~4; [L451] havoc is_transmit4_triggered_~__retres1~4; [L454] COND FALSE !(1 == ~t4_pc~0) [L464] is_transmit4_triggered_~__retres1~4 := 0; [L466] is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; [L987] activate_threads_#t~ret15 := is_transmit4_triggered_#res; [L987] activate_threads_~tmp___3~0 := activate_threads_#t~ret15; [L987] havoc activate_threads_#t~ret15; [L989-L993] COND FALSE !(0 != activate_threads_~tmp___3~0) [L995] havoc is_transmit5_triggered_#res; [L995] havoc is_transmit5_triggered_~__retres1~5; [L470] havoc is_transmit5_triggered_~__retres1~5; [L473] COND FALSE !(1 == ~t5_pc~0) [L483] is_transmit5_triggered_~__retres1~5 := 0; [L485] is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; [L995] activate_threads_#t~ret16 := is_transmit5_triggered_#res; [L995] activate_threads_~tmp___4~0 := activate_threads_#t~ret16; [L995] havoc activate_threads_#t~ret16; [L997-L1001] COND FALSE !(0 != activate_threads_~tmp___4~0) [L1003] havoc is_transmit6_triggered_#res; [L1003] havoc is_transmit6_triggered_~__retres1~6; [L489] havoc is_transmit6_triggered_~__retres1~6; [L492] COND FALSE !(1 == ~t6_pc~0) [L502] is_transmit6_triggered_~__retres1~6 := 0; [L504] is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; [L1003] activate_threads_#t~ret17 := is_transmit6_triggered_#res; [L1003] activate_threads_~tmp___5~0 := activate_threads_#t~ret17; [L1003] havoc activate_threads_#t~ret17; [L1005-L1009] COND FALSE !(0 != activate_threads_~tmp___5~0) [L1011] havoc is_transmit7_triggered_#res; [L1011] havoc is_transmit7_triggered_~__retres1~7; [L508] havoc is_transmit7_triggered_~__retres1~7; [L511] COND FALSE !(1 == ~t7_pc~0) [L521] is_transmit7_triggered_~__retres1~7 := 0; [L523] is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; [L1011] activate_threads_#t~ret18 := is_transmit7_triggered_#res; [L1011] activate_threads_~tmp___6~0 := activate_threads_#t~ret18; [L1011] havoc activate_threads_#t~ret18; [L1013-L1017] COND FALSE !(0 != activate_threads_~tmp___6~0) [L859] COND FALSE !(1 == ~M_E~0) [L864] COND FALSE !(1 == ~T1_E~0) [L869] COND FALSE !(1 == ~T2_E~0) [L874] COND FALSE !(1 == ~T3_E~0) [L879] COND FALSE !(1 == ~T4_E~0) [L884] COND FALSE !(1 == ~T5_E~0) [L889] COND FALSE !(1 == ~T6_E~0) [L894] COND FALSE !(1 == ~T7_E~0) [L899] COND FALSE !(1 == ~E_M~0) [L904] COND FALSE !(1 == ~E_1~0) [L909] COND FALSE !(1 == ~E_2~0) [L914] COND FALSE !(1 == ~E_3~0) [L919] COND FALSE !(1 == ~E_4~0) [L924] COND FALSE !(1 == ~E_5~0) [L929] COND FALSE !(1 == ~E_6~0) [L934] COND FALSE !(1 == ~E_7~0) [L1180-L1217] COND FALSE !(false) [L1183] start_simulation_~kernel_st~0 := 1; [L1184] havoc eval_#t~ret2, eval_#t~nondet3, eval_~tmp_ndt_1~0, eval_#t~nondet4, eval_~tmp_ndt_2~0, eval_#t~nondet5, eval_~tmp_ndt_3~0, eval_#t~nondet6, eval_~tmp_ndt_4~0, eval_#t~nondet7, eval_~tmp_ndt_5~0, eval_#t~nondet8, eval_~tmp_ndt_6~0, eval_#t~nondet9, eval_~tmp_ndt_7~0, eval_#t~nondet10, eval_~tmp_ndt_8~0, eval_~tmp~0; [L634] havoc eval_~tmp~0; [L14] ~m_pc~0 := 0; [L15] ~t1_pc~0 := 0; [L16] ~t2_pc~0 := 0; [L17] ~t3_pc~0 := 0; [L18] ~t4_pc~0 := 0; [L19] ~t5_pc~0 := 0; [L20] ~t6_pc~0 := 0; [L21] ~t7_pc~0 := 0; [L22] ~m_st~0 := 0; [L23] ~t1_st~0 := 0; [L24] ~t2_st~0 := 0; [L25] ~t3_st~0 := 0; [L26] ~t4_st~0 := 0; [L27] ~t5_st~0 := 0; [L28] ~t6_st~0 := 0; [L29] ~t7_st~0 := 0; [L30] ~m_i~0 := 0; [L31] ~t1_i~0 := 0; [L32] ~t2_i~0 := 0; [L33] ~t3_i~0 := 0; [L34] ~t4_i~0 := 0; [L35] ~t5_i~0 := 0; [L36] ~t6_i~0 := 0; [L37] ~t7_i~0 := 0; [L38] ~M_E~0 := 2; [L39] ~T1_E~0 := 2; [L40] ~T2_E~0 := 2; [L41] ~T3_E~0 := 2; [L42] ~T4_E~0 := 2; [L43] ~T5_E~0 := 2; [L44] ~T6_E~0 := 2; [L45] ~T7_E~0 := 2; [L46] ~E_M~0 := 2; [L47] ~E_1~0 := 2; [L48] ~E_2~0 := 2; [L49] ~E_3~0 := 2; [L50] ~E_4~0 := 2; [L51] ~E_5~0 := 2; [L52] ~E_6~0 := 2; [L53] ~E_7~0 := 2; [L63] ~token~0 := 0; [L65] ~local~0 := 0; [L1225] havoc ~__retres1~9; [L1134] ~m_i~0 := 1; [L1135] ~t1_i~0 := 1; [L1136] ~t2_i~0 := 1; [L1137] ~t3_i~0 := 1; [L1138] ~t4_i~0 := 1; [L1139] ~t5_i~0 := 1; [L1140] ~t6_i~0 := 1; [L1141] ~t7_i~0 := 1; [L1166] havoc ~kernel_st~0; [L1167] havoc ~tmp~3; [L1168] havoc ~tmp___0~1; [L1172] ~kernel_st~0 := 0; [L538] COND TRUE 1 == ~m_i~0 [L539] ~m_st~0 := 0; [L543] COND TRUE 1 == ~t1_i~0 [L544] ~t1_st~0 := 0; [L548] COND TRUE 1 == ~t2_i~0 [L549] ~t2_st~0 := 0; [L553] COND TRUE 1 == ~t3_i~0 [L554] ~t3_st~0 := 0; [L558] COND TRUE 1 == ~t4_i~0 [L559] ~t4_st~0 := 0; [L563] COND TRUE 1 == ~t5_i~0 [L564] ~t5_st~0 := 0; [L568] COND TRUE 1 == ~t6_i~0 [L569] ~t6_st~0 := 0; [L573] COND TRUE 1 == ~t7_i~0 [L574] ~t7_st~0 := 0; [L771] COND FALSE !(0 == ~M_E~0) [L776] COND FALSE !(0 == ~T1_E~0) [L781] COND FALSE !(0 == ~T2_E~0) [L786] COND FALSE !(0 == ~T3_E~0) [L791] COND FALSE !(0 == ~T4_E~0) [L796] COND FALSE !(0 == ~T5_E~0) [L801] COND FALSE !(0 == ~T6_E~0) [L806] COND FALSE !(0 == ~T7_E~0) [L811] COND FALSE !(0 == ~E_M~0) [L816] COND FALSE !(0 == ~E_1~0) [L821] COND FALSE !(0 == ~E_2~0) [L826] COND FALSE !(0 == ~E_3~0) [L831] COND FALSE !(0 == ~E_4~0) [L836] COND FALSE !(0 == ~E_5~0) [L841] COND FALSE !(0 == ~E_6~0) [L846] COND FALSE !(0 == ~E_7~0) [L944] havoc ~tmp~1; [L945] havoc ~tmp___0~0; [L946] havoc ~tmp___1~0; [L947] havoc ~tmp___2~0; [L948] havoc ~tmp___3~0; [L949] havoc ~tmp___4~0; [L950] havoc ~tmp___5~0; [L951] havoc ~tmp___6~0; [L375] havoc ~__retres1~0; [L378] COND FALSE !(1 == ~m_pc~0) [L388] ~__retres1~0 := 0; [L390] #res := ~__retres1~0; [L955] ~tmp~1 := #t~ret11; [L955] havoc #t~ret11; [L957-L961] COND FALSE !(0 != ~tmp~1) [L394] havoc ~__retres1~1; [L397] COND FALSE !(1 == ~t1_pc~0) [L407] ~__retres1~1 := 0; [L409] #res := ~__retres1~1; [L963] ~tmp___0~0 := #t~ret12; [L963] havoc #t~ret12; [L965-L969] COND FALSE !(0 != ~tmp___0~0) [L413] havoc ~__retres1~2; [L416] COND FALSE !(1 == ~t2_pc~0) [L426] ~__retres1~2 := 0; [L428] #res := ~__retres1~2; [L971] ~tmp___1~0 := #t~ret13; [L971] havoc #t~ret13; [L973-L977] COND FALSE !(0 != ~tmp___1~0) [L432] havoc ~__retres1~3; [L435] COND FALSE !(1 == ~t3_pc~0) [L445] ~__retres1~3 := 0; [L447] #res := ~__retres1~3; [L979] ~tmp___2~0 := #t~ret14; [L979] havoc #t~ret14; [L981-L985] COND FALSE !(0 != ~tmp___2~0) [L451] havoc ~__retres1~4; [L454] COND FALSE !(1 == ~t4_pc~0) [L464] ~__retres1~4 := 0; [L466] #res := ~__retres1~4; [L987] ~tmp___3~0 := #t~ret15; [L987] havoc #t~ret15; [L989-L993] COND FALSE !(0 != ~tmp___3~0) [L470] havoc ~__retres1~5; [L473] COND FALSE !(1 == ~t5_pc~0) [L483] ~__retres1~5 := 0; [L485] #res := ~__retres1~5; [L995] ~tmp___4~0 := #t~ret16; [L995] havoc #t~ret16; [L997-L1001] COND FALSE !(0 != ~tmp___4~0) [L489] havoc ~__retres1~6; [L492] COND FALSE !(1 == ~t6_pc~0) [L502] ~__retres1~6 := 0; [L504] #res := ~__retres1~6; [L1003] ~tmp___5~0 := #t~ret17; [L1003] havoc #t~ret17; [L1005-L1009] COND FALSE !(0 != ~tmp___5~0) [L508] havoc ~__retres1~7; [L511] COND FALSE !(1 == ~t7_pc~0) [L521] ~__retres1~7 := 0; [L523] #res := ~__retres1~7; [L1011] ~tmp___6~0 := #t~ret18; [L1011] havoc #t~ret18; [L1013-L1017] COND FALSE !(0 != ~tmp___6~0) [L859] COND FALSE !(1 == ~M_E~0) [L864] COND FALSE !(1 == ~T1_E~0) [L869] COND FALSE !(1 == ~T2_E~0) [L874] COND FALSE !(1 == ~T3_E~0) [L879] COND FALSE !(1 == ~T4_E~0) [L884] COND FALSE !(1 == ~T5_E~0) [L889] COND FALSE !(1 == ~T6_E~0) [L894] COND FALSE !(1 == ~T7_E~0) [L899] COND FALSE !(1 == ~E_M~0) [L904] COND FALSE !(1 == ~E_1~0) [L909] COND FALSE !(1 == ~E_2~0) [L914] COND FALSE !(1 == ~E_3~0) [L919] COND FALSE !(1 == ~E_4~0) [L924] COND FALSE !(1 == ~E_5~0) [L929] COND FALSE !(1 == ~E_6~0) [L934] COND FALSE !(1 == ~E_7~0) [L1180-L1217] COND FALSE !(false) [L1183] ~kernel_st~0 := 1; [L634] havoc ~tmp~0; ----- ----- class de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.CACSL2BoogieBacktranslator [L14] ~m_pc~0 := 0; [L15] ~t1_pc~0 := 0; [L16] ~t2_pc~0 := 0; [L17] ~t3_pc~0 := 0; [L18] ~t4_pc~0 := 0; [L19] ~t5_pc~0 := 0; [L20] ~t6_pc~0 := 0; [L21] ~t7_pc~0 := 0; [L22] ~m_st~0 := 0; [L23] ~t1_st~0 := 0; [L24] ~t2_st~0 := 0; [L25] ~t3_st~0 := 0; [L26] ~t4_st~0 := 0; [L27] ~t5_st~0 := 0; [L28] ~t6_st~0 := 0; [L29] ~t7_st~0 := 0; [L30] ~m_i~0 := 0; [L31] ~t1_i~0 := 0; [L32] ~t2_i~0 := 0; [L33] ~t3_i~0 := 0; [L34] ~t4_i~0 := 0; [L35] ~t5_i~0 := 0; [L36] ~t6_i~0 := 0; [L37] ~t7_i~0 := 0; [L38] ~M_E~0 := 2; [L39] ~T1_E~0 := 2; [L40] ~T2_E~0 := 2; [L41] ~T3_E~0 := 2; [L42] ~T4_E~0 := 2; [L43] ~T5_E~0 := 2; [L44] ~T6_E~0 := 2; [L45] ~T7_E~0 := 2; [L46] ~E_M~0 := 2; [L47] ~E_1~0 := 2; [L48] ~E_2~0 := 2; [L49] ~E_3~0 := 2; [L50] ~E_4~0 := 2; [L51] ~E_5~0 := 2; [L52] ~E_6~0 := 2; [L53] ~E_7~0 := 2; [L63] ~token~0 := 0; [L65] ~local~0 := 0; [L1225] havoc ~__retres1~9; [L1134] ~m_i~0 := 1; [L1135] ~t1_i~0 := 1; [L1136] ~t2_i~0 := 1; [L1137] ~t3_i~0 := 1; [L1138] ~t4_i~0 := 1; [L1139] ~t5_i~0 := 1; [L1140] ~t6_i~0 := 1; [L1141] ~t7_i~0 := 1; [L1166] havoc ~kernel_st~0; [L1167] havoc ~tmp~3; [L1168] havoc ~tmp___0~1; [L1172] ~kernel_st~0 := 0; [L538] COND TRUE 1 == ~m_i~0 [L539] ~m_st~0 := 0; [L543] COND TRUE 1 == ~t1_i~0 [L544] ~t1_st~0 := 0; [L548] COND TRUE 1 == ~t2_i~0 [L549] ~t2_st~0 := 0; [L553] COND TRUE 1 == ~t3_i~0 [L554] ~t3_st~0 := 0; [L558] COND TRUE 1 == ~t4_i~0 [L559] ~t4_st~0 := 0; [L563] COND TRUE 1 == ~t5_i~0 [L564] ~t5_st~0 := 0; [L568] COND TRUE 1 == ~t6_i~0 [L569] ~t6_st~0 := 0; [L573] COND TRUE 1 == ~t7_i~0 [L574] ~t7_st~0 := 0; [L771] COND FALSE !(0 == ~M_E~0) [L776] COND FALSE !(0 == ~T1_E~0) [L781] COND FALSE !(0 == ~T2_E~0) [L786] COND FALSE !(0 == ~T3_E~0) [L791] COND FALSE !(0 == ~T4_E~0) [L796] COND FALSE !(0 == ~T5_E~0) [L801] COND FALSE !(0 == ~T6_E~0) [L806] COND FALSE !(0 == ~T7_E~0) [L811] COND FALSE !(0 == ~E_M~0) [L816] COND FALSE !(0 == ~E_1~0) [L821] COND FALSE !(0 == ~E_2~0) [L826] COND FALSE !(0 == ~E_3~0) [L831] COND FALSE !(0 == ~E_4~0) [L836] COND FALSE !(0 == ~E_5~0) [L841] COND FALSE !(0 == ~E_6~0) [L846] COND FALSE !(0 == ~E_7~0) [L944] havoc ~tmp~1; [L945] havoc ~tmp___0~0; [L946] havoc ~tmp___1~0; [L947] havoc ~tmp___2~0; [L948] havoc ~tmp___3~0; [L949] havoc ~tmp___4~0; [L950] havoc ~tmp___5~0; [L951] havoc ~tmp___6~0; [L375] havoc ~__retres1~0; [L378] COND FALSE !(1 == ~m_pc~0) [L388] ~__retres1~0 := 0; [L390] #res := ~__retres1~0; [L955] ~tmp~1 := #t~ret11; [L955] havoc #t~ret11; [L957-L961] COND FALSE !(0 != ~tmp~1) [L394] havoc ~__retres1~1; [L397] COND FALSE !(1 == ~t1_pc~0) [L407] ~__retres1~1 := 0; [L409] #res := ~__retres1~1; [L963] ~tmp___0~0 := #t~ret12; [L963] havoc #t~ret12; [L965-L969] COND FALSE !(0 != ~tmp___0~0) [L413] havoc ~__retres1~2; [L416] COND FALSE !(1 == ~t2_pc~0) [L426] ~__retres1~2 := 0; [L428] #res := ~__retres1~2; [L971] ~tmp___1~0 := #t~ret13; [L971] havoc #t~ret13; [L973-L977] COND FALSE !(0 != ~tmp___1~0) [L432] havoc ~__retres1~3; [L435] COND FALSE !(1 == ~t3_pc~0) [L445] ~__retres1~3 := 0; [L447] #res := ~__retres1~3; [L979] ~tmp___2~0 := #t~ret14; [L979] havoc #t~ret14; [L981-L985] COND FALSE !(0 != ~tmp___2~0) [L451] havoc ~__retres1~4; [L454] COND FALSE !(1 == ~t4_pc~0) [L464] ~__retres1~4 := 0; [L466] #res := ~__retres1~4; [L987] ~tmp___3~0 := #t~ret15; [L987] havoc #t~ret15; [L989-L993] COND FALSE !(0 != ~tmp___3~0) [L470] havoc ~__retres1~5; [L473] COND FALSE !(1 == ~t5_pc~0) [L483] ~__retres1~5 := 0; [L485] #res := ~__retres1~5; [L995] ~tmp___4~0 := #t~ret16; [L995] havoc #t~ret16; [L997-L1001] COND FALSE !(0 != ~tmp___4~0) [L489] havoc ~__retres1~6; [L492] COND FALSE !(1 == ~t6_pc~0) [L502] ~__retres1~6 := 0; [L504] #res := ~__retres1~6; [L1003] ~tmp___5~0 := #t~ret17; [L1003] havoc #t~ret17; [L1005-L1009] COND FALSE !(0 != ~tmp___5~0) [L508] havoc ~__retres1~7; [L511] COND FALSE !(1 == ~t7_pc~0) [L521] ~__retres1~7 := 0; [L523] #res := ~__retres1~7; [L1011] ~tmp___6~0 := #t~ret18; [L1011] havoc #t~ret18; [L1013-L1017] COND FALSE !(0 != ~tmp___6~0) [L859] COND FALSE !(1 == ~M_E~0) [L864] COND FALSE !(1 == ~T1_E~0) [L869] COND FALSE !(1 == ~T2_E~0) [L874] COND FALSE !(1 == ~T3_E~0) [L879] COND FALSE !(1 == ~T4_E~0) [L884] COND FALSE !(1 == ~T5_E~0) [L889] COND FALSE !(1 == ~T6_E~0) [L894] COND FALSE !(1 == ~T7_E~0) [L899] COND FALSE !(1 == ~E_M~0) [L904] COND FALSE !(1 == ~E_1~0) [L909] COND FALSE !(1 == ~E_2~0) [L914] COND FALSE !(1 == ~E_3~0) [L919] COND FALSE !(1 == ~E_4~0) [L924] COND FALSE !(1 == ~E_5~0) [L929] COND FALSE !(1 == ~E_6~0) [L934] COND FALSE !(1 == ~E_7~0) [L1180-L1217] COND FALSE !(false) [L1183] ~kernel_st~0 := 1; [L634] havoc ~tmp~0; [L14] int m_pc = 0; [L15] int t1_pc = 0; [L16] int t2_pc = 0; [L17] int t3_pc = 0; [L18] int t4_pc = 0; [L19] int t5_pc = 0; [L20] int t6_pc = 0; [L21] int t7_pc = 0; [L22] int m_st ; [L23] int t1_st ; [L24] int t2_st ; [L25] int t3_st ; [L26] int t4_st ; [L27] int t5_st ; [L28] int t6_st ; [L29] int t7_st ; [L30] int m_i ; [L31] int t1_i ; [L32] int t2_i ; [L33] int t3_i ; [L34] int t4_i ; [L35] int t5_i ; [L36] int t6_i ; [L37] int t7_i ; [L38] int M_E = 2; [L39] int T1_E = 2; [L40] int T2_E = 2; [L41] int T3_E = 2; [L42] int T4_E = 2; [L43] int T5_E = 2; [L44] int T6_E = 2; [L45] int T7_E = 2; [L46] int E_M = 2; [L47] int E_1 = 2; [L48] int E_2 = 2; [L49] int E_3 = 2; [L50] int E_4 = 2; [L51] int E_5 = 2; [L52] int E_6 = 2; [L53] int E_7 = 2; [L63] int token ; [L65] int local ; [L1225] int __retres1 ; [L1134] m_i = 1 [L1135] t1_i = 1 [L1136] t2_i = 1 [L1137] t3_i = 1 [L1138] t4_i = 1 [L1139] t5_i = 1 [L1140] t6_i = 1 [L1141] t7_i = 1 [L1166] int kernel_st ; [L1167] int tmp ; [L1168] int tmp___0 ; [L1172] kernel_st = 0 [L538] COND TRUE m_i == 1 [L539] m_st = 0 [L543] COND TRUE t1_i == 1 [L544] t1_st = 0 [L548] COND TRUE t2_i == 1 [L549] t2_st = 0 [L553] COND TRUE t3_i == 1 [L554] t3_st = 0 [L558] COND TRUE t4_i == 1 [L559] t4_st = 0 [L563] COND TRUE t5_i == 1 [L564] t5_st = 0 [L568] COND TRUE t6_i == 1 [L569] t6_st = 0 [L573] COND TRUE t7_i == 1 [L574] t7_st = 0 [L771] COND FALSE !(M_E == 0) [L776] COND FALSE !(T1_E == 0) [L781] COND FALSE !(T2_E == 0) [L786] COND FALSE !(T3_E == 0) [L791] COND FALSE !(T4_E == 0) [L796] COND FALSE !(T5_E == 0) [L801] COND FALSE !(T6_E == 0) [L806] COND FALSE !(T7_E == 0) [L811] COND FALSE !(E_M == 0) [L816] COND FALSE !(E_1 == 0) [L821] COND FALSE !(E_2 == 0) [L826] COND FALSE !(E_3 == 0) [L831] COND FALSE !(E_4 == 0) [L836] COND FALSE !(E_5 == 0) [L841] COND FALSE !(E_6 == 0) [L846] COND FALSE !(E_7 == 0) [L944] int tmp ; [L945] int tmp___0 ; [L946] int tmp___1 ; [L947] int tmp___2 ; [L948] int tmp___3 ; [L949] int tmp___4 ; [L950] int tmp___5 ; [L951] int tmp___6 ; [L375] int __retres1 ; [L378] COND FALSE !(m_pc == 1) [L388] __retres1 = 0 [L390] return (__retres1); [L955] tmp = is_master_triggered() [L957] COND FALSE !(\read(tmp)) [L394] int __retres1 ; [L397] COND FALSE !(t1_pc == 1) [L407] __retres1 = 0 [L409] return (__retres1); [L963] tmp___0 = is_transmit1_triggered() [L965] COND FALSE !(\read(tmp___0)) [L413] int __retres1 ; [L416] COND FALSE !(t2_pc == 1) [L426] __retres1 = 0 [L428] return (__retres1); [L971] tmp___1 = is_transmit2_triggered() [L973] COND FALSE !(\read(tmp___1)) [L432] int __retres1 ; [L435] COND FALSE !(t3_pc == 1) [L445] __retres1 = 0 [L447] return (__retres1); [L979] tmp___2 = is_transmit3_triggered() [L981] COND FALSE !(\read(tmp___2)) [L451] int __retres1 ; [L454] COND FALSE !(t4_pc == 1) [L464] __retres1 = 0 [L466] return (__retres1); [L987] tmp___3 = is_transmit4_triggered() [L989] COND FALSE !(\read(tmp___3)) [L470] int __retres1 ; [L473] COND FALSE !(t5_pc == 1) [L483] __retres1 = 0 [L485] return (__retres1); [L995] tmp___4 = is_transmit5_triggered() [L997] COND FALSE !(\read(tmp___4)) [L489] int __retres1 ; [L492] COND FALSE !(t6_pc == 1) [L502] __retres1 = 0 [L504] return (__retres1); [L1003] tmp___5 = is_transmit6_triggered() [L1005] COND FALSE !(\read(tmp___5)) [L508] int __retres1 ; [L511] COND FALSE !(t7_pc == 1) [L521] __retres1 = 0 [L523] return (__retres1); [L1011] tmp___6 = is_transmit7_triggered() [L1013] COND FALSE !(\read(tmp___6)) [L859] COND FALSE !(M_E == 1) [L864] COND FALSE !(T1_E == 1) [L869] COND FALSE !(T2_E == 1) [L874] COND FALSE !(T3_E == 1) [L879] COND FALSE !(T4_E == 1) [L884] COND FALSE !(T5_E == 1) [L889] COND FALSE !(T6_E == 1) [L894] COND FALSE !(T7_E == 1) [L899] COND FALSE !(E_M == 1) [L904] COND FALSE !(E_1 == 1) [L909] COND FALSE !(E_2 == 1) [L914] COND FALSE !(E_3 == 1) [L919] COND FALSE !(E_4 == 1) [L924] COND FALSE !(E_5 == 1) [L929] COND FALSE !(E_6 == 1) [L934] COND FALSE !(E_7 == 1) [L1180] COND TRUE 1 [L1183] kernel_st = 1 [L634] int tmp ; ----- ----- class de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder.RCFGBacktranslator [?] assume !false; [?] havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~8;havoc exists_runnable_thread_~__retres1~8; [?] assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8 := 1; [?] exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; [?] eval_#t~ret2 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret2;havoc eval_#t~ret2; [?] assume 0 != eval_~tmp~0; [?] assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0;eval_~tmp_ndt_1~0 := eval_#t~nondet3;havoc eval_#t~nondet3; [?] assume !(0 != eval_~tmp_ndt_1~0); [?] assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0;eval_~tmp_ndt_2~0 := eval_#t~nondet4;havoc eval_#t~nondet4; [?] assume !(0 != eval_~tmp_ndt_2~0); [?] assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0;eval_~tmp_ndt_3~0 := eval_#t~nondet5;havoc eval_#t~nondet5; [?] assume !(0 != eval_~tmp_ndt_3~0); [?] assume 0 == ~t3_st~0;havoc eval_~tmp_ndt_4~0;eval_~tmp_ndt_4~0 := eval_#t~nondet6;havoc eval_#t~nondet6; [?] assume !(0 != eval_~tmp_ndt_4~0); [?] assume 0 == ~t4_st~0;havoc eval_~tmp_ndt_5~0;eval_~tmp_ndt_5~0 := eval_#t~nondet7;havoc eval_#t~nondet7; [?] assume !(0 != eval_~tmp_ndt_5~0); [?] assume 0 == ~t5_st~0;havoc eval_~tmp_ndt_6~0;eval_~tmp_ndt_6~0 := eval_#t~nondet8;havoc eval_#t~nondet8; [?] assume !(0 != eval_~tmp_ndt_6~0); [?] assume 0 == ~t6_st~0;havoc eval_~tmp_ndt_7~0;eval_~tmp_ndt_7~0 := eval_#t~nondet9;havoc eval_#t~nondet9; [?] assume !(0 != eval_~tmp_ndt_7~0); [?] assume 0 == ~t7_st~0;havoc eval_~tmp_ndt_8~0;eval_~tmp_ndt_8~0 := eval_#t~nondet10;havoc eval_#t~nondet10; [?] assume !(0 != eval_~tmp_ndt_8~0); [L638-L760] assume !false; [L641] havoc exists_runnable_thread_#res; [L641] havoc exists_runnable_thread_~__retres1~8; [L583] havoc exists_runnable_thread_~__retres1~8; [L586-L626] assume 0 == ~m_st~0; [L587] exists_runnable_thread_~__retres1~8 := 1; [L629] exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; [L641] eval_#t~ret2 := exists_runnable_thread_#res; [L641] eval_~tmp~0 := eval_#t~ret2; [L641] havoc eval_#t~ret2; [L643-L647] assume 0 != eval_~tmp~0; [L648-L661] assume 0 == ~m_st~0; [L649] havoc eval_~tmp_ndt_1~0; [L650] eval_~tmp_ndt_1~0 := eval_#t~nondet3; [L650] havoc eval_#t~nondet3; [L651-L658] assume !(0 != eval_~tmp_ndt_1~0); [L662-L675] assume 0 == ~t1_st~0; [L663] havoc eval_~tmp_ndt_2~0; [L664] eval_~tmp_ndt_2~0 := eval_#t~nondet4; [L664] havoc eval_#t~nondet4; [L665-L672] assume !(0 != eval_~tmp_ndt_2~0); [L676-L689] assume 0 == ~t2_st~0; [L677] havoc eval_~tmp_ndt_3~0; [L678] eval_~tmp_ndt_3~0 := eval_#t~nondet5; [L678] havoc eval_#t~nondet5; [L679-L686] assume !(0 != eval_~tmp_ndt_3~0); [L690-L703] assume 0 == ~t3_st~0; [L691] havoc eval_~tmp_ndt_4~0; [L692] eval_~tmp_ndt_4~0 := eval_#t~nondet6; [L692] havoc eval_#t~nondet6; [L693-L700] assume !(0 != eval_~tmp_ndt_4~0); [L704-L717] assume 0 == ~t4_st~0; [L705] havoc eval_~tmp_ndt_5~0; [L706] eval_~tmp_ndt_5~0 := eval_#t~nondet7; [L706] havoc eval_#t~nondet7; [L707-L714] assume !(0 != eval_~tmp_ndt_5~0); [L718-L731] assume 0 == ~t5_st~0; [L719] havoc eval_~tmp_ndt_6~0; [L720] eval_~tmp_ndt_6~0 := eval_#t~nondet8; [L720] havoc eval_#t~nondet8; [L721-L728] assume !(0 != eval_~tmp_ndt_6~0); [L732-L745] assume 0 == ~t6_st~0; [L733] havoc eval_~tmp_ndt_7~0; [L734] eval_~tmp_ndt_7~0 := eval_#t~nondet9; [L734] havoc eval_#t~nondet9; [L735-L742] assume !(0 != eval_~tmp_ndt_7~0); [L746-L759] assume 0 == ~t7_st~0; [L747] havoc eval_~tmp_ndt_8~0; [L748] eval_~tmp_ndt_8~0 := eval_#t~nondet10; [L748] havoc eval_#t~nondet10; [L749-L756] assume !(0 != eval_~tmp_ndt_8~0); ----- ----- class de.uni_freiburg.informatik.ultimate.boogie.preprocessor.BoogiePreprocessorBacktranslator [L638-L760] assume !false; [L641] havoc exists_runnable_thread_#res; [L641] havoc exists_runnable_thread_~__retres1~8; [L583] havoc exists_runnable_thread_~__retres1~8; [L586-L626] assume 0 == ~m_st~0; [L587] exists_runnable_thread_~__retres1~8 := 1; [L629] exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; [L641] eval_#t~ret2 := exists_runnable_thread_#res; [L641] eval_~tmp~0 := eval_#t~ret2; [L641] havoc eval_#t~ret2; [L643-L647] assume 0 != eval_~tmp~0; [L648-L661] assume 0 == ~m_st~0; [L649] havoc eval_~tmp_ndt_1~0; [L650] eval_~tmp_ndt_1~0 := eval_#t~nondet3; [L650] havoc eval_#t~nondet3; [L651-L658] assume !(0 != eval_~tmp_ndt_1~0); [L662-L675] assume 0 == ~t1_st~0; [L663] havoc eval_~tmp_ndt_2~0; [L664] eval_~tmp_ndt_2~0 := eval_#t~nondet4; [L664] havoc eval_#t~nondet4; [L665-L672] assume !(0 != eval_~tmp_ndt_2~0); [L676-L689] assume 0 == ~t2_st~0; [L677] havoc eval_~tmp_ndt_3~0; [L678] eval_~tmp_ndt_3~0 := eval_#t~nondet5; [L678] havoc eval_#t~nondet5; [L679-L686] assume !(0 != eval_~tmp_ndt_3~0); [L690-L703] assume 0 == ~t3_st~0; [L691] havoc eval_~tmp_ndt_4~0; [L692] eval_~tmp_ndt_4~0 := eval_#t~nondet6; [L692] havoc eval_#t~nondet6; [L693-L700] assume !(0 != eval_~tmp_ndt_4~0); [L704-L717] assume 0 == ~t4_st~0; [L705] havoc eval_~tmp_ndt_5~0; [L706] eval_~tmp_ndt_5~0 := eval_#t~nondet7; [L706] havoc eval_#t~nondet7; [L707-L714] assume !(0 != eval_~tmp_ndt_5~0); [L718-L731] assume 0 == ~t5_st~0; [L719] havoc eval_~tmp_ndt_6~0; [L720] eval_~tmp_ndt_6~0 := eval_#t~nondet8; [L720] havoc eval_#t~nondet8; [L721-L728] assume !(0 != eval_~tmp_ndt_6~0); [L732-L745] assume 0 == ~t6_st~0; [L733] havoc eval_~tmp_ndt_7~0; [L734] eval_~tmp_ndt_7~0 := eval_#t~nondet9; [L734] havoc eval_#t~nondet9; [L735-L742] assume !(0 != eval_~tmp_ndt_7~0); [L746-L759] assume 0 == ~t7_st~0; [L747] havoc eval_~tmp_ndt_8~0; [L748] eval_~tmp_ndt_8~0 := eval_#t~nondet10; [L748] havoc eval_#t~nondet10; [L749-L756] assume !(0 != eval_~tmp_ndt_8~0); [L638-L760] COND FALSE !(false) [L641] havoc exists_runnable_thread_#res; [L641] havoc exists_runnable_thread_~__retres1~8; [L583] havoc exists_runnable_thread_~__retres1~8; [L586] COND TRUE 0 == ~m_st~0 [L587] exists_runnable_thread_~__retres1~8 := 1; [L629] exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; [L641] eval_#t~ret2 := exists_runnable_thread_#res; [L641] eval_~tmp~0 := eval_#t~ret2; [L641] havoc eval_#t~ret2; [L643-L647] COND TRUE 0 != eval_~tmp~0 [L648] COND TRUE 0 == ~m_st~0 [L649] havoc eval_~tmp_ndt_1~0; [L650] eval_~tmp_ndt_1~0 := eval_#t~nondet3; [L650] havoc eval_#t~nondet3; [L651-L658] COND FALSE !(0 != eval_~tmp_ndt_1~0) [L662] COND TRUE 0 == ~t1_st~0 [L663] havoc eval_~tmp_ndt_2~0; [L664] eval_~tmp_ndt_2~0 := eval_#t~nondet4; [L664] havoc eval_#t~nondet4; [L665-L672] COND FALSE !(0 != eval_~tmp_ndt_2~0) [L676] COND TRUE 0 == ~t2_st~0 [L677] havoc eval_~tmp_ndt_3~0; [L678] eval_~tmp_ndt_3~0 := eval_#t~nondet5; [L678] havoc eval_#t~nondet5; [L679-L686] COND FALSE !(0 != eval_~tmp_ndt_3~0) [L690] COND TRUE 0 == ~t3_st~0 [L691] havoc eval_~tmp_ndt_4~0; [L692] eval_~tmp_ndt_4~0 := eval_#t~nondet6; [L692] havoc eval_#t~nondet6; [L693-L700] COND FALSE !(0 != eval_~tmp_ndt_4~0) [L704] COND TRUE 0 == ~t4_st~0 [L705] havoc eval_~tmp_ndt_5~0; [L706] eval_~tmp_ndt_5~0 := eval_#t~nondet7; [L706] havoc eval_#t~nondet7; [L707-L714] COND FALSE !(0 != eval_~tmp_ndt_5~0) [L718] COND TRUE 0 == ~t5_st~0 [L719] havoc eval_~tmp_ndt_6~0; [L720] eval_~tmp_ndt_6~0 := eval_#t~nondet8; [L720] havoc eval_#t~nondet8; [L721-L728] COND FALSE !(0 != eval_~tmp_ndt_6~0) [L732] COND TRUE 0 == ~t6_st~0 [L733] havoc eval_~tmp_ndt_7~0; [L734] eval_~tmp_ndt_7~0 := eval_#t~nondet9; [L734] havoc eval_#t~nondet9; [L735-L742] COND FALSE !(0 != eval_~tmp_ndt_7~0) [L746] COND TRUE 0 == ~t7_st~0 [L747] havoc eval_~tmp_ndt_8~0; [L748] eval_~tmp_ndt_8~0 := eval_#t~nondet10; [L748] havoc eval_#t~nondet10; [L749-L756] COND FALSE !(0 != eval_~tmp_ndt_8~0) ----- ----- class de.uni_freiburg.informatik.ultimate.boogie.procedureinliner.backtranslation.InlinerBacktranslator [L638-L760] COND FALSE !(false) [L641] havoc exists_runnable_thread_#res; [L641] havoc exists_runnable_thread_~__retres1~8; [L583] havoc exists_runnable_thread_~__retres1~8; [L586] COND TRUE 0 == ~m_st~0 [L587] exists_runnable_thread_~__retres1~8 := 1; [L629] exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; [L641] eval_#t~ret2 := exists_runnable_thread_#res; [L641] eval_~tmp~0 := eval_#t~ret2; [L641] havoc eval_#t~ret2; [L643-L647] COND TRUE 0 != eval_~tmp~0 [L648] COND TRUE 0 == ~m_st~0 [L649] havoc eval_~tmp_ndt_1~0; [L650] eval_~tmp_ndt_1~0 := eval_#t~nondet3; [L650] havoc eval_#t~nondet3; [L651-L658] COND FALSE !(0 != eval_~tmp_ndt_1~0) [L662] COND TRUE 0 == ~t1_st~0 [L663] havoc eval_~tmp_ndt_2~0; [L664] eval_~tmp_ndt_2~0 := eval_#t~nondet4; [L664] havoc eval_#t~nondet4; [L665-L672] COND FALSE !(0 != eval_~tmp_ndt_2~0) [L676] COND TRUE 0 == ~t2_st~0 [L677] havoc eval_~tmp_ndt_3~0; [L678] eval_~tmp_ndt_3~0 := eval_#t~nondet5; [L678] havoc eval_#t~nondet5; [L679-L686] COND FALSE !(0 != eval_~tmp_ndt_3~0) [L690] COND TRUE 0 == ~t3_st~0 [L691] havoc eval_~tmp_ndt_4~0; [L692] eval_~tmp_ndt_4~0 := eval_#t~nondet6; [L692] havoc eval_#t~nondet6; [L693-L700] COND FALSE !(0 != eval_~tmp_ndt_4~0) [L704] COND TRUE 0 == ~t4_st~0 [L705] havoc eval_~tmp_ndt_5~0; [L706] eval_~tmp_ndt_5~0 := eval_#t~nondet7; [L706] havoc eval_#t~nondet7; [L707-L714] COND FALSE !(0 != eval_~tmp_ndt_5~0) [L718] COND TRUE 0 == ~t5_st~0 [L719] havoc eval_~tmp_ndt_6~0; [L720] eval_~tmp_ndt_6~0 := eval_#t~nondet8; [L720] havoc eval_#t~nondet8; [L721-L728] COND FALSE !(0 != eval_~tmp_ndt_6~0) [L732] COND TRUE 0 == ~t6_st~0 [L733] havoc eval_~tmp_ndt_7~0; [L734] eval_~tmp_ndt_7~0 := eval_#t~nondet9; [L734] havoc eval_#t~nondet9; [L735-L742] COND FALSE !(0 != eval_~tmp_ndt_7~0) [L746] COND TRUE 0 == ~t7_st~0 [L747] havoc eval_~tmp_ndt_8~0; [L748] eval_~tmp_ndt_8~0 := eval_#t~nondet10; [L748] havoc eval_#t~nondet10; [L749-L756] COND FALSE !(0 != eval_~tmp_ndt_8~0) [L638-L760] COND FALSE !(false) [L583] havoc ~__retres1~8; [L586] COND TRUE 0 == ~m_st~0 [L587] ~__retres1~8 := 1; [L629] #res := ~__retres1~8; [L641] ~tmp~0 := #t~ret2; [L641] havoc #t~ret2; [L643-L647] COND TRUE 0 != ~tmp~0 [L648] COND TRUE 0 == ~m_st~0 [L649] havoc ~tmp_ndt_1~0; [L650] ~tmp_ndt_1~0 := #t~nondet3; [L650] havoc #t~nondet3; [L651-L658] COND FALSE !(0 != ~tmp_ndt_1~0) [L662] COND TRUE 0 == ~t1_st~0 [L663] havoc ~tmp_ndt_2~0; [L664] ~tmp_ndt_2~0 := #t~nondet4; [L664] havoc #t~nondet4; [L665-L672] COND FALSE !(0 != ~tmp_ndt_2~0) [L676] COND TRUE 0 == ~t2_st~0 [L677] havoc ~tmp_ndt_3~0; [L678] ~tmp_ndt_3~0 := #t~nondet5; [L678] havoc #t~nondet5; [L679-L686] COND FALSE !(0 != ~tmp_ndt_3~0) [L690] COND TRUE 0 == ~t3_st~0 [L691] havoc ~tmp_ndt_4~0; [L692] ~tmp_ndt_4~0 := #t~nondet6; [L692] havoc #t~nondet6; [L693-L700] COND FALSE !(0 != ~tmp_ndt_4~0) [L704] COND TRUE 0 == ~t4_st~0 [L705] havoc ~tmp_ndt_5~0; [L706] ~tmp_ndt_5~0 := #t~nondet7; [L706] havoc #t~nondet7; [L707-L714] COND FALSE !(0 != ~tmp_ndt_5~0) [L718] COND TRUE 0 == ~t5_st~0 [L719] havoc ~tmp_ndt_6~0; [L720] ~tmp_ndt_6~0 := #t~nondet8; [L720] havoc #t~nondet8; [L721-L728] COND FALSE !(0 != ~tmp_ndt_6~0) [L732] COND TRUE 0 == ~t6_st~0 [L733] havoc ~tmp_ndt_7~0; [L734] ~tmp_ndt_7~0 := #t~nondet9; [L734] havoc #t~nondet9; [L735-L742] COND FALSE !(0 != ~tmp_ndt_7~0) [L746] COND TRUE 0 == ~t7_st~0 [L747] havoc ~tmp_ndt_8~0; [L748] ~tmp_ndt_8~0 := #t~nondet10; [L748] havoc #t~nondet10; [L749-L756] COND FALSE !(0 != ~tmp_ndt_8~0) ----- ----- class de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.CACSL2BoogieBacktranslator [L638-L760] COND FALSE !(false) [L583] havoc ~__retres1~8; [L586] COND TRUE 0 == ~m_st~0 [L587] ~__retres1~8 := 1; [L629] #res := ~__retres1~8; [L641] ~tmp~0 := #t~ret2; [L641] havoc #t~ret2; [L643-L647] COND TRUE 0 != ~tmp~0 [L648] COND TRUE 0 == ~m_st~0 [L649] havoc ~tmp_ndt_1~0; [L650] ~tmp_ndt_1~0 := #t~nondet3; [L650] havoc #t~nondet3; [L651-L658] COND FALSE !(0 != ~tmp_ndt_1~0) [L662] COND TRUE 0 == ~t1_st~0 [L663] havoc ~tmp_ndt_2~0; [L664] ~tmp_ndt_2~0 := #t~nondet4; [L664] havoc #t~nondet4; [L665-L672] COND FALSE !(0 != ~tmp_ndt_2~0) [L676] COND TRUE 0 == ~t2_st~0 [L677] havoc ~tmp_ndt_3~0; [L678] ~tmp_ndt_3~0 := #t~nondet5; [L678] havoc #t~nondet5; [L679-L686] COND FALSE !(0 != ~tmp_ndt_3~0) [L690] COND TRUE 0 == ~t3_st~0 [L691] havoc ~tmp_ndt_4~0; [L692] ~tmp_ndt_4~0 := #t~nondet6; [L692] havoc #t~nondet6; [L693-L700] COND FALSE !(0 != ~tmp_ndt_4~0) [L704] COND TRUE 0 == ~t4_st~0 [L705] havoc ~tmp_ndt_5~0; [L706] ~tmp_ndt_5~0 := #t~nondet7; [L706] havoc #t~nondet7; [L707-L714] COND FALSE !(0 != ~tmp_ndt_5~0) [L718] COND TRUE 0 == ~t5_st~0 [L719] havoc ~tmp_ndt_6~0; [L720] ~tmp_ndt_6~0 := #t~nondet8; [L720] havoc #t~nondet8; [L721-L728] COND FALSE !(0 != ~tmp_ndt_6~0) [L732] COND TRUE 0 == ~t6_st~0 [L733] havoc ~tmp_ndt_7~0; [L734] ~tmp_ndt_7~0 := #t~nondet9; [L734] havoc #t~nondet9; [L735-L742] COND FALSE !(0 != ~tmp_ndt_7~0) [L746] COND TRUE 0 == ~t7_st~0 [L747] havoc ~tmp_ndt_8~0; [L748] ~tmp_ndt_8~0 := #t~nondet10; [L748] havoc #t~nondet10; [L749-L756] COND FALSE !(0 != ~tmp_ndt_8~0) [L638] COND TRUE 1 [L583] int __retres1 ; [L586] COND TRUE m_st == 0 [L587] __retres1 = 1 [L629] return (__retres1); [L641] tmp = exists_runnable_thread() [L643] COND TRUE \read(tmp) [L648] COND TRUE m_st == 0 [L649] int tmp_ndt_1; [L650] tmp_ndt_1 = __VERIFIER_nondet_int() [L651] COND FALSE !(\read(tmp_ndt_1)) [L662] COND TRUE t1_st == 0 [L663] int tmp_ndt_2; [L664] tmp_ndt_2 = __VERIFIER_nondet_int() [L665] COND FALSE !(\read(tmp_ndt_2)) [L676] COND TRUE t2_st == 0 [L677] int tmp_ndt_3; [L678] tmp_ndt_3 = __VERIFIER_nondet_int() [L679] COND FALSE !(\read(tmp_ndt_3)) [L690] COND TRUE t3_st == 0 [L691] int tmp_ndt_4; [L692] tmp_ndt_4 = __VERIFIER_nondet_int() [L693] COND FALSE !(\read(tmp_ndt_4)) [L704] COND TRUE t4_st == 0 [L705] int tmp_ndt_5; [L706] tmp_ndt_5 = __VERIFIER_nondet_int() [L707] COND FALSE !(\read(tmp_ndt_5)) [L718] COND TRUE t5_st == 0 [L719] int tmp_ndt_6; [L720] tmp_ndt_6 = __VERIFIER_nondet_int() [L721] COND FALSE !(\read(tmp_ndt_6)) [L732] COND TRUE t6_st == 0 [L733] int tmp_ndt_7; [L734] tmp_ndt_7 = __VERIFIER_nondet_int() [L735] COND FALSE !(\read(tmp_ndt_7)) [L746] COND TRUE t7_st == 0 [L747] int tmp_ndt_8; [L748] tmp_ndt_8 = __VERIFIER_nondet_int() [L749] COND FALSE !(\read(tmp_ndt_8)) ----- ----- class de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder.RCFGBacktranslator [?] ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; [?] havoc main_#res;havoc main_~__retres1~9;havoc main_~__retres1~9;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; [?] havoc start_simulation_#t~ret20, start_simulation_#t~ret21, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; [?] assume 1 == ~m_i~0;~m_st~0 := 0; [?] assume 1 == ~t1_i~0;~t1_st~0 := 0; [?] assume 1 == ~t2_i~0;~t2_st~0 := 0; [?] assume 1 == ~t3_i~0;~t3_st~0 := 0; [?] assume 1 == ~t4_i~0;~t4_st~0 := 0; [?] assume 1 == ~t5_i~0;~t5_st~0 := 0; [?] assume 1 == ~t6_i~0;~t6_st~0 := 0; [?] assume 1 == ~t7_i~0;~t7_st~0 := 0; [?] assume !(0 == ~M_E~0); [?] assume !(0 == ~T1_E~0); [?] assume !(0 == ~T2_E~0); [?] assume !(0 == ~T3_E~0); [?] assume !(0 == ~T4_E~0); [?] assume !(0 == ~T5_E~0); [?] assume !(0 == ~T6_E~0); [?] assume !(0 == ~T7_E~0); [?] assume !(0 == ~E_M~0); [?] assume !(0 == ~E_1~0); [?] assume !(0 == ~E_2~0); [?] assume !(0 == ~E_3~0); [?] assume !(0 == ~E_4~0); [?] assume !(0 == ~E_5~0); [?] assume !(0 == ~E_6~0); [?] assume !(0 == ~E_7~0); [?] havoc activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; [?] assume !(1 == ~m_pc~0); [?] is_master_triggered_~__retres1~0 := 0; [?] is_master_triggered_#res := is_master_triggered_~__retres1~0; [?] activate_threads_#t~ret11 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; [?] assume !(0 != activate_threads_~tmp~1); [?] havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; [?] assume !(1 == ~t1_pc~0); [?] is_transmit1_triggered_~__retres1~1 := 0; [?] is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; [?] activate_threads_#t~ret12 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; [?] assume !(0 != activate_threads_~tmp___0~0); [?] havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; [?] assume !(1 == ~t2_pc~0); [?] is_transmit2_triggered_~__retres1~2 := 0; [?] is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; [?] activate_threads_#t~ret13 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; [?] assume !(0 != activate_threads_~tmp___1~0); [?] havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; [?] assume !(1 == ~t3_pc~0); [?] is_transmit3_triggered_~__retres1~3 := 0; [?] is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; [?] activate_threads_#t~ret14 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; [?] assume !(0 != activate_threads_~tmp___2~0); [?] havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; [?] assume !(1 == ~t4_pc~0); [?] is_transmit4_triggered_~__retres1~4 := 0; [?] is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; [?] activate_threads_#t~ret15 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; [?] assume !(0 != activate_threads_~tmp___3~0); [?] havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; [?] assume !(1 == ~t5_pc~0); [?] is_transmit5_triggered_~__retres1~5 := 0; [?] is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; [?] activate_threads_#t~ret16 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; [?] assume !(0 != activate_threads_~tmp___4~0); [?] havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; [?] assume !(1 == ~t6_pc~0); [?] is_transmit6_triggered_~__retres1~6 := 0; [?] is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; [?] activate_threads_#t~ret17 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; [?] assume !(0 != activate_threads_~tmp___5~0); [?] havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; [?] assume !(1 == ~t7_pc~0); [?] is_transmit7_triggered_~__retres1~7 := 0; [?] is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; [?] activate_threads_#t~ret18 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; [?] assume !(0 != activate_threads_~tmp___6~0); [?] assume !(1 == ~M_E~0); [?] assume !(1 == ~T1_E~0); [?] assume !(1 == ~T2_E~0); [?] assume !(1 == ~T3_E~0); [?] assume !(1 == ~T4_E~0); [?] assume !(1 == ~T5_E~0); [?] assume !(1 == ~T6_E~0); [?] assume !(1 == ~T7_E~0); [?] assume !(1 == ~E_M~0); [?] assume !(1 == ~E_1~0); [?] assume !(1 == ~E_2~0); [?] assume !(1 == ~E_3~0); [?] assume !(1 == ~E_4~0); [?] assume !(1 == ~E_5~0); [?] assume !(1 == ~E_6~0); [?] assume !(1 == ~E_7~0); [?] assume !false; [?] start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret2, eval_#t~nondet3, eval_~tmp_ndt_1~0, eval_#t~nondet4, eval_~tmp_ndt_2~0, eval_#t~nondet5, eval_~tmp_ndt_3~0, eval_#t~nondet6, eval_~tmp_ndt_4~0, eval_#t~nondet7, eval_~tmp_ndt_5~0, eval_#t~nondet8, eval_~tmp_ndt_6~0, eval_#t~nondet9, eval_~tmp_ndt_7~0, eval_#t~nondet10, eval_~tmp_ndt_8~0, eval_~tmp~0;havoc eval_~tmp~0; [L14] ~m_pc~0 := 0; [L15] ~t1_pc~0 := 0; [L16] ~t2_pc~0 := 0; [L17] ~t3_pc~0 := 0; [L18] ~t4_pc~0 := 0; [L19] ~t5_pc~0 := 0; [L20] ~t6_pc~0 := 0; [L21] ~t7_pc~0 := 0; [L22] ~m_st~0 := 0; [L23] ~t1_st~0 := 0; [L24] ~t2_st~0 := 0; [L25] ~t3_st~0 := 0; [L26] ~t4_st~0 := 0; [L27] ~t5_st~0 := 0; [L28] ~t6_st~0 := 0; [L29] ~t7_st~0 := 0; [L30] ~m_i~0 := 0; [L31] ~t1_i~0 := 0; [L32] ~t2_i~0 := 0; [L33] ~t3_i~0 := 0; [L34] ~t4_i~0 := 0; [L35] ~t5_i~0 := 0; [L36] ~t6_i~0 := 0; [L37] ~t7_i~0 := 0; [L38] ~M_E~0 := 2; [L39] ~T1_E~0 := 2; [L40] ~T2_E~0 := 2; [L41] ~T3_E~0 := 2; [L42] ~T4_E~0 := 2; [L43] ~T5_E~0 := 2; [L44] ~T6_E~0 := 2; [L45] ~T7_E~0 := 2; [L46] ~E_M~0 := 2; [L47] ~E_1~0 := 2; [L48] ~E_2~0 := 2; [L49] ~E_3~0 := 2; [L50] ~E_4~0 := 2; [L51] ~E_5~0 := 2; [L52] ~E_6~0 := 2; [L53] ~E_7~0 := 2; [L63] ~token~0 := 0; [L65] ~local~0 := 0; [?] havoc main_#res; [?] havoc main_~__retres1~9; [L1225] havoc main_~__retres1~9; [L1134] ~m_i~0 := 1; [L1135] ~t1_i~0 := 1; [L1136] ~t2_i~0 := 1; [L1137] ~t3_i~0 := 1; [L1138] ~t4_i~0 := 1; [L1139] ~t5_i~0 := 1; [L1140] ~t6_i~0 := 1; [L1141] ~t7_i~0 := 1; [L1230] havoc start_simulation_#t~ret20, start_simulation_#t~ret21, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1; [L1166] havoc start_simulation_~kernel_st~0; [L1167] havoc start_simulation_~tmp~3; [L1168] havoc start_simulation_~tmp___0~1; [L1172] start_simulation_~kernel_st~0 := 0; [L538-L542] assume 1 == ~m_i~0; [L539] ~m_st~0 := 0; [L543-L547] assume 1 == ~t1_i~0; [L544] ~t1_st~0 := 0; [L548-L552] assume 1 == ~t2_i~0; [L549] ~t2_st~0 := 0; [L553-L557] assume 1 == ~t3_i~0; [L554] ~t3_st~0 := 0; [L558-L562] assume 1 == ~t4_i~0; [L559] ~t4_st~0 := 0; [L563-L567] assume 1 == ~t5_i~0; [L564] ~t5_st~0 := 0; [L568-L572] assume 1 == ~t6_i~0; [L569] ~t6_st~0 := 0; [L573-L577] assume 1 == ~t7_i~0; [L574] ~t7_st~0 := 0; [L771-L775] assume !(0 == ~M_E~0); [L776-L780] assume !(0 == ~T1_E~0); [L781-L785] assume !(0 == ~T2_E~0); [L786-L790] assume !(0 == ~T3_E~0); [L791-L795] assume !(0 == ~T4_E~0); [L796-L800] assume !(0 == ~T5_E~0); [L801-L805] assume !(0 == ~T6_E~0); [L806-L810] assume !(0 == ~T7_E~0); [L811-L815] assume !(0 == ~E_M~0); [L816-L820] assume !(0 == ~E_1~0); [L821-L825] assume !(0 == ~E_2~0); [L826-L830] assume !(0 == ~E_3~0); [L831-L835] assume !(0 == ~E_4~0); [L836-L840] assume !(0 == ~E_5~0); [L841-L845] assume !(0 == ~E_6~0); [L846-L850] assume !(0 == ~E_7~0); [L1176] havoc activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0; [L944] havoc activate_threads_~tmp~1; [L945] havoc activate_threads_~tmp___0~0; [L946] havoc activate_threads_~tmp___1~0; [L947] havoc activate_threads_~tmp___2~0; [L948] havoc activate_threads_~tmp___3~0; [L949] havoc activate_threads_~tmp___4~0; [L950] havoc activate_threads_~tmp___5~0; [L951] havoc activate_threads_~tmp___6~0; [L955] havoc is_master_triggered_#res; [L955] havoc is_master_triggered_~__retres1~0; [L375] havoc is_master_triggered_~__retres1~0; [L378-L387] assume !(1 == ~m_pc~0); [L388] is_master_triggered_~__retres1~0 := 0; [L390] is_master_triggered_#res := is_master_triggered_~__retres1~0; [L955] activate_threads_#t~ret11 := is_master_triggered_#res; [L955] activate_threads_~tmp~1 := activate_threads_#t~ret11; [L955] havoc activate_threads_#t~ret11; [L957-L961] assume !(0 != activate_threads_~tmp~1); [L963] havoc is_transmit1_triggered_#res; [L963] havoc is_transmit1_triggered_~__retres1~1; [L394] havoc is_transmit1_triggered_~__retres1~1; [L397-L406] assume !(1 == ~t1_pc~0); [L407] is_transmit1_triggered_~__retres1~1 := 0; [L409] is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; [L963] activate_threads_#t~ret12 := is_transmit1_triggered_#res; [L963] activate_threads_~tmp___0~0 := activate_threads_#t~ret12; [L963] havoc activate_threads_#t~ret12; [L965-L969] assume !(0 != activate_threads_~tmp___0~0); [L971] havoc is_transmit2_triggered_#res; [L971] havoc is_transmit2_triggered_~__retres1~2; [L413] havoc is_transmit2_triggered_~__retres1~2; [L416-L425] assume !(1 == ~t2_pc~0); [L426] is_transmit2_triggered_~__retres1~2 := 0; [L428] is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; [L971] activate_threads_#t~ret13 := is_transmit2_triggered_#res; [L971] activate_threads_~tmp___1~0 := activate_threads_#t~ret13; [L971] havoc activate_threads_#t~ret13; [L973-L977] assume !(0 != activate_threads_~tmp___1~0); [L979] havoc is_transmit3_triggered_#res; [L979] havoc is_transmit3_triggered_~__retres1~3; [L432] havoc is_transmit3_triggered_~__retres1~3; [L435-L444] assume !(1 == ~t3_pc~0); [L445] is_transmit3_triggered_~__retres1~3 := 0; [L447] is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; [L979] activate_threads_#t~ret14 := is_transmit3_triggered_#res; [L979] activate_threads_~tmp___2~0 := activate_threads_#t~ret14; [L979] havoc activate_threads_#t~ret14; [L981-L985] assume !(0 != activate_threads_~tmp___2~0); [L987] havoc is_transmit4_triggered_#res; [L987] havoc is_transmit4_triggered_~__retres1~4; [L451] havoc is_transmit4_triggered_~__retres1~4; [L454-L463] assume !(1 == ~t4_pc~0); [L464] is_transmit4_triggered_~__retres1~4 := 0; [L466] is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; [L987] activate_threads_#t~ret15 := is_transmit4_triggered_#res; [L987] activate_threads_~tmp___3~0 := activate_threads_#t~ret15; [L987] havoc activate_threads_#t~ret15; [L989-L993] assume !(0 != activate_threads_~tmp___3~0); [L995] havoc is_transmit5_triggered_#res; [L995] havoc is_transmit5_triggered_~__retres1~5; [L470] havoc is_transmit5_triggered_~__retres1~5; [L473-L482] assume !(1 == ~t5_pc~0); [L483] is_transmit5_triggered_~__retres1~5 := 0; [L485] is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; [L995] activate_threads_#t~ret16 := is_transmit5_triggered_#res; [L995] activate_threads_~tmp___4~0 := activate_threads_#t~ret16; [L995] havoc activate_threads_#t~ret16; [L997-L1001] assume !(0 != activate_threads_~tmp___4~0); [L1003] havoc is_transmit6_triggered_#res; [L1003] havoc is_transmit6_triggered_~__retres1~6; [L489] havoc is_transmit6_triggered_~__retres1~6; [L492-L501] assume !(1 == ~t6_pc~0); [L502] is_transmit6_triggered_~__retres1~6 := 0; [L504] is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; [L1003] activate_threads_#t~ret17 := is_transmit6_triggered_#res; [L1003] activate_threads_~tmp___5~0 := activate_threads_#t~ret17; [L1003] havoc activate_threads_#t~ret17; [L1005-L1009] assume !(0 != activate_threads_~tmp___5~0); [L1011] havoc is_transmit7_triggered_#res; [L1011] havoc is_transmit7_triggered_~__retres1~7; [L508] havoc is_transmit7_triggered_~__retres1~7; [L511-L520] assume !(1 == ~t7_pc~0); [L521] is_transmit7_triggered_~__retres1~7 := 0; [L523] is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; [L1011] activate_threads_#t~ret18 := is_transmit7_triggered_#res; [L1011] activate_threads_~tmp___6~0 := activate_threads_#t~ret18; [L1011] havoc activate_threads_#t~ret18; [L1013-L1017] assume !(0 != activate_threads_~tmp___6~0); [L859-L863] assume !(1 == ~M_E~0); [L864-L868] assume !(1 == ~T1_E~0); [L869-L873] assume !(1 == ~T2_E~0); [L874-L878] assume !(1 == ~T3_E~0); [L879-L883] assume !(1 == ~T4_E~0); [L884-L888] assume !(1 == ~T5_E~0); [L889-L893] assume !(1 == ~T6_E~0); [L894-L898] assume !(1 == ~T7_E~0); [L899-L903] assume !(1 == ~E_M~0); [L904-L908] assume !(1 == ~E_1~0); [L909-L913] assume !(1 == ~E_2~0); [L914-L918] assume !(1 == ~E_3~0); [L919-L923] assume !(1 == ~E_4~0); [L924-L928] assume !(1 == ~E_5~0); [L929-L933] assume !(1 == ~E_6~0); [L934-L938] assume !(1 == ~E_7~0); [L1180-L1217] assume !false; [L1183] start_simulation_~kernel_st~0 := 1; [L1184] havoc eval_#t~ret2, eval_#t~nondet3, eval_~tmp_ndt_1~0, eval_#t~nondet4, eval_~tmp_ndt_2~0, eval_#t~nondet5, eval_~tmp_ndt_3~0, eval_#t~nondet6, eval_~tmp_ndt_4~0, eval_#t~nondet7, eval_~tmp_ndt_5~0, eval_#t~nondet8, eval_~tmp_ndt_6~0, eval_#t~nondet9, eval_~tmp_ndt_7~0, eval_#t~nondet10, eval_~tmp_ndt_8~0, eval_~tmp~0; [L634] havoc eval_~tmp~0; ----- ----- class de.uni_freiburg.informatik.ultimate.boogie.preprocessor.BoogiePreprocessorBacktranslator [L14] ~m_pc~0 := 0; [L15] ~t1_pc~0 := 0; [L16] ~t2_pc~0 := 0; [L17] ~t3_pc~0 := 0; [L18] ~t4_pc~0 := 0; [L19] ~t5_pc~0 := 0; [L20] ~t6_pc~0 := 0; [L21] ~t7_pc~0 := 0; [L22] ~m_st~0 := 0; [L23] ~t1_st~0 := 0; [L24] ~t2_st~0 := 0; [L25] ~t3_st~0 := 0; [L26] ~t4_st~0 := 0; [L27] ~t5_st~0 := 0; [L28] ~t6_st~0 := 0; [L29] ~t7_st~0 := 0; [L30] ~m_i~0 := 0; [L31] ~t1_i~0 := 0; [L32] ~t2_i~0 := 0; [L33] ~t3_i~0 := 0; [L34] ~t4_i~0 := 0; [L35] ~t5_i~0 := 0; [L36] ~t6_i~0 := 0; [L37] ~t7_i~0 := 0; [L38] ~M_E~0 := 2; [L39] ~T1_E~0 := 2; [L40] ~T2_E~0 := 2; [L41] ~T3_E~0 := 2; [L42] ~T4_E~0 := 2; [L43] ~T5_E~0 := 2; [L44] ~T6_E~0 := 2; [L45] ~T7_E~0 := 2; [L46] ~E_M~0 := 2; [L47] ~E_1~0 := 2; [L48] ~E_2~0 := 2; [L49] ~E_3~0 := 2; [L50] ~E_4~0 := 2; [L51] ~E_5~0 := 2; [L52] ~E_6~0 := 2; [L53] ~E_7~0 := 2; [L63] ~token~0 := 0; [L65] ~local~0 := 0; [?] havoc main_#res; [?] havoc main_~__retres1~9; [L1225] havoc main_~__retres1~9; [L1134] ~m_i~0 := 1; [L1135] ~t1_i~0 := 1; [L1136] ~t2_i~0 := 1; [L1137] ~t3_i~0 := 1; [L1138] ~t4_i~0 := 1; [L1139] ~t5_i~0 := 1; [L1140] ~t6_i~0 := 1; [L1141] ~t7_i~0 := 1; [L1230] havoc start_simulation_#t~ret20, start_simulation_#t~ret21, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1; [L1166] havoc start_simulation_~kernel_st~0; [L1167] havoc start_simulation_~tmp~3; [L1168] havoc start_simulation_~tmp___0~1; [L1172] start_simulation_~kernel_st~0 := 0; [L538-L542] assume 1 == ~m_i~0; [L539] ~m_st~0 := 0; [L543-L547] assume 1 == ~t1_i~0; [L544] ~t1_st~0 := 0; [L548-L552] assume 1 == ~t2_i~0; [L549] ~t2_st~0 := 0; [L553-L557] assume 1 == ~t3_i~0; [L554] ~t3_st~0 := 0; [L558-L562] assume 1 == ~t4_i~0; [L559] ~t4_st~0 := 0; [L563-L567] assume 1 == ~t5_i~0; [L564] ~t5_st~0 := 0; [L568-L572] assume 1 == ~t6_i~0; [L569] ~t6_st~0 := 0; [L573-L577] assume 1 == ~t7_i~0; [L574] ~t7_st~0 := 0; [L771-L775] assume !(0 == ~M_E~0); [L776-L780] assume !(0 == ~T1_E~0); [L781-L785] assume !(0 == ~T2_E~0); [L786-L790] assume !(0 == ~T3_E~0); [L791-L795] assume !(0 == ~T4_E~0); [L796-L800] assume !(0 == ~T5_E~0); [L801-L805] assume !(0 == ~T6_E~0); [L806-L810] assume !(0 == ~T7_E~0); [L811-L815] assume !(0 == ~E_M~0); [L816-L820] assume !(0 == ~E_1~0); [L821-L825] assume !(0 == ~E_2~0); [L826-L830] assume !(0 == ~E_3~0); [L831-L835] assume !(0 == ~E_4~0); [L836-L840] assume !(0 == ~E_5~0); [L841-L845] assume !(0 == ~E_6~0); [L846-L850] assume !(0 == ~E_7~0); [L1176] havoc activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0; [L944] havoc activate_threads_~tmp~1; [L945] havoc activate_threads_~tmp___0~0; [L946] havoc activate_threads_~tmp___1~0; [L947] havoc activate_threads_~tmp___2~0; [L948] havoc activate_threads_~tmp___3~0; [L949] havoc activate_threads_~tmp___4~0; [L950] havoc activate_threads_~tmp___5~0; [L951] havoc activate_threads_~tmp___6~0; [L955] havoc is_master_triggered_#res; [L955] havoc is_master_triggered_~__retres1~0; [L375] havoc is_master_triggered_~__retres1~0; [L378-L387] assume !(1 == ~m_pc~0); [L388] is_master_triggered_~__retres1~0 := 0; [L390] is_master_triggered_#res := is_master_triggered_~__retres1~0; [L955] activate_threads_#t~ret11 := is_master_triggered_#res; [L955] activate_threads_~tmp~1 := activate_threads_#t~ret11; [L955] havoc activate_threads_#t~ret11; [L957-L961] assume !(0 != activate_threads_~tmp~1); [L963] havoc is_transmit1_triggered_#res; [L963] havoc is_transmit1_triggered_~__retres1~1; [L394] havoc is_transmit1_triggered_~__retres1~1; [L397-L406] assume !(1 == ~t1_pc~0); [L407] is_transmit1_triggered_~__retres1~1 := 0; [L409] is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; [L963] activate_threads_#t~ret12 := is_transmit1_triggered_#res; [L963] activate_threads_~tmp___0~0 := activate_threads_#t~ret12; [L963] havoc activate_threads_#t~ret12; [L965-L969] assume !(0 != activate_threads_~tmp___0~0); [L971] havoc is_transmit2_triggered_#res; [L971] havoc is_transmit2_triggered_~__retres1~2; [L413] havoc is_transmit2_triggered_~__retres1~2; [L416-L425] assume !(1 == ~t2_pc~0); [L426] is_transmit2_triggered_~__retres1~2 := 0; [L428] is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; [L971] activate_threads_#t~ret13 := is_transmit2_triggered_#res; [L971] activate_threads_~tmp___1~0 := activate_threads_#t~ret13; [L971] havoc activate_threads_#t~ret13; [L973-L977] assume !(0 != activate_threads_~tmp___1~0); [L979] havoc is_transmit3_triggered_#res; [L979] havoc is_transmit3_triggered_~__retres1~3; [L432] havoc is_transmit3_triggered_~__retres1~3; [L435-L444] assume !(1 == ~t3_pc~0); [L445] is_transmit3_triggered_~__retres1~3 := 0; [L447] is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; [L979] activate_threads_#t~ret14 := is_transmit3_triggered_#res; [L979] activate_threads_~tmp___2~0 := activate_threads_#t~ret14; [L979] havoc activate_threads_#t~ret14; [L981-L985] assume !(0 != activate_threads_~tmp___2~0); [L987] havoc is_transmit4_triggered_#res; [L987] havoc is_transmit4_triggered_~__retres1~4; [L451] havoc is_transmit4_triggered_~__retres1~4; [L454-L463] assume !(1 == ~t4_pc~0); [L464] is_transmit4_triggered_~__retres1~4 := 0; [L466] is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; [L987] activate_threads_#t~ret15 := is_transmit4_triggered_#res; [L987] activate_threads_~tmp___3~0 := activate_threads_#t~ret15; [L987] havoc activate_threads_#t~ret15; [L989-L993] assume !(0 != activate_threads_~tmp___3~0); [L995] havoc is_transmit5_triggered_#res; [L995] havoc is_transmit5_triggered_~__retres1~5; [L470] havoc is_transmit5_triggered_~__retres1~5; [L473-L482] assume !(1 == ~t5_pc~0); [L483] is_transmit5_triggered_~__retres1~5 := 0; [L485] is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; [L995] activate_threads_#t~ret16 := is_transmit5_triggered_#res; [L995] activate_threads_~tmp___4~0 := activate_threads_#t~ret16; [L995] havoc activate_threads_#t~ret16; [L997-L1001] assume !(0 != activate_threads_~tmp___4~0); [L1003] havoc is_transmit6_triggered_#res; [L1003] havoc is_transmit6_triggered_~__retres1~6; [L489] havoc is_transmit6_triggered_~__retres1~6; [L492-L501] assume !(1 == ~t6_pc~0); [L502] is_transmit6_triggered_~__retres1~6 := 0; [L504] is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; [L1003] activate_threads_#t~ret17 := is_transmit6_triggered_#res; [L1003] activate_threads_~tmp___5~0 := activate_threads_#t~ret17; [L1003] havoc activate_threads_#t~ret17; [L1005-L1009] assume !(0 != activate_threads_~tmp___5~0); [L1011] havoc is_transmit7_triggered_#res; [L1011] havoc is_transmit7_triggered_~__retres1~7; [L508] havoc is_transmit7_triggered_~__retres1~7; [L511-L520] assume !(1 == ~t7_pc~0); [L521] is_transmit7_triggered_~__retres1~7 := 0; [L523] is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; [L1011] activate_threads_#t~ret18 := is_transmit7_triggered_#res; [L1011] activate_threads_~tmp___6~0 := activate_threads_#t~ret18; [L1011] havoc activate_threads_#t~ret18; [L1013-L1017] assume !(0 != activate_threads_~tmp___6~0); [L859-L863] assume !(1 == ~M_E~0); [L864-L868] assume !(1 == ~T1_E~0); [L869-L873] assume !(1 == ~T2_E~0); [L874-L878] assume !(1 == ~T3_E~0); [L879-L883] assume !(1 == ~T4_E~0); [L884-L888] assume !(1 == ~T5_E~0); [L889-L893] assume !(1 == ~T6_E~0); [L894-L898] assume !(1 == ~T7_E~0); [L899-L903] assume !(1 == ~E_M~0); [L904-L908] assume !(1 == ~E_1~0); [L909-L913] assume !(1 == ~E_2~0); [L914-L918] assume !(1 == ~E_3~0); [L919-L923] assume !(1 == ~E_4~0); [L924-L928] assume !(1 == ~E_5~0); [L929-L933] assume !(1 == ~E_6~0); [L934-L938] assume !(1 == ~E_7~0); [L1180-L1217] assume !false; [L1183] start_simulation_~kernel_st~0 := 1; [L1184] havoc eval_#t~ret2, eval_#t~nondet3, eval_~tmp_ndt_1~0, eval_#t~nondet4, eval_~tmp_ndt_2~0, eval_#t~nondet5, eval_~tmp_ndt_3~0, eval_#t~nondet6, eval_~tmp_ndt_4~0, eval_#t~nondet7, eval_~tmp_ndt_5~0, eval_#t~nondet8, eval_~tmp_ndt_6~0, eval_#t~nondet9, eval_~tmp_ndt_7~0, eval_#t~nondet10, eval_~tmp_ndt_8~0, eval_~tmp~0; [L634] havoc eval_~tmp~0; [L14] ~m_pc~0 := 0; [L15] ~t1_pc~0 := 0; [L16] ~t2_pc~0 := 0; [L17] ~t3_pc~0 := 0; [L18] ~t4_pc~0 := 0; [L19] ~t5_pc~0 := 0; [L20] ~t6_pc~0 := 0; [L21] ~t7_pc~0 := 0; [L22] ~m_st~0 := 0; [L23] ~t1_st~0 := 0; [L24] ~t2_st~0 := 0; [L25] ~t3_st~0 := 0; [L26] ~t4_st~0 := 0; [L27] ~t5_st~0 := 0; [L28] ~t6_st~0 := 0; [L29] ~t7_st~0 := 0; [L30] ~m_i~0 := 0; [L31] ~t1_i~0 := 0; [L32] ~t2_i~0 := 0; [L33] ~t3_i~0 := 0; [L34] ~t4_i~0 := 0; [L35] ~t5_i~0 := 0; [L36] ~t6_i~0 := 0; [L37] ~t7_i~0 := 0; [L38] ~M_E~0 := 2; [L39] ~T1_E~0 := 2; [L40] ~T2_E~0 := 2; [L41] ~T3_E~0 := 2; [L42] ~T4_E~0 := 2; [L43] ~T5_E~0 := 2; [L44] ~T6_E~0 := 2; [L45] ~T7_E~0 := 2; [L46] ~E_M~0 := 2; [L47] ~E_1~0 := 2; [L48] ~E_2~0 := 2; [L49] ~E_3~0 := 2; [L50] ~E_4~0 := 2; [L51] ~E_5~0 := 2; [L52] ~E_6~0 := 2; [L53] ~E_7~0 := 2; [L63] ~token~0 := 0; [L65] ~local~0 := 0; [?] havoc main_#res; [?] havoc main_~__retres1~9; [L1225] havoc main_~__retres1~9; [L1134] ~m_i~0 := 1; [L1135] ~t1_i~0 := 1; [L1136] ~t2_i~0 := 1; [L1137] ~t3_i~0 := 1; [L1138] ~t4_i~0 := 1; [L1139] ~t5_i~0 := 1; [L1140] ~t6_i~0 := 1; [L1141] ~t7_i~0 := 1; [L1230] havoc start_simulation_#t~ret20, start_simulation_#t~ret21, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1; [L1166] havoc start_simulation_~kernel_st~0; [L1167] havoc start_simulation_~tmp~3; [L1168] havoc start_simulation_~tmp___0~1; [L1172] start_simulation_~kernel_st~0 := 0; [L538] COND TRUE 1 == ~m_i~0 [L539] ~m_st~0 := 0; [L543] COND TRUE 1 == ~t1_i~0 [L544] ~t1_st~0 := 0; [L548] COND TRUE 1 == ~t2_i~0 [L549] ~t2_st~0 := 0; [L553] COND TRUE 1 == ~t3_i~0 [L554] ~t3_st~0 := 0; [L558] COND TRUE 1 == ~t4_i~0 [L559] ~t4_st~0 := 0; [L563] COND TRUE 1 == ~t5_i~0 [L564] ~t5_st~0 := 0; [L568] COND TRUE 1 == ~t6_i~0 [L569] ~t6_st~0 := 0; [L573] COND TRUE 1 == ~t7_i~0 [L574] ~t7_st~0 := 0; [L771] COND FALSE !(0 == ~M_E~0) [L776] COND FALSE !(0 == ~T1_E~0) [L781] COND FALSE !(0 == ~T2_E~0) [L786] COND FALSE !(0 == ~T3_E~0) [L791] COND FALSE !(0 == ~T4_E~0) [L796] COND FALSE !(0 == ~T5_E~0) [L801] COND FALSE !(0 == ~T6_E~0) [L806] COND FALSE !(0 == ~T7_E~0) [L811] COND FALSE !(0 == ~E_M~0) [L816] COND FALSE !(0 == ~E_1~0) [L821] COND FALSE !(0 == ~E_2~0) [L826] COND FALSE !(0 == ~E_3~0) [L831] COND FALSE !(0 == ~E_4~0) [L836] COND FALSE !(0 == ~E_5~0) [L841] COND FALSE !(0 == ~E_6~0) [L846] COND FALSE !(0 == ~E_7~0) [L1176] havoc activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0; [L944] havoc activate_threads_~tmp~1; [L945] havoc activate_threads_~tmp___0~0; [L946] havoc activate_threads_~tmp___1~0; [L947] havoc activate_threads_~tmp___2~0; [L948] havoc activate_threads_~tmp___3~0; [L949] havoc activate_threads_~tmp___4~0; [L950] havoc activate_threads_~tmp___5~0; [L951] havoc activate_threads_~tmp___6~0; [L955] havoc is_master_triggered_#res; [L955] havoc is_master_triggered_~__retres1~0; [L375] havoc is_master_triggered_~__retres1~0; [L378] COND FALSE !(1 == ~m_pc~0) [L388] is_master_triggered_~__retres1~0 := 0; [L390] is_master_triggered_#res := is_master_triggered_~__retres1~0; [L955] activate_threads_#t~ret11 := is_master_triggered_#res; [L955] activate_threads_~tmp~1 := activate_threads_#t~ret11; [L955] havoc activate_threads_#t~ret11; [L957-L961] COND FALSE !(0 != activate_threads_~tmp~1) [L963] havoc is_transmit1_triggered_#res; [L963] havoc is_transmit1_triggered_~__retres1~1; [L394] havoc is_transmit1_triggered_~__retres1~1; [L397] COND FALSE !(1 == ~t1_pc~0) [L407] is_transmit1_triggered_~__retres1~1 := 0; [L409] is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; [L963] activate_threads_#t~ret12 := is_transmit1_triggered_#res; [L963] activate_threads_~tmp___0~0 := activate_threads_#t~ret12; [L963] havoc activate_threads_#t~ret12; [L965-L969] COND FALSE !(0 != activate_threads_~tmp___0~0) [L971] havoc is_transmit2_triggered_#res; [L971] havoc is_transmit2_triggered_~__retres1~2; [L413] havoc is_transmit2_triggered_~__retres1~2; [L416] COND FALSE !(1 == ~t2_pc~0) [L426] is_transmit2_triggered_~__retres1~2 := 0; [L428] is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; [L971] activate_threads_#t~ret13 := is_transmit2_triggered_#res; [L971] activate_threads_~tmp___1~0 := activate_threads_#t~ret13; [L971] havoc activate_threads_#t~ret13; [L973-L977] COND FALSE !(0 != activate_threads_~tmp___1~0) [L979] havoc is_transmit3_triggered_#res; [L979] havoc is_transmit3_triggered_~__retres1~3; [L432] havoc is_transmit3_triggered_~__retres1~3; [L435] COND FALSE !(1 == ~t3_pc~0) [L445] is_transmit3_triggered_~__retres1~3 := 0; [L447] is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; [L979] activate_threads_#t~ret14 := is_transmit3_triggered_#res; [L979] activate_threads_~tmp___2~0 := activate_threads_#t~ret14; [L979] havoc activate_threads_#t~ret14; [L981-L985] COND FALSE !(0 != activate_threads_~tmp___2~0) [L987] havoc is_transmit4_triggered_#res; [L987] havoc is_transmit4_triggered_~__retres1~4; [L451] havoc is_transmit4_triggered_~__retres1~4; [L454] COND FALSE !(1 == ~t4_pc~0) [L464] is_transmit4_triggered_~__retres1~4 := 0; [L466] is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; [L987] activate_threads_#t~ret15 := is_transmit4_triggered_#res; [L987] activate_threads_~tmp___3~0 := activate_threads_#t~ret15; [L987] havoc activate_threads_#t~ret15; [L989-L993] COND FALSE !(0 != activate_threads_~tmp___3~0) [L995] havoc is_transmit5_triggered_#res; [L995] havoc is_transmit5_triggered_~__retres1~5; [L470] havoc is_transmit5_triggered_~__retres1~5; [L473] COND FALSE !(1 == ~t5_pc~0) [L483] is_transmit5_triggered_~__retres1~5 := 0; [L485] is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; [L995] activate_threads_#t~ret16 := is_transmit5_triggered_#res; [L995] activate_threads_~tmp___4~0 := activate_threads_#t~ret16; [L995] havoc activate_threads_#t~ret16; [L997-L1001] COND FALSE !(0 != activate_threads_~tmp___4~0) [L1003] havoc is_transmit6_triggered_#res; [L1003] havoc is_transmit6_triggered_~__retres1~6; [L489] havoc is_transmit6_triggered_~__retres1~6; [L492] COND FALSE !(1 == ~t6_pc~0) [L502] is_transmit6_triggered_~__retres1~6 := 0; [L504] is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; [L1003] activate_threads_#t~ret17 := is_transmit6_triggered_#res; [L1003] activate_threads_~tmp___5~0 := activate_threads_#t~ret17; [L1003] havoc activate_threads_#t~ret17; [L1005-L1009] COND FALSE !(0 != activate_threads_~tmp___5~0) [L1011] havoc is_transmit7_triggered_#res; [L1011] havoc is_transmit7_triggered_~__retres1~7; [L508] havoc is_transmit7_triggered_~__retres1~7; [L511] COND FALSE !(1 == ~t7_pc~0) [L521] is_transmit7_triggered_~__retres1~7 := 0; [L523] is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; [L1011] activate_threads_#t~ret18 := is_transmit7_triggered_#res; [L1011] activate_threads_~tmp___6~0 := activate_threads_#t~ret18; [L1011] havoc activate_threads_#t~ret18; [L1013-L1017] COND FALSE !(0 != activate_threads_~tmp___6~0) [L859] COND FALSE !(1 == ~M_E~0) [L864] COND FALSE !(1 == ~T1_E~0) [L869] COND FALSE !(1 == ~T2_E~0) [L874] COND FALSE !(1 == ~T3_E~0) [L879] COND FALSE !(1 == ~T4_E~0) [L884] COND FALSE !(1 == ~T5_E~0) [L889] COND FALSE !(1 == ~T6_E~0) [L894] COND FALSE !(1 == ~T7_E~0) [L899] COND FALSE !(1 == ~E_M~0) [L904] COND FALSE !(1 == ~E_1~0) [L909] COND FALSE !(1 == ~E_2~0) [L914] COND FALSE !(1 == ~E_3~0) [L919] COND FALSE !(1 == ~E_4~0) [L924] COND FALSE !(1 == ~E_5~0) [L929] COND FALSE !(1 == ~E_6~0) [L934] COND FALSE !(1 == ~E_7~0) [L1180-L1217] COND FALSE !(false) [L1183] start_simulation_~kernel_st~0 := 1; [L1184] havoc eval_#t~ret2, eval_#t~nondet3, eval_~tmp_ndt_1~0, eval_#t~nondet4, eval_~tmp_ndt_2~0, eval_#t~nondet5, eval_~tmp_ndt_3~0, eval_#t~nondet6, eval_~tmp_ndt_4~0, eval_#t~nondet7, eval_~tmp_ndt_5~0, eval_#t~nondet8, eval_~tmp_ndt_6~0, eval_#t~nondet9, eval_~tmp_ndt_7~0, eval_#t~nondet10, eval_~tmp_ndt_8~0, eval_~tmp~0; [L634] havoc eval_~tmp~0; ----- ----- class de.uni_freiburg.informatik.ultimate.boogie.procedureinliner.backtranslation.InlinerBacktranslator [L14] ~m_pc~0 := 0; [L15] ~t1_pc~0 := 0; [L16] ~t2_pc~0 := 0; [L17] ~t3_pc~0 := 0; [L18] ~t4_pc~0 := 0; [L19] ~t5_pc~0 := 0; [L20] ~t6_pc~0 := 0; [L21] ~t7_pc~0 := 0; [L22] ~m_st~0 := 0; [L23] ~t1_st~0 := 0; [L24] ~t2_st~0 := 0; [L25] ~t3_st~0 := 0; [L26] ~t4_st~0 := 0; [L27] ~t5_st~0 := 0; [L28] ~t6_st~0 := 0; [L29] ~t7_st~0 := 0; [L30] ~m_i~0 := 0; [L31] ~t1_i~0 := 0; [L32] ~t2_i~0 := 0; [L33] ~t3_i~0 := 0; [L34] ~t4_i~0 := 0; [L35] ~t5_i~0 := 0; [L36] ~t6_i~0 := 0; [L37] ~t7_i~0 := 0; [L38] ~M_E~0 := 2; [L39] ~T1_E~0 := 2; [L40] ~T2_E~0 := 2; [L41] ~T3_E~0 := 2; [L42] ~T4_E~0 := 2; [L43] ~T5_E~0 := 2; [L44] ~T6_E~0 := 2; [L45] ~T7_E~0 := 2; [L46] ~E_M~0 := 2; [L47] ~E_1~0 := 2; [L48] ~E_2~0 := 2; [L49] ~E_3~0 := 2; [L50] ~E_4~0 := 2; [L51] ~E_5~0 := 2; [L52] ~E_6~0 := 2; [L53] ~E_7~0 := 2; [L63] ~token~0 := 0; [L65] ~local~0 := 0; [?] havoc main_#res; [?] havoc main_~__retres1~9; [L1225] havoc main_~__retres1~9; [L1134] ~m_i~0 := 1; [L1135] ~t1_i~0 := 1; [L1136] ~t2_i~0 := 1; [L1137] ~t3_i~0 := 1; [L1138] ~t4_i~0 := 1; [L1139] ~t5_i~0 := 1; [L1140] ~t6_i~0 := 1; [L1141] ~t7_i~0 := 1; [L1230] havoc start_simulation_#t~ret20, start_simulation_#t~ret21, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1; [L1166] havoc start_simulation_~kernel_st~0; [L1167] havoc start_simulation_~tmp~3; [L1168] havoc start_simulation_~tmp___0~1; [L1172] start_simulation_~kernel_st~0 := 0; [L538] COND TRUE 1 == ~m_i~0 [L539] ~m_st~0 := 0; [L543] COND TRUE 1 == ~t1_i~0 [L544] ~t1_st~0 := 0; [L548] COND TRUE 1 == ~t2_i~0 [L549] ~t2_st~0 := 0; [L553] COND TRUE 1 == ~t3_i~0 [L554] ~t3_st~0 := 0; [L558] COND TRUE 1 == ~t4_i~0 [L559] ~t4_st~0 := 0; [L563] COND TRUE 1 == ~t5_i~0 [L564] ~t5_st~0 := 0; [L568] COND TRUE 1 == ~t6_i~0 [L569] ~t6_st~0 := 0; [L573] COND TRUE 1 == ~t7_i~0 [L574] ~t7_st~0 := 0; [L771] COND FALSE !(0 == ~M_E~0) [L776] COND FALSE !(0 == ~T1_E~0) [L781] COND FALSE !(0 == ~T2_E~0) [L786] COND FALSE !(0 == ~T3_E~0) [L791] COND FALSE !(0 == ~T4_E~0) [L796] COND FALSE !(0 == ~T5_E~0) [L801] COND FALSE !(0 == ~T6_E~0) [L806] COND FALSE !(0 == ~T7_E~0) [L811] COND FALSE !(0 == ~E_M~0) [L816] COND FALSE !(0 == ~E_1~0) [L821] COND FALSE !(0 == ~E_2~0) [L826] COND FALSE !(0 == ~E_3~0) [L831] COND FALSE !(0 == ~E_4~0) [L836] COND FALSE !(0 == ~E_5~0) [L841] COND FALSE !(0 == ~E_6~0) [L846] COND FALSE !(0 == ~E_7~0) [L1176] havoc activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0; [L944] havoc activate_threads_~tmp~1; [L945] havoc activate_threads_~tmp___0~0; [L946] havoc activate_threads_~tmp___1~0; [L947] havoc activate_threads_~tmp___2~0; [L948] havoc activate_threads_~tmp___3~0; [L949] havoc activate_threads_~tmp___4~0; [L950] havoc activate_threads_~tmp___5~0; [L951] havoc activate_threads_~tmp___6~0; [L955] havoc is_master_triggered_#res; [L955] havoc is_master_triggered_~__retres1~0; [L375] havoc is_master_triggered_~__retres1~0; [L378] COND FALSE !(1 == ~m_pc~0) [L388] is_master_triggered_~__retres1~0 := 0; [L390] is_master_triggered_#res := is_master_triggered_~__retres1~0; [L955] activate_threads_#t~ret11 := is_master_triggered_#res; [L955] activate_threads_~tmp~1 := activate_threads_#t~ret11; [L955] havoc activate_threads_#t~ret11; [L957-L961] COND FALSE !(0 != activate_threads_~tmp~1) [L963] havoc is_transmit1_triggered_#res; [L963] havoc is_transmit1_triggered_~__retres1~1; [L394] havoc is_transmit1_triggered_~__retres1~1; [L397] COND FALSE !(1 == ~t1_pc~0) [L407] is_transmit1_triggered_~__retres1~1 := 0; [L409] is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; [L963] activate_threads_#t~ret12 := is_transmit1_triggered_#res; [L963] activate_threads_~tmp___0~0 := activate_threads_#t~ret12; [L963] havoc activate_threads_#t~ret12; [L965-L969] COND FALSE !(0 != activate_threads_~tmp___0~0) [L971] havoc is_transmit2_triggered_#res; [L971] havoc is_transmit2_triggered_~__retres1~2; [L413] havoc is_transmit2_triggered_~__retres1~2; [L416] COND FALSE !(1 == ~t2_pc~0) [L426] is_transmit2_triggered_~__retres1~2 := 0; [L428] is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; [L971] activate_threads_#t~ret13 := is_transmit2_triggered_#res; [L971] activate_threads_~tmp___1~0 := activate_threads_#t~ret13; [L971] havoc activate_threads_#t~ret13; [L973-L977] COND FALSE !(0 != activate_threads_~tmp___1~0) [L979] havoc is_transmit3_triggered_#res; [L979] havoc is_transmit3_triggered_~__retres1~3; [L432] havoc is_transmit3_triggered_~__retres1~3; [L435] COND FALSE !(1 == ~t3_pc~0) [L445] is_transmit3_triggered_~__retres1~3 := 0; [L447] is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; [L979] activate_threads_#t~ret14 := is_transmit3_triggered_#res; [L979] activate_threads_~tmp___2~0 := activate_threads_#t~ret14; [L979] havoc activate_threads_#t~ret14; [L981-L985] COND FALSE !(0 != activate_threads_~tmp___2~0) [L987] havoc is_transmit4_triggered_#res; [L987] havoc is_transmit4_triggered_~__retres1~4; [L451] havoc is_transmit4_triggered_~__retres1~4; [L454] COND FALSE !(1 == ~t4_pc~0) [L464] is_transmit4_triggered_~__retres1~4 := 0; [L466] is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; [L987] activate_threads_#t~ret15 := is_transmit4_triggered_#res; [L987] activate_threads_~tmp___3~0 := activate_threads_#t~ret15; [L987] havoc activate_threads_#t~ret15; [L989-L993] COND FALSE !(0 != activate_threads_~tmp___3~0) [L995] havoc is_transmit5_triggered_#res; [L995] havoc is_transmit5_triggered_~__retres1~5; [L470] havoc is_transmit5_triggered_~__retres1~5; [L473] COND FALSE !(1 == ~t5_pc~0) [L483] is_transmit5_triggered_~__retres1~5 := 0; [L485] is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; [L995] activate_threads_#t~ret16 := is_transmit5_triggered_#res; [L995] activate_threads_~tmp___4~0 := activate_threads_#t~ret16; [L995] havoc activate_threads_#t~ret16; [L997-L1001] COND FALSE !(0 != activate_threads_~tmp___4~0) [L1003] havoc is_transmit6_triggered_#res; [L1003] havoc is_transmit6_triggered_~__retres1~6; [L489] havoc is_transmit6_triggered_~__retres1~6; [L492] COND FALSE !(1 == ~t6_pc~0) [L502] is_transmit6_triggered_~__retres1~6 := 0; [L504] is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; [L1003] activate_threads_#t~ret17 := is_transmit6_triggered_#res; [L1003] activate_threads_~tmp___5~0 := activate_threads_#t~ret17; [L1003] havoc activate_threads_#t~ret17; [L1005-L1009] COND FALSE !(0 != activate_threads_~tmp___5~0) [L1011] havoc is_transmit7_triggered_#res; [L1011] havoc is_transmit7_triggered_~__retres1~7; [L508] havoc is_transmit7_triggered_~__retres1~7; [L511] COND FALSE !(1 == ~t7_pc~0) [L521] is_transmit7_triggered_~__retres1~7 := 0; [L523] is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; [L1011] activate_threads_#t~ret18 := is_transmit7_triggered_#res; [L1011] activate_threads_~tmp___6~0 := activate_threads_#t~ret18; [L1011] havoc activate_threads_#t~ret18; [L1013-L1017] COND FALSE !(0 != activate_threads_~tmp___6~0) [L859] COND FALSE !(1 == ~M_E~0) [L864] COND FALSE !(1 == ~T1_E~0) [L869] COND FALSE !(1 == ~T2_E~0) [L874] COND FALSE !(1 == ~T3_E~0) [L879] COND FALSE !(1 == ~T4_E~0) [L884] COND FALSE !(1 == ~T5_E~0) [L889] COND FALSE !(1 == ~T6_E~0) [L894] COND FALSE !(1 == ~T7_E~0) [L899] COND FALSE !(1 == ~E_M~0) [L904] COND FALSE !(1 == ~E_1~0) [L909] COND FALSE !(1 == ~E_2~0) [L914] COND FALSE !(1 == ~E_3~0) [L919] COND FALSE !(1 == ~E_4~0) [L924] COND FALSE !(1 == ~E_5~0) [L929] COND FALSE !(1 == ~E_6~0) [L934] COND FALSE !(1 == ~E_7~0) [L1180-L1217] COND FALSE !(false) [L1183] start_simulation_~kernel_st~0 := 1; [L1184] havoc eval_#t~ret2, eval_#t~nondet3, eval_~tmp_ndt_1~0, eval_#t~nondet4, eval_~tmp_ndt_2~0, eval_#t~nondet5, eval_~tmp_ndt_3~0, eval_#t~nondet6, eval_~tmp_ndt_4~0, eval_#t~nondet7, eval_~tmp_ndt_5~0, eval_#t~nondet8, eval_~tmp_ndt_6~0, eval_#t~nondet9, eval_~tmp_ndt_7~0, eval_#t~nondet10, eval_~tmp_ndt_8~0, eval_~tmp~0; [L634] havoc eval_~tmp~0; [L14] ~m_pc~0 := 0; [L15] ~t1_pc~0 := 0; [L16] ~t2_pc~0 := 0; [L17] ~t3_pc~0 := 0; [L18] ~t4_pc~0 := 0; [L19] ~t5_pc~0 := 0; [L20] ~t6_pc~0 := 0; [L21] ~t7_pc~0 := 0; [L22] ~m_st~0 := 0; [L23] ~t1_st~0 := 0; [L24] ~t2_st~0 := 0; [L25] ~t3_st~0 := 0; [L26] ~t4_st~0 := 0; [L27] ~t5_st~0 := 0; [L28] ~t6_st~0 := 0; [L29] ~t7_st~0 := 0; [L30] ~m_i~0 := 0; [L31] ~t1_i~0 := 0; [L32] ~t2_i~0 := 0; [L33] ~t3_i~0 := 0; [L34] ~t4_i~0 := 0; [L35] ~t5_i~0 := 0; [L36] ~t6_i~0 := 0; [L37] ~t7_i~0 := 0; [L38] ~M_E~0 := 2; [L39] ~T1_E~0 := 2; [L40] ~T2_E~0 := 2; [L41] ~T3_E~0 := 2; [L42] ~T4_E~0 := 2; [L43] ~T5_E~0 := 2; [L44] ~T6_E~0 := 2; [L45] ~T7_E~0 := 2; [L46] ~E_M~0 := 2; [L47] ~E_1~0 := 2; [L48] ~E_2~0 := 2; [L49] ~E_3~0 := 2; [L50] ~E_4~0 := 2; [L51] ~E_5~0 := 2; [L52] ~E_6~0 := 2; [L53] ~E_7~0 := 2; [L63] ~token~0 := 0; [L65] ~local~0 := 0; [L1225] havoc ~__retres1~9; [L1134] ~m_i~0 := 1; [L1135] ~t1_i~0 := 1; [L1136] ~t2_i~0 := 1; [L1137] ~t3_i~0 := 1; [L1138] ~t4_i~0 := 1; [L1139] ~t5_i~0 := 1; [L1140] ~t6_i~0 := 1; [L1141] ~t7_i~0 := 1; [L1166] havoc ~kernel_st~0; [L1167] havoc ~tmp~3; [L1168] havoc ~tmp___0~1; [L1172] ~kernel_st~0 := 0; [L538] COND TRUE 1 == ~m_i~0 [L539] ~m_st~0 := 0; [L543] COND TRUE 1 == ~t1_i~0 [L544] ~t1_st~0 := 0; [L548] COND TRUE 1 == ~t2_i~0 [L549] ~t2_st~0 := 0; [L553] COND TRUE 1 == ~t3_i~0 [L554] ~t3_st~0 := 0; [L558] COND TRUE 1 == ~t4_i~0 [L559] ~t4_st~0 := 0; [L563] COND TRUE 1 == ~t5_i~0 [L564] ~t5_st~0 := 0; [L568] COND TRUE 1 == ~t6_i~0 [L569] ~t6_st~0 := 0; [L573] COND TRUE 1 == ~t7_i~0 [L574] ~t7_st~0 := 0; [L771] COND FALSE !(0 == ~M_E~0) [L776] COND FALSE !(0 == ~T1_E~0) [L781] COND FALSE !(0 == ~T2_E~0) [L786] COND FALSE !(0 == ~T3_E~0) [L791] COND FALSE !(0 == ~T4_E~0) [L796] COND FALSE !(0 == ~T5_E~0) [L801] COND FALSE !(0 == ~T6_E~0) [L806] COND FALSE !(0 == ~T7_E~0) [L811] COND FALSE !(0 == ~E_M~0) [L816] COND FALSE !(0 == ~E_1~0) [L821] COND FALSE !(0 == ~E_2~0) [L826] COND FALSE !(0 == ~E_3~0) [L831] COND FALSE !(0 == ~E_4~0) [L836] COND FALSE !(0 == ~E_5~0) [L841] COND FALSE !(0 == ~E_6~0) [L846] COND FALSE !(0 == ~E_7~0) [L944] havoc ~tmp~1; [L945] havoc ~tmp___0~0; [L946] havoc ~tmp___1~0; [L947] havoc ~tmp___2~0; [L948] havoc ~tmp___3~0; [L949] havoc ~tmp___4~0; [L950] havoc ~tmp___5~0; [L951] havoc ~tmp___6~0; [L375] havoc ~__retres1~0; [L378] COND FALSE !(1 == ~m_pc~0) [L388] ~__retres1~0 := 0; [L390] #res := ~__retres1~0; [L955] ~tmp~1 := #t~ret11; [L955] havoc #t~ret11; [L957-L961] COND FALSE !(0 != ~tmp~1) [L394] havoc ~__retres1~1; [L397] COND FALSE !(1 == ~t1_pc~0) [L407] ~__retres1~1 := 0; [L409] #res := ~__retres1~1; [L963] ~tmp___0~0 := #t~ret12; [L963] havoc #t~ret12; [L965-L969] COND FALSE !(0 != ~tmp___0~0) [L413] havoc ~__retres1~2; [L416] COND FALSE !(1 == ~t2_pc~0) [L426] ~__retres1~2 := 0; [L428] #res := ~__retres1~2; [L971] ~tmp___1~0 := #t~ret13; [L971] havoc #t~ret13; [L973-L977] COND FALSE !(0 != ~tmp___1~0) [L432] havoc ~__retres1~3; [L435] COND FALSE !(1 == ~t3_pc~0) [L445] ~__retres1~3 := 0; [L447] #res := ~__retres1~3; [L979] ~tmp___2~0 := #t~ret14; [L979] havoc #t~ret14; [L981-L985] COND FALSE !(0 != ~tmp___2~0) [L451] havoc ~__retres1~4; [L454] COND FALSE !(1 == ~t4_pc~0) [L464] ~__retres1~4 := 0; [L466] #res := ~__retres1~4; [L987] ~tmp___3~0 := #t~ret15; [L987] havoc #t~ret15; [L989-L993] COND FALSE !(0 != ~tmp___3~0) [L470] havoc ~__retres1~5; [L473] COND FALSE !(1 == ~t5_pc~0) [L483] ~__retres1~5 := 0; [L485] #res := ~__retres1~5; [L995] ~tmp___4~0 := #t~ret16; [L995] havoc #t~ret16; [L997-L1001] COND FALSE !(0 != ~tmp___4~0) [L489] havoc ~__retres1~6; [L492] COND FALSE !(1 == ~t6_pc~0) [L502] ~__retres1~6 := 0; [L504] #res := ~__retres1~6; [L1003] ~tmp___5~0 := #t~ret17; [L1003] havoc #t~ret17; [L1005-L1009] COND FALSE !(0 != ~tmp___5~0) [L508] havoc ~__retres1~7; [L511] COND FALSE !(1 == ~t7_pc~0) [L521] ~__retres1~7 := 0; [L523] #res := ~__retres1~7; [L1011] ~tmp___6~0 := #t~ret18; [L1011] havoc #t~ret18; [L1013-L1017] COND FALSE !(0 != ~tmp___6~0) [L859] COND FALSE !(1 == ~M_E~0) [L864] COND FALSE !(1 == ~T1_E~0) [L869] COND FALSE !(1 == ~T2_E~0) [L874] COND FALSE !(1 == ~T3_E~0) [L879] COND FALSE !(1 == ~T4_E~0) [L884] COND FALSE !(1 == ~T5_E~0) [L889] COND FALSE !(1 == ~T6_E~0) [L894] COND FALSE !(1 == ~T7_E~0) [L899] COND FALSE !(1 == ~E_M~0) [L904] COND FALSE !(1 == ~E_1~0) [L909] COND FALSE !(1 == ~E_2~0) [L914] COND FALSE !(1 == ~E_3~0) [L919] COND FALSE !(1 == ~E_4~0) [L924] COND FALSE !(1 == ~E_5~0) [L929] COND FALSE !(1 == ~E_6~0) [L934] COND FALSE !(1 == ~E_7~0) [L1180-L1217] COND FALSE !(false) [L1183] ~kernel_st~0 := 1; [L634] havoc ~tmp~0; ----- ----- class de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.CACSL2BoogieBacktranslator [L14] ~m_pc~0 := 0; [L15] ~t1_pc~0 := 0; [L16] ~t2_pc~0 := 0; [L17] ~t3_pc~0 := 0; [L18] ~t4_pc~0 := 0; [L19] ~t5_pc~0 := 0; [L20] ~t6_pc~0 := 0; [L21] ~t7_pc~0 := 0; [L22] ~m_st~0 := 0; [L23] ~t1_st~0 := 0; [L24] ~t2_st~0 := 0; [L25] ~t3_st~0 := 0; [L26] ~t4_st~0 := 0; [L27] ~t5_st~0 := 0; [L28] ~t6_st~0 := 0; [L29] ~t7_st~0 := 0; [L30] ~m_i~0 := 0; [L31] ~t1_i~0 := 0; [L32] ~t2_i~0 := 0; [L33] ~t3_i~0 := 0; [L34] ~t4_i~0 := 0; [L35] ~t5_i~0 := 0; [L36] ~t6_i~0 := 0; [L37] ~t7_i~0 := 0; [L38] ~M_E~0 := 2; [L39] ~T1_E~0 := 2; [L40] ~T2_E~0 := 2; [L41] ~T3_E~0 := 2; [L42] ~T4_E~0 := 2; [L43] ~T5_E~0 := 2; [L44] ~T6_E~0 := 2; [L45] ~T7_E~0 := 2; [L46] ~E_M~0 := 2; [L47] ~E_1~0 := 2; [L48] ~E_2~0 := 2; [L49] ~E_3~0 := 2; [L50] ~E_4~0 := 2; [L51] ~E_5~0 := 2; [L52] ~E_6~0 := 2; [L53] ~E_7~0 := 2; [L63] ~token~0 := 0; [L65] ~local~0 := 0; [L1225] havoc ~__retres1~9; [L1134] ~m_i~0 := 1; [L1135] ~t1_i~0 := 1; [L1136] ~t2_i~0 := 1; [L1137] ~t3_i~0 := 1; [L1138] ~t4_i~0 := 1; [L1139] ~t5_i~0 := 1; [L1140] ~t6_i~0 := 1; [L1141] ~t7_i~0 := 1; [L1166] havoc ~kernel_st~0; [L1167] havoc ~tmp~3; [L1168] havoc ~tmp___0~1; [L1172] ~kernel_st~0 := 0; [L538] COND TRUE 1 == ~m_i~0 [L539] ~m_st~0 := 0; [L543] COND TRUE 1 == ~t1_i~0 [L544] ~t1_st~0 := 0; [L548] COND TRUE 1 == ~t2_i~0 [L549] ~t2_st~0 := 0; [L553] COND TRUE 1 == ~t3_i~0 [L554] ~t3_st~0 := 0; [L558] COND TRUE 1 == ~t4_i~0 [L559] ~t4_st~0 := 0; [L563] COND TRUE 1 == ~t5_i~0 [L564] ~t5_st~0 := 0; [L568] COND TRUE 1 == ~t6_i~0 [L569] ~t6_st~0 := 0; [L573] COND TRUE 1 == ~t7_i~0 [L574] ~t7_st~0 := 0; [L771] COND FALSE !(0 == ~M_E~0) [L776] COND FALSE !(0 == ~T1_E~0) [L781] COND FALSE !(0 == ~T2_E~0) [L786] COND FALSE !(0 == ~T3_E~0) [L791] COND FALSE !(0 == ~T4_E~0) [L796] COND FALSE !(0 == ~T5_E~0) [L801] COND FALSE !(0 == ~T6_E~0) [L806] COND FALSE !(0 == ~T7_E~0) [L811] COND FALSE !(0 == ~E_M~0) [L816] COND FALSE !(0 == ~E_1~0) [L821] COND FALSE !(0 == ~E_2~0) [L826] COND FALSE !(0 == ~E_3~0) [L831] COND FALSE !(0 == ~E_4~0) [L836] COND FALSE !(0 == ~E_5~0) [L841] COND FALSE !(0 == ~E_6~0) [L846] COND FALSE !(0 == ~E_7~0) [L944] havoc ~tmp~1; [L945] havoc ~tmp___0~0; [L946] havoc ~tmp___1~0; [L947] havoc ~tmp___2~0; [L948] havoc ~tmp___3~0; [L949] havoc ~tmp___4~0; [L950] havoc ~tmp___5~0; [L951] havoc ~tmp___6~0; [L375] havoc ~__retres1~0; [L378] COND FALSE !(1 == ~m_pc~0) [L388] ~__retres1~0 := 0; [L390] #res := ~__retres1~0; [L955] ~tmp~1 := #t~ret11; [L955] havoc #t~ret11; [L957-L961] COND FALSE !(0 != ~tmp~1) [L394] havoc ~__retres1~1; [L397] COND FALSE !(1 == ~t1_pc~0) [L407] ~__retres1~1 := 0; [L409] #res := ~__retres1~1; [L963] ~tmp___0~0 := #t~ret12; [L963] havoc #t~ret12; [L965-L969] COND FALSE !(0 != ~tmp___0~0) [L413] havoc ~__retres1~2; [L416] COND FALSE !(1 == ~t2_pc~0) [L426] ~__retres1~2 := 0; [L428] #res := ~__retres1~2; [L971] ~tmp___1~0 := #t~ret13; [L971] havoc #t~ret13; [L973-L977] COND FALSE !(0 != ~tmp___1~0) [L432] havoc ~__retres1~3; [L435] COND FALSE !(1 == ~t3_pc~0) [L445] ~__retres1~3 := 0; [L447] #res := ~__retres1~3; [L979] ~tmp___2~0 := #t~ret14; [L979] havoc #t~ret14; [L981-L985] COND FALSE !(0 != ~tmp___2~0) [L451] havoc ~__retres1~4; [L454] COND FALSE !(1 == ~t4_pc~0) [L464] ~__retres1~4 := 0; [L466] #res := ~__retres1~4; [L987] ~tmp___3~0 := #t~ret15; [L987] havoc #t~ret15; [L989-L993] COND FALSE !(0 != ~tmp___3~0) [L470] havoc ~__retres1~5; [L473] COND FALSE !(1 == ~t5_pc~0) [L483] ~__retres1~5 := 0; [L485] #res := ~__retres1~5; [L995] ~tmp___4~0 := #t~ret16; [L995] havoc #t~ret16; [L997-L1001] COND FALSE !(0 != ~tmp___4~0) [L489] havoc ~__retres1~6; [L492] COND FALSE !(1 == ~t6_pc~0) [L502] ~__retres1~6 := 0; [L504] #res := ~__retres1~6; [L1003] ~tmp___5~0 := #t~ret17; [L1003] havoc #t~ret17; [L1005-L1009] COND FALSE !(0 != ~tmp___5~0) [L508] havoc ~__retres1~7; [L511] COND FALSE !(1 == ~t7_pc~0) [L521] ~__retres1~7 := 0; [L523] #res := ~__retres1~7; [L1011] ~tmp___6~0 := #t~ret18; [L1011] havoc #t~ret18; [L1013-L1017] COND FALSE !(0 != ~tmp___6~0) [L859] COND FALSE !(1 == ~M_E~0) [L864] COND FALSE !(1 == ~T1_E~0) [L869] COND FALSE !(1 == ~T2_E~0) [L874] COND FALSE !(1 == ~T3_E~0) [L879] COND FALSE !(1 == ~T4_E~0) [L884] COND FALSE !(1 == ~T5_E~0) [L889] COND FALSE !(1 == ~T6_E~0) [L894] COND FALSE !(1 == ~T7_E~0) [L899] COND FALSE !(1 == ~E_M~0) [L904] COND FALSE !(1 == ~E_1~0) [L909] COND FALSE !(1 == ~E_2~0) [L914] COND FALSE !(1 == ~E_3~0) [L919] COND FALSE !(1 == ~E_4~0) [L924] COND FALSE !(1 == ~E_5~0) [L929] COND FALSE !(1 == ~E_6~0) [L934] COND FALSE !(1 == ~E_7~0) [L1180-L1217] COND FALSE !(false) [L1183] ~kernel_st~0 := 1; [L634] havoc ~tmp~0; [L14] int m_pc = 0; [L15] int t1_pc = 0; [L16] int t2_pc = 0; [L17] int t3_pc = 0; [L18] int t4_pc = 0; [L19] int t5_pc = 0; [L20] int t6_pc = 0; [L21] int t7_pc = 0; [L22] int m_st ; [L23] int t1_st ; [L24] int t2_st ; [L25] int t3_st ; [L26] int t4_st ; [L27] int t5_st ; [L28] int t6_st ; [L29] int t7_st ; [L30] int m_i ; [L31] int t1_i ; [L32] int t2_i ; [L33] int t3_i ; [L34] int t4_i ; [L35] int t5_i ; [L36] int t6_i ; [L37] int t7_i ; [L38] int M_E = 2; [L39] int T1_E = 2; [L40] int T2_E = 2; [L41] int T3_E = 2; [L42] int T4_E = 2; [L43] int T5_E = 2; [L44] int T6_E = 2; [L45] int T7_E = 2; [L46] int E_M = 2; [L47] int E_1 = 2; [L48] int E_2 = 2; [L49] int E_3 = 2; [L50] int E_4 = 2; [L51] int E_5 = 2; [L52] int E_6 = 2; [L53] int E_7 = 2; [L63] int token ; [L65] int local ; [L1225] int __retres1 ; [L1134] m_i = 1 [L1135] t1_i = 1 [L1136] t2_i = 1 [L1137] t3_i = 1 [L1138] t4_i = 1 [L1139] t5_i = 1 [L1140] t6_i = 1 [L1141] t7_i = 1 [L1166] int kernel_st ; [L1167] int tmp ; [L1168] int tmp___0 ; [L1172] kernel_st = 0 [L538] COND TRUE m_i == 1 [L539] m_st = 0 [L543] COND TRUE t1_i == 1 [L544] t1_st = 0 [L548] COND TRUE t2_i == 1 [L549] t2_st = 0 [L553] COND TRUE t3_i == 1 [L554] t3_st = 0 [L558] COND TRUE t4_i == 1 [L559] t4_st = 0 [L563] COND TRUE t5_i == 1 [L564] t5_st = 0 [L568] COND TRUE t6_i == 1 [L569] t6_st = 0 [L573] COND TRUE t7_i == 1 [L574] t7_st = 0 [L771] COND FALSE !(M_E == 0) [L776] COND FALSE !(T1_E == 0) [L781] COND FALSE !(T2_E == 0) [L786] COND FALSE !(T3_E == 0) [L791] COND FALSE !(T4_E == 0) [L796] COND FALSE !(T5_E == 0) [L801] COND FALSE !(T6_E == 0) [L806] COND FALSE !(T7_E == 0) [L811] COND FALSE !(E_M == 0) [L816] COND FALSE !(E_1 == 0) [L821] COND FALSE !(E_2 == 0) [L826] COND FALSE !(E_3 == 0) [L831] COND FALSE !(E_4 == 0) [L836] COND FALSE !(E_5 == 0) [L841] COND FALSE !(E_6 == 0) [L846] COND FALSE !(E_7 == 0) [L944] int tmp ; [L945] int tmp___0 ; [L946] int tmp___1 ; [L947] int tmp___2 ; [L948] int tmp___3 ; [L949] int tmp___4 ; [L950] int tmp___5 ; [L951] int tmp___6 ; [L375] int __retres1 ; [L378] COND FALSE !(m_pc == 1) [L388] __retres1 = 0 [L390] return (__retres1); [L955] tmp = is_master_triggered() [L957] COND FALSE !(\read(tmp)) [L394] int __retres1 ; [L397] COND FALSE !(t1_pc == 1) [L407] __retres1 = 0 [L409] return (__retres1); [L963] tmp___0 = is_transmit1_triggered() [L965] COND FALSE !(\read(tmp___0)) [L413] int __retres1 ; [L416] COND FALSE !(t2_pc == 1) [L426] __retres1 = 0 [L428] return (__retres1); [L971] tmp___1 = is_transmit2_triggered() [L973] COND FALSE !(\read(tmp___1)) [L432] int __retres1 ; [L435] COND FALSE !(t3_pc == 1) [L445] __retres1 = 0 [L447] return (__retres1); [L979] tmp___2 = is_transmit3_triggered() [L981] COND FALSE !(\read(tmp___2)) [L451] int __retres1 ; [L454] COND FALSE !(t4_pc == 1) [L464] __retres1 = 0 [L466] return (__retres1); [L987] tmp___3 = is_transmit4_triggered() [L989] COND FALSE !(\read(tmp___3)) [L470] int __retres1 ; [L473] COND FALSE !(t5_pc == 1) [L483] __retres1 = 0 [L485] return (__retres1); [L995] tmp___4 = is_transmit5_triggered() [L997] COND FALSE !(\read(tmp___4)) [L489] int __retres1 ; [L492] COND FALSE !(t6_pc == 1) [L502] __retres1 = 0 [L504] return (__retres1); [L1003] tmp___5 = is_transmit6_triggered() [L1005] COND FALSE !(\read(tmp___5)) [L508] int __retres1 ; [L511] COND FALSE !(t7_pc == 1) [L521] __retres1 = 0 [L523] return (__retres1); [L1011] tmp___6 = is_transmit7_triggered() [L1013] COND FALSE !(\read(tmp___6)) [L859] COND FALSE !(M_E == 1) [L864] COND FALSE !(T1_E == 1) [L869] COND FALSE !(T2_E == 1) [L874] COND FALSE !(T3_E == 1) [L879] COND FALSE !(T4_E == 1) [L884] COND FALSE !(T5_E == 1) [L889] COND FALSE !(T6_E == 1) [L894] COND FALSE !(T7_E == 1) [L899] COND FALSE !(E_M == 1) [L904] COND FALSE !(E_1 == 1) [L909] COND FALSE !(E_2 == 1) [L914] COND FALSE !(E_3 == 1) [L919] COND FALSE !(E_4 == 1) [L924] COND FALSE !(E_5 == 1) [L929] COND FALSE !(E_6 == 1) [L934] COND FALSE !(E_7 == 1) [L1180] COND TRUE 1 [L1183] kernel_st = 1 [L634] int tmp ; ----- ----- class de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder.RCFGBacktranslator [?] assume !false; [?] havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~8;havoc exists_runnable_thread_~__retres1~8; [?] assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8 := 1; [?] exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; [?] eval_#t~ret2 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret2;havoc eval_#t~ret2; [?] assume 0 != eval_~tmp~0; [?] assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0;eval_~tmp_ndt_1~0 := eval_#t~nondet3;havoc eval_#t~nondet3; [?] assume !(0 != eval_~tmp_ndt_1~0); [?] assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0;eval_~tmp_ndt_2~0 := eval_#t~nondet4;havoc eval_#t~nondet4; [?] assume !(0 != eval_~tmp_ndt_2~0); [?] assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0;eval_~tmp_ndt_3~0 := eval_#t~nondet5;havoc eval_#t~nondet5; [?] assume !(0 != eval_~tmp_ndt_3~0); [?] assume 0 == ~t3_st~0;havoc eval_~tmp_ndt_4~0;eval_~tmp_ndt_4~0 := eval_#t~nondet6;havoc eval_#t~nondet6; [?] assume !(0 != eval_~tmp_ndt_4~0); [?] assume 0 == ~t4_st~0;havoc eval_~tmp_ndt_5~0;eval_~tmp_ndt_5~0 := eval_#t~nondet7;havoc eval_#t~nondet7; [?] assume !(0 != eval_~tmp_ndt_5~0); [?] assume 0 == ~t5_st~0;havoc eval_~tmp_ndt_6~0;eval_~tmp_ndt_6~0 := eval_#t~nondet8;havoc eval_#t~nondet8; [?] assume !(0 != eval_~tmp_ndt_6~0); [?] assume 0 == ~t6_st~0;havoc eval_~tmp_ndt_7~0;eval_~tmp_ndt_7~0 := eval_#t~nondet9;havoc eval_#t~nondet9; [?] assume !(0 != eval_~tmp_ndt_7~0); [?] assume 0 == ~t7_st~0;havoc eval_~tmp_ndt_8~0;eval_~tmp_ndt_8~0 := eval_#t~nondet10;havoc eval_#t~nondet10; [?] assume !(0 != eval_~tmp_ndt_8~0); [L638-L760] assume !false; [L641] havoc exists_runnable_thread_#res; [L641] havoc exists_runnable_thread_~__retres1~8; [L583] havoc exists_runnable_thread_~__retres1~8; [L586-L626] assume 0 == ~m_st~0; [L587] exists_runnable_thread_~__retres1~8 := 1; [L629] exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; [L641] eval_#t~ret2 := exists_runnable_thread_#res; [L641] eval_~tmp~0 := eval_#t~ret2; [L641] havoc eval_#t~ret2; [L643-L647] assume 0 != eval_~tmp~0; [L648-L661] assume 0 == ~m_st~0; [L649] havoc eval_~tmp_ndt_1~0; [L650] eval_~tmp_ndt_1~0 := eval_#t~nondet3; [L650] havoc eval_#t~nondet3; [L651-L658] assume !(0 != eval_~tmp_ndt_1~0); [L662-L675] assume 0 == ~t1_st~0; [L663] havoc eval_~tmp_ndt_2~0; [L664] eval_~tmp_ndt_2~0 := eval_#t~nondet4; [L664] havoc eval_#t~nondet4; [L665-L672] assume !(0 != eval_~tmp_ndt_2~0); [L676-L689] assume 0 == ~t2_st~0; [L677] havoc eval_~tmp_ndt_3~0; [L678] eval_~tmp_ndt_3~0 := eval_#t~nondet5; [L678] havoc eval_#t~nondet5; [L679-L686] assume !(0 != eval_~tmp_ndt_3~0); [L690-L703] assume 0 == ~t3_st~0; [L691] havoc eval_~tmp_ndt_4~0; [L692] eval_~tmp_ndt_4~0 := eval_#t~nondet6; [L692] havoc eval_#t~nondet6; [L693-L700] assume !(0 != eval_~tmp_ndt_4~0); [L704-L717] assume 0 == ~t4_st~0; [L705] havoc eval_~tmp_ndt_5~0; [L706] eval_~tmp_ndt_5~0 := eval_#t~nondet7; [L706] havoc eval_#t~nondet7; [L707-L714] assume !(0 != eval_~tmp_ndt_5~0); [L718-L731] assume 0 == ~t5_st~0; [L719] havoc eval_~tmp_ndt_6~0; [L720] eval_~tmp_ndt_6~0 := eval_#t~nondet8; [L720] havoc eval_#t~nondet8; [L721-L728] assume !(0 != eval_~tmp_ndt_6~0); [L732-L745] assume 0 == ~t6_st~0; [L733] havoc eval_~tmp_ndt_7~0; [L734] eval_~tmp_ndt_7~0 := eval_#t~nondet9; [L734] havoc eval_#t~nondet9; [L735-L742] assume !(0 != eval_~tmp_ndt_7~0); [L746-L759] assume 0 == ~t7_st~0; [L747] havoc eval_~tmp_ndt_8~0; [L748] eval_~tmp_ndt_8~0 := eval_#t~nondet10; [L748] havoc eval_#t~nondet10; [L749-L756] assume !(0 != eval_~tmp_ndt_8~0); ----- ----- class de.uni_freiburg.informatik.ultimate.boogie.preprocessor.BoogiePreprocessorBacktranslator [L638-L760] assume !false; [L641] havoc exists_runnable_thread_#res; [L641] havoc exists_runnable_thread_~__retres1~8; [L583] havoc exists_runnable_thread_~__retres1~8; [L586-L626] assume 0 == ~m_st~0; [L587] exists_runnable_thread_~__retres1~8 := 1; [L629] exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; [L641] eval_#t~ret2 := exists_runnable_thread_#res; [L641] eval_~tmp~0 := eval_#t~ret2; [L641] havoc eval_#t~ret2; [L643-L647] assume 0 != eval_~tmp~0; [L648-L661] assume 0 == ~m_st~0; [L649] havoc eval_~tmp_ndt_1~0; [L650] eval_~tmp_ndt_1~0 := eval_#t~nondet3; [L650] havoc eval_#t~nondet3; [L651-L658] assume !(0 != eval_~tmp_ndt_1~0); [L662-L675] assume 0 == ~t1_st~0; [L663] havoc eval_~tmp_ndt_2~0; [L664] eval_~tmp_ndt_2~0 := eval_#t~nondet4; [L664] havoc eval_#t~nondet4; [L665-L672] assume !(0 != eval_~tmp_ndt_2~0); [L676-L689] assume 0 == ~t2_st~0; [L677] havoc eval_~tmp_ndt_3~0; [L678] eval_~tmp_ndt_3~0 := eval_#t~nondet5; [L678] havoc eval_#t~nondet5; [L679-L686] assume !(0 != eval_~tmp_ndt_3~0); [L690-L703] assume 0 == ~t3_st~0; [L691] havoc eval_~tmp_ndt_4~0; [L692] eval_~tmp_ndt_4~0 := eval_#t~nondet6; [L692] havoc eval_#t~nondet6; [L693-L700] assume !(0 != eval_~tmp_ndt_4~0); [L704-L717] assume 0 == ~t4_st~0; [L705] havoc eval_~tmp_ndt_5~0; [L706] eval_~tmp_ndt_5~0 := eval_#t~nondet7; [L706] havoc eval_#t~nondet7; [L707-L714] assume !(0 != eval_~tmp_ndt_5~0); [L718-L731] assume 0 == ~t5_st~0; [L719] havoc eval_~tmp_ndt_6~0; [L720] eval_~tmp_ndt_6~0 := eval_#t~nondet8; [L720] havoc eval_#t~nondet8; [L721-L728] assume !(0 != eval_~tmp_ndt_6~0); [L732-L745] assume 0 == ~t6_st~0; [L733] havoc eval_~tmp_ndt_7~0; [L734] eval_~tmp_ndt_7~0 := eval_#t~nondet9; [L734] havoc eval_#t~nondet9; [L735-L742] assume !(0 != eval_~tmp_ndt_7~0); [L746-L759] assume 0 == ~t7_st~0; [L747] havoc eval_~tmp_ndt_8~0; [L748] eval_~tmp_ndt_8~0 := eval_#t~nondet10; [L748] havoc eval_#t~nondet10; [L749-L756] assume !(0 != eval_~tmp_ndt_8~0); [L638-L760] COND FALSE !(false) [L641] havoc exists_runnable_thread_#res; [L641] havoc exists_runnable_thread_~__retres1~8; [L583] havoc exists_runnable_thread_~__retres1~8; [L586] COND TRUE 0 == ~m_st~0 [L587] exists_runnable_thread_~__retres1~8 := 1; [L629] exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; [L641] eval_#t~ret2 := exists_runnable_thread_#res; [L641] eval_~tmp~0 := eval_#t~ret2; [L641] havoc eval_#t~ret2; [L643-L647] COND TRUE 0 != eval_~tmp~0 [L648] COND TRUE 0 == ~m_st~0 [L649] havoc eval_~tmp_ndt_1~0; [L650] eval_~tmp_ndt_1~0 := eval_#t~nondet3; [L650] havoc eval_#t~nondet3; [L651-L658] COND FALSE !(0 != eval_~tmp_ndt_1~0) [L662] COND TRUE 0 == ~t1_st~0 [L663] havoc eval_~tmp_ndt_2~0; [L664] eval_~tmp_ndt_2~0 := eval_#t~nondet4; [L664] havoc eval_#t~nondet4; [L665-L672] COND FALSE !(0 != eval_~tmp_ndt_2~0) [L676] COND TRUE 0 == ~t2_st~0 [L677] havoc eval_~tmp_ndt_3~0; [L678] eval_~tmp_ndt_3~0 := eval_#t~nondet5; [L678] havoc eval_#t~nondet5; [L679-L686] COND FALSE !(0 != eval_~tmp_ndt_3~0) [L690] COND TRUE 0 == ~t3_st~0 [L691] havoc eval_~tmp_ndt_4~0; [L692] eval_~tmp_ndt_4~0 := eval_#t~nondet6; [L692] havoc eval_#t~nondet6; [L693-L700] COND FALSE !(0 != eval_~tmp_ndt_4~0) [L704] COND TRUE 0 == ~t4_st~0 [L705] havoc eval_~tmp_ndt_5~0; [L706] eval_~tmp_ndt_5~0 := eval_#t~nondet7; [L706] havoc eval_#t~nondet7; [L707-L714] COND FALSE !(0 != eval_~tmp_ndt_5~0) [L718] COND TRUE 0 == ~t5_st~0 [L719] havoc eval_~tmp_ndt_6~0; [L720] eval_~tmp_ndt_6~0 := eval_#t~nondet8; [L720] havoc eval_#t~nondet8; [L721-L728] COND FALSE !(0 != eval_~tmp_ndt_6~0) [L732] COND TRUE 0 == ~t6_st~0 [L733] havoc eval_~tmp_ndt_7~0; [L734] eval_~tmp_ndt_7~0 := eval_#t~nondet9; [L734] havoc eval_#t~nondet9; [L735-L742] COND FALSE !(0 != eval_~tmp_ndt_7~0) [L746] COND TRUE 0 == ~t7_st~0 [L747] havoc eval_~tmp_ndt_8~0; [L748] eval_~tmp_ndt_8~0 := eval_#t~nondet10; [L748] havoc eval_#t~nondet10; [L749-L756] COND FALSE !(0 != eval_~tmp_ndt_8~0) ----- ----- class de.uni_freiburg.informatik.ultimate.boogie.procedureinliner.backtranslation.InlinerBacktranslator [L638-L760] COND FALSE !(false) [L641] havoc exists_runnable_thread_#res; [L641] havoc exists_runnable_thread_~__retres1~8; [L583] havoc exists_runnable_thread_~__retres1~8; [L586] COND TRUE 0 == ~m_st~0 [L587] exists_runnable_thread_~__retres1~8 := 1; [L629] exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; [L641] eval_#t~ret2 := exists_runnable_thread_#res; [L641] eval_~tmp~0 := eval_#t~ret2; [L641] havoc eval_#t~ret2; [L643-L647] COND TRUE 0 != eval_~tmp~0 [L648] COND TRUE 0 == ~m_st~0 [L649] havoc eval_~tmp_ndt_1~0; [L650] eval_~tmp_ndt_1~0 := eval_#t~nondet3; [L650] havoc eval_#t~nondet3; [L651-L658] COND FALSE !(0 != eval_~tmp_ndt_1~0) [L662] COND TRUE 0 == ~t1_st~0 [L663] havoc eval_~tmp_ndt_2~0; [L664] eval_~tmp_ndt_2~0 := eval_#t~nondet4; [L664] havoc eval_#t~nondet4; [L665-L672] COND FALSE !(0 != eval_~tmp_ndt_2~0) [L676] COND TRUE 0 == ~t2_st~0 [L677] havoc eval_~tmp_ndt_3~0; [L678] eval_~tmp_ndt_3~0 := eval_#t~nondet5; [L678] havoc eval_#t~nondet5; [L679-L686] COND FALSE !(0 != eval_~tmp_ndt_3~0) [L690] COND TRUE 0 == ~t3_st~0 [L691] havoc eval_~tmp_ndt_4~0; [L692] eval_~tmp_ndt_4~0 := eval_#t~nondet6; [L692] havoc eval_#t~nondet6; [L693-L700] COND FALSE !(0 != eval_~tmp_ndt_4~0) [L704] COND TRUE 0 == ~t4_st~0 [L705] havoc eval_~tmp_ndt_5~0; [L706] eval_~tmp_ndt_5~0 := eval_#t~nondet7; [L706] havoc eval_#t~nondet7; [L707-L714] COND FALSE !(0 != eval_~tmp_ndt_5~0) [L718] COND TRUE 0 == ~t5_st~0 [L719] havoc eval_~tmp_ndt_6~0; [L720] eval_~tmp_ndt_6~0 := eval_#t~nondet8; [L720] havoc eval_#t~nondet8; [L721-L728] COND FALSE !(0 != eval_~tmp_ndt_6~0) [L732] COND TRUE 0 == ~t6_st~0 [L733] havoc eval_~tmp_ndt_7~0; [L734] eval_~tmp_ndt_7~0 := eval_#t~nondet9; [L734] havoc eval_#t~nondet9; [L735-L742] COND FALSE !(0 != eval_~tmp_ndt_7~0) [L746] COND TRUE 0 == ~t7_st~0 [L747] havoc eval_~tmp_ndt_8~0; [L748] eval_~tmp_ndt_8~0 := eval_#t~nondet10; [L748] havoc eval_#t~nondet10; [L749-L756] COND FALSE !(0 != eval_~tmp_ndt_8~0) [L638-L760] COND FALSE !(false) [L583] havoc ~__retres1~8; [L586] COND TRUE 0 == ~m_st~0 [L587] ~__retres1~8 := 1; [L629] #res := ~__retres1~8; [L641] ~tmp~0 := #t~ret2; [L641] havoc #t~ret2; [L643-L647] COND TRUE 0 != ~tmp~0 [L648] COND TRUE 0 == ~m_st~0 [L649] havoc ~tmp_ndt_1~0; [L650] ~tmp_ndt_1~0 := #t~nondet3; [L650] havoc #t~nondet3; [L651-L658] COND FALSE !(0 != ~tmp_ndt_1~0) [L662] COND TRUE 0 == ~t1_st~0 [L663] havoc ~tmp_ndt_2~0; [L664] ~tmp_ndt_2~0 := #t~nondet4; [L664] havoc #t~nondet4; [L665-L672] COND FALSE !(0 != ~tmp_ndt_2~0) [L676] COND TRUE 0 == ~t2_st~0 [L677] havoc ~tmp_ndt_3~0; [L678] ~tmp_ndt_3~0 := #t~nondet5; [L678] havoc #t~nondet5; [L679-L686] COND FALSE !(0 != ~tmp_ndt_3~0) [L690] COND TRUE 0 == ~t3_st~0 [L691] havoc ~tmp_ndt_4~0; [L692] ~tmp_ndt_4~0 := #t~nondet6; [L692] havoc #t~nondet6; [L693-L700] COND FALSE !(0 != ~tmp_ndt_4~0) [L704] COND TRUE 0 == ~t4_st~0 [L705] havoc ~tmp_ndt_5~0; [L706] ~tmp_ndt_5~0 := #t~nondet7; [L706] havoc #t~nondet7; [L707-L714] COND FALSE !(0 != ~tmp_ndt_5~0) [L718] COND TRUE 0 == ~t5_st~0 [L719] havoc ~tmp_ndt_6~0; [L720] ~tmp_ndt_6~0 := #t~nondet8; [L720] havoc #t~nondet8; [L721-L728] COND FALSE !(0 != ~tmp_ndt_6~0) [L732] COND TRUE 0 == ~t6_st~0 [L733] havoc ~tmp_ndt_7~0; [L734] ~tmp_ndt_7~0 := #t~nondet9; [L734] havoc #t~nondet9; [L735-L742] COND FALSE !(0 != ~tmp_ndt_7~0) [L746] COND TRUE 0 == ~t7_st~0 [L747] havoc ~tmp_ndt_8~0; [L748] ~tmp_ndt_8~0 := #t~nondet10; [L748] havoc #t~nondet10; [L749-L756] COND FALSE !(0 != ~tmp_ndt_8~0) ----- ----- class de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.CACSL2BoogieBacktranslator [L638-L760] COND FALSE !(false) [L583] havoc ~__retres1~8; [L586] COND TRUE 0 == ~m_st~0 [L587] ~__retres1~8 := 1; [L629] #res := ~__retres1~8; [L641] ~tmp~0 := #t~ret2; [L641] havoc #t~ret2; [L643-L647] COND TRUE 0 != ~tmp~0 [L648] COND TRUE 0 == ~m_st~0 [L649] havoc ~tmp_ndt_1~0; [L650] ~tmp_ndt_1~0 := #t~nondet3; [L650] havoc #t~nondet3; [L651-L658] COND FALSE !(0 != ~tmp_ndt_1~0) [L662] COND TRUE 0 == ~t1_st~0 [L663] havoc ~tmp_ndt_2~0; [L664] ~tmp_ndt_2~0 := #t~nondet4; [L664] havoc #t~nondet4; [L665-L672] COND FALSE !(0 != ~tmp_ndt_2~0) [L676] COND TRUE 0 == ~t2_st~0 [L677] havoc ~tmp_ndt_3~0; [L678] ~tmp_ndt_3~0 := #t~nondet5; [L678] havoc #t~nondet5; [L679-L686] COND FALSE !(0 != ~tmp_ndt_3~0) [L690] COND TRUE 0 == ~t3_st~0 [L691] havoc ~tmp_ndt_4~0; [L692] ~tmp_ndt_4~0 := #t~nondet6; [L692] havoc #t~nondet6; [L693-L700] COND FALSE !(0 != ~tmp_ndt_4~0) [L704] COND TRUE 0 == ~t4_st~0 [L705] havoc ~tmp_ndt_5~0; [L706] ~tmp_ndt_5~0 := #t~nondet7; [L706] havoc #t~nondet7; [L707-L714] COND FALSE !(0 != ~tmp_ndt_5~0) [L718] COND TRUE 0 == ~t5_st~0 [L719] havoc ~tmp_ndt_6~0; [L720] ~tmp_ndt_6~0 := #t~nondet8; [L720] havoc #t~nondet8; [L721-L728] COND FALSE !(0 != ~tmp_ndt_6~0) [L732] COND TRUE 0 == ~t6_st~0 [L733] havoc ~tmp_ndt_7~0; [L734] ~tmp_ndt_7~0 := #t~nondet9; [L734] havoc #t~nondet9; [L735-L742] COND FALSE !(0 != ~tmp_ndt_7~0) [L746] COND TRUE 0 == ~t7_st~0 [L747] havoc ~tmp_ndt_8~0; [L748] ~tmp_ndt_8~0 := #t~nondet10; [L748] havoc #t~nondet10; [L749-L756] COND FALSE !(0 != ~tmp_ndt_8~0) [L638] COND TRUE 1 [L583] int __retres1 ; [L586] COND TRUE m_st == 0 [L587] __retres1 = 1 [L629] return (__retres1); [L641] tmp = exists_runnable_thread() [L643] COND TRUE \read(tmp) [L648] COND TRUE m_st == 0 [L649] int tmp_ndt_1; [L650] tmp_ndt_1 = __VERIFIER_nondet_int() [L651] COND FALSE !(\read(tmp_ndt_1)) [L662] COND TRUE t1_st == 0 [L663] int tmp_ndt_2; [L664] tmp_ndt_2 = __VERIFIER_nondet_int() [L665] COND FALSE !(\read(tmp_ndt_2)) [L676] COND TRUE t2_st == 0 [L677] int tmp_ndt_3; [L678] tmp_ndt_3 = __VERIFIER_nondet_int() [L679] COND FALSE !(\read(tmp_ndt_3)) [L690] COND TRUE t3_st == 0 [L691] int tmp_ndt_4; [L692] tmp_ndt_4 = __VERIFIER_nondet_int() [L693] COND FALSE !(\read(tmp_ndt_4)) [L704] COND TRUE t4_st == 0 [L705] int tmp_ndt_5; [L706] tmp_ndt_5 = __VERIFIER_nondet_int() [L707] COND FALSE !(\read(tmp_ndt_5)) [L718] COND TRUE t5_st == 0 [L719] int tmp_ndt_6; [L720] tmp_ndt_6 = __VERIFIER_nondet_int() [L721] COND FALSE !(\read(tmp_ndt_6)) [L732] COND TRUE t6_st == 0 [L733] int tmp_ndt_7; [L734] tmp_ndt_7 = __VERIFIER_nondet_int() [L735] COND FALSE !(\read(tmp_ndt_7)) [L746] COND TRUE t7_st == 0 [L747] int tmp_ndt_8; [L748] tmp_ndt_8 = __VERIFIER_nondet_int() [L749] COND FALSE !(\read(tmp_ndt_8)) ----- Found a nonterminating execution for the following lasso shaped sequence of statements. Stem: [L14] int m_pc = 0; [L15] int t1_pc = 0; [L16] int t2_pc = 0; [L17] int t3_pc = 0; [L18] int t4_pc = 0; [L19] int t5_pc = 0; [L20] int t6_pc = 0; [L21] int t7_pc = 0; [L22] int m_st ; [L23] int t1_st ; [L24] int t2_st ; [L25] int t3_st ; [L26] int t4_st ; [L27] int t5_st ; [L28] int t6_st ; [L29] int t7_st ; [L30] int m_i ; [L31] int t1_i ; [L32] int t2_i ; [L33] int t3_i ; [L34] int t4_i ; [L35] int t5_i ; [L36] int t6_i ; [L37] int t7_i ; [L38] int M_E = 2; [L39] int T1_E = 2; [L40] int T2_E = 2; [L41] int T3_E = 2; [L42] int T4_E = 2; [L43] int T5_E = 2; [L44] int T6_E = 2; [L45] int T7_E = 2; [L46] int E_M = 2; [L47] int E_1 = 2; [L48] int E_2 = 2; [L49] int E_3 = 2; [L50] int E_4 = 2; [L51] int E_5 = 2; [L52] int E_6 = 2; [L53] int E_7 = 2; [L63] int token ; [L65] int local ; [L1225] int __retres1 ; [L1134] m_i = 1 [L1135] t1_i = 1 [L1136] t2_i = 1 [L1137] t3_i = 1 [L1138] t4_i = 1 [L1139] t5_i = 1 [L1140] t6_i = 1 [L1141] t7_i = 1 [L1166] int kernel_st ; [L1167] int tmp ; [L1168] int tmp___0 ; [L1172] kernel_st = 0 [L538] COND TRUE m_i == 1 [L539] m_st = 0 [L543] COND TRUE t1_i == 1 [L544] t1_st = 0 [L548] COND TRUE t2_i == 1 [L549] t2_st = 0 [L553] COND TRUE t3_i == 1 [L554] t3_st = 0 [L558] COND TRUE t4_i == 1 [L559] t4_st = 0 [L563] COND TRUE t5_i == 1 [L564] t5_st = 0 [L568] COND TRUE t6_i == 1 [L569] t6_st = 0 [L573] COND TRUE t7_i == 1 [L574] t7_st = 0 [L771] COND FALSE !(M_E == 0) [L776] COND FALSE !(T1_E == 0) [L781] COND FALSE !(T2_E == 0) [L786] COND FALSE !(T3_E == 0) [L791] COND FALSE !(T4_E == 0) [L796] COND FALSE !(T5_E == 0) [L801] COND FALSE !(T6_E == 0) [L806] COND FALSE !(T7_E == 0) [L811] COND FALSE !(E_M == 0) [L816] COND FALSE !(E_1 == 0) [L821] COND FALSE !(E_2 == 0) [L826] COND FALSE !(E_3 == 0) [L831] COND FALSE !(E_4 == 0) [L836] COND FALSE !(E_5 == 0) [L841] COND FALSE !(E_6 == 0) [L846] COND FALSE !(E_7 == 0) [L944] int tmp ; [L945] int tmp___0 ; [L946] int tmp___1 ; [L947] int tmp___2 ; [L948] int tmp___3 ; [L949] int tmp___4 ; [L950] int tmp___5 ; [L951] int tmp___6 ; [L375] int __retres1 ; [L378] COND FALSE !(m_pc == 1) [L388] __retres1 = 0 [L390] return (__retres1); [L955] tmp = is_master_triggered() [L957] COND FALSE !(\read(tmp)) [L394] int __retres1 ; [L397] COND FALSE !(t1_pc == 1) [L407] __retres1 = 0 [L409] return (__retres1); [L963] tmp___0 = is_transmit1_triggered() [L965] COND FALSE !(\read(tmp___0)) [L413] int __retres1 ; [L416] COND FALSE !(t2_pc == 1) [L426] __retres1 = 0 [L428] return (__retres1); [L971] tmp___1 = is_transmit2_triggered() [L973] COND FALSE !(\read(tmp___1)) [L432] int __retres1 ; [L435] COND FALSE !(t3_pc == 1) [L445] __retres1 = 0 [L447] return (__retres1); [L979] tmp___2 = is_transmit3_triggered() [L981] COND FALSE !(\read(tmp___2)) [L451] int __retres1 ; [L454] COND FALSE !(t4_pc == 1) [L464] __retres1 = 0 [L466] return (__retres1); [L987] tmp___3 = is_transmit4_triggered() [L989] COND FALSE !(\read(tmp___3)) [L470] int __retres1 ; [L473] COND FALSE !(t5_pc == 1) [L483] __retres1 = 0 [L485] return (__retres1); [L995] tmp___4 = is_transmit5_triggered() [L997] COND FALSE !(\read(tmp___4)) [L489] int __retres1 ; [L492] COND FALSE !(t6_pc == 1) [L502] __retres1 = 0 [L504] return (__retres1); [L1003] tmp___5 = is_transmit6_triggered() [L1005] COND FALSE !(\read(tmp___5)) [L508] int __retres1 ; [L511] COND FALSE !(t7_pc == 1) [L521] __retres1 = 0 [L523] return (__retres1); [L1011] tmp___6 = is_transmit7_triggered() [L1013] COND FALSE !(\read(tmp___6)) [L859] COND FALSE !(M_E == 1) [L864] COND FALSE !(T1_E == 1) [L869] COND FALSE !(T2_E == 1) [L874] COND FALSE !(T3_E == 1) [L879] COND FALSE !(T4_E == 1) [L884] COND FALSE !(T5_E == 1) [L889] COND FALSE !(T6_E == 1) [L894] COND FALSE !(T7_E == 1) [L899] COND FALSE !(E_M == 1) [L904] COND FALSE !(E_1 == 1) [L909] COND FALSE !(E_2 == 1) [L914] COND FALSE !(E_3 == 1) [L919] COND FALSE !(E_4 == 1) [L924] COND FALSE !(E_5 == 1) [L929] COND FALSE !(E_6 == 1) [L934] COND FALSE !(E_7 == 1) [L1180] COND TRUE 1 [L1183] kernel_st = 1 [L634] int tmp ; Loop: [L638] COND TRUE 1 [L583] int __retres1 ; [L586] COND TRUE m_st == 0 [L587] __retres1 = 1 [L629] return (__retres1); [L641] tmp = exists_runnable_thread() [L643] COND TRUE \read(tmp) [L648] COND TRUE m_st == 0 [L649] int tmp_ndt_1; [L650] tmp_ndt_1 = __VERIFIER_nondet_int() [L651] COND FALSE !(\read(tmp_ndt_1)) [L662] COND TRUE t1_st == 0 [L663] int tmp_ndt_2; [L664] tmp_ndt_2 = __VERIFIER_nondet_int() [L665] COND FALSE !(\read(tmp_ndt_2)) [L676] COND TRUE t2_st == 0 [L677] int tmp_ndt_3; [L678] tmp_ndt_3 = __VERIFIER_nondet_int() [L679] COND FALSE !(\read(tmp_ndt_3)) [L690] COND TRUE t3_st == 0 [L691] int tmp_ndt_4; [L692] tmp_ndt_4 = __VERIFIER_nondet_int() [L693] COND FALSE !(\read(tmp_ndt_4)) [L704] COND TRUE t4_st == 0 [L705] int tmp_ndt_5; [L706] tmp_ndt_5 = __VERIFIER_nondet_int() [L707] COND FALSE !(\read(tmp_ndt_5)) [L718] COND TRUE t5_st == 0 [L719] int tmp_ndt_6; [L720] tmp_ndt_6 = __VERIFIER_nondet_int() [L721] COND FALSE !(\read(tmp_ndt_6)) [L732] COND TRUE t6_st == 0 [L733] int tmp_ndt_7; [L734] tmp_ndt_7 = __VERIFIER_nondet_int() [L735] COND FALSE !(\read(tmp_ndt_7)) [L746] COND TRUE t7_st == 0 [L747] int tmp_ndt_8; [L748] tmp_ndt_8 = __VERIFIER_nondet_int() [L749] COND FALSE !(\read(tmp_ndt_8)) End of lasso representation. RESULT: Ultimate proved your program to be incorrect! Received shutdown request...