./Ultimate.py --spec ../../sv-benchmarks/c/properties/termination.prp --file ../../sv-benchmarks/c/systemc/transmitter.04_false-unreach-call_false-termination.cil.c --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for termination Using default analysis Version aa418289 Calling Ultimate with: java -Dosgi.configuration.area=/tmp/vcloud-vcloud-master/worker/working_dir_4e85c2a5-7fb1-4118-9476-ba8baa068460/bin-2019/uautomizer/data/config -Xmx12G -Xms1G -jar /tmp/vcloud-vcloud-master/worker/working_dir_4e85c2a5-7fb1-4118-9476-ba8baa068460/bin-2019/uautomizer/plugins/org.eclipse.equinox.launcher_1.3.100.v20150511-1540.jar -data @noDefault -ultimatedata /tmp/vcloud-vcloud-master/worker/working_dir_4e85c2a5-7fb1-4118-9476-ba8baa068460/bin-2019/uautomizer/data -tc /tmp/vcloud-vcloud-master/worker/working_dir_4e85c2a5-7fb1-4118-9476-ba8baa068460/bin-2019/uautomizer/config/AutomizerTermination.xml -i ../../sv-benchmarks/c/systemc/transmitter.04_false-unreach-call_false-termination.cil.c -s /tmp/vcloud-vcloud-master/worker/working_dir_4e85c2a5-7fb1-4118-9476-ba8baa068460/bin-2019/uautomizer/config/svcomp-Termination-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud-vcloud-master/worker/working_dir_4e85c2a5-7fb1-4118-9476-ba8baa068460/bin-2019/uautomizer --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash bcbeb24241e70d50816527d1472e428919d63db5 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Execution finished normally Writing output log to file Ultimate.log Writing human readable error path to file UltimateCounterExample.errorpath Result: FALSE(TERM) --- Real Ultimate output --- This is Ultimate 0.1.23-aa41828 [2018-11-23 12:43:35,499 INFO L170 SettingsManager]: Resetting all preferences to default values... [2018-11-23 12:43:35,500 INFO L174 SettingsManager]: Resetting UltimateCore preferences to default values [2018-11-23 12:43:35,507 INFO L177 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2018-11-23 12:43:35,507 INFO L174 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2018-11-23 12:43:35,507 INFO L174 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2018-11-23 12:43:35,508 INFO L174 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2018-11-23 12:43:35,509 INFO L174 SettingsManager]: Resetting LassoRanker preferences to default values [2018-11-23 12:43:35,510 INFO L174 SettingsManager]: Resetting Reaching Definitions preferences to default values [2018-11-23 12:43:35,511 INFO L174 SettingsManager]: Resetting SyntaxChecker preferences to default values [2018-11-23 12:43:35,511 INFO L177 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2018-11-23 12:43:35,511 INFO L174 SettingsManager]: Resetting LTL2Aut preferences to default values [2018-11-23 12:43:35,512 INFO L174 SettingsManager]: Resetting PEA to Boogie preferences to default values [2018-11-23 12:43:35,513 INFO L174 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2018-11-23 12:43:35,514 INFO L174 SettingsManager]: Resetting ChcToBoogie preferences to default values [2018-11-23 12:43:35,515 INFO L174 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2018-11-23 12:43:35,515 INFO L174 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2018-11-23 12:43:35,516 INFO L174 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2018-11-23 12:43:35,518 INFO L174 SettingsManager]: Resetting CodeCheck preferences to default values [2018-11-23 12:43:35,519 INFO L174 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2018-11-23 12:43:35,520 INFO L174 SettingsManager]: Resetting RCFGBuilder preferences to default values [2018-11-23 12:43:35,520 INFO L174 SettingsManager]: Resetting TraceAbstraction preferences to default values [2018-11-23 12:43:35,521 INFO L177 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2018-11-23 12:43:35,521 INFO L177 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2018-11-23 12:43:35,521 INFO L174 SettingsManager]: Resetting TreeAutomizer preferences to default values [2018-11-23 12:43:35,522 INFO L174 SettingsManager]: Resetting IcfgTransformer preferences to default values [2018-11-23 12:43:35,523 INFO L174 SettingsManager]: Resetting Boogie Printer preferences to default values [2018-11-23 12:43:35,523 INFO L174 SettingsManager]: Resetting ReqPrinter preferences to default values [2018-11-23 12:43:35,524 INFO L174 SettingsManager]: Resetting Witness Printer preferences to default values [2018-11-23 12:43:35,525 INFO L177 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2018-11-23 12:43:35,525 INFO L174 SettingsManager]: Resetting CDTParser preferences to default values [2018-11-23 12:43:35,525 INFO L177 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2018-11-23 12:43:35,525 INFO L177 SettingsManager]: ReqParser provides no preferences, ignoring... [2018-11-23 12:43:35,525 INFO L174 SettingsManager]: Resetting SmtParser preferences to default values [2018-11-23 12:43:35,526 INFO L174 SettingsManager]: Resetting Witness Parser preferences to default values [2018-11-23 12:43:35,527 INFO L181 SettingsManager]: Finished resetting all preferences to default values... [2018-11-23 12:43:35,527 INFO L98 SettingsManager]: Beginning loading settings from /tmp/vcloud-vcloud-master/worker/working_dir_4e85c2a5-7fb1-4118-9476-ba8baa068460/bin-2019/uautomizer/config/svcomp-Termination-32bit-Automizer_Default.epf [2018-11-23 12:43:35,536 INFO L110 SettingsManager]: Loading preferences was successful [2018-11-23 12:43:35,536 INFO L112 SettingsManager]: Preferences different from defaults after loading the file: [2018-11-23 12:43:35,537 INFO L131 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2018-11-23 12:43:35,537 INFO L133 SettingsManager]: * Create parallel compositions if possible=false [2018-11-23 12:43:35,537 INFO L133 SettingsManager]: * Use SBE=true [2018-11-23 12:43:35,537 INFO L131 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: [2018-11-23 12:43:35,537 INFO L133 SettingsManager]: * NCSB implementation=INTSET_LAZY3 [2018-11-23 12:43:35,538 INFO L133 SettingsManager]: * Use old map elimination=false [2018-11-23 12:43:35,538 INFO L133 SettingsManager]: * Use external solver (rank synthesis)=false [2018-11-23 12:43:35,538 INFO L133 SettingsManager]: * Use only trivial implications for array writes=true [2018-11-23 12:43:35,538 INFO L133 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES [2018-11-23 12:43:35,538 INFO L131 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2018-11-23 12:43:35,538 INFO L133 SettingsManager]: * sizeof long=4 [2018-11-23 12:43:35,538 INFO L133 SettingsManager]: * Check unreachability of error function in SV-COMP mode=false [2018-11-23 12:43:35,538 INFO L133 SettingsManager]: * Overapproximate operations on floating types=true [2018-11-23 12:43:35,539 INFO L133 SettingsManager]: * sizeof POINTER=4 [2018-11-23 12:43:35,539 INFO L133 SettingsManager]: * Check division by zero=IGNORE [2018-11-23 12:43:35,539 INFO L133 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME [2018-11-23 12:43:35,539 INFO L133 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME [2018-11-23 12:43:35,539 INFO L133 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME [2018-11-23 12:43:35,539 INFO L133 SettingsManager]: * sizeof long double=12 [2018-11-23 12:43:35,539 INFO L133 SettingsManager]: * Check if freed pointer was valid=false [2018-11-23 12:43:35,539 INFO L133 SettingsManager]: * Assume nondeterminstic values are in range=false [2018-11-23 12:43:35,540 INFO L133 SettingsManager]: * Use constant arrays=true [2018-11-23 12:43:35,540 INFO L133 SettingsManager]: * Pointer base address is valid at dereference=ASSUME [2018-11-23 12:43:35,540 INFO L131 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2018-11-23 12:43:35,540 INFO L133 SettingsManager]: * Size of a code block=SequenceOfStatements [2018-11-23 12:43:35,540 INFO L133 SettingsManager]: * To the following directory=/home/matthias/ultimate/dump [2018-11-23 12:43:35,540 INFO L131 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2018-11-23 12:43:35,540 INFO L133 SettingsManager]: * Trace refinement strategy=CAMEL [2018-11-23 12:43:35,541 INFO L133 SettingsManager]: * Dump automata to the following directory=/home/matthias/ultimate/dump/auto [2018-11-23 12:43:35,541 INFO L131 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2018-11-23 12:43:35,541 INFO L133 SettingsManager]: * TransformationType=MODULO_NEIGHBOR Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud-vcloud-master/worker/working_dir_4e85c2a5-7fb1-4118-9476-ba8baa068460/bin-2019/uautomizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> bcbeb24241e70d50816527d1472e428919d63db5 [2018-11-23 12:43:35,563 INFO L81 nceAwareModelManager]: Repository-Root is: /tmp [2018-11-23 12:43:35,571 INFO L258 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2018-11-23 12:43:35,573 INFO L214 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2018-11-23 12:43:35,574 INFO L271 PluginConnector]: Initializing CDTParser... [2018-11-23 12:43:35,574 INFO L276 PluginConnector]: CDTParser initialized [2018-11-23 12:43:35,575 INFO L418 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud-vcloud-master/worker/working_dir_4e85c2a5-7fb1-4118-9476-ba8baa068460/bin-2019/uautomizer/../../sv-benchmarks/c/systemc/transmitter.04_false-unreach-call_false-termination.cil.c [2018-11-23 12:43:35,611 INFO L221 CDTParser]: Created temporary CDT project at /tmp/vcloud-vcloud-master/worker/working_dir_4e85c2a5-7fb1-4118-9476-ba8baa068460/bin-2019/uautomizer/data/f8da15940/8ed7b0844ec244a7af173ed83698a025/FLAGb62d9d7bf [2018-11-23 12:43:36,028 INFO L307 CDTParser]: Found 1 translation units. [2018-11-23 12:43:36,028 INFO L161 CDTParser]: Scanning /tmp/vcloud-vcloud-master/worker/working_dir_4e85c2a5-7fb1-4118-9476-ba8baa068460/sv-benchmarks/c/systemc/transmitter.04_false-unreach-call_false-termination.cil.c [2018-11-23 12:43:36,036 INFO L355 CDTParser]: About to delete temporary CDT project at /tmp/vcloud-vcloud-master/worker/working_dir_4e85c2a5-7fb1-4118-9476-ba8baa068460/bin-2019/uautomizer/data/f8da15940/8ed7b0844ec244a7af173ed83698a025/FLAGb62d9d7bf [2018-11-23 12:43:36,047 INFO L363 CDTParser]: Successfully deleted /tmp/vcloud-vcloud-master/worker/working_dir_4e85c2a5-7fb1-4118-9476-ba8baa068460/bin-2019/uautomizer/data/f8da15940/8ed7b0844ec244a7af173ed83698a025 [2018-11-23 12:43:36,049 INFO L296 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2018-11-23 12:43:36,050 INFO L131 ToolchainWalker]: Walking toolchain with 6 elements. [2018-11-23 12:43:36,051 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2018-11-23 12:43:36,051 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2018-11-23 12:43:36,054 INFO L276 PluginConnector]: CACSL2BoogieTranslator initialized [2018-11-23 12:43:36,054 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 23.11 12:43:36" (1/1) ... [2018-11-23 12:43:36,056 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@2ebf8353 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 12:43:36, skipping insertion in model container [2018-11-23 12:43:36,057 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 23.11 12:43:36" (1/1) ... [2018-11-23 12:43:36,064 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2018-11-23 12:43:36,090 INFO L176 MainTranslator]: Built tables and reachable declarations [2018-11-23 12:43:36,264 INFO L201 PostProcessor]: Analyzing one entry point: main [2018-11-23 12:43:36,268 INFO L191 MainTranslator]: Completed pre-run [2018-11-23 12:43:36,304 INFO L201 PostProcessor]: Analyzing one entry point: main [2018-11-23 12:43:36,318 INFO L195 MainTranslator]: Completed translation [2018-11-23 12:43:36,318 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 12:43:36 WrapperNode [2018-11-23 12:43:36,318 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2018-11-23 12:43:36,319 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2018-11-23 12:43:36,319 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2018-11-23 12:43:36,319 INFO L276 PluginConnector]: Boogie Procedure Inliner initialized [2018-11-23 12:43:36,324 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 12:43:36" (1/1) ... [2018-11-23 12:43:36,330 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 12:43:36" (1/1) ... [2018-11-23 12:43:36,401 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2018-11-23 12:43:36,402 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2018-11-23 12:43:36,402 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2018-11-23 12:43:36,402 INFO L276 PluginConnector]: Boogie Preprocessor initialized [2018-11-23 12:43:36,411 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 12:43:36" (1/1) ... [2018-11-23 12:43:36,412 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 12:43:36" (1/1) ... [2018-11-23 12:43:36,419 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 12:43:36" (1/1) ... [2018-11-23 12:43:36,419 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 12:43:36" (1/1) ... [2018-11-23 12:43:36,428 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 12:43:36" (1/1) ... [2018-11-23 12:43:36,440 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 12:43:36" (1/1) ... [2018-11-23 12:43:36,443 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 12:43:36" (1/1) ... [2018-11-23 12:43:36,448 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2018-11-23 12:43:36,448 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2018-11-23 12:43:36,448 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2018-11-23 12:43:36,448 INFO L276 PluginConnector]: RCFGBuilder initialized [2018-11-23 12:43:36,450 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 12:43:36" (1/1) ... No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_4e85c2a5-7fb1-4118-9476-ba8baa068460/bin-2019/uautomizer/z3 Starting monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2018-11-23 12:43:36,494 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2018-11-23 12:43:36,495 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2018-11-23 12:43:37,224 INFO L275 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2018-11-23 12:43:37,224 INFO L280 CfgBuilder]: Removed 148 assue(true) statements. [2018-11-23 12:43:37,224 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 23.11 12:43:37 BoogieIcfgContainer [2018-11-23 12:43:37,225 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2018-11-23 12:43:37,225 INFO L113 PluginConnector]: ------------------------BuchiAutomizer---------------------------- [2018-11-23 12:43:37,225 INFO L271 PluginConnector]: Initializing BuchiAutomizer... [2018-11-23 12:43:37,228 INFO L276 PluginConnector]: BuchiAutomizer initialized [2018-11-23 12:43:37,229 INFO L102 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2018-11-23 12:43:37,229 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 23.11 12:43:36" (1/3) ... [2018-11-23 12:43:37,230 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@49aa7b45 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 23.11 12:43:37, skipping insertion in model container [2018-11-23 12:43:37,230 INFO L102 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2018-11-23 12:43:37,230 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 12:43:36" (2/3) ... [2018-11-23 12:43:37,230 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@49aa7b45 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 23.11 12:43:37, skipping insertion in model container [2018-11-23 12:43:37,230 INFO L102 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2018-11-23 12:43:37,230 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 23.11 12:43:37" (3/3) ... [2018-11-23 12:43:37,232 INFO L375 chiAutomizerObserver]: Analyzing ICFG transmitter.04_false-unreach-call_false-termination.cil.c [2018-11-23 12:43:37,273 INFO L133 ementStrategyFactory]: Using default assertion order modulation [2018-11-23 12:43:37,274 INFO L374 BuchiCegarLoop]: Interprodecural is true [2018-11-23 12:43:37,274 INFO L375 BuchiCegarLoop]: Hoare is false [2018-11-23 12:43:37,274 INFO L376 BuchiCegarLoop]: Compute interpolants for ForwardPredicates [2018-11-23 12:43:37,274 INFO L377 BuchiCegarLoop]: Backedges is STRAIGHT_LINE [2018-11-23 12:43:37,274 INFO L378 BuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2018-11-23 12:43:37,274 INFO L379 BuchiCegarLoop]: Difference is false [2018-11-23 12:43:37,274 INFO L380 BuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2018-11-23 12:43:37,274 INFO L383 BuchiCegarLoop]: ======== Iteration 0==of CEGAR loop == BuchiCegarLoop======== [2018-11-23 12:43:37,293 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 373 states. [2018-11-23 12:43:37,322 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 308 [2018-11-23 12:43:37,322 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-23 12:43:37,322 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-23 12:43:37,331 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 12:43:37,331 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 12:43:37,331 INFO L442 BuchiCegarLoop]: ======== Iteration 1============ [2018-11-23 12:43:37,331 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 373 states. [2018-11-23 12:43:37,338 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 308 [2018-11-23 12:43:37,338 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-23 12:43:37,338 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-23 12:43:37,340 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 12:43:37,340 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 12:43:37,347 INFO L794 eck$LassoCheckResult]: Stem: 125#ULTIMATE.startENTRYtrue ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2; 17#L-1true havoc main_#res;havoc main_~__retres1~6;havoc main_~__retres1~6;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 301#L729true havoc start_simulation_#t~ret12, start_simulation_#t~ret13, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 162#L324true assume !(1 == ~m_i~0);~m_st~0 := 2; 256#L331-1true assume 1 == ~t1_i~0;~t1_st~0 := 0; 101#L336-1true assume !(1 == ~t2_i~0);~t2_st~0 := 2; 122#L341-1true assume !(1 == ~t3_i~0);~t3_st~0 := 2; 165#L346-1true assume !(1 == ~t4_i~0);~t4_st~0 := 2; 19#L351-1true assume !(0 == ~M_E~0); 357#L492-1true assume !(0 == ~T1_E~0); 214#L497-1true assume !(0 == ~T2_E~0); 243#L502-1true assume !(0 == ~T3_E~0); 259#L507-1true assume 0 == ~T4_E~0;~T4_E~0 := 1; 121#L512-1true assume !(0 == ~E_1~0); 134#L517-1true assume !(0 == ~E_2~0); 176#L522-1true assume !(0 == ~E_3~0); 32#L527-1true assume !(0 == ~E_4~0); 51#L532-1true havoc activate_threads_#t~ret6, activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 340#L228true assume !(1 == ~m_pc~0); 329#L228-2true is_master_triggered_~__retres1~0 := 0; 299#L239true is_master_triggered_#res := is_master_triggered_~__retres1~0; 58#L240true activate_threads_#t~ret6 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret6;havoc activate_threads_#t~ret6; 154#L605true assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 157#L605-2true havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 189#L247true assume 1 == ~t1_pc~0; 96#L248true assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 190#L258true is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 98#L259true activate_threads_#t~ret7 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 373#L613true assume !(0 != activate_threads_~tmp___0~0); 346#L613-2true havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 207#L266true assume !(1 == ~t2_pc~0); 358#L266-2true is_transmit2_triggered_~__retres1~2 := 0; 208#L277true is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 293#L278true activate_threads_#t~ret8 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 7#L621true assume !(0 != activate_threads_~tmp___1~0); 12#L621-2true havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 11#L285true assume 1 == ~t3_pc~0; 118#L286true assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 13#L296true is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 119#L297true activate_threads_#t~ret9 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 228#L629true assume !(0 != activate_threads_~tmp___2~0); 209#L629-2true havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 240#L304true assume !(1 == ~t4_pc~0); 221#L304-2true is_transmit4_triggered_~__retres1~4 := 0; 239#L315true is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 327#L316true activate_threads_#t~ret10 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 44#L637true assume !(0 != activate_threads_~tmp___3~0); 46#L637-2true assume !(1 == ~M_E~0); 117#L545-1true assume !(1 == ~T1_E~0); 159#L550-1true assume 1 == ~T2_E~0;~T2_E~0 := 2; 15#L555-1true assume !(1 == ~T3_E~0); 48#L560-1true assume !(1 == ~T4_E~0); 50#L565-1true assume !(1 == ~E_1~0); 260#L570-1true assume !(1 == ~E_2~0); 288#L575-1true assume !(1 == ~E_3~0); 347#L580-1true assume !(1 == ~E_4~0); 244#L766-1true [2018-11-23 12:43:37,348 INFO L796 eck$LassoCheckResult]: Loop: 244#L766-1true assume !false; 205#L767true start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret0, eval_#t~nondet1, eval_~tmp_ndt_1~0, eval_#t~nondet2, eval_~tmp_ndt_2~0, eval_#t~nondet3, eval_~tmp_ndt_3~0, eval_#t~nondet4, eval_~tmp_ndt_4~0, eval_#t~nondet5, eval_~tmp_ndt_5~0, eval_~tmp~0;havoc eval_~tmp~0; 179#L467true assume !true; 267#L482true start_simulation_~kernel_st~0 := 2; 167#L324-1true start_simulation_~kernel_st~0 := 3; 361#L492-2true assume !(0 == ~M_E~0); 320#L492-4true assume 0 == ~T1_E~0;~T1_E~0 := 1; 196#L497-3true assume 0 == ~T2_E~0;~T2_E~0 := 1; 233#L502-3true assume 0 == ~T3_E~0;~T3_E~0 := 1; 247#L507-3true assume 0 == ~T4_E~0;~T4_E~0 := 1; 87#L512-3true assume 0 == ~E_1~0;~E_1~0 := 1; 140#L517-3true assume 0 == ~E_2~0;~E_2~0 := 1; 186#L522-3true assume 0 == ~E_3~0;~E_3~0 := 1; 38#L527-3true assume !(0 == ~E_4~0); 53#L532-3true havoc activate_threads_#t~ret6, activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 289#L228-15true assume 1 == ~m_pc~0; 64#L229-5true assume 1 == ~M_E~0;is_master_triggered_~__retres1~0 := 1; 319#L239-5true is_master_triggered_#res := is_master_triggered_~__retres1~0; 66#L240-5true activate_threads_#t~ret6 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret6;havoc activate_threads_#t~ret6; 103#L605-15true assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 111#L605-17true havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 114#L247-15true assume !(1 == ~t1_pc~0); 108#L247-17true is_transmit1_triggered_~__retres1~1 := 0; 146#L258-5true is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 255#L259-5true activate_threads_#t~ret7 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 314#L613-15true assume !(0 != activate_threads_~tmp___0~0); 286#L613-17true havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 305#L266-15true assume !(1 == ~t2_pc~0); 338#L266-17true is_transmit2_triggered_~__retres1~2 := 0; 348#L277-5true is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 268#L278-5true activate_threads_#t~ret8 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 152#L621-15true assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 156#L621-17true havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 193#L285-15true assume 1 == ~t3_pc~0; 131#L286-5true assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 28#L296-5true is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 133#L297-5true activate_threads_#t~ret9 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 372#L629-15true assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 342#L629-17true havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 202#L304-15true assume 1 == ~t4_pc~0; 312#L305-5true assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 225#L315-5true is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 310#L316-5true activate_threads_#t~ret10 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 5#L637-15true assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 10#L637-17true assume 1 == ~M_E~0;~M_E~0 := 2; 84#L545-3true assume 1 == ~T1_E~0;~T1_E~0 := 2; 137#L550-3true assume 1 == ~T2_E~0;~T2_E~0 := 2; 183#L555-3true assume 1 == ~T3_E~0;~T3_E~0 := 2; 34#L560-3true assume 1 == ~T4_E~0;~T4_E~0 := 2; 52#L565-3true assume 1 == ~E_1~0;~E_1~0 := 2; 269#L570-3true assume !(1 == ~E_2~0); 295#L575-3true assume 1 == ~E_3~0;~E_3~0 := 2; 354#L580-3true assume 1 == ~E_4~0;~E_4~0 := 2; 213#L585-3true havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 252#L364-1true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 95#L391-1true exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 237#L392-1true start_simulation_#t~ret12 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret12;havoc start_simulation_#t~ret12; 71#L785true assume !(0 == start_simulation_~tmp~3); 75#L785-1true havoc stop_simulation_#res;havoc stop_simulation_#t~ret11, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 257#L364-2true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 99#L391-2true exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 238#L392-2true stop_simulation_#t~ret11 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret11;havoc stop_simulation_#t~ret11; 300#L740true assume !(0 != stop_simulation_~tmp~2);stop_simulation_~__retres2~0 := 1; 49#L747true stop_simulation_#res := stop_simulation_~__retres2~0; 170#L748true start_simulation_#t~ret13 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret13;havoc start_simulation_#t~ret13; 124#L798true assume !(0 != start_simulation_~tmp___0~1); 244#L766-1true [2018-11-23 12:43:37,353 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 12:43:37,353 INFO L82 PathProgramCache]: Analyzing trace with hash 1688618289, now seen corresponding path program 1 times [2018-11-23 12:43:37,354 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 12:43:37,355 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 12:43:37,395 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 12:43:37,395 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 12:43:37,395 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 12:43:37,420 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 12:43:37,473 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 12:43:37,475 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 12:43:37,476 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-23 12:43:37,479 INFO L799 eck$LassoCheckResult]: stem already infeasible [2018-11-23 12:43:37,480 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 12:43:37,480 INFO L82 PathProgramCache]: Analyzing trace with hash -1580088769, now seen corresponding path program 1 times [2018-11-23 12:43:37,480 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 12:43:37,480 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 12:43:37,481 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 12:43:37,481 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 12:43:37,481 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 12:43:37,484 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 12:43:37,494 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 12:43:37,494 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 12:43:37,494 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2018-11-23 12:43:37,495 INFO L811 eck$LassoCheckResult]: loop already infeasible [2018-11-23 12:43:37,509 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-23 12:43:37,509 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-23 12:43:37,511 INFO L87 Difference]: Start difference. First operand 373 states. Second operand 3 states. [2018-11-23 12:43:37,538 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 12:43:37,538 INFO L93 Difference]: Finished difference Result 373 states and 564 transitions. [2018-11-23 12:43:37,539 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-23 12:43:37,540 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 373 states and 564 transitions. [2018-11-23 12:43:37,544 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 307 [2018-11-23 12:43:37,548 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 373 states to 368 states and 559 transitions. [2018-11-23 12:43:37,549 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 368 [2018-11-23 12:43:37,549 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 368 [2018-11-23 12:43:37,550 INFO L73 IsDeterministic]: Start isDeterministic. Operand 368 states and 559 transitions. [2018-11-23 12:43:37,551 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-23 12:43:37,551 INFO L705 BuchiCegarLoop]: Abstraction has 368 states and 559 transitions. [2018-11-23 12:43:37,565 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 368 states and 559 transitions. [2018-11-23 12:43:37,579 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 368 to 368. [2018-11-23 12:43:37,579 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 368 states. [2018-11-23 12:43:37,580 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 368 states to 368 states and 559 transitions. [2018-11-23 12:43:37,581 INFO L728 BuchiCegarLoop]: Abstraction has 368 states and 559 transitions. [2018-11-23 12:43:37,581 INFO L608 BuchiCegarLoop]: Abstraction has 368 states and 559 transitions. [2018-11-23 12:43:37,581 INFO L442 BuchiCegarLoop]: ======== Iteration 2============ [2018-11-23 12:43:37,581 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 368 states and 559 transitions. [2018-11-23 12:43:37,583 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 307 [2018-11-23 12:43:37,583 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-23 12:43:37,583 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-23 12:43:37,584 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 12:43:37,584 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 12:43:37,584 INFO L794 eck$LassoCheckResult]: Stem: 961#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2; 782#L-1 havoc main_#res;havoc main_~__retres1~6;havoc main_~__retres1~6;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 783#L729 havoc start_simulation_#t~ret12, start_simulation_#t~ret13, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 996#L324 assume 1 == ~m_i~0;~m_st~0 := 0; 997#L331-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 932#L336-1 assume !(1 == ~t2_i~0);~t2_st~0 := 2; 933#L341-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 958#L346-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 785#L351-1 assume !(0 == ~M_E~0); 786#L492-1 assume !(0 == ~T1_E~0); 1039#L497-1 assume !(0 == ~T2_E~0); 1040#L502-1 assume !(0 == ~T3_E~0); 1064#L507-1 assume 0 == ~T4_E~0;~T4_E~0 := 1; 955#L512-1 assume !(0 == ~E_1~0); 956#L517-1 assume !(0 == ~E_2~0); 972#L522-1 assume !(0 == ~E_3~0); 803#L527-1 assume !(0 == ~E_4~0); 804#L532-1 havoc activate_threads_#t~ret6, activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 838#L228 assume !(1 == ~m_pc~0); 847#L228-2 is_master_triggered_~__retres1~0 := 0; 846#L239 is_master_triggered_#res := is_master_triggered_~__retres1~0; 848#L240 activate_threads_#t~ret6 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret6;havoc activate_threads_#t~ret6; 849#L605 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 990#L605-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 993#L247 assume 1 == ~t1_pc~0; 925#L248 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 926#L258 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 928#L259 activate_threads_#t~ret7 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 929#L613 assume !(0 != activate_threads_~tmp___0~0); 1118#L613-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 1024#L266 assume !(1 == ~t2_pc~0); 1025#L266-2 is_transmit2_triggered_~__retres1~2 := 0; 1027#L277 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 1028#L278 activate_threads_#t~ret8 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 766#L621 assume !(0 != activate_threads_~tmp___1~0); 767#L621-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 771#L285 assume 1 == ~t3_pc~0; 772#L286 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 763#L296 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 775#L297 activate_threads_#t~ret9 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 954#L629 assume !(0 != activate_threads_~tmp___2~0); 1029#L629-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 1030#L304 assume !(1 == ~t4_pc~0); 1045#L304-2 is_transmit4_triggered_~__retres1~4 := 0; 1046#L315 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 1061#L316 activate_threads_#t~ret10 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 830#L637 assume !(0 != activate_threads_~tmp___3~0); 831#L637-2 assume !(1 == ~M_E~0); 832#L545-1 assume !(1 == ~T1_E~0); 951#L550-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 778#L555-1 assume !(1 == ~T3_E~0); 779#L560-1 assume !(1 == ~T4_E~0); 834#L565-1 assume !(1 == ~E_1~0); 837#L570-1 assume !(1 == ~E_2~0); 1069#L575-1 assume !(1 == ~E_3~0); 1101#L580-1 assume !(1 == ~E_4~0); 960#L766-1 [2018-11-23 12:43:37,585 INFO L796 eck$LassoCheckResult]: Loop: 960#L766-1 assume !false; 1023#L767 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret0, eval_#t~nondet1, eval_~tmp_ndt_1~0, eval_#t~nondet2, eval_~tmp_ndt_2~0, eval_#t~nondet3, eval_~tmp_ndt_3~0, eval_#t~nondet4, eval_~tmp_ndt_4~0, eval_#t~nondet5, eval_~tmp_ndt_5~0, eval_~tmp~0;havoc eval_~tmp~0; 844#L467 assume !false; 914#L402 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 915#L364 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 855#L391 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 916#L392 eval_#t~ret0 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret0;havoc eval_#t~ret0; 820#L406 assume !(0 != eval_~tmp~0); 822#L482 start_simulation_~kernel_st~0 := 2; 999#L324-1 start_simulation_~kernel_st~0 := 3; 1000#L492-2 assume !(0 == ~M_E~0); 1110#L492-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 1012#L497-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 1013#L502-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 1059#L507-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 910#L512-3 assume 0 == ~E_1~0;~E_1~0 := 1; 911#L517-3 assume 0 == ~E_2~0;~E_2~0 := 1; 978#L522-3 assume 0 == ~E_3~0;~E_3~0 := 1; 814#L527-3 assume !(0 == ~E_4~0); 815#L532-3 havoc activate_threads_#t~ret6, activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 840#L228-15 assume 1 == ~m_pc~0; 860#L229-5 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0 := 1; 861#L239-5 is_master_triggered_#res := is_master_triggered_~__retres1~0; 866#L240-5 activate_threads_#t~ret6 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret6;havoc activate_threads_#t~ret6; 867#L605-15 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 936#L605-17 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 947#L247-15 assume 1 == ~t1_pc~0; 949#L248-5 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 943#L258-5 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 984#L259-5 activate_threads_#t~ret7 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 1067#L613-15 assume !(0 != activate_threads_~tmp___0~0); 1095#L613-17 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 1096#L266-15 assume 1 == ~t2_pc~0; 1074#L267-5 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 1075#L277-5 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 1078#L278-5 activate_threads_#t~ret8 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 987#L621-15 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 988#L621-17 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 991#L285-15 assume 1 == ~t3_pc~0; 968#L286-5 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 796#L296-5 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 797#L297-5 activate_threads_#t~ret9 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 971#L629-15 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 1116#L629-17 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 1018#L304-15 assume 1 == ~t4_pc~0; 1019#L305-5 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 1022#L315-5 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 1051#L316-5 activate_threads_#t~ret10 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 760#L637-15 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 761#L637-17 assume 1 == ~M_E~0;~M_E~0 := 2; 770#L545-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 903#L550-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 975#L555-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 807#L560-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 808#L565-3 assume 1 == ~E_1~0;~E_1~0 := 2; 839#L570-3 assume !(1 == ~E_2~0); 1079#L575-3 assume 1 == ~E_3~0;~E_3~0 := 2; 1103#L580-3 assume 1 == ~E_4~0;~E_4~0 := 2; 1036#L585-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 1037#L364-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 864#L391-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 923#L392-1 start_simulation_#t~ret12 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret12;havoc start_simulation_#t~ret12; 876#L785 assume !(0 == start_simulation_~tmp~3); 877#L785-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret11, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 884#L364-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 872#L391-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 930#L392-2 stop_simulation_#t~ret11 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret11;havoc stop_simulation_#t~ret11; 1060#L740 assume !(0 != stop_simulation_~tmp~2);stop_simulation_~__retres2~0 := 1; 835#L747 stop_simulation_#res := stop_simulation_~__retres2~0; 836#L748 start_simulation_#t~ret13 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret13;havoc start_simulation_#t~ret13; 959#L798 assume !(0 != start_simulation_~tmp___0~1); 960#L766-1 [2018-11-23 12:43:37,585 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 12:43:37,585 INFO L82 PathProgramCache]: Analyzing trace with hash 1244717615, now seen corresponding path program 1 times [2018-11-23 12:43:37,585 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 12:43:37,585 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 12:43:37,586 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 12:43:37,586 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 12:43:37,586 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 12:43:37,591 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 12:43:37,613 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 12:43:37,614 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 12:43:37,614 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-23 12:43:37,614 INFO L799 eck$LassoCheckResult]: stem already infeasible [2018-11-23 12:43:37,614 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 12:43:37,615 INFO L82 PathProgramCache]: Analyzing trace with hash 554242591, now seen corresponding path program 1 times [2018-11-23 12:43:37,615 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 12:43:37,615 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 12:43:37,616 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 12:43:37,616 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 12:43:37,616 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 12:43:37,630 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 12:43:37,687 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 12:43:37,687 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 12:43:37,687 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-23 12:43:37,688 INFO L811 eck$LassoCheckResult]: loop already infeasible [2018-11-23 12:43:37,688 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-23 12:43:37,688 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-23 12:43:37,688 INFO L87 Difference]: Start difference. First operand 368 states and 559 transitions. cyclomatic complexity: 192 Second operand 3 states. [2018-11-23 12:43:37,708 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 12:43:37,709 INFO L93 Difference]: Finished difference Result 368 states and 558 transitions. [2018-11-23 12:43:37,709 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-23 12:43:37,710 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 368 states and 558 transitions. [2018-11-23 12:43:37,712 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 307 [2018-11-23 12:43:37,714 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 368 states to 368 states and 558 transitions. [2018-11-23 12:43:37,714 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 368 [2018-11-23 12:43:37,715 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 368 [2018-11-23 12:43:37,715 INFO L73 IsDeterministic]: Start isDeterministic. Operand 368 states and 558 transitions. [2018-11-23 12:43:37,717 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-23 12:43:37,718 INFO L705 BuchiCegarLoop]: Abstraction has 368 states and 558 transitions. [2018-11-23 12:43:37,718 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 368 states and 558 transitions. [2018-11-23 12:43:37,727 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 368 to 368. [2018-11-23 12:43:37,727 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 368 states. [2018-11-23 12:43:37,728 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 368 states to 368 states and 558 transitions. [2018-11-23 12:43:37,729 INFO L728 BuchiCegarLoop]: Abstraction has 368 states and 558 transitions. [2018-11-23 12:43:37,729 INFO L608 BuchiCegarLoop]: Abstraction has 368 states and 558 transitions. [2018-11-23 12:43:37,729 INFO L442 BuchiCegarLoop]: ======== Iteration 3============ [2018-11-23 12:43:37,729 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 368 states and 558 transitions. [2018-11-23 12:43:37,731 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 307 [2018-11-23 12:43:37,731 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-23 12:43:37,731 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-23 12:43:37,733 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 12:43:37,733 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 12:43:37,733 INFO L794 eck$LassoCheckResult]: Stem: 1704#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2; 1523#L-1 havoc main_#res;havoc main_~__retres1~6;havoc main_~__retres1~6;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 1524#L729 havoc start_simulation_#t~ret12, start_simulation_#t~ret13, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 1737#L324 assume 1 == ~m_i~0;~m_st~0 := 0; 1738#L331-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1675#L336-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1676#L341-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 1700#L346-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 1527#L351-1 assume !(0 == ~M_E~0); 1528#L492-1 assume !(0 == ~T1_E~0); 1781#L497-1 assume !(0 == ~T2_E~0); 1782#L502-1 assume !(0 == ~T3_E~0); 1807#L507-1 assume 0 == ~T4_E~0;~T4_E~0 := 1; 1698#L512-1 assume !(0 == ~E_1~0); 1699#L517-1 assume !(0 == ~E_2~0); 1715#L522-1 assume !(0 == ~E_3~0); 1546#L527-1 assume !(0 == ~E_4~0); 1547#L532-1 havoc activate_threads_#t~ret6, activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 1581#L228 assume !(1 == ~m_pc~0); 1590#L228-2 is_master_triggered_~__retres1~0 := 0; 1589#L239 is_master_triggered_#res := is_master_triggered_~__retres1~0; 1591#L240 activate_threads_#t~ret6 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret6;havoc activate_threads_#t~ret6; 1592#L605 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 1733#L605-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 1735#L247 assume 1 == ~t1_pc~0; 1667#L248 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 1668#L258 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 1671#L259 activate_threads_#t~ret7 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 1672#L613 assume !(0 != activate_threads_~tmp___0~0); 1860#L613-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 1767#L266 assume !(1 == ~t2_pc~0); 1768#L266-2 is_transmit2_triggered_~__retres1~2 := 0; 1770#L277 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 1771#L278 activate_threads_#t~ret8 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 1507#L621 assume !(0 != activate_threads_~tmp___1~0); 1508#L621-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 1514#L285 assume 1 == ~t3_pc~0; 1515#L286 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 1506#L296 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 1516#L297 activate_threads_#t~ret9 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 1695#L629 assume !(0 != activate_threads_~tmp___2~0); 1772#L629-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 1773#L304 assume !(1 == ~t4_pc~0); 1788#L304-2 is_transmit4_triggered_~__retres1~4 := 0; 1789#L315 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 1804#L316 activate_threads_#t~ret10 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 1571#L637 assume !(0 != activate_threads_~tmp___3~0); 1572#L637-2 assume !(1 == ~M_E~0); 1575#L545-1 assume !(1 == ~T1_E~0); 1694#L550-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 1519#L555-1 assume !(1 == ~T3_E~0); 1520#L560-1 assume !(1 == ~T4_E~0); 1577#L565-1 assume !(1 == ~E_1~0); 1580#L570-1 assume !(1 == ~E_2~0); 1812#L575-1 assume !(1 == ~E_3~0); 1843#L580-1 assume !(1 == ~E_4~0); 1703#L766-1 [2018-11-23 12:43:37,734 INFO L796 eck$LassoCheckResult]: Loop: 1703#L766-1 assume !false; 1765#L767 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret0, eval_#t~nondet1, eval_~tmp_ndt_1~0, eval_#t~nondet2, eval_~tmp_ndt_2~0, eval_#t~nondet3, eval_~tmp_ndt_3~0, eval_#t~nondet4, eval_~tmp_ndt_4~0, eval_#t~nondet5, eval_~tmp_ndt_5~0, eval_~tmp~0;havoc eval_~tmp~0; 1587#L467 assume !false; 1655#L402 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 1656#L364 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 1595#L391 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 1659#L392 eval_#t~ret0 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret0;havoc eval_#t~ret0; 1563#L406 assume !(0 != eval_~tmp~0); 1565#L482 start_simulation_~kernel_st~0 := 2; 1742#L324-1 start_simulation_~kernel_st~0 := 3; 1743#L492-2 assume !(0 == ~M_E~0); 1853#L492-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 1755#L497-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 1756#L502-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 1802#L507-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 1650#L512-3 assume 0 == ~E_1~0;~E_1~0 := 1; 1651#L517-3 assume 0 == ~E_2~0;~E_2~0 := 1; 1723#L522-3 assume 0 == ~E_3~0;~E_3~0 := 1; 1561#L527-3 assume !(0 == ~E_4~0); 1562#L532-3 havoc activate_threads_#t~ret6, activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 1583#L228-15 assume 1 == ~m_pc~0; 1603#L229-5 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0 := 1; 1604#L239-5 is_master_triggered_#res := is_master_triggered_~__retres1~0; 1609#L240-5 activate_threads_#t~ret6 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret6;havoc activate_threads_#t~ret6; 1610#L605-15 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 1679#L605-17 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 1690#L247-15 assume !(1 == ~t1_pc~0); 1687#L247-17 is_transmit1_triggered_~__retres1~1 := 0; 1688#L258-5 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 1729#L259-5 activate_threads_#t~ret7 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 1811#L613-15 assume !(0 != activate_threads_~tmp___0~0); 1838#L613-17 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 1839#L266-15 assume 1 == ~t2_pc~0; 1818#L267-5 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 1819#L277-5 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 1821#L278-5 activate_threads_#t~ret8 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 1730#L621-15 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 1731#L621-17 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 1734#L285-15 assume !(1 == ~t3_pc~0); 1712#L285-17 is_transmit3_triggered_~__retres1~3 := 0; 1539#L296-5 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 1540#L297-5 activate_threads_#t~ret9 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 1714#L629-15 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 1859#L629-17 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 1761#L304-15 assume 1 == ~t4_pc~0; 1762#L305-5 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 1766#L315-5 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 1794#L316-5 activate_threads_#t~ret10 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 1503#L637-15 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 1504#L637-17 assume 1 == ~M_E~0;~M_E~0 := 2; 1513#L545-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 1646#L550-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 1718#L555-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 1550#L560-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 1551#L565-3 assume 1 == ~E_1~0;~E_1~0 := 2; 1582#L570-3 assume !(1 == ~E_2~0); 1822#L575-3 assume 1 == ~E_3~0;~E_3~0 := 2; 1846#L580-3 assume 1 == ~E_4~0;~E_4~0 := 2; 1779#L585-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 1780#L364-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 1607#L391-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 1666#L392-1 start_simulation_#t~ret12 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret12;havoc start_simulation_#t~ret12; 1622#L785 assume !(0 == start_simulation_~tmp~3); 1623#L785-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret11, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 1631#L364-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 1615#L391-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 1673#L392-2 stop_simulation_#t~ret11 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret11;havoc stop_simulation_#t~ret11; 1803#L740 assume !(0 != stop_simulation_~tmp~2);stop_simulation_~__retres2~0 := 1; 1578#L747 stop_simulation_#res := stop_simulation_~__retres2~0; 1579#L748 start_simulation_#t~ret13 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret13;havoc start_simulation_#t~ret13; 1702#L798 assume !(0 != start_simulation_~tmp___0~1); 1703#L766-1 [2018-11-23 12:43:37,734 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 12:43:37,734 INFO L82 PathProgramCache]: Analyzing trace with hash -1021663571, now seen corresponding path program 1 times [2018-11-23 12:43:37,734 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 12:43:37,734 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 12:43:37,735 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 12:43:37,735 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 12:43:37,735 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 12:43:37,740 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 12:43:37,756 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 12:43:37,756 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 12:43:37,756 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-23 12:43:37,756 INFO L799 eck$LassoCheckResult]: stem already infeasible [2018-11-23 12:43:37,757 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 12:43:37,757 INFO L82 PathProgramCache]: Analyzing trace with hash -1895792863, now seen corresponding path program 1 times [2018-11-23 12:43:37,757 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 12:43:37,757 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 12:43:37,758 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 12:43:37,758 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 12:43:37,758 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 12:43:37,766 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 12:43:37,794 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 12:43:37,795 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 12:43:37,795 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-23 12:43:37,795 INFO L811 eck$LassoCheckResult]: loop already infeasible [2018-11-23 12:43:37,795 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-23 12:43:37,795 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-23 12:43:37,796 INFO L87 Difference]: Start difference. First operand 368 states and 558 transitions. cyclomatic complexity: 191 Second operand 3 states. [2018-11-23 12:43:37,804 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 12:43:37,804 INFO L93 Difference]: Finished difference Result 368 states and 557 transitions. [2018-11-23 12:43:37,805 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-23 12:43:37,805 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 368 states and 557 transitions. [2018-11-23 12:43:37,808 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 307 [2018-11-23 12:43:37,810 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 368 states to 368 states and 557 transitions. [2018-11-23 12:43:37,810 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 368 [2018-11-23 12:43:37,811 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 368 [2018-11-23 12:43:37,811 INFO L73 IsDeterministic]: Start isDeterministic. Operand 368 states and 557 transitions. [2018-11-23 12:43:37,812 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-23 12:43:37,812 INFO L705 BuchiCegarLoop]: Abstraction has 368 states and 557 transitions. [2018-11-23 12:43:37,812 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 368 states and 557 transitions. [2018-11-23 12:43:37,818 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 368 to 368. [2018-11-23 12:43:37,819 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 368 states. [2018-11-23 12:43:37,820 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 368 states to 368 states and 557 transitions. [2018-11-23 12:43:37,820 INFO L728 BuchiCegarLoop]: Abstraction has 368 states and 557 transitions. [2018-11-23 12:43:37,820 INFO L608 BuchiCegarLoop]: Abstraction has 368 states and 557 transitions. [2018-11-23 12:43:37,820 INFO L442 BuchiCegarLoop]: ======== Iteration 4============ [2018-11-23 12:43:37,820 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 368 states and 557 transitions. [2018-11-23 12:43:37,822 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 307 [2018-11-23 12:43:37,822 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-23 12:43:37,822 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-23 12:43:37,824 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 12:43:37,824 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 12:43:37,824 INFO L794 eck$LassoCheckResult]: Stem: 2447#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2; 2268#L-1 havoc main_#res;havoc main_~__retres1~6;havoc main_~__retres1~6;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 2269#L729 havoc start_simulation_#t~ret12, start_simulation_#t~ret13, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 2482#L324 assume 1 == ~m_i~0;~m_st~0 := 0; 2483#L331-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 2418#L336-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 2419#L341-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 2443#L346-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 2271#L351-1 assume !(0 == ~M_E~0); 2272#L492-1 assume !(0 == ~T1_E~0); 2525#L497-1 assume !(0 == ~T2_E~0); 2526#L502-1 assume !(0 == ~T3_E~0); 2550#L507-1 assume 0 == ~T4_E~0;~T4_E~0 := 1; 2441#L512-1 assume !(0 == ~E_1~0); 2442#L517-1 assume !(0 == ~E_2~0); 2458#L522-1 assume !(0 == ~E_3~0); 2289#L527-1 assume !(0 == ~E_4~0); 2290#L532-1 havoc activate_threads_#t~ret6, activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 2324#L228 assume !(1 == ~m_pc~0); 2333#L228-2 is_master_triggered_~__retres1~0 := 0; 2332#L239 is_master_triggered_#res := is_master_triggered_~__retres1~0; 2334#L240 activate_threads_#t~ret6 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret6;havoc activate_threads_#t~ret6; 2335#L605 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 2476#L605-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 2479#L247 assume 1 == ~t1_pc~0; 2411#L248 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 2412#L258 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 2414#L259 activate_threads_#t~ret7 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 2415#L613 assume !(0 != activate_threads_~tmp___0~0); 2604#L613-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 2510#L266 assume !(1 == ~t2_pc~0); 2511#L266-2 is_transmit2_triggered_~__retres1~2 := 0; 2513#L277 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 2514#L278 activate_threads_#t~ret8 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 2252#L621 assume !(0 != activate_threads_~tmp___1~0); 2253#L621-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 2257#L285 assume 1 == ~t3_pc~0; 2258#L286 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 2249#L296 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 2261#L297 activate_threads_#t~ret9 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 2438#L629 assume !(0 != activate_threads_~tmp___2~0); 2515#L629-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 2516#L304 assume !(1 == ~t4_pc~0); 2531#L304-2 is_transmit4_triggered_~__retres1~4 := 0; 2532#L315 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 2547#L316 activate_threads_#t~ret10 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 2316#L637 assume !(0 != activate_threads_~tmp___3~0); 2317#L637-2 assume !(1 == ~M_E~0); 2318#L545-1 assume !(1 == ~T1_E~0); 2437#L550-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 2264#L555-1 assume !(1 == ~T3_E~0); 2265#L560-1 assume !(1 == ~T4_E~0); 2320#L565-1 assume !(1 == ~E_1~0); 2323#L570-1 assume !(1 == ~E_2~0); 2555#L575-1 assume !(1 == ~E_3~0); 2587#L580-1 assume !(1 == ~E_4~0); 2446#L766-1 [2018-11-23 12:43:37,824 INFO L796 eck$LassoCheckResult]: Loop: 2446#L766-1 assume !false; 2509#L767 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret0, eval_#t~nondet1, eval_~tmp_ndt_1~0, eval_#t~nondet2, eval_~tmp_ndt_2~0, eval_#t~nondet3, eval_~tmp_ndt_3~0, eval_#t~nondet4, eval_~tmp_ndt_4~0, eval_#t~nondet5, eval_~tmp_ndt_5~0, eval_~tmp~0;havoc eval_~tmp~0; 2330#L467 assume !false; 2398#L402 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 2399#L364 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 2341#L391 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 2402#L392 eval_#t~ret0 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret0;havoc eval_#t~ret0; 2306#L406 assume !(0 != eval_~tmp~0); 2308#L482 start_simulation_~kernel_st~0 := 2; 2485#L324-1 start_simulation_~kernel_st~0 := 3; 2486#L492-2 assume !(0 == ~M_E~0); 2596#L492-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 2498#L497-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 2499#L502-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 2545#L507-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 2393#L512-3 assume 0 == ~E_1~0;~E_1~0 := 1; 2394#L517-3 assume 0 == ~E_2~0;~E_2~0 := 1; 2466#L522-3 assume 0 == ~E_3~0;~E_3~0 := 1; 2304#L527-3 assume !(0 == ~E_4~0); 2305#L532-3 havoc activate_threads_#t~ret6, activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 2326#L228-15 assume 1 == ~m_pc~0; 2349#L229-5 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0 := 1; 2350#L239-5 is_master_triggered_#res := is_master_triggered_~__retres1~0; 2352#L240-5 activate_threads_#t~ret6 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret6;havoc activate_threads_#t~ret6; 2353#L605-15 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 2422#L605-17 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 2433#L247-15 assume 1 == ~t1_pc~0; 2435#L248-5 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 2429#L258-5 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 2470#L259-5 activate_threads_#t~ret7 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 2553#L613-15 assume !(0 != activate_threads_~tmp___0~0); 2581#L613-17 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 2582#L266-15 assume 1 == ~t2_pc~0; 2560#L267-5 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 2561#L277-5 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 2564#L278-5 activate_threads_#t~ret8 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 2473#L621-15 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 2474#L621-17 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 2477#L285-15 assume 1 == ~t3_pc~0; 2454#L286-5 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 2282#L296-5 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 2283#L297-5 activate_threads_#t~ret9 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 2456#L629-15 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 2602#L629-17 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 2504#L304-15 assume 1 == ~t4_pc~0; 2505#L305-5 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 2508#L315-5 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 2537#L316-5 activate_threads_#t~ret10 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 2246#L637-15 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 2247#L637-17 assume 1 == ~M_E~0;~M_E~0 := 2; 2256#L545-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 2386#L550-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 2461#L555-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 2293#L560-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 2294#L565-3 assume 1 == ~E_1~0;~E_1~0 := 2; 2325#L570-3 assume !(1 == ~E_2~0); 2565#L575-3 assume 1 == ~E_3~0;~E_3~0 := 2; 2589#L580-3 assume 1 == ~E_4~0;~E_4~0 := 2; 2522#L585-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 2523#L364-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 2347#L391-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 2409#L392-1 start_simulation_#t~ret12 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret12;havoc start_simulation_#t~ret12; 2362#L785 assume !(0 == start_simulation_~tmp~3); 2363#L785-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret11, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 2370#L364-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 2355#L391-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 2416#L392-2 stop_simulation_#t~ret11 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret11;havoc stop_simulation_#t~ret11; 2546#L740 assume !(0 != stop_simulation_~tmp~2);stop_simulation_~__retres2~0 := 1; 2321#L747 stop_simulation_#res := stop_simulation_~__retres2~0; 2322#L748 start_simulation_#t~ret13 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret13;havoc start_simulation_#t~ret13; 2445#L798 assume !(0 != start_simulation_~tmp___0~1); 2446#L766-1 [2018-11-23 12:43:37,825 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 12:43:37,825 INFO L82 PathProgramCache]: Analyzing trace with hash -540583313, now seen corresponding path program 1 times [2018-11-23 12:43:37,825 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 12:43:37,825 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 12:43:37,826 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 12:43:37,826 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 12:43:37,826 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 12:43:37,832 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 12:43:37,846 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 12:43:37,846 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 12:43:37,846 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-23 12:43:37,846 INFO L799 eck$LassoCheckResult]: stem already infeasible [2018-11-23 12:43:37,846 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 12:43:37,847 INFO L82 PathProgramCache]: Analyzing trace with hash 554242591, now seen corresponding path program 2 times [2018-11-23 12:43:37,847 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 12:43:37,847 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 12:43:37,847 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 12:43:37,847 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 12:43:37,847 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 12:43:37,855 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 12:43:37,894 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 12:43:37,894 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 12:43:37,895 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-23 12:43:37,895 INFO L811 eck$LassoCheckResult]: loop already infeasible [2018-11-23 12:43:37,895 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-23 12:43:37,895 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-23 12:43:37,896 INFO L87 Difference]: Start difference. First operand 368 states and 557 transitions. cyclomatic complexity: 190 Second operand 3 states. [2018-11-23 12:43:37,904 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 12:43:37,905 INFO L93 Difference]: Finished difference Result 368 states and 556 transitions. [2018-11-23 12:43:37,905 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-23 12:43:37,905 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 368 states and 556 transitions. [2018-11-23 12:43:37,907 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 307 [2018-11-23 12:43:37,909 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 368 states to 368 states and 556 transitions. [2018-11-23 12:43:37,909 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 368 [2018-11-23 12:43:37,909 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 368 [2018-11-23 12:43:37,909 INFO L73 IsDeterministic]: Start isDeterministic. Operand 368 states and 556 transitions. [2018-11-23 12:43:37,910 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-23 12:43:37,910 INFO L705 BuchiCegarLoop]: Abstraction has 368 states and 556 transitions. [2018-11-23 12:43:37,910 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 368 states and 556 transitions. [2018-11-23 12:43:37,913 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 368 to 368. [2018-11-23 12:43:37,913 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 368 states. [2018-11-23 12:43:37,914 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 368 states to 368 states and 556 transitions. [2018-11-23 12:43:37,914 INFO L728 BuchiCegarLoop]: Abstraction has 368 states and 556 transitions. [2018-11-23 12:43:37,915 INFO L608 BuchiCegarLoop]: Abstraction has 368 states and 556 transitions. [2018-11-23 12:43:37,915 INFO L442 BuchiCegarLoop]: ======== Iteration 5============ [2018-11-23 12:43:37,915 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 368 states and 556 transitions. [2018-11-23 12:43:37,916 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 307 [2018-11-23 12:43:37,916 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-23 12:43:37,917 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-23 12:43:37,918 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 12:43:37,918 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 12:43:37,918 INFO L794 eck$LassoCheckResult]: Stem: 3190#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2; 3009#L-1 havoc main_#res;havoc main_~__retres1~6;havoc main_~__retres1~6;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 3010#L729 havoc start_simulation_#t~ret12, start_simulation_#t~ret13, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 3223#L324 assume 1 == ~m_i~0;~m_st~0 := 0; 3224#L331-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 3161#L336-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 3162#L341-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 3186#L346-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 3013#L351-1 assume !(0 == ~M_E~0); 3014#L492-1 assume !(0 == ~T1_E~0); 3267#L497-1 assume !(0 == ~T2_E~0); 3268#L502-1 assume !(0 == ~T3_E~0); 3293#L507-1 assume 0 == ~T4_E~0;~T4_E~0 := 1; 3184#L512-1 assume !(0 == ~E_1~0); 3185#L517-1 assume !(0 == ~E_2~0); 3201#L522-1 assume !(0 == ~E_3~0); 3032#L527-1 assume !(0 == ~E_4~0); 3033#L532-1 havoc activate_threads_#t~ret6, activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 3067#L228 assume !(1 == ~m_pc~0); 3076#L228-2 is_master_triggered_~__retres1~0 := 0; 3075#L239 is_master_triggered_#res := is_master_triggered_~__retres1~0; 3077#L240 activate_threads_#t~ret6 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret6;havoc activate_threads_#t~ret6; 3078#L605 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 3219#L605-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 3221#L247 assume 1 == ~t1_pc~0; 3153#L248 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 3154#L258 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 3157#L259 activate_threads_#t~ret7 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 3158#L613 assume !(0 != activate_threads_~tmp___0~0); 3346#L613-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 3253#L266 assume !(1 == ~t2_pc~0); 3254#L266-2 is_transmit2_triggered_~__retres1~2 := 0; 3256#L277 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 3257#L278 activate_threads_#t~ret8 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 2993#L621 assume !(0 != activate_threads_~tmp___1~0); 2994#L621-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 3000#L285 assume 1 == ~t3_pc~0; 3001#L286 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 2992#L296 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 3002#L297 activate_threads_#t~ret9 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 3181#L629 assume !(0 != activate_threads_~tmp___2~0); 3258#L629-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 3259#L304 assume !(1 == ~t4_pc~0); 3274#L304-2 is_transmit4_triggered_~__retres1~4 := 0; 3275#L315 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 3290#L316 activate_threads_#t~ret10 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 3057#L637 assume !(0 != activate_threads_~tmp___3~0); 3058#L637-2 assume !(1 == ~M_E~0); 3061#L545-1 assume !(1 == ~T1_E~0); 3180#L550-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 3005#L555-1 assume !(1 == ~T3_E~0); 3006#L560-1 assume !(1 == ~T4_E~0); 3063#L565-1 assume !(1 == ~E_1~0); 3066#L570-1 assume !(1 == ~E_2~0); 3298#L575-1 assume !(1 == ~E_3~0); 3329#L580-1 assume !(1 == ~E_4~0); 3189#L766-1 [2018-11-23 12:43:37,918 INFO L796 eck$LassoCheckResult]: Loop: 3189#L766-1 assume !false; 3251#L767 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret0, eval_#t~nondet1, eval_~tmp_ndt_1~0, eval_#t~nondet2, eval_~tmp_ndt_2~0, eval_#t~nondet3, eval_~tmp_ndt_3~0, eval_#t~nondet4, eval_~tmp_ndt_4~0, eval_#t~nondet5, eval_~tmp_ndt_5~0, eval_~tmp~0;havoc eval_~tmp~0; 3073#L467 assume !false; 3141#L402 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 3142#L364 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 3081#L391 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 3145#L392 eval_#t~ret0 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret0;havoc eval_#t~ret0; 3049#L406 assume !(0 != eval_~tmp~0); 3051#L482 start_simulation_~kernel_st~0 := 2; 3228#L324-1 start_simulation_~kernel_st~0 := 3; 3229#L492-2 assume !(0 == ~M_E~0); 3339#L492-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 3241#L497-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 3242#L502-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 3288#L507-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 3136#L512-3 assume 0 == ~E_1~0;~E_1~0 := 1; 3137#L517-3 assume 0 == ~E_2~0;~E_2~0 := 1; 3209#L522-3 assume 0 == ~E_3~0;~E_3~0 := 1; 3047#L527-3 assume !(0 == ~E_4~0); 3048#L532-3 havoc activate_threads_#t~ret6, activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 3069#L228-15 assume 1 == ~m_pc~0; 3089#L229-5 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0 := 1; 3090#L239-5 is_master_triggered_#res := is_master_triggered_~__retres1~0; 3095#L240-5 activate_threads_#t~ret6 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret6;havoc activate_threads_#t~ret6; 3096#L605-15 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 3165#L605-17 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 3176#L247-15 assume !(1 == ~t1_pc~0); 3173#L247-17 is_transmit1_triggered_~__retres1~1 := 0; 3174#L258-5 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 3215#L259-5 activate_threads_#t~ret7 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 3297#L613-15 assume !(0 != activate_threads_~tmp___0~0); 3324#L613-17 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 3325#L266-15 assume 1 == ~t2_pc~0; 3304#L267-5 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 3305#L277-5 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 3307#L278-5 activate_threads_#t~ret8 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 3216#L621-15 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 3217#L621-17 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 3220#L285-15 assume 1 == ~t3_pc~0; 3197#L286-5 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 3025#L296-5 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 3026#L297-5 activate_threads_#t~ret9 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 3200#L629-15 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 3345#L629-17 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 3247#L304-15 assume 1 == ~t4_pc~0; 3248#L305-5 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 3252#L315-5 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 3280#L316-5 activate_threads_#t~ret10 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 2989#L637-15 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 2990#L637-17 assume 1 == ~M_E~0;~M_E~0 := 2; 2999#L545-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 3132#L550-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 3204#L555-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 3036#L560-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 3037#L565-3 assume 1 == ~E_1~0;~E_1~0 := 2; 3068#L570-3 assume !(1 == ~E_2~0); 3308#L575-3 assume 1 == ~E_3~0;~E_3~0 := 2; 3332#L580-3 assume 1 == ~E_4~0;~E_4~0 := 2; 3265#L585-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 3266#L364-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 3093#L391-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 3152#L392-1 start_simulation_#t~ret12 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret12;havoc start_simulation_#t~ret12; 3108#L785 assume !(0 == start_simulation_~tmp~3); 3109#L785-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret11, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 3117#L364-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 3101#L391-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 3159#L392-2 stop_simulation_#t~ret11 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret11;havoc stop_simulation_#t~ret11; 3289#L740 assume !(0 != stop_simulation_~tmp~2);stop_simulation_~__retres2~0 := 1; 3064#L747 stop_simulation_#res := stop_simulation_~__retres2~0; 3065#L748 start_simulation_#t~ret13 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret13;havoc start_simulation_#t~ret13; 3188#L798 assume !(0 != start_simulation_~tmp___0~1); 3189#L766-1 [2018-11-23 12:43:37,919 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 12:43:37,919 INFO L82 PathProgramCache]: Analyzing trace with hash -525064595, now seen corresponding path program 1 times [2018-11-23 12:43:37,919 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 12:43:37,919 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 12:43:37,920 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 12:43:37,920 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-23 12:43:37,920 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 12:43:37,926 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 12:43:37,956 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 12:43:37,956 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 12:43:37,956 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2018-11-23 12:43:37,957 INFO L799 eck$LassoCheckResult]: stem already infeasible [2018-11-23 12:43:37,957 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 12:43:37,957 INFO L82 PathProgramCache]: Analyzing trace with hash -319235104, now seen corresponding path program 1 times [2018-11-23 12:43:37,957 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 12:43:37,957 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 12:43:37,958 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 12:43:37,958 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 12:43:37,958 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 12:43:37,964 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 12:43:37,989 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 12:43:37,989 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 12:43:37,989 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-23 12:43:37,990 INFO L811 eck$LassoCheckResult]: loop already infeasible [2018-11-23 12:43:37,990 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-23 12:43:37,990 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-23 12:43:37,990 INFO L87 Difference]: Start difference. First operand 368 states and 556 transitions. cyclomatic complexity: 189 Second operand 3 states. [2018-11-23 12:43:38,013 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 12:43:38,013 INFO L93 Difference]: Finished difference Result 368 states and 551 transitions. [2018-11-23 12:43:38,014 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-23 12:43:38,015 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 368 states and 551 transitions. [2018-11-23 12:43:38,016 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 307 [2018-11-23 12:43:38,017 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 368 states to 368 states and 551 transitions. [2018-11-23 12:43:38,017 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 368 [2018-11-23 12:43:38,018 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 368 [2018-11-23 12:43:38,018 INFO L73 IsDeterministic]: Start isDeterministic. Operand 368 states and 551 transitions. [2018-11-23 12:43:38,018 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-23 12:43:38,018 INFO L705 BuchiCegarLoop]: Abstraction has 368 states and 551 transitions. [2018-11-23 12:43:38,019 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 368 states and 551 transitions. [2018-11-23 12:43:38,022 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 368 to 368. [2018-11-23 12:43:38,022 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 368 states. [2018-11-23 12:43:38,023 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 368 states to 368 states and 551 transitions. [2018-11-23 12:43:38,023 INFO L728 BuchiCegarLoop]: Abstraction has 368 states and 551 transitions. [2018-11-23 12:43:38,023 INFO L608 BuchiCegarLoop]: Abstraction has 368 states and 551 transitions. [2018-11-23 12:43:38,023 INFO L442 BuchiCegarLoop]: ======== Iteration 6============ [2018-11-23 12:43:38,023 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 368 states and 551 transitions. [2018-11-23 12:43:38,024 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 307 [2018-11-23 12:43:38,025 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-23 12:43:38,025 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-23 12:43:38,026 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 12:43:38,026 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 12:43:38,026 INFO L794 eck$LassoCheckResult]: Stem: 3933#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2; 3754#L-1 havoc main_#res;havoc main_~__retres1~6;havoc main_~__retres1~6;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 3755#L729 havoc start_simulation_#t~ret12, start_simulation_#t~ret13, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 3966#L324 assume 1 == ~m_i~0;~m_st~0 := 0; 3967#L331-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 3904#L336-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 3905#L341-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 3929#L346-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 3757#L351-1 assume !(0 == ~M_E~0); 3758#L492-1 assume !(0 == ~T1_E~0); 4011#L497-1 assume !(0 == ~T2_E~0); 4012#L502-1 assume !(0 == ~T3_E~0); 4036#L507-1 assume !(0 == ~T4_E~0); 3927#L512-1 assume !(0 == ~E_1~0); 3928#L517-1 assume !(0 == ~E_2~0); 3944#L522-1 assume !(0 == ~E_3~0); 3775#L527-1 assume !(0 == ~E_4~0); 3776#L532-1 havoc activate_threads_#t~ret6, activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 3810#L228 assume !(1 == ~m_pc~0); 3819#L228-2 is_master_triggered_~__retres1~0 := 0; 3818#L239 is_master_triggered_#res := is_master_triggered_~__retres1~0; 3820#L240 activate_threads_#t~ret6 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret6;havoc activate_threads_#t~ret6; 3821#L605 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 3962#L605-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 3965#L247 assume 1 == ~t1_pc~0; 3897#L248 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 3898#L258 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 3900#L259 activate_threads_#t~ret7 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 3901#L613 assume !(0 != activate_threads_~tmp___0~0); 4090#L613-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 3996#L266 assume !(1 == ~t2_pc~0); 3997#L266-2 is_transmit2_triggered_~__retres1~2 := 0; 3999#L277 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 4000#L278 activate_threads_#t~ret8 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 3738#L621 assume !(0 != activate_threads_~tmp___1~0); 3739#L621-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 3743#L285 assume 1 == ~t3_pc~0; 3744#L286 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 3735#L296 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 3747#L297 activate_threads_#t~ret9 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 3924#L629 assume !(0 != activate_threads_~tmp___2~0); 4001#L629-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 4002#L304 assume !(1 == ~t4_pc~0); 4017#L304-2 is_transmit4_triggered_~__retres1~4 := 0; 4018#L315 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 4033#L316 activate_threads_#t~ret10 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 3802#L637 assume !(0 != activate_threads_~tmp___3~0); 3803#L637-2 assume !(1 == ~M_E~0); 3804#L545-1 assume !(1 == ~T1_E~0); 3923#L550-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 3748#L555-1 assume !(1 == ~T3_E~0); 3749#L560-1 assume !(1 == ~T4_E~0); 3806#L565-1 assume !(1 == ~E_1~0); 3809#L570-1 assume !(1 == ~E_2~0); 4041#L575-1 assume !(1 == ~E_3~0); 4072#L580-1 assume !(1 == ~E_4~0); 3932#L766-1 [2018-11-23 12:43:38,026 INFO L796 eck$LassoCheckResult]: Loop: 3932#L766-1 assume !false; 3995#L767 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret0, eval_#t~nondet1, eval_~tmp_ndt_1~0, eval_#t~nondet2, eval_~tmp_ndt_2~0, eval_#t~nondet3, eval_~tmp_ndt_3~0, eval_#t~nondet4, eval_~tmp_ndt_4~0, eval_#t~nondet5, eval_~tmp_ndt_5~0, eval_~tmp~0;havoc eval_~tmp~0; 3816#L467 assume !false; 3884#L402 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 3885#L364 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 3827#L391 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 3888#L392 eval_#t~ret0 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret0;havoc eval_#t~ret0; 3792#L406 assume !(0 != eval_~tmp~0); 3794#L482 start_simulation_~kernel_st~0 := 2; 3971#L324-1 start_simulation_~kernel_st~0 := 3; 3972#L492-2 assume !(0 == ~M_E~0); 4082#L492-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 3984#L497-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 3985#L502-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 4031#L507-3 assume !(0 == ~T4_E~0); 3879#L512-3 assume 0 == ~E_1~0;~E_1~0 := 1; 3880#L517-3 assume 0 == ~E_2~0;~E_2~0 := 1; 3952#L522-3 assume 0 == ~E_3~0;~E_3~0 := 1; 3790#L527-3 assume !(0 == ~E_4~0); 3791#L532-3 havoc activate_threads_#t~ret6, activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 3812#L228-15 assume 1 == ~m_pc~0; 3835#L229-5 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0 := 1; 3836#L239-5 is_master_triggered_#res := is_master_triggered_~__retres1~0; 3838#L240-5 activate_threads_#t~ret6 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret6;havoc activate_threads_#t~ret6; 3839#L605-15 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 3911#L605-17 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 3920#L247-15 assume 1 == ~t1_pc~0; 3922#L248-5 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 3918#L258-5 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 3958#L259-5 activate_threads_#t~ret7 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 4040#L613-15 assume !(0 != activate_threads_~tmp___0~0); 4067#L613-17 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 4068#L266-15 assume !(1 == ~t2_pc~0); 4048#L266-17 is_transmit2_triggered_~__retres1~2 := 0; 4047#L277-5 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 4050#L278-5 activate_threads_#t~ret8 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 3959#L621-15 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 3960#L621-17 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 3963#L285-15 assume 1 == ~t3_pc~0; 3940#L286-5 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 3768#L296-5 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 3769#L297-5 activate_threads_#t~ret9 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 3942#L629-15 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 4088#L629-17 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 3990#L304-15 assume 1 == ~t4_pc~0; 3991#L305-5 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 3994#L315-5 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 4023#L316-5 activate_threads_#t~ret10 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 3732#L637-15 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 3733#L637-17 assume 1 == ~M_E~0;~M_E~0 := 2; 3740#L545-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 3872#L550-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 3947#L555-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 3779#L560-3 assume !(1 == ~T4_E~0); 3780#L565-3 assume 1 == ~E_1~0;~E_1~0 := 2; 3811#L570-3 assume !(1 == ~E_2~0); 4051#L575-3 assume 1 == ~E_3~0;~E_3~0 := 2; 4075#L580-3 assume 1 == ~E_4~0;~E_4~0 := 2; 4008#L585-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 4009#L364-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 3833#L391-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 3895#L392-1 start_simulation_#t~ret12 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret12;havoc start_simulation_#t~ret12; 3848#L785 assume !(0 == start_simulation_~tmp~3); 3849#L785-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret11, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 3856#L364-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 3841#L391-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 3902#L392-2 stop_simulation_#t~ret11 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret11;havoc stop_simulation_#t~ret11; 4032#L740 assume !(0 != stop_simulation_~tmp~2);stop_simulation_~__retres2~0 := 1; 3807#L747 stop_simulation_#res := stop_simulation_~__retres2~0; 3808#L748 start_simulation_#t~ret13 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret13;havoc start_simulation_#t~ret13; 3931#L798 assume !(0 != start_simulation_~tmp___0~1); 3932#L766-1 [2018-11-23 12:43:38,027 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 12:43:38,027 INFO L82 PathProgramCache]: Analyzing trace with hash 1720514859, now seen corresponding path program 1 times [2018-11-23 12:43:38,027 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 12:43:38,027 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 12:43:38,028 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 12:43:38,028 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 12:43:38,028 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 12:43:38,032 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 12:43:38,057 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 12:43:38,057 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 12:43:38,057 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2018-11-23 12:43:38,057 INFO L799 eck$LassoCheckResult]: stem already infeasible [2018-11-23 12:43:38,058 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 12:43:38,058 INFO L82 PathProgramCache]: Analyzing trace with hash -1135913248, now seen corresponding path program 1 times [2018-11-23 12:43:38,058 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 12:43:38,058 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 12:43:38,059 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 12:43:38,059 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 12:43:38,059 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 12:43:38,064 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 12:43:38,090 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 12:43:38,090 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 12:43:38,090 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-23 12:43:38,091 INFO L811 eck$LassoCheckResult]: loop already infeasible [2018-11-23 12:43:38,091 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-23 12:43:38,091 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-23 12:43:38,091 INFO L87 Difference]: Start difference. First operand 368 states and 551 transitions. cyclomatic complexity: 184 Second operand 3 states. [2018-11-23 12:43:38,138 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 12:43:38,138 INFO L93 Difference]: Finished difference Result 633 states and 939 transitions. [2018-11-23 12:43:38,139 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-23 12:43:38,139 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 633 states and 939 transitions. [2018-11-23 12:43:38,141 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 571 [2018-11-23 12:43:38,143 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 633 states to 633 states and 939 transitions. [2018-11-23 12:43:38,143 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 633 [2018-11-23 12:43:38,144 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 633 [2018-11-23 12:43:38,144 INFO L73 IsDeterministic]: Start isDeterministic. Operand 633 states and 939 transitions. [2018-11-23 12:43:38,145 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-23 12:43:38,145 INFO L705 BuchiCegarLoop]: Abstraction has 633 states and 939 transitions. [2018-11-23 12:43:38,145 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 633 states and 939 transitions. [2018-11-23 12:43:38,150 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 633 to 631. [2018-11-23 12:43:38,150 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 631 states. [2018-11-23 12:43:38,151 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 631 states to 631 states and 937 transitions. [2018-11-23 12:43:38,151 INFO L728 BuchiCegarLoop]: Abstraction has 631 states and 937 transitions. [2018-11-23 12:43:38,151 INFO L608 BuchiCegarLoop]: Abstraction has 631 states and 937 transitions. [2018-11-23 12:43:38,151 INFO L442 BuchiCegarLoop]: ======== Iteration 7============ [2018-11-23 12:43:38,152 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 631 states and 937 transitions. [2018-11-23 12:43:38,153 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 569 [2018-11-23 12:43:38,153 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-23 12:43:38,153 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-23 12:43:38,154 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 12:43:38,154 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 12:43:38,155 INFO L794 eck$LassoCheckResult]: Stem: 4938#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2; 4760#L-1 havoc main_#res;havoc main_~__retres1~6;havoc main_~__retres1~6;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 4761#L729 havoc start_simulation_#t~ret12, start_simulation_#t~ret13, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 4972#L324 assume 1 == ~m_i~0;~m_st~0 := 0; 4973#L331-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 4910#L336-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 4911#L341-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 4934#L346-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 4764#L351-1 assume !(0 == ~M_E~0); 4765#L492-1 assume !(0 == ~T1_E~0); 5021#L497-1 assume !(0 == ~T2_E~0); 5022#L502-1 assume !(0 == ~T3_E~0); 5050#L507-1 assume !(0 == ~T4_E~0); 4932#L512-1 assume !(0 == ~E_1~0); 4933#L517-1 assume !(0 == ~E_2~0); 4949#L522-1 assume !(0 == ~E_3~0); 4783#L527-1 assume !(0 == ~E_4~0); 4784#L532-1 havoc activate_threads_#t~ret6, activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 4819#L228 assume !(1 == ~m_pc~0); 4828#L228-2 is_master_triggered_~__retres1~0 := 0; 4827#L239 is_master_triggered_#res := is_master_triggered_~__retres1~0; 4829#L240 activate_threads_#t~ret6 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret6;havoc activate_threads_#t~ret6; 4830#L605 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 4967#L605-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 4969#L247 assume !(1 == ~t1_pc~0); 4983#L247-2 is_transmit1_triggered_~__retres1~1 := 0; 4984#L258 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 4906#L259 activate_threads_#t~ret7 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 4907#L613 assume !(0 != activate_threads_~tmp___0~0); 5114#L613-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 5007#L266 assume !(1 == ~t2_pc~0); 5008#L266-2 is_transmit2_triggered_~__retres1~2 := 0; 5010#L277 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 5011#L278 activate_threads_#t~ret8 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 4744#L621 assume !(0 != activate_threads_~tmp___1~0); 4745#L621-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 4751#L285 assume 1 == ~t3_pc~0; 4752#L286 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 4743#L296 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 4753#L297 activate_threads_#t~ret9 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 4929#L629 assume !(0 != activate_threads_~tmp___2~0); 5012#L629-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 5013#L304 assume !(1 == ~t4_pc~0); 5030#L304-2 is_transmit4_triggered_~__retres1~4 := 0; 5031#L315 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 5047#L316 activate_threads_#t~ret10 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 4809#L637 assume !(0 != activate_threads_~tmp___3~0); 4810#L637-2 assume !(1 == ~M_E~0); 4813#L545-1 assume !(1 == ~T1_E~0); 4928#L550-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 4756#L555-1 assume !(1 == ~T3_E~0); 4757#L560-1 assume !(1 == ~T4_E~0); 4815#L565-1 assume !(1 == ~E_1~0); 4818#L570-1 assume !(1 == ~E_2~0); 5064#L575-1 assume !(1 == ~E_3~0); 5096#L580-1 assume !(1 == ~E_4~0); 5115#L766-1 [2018-11-23 12:43:38,155 INFO L796 eck$LassoCheckResult]: Loop: 5115#L766-1 assume !false; 5005#L767 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret0, eval_#t~nondet1, eval_~tmp_ndt_1~0, eval_#t~nondet2, eval_~tmp_ndt_2~0, eval_#t~nondet3, eval_~tmp_ndt_3~0, eval_#t~nondet4, eval_~tmp_ndt_4~0, eval_#t~nondet5, eval_~tmp_ndt_5~0, eval_~tmp~0;havoc eval_~tmp~0; 4825#L467 assume !false; 4893#L402 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 4894#L364 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 4833#L391 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 4897#L392 eval_#t~ret0 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret0;havoc eval_#t~ret0; 4800#L406 assume !(0 != eval_~tmp~0); 4802#L482 start_simulation_~kernel_st~0 := 2; 4977#L324-1 start_simulation_~kernel_st~0 := 3; 4978#L492-2 assume !(0 == ~M_E~0); 5107#L492-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 4995#L497-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 4996#L502-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 5044#L507-3 assume !(0 == ~T4_E~0); 4888#L512-3 assume 0 == ~E_1~0;~E_1~0 := 1; 4889#L517-3 assume 0 == ~E_2~0;~E_2~0 := 1; 4957#L522-3 assume 0 == ~E_3~0;~E_3~0 := 1; 4798#L527-3 assume !(0 == ~E_4~0); 4799#L532-3 havoc activate_threads_#t~ret6, activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 4821#L228-15 assume 1 == ~m_pc~0; 4841#L229-5 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0 := 1; 4842#L239-5 is_master_triggered_#res := is_master_triggered_~__retres1~0; 4847#L240-5 activate_threads_#t~ret6 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret6;havoc activate_threads_#t~ret6; 4848#L605-15 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 4914#L605-17 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 4924#L247-15 assume !(1 == ~t1_pc~0); 4926#L247-17 is_transmit1_triggered_~__retres1~1 := 0; 5308#L258-5 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 5307#L259-5 activate_threads_#t~ret7 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 5306#L613-15 assume !(0 != activate_threads_~tmp___0~0); 5305#L613-17 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 5304#L266-15 assume 1 == ~t2_pc~0; 5302#L267-5 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 5301#L277-5 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 5300#L278-5 activate_threads_#t~ret8 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 5299#L621-15 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 5297#L621-17 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 5295#L285-15 assume !(1 == ~t3_pc~0); 5292#L285-17 is_transmit3_triggered_~__retres1~3 := 0; 5290#L296-5 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 5289#L297-5 activate_threads_#t~ret9 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 5286#L629-15 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 5284#L629-17 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 5282#L304-15 assume !(1 == ~t4_pc~0); 5280#L304-17 is_transmit4_triggered_~__retres1~4 := 0; 5277#L315-5 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 5275#L316-5 activate_threads_#t~ret10 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 5274#L637-15 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 5273#L637-17 assume 1 == ~M_E~0;~M_E~0 := 2; 5271#L545-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 5269#L550-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 5267#L555-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 5265#L560-3 assume !(1 == ~T4_E~0); 5263#L565-3 assume 1 == ~E_1~0;~E_1~0 := 2; 5260#L570-3 assume !(1 == ~E_2~0); 5258#L575-3 assume 1 == ~E_3~0;~E_3~0 := 2; 5256#L580-3 assume 1 == ~E_4~0;~E_4~0 := 2; 5254#L585-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 5245#L364-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 5241#L391-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 5239#L392-1 start_simulation_#t~ret12 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret12;havoc start_simulation_#t~ret12; 5238#L785 assume !(0 == start_simulation_~tmp~3); 5236#L785-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret11, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 5233#L364-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 5230#L391-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 5229#L392-2 stop_simulation_#t~ret11 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret11;havoc stop_simulation_#t~ret11; 5228#L740 assume !(0 != stop_simulation_~tmp~2);stop_simulation_~__retres2~0 := 1; 5227#L747 stop_simulation_#res := stop_simulation_~__retres2~0; 5226#L748 start_simulation_#t~ret13 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret13;havoc start_simulation_#t~ret13; 5225#L798 assume !(0 != start_simulation_~tmp___0~1); 5115#L766-1 [2018-11-23 12:43:38,155 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 12:43:38,155 INFO L82 PathProgramCache]: Analyzing trace with hash -1655477814, now seen corresponding path program 1 times [2018-11-23 12:43:38,155 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 12:43:38,155 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 12:43:38,156 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 12:43:38,156 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 12:43:38,156 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 12:43:38,159 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 12:43:38,174 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 12:43:38,175 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 12:43:38,175 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2018-11-23 12:43:38,175 INFO L799 eck$LassoCheckResult]: stem already infeasible [2018-11-23 12:43:38,175 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 12:43:38,175 INFO L82 PathProgramCache]: Analyzing trace with hash -6570654, now seen corresponding path program 1 times [2018-11-23 12:43:38,175 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 12:43:38,175 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 12:43:38,176 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 12:43:38,176 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 12:43:38,176 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 12:43:38,181 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 12:43:38,205 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 12:43:38,205 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 12:43:38,205 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-23 12:43:38,206 INFO L811 eck$LassoCheckResult]: loop already infeasible [2018-11-23 12:43:38,206 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-23 12:43:38,206 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-23 12:43:38,206 INFO L87 Difference]: Start difference. First operand 631 states and 937 transitions. cyclomatic complexity: 308 Second operand 3 states. [2018-11-23 12:43:38,256 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 12:43:38,256 INFO L93 Difference]: Finished difference Result 1121 states and 1653 transitions. [2018-11-23 12:43:38,258 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-23 12:43:38,258 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1121 states and 1653 transitions. [2018-11-23 12:43:38,263 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 1054 [2018-11-23 12:43:38,266 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1121 states to 1121 states and 1653 transitions. [2018-11-23 12:43:38,266 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1121 [2018-11-23 12:43:38,267 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1121 [2018-11-23 12:43:38,267 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1121 states and 1653 transitions. [2018-11-23 12:43:38,269 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-23 12:43:38,269 INFO L705 BuchiCegarLoop]: Abstraction has 1121 states and 1653 transitions. [2018-11-23 12:43:38,270 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1121 states and 1653 transitions. [2018-11-23 12:43:38,280 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1121 to 1117. [2018-11-23 12:43:38,280 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1117 states. [2018-11-23 12:43:38,282 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1117 states to 1117 states and 1649 transitions. [2018-11-23 12:43:38,282 INFO L728 BuchiCegarLoop]: Abstraction has 1117 states and 1649 transitions. [2018-11-23 12:43:38,283 INFO L608 BuchiCegarLoop]: Abstraction has 1117 states and 1649 transitions. [2018-11-23 12:43:38,283 INFO L442 BuchiCegarLoop]: ======== Iteration 8============ [2018-11-23 12:43:38,283 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1117 states and 1649 transitions. [2018-11-23 12:43:38,286 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 1050 [2018-11-23 12:43:38,286 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-23 12:43:38,287 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-23 12:43:38,287 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 12:43:38,287 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 12:43:38,288 INFO L794 eck$LassoCheckResult]: Stem: 6700#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2; 6520#L-1 havoc main_#res;havoc main_~__retres1~6;havoc main_~__retres1~6;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 6521#L729 havoc start_simulation_#t~ret12, start_simulation_#t~ret13, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 6742#L324 assume 1 == ~m_i~0;~m_st~0 := 0; 6743#L331-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 6668#L336-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 6669#L341-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 6696#L346-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 6522#L351-1 assume !(0 == ~M_E~0); 6523#L492-1 assume !(0 == ~T1_E~0); 6793#L497-1 assume !(0 == ~T2_E~0); 6794#L502-1 assume !(0 == ~T3_E~0); 6820#L507-1 assume !(0 == ~T4_E~0); 6694#L512-1 assume !(0 == ~E_1~0); 6695#L517-1 assume !(0 == ~E_2~0); 6712#L522-1 assume !(0 == ~E_3~0); 6540#L527-1 assume !(0 == ~E_4~0); 6541#L532-1 havoc activate_threads_#t~ret6, activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 6576#L228 assume !(1 == ~m_pc~0); 6586#L228-2 is_master_triggered_~__retres1~0 := 0; 6585#L239 is_master_triggered_#res := is_master_triggered_~__retres1~0; 6587#L240 activate_threads_#t~ret6 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret6;havoc activate_threads_#t~ret6; 6588#L605 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 6735#L605-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 6741#L247 assume !(1 == ~t1_pc~0); 6756#L247-2 is_transmit1_triggered_~__retres1~1 := 0; 6757#L258 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 6664#L259 activate_threads_#t~ret7 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 6665#L613 assume !(0 != activate_threads_~tmp___0~0); 6894#L613-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 6779#L266 assume !(1 == ~t2_pc~0); 6780#L266-2 is_transmit2_triggered_~__retres1~2 := 0; 6782#L277 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 6783#L278 activate_threads_#t~ret8 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 6503#L621 assume !(0 != activate_threads_~tmp___1~0); 6504#L621-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 6510#L285 assume !(1 == ~t3_pc~0); 6501#L285-2 is_transmit3_triggered_~__retres1~3 := 0; 6502#L296 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 6513#L297 activate_threads_#t~ret9 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 6691#L629 assume !(0 != activate_threads_~tmp___2~0); 6784#L629-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 6785#L304 assume !(1 == ~t4_pc~0); 6800#L304-2 is_transmit4_triggered_~__retres1~4 := 0; 6801#L315 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 6817#L316 activate_threads_#t~ret10 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 6568#L637 assume !(0 != activate_threads_~tmp___3~0); 6569#L637-2 assume !(1 == ~M_E~0); 6570#L545-1 assume !(1 == ~T1_E~0); 6690#L550-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 6514#L555-1 assume !(1 == ~T3_E~0); 6515#L560-1 assume !(1 == ~T4_E~0); 6572#L565-1 assume !(1 == ~E_1~0); 6575#L570-1 assume !(1 == ~E_2~0); 6836#L575-1 assume !(1 == ~E_3~0); 6869#L580-1 assume !(1 == ~E_4~0); 6895#L766-1 [2018-11-23 12:43:38,288 INFO L796 eck$LassoCheckResult]: Loop: 6895#L766-1 assume !false; 7349#L767 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret0, eval_#t~nondet1, eval_~tmp_ndt_1~0, eval_#t~nondet2, eval_~tmp_ndt_2~0, eval_#t~nondet3, eval_~tmp_ndt_3~0, eval_#t~nondet4, eval_~tmp_ndt_4~0, eval_#t~nondet5, eval_~tmp_ndt_5~0, eval_~tmp~0;havoc eval_~tmp~0; 7348#L467 assume !false; 7302#L402 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 7026#L364 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 7016#L391 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 7014#L392 eval_#t~ret0 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret0;havoc eval_#t~ret0; 7011#L406 assume !(0 != eval_~tmp~0); 7012#L482 start_simulation_~kernel_st~0 := 2; 7608#L324-1 start_simulation_~kernel_st~0 := 3; 7606#L492-2 assume !(0 == ~M_E~0); 7604#L492-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 7603#L497-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 7602#L502-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 7601#L507-3 assume !(0 == ~T4_E~0); 7600#L512-3 assume 0 == ~E_1~0;~E_1~0 := 1; 7599#L517-3 assume 0 == ~E_2~0;~E_2~0 := 1; 7598#L522-3 assume 0 == ~E_3~0;~E_3~0 := 1; 7597#L527-3 assume !(0 == ~E_4~0); 7521#L532-3 havoc activate_threads_#t~ret6, activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 7520#L228-15 assume !(1 == ~m_pc~0); 7518#L228-17 is_master_triggered_~__retres1~0 := 0; 7517#L239-5 is_master_triggered_#res := is_master_triggered_~__retres1~0; 7516#L240-5 activate_threads_#t~ret6 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret6;havoc activate_threads_#t~ret6; 7515#L605-15 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 7514#L605-17 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 7513#L247-15 assume !(1 == ~t1_pc~0); 7512#L247-17 is_transmit1_triggered_~__retres1~1 := 0; 7511#L258-5 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 7510#L259-5 activate_threads_#t~ret7 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 7509#L613-15 assume !(0 != activate_threads_~tmp___0~0); 7508#L613-17 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 7507#L266-15 assume 1 == ~t2_pc~0; 7475#L267-5 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 7474#L277-5 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 6847#L278-5 activate_threads_#t~ret8 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 6733#L621-15 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 6734#L621-17 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 7339#L285-15 assume !(1 == ~t3_pc~0); 7340#L285-17 is_transmit3_triggered_~__retres1~3 := 0; 7450#L296-5 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 7448#L297-5 activate_threads_#t~ret9 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 6902#L629-15 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 6892#L629-17 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 6773#L304-15 assume 1 == ~t4_pc~0; 6774#L305-5 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 6777#L315-5 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 6806#L316-5 activate_threads_#t~ret10 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 6497#L637-15 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 6498#L637-17 assume 1 == ~M_E~0;~M_E~0 := 2; 6507#L545-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 6639#L550-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 6715#L555-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 6544#L560-3 assume !(1 == ~T4_E~0); 6545#L565-3 assume 1 == ~E_1~0;~E_1~0 := 2; 6577#L570-3 assume !(1 == ~E_2~0); 6848#L575-3 assume 1 == ~E_3~0;~E_3~0 := 2; 6872#L580-3 assume 1 == ~E_4~0;~E_4~0 := 2; 6791#L585-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 6792#L364-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 7403#L391-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 7401#L392-1 start_simulation_#t~ret12 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret12;havoc start_simulation_#t~ret12; 7398#L785 assume !(0 == start_simulation_~tmp~3); 7395#L785-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret11, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 7384#L364-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 7380#L391-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 7378#L392-2 stop_simulation_#t~ret11 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret11;havoc stop_simulation_#t~ret11; 7376#L740 assume !(0 != stop_simulation_~tmp~2);stop_simulation_~__retres2~0 := 1; 7375#L747 stop_simulation_#res := stop_simulation_~__retres2~0; 7374#L748 start_simulation_#t~ret13 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret13;havoc start_simulation_#t~ret13; 7372#L798 assume !(0 != start_simulation_~tmp___0~1); 6895#L766-1 [2018-11-23 12:43:38,288 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 12:43:38,288 INFO L82 PathProgramCache]: Analyzing trace with hash -994144023, now seen corresponding path program 1 times [2018-11-23 12:43:38,288 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 12:43:38,288 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 12:43:38,289 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 12:43:38,289 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 12:43:38,289 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 12:43:38,293 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 12:43:38,313 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 12:43:38,313 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 12:43:38,313 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2018-11-23 12:43:38,313 INFO L799 eck$LassoCheckResult]: stem already infeasible [2018-11-23 12:43:38,314 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 12:43:38,314 INFO L82 PathProgramCache]: Analyzing trace with hash -434894238, now seen corresponding path program 1 times [2018-11-23 12:43:38,314 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 12:43:38,314 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 12:43:38,314 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 12:43:38,315 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 12:43:38,315 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 12:43:38,319 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 12:43:38,343 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 12:43:38,344 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 12:43:38,344 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-23 12:43:38,344 INFO L811 eck$LassoCheckResult]: loop already infeasible [2018-11-23 12:43:38,344 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-23 12:43:38,344 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-23 12:43:38,344 INFO L87 Difference]: Start difference. First operand 1117 states and 1649 transitions. cyclomatic complexity: 536 Second operand 3 states. [2018-11-23 12:43:38,381 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 12:43:38,381 INFO L93 Difference]: Finished difference Result 1117 states and 1635 transitions. [2018-11-23 12:43:38,382 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-23 12:43:38,382 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1117 states and 1635 transitions. [2018-11-23 12:43:38,387 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 1050 [2018-11-23 12:43:38,391 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1117 states to 1117 states and 1635 transitions. [2018-11-23 12:43:38,392 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1117 [2018-11-23 12:43:38,392 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1117 [2018-11-23 12:43:38,393 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1117 states and 1635 transitions. [2018-11-23 12:43:38,394 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-23 12:43:38,394 INFO L705 BuchiCegarLoop]: Abstraction has 1117 states and 1635 transitions. [2018-11-23 12:43:38,395 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1117 states and 1635 transitions. [2018-11-23 12:43:38,406 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1117 to 1117. [2018-11-23 12:43:38,406 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1117 states. [2018-11-23 12:43:38,409 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1117 states to 1117 states and 1635 transitions. [2018-11-23 12:43:38,409 INFO L728 BuchiCegarLoop]: Abstraction has 1117 states and 1635 transitions. [2018-11-23 12:43:38,409 INFO L608 BuchiCegarLoop]: Abstraction has 1117 states and 1635 transitions. [2018-11-23 12:43:38,409 INFO L442 BuchiCegarLoop]: ======== Iteration 9============ [2018-11-23 12:43:38,409 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1117 states and 1635 transitions. [2018-11-23 12:43:38,413 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 1050 [2018-11-23 12:43:38,413 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-23 12:43:38,413 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-23 12:43:38,414 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 12:43:38,414 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 12:43:38,414 INFO L794 eck$LassoCheckResult]: Stem: 8943#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2; 8760#L-1 havoc main_#res;havoc main_~__retres1~6;havoc main_~__retres1~6;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 8761#L729 havoc start_simulation_#t~ret12, start_simulation_#t~ret13, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 8984#L324 assume 1 == ~m_i~0;~m_st~0 := 0; 8985#L331-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 8907#L336-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 8908#L341-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 8939#L346-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 8763#L351-1 assume !(0 == ~M_E~0); 8764#L492-1 assume !(0 == ~T1_E~0); 9033#L497-1 assume !(0 == ~T2_E~0); 9034#L502-1 assume !(0 == ~T3_E~0); 9060#L507-1 assume !(0 == ~T4_E~0); 8937#L512-1 assume !(0 == ~E_1~0); 8938#L517-1 assume !(0 == ~E_2~0); 8957#L522-1 assume !(0 == ~E_3~0); 8780#L527-1 assume !(0 == ~E_4~0); 8781#L532-1 havoc activate_threads_#t~ret6, activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 8815#L228 assume !(1 == ~m_pc~0); 8825#L228-2 is_master_triggered_~__retres1~0 := 0; 8824#L239 is_master_triggered_#res := is_master_triggered_~__retres1~0; 8826#L240 activate_threads_#t~ret6 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret6;havoc activate_threads_#t~ret6; 8827#L605 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 8976#L605-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 8981#L247 assume !(1 == ~t1_pc~0); 8994#L247-2 is_transmit1_triggered_~__retres1~1 := 0; 8995#L258 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 8903#L259 activate_threads_#t~ret7 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 8904#L613 assume !(0 != activate_threads_~tmp___0~0); 9138#L613-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 9018#L266 assume !(1 == ~t2_pc~0); 9019#L266-2 is_transmit2_triggered_~__retres1~2 := 0; 9021#L277 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 9022#L278 activate_threads_#t~ret8 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 8745#L621 assume !(0 != activate_threads_~tmp___1~0); 8746#L621-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 8750#L285 assume !(1 == ~t3_pc~0); 8741#L285-2 is_transmit3_triggered_~__retres1~3 := 0; 8742#L296 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 8753#L297 activate_threads_#t~ret9 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 8934#L629 assume !(0 != activate_threads_~tmp___2~0); 9023#L629-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 9024#L304 assume !(1 == ~t4_pc~0); 9040#L304-2 is_transmit4_triggered_~__retres1~4 := 0; 9041#L315 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 9057#L316 activate_threads_#t~ret10 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 8807#L637 assume !(0 != activate_threads_~tmp___3~0); 8808#L637-2 assume !(1 == ~M_E~0); 8809#L545-1 assume !(1 == ~T1_E~0); 8933#L550-1 assume !(1 == ~T2_E~0); 8756#L555-1 assume !(1 == ~T3_E~0); 8757#L560-1 assume !(1 == ~T4_E~0); 8811#L565-1 assume !(1 == ~E_1~0); 8814#L570-1 assume !(1 == ~E_2~0); 9073#L575-1 assume !(1 == ~E_3~0); 9115#L580-1 assume !(1 == ~E_4~0); 9139#L766-1 [2018-11-23 12:43:38,415 INFO L796 eck$LassoCheckResult]: Loop: 9139#L766-1 assume !false; 9696#L767 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret0, eval_#t~nondet1, eval_~tmp_ndt_1~0, eval_#t~nondet2, eval_~tmp_ndt_2~0, eval_#t~nondet3, eval_~tmp_ndt_3~0, eval_#t~nondet4, eval_~tmp_ndt_4~0, eval_#t~nondet5, eval_~tmp_ndt_5~0, eval_~tmp~0;havoc eval_~tmp~0; 9694#L467 assume !false; 9693#L402 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 9691#L364 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 9683#L391 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 9678#L392 eval_#t~ret0 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret0;havoc eval_#t~ret0; 9674#L406 assume !(0 != eval_~tmp~0); 9675#L482 start_simulation_~kernel_st~0 := 2; 9719#L324-1 start_simulation_~kernel_st~0 := 3; 9717#L492-2 assume !(0 == ~M_E~0); 9715#L492-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 9713#L497-3 assume !(0 == ~T2_E~0); 9711#L502-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 9709#L507-3 assume !(0 == ~T4_E~0); 9706#L512-3 assume 0 == ~E_1~0;~E_1~0 := 1; 9704#L517-3 assume 0 == ~E_2~0;~E_2~0 := 1; 9702#L522-3 assume 0 == ~E_3~0;~E_3~0 := 1; 9700#L527-3 assume !(0 == ~E_4~0); 9698#L532-3 havoc activate_threads_#t~ret6, activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 9685#L228-15 assume !(1 == ~m_pc~0); 9680#L228-17 is_master_triggered_~__retres1~0 := 0; 9677#L239-5 is_master_triggered_#res := is_master_triggered_~__retres1~0; 8844#L240-5 activate_threads_#t~ret6 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret6;havoc activate_threads_#t~ret6; 8845#L605-15 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 8913#L605-17 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 8927#L247-15 assume !(1 == ~t1_pc~0); 8931#L247-17 is_transmit1_triggered_~__retres1~1 := 0; 9795#L258-5 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 9793#L259-5 activate_threads_#t~ret7 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 9791#L613-15 assume !(0 != activate_threads_~tmp___0~0); 9789#L613-17 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 9787#L266-15 assume 1 == ~t2_pc~0; 9784#L267-5 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 9782#L277-5 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 9779#L278-5 activate_threads_#t~ret8 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 9777#L621-15 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 9775#L621-17 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 9773#L285-15 assume !(1 == ~t3_pc~0); 9771#L285-17 is_transmit3_triggered_~__retres1~3 := 0; 9769#L296-5 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 9767#L297-5 activate_threads_#t~ret9 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 9765#L629-15 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 9763#L629-17 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 9761#L304-15 assume 1 == ~t4_pc~0; 9758#L305-5 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 9756#L315-5 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 9754#L316-5 activate_threads_#t~ret10 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 9753#L637-15 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 9752#L637-17 assume 1 == ~M_E~0;~M_E~0 := 2; 9751#L545-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 9750#L550-3 assume !(1 == ~T2_E~0); 9744#L555-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 9742#L560-3 assume !(1 == ~T4_E~0); 9740#L565-3 assume 1 == ~E_1~0;~E_1~0 := 2; 9738#L570-3 assume !(1 == ~E_2~0); 9736#L575-3 assume 1 == ~E_3~0;~E_3~0 := 2; 9735#L580-3 assume 1 == ~E_4~0;~E_4~0 := 2; 9734#L585-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 9731#L364-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 9728#L391-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 9727#L392-1 start_simulation_#t~ret12 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret12;havoc start_simulation_#t~ret12; 9725#L785 assume !(0 == start_simulation_~tmp~3); 9726#L785-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret11, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 9747#L364-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 9743#L391-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 9741#L392-2 stop_simulation_#t~ret11 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret11;havoc stop_simulation_#t~ret11; 9739#L740 assume !(0 != stop_simulation_~tmp~2);stop_simulation_~__retres2~0 := 1; 9737#L747 stop_simulation_#res := stop_simulation_~__retres2~0; 9724#L748 start_simulation_#t~ret13 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret13;havoc start_simulation_#t~ret13; 9723#L798 assume !(0 != start_simulation_~tmp___0~1); 9139#L766-1 [2018-11-23 12:43:38,415 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 12:43:38,415 INFO L82 PathProgramCache]: Analyzing trace with hash 780863339, now seen corresponding path program 1 times [2018-11-23 12:43:38,415 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 12:43:38,415 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 12:43:38,416 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 12:43:38,416 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 12:43:38,416 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 12:43:38,421 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 12:43:38,476 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 12:43:38,476 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 12:43:38,476 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-11-23 12:43:38,476 INFO L799 eck$LassoCheckResult]: stem already infeasible [2018-11-23 12:43:38,477 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 12:43:38,477 INFO L82 PathProgramCache]: Analyzing trace with hash -691842910, now seen corresponding path program 1 times [2018-11-23 12:43:38,477 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 12:43:38,477 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 12:43:38,477 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 12:43:38,478 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 12:43:38,478 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 12:43:38,482 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 12:43:38,503 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 12:43:38,503 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 12:43:38,504 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-23 12:43:38,504 INFO L811 eck$LassoCheckResult]: loop already infeasible [2018-11-23 12:43:38,504 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-11-23 12:43:38,504 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-11-23 12:43:38,504 INFO L87 Difference]: Start difference. First operand 1117 states and 1635 transitions. cyclomatic complexity: 522 Second operand 5 states. [2018-11-23 12:43:38,608 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 12:43:38,608 INFO L93 Difference]: Finished difference Result 3126 states and 4538 transitions. [2018-11-23 12:43:38,609 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2018-11-23 12:43:38,609 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 3126 states and 4538 transitions. [2018-11-23 12:43:38,617 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 2970 [2018-11-23 12:43:38,624 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 3126 states to 3126 states and 4538 transitions. [2018-11-23 12:43:38,624 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 3126 [2018-11-23 12:43:38,626 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 3126 [2018-11-23 12:43:38,626 INFO L73 IsDeterministic]: Start isDeterministic. Operand 3126 states and 4538 transitions. [2018-11-23 12:43:38,629 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-23 12:43:38,629 INFO L705 BuchiCegarLoop]: Abstraction has 3126 states and 4538 transitions. [2018-11-23 12:43:38,631 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3126 states and 4538 transitions. [2018-11-23 12:43:38,642 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3126 to 1180. [2018-11-23 12:43:38,642 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1180 states. [2018-11-23 12:43:38,644 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1180 states to 1180 states and 1698 transitions. [2018-11-23 12:43:38,644 INFO L728 BuchiCegarLoop]: Abstraction has 1180 states and 1698 transitions. [2018-11-23 12:43:38,644 INFO L608 BuchiCegarLoop]: Abstraction has 1180 states and 1698 transitions. [2018-11-23 12:43:38,644 INFO L442 BuchiCegarLoop]: ======== Iteration 10============ [2018-11-23 12:43:38,644 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1180 states and 1698 transitions. [2018-11-23 12:43:38,647 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 1110 [2018-11-23 12:43:38,647 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-23 12:43:38,647 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-23 12:43:38,648 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 12:43:38,648 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 12:43:38,648 INFO L794 eck$LassoCheckResult]: Stem: 13201#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2; 13014#L-1 havoc main_#res;havoc main_~__retres1~6;havoc main_~__retres1~6;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 13015#L729 havoc start_simulation_#t~ret12, start_simulation_#t~ret13, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 13245#L324 assume 1 == ~m_i~0;~m_st~0 := 0; 13246#L331-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 13165#L336-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 13166#L341-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 13196#L346-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 13018#L351-1 assume !(0 == ~M_E~0); 13019#L492-1 assume !(0 == ~T1_E~0); 13294#L497-1 assume !(0 == ~T2_E~0); 13295#L502-1 assume !(0 == ~T3_E~0); 13322#L507-1 assume !(0 == ~T4_E~0); 13194#L512-1 assume !(0 == ~E_1~0); 13195#L517-1 assume !(0 == ~E_2~0); 13216#L522-1 assume !(0 == ~E_3~0); 13036#L527-1 assume !(0 == ~E_4~0); 13037#L532-1 havoc activate_threads_#t~ret6, activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 13071#L228 assume !(1 == ~m_pc~0); 13080#L228-2 is_master_triggered_~__retres1~0 := 0; 13392#L239 is_master_triggered_#res := is_master_triggered_~__retres1~0; 13393#L240 activate_threads_#t~ret6 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret6;havoc activate_threads_#t~ret6; 13238#L605 assume !(0 != activate_threads_~tmp~1); 13239#L605-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 13243#L247 assume !(1 == ~t1_pc~0); 13258#L247-2 is_transmit1_triggered_~__retres1~1 := 0; 13259#L258 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 13160#L259 activate_threads_#t~ret7 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 13161#L613 assume !(0 != activate_threads_~tmp___0~0); 13415#L613-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 13280#L266 assume !(1 == ~t2_pc~0); 13281#L266-2 is_transmit2_triggered_~__retres1~2 := 0; 13283#L277 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 13284#L278 activate_threads_#t~ret8 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 12999#L621 assume !(0 != activate_threads_~tmp___1~0); 13000#L621-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 13006#L285 assume !(1 == ~t3_pc~0); 12997#L285-2 is_transmit3_triggered_~__retres1~3 := 0; 12998#L296 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 13007#L297 activate_threads_#t~ret9 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 13191#L629 assume !(0 != activate_threads_~tmp___2~0); 13285#L629-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 13286#L304 assume !(1 == ~t4_pc~0); 13301#L304-2 is_transmit4_triggered_~__retres1~4 := 0; 13302#L315 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 13319#L316 activate_threads_#t~ret10 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 13061#L637 assume !(0 != activate_threads_~tmp___3~0); 13062#L637-2 assume !(1 == ~M_E~0); 13065#L545-1 assume !(1 == ~T1_E~0); 13190#L550-1 assume !(1 == ~T2_E~0); 13010#L555-1 assume !(1 == ~T3_E~0); 13011#L560-1 assume !(1 == ~T4_E~0); 13067#L565-1 assume !(1 == ~E_1~0); 13070#L570-1 assume !(1 == ~E_2~0); 13335#L575-1 assume !(1 == ~E_3~0); 13379#L580-1 assume !(1 == ~E_4~0); 13416#L766-1 [2018-11-23 12:43:38,648 INFO L796 eck$LassoCheckResult]: Loop: 13416#L766-1 assume !false; 13278#L767 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret0, eval_#t~nondet1, eval_~tmp_ndt_1~0, eval_#t~nondet2, eval_~tmp_ndt_2~0, eval_#t~nondet3, eval_~tmp_ndt_3~0, eval_#t~nondet4, eval_~tmp_ndt_4~0, eval_#t~nondet5, eval_~tmp_ndt_5~0, eval_~tmp~0;havoc eval_~tmp~0; 13077#L467 assume !false; 13147#L402 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 13148#L364 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 13086#L391 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 13151#L392 eval_#t~ret0 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret0;havoc eval_#t~ret0; 13053#L406 assume !(0 != eval_~tmp~0); 13055#L482 start_simulation_~kernel_st~0 := 2; 14135#L324-1 start_simulation_~kernel_st~0 := 3; 14133#L492-2 assume !(0 == ~M_E~0); 14131#L492-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 14129#L497-3 assume !(0 == ~T2_E~0); 14126#L502-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 13324#L507-3 assume !(0 == ~T4_E~0); 13142#L512-3 assume 0 == ~E_1~0;~E_1~0 := 1; 13143#L517-3 assume 0 == ~E_2~0;~E_2~0 := 1; 13225#L522-3 assume 0 == ~E_3~0;~E_3~0 := 1; 13051#L527-3 assume !(0 == ~E_4~0); 13052#L532-3 havoc activate_threads_#t~ret6, activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 13073#L228-15 assume 1 == ~m_pc~0; 13094#L229-5 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0 := 1; 13095#L239-5 is_master_triggered_#res := is_master_triggered_~__retres1~0; 14142#L240-5 activate_threads_#t~ret6 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret6;havoc activate_threads_#t~ret6; 14141#L605-15 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 13169#L605-17 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 13182#L247-15 assume !(1 == ~t1_pc~0); 13187#L247-17 is_transmit1_triggered_~__retres1~1 := 0; 14140#L258-5 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 14139#L259-5 activate_threads_#t~ret7 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 14138#L613-15 assume !(0 != activate_threads_~tmp___0~0); 14123#L613-17 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 13395#L266-15 assume !(1 == ~t2_pc~0); 13345#L266-17 is_transmit2_triggered_~__retres1~2 := 0; 13344#L277-5 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 13347#L278-5 activate_threads_#t~ret8 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 13236#L621-15 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 13237#L621-17 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 13242#L285-15 assume !(1 == ~t3_pc~0); 13260#L285-17 is_transmit3_triggered_~__retres1~3 := 0; 13029#L296-5 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 13030#L297-5 activate_threads_#t~ret9 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 13215#L629-15 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 13414#L629-17 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 13274#L304-15 assume 1 == ~t4_pc~0; 13275#L305-5 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 13279#L315-5 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 13307#L316-5 activate_threads_#t~ret10 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 12995#L637-15 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 12996#L637-17 assume 1 == ~M_E~0;~M_E~0 := 2; 13005#L545-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 13138#L550-3 assume !(1 == ~T2_E~0); 13219#L555-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 13040#L560-3 assume !(1 == ~T4_E~0); 13041#L565-3 assume 1 == ~E_1~0;~E_1~0 := 2; 13072#L570-3 assume !(1 == ~E_2~0); 13348#L575-3 assume 1 == ~E_3~0;~E_3~0 := 2; 13386#L580-3 assume 1 == ~E_4~0;~E_4~0 := 2; 13292#L585-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 13293#L364-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 13098#L391-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 13158#L392-1 start_simulation_#t~ret12 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret12;havoc start_simulation_#t~ret12; 13113#L785 assume !(0 == start_simulation_~tmp~3); 13114#L785-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret11, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 13122#L364-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 13106#L391-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 13995#L392-2 stop_simulation_#t~ret11 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret11;havoc stop_simulation_#t~ret11; 13994#L740 assume !(0 != stop_simulation_~tmp~2);stop_simulation_~__retres2~0 := 1; 13993#L747 stop_simulation_#res := stop_simulation_~__retres2~0; 13992#L748 start_simulation_#t~ret13 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret13;havoc start_simulation_#t~ret13; 13990#L798 assume !(0 != start_simulation_~tmp___0~1); 13416#L766-1 [2018-11-23 12:43:38,648 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 12:43:38,649 INFO L82 PathProgramCache]: Analyzing trace with hash -1463119959, now seen corresponding path program 1 times [2018-11-23 12:43:38,649 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 12:43:38,649 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 12:43:38,649 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 12:43:38,649 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 12:43:38,649 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 12:43:38,653 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-23 12:43:38,656 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-23 12:43:38,675 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 12:43:38,675 INFO L82 PathProgramCache]: Analyzing trace with hash 452069922, now seen corresponding path program 1 times [2018-11-23 12:43:38,675 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 12:43:38,675 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 12:43:38,676 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 12:43:38,676 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 12:43:38,676 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 12:43:38,679 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 12:43:38,703 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 12:43:38,704 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 12:43:38,704 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-23 12:43:38,704 INFO L811 eck$LassoCheckResult]: loop already infeasible [2018-11-23 12:43:38,704 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-23 12:43:38,704 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-23 12:43:38,704 INFO L87 Difference]: Start difference. First operand 1180 states and 1698 transitions. cyclomatic complexity: 522 Second operand 3 states. [2018-11-23 12:43:38,747 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 12:43:38,747 INFO L93 Difference]: Finished difference Result 2078 states and 2956 transitions. [2018-11-23 12:43:38,748 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-23 12:43:38,748 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2078 states and 2956 transitions. [2018-11-23 12:43:38,753 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 1955 [2018-11-23 12:43:38,758 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2078 states to 2078 states and 2956 transitions. [2018-11-23 12:43:38,758 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2078 [2018-11-23 12:43:38,759 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2078 [2018-11-23 12:43:38,759 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2078 states and 2956 transitions. [2018-11-23 12:43:38,761 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-23 12:43:38,761 INFO L705 BuchiCegarLoop]: Abstraction has 2078 states and 2956 transitions. [2018-11-23 12:43:38,762 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2078 states and 2956 transitions. [2018-11-23 12:43:38,775 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2078 to 2076. [2018-11-23 12:43:38,775 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2076 states. [2018-11-23 12:43:38,777 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2076 states to 2076 states and 2954 transitions. [2018-11-23 12:43:38,778 INFO L728 BuchiCegarLoop]: Abstraction has 2076 states and 2954 transitions. [2018-11-23 12:43:38,778 INFO L608 BuchiCegarLoop]: Abstraction has 2076 states and 2954 transitions. [2018-11-23 12:43:38,778 INFO L442 BuchiCegarLoop]: ======== Iteration 11============ [2018-11-23 12:43:38,778 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2076 states and 2954 transitions. [2018-11-23 12:43:38,783 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 1953 [2018-11-23 12:43:38,783 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-23 12:43:38,783 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-23 12:43:38,784 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 12:43:38,784 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 12:43:38,784 INFO L794 eck$LassoCheckResult]: Stem: 16466#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2; 16280#L-1 havoc main_#res;havoc main_~__retres1~6;havoc main_~__retres1~6;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 16281#L729 havoc start_simulation_#t~ret12, start_simulation_#t~ret13, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 16510#L324 assume 1 == ~m_i~0;~m_st~0 := 0; 16511#L331-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 16430#L336-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 16431#L341-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 16462#L346-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 16284#L351-1 assume !(0 == ~M_E~0); 16285#L492-1 assume !(0 == ~T1_E~0); 16564#L497-1 assume !(0 == ~T2_E~0); 16565#L502-1 assume !(0 == ~T3_E~0); 16592#L507-1 assume !(0 == ~T4_E~0); 16460#L512-1 assume !(0 == ~E_1~0); 16461#L517-1 assume 0 == ~E_2~0;~E_2~0 := 1; 16478#L522-1 assume !(0 == ~E_3~0); 16303#L527-1 assume !(0 == ~E_4~0); 16304#L532-1 havoc activate_threads_#t~ret6, activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 16339#L228 assume !(1 == ~m_pc~0); 16740#L228-2 is_master_triggered_~__retres1~0 := 0; 16653#L239 is_master_triggered_#res := is_master_triggered_~__retres1~0; 16349#L240 activate_threads_#t~ret6 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret6;havoc activate_threads_#t~ret6; 16350#L605 assume !(0 != activate_threads_~tmp~1); 16502#L605-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 16737#L247 assume !(1 == ~t1_pc~0); 16523#L247-2 is_transmit1_triggered_~__retres1~1 := 0; 16524#L258 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 16426#L259 activate_threads_#t~ret7 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 16427#L613 assume !(0 != activate_threads_~tmp___0~0); 16695#L613-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 16729#L266 assume !(1 == ~t2_pc~0); 16728#L266-2 is_transmit2_triggered_~__retres1~2 := 0; 16646#L277 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 16647#L278 activate_threads_#t~ret8 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 16648#L621 assume !(0 != activate_threads_~tmp___1~0); 16271#L621-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 16272#L285 assume !(1 == ~t3_pc~0); 16727#L285-2 is_transmit3_triggered_~__retres1~3 := 0; 16726#L296 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 16725#L297 activate_threads_#t~ret9 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 16724#L629 assume !(0 != activate_threads_~tmp___2~0); 16717#L629-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 16589#L304 assume !(1 == ~t4_pc~0); 16571#L304-2 is_transmit4_triggered_~__retres1~4 := 0; 16572#L315 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 16588#L316 activate_threads_#t~ret10 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 16329#L637 assume !(0 != activate_threads_~tmp___3~0); 16330#L637-2 assume !(1 == ~M_E~0); 16333#L545-1 assume !(1 == ~T1_E~0); 16456#L550-1 assume !(1 == ~T2_E~0); 16276#L555-1 assume !(1 == ~T3_E~0); 16277#L560-1 assume !(1 == ~T4_E~0); 16335#L565-1 assume !(1 == ~E_1~0); 16338#L570-1 assume 1 == ~E_2~0;~E_2~0 := 2; 16608#L575-1 assume !(1 == ~E_3~0); 16642#L580-1 assume !(1 == ~E_4~0); 16465#L766-1 [2018-11-23 12:43:38,785 INFO L796 eck$LassoCheckResult]: Loop: 16465#L766-1 assume !false; 16547#L767 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret0, eval_#t~nondet1, eval_~tmp_ndt_1~0, eval_#t~nondet2, eval_~tmp_ndt_2~0, eval_#t~nondet3, eval_~tmp_ndt_3~0, eval_#t~nondet4, eval_~tmp_ndt_4~0, eval_#t~nondet5, eval_~tmp_ndt_5~0, eval_~tmp~0;havoc eval_~tmp~0; 16548#L467 assume !false; 17624#L402 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 17517#L364 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 17511#L391 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 17509#L392 eval_#t~ret0 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret0;havoc eval_#t~ret0; 17506#L406 assume !(0 != eval_~tmp~0); 17507#L482 start_simulation_~kernel_st~0 := 2; 18174#L324-1 start_simulation_~kernel_st~0 := 3; 18172#L492-2 assume !(0 == ~M_E~0); 18170#L492-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 18168#L497-3 assume !(0 == ~T2_E~0); 18166#L502-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 18164#L507-3 assume !(0 == ~T4_E~0); 18162#L512-3 assume 0 == ~E_1~0;~E_1~0 := 1; 18161#L517-3 assume !(0 == ~E_2~0); 18160#L522-3 assume 0 == ~E_3~0;~E_3~0 := 1; 18158#L527-3 assume !(0 == ~E_4~0); 18157#L532-3 havoc activate_threads_#t~ret6, activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 18156#L228-15 assume !(1 == ~m_pc~0); 18153#L228-17 is_master_triggered_~__retres1~0 := 0; 18151#L239-5 is_master_triggered_#res := is_master_triggered_~__retres1~0; 18149#L240-5 activate_threads_#t~ret6 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret6;havoc activate_threads_#t~ret6; 18147#L605-15 assume !(0 != activate_threads_~tmp~1); 18144#L605-17 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 18142#L247-15 assume !(1 == ~t1_pc~0); 18140#L247-17 is_transmit1_triggered_~__retres1~1 := 0; 18138#L258-5 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 18134#L259-5 activate_threads_#t~ret7 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 18132#L613-15 assume !(0 != activate_threads_~tmp___0~0); 18131#L613-17 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 18130#L266-15 assume !(1 == ~t2_pc~0); 18128#L266-17 is_transmit2_triggered_~__retres1~2 := 0; 18126#L277-5 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 18124#L278-5 activate_threads_#t~ret8 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 18121#L621-15 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 18116#L621-17 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 18111#L285-15 assume !(1 == ~t3_pc~0); 18106#L285-17 is_transmit3_triggered_~__retres1~3 := 0; 18101#L296-5 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 18098#L297-5 activate_threads_#t~ret9 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 18095#L629-15 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 18093#L629-17 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 18091#L304-15 assume 1 == ~t4_pc~0; 18087#L305-5 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 18084#L315-5 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 18081#L316-5 activate_threads_#t~ret10 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 18078#L637-15 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 18072#L637-17 assume 1 == ~M_E~0;~M_E~0 := 2; 18068#L545-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 18063#L550-3 assume !(1 == ~T2_E~0); 18058#L555-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 18053#L560-3 assume !(1 == ~T4_E~0); 18049#L565-3 assume 1 == ~E_1~0;~E_1~0 := 2; 17984#L570-3 assume !(1 == ~E_2~0); 16619#L575-3 assume 1 == ~E_3~0;~E_3~0 := 2; 16650#L580-3 assume 1 == ~E_4~0;~E_4~0 := 2; 16562#L585-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 16563#L364-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 16365#L391-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 16424#L392-1 start_simulation_#t~ret12 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret12;havoc start_simulation_#t~ret12; 16380#L785 assume !(0 == start_simulation_~tmp~3); 16381#L785-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret11, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 16389#L364-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 16373#L391-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 16428#L392-2 stop_simulation_#t~ret11 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret11;havoc stop_simulation_#t~ret11; 16587#L740 assume !(0 != stop_simulation_~tmp~2);stop_simulation_~__retres2~0 := 1; 16336#L747 stop_simulation_#res := stop_simulation_~__retres2~0; 16337#L748 start_simulation_#t~ret13 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret13;havoc start_simulation_#t~ret13; 16464#L798 assume !(0 != start_simulation_~tmp___0~1); 16465#L766-1 [2018-11-23 12:43:38,785 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 12:43:38,785 INFO L82 PathProgramCache]: Analyzing trace with hash -1711268375, now seen corresponding path program 1 times [2018-11-23 12:43:38,785 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 12:43:38,785 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 12:43:38,786 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 12:43:38,786 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 12:43:38,786 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 12:43:38,788 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 12:43:38,802 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 12:43:38,802 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 12:43:38,802 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2018-11-23 12:43:38,803 INFO L799 eck$LassoCheckResult]: stem already infeasible [2018-11-23 12:43:38,803 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 12:43:38,803 INFO L82 PathProgramCache]: Analyzing trace with hash -615074265, now seen corresponding path program 1 times [2018-11-23 12:43:38,803 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 12:43:38,803 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 12:43:38,804 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 12:43:38,804 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 12:43:38,804 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 12:43:38,808 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 12:43:38,855 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 12:43:38,855 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 12:43:38,855 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-11-23 12:43:38,856 INFO L811 eck$LassoCheckResult]: loop already infeasible [2018-11-23 12:43:38,856 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-23 12:43:38,856 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-23 12:43:38,856 INFO L87 Difference]: Start difference. First operand 2076 states and 2954 transitions. cyclomatic complexity: 882 Second operand 3 states. [2018-11-23 12:43:38,876 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 12:43:38,876 INFO L93 Difference]: Finished difference Result 1180 states and 1663 transitions. [2018-11-23 12:43:38,877 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-23 12:43:38,877 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1180 states and 1663 transitions. [2018-11-23 12:43:38,880 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 1110 [2018-11-23 12:43:38,883 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1180 states to 1180 states and 1663 transitions. [2018-11-23 12:43:38,883 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1180 [2018-11-23 12:43:38,884 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1180 [2018-11-23 12:43:38,884 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1180 states and 1663 transitions. [2018-11-23 12:43:38,885 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-23 12:43:38,885 INFO L705 BuchiCegarLoop]: Abstraction has 1180 states and 1663 transitions. [2018-11-23 12:43:38,886 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1180 states and 1663 transitions. [2018-11-23 12:43:38,893 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1180 to 1180. [2018-11-23 12:43:38,893 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1180 states. [2018-11-23 12:43:38,895 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1180 states to 1180 states and 1663 transitions. [2018-11-23 12:43:38,895 INFO L728 BuchiCegarLoop]: Abstraction has 1180 states and 1663 transitions. [2018-11-23 12:43:38,895 INFO L608 BuchiCegarLoop]: Abstraction has 1180 states and 1663 transitions. [2018-11-23 12:43:38,895 INFO L442 BuchiCegarLoop]: ======== Iteration 12============ [2018-11-23 12:43:38,895 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1180 states and 1663 transitions. [2018-11-23 12:43:38,898 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 1110 [2018-11-23 12:43:38,898 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-23 12:43:38,898 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-23 12:43:38,899 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 12:43:38,899 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 12:43:38,899 INFO L794 eck$LassoCheckResult]: Stem: 19728#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2; 19545#L-1 havoc main_#res;havoc main_~__retres1~6;havoc main_~__retres1~6;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 19546#L729 havoc start_simulation_#t~ret12, start_simulation_#t~ret13, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 19771#L324 assume 1 == ~m_i~0;~m_st~0 := 0; 19772#L331-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 19692#L336-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 19693#L341-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 19725#L346-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 19548#L351-1 assume !(0 == ~M_E~0); 19549#L492-1 assume !(0 == ~T1_E~0); 19820#L497-1 assume !(0 == ~T2_E~0); 19821#L502-1 assume !(0 == ~T3_E~0); 19846#L507-1 assume !(0 == ~T4_E~0); 19722#L512-1 assume !(0 == ~E_1~0); 19723#L517-1 assume !(0 == ~E_2~0); 19741#L522-1 assume !(0 == ~E_3~0); 19565#L527-1 assume !(0 == ~E_4~0); 19566#L532-1 havoc activate_threads_#t~ret6, activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 19600#L228 assume !(1 == ~m_pc~0); 19609#L228-2 is_master_triggered_~__retres1~0 := 0; 19895#L239 is_master_triggered_#res := is_master_triggered_~__retres1~0; 19610#L240 activate_threads_#t~ret6 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret6;havoc activate_threads_#t~ret6; 19611#L605 assume !(0 != activate_threads_~tmp~1); 19762#L605-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 19767#L247 assume !(1 == ~t1_pc~0); 19783#L247-2 is_transmit1_triggered_~__retres1~1 := 0; 19784#L258 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 19688#L259 activate_threads_#t~ret7 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 19689#L613 assume !(0 != activate_threads_~tmp___0~0); 19916#L613-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 19805#L266 assume !(1 == ~t2_pc~0); 19806#L266-2 is_transmit2_triggered_~__retres1~2 := 0; 19808#L277 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 19809#L278 activate_threads_#t~ret8 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 19530#L621 assume !(0 != activate_threads_~tmp___1~0); 19531#L621-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 19535#L285 assume !(1 == ~t3_pc~0); 19526#L285-2 is_transmit3_triggered_~__retres1~3 := 0; 19527#L296 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 19538#L297 activate_threads_#t~ret9 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 19721#L629 assume !(0 != activate_threads_~tmp___2~0); 19810#L629-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 19811#L304 assume !(1 == ~t4_pc~0); 19826#L304-2 is_transmit4_triggered_~__retres1~4 := 0; 19827#L315 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 19843#L316 activate_threads_#t~ret10 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 19592#L637 assume !(0 != activate_threads_~tmp___3~0); 19593#L637-2 assume !(1 == ~M_E~0); 19594#L545-1 assume !(1 == ~T1_E~0); 19718#L550-1 assume !(1 == ~T2_E~0); 19541#L555-1 assume !(1 == ~T3_E~0); 19542#L560-1 assume !(1 == ~T4_E~0); 19596#L565-1 assume !(1 == ~E_1~0); 19599#L570-1 assume !(1 == ~E_2~0); 19857#L575-1 assume !(1 == ~E_3~0); 19889#L580-1 assume !(1 == ~E_4~0); 19727#L766-1 [2018-11-23 12:43:38,899 INFO L796 eck$LassoCheckResult]: Loop: 19727#L766-1 assume !false; 19804#L767 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret0, eval_#t~nondet1, eval_~tmp_ndt_1~0, eval_#t~nondet2, eval_~tmp_ndt_2~0, eval_#t~nondet3, eval_~tmp_ndt_3~0, eval_#t~nondet4, eval_~tmp_ndt_4~0, eval_#t~nondet5, eval_~tmp_ndt_5~0, eval_~tmp~0;havoc eval_~tmp~0; 19606#L467 assume !false; 19675#L402 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 19676#L364 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 19614#L391 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 19679#L392 eval_#t~ret0 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret0;havoc eval_#t~ret0; 19584#L406 assume !(0 != eval_~tmp~0); 19586#L482 start_simulation_~kernel_st~0 := 2; 20698#L324-1 start_simulation_~kernel_st~0 := 3; 20697#L492-2 assume !(0 == ~M_E~0); 20696#L492-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 20695#L497-3 assume !(0 == ~T2_E~0); 20694#L502-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 20693#L507-3 assume !(0 == ~T4_E~0); 19670#L512-3 assume 0 == ~E_1~0;~E_1~0 := 1; 19671#L517-3 assume !(0 == ~E_2~0); 20668#L522-3 assume 0 == ~E_3~0;~E_3~0 := 1; 20667#L527-3 assume !(0 == ~E_4~0); 20573#L532-3 havoc activate_threads_#t~ret6, activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 20572#L228-15 assume !(1 == ~m_pc~0); 20570#L228-17 is_master_triggered_~__retres1~0 := 0; 20568#L239-5 is_master_triggered_#res := is_master_triggered_~__retres1~0; 20566#L240-5 activate_threads_#t~ret6 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret6;havoc activate_threads_#t~ret6; 20565#L605-15 assume !(0 != activate_threads_~tmp~1); 20563#L605-17 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 20542#L247-15 assume !(1 == ~t1_pc~0); 20513#L247-17 is_transmit1_triggered_~__retres1~1 := 0; 20509#L258-5 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 20507#L259-5 activate_threads_#t~ret7 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 20505#L613-15 assume !(0 != activate_threads_~tmp___0~0); 20503#L613-17 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 20500#L266-15 assume !(1 == ~t2_pc~0); 20497#L266-17 is_transmit2_triggered_~__retres1~2 := 0; 20495#L277-5 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 20493#L278-5 activate_threads_#t~ret8 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 20491#L621-15 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 20489#L621-17 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 20487#L285-15 assume !(1 == ~t3_pc~0); 20485#L285-17 is_transmit3_triggered_~__retres1~3 := 0; 20482#L296-5 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 20480#L297-5 activate_threads_#t~ret9 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 20478#L629-15 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 20476#L629-17 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 20474#L304-15 assume 1 == ~t4_pc~0; 20471#L305-5 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 20469#L315-5 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 20467#L316-5 activate_threads_#t~ret10 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 20465#L637-15 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 20463#L637-17 assume 1 == ~M_E~0;~M_E~0 := 2; 20461#L545-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 20459#L550-3 assume !(1 == ~T2_E~0); 20457#L555-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 20454#L560-3 assume !(1 == ~T4_E~0); 20452#L565-3 assume 1 == ~E_1~0;~E_1~0 := 2; 20450#L570-3 assume !(1 == ~E_2~0); 20448#L575-3 assume 1 == ~E_3~0;~E_3~0 := 2; 20446#L580-3 assume 1 == ~E_4~0;~E_4~0 := 2; 20444#L585-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 20437#L364-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 20433#L391-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 20431#L392-1 start_simulation_#t~ret12 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret12;havoc start_simulation_#t~ret12; 20429#L785 assume !(0 == start_simulation_~tmp~3); 19650#L785-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret11, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 19651#L364-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 19634#L391-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 19690#L392-2 stop_simulation_#t~ret11 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret11;havoc stop_simulation_#t~ret11; 19842#L740 assume !(0 != stop_simulation_~tmp~2);stop_simulation_~__retres2~0 := 1; 19597#L747 stop_simulation_#res := stop_simulation_~__retres2~0; 19598#L748 start_simulation_#t~ret13 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret13;havoc start_simulation_#t~ret13; 19726#L798 assume !(0 != start_simulation_~tmp___0~1); 19727#L766-1 [2018-11-23 12:43:38,899 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 12:43:38,899 INFO L82 PathProgramCache]: Analyzing trace with hash -1463119959, now seen corresponding path program 2 times [2018-11-23 12:43:38,899 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 12:43:38,899 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 12:43:38,900 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 12:43:38,900 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 12:43:38,900 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 12:43:38,903 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-23 12:43:38,907 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-23 12:43:38,915 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 12:43:38,915 INFO L82 PathProgramCache]: Analyzing trace with hash -615074265, now seen corresponding path program 2 times [2018-11-23 12:43:38,915 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 12:43:38,915 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 12:43:38,916 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 12:43:38,916 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-23 12:43:38,916 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 12:43:38,919 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 12:43:38,958 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 12:43:38,958 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 12:43:38,958 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-11-23 12:43:38,958 INFO L811 eck$LassoCheckResult]: loop already infeasible [2018-11-23 12:43:38,959 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-11-23 12:43:38,959 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-11-23 12:43:38,959 INFO L87 Difference]: Start difference. First operand 1180 states and 1663 transitions. cyclomatic complexity: 487 Second operand 5 states. [2018-11-23 12:43:39,020 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 12:43:39,020 INFO L93 Difference]: Finished difference Result 2050 states and 2853 transitions. [2018-11-23 12:43:39,021 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2018-11-23 12:43:39,021 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2050 states and 2853 transitions. [2018-11-23 12:43:39,025 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 1972 [2018-11-23 12:43:39,029 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2050 states to 2050 states and 2853 transitions. [2018-11-23 12:43:39,029 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2050 [2018-11-23 12:43:39,030 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2050 [2018-11-23 12:43:39,030 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2050 states and 2853 transitions. [2018-11-23 12:43:39,032 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-23 12:43:39,032 INFO L705 BuchiCegarLoop]: Abstraction has 2050 states and 2853 transitions. [2018-11-23 12:43:39,033 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2050 states and 2853 transitions. [2018-11-23 12:43:39,042 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2050 to 1192. [2018-11-23 12:43:39,042 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1192 states. [2018-11-23 12:43:39,044 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1192 states to 1192 states and 1675 transitions. [2018-11-23 12:43:39,044 INFO L728 BuchiCegarLoop]: Abstraction has 1192 states and 1675 transitions. [2018-11-23 12:43:39,044 INFO L608 BuchiCegarLoop]: Abstraction has 1192 states and 1675 transitions. [2018-11-23 12:43:39,045 INFO L442 BuchiCegarLoop]: ======== Iteration 13============ [2018-11-23 12:43:39,045 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1192 states and 1675 transitions. [2018-11-23 12:43:39,047 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 1122 [2018-11-23 12:43:39,047 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-23 12:43:39,047 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-23 12:43:39,048 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 12:43:39,048 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 12:43:39,048 INFO L794 eck$LassoCheckResult]: Stem: 22972#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2; 22790#L-1 havoc main_#res;havoc main_~__retres1~6;havoc main_~__retres1~6;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 22791#L729 havoc start_simulation_#t~ret12, start_simulation_#t~ret13, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 23015#L324 assume 1 == ~m_i~0;~m_st~0 := 0; 23016#L331-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 22940#L336-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 22941#L341-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 22968#L346-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 22794#L351-1 assume !(0 == ~M_E~0); 22795#L492-1 assume !(0 == ~T1_E~0); 23070#L497-1 assume !(0 == ~T2_E~0); 23071#L502-1 assume !(0 == ~T3_E~0); 23099#L507-1 assume !(0 == ~T4_E~0); 22966#L512-1 assume !(0 == ~E_1~0); 22967#L517-1 assume !(0 == ~E_2~0); 22986#L522-1 assume !(0 == ~E_3~0); 22813#L527-1 assume !(0 == ~E_4~0); 22814#L532-1 havoc activate_threads_#t~ret6, activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 22848#L228 assume !(1 == ~m_pc~0); 22857#L228-2 is_master_triggered_~__retres1~0 := 0; 23182#L239 is_master_triggered_#res := is_master_triggered_~__retres1~0; 23207#L240 activate_threads_#t~ret6 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret6;havoc activate_threads_#t~ret6; 23009#L605 assume !(0 != activate_threads_~tmp~1); 23010#L605-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 23012#L247 assume !(1 == ~t1_pc~0); 23029#L247-2 is_transmit1_triggered_~__retres1~1 := 0; 23030#L258 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 22936#L259 activate_threads_#t~ret7 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 22937#L613 assume !(0 != activate_threads_~tmp___0~0); 23192#L613-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 23055#L266 assume !(1 == ~t2_pc~0); 23056#L266-2 is_transmit2_triggered_~__retres1~2 := 0; 23058#L277 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 23059#L278 activate_threads_#t~ret8 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 22775#L621 assume !(0 != activate_threads_~tmp___1~0); 22776#L621-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 22782#L285 assume !(1 == ~t3_pc~0); 22773#L285-2 is_transmit3_triggered_~__retres1~3 := 0; 22774#L296 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 22783#L297 activate_threads_#t~ret9 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 22963#L629 assume !(0 != activate_threads_~tmp___2~0); 23060#L629-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 23061#L304 assume !(1 == ~t4_pc~0); 23077#L304-2 is_transmit4_triggered_~__retres1~4 := 0; 23078#L315 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 23096#L316 activate_threads_#t~ret10 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 22838#L637 assume !(0 != activate_threads_~tmp___3~0); 22839#L637-2 assume !(1 == ~M_E~0); 22842#L545-1 assume !(1 == ~T1_E~0); 22962#L550-1 assume !(1 == ~T2_E~0); 22786#L555-1 assume !(1 == ~T3_E~0); 22787#L560-1 assume !(1 == ~T4_E~0); 22844#L565-1 assume !(1 == ~E_1~0); 22847#L570-1 assume !(1 == ~E_2~0); 23115#L575-1 assume !(1 == ~E_3~0); 23150#L580-1 assume !(1 == ~E_4~0); 23193#L766-1 [2018-11-23 12:43:39,048 INFO L796 eck$LassoCheckResult]: Loop: 23193#L766-1 assume !false; 23053#L767 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret0, eval_#t~nondet1, eval_~tmp_ndt_1~0, eval_#t~nondet2, eval_~tmp_ndt_2~0, eval_#t~nondet3, eval_~tmp_ndt_3~0, eval_#t~nondet4, eval_~tmp_ndt_4~0, eval_#t~nondet5, eval_~tmp_ndt_5~0, eval_~tmp~0;havoc eval_~tmp~0; 22854#L467 assume !false; 23410#L402 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 23409#L364 assume !(0 == ~m_st~0); 23406#L368 assume !(0 == ~t1_st~0); 23407#L372 assume !(0 == ~t2_st~0); 23408#L376 assume !(0 == ~t3_st~0); 23405#L380 assume !(0 == ~t4_st~0);exists_runnable_thread_~__retres1~5 := 0; 23389#L391 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 23381#L392 eval_#t~ret0 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret0;havoc eval_#t~ret0; 23378#L406 assume !(0 != eval_~tmp~0); 23379#L482 start_simulation_~kernel_st~0 := 2; 23664#L324-1 start_simulation_~kernel_st~0 := 3; 23661#L492-2 assume !(0 == ~M_E~0); 23658#L492-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 23655#L497-3 assume !(0 == ~T2_E~0); 23556#L502-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 23555#L507-3 assume !(0 == ~T4_E~0); 23553#L512-3 assume 0 == ~E_1~0;~E_1~0 := 1; 22994#L517-3 assume !(0 == ~E_2~0); 22995#L522-3 assume 0 == ~E_3~0;~E_3~0 := 1; 22829#L527-3 assume !(0 == ~E_4~0); 22830#L532-3 havoc activate_threads_#t~ret6, activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 22850#L228-15 assume 1 == ~m_pc~0; 22870#L229-5 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0 := 1; 22871#L239-5 is_master_triggered_#res := is_master_triggered_~__retres1~0; 23957#L240-5 activate_threads_#t~ret6 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret6;havoc activate_threads_#t~ret6; 23954#L605-15 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 22944#L605-17 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 22959#L247-15 assume !(1 == ~t1_pc~0); 22952#L247-17 is_transmit1_triggered_~__retres1~1 := 0; 22953#L258-5 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 23002#L259-5 activate_threads_#t~ret7 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 23113#L613-15 assume !(0 != activate_threads_~tmp___0~0); 23168#L613-17 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 23449#L266-15 assume !(1 == ~t2_pc~0); 23448#L266-17 is_transmit2_triggered_~__retres1~2 := 0; 23256#L277-5 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 23257#L278-5 activate_threads_#t~ret8 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 23006#L621-15 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 23007#L621-17 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 23011#L285-15 assume !(1 == ~t3_pc~0); 23033#L285-17 is_transmit3_triggered_~__retres1~3 := 0; 22806#L296-5 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 22807#L297-5 activate_threads_#t~ret9 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 22985#L629-15 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 23188#L629-17 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 23048#L304-15 assume 1 == ~t4_pc~0; 23049#L305-5 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 23054#L315-5 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 23084#L316-5 activate_threads_#t~ret10 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 22771#L637-15 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 22772#L637-17 assume 1 == ~M_E~0;~M_E~0 := 2; 22781#L545-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 22913#L550-3 assume !(1 == ~T2_E~0); 22989#L555-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 22817#L560-3 assume !(1 == ~T4_E~0); 22818#L565-3 assume 1 == ~E_1~0;~E_1~0 := 2; 22849#L570-3 assume !(1 == ~E_2~0); 23127#L575-3 assume 1 == ~E_3~0;~E_3~0 := 2; 23157#L580-3 assume 1 == ~E_4~0;~E_4~0 := 2; 23068#L585-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 23069#L364-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 23788#L391-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 23786#L392-1 start_simulation_#t~ret12 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret12;havoc start_simulation_#t~ret12; 23785#L785 assume !(0 == start_simulation_~tmp~3); 23783#L785-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret11, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 23776#L364-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 23772#L391-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 23771#L392-2 stop_simulation_#t~ret11 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret11;havoc stop_simulation_#t~ret11; 23770#L740 assume !(0 != stop_simulation_~tmp~2);stop_simulation_~__retres2~0 := 1; 23769#L747 stop_simulation_#res := stop_simulation_~__retres2~0; 23768#L748 start_simulation_#t~ret13 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret13;havoc start_simulation_#t~ret13; 23767#L798 assume !(0 != start_simulation_~tmp___0~1); 23193#L766-1 [2018-11-23 12:43:39,048 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 12:43:39,049 INFO L82 PathProgramCache]: Analyzing trace with hash -1463119959, now seen corresponding path program 3 times [2018-11-23 12:43:39,049 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 12:43:39,049 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 12:43:39,049 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 12:43:39,049 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-23 12:43:39,050 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 12:43:39,052 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-23 12:43:39,056 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-23 12:43:39,063 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 12:43:39,063 INFO L82 PathProgramCache]: Analyzing trace with hash -1470455504, now seen corresponding path program 1 times [2018-11-23 12:43:39,063 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 12:43:39,064 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 12:43:39,064 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 12:43:39,064 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-23 12:43:39,064 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 12:43:39,068 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 12:43:39,099 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 12:43:39,099 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 12:43:39,099 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-11-23 12:43:39,099 INFO L811 eck$LassoCheckResult]: loop already infeasible [2018-11-23 12:43:39,099 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-11-23 12:43:39,099 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-11-23 12:43:39,099 INFO L87 Difference]: Start difference. First operand 1192 states and 1675 transitions. cyclomatic complexity: 487 Second operand 5 states. [2018-11-23 12:43:39,184 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 12:43:39,184 INFO L93 Difference]: Finished difference Result 3866 states and 5377 transitions. [2018-11-23 12:43:39,185 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2018-11-23 12:43:39,185 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 3866 states and 5377 transitions. [2018-11-23 12:43:39,193 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 3772 [2018-11-23 12:43:39,202 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 3866 states to 3866 states and 5377 transitions. [2018-11-23 12:43:39,202 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 3866 [2018-11-23 12:43:39,204 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 3866 [2018-11-23 12:43:39,204 INFO L73 IsDeterministic]: Start isDeterministic. Operand 3866 states and 5377 transitions. [2018-11-23 12:43:39,207 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-23 12:43:39,207 INFO L705 BuchiCegarLoop]: Abstraction has 3866 states and 5377 transitions. [2018-11-23 12:43:39,209 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3866 states and 5377 transitions. [2018-11-23 12:43:39,223 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3866 to 1204. [2018-11-23 12:43:39,223 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1204 states. [2018-11-23 12:43:39,225 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1204 states to 1204 states and 1687 transitions. [2018-11-23 12:43:39,225 INFO L728 BuchiCegarLoop]: Abstraction has 1204 states and 1687 transitions. [2018-11-23 12:43:39,225 INFO L608 BuchiCegarLoop]: Abstraction has 1204 states and 1687 transitions. [2018-11-23 12:43:39,225 INFO L442 BuchiCegarLoop]: ======== Iteration 14============ [2018-11-23 12:43:39,226 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1204 states and 1687 transitions. [2018-11-23 12:43:39,228 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 1134 [2018-11-23 12:43:39,228 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-23 12:43:39,228 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-23 12:43:39,229 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 12:43:39,229 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 12:43:39,229 INFO L794 eck$LassoCheckResult]: Stem: 28051#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2; 27866#L-1 havoc main_#res;havoc main_~__retres1~6;havoc main_~__retres1~6;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 27867#L729 havoc start_simulation_#t~ret12, start_simulation_#t~ret13, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 28095#L324 assume 1 == ~m_i~0;~m_st~0 := 0; 28096#L331-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 28016#L336-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 28017#L341-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 28048#L346-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 27869#L351-1 assume !(0 == ~M_E~0); 27870#L492-1 assume !(0 == ~T1_E~0); 28144#L497-1 assume !(0 == ~T2_E~0); 28145#L502-1 assume !(0 == ~T3_E~0); 28170#L507-1 assume !(0 == ~T4_E~0); 28044#L512-1 assume !(0 == ~E_1~0); 28045#L517-1 assume !(0 == ~E_2~0); 28065#L522-1 assume !(0 == ~E_3~0); 27887#L527-1 assume !(0 == ~E_4~0); 27888#L532-1 havoc activate_threads_#t~ret6, activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 27921#L228 assume !(1 == ~m_pc~0); 27930#L228-2 is_master_triggered_~__retres1~0 := 0; 28242#L239 is_master_triggered_#res := is_master_triggered_~__retres1~0; 28259#L240 activate_threads_#t~ret6 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret6;havoc activate_threads_#t~ret6; 28088#L605 assume !(0 != activate_threads_~tmp~1); 28089#L605-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 28092#L247 assume !(1 == ~t1_pc~0); 28104#L247-2 is_transmit1_triggered_~__retres1~1 := 0; 28105#L258 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 28011#L259 activate_threads_#t~ret7 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 28012#L613 assume !(0 != activate_threads_~tmp___0~0); 28251#L613-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 28129#L266 assume !(1 == ~t2_pc~0); 28130#L266-2 is_transmit2_triggered_~__retres1~2 := 0; 28132#L277 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 28133#L278 activate_threads_#t~ret8 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 27851#L621 assume !(0 != activate_threads_~tmp___1~0); 27852#L621-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 27856#L285 assume !(1 == ~t3_pc~0); 27847#L285-2 is_transmit3_triggered_~__retres1~3 := 0; 27848#L296 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 27859#L297 activate_threads_#t~ret9 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 28043#L629 assume !(0 != activate_threads_~tmp___2~0); 28134#L629-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 28135#L304 assume !(1 == ~t4_pc~0); 28150#L304-2 is_transmit4_triggered_~__retres1~4 := 0; 28151#L315 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 28167#L316 activate_threads_#t~ret10 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 27913#L637 assume !(0 != activate_threads_~tmp___3~0); 27914#L637-2 assume !(1 == ~M_E~0); 27915#L545-1 assume !(1 == ~T1_E~0); 28040#L550-1 assume !(1 == ~T2_E~0); 27862#L555-1 assume !(1 == ~T3_E~0); 27863#L560-1 assume !(1 == ~T4_E~0); 27917#L565-1 assume !(1 == ~E_1~0); 27920#L570-1 assume !(1 == ~E_2~0); 28181#L575-1 assume !(1 == ~E_3~0); 28215#L580-1 assume !(1 == ~E_4~0); 28252#L766-1 [2018-11-23 12:43:39,229 INFO L796 eck$LassoCheckResult]: Loop: 28252#L766-1 assume !false; 28530#L767 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret0, eval_#t~nondet1, eval_~tmp_ndt_1~0, eval_#t~nondet2, eval_~tmp_ndt_2~0, eval_#t~nondet3, eval_~tmp_ndt_3~0, eval_#t~nondet4, eval_~tmp_ndt_4~0, eval_#t~nondet5, eval_~tmp_ndt_5~0, eval_~tmp~0;havoc eval_~tmp~0; 28508#L467 assume !false; 28427#L402 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 28428#L364 assume !(0 == ~m_st~0); 28420#L368 assume !(0 == ~t1_st~0); 28421#L372 assume !(0 == ~t2_st~0); 28414#L376 assume !(0 == ~t3_st~0); 28415#L380 assume !(0 == ~t4_st~0);exists_runnable_thread_~__retres1~5 := 0; 28405#L391 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 28406#L392 eval_#t~ret0 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret0;havoc eval_#t~ret0; 28376#L406 assume !(0 != eval_~tmp~0); 28377#L482 start_simulation_~kernel_st~0 := 2; 28352#L324-1 start_simulation_~kernel_st~0 := 3; 28353#L492-2 assume !(0 == ~M_E~0); 28344#L492-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 28345#L497-3 assume !(0 == ~T2_E~0); 28334#L502-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 28335#L507-3 assume !(0 == ~T4_E~0); 28503#L512-3 assume 0 == ~E_1~0;~E_1~0 := 1; 28072#L517-3 assume !(0 == ~E_2~0); 28073#L522-3 assume 0 == ~E_3~0;~E_3~0 := 1; 28107#L527-3 assume !(0 == ~E_4~0); 28501#L532-3 havoc activate_threads_#t~ret6, activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 28500#L228-15 assume 1 == ~m_pc~0; 27943#L229-5 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0 := 1; 27944#L239-5 is_master_triggered_#res := is_master_triggered_~__retres1~0; 27949#L240-5 activate_threads_#t~ret6 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret6;havoc activate_threads_#t~ret6; 27950#L605-15 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 28021#L605-17 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 28032#L247-15 assume !(1 == ~t1_pc~0); 28038#L247-17 is_transmit1_triggered_~__retres1~1 := 0; 28082#L258-5 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 28083#L259-5 activate_threads_#t~ret7 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 28178#L613-15 assume !(0 != activate_threads_~tmp___0~0); 28208#L613-17 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 28209#L266-15 assume !(1 == ~t2_pc~0); 28839#L266-17 is_transmit2_triggered_~__retres1~2 := 0; 28838#L277-5 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 28189#L278-5 activate_threads_#t~ret8 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 28190#L621-15 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 28837#L621-17 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 28836#L285-15 assume !(1 == ~t3_pc~0); 28835#L285-17 is_transmit3_triggered_~__retres1~3 := 0; 28834#L296-5 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 28833#L297-5 activate_threads_#t~ret9 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 28832#L629-15 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 28831#L629-17 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 28830#L304-15 assume 1 == ~t4_pc~0; 28828#L305-5 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 28827#L315-5 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 28826#L316-5 activate_threads_#t~ret10 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 28825#L637-15 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 28824#L637-17 assume 1 == ~M_E~0;~M_E~0 := 2; 28823#L545-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 28822#L550-3 assume !(1 == ~T2_E~0); 28821#L555-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 28820#L560-3 assume !(1 == ~T4_E~0); 28819#L565-3 assume 1 == ~E_1~0;~E_1~0 := 2; 28818#L570-3 assume !(1 == ~E_2~0); 28817#L575-3 assume 1 == ~E_3~0;~E_3~0 := 2; 28816#L580-3 assume 1 == ~E_4~0;~E_4~0 := 2; 28815#L585-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 28812#L364-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 28801#L391-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 28797#L392-1 start_simulation_#t~ret12 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret12;havoc start_simulation_#t~ret12; 28788#L785 assume !(0 == start_simulation_~tmp~3); 27971#L785-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret11, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 27972#L364-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 28562#L391-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 28560#L392-2 stop_simulation_#t~ret11 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret11;havoc stop_simulation_#t~ret11; 28558#L740 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 28556#L747 stop_simulation_#res := stop_simulation_~__retres2~0; 28543#L748 start_simulation_#t~ret13 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret13;havoc start_simulation_#t~ret13; 28541#L798 assume !(0 != start_simulation_~tmp___0~1); 28252#L766-1 [2018-11-23 12:43:39,230 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 12:43:39,230 INFO L82 PathProgramCache]: Analyzing trace with hash -1463119959, now seen corresponding path program 4 times [2018-11-23 12:43:39,230 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 12:43:39,230 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 12:43:39,230 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 12:43:39,230 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 12:43:39,231 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 12:43:39,233 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-23 12:43:39,237 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-23 12:43:39,243 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 12:43:39,243 INFO L82 PathProgramCache]: Analyzing trace with hash -1470515086, now seen corresponding path program 1 times [2018-11-23 12:43:39,243 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 12:43:39,244 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 12:43:39,244 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 12:43:39,244 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-23 12:43:39,244 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 12:43:39,249 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 12:43:39,304 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 12:43:39,304 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 12:43:39,304 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-11-23 12:43:39,304 INFO L811 eck$LassoCheckResult]: loop already infeasible [2018-11-23 12:43:39,304 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-11-23 12:43:39,305 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-11-23 12:43:39,305 INFO L87 Difference]: Start difference. First operand 1204 states and 1687 transitions. cyclomatic complexity: 487 Second operand 5 states. [2018-11-23 12:43:39,368 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 12:43:39,368 INFO L93 Difference]: Finished difference Result 1655 states and 2315 transitions. [2018-11-23 12:43:39,369 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2018-11-23 12:43:39,369 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1655 states and 2315 transitions. [2018-11-23 12:43:39,373 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 1581 [2018-11-23 12:43:39,378 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1655 states to 1655 states and 2315 transitions. [2018-11-23 12:43:39,378 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1655 [2018-11-23 12:43:39,379 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1655 [2018-11-23 12:43:39,379 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1655 states and 2315 transitions. [2018-11-23 12:43:39,380 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-23 12:43:39,380 INFO L705 BuchiCegarLoop]: Abstraction has 1655 states and 2315 transitions. [2018-11-23 12:43:39,382 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1655 states and 2315 transitions. [2018-11-23 12:43:39,392 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1655 to 1210. [2018-11-23 12:43:39,392 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1210 states. [2018-11-23 12:43:39,394 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1210 states to 1210 states and 1674 transitions. [2018-11-23 12:43:39,394 INFO L728 BuchiCegarLoop]: Abstraction has 1210 states and 1674 transitions. [2018-11-23 12:43:39,394 INFO L608 BuchiCegarLoop]: Abstraction has 1210 states and 1674 transitions. [2018-11-23 12:43:39,394 INFO L442 BuchiCegarLoop]: ======== Iteration 15============ [2018-11-23 12:43:39,394 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1210 states and 1674 transitions. [2018-11-23 12:43:39,397 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 1140 [2018-11-23 12:43:39,397 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-23 12:43:39,397 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-23 12:43:39,398 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 12:43:39,398 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 12:43:39,398 INFO L794 eck$LassoCheckResult]: Stem: 30927#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2; 30737#L-1 havoc main_#res;havoc main_~__retres1~6;havoc main_~__retres1~6;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 30738#L729 havoc start_simulation_#t~ret12, start_simulation_#t~ret13, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 30969#L324 assume 1 == ~m_i~0;~m_st~0 := 0; 30970#L331-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 30891#L336-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 30892#L341-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 30922#L346-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 30741#L351-1 assume !(0 == ~M_E~0); 30742#L492-1 assume !(0 == ~T1_E~0); 31023#L497-1 assume !(0 == ~T2_E~0); 31024#L502-1 assume !(0 == ~T3_E~0); 31052#L507-1 assume !(0 == ~T4_E~0); 30920#L512-1 assume !(0 == ~E_1~0); 30921#L517-1 assume !(0 == ~E_2~0); 30942#L522-1 assume !(0 == ~E_3~0); 30760#L527-1 assume !(0 == ~E_4~0); 30761#L532-1 havoc activate_threads_#t~ret6, activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 30794#L228 assume !(1 == ~m_pc~0); 30804#L228-2 is_master_triggered_~__retres1~0 := 0; 31134#L239 is_master_triggered_#res := is_master_triggered_~__retres1~0; 31163#L240 activate_threads_#t~ret6 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret6;havoc activate_threads_#t~ret6; 30962#L605 assume !(0 != activate_threads_~tmp~1); 30963#L605-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 30965#L247 assume !(1 == ~t1_pc~0); 30983#L247-2 is_transmit1_triggered_~__retres1~1 := 0; 30984#L258 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 30886#L259 activate_threads_#t~ret7 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 30887#L613 assume !(0 != activate_threads_~tmp___0~0); 31142#L613-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 31009#L266 assume !(1 == ~t2_pc~0); 31010#L266-2 is_transmit2_triggered_~__retres1~2 := 0; 31012#L277 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 31013#L278 activate_threads_#t~ret8 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 30722#L621 assume !(0 != activate_threads_~tmp___1~0); 30723#L621-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 30729#L285 assume !(1 == ~t3_pc~0); 30720#L285-2 is_transmit3_triggered_~__retres1~3 := 0; 30721#L296 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 30730#L297 activate_threads_#t~ret9 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 30917#L629 assume !(0 != activate_threads_~tmp___2~0); 31014#L629-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 31015#L304 assume !(1 == ~t4_pc~0); 31030#L304-2 is_transmit4_triggered_~__retres1~4 := 0; 31031#L315 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 31049#L316 activate_threads_#t~ret10 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 30784#L637 assume !(0 != activate_threads_~tmp___3~0); 30785#L637-2 assume !(1 == ~M_E~0); 30788#L545-1 assume !(1 == ~T1_E~0); 30916#L550-1 assume !(1 == ~T2_E~0); 30733#L555-1 assume !(1 == ~T3_E~0); 30734#L560-1 assume !(1 == ~T4_E~0); 30790#L565-1 assume !(1 == ~E_1~0); 30793#L570-1 assume !(1 == ~E_2~0); 31068#L575-1 assume !(1 == ~E_3~0); 31098#L580-1 assume !(1 == ~E_4~0); 31143#L766-1 [2018-11-23 12:43:39,398 INFO L796 eck$LassoCheckResult]: Loop: 31143#L766-1 assume !false; 31714#L767 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret0, eval_#t~nondet1, eval_~tmp_ndt_1~0, eval_#t~nondet2, eval_~tmp_ndt_2~0, eval_#t~nondet3, eval_~tmp_ndt_3~0, eval_#t~nondet4, eval_~tmp_ndt_4~0, eval_#t~nondet5, eval_~tmp_ndt_5~0, eval_~tmp~0;havoc eval_~tmp~0; 31707#L467 assume !false; 31661#L402 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 31658#L364 assume !(0 == ~m_st~0); 31655#L368 assume !(0 == ~t1_st~0); 31656#L372 assume !(0 == ~t2_st~0); 31657#L376 assume !(0 == ~t3_st~0); 31653#L380 assume !(0 == ~t4_st~0);exists_runnable_thread_~__retres1~5 := 0; 31654#L391 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 31647#L392 eval_#t~ret0 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret0;havoc eval_#t~ret0; 31648#L406 assume !(0 != eval_~tmp~0); 31076#L482 start_simulation_~kernel_st~0 := 2; 30974#L324-1 start_simulation_~kernel_st~0 := 3; 30975#L492-2 assume !(0 == ~M_E~0); 31126#L492-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 30995#L497-3 assume !(0 == ~T2_E~0); 30996#L502-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 31044#L507-3 assume !(0 == ~T4_E~0); 30866#L512-3 assume 0 == ~E_1~0;~E_1~0 := 1; 30867#L517-3 assume !(0 == ~E_2~0); 30951#L522-3 assume 0 == ~E_3~0;~E_3~0 := 1; 30986#L527-3 assume !(0 == ~E_4~0); 30796#L532-3 havoc activate_threads_#t~ret6, activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 30797#L228-15 assume 1 == ~m_pc~0; 30817#L229-5 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0 := 1; 30818#L239-5 is_master_triggered_#res := is_master_triggered_~__retres1~0; 31900#L240-5 activate_threads_#t~ret6 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret6;havoc activate_threads_#t~ret6; 31897#L605-15 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 30896#L605-17 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 30910#L247-15 assume !(1 == ~t1_pc~0); 30904#L247-17 is_transmit1_triggered_~__retres1~1 := 0; 30905#L258-5 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 30956#L259-5 activate_threads_#t~ret7 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 31065#L613-15 assume !(0 != activate_threads_~tmp___0~0); 31094#L613-17 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 31095#L266-15 assume !(1 == ~t2_pc~0); 31075#L266-17 is_transmit2_triggered_~__retres1~2 := 0; 31138#L277-5 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 31144#L278-5 activate_threads_#t~ret8 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 31569#L621-15 assume !(0 != activate_threads_~tmp___1~0); 31568#L621-17 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 31567#L285-15 assume !(1 == ~t3_pc~0); 31566#L285-17 is_transmit3_triggered_~__retres1~3 := 0; 31565#L296-5 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 31563#L297-5 activate_threads_#t~ret9 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 31162#L629-15 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 31139#L629-17 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 31002#L304-15 assume 1 == ~t4_pc~0; 31003#L305-5 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 31557#L315-5 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 31556#L316-5 activate_threads_#t~ret10 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 31555#L637-15 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 31554#L637-17 assume 1 == ~M_E~0;~M_E~0 := 2; 31553#L545-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 31552#L550-3 assume !(1 == ~T2_E~0); 31551#L555-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 31549#L560-3 assume !(1 == ~T4_E~0); 31547#L565-3 assume 1 == ~E_1~0;~E_1~0 := 2; 31545#L570-3 assume !(1 == ~E_2~0); 31542#L575-3 assume 1 == ~E_3~0;~E_3~0 := 2; 31538#L580-3 assume 1 == ~E_4~0;~E_4~0 := 2; 31535#L585-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 31530#L364-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 31525#L391-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 31521#L392-1 start_simulation_#t~ret12 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret12;havoc start_simulation_#t~ret12; 30836#L785 assume !(0 == start_simulation_~tmp~3); 30837#L785-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret11, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 31743#L364-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 31739#L391-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 31737#L392-2 stop_simulation_#t~ret11 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret11;havoc stop_simulation_#t~ret11; 31734#L740 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 31731#L747 stop_simulation_#res := stop_simulation_~__retres2~0; 31729#L748 start_simulation_#t~ret13 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret13;havoc start_simulation_#t~ret13; 31727#L798 assume !(0 != start_simulation_~tmp___0~1); 31143#L766-1 [2018-11-23 12:43:39,399 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 12:43:39,399 INFO L82 PathProgramCache]: Analyzing trace with hash -1463119959, now seen corresponding path program 5 times [2018-11-23 12:43:39,399 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 12:43:39,399 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 12:43:39,400 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 12:43:39,400 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 12:43:39,400 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 12:43:39,403 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-23 12:43:39,407 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-23 12:43:39,414 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 12:43:39,415 INFO L82 PathProgramCache]: Analyzing trace with hash 1980446708, now seen corresponding path program 1 times [2018-11-23 12:43:39,415 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 12:43:39,415 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 12:43:39,415 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 12:43:39,416 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-23 12:43:39,416 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 12:43:39,421 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 12:43:39,467 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 12:43:39,467 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 12:43:39,467 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-11-23 12:43:39,467 INFO L811 eck$LassoCheckResult]: loop already infeasible [2018-11-23 12:43:39,468 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-11-23 12:43:39,468 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-11-23 12:43:39,468 INFO L87 Difference]: Start difference. First operand 1210 states and 1674 transitions. cyclomatic complexity: 468 Second operand 5 states. [2018-11-23 12:43:39,572 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 12:43:39,572 INFO L93 Difference]: Finished difference Result 2087 states and 2893 transitions. [2018-11-23 12:43:39,573 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2018-11-23 12:43:39,573 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2087 states and 2893 transitions. [2018-11-23 12:43:39,578 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 2013 [2018-11-23 12:43:39,585 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2087 states to 2087 states and 2893 transitions. [2018-11-23 12:43:39,585 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2087 [2018-11-23 12:43:39,586 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2087 [2018-11-23 12:43:39,586 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2087 states and 2893 transitions. [2018-11-23 12:43:39,587 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-23 12:43:39,588 INFO L705 BuchiCegarLoop]: Abstraction has 2087 states and 2893 transitions. [2018-11-23 12:43:39,589 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2087 states and 2893 transitions. [2018-11-23 12:43:39,600 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2087 to 1243. [2018-11-23 12:43:39,600 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1243 states. [2018-11-23 12:43:39,602 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1243 states to 1243 states and 1697 transitions. [2018-11-23 12:43:39,603 INFO L728 BuchiCegarLoop]: Abstraction has 1243 states and 1697 transitions. [2018-11-23 12:43:39,603 INFO L608 BuchiCegarLoop]: Abstraction has 1243 states and 1697 transitions. [2018-11-23 12:43:39,603 INFO L442 BuchiCegarLoop]: ======== Iteration 16============ [2018-11-23 12:43:39,603 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1243 states and 1697 transitions. [2018-11-23 12:43:39,606 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 1173 [2018-11-23 12:43:39,606 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-23 12:43:39,606 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-23 12:43:39,607 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 12:43:39,607 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 12:43:39,607 INFO L794 eck$LassoCheckResult]: Stem: 34238#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2; 34051#L-1 havoc main_#res;havoc main_~__retres1~6;havoc main_~__retres1~6;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 34052#L729 havoc start_simulation_#t~ret12, start_simulation_#t~ret13, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 34279#L324 assume 1 == ~m_i~0;~m_st~0 := 0; 34280#L331-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 34202#L336-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 34203#L341-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 34235#L346-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 34053#L351-1 assume !(0 == ~M_E~0); 34054#L492-1 assume !(0 == ~T1_E~0); 34338#L497-1 assume !(0 == ~T2_E~0); 34339#L502-1 assume !(0 == ~T3_E~0); 34366#L507-1 assume !(0 == ~T4_E~0); 34232#L512-1 assume !(0 == ~E_1~0); 34233#L517-1 assume !(0 == ~E_2~0); 34251#L522-1 assume !(0 == ~E_3~0); 34073#L527-1 assume !(0 == ~E_4~0); 34074#L532-1 havoc activate_threads_#t~ret6, activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 34107#L228 assume !(1 == ~m_pc~0); 34116#L228-2 is_master_triggered_~__retres1~0 := 0; 34438#L239 is_master_triggered_#res := is_master_triggered_~__retres1~0; 34463#L240 activate_threads_#t~ret6 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret6;havoc activate_threads_#t~ret6; 34270#L605 assume !(0 != activate_threads_~tmp~1); 34271#L605-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 34274#L247 assume !(1 == ~t1_pc~0); 34295#L247-2 is_transmit1_triggered_~__retres1~1 := 0; 34296#L258 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 34197#L259 activate_threads_#t~ret7 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 34198#L613 assume !(0 != activate_threads_~tmp___0~0); 34447#L613-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 34322#L266 assume !(1 == ~t2_pc~0); 34323#L266-2 is_transmit2_triggered_~__retres1~2 := 0; 34325#L277 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 34326#L278 activate_threads_#t~ret8 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 34034#L621 assume !(0 != activate_threads_~tmp___1~0); 34035#L621-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 34041#L285 assume !(1 == ~t3_pc~0); 34032#L285-2 is_transmit3_triggered_~__retres1~3 := 0; 34033#L296 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 34044#L297 activate_threads_#t~ret9 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 34231#L629 assume !(0 != activate_threads_~tmp___2~0); 34327#L629-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 34328#L304 assume !(1 == ~t4_pc~0); 34345#L304-2 is_transmit4_triggered_~__retres1~4 := 0; 34346#L315 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 34363#L316 activate_threads_#t~ret10 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 34099#L637 assume !(0 != activate_threads_~tmp___3~0); 34100#L637-2 assume !(1 == ~M_E~0); 34101#L545-1 assume !(1 == ~T1_E~0); 34228#L550-1 assume !(1 == ~T2_E~0); 34047#L555-1 assume !(1 == ~T3_E~0); 34048#L560-1 assume !(1 == ~T4_E~0); 34103#L565-1 assume !(1 == ~E_1~0); 34106#L570-1 assume !(1 == ~E_2~0); 34382#L575-1 assume !(1 == ~E_3~0); 34415#L580-1 assume !(1 == ~E_4~0); 34448#L766-1 [2018-11-23 12:43:39,607 INFO L796 eck$LassoCheckResult]: Loop: 34448#L766-1 assume !false; 34890#L767 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret0, eval_#t~nondet1, eval_~tmp_ndt_1~0, eval_#t~nondet2, eval_~tmp_ndt_2~0, eval_#t~nondet3, eval_~tmp_ndt_3~0, eval_#t~nondet4, eval_~tmp_ndt_4~0, eval_#t~nondet5, eval_~tmp_ndt_5~0, eval_~tmp~0;havoc eval_~tmp~0; 34889#L467 assume !false; 34888#L402 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 34887#L364 assume !(0 == ~m_st~0); 34884#L368 assume !(0 == ~t1_st~0); 34885#L372 assume !(0 == ~t2_st~0); 34886#L376 assume !(0 == ~t3_st~0); 34882#L380 assume !(0 == ~t4_st~0);exists_runnable_thread_~__retres1~5 := 0; 34883#L391 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 34799#L392 eval_#t~ret0 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret0;havoc eval_#t~ret0; 34800#L406 assume !(0 != eval_~tmp~0); 35077#L482 start_simulation_~kernel_st~0 := 2; 35076#L324-1 start_simulation_~kernel_st~0 := 3; 35075#L492-2 assume !(0 == ~M_E~0); 35074#L492-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 35073#L497-3 assume !(0 == ~T2_E~0); 35072#L502-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 35071#L507-3 assume !(0 == ~T4_E~0); 35070#L512-3 assume 0 == ~E_1~0;~E_1~0 := 1; 35069#L517-3 assume !(0 == ~E_2~0); 35068#L522-3 assume 0 == ~E_3~0;~E_3~0 := 1; 35067#L527-3 assume !(0 == ~E_4~0); 35066#L532-3 havoc activate_threads_#t~ret6, activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 35065#L228-15 assume 1 == ~m_pc~0; 35063#L229-5 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0 := 1; 35061#L239-5 is_master_triggered_#res := is_master_triggered_~__retres1~0; 35059#L240-5 activate_threads_#t~ret6 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret6;havoc activate_threads_#t~ret6; 35057#L605-15 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 34222#L605-17 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 34223#L247-15 assume !(1 == ~t1_pc~0); 34216#L247-17 is_transmit1_triggered_~__retres1~1 := 0; 34217#L258-5 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 34265#L259-5 activate_threads_#t~ret7 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 34379#L613-15 assume !(0 != activate_threads_~tmp___0~0); 34410#L613-17 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 34411#L266-15 assume !(1 == ~t2_pc~0); 34388#L266-17 is_transmit2_triggered_~__retres1~2 := 0; 34441#L277-5 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 34391#L278-5 activate_threads_#t~ret8 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 34268#L621-15 assume !(0 != activate_threads_~tmp___1~0); 34269#L621-17 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 34272#L285-15 assume !(1 == ~t3_pc~0); 34304#L285-17 is_transmit3_triggered_~__retres1~3 := 0; 34978#L296-5 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 34977#L297-5 activate_threads_#t~ret9 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 34976#L629-15 assume !(0 != activate_threads_~tmp___2~0); 34975#L629-17 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 34974#L304-15 assume 1 == ~t4_pc~0; 34972#L305-5 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 34970#L315-5 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 34968#L316-5 activate_threads_#t~ret10 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 34966#L637-15 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 34964#L637-17 assume 1 == ~M_E~0;~M_E~0 := 2; 34962#L545-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 34959#L550-3 assume !(1 == ~T2_E~0); 34957#L555-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 34955#L560-3 assume !(1 == ~T4_E~0); 34953#L565-3 assume 1 == ~E_1~0;~E_1~0 := 2; 34951#L570-3 assume !(1 == ~E_2~0); 34949#L575-3 assume 1 == ~E_3~0;~E_3~0 := 2; 34947#L580-3 assume 1 == ~E_4~0;~E_4~0 := 2; 34945#L585-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 34940#L364-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 34935#L391-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 34932#L392-1 start_simulation_#t~ret12 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret12;havoc start_simulation_#t~ret12; 34928#L785 assume !(0 == start_simulation_~tmp~3); 34925#L785-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret11, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 34920#L364-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 34916#L391-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 34913#L392-2 stop_simulation_#t~ret11 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret11;havoc stop_simulation_#t~ret11; 34910#L740 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 34906#L747 stop_simulation_#res := stop_simulation_~__retres2~0; 34904#L748 start_simulation_#t~ret13 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret13;havoc start_simulation_#t~ret13; 34899#L798 assume !(0 != start_simulation_~tmp___0~1); 34448#L766-1 [2018-11-23 12:43:39,607 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 12:43:39,607 INFO L82 PathProgramCache]: Analyzing trace with hash -1463119959, now seen corresponding path program 6 times [2018-11-23 12:43:39,608 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 12:43:39,608 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 12:43:39,608 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 12:43:39,608 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 12:43:39,608 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 12:43:39,612 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-23 12:43:39,615 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-23 12:43:39,633 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 12:43:39,633 INFO L82 PathProgramCache]: Analyzing trace with hash -928317194, now seen corresponding path program 1 times [2018-11-23 12:43:39,633 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 12:43:39,634 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 12:43:39,634 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 12:43:39,634 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-23 12:43:39,634 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 12:43:39,639 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-23 12:43:39,644 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-23 12:43:39,652 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 12:43:39,652 INFO L82 PathProgramCache]: Analyzing trace with hash 1060034638, now seen corresponding path program 1 times [2018-11-23 12:43:39,652 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 12:43:39,652 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 12:43:39,653 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 12:43:39,655 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 12:43:39,655 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 12:43:39,660 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 12:43:39,702 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 12:43:39,702 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 12:43:39,703 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-23 12:43:40,033 WARN L180 SmtUtils]: Spent 324.00 ms on a formula simplification. DAG size of input: 161 DAG size of output: 144 [2018-11-23 12:43:40,147 WARN L180 SmtUtils]: Spent 106.00 ms on a formula simplification that was a NOOP. DAG size: 124 [2018-11-23 12:43:40,153 INFO L216 LassoAnalysis]: Preferences: [2018-11-23 12:43:40,154 INFO L124 ssoRankerPreferences]: Compute integeral hull: false [2018-11-23 12:43:40,154 INFO L125 ssoRankerPreferences]: Enable LassoPartitioneer: true [2018-11-23 12:43:40,154 INFO L126 ssoRankerPreferences]: Term annotations enabled: false [2018-11-23 12:43:40,155 INFO L127 ssoRankerPreferences]: Use exernal solver: true [2018-11-23 12:43:40,155 INFO L128 ssoRankerPreferences]: SMT solver command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2018-11-23 12:43:40,155 INFO L129 ssoRankerPreferences]: Dump SMT script to file: false [2018-11-23 12:43:40,155 INFO L130 ssoRankerPreferences]: Path of dumped script: [2018-11-23 12:43:40,155 INFO L131 ssoRankerPreferences]: Filename of dumped script: transmitter.04_false-unreach-call_false-termination.cil.c_Iteration16_Loop [2018-11-23 12:43:40,155 INFO L132 ssoRankerPreferences]: MapElimAlgo: Frank [2018-11-23 12:43:40,155 INFO L282 LassoAnalysis]: Starting lasso preprocessing... [2018-11-23 12:43:40,172 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 12:43:40,175 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 12:43:40,180 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 12:43:40,184 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 12:43:40,188 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 12:43:40,190 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 12:43:40,194 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 12:43:40,196 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 12:43:40,197 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 12:43:40,199 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 12:43:40,202 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 12:43:40,206 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 12:43:40,211 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 12:43:40,214 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 12:43:40,216 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 12:43:40,217 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 12:43:40,221 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 12:43:40,223 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 12:43:40,226 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 12:43:40,229 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 12:43:40,231 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 12:43:40,233 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 12:43:40,234 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 12:43:40,238 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 12:43:40,240 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 12:43:40,248 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 12:43:40,250 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 12:43:40,252 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 12:43:40,254 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 12:43:40,256 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 12:43:40,259 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 12:43:40,263 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 12:43:40,265 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 12:43:40,269 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 12:43:40,272 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 12:43:40,274 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 12:43:40,276 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 12:43:40,277 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 12:43:40,279 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 12:43:40,282 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 12:43:40,285 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 12:43:40,286 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 12:43:40,288 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 12:43:40,293 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 12:43:40,295 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 12:43:40,297 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 12:43:40,299 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 12:43:40,301 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 12:43:40,305 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 12:43:40,309 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 12:43:40,637 INFO L300 LassoAnalysis]: Preprocessing complete. [2018-11-23 12:43:40,638 INFO L412 LassoAnalysis]: Checking for nontermination... No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_4e85c2a5-7fb1-4118-9476-ba8baa068460/bin-2019/uautomizer/z3 Starting monitored process 2 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 2 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2018-11-23 12:43:40,650 INFO L151 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2018-11-23 12:43:40,651 INFO L163 nArgumentSynthesizer]: Using integer mode. [2018-11-23 12:43:40,662 INFO L445 LassoAnalysis]: Proved nontermination for one component. [2018-11-23 12:43:40,662 INFO L448 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {ULTIMATE.start_stop_simulation_#t~ret11=0} Honda state: {ULTIMATE.start_stop_simulation_#t~ret11=0} Generalized eigenvectors: [] Lambdas: [] Nus: [] No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_4e85c2a5-7fb1-4118-9476-ba8baa068460/bin-2019/uautomizer/z3 Starting monitored process 3 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 3 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2018-11-23 12:43:40,680 INFO L151 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2018-11-23 12:43:40,681 INFO L163 nArgumentSynthesizer]: Using integer mode. [2018-11-23 12:43:40,685 INFO L445 LassoAnalysis]: Proved nontermination for one component. [2018-11-23 12:43:40,685 INFO L448 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {ULTIMATE.start_activate_threads_~tmp___0~0=0, ULTIMATE.start_is_transmit1_triggered_~__retres1~1=0, ULTIMATE.start_is_transmit1_triggered_#res=0} Honda state: {ULTIMATE.start_activate_threads_~tmp___0~0=0, ULTIMATE.start_is_transmit1_triggered_~__retres1~1=0, ULTIMATE.start_is_transmit1_triggered_#res=0} Generalized eigenvectors: [] Lambdas: [] Nus: [] No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_4e85c2a5-7fb1-4118-9476-ba8baa068460/bin-2019/uautomizer/z3 Starting monitored process 4 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 4 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2018-11-23 12:43:40,710 INFO L151 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2018-11-23 12:43:40,710 INFO L163 nArgumentSynthesizer]: Using integer mode. [2018-11-23 12:43:40,714 INFO L445 LassoAnalysis]: Proved nontermination for one component. [2018-11-23 12:43:40,714 INFO L448 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {ULTIMATE.start_stop_simulation_~__retres2~0=0, ULTIMATE.start_start_simulation_~tmp___0~1=0, ULTIMATE.start_stop_simulation_#res=0} Honda state: {ULTIMATE.start_stop_simulation_~__retres2~0=0, ULTIMATE.start_start_simulation_~tmp___0~1=0, ULTIMATE.start_stop_simulation_#res=0} Generalized eigenvectors: [] Lambdas: [] Nus: [] No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_4e85c2a5-7fb1-4118-9476-ba8baa068460/bin-2019/uautomizer/z3 Starting monitored process 5 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 5 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2018-11-23 12:43:40,745 INFO L151 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2018-11-23 12:43:40,746 INFO L163 nArgumentSynthesizer]: Using integer mode. No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_4e85c2a5-7fb1-4118-9476-ba8baa068460/bin-2019/uautomizer/z3 Starting monitored process 6 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 6 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2018-11-23 12:43:40,765 INFO L151 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 3 Nilpotent components: true [2018-11-23 12:43:40,766 INFO L163 nArgumentSynthesizer]: Using integer mode. [2018-11-23 12:43:40,789 INFO L452 LassoAnalysis]: Proving nontermination failed: No geometric nontermination argument exists. [2018-11-23 12:43:40,791 INFO L216 LassoAnalysis]: Preferences: [2018-11-23 12:43:40,791 INFO L124 ssoRankerPreferences]: Compute integeral hull: false [2018-11-23 12:43:40,791 INFO L125 ssoRankerPreferences]: Enable LassoPartitioneer: true [2018-11-23 12:43:40,791 INFO L126 ssoRankerPreferences]: Term annotations enabled: false [2018-11-23 12:43:40,791 INFO L127 ssoRankerPreferences]: Use exernal solver: false [2018-11-23 12:43:40,791 INFO L128 ssoRankerPreferences]: SMT solver command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2018-11-23 12:43:40,791 INFO L129 ssoRankerPreferences]: Dump SMT script to file: false [2018-11-23 12:43:40,791 INFO L130 ssoRankerPreferences]: Path of dumped script: [2018-11-23 12:43:40,791 INFO L131 ssoRankerPreferences]: Filename of dumped script: transmitter.04_false-unreach-call_false-termination.cil.c_Iteration16_Loop [2018-11-23 12:43:40,791 INFO L132 ssoRankerPreferences]: MapElimAlgo: Frank [2018-11-23 12:43:40,791 INFO L282 LassoAnalysis]: Starting lasso preprocessing... [2018-11-23 12:43:40,794 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 12:43:40,810 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 12:43:40,813 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 12:43:40,839 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 12:43:40,844 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 12:43:40,846 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 12:43:40,847 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 12:43:40,849 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 12:43:40,851 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 12:43:40,854 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 12:43:40,857 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 12:43:40,862 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 12:43:40,866 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 12:43:40,868 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 12:43:40,872 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 12:43:40,880 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 12:43:40,885 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 12:43:40,887 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 12:43:40,889 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 12:43:40,890 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 12:43:40,895 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 12:43:40,897 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 12:43:40,899 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 12:43:40,901 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 12:43:40,905 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 12:43:40,908 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 12:43:40,910 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 12:43:40,912 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 12:43:40,914 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 12:43:40,916 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 12:43:40,919 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 12:43:40,923 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 12:43:40,925 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 12:43:40,929 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 12:43:40,932 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 12:43:40,934 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 12:43:40,937 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 12:43:40,939 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 12:43:40,941 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 12:43:40,944 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 12:43:40,946 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 12:43:40,948 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 12:43:40,949 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 12:43:40,952 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 12:43:40,954 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 12:43:40,956 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 12:43:40,958 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 12:43:40,960 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 12:43:40,964 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 12:43:40,969 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-23 12:43:41,302 INFO L300 LassoAnalysis]: Preprocessing complete. [2018-11-23 12:43:41,307 INFO L497 LassoAnalysis]: Using template 'affine'. [2018-11-23 12:43:41,309 INFO L122 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSES Number of strict supporting invariants: 0 Number of non-strict supporting invariants: 1 Consider only non-deceasing supporting invariants: true Simplify termination arguments: true Simplify supporting invariants: trueOverapproximate stem: false [2018-11-23 12:43:41,314 INFO L339 nArgumentSynthesizer]: Template has degree 0. [2018-11-23 12:43:41,314 INFO L352 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2018-11-23 12:43:41,315 INFO L205 nArgumentSynthesizer]: 1 stem disjuncts [2018-11-23 12:43:41,315 INFO L206 nArgumentSynthesizer]: 2 loop disjuncts [2018-11-23 12:43:41,315 INFO L207 nArgumentSynthesizer]: 2 template conjuncts. [2018-11-23 12:43:41,316 INFO L402 nArgumentSynthesizer]: We have 4 Motzkin's Theorem applications. [2018-11-23 12:43:41,317 INFO L403 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2018-11-23 12:43:41,323 INFO L530 LassoAnalysis]: Proving termination failed for this template and these settings. [2018-11-23 12:43:41,324 INFO L122 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSES Number of strict supporting invariants: 0 Number of non-strict supporting invariants: 1 Consider only non-deceasing supporting invariants: true Simplify termination arguments: true Simplify supporting invariants: trueOverapproximate stem: false [2018-11-23 12:43:41,324 INFO L339 nArgumentSynthesizer]: Template has degree 0. [2018-11-23 12:43:41,324 INFO L352 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2018-11-23 12:43:41,324 INFO L205 nArgumentSynthesizer]: 1 stem disjuncts [2018-11-23 12:43:41,324 INFO L206 nArgumentSynthesizer]: 1 loop disjuncts [2018-11-23 12:43:41,324 INFO L207 nArgumentSynthesizer]: 2 template conjuncts. [2018-11-23 12:43:41,325 INFO L402 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2018-11-23 12:43:41,325 INFO L403 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2018-11-23 12:43:41,326 INFO L530 LassoAnalysis]: Proving termination failed for this template and these settings. [2018-11-23 12:43:41,326 INFO L122 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSES Number of strict supporting invariants: 0 Number of non-strict supporting invariants: 1 Consider only non-deceasing supporting invariants: true Simplify termination arguments: true Simplify supporting invariants: trueOverapproximate stem: false [2018-11-23 12:43:41,326 INFO L339 nArgumentSynthesizer]: Template has degree 0. [2018-11-23 12:43:41,326 INFO L352 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2018-11-23 12:43:41,326 INFO L205 nArgumentSynthesizer]: 1 stem disjuncts [2018-11-23 12:43:41,327 INFO L206 nArgumentSynthesizer]: 1 loop disjuncts [2018-11-23 12:43:41,327 INFO L207 nArgumentSynthesizer]: 2 template conjuncts. [2018-11-23 12:43:41,327 INFO L402 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2018-11-23 12:43:41,327 INFO L403 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2018-11-23 12:43:41,329 INFO L421 nArgumentSynthesizer]: Found a termination argument, trying to simplify. [2018-11-23 12:43:41,331 INFO L443 ModelExtractionUtils]: Simplification made 3 calls to the SMT solver. [2018-11-23 12:43:41,331 INFO L444 ModelExtractionUtils]: 0 out of 3 variables were initially zero. Simplification set additionally 0 variables to zero. [2018-11-23 12:43:41,332 INFO L437 nArgumentSynthesizer]: Simplifying supporting invariants... [2018-11-23 12:43:41,332 INFO L440 nArgumentSynthesizer]: Removed 0 redundant supporting invariants from a total of 0. [2018-11-23 12:43:41,333 INFO L518 LassoAnalysis]: Proved termination. [2018-11-23 12:43:41,333 INFO L520 LassoAnalysis]: Termination argument consisting of: Ranking function f(~E_3~0) = -1*~E_3~0 + 1 Supporting invariants [] [2018-11-23 12:43:41,334 INFO L297 tatePredicateManager]: 0 out of 0 supporting invariants were superfluous and have been removed [2018-11-23 12:43:41,364 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 12:43:41,382 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 12:43:41,385 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-23 12:43:41,409 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 12:43:41,411 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-23 12:43:41,433 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 12:43:41,437 INFO L152 lantAutomatonBouncer]: Defining deterministic Buchi interpolant automaton with honda bouncer for stem and without honda bouncer for loop.1 stem predicates 3 loop predicates [2018-11-23 12:43:41,437 INFO L72 iDifferenceNCSBLazy3]: Start buchiDifferenceNCSBLazy3. First operand 1243 states and 1697 transitions. cyclomatic complexity: 458 Second operand 5 states. [2018-11-23 12:43:41,552 INFO L76 iDifferenceNCSBLazy3]: Finished buchiDifferenceNCSBLazy3. First operand 1243 states and 1697 transitions. cyclomatic complexity: 458. Second operand 5 states. Result 4504 states and 6194 transitions. Complement of second has 5 states. [2018-11-23 12:43:41,553 INFO L142 InterpolantAutomaton]: Switched to read-only mode: Buchi interpolant automaton has 3 states 1 stem states 1 non-accepting loop states 1 accepting loop states [2018-11-23 12:43:41,553 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 5 states. [2018-11-23 12:43:41,554 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3 states to 3 states and 920 transitions. [2018-11-23 12:43:41,555 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 3 states and 920 transitions. Stem has 56 letters. Loop has 75 letters. [2018-11-23 12:43:41,559 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2018-11-23 12:43:41,559 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 3 states and 920 transitions. Stem has 131 letters. Loop has 75 letters. [2018-11-23 12:43:41,560 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2018-11-23 12:43:41,560 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 3 states and 920 transitions. Stem has 56 letters. Loop has 150 letters. [2018-11-23 12:43:41,561 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2018-11-23 12:43:41,561 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 4504 states and 6194 transitions. [2018-11-23 12:43:41,577 INFO L131 ngComponentsAnalysis]: Automaton has 12 accepting balls. 3361 [2018-11-23 12:43:41,589 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 4504 states to 4500 states and 6190 transitions. [2018-11-23 12:43:41,589 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 3452 [2018-11-23 12:43:41,592 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 3465 [2018-11-23 12:43:41,592 INFO L73 IsDeterministic]: Start isDeterministic. Operand 4500 states and 6190 transitions. [2018-11-23 12:43:41,592 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2018-11-23 12:43:41,592 INFO L705 BuchiCegarLoop]: Abstraction has 4500 states and 6190 transitions. [2018-11-23 12:43:41,595 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 4500 states and 6190 transitions. [2018-11-23 12:43:41,623 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 4500 to 3302. [2018-11-23 12:43:41,623 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3302 states. [2018-11-23 12:43:41,627 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3302 states to 3302 states and 4559 transitions. [2018-11-23 12:43:41,628 INFO L728 BuchiCegarLoop]: Abstraction has 3302 states and 4559 transitions. [2018-11-23 12:43:41,628 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-23 12:43:41,628 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-23 12:43:41,628 INFO L87 Difference]: Start difference. First operand 3302 states and 4559 transitions. Second operand 3 states. [2018-11-23 12:43:41,686 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 12:43:41,686 INFO L93 Difference]: Finished difference Result 5901 states and 7989 transitions. [2018-11-23 12:43:41,687 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-23 12:43:41,687 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 5901 states and 7989 transitions. [2018-11-23 12:43:41,702 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 3952 [2018-11-23 12:43:41,715 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 5901 states to 5901 states and 7989 transitions. [2018-11-23 12:43:41,715 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 4047 [2018-11-23 12:43:41,717 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 4047 [2018-11-23 12:43:41,718 INFO L73 IsDeterministic]: Start isDeterministic. Operand 5901 states and 7989 transitions. [2018-11-23 12:43:41,718 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2018-11-23 12:43:41,718 INFO L705 BuchiCegarLoop]: Abstraction has 5901 states and 7989 transitions. [2018-11-23 12:43:41,722 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 5901 states and 7989 transitions. [2018-11-23 12:43:41,760 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 5901 to 5523. [2018-11-23 12:43:41,760 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 5523 states. [2018-11-23 12:43:41,767 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 5523 states to 5523 states and 7521 transitions. [2018-11-23 12:43:41,767 INFO L728 BuchiCegarLoop]: Abstraction has 5523 states and 7521 transitions. [2018-11-23 12:43:41,767 INFO L608 BuchiCegarLoop]: Abstraction has 5523 states and 7521 transitions. [2018-11-23 12:43:41,767 INFO L442 BuchiCegarLoop]: ======== Iteration 17============ [2018-11-23 12:43:41,767 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 5523 states and 7521 transitions. [2018-11-23 12:43:41,779 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 3700 [2018-11-23 12:43:41,779 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-23 12:43:41,779 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-23 12:43:41,780 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 12:43:41,780 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 12:43:41,780 INFO L794 eck$LassoCheckResult]: Stem: 49772#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2; 49427#L-1 havoc main_#res;havoc main_~__retres1~6;havoc main_~__retres1~6;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 49428#L729 havoc start_simulation_#t~ret12, start_simulation_#t~ret13, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 49845#L324 assume 1 == ~m_i~0;~m_st~0 := 0; 49846#L331-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 49708#L336-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 49709#L341-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 49766#L346-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 49431#L351-1 assume !(0 == ~M_E~0); 49432#L492-1 assume !(0 == ~T1_E~0); 49939#L497-1 assume !(0 == ~T2_E~0); 49940#L502-1 assume !(0 == ~T3_E~0); 49990#L507-1 assume !(0 == ~T4_E~0); 49764#L512-1 assume !(0 == ~E_1~0); 49765#L517-1 assume !(0 == ~E_2~0); 49796#L522-1 assume !(0 == ~E_3~0); 49466#L527-1 assume !(0 == ~E_4~0); 49467#L532-1 havoc activate_threads_#t~ret6, activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 49527#L228 assume !(1 == ~m_pc~0); 49547#L228-2 is_master_triggered_~__retres1~0 := 0; 50103#L239 is_master_triggered_#res := is_master_triggered_~__retres1~0; 49548#L240 activate_threads_#t~ret6 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret6;havoc activate_threads_#t~ret6; 49549#L605 assume !(0 != activate_threads_~tmp~1); 49836#L605-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 49841#L247 assume !(1 == ~t1_pc~0); 49867#L247-2 is_transmit1_triggered_~__retres1~1 := 0; 49868#L258 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 49698#L259 activate_threads_#t~ret7 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 49699#L613 assume !(0 != activate_threads_~tmp___0~0); 50149#L613-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 49919#L266 assume !(1 == ~t2_pc~0); 49920#L266-2 is_transmit2_triggered_~__retres1~2 := 0; 49922#L277 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 49923#L278 activate_threads_#t~ret8 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 49403#L621 assume !(0 != activate_threads_~tmp___1~0); 49404#L621-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 49415#L285 assume !(1 == ~t3_pc~0); 49401#L285-2 is_transmit3_triggered_~__retres1~3 := 0; 49402#L296 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 49420#L297 activate_threads_#t~ret9 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 49759#L629 assume !(0 != activate_threads_~tmp___2~0); 49924#L629-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 49925#L304 assume !(1 == ~t4_pc~0); 49953#L304-2 is_transmit4_triggered_~__retres1~4 := 0; 49954#L315 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 49986#L316 activate_threads_#t~ret10 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 49516#L637 assume !(0 != activate_threads_~tmp___3~0); 49517#L637-2 assume !(1 == ~M_E~0); 49518#L545-1 assume !(1 == ~T1_E~0); 49758#L550-1 assume !(1 == ~T2_E~0); 49421#L555-1 assume !(1 == ~T3_E~0); 49422#L560-1 assume !(1 == ~T4_E~0); 49521#L565-1 assume !(1 == ~E_1~0); 49526#L570-1 assume !(1 == ~E_2~0); 50025#L575-1 assume !(1 == ~E_3~0); 50088#L580-1 assume 1 == ~E_4~0;~E_4~0 := 2; 50150#L766-1 [2018-11-23 12:43:41,780 INFO L796 eck$LassoCheckResult]: Loop: 50150#L766-1 assume !false; 54159#L767 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret0, eval_#t~nondet1, eval_~tmp_ndt_1~0, eval_#t~nondet2, eval_~tmp_ndt_2~0, eval_#t~nondet3, eval_~tmp_ndt_3~0, eval_#t~nondet4, eval_~tmp_ndt_4~0, eval_#t~nondet5, eval_~tmp_ndt_5~0, eval_~tmp~0;havoc eval_~tmp~0; 54158#L467 assume !false; 54150#L402 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 49996#L364 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 49674#L391 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 49675#L392 eval_#t~ret0 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret0;havoc eval_#t~ret0; 49500#L406 assume 0 != eval_~tmp~0; 49501#L406-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0;eval_~tmp_ndt_1~0 := eval_#t~nondet1;havoc eval_#t~nondet1; 49508#L414 assume 0 != eval_~tmp_ndt_1~0;~m_st~0 := 1; 49808#L49 assume !(0 == ~m_pc~0); 49809#L52 assume 1 == ~m_pc~0; 49469#L53 assume !false; 49568#L69 ~m_pc~0 := 1;~m_st~0 := 2; 52219#L411 assume !(0 == ~t1_st~0); 52215#L425 assume !(0 == ~t2_st~0); 52212#L439 assume !(0 == ~t3_st~0); 52209#L453 assume !(0 == ~t4_st~0); 52769#L467 assume !false; 52765#L402 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 52763#L364 assume !(0 == ~m_st~0); 52760#L368 assume !(0 == ~t1_st~0); 52761#L372 assume !(0 == ~t2_st~0); 52762#L376 assume !(0 == ~t3_st~0); 52758#L380 assume !(0 == ~t4_st~0);exists_runnable_thread_~__retres1~5 := 0; 52754#L391 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 52755#L392 eval_#t~ret0 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret0;havoc eval_#t~ret0; 54367#L406 assume !(0 != eval_~tmp~0); 54365#L482 start_simulation_~kernel_st~0 := 2; 54363#L324-1 start_simulation_~kernel_st~0 := 3; 54361#L492-2 assume !(0 == ~M_E~0); 54359#L492-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 54357#L497-3 assume !(0 == ~T2_E~0); 54355#L502-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 54354#L507-3 assume !(0 == ~T4_E~0); 54353#L512-3 assume 0 == ~E_1~0;~E_1~0 := 1; 54351#L517-3 assume !(0 == ~E_2~0); 54349#L522-3 assume 0 == ~E_3~0;~E_3~0 := 1; 54347#L527-3 assume !(0 == ~E_4~0); 54346#L532-3 havoc activate_threads_#t~ret6, activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 54344#L228-15 assume !(1 == ~m_pc~0); 54342#L228-17 is_master_triggered_~__retres1~0 := 0; 54341#L239-5 is_master_triggered_#res := is_master_triggered_~__retres1~0; 54157#L240-5 activate_threads_#t~ret6 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret6;havoc activate_threads_#t~ret6; 52202#L605-15 assume !(0 != activate_threads_~tmp~1); 52203#L605-17 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 52196#L247-15 assume !(1 == ~t1_pc~0); 52197#L247-17 is_transmit1_triggered_~__retres1~1 := 0; 51845#L258-5 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 51846#L259-5 activate_threads_#t~ret7 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 51833#L613-15 assume !(0 != activate_threads_~tmp___0~0); 51834#L613-17 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 51826#L266-15 assume !(1 == ~t2_pc~0); 51825#L266-17 is_transmit2_triggered_~__retres1~2 := 0; 51816#L277-5 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 51817#L278-5 activate_threads_#t~ret8 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 51808#L621-15 assume !(0 != activate_threads_~tmp___1~0); 51809#L621-17 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 51801#L285-15 assume !(1 == ~t3_pc~0); 51794#L285-17 is_transmit3_triggered_~__retres1~3 := 0; 51795#L296-5 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 51755#L297-5 activate_threads_#t~ret9 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 51753#L629-15 assume !(0 != activate_threads_~tmp___2~0); 51754#L629-17 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 51746#L304-15 assume 1 == ~t4_pc~0; 51747#L305-5 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 51740#L315-5 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 51741#L316-5 activate_threads_#t~ret10 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 51734#L637-15 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 51733#L637-17 assume 1 == ~M_E~0;~M_E~0 := 2; 51729#L545-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 51726#L550-3 assume !(1 == ~T2_E~0); 51722#L555-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 51723#L560-3 assume !(1 == ~T4_E~0); 51713#L565-3 assume 1 == ~E_1~0;~E_1~0 := 2; 51710#L570-3 assume !(1 == ~E_2~0); 51702#L575-3 assume 1 == ~E_3~0;~E_3~0 := 2; 51703#L580-3 assume 1 == ~E_4~0;~E_4~0 := 2; 53637#L585-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 53635#L364-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 53636#L391-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 54204#L392-1 start_simulation_#t~ret12 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret12;havoc start_simulation_#t~ret12; 54202#L785 assume !(0 == start_simulation_~tmp~3); 54195#L785-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret11, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 54181#L364-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 53360#L391-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 54179#L392-2 stop_simulation_#t~ret11 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret11;havoc stop_simulation_#t~ret11; 54178#L740 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 54175#L747 stop_simulation_#res := stop_simulation_~__retres2~0; 54173#L748 start_simulation_#t~ret13 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret13;havoc start_simulation_#t~ret13; 54168#L798 assume !(0 != start_simulation_~tmp___0~1); 50150#L766-1 [2018-11-23 12:43:41,781 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 12:43:41,781 INFO L82 PathProgramCache]: Analyzing trace with hash -1463119961, now seen corresponding path program 1 times [2018-11-23 12:43:41,781 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 12:43:41,781 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 12:43:41,781 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 12:43:41,782 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 12:43:41,782 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 12:43:41,785 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 12:43:41,803 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 12:43:41,803 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 12:43:41,803 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [1] imperfect sequences [] total 1 [2018-11-23 12:43:41,803 INFO L799 eck$LassoCheckResult]: stem already infeasible [2018-11-23 12:43:41,803 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 12:43:41,803 INFO L82 PathProgramCache]: Analyzing trace with hash 64244943, now seen corresponding path program 1 times [2018-11-23 12:43:41,803 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 12:43:41,803 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 12:43:41,804 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 12:43:41,804 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 12:43:41,804 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 12:43:41,810 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 12:43:41,824 INFO L134 CoverageAnalysis]: Checked inductivity of 6 backedges. 6 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 12:43:41,824 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 12:43:41,824 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-23 12:43:41,824 INFO L811 eck$LassoCheckResult]: loop already infeasible [2018-11-23 12:43:41,824 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-23 12:43:41,824 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-23 12:43:41,825 INFO L87 Difference]: Start difference. First operand 5523 states and 7521 transitions. cyclomatic complexity: 2010 Second operand 3 states. [2018-11-23 12:43:41,858 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 12:43:41,858 INFO L93 Difference]: Finished difference Result 5523 states and 7338 transitions. [2018-11-23 12:43:41,859 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-23 12:43:41,859 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 5523 states and 7338 transitions. [2018-11-23 12:43:41,872 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 3700 [2018-11-23 12:43:41,883 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 5523 states to 5523 states and 7338 transitions. [2018-11-23 12:43:41,883 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 3795 [2018-11-23 12:43:41,885 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 3795 [2018-11-23 12:43:41,885 INFO L73 IsDeterministic]: Start isDeterministic. Operand 5523 states and 7338 transitions. [2018-11-23 12:43:41,886 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2018-11-23 12:43:41,886 INFO L705 BuchiCegarLoop]: Abstraction has 5523 states and 7338 transitions. [2018-11-23 12:43:41,889 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 5523 states and 7338 transitions. [2018-11-23 12:43:41,920 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 5523 to 5523. [2018-11-23 12:43:41,920 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 5523 states. [2018-11-23 12:43:41,926 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 5523 states to 5523 states and 7338 transitions. [2018-11-23 12:43:41,927 INFO L728 BuchiCegarLoop]: Abstraction has 5523 states and 7338 transitions. [2018-11-23 12:43:41,927 INFO L608 BuchiCegarLoop]: Abstraction has 5523 states and 7338 transitions. [2018-11-23 12:43:41,927 INFO L442 BuchiCegarLoop]: ======== Iteration 18============ [2018-11-23 12:43:41,927 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 5523 states and 7338 transitions. [2018-11-23 12:43:41,938 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 3700 [2018-11-23 12:43:41,938 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-23 12:43:41,938 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-23 12:43:41,939 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 12:43:41,939 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 12:43:41,939 INFO L794 eck$LassoCheckResult]: Stem: 60823#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2; 60482#L-1 havoc main_#res;havoc main_~__retres1~6;havoc main_~__retres1~6;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 60483#L729 havoc start_simulation_#t~ret12, start_simulation_#t~ret13, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 60897#L324 assume 1 == ~m_i~0;~m_st~0 := 0; 60898#L331-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 60761#L336-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 60762#L341-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 60817#L346-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 60486#L351-1 assume !(0 == ~M_E~0); 60487#L492-1 assume !(0 == ~T1_E~0); 60987#L497-1 assume !(0 == ~T2_E~0); 60988#L502-1 assume !(0 == ~T3_E~0); 61040#L507-1 assume !(0 == ~T4_E~0); 60815#L512-1 assume !(0 == ~E_1~0); 60816#L517-1 assume !(0 == ~E_2~0); 60849#L522-1 assume !(0 == ~E_3~0); 60522#L527-1 assume !(0 == ~E_4~0); 60523#L532-1 havoc activate_threads_#t~ret6, activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 60585#L228 assume !(1 == ~m_pc~0); 60602#L228-2 is_master_triggered_~__retres1~0 := 0; 61154#L239 is_master_triggered_#res := is_master_triggered_~__retres1~0; 60603#L240 activate_threads_#t~ret6 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret6;havoc activate_threads_#t~ret6; 60604#L605 assume !(0 != activate_threads_~tmp~1); 60887#L605-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 60893#L247 assume !(1 == ~t1_pc~0); 60915#L247-2 is_transmit1_triggered_~__retres1~1 := 0; 60916#L258 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 60752#L259 activate_threads_#t~ret7 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 60753#L613 assume !(0 != activate_threads_~tmp___0~0); 61209#L613-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 60964#L266 assume !(1 == ~t2_pc~0); 60965#L266-2 is_transmit2_triggered_~__retres1~2 := 0; 60967#L277 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 60968#L278 activate_threads_#t~ret8 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 60460#L621 assume !(0 != activate_threads_~tmp___1~0); 60461#L621-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 60468#L285 assume !(1 == ~t3_pc~0); 60454#L285-2 is_transmit3_triggered_~__retres1~3 := 0; 60455#L296 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 60473#L297 activate_threads_#t~ret9 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 60814#L629 assume !(0 != activate_threads_~tmp___2~0); 60969#L629-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 60970#L304 assume !(1 == ~t4_pc~0); 60998#L304-2 is_transmit4_triggered_~__retres1~4 := 0; 60999#L315 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 61035#L316 activate_threads_#t~ret10 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 60573#L637 assume !(0 != activate_threads_~tmp___3~0); 60574#L637-2 assume !(1 == ~M_E~0); 60575#L545-1 assume !(1 == ~T1_E~0); 60809#L550-1 assume !(1 == ~T2_E~0); 60478#L555-1 assume !(1 == ~T3_E~0); 60479#L560-1 assume !(1 == ~T4_E~0); 60579#L565-1 assume !(1 == ~E_1~0); 60584#L570-1 assume !(1 == ~E_2~0); 61075#L575-1 assume !(1 == ~E_3~0); 61141#L580-1 assume !(1 == ~E_4~0); 61210#L766-1 assume !false; 61738#L767 [2018-11-23 12:43:41,939 INFO L796 eck$LassoCheckResult]: Loop: 61738#L767 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret0, eval_#t~nondet1, eval_~tmp_ndt_1~0, eval_#t~nondet2, eval_~tmp_ndt_2~0, eval_#t~nondet3, eval_~tmp_ndt_3~0, eval_#t~nondet4, eval_~tmp_ndt_4~0, eval_#t~nondet5, eval_~tmp_ndt_5~0, eval_~tmp~0;havoc eval_~tmp~0; 65580#L467 assume !false; 65578#L402 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 61045#L364 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 61046#L391 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 65448#L392 eval_#t~ret0 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret0;havoc eval_#t~ret0; 60555#L406 assume 0 != eval_~tmp~0; 60556#L406-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0;eval_~tmp_ndt_1~0 := eval_#t~nondet1;havoc eval_#t~nondet1; 64152#L414 assume 0 != eval_~tmp_ndt_1~0;~m_st~0 := 1; 64153#L49 assume !(0 == ~m_pc~0); 64808#L52 assume 1 == ~m_pc~0; 60623#L53 assume !false; 60624#L69 ~m_pc~0 := 1;~m_st~0 := 2; 61076#L411 assume !(0 == ~t1_st~0); 64801#L425 assume !(0 == ~t2_st~0); 64798#L439 assume !(0 == ~t3_st~0); 64797#L453 assume !(0 == ~t4_st~0); 64886#L467 assume !false; 64885#L402 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 64884#L364 assume !(0 == ~m_st~0); 64881#L368 assume !(0 == ~t1_st~0); 64882#L372 assume !(0 == ~t2_st~0); 64883#L376 assume !(0 == ~t3_st~0); 64879#L380 assume !(0 == ~t4_st~0);exists_runnable_thread_~__retres1~5 := 0; 64880#L391 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 64816#L392 eval_#t~ret0 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret0;havoc eval_#t~ret0; 64817#L406 assume !(0 != eval_~tmp~0); 65385#L482 start_simulation_~kernel_st~0 := 2; 65384#L324-1 start_simulation_~kernel_st~0 := 3; 65383#L492-2 assume !(0 == ~M_E~0); 65382#L492-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 65381#L497-3 assume !(0 == ~T2_E~0); 65380#L502-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 65379#L507-3 assume !(0 == ~T4_E~0); 65378#L512-3 assume 0 == ~E_1~0;~E_1~0 := 1; 65377#L517-3 assume !(0 == ~E_2~0); 65376#L522-3 assume !(0 == ~E_3~0); 65375#L527-3 assume !(0 == ~E_4~0); 65374#L532-3 havoc activate_threads_#t~ret6, activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 65373#L228-15 assume !(1 == ~m_pc~0); 65370#L228-17 is_master_triggered_~__retres1~0 := 0; 65371#L239-5 is_master_triggered_#res := is_master_triggered_~__retres1~0; 65767#L240-5 activate_threads_#t~ret6 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret6;havoc activate_threads_#t~ret6; 65071#L605-15 assume !(0 != activate_threads_~tmp~1); 65069#L605-17 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 65067#L247-15 assume !(1 == ~t1_pc~0); 65065#L247-17 is_transmit1_triggered_~__retres1~1 := 0; 65062#L258-5 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 65060#L259-5 activate_threads_#t~ret7 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 65058#L613-15 assume !(0 != activate_threads_~tmp___0~0); 65056#L613-17 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 65054#L266-15 assume !(1 == ~t2_pc~0); 65051#L266-17 is_transmit2_triggered_~__retres1~2 := 0; 65049#L277-5 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 65040#L278-5 activate_threads_#t~ret8 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 65035#L621-15 assume !(0 != activate_threads_~tmp___1~0); 65030#L621-17 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 65024#L285-15 assume !(1 == ~t3_pc~0); 65018#L285-17 is_transmit3_triggered_~__retres1~3 := 0; 65013#L296-5 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 65006#L297-5 activate_threads_#t~ret9 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 65001#L629-15 assume !(0 != activate_threads_~tmp___2~0); 64996#L629-17 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 64988#L304-15 assume !(1 == ~t4_pc~0); 64985#L304-17 is_transmit4_triggered_~__retres1~4 := 0; 64983#L315-5 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 64981#L316-5 activate_threads_#t~ret10 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 64979#L637-15 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 64977#L637-17 assume 1 == ~M_E~0;~M_E~0 := 2; 64975#L545-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 64972#L550-3 assume !(1 == ~T2_E~0); 64970#L555-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 64961#L560-3 assume !(1 == ~T4_E~0); 64954#L565-3 assume 1 == ~E_1~0;~E_1~0 := 2; 64946#L570-3 assume !(1 == ~E_2~0); 64942#L575-3 assume !(1 == ~E_3~0); 64936#L580-3 assume !(1 == ~E_4~0); 64926#L585-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 64923#L364-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 64924#L391-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 65564#L392-1 start_simulation_#t~ret12 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret12;havoc start_simulation_#t~ret12; 65565#L785 assume !(0 == start_simulation_~tmp~3); 65542#L785-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret11, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 65599#L364-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 64908#L391-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 65596#L392-2 stop_simulation_#t~ret11 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret11;havoc stop_simulation_#t~ret11; 65594#L740 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 65592#L747 stop_simulation_#res := stop_simulation_~__retres2~0; 65590#L748 start_simulation_#t~ret13 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret13;havoc start_simulation_#t~ret13; 65588#L798 assume !(0 != start_simulation_~tmp___0~1); 65586#L766-1 assume !false; 61738#L767 [2018-11-23 12:43:41,939 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 12:43:41,939 INFO L82 PathProgramCache]: Analyzing trace with hash 1887921798, now seen corresponding path program 1 times [2018-11-23 12:43:41,939 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 12:43:41,940 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 12:43:41,940 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 12:43:41,940 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 12:43:41,940 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 12:43:41,943 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-23 12:43:41,947 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-23 12:43:41,952 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 12:43:41,952 INFO L82 PathProgramCache]: Analyzing trace with hash 763334222, now seen corresponding path program 1 times [2018-11-23 12:43:41,952 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 12:43:41,952 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 12:43:41,953 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 12:43:41,953 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 12:43:41,953 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 12:43:41,956 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 12:43:41,975 INFO L134 CoverageAnalysis]: Checked inductivity of 6 backedges. 6 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 12:43:41,975 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 12:43:41,975 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-23 12:43:41,975 INFO L811 eck$LassoCheckResult]: loop already infeasible [2018-11-23 12:43:41,976 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-23 12:43:41,976 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-23 12:43:41,976 INFO L87 Difference]: Start difference. First operand 5523 states and 7338 transitions. cyclomatic complexity: 1827 Second operand 3 states. [2018-11-23 12:43:42,022 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 12:43:42,022 INFO L93 Difference]: Finished difference Result 6976 states and 9134 transitions. [2018-11-23 12:43:42,023 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-23 12:43:42,023 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 6976 states and 9134 transitions. [2018-11-23 12:43:42,040 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 4048 [2018-11-23 12:43:42,052 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 6976 states to 6976 states and 9134 transitions. [2018-11-23 12:43:42,052 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 4824 [2018-11-23 12:43:42,055 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 4824 [2018-11-23 12:43:42,055 INFO L73 IsDeterministic]: Start isDeterministic. Operand 6976 states and 9134 transitions. [2018-11-23 12:43:42,055 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2018-11-23 12:43:42,055 INFO L705 BuchiCegarLoop]: Abstraction has 6976 states and 9134 transitions. [2018-11-23 12:43:42,059 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 6976 states and 9134 transitions. [2018-11-23 12:43:42,099 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 6976 to 6550. [2018-11-23 12:43:42,099 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 6550 states. [2018-11-23 12:43:42,107 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 6550 states to 6550 states and 8630 transitions. [2018-11-23 12:43:42,107 INFO L728 BuchiCegarLoop]: Abstraction has 6550 states and 8630 transitions. [2018-11-23 12:43:42,107 INFO L608 BuchiCegarLoop]: Abstraction has 6550 states and 8630 transitions. [2018-11-23 12:43:42,107 INFO L442 BuchiCegarLoop]: ======== Iteration 19============ [2018-11-23 12:43:42,107 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 6550 states and 8630 transitions. [2018-11-23 12:43:42,121 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 4048 [2018-11-23 12:43:42,121 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-23 12:43:42,121 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-23 12:43:42,122 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 12:43:42,122 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 12:43:42,123 INFO L794 eck$LassoCheckResult]: Stem: 73332#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2; 72986#L-1 havoc main_#res;havoc main_~__retres1~6;havoc main_~__retres1~6;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 72987#L729 havoc start_simulation_#t~ret12, start_simulation_#t~ret13, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 73414#L324 assume 1 == ~m_i~0;~m_st~0 := 0; 73415#L331-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 73266#L336-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 73267#L341-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 73326#L346-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 72990#L351-1 assume !(0 == ~M_E~0); 72991#L492-1 assume !(0 == ~T1_E~0); 73509#L497-1 assume !(0 == ~T2_E~0); 73510#L502-1 assume !(0 == ~T3_E~0); 73563#L507-1 assume !(0 == ~T4_E~0); 73324#L512-1 assume !(0 == ~E_1~0); 73325#L517-1 assume !(0 == ~E_2~0); 73359#L522-1 assume !(0 == ~E_3~0); 73025#L527-1 assume !(0 == ~E_4~0); 73026#L532-1 havoc activate_threads_#t~ret6, activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 73087#L228 assume 1 == ~m_pc~0; 73102#L229 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0 := 1; 73103#L239 is_master_triggered_#res := is_master_triggered_~__retres1~0; 73770#L240 activate_threads_#t~ret6 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret6;havoc activate_threads_#t~ret6; 73769#L605 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 73403#L605-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 73407#L247 assume !(1 == ~t1_pc~0); 73437#L247-2 is_transmit1_triggered_~__retres1~1 := 0; 73438#L258 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 73257#L259 activate_threads_#t~ret7 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 73258#L613 assume !(0 != activate_threads_~tmp___0~0); 73735#L613-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 73490#L266 assume !(1 == ~t2_pc~0); 73491#L266-2 is_transmit2_triggered_~__retres1~2 := 0; 73493#L277 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 73494#L278 activate_threads_#t~ret8 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 72961#L621 assume !(0 != activate_threads_~tmp___1~0); 72962#L621-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 72974#L285 assume !(1 == ~t3_pc~0); 72959#L285-2 is_transmit3_triggered_~__retres1~3 := 0; 72960#L296 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 72975#L297 activate_threads_#t~ret9 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 73319#L629 assume !(0 != activate_threads_~tmp___2~0); 73495#L629-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 73496#L304 assume !(1 == ~t4_pc~0); 73523#L304-2 is_transmit4_triggered_~__retres1~4 := 0; 73524#L315 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 73559#L316 activate_threads_#t~ret10 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 73072#L637 assume !(0 != activate_threads_~tmp___3~0); 73073#L637-2 assume !(1 == ~M_E~0); 73078#L545-1 assume !(1 == ~T1_E~0); 73318#L550-1 assume !(1 == ~T2_E~0); 72980#L555-1 assume !(1 == ~T3_E~0); 72981#L560-1 assume !(1 == ~T4_E~0); 73081#L565-1 assume !(1 == ~E_1~0); 73086#L570-1 assume !(1 == ~E_2~0); 73589#L575-1 assume !(1 == ~E_3~0); 73736#L580-1 assume !(1 == ~E_4~0); 73737#L766-1 assume !false; 75435#L767 [2018-11-23 12:43:42,123 INFO L796 eck$LassoCheckResult]: Loop: 75435#L767 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret0, eval_#t~nondet1, eval_~tmp_ndt_1~0, eval_#t~nondet2, eval_~tmp_ndt_2~0, eval_#t~nondet3, eval_~tmp_ndt_3~0, eval_#t~nondet4, eval_~tmp_ndt_4~0, eval_#t~nondet5, eval_~tmp_ndt_5~0, eval_~tmp~0;havoc eval_~tmp~0; 77447#L467 assume !false; 77446#L402 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 77445#L364 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 77314#L391 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 77444#L392 eval_#t~ret0 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret0;havoc eval_#t~ret0; 77443#L406 assume 0 != eval_~tmp~0; 77442#L406-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0;eval_~tmp_ndt_1~0 := eval_#t~nondet1;havoc eval_#t~nondet1; 77061#L414 assume 0 != eval_~tmp_ndt_1~0;~m_st~0 := 1; 77433#L49 assume !(0 == ~m_pc~0); 77341#L52 assume 1 == ~m_pc~0; 77264#L53 assume !false; 77062#L69 ~m_pc~0 := 1;~m_st~0 := 2; 77057#L411 assume !(0 == ~t1_st~0); 77052#L425 assume !(0 == ~t2_st~0); 77049#L439 assume !(0 == ~t3_st~0); 77047#L453 assume !(0 == ~t4_st~0); 77316#L467 assume !false; 77315#L402 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 77313#L364 assume !(0 == ~m_st~0); 77310#L368 assume !(0 == ~t1_st~0); 77311#L372 assume !(0 == ~t2_st~0); 77312#L376 assume !(0 == ~t3_st~0); 77308#L380 assume !(0 == ~t4_st~0);exists_runnable_thread_~__retres1~5 := 0; 77309#L391 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 77098#L392 eval_#t~ret0 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret0;havoc eval_#t~ret0; 77099#L406 assume !(0 != eval_~tmp~0); 77581#L482 start_simulation_~kernel_st~0 := 2; 77580#L324-1 start_simulation_~kernel_st~0 := 3; 77579#L492-2 assume !(0 == ~M_E~0); 77578#L492-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 77577#L497-3 assume !(0 == ~T2_E~0); 77576#L502-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 77575#L507-3 assume !(0 == ~T4_E~0); 77574#L512-3 assume 0 == ~E_1~0;~E_1~0 := 1; 77573#L517-3 assume !(0 == ~E_2~0); 77572#L522-3 assume !(0 == ~E_3~0); 77571#L527-3 assume !(0 == ~E_4~0); 77570#L532-3 havoc activate_threads_#t~ret6, activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 77569#L228-15 assume 1 == ~m_pc~0; 77567#L229-5 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0 := 1; 77565#L239-5 is_master_triggered_#res := is_master_triggered_~__retres1~0; 77436#L240-5 activate_threads_#t~ret6 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret6;havoc activate_threads_#t~ret6; 77437#L605-15 assume !(0 != activate_threads_~tmp~1); 77427#L605-17 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 77426#L247-15 assume !(1 == ~t1_pc~0); 77425#L247-17 is_transmit1_triggered_~__retres1~1 := 0; 77424#L258-5 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 77423#L259-5 activate_threads_#t~ret7 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 77422#L613-15 assume !(0 != activate_threads_~tmp___0~0); 77420#L613-17 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 77418#L266-15 assume !(1 == ~t2_pc~0); 77415#L266-17 is_transmit2_triggered_~__retres1~2 := 0; 77413#L277-5 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 77411#L278-5 activate_threads_#t~ret8 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 77409#L621-15 assume !(0 != activate_threads_~tmp___1~0); 77407#L621-17 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 77405#L285-15 assume !(1 == ~t3_pc~0); 77402#L285-17 is_transmit3_triggered_~__retres1~3 := 0; 77400#L296-5 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 77398#L297-5 activate_threads_#t~ret9 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 77396#L629-15 assume !(0 != activate_threads_~tmp___2~0); 77394#L629-17 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 77392#L304-15 assume !(1 == ~t4_pc~0); 77389#L304-17 is_transmit4_triggered_~__retres1~4 := 0; 77387#L315-5 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 77385#L316-5 activate_threads_#t~ret10 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 77383#L637-15 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 77381#L637-17 assume 1 == ~M_E~0;~M_E~0 := 2; 77379#L545-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 77376#L550-3 assume !(1 == ~T2_E~0); 77374#L555-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 77372#L560-3 assume !(1 == ~T4_E~0); 77370#L565-3 assume 1 == ~E_1~0;~E_1~0 := 2; 77368#L570-3 assume !(1 == ~E_2~0); 77366#L575-3 assume !(1 == ~E_3~0); 77364#L580-3 assume !(1 == ~E_4~0); 77362#L585-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 77359#L364-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 77360#L391-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 77477#L392-1 start_simulation_#t~ret12 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret12;havoc start_simulation_#t~ret12; 77474#L785 assume !(0 == start_simulation_~tmp~3); 77472#L785-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret11, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 77471#L364-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 77339#L391-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 77470#L392-2 stop_simulation_#t~ret11 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret11;havoc stop_simulation_#t~ret11; 77469#L740 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 77467#L747 stop_simulation_#res := stop_simulation_~__retres2~0; 77463#L748 start_simulation_#t~ret13 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret13;havoc start_simulation_#t~ret13; 77457#L798 assume !(0 != start_simulation_~tmp___0~1); 77452#L766-1 assume !false; 75435#L767 [2018-11-23 12:43:42,123 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 12:43:42,123 INFO L82 PathProgramCache]: Analyzing trace with hash -606111613, now seen corresponding path program 1 times [2018-11-23 12:43:42,123 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 12:43:42,123 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 12:43:42,124 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 12:43:42,124 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 12:43:42,124 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 12:43:42,127 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 12:43:42,146 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 12:43:42,146 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 12:43:42,146 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2018-11-23 12:43:42,147 INFO L799 eck$LassoCheckResult]: stem already infeasible [2018-11-23 12:43:42,147 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 12:43:42,147 INFO L82 PathProgramCache]: Analyzing trace with hash 1464902447, now seen corresponding path program 1 times [2018-11-23 12:43:42,147 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 12:43:42,147 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 12:43:42,148 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 12:43:42,148 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 12:43:42,148 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 12:43:42,152 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 12:43:42,195 INFO L134 CoverageAnalysis]: Checked inductivity of 6 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 6 trivial. 0 not checked. [2018-11-23 12:43:42,195 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 12:43:42,195 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2018-11-23 12:43:42,195 INFO L811 eck$LassoCheckResult]: loop already infeasible [2018-11-23 12:43:42,195 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-23 12:43:42,196 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-23 12:43:42,196 INFO L87 Difference]: Start difference. First operand 6550 states and 8630 transitions. cyclomatic complexity: 2104 Second operand 3 states. [2018-11-23 12:43:42,228 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 12:43:42,228 INFO L93 Difference]: Finished difference Result 6482 states and 8485 transitions. [2018-11-23 12:43:42,229 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-23 12:43:42,229 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 6482 states and 8485 transitions. [2018-11-23 12:43:42,245 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 4048 [2018-11-23 12:43:42,257 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 6482 states to 6482 states and 8485 transitions. [2018-11-23 12:43:42,258 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 4480 [2018-11-23 12:43:42,260 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 4480 [2018-11-23 12:43:42,260 INFO L73 IsDeterministic]: Start isDeterministic. Operand 6482 states and 8485 transitions. [2018-11-23 12:43:42,260 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2018-11-23 12:43:42,260 INFO L705 BuchiCegarLoop]: Abstraction has 6482 states and 8485 transitions. [2018-11-23 12:43:42,264 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 6482 states and 8485 transitions. [2018-11-23 12:43:42,306 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 6482 to 6458. [2018-11-23 12:43:42,306 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 6458 states. [2018-11-23 12:43:42,314 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 6458 states to 6458 states and 8461 transitions. [2018-11-23 12:43:42,314 INFO L728 BuchiCegarLoop]: Abstraction has 6458 states and 8461 transitions. [2018-11-23 12:43:42,315 INFO L608 BuchiCegarLoop]: Abstraction has 6458 states and 8461 transitions. [2018-11-23 12:43:42,315 INFO L442 BuchiCegarLoop]: ======== Iteration 20============ [2018-11-23 12:43:42,315 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 6458 states and 8461 transitions. [2018-11-23 12:43:42,328 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 4048 [2018-11-23 12:43:42,328 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-23 12:43:42,328 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-23 12:43:42,329 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 12:43:42,329 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 12:43:42,329 INFO L794 eck$LassoCheckResult]: Stem: 86360#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2; 86029#L-1 havoc main_#res;havoc main_~__retres1~6;havoc main_~__retres1~6;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 86030#L729 havoc start_simulation_#t~ret12, start_simulation_#t~ret13, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 86437#L324 assume 1 == ~m_i~0;~m_st~0 := 0; 86438#L331-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 86302#L336-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 86303#L341-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 86354#L346-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 86033#L351-1 assume !(0 == ~M_E~0); 86034#L492-1 assume !(0 == ~T1_E~0); 86528#L497-1 assume !(0 == ~T2_E~0); 86529#L502-1 assume !(0 == ~T3_E~0); 86584#L507-1 assume !(0 == ~T4_E~0); 86352#L512-1 assume !(0 == ~E_1~0); 86353#L517-1 assume !(0 == ~E_2~0); 86385#L522-1 assume !(0 == ~E_3~0); 86068#L527-1 assume !(0 == ~E_4~0); 86069#L532-1 havoc activate_threads_#t~ret6, activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 86132#L228 assume !(1 == ~m_pc~0); 86734#L228-2 is_master_triggered_~__retres1~0 := 0; 86698#L239 is_master_triggered_#res := is_master_triggered_~__retres1~0; 86148#L240 activate_threads_#t~ret6 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret6;havoc activate_threads_#t~ret6; 86149#L605 assume !(0 != activate_threads_~tmp~1); 86425#L605-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 86430#L247 assume !(1 == ~t1_pc~0); 86457#L247-2 is_transmit1_triggered_~__retres1~1 := 0; 86458#L258 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 86294#L259 activate_threads_#t~ret7 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 86295#L613 assume !(0 != activate_threads_~tmp___0~0); 86755#L613-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 86507#L266 assume !(1 == ~t2_pc~0); 86508#L266-2 is_transmit2_triggered_~__retres1~2 := 0; 86510#L277 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 86511#L278 activate_threads_#t~ret8 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 86007#L621 assume !(0 != activate_threads_~tmp___1~0); 86008#L621-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 86015#L285 assume !(1 == ~t3_pc~0); 86001#L285-2 is_transmit3_triggered_~__retres1~3 := 0; 86002#L296 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 86020#L297 activate_threads_#t~ret9 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 86351#L629 assume !(0 != activate_threads_~tmp___2~0); 86512#L629-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 86513#L304 assume !(1 == ~t4_pc~0); 86538#L304-2 is_transmit4_triggered_~__retres1~4 := 0; 86539#L315 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 86580#L316 activate_threads_#t~ret10 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 86121#L637 assume !(0 != activate_threads_~tmp___3~0); 86122#L637-2 assume !(1 == ~M_E~0); 86123#L545-1 assume !(1 == ~T1_E~0); 86346#L550-1 assume !(1 == ~T2_E~0); 86025#L555-1 assume !(1 == ~T3_E~0); 86026#L560-1 assume !(1 == ~T4_E~0); 86126#L565-1 assume !(1 == ~E_1~0); 86131#L570-1 assume !(1 == ~E_2~0); 86619#L575-1 assume !(1 == ~E_3~0); 86682#L580-1 assume !(1 == ~E_4~0); 86756#L766-1 assume !false; 87072#L767 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret0, eval_#t~nondet1, eval_~tmp_ndt_1~0, eval_#t~nondet2, eval_~tmp_ndt_2~0, eval_#t~nondet3, eval_~tmp_ndt_3~0, eval_#t~nondet4, eval_~tmp_ndt_4~0, eval_#t~nondet5, eval_~tmp_ndt_5~0, eval_~tmp~0;havoc eval_~tmp~0; 88866#L467 [2018-11-23 12:43:42,329 INFO L796 eck$LassoCheckResult]: Loop: 88866#L467 assume !false; 88856#L402 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 88857#L364 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 88806#L391 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 88807#L392 eval_#t~ret0 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret0;havoc eval_#t~ret0; 88793#L406 assume 0 != eval_~tmp~0; 88794#L406-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0;eval_~tmp_ndt_1~0 := eval_#t~nondet1;havoc eval_#t~nondet1; 88783#L414 assume !(0 != eval_~tmp_ndt_1~0); 88780#L411 assume !(0 == ~t1_st~0); 88776#L425 assume !(0 == ~t2_st~0); 88882#L439 assume !(0 == ~t3_st~0); 88869#L453 assume !(0 == ~t4_st~0); 88866#L467 [2018-11-23 12:43:42,329 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 12:43:42,330 INFO L82 PathProgramCache]: Analyzing trace with hash -1603966133, now seen corresponding path program 1 times [2018-11-23 12:43:42,330 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 12:43:42,330 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 12:43:42,330 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 12:43:42,330 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 12:43:42,330 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 12:43:42,334 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-23 12:43:42,338 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-23 12:43:42,344 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 12:43:42,344 INFO L82 PathProgramCache]: Analyzing trace with hash 590384517, now seen corresponding path program 1 times [2018-11-23 12:43:42,344 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 12:43:42,345 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 12:43:42,345 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 12:43:42,345 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 12:43:42,345 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 12:43:42,347 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-23 12:43:42,348 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-23 12:43:42,349 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 12:43:42,349 INFO L82 PathProgramCache]: Analyzing trace with hash 162355663, now seen corresponding path program 1 times [2018-11-23 12:43:42,349 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 12:43:42,350 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 12:43:42,350 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 12:43:42,350 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 12:43:42,350 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 12:43:42,354 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 12:43:42,371 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 12:43:42,372 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 12:43:42,372 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-23 12:43:42,430 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-23 12:43:42,430 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-23 12:43:42,431 INFO L87 Difference]: Start difference. First operand 6458 states and 8461 transitions. cyclomatic complexity: 2027 Second operand 3 states. [2018-11-23 12:43:42,466 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 12:43:42,466 INFO L93 Difference]: Finished difference Result 11929 states and 15430 transitions. [2018-11-23 12:43:42,467 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-23 12:43:42,467 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 11929 states and 15430 transitions. [2018-11-23 12:43:42,539 INFO L131 ngComponentsAnalysis]: Automaton has 24 accepting balls. 6716 [2018-11-23 12:43:42,565 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 11929 states to 11929 states and 15430 transitions. [2018-11-23 12:43:42,565 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 8271 [2018-11-23 12:43:42,570 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 8271 [2018-11-23 12:43:42,570 INFO L73 IsDeterministic]: Start isDeterministic. Operand 11929 states and 15430 transitions. [2018-11-23 12:43:42,572 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2018-11-23 12:43:42,573 INFO L705 BuchiCegarLoop]: Abstraction has 11929 states and 15430 transitions. [2018-11-23 12:43:42,580 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 11929 states and 15430 transitions. [2018-11-23 12:43:42,676 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 11929 to 11425. [2018-11-23 12:43:42,676 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 11425 states. [2018-11-23 12:43:42,693 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 11425 states to 11425 states and 14827 transitions. [2018-11-23 12:43:42,693 INFO L728 BuchiCegarLoop]: Abstraction has 11425 states and 14827 transitions. [2018-11-23 12:43:42,693 INFO L608 BuchiCegarLoop]: Abstraction has 11425 states and 14827 transitions. [2018-11-23 12:43:42,693 INFO L442 BuchiCegarLoop]: ======== Iteration 21============ [2018-11-23 12:43:42,693 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 11425 states and 14827 transitions. [2018-11-23 12:43:42,719 INFO L131 ngComponentsAnalysis]: Automaton has 24 accepting balls. 6380 [2018-11-23 12:43:42,719 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-23 12:43:42,719 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-23 12:43:42,720 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 12:43:42,720 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 12:43:42,720 INFO L794 eck$LassoCheckResult]: Stem: 104765#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2; 104430#L-1 havoc main_#res;havoc main_~__retres1~6;havoc main_~__retres1~6;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 104431#L729 havoc start_simulation_#t~ret12, start_simulation_#t~ret13, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 104852#L324 assume 1 == ~m_i~0;~m_st~0 := 0; 104853#L331-1 assume !(1 == ~t1_i~0);~t1_st~0 := 2; 104703#L336-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 104704#L341-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 104856#L346-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 104857#L351-1 assume !(0 == ~M_E~0); 105233#L492-1 assume !(0 == ~T1_E~0); 105234#L497-1 assume !(0 == ~T2_E~0); 105014#L502-1 assume !(0 == ~T3_E~0); 105015#L507-1 assume !(0 == ~T4_E~0); 104756#L512-1 assume !(0 == ~E_1~0); 104757#L517-1 assume !(0 == ~E_2~0); 104878#L522-1 assume !(0 == ~E_3~0); 104879#L527-1 assume !(0 == ~E_4~0); 104531#L532-1 havoc activate_threads_#t~ret6, activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 104532#L228 assume !(1 == ~m_pc~0); 105192#L228-2 is_master_triggered_~__retres1~0 := 0; 105193#L239 is_master_triggered_#res := is_master_triggered_~__retres1~0; 104548#L240 activate_threads_#t~ret6 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret6;havoc activate_threads_#t~ret6; 104549#L605 assume !(0 != activate_threads_~tmp~1); 104845#L605-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 104846#L247 assume !(1 == ~t1_pc~0); 104880#L247-2 is_transmit1_triggered_~__retres1~1 := 0; 104881#L258 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 104693#L259 activate_threads_#t~ret7 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 104694#L613 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 105256#L613-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 104939#L266 assume !(1 == ~t2_pc~0); 104940#L266-2 is_transmit2_triggered_~__retres1~2 := 0; 104942#L277 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 104943#L278 activate_threads_#t~ret8 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 104403#L621 assume !(0 != activate_threads_~tmp___1~0); 104404#L621-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 104412#L285 assume !(1 == ~t3_pc~0); 104413#L285-2 is_transmit3_triggered_~__retres1~3 := 0; 104420#L296 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 104421#L297 activate_threads_#t~ret9 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 104992#L629 assume !(0 != activate_threads_~tmp___2~0); 104993#L629-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 105009#L304 assume !(1 == ~t4_pc~0); 105010#L304-2 is_transmit4_triggered_~__retres1~4 := 0; 105007#L315 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 105008#L316 activate_threads_#t~ret10 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 104519#L637 assume !(0 != activate_threads_~tmp___3~0); 104520#L637-2 assume !(1 == ~M_E~0); 104748#L545-1 assume !(1 == ~T1_E~0); 104749#L550-1 assume !(1 == ~T2_E~0); 104422#L555-1 assume !(1 == ~T3_E~0); 104423#L560-1 assume !(1 == ~T4_E~0); 104525#L565-1 assume !(1 == ~E_1~0); 104530#L570-1 assume !(1 == ~E_2~0); 105054#L575-1 assume !(1 == ~E_3~0); 105126#L580-1 assume !(1 == ~E_4~0); 105223#L766-1 assume !false; 105641#L767 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret0, eval_#t~nondet1, eval_~tmp_ndt_1~0, eval_#t~nondet2, eval_~tmp_ndt_2~0, eval_#t~nondet3, eval_~tmp_ndt_3~0, eval_#t~nondet4, eval_~tmp_ndt_4~0, eval_#t~nondet5, eval_~tmp_ndt_5~0, eval_~tmp~0;havoc eval_~tmp~0; 110758#L467 [2018-11-23 12:43:42,720 INFO L796 eck$LassoCheckResult]: Loop: 110758#L467 assume !false; 110756#L402 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 110754#L364 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 110752#L391 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 110750#L392 eval_#t~ret0 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret0;havoc eval_#t~ret0; 110748#L406 assume 0 != eval_~tmp~0; 110746#L406-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0;eval_~tmp_ndt_1~0 := eval_#t~nondet1;havoc eval_#t~nondet1; 110744#L414 assume !(0 != eval_~tmp_ndt_1~0); 109162#L411 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0;eval_~tmp_ndt_2~0 := eval_#t~nondet2;havoc eval_#t~nondet2; 108965#L428 assume !(0 != eval_~tmp_ndt_2~0); 108966#L425 assume !(0 == ~t2_st~0); 110767#L439 assume !(0 == ~t3_st~0); 110762#L453 assume !(0 == ~t4_st~0); 110758#L467 [2018-11-23 12:43:42,721 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 12:43:42,721 INFO L82 PathProgramCache]: Analyzing trace with hash -750579381, now seen corresponding path program 1 times [2018-11-23 12:43:42,721 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 12:43:42,721 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 12:43:42,721 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 12:43:42,721 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 12:43:42,722 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 12:43:42,724 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 12:43:42,755 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 12:43:42,755 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 12:43:42,755 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-23 12:43:42,755 INFO L799 eck$LassoCheckResult]: stem already infeasible [2018-11-23 12:43:42,755 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 12:43:42,755 INFO L82 PathProgramCache]: Analyzing trace with hash 976788691, now seen corresponding path program 1 times [2018-11-23 12:43:42,756 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 12:43:42,756 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 12:43:42,756 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 12:43:42,756 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 12:43:42,756 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 12:43:42,765 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-23 12:43:42,766 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-23 12:43:42,817 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-23 12:43:42,817 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-23 12:43:42,817 INFO L87 Difference]: Start difference. First operand 11425 states and 14827 transitions. cyclomatic complexity: 3438 Second operand 3 states. [2018-11-23 12:43:42,839 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 12:43:42,839 INFO L93 Difference]: Finished difference Result 7504 states and 9787 transitions. [2018-11-23 12:43:42,841 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-23 12:43:42,842 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 7504 states and 9787 transitions. [2018-11-23 12:43:42,863 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 4656 [2018-11-23 12:43:42,880 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 7504 states to 7504 states and 9787 transitions. [2018-11-23 12:43:42,881 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 5240 [2018-11-23 12:43:42,885 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 5240 [2018-11-23 12:43:42,885 INFO L73 IsDeterministic]: Start isDeterministic. Operand 7504 states and 9787 transitions. [2018-11-23 12:43:42,885 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2018-11-23 12:43:42,885 INFO L705 BuchiCegarLoop]: Abstraction has 7504 states and 9787 transitions. [2018-11-23 12:43:42,889 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 7504 states and 9787 transitions. [2018-11-23 12:43:42,942 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 7504 to 7504. [2018-11-23 12:43:42,942 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 7504 states. [2018-11-23 12:43:42,954 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 7504 states to 7504 states and 9787 transitions. [2018-11-23 12:43:42,954 INFO L728 BuchiCegarLoop]: Abstraction has 7504 states and 9787 transitions. [2018-11-23 12:43:42,954 INFO L608 BuchiCegarLoop]: Abstraction has 7504 states and 9787 transitions. [2018-11-23 12:43:42,954 INFO L442 BuchiCegarLoop]: ======== Iteration 22============ [2018-11-23 12:43:42,954 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 7504 states and 9787 transitions. [2018-11-23 12:43:42,971 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 4656 [2018-11-23 12:43:42,971 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-23 12:43:42,971 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-23 12:43:42,972 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 12:43:42,972 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 12:43:42,972 INFO L794 eck$LassoCheckResult]: Stem: 123693#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2; 123357#L-1 havoc main_#res;havoc main_~__retres1~6;havoc main_~__retres1~6;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 123358#L729 havoc start_simulation_#t~ret12, start_simulation_#t~ret13, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 123769#L324 assume 1 == ~m_i~0;~m_st~0 := 0; 123770#L331-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 123629#L336-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 123630#L341-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 123687#L346-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 123361#L351-1 assume !(0 == ~M_E~0); 123362#L492-1 assume !(0 == ~T1_E~0); 123872#L497-1 assume !(0 == ~T2_E~0); 123873#L502-1 assume !(0 == ~T3_E~0); 123926#L507-1 assume !(0 == ~T4_E~0); 123685#L512-1 assume !(0 == ~E_1~0); 123686#L517-1 assume !(0 == ~E_2~0); 123719#L522-1 assume !(0 == ~E_3~0); 123396#L527-1 assume !(0 == ~E_4~0); 123397#L532-1 havoc activate_threads_#t~ret6, activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 123457#L228 assume !(1 == ~m_pc~0); 124075#L228-2 is_master_triggered_~__retres1~0 := 0; 124030#L239 is_master_triggered_#res := is_master_triggered_~__retres1~0; 123473#L240 activate_threads_#t~ret6 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret6;havoc activate_threads_#t~ret6; 123474#L605 assume !(0 != activate_threads_~tmp~1); 123760#L605-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 123763#L247 assume !(1 == ~t1_pc~0); 123795#L247-2 is_transmit1_triggered_~__retres1~1 := 0; 123796#L258 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 123619#L259 activate_threads_#t~ret7 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 123620#L613 assume !(0 != activate_threads_~tmp___0~0); 124097#L613-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 123852#L266 assume !(1 == ~t2_pc~0); 123853#L266-2 is_transmit2_triggered_~__retres1~2 := 0; 123855#L277 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 123856#L278 activate_threads_#t~ret8 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 123333#L621 assume !(0 != activate_threads_~tmp___1~0); 123334#L621-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 123345#L285 assume !(1 == ~t3_pc~0); 123331#L285-2 is_transmit3_triggered_~__retres1~3 := 0; 123332#L296 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 123346#L297 activate_threads_#t~ret9 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 123680#L629 assume !(0 != activate_threads_~tmp___2~0); 123857#L629-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 123858#L304 assume !(1 == ~t4_pc~0); 123885#L304-2 is_transmit4_triggered_~__retres1~4 := 0; 123886#L315 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 123922#L316 activate_threads_#t~ret10 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 123442#L637 assume !(0 != activate_threads_~tmp___3~0); 123443#L637-2 assume !(1 == ~M_E~0); 123448#L545-1 assume !(1 == ~T1_E~0); 123679#L550-1 assume !(1 == ~T2_E~0); 123351#L555-1 assume !(1 == ~T3_E~0); 123352#L560-1 assume !(1 == ~T4_E~0); 123451#L565-1 assume !(1 == ~E_1~0); 123456#L570-1 assume !(1 == ~E_2~0); 123951#L575-1 assume !(1 == ~E_3~0); 124011#L580-1 assume !(1 == ~E_4~0); 124098#L766-1 assume !false; 125926#L767 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret0, eval_#t~nondet1, eval_~tmp_ndt_1~0, eval_#t~nondet2, eval_~tmp_ndt_2~0, eval_#t~nondet3, eval_~tmp_ndt_3~0, eval_#t~nondet4, eval_~tmp_ndt_4~0, eval_#t~nondet5, eval_~tmp_ndt_5~0, eval_~tmp~0;havoc eval_~tmp~0; 127069#L467 [2018-11-23 12:43:42,972 INFO L796 eck$LassoCheckResult]: Loop: 127069#L467 assume !false; 127065#L402 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 127061#L364 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 127056#L391 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 127049#L392 eval_#t~ret0 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret0;havoc eval_#t~ret0; 127045#L406 assume 0 != eval_~tmp~0; 127041#L406-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0;eval_~tmp_ndt_1~0 := eval_#t~nondet1;havoc eval_#t~nondet1; 127037#L414 assume !(0 != eval_~tmp_ndt_1~0); 127032#L411 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0;eval_~tmp_ndt_2~0 := eval_#t~nondet2;havoc eval_#t~nondet2; 127028#L428 assume !(0 != eval_~tmp_ndt_2~0); 127023#L425 assume !(0 == ~t2_st~0); 127017#L439 assume !(0 == ~t3_st~0); 127014#L453 assume !(0 == ~t4_st~0); 127069#L467 [2018-11-23 12:43:42,972 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 12:43:42,972 INFO L82 PathProgramCache]: Analyzing trace with hash -1603966133, now seen corresponding path program 2 times [2018-11-23 12:43:42,972 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 12:43:42,972 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 12:43:42,973 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 12:43:42,973 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 12:43:42,973 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 12:43:42,977 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-23 12:43:42,980 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-23 12:43:42,986 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 12:43:42,986 INFO L82 PathProgramCache]: Analyzing trace with hash 976788691, now seen corresponding path program 2 times [2018-11-23 12:43:42,986 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 12:43:42,986 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 12:43:42,987 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 12:43:42,987 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-23 12:43:42,987 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 12:43:42,988 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-23 12:43:42,989 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-23 12:43:42,991 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 12:43:42,991 INFO L82 PathProgramCache]: Analyzing trace with hash 592796105, now seen corresponding path program 1 times [2018-11-23 12:43:42,991 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 12:43:42,991 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 12:43:42,991 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 12:43:42,992 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-23 12:43:42,992 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 12:43:42,995 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 12:43:43,029 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 12:43:43,029 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 12:43:43,029 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-23 12:43:43,130 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-23 12:43:43,130 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-23 12:43:43,130 INFO L87 Difference]: Start difference. First operand 7504 states and 9787 transitions. cyclomatic complexity: 2307 Second operand 3 states. [2018-11-23 12:43:43,202 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 12:43:43,203 INFO L93 Difference]: Finished difference Result 12567 states and 16293 transitions. [2018-11-23 12:43:43,203 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-23 12:43:43,203 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 12567 states and 16293 transitions. [2018-11-23 12:43:43,238 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 7502 [2018-11-23 12:43:43,270 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 12567 states to 12567 states and 16293 transitions. [2018-11-23 12:43:43,270 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 8610 [2018-11-23 12:43:43,277 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 8610 [2018-11-23 12:43:43,277 INFO L73 IsDeterministic]: Start isDeterministic. Operand 12567 states and 16293 transitions. [2018-11-23 12:43:43,282 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2018-11-23 12:43:43,282 INFO L705 BuchiCegarLoop]: Abstraction has 12567 states and 16293 transitions. [2018-11-23 12:43:43,289 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 12567 states and 16293 transitions. [2018-11-23 12:43:43,373 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 12567 to 12567. [2018-11-23 12:43:43,373 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 12567 states. [2018-11-23 12:43:43,392 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 12567 states to 12567 states and 16293 transitions. [2018-11-23 12:43:43,392 INFO L728 BuchiCegarLoop]: Abstraction has 12567 states and 16293 transitions. [2018-11-23 12:43:43,392 INFO L608 BuchiCegarLoop]: Abstraction has 12567 states and 16293 transitions. [2018-11-23 12:43:43,393 INFO L442 BuchiCegarLoop]: ======== Iteration 23============ [2018-11-23 12:43:43,393 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 12567 states and 16293 transitions. [2018-11-23 12:43:43,418 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 7502 [2018-11-23 12:43:43,418 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-23 12:43:43,418 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-23 12:43:43,419 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 12:43:43,419 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 12:43:43,419 INFO L794 eck$LassoCheckResult]: Stem: 143769#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2; 143440#L-1 havoc main_#res;havoc main_~__retres1~6;havoc main_~__retres1~6;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 143441#L729 havoc start_simulation_#t~ret12, start_simulation_#t~ret13, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 143847#L324 assume 1 == ~m_i~0;~m_st~0 := 0; 143848#L331-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 143712#L336-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 143713#L341-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 143764#L346-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 143444#L351-1 assume !(0 == ~M_E~0); 143445#L492-1 assume !(0 == ~T1_E~0); 143947#L497-1 assume !(0 == ~T2_E~0); 143948#L502-1 assume !(0 == ~T3_E~0); 143999#L507-1 assume !(0 == ~T4_E~0); 143760#L512-1 assume !(0 == ~E_1~0); 143761#L517-1 assume !(0 == ~E_2~0); 143797#L522-1 assume !(0 == ~E_3~0); 143478#L527-1 assume !(0 == ~E_4~0); 143479#L532-1 havoc activate_threads_#t~ret6, activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 143539#L228 assume !(1 == ~m_pc~0); 144156#L228-2 is_master_triggered_~__retres1~0 := 0; 144114#L239 is_master_triggered_#res := is_master_triggered_~__retres1~0; 143555#L240 activate_threads_#t~ret6 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret6;havoc activate_threads_#t~ret6; 143556#L605 assume !(0 != activate_threads_~tmp~1); 143837#L605-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 143842#L247 assume !(1 == ~t1_pc~0); 143868#L247-2 is_transmit1_triggered_~__retres1~1 := 0; 143869#L258 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 143700#L259 activate_threads_#t~ret7 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 143701#L613 assume !(0 != activate_threads_~tmp___0~0); 144173#L613-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 143926#L266 assume !(1 == ~t2_pc~0); 143927#L266-2 is_transmit2_triggered_~__retres1~2 := 0; 143929#L277 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 143930#L278 activate_threads_#t~ret8 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 143417#L621 assume !(0 != activate_threads_~tmp___1~0); 143418#L621-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 143426#L285 assume !(1 == ~t3_pc~0); 143411#L285-2 is_transmit3_triggered_~__retres1~3 := 0; 143412#L296 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 143431#L297 activate_threads_#t~ret9 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 143759#L629 assume !(0 != activate_threads_~tmp___2~0); 143931#L629-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 143932#L304 assume !(1 == ~t4_pc~0); 143960#L304-2 is_transmit4_triggered_~__retres1~4 := 0; 143961#L315 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 143995#L316 activate_threads_#t~ret10 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 143528#L637 assume !(0 != activate_threads_~tmp___3~0); 143529#L637-2 assume !(1 == ~M_E~0); 143530#L545-1 assume !(1 == ~T1_E~0); 143754#L550-1 assume !(1 == ~T2_E~0); 143436#L555-1 assume !(1 == ~T3_E~0); 143437#L560-1 assume !(1 == ~T4_E~0); 143533#L565-1 assume !(1 == ~E_1~0); 143538#L570-1 assume !(1 == ~E_2~0); 144027#L575-1 assume !(1 == ~E_3~0); 144099#L580-1 assume !(1 == ~E_4~0); 144174#L766-1 assume !false; 146205#L767 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret0, eval_#t~nondet1, eval_~tmp_ndt_1~0, eval_#t~nondet2, eval_~tmp_ndt_2~0, eval_#t~nondet3, eval_~tmp_ndt_3~0, eval_#t~nondet4, eval_~tmp_ndt_4~0, eval_#t~nondet5, eval_~tmp_ndt_5~0, eval_~tmp~0;havoc eval_~tmp~0; 150556#L467 [2018-11-23 12:43:43,419 INFO L796 eck$LassoCheckResult]: Loop: 150556#L467 assume !false; 150554#L402 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 150552#L364 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 150549#L391 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 150547#L392 eval_#t~ret0 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret0;havoc eval_#t~ret0; 150545#L406 assume 0 != eval_~tmp~0; 150543#L406-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0;eval_~tmp_ndt_1~0 := eval_#t~nondet1;havoc eval_#t~nondet1; 150540#L414 assume !(0 != eval_~tmp_ndt_1~0); 150539#L411 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0;eval_~tmp_ndt_2~0 := eval_#t~nondet2;havoc eval_#t~nondet2; 150537#L428 assume !(0 != eval_~tmp_ndt_2~0); 150538#L425 assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0;eval_~tmp_ndt_3~0 := eval_#t~nondet3;havoc eval_#t~nondet3; 150573#L442 assume !(0 != eval_~tmp_ndt_3~0); 150571#L439 assume !(0 == ~t3_st~0); 150560#L453 assume !(0 == ~t4_st~0); 150556#L467 [2018-11-23 12:43:43,419 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 12:43:43,419 INFO L82 PathProgramCache]: Analyzing trace with hash -1603966133, now seen corresponding path program 3 times [2018-11-23 12:43:43,419 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 12:43:43,419 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 12:43:43,420 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 12:43:43,420 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 12:43:43,420 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 12:43:43,424 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-23 12:43:43,427 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-23 12:43:43,433 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 12:43:43,433 INFO L82 PathProgramCache]: Analyzing trace with hash 210997043, now seen corresponding path program 1 times [2018-11-23 12:43:43,433 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 12:43:43,433 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 12:43:43,434 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 12:43:43,434 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-23 12:43:43,434 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 12:43:43,435 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-23 12:43:43,437 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-23 12:43:43,438 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 12:43:43,438 INFO L82 PathProgramCache]: Analyzing trace with hash 1192128765, now seen corresponding path program 1 times [2018-11-23 12:43:43,438 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 12:43:43,438 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 12:43:43,439 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 12:43:43,439 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 12:43:43,439 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 12:43:43,443 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 12:43:43,474 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 12:43:43,474 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 12:43:43,474 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-23 12:43:43,533 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-23 12:43:43,533 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-23 12:43:43,534 INFO L87 Difference]: Start difference. First operand 12567 states and 16293 transitions. cyclomatic complexity: 3750 Second operand 3 states. [2018-11-23 12:43:43,572 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 12:43:43,572 INFO L93 Difference]: Finished difference Result 16073 states and 20813 transitions. [2018-11-23 12:43:43,572 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-23 12:43:43,572 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 16073 states and 20813 transitions. [2018-11-23 12:43:43,604 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 9449 [2018-11-23 12:43:43,629 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 16073 states to 16073 states and 20813 transitions. [2018-11-23 12:43:43,629 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 11069 [2018-11-23 12:43:43,635 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 11069 [2018-11-23 12:43:43,635 INFO L73 IsDeterministic]: Start isDeterministic. Operand 16073 states and 20813 transitions. [2018-11-23 12:43:43,639 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2018-11-23 12:43:43,639 INFO L705 BuchiCegarLoop]: Abstraction has 16073 states and 20813 transitions. [2018-11-23 12:43:43,645 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 16073 states and 20813 transitions. [2018-11-23 12:43:43,719 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 16073 to 15533. [2018-11-23 12:43:43,719 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 15533 states. [2018-11-23 12:43:43,738 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 15533 states to 15533 states and 20111 transitions. [2018-11-23 12:43:43,738 INFO L728 BuchiCegarLoop]: Abstraction has 15533 states and 20111 transitions. [2018-11-23 12:43:43,739 INFO L608 BuchiCegarLoop]: Abstraction has 15533 states and 20111 transitions. [2018-11-23 12:43:43,739 INFO L442 BuchiCegarLoop]: ======== Iteration 24============ [2018-11-23 12:43:43,739 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 15533 states and 20111 transitions. [2018-11-23 12:43:43,767 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 9089 [2018-11-23 12:43:43,767 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-23 12:43:43,767 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-23 12:43:43,768 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 12:43:43,768 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 12:43:43,768 INFO L794 eck$LassoCheckResult]: Stem: 172423#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2; 172087#L-1 havoc main_#res;havoc main_~__retres1~6;havoc main_~__retres1~6;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 172088#L729 havoc start_simulation_#t~ret12, start_simulation_#t~ret13, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 172498#L324 assume 1 == ~m_i~0;~m_st~0 := 0; 172499#L331-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 172360#L336-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 172361#L341-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 172418#L346-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 172091#L351-1 assume !(0 == ~M_E~0); 172092#L492-1 assume !(0 == ~T1_E~0); 172601#L497-1 assume !(0 == ~T2_E~0); 172602#L502-1 assume !(0 == ~T3_E~0); 172656#L507-1 assume !(0 == ~T4_E~0); 172415#L512-1 assume !(0 == ~E_1~0); 172416#L517-1 assume !(0 == ~E_2~0); 172450#L522-1 assume !(0 == ~E_3~0); 172127#L527-1 assume !(0 == ~E_4~0); 172128#L532-1 havoc activate_threads_#t~ret6, activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 172186#L228 assume !(1 == ~m_pc~0); 172790#L228-2 is_master_triggered_~__retres1~0 := 0; 172753#L239 is_master_triggered_#res := is_master_triggered_~__retres1~0; 172202#L240 activate_threads_#t~ret6 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret6;havoc activate_threads_#t~ret6; 172203#L605 assume !(0 != activate_threads_~tmp~1); 172489#L605-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 172494#L247 assume !(1 == ~t1_pc~0); 172519#L247-2 is_transmit1_triggered_~__retres1~1 := 0; 172520#L258 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 172348#L259 activate_threads_#t~ret7 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 172349#L613 assume !(0 != activate_threads_~tmp___0~0); 172808#L613-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 172579#L266 assume !(1 == ~t2_pc~0); 172580#L266-2 is_transmit2_triggered_~__retres1~2 := 0; 172582#L277 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 172583#L278 activate_threads_#t~ret8 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 172065#L621 assume !(0 != activate_threads_~tmp___1~0); 172066#L621-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 172073#L285 assume !(1 == ~t3_pc~0); 172059#L285-2 is_transmit3_triggered_~__retres1~3 := 0; 172060#L296 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 172078#L297 activate_threads_#t~ret9 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 172414#L629 assume !(0 != activate_threads_~tmp___2~0); 172584#L629-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 172585#L304 assume !(1 == ~t4_pc~0); 172615#L304-2 is_transmit4_triggered_~__retres1~4 := 0; 172616#L315 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 172652#L316 activate_threads_#t~ret10 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 172175#L637 assume !(0 != activate_threads_~tmp___3~0); 172176#L637-2 assume !(1 == ~M_E~0); 172177#L545-1 assume !(1 == ~T1_E~0); 172409#L550-1 assume !(1 == ~T2_E~0); 172083#L555-1 assume !(1 == ~T3_E~0); 172084#L560-1 assume !(1 == ~T4_E~0); 172180#L565-1 assume !(1 == ~E_1~0); 172185#L570-1 assume !(1 == ~E_2~0); 172672#L575-1 assume !(1 == ~E_3~0); 172737#L580-1 assume !(1 == ~E_4~0); 172809#L766-1 assume !false; 174807#L767 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret0, eval_#t~nondet1, eval_~tmp_ndt_1~0, eval_#t~nondet2, eval_~tmp_ndt_2~0, eval_#t~nondet3, eval_~tmp_ndt_3~0, eval_#t~nondet4, eval_~tmp_ndt_4~0, eval_#t~nondet5, eval_~tmp_ndt_5~0, eval_~tmp~0;havoc eval_~tmp~0; 182042#L467 [2018-11-23 12:43:43,769 INFO L796 eck$LassoCheckResult]: Loop: 182042#L467 assume !false; 182040#L402 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 182035#L364 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 182033#L391 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 182031#L392 eval_#t~ret0 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret0;havoc eval_#t~ret0; 182029#L406 assume 0 != eval_~tmp~0; 182027#L406-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0;eval_~tmp_ndt_1~0 := eval_#t~nondet1;havoc eval_#t~nondet1; 182024#L414 assume !(0 != eval_~tmp_ndt_1~0); 182025#L411 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0;eval_~tmp_ndt_2~0 := eval_#t~nondet2;havoc eval_#t~nondet2; 182126#L428 assume !(0 != eval_~tmp_ndt_2~0); 182051#L425 assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0;eval_~tmp_ndt_3~0 := eval_#t~nondet3;havoc eval_#t~nondet3; 182050#L442 assume !(0 != eval_~tmp_ndt_3~0); 182049#L439 assume 0 == ~t3_st~0;havoc eval_~tmp_ndt_4~0;eval_~tmp_ndt_4~0 := eval_#t~nondet4;havoc eval_#t~nondet4; 182048#L456 assume !(0 != eval_~tmp_ndt_4~0); 182046#L453 assume !(0 == ~t4_st~0); 182042#L467 [2018-11-23 12:43:43,769 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 12:43:43,769 INFO L82 PathProgramCache]: Analyzing trace with hash -1603966133, now seen corresponding path program 4 times [2018-11-23 12:43:43,769 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 12:43:43,769 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 12:43:43,770 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 12:43:43,770 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 12:43:43,770 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 12:43:43,775 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-23 12:43:43,779 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-23 12:43:43,786 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 12:43:43,786 INFO L82 PathProgramCache]: Analyzing trace with hash -2049172699, now seen corresponding path program 1 times [2018-11-23 12:43:43,786 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 12:43:43,787 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 12:43:43,787 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 12:43:43,787 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-23 12:43:43,787 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 12:43:43,789 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-23 12:43:43,791 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-23 12:43:43,792 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 12:43:43,792 INFO L82 PathProgramCache]: Analyzing trace with hash -1698860389, now seen corresponding path program 1 times [2018-11-23 12:43:43,793 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 12:43:43,793 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 12:43:43,793 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 12:43:43,793 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 12:43:43,794 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 12:43:43,798 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 12:43:43,818 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 12:43:43,818 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 12:43:43,818 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2018-11-23 12:43:43,934 WARN L180 SmtUtils]: Spent 115.00 ms on a formula simplification. DAG size of input: 38 DAG size of output: 36 [2018-11-23 12:43:43,952 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-23 12:43:43,952 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-23 12:43:43,952 INFO L87 Difference]: Start difference. First operand 15533 states and 20111 transitions. cyclomatic complexity: 4602 Second operand 3 states. [2018-11-23 12:43:44,014 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 12:43:44,014 INFO L93 Difference]: Finished difference Result 29681 states and 38186 transitions. [2018-11-23 12:43:44,014 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-23 12:43:44,014 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 29681 states and 38186 transitions. [2018-11-23 12:43:44,078 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 17296 [2018-11-23 12:43:44,125 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 29681 states to 29681 states and 38186 transitions. [2018-11-23 12:43:44,125 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 20476 [2018-11-23 12:43:44,134 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 20476 [2018-11-23 12:43:44,134 INFO L73 IsDeterministic]: Start isDeterministic. Operand 29681 states and 38186 transitions. [2018-11-23 12:43:44,137 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2018-11-23 12:43:44,138 INFO L705 BuchiCegarLoop]: Abstraction has 29681 states and 38186 transitions. [2018-11-23 12:43:44,149 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 29681 states and 38186 transitions. [2018-11-23 12:43:44,286 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 29681 to 29681. [2018-11-23 12:43:44,286 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 29681 states. [2018-11-23 12:43:44,314 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 29681 states to 29681 states and 38186 transitions. [2018-11-23 12:43:44,314 INFO L728 BuchiCegarLoop]: Abstraction has 29681 states and 38186 transitions. [2018-11-23 12:43:44,314 INFO L608 BuchiCegarLoop]: Abstraction has 29681 states and 38186 transitions. [2018-11-23 12:43:44,315 INFO L442 BuchiCegarLoop]: ======== Iteration 25============ [2018-11-23 12:43:44,315 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 29681 states and 38186 transitions. [2018-11-23 12:43:44,365 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 17296 [2018-11-23 12:43:44,365 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-23 12:43:44,365 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-23 12:43:44,366 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 12:43:44,366 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 12:43:44,366 INFO L794 eck$LassoCheckResult]: Stem: 217656#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2; 217311#L-1 havoc main_#res;havoc main_~__retres1~6;havoc main_~__retres1~6;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 217312#L729 havoc start_simulation_#t~ret12, start_simulation_#t~ret13, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 217738#L324 assume 1 == ~m_i~0;~m_st~0 := 0; 217739#L331-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 217587#L336-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 217588#L341-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 217651#L346-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 217316#L351-1 assume !(0 == ~M_E~0); 217317#L492-1 assume !(0 == ~T1_E~0); 217854#L497-1 assume !(0 == ~T2_E~0); 217855#L502-1 assume !(0 == ~T3_E~0); 217911#L507-1 assume !(0 == ~T4_E~0); 217647#L512-1 assume !(0 == ~E_1~0); 217648#L517-1 assume !(0 == ~E_2~0); 217683#L522-1 assume !(0 == ~E_3~0); 217354#L527-1 assume !(0 == ~E_4~0); 217355#L532-1 havoc activate_threads_#t~ret6, activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 217419#L228 assume !(1 == ~m_pc~0); 218060#L228-2 is_master_triggered_~__retres1~0 := 0; 218021#L239 is_master_triggered_#res := is_master_triggered_~__retres1~0; 217435#L240 activate_threads_#t~ret6 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret6;havoc activate_threads_#t~ret6; 217436#L605 assume !(0 != activate_threads_~tmp~1); 217725#L605-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 217733#L247 assume !(1 == ~t1_pc~0); 217764#L247-2 is_transmit1_triggered_~__retres1~1 := 0; 217765#L258 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 217577#L259 activate_threads_#t~ret7 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 217578#L613 assume !(0 != activate_threads_~tmp___0~0); 218077#L613-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 217832#L266 assume !(1 == ~t2_pc~0); 217833#L266-2 is_transmit2_triggered_~__retres1~2 := 0; 217835#L277 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 217836#L278 activate_threads_#t~ret8 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 217288#L621 assume !(0 != activate_threads_~tmp___1~0); 217289#L621-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 217297#L285 assume !(1 == ~t3_pc~0); 217282#L285-2 is_transmit3_triggered_~__retres1~3 := 0; 217283#L296 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 217302#L297 activate_threads_#t~ret9 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 217646#L629 assume !(0 != activate_threads_~tmp___2~0); 217837#L629-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 217838#L304 assume !(1 == ~t4_pc~0); 217870#L304-2 is_transmit4_triggered_~__retres1~4 := 0; 217871#L315 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 217907#L316 activate_threads_#t~ret10 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 217406#L637 assume !(0 != activate_threads_~tmp___3~0); 217407#L637-2 assume !(1 == ~M_E~0); 217408#L545-1 assume !(1 == ~T1_E~0); 217641#L550-1 assume !(1 == ~T2_E~0); 217307#L555-1 assume !(1 == ~T3_E~0); 217308#L560-1 assume !(1 == ~T4_E~0); 217413#L565-1 assume !(1 == ~E_1~0); 217418#L570-1 assume !(1 == ~E_2~0); 217938#L575-1 assume !(1 == ~E_3~0); 218006#L580-1 assume !(1 == ~E_4~0); 218078#L766-1 assume !false; 220907#L767 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret0, eval_#t~nondet1, eval_~tmp_ndt_1~0, eval_#t~nondet2, eval_~tmp_ndt_2~0, eval_#t~nondet3, eval_~tmp_ndt_3~0, eval_#t~nondet4, eval_~tmp_ndt_4~0, eval_#t~nondet5, eval_~tmp_ndt_5~0, eval_~tmp~0;havoc eval_~tmp~0; 234252#L467 [2018-11-23 12:43:44,366 INFO L796 eck$LassoCheckResult]: Loop: 234252#L467 assume !false; 234250#L402 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 234246#L364 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 234244#L391 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 234242#L392 eval_#t~ret0 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret0;havoc eval_#t~ret0; 234240#L406 assume 0 != eval_~tmp~0; 234238#L406-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0;eval_~tmp_ndt_1~0 := eval_#t~nondet1;havoc eval_#t~nondet1; 234235#L414 assume !(0 != eval_~tmp_ndt_1~0); 234233#L411 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0;eval_~tmp_ndt_2~0 := eval_#t~nondet2;havoc eval_#t~nondet2; 234230#L428 assume !(0 != eval_~tmp_ndt_2~0); 234231#L425 assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0;eval_~tmp_ndt_3~0 := eval_#t~nondet3;havoc eval_#t~nondet3; 236396#L442 assume !(0 != eval_~tmp_ndt_3~0); 236397#L439 assume 0 == ~t3_st~0;havoc eval_~tmp_ndt_4~0;eval_~tmp_ndt_4~0 := eval_#t~nondet4;havoc eval_#t~nondet4; 240216#L456 assume !(0 != eval_~tmp_ndt_4~0); 234257#L453 assume 0 == ~t4_st~0;havoc eval_~tmp_ndt_5~0;eval_~tmp_ndt_5~0 := eval_#t~nondet5;havoc eval_#t~nondet5; 234254#L470 assume !(0 != eval_~tmp_ndt_5~0); 234252#L467 [2018-11-23 12:43:44,366 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 12:43:44,367 INFO L82 PathProgramCache]: Analyzing trace with hash -1603966133, now seen corresponding path program 5 times [2018-11-23 12:43:44,367 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 12:43:44,367 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 12:43:44,367 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 12:43:44,368 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 12:43:44,368 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 12:43:44,371 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-23 12:43:44,375 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-23 12:43:44,382 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 12:43:44,382 INFO L82 PathProgramCache]: Analyzing trace with hash 900155617, now seen corresponding path program 1 times [2018-11-23 12:43:44,382 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 12:43:44,382 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 12:43:44,382 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 12:43:44,382 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-23 12:43:44,383 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 12:43:44,384 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-23 12:43:44,386 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-23 12:43:44,387 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 12:43:44,387 INFO L82 PathProgramCache]: Analyzing trace with hash -1125064661, now seen corresponding path program 1 times [2018-11-23 12:43:44,387 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 12:43:44,387 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 12:43:44,388 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 12:43:44,388 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 12:43:44,388 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 12:43:44,392 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-23 12:43:44,397 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-23 12:43:44,729 WARN L180 SmtUtils]: Spent 233.00 ms on a formula simplification. DAG size of input: 157 DAG size of output: 106 ----- class de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder.RCFGBacktranslator [?] ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2; [?] havoc main_#res;havoc main_~__retres1~6;havoc main_~__retres1~6;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; [?] havoc start_simulation_#t~ret12, start_simulation_#t~ret13, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; [?] assume 1 == ~m_i~0;~m_st~0 := 0; [?] assume 1 == ~t1_i~0;~t1_st~0 := 0; [?] assume 1 == ~t2_i~0;~t2_st~0 := 0; [?] assume 1 == ~t3_i~0;~t3_st~0 := 0; [?] assume 1 == ~t4_i~0;~t4_st~0 := 0; [?] assume !(0 == ~M_E~0); [?] assume !(0 == ~T1_E~0); [?] assume !(0 == ~T2_E~0); [?] assume !(0 == ~T3_E~0); [?] assume !(0 == ~T4_E~0); [?] assume !(0 == ~E_1~0); [?] assume !(0 == ~E_2~0); [?] assume !(0 == ~E_3~0); [?] assume !(0 == ~E_4~0); [?] havoc activate_threads_#t~ret6, activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; [?] assume !(1 == ~m_pc~0); [?] is_master_triggered_~__retres1~0 := 0; [?] is_master_triggered_#res := is_master_triggered_~__retres1~0; [?] activate_threads_#t~ret6 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret6;havoc activate_threads_#t~ret6; [?] assume !(0 != activate_threads_~tmp~1); [?] havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; [?] assume !(1 == ~t1_pc~0); [?] is_transmit1_triggered_~__retres1~1 := 0; [?] is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; [?] activate_threads_#t~ret7 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; [?] assume !(0 != activate_threads_~tmp___0~0); [?] havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; [?] assume !(1 == ~t2_pc~0); [?] is_transmit2_triggered_~__retres1~2 := 0; [?] is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; [?] activate_threads_#t~ret8 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; [?] assume !(0 != activate_threads_~tmp___1~0); [?] havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; [?] assume !(1 == ~t3_pc~0); [?] is_transmit3_triggered_~__retres1~3 := 0; [?] is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; [?] activate_threads_#t~ret9 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; [?] assume !(0 != activate_threads_~tmp___2~0); [?] havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; [?] assume !(1 == ~t4_pc~0); [?] is_transmit4_triggered_~__retres1~4 := 0; [?] is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; [?] activate_threads_#t~ret10 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; [?] assume !(0 != activate_threads_~tmp___3~0); [?] assume !(1 == ~M_E~0); [?] assume !(1 == ~T1_E~0); [?] assume !(1 == ~T2_E~0); [?] assume !(1 == ~T3_E~0); [?] assume !(1 == ~T4_E~0); [?] assume !(1 == ~E_1~0); [?] assume !(1 == ~E_2~0); [?] assume !(1 == ~E_3~0); [?] assume !(1 == ~E_4~0); [?] assume !false; [?] start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret0, eval_#t~nondet1, eval_~tmp_ndt_1~0, eval_#t~nondet2, eval_~tmp_ndt_2~0, eval_#t~nondet3, eval_~tmp_ndt_3~0, eval_#t~nondet4, eval_~tmp_ndt_4~0, eval_#t~nondet5, eval_~tmp_ndt_5~0, eval_~tmp~0;havoc eval_~tmp~0; [L15] ~m_pc~0 := 0; [L16] ~t1_pc~0 := 0; [L17] ~t2_pc~0 := 0; [L18] ~t3_pc~0 := 0; [L19] ~t4_pc~0 := 0; [L20] ~m_st~0 := 0; [L21] ~t1_st~0 := 0; [L22] ~t2_st~0 := 0; [L23] ~t3_st~0 := 0; [L24] ~t4_st~0 := 0; [L25] ~m_i~0 := 0; [L26] ~t1_i~0 := 0; [L27] ~t2_i~0 := 0; [L28] ~t3_i~0 := 0; [L29] ~t4_i~0 := 0; [L30] ~M_E~0 := 2; [L31] ~T1_E~0 := 2; [L32] ~T2_E~0 := 2; [L33] ~T3_E~0 := 2; [L34] ~T4_E~0 := 2; [L35] ~E_1~0 := 2; [L36] ~E_2~0 := 2; [L37] ~E_3~0 := 2; [L38] ~E_4~0 := 2; [?] havoc main_#res; [?] havoc main_~__retres1~6; [L811] havoc main_~__retres1~6; [L723] ~m_i~0 := 1; [L724] ~t1_i~0 := 1; [L725] ~t2_i~0 := 1; [L726] ~t3_i~0 := 1; [L727] ~t4_i~0 := 1; [L816] havoc start_simulation_#t~ret12, start_simulation_#t~ret13, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1; [L752] havoc start_simulation_~kernel_st~0; [L753] havoc start_simulation_~tmp~3; [L754] havoc start_simulation_~tmp___0~1; [L758] start_simulation_~kernel_st~0 := 0; [L331-L335] assume 1 == ~m_i~0; [L332] ~m_st~0 := 0; [L336-L340] assume 1 == ~t1_i~0; [L337] ~t1_st~0 := 0; [L341-L345] assume 1 == ~t2_i~0; [L342] ~t2_st~0 := 0; [L346-L350] assume 1 == ~t3_i~0; [L347] ~t3_st~0 := 0; [L351-L355] assume 1 == ~t4_i~0; [L352] ~t4_st~0 := 0; [L492-L496] assume !(0 == ~M_E~0); [L497-L501] assume !(0 == ~T1_E~0); [L502-L506] assume !(0 == ~T2_E~0); [L507-L511] assume !(0 == ~T3_E~0); [L512-L516] assume !(0 == ~T4_E~0); [L517-L521] assume !(0 == ~E_1~0); [L522-L526] assume !(0 == ~E_2~0); [L527-L531] assume !(0 == ~E_3~0); [L532-L536] assume !(0 == ~E_4~0); [L762] havoc activate_threads_#t~ret6, activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0; [L595] havoc activate_threads_~tmp~1; [L596] havoc activate_threads_~tmp___0~0; [L597] havoc activate_threads_~tmp___1~0; [L598] havoc activate_threads_~tmp___2~0; [L599] havoc activate_threads_~tmp___3~0; [L603] havoc is_master_triggered_#res; [L603] havoc is_master_triggered_~__retres1~0; [L225] havoc is_master_triggered_~__retres1~0; [L228-L237] assume !(1 == ~m_pc~0); [L238] is_master_triggered_~__retres1~0 := 0; [L240] is_master_triggered_#res := is_master_triggered_~__retres1~0; [L603] activate_threads_#t~ret6 := is_master_triggered_#res; [L603] activate_threads_~tmp~1 := activate_threads_#t~ret6; [L603] havoc activate_threads_#t~ret6; [L605-L609] assume !(0 != activate_threads_~tmp~1); [L611] havoc is_transmit1_triggered_#res; [L611] havoc is_transmit1_triggered_~__retres1~1; [L244] havoc is_transmit1_triggered_~__retres1~1; [L247-L256] assume !(1 == ~t1_pc~0); [L257] is_transmit1_triggered_~__retres1~1 := 0; [L259] is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; [L611] activate_threads_#t~ret7 := is_transmit1_triggered_#res; [L611] activate_threads_~tmp___0~0 := activate_threads_#t~ret7; [L611] havoc activate_threads_#t~ret7; [L613-L617] assume !(0 != activate_threads_~tmp___0~0); [L619] havoc is_transmit2_triggered_#res; [L619] havoc is_transmit2_triggered_~__retres1~2; [L263] havoc is_transmit2_triggered_~__retres1~2; [L266-L275] assume !(1 == ~t2_pc~0); [L276] is_transmit2_triggered_~__retres1~2 := 0; [L278] is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; [L619] activate_threads_#t~ret8 := is_transmit2_triggered_#res; [L619] activate_threads_~tmp___1~0 := activate_threads_#t~ret8; [L619] havoc activate_threads_#t~ret8; [L621-L625] assume !(0 != activate_threads_~tmp___1~0); [L627] havoc is_transmit3_triggered_#res; [L627] havoc is_transmit3_triggered_~__retres1~3; [L282] havoc is_transmit3_triggered_~__retres1~3; [L285-L294] assume !(1 == ~t3_pc~0); [L295] is_transmit3_triggered_~__retres1~3 := 0; [L297] is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; [L627] activate_threads_#t~ret9 := is_transmit3_triggered_#res; [L627] activate_threads_~tmp___2~0 := activate_threads_#t~ret9; [L627] havoc activate_threads_#t~ret9; [L629-L633] assume !(0 != activate_threads_~tmp___2~0); [L635] havoc is_transmit4_triggered_#res; [L635] havoc is_transmit4_triggered_~__retres1~4; [L301] havoc is_transmit4_triggered_~__retres1~4; [L304-L313] assume !(1 == ~t4_pc~0); [L314] is_transmit4_triggered_~__retres1~4 := 0; [L316] is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; [L635] activate_threads_#t~ret10 := is_transmit4_triggered_#res; [L635] activate_threads_~tmp___3~0 := activate_threads_#t~ret10; [L635] havoc activate_threads_#t~ret10; [L637-L641] assume !(0 != activate_threads_~tmp___3~0); [L545-L549] assume !(1 == ~M_E~0); [L550-L554] assume !(1 == ~T1_E~0); [L555-L559] assume !(1 == ~T2_E~0); [L560-L564] assume !(1 == ~T3_E~0); [L565-L569] assume !(1 == ~T4_E~0); [L570-L574] assume !(1 == ~E_1~0); [L575-L579] assume !(1 == ~E_2~0); [L580-L584] assume !(1 == ~E_3~0); [L585-L589] assume !(1 == ~E_4~0); [L766-L803] assume !false; [L769] start_simulation_~kernel_st~0 := 1; [L770] havoc eval_#t~ret0, eval_#t~nondet1, eval_~tmp_ndt_1~0, eval_#t~nondet2, eval_~tmp_ndt_2~0, eval_#t~nondet3, eval_~tmp_ndt_3~0, eval_#t~nondet4, eval_~tmp_ndt_4~0, eval_#t~nondet5, eval_~tmp_ndt_5~0, eval_~tmp~0; [L397] havoc eval_~tmp~0; ----- ----- class de.uni_freiburg.informatik.ultimate.boogie.preprocessor.BoogiePreprocessorBacktranslator [L15] ~m_pc~0 := 0; [L16] ~t1_pc~0 := 0; [L17] ~t2_pc~0 := 0; [L18] ~t3_pc~0 := 0; [L19] ~t4_pc~0 := 0; [L20] ~m_st~0 := 0; [L21] ~t1_st~0 := 0; [L22] ~t2_st~0 := 0; [L23] ~t3_st~0 := 0; [L24] ~t4_st~0 := 0; [L25] ~m_i~0 := 0; [L26] ~t1_i~0 := 0; [L27] ~t2_i~0 := 0; [L28] ~t3_i~0 := 0; [L29] ~t4_i~0 := 0; [L30] ~M_E~0 := 2; [L31] ~T1_E~0 := 2; [L32] ~T2_E~0 := 2; [L33] ~T3_E~0 := 2; [L34] ~T4_E~0 := 2; [L35] ~E_1~0 := 2; [L36] ~E_2~0 := 2; [L37] ~E_3~0 := 2; [L38] ~E_4~0 := 2; [?] havoc main_#res; [?] havoc main_~__retres1~6; [L811] havoc main_~__retres1~6; [L723] ~m_i~0 := 1; [L724] ~t1_i~0 := 1; [L725] ~t2_i~0 := 1; [L726] ~t3_i~0 := 1; [L727] ~t4_i~0 := 1; [L816] havoc start_simulation_#t~ret12, start_simulation_#t~ret13, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1; [L752] havoc start_simulation_~kernel_st~0; [L753] havoc start_simulation_~tmp~3; [L754] havoc start_simulation_~tmp___0~1; [L758] start_simulation_~kernel_st~0 := 0; [L331-L335] assume 1 == ~m_i~0; [L332] ~m_st~0 := 0; [L336-L340] assume 1 == ~t1_i~0; [L337] ~t1_st~0 := 0; [L341-L345] assume 1 == ~t2_i~0; [L342] ~t2_st~0 := 0; [L346-L350] assume 1 == ~t3_i~0; [L347] ~t3_st~0 := 0; [L351-L355] assume 1 == ~t4_i~0; [L352] ~t4_st~0 := 0; [L492-L496] assume !(0 == ~M_E~0); [L497-L501] assume !(0 == ~T1_E~0); [L502-L506] assume !(0 == ~T2_E~0); [L507-L511] assume !(0 == ~T3_E~0); [L512-L516] assume !(0 == ~T4_E~0); [L517-L521] assume !(0 == ~E_1~0); [L522-L526] assume !(0 == ~E_2~0); [L527-L531] assume !(0 == ~E_3~0); [L532-L536] assume !(0 == ~E_4~0); [L762] havoc activate_threads_#t~ret6, activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0; [L595] havoc activate_threads_~tmp~1; [L596] havoc activate_threads_~tmp___0~0; [L597] havoc activate_threads_~tmp___1~0; [L598] havoc activate_threads_~tmp___2~0; [L599] havoc activate_threads_~tmp___3~0; [L603] havoc is_master_triggered_#res; [L603] havoc is_master_triggered_~__retres1~0; [L225] havoc is_master_triggered_~__retres1~0; [L228-L237] assume !(1 == ~m_pc~0); [L238] is_master_triggered_~__retres1~0 := 0; [L240] is_master_triggered_#res := is_master_triggered_~__retres1~0; [L603] activate_threads_#t~ret6 := is_master_triggered_#res; [L603] activate_threads_~tmp~1 := activate_threads_#t~ret6; [L603] havoc activate_threads_#t~ret6; [L605-L609] assume !(0 != activate_threads_~tmp~1); [L611] havoc is_transmit1_triggered_#res; [L611] havoc is_transmit1_triggered_~__retres1~1; [L244] havoc is_transmit1_triggered_~__retres1~1; [L247-L256] assume !(1 == ~t1_pc~0); [L257] is_transmit1_triggered_~__retres1~1 := 0; [L259] is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; [L611] activate_threads_#t~ret7 := is_transmit1_triggered_#res; [L611] activate_threads_~tmp___0~0 := activate_threads_#t~ret7; [L611] havoc activate_threads_#t~ret7; [L613-L617] assume !(0 != activate_threads_~tmp___0~0); [L619] havoc is_transmit2_triggered_#res; [L619] havoc is_transmit2_triggered_~__retres1~2; [L263] havoc is_transmit2_triggered_~__retres1~2; [L266-L275] assume !(1 == ~t2_pc~0); [L276] is_transmit2_triggered_~__retres1~2 := 0; [L278] is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; [L619] activate_threads_#t~ret8 := is_transmit2_triggered_#res; [L619] activate_threads_~tmp___1~0 := activate_threads_#t~ret8; [L619] havoc activate_threads_#t~ret8; [L621-L625] assume !(0 != activate_threads_~tmp___1~0); [L627] havoc is_transmit3_triggered_#res; [L627] havoc is_transmit3_triggered_~__retres1~3; [L282] havoc is_transmit3_triggered_~__retres1~3; [L285-L294] assume !(1 == ~t3_pc~0); [L295] is_transmit3_triggered_~__retres1~3 := 0; [L297] is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; [L627] activate_threads_#t~ret9 := is_transmit3_triggered_#res; [L627] activate_threads_~tmp___2~0 := activate_threads_#t~ret9; [L627] havoc activate_threads_#t~ret9; [L629-L633] assume !(0 != activate_threads_~tmp___2~0); [L635] havoc is_transmit4_triggered_#res; [L635] havoc is_transmit4_triggered_~__retres1~4; [L301] havoc is_transmit4_triggered_~__retres1~4; [L304-L313] assume !(1 == ~t4_pc~0); [L314] is_transmit4_triggered_~__retres1~4 := 0; [L316] is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; [L635] activate_threads_#t~ret10 := is_transmit4_triggered_#res; [L635] activate_threads_~tmp___3~0 := activate_threads_#t~ret10; [L635] havoc activate_threads_#t~ret10; [L637-L641] assume !(0 != activate_threads_~tmp___3~0); [L545-L549] assume !(1 == ~M_E~0); [L550-L554] assume !(1 == ~T1_E~0); [L555-L559] assume !(1 == ~T2_E~0); [L560-L564] assume !(1 == ~T3_E~0); [L565-L569] assume !(1 == ~T4_E~0); [L570-L574] assume !(1 == ~E_1~0); [L575-L579] assume !(1 == ~E_2~0); [L580-L584] assume !(1 == ~E_3~0); [L585-L589] assume !(1 == ~E_4~0); [L766-L803] assume !false; [L769] start_simulation_~kernel_st~0 := 1; [L770] havoc eval_#t~ret0, eval_#t~nondet1, eval_~tmp_ndt_1~0, eval_#t~nondet2, eval_~tmp_ndt_2~0, eval_#t~nondet3, eval_~tmp_ndt_3~0, eval_#t~nondet4, eval_~tmp_ndt_4~0, eval_#t~nondet5, eval_~tmp_ndt_5~0, eval_~tmp~0; [L397] havoc eval_~tmp~0; [L15] ~m_pc~0 := 0; [L16] ~t1_pc~0 := 0; [L17] ~t2_pc~0 := 0; [L18] ~t3_pc~0 := 0; [L19] ~t4_pc~0 := 0; [L20] ~m_st~0 := 0; [L21] ~t1_st~0 := 0; [L22] ~t2_st~0 := 0; [L23] ~t3_st~0 := 0; [L24] ~t4_st~0 := 0; [L25] ~m_i~0 := 0; [L26] ~t1_i~0 := 0; [L27] ~t2_i~0 := 0; [L28] ~t3_i~0 := 0; [L29] ~t4_i~0 := 0; [L30] ~M_E~0 := 2; [L31] ~T1_E~0 := 2; [L32] ~T2_E~0 := 2; [L33] ~T3_E~0 := 2; [L34] ~T4_E~0 := 2; [L35] ~E_1~0 := 2; [L36] ~E_2~0 := 2; [L37] ~E_3~0 := 2; [L38] ~E_4~0 := 2; [?] havoc main_#res; [?] havoc main_~__retres1~6; [L811] havoc main_~__retres1~6; [L723] ~m_i~0 := 1; [L724] ~t1_i~0 := 1; [L725] ~t2_i~0 := 1; [L726] ~t3_i~0 := 1; [L727] ~t4_i~0 := 1; [L816] havoc start_simulation_#t~ret12, start_simulation_#t~ret13, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1; [L752] havoc start_simulation_~kernel_st~0; [L753] havoc start_simulation_~tmp~3; [L754] havoc start_simulation_~tmp___0~1; [L758] start_simulation_~kernel_st~0 := 0; [L331] COND TRUE 1 == ~m_i~0 [L332] ~m_st~0 := 0; [L336] COND TRUE 1 == ~t1_i~0 [L337] ~t1_st~0 := 0; [L341] COND TRUE 1 == ~t2_i~0 [L342] ~t2_st~0 := 0; [L346] COND TRUE 1 == ~t3_i~0 [L347] ~t3_st~0 := 0; [L351] COND TRUE 1 == ~t4_i~0 [L352] ~t4_st~0 := 0; [L492] COND FALSE !(0 == ~M_E~0) [L497] COND FALSE !(0 == ~T1_E~0) [L502] COND FALSE !(0 == ~T2_E~0) [L507] COND FALSE !(0 == ~T3_E~0) [L512] COND FALSE !(0 == ~T4_E~0) [L517] COND FALSE !(0 == ~E_1~0) [L522] COND FALSE !(0 == ~E_2~0) [L527] COND FALSE !(0 == ~E_3~0) [L532] COND FALSE !(0 == ~E_4~0) [L762] havoc activate_threads_#t~ret6, activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0; [L595] havoc activate_threads_~tmp~1; [L596] havoc activate_threads_~tmp___0~0; [L597] havoc activate_threads_~tmp___1~0; [L598] havoc activate_threads_~tmp___2~0; [L599] havoc activate_threads_~tmp___3~0; [L603] havoc is_master_triggered_#res; [L603] havoc is_master_triggered_~__retres1~0; [L225] havoc is_master_triggered_~__retres1~0; [L228] COND FALSE !(1 == ~m_pc~0) [L238] is_master_triggered_~__retres1~0 := 0; [L240] is_master_triggered_#res := is_master_triggered_~__retres1~0; [L603] activate_threads_#t~ret6 := is_master_triggered_#res; [L603] activate_threads_~tmp~1 := activate_threads_#t~ret6; [L603] havoc activate_threads_#t~ret6; [L605-L609] COND FALSE !(0 != activate_threads_~tmp~1) [L611] havoc is_transmit1_triggered_#res; [L611] havoc is_transmit1_triggered_~__retres1~1; [L244] havoc is_transmit1_triggered_~__retres1~1; [L247] COND FALSE !(1 == ~t1_pc~0) [L257] is_transmit1_triggered_~__retres1~1 := 0; [L259] is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; [L611] activate_threads_#t~ret7 := is_transmit1_triggered_#res; [L611] activate_threads_~tmp___0~0 := activate_threads_#t~ret7; [L611] havoc activate_threads_#t~ret7; [L613-L617] COND FALSE !(0 != activate_threads_~tmp___0~0) [L619] havoc is_transmit2_triggered_#res; [L619] havoc is_transmit2_triggered_~__retres1~2; [L263] havoc is_transmit2_triggered_~__retres1~2; [L266] COND FALSE !(1 == ~t2_pc~0) [L276] is_transmit2_triggered_~__retres1~2 := 0; [L278] is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; [L619] activate_threads_#t~ret8 := is_transmit2_triggered_#res; [L619] activate_threads_~tmp___1~0 := activate_threads_#t~ret8; [L619] havoc activate_threads_#t~ret8; [L621-L625] COND FALSE !(0 != activate_threads_~tmp___1~0) [L627] havoc is_transmit3_triggered_#res; [L627] havoc is_transmit3_triggered_~__retres1~3; [L282] havoc is_transmit3_triggered_~__retres1~3; [L285] COND FALSE !(1 == ~t3_pc~0) [L295] is_transmit3_triggered_~__retres1~3 := 0; [L297] is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; [L627] activate_threads_#t~ret9 := is_transmit3_triggered_#res; [L627] activate_threads_~tmp___2~0 := activate_threads_#t~ret9; [L627] havoc activate_threads_#t~ret9; [L629-L633] COND FALSE !(0 != activate_threads_~tmp___2~0) [L635] havoc is_transmit4_triggered_#res; [L635] havoc is_transmit4_triggered_~__retres1~4; [L301] havoc is_transmit4_triggered_~__retres1~4; [L304] COND FALSE !(1 == ~t4_pc~0) [L314] is_transmit4_triggered_~__retres1~4 := 0; [L316] is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; [L635] activate_threads_#t~ret10 := is_transmit4_triggered_#res; [L635] activate_threads_~tmp___3~0 := activate_threads_#t~ret10; [L635] havoc activate_threads_#t~ret10; [L637-L641] COND FALSE !(0 != activate_threads_~tmp___3~0) [L545] COND FALSE !(1 == ~M_E~0) [L550] COND FALSE !(1 == ~T1_E~0) [L555] COND FALSE !(1 == ~T2_E~0) [L560] COND FALSE !(1 == ~T3_E~0) [L565] COND FALSE !(1 == ~T4_E~0) [L570] COND FALSE !(1 == ~E_1~0) [L575] COND FALSE !(1 == ~E_2~0) [L580] COND FALSE !(1 == ~E_3~0) [L585] COND FALSE !(1 == ~E_4~0) [L766-L803] COND FALSE !(false) [L769] start_simulation_~kernel_st~0 := 1; [L770] havoc eval_#t~ret0, eval_#t~nondet1, eval_~tmp_ndt_1~0, eval_#t~nondet2, eval_~tmp_ndt_2~0, eval_#t~nondet3, eval_~tmp_ndt_3~0, eval_#t~nondet4, eval_~tmp_ndt_4~0, eval_#t~nondet5, eval_~tmp_ndt_5~0, eval_~tmp~0; [L397] havoc eval_~tmp~0; ----- ----- class de.uni_freiburg.informatik.ultimate.boogie.procedureinliner.backtranslation.InlinerBacktranslator [L15] ~m_pc~0 := 0; [L16] ~t1_pc~0 := 0; [L17] ~t2_pc~0 := 0; [L18] ~t3_pc~0 := 0; [L19] ~t4_pc~0 := 0; [L20] ~m_st~0 := 0; [L21] ~t1_st~0 := 0; [L22] ~t2_st~0 := 0; [L23] ~t3_st~0 := 0; [L24] ~t4_st~0 := 0; [L25] ~m_i~0 := 0; [L26] ~t1_i~0 := 0; [L27] ~t2_i~0 := 0; [L28] ~t3_i~0 := 0; [L29] ~t4_i~0 := 0; [L30] ~M_E~0 := 2; [L31] ~T1_E~0 := 2; [L32] ~T2_E~0 := 2; [L33] ~T3_E~0 := 2; [L34] ~T4_E~0 := 2; [L35] ~E_1~0 := 2; [L36] ~E_2~0 := 2; [L37] ~E_3~0 := 2; [L38] ~E_4~0 := 2; [?] havoc main_#res; [?] havoc main_~__retres1~6; [L811] havoc main_~__retres1~6; [L723] ~m_i~0 := 1; [L724] ~t1_i~0 := 1; [L725] ~t2_i~0 := 1; [L726] ~t3_i~0 := 1; [L727] ~t4_i~0 := 1; [L816] havoc start_simulation_#t~ret12, start_simulation_#t~ret13, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1; [L752] havoc start_simulation_~kernel_st~0; [L753] havoc start_simulation_~tmp~3; [L754] havoc start_simulation_~tmp___0~1; [L758] start_simulation_~kernel_st~0 := 0; [L331] COND TRUE 1 == ~m_i~0 [L332] ~m_st~0 := 0; [L336] COND TRUE 1 == ~t1_i~0 [L337] ~t1_st~0 := 0; [L341] COND TRUE 1 == ~t2_i~0 [L342] ~t2_st~0 := 0; [L346] COND TRUE 1 == ~t3_i~0 [L347] ~t3_st~0 := 0; [L351] COND TRUE 1 == ~t4_i~0 [L352] ~t4_st~0 := 0; [L492] COND FALSE !(0 == ~M_E~0) [L497] COND FALSE !(0 == ~T1_E~0) [L502] COND FALSE !(0 == ~T2_E~0) [L507] COND FALSE !(0 == ~T3_E~0) [L512] COND FALSE !(0 == ~T4_E~0) [L517] COND FALSE !(0 == ~E_1~0) [L522] COND FALSE !(0 == ~E_2~0) [L527] COND FALSE !(0 == ~E_3~0) [L532] COND FALSE !(0 == ~E_4~0) [L762] havoc activate_threads_#t~ret6, activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0; [L595] havoc activate_threads_~tmp~1; [L596] havoc activate_threads_~tmp___0~0; [L597] havoc activate_threads_~tmp___1~0; [L598] havoc activate_threads_~tmp___2~0; [L599] havoc activate_threads_~tmp___3~0; [L603] havoc is_master_triggered_#res; [L603] havoc is_master_triggered_~__retres1~0; [L225] havoc is_master_triggered_~__retres1~0; [L228] COND FALSE !(1 == ~m_pc~0) [L238] is_master_triggered_~__retres1~0 := 0; [L240] is_master_triggered_#res := is_master_triggered_~__retres1~0; [L603] activate_threads_#t~ret6 := is_master_triggered_#res; [L603] activate_threads_~tmp~1 := activate_threads_#t~ret6; [L603] havoc activate_threads_#t~ret6; [L605-L609] COND FALSE !(0 != activate_threads_~tmp~1) [L611] havoc is_transmit1_triggered_#res; [L611] havoc is_transmit1_triggered_~__retres1~1; [L244] havoc is_transmit1_triggered_~__retres1~1; [L247] COND FALSE !(1 == ~t1_pc~0) [L257] is_transmit1_triggered_~__retres1~1 := 0; [L259] is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; [L611] activate_threads_#t~ret7 := is_transmit1_triggered_#res; [L611] activate_threads_~tmp___0~0 := activate_threads_#t~ret7; [L611] havoc activate_threads_#t~ret7; [L613-L617] COND FALSE !(0 != activate_threads_~tmp___0~0) [L619] havoc is_transmit2_triggered_#res; [L619] havoc is_transmit2_triggered_~__retres1~2; [L263] havoc is_transmit2_triggered_~__retres1~2; [L266] COND FALSE !(1 == ~t2_pc~0) [L276] is_transmit2_triggered_~__retres1~2 := 0; [L278] is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; [L619] activate_threads_#t~ret8 := is_transmit2_triggered_#res; [L619] activate_threads_~tmp___1~0 := activate_threads_#t~ret8; [L619] havoc activate_threads_#t~ret8; [L621-L625] COND FALSE !(0 != activate_threads_~tmp___1~0) [L627] havoc is_transmit3_triggered_#res; [L627] havoc is_transmit3_triggered_~__retres1~3; [L282] havoc is_transmit3_triggered_~__retres1~3; [L285] COND FALSE !(1 == ~t3_pc~0) [L295] is_transmit3_triggered_~__retres1~3 := 0; [L297] is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; [L627] activate_threads_#t~ret9 := is_transmit3_triggered_#res; [L627] activate_threads_~tmp___2~0 := activate_threads_#t~ret9; [L627] havoc activate_threads_#t~ret9; [L629-L633] COND FALSE !(0 != activate_threads_~tmp___2~0) [L635] havoc is_transmit4_triggered_#res; [L635] havoc is_transmit4_triggered_~__retres1~4; [L301] havoc is_transmit4_triggered_~__retres1~4; [L304] COND FALSE !(1 == ~t4_pc~0) [L314] is_transmit4_triggered_~__retres1~4 := 0; [L316] is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; [L635] activate_threads_#t~ret10 := is_transmit4_triggered_#res; [L635] activate_threads_~tmp___3~0 := activate_threads_#t~ret10; [L635] havoc activate_threads_#t~ret10; [L637-L641] COND FALSE !(0 != activate_threads_~tmp___3~0) [L545] COND FALSE !(1 == ~M_E~0) [L550] COND FALSE !(1 == ~T1_E~0) [L555] COND FALSE !(1 == ~T2_E~0) [L560] COND FALSE !(1 == ~T3_E~0) [L565] COND FALSE !(1 == ~T4_E~0) [L570] COND FALSE !(1 == ~E_1~0) [L575] COND FALSE !(1 == ~E_2~0) [L580] COND FALSE !(1 == ~E_3~0) [L585] COND FALSE !(1 == ~E_4~0) [L766-L803] COND FALSE !(false) [L769] start_simulation_~kernel_st~0 := 1; [L770] havoc eval_#t~ret0, eval_#t~nondet1, eval_~tmp_ndt_1~0, eval_#t~nondet2, eval_~tmp_ndt_2~0, eval_#t~nondet3, eval_~tmp_ndt_3~0, eval_#t~nondet4, eval_~tmp_ndt_4~0, eval_#t~nondet5, eval_~tmp_ndt_5~0, eval_~tmp~0; [L397] havoc eval_~tmp~0; [L15] ~m_pc~0 := 0; [L16] ~t1_pc~0 := 0; [L17] ~t2_pc~0 := 0; [L18] ~t3_pc~0 := 0; [L19] ~t4_pc~0 := 0; [L20] ~m_st~0 := 0; [L21] ~t1_st~0 := 0; [L22] ~t2_st~0 := 0; [L23] ~t3_st~0 := 0; [L24] ~t4_st~0 := 0; [L25] ~m_i~0 := 0; [L26] ~t1_i~0 := 0; [L27] ~t2_i~0 := 0; [L28] ~t3_i~0 := 0; [L29] ~t4_i~0 := 0; [L30] ~M_E~0 := 2; [L31] ~T1_E~0 := 2; [L32] ~T2_E~0 := 2; [L33] ~T3_E~0 := 2; [L34] ~T4_E~0 := 2; [L35] ~E_1~0 := 2; [L36] ~E_2~0 := 2; [L37] ~E_3~0 := 2; [L38] ~E_4~0 := 2; [L811] havoc ~__retres1~6; [L723] ~m_i~0 := 1; [L724] ~t1_i~0 := 1; [L725] ~t2_i~0 := 1; [L726] ~t3_i~0 := 1; [L727] ~t4_i~0 := 1; [L752] havoc ~kernel_st~0; [L753] havoc ~tmp~3; [L754] havoc ~tmp___0~1; [L758] ~kernel_st~0 := 0; [L331] COND TRUE 1 == ~m_i~0 [L332] ~m_st~0 := 0; [L336] COND TRUE 1 == ~t1_i~0 [L337] ~t1_st~0 := 0; [L341] COND TRUE 1 == ~t2_i~0 [L342] ~t2_st~0 := 0; [L346] COND TRUE 1 == ~t3_i~0 [L347] ~t3_st~0 := 0; [L351] COND TRUE 1 == ~t4_i~0 [L352] ~t4_st~0 := 0; [L492] COND FALSE !(0 == ~M_E~0) [L497] COND FALSE !(0 == ~T1_E~0) [L502] COND FALSE !(0 == ~T2_E~0) [L507] COND FALSE !(0 == ~T3_E~0) [L512] COND FALSE !(0 == ~T4_E~0) [L517] COND FALSE !(0 == ~E_1~0) [L522] COND FALSE !(0 == ~E_2~0) [L527] COND FALSE !(0 == ~E_3~0) [L532] COND FALSE !(0 == ~E_4~0) [L595] havoc ~tmp~1; [L596] havoc ~tmp___0~0; [L597] havoc ~tmp___1~0; [L598] havoc ~tmp___2~0; [L599] havoc ~tmp___3~0; [L225] havoc ~__retres1~0; [L228] COND FALSE !(1 == ~m_pc~0) [L238] ~__retres1~0 := 0; [L240] #res := ~__retres1~0; [L603] ~tmp~1 := #t~ret6; [L603] havoc #t~ret6; [L605-L609] COND FALSE !(0 != ~tmp~1) [L244] havoc ~__retres1~1; [L247] COND FALSE !(1 == ~t1_pc~0) [L257] ~__retres1~1 := 0; [L259] #res := ~__retres1~1; [L611] ~tmp___0~0 := #t~ret7; [L611] havoc #t~ret7; [L613-L617] COND FALSE !(0 != ~tmp___0~0) [L263] havoc ~__retres1~2; [L266] COND FALSE !(1 == ~t2_pc~0) [L276] ~__retres1~2 := 0; [L278] #res := ~__retres1~2; [L619] ~tmp___1~0 := #t~ret8; [L619] havoc #t~ret8; [L621-L625] COND FALSE !(0 != ~tmp___1~0) [L282] havoc ~__retres1~3; [L285] COND FALSE !(1 == ~t3_pc~0) [L295] ~__retres1~3 := 0; [L297] #res := ~__retres1~3; [L627] ~tmp___2~0 := #t~ret9; [L627] havoc #t~ret9; [L629-L633] COND FALSE !(0 != ~tmp___2~0) [L301] havoc ~__retres1~4; [L304] COND FALSE !(1 == ~t4_pc~0) [L314] ~__retres1~4 := 0; [L316] #res := ~__retres1~4; [L635] ~tmp___3~0 := #t~ret10; [L635] havoc #t~ret10; [L637-L641] COND FALSE !(0 != ~tmp___3~0) [L545] COND FALSE !(1 == ~M_E~0) [L550] COND FALSE !(1 == ~T1_E~0) [L555] COND FALSE !(1 == ~T2_E~0) [L560] COND FALSE !(1 == ~T3_E~0) [L565] COND FALSE !(1 == ~T4_E~0) [L570] COND FALSE !(1 == ~E_1~0) [L575] COND FALSE !(1 == ~E_2~0) [L580] COND FALSE !(1 == ~E_3~0) [L585] COND FALSE !(1 == ~E_4~0) [L766-L803] COND FALSE !(false) [L769] ~kernel_st~0 := 1; [L397] havoc ~tmp~0; ----- ----- class de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.CACSL2BoogieBacktranslator [L15] ~m_pc~0 := 0; [L16] ~t1_pc~0 := 0; [L17] ~t2_pc~0 := 0; [L18] ~t3_pc~0 := 0; [L19] ~t4_pc~0 := 0; [L20] ~m_st~0 := 0; [L21] ~t1_st~0 := 0; [L22] ~t2_st~0 := 0; [L23] ~t3_st~0 := 0; [L24] ~t4_st~0 := 0; [L25] ~m_i~0 := 0; [L26] ~t1_i~0 := 0; [L27] ~t2_i~0 := 0; [L28] ~t3_i~0 := 0; [L29] ~t4_i~0 := 0; [L30] ~M_E~0 := 2; [L31] ~T1_E~0 := 2; [L32] ~T2_E~0 := 2; [L33] ~T3_E~0 := 2; [L34] ~T4_E~0 := 2; [L35] ~E_1~0 := 2; [L36] ~E_2~0 := 2; [L37] ~E_3~0 := 2; [L38] ~E_4~0 := 2; [L811] havoc ~__retres1~6; [L723] ~m_i~0 := 1; [L724] ~t1_i~0 := 1; [L725] ~t2_i~0 := 1; [L726] ~t3_i~0 := 1; [L727] ~t4_i~0 := 1; [L752] havoc ~kernel_st~0; [L753] havoc ~tmp~3; [L754] havoc ~tmp___0~1; [L758] ~kernel_st~0 := 0; [L331] COND TRUE 1 == ~m_i~0 [L332] ~m_st~0 := 0; [L336] COND TRUE 1 == ~t1_i~0 [L337] ~t1_st~0 := 0; [L341] COND TRUE 1 == ~t2_i~0 [L342] ~t2_st~0 := 0; [L346] COND TRUE 1 == ~t3_i~0 [L347] ~t3_st~0 := 0; [L351] COND TRUE 1 == ~t4_i~0 [L352] ~t4_st~0 := 0; [L492] COND FALSE !(0 == ~M_E~0) [L497] COND FALSE !(0 == ~T1_E~0) [L502] COND FALSE !(0 == ~T2_E~0) [L507] COND FALSE !(0 == ~T3_E~0) [L512] COND FALSE !(0 == ~T4_E~0) [L517] COND FALSE !(0 == ~E_1~0) [L522] COND FALSE !(0 == ~E_2~0) [L527] COND FALSE !(0 == ~E_3~0) [L532] COND FALSE !(0 == ~E_4~0) [L595] havoc ~tmp~1; [L596] havoc ~tmp___0~0; [L597] havoc ~tmp___1~0; [L598] havoc ~tmp___2~0; [L599] havoc ~tmp___3~0; [L225] havoc ~__retres1~0; [L228] COND FALSE !(1 == ~m_pc~0) [L238] ~__retres1~0 := 0; [L240] #res := ~__retres1~0; [L603] ~tmp~1 := #t~ret6; [L603] havoc #t~ret6; [L605-L609] COND FALSE !(0 != ~tmp~1) [L244] havoc ~__retres1~1; [L247] COND FALSE !(1 == ~t1_pc~0) [L257] ~__retres1~1 := 0; [L259] #res := ~__retres1~1; [L611] ~tmp___0~0 := #t~ret7; [L611] havoc #t~ret7; [L613-L617] COND FALSE !(0 != ~tmp___0~0) [L263] havoc ~__retres1~2; [L266] COND FALSE !(1 == ~t2_pc~0) [L276] ~__retres1~2 := 0; [L278] #res := ~__retres1~2; [L619] ~tmp___1~0 := #t~ret8; [L619] havoc #t~ret8; [L621-L625] COND FALSE !(0 != ~tmp___1~0) [L282] havoc ~__retres1~3; [L285] COND FALSE !(1 == ~t3_pc~0) [L295] ~__retres1~3 := 0; [L297] #res := ~__retres1~3; [L627] ~tmp___2~0 := #t~ret9; [L627] havoc #t~ret9; [L629-L633] COND FALSE !(0 != ~tmp___2~0) [L301] havoc ~__retres1~4; [L304] COND FALSE !(1 == ~t4_pc~0) [L314] ~__retres1~4 := 0; [L316] #res := ~__retres1~4; [L635] ~tmp___3~0 := #t~ret10; [L635] havoc #t~ret10; [L637-L641] COND FALSE !(0 != ~tmp___3~0) [L545] COND FALSE !(1 == ~M_E~0) [L550] COND FALSE !(1 == ~T1_E~0) [L555] COND FALSE !(1 == ~T2_E~0) [L560] COND FALSE !(1 == ~T3_E~0) [L565] COND FALSE !(1 == ~T4_E~0) [L570] COND FALSE !(1 == ~E_1~0) [L575] COND FALSE !(1 == ~E_2~0) [L580] COND FALSE !(1 == ~E_3~0) [L585] COND FALSE !(1 == ~E_4~0) [L766-L803] COND FALSE !(false) [L769] ~kernel_st~0 := 1; [L397] havoc ~tmp~0; [L15] int m_pc = 0; [L16] int t1_pc = 0; [L17] int t2_pc = 0; [L18] int t3_pc = 0; [L19] int t4_pc = 0; [L20] int m_st ; [L21] int t1_st ; [L22] int t2_st ; [L23] int t3_st ; [L24] int t4_st ; [L25] int m_i ; [L26] int t1_i ; [L27] int t2_i ; [L28] int t3_i ; [L29] int t4_i ; [L30] int M_E = 2; [L31] int T1_E = 2; [L32] int T2_E = 2; [L33] int T3_E = 2; [L34] int T4_E = 2; [L35] int E_1 = 2; [L36] int E_2 = 2; [L37] int E_3 = 2; [L38] int E_4 = 2; [L811] int __retres1 ; [L723] m_i = 1 [L724] t1_i = 1 [L725] t2_i = 1 [L726] t3_i = 1 [L727] t4_i = 1 [L752] int kernel_st ; [L753] int tmp ; [L754] int tmp___0 ; [L758] kernel_st = 0 [L331] COND TRUE m_i == 1 [L332] m_st = 0 [L336] COND TRUE t1_i == 1 [L337] t1_st = 0 [L341] COND TRUE t2_i == 1 [L342] t2_st = 0 [L346] COND TRUE t3_i == 1 [L347] t3_st = 0 [L351] COND TRUE t4_i == 1 [L352] t4_st = 0 [L492] COND FALSE !(M_E == 0) [L497] COND FALSE !(T1_E == 0) [L502] COND FALSE !(T2_E == 0) [L507] COND FALSE !(T3_E == 0) [L512] COND FALSE !(T4_E == 0) [L517] COND FALSE !(E_1 == 0) [L522] COND FALSE !(E_2 == 0) [L527] COND FALSE !(E_3 == 0) [L532] COND FALSE !(E_4 == 0) [L595] int tmp ; [L596] int tmp___0 ; [L597] int tmp___1 ; [L598] int tmp___2 ; [L599] int tmp___3 ; [L225] int __retres1 ; [L228] COND FALSE !(m_pc == 1) [L238] __retres1 = 0 [L240] return (__retres1); [L603] tmp = is_master_triggered() [L605] COND FALSE !(\read(tmp)) [L244] int __retres1 ; [L247] COND FALSE !(t1_pc == 1) [L257] __retres1 = 0 [L259] return (__retres1); [L611] tmp___0 = is_transmit1_triggered() [L613] COND FALSE !(\read(tmp___0)) [L263] int __retres1 ; [L266] COND FALSE !(t2_pc == 1) [L276] __retres1 = 0 [L278] return (__retres1); [L619] tmp___1 = is_transmit2_triggered() [L621] COND FALSE !(\read(tmp___1)) [L282] int __retres1 ; [L285] COND FALSE !(t3_pc == 1) [L295] __retres1 = 0 [L297] return (__retres1); [L627] tmp___2 = is_transmit3_triggered() [L629] COND FALSE !(\read(tmp___2)) [L301] int __retres1 ; [L304] COND FALSE !(t4_pc == 1) [L314] __retres1 = 0 [L316] return (__retres1); [L635] tmp___3 = is_transmit4_triggered() [L637] COND FALSE !(\read(tmp___3)) [L545] COND FALSE !(M_E == 1) [L550] COND FALSE !(T1_E == 1) [L555] COND FALSE !(T2_E == 1) [L560] COND FALSE !(T3_E == 1) [L565] COND FALSE !(T4_E == 1) [L570] COND FALSE !(E_1 == 1) [L575] COND FALSE !(E_2 == 1) [L580] COND FALSE !(E_3 == 1) [L585] COND FALSE !(E_4 == 1) [L766] COND TRUE 1 [L769] kernel_st = 1 [L397] int tmp ; ----- ----- class de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder.RCFGBacktranslator [?] assume !false; [?] havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; [?] assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; [?] exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; [?] eval_#t~ret0 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret0;havoc eval_#t~ret0; [?] assume 0 != eval_~tmp~0; [?] assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0;eval_~tmp_ndt_1~0 := eval_#t~nondet1;havoc eval_#t~nondet1; [?] assume !(0 != eval_~tmp_ndt_1~0); [?] assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0;eval_~tmp_ndt_2~0 := eval_#t~nondet2;havoc eval_#t~nondet2; [?] assume !(0 != eval_~tmp_ndt_2~0); [?] assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0;eval_~tmp_ndt_3~0 := eval_#t~nondet3;havoc eval_#t~nondet3; [?] assume !(0 != eval_~tmp_ndt_3~0); [?] assume 0 == ~t3_st~0;havoc eval_~tmp_ndt_4~0;eval_~tmp_ndt_4~0 := eval_#t~nondet4;havoc eval_#t~nondet4; [?] assume !(0 != eval_~tmp_ndt_4~0); [?] assume 0 == ~t4_st~0;havoc eval_~tmp_ndt_5~0;eval_~tmp_ndt_5~0 := eval_#t~nondet5;havoc eval_#t~nondet5; [?] assume !(0 != eval_~tmp_ndt_5~0); [L401-L481] assume !false; [L404] havoc exists_runnable_thread_#res; [L404] havoc exists_runnable_thread_~__retres1~5; [L361] havoc exists_runnable_thread_~__retres1~5; [L364-L389] assume 0 == ~m_st~0; [L365] exists_runnable_thread_~__retres1~5 := 1; [L392] exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; [L404] eval_#t~ret0 := exists_runnable_thread_#res; [L404] eval_~tmp~0 := eval_#t~ret0; [L404] havoc eval_#t~ret0; [L406-L410] assume 0 != eval_~tmp~0; [L411-L424] assume 0 == ~m_st~0; [L412] havoc eval_~tmp_ndt_1~0; [L413] eval_~tmp_ndt_1~0 := eval_#t~nondet1; [L413] havoc eval_#t~nondet1; [L414-L421] assume !(0 != eval_~tmp_ndt_1~0); [L425-L438] assume 0 == ~t1_st~0; [L426] havoc eval_~tmp_ndt_2~0; [L427] eval_~tmp_ndt_2~0 := eval_#t~nondet2; [L427] havoc eval_#t~nondet2; [L428-L435] assume !(0 != eval_~tmp_ndt_2~0); [L439-L452] assume 0 == ~t2_st~0; [L440] havoc eval_~tmp_ndt_3~0; [L441] eval_~tmp_ndt_3~0 := eval_#t~nondet3; [L441] havoc eval_#t~nondet3; [L442-L449] assume !(0 != eval_~tmp_ndt_3~0); [L453-L466] assume 0 == ~t3_st~0; [L454] havoc eval_~tmp_ndt_4~0; [L455] eval_~tmp_ndt_4~0 := eval_#t~nondet4; [L455] havoc eval_#t~nondet4; [L456-L463] assume !(0 != eval_~tmp_ndt_4~0); [L467-L480] assume 0 == ~t4_st~0; [L468] havoc eval_~tmp_ndt_5~0; [L469] eval_~tmp_ndt_5~0 := eval_#t~nondet5; [L469] havoc eval_#t~nondet5; [L470-L477] assume !(0 != eval_~tmp_ndt_5~0); ----- ----- class de.uni_freiburg.informatik.ultimate.boogie.preprocessor.BoogiePreprocessorBacktranslator [L401-L481] assume !false; [L404] havoc exists_runnable_thread_#res; [L404] havoc exists_runnable_thread_~__retres1~5; [L361] havoc exists_runnable_thread_~__retres1~5; [L364-L389] assume 0 == ~m_st~0; [L365] exists_runnable_thread_~__retres1~5 := 1; [L392] exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; [L404] eval_#t~ret0 := exists_runnable_thread_#res; [L404] eval_~tmp~0 := eval_#t~ret0; [L404] havoc eval_#t~ret0; [L406-L410] assume 0 != eval_~tmp~0; [L411-L424] assume 0 == ~m_st~0; [L412] havoc eval_~tmp_ndt_1~0; [L413] eval_~tmp_ndt_1~0 := eval_#t~nondet1; [L413] havoc eval_#t~nondet1; [L414-L421] assume !(0 != eval_~tmp_ndt_1~0); [L425-L438] assume 0 == ~t1_st~0; [L426] havoc eval_~tmp_ndt_2~0; [L427] eval_~tmp_ndt_2~0 := eval_#t~nondet2; [L427] havoc eval_#t~nondet2; [L428-L435] assume !(0 != eval_~tmp_ndt_2~0); [L439-L452] assume 0 == ~t2_st~0; [L440] havoc eval_~tmp_ndt_3~0; [L441] eval_~tmp_ndt_3~0 := eval_#t~nondet3; [L441] havoc eval_#t~nondet3; [L442-L449] assume !(0 != eval_~tmp_ndt_3~0); [L453-L466] assume 0 == ~t3_st~0; [L454] havoc eval_~tmp_ndt_4~0; [L455] eval_~tmp_ndt_4~0 := eval_#t~nondet4; [L455] havoc eval_#t~nondet4; [L456-L463] assume !(0 != eval_~tmp_ndt_4~0); [L467-L480] assume 0 == ~t4_st~0; [L468] havoc eval_~tmp_ndt_5~0; [L469] eval_~tmp_ndt_5~0 := eval_#t~nondet5; [L469] havoc eval_#t~nondet5; [L470-L477] assume !(0 != eval_~tmp_ndt_5~0); [L401-L481] COND FALSE !(false) [L404] havoc exists_runnable_thread_#res; [L404] havoc exists_runnable_thread_~__retres1~5; [L361] havoc exists_runnable_thread_~__retres1~5; [L364] COND TRUE 0 == ~m_st~0 [L365] exists_runnable_thread_~__retres1~5 := 1; [L392] exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; [L404] eval_#t~ret0 := exists_runnable_thread_#res; [L404] eval_~tmp~0 := eval_#t~ret0; [L404] havoc eval_#t~ret0; [L406-L410] COND TRUE 0 != eval_~tmp~0 [L411] COND TRUE 0 == ~m_st~0 [L412] havoc eval_~tmp_ndt_1~0; [L413] eval_~tmp_ndt_1~0 := eval_#t~nondet1; [L413] havoc eval_#t~nondet1; [L414-L421] COND FALSE !(0 != eval_~tmp_ndt_1~0) [L425] COND TRUE 0 == ~t1_st~0 [L426] havoc eval_~tmp_ndt_2~0; [L427] eval_~tmp_ndt_2~0 := eval_#t~nondet2; [L427] havoc eval_#t~nondet2; [L428-L435] COND FALSE !(0 != eval_~tmp_ndt_2~0) [L439] COND TRUE 0 == ~t2_st~0 [L440] havoc eval_~tmp_ndt_3~0; [L441] eval_~tmp_ndt_3~0 := eval_#t~nondet3; [L441] havoc eval_#t~nondet3; [L442-L449] COND FALSE !(0 != eval_~tmp_ndt_3~0) [L453] COND TRUE 0 == ~t3_st~0 [L454] havoc eval_~tmp_ndt_4~0; [L455] eval_~tmp_ndt_4~0 := eval_#t~nondet4; [L455] havoc eval_#t~nondet4; [L456-L463] COND FALSE !(0 != eval_~tmp_ndt_4~0) [L467] COND TRUE 0 == ~t4_st~0 [L468] havoc eval_~tmp_ndt_5~0; [L469] eval_~tmp_ndt_5~0 := eval_#t~nondet5; [L469] havoc eval_#t~nondet5; [L470-L477] COND FALSE !(0 != eval_~tmp_ndt_5~0) ----- ----- class de.uni_freiburg.informatik.ultimate.boogie.procedureinliner.backtranslation.InlinerBacktranslator [L401-L481] COND FALSE !(false) [L404] havoc exists_runnable_thread_#res; [L404] havoc exists_runnable_thread_~__retres1~5; [L361] havoc exists_runnable_thread_~__retres1~5; [L364] COND TRUE 0 == ~m_st~0 [L365] exists_runnable_thread_~__retres1~5 := 1; [L392] exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; [L404] eval_#t~ret0 := exists_runnable_thread_#res; [L404] eval_~tmp~0 := eval_#t~ret0; [L404] havoc eval_#t~ret0; [L406-L410] COND TRUE 0 != eval_~tmp~0 [L411] COND TRUE 0 == ~m_st~0 [L412] havoc eval_~tmp_ndt_1~0; [L413] eval_~tmp_ndt_1~0 := eval_#t~nondet1; [L413] havoc eval_#t~nondet1; [L414-L421] COND FALSE !(0 != eval_~tmp_ndt_1~0) [L425] COND TRUE 0 == ~t1_st~0 [L426] havoc eval_~tmp_ndt_2~0; [L427] eval_~tmp_ndt_2~0 := eval_#t~nondet2; [L427] havoc eval_#t~nondet2; [L428-L435] COND FALSE !(0 != eval_~tmp_ndt_2~0) [L439] COND TRUE 0 == ~t2_st~0 [L440] havoc eval_~tmp_ndt_3~0; [L441] eval_~tmp_ndt_3~0 := eval_#t~nondet3; [L441] havoc eval_#t~nondet3; [L442-L449] COND FALSE !(0 != eval_~tmp_ndt_3~0) [L453] COND TRUE 0 == ~t3_st~0 [L454] havoc eval_~tmp_ndt_4~0; [L455] eval_~tmp_ndt_4~0 := eval_#t~nondet4; [L455] havoc eval_#t~nondet4; [L456-L463] COND FALSE !(0 != eval_~tmp_ndt_4~0) [L467] COND TRUE 0 == ~t4_st~0 [L468] havoc eval_~tmp_ndt_5~0; [L469] eval_~tmp_ndt_5~0 := eval_#t~nondet5; [L469] havoc eval_#t~nondet5; [L470-L477] COND FALSE !(0 != eval_~tmp_ndt_5~0) [L401-L481] COND FALSE !(false) [L361] havoc ~__retres1~5; [L364] COND TRUE 0 == ~m_st~0 [L365] ~__retres1~5 := 1; [L392] #res := ~__retres1~5; [L404] ~tmp~0 := #t~ret0; [L404] havoc #t~ret0; [L406-L410] COND TRUE 0 != ~tmp~0 [L411] COND TRUE 0 == ~m_st~0 [L412] havoc ~tmp_ndt_1~0; [L413] ~tmp_ndt_1~0 := #t~nondet1; [L413] havoc #t~nondet1; [L414-L421] COND FALSE !(0 != ~tmp_ndt_1~0) [L425] COND TRUE 0 == ~t1_st~0 [L426] havoc ~tmp_ndt_2~0; [L427] ~tmp_ndt_2~0 := #t~nondet2; [L427] havoc #t~nondet2; [L428-L435] COND FALSE !(0 != ~tmp_ndt_2~0) [L439] COND TRUE 0 == ~t2_st~0 [L440] havoc ~tmp_ndt_3~0; [L441] ~tmp_ndt_3~0 := #t~nondet3; [L441] havoc #t~nondet3; [L442-L449] COND FALSE !(0 != ~tmp_ndt_3~0) [L453] COND TRUE 0 == ~t3_st~0 [L454] havoc ~tmp_ndt_4~0; [L455] ~tmp_ndt_4~0 := #t~nondet4; [L455] havoc #t~nondet4; [L456-L463] COND FALSE !(0 != ~tmp_ndt_4~0) [L467] COND TRUE 0 == ~t4_st~0 [L468] havoc ~tmp_ndt_5~0; [L469] ~tmp_ndt_5~0 := #t~nondet5; [L469] havoc #t~nondet5; [L470-L477] COND FALSE !(0 != ~tmp_ndt_5~0) ----- ----- class de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.CACSL2BoogieBacktranslator [L401-L481] COND FALSE !(false) [L361] havoc ~__retres1~5; [L364] COND TRUE 0 == ~m_st~0 [L365] ~__retres1~5 := 1; [L392] #res := ~__retres1~5; [L404] ~tmp~0 := #t~ret0; [L404] havoc #t~ret0; [L406-L410] COND TRUE 0 != ~tmp~0 [L411] COND TRUE 0 == ~m_st~0 [L412] havoc ~tmp_ndt_1~0; [L413] ~tmp_ndt_1~0 := #t~nondet1; [L413] havoc #t~nondet1; [L414-L421] COND FALSE !(0 != ~tmp_ndt_1~0) [L425] COND TRUE 0 == ~t1_st~0 [L426] havoc ~tmp_ndt_2~0; [L427] ~tmp_ndt_2~0 := #t~nondet2; [L427] havoc #t~nondet2; [L428-L435] COND FALSE !(0 != ~tmp_ndt_2~0) [L439] COND TRUE 0 == ~t2_st~0 [L440] havoc ~tmp_ndt_3~0; [L441] ~tmp_ndt_3~0 := #t~nondet3; [L441] havoc #t~nondet3; [L442-L449] COND FALSE !(0 != ~tmp_ndt_3~0) [L453] COND TRUE 0 == ~t3_st~0 [L454] havoc ~tmp_ndt_4~0; [L455] ~tmp_ndt_4~0 := #t~nondet4; [L455] havoc #t~nondet4; [L456-L463] COND FALSE !(0 != ~tmp_ndt_4~0) [L467] COND TRUE 0 == ~t4_st~0 [L468] havoc ~tmp_ndt_5~0; [L469] ~tmp_ndt_5~0 := #t~nondet5; [L469] havoc #t~nondet5; [L470-L477] COND FALSE !(0 != ~tmp_ndt_5~0) [L401] COND TRUE 1 [L361] int __retres1 ; [L364] COND TRUE m_st == 0 [L365] __retres1 = 1 [L392] return (__retres1); [L404] tmp = exists_runnable_thread() [L406] COND TRUE \read(tmp) [L411] COND TRUE m_st == 0 [L412] int tmp_ndt_1; [L413] tmp_ndt_1 = __VERIFIER_nondet_int() [L414] COND FALSE !(\read(tmp_ndt_1)) [L425] COND TRUE t1_st == 0 [L426] int tmp_ndt_2; [L427] tmp_ndt_2 = __VERIFIER_nondet_int() [L428] COND FALSE !(\read(tmp_ndt_2)) [L439] COND TRUE t2_st == 0 [L440] int tmp_ndt_3; [L441] tmp_ndt_3 = __VERIFIER_nondet_int() [L442] COND FALSE !(\read(tmp_ndt_3)) [L453] COND TRUE t3_st == 0 [L454] int tmp_ndt_4; [L455] tmp_ndt_4 = __VERIFIER_nondet_int() [L456] COND FALSE !(\read(tmp_ndt_4)) [L467] COND TRUE t4_st == 0 [L468] int tmp_ndt_5; [L469] tmp_ndt_5 = __VERIFIER_nondet_int() [L470] COND FALSE !(\read(tmp_ndt_5)) ----- [2018-11-23 12:43:44,867 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer CFG 23.11 12:43:44 BoogieIcfgContainer [2018-11-23 12:43:44,867 INFO L132 PluginConnector]: ------------------------ END BuchiAutomizer---------------------------- [2018-11-23 12:43:44,867 INFO L113 PluginConnector]: ------------------------Witness Printer---------------------------- [2018-11-23 12:43:44,867 INFO L271 PluginConnector]: Initializing Witness Printer... [2018-11-23 12:43:44,868 INFO L276 PluginConnector]: Witness Printer initialized [2018-11-23 12:43:44,868 INFO L185 PluginConnector]: Executing the observer RCFGCatcher from plugin Witness Printer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 23.11 12:43:37" (3/4) ... [2018-11-23 12:43:44,871 INFO L141 WitnessPrinter]: Generating witness for non-termination counterexample ----- class de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder.RCFGBacktranslator [?] ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2; [?] havoc main_#res;havoc main_~__retres1~6;havoc main_~__retres1~6;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; [?] havoc start_simulation_#t~ret12, start_simulation_#t~ret13, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; [?] assume 1 == ~m_i~0;~m_st~0 := 0; [?] assume 1 == ~t1_i~0;~t1_st~0 := 0; [?] assume 1 == ~t2_i~0;~t2_st~0 := 0; [?] assume 1 == ~t3_i~0;~t3_st~0 := 0; [?] assume 1 == ~t4_i~0;~t4_st~0 := 0; [?] assume !(0 == ~M_E~0); [?] assume !(0 == ~T1_E~0); [?] assume !(0 == ~T2_E~0); [?] assume !(0 == ~T3_E~0); [?] assume !(0 == ~T4_E~0); [?] assume !(0 == ~E_1~0); [?] assume !(0 == ~E_2~0); [?] assume !(0 == ~E_3~0); [?] assume !(0 == ~E_4~0); [?] havoc activate_threads_#t~ret6, activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; [?] assume !(1 == ~m_pc~0); [?] is_master_triggered_~__retres1~0 := 0; [?] is_master_triggered_#res := is_master_triggered_~__retres1~0; [?] activate_threads_#t~ret6 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret6;havoc activate_threads_#t~ret6; [?] assume !(0 != activate_threads_~tmp~1); [?] havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; [?] assume !(1 == ~t1_pc~0); [?] is_transmit1_triggered_~__retres1~1 := 0; [?] is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; [?] activate_threads_#t~ret7 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; [?] assume !(0 != activate_threads_~tmp___0~0); [?] havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; [?] assume !(1 == ~t2_pc~0); [?] is_transmit2_triggered_~__retres1~2 := 0; [?] is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; [?] activate_threads_#t~ret8 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; [?] assume !(0 != activate_threads_~tmp___1~0); [?] havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; [?] assume !(1 == ~t3_pc~0); [?] is_transmit3_triggered_~__retres1~3 := 0; [?] is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; [?] activate_threads_#t~ret9 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; [?] assume !(0 != activate_threads_~tmp___2~0); [?] havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; [?] assume !(1 == ~t4_pc~0); [?] is_transmit4_triggered_~__retres1~4 := 0; [?] is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; [?] activate_threads_#t~ret10 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; [?] assume !(0 != activate_threads_~tmp___3~0); [?] assume !(1 == ~M_E~0); [?] assume !(1 == ~T1_E~0); [?] assume !(1 == ~T2_E~0); [?] assume !(1 == ~T3_E~0); [?] assume !(1 == ~T4_E~0); [?] assume !(1 == ~E_1~0); [?] assume !(1 == ~E_2~0); [?] assume !(1 == ~E_3~0); [?] assume !(1 == ~E_4~0); [?] assume !false; [?] start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret0, eval_#t~nondet1, eval_~tmp_ndt_1~0, eval_#t~nondet2, eval_~tmp_ndt_2~0, eval_#t~nondet3, eval_~tmp_ndt_3~0, eval_#t~nondet4, eval_~tmp_ndt_4~0, eval_#t~nondet5, eval_~tmp_ndt_5~0, eval_~tmp~0;havoc eval_~tmp~0; [L15] ~m_pc~0 := 0; [L16] ~t1_pc~0 := 0; [L17] ~t2_pc~0 := 0; [L18] ~t3_pc~0 := 0; [L19] ~t4_pc~0 := 0; [L20] ~m_st~0 := 0; [L21] ~t1_st~0 := 0; [L22] ~t2_st~0 := 0; [L23] ~t3_st~0 := 0; [L24] ~t4_st~0 := 0; [L25] ~m_i~0 := 0; [L26] ~t1_i~0 := 0; [L27] ~t2_i~0 := 0; [L28] ~t3_i~0 := 0; [L29] ~t4_i~0 := 0; [L30] ~M_E~0 := 2; [L31] ~T1_E~0 := 2; [L32] ~T2_E~0 := 2; [L33] ~T3_E~0 := 2; [L34] ~T4_E~0 := 2; [L35] ~E_1~0 := 2; [L36] ~E_2~0 := 2; [L37] ~E_3~0 := 2; [L38] ~E_4~0 := 2; [?] havoc main_#res; [?] havoc main_~__retres1~6; [L811] havoc main_~__retres1~6; [L723] ~m_i~0 := 1; [L724] ~t1_i~0 := 1; [L725] ~t2_i~0 := 1; [L726] ~t3_i~0 := 1; [L727] ~t4_i~0 := 1; [L816] havoc start_simulation_#t~ret12, start_simulation_#t~ret13, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1; [L752] havoc start_simulation_~kernel_st~0; [L753] havoc start_simulation_~tmp~3; [L754] havoc start_simulation_~tmp___0~1; [L758] start_simulation_~kernel_st~0 := 0; [L331-L335] assume 1 == ~m_i~0; [L332] ~m_st~0 := 0; [L336-L340] assume 1 == ~t1_i~0; [L337] ~t1_st~0 := 0; [L341-L345] assume 1 == ~t2_i~0; [L342] ~t2_st~0 := 0; [L346-L350] assume 1 == ~t3_i~0; [L347] ~t3_st~0 := 0; [L351-L355] assume 1 == ~t4_i~0; [L352] ~t4_st~0 := 0; [L492-L496] assume !(0 == ~M_E~0); [L497-L501] assume !(0 == ~T1_E~0); [L502-L506] assume !(0 == ~T2_E~0); [L507-L511] assume !(0 == ~T3_E~0); [L512-L516] assume !(0 == ~T4_E~0); [L517-L521] assume !(0 == ~E_1~0); [L522-L526] assume !(0 == ~E_2~0); [L527-L531] assume !(0 == ~E_3~0); [L532-L536] assume !(0 == ~E_4~0); [L762] havoc activate_threads_#t~ret6, activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0; [L595] havoc activate_threads_~tmp~1; [L596] havoc activate_threads_~tmp___0~0; [L597] havoc activate_threads_~tmp___1~0; [L598] havoc activate_threads_~tmp___2~0; [L599] havoc activate_threads_~tmp___3~0; [L603] havoc is_master_triggered_#res; [L603] havoc is_master_triggered_~__retres1~0; [L225] havoc is_master_triggered_~__retres1~0; [L228-L237] assume !(1 == ~m_pc~0); [L238] is_master_triggered_~__retres1~0 := 0; [L240] is_master_triggered_#res := is_master_triggered_~__retres1~0; [L603] activate_threads_#t~ret6 := is_master_triggered_#res; [L603] activate_threads_~tmp~1 := activate_threads_#t~ret6; [L603] havoc activate_threads_#t~ret6; [L605-L609] assume !(0 != activate_threads_~tmp~1); [L611] havoc is_transmit1_triggered_#res; [L611] havoc is_transmit1_triggered_~__retres1~1; [L244] havoc is_transmit1_triggered_~__retres1~1; [L247-L256] assume !(1 == ~t1_pc~0); [L257] is_transmit1_triggered_~__retres1~1 := 0; [L259] is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; [L611] activate_threads_#t~ret7 := is_transmit1_triggered_#res; [L611] activate_threads_~tmp___0~0 := activate_threads_#t~ret7; [L611] havoc activate_threads_#t~ret7; [L613-L617] assume !(0 != activate_threads_~tmp___0~0); [L619] havoc is_transmit2_triggered_#res; [L619] havoc is_transmit2_triggered_~__retres1~2; [L263] havoc is_transmit2_triggered_~__retres1~2; [L266-L275] assume !(1 == ~t2_pc~0); [L276] is_transmit2_triggered_~__retres1~2 := 0; [L278] is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; [L619] activate_threads_#t~ret8 := is_transmit2_triggered_#res; [L619] activate_threads_~tmp___1~0 := activate_threads_#t~ret8; [L619] havoc activate_threads_#t~ret8; [L621-L625] assume !(0 != activate_threads_~tmp___1~0); [L627] havoc is_transmit3_triggered_#res; [L627] havoc is_transmit3_triggered_~__retres1~3; [L282] havoc is_transmit3_triggered_~__retres1~3; [L285-L294] assume !(1 == ~t3_pc~0); [L295] is_transmit3_triggered_~__retres1~3 := 0; [L297] is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; [L627] activate_threads_#t~ret9 := is_transmit3_triggered_#res; [L627] activate_threads_~tmp___2~0 := activate_threads_#t~ret9; [L627] havoc activate_threads_#t~ret9; [L629-L633] assume !(0 != activate_threads_~tmp___2~0); [L635] havoc is_transmit4_triggered_#res; [L635] havoc is_transmit4_triggered_~__retres1~4; [L301] havoc is_transmit4_triggered_~__retres1~4; [L304-L313] assume !(1 == ~t4_pc~0); [L314] is_transmit4_triggered_~__retres1~4 := 0; [L316] is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; [L635] activate_threads_#t~ret10 := is_transmit4_triggered_#res; [L635] activate_threads_~tmp___3~0 := activate_threads_#t~ret10; [L635] havoc activate_threads_#t~ret10; [L637-L641] assume !(0 != activate_threads_~tmp___3~0); [L545-L549] assume !(1 == ~M_E~0); [L550-L554] assume !(1 == ~T1_E~0); [L555-L559] assume !(1 == ~T2_E~0); [L560-L564] assume !(1 == ~T3_E~0); [L565-L569] assume !(1 == ~T4_E~0); [L570-L574] assume !(1 == ~E_1~0); [L575-L579] assume !(1 == ~E_2~0); [L580-L584] assume !(1 == ~E_3~0); [L585-L589] assume !(1 == ~E_4~0); [L766-L803] assume !false; [L769] start_simulation_~kernel_st~0 := 1; [L770] havoc eval_#t~ret0, eval_#t~nondet1, eval_~tmp_ndt_1~0, eval_#t~nondet2, eval_~tmp_ndt_2~0, eval_#t~nondet3, eval_~tmp_ndt_3~0, eval_#t~nondet4, eval_~tmp_ndt_4~0, eval_#t~nondet5, eval_~tmp_ndt_5~0, eval_~tmp~0; [L397] havoc eval_~tmp~0; ----- ----- class de.uni_freiburg.informatik.ultimate.boogie.preprocessor.BoogiePreprocessorBacktranslator [L15] ~m_pc~0 := 0; [L16] ~t1_pc~0 := 0; [L17] ~t2_pc~0 := 0; [L18] ~t3_pc~0 := 0; [L19] ~t4_pc~0 := 0; [L20] ~m_st~0 := 0; [L21] ~t1_st~0 := 0; [L22] ~t2_st~0 := 0; [L23] ~t3_st~0 := 0; [L24] ~t4_st~0 := 0; [L25] ~m_i~0 := 0; [L26] ~t1_i~0 := 0; [L27] ~t2_i~0 := 0; [L28] ~t3_i~0 := 0; [L29] ~t4_i~0 := 0; [L30] ~M_E~0 := 2; [L31] ~T1_E~0 := 2; [L32] ~T2_E~0 := 2; [L33] ~T3_E~0 := 2; [L34] ~T4_E~0 := 2; [L35] ~E_1~0 := 2; [L36] ~E_2~0 := 2; [L37] ~E_3~0 := 2; [L38] ~E_4~0 := 2; [?] havoc main_#res; [?] havoc main_~__retres1~6; [L811] havoc main_~__retres1~6; [L723] ~m_i~0 := 1; [L724] ~t1_i~0 := 1; [L725] ~t2_i~0 := 1; [L726] ~t3_i~0 := 1; [L727] ~t4_i~0 := 1; [L816] havoc start_simulation_#t~ret12, start_simulation_#t~ret13, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1; [L752] havoc start_simulation_~kernel_st~0; [L753] havoc start_simulation_~tmp~3; [L754] havoc start_simulation_~tmp___0~1; [L758] start_simulation_~kernel_st~0 := 0; [L331-L335] assume 1 == ~m_i~0; [L332] ~m_st~0 := 0; [L336-L340] assume 1 == ~t1_i~0; [L337] ~t1_st~0 := 0; [L341-L345] assume 1 == ~t2_i~0; [L342] ~t2_st~0 := 0; [L346-L350] assume 1 == ~t3_i~0; [L347] ~t3_st~0 := 0; [L351-L355] assume 1 == ~t4_i~0; [L352] ~t4_st~0 := 0; [L492-L496] assume !(0 == ~M_E~0); [L497-L501] assume !(0 == ~T1_E~0); [L502-L506] assume !(0 == ~T2_E~0); [L507-L511] assume !(0 == ~T3_E~0); [L512-L516] assume !(0 == ~T4_E~0); [L517-L521] assume !(0 == ~E_1~0); [L522-L526] assume !(0 == ~E_2~0); [L527-L531] assume !(0 == ~E_3~0); [L532-L536] assume !(0 == ~E_4~0); [L762] havoc activate_threads_#t~ret6, activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0; [L595] havoc activate_threads_~tmp~1; [L596] havoc activate_threads_~tmp___0~0; [L597] havoc activate_threads_~tmp___1~0; [L598] havoc activate_threads_~tmp___2~0; [L599] havoc activate_threads_~tmp___3~0; [L603] havoc is_master_triggered_#res; [L603] havoc is_master_triggered_~__retres1~0; [L225] havoc is_master_triggered_~__retres1~0; [L228-L237] assume !(1 == ~m_pc~0); [L238] is_master_triggered_~__retres1~0 := 0; [L240] is_master_triggered_#res := is_master_triggered_~__retres1~0; [L603] activate_threads_#t~ret6 := is_master_triggered_#res; [L603] activate_threads_~tmp~1 := activate_threads_#t~ret6; [L603] havoc activate_threads_#t~ret6; [L605-L609] assume !(0 != activate_threads_~tmp~1); [L611] havoc is_transmit1_triggered_#res; [L611] havoc is_transmit1_triggered_~__retres1~1; [L244] havoc is_transmit1_triggered_~__retres1~1; [L247-L256] assume !(1 == ~t1_pc~0); [L257] is_transmit1_triggered_~__retres1~1 := 0; [L259] is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; [L611] activate_threads_#t~ret7 := is_transmit1_triggered_#res; [L611] activate_threads_~tmp___0~0 := activate_threads_#t~ret7; [L611] havoc activate_threads_#t~ret7; [L613-L617] assume !(0 != activate_threads_~tmp___0~0); [L619] havoc is_transmit2_triggered_#res; [L619] havoc is_transmit2_triggered_~__retres1~2; [L263] havoc is_transmit2_triggered_~__retres1~2; [L266-L275] assume !(1 == ~t2_pc~0); [L276] is_transmit2_triggered_~__retres1~2 := 0; [L278] is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; [L619] activate_threads_#t~ret8 := is_transmit2_triggered_#res; [L619] activate_threads_~tmp___1~0 := activate_threads_#t~ret8; [L619] havoc activate_threads_#t~ret8; [L621-L625] assume !(0 != activate_threads_~tmp___1~0); [L627] havoc is_transmit3_triggered_#res; [L627] havoc is_transmit3_triggered_~__retres1~3; [L282] havoc is_transmit3_triggered_~__retres1~3; [L285-L294] assume !(1 == ~t3_pc~0); [L295] is_transmit3_triggered_~__retres1~3 := 0; [L297] is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; [L627] activate_threads_#t~ret9 := is_transmit3_triggered_#res; [L627] activate_threads_~tmp___2~0 := activate_threads_#t~ret9; [L627] havoc activate_threads_#t~ret9; [L629-L633] assume !(0 != activate_threads_~tmp___2~0); [L635] havoc is_transmit4_triggered_#res; [L635] havoc is_transmit4_triggered_~__retres1~4; [L301] havoc is_transmit4_triggered_~__retres1~4; [L304-L313] assume !(1 == ~t4_pc~0); [L314] is_transmit4_triggered_~__retres1~4 := 0; [L316] is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; [L635] activate_threads_#t~ret10 := is_transmit4_triggered_#res; [L635] activate_threads_~tmp___3~0 := activate_threads_#t~ret10; [L635] havoc activate_threads_#t~ret10; [L637-L641] assume !(0 != activate_threads_~tmp___3~0); [L545-L549] assume !(1 == ~M_E~0); [L550-L554] assume !(1 == ~T1_E~0); [L555-L559] assume !(1 == ~T2_E~0); [L560-L564] assume !(1 == ~T3_E~0); [L565-L569] assume !(1 == ~T4_E~0); [L570-L574] assume !(1 == ~E_1~0); [L575-L579] assume !(1 == ~E_2~0); [L580-L584] assume !(1 == ~E_3~0); [L585-L589] assume !(1 == ~E_4~0); [L766-L803] assume !false; [L769] start_simulation_~kernel_st~0 := 1; [L770] havoc eval_#t~ret0, eval_#t~nondet1, eval_~tmp_ndt_1~0, eval_#t~nondet2, eval_~tmp_ndt_2~0, eval_#t~nondet3, eval_~tmp_ndt_3~0, eval_#t~nondet4, eval_~tmp_ndt_4~0, eval_#t~nondet5, eval_~tmp_ndt_5~0, eval_~tmp~0; [L397] havoc eval_~tmp~0; [L15] ~m_pc~0 := 0; [L16] ~t1_pc~0 := 0; [L17] ~t2_pc~0 := 0; [L18] ~t3_pc~0 := 0; [L19] ~t4_pc~0 := 0; [L20] ~m_st~0 := 0; [L21] ~t1_st~0 := 0; [L22] ~t2_st~0 := 0; [L23] ~t3_st~0 := 0; [L24] ~t4_st~0 := 0; [L25] ~m_i~0 := 0; [L26] ~t1_i~0 := 0; [L27] ~t2_i~0 := 0; [L28] ~t3_i~0 := 0; [L29] ~t4_i~0 := 0; [L30] ~M_E~0 := 2; [L31] ~T1_E~0 := 2; [L32] ~T2_E~0 := 2; [L33] ~T3_E~0 := 2; [L34] ~T4_E~0 := 2; [L35] ~E_1~0 := 2; [L36] ~E_2~0 := 2; [L37] ~E_3~0 := 2; [L38] ~E_4~0 := 2; [?] havoc main_#res; [?] havoc main_~__retres1~6; [L811] havoc main_~__retres1~6; [L723] ~m_i~0 := 1; [L724] ~t1_i~0 := 1; [L725] ~t2_i~0 := 1; [L726] ~t3_i~0 := 1; [L727] ~t4_i~0 := 1; [L816] havoc start_simulation_#t~ret12, start_simulation_#t~ret13, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1; [L752] havoc start_simulation_~kernel_st~0; [L753] havoc start_simulation_~tmp~3; [L754] havoc start_simulation_~tmp___0~1; [L758] start_simulation_~kernel_st~0 := 0; [L331] COND TRUE 1 == ~m_i~0 [L332] ~m_st~0 := 0; [L336] COND TRUE 1 == ~t1_i~0 [L337] ~t1_st~0 := 0; [L341] COND TRUE 1 == ~t2_i~0 [L342] ~t2_st~0 := 0; [L346] COND TRUE 1 == ~t3_i~0 [L347] ~t3_st~0 := 0; [L351] COND TRUE 1 == ~t4_i~0 [L352] ~t4_st~0 := 0; [L492] COND FALSE !(0 == ~M_E~0) [L497] COND FALSE !(0 == ~T1_E~0) [L502] COND FALSE !(0 == ~T2_E~0) [L507] COND FALSE !(0 == ~T3_E~0) [L512] COND FALSE !(0 == ~T4_E~0) [L517] COND FALSE !(0 == ~E_1~0) [L522] COND FALSE !(0 == ~E_2~0) [L527] COND FALSE !(0 == ~E_3~0) [L532] COND FALSE !(0 == ~E_4~0) [L762] havoc activate_threads_#t~ret6, activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0; [L595] havoc activate_threads_~tmp~1; [L596] havoc activate_threads_~tmp___0~0; [L597] havoc activate_threads_~tmp___1~0; [L598] havoc activate_threads_~tmp___2~0; [L599] havoc activate_threads_~tmp___3~0; [L603] havoc is_master_triggered_#res; [L603] havoc is_master_triggered_~__retres1~0; [L225] havoc is_master_triggered_~__retres1~0; [L228] COND FALSE !(1 == ~m_pc~0) [L238] is_master_triggered_~__retres1~0 := 0; [L240] is_master_triggered_#res := is_master_triggered_~__retres1~0; [L603] activate_threads_#t~ret6 := is_master_triggered_#res; [L603] activate_threads_~tmp~1 := activate_threads_#t~ret6; [L603] havoc activate_threads_#t~ret6; [L605-L609] COND FALSE !(0 != activate_threads_~tmp~1) [L611] havoc is_transmit1_triggered_#res; [L611] havoc is_transmit1_triggered_~__retres1~1; [L244] havoc is_transmit1_triggered_~__retres1~1; [L247] COND FALSE !(1 == ~t1_pc~0) [L257] is_transmit1_triggered_~__retres1~1 := 0; [L259] is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; [L611] activate_threads_#t~ret7 := is_transmit1_triggered_#res; [L611] activate_threads_~tmp___0~0 := activate_threads_#t~ret7; [L611] havoc activate_threads_#t~ret7; [L613-L617] COND FALSE !(0 != activate_threads_~tmp___0~0) [L619] havoc is_transmit2_triggered_#res; [L619] havoc is_transmit2_triggered_~__retres1~2; [L263] havoc is_transmit2_triggered_~__retres1~2; [L266] COND FALSE !(1 == ~t2_pc~0) [L276] is_transmit2_triggered_~__retres1~2 := 0; [L278] is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; [L619] activate_threads_#t~ret8 := is_transmit2_triggered_#res; [L619] activate_threads_~tmp___1~0 := activate_threads_#t~ret8; [L619] havoc activate_threads_#t~ret8; [L621-L625] COND FALSE !(0 != activate_threads_~tmp___1~0) [L627] havoc is_transmit3_triggered_#res; [L627] havoc is_transmit3_triggered_~__retres1~3; [L282] havoc is_transmit3_triggered_~__retres1~3; [L285] COND FALSE !(1 == ~t3_pc~0) [L295] is_transmit3_triggered_~__retres1~3 := 0; [L297] is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; [L627] activate_threads_#t~ret9 := is_transmit3_triggered_#res; [L627] activate_threads_~tmp___2~0 := activate_threads_#t~ret9; [L627] havoc activate_threads_#t~ret9; [L629-L633] COND FALSE !(0 != activate_threads_~tmp___2~0) [L635] havoc is_transmit4_triggered_#res; [L635] havoc is_transmit4_triggered_~__retres1~4; [L301] havoc is_transmit4_triggered_~__retres1~4; [L304] COND FALSE !(1 == ~t4_pc~0) [L314] is_transmit4_triggered_~__retres1~4 := 0; [L316] is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; [L635] activate_threads_#t~ret10 := is_transmit4_triggered_#res; [L635] activate_threads_~tmp___3~0 := activate_threads_#t~ret10; [L635] havoc activate_threads_#t~ret10; [L637-L641] COND FALSE !(0 != activate_threads_~tmp___3~0) [L545] COND FALSE !(1 == ~M_E~0) [L550] COND FALSE !(1 == ~T1_E~0) [L555] COND FALSE !(1 == ~T2_E~0) [L560] COND FALSE !(1 == ~T3_E~0) [L565] COND FALSE !(1 == ~T4_E~0) [L570] COND FALSE !(1 == ~E_1~0) [L575] COND FALSE !(1 == ~E_2~0) [L580] COND FALSE !(1 == ~E_3~0) [L585] COND FALSE !(1 == ~E_4~0) [L766-L803] COND FALSE !(false) [L769] start_simulation_~kernel_st~0 := 1; [L770] havoc eval_#t~ret0, eval_#t~nondet1, eval_~tmp_ndt_1~0, eval_#t~nondet2, eval_~tmp_ndt_2~0, eval_#t~nondet3, eval_~tmp_ndt_3~0, eval_#t~nondet4, eval_~tmp_ndt_4~0, eval_#t~nondet5, eval_~tmp_ndt_5~0, eval_~tmp~0; [L397] havoc eval_~tmp~0; ----- ----- class de.uni_freiburg.informatik.ultimate.boogie.procedureinliner.backtranslation.InlinerBacktranslator [L15] ~m_pc~0 := 0; [L16] ~t1_pc~0 := 0; [L17] ~t2_pc~0 := 0; [L18] ~t3_pc~0 := 0; [L19] ~t4_pc~0 := 0; [L20] ~m_st~0 := 0; [L21] ~t1_st~0 := 0; [L22] ~t2_st~0 := 0; [L23] ~t3_st~0 := 0; [L24] ~t4_st~0 := 0; [L25] ~m_i~0 := 0; [L26] ~t1_i~0 := 0; [L27] ~t2_i~0 := 0; [L28] ~t3_i~0 := 0; [L29] ~t4_i~0 := 0; [L30] ~M_E~0 := 2; [L31] ~T1_E~0 := 2; [L32] ~T2_E~0 := 2; [L33] ~T3_E~0 := 2; [L34] ~T4_E~0 := 2; [L35] ~E_1~0 := 2; [L36] ~E_2~0 := 2; [L37] ~E_3~0 := 2; [L38] ~E_4~0 := 2; [?] havoc main_#res; [?] havoc main_~__retres1~6; [L811] havoc main_~__retres1~6; [L723] ~m_i~0 := 1; [L724] ~t1_i~0 := 1; [L725] ~t2_i~0 := 1; [L726] ~t3_i~0 := 1; [L727] ~t4_i~0 := 1; [L816] havoc start_simulation_#t~ret12, start_simulation_#t~ret13, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1; [L752] havoc start_simulation_~kernel_st~0; [L753] havoc start_simulation_~tmp~3; [L754] havoc start_simulation_~tmp___0~1; [L758] start_simulation_~kernel_st~0 := 0; [L331] COND TRUE 1 == ~m_i~0 [L332] ~m_st~0 := 0; [L336] COND TRUE 1 == ~t1_i~0 [L337] ~t1_st~0 := 0; [L341] COND TRUE 1 == ~t2_i~0 [L342] ~t2_st~0 := 0; [L346] COND TRUE 1 == ~t3_i~0 [L347] ~t3_st~0 := 0; [L351] COND TRUE 1 == ~t4_i~0 [L352] ~t4_st~0 := 0; [L492] COND FALSE !(0 == ~M_E~0) [L497] COND FALSE !(0 == ~T1_E~0) [L502] COND FALSE !(0 == ~T2_E~0) [L507] COND FALSE !(0 == ~T3_E~0) [L512] COND FALSE !(0 == ~T4_E~0) [L517] COND FALSE !(0 == ~E_1~0) [L522] COND FALSE !(0 == ~E_2~0) [L527] COND FALSE !(0 == ~E_3~0) [L532] COND FALSE !(0 == ~E_4~0) [L762] havoc activate_threads_#t~ret6, activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0; [L595] havoc activate_threads_~tmp~1; [L596] havoc activate_threads_~tmp___0~0; [L597] havoc activate_threads_~tmp___1~0; [L598] havoc activate_threads_~tmp___2~0; [L599] havoc activate_threads_~tmp___3~0; [L603] havoc is_master_triggered_#res; [L603] havoc is_master_triggered_~__retres1~0; [L225] havoc is_master_triggered_~__retres1~0; [L228] COND FALSE !(1 == ~m_pc~0) [L238] is_master_triggered_~__retres1~0 := 0; [L240] is_master_triggered_#res := is_master_triggered_~__retres1~0; [L603] activate_threads_#t~ret6 := is_master_triggered_#res; [L603] activate_threads_~tmp~1 := activate_threads_#t~ret6; [L603] havoc activate_threads_#t~ret6; [L605-L609] COND FALSE !(0 != activate_threads_~tmp~1) [L611] havoc is_transmit1_triggered_#res; [L611] havoc is_transmit1_triggered_~__retres1~1; [L244] havoc is_transmit1_triggered_~__retres1~1; [L247] COND FALSE !(1 == ~t1_pc~0) [L257] is_transmit1_triggered_~__retres1~1 := 0; [L259] is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; [L611] activate_threads_#t~ret7 := is_transmit1_triggered_#res; [L611] activate_threads_~tmp___0~0 := activate_threads_#t~ret7; [L611] havoc activate_threads_#t~ret7; [L613-L617] COND FALSE !(0 != activate_threads_~tmp___0~0) [L619] havoc is_transmit2_triggered_#res; [L619] havoc is_transmit2_triggered_~__retres1~2; [L263] havoc is_transmit2_triggered_~__retres1~2; [L266] COND FALSE !(1 == ~t2_pc~0) [L276] is_transmit2_triggered_~__retres1~2 := 0; [L278] is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; [L619] activate_threads_#t~ret8 := is_transmit2_triggered_#res; [L619] activate_threads_~tmp___1~0 := activate_threads_#t~ret8; [L619] havoc activate_threads_#t~ret8; [L621-L625] COND FALSE !(0 != activate_threads_~tmp___1~0) [L627] havoc is_transmit3_triggered_#res; [L627] havoc is_transmit3_triggered_~__retres1~3; [L282] havoc is_transmit3_triggered_~__retres1~3; [L285] COND FALSE !(1 == ~t3_pc~0) [L295] is_transmit3_triggered_~__retres1~3 := 0; [L297] is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; [L627] activate_threads_#t~ret9 := is_transmit3_triggered_#res; [L627] activate_threads_~tmp___2~0 := activate_threads_#t~ret9; [L627] havoc activate_threads_#t~ret9; [L629-L633] COND FALSE !(0 != activate_threads_~tmp___2~0) [L635] havoc is_transmit4_triggered_#res; [L635] havoc is_transmit4_triggered_~__retres1~4; [L301] havoc is_transmit4_triggered_~__retres1~4; [L304] COND FALSE !(1 == ~t4_pc~0) [L314] is_transmit4_triggered_~__retres1~4 := 0; [L316] is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; [L635] activate_threads_#t~ret10 := is_transmit4_triggered_#res; [L635] activate_threads_~tmp___3~0 := activate_threads_#t~ret10; [L635] havoc activate_threads_#t~ret10; [L637-L641] COND FALSE !(0 != activate_threads_~tmp___3~0) [L545] COND FALSE !(1 == ~M_E~0) [L550] COND FALSE !(1 == ~T1_E~0) [L555] COND FALSE !(1 == ~T2_E~0) [L560] COND FALSE !(1 == ~T3_E~0) [L565] COND FALSE !(1 == ~T4_E~0) [L570] COND FALSE !(1 == ~E_1~0) [L575] COND FALSE !(1 == ~E_2~0) [L580] COND FALSE !(1 == ~E_3~0) [L585] COND FALSE !(1 == ~E_4~0) [L766-L803] COND FALSE !(false) [L769] start_simulation_~kernel_st~0 := 1; [L770] havoc eval_#t~ret0, eval_#t~nondet1, eval_~tmp_ndt_1~0, eval_#t~nondet2, eval_~tmp_ndt_2~0, eval_#t~nondet3, eval_~tmp_ndt_3~0, eval_#t~nondet4, eval_~tmp_ndt_4~0, eval_#t~nondet5, eval_~tmp_ndt_5~0, eval_~tmp~0; [L397] havoc eval_~tmp~0; [L15] ~m_pc~0 := 0; [L16] ~t1_pc~0 := 0; [L17] ~t2_pc~0 := 0; [L18] ~t3_pc~0 := 0; [L19] ~t4_pc~0 := 0; [L20] ~m_st~0 := 0; [L21] ~t1_st~0 := 0; [L22] ~t2_st~0 := 0; [L23] ~t3_st~0 := 0; [L24] ~t4_st~0 := 0; [L25] ~m_i~0 := 0; [L26] ~t1_i~0 := 0; [L27] ~t2_i~0 := 0; [L28] ~t3_i~0 := 0; [L29] ~t4_i~0 := 0; [L30] ~M_E~0 := 2; [L31] ~T1_E~0 := 2; [L32] ~T2_E~0 := 2; [L33] ~T3_E~0 := 2; [L34] ~T4_E~0 := 2; [L35] ~E_1~0 := 2; [L36] ~E_2~0 := 2; [L37] ~E_3~0 := 2; [L38] ~E_4~0 := 2; [L811] havoc ~__retres1~6; [L723] ~m_i~0 := 1; [L724] ~t1_i~0 := 1; [L725] ~t2_i~0 := 1; [L726] ~t3_i~0 := 1; [L727] ~t4_i~0 := 1; [L752] havoc ~kernel_st~0; [L753] havoc ~tmp~3; [L754] havoc ~tmp___0~1; [L758] ~kernel_st~0 := 0; [L331] COND TRUE 1 == ~m_i~0 [L332] ~m_st~0 := 0; [L336] COND TRUE 1 == ~t1_i~0 [L337] ~t1_st~0 := 0; [L341] COND TRUE 1 == ~t2_i~0 [L342] ~t2_st~0 := 0; [L346] COND TRUE 1 == ~t3_i~0 [L347] ~t3_st~0 := 0; [L351] COND TRUE 1 == ~t4_i~0 [L352] ~t4_st~0 := 0; [L492] COND FALSE !(0 == ~M_E~0) [L497] COND FALSE !(0 == ~T1_E~0) [L502] COND FALSE !(0 == ~T2_E~0) [L507] COND FALSE !(0 == ~T3_E~0) [L512] COND FALSE !(0 == ~T4_E~0) [L517] COND FALSE !(0 == ~E_1~0) [L522] COND FALSE !(0 == ~E_2~0) [L527] COND FALSE !(0 == ~E_3~0) [L532] COND FALSE !(0 == ~E_4~0) [L595] havoc ~tmp~1; [L596] havoc ~tmp___0~0; [L597] havoc ~tmp___1~0; [L598] havoc ~tmp___2~0; [L599] havoc ~tmp___3~0; [L225] havoc ~__retres1~0; [L228] COND FALSE !(1 == ~m_pc~0) [L238] ~__retres1~0 := 0; [L240] #res := ~__retres1~0; [L603] ~tmp~1 := #t~ret6; [L603] havoc #t~ret6; [L605-L609] COND FALSE !(0 != ~tmp~1) [L244] havoc ~__retres1~1; [L247] COND FALSE !(1 == ~t1_pc~0) [L257] ~__retres1~1 := 0; [L259] #res := ~__retres1~1; [L611] ~tmp___0~0 := #t~ret7; [L611] havoc #t~ret7; [L613-L617] COND FALSE !(0 != ~tmp___0~0) [L263] havoc ~__retres1~2; [L266] COND FALSE !(1 == ~t2_pc~0) [L276] ~__retres1~2 := 0; [L278] #res := ~__retres1~2; [L619] ~tmp___1~0 := #t~ret8; [L619] havoc #t~ret8; [L621-L625] COND FALSE !(0 != ~tmp___1~0) [L282] havoc ~__retres1~3; [L285] COND FALSE !(1 == ~t3_pc~0) [L295] ~__retres1~3 := 0; [L297] #res := ~__retres1~3; [L627] ~tmp___2~0 := #t~ret9; [L627] havoc #t~ret9; [L629-L633] COND FALSE !(0 != ~tmp___2~0) [L301] havoc ~__retres1~4; [L304] COND FALSE !(1 == ~t4_pc~0) [L314] ~__retres1~4 := 0; [L316] #res := ~__retres1~4; [L635] ~tmp___3~0 := #t~ret10; [L635] havoc #t~ret10; [L637-L641] COND FALSE !(0 != ~tmp___3~0) [L545] COND FALSE !(1 == ~M_E~0) [L550] COND FALSE !(1 == ~T1_E~0) [L555] COND FALSE !(1 == ~T2_E~0) [L560] COND FALSE !(1 == ~T3_E~0) [L565] COND FALSE !(1 == ~T4_E~0) [L570] COND FALSE !(1 == ~E_1~0) [L575] COND FALSE !(1 == ~E_2~0) [L580] COND FALSE !(1 == ~E_3~0) [L585] COND FALSE !(1 == ~E_4~0) [L766-L803] COND FALSE !(false) [L769] ~kernel_st~0 := 1; [L397] havoc ~tmp~0; ----- ----- class de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.CACSL2BoogieBacktranslator [L15] ~m_pc~0 := 0; [L16] ~t1_pc~0 := 0; [L17] ~t2_pc~0 := 0; [L18] ~t3_pc~0 := 0; [L19] ~t4_pc~0 := 0; [L20] ~m_st~0 := 0; [L21] ~t1_st~0 := 0; [L22] ~t2_st~0 := 0; [L23] ~t3_st~0 := 0; [L24] ~t4_st~0 := 0; [L25] ~m_i~0 := 0; [L26] ~t1_i~0 := 0; [L27] ~t2_i~0 := 0; [L28] ~t3_i~0 := 0; [L29] ~t4_i~0 := 0; [L30] ~M_E~0 := 2; [L31] ~T1_E~0 := 2; [L32] ~T2_E~0 := 2; [L33] ~T3_E~0 := 2; [L34] ~T4_E~0 := 2; [L35] ~E_1~0 := 2; [L36] ~E_2~0 := 2; [L37] ~E_3~0 := 2; [L38] ~E_4~0 := 2; [L811] havoc ~__retres1~6; [L723] ~m_i~0 := 1; [L724] ~t1_i~0 := 1; [L725] ~t2_i~0 := 1; [L726] ~t3_i~0 := 1; [L727] ~t4_i~0 := 1; [L752] havoc ~kernel_st~0; [L753] havoc ~tmp~3; [L754] havoc ~tmp___0~1; [L758] ~kernel_st~0 := 0; [L331] COND TRUE 1 == ~m_i~0 [L332] ~m_st~0 := 0; [L336] COND TRUE 1 == ~t1_i~0 [L337] ~t1_st~0 := 0; [L341] COND TRUE 1 == ~t2_i~0 [L342] ~t2_st~0 := 0; [L346] COND TRUE 1 == ~t3_i~0 [L347] ~t3_st~0 := 0; [L351] COND TRUE 1 == ~t4_i~0 [L352] ~t4_st~0 := 0; [L492] COND FALSE !(0 == ~M_E~0) [L497] COND FALSE !(0 == ~T1_E~0) [L502] COND FALSE !(0 == ~T2_E~0) [L507] COND FALSE !(0 == ~T3_E~0) [L512] COND FALSE !(0 == ~T4_E~0) [L517] COND FALSE !(0 == ~E_1~0) [L522] COND FALSE !(0 == ~E_2~0) [L527] COND FALSE !(0 == ~E_3~0) [L532] COND FALSE !(0 == ~E_4~0) [L595] havoc ~tmp~1; [L596] havoc ~tmp___0~0; [L597] havoc ~tmp___1~0; [L598] havoc ~tmp___2~0; [L599] havoc ~tmp___3~0; [L225] havoc ~__retres1~0; [L228] COND FALSE !(1 == ~m_pc~0) [L238] ~__retres1~0 := 0; [L240] #res := ~__retres1~0; [L603] ~tmp~1 := #t~ret6; [L603] havoc #t~ret6; [L605-L609] COND FALSE !(0 != ~tmp~1) [L244] havoc ~__retres1~1; [L247] COND FALSE !(1 == ~t1_pc~0) [L257] ~__retres1~1 := 0; [L259] #res := ~__retres1~1; [L611] ~tmp___0~0 := #t~ret7; [L611] havoc #t~ret7; [L613-L617] COND FALSE !(0 != ~tmp___0~0) [L263] havoc ~__retres1~2; [L266] COND FALSE !(1 == ~t2_pc~0) [L276] ~__retres1~2 := 0; [L278] #res := ~__retres1~2; [L619] ~tmp___1~0 := #t~ret8; [L619] havoc #t~ret8; [L621-L625] COND FALSE !(0 != ~tmp___1~0) [L282] havoc ~__retres1~3; [L285] COND FALSE !(1 == ~t3_pc~0) [L295] ~__retres1~3 := 0; [L297] #res := ~__retres1~3; [L627] ~tmp___2~0 := #t~ret9; [L627] havoc #t~ret9; [L629-L633] COND FALSE !(0 != ~tmp___2~0) [L301] havoc ~__retres1~4; [L304] COND FALSE !(1 == ~t4_pc~0) [L314] ~__retres1~4 := 0; [L316] #res := ~__retres1~4; [L635] ~tmp___3~0 := #t~ret10; [L635] havoc #t~ret10; [L637-L641] COND FALSE !(0 != ~tmp___3~0) [L545] COND FALSE !(1 == ~M_E~0) [L550] COND FALSE !(1 == ~T1_E~0) [L555] COND FALSE !(1 == ~T2_E~0) [L560] COND FALSE !(1 == ~T3_E~0) [L565] COND FALSE !(1 == ~T4_E~0) [L570] COND FALSE !(1 == ~E_1~0) [L575] COND FALSE !(1 == ~E_2~0) [L580] COND FALSE !(1 == ~E_3~0) [L585] COND FALSE !(1 == ~E_4~0) [L766-L803] COND FALSE !(false) [L769] ~kernel_st~0 := 1; [L397] havoc ~tmp~0; [L15] int m_pc = 0; [L16] int t1_pc = 0; [L17] int t2_pc = 0; [L18] int t3_pc = 0; [L19] int t4_pc = 0; [L20] int m_st ; [L21] int t1_st ; [L22] int t2_st ; [L23] int t3_st ; [L24] int t4_st ; [L25] int m_i ; [L26] int t1_i ; [L27] int t2_i ; [L28] int t3_i ; [L29] int t4_i ; [L30] int M_E = 2; [L31] int T1_E = 2; [L32] int T2_E = 2; [L33] int T3_E = 2; [L34] int T4_E = 2; [L35] int E_1 = 2; [L36] int E_2 = 2; [L37] int E_3 = 2; [L38] int E_4 = 2; [L811] int __retres1 ; [L723] m_i = 1 [L724] t1_i = 1 [L725] t2_i = 1 [L726] t3_i = 1 [L727] t4_i = 1 [L752] int kernel_st ; [L753] int tmp ; [L754] int tmp___0 ; [L758] kernel_st = 0 [L331] COND TRUE m_i == 1 [L332] m_st = 0 [L336] COND TRUE t1_i == 1 [L337] t1_st = 0 [L341] COND TRUE t2_i == 1 [L342] t2_st = 0 [L346] COND TRUE t3_i == 1 [L347] t3_st = 0 [L351] COND TRUE t4_i == 1 [L352] t4_st = 0 [L492] COND FALSE !(M_E == 0) [L497] COND FALSE !(T1_E == 0) [L502] COND FALSE !(T2_E == 0) [L507] COND FALSE !(T3_E == 0) [L512] COND FALSE !(T4_E == 0) [L517] COND FALSE !(E_1 == 0) [L522] COND FALSE !(E_2 == 0) [L527] COND FALSE !(E_3 == 0) [L532] COND FALSE !(E_4 == 0) [L595] int tmp ; [L596] int tmp___0 ; [L597] int tmp___1 ; [L598] int tmp___2 ; [L599] int tmp___3 ; [L225] int __retres1 ; [L228] COND FALSE !(m_pc == 1) [L238] __retres1 = 0 [L240] return (__retres1); [L603] tmp = is_master_triggered() [L605] COND FALSE !(\read(tmp)) [L244] int __retres1 ; [L247] COND FALSE !(t1_pc == 1) [L257] __retres1 = 0 [L259] return (__retres1); [L611] tmp___0 = is_transmit1_triggered() [L613] COND FALSE !(\read(tmp___0)) [L263] int __retres1 ; [L266] COND FALSE !(t2_pc == 1) [L276] __retres1 = 0 [L278] return (__retres1); [L619] tmp___1 = is_transmit2_triggered() [L621] COND FALSE !(\read(tmp___1)) [L282] int __retres1 ; [L285] COND FALSE !(t3_pc == 1) [L295] __retres1 = 0 [L297] return (__retres1); [L627] tmp___2 = is_transmit3_triggered() [L629] COND FALSE !(\read(tmp___2)) [L301] int __retres1 ; [L304] COND FALSE !(t4_pc == 1) [L314] __retres1 = 0 [L316] return (__retres1); [L635] tmp___3 = is_transmit4_triggered() [L637] COND FALSE !(\read(tmp___3)) [L545] COND FALSE !(M_E == 1) [L550] COND FALSE !(T1_E == 1) [L555] COND FALSE !(T2_E == 1) [L560] COND FALSE !(T3_E == 1) [L565] COND FALSE !(T4_E == 1) [L570] COND FALSE !(E_1 == 1) [L575] COND FALSE !(E_2 == 1) [L580] COND FALSE !(E_3 == 1) [L585] COND FALSE !(E_4 == 1) [L766] COND TRUE 1 [L769] kernel_st = 1 [L397] int tmp ; ----- ----- class de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder.RCFGBacktranslator [?] assume !false; [?] havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; [?] assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; [?] exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; [?] eval_#t~ret0 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret0;havoc eval_#t~ret0; [?] assume 0 != eval_~tmp~0; [?] assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0;eval_~tmp_ndt_1~0 := eval_#t~nondet1;havoc eval_#t~nondet1; [?] assume !(0 != eval_~tmp_ndt_1~0); [?] assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0;eval_~tmp_ndt_2~0 := eval_#t~nondet2;havoc eval_#t~nondet2; [?] assume !(0 != eval_~tmp_ndt_2~0); [?] assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0;eval_~tmp_ndt_3~0 := eval_#t~nondet3;havoc eval_#t~nondet3; [?] assume !(0 != eval_~tmp_ndt_3~0); [?] assume 0 == ~t3_st~0;havoc eval_~tmp_ndt_4~0;eval_~tmp_ndt_4~0 := eval_#t~nondet4;havoc eval_#t~nondet4; [?] assume !(0 != eval_~tmp_ndt_4~0); [?] assume 0 == ~t4_st~0;havoc eval_~tmp_ndt_5~0;eval_~tmp_ndt_5~0 := eval_#t~nondet5;havoc eval_#t~nondet5; [?] assume !(0 != eval_~tmp_ndt_5~0); [L401-L481] assume !false; [L404] havoc exists_runnable_thread_#res; [L404] havoc exists_runnable_thread_~__retres1~5; [L361] havoc exists_runnable_thread_~__retres1~5; [L364-L389] assume 0 == ~m_st~0; [L365] exists_runnable_thread_~__retres1~5 := 1; [L392] exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; [L404] eval_#t~ret0 := exists_runnable_thread_#res; [L404] eval_~tmp~0 := eval_#t~ret0; [L404] havoc eval_#t~ret0; [L406-L410] assume 0 != eval_~tmp~0; [L411-L424] assume 0 == ~m_st~0; [L412] havoc eval_~tmp_ndt_1~0; [L413] eval_~tmp_ndt_1~0 := eval_#t~nondet1; [L413] havoc eval_#t~nondet1; [L414-L421] assume !(0 != eval_~tmp_ndt_1~0); [L425-L438] assume 0 == ~t1_st~0; [L426] havoc eval_~tmp_ndt_2~0; [L427] eval_~tmp_ndt_2~0 := eval_#t~nondet2; [L427] havoc eval_#t~nondet2; [L428-L435] assume !(0 != eval_~tmp_ndt_2~0); [L439-L452] assume 0 == ~t2_st~0; [L440] havoc eval_~tmp_ndt_3~0; [L441] eval_~tmp_ndt_3~0 := eval_#t~nondet3; [L441] havoc eval_#t~nondet3; [L442-L449] assume !(0 != eval_~tmp_ndt_3~0); [L453-L466] assume 0 == ~t3_st~0; [L454] havoc eval_~tmp_ndt_4~0; [L455] eval_~tmp_ndt_4~0 := eval_#t~nondet4; [L455] havoc eval_#t~nondet4; [L456-L463] assume !(0 != eval_~tmp_ndt_4~0); [L467-L480] assume 0 == ~t4_st~0; [L468] havoc eval_~tmp_ndt_5~0; [L469] eval_~tmp_ndt_5~0 := eval_#t~nondet5; [L469] havoc eval_#t~nondet5; [L470-L477] assume !(0 != eval_~tmp_ndt_5~0); ----- ----- class de.uni_freiburg.informatik.ultimate.boogie.preprocessor.BoogiePreprocessorBacktranslator [L401-L481] assume !false; [L404] havoc exists_runnable_thread_#res; [L404] havoc exists_runnable_thread_~__retres1~5; [L361] havoc exists_runnable_thread_~__retres1~5; [L364-L389] assume 0 == ~m_st~0; [L365] exists_runnable_thread_~__retres1~5 := 1; [L392] exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; [L404] eval_#t~ret0 := exists_runnable_thread_#res; [L404] eval_~tmp~0 := eval_#t~ret0; [L404] havoc eval_#t~ret0; [L406-L410] assume 0 != eval_~tmp~0; [L411-L424] assume 0 == ~m_st~0; [L412] havoc eval_~tmp_ndt_1~0; [L413] eval_~tmp_ndt_1~0 := eval_#t~nondet1; [L413] havoc eval_#t~nondet1; [L414-L421] assume !(0 != eval_~tmp_ndt_1~0); [L425-L438] assume 0 == ~t1_st~0; [L426] havoc eval_~tmp_ndt_2~0; [L427] eval_~tmp_ndt_2~0 := eval_#t~nondet2; [L427] havoc eval_#t~nondet2; [L428-L435] assume !(0 != eval_~tmp_ndt_2~0); [L439-L452] assume 0 == ~t2_st~0; [L440] havoc eval_~tmp_ndt_3~0; [L441] eval_~tmp_ndt_3~0 := eval_#t~nondet3; [L441] havoc eval_#t~nondet3; [L442-L449] assume !(0 != eval_~tmp_ndt_3~0); [L453-L466] assume 0 == ~t3_st~0; [L454] havoc eval_~tmp_ndt_4~0; [L455] eval_~tmp_ndt_4~0 := eval_#t~nondet4; [L455] havoc eval_#t~nondet4; [L456-L463] assume !(0 != eval_~tmp_ndt_4~0); [L467-L480] assume 0 == ~t4_st~0; [L468] havoc eval_~tmp_ndt_5~0; [L469] eval_~tmp_ndt_5~0 := eval_#t~nondet5; [L469] havoc eval_#t~nondet5; [L470-L477] assume !(0 != eval_~tmp_ndt_5~0); [L401-L481] COND FALSE !(false) [L404] havoc exists_runnable_thread_#res; [L404] havoc exists_runnable_thread_~__retres1~5; [L361] havoc exists_runnable_thread_~__retres1~5; [L364] COND TRUE 0 == ~m_st~0 [L365] exists_runnable_thread_~__retres1~5 := 1; [L392] exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; [L404] eval_#t~ret0 := exists_runnable_thread_#res; [L404] eval_~tmp~0 := eval_#t~ret0; [L404] havoc eval_#t~ret0; [L406-L410] COND TRUE 0 != eval_~tmp~0 [L411] COND TRUE 0 == ~m_st~0 [L412] havoc eval_~tmp_ndt_1~0; [L413] eval_~tmp_ndt_1~0 := eval_#t~nondet1; [L413] havoc eval_#t~nondet1; [L414-L421] COND FALSE !(0 != eval_~tmp_ndt_1~0) [L425] COND TRUE 0 == ~t1_st~0 [L426] havoc eval_~tmp_ndt_2~0; [L427] eval_~tmp_ndt_2~0 := eval_#t~nondet2; [L427] havoc eval_#t~nondet2; [L428-L435] COND FALSE !(0 != eval_~tmp_ndt_2~0) [L439] COND TRUE 0 == ~t2_st~0 [L440] havoc eval_~tmp_ndt_3~0; [L441] eval_~tmp_ndt_3~0 := eval_#t~nondet3; [L441] havoc eval_#t~nondet3; [L442-L449] COND FALSE !(0 != eval_~tmp_ndt_3~0) [L453] COND TRUE 0 == ~t3_st~0 [L454] havoc eval_~tmp_ndt_4~0; [L455] eval_~tmp_ndt_4~0 := eval_#t~nondet4; [L455] havoc eval_#t~nondet4; [L456-L463] COND FALSE !(0 != eval_~tmp_ndt_4~0) [L467] COND TRUE 0 == ~t4_st~0 [L468] havoc eval_~tmp_ndt_5~0; [L469] eval_~tmp_ndt_5~0 := eval_#t~nondet5; [L469] havoc eval_#t~nondet5; [L470-L477] COND FALSE !(0 != eval_~tmp_ndt_5~0) ----- ----- class de.uni_freiburg.informatik.ultimate.boogie.procedureinliner.backtranslation.InlinerBacktranslator [L401-L481] COND FALSE !(false) [L404] havoc exists_runnable_thread_#res; [L404] havoc exists_runnable_thread_~__retres1~5; [L361] havoc exists_runnable_thread_~__retres1~5; [L364] COND TRUE 0 == ~m_st~0 [L365] exists_runnable_thread_~__retres1~5 := 1; [L392] exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; [L404] eval_#t~ret0 := exists_runnable_thread_#res; [L404] eval_~tmp~0 := eval_#t~ret0; [L404] havoc eval_#t~ret0; [L406-L410] COND TRUE 0 != eval_~tmp~0 [L411] COND TRUE 0 == ~m_st~0 [L412] havoc eval_~tmp_ndt_1~0; [L413] eval_~tmp_ndt_1~0 := eval_#t~nondet1; [L413] havoc eval_#t~nondet1; [L414-L421] COND FALSE !(0 != eval_~tmp_ndt_1~0) [L425] COND TRUE 0 == ~t1_st~0 [L426] havoc eval_~tmp_ndt_2~0; [L427] eval_~tmp_ndt_2~0 := eval_#t~nondet2; [L427] havoc eval_#t~nondet2; [L428-L435] COND FALSE !(0 != eval_~tmp_ndt_2~0) [L439] COND TRUE 0 == ~t2_st~0 [L440] havoc eval_~tmp_ndt_3~0; [L441] eval_~tmp_ndt_3~0 := eval_#t~nondet3; [L441] havoc eval_#t~nondet3; [L442-L449] COND FALSE !(0 != eval_~tmp_ndt_3~0) [L453] COND TRUE 0 == ~t3_st~0 [L454] havoc eval_~tmp_ndt_4~0; [L455] eval_~tmp_ndt_4~0 := eval_#t~nondet4; [L455] havoc eval_#t~nondet4; [L456-L463] COND FALSE !(0 != eval_~tmp_ndt_4~0) [L467] COND TRUE 0 == ~t4_st~0 [L468] havoc eval_~tmp_ndt_5~0; [L469] eval_~tmp_ndt_5~0 := eval_#t~nondet5; [L469] havoc eval_#t~nondet5; [L470-L477] COND FALSE !(0 != eval_~tmp_ndt_5~0) [L401-L481] COND FALSE !(false) [L361] havoc ~__retres1~5; [L364] COND TRUE 0 == ~m_st~0 [L365] ~__retres1~5 := 1; [L392] #res := ~__retres1~5; [L404] ~tmp~0 := #t~ret0; [L404] havoc #t~ret0; [L406-L410] COND TRUE 0 != ~tmp~0 [L411] COND TRUE 0 == ~m_st~0 [L412] havoc ~tmp_ndt_1~0; [L413] ~tmp_ndt_1~0 := #t~nondet1; [L413] havoc #t~nondet1; [L414-L421] COND FALSE !(0 != ~tmp_ndt_1~0) [L425] COND TRUE 0 == ~t1_st~0 [L426] havoc ~tmp_ndt_2~0; [L427] ~tmp_ndt_2~0 := #t~nondet2; [L427] havoc #t~nondet2; [L428-L435] COND FALSE !(0 != ~tmp_ndt_2~0) [L439] COND TRUE 0 == ~t2_st~0 [L440] havoc ~tmp_ndt_3~0; [L441] ~tmp_ndt_3~0 := #t~nondet3; [L441] havoc #t~nondet3; [L442-L449] COND FALSE !(0 != ~tmp_ndt_3~0) [L453] COND TRUE 0 == ~t3_st~0 [L454] havoc ~tmp_ndt_4~0; [L455] ~tmp_ndt_4~0 := #t~nondet4; [L455] havoc #t~nondet4; [L456-L463] COND FALSE !(0 != ~tmp_ndt_4~0) [L467] COND TRUE 0 == ~t4_st~0 [L468] havoc ~tmp_ndt_5~0; [L469] ~tmp_ndt_5~0 := #t~nondet5; [L469] havoc #t~nondet5; [L470-L477] COND FALSE !(0 != ~tmp_ndt_5~0) ----- ----- class de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.CACSL2BoogieBacktranslator [L401-L481] COND FALSE !(false) [L361] havoc ~__retres1~5; [L364] COND TRUE 0 == ~m_st~0 [L365] ~__retres1~5 := 1; [L392] #res := ~__retres1~5; [L404] ~tmp~0 := #t~ret0; [L404] havoc #t~ret0; [L406-L410] COND TRUE 0 != ~tmp~0 [L411] COND TRUE 0 == ~m_st~0 [L412] havoc ~tmp_ndt_1~0; [L413] ~tmp_ndt_1~0 := #t~nondet1; [L413] havoc #t~nondet1; [L414-L421] COND FALSE !(0 != ~tmp_ndt_1~0) [L425] COND TRUE 0 == ~t1_st~0 [L426] havoc ~tmp_ndt_2~0; [L427] ~tmp_ndt_2~0 := #t~nondet2; [L427] havoc #t~nondet2; [L428-L435] COND FALSE !(0 != ~tmp_ndt_2~0) [L439] COND TRUE 0 == ~t2_st~0 [L440] havoc ~tmp_ndt_3~0; [L441] ~tmp_ndt_3~0 := #t~nondet3; [L441] havoc #t~nondet3; [L442-L449] COND FALSE !(0 != ~tmp_ndt_3~0) [L453] COND TRUE 0 == ~t3_st~0 [L454] havoc ~tmp_ndt_4~0; [L455] ~tmp_ndt_4~0 := #t~nondet4; [L455] havoc #t~nondet4; [L456-L463] COND FALSE !(0 != ~tmp_ndt_4~0) [L467] COND TRUE 0 == ~t4_st~0 [L468] havoc ~tmp_ndt_5~0; [L469] ~tmp_ndt_5~0 := #t~nondet5; [L469] havoc #t~nondet5; [L470-L477] COND FALSE !(0 != ~tmp_ndt_5~0) [L401] COND TRUE 1 [L361] int __retres1 ; [L364] COND TRUE m_st == 0 [L365] __retres1 = 1 [L392] return (__retres1); [L404] tmp = exists_runnable_thread() [L406] COND TRUE \read(tmp) [L411] COND TRUE m_st == 0 [L412] int tmp_ndt_1; [L413] tmp_ndt_1 = __VERIFIER_nondet_int() [L414] COND FALSE !(\read(tmp_ndt_1)) [L425] COND TRUE t1_st == 0 [L426] int tmp_ndt_2; [L427] tmp_ndt_2 = __VERIFIER_nondet_int() [L428] COND FALSE !(\read(tmp_ndt_2)) [L439] COND TRUE t2_st == 0 [L440] int tmp_ndt_3; [L441] tmp_ndt_3 = __VERIFIER_nondet_int() [L442] COND FALSE !(\read(tmp_ndt_3)) [L453] COND TRUE t3_st == 0 [L454] int tmp_ndt_4; [L455] tmp_ndt_4 = __VERIFIER_nondet_int() [L456] COND FALSE !(\read(tmp_ndt_4)) [L467] COND TRUE t4_st == 0 [L468] int tmp_ndt_5; [L469] tmp_ndt_5 = __VERIFIER_nondet_int() [L470] COND FALSE !(\read(tmp_ndt_5)) ----- [2018-11-23 12:43:45,578 INFO L145 WitnessManager]: Wrote witness to /tmp/vcloud-vcloud-master/worker/working_dir_4e85c2a5-7fb1-4118-9476-ba8baa068460/bin-2019/uautomizer/witness.graphml [2018-11-23 12:43:45,579 INFO L132 PluginConnector]: ------------------------ END Witness Printer---------------------------- [2018-11-23 12:43:45,579 INFO L168 Benchmark]: Toolchain (without parser) took 9529.70 ms. Allocated memory was 1.0 GB in the beginning and 1.4 GB in the end (delta: 398.5 MB). Free memory was 953.7 MB in the beginning and 842.7 MB in the end (delta: 111.1 MB). Peak memory consumption was 509.5 MB. Max. memory is 11.5 GB. [2018-11-23 12:43:45,580 INFO L168 Benchmark]: CDTParser took 0.11 ms. Allocated memory is still 1.0 GB. Free memory is still 980.1 MB. There was no memory consumed. Max. memory is 11.5 GB. [2018-11-23 12:43:45,580 INFO L168 Benchmark]: CACSL2BoogieTranslator took 267.83 ms. Allocated memory is still 1.0 GB. Free memory was 953.7 MB in the beginning and 935.0 MB in the end (delta: 18.8 MB). Peak memory consumption was 18.8 MB. Max. memory is 11.5 GB. [2018-11-23 12:43:45,580 INFO L168 Benchmark]: Boogie Procedure Inliner took 82.63 ms. Allocated memory was 1.0 GB in the beginning and 1.2 GB in the end (delta: 132.6 MB). Free memory was 935.0 MB in the beginning and 1.1 GB in the end (delta: -192.4 MB). Peak memory consumption was 14.8 MB. Max. memory is 11.5 GB. [2018-11-23 12:43:45,581 INFO L168 Benchmark]: Boogie Preprocessor took 46.28 ms. Allocated memory is still 1.2 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 6.7 MB). Peak memory consumption was 6.7 MB. Max. memory is 11.5 GB. [2018-11-23 12:43:45,581 INFO L168 Benchmark]: RCFGBuilder took 776.40 ms. Allocated memory is still 1.2 GB. Free memory was 1.1 GB in the beginning and 1.0 GB in the end (delta: 84.5 MB). Peak memory consumption was 84.5 MB. Max. memory is 11.5 GB. [2018-11-23 12:43:45,581 INFO L168 Benchmark]: BuchiAutomizer took 7642.07 ms. Allocated memory was 1.2 GB in the beginning and 1.4 GB in the end (delta: 265.8 MB). Free memory was 1.0 GB in the beginning and 865.0 MB in the end (delta: 171.2 MB). Peak memory consumption was 437.0 MB. Max. memory is 11.5 GB. [2018-11-23 12:43:45,582 INFO L168 Benchmark]: Witness Printer took 711.23 ms. Allocated memory is still 1.4 GB. Free memory was 865.0 MB in the beginning and 842.7 MB in the end (delta: 22.3 MB). Peak memory consumption was 22.3 MB. Max. memory is 11.5 GB. [2018-11-23 12:43:45,584 INFO L336 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.11 ms. Allocated memory is still 1.0 GB. Free memory is still 980.1 MB. There was no memory consumed. Max. memory is 11.5 GB. * CACSL2BoogieTranslator took 267.83 ms. Allocated memory is still 1.0 GB. Free memory was 953.7 MB in the beginning and 935.0 MB in the end (delta: 18.8 MB). Peak memory consumption was 18.8 MB. Max. memory is 11.5 GB. * Boogie Procedure Inliner took 82.63 ms. Allocated memory was 1.0 GB in the beginning and 1.2 GB in the end (delta: 132.6 MB). Free memory was 935.0 MB in the beginning and 1.1 GB in the end (delta: -192.4 MB). Peak memory consumption was 14.8 MB. Max. memory is 11.5 GB. * Boogie Preprocessor took 46.28 ms. Allocated memory is still 1.2 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 6.7 MB). Peak memory consumption was 6.7 MB. Max. memory is 11.5 GB. * RCFGBuilder took 776.40 ms. Allocated memory is still 1.2 GB. Free memory was 1.1 GB in the beginning and 1.0 GB in the end (delta: 84.5 MB). Peak memory consumption was 84.5 MB. Max. memory is 11.5 GB. * BuchiAutomizer took 7642.07 ms. Allocated memory was 1.2 GB in the beginning and 1.4 GB in the end (delta: 265.8 MB). Free memory was 1.0 GB in the beginning and 865.0 MB in the end (delta: 171.2 MB). Peak memory consumption was 437.0 MB. Max. memory is 11.5 GB. * Witness Printer took 711.23 ms. Allocated memory is still 1.4 GB. Free memory was 865.0 MB in the beginning and 842.7 MB in the end (delta: 22.3 MB). Peak memory consumption was 22.3 MB. Max. memory is 11.5 GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - StatisticsResult: Constructed decomposition of program Your program was decomposed into 25 terminating modules (24 trivial, 1 deterministic, 0 nondeterministic) and one nonterminating remainder module.One deterministic module has affine ranking function -1 * E_3 + 1 and consists of 3 locations. 24 modules have a trivial ranking function, the largest among these consists of 5 locations. The remainder module has 29681 locations. - StatisticsResult: Timing statistics BüchiAutomizer plugin needed 7.5s and 25 iterations. TraceHistogramMax:2. Analysis of lassos took 4.0s. Construction of modules took 0.6s. Büchi inclusion checks took 0.7s. Highest rank in rank-based complementation 3. Minimization of det autom 15. Minimization of nondet autom 10. Automata minimization 0.9s AutomataMinimizationTime, 25 MinimizatonAttempts, 9833 StatesRemovedByMinimization, 14 NontrivialMinimizations. Non-live state removal took 0.6s Buchi closure took 0.0s. Biggest automaton had 29681 states and ocurred in iteration 24. Nontrivial modules had stage [1, 0, 0, 0, 0]. InterpolantCoveringCapabilityFinite: 0/0 InterpolantCoveringCapabilityBuchi: 0/0 HoareTripleCheckerStatistics: 15250 SDtfs, 15669 SDslu, 13982 SDs, 0 SdLazy, 588 SolverSat, 277 SolverUnsat, 0 SolverUnknown, 0 SolverNotchecked, 0.6s Time LassoAnalysisResults: nont1 unkn0 SFLI6 SFLT0 conc4 concLT1 SILN1 SILU0 SILI12 SILT0 lasso0 LassoPreprocessingBenchmarks: Lassos: inital178 mio100 ax100 hnf100 lsp6 ukn100 mio100 lsp100 div100 bol100 ite100 ukn100 eq209 hnf86 smp100 dnf189 smp63 tf108 neg92 sie116 LassoTerminationAnalysisBenchmarks: ConstraintsSatisfiability: unsat Degree: 0 Time: 15ms VariablesStem: 0 VariablesLoop: 2 DisjunctsStem: 1 DisjunctsLoop: 2 SupportingInvariants: 0 MotzkinApplications: 4 LassoTerminationAnalysisBenchmarks: LassoNonterminationAnalysisSatFixpoint: 3 LassoNonterminationAnalysisSatUnbounded: 0 LassoNonterminationAnalysisUnsat: 1 LassoNonterminationAnalysisUnknown: 0 LassoNonterminationAnalysisTime: 0.0s - TerminationAnalysisResult: Nontermination possible Buchi Automizer proved that your program is nonterminating for some inputs - FixpointNonTerminationResult [Line: 401]: Nontermination argument in form of an infinite program execution. Nontermination argument in form of an infinite execution State at position 0 is {} State at position 1 is {__retres1=0, t3_st=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@b7c24be=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@d99e593=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@6f9d1557=0, tmp=1, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@34e8d971=0, __retres1=0, kernel_st=1, t2_st=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@4c8fed22=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@4987b1fe=0, t4_i=1, E_3=2, t4_pc=0, \result=0, E_1=2, tmp_ndt_2=0, \result=0, __retres1=0, \result=0, tmp_ndt_4=0, m_st=0, tmp___2=0, tmp___0=0, t3_pc=0, tmp=0, \result=0, __retres1=0, m_pc=0, \result=0, __retres1=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@589fe9dd=0, \result=0, T2_E=2, tmp___0=0, t1_pc=0, E_2=2, E_4=2, __retres1=1, T1_E=2, tmp_ndt_1=0, M_E=2, tmp=0, tmp_ndt_3=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@4b251d7f=0, __retres1=0, t2_i=1, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@6477c95d=0, T4_E=2, t3_i=1, t4_st=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@7daf23c=0, m_i=1, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@42dacd0e=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@4351647f=0, t1_st=0, tmp_ndt_5=0, t2_pc=0, tmp___3=0, tmp___1=0, T3_E=2, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@6bafb1ac=0, t1_i=1, \result=1} - StatisticsResult: NonterminationArgumentStatistics Fixpoint - NonterminatingLassoResult [Line: 401]: Nonterminating execution ----- class de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder.RCFGBacktranslator [?] ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2; [?] havoc main_#res;havoc main_~__retres1~6;havoc main_~__retres1~6;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; [?] havoc start_simulation_#t~ret12, start_simulation_#t~ret13, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; [?] assume 1 == ~m_i~0;~m_st~0 := 0; [?] assume 1 == ~t1_i~0;~t1_st~0 := 0; [?] assume 1 == ~t2_i~0;~t2_st~0 := 0; [?] assume 1 == ~t3_i~0;~t3_st~0 := 0; [?] assume 1 == ~t4_i~0;~t4_st~0 := 0; [?] assume !(0 == ~M_E~0); [?] assume !(0 == ~T1_E~0); [?] assume !(0 == ~T2_E~0); [?] assume !(0 == ~T3_E~0); [?] assume !(0 == ~T4_E~0); [?] assume !(0 == ~E_1~0); [?] assume !(0 == ~E_2~0); [?] assume !(0 == ~E_3~0); [?] assume !(0 == ~E_4~0); [?] havoc activate_threads_#t~ret6, activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; [?] assume !(1 == ~m_pc~0); [?] is_master_triggered_~__retres1~0 := 0; [?] is_master_triggered_#res := is_master_triggered_~__retres1~0; [?] activate_threads_#t~ret6 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret6;havoc activate_threads_#t~ret6; [?] assume !(0 != activate_threads_~tmp~1); [?] havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; [?] assume !(1 == ~t1_pc~0); [?] is_transmit1_triggered_~__retres1~1 := 0; [?] is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; [?] activate_threads_#t~ret7 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; [?] assume !(0 != activate_threads_~tmp___0~0); [?] havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; [?] assume !(1 == ~t2_pc~0); [?] is_transmit2_triggered_~__retres1~2 := 0; [?] is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; [?] activate_threads_#t~ret8 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; [?] assume !(0 != activate_threads_~tmp___1~0); [?] havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; [?] assume !(1 == ~t3_pc~0); [?] is_transmit3_triggered_~__retres1~3 := 0; [?] is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; [?] activate_threads_#t~ret9 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; [?] assume !(0 != activate_threads_~tmp___2~0); [?] havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; [?] assume !(1 == ~t4_pc~0); [?] is_transmit4_triggered_~__retres1~4 := 0; [?] is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; [?] activate_threads_#t~ret10 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; [?] assume !(0 != activate_threads_~tmp___3~0); [?] assume !(1 == ~M_E~0); [?] assume !(1 == ~T1_E~0); [?] assume !(1 == ~T2_E~0); [?] assume !(1 == ~T3_E~0); [?] assume !(1 == ~T4_E~0); [?] assume !(1 == ~E_1~0); [?] assume !(1 == ~E_2~0); [?] assume !(1 == ~E_3~0); [?] assume !(1 == ~E_4~0); [?] assume !false; [?] start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret0, eval_#t~nondet1, eval_~tmp_ndt_1~0, eval_#t~nondet2, eval_~tmp_ndt_2~0, eval_#t~nondet3, eval_~tmp_ndt_3~0, eval_#t~nondet4, eval_~tmp_ndt_4~0, eval_#t~nondet5, eval_~tmp_ndt_5~0, eval_~tmp~0;havoc eval_~tmp~0; [L15] ~m_pc~0 := 0; [L16] ~t1_pc~0 := 0; [L17] ~t2_pc~0 := 0; [L18] ~t3_pc~0 := 0; [L19] ~t4_pc~0 := 0; [L20] ~m_st~0 := 0; [L21] ~t1_st~0 := 0; [L22] ~t2_st~0 := 0; [L23] ~t3_st~0 := 0; [L24] ~t4_st~0 := 0; [L25] ~m_i~0 := 0; [L26] ~t1_i~0 := 0; [L27] ~t2_i~0 := 0; [L28] ~t3_i~0 := 0; [L29] ~t4_i~0 := 0; [L30] ~M_E~0 := 2; [L31] ~T1_E~0 := 2; [L32] ~T2_E~0 := 2; [L33] ~T3_E~0 := 2; [L34] ~T4_E~0 := 2; [L35] ~E_1~0 := 2; [L36] ~E_2~0 := 2; [L37] ~E_3~0 := 2; [L38] ~E_4~0 := 2; [?] havoc main_#res; [?] havoc main_~__retres1~6; [L811] havoc main_~__retres1~6; [L723] ~m_i~0 := 1; [L724] ~t1_i~0 := 1; [L725] ~t2_i~0 := 1; [L726] ~t3_i~0 := 1; [L727] ~t4_i~0 := 1; [L816] havoc start_simulation_#t~ret12, start_simulation_#t~ret13, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1; [L752] havoc start_simulation_~kernel_st~0; [L753] havoc start_simulation_~tmp~3; [L754] havoc start_simulation_~tmp___0~1; [L758] start_simulation_~kernel_st~0 := 0; [L331-L335] assume 1 == ~m_i~0; [L332] ~m_st~0 := 0; [L336-L340] assume 1 == ~t1_i~0; [L337] ~t1_st~0 := 0; [L341-L345] assume 1 == ~t2_i~0; [L342] ~t2_st~0 := 0; [L346-L350] assume 1 == ~t3_i~0; [L347] ~t3_st~0 := 0; [L351-L355] assume 1 == ~t4_i~0; [L352] ~t4_st~0 := 0; [L492-L496] assume !(0 == ~M_E~0); [L497-L501] assume !(0 == ~T1_E~0); [L502-L506] assume !(0 == ~T2_E~0); [L507-L511] assume !(0 == ~T3_E~0); [L512-L516] assume !(0 == ~T4_E~0); [L517-L521] assume !(0 == ~E_1~0); [L522-L526] assume !(0 == ~E_2~0); [L527-L531] assume !(0 == ~E_3~0); [L532-L536] assume !(0 == ~E_4~0); [L762] havoc activate_threads_#t~ret6, activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0; [L595] havoc activate_threads_~tmp~1; [L596] havoc activate_threads_~tmp___0~0; [L597] havoc activate_threads_~tmp___1~0; [L598] havoc activate_threads_~tmp___2~0; [L599] havoc activate_threads_~tmp___3~0; [L603] havoc is_master_triggered_#res; [L603] havoc is_master_triggered_~__retres1~0; [L225] havoc is_master_triggered_~__retres1~0; [L228-L237] assume !(1 == ~m_pc~0); [L238] is_master_triggered_~__retres1~0 := 0; [L240] is_master_triggered_#res := is_master_triggered_~__retres1~0; [L603] activate_threads_#t~ret6 := is_master_triggered_#res; [L603] activate_threads_~tmp~1 := activate_threads_#t~ret6; [L603] havoc activate_threads_#t~ret6; [L605-L609] assume !(0 != activate_threads_~tmp~1); [L611] havoc is_transmit1_triggered_#res; [L611] havoc is_transmit1_triggered_~__retres1~1; [L244] havoc is_transmit1_triggered_~__retres1~1; [L247-L256] assume !(1 == ~t1_pc~0); [L257] is_transmit1_triggered_~__retres1~1 := 0; [L259] is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; [L611] activate_threads_#t~ret7 := is_transmit1_triggered_#res; [L611] activate_threads_~tmp___0~0 := activate_threads_#t~ret7; [L611] havoc activate_threads_#t~ret7; [L613-L617] assume !(0 != activate_threads_~tmp___0~0); [L619] havoc is_transmit2_triggered_#res; [L619] havoc is_transmit2_triggered_~__retres1~2; [L263] havoc is_transmit2_triggered_~__retres1~2; [L266-L275] assume !(1 == ~t2_pc~0); [L276] is_transmit2_triggered_~__retres1~2 := 0; [L278] is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; [L619] activate_threads_#t~ret8 := is_transmit2_triggered_#res; [L619] activate_threads_~tmp___1~0 := activate_threads_#t~ret8; [L619] havoc activate_threads_#t~ret8; [L621-L625] assume !(0 != activate_threads_~tmp___1~0); [L627] havoc is_transmit3_triggered_#res; [L627] havoc is_transmit3_triggered_~__retres1~3; [L282] havoc is_transmit3_triggered_~__retres1~3; [L285-L294] assume !(1 == ~t3_pc~0); [L295] is_transmit3_triggered_~__retres1~3 := 0; [L297] is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; [L627] activate_threads_#t~ret9 := is_transmit3_triggered_#res; [L627] activate_threads_~tmp___2~0 := activate_threads_#t~ret9; [L627] havoc activate_threads_#t~ret9; [L629-L633] assume !(0 != activate_threads_~tmp___2~0); [L635] havoc is_transmit4_triggered_#res; [L635] havoc is_transmit4_triggered_~__retres1~4; [L301] havoc is_transmit4_triggered_~__retres1~4; [L304-L313] assume !(1 == ~t4_pc~0); [L314] is_transmit4_triggered_~__retres1~4 := 0; [L316] is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; [L635] activate_threads_#t~ret10 := is_transmit4_triggered_#res; [L635] activate_threads_~tmp___3~0 := activate_threads_#t~ret10; [L635] havoc activate_threads_#t~ret10; [L637-L641] assume !(0 != activate_threads_~tmp___3~0); [L545-L549] assume !(1 == ~M_E~0); [L550-L554] assume !(1 == ~T1_E~0); [L555-L559] assume !(1 == ~T2_E~0); [L560-L564] assume !(1 == ~T3_E~0); [L565-L569] assume !(1 == ~T4_E~0); [L570-L574] assume !(1 == ~E_1~0); [L575-L579] assume !(1 == ~E_2~0); [L580-L584] assume !(1 == ~E_3~0); [L585-L589] assume !(1 == ~E_4~0); [L766-L803] assume !false; [L769] start_simulation_~kernel_st~0 := 1; [L770] havoc eval_#t~ret0, eval_#t~nondet1, eval_~tmp_ndt_1~0, eval_#t~nondet2, eval_~tmp_ndt_2~0, eval_#t~nondet3, eval_~tmp_ndt_3~0, eval_#t~nondet4, eval_~tmp_ndt_4~0, eval_#t~nondet5, eval_~tmp_ndt_5~0, eval_~tmp~0; [L397] havoc eval_~tmp~0; ----- ----- class de.uni_freiburg.informatik.ultimate.boogie.preprocessor.BoogiePreprocessorBacktranslator [L15] ~m_pc~0 := 0; [L16] ~t1_pc~0 := 0; [L17] ~t2_pc~0 := 0; [L18] ~t3_pc~0 := 0; [L19] ~t4_pc~0 := 0; [L20] ~m_st~0 := 0; [L21] ~t1_st~0 := 0; [L22] ~t2_st~0 := 0; [L23] ~t3_st~0 := 0; [L24] ~t4_st~0 := 0; [L25] ~m_i~0 := 0; [L26] ~t1_i~0 := 0; [L27] ~t2_i~0 := 0; [L28] ~t3_i~0 := 0; [L29] ~t4_i~0 := 0; [L30] ~M_E~0 := 2; [L31] ~T1_E~0 := 2; [L32] ~T2_E~0 := 2; [L33] ~T3_E~0 := 2; [L34] ~T4_E~0 := 2; [L35] ~E_1~0 := 2; [L36] ~E_2~0 := 2; [L37] ~E_3~0 := 2; [L38] ~E_4~0 := 2; [?] havoc main_#res; [?] havoc main_~__retres1~6; [L811] havoc main_~__retres1~6; [L723] ~m_i~0 := 1; [L724] ~t1_i~0 := 1; [L725] ~t2_i~0 := 1; [L726] ~t3_i~0 := 1; [L727] ~t4_i~0 := 1; [L816] havoc start_simulation_#t~ret12, start_simulation_#t~ret13, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1; [L752] havoc start_simulation_~kernel_st~0; [L753] havoc start_simulation_~tmp~3; [L754] havoc start_simulation_~tmp___0~1; [L758] start_simulation_~kernel_st~0 := 0; [L331-L335] assume 1 == ~m_i~0; [L332] ~m_st~0 := 0; [L336-L340] assume 1 == ~t1_i~0; [L337] ~t1_st~0 := 0; [L341-L345] assume 1 == ~t2_i~0; [L342] ~t2_st~0 := 0; [L346-L350] assume 1 == ~t3_i~0; [L347] ~t3_st~0 := 0; [L351-L355] assume 1 == ~t4_i~0; [L352] ~t4_st~0 := 0; [L492-L496] assume !(0 == ~M_E~0); [L497-L501] assume !(0 == ~T1_E~0); [L502-L506] assume !(0 == ~T2_E~0); [L507-L511] assume !(0 == ~T3_E~0); [L512-L516] assume !(0 == ~T4_E~0); [L517-L521] assume !(0 == ~E_1~0); [L522-L526] assume !(0 == ~E_2~0); [L527-L531] assume !(0 == ~E_3~0); [L532-L536] assume !(0 == ~E_4~0); [L762] havoc activate_threads_#t~ret6, activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0; [L595] havoc activate_threads_~tmp~1; [L596] havoc activate_threads_~tmp___0~0; [L597] havoc activate_threads_~tmp___1~0; [L598] havoc activate_threads_~tmp___2~0; [L599] havoc activate_threads_~tmp___3~0; [L603] havoc is_master_triggered_#res; [L603] havoc is_master_triggered_~__retres1~0; [L225] havoc is_master_triggered_~__retres1~0; [L228-L237] assume !(1 == ~m_pc~0); [L238] is_master_triggered_~__retres1~0 := 0; [L240] is_master_triggered_#res := is_master_triggered_~__retres1~0; [L603] activate_threads_#t~ret6 := is_master_triggered_#res; [L603] activate_threads_~tmp~1 := activate_threads_#t~ret6; [L603] havoc activate_threads_#t~ret6; [L605-L609] assume !(0 != activate_threads_~tmp~1); [L611] havoc is_transmit1_triggered_#res; [L611] havoc is_transmit1_triggered_~__retres1~1; [L244] havoc is_transmit1_triggered_~__retres1~1; [L247-L256] assume !(1 == ~t1_pc~0); [L257] is_transmit1_triggered_~__retres1~1 := 0; [L259] is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; [L611] activate_threads_#t~ret7 := is_transmit1_triggered_#res; [L611] activate_threads_~tmp___0~0 := activate_threads_#t~ret7; [L611] havoc activate_threads_#t~ret7; [L613-L617] assume !(0 != activate_threads_~tmp___0~0); [L619] havoc is_transmit2_triggered_#res; [L619] havoc is_transmit2_triggered_~__retres1~2; [L263] havoc is_transmit2_triggered_~__retres1~2; [L266-L275] assume !(1 == ~t2_pc~0); [L276] is_transmit2_triggered_~__retres1~2 := 0; [L278] is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; [L619] activate_threads_#t~ret8 := is_transmit2_triggered_#res; [L619] activate_threads_~tmp___1~0 := activate_threads_#t~ret8; [L619] havoc activate_threads_#t~ret8; [L621-L625] assume !(0 != activate_threads_~tmp___1~0); [L627] havoc is_transmit3_triggered_#res; [L627] havoc is_transmit3_triggered_~__retres1~3; [L282] havoc is_transmit3_triggered_~__retres1~3; [L285-L294] assume !(1 == ~t3_pc~0); [L295] is_transmit3_triggered_~__retres1~3 := 0; [L297] is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; [L627] activate_threads_#t~ret9 := is_transmit3_triggered_#res; [L627] activate_threads_~tmp___2~0 := activate_threads_#t~ret9; [L627] havoc activate_threads_#t~ret9; [L629-L633] assume !(0 != activate_threads_~tmp___2~0); [L635] havoc is_transmit4_triggered_#res; [L635] havoc is_transmit4_triggered_~__retres1~4; [L301] havoc is_transmit4_triggered_~__retres1~4; [L304-L313] assume !(1 == ~t4_pc~0); [L314] is_transmit4_triggered_~__retres1~4 := 0; [L316] is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; [L635] activate_threads_#t~ret10 := is_transmit4_triggered_#res; [L635] activate_threads_~tmp___3~0 := activate_threads_#t~ret10; [L635] havoc activate_threads_#t~ret10; [L637-L641] assume !(0 != activate_threads_~tmp___3~0); [L545-L549] assume !(1 == ~M_E~0); [L550-L554] assume !(1 == ~T1_E~0); [L555-L559] assume !(1 == ~T2_E~0); [L560-L564] assume !(1 == ~T3_E~0); [L565-L569] assume !(1 == ~T4_E~0); [L570-L574] assume !(1 == ~E_1~0); [L575-L579] assume !(1 == ~E_2~0); [L580-L584] assume !(1 == ~E_3~0); [L585-L589] assume !(1 == ~E_4~0); [L766-L803] assume !false; [L769] start_simulation_~kernel_st~0 := 1; [L770] havoc eval_#t~ret0, eval_#t~nondet1, eval_~tmp_ndt_1~0, eval_#t~nondet2, eval_~tmp_ndt_2~0, eval_#t~nondet3, eval_~tmp_ndt_3~0, eval_#t~nondet4, eval_~tmp_ndt_4~0, eval_#t~nondet5, eval_~tmp_ndt_5~0, eval_~tmp~0; [L397] havoc eval_~tmp~0; [L15] ~m_pc~0 := 0; [L16] ~t1_pc~0 := 0; [L17] ~t2_pc~0 := 0; [L18] ~t3_pc~0 := 0; [L19] ~t4_pc~0 := 0; [L20] ~m_st~0 := 0; [L21] ~t1_st~0 := 0; [L22] ~t2_st~0 := 0; [L23] ~t3_st~0 := 0; [L24] ~t4_st~0 := 0; [L25] ~m_i~0 := 0; [L26] ~t1_i~0 := 0; [L27] ~t2_i~0 := 0; [L28] ~t3_i~0 := 0; [L29] ~t4_i~0 := 0; [L30] ~M_E~0 := 2; [L31] ~T1_E~0 := 2; [L32] ~T2_E~0 := 2; [L33] ~T3_E~0 := 2; [L34] ~T4_E~0 := 2; [L35] ~E_1~0 := 2; [L36] ~E_2~0 := 2; [L37] ~E_3~0 := 2; [L38] ~E_4~0 := 2; [?] havoc main_#res; [?] havoc main_~__retres1~6; [L811] havoc main_~__retres1~6; [L723] ~m_i~0 := 1; [L724] ~t1_i~0 := 1; [L725] ~t2_i~0 := 1; [L726] ~t3_i~0 := 1; [L727] ~t4_i~0 := 1; [L816] havoc start_simulation_#t~ret12, start_simulation_#t~ret13, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1; [L752] havoc start_simulation_~kernel_st~0; [L753] havoc start_simulation_~tmp~3; [L754] havoc start_simulation_~tmp___0~1; [L758] start_simulation_~kernel_st~0 := 0; [L331] COND TRUE 1 == ~m_i~0 [L332] ~m_st~0 := 0; [L336] COND TRUE 1 == ~t1_i~0 [L337] ~t1_st~0 := 0; [L341] COND TRUE 1 == ~t2_i~0 [L342] ~t2_st~0 := 0; [L346] COND TRUE 1 == ~t3_i~0 [L347] ~t3_st~0 := 0; [L351] COND TRUE 1 == ~t4_i~0 [L352] ~t4_st~0 := 0; [L492] COND FALSE !(0 == ~M_E~0) [L497] COND FALSE !(0 == ~T1_E~0) [L502] COND FALSE !(0 == ~T2_E~0) [L507] COND FALSE !(0 == ~T3_E~0) [L512] COND FALSE !(0 == ~T4_E~0) [L517] COND FALSE !(0 == ~E_1~0) [L522] COND FALSE !(0 == ~E_2~0) [L527] COND FALSE !(0 == ~E_3~0) [L532] COND FALSE !(0 == ~E_4~0) [L762] havoc activate_threads_#t~ret6, activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0; [L595] havoc activate_threads_~tmp~1; [L596] havoc activate_threads_~tmp___0~0; [L597] havoc activate_threads_~tmp___1~0; [L598] havoc activate_threads_~tmp___2~0; [L599] havoc activate_threads_~tmp___3~0; [L603] havoc is_master_triggered_#res; [L603] havoc is_master_triggered_~__retres1~0; [L225] havoc is_master_triggered_~__retres1~0; [L228] COND FALSE !(1 == ~m_pc~0) [L238] is_master_triggered_~__retres1~0 := 0; [L240] is_master_triggered_#res := is_master_triggered_~__retres1~0; [L603] activate_threads_#t~ret6 := is_master_triggered_#res; [L603] activate_threads_~tmp~1 := activate_threads_#t~ret6; [L603] havoc activate_threads_#t~ret6; [L605-L609] COND FALSE !(0 != activate_threads_~tmp~1) [L611] havoc is_transmit1_triggered_#res; [L611] havoc is_transmit1_triggered_~__retres1~1; [L244] havoc is_transmit1_triggered_~__retres1~1; [L247] COND FALSE !(1 == ~t1_pc~0) [L257] is_transmit1_triggered_~__retres1~1 := 0; [L259] is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; [L611] activate_threads_#t~ret7 := is_transmit1_triggered_#res; [L611] activate_threads_~tmp___0~0 := activate_threads_#t~ret7; [L611] havoc activate_threads_#t~ret7; [L613-L617] COND FALSE !(0 != activate_threads_~tmp___0~0) [L619] havoc is_transmit2_triggered_#res; [L619] havoc is_transmit2_triggered_~__retres1~2; [L263] havoc is_transmit2_triggered_~__retres1~2; [L266] COND FALSE !(1 == ~t2_pc~0) [L276] is_transmit2_triggered_~__retres1~2 := 0; [L278] is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; [L619] activate_threads_#t~ret8 := is_transmit2_triggered_#res; [L619] activate_threads_~tmp___1~0 := activate_threads_#t~ret8; [L619] havoc activate_threads_#t~ret8; [L621-L625] COND FALSE !(0 != activate_threads_~tmp___1~0) [L627] havoc is_transmit3_triggered_#res; [L627] havoc is_transmit3_triggered_~__retres1~3; [L282] havoc is_transmit3_triggered_~__retres1~3; [L285] COND FALSE !(1 == ~t3_pc~0) [L295] is_transmit3_triggered_~__retres1~3 := 0; [L297] is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; [L627] activate_threads_#t~ret9 := is_transmit3_triggered_#res; [L627] activate_threads_~tmp___2~0 := activate_threads_#t~ret9; [L627] havoc activate_threads_#t~ret9; [L629-L633] COND FALSE !(0 != activate_threads_~tmp___2~0) [L635] havoc is_transmit4_triggered_#res; [L635] havoc is_transmit4_triggered_~__retres1~4; [L301] havoc is_transmit4_triggered_~__retres1~4; [L304] COND FALSE !(1 == ~t4_pc~0) [L314] is_transmit4_triggered_~__retres1~4 := 0; [L316] is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; [L635] activate_threads_#t~ret10 := is_transmit4_triggered_#res; [L635] activate_threads_~tmp___3~0 := activate_threads_#t~ret10; [L635] havoc activate_threads_#t~ret10; [L637-L641] COND FALSE !(0 != activate_threads_~tmp___3~0) [L545] COND FALSE !(1 == ~M_E~0) [L550] COND FALSE !(1 == ~T1_E~0) [L555] COND FALSE !(1 == ~T2_E~0) [L560] COND FALSE !(1 == ~T3_E~0) [L565] COND FALSE !(1 == ~T4_E~0) [L570] COND FALSE !(1 == ~E_1~0) [L575] COND FALSE !(1 == ~E_2~0) [L580] COND FALSE !(1 == ~E_3~0) [L585] COND FALSE !(1 == ~E_4~0) [L766-L803] COND FALSE !(false) [L769] start_simulation_~kernel_st~0 := 1; [L770] havoc eval_#t~ret0, eval_#t~nondet1, eval_~tmp_ndt_1~0, eval_#t~nondet2, eval_~tmp_ndt_2~0, eval_#t~nondet3, eval_~tmp_ndt_3~0, eval_#t~nondet4, eval_~tmp_ndt_4~0, eval_#t~nondet5, eval_~tmp_ndt_5~0, eval_~tmp~0; [L397] havoc eval_~tmp~0; ----- ----- class de.uni_freiburg.informatik.ultimate.boogie.procedureinliner.backtranslation.InlinerBacktranslator [L15] ~m_pc~0 := 0; [L16] ~t1_pc~0 := 0; [L17] ~t2_pc~0 := 0; [L18] ~t3_pc~0 := 0; [L19] ~t4_pc~0 := 0; [L20] ~m_st~0 := 0; [L21] ~t1_st~0 := 0; [L22] ~t2_st~0 := 0; [L23] ~t3_st~0 := 0; [L24] ~t4_st~0 := 0; [L25] ~m_i~0 := 0; [L26] ~t1_i~0 := 0; [L27] ~t2_i~0 := 0; [L28] ~t3_i~0 := 0; [L29] ~t4_i~0 := 0; [L30] ~M_E~0 := 2; [L31] ~T1_E~0 := 2; [L32] ~T2_E~0 := 2; [L33] ~T3_E~0 := 2; [L34] ~T4_E~0 := 2; [L35] ~E_1~0 := 2; [L36] ~E_2~0 := 2; [L37] ~E_3~0 := 2; [L38] ~E_4~0 := 2; [?] havoc main_#res; [?] havoc main_~__retres1~6; [L811] havoc main_~__retres1~6; [L723] ~m_i~0 := 1; [L724] ~t1_i~0 := 1; [L725] ~t2_i~0 := 1; [L726] ~t3_i~0 := 1; [L727] ~t4_i~0 := 1; [L816] havoc start_simulation_#t~ret12, start_simulation_#t~ret13, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1; [L752] havoc start_simulation_~kernel_st~0; [L753] havoc start_simulation_~tmp~3; [L754] havoc start_simulation_~tmp___0~1; [L758] start_simulation_~kernel_st~0 := 0; [L331] COND TRUE 1 == ~m_i~0 [L332] ~m_st~0 := 0; [L336] COND TRUE 1 == ~t1_i~0 [L337] ~t1_st~0 := 0; [L341] COND TRUE 1 == ~t2_i~0 [L342] ~t2_st~0 := 0; [L346] COND TRUE 1 == ~t3_i~0 [L347] ~t3_st~0 := 0; [L351] COND TRUE 1 == ~t4_i~0 [L352] ~t4_st~0 := 0; [L492] COND FALSE !(0 == ~M_E~0) [L497] COND FALSE !(0 == ~T1_E~0) [L502] COND FALSE !(0 == ~T2_E~0) [L507] COND FALSE !(0 == ~T3_E~0) [L512] COND FALSE !(0 == ~T4_E~0) [L517] COND FALSE !(0 == ~E_1~0) [L522] COND FALSE !(0 == ~E_2~0) [L527] COND FALSE !(0 == ~E_3~0) [L532] COND FALSE !(0 == ~E_4~0) [L762] havoc activate_threads_#t~ret6, activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0; [L595] havoc activate_threads_~tmp~1; [L596] havoc activate_threads_~tmp___0~0; [L597] havoc activate_threads_~tmp___1~0; [L598] havoc activate_threads_~tmp___2~0; [L599] havoc activate_threads_~tmp___3~0; [L603] havoc is_master_triggered_#res; [L603] havoc is_master_triggered_~__retres1~0; [L225] havoc is_master_triggered_~__retres1~0; [L228] COND FALSE !(1 == ~m_pc~0) [L238] is_master_triggered_~__retres1~0 := 0; [L240] is_master_triggered_#res := is_master_triggered_~__retres1~0; [L603] activate_threads_#t~ret6 := is_master_triggered_#res; [L603] activate_threads_~tmp~1 := activate_threads_#t~ret6; [L603] havoc activate_threads_#t~ret6; [L605-L609] COND FALSE !(0 != activate_threads_~tmp~1) [L611] havoc is_transmit1_triggered_#res; [L611] havoc is_transmit1_triggered_~__retres1~1; [L244] havoc is_transmit1_triggered_~__retres1~1; [L247] COND FALSE !(1 == ~t1_pc~0) [L257] is_transmit1_triggered_~__retres1~1 := 0; [L259] is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; [L611] activate_threads_#t~ret7 := is_transmit1_triggered_#res; [L611] activate_threads_~tmp___0~0 := activate_threads_#t~ret7; [L611] havoc activate_threads_#t~ret7; [L613-L617] COND FALSE !(0 != activate_threads_~tmp___0~0) [L619] havoc is_transmit2_triggered_#res; [L619] havoc is_transmit2_triggered_~__retres1~2; [L263] havoc is_transmit2_triggered_~__retres1~2; [L266] COND FALSE !(1 == ~t2_pc~0) [L276] is_transmit2_triggered_~__retres1~2 := 0; [L278] is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; [L619] activate_threads_#t~ret8 := is_transmit2_triggered_#res; [L619] activate_threads_~tmp___1~0 := activate_threads_#t~ret8; [L619] havoc activate_threads_#t~ret8; [L621-L625] COND FALSE !(0 != activate_threads_~tmp___1~0) [L627] havoc is_transmit3_triggered_#res; [L627] havoc is_transmit3_triggered_~__retres1~3; [L282] havoc is_transmit3_triggered_~__retres1~3; [L285] COND FALSE !(1 == ~t3_pc~0) [L295] is_transmit3_triggered_~__retres1~3 := 0; [L297] is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; [L627] activate_threads_#t~ret9 := is_transmit3_triggered_#res; [L627] activate_threads_~tmp___2~0 := activate_threads_#t~ret9; [L627] havoc activate_threads_#t~ret9; [L629-L633] COND FALSE !(0 != activate_threads_~tmp___2~0) [L635] havoc is_transmit4_triggered_#res; [L635] havoc is_transmit4_triggered_~__retres1~4; [L301] havoc is_transmit4_triggered_~__retres1~4; [L304] COND FALSE !(1 == ~t4_pc~0) [L314] is_transmit4_triggered_~__retres1~4 := 0; [L316] is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; [L635] activate_threads_#t~ret10 := is_transmit4_triggered_#res; [L635] activate_threads_~tmp___3~0 := activate_threads_#t~ret10; [L635] havoc activate_threads_#t~ret10; [L637-L641] COND FALSE !(0 != activate_threads_~tmp___3~0) [L545] COND FALSE !(1 == ~M_E~0) [L550] COND FALSE !(1 == ~T1_E~0) [L555] COND FALSE !(1 == ~T2_E~0) [L560] COND FALSE !(1 == ~T3_E~0) [L565] COND FALSE !(1 == ~T4_E~0) [L570] COND FALSE !(1 == ~E_1~0) [L575] COND FALSE !(1 == ~E_2~0) [L580] COND FALSE !(1 == ~E_3~0) [L585] COND FALSE !(1 == ~E_4~0) [L766-L803] COND FALSE !(false) [L769] start_simulation_~kernel_st~0 := 1; [L770] havoc eval_#t~ret0, eval_#t~nondet1, eval_~tmp_ndt_1~0, eval_#t~nondet2, eval_~tmp_ndt_2~0, eval_#t~nondet3, eval_~tmp_ndt_3~0, eval_#t~nondet4, eval_~tmp_ndt_4~0, eval_#t~nondet5, eval_~tmp_ndt_5~0, eval_~tmp~0; [L397] havoc eval_~tmp~0; [L15] ~m_pc~0 := 0; [L16] ~t1_pc~0 := 0; [L17] ~t2_pc~0 := 0; [L18] ~t3_pc~0 := 0; [L19] ~t4_pc~0 := 0; [L20] ~m_st~0 := 0; [L21] ~t1_st~0 := 0; [L22] ~t2_st~0 := 0; [L23] ~t3_st~0 := 0; [L24] ~t4_st~0 := 0; [L25] ~m_i~0 := 0; [L26] ~t1_i~0 := 0; [L27] ~t2_i~0 := 0; [L28] ~t3_i~0 := 0; [L29] ~t4_i~0 := 0; [L30] ~M_E~0 := 2; [L31] ~T1_E~0 := 2; [L32] ~T2_E~0 := 2; [L33] ~T3_E~0 := 2; [L34] ~T4_E~0 := 2; [L35] ~E_1~0 := 2; [L36] ~E_2~0 := 2; [L37] ~E_3~0 := 2; [L38] ~E_4~0 := 2; [L811] havoc ~__retres1~6; [L723] ~m_i~0 := 1; [L724] ~t1_i~0 := 1; [L725] ~t2_i~0 := 1; [L726] ~t3_i~0 := 1; [L727] ~t4_i~0 := 1; [L752] havoc ~kernel_st~0; [L753] havoc ~tmp~3; [L754] havoc ~tmp___0~1; [L758] ~kernel_st~0 := 0; [L331] COND TRUE 1 == ~m_i~0 [L332] ~m_st~0 := 0; [L336] COND TRUE 1 == ~t1_i~0 [L337] ~t1_st~0 := 0; [L341] COND TRUE 1 == ~t2_i~0 [L342] ~t2_st~0 := 0; [L346] COND TRUE 1 == ~t3_i~0 [L347] ~t3_st~0 := 0; [L351] COND TRUE 1 == ~t4_i~0 [L352] ~t4_st~0 := 0; [L492] COND FALSE !(0 == ~M_E~0) [L497] COND FALSE !(0 == ~T1_E~0) [L502] COND FALSE !(0 == ~T2_E~0) [L507] COND FALSE !(0 == ~T3_E~0) [L512] COND FALSE !(0 == ~T4_E~0) [L517] COND FALSE !(0 == ~E_1~0) [L522] COND FALSE !(0 == ~E_2~0) [L527] COND FALSE !(0 == ~E_3~0) [L532] COND FALSE !(0 == ~E_4~0) [L595] havoc ~tmp~1; [L596] havoc ~tmp___0~0; [L597] havoc ~tmp___1~0; [L598] havoc ~tmp___2~0; [L599] havoc ~tmp___3~0; [L225] havoc ~__retres1~0; [L228] COND FALSE !(1 == ~m_pc~0) [L238] ~__retres1~0 := 0; [L240] #res := ~__retres1~0; [L603] ~tmp~1 := #t~ret6; [L603] havoc #t~ret6; [L605-L609] COND FALSE !(0 != ~tmp~1) [L244] havoc ~__retres1~1; [L247] COND FALSE !(1 == ~t1_pc~0) [L257] ~__retres1~1 := 0; [L259] #res := ~__retres1~1; [L611] ~tmp___0~0 := #t~ret7; [L611] havoc #t~ret7; [L613-L617] COND FALSE !(0 != ~tmp___0~0) [L263] havoc ~__retres1~2; [L266] COND FALSE !(1 == ~t2_pc~0) [L276] ~__retres1~2 := 0; [L278] #res := ~__retres1~2; [L619] ~tmp___1~0 := #t~ret8; [L619] havoc #t~ret8; [L621-L625] COND FALSE !(0 != ~tmp___1~0) [L282] havoc ~__retres1~3; [L285] COND FALSE !(1 == ~t3_pc~0) [L295] ~__retres1~3 := 0; [L297] #res := ~__retres1~3; [L627] ~tmp___2~0 := #t~ret9; [L627] havoc #t~ret9; [L629-L633] COND FALSE !(0 != ~tmp___2~0) [L301] havoc ~__retres1~4; [L304] COND FALSE !(1 == ~t4_pc~0) [L314] ~__retres1~4 := 0; [L316] #res := ~__retres1~4; [L635] ~tmp___3~0 := #t~ret10; [L635] havoc #t~ret10; [L637-L641] COND FALSE !(0 != ~tmp___3~0) [L545] COND FALSE !(1 == ~M_E~0) [L550] COND FALSE !(1 == ~T1_E~0) [L555] COND FALSE !(1 == ~T2_E~0) [L560] COND FALSE !(1 == ~T3_E~0) [L565] COND FALSE !(1 == ~T4_E~0) [L570] COND FALSE !(1 == ~E_1~0) [L575] COND FALSE !(1 == ~E_2~0) [L580] COND FALSE !(1 == ~E_3~0) [L585] COND FALSE !(1 == ~E_4~0) [L766-L803] COND FALSE !(false) [L769] ~kernel_st~0 := 1; [L397] havoc ~tmp~0; ----- ----- class de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.CACSL2BoogieBacktranslator [L15] ~m_pc~0 := 0; [L16] ~t1_pc~0 := 0; [L17] ~t2_pc~0 := 0; [L18] ~t3_pc~0 := 0; [L19] ~t4_pc~0 := 0; [L20] ~m_st~0 := 0; [L21] ~t1_st~0 := 0; [L22] ~t2_st~0 := 0; [L23] ~t3_st~0 := 0; [L24] ~t4_st~0 := 0; [L25] ~m_i~0 := 0; [L26] ~t1_i~0 := 0; [L27] ~t2_i~0 := 0; [L28] ~t3_i~0 := 0; [L29] ~t4_i~0 := 0; [L30] ~M_E~0 := 2; [L31] ~T1_E~0 := 2; [L32] ~T2_E~0 := 2; [L33] ~T3_E~0 := 2; [L34] ~T4_E~0 := 2; [L35] ~E_1~0 := 2; [L36] ~E_2~0 := 2; [L37] ~E_3~0 := 2; [L38] ~E_4~0 := 2; [L811] havoc ~__retres1~6; [L723] ~m_i~0 := 1; [L724] ~t1_i~0 := 1; [L725] ~t2_i~0 := 1; [L726] ~t3_i~0 := 1; [L727] ~t4_i~0 := 1; [L752] havoc ~kernel_st~0; [L753] havoc ~tmp~3; [L754] havoc ~tmp___0~1; [L758] ~kernel_st~0 := 0; [L331] COND TRUE 1 == ~m_i~0 [L332] ~m_st~0 := 0; [L336] COND TRUE 1 == ~t1_i~0 [L337] ~t1_st~0 := 0; [L341] COND TRUE 1 == ~t2_i~0 [L342] ~t2_st~0 := 0; [L346] COND TRUE 1 == ~t3_i~0 [L347] ~t3_st~0 := 0; [L351] COND TRUE 1 == ~t4_i~0 [L352] ~t4_st~0 := 0; [L492] COND FALSE !(0 == ~M_E~0) [L497] COND FALSE !(0 == ~T1_E~0) [L502] COND FALSE !(0 == ~T2_E~0) [L507] COND FALSE !(0 == ~T3_E~0) [L512] COND FALSE !(0 == ~T4_E~0) [L517] COND FALSE !(0 == ~E_1~0) [L522] COND FALSE !(0 == ~E_2~0) [L527] COND FALSE !(0 == ~E_3~0) [L532] COND FALSE !(0 == ~E_4~0) [L595] havoc ~tmp~1; [L596] havoc ~tmp___0~0; [L597] havoc ~tmp___1~0; [L598] havoc ~tmp___2~0; [L599] havoc ~tmp___3~0; [L225] havoc ~__retres1~0; [L228] COND FALSE !(1 == ~m_pc~0) [L238] ~__retres1~0 := 0; [L240] #res := ~__retres1~0; [L603] ~tmp~1 := #t~ret6; [L603] havoc #t~ret6; [L605-L609] COND FALSE !(0 != ~tmp~1) [L244] havoc ~__retres1~1; [L247] COND FALSE !(1 == ~t1_pc~0) [L257] ~__retres1~1 := 0; [L259] #res := ~__retres1~1; [L611] ~tmp___0~0 := #t~ret7; [L611] havoc #t~ret7; [L613-L617] COND FALSE !(0 != ~tmp___0~0) [L263] havoc ~__retres1~2; [L266] COND FALSE !(1 == ~t2_pc~0) [L276] ~__retres1~2 := 0; [L278] #res := ~__retres1~2; [L619] ~tmp___1~0 := #t~ret8; [L619] havoc #t~ret8; [L621-L625] COND FALSE !(0 != ~tmp___1~0) [L282] havoc ~__retres1~3; [L285] COND FALSE !(1 == ~t3_pc~0) [L295] ~__retres1~3 := 0; [L297] #res := ~__retres1~3; [L627] ~tmp___2~0 := #t~ret9; [L627] havoc #t~ret9; [L629-L633] COND FALSE !(0 != ~tmp___2~0) [L301] havoc ~__retres1~4; [L304] COND FALSE !(1 == ~t4_pc~0) [L314] ~__retres1~4 := 0; [L316] #res := ~__retres1~4; [L635] ~tmp___3~0 := #t~ret10; [L635] havoc #t~ret10; [L637-L641] COND FALSE !(0 != ~tmp___3~0) [L545] COND FALSE !(1 == ~M_E~0) [L550] COND FALSE !(1 == ~T1_E~0) [L555] COND FALSE !(1 == ~T2_E~0) [L560] COND FALSE !(1 == ~T3_E~0) [L565] COND FALSE !(1 == ~T4_E~0) [L570] COND FALSE !(1 == ~E_1~0) [L575] COND FALSE !(1 == ~E_2~0) [L580] COND FALSE !(1 == ~E_3~0) [L585] COND FALSE !(1 == ~E_4~0) [L766-L803] COND FALSE !(false) [L769] ~kernel_st~0 := 1; [L397] havoc ~tmp~0; [L15] int m_pc = 0; [L16] int t1_pc = 0; [L17] int t2_pc = 0; [L18] int t3_pc = 0; [L19] int t4_pc = 0; [L20] int m_st ; [L21] int t1_st ; [L22] int t2_st ; [L23] int t3_st ; [L24] int t4_st ; [L25] int m_i ; [L26] int t1_i ; [L27] int t2_i ; [L28] int t3_i ; [L29] int t4_i ; [L30] int M_E = 2; [L31] int T1_E = 2; [L32] int T2_E = 2; [L33] int T3_E = 2; [L34] int T4_E = 2; [L35] int E_1 = 2; [L36] int E_2 = 2; [L37] int E_3 = 2; [L38] int E_4 = 2; [L811] int __retres1 ; [L723] m_i = 1 [L724] t1_i = 1 [L725] t2_i = 1 [L726] t3_i = 1 [L727] t4_i = 1 [L752] int kernel_st ; [L753] int tmp ; [L754] int tmp___0 ; [L758] kernel_st = 0 [L331] COND TRUE m_i == 1 [L332] m_st = 0 [L336] COND TRUE t1_i == 1 [L337] t1_st = 0 [L341] COND TRUE t2_i == 1 [L342] t2_st = 0 [L346] COND TRUE t3_i == 1 [L347] t3_st = 0 [L351] COND TRUE t4_i == 1 [L352] t4_st = 0 [L492] COND FALSE !(M_E == 0) [L497] COND FALSE !(T1_E == 0) [L502] COND FALSE !(T2_E == 0) [L507] COND FALSE !(T3_E == 0) [L512] COND FALSE !(T4_E == 0) [L517] COND FALSE !(E_1 == 0) [L522] COND FALSE !(E_2 == 0) [L527] COND FALSE !(E_3 == 0) [L532] COND FALSE !(E_4 == 0) [L595] int tmp ; [L596] int tmp___0 ; [L597] int tmp___1 ; [L598] int tmp___2 ; [L599] int tmp___3 ; [L225] int __retres1 ; [L228] COND FALSE !(m_pc == 1) [L238] __retres1 = 0 [L240] return (__retres1); [L603] tmp = is_master_triggered() [L605] COND FALSE !(\read(tmp)) [L244] int __retres1 ; [L247] COND FALSE !(t1_pc == 1) [L257] __retres1 = 0 [L259] return (__retres1); [L611] tmp___0 = is_transmit1_triggered() [L613] COND FALSE !(\read(tmp___0)) [L263] int __retres1 ; [L266] COND FALSE !(t2_pc == 1) [L276] __retres1 = 0 [L278] return (__retres1); [L619] tmp___1 = is_transmit2_triggered() [L621] COND FALSE !(\read(tmp___1)) [L282] int __retres1 ; [L285] COND FALSE !(t3_pc == 1) [L295] __retres1 = 0 [L297] return (__retres1); [L627] tmp___2 = is_transmit3_triggered() [L629] COND FALSE !(\read(tmp___2)) [L301] int __retres1 ; [L304] COND FALSE !(t4_pc == 1) [L314] __retres1 = 0 [L316] return (__retres1); [L635] tmp___3 = is_transmit4_triggered() [L637] COND FALSE !(\read(tmp___3)) [L545] COND FALSE !(M_E == 1) [L550] COND FALSE !(T1_E == 1) [L555] COND FALSE !(T2_E == 1) [L560] COND FALSE !(T3_E == 1) [L565] COND FALSE !(T4_E == 1) [L570] COND FALSE !(E_1 == 1) [L575] COND FALSE !(E_2 == 1) [L580] COND FALSE !(E_3 == 1) [L585] COND FALSE !(E_4 == 1) [L766] COND TRUE 1 [L769] kernel_st = 1 [L397] int tmp ; ----- ----- class de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder.RCFGBacktranslator [?] assume !false; [?] havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; [?] assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; [?] exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; [?] eval_#t~ret0 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret0;havoc eval_#t~ret0; [?] assume 0 != eval_~tmp~0; [?] assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0;eval_~tmp_ndt_1~0 := eval_#t~nondet1;havoc eval_#t~nondet1; [?] assume !(0 != eval_~tmp_ndt_1~0); [?] assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0;eval_~tmp_ndt_2~0 := eval_#t~nondet2;havoc eval_#t~nondet2; [?] assume !(0 != eval_~tmp_ndt_2~0); [?] assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0;eval_~tmp_ndt_3~0 := eval_#t~nondet3;havoc eval_#t~nondet3; [?] assume !(0 != eval_~tmp_ndt_3~0); [?] assume 0 == ~t3_st~0;havoc eval_~tmp_ndt_4~0;eval_~tmp_ndt_4~0 := eval_#t~nondet4;havoc eval_#t~nondet4; [?] assume !(0 != eval_~tmp_ndt_4~0); [?] assume 0 == ~t4_st~0;havoc eval_~tmp_ndt_5~0;eval_~tmp_ndt_5~0 := eval_#t~nondet5;havoc eval_#t~nondet5; [?] assume !(0 != eval_~tmp_ndt_5~0); [L401-L481] assume !false; [L404] havoc exists_runnable_thread_#res; [L404] havoc exists_runnable_thread_~__retres1~5; [L361] havoc exists_runnable_thread_~__retres1~5; [L364-L389] assume 0 == ~m_st~0; [L365] exists_runnable_thread_~__retres1~5 := 1; [L392] exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; [L404] eval_#t~ret0 := exists_runnable_thread_#res; [L404] eval_~tmp~0 := eval_#t~ret0; [L404] havoc eval_#t~ret0; [L406-L410] assume 0 != eval_~tmp~0; [L411-L424] assume 0 == ~m_st~0; [L412] havoc eval_~tmp_ndt_1~0; [L413] eval_~tmp_ndt_1~0 := eval_#t~nondet1; [L413] havoc eval_#t~nondet1; [L414-L421] assume !(0 != eval_~tmp_ndt_1~0); [L425-L438] assume 0 == ~t1_st~0; [L426] havoc eval_~tmp_ndt_2~0; [L427] eval_~tmp_ndt_2~0 := eval_#t~nondet2; [L427] havoc eval_#t~nondet2; [L428-L435] assume !(0 != eval_~tmp_ndt_2~0); [L439-L452] assume 0 == ~t2_st~0; [L440] havoc eval_~tmp_ndt_3~0; [L441] eval_~tmp_ndt_3~0 := eval_#t~nondet3; [L441] havoc eval_#t~nondet3; [L442-L449] assume !(0 != eval_~tmp_ndt_3~0); [L453-L466] assume 0 == ~t3_st~0; [L454] havoc eval_~tmp_ndt_4~0; [L455] eval_~tmp_ndt_4~0 := eval_#t~nondet4; [L455] havoc eval_#t~nondet4; [L456-L463] assume !(0 != eval_~tmp_ndt_4~0); [L467-L480] assume 0 == ~t4_st~0; [L468] havoc eval_~tmp_ndt_5~0; [L469] eval_~tmp_ndt_5~0 := eval_#t~nondet5; [L469] havoc eval_#t~nondet5; [L470-L477] assume !(0 != eval_~tmp_ndt_5~0); ----- ----- class de.uni_freiburg.informatik.ultimate.boogie.preprocessor.BoogiePreprocessorBacktranslator [L401-L481] assume !false; [L404] havoc exists_runnable_thread_#res; [L404] havoc exists_runnable_thread_~__retres1~5; [L361] havoc exists_runnable_thread_~__retres1~5; [L364-L389] assume 0 == ~m_st~0; [L365] exists_runnable_thread_~__retres1~5 := 1; [L392] exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; [L404] eval_#t~ret0 := exists_runnable_thread_#res; [L404] eval_~tmp~0 := eval_#t~ret0; [L404] havoc eval_#t~ret0; [L406-L410] assume 0 != eval_~tmp~0; [L411-L424] assume 0 == ~m_st~0; [L412] havoc eval_~tmp_ndt_1~0; [L413] eval_~tmp_ndt_1~0 := eval_#t~nondet1; [L413] havoc eval_#t~nondet1; [L414-L421] assume !(0 != eval_~tmp_ndt_1~0); [L425-L438] assume 0 == ~t1_st~0; [L426] havoc eval_~tmp_ndt_2~0; [L427] eval_~tmp_ndt_2~0 := eval_#t~nondet2; [L427] havoc eval_#t~nondet2; [L428-L435] assume !(0 != eval_~tmp_ndt_2~0); [L439-L452] assume 0 == ~t2_st~0; [L440] havoc eval_~tmp_ndt_3~0; [L441] eval_~tmp_ndt_3~0 := eval_#t~nondet3; [L441] havoc eval_#t~nondet3; [L442-L449] assume !(0 != eval_~tmp_ndt_3~0); [L453-L466] assume 0 == ~t3_st~0; [L454] havoc eval_~tmp_ndt_4~0; [L455] eval_~tmp_ndt_4~0 := eval_#t~nondet4; [L455] havoc eval_#t~nondet4; [L456-L463] assume !(0 != eval_~tmp_ndt_4~0); [L467-L480] assume 0 == ~t4_st~0; [L468] havoc eval_~tmp_ndt_5~0; [L469] eval_~tmp_ndt_5~0 := eval_#t~nondet5; [L469] havoc eval_#t~nondet5; [L470-L477] assume !(0 != eval_~tmp_ndt_5~0); [L401-L481] COND FALSE !(false) [L404] havoc exists_runnable_thread_#res; [L404] havoc exists_runnable_thread_~__retres1~5; [L361] havoc exists_runnable_thread_~__retres1~5; [L364] COND TRUE 0 == ~m_st~0 [L365] exists_runnable_thread_~__retres1~5 := 1; [L392] exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; [L404] eval_#t~ret0 := exists_runnable_thread_#res; [L404] eval_~tmp~0 := eval_#t~ret0; [L404] havoc eval_#t~ret0; [L406-L410] COND TRUE 0 != eval_~tmp~0 [L411] COND TRUE 0 == ~m_st~0 [L412] havoc eval_~tmp_ndt_1~0; [L413] eval_~tmp_ndt_1~0 := eval_#t~nondet1; [L413] havoc eval_#t~nondet1; [L414-L421] COND FALSE !(0 != eval_~tmp_ndt_1~0) [L425] COND TRUE 0 == ~t1_st~0 [L426] havoc eval_~tmp_ndt_2~0; [L427] eval_~tmp_ndt_2~0 := eval_#t~nondet2; [L427] havoc eval_#t~nondet2; [L428-L435] COND FALSE !(0 != eval_~tmp_ndt_2~0) [L439] COND TRUE 0 == ~t2_st~0 [L440] havoc eval_~tmp_ndt_3~0; [L441] eval_~tmp_ndt_3~0 := eval_#t~nondet3; [L441] havoc eval_#t~nondet3; [L442-L449] COND FALSE !(0 != eval_~tmp_ndt_3~0) [L453] COND TRUE 0 == ~t3_st~0 [L454] havoc eval_~tmp_ndt_4~0; [L455] eval_~tmp_ndt_4~0 := eval_#t~nondet4; [L455] havoc eval_#t~nondet4; [L456-L463] COND FALSE !(0 != eval_~tmp_ndt_4~0) [L467] COND TRUE 0 == ~t4_st~0 [L468] havoc eval_~tmp_ndt_5~0; [L469] eval_~tmp_ndt_5~0 := eval_#t~nondet5; [L469] havoc eval_#t~nondet5; [L470-L477] COND FALSE !(0 != eval_~tmp_ndt_5~0) ----- ----- class de.uni_freiburg.informatik.ultimate.boogie.procedureinliner.backtranslation.InlinerBacktranslator [L401-L481] COND FALSE !(false) [L404] havoc exists_runnable_thread_#res; [L404] havoc exists_runnable_thread_~__retres1~5; [L361] havoc exists_runnable_thread_~__retres1~5; [L364] COND TRUE 0 == ~m_st~0 [L365] exists_runnable_thread_~__retres1~5 := 1; [L392] exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; [L404] eval_#t~ret0 := exists_runnable_thread_#res; [L404] eval_~tmp~0 := eval_#t~ret0; [L404] havoc eval_#t~ret0; [L406-L410] COND TRUE 0 != eval_~tmp~0 [L411] COND TRUE 0 == ~m_st~0 [L412] havoc eval_~tmp_ndt_1~0; [L413] eval_~tmp_ndt_1~0 := eval_#t~nondet1; [L413] havoc eval_#t~nondet1; [L414-L421] COND FALSE !(0 != eval_~tmp_ndt_1~0) [L425] COND TRUE 0 == ~t1_st~0 [L426] havoc eval_~tmp_ndt_2~0; [L427] eval_~tmp_ndt_2~0 := eval_#t~nondet2; [L427] havoc eval_#t~nondet2; [L428-L435] COND FALSE !(0 != eval_~tmp_ndt_2~0) [L439] COND TRUE 0 == ~t2_st~0 [L440] havoc eval_~tmp_ndt_3~0; [L441] eval_~tmp_ndt_3~0 := eval_#t~nondet3; [L441] havoc eval_#t~nondet3; [L442-L449] COND FALSE !(0 != eval_~tmp_ndt_3~0) [L453] COND TRUE 0 == ~t3_st~0 [L454] havoc eval_~tmp_ndt_4~0; [L455] eval_~tmp_ndt_4~0 := eval_#t~nondet4; [L455] havoc eval_#t~nondet4; [L456-L463] COND FALSE !(0 != eval_~tmp_ndt_4~0) [L467] COND TRUE 0 == ~t4_st~0 [L468] havoc eval_~tmp_ndt_5~0; [L469] eval_~tmp_ndt_5~0 := eval_#t~nondet5; [L469] havoc eval_#t~nondet5; [L470-L477] COND FALSE !(0 != eval_~tmp_ndt_5~0) [L401-L481] COND FALSE !(false) [L361] havoc ~__retres1~5; [L364] COND TRUE 0 == ~m_st~0 [L365] ~__retres1~5 := 1; [L392] #res := ~__retres1~5; [L404] ~tmp~0 := #t~ret0; [L404] havoc #t~ret0; [L406-L410] COND TRUE 0 != ~tmp~0 [L411] COND TRUE 0 == ~m_st~0 [L412] havoc ~tmp_ndt_1~0; [L413] ~tmp_ndt_1~0 := #t~nondet1; [L413] havoc #t~nondet1; [L414-L421] COND FALSE !(0 != ~tmp_ndt_1~0) [L425] COND TRUE 0 == ~t1_st~0 [L426] havoc ~tmp_ndt_2~0; [L427] ~tmp_ndt_2~0 := #t~nondet2; [L427] havoc #t~nondet2; [L428-L435] COND FALSE !(0 != ~tmp_ndt_2~0) [L439] COND TRUE 0 == ~t2_st~0 [L440] havoc ~tmp_ndt_3~0; [L441] ~tmp_ndt_3~0 := #t~nondet3; [L441] havoc #t~nondet3; [L442-L449] COND FALSE !(0 != ~tmp_ndt_3~0) [L453] COND TRUE 0 == ~t3_st~0 [L454] havoc ~tmp_ndt_4~0; [L455] ~tmp_ndt_4~0 := #t~nondet4; [L455] havoc #t~nondet4; [L456-L463] COND FALSE !(0 != ~tmp_ndt_4~0) [L467] COND TRUE 0 == ~t4_st~0 [L468] havoc ~tmp_ndt_5~0; [L469] ~tmp_ndt_5~0 := #t~nondet5; [L469] havoc #t~nondet5; [L470-L477] COND FALSE !(0 != ~tmp_ndt_5~0) ----- ----- class de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.CACSL2BoogieBacktranslator [L401-L481] COND FALSE !(false) [L361] havoc ~__retres1~5; [L364] COND TRUE 0 == ~m_st~0 [L365] ~__retres1~5 := 1; [L392] #res := ~__retres1~5; [L404] ~tmp~0 := #t~ret0; [L404] havoc #t~ret0; [L406-L410] COND TRUE 0 != ~tmp~0 [L411] COND TRUE 0 == ~m_st~0 [L412] havoc ~tmp_ndt_1~0; [L413] ~tmp_ndt_1~0 := #t~nondet1; [L413] havoc #t~nondet1; [L414-L421] COND FALSE !(0 != ~tmp_ndt_1~0) [L425] COND TRUE 0 == ~t1_st~0 [L426] havoc ~tmp_ndt_2~0; [L427] ~tmp_ndt_2~0 := #t~nondet2; [L427] havoc #t~nondet2; [L428-L435] COND FALSE !(0 != ~tmp_ndt_2~0) [L439] COND TRUE 0 == ~t2_st~0 [L440] havoc ~tmp_ndt_3~0; [L441] ~tmp_ndt_3~0 := #t~nondet3; [L441] havoc #t~nondet3; [L442-L449] COND FALSE !(0 != ~tmp_ndt_3~0) [L453] COND TRUE 0 == ~t3_st~0 [L454] havoc ~tmp_ndt_4~0; [L455] ~tmp_ndt_4~0 := #t~nondet4; [L455] havoc #t~nondet4; [L456-L463] COND FALSE !(0 != ~tmp_ndt_4~0) [L467] COND TRUE 0 == ~t4_st~0 [L468] havoc ~tmp_ndt_5~0; [L469] ~tmp_ndt_5~0 := #t~nondet5; [L469] havoc #t~nondet5; [L470-L477] COND FALSE !(0 != ~tmp_ndt_5~0) [L401] COND TRUE 1 [L361] int __retres1 ; [L364] COND TRUE m_st == 0 [L365] __retres1 = 1 [L392] return (__retres1); [L404] tmp = exists_runnable_thread() [L406] COND TRUE \read(tmp) [L411] COND TRUE m_st == 0 [L412] int tmp_ndt_1; [L413] tmp_ndt_1 = __VERIFIER_nondet_int() [L414] COND FALSE !(\read(tmp_ndt_1)) [L425] COND TRUE t1_st == 0 [L426] int tmp_ndt_2; [L427] tmp_ndt_2 = __VERIFIER_nondet_int() [L428] COND FALSE !(\read(tmp_ndt_2)) [L439] COND TRUE t2_st == 0 [L440] int tmp_ndt_3; [L441] tmp_ndt_3 = __VERIFIER_nondet_int() [L442] COND FALSE !(\read(tmp_ndt_3)) [L453] COND TRUE t3_st == 0 [L454] int tmp_ndt_4; [L455] tmp_ndt_4 = __VERIFIER_nondet_int() [L456] COND FALSE !(\read(tmp_ndt_4)) [L467] COND TRUE t4_st == 0 [L468] int tmp_ndt_5; [L469] tmp_ndt_5 = __VERIFIER_nondet_int() [L470] COND FALSE !(\read(tmp_ndt_5)) ----- ----- class de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder.RCFGBacktranslator [?] ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2; [?] havoc main_#res;havoc main_~__retres1~6;havoc main_~__retres1~6;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; [?] havoc start_simulation_#t~ret12, start_simulation_#t~ret13, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; [?] assume 1 == ~m_i~0;~m_st~0 := 0; [?] assume 1 == ~t1_i~0;~t1_st~0 := 0; [?] assume 1 == ~t2_i~0;~t2_st~0 := 0; [?] assume 1 == ~t3_i~0;~t3_st~0 := 0; [?] assume 1 == ~t4_i~0;~t4_st~0 := 0; [?] assume !(0 == ~M_E~0); [?] assume !(0 == ~T1_E~0); [?] assume !(0 == ~T2_E~0); [?] assume !(0 == ~T3_E~0); [?] assume !(0 == ~T4_E~0); [?] assume !(0 == ~E_1~0); [?] assume !(0 == ~E_2~0); [?] assume !(0 == ~E_3~0); [?] assume !(0 == ~E_4~0); [?] havoc activate_threads_#t~ret6, activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; [?] assume !(1 == ~m_pc~0); [?] is_master_triggered_~__retres1~0 := 0; [?] is_master_triggered_#res := is_master_triggered_~__retres1~0; [?] activate_threads_#t~ret6 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret6;havoc activate_threads_#t~ret6; [?] assume !(0 != activate_threads_~tmp~1); [?] havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; [?] assume !(1 == ~t1_pc~0); [?] is_transmit1_triggered_~__retres1~1 := 0; [?] is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; [?] activate_threads_#t~ret7 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; [?] assume !(0 != activate_threads_~tmp___0~0); [?] havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; [?] assume !(1 == ~t2_pc~0); [?] is_transmit2_triggered_~__retres1~2 := 0; [?] is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; [?] activate_threads_#t~ret8 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; [?] assume !(0 != activate_threads_~tmp___1~0); [?] havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; [?] assume !(1 == ~t3_pc~0); [?] is_transmit3_triggered_~__retres1~3 := 0; [?] is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; [?] activate_threads_#t~ret9 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; [?] assume !(0 != activate_threads_~tmp___2~0); [?] havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; [?] assume !(1 == ~t4_pc~0); [?] is_transmit4_triggered_~__retres1~4 := 0; [?] is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; [?] activate_threads_#t~ret10 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; [?] assume !(0 != activate_threads_~tmp___3~0); [?] assume !(1 == ~M_E~0); [?] assume !(1 == ~T1_E~0); [?] assume !(1 == ~T2_E~0); [?] assume !(1 == ~T3_E~0); [?] assume !(1 == ~T4_E~0); [?] assume !(1 == ~E_1~0); [?] assume !(1 == ~E_2~0); [?] assume !(1 == ~E_3~0); [?] assume !(1 == ~E_4~0); [?] assume !false; [?] start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret0, eval_#t~nondet1, eval_~tmp_ndt_1~0, eval_#t~nondet2, eval_~tmp_ndt_2~0, eval_#t~nondet3, eval_~tmp_ndt_3~0, eval_#t~nondet4, eval_~tmp_ndt_4~0, eval_#t~nondet5, eval_~tmp_ndt_5~0, eval_~tmp~0;havoc eval_~tmp~0; [L15] ~m_pc~0 := 0; [L16] ~t1_pc~0 := 0; [L17] ~t2_pc~0 := 0; [L18] ~t3_pc~0 := 0; [L19] ~t4_pc~0 := 0; [L20] ~m_st~0 := 0; [L21] ~t1_st~0 := 0; [L22] ~t2_st~0 := 0; [L23] ~t3_st~0 := 0; [L24] ~t4_st~0 := 0; [L25] ~m_i~0 := 0; [L26] ~t1_i~0 := 0; [L27] ~t2_i~0 := 0; [L28] ~t3_i~0 := 0; [L29] ~t4_i~0 := 0; [L30] ~M_E~0 := 2; [L31] ~T1_E~0 := 2; [L32] ~T2_E~0 := 2; [L33] ~T3_E~0 := 2; [L34] ~T4_E~0 := 2; [L35] ~E_1~0 := 2; [L36] ~E_2~0 := 2; [L37] ~E_3~0 := 2; [L38] ~E_4~0 := 2; [?] havoc main_#res; [?] havoc main_~__retres1~6; [L811] havoc main_~__retres1~6; [L723] ~m_i~0 := 1; [L724] ~t1_i~0 := 1; [L725] ~t2_i~0 := 1; [L726] ~t3_i~0 := 1; [L727] ~t4_i~0 := 1; [L816] havoc start_simulation_#t~ret12, start_simulation_#t~ret13, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1; [L752] havoc start_simulation_~kernel_st~0; [L753] havoc start_simulation_~tmp~3; [L754] havoc start_simulation_~tmp___0~1; [L758] start_simulation_~kernel_st~0 := 0; [L331-L335] assume 1 == ~m_i~0; [L332] ~m_st~0 := 0; [L336-L340] assume 1 == ~t1_i~0; [L337] ~t1_st~0 := 0; [L341-L345] assume 1 == ~t2_i~0; [L342] ~t2_st~0 := 0; [L346-L350] assume 1 == ~t3_i~0; [L347] ~t3_st~0 := 0; [L351-L355] assume 1 == ~t4_i~0; [L352] ~t4_st~0 := 0; [L492-L496] assume !(0 == ~M_E~0); [L497-L501] assume !(0 == ~T1_E~0); [L502-L506] assume !(0 == ~T2_E~0); [L507-L511] assume !(0 == ~T3_E~0); [L512-L516] assume !(0 == ~T4_E~0); [L517-L521] assume !(0 == ~E_1~0); [L522-L526] assume !(0 == ~E_2~0); [L527-L531] assume !(0 == ~E_3~0); [L532-L536] assume !(0 == ~E_4~0); [L762] havoc activate_threads_#t~ret6, activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0; [L595] havoc activate_threads_~tmp~1; [L596] havoc activate_threads_~tmp___0~0; [L597] havoc activate_threads_~tmp___1~0; [L598] havoc activate_threads_~tmp___2~0; [L599] havoc activate_threads_~tmp___3~0; [L603] havoc is_master_triggered_#res; [L603] havoc is_master_triggered_~__retres1~0; [L225] havoc is_master_triggered_~__retres1~0; [L228-L237] assume !(1 == ~m_pc~0); [L238] is_master_triggered_~__retres1~0 := 0; [L240] is_master_triggered_#res := is_master_triggered_~__retres1~0; [L603] activate_threads_#t~ret6 := is_master_triggered_#res; [L603] activate_threads_~tmp~1 := activate_threads_#t~ret6; [L603] havoc activate_threads_#t~ret6; [L605-L609] assume !(0 != activate_threads_~tmp~1); [L611] havoc is_transmit1_triggered_#res; [L611] havoc is_transmit1_triggered_~__retres1~1; [L244] havoc is_transmit1_triggered_~__retres1~1; [L247-L256] assume !(1 == ~t1_pc~0); [L257] is_transmit1_triggered_~__retres1~1 := 0; [L259] is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; [L611] activate_threads_#t~ret7 := is_transmit1_triggered_#res; [L611] activate_threads_~tmp___0~0 := activate_threads_#t~ret7; [L611] havoc activate_threads_#t~ret7; [L613-L617] assume !(0 != activate_threads_~tmp___0~0); [L619] havoc is_transmit2_triggered_#res; [L619] havoc is_transmit2_triggered_~__retres1~2; [L263] havoc is_transmit2_triggered_~__retres1~2; [L266-L275] assume !(1 == ~t2_pc~0); [L276] is_transmit2_triggered_~__retres1~2 := 0; [L278] is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; [L619] activate_threads_#t~ret8 := is_transmit2_triggered_#res; [L619] activate_threads_~tmp___1~0 := activate_threads_#t~ret8; [L619] havoc activate_threads_#t~ret8; [L621-L625] assume !(0 != activate_threads_~tmp___1~0); [L627] havoc is_transmit3_triggered_#res; [L627] havoc is_transmit3_triggered_~__retres1~3; [L282] havoc is_transmit3_triggered_~__retres1~3; [L285-L294] assume !(1 == ~t3_pc~0); [L295] is_transmit3_triggered_~__retres1~3 := 0; [L297] is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; [L627] activate_threads_#t~ret9 := is_transmit3_triggered_#res; [L627] activate_threads_~tmp___2~0 := activate_threads_#t~ret9; [L627] havoc activate_threads_#t~ret9; [L629-L633] assume !(0 != activate_threads_~tmp___2~0); [L635] havoc is_transmit4_triggered_#res; [L635] havoc is_transmit4_triggered_~__retres1~4; [L301] havoc is_transmit4_triggered_~__retres1~4; [L304-L313] assume !(1 == ~t4_pc~0); [L314] is_transmit4_triggered_~__retres1~4 := 0; [L316] is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; [L635] activate_threads_#t~ret10 := is_transmit4_triggered_#res; [L635] activate_threads_~tmp___3~0 := activate_threads_#t~ret10; [L635] havoc activate_threads_#t~ret10; [L637-L641] assume !(0 != activate_threads_~tmp___3~0); [L545-L549] assume !(1 == ~M_E~0); [L550-L554] assume !(1 == ~T1_E~0); [L555-L559] assume !(1 == ~T2_E~0); [L560-L564] assume !(1 == ~T3_E~0); [L565-L569] assume !(1 == ~T4_E~0); [L570-L574] assume !(1 == ~E_1~0); [L575-L579] assume !(1 == ~E_2~0); [L580-L584] assume !(1 == ~E_3~0); [L585-L589] assume !(1 == ~E_4~0); [L766-L803] assume !false; [L769] start_simulation_~kernel_st~0 := 1; [L770] havoc eval_#t~ret0, eval_#t~nondet1, eval_~tmp_ndt_1~0, eval_#t~nondet2, eval_~tmp_ndt_2~0, eval_#t~nondet3, eval_~tmp_ndt_3~0, eval_#t~nondet4, eval_~tmp_ndt_4~0, eval_#t~nondet5, eval_~tmp_ndt_5~0, eval_~tmp~0; [L397] havoc eval_~tmp~0; ----- ----- class de.uni_freiburg.informatik.ultimate.boogie.preprocessor.BoogiePreprocessorBacktranslator [L15] ~m_pc~0 := 0; [L16] ~t1_pc~0 := 0; [L17] ~t2_pc~0 := 0; [L18] ~t3_pc~0 := 0; [L19] ~t4_pc~0 := 0; [L20] ~m_st~0 := 0; [L21] ~t1_st~0 := 0; [L22] ~t2_st~0 := 0; [L23] ~t3_st~0 := 0; [L24] ~t4_st~0 := 0; [L25] ~m_i~0 := 0; [L26] ~t1_i~0 := 0; [L27] ~t2_i~0 := 0; [L28] ~t3_i~0 := 0; [L29] ~t4_i~0 := 0; [L30] ~M_E~0 := 2; [L31] ~T1_E~0 := 2; [L32] ~T2_E~0 := 2; [L33] ~T3_E~0 := 2; [L34] ~T4_E~0 := 2; [L35] ~E_1~0 := 2; [L36] ~E_2~0 := 2; [L37] ~E_3~0 := 2; [L38] ~E_4~0 := 2; [?] havoc main_#res; [?] havoc main_~__retres1~6; [L811] havoc main_~__retres1~6; [L723] ~m_i~0 := 1; [L724] ~t1_i~0 := 1; [L725] ~t2_i~0 := 1; [L726] ~t3_i~0 := 1; [L727] ~t4_i~0 := 1; [L816] havoc start_simulation_#t~ret12, start_simulation_#t~ret13, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1; [L752] havoc start_simulation_~kernel_st~0; [L753] havoc start_simulation_~tmp~3; [L754] havoc start_simulation_~tmp___0~1; [L758] start_simulation_~kernel_st~0 := 0; [L331-L335] assume 1 == ~m_i~0; [L332] ~m_st~0 := 0; [L336-L340] assume 1 == ~t1_i~0; [L337] ~t1_st~0 := 0; [L341-L345] assume 1 == ~t2_i~0; [L342] ~t2_st~0 := 0; [L346-L350] assume 1 == ~t3_i~0; [L347] ~t3_st~0 := 0; [L351-L355] assume 1 == ~t4_i~0; [L352] ~t4_st~0 := 0; [L492-L496] assume !(0 == ~M_E~0); [L497-L501] assume !(0 == ~T1_E~0); [L502-L506] assume !(0 == ~T2_E~0); [L507-L511] assume !(0 == ~T3_E~0); [L512-L516] assume !(0 == ~T4_E~0); [L517-L521] assume !(0 == ~E_1~0); [L522-L526] assume !(0 == ~E_2~0); [L527-L531] assume !(0 == ~E_3~0); [L532-L536] assume !(0 == ~E_4~0); [L762] havoc activate_threads_#t~ret6, activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0; [L595] havoc activate_threads_~tmp~1; [L596] havoc activate_threads_~tmp___0~0; [L597] havoc activate_threads_~tmp___1~0; [L598] havoc activate_threads_~tmp___2~0; [L599] havoc activate_threads_~tmp___3~0; [L603] havoc is_master_triggered_#res; [L603] havoc is_master_triggered_~__retres1~0; [L225] havoc is_master_triggered_~__retres1~0; [L228-L237] assume !(1 == ~m_pc~0); [L238] is_master_triggered_~__retres1~0 := 0; [L240] is_master_triggered_#res := is_master_triggered_~__retres1~0; [L603] activate_threads_#t~ret6 := is_master_triggered_#res; [L603] activate_threads_~tmp~1 := activate_threads_#t~ret6; [L603] havoc activate_threads_#t~ret6; [L605-L609] assume !(0 != activate_threads_~tmp~1); [L611] havoc is_transmit1_triggered_#res; [L611] havoc is_transmit1_triggered_~__retres1~1; [L244] havoc is_transmit1_triggered_~__retres1~1; [L247-L256] assume !(1 == ~t1_pc~0); [L257] is_transmit1_triggered_~__retres1~1 := 0; [L259] is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; [L611] activate_threads_#t~ret7 := is_transmit1_triggered_#res; [L611] activate_threads_~tmp___0~0 := activate_threads_#t~ret7; [L611] havoc activate_threads_#t~ret7; [L613-L617] assume !(0 != activate_threads_~tmp___0~0); [L619] havoc is_transmit2_triggered_#res; [L619] havoc is_transmit2_triggered_~__retres1~2; [L263] havoc is_transmit2_triggered_~__retres1~2; [L266-L275] assume !(1 == ~t2_pc~0); [L276] is_transmit2_triggered_~__retres1~2 := 0; [L278] is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; [L619] activate_threads_#t~ret8 := is_transmit2_triggered_#res; [L619] activate_threads_~tmp___1~0 := activate_threads_#t~ret8; [L619] havoc activate_threads_#t~ret8; [L621-L625] assume !(0 != activate_threads_~tmp___1~0); [L627] havoc is_transmit3_triggered_#res; [L627] havoc is_transmit3_triggered_~__retres1~3; [L282] havoc is_transmit3_triggered_~__retres1~3; [L285-L294] assume !(1 == ~t3_pc~0); [L295] is_transmit3_triggered_~__retres1~3 := 0; [L297] is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; [L627] activate_threads_#t~ret9 := is_transmit3_triggered_#res; [L627] activate_threads_~tmp___2~0 := activate_threads_#t~ret9; [L627] havoc activate_threads_#t~ret9; [L629-L633] assume !(0 != activate_threads_~tmp___2~0); [L635] havoc is_transmit4_triggered_#res; [L635] havoc is_transmit4_triggered_~__retres1~4; [L301] havoc is_transmit4_triggered_~__retres1~4; [L304-L313] assume !(1 == ~t4_pc~0); [L314] is_transmit4_triggered_~__retres1~4 := 0; [L316] is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; [L635] activate_threads_#t~ret10 := is_transmit4_triggered_#res; [L635] activate_threads_~tmp___3~0 := activate_threads_#t~ret10; [L635] havoc activate_threads_#t~ret10; [L637-L641] assume !(0 != activate_threads_~tmp___3~0); [L545-L549] assume !(1 == ~M_E~0); [L550-L554] assume !(1 == ~T1_E~0); [L555-L559] assume !(1 == ~T2_E~0); [L560-L564] assume !(1 == ~T3_E~0); [L565-L569] assume !(1 == ~T4_E~0); [L570-L574] assume !(1 == ~E_1~0); [L575-L579] assume !(1 == ~E_2~0); [L580-L584] assume !(1 == ~E_3~0); [L585-L589] assume !(1 == ~E_4~0); [L766-L803] assume !false; [L769] start_simulation_~kernel_st~0 := 1; [L770] havoc eval_#t~ret0, eval_#t~nondet1, eval_~tmp_ndt_1~0, eval_#t~nondet2, eval_~tmp_ndt_2~0, eval_#t~nondet3, eval_~tmp_ndt_3~0, eval_#t~nondet4, eval_~tmp_ndt_4~0, eval_#t~nondet5, eval_~tmp_ndt_5~0, eval_~tmp~0; [L397] havoc eval_~tmp~0; [L15] ~m_pc~0 := 0; [L16] ~t1_pc~0 := 0; [L17] ~t2_pc~0 := 0; [L18] ~t3_pc~0 := 0; [L19] ~t4_pc~0 := 0; [L20] ~m_st~0 := 0; [L21] ~t1_st~0 := 0; [L22] ~t2_st~0 := 0; [L23] ~t3_st~0 := 0; [L24] ~t4_st~0 := 0; [L25] ~m_i~0 := 0; [L26] ~t1_i~0 := 0; [L27] ~t2_i~0 := 0; [L28] ~t3_i~0 := 0; [L29] ~t4_i~0 := 0; [L30] ~M_E~0 := 2; [L31] ~T1_E~0 := 2; [L32] ~T2_E~0 := 2; [L33] ~T3_E~0 := 2; [L34] ~T4_E~0 := 2; [L35] ~E_1~0 := 2; [L36] ~E_2~0 := 2; [L37] ~E_3~0 := 2; [L38] ~E_4~0 := 2; [?] havoc main_#res; [?] havoc main_~__retres1~6; [L811] havoc main_~__retres1~6; [L723] ~m_i~0 := 1; [L724] ~t1_i~0 := 1; [L725] ~t2_i~0 := 1; [L726] ~t3_i~0 := 1; [L727] ~t4_i~0 := 1; [L816] havoc start_simulation_#t~ret12, start_simulation_#t~ret13, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1; [L752] havoc start_simulation_~kernel_st~0; [L753] havoc start_simulation_~tmp~3; [L754] havoc start_simulation_~tmp___0~1; [L758] start_simulation_~kernel_st~0 := 0; [L331] COND TRUE 1 == ~m_i~0 [L332] ~m_st~0 := 0; [L336] COND TRUE 1 == ~t1_i~0 [L337] ~t1_st~0 := 0; [L341] COND TRUE 1 == ~t2_i~0 [L342] ~t2_st~0 := 0; [L346] COND TRUE 1 == ~t3_i~0 [L347] ~t3_st~0 := 0; [L351] COND TRUE 1 == ~t4_i~0 [L352] ~t4_st~0 := 0; [L492] COND FALSE !(0 == ~M_E~0) [L497] COND FALSE !(0 == ~T1_E~0) [L502] COND FALSE !(0 == ~T2_E~0) [L507] COND FALSE !(0 == ~T3_E~0) [L512] COND FALSE !(0 == ~T4_E~0) [L517] COND FALSE !(0 == ~E_1~0) [L522] COND FALSE !(0 == ~E_2~0) [L527] COND FALSE !(0 == ~E_3~0) [L532] COND FALSE !(0 == ~E_4~0) [L762] havoc activate_threads_#t~ret6, activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0; [L595] havoc activate_threads_~tmp~1; [L596] havoc activate_threads_~tmp___0~0; [L597] havoc activate_threads_~tmp___1~0; [L598] havoc activate_threads_~tmp___2~0; [L599] havoc activate_threads_~tmp___3~0; [L603] havoc is_master_triggered_#res; [L603] havoc is_master_triggered_~__retres1~0; [L225] havoc is_master_triggered_~__retres1~0; [L228] COND FALSE !(1 == ~m_pc~0) [L238] is_master_triggered_~__retres1~0 := 0; [L240] is_master_triggered_#res := is_master_triggered_~__retres1~0; [L603] activate_threads_#t~ret6 := is_master_triggered_#res; [L603] activate_threads_~tmp~1 := activate_threads_#t~ret6; [L603] havoc activate_threads_#t~ret6; [L605-L609] COND FALSE !(0 != activate_threads_~tmp~1) [L611] havoc is_transmit1_triggered_#res; [L611] havoc is_transmit1_triggered_~__retres1~1; [L244] havoc is_transmit1_triggered_~__retres1~1; [L247] COND FALSE !(1 == ~t1_pc~0) [L257] is_transmit1_triggered_~__retres1~1 := 0; [L259] is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; [L611] activate_threads_#t~ret7 := is_transmit1_triggered_#res; [L611] activate_threads_~tmp___0~0 := activate_threads_#t~ret7; [L611] havoc activate_threads_#t~ret7; [L613-L617] COND FALSE !(0 != activate_threads_~tmp___0~0) [L619] havoc is_transmit2_triggered_#res; [L619] havoc is_transmit2_triggered_~__retres1~2; [L263] havoc is_transmit2_triggered_~__retres1~2; [L266] COND FALSE !(1 == ~t2_pc~0) [L276] is_transmit2_triggered_~__retres1~2 := 0; [L278] is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; [L619] activate_threads_#t~ret8 := is_transmit2_triggered_#res; [L619] activate_threads_~tmp___1~0 := activate_threads_#t~ret8; [L619] havoc activate_threads_#t~ret8; [L621-L625] COND FALSE !(0 != activate_threads_~tmp___1~0) [L627] havoc is_transmit3_triggered_#res; [L627] havoc is_transmit3_triggered_~__retres1~3; [L282] havoc is_transmit3_triggered_~__retres1~3; [L285] COND FALSE !(1 == ~t3_pc~0) [L295] is_transmit3_triggered_~__retres1~3 := 0; [L297] is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; [L627] activate_threads_#t~ret9 := is_transmit3_triggered_#res; [L627] activate_threads_~tmp___2~0 := activate_threads_#t~ret9; [L627] havoc activate_threads_#t~ret9; [L629-L633] COND FALSE !(0 != activate_threads_~tmp___2~0) [L635] havoc is_transmit4_triggered_#res; [L635] havoc is_transmit4_triggered_~__retres1~4; [L301] havoc is_transmit4_triggered_~__retres1~4; [L304] COND FALSE !(1 == ~t4_pc~0) [L314] is_transmit4_triggered_~__retres1~4 := 0; [L316] is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; [L635] activate_threads_#t~ret10 := is_transmit4_triggered_#res; [L635] activate_threads_~tmp___3~0 := activate_threads_#t~ret10; [L635] havoc activate_threads_#t~ret10; [L637-L641] COND FALSE !(0 != activate_threads_~tmp___3~0) [L545] COND FALSE !(1 == ~M_E~0) [L550] COND FALSE !(1 == ~T1_E~0) [L555] COND FALSE !(1 == ~T2_E~0) [L560] COND FALSE !(1 == ~T3_E~0) [L565] COND FALSE !(1 == ~T4_E~0) [L570] COND FALSE !(1 == ~E_1~0) [L575] COND FALSE !(1 == ~E_2~0) [L580] COND FALSE !(1 == ~E_3~0) [L585] COND FALSE !(1 == ~E_4~0) [L766-L803] COND FALSE !(false) [L769] start_simulation_~kernel_st~0 := 1; [L770] havoc eval_#t~ret0, eval_#t~nondet1, eval_~tmp_ndt_1~0, eval_#t~nondet2, eval_~tmp_ndt_2~0, eval_#t~nondet3, eval_~tmp_ndt_3~0, eval_#t~nondet4, eval_~tmp_ndt_4~0, eval_#t~nondet5, eval_~tmp_ndt_5~0, eval_~tmp~0; [L397] havoc eval_~tmp~0; ----- ----- class de.uni_freiburg.informatik.ultimate.boogie.procedureinliner.backtranslation.InlinerBacktranslator [L15] ~m_pc~0 := 0; [L16] ~t1_pc~0 := 0; [L17] ~t2_pc~0 := 0; [L18] ~t3_pc~0 := 0; [L19] ~t4_pc~0 := 0; [L20] ~m_st~0 := 0; [L21] ~t1_st~0 := 0; [L22] ~t2_st~0 := 0; [L23] ~t3_st~0 := 0; [L24] ~t4_st~0 := 0; [L25] ~m_i~0 := 0; [L26] ~t1_i~0 := 0; [L27] ~t2_i~0 := 0; [L28] ~t3_i~0 := 0; [L29] ~t4_i~0 := 0; [L30] ~M_E~0 := 2; [L31] ~T1_E~0 := 2; [L32] ~T2_E~0 := 2; [L33] ~T3_E~0 := 2; [L34] ~T4_E~0 := 2; [L35] ~E_1~0 := 2; [L36] ~E_2~0 := 2; [L37] ~E_3~0 := 2; [L38] ~E_4~0 := 2; [?] havoc main_#res; [?] havoc main_~__retres1~6; [L811] havoc main_~__retres1~6; [L723] ~m_i~0 := 1; [L724] ~t1_i~0 := 1; [L725] ~t2_i~0 := 1; [L726] ~t3_i~0 := 1; [L727] ~t4_i~0 := 1; [L816] havoc start_simulation_#t~ret12, start_simulation_#t~ret13, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1; [L752] havoc start_simulation_~kernel_st~0; [L753] havoc start_simulation_~tmp~3; [L754] havoc start_simulation_~tmp___0~1; [L758] start_simulation_~kernel_st~0 := 0; [L331] COND TRUE 1 == ~m_i~0 [L332] ~m_st~0 := 0; [L336] COND TRUE 1 == ~t1_i~0 [L337] ~t1_st~0 := 0; [L341] COND TRUE 1 == ~t2_i~0 [L342] ~t2_st~0 := 0; [L346] COND TRUE 1 == ~t3_i~0 [L347] ~t3_st~0 := 0; [L351] COND TRUE 1 == ~t4_i~0 [L352] ~t4_st~0 := 0; [L492] COND FALSE !(0 == ~M_E~0) [L497] COND FALSE !(0 == ~T1_E~0) [L502] COND FALSE !(0 == ~T2_E~0) [L507] COND FALSE !(0 == ~T3_E~0) [L512] COND FALSE !(0 == ~T4_E~0) [L517] COND FALSE !(0 == ~E_1~0) [L522] COND FALSE !(0 == ~E_2~0) [L527] COND FALSE !(0 == ~E_3~0) [L532] COND FALSE !(0 == ~E_4~0) [L762] havoc activate_threads_#t~ret6, activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0; [L595] havoc activate_threads_~tmp~1; [L596] havoc activate_threads_~tmp___0~0; [L597] havoc activate_threads_~tmp___1~0; [L598] havoc activate_threads_~tmp___2~0; [L599] havoc activate_threads_~tmp___3~0; [L603] havoc is_master_triggered_#res; [L603] havoc is_master_triggered_~__retres1~0; [L225] havoc is_master_triggered_~__retres1~0; [L228] COND FALSE !(1 == ~m_pc~0) [L238] is_master_triggered_~__retres1~0 := 0; [L240] is_master_triggered_#res := is_master_triggered_~__retres1~0; [L603] activate_threads_#t~ret6 := is_master_triggered_#res; [L603] activate_threads_~tmp~1 := activate_threads_#t~ret6; [L603] havoc activate_threads_#t~ret6; [L605-L609] COND FALSE !(0 != activate_threads_~tmp~1) [L611] havoc is_transmit1_triggered_#res; [L611] havoc is_transmit1_triggered_~__retres1~1; [L244] havoc is_transmit1_triggered_~__retres1~1; [L247] COND FALSE !(1 == ~t1_pc~0) [L257] is_transmit1_triggered_~__retres1~1 := 0; [L259] is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; [L611] activate_threads_#t~ret7 := is_transmit1_triggered_#res; [L611] activate_threads_~tmp___0~0 := activate_threads_#t~ret7; [L611] havoc activate_threads_#t~ret7; [L613-L617] COND FALSE !(0 != activate_threads_~tmp___0~0) [L619] havoc is_transmit2_triggered_#res; [L619] havoc is_transmit2_triggered_~__retres1~2; [L263] havoc is_transmit2_triggered_~__retres1~2; [L266] COND FALSE !(1 == ~t2_pc~0) [L276] is_transmit2_triggered_~__retres1~2 := 0; [L278] is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; [L619] activate_threads_#t~ret8 := is_transmit2_triggered_#res; [L619] activate_threads_~tmp___1~0 := activate_threads_#t~ret8; [L619] havoc activate_threads_#t~ret8; [L621-L625] COND FALSE !(0 != activate_threads_~tmp___1~0) [L627] havoc is_transmit3_triggered_#res; [L627] havoc is_transmit3_triggered_~__retres1~3; [L282] havoc is_transmit3_triggered_~__retres1~3; [L285] COND FALSE !(1 == ~t3_pc~0) [L295] is_transmit3_triggered_~__retres1~3 := 0; [L297] is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; [L627] activate_threads_#t~ret9 := is_transmit3_triggered_#res; [L627] activate_threads_~tmp___2~0 := activate_threads_#t~ret9; [L627] havoc activate_threads_#t~ret9; [L629-L633] COND FALSE !(0 != activate_threads_~tmp___2~0) [L635] havoc is_transmit4_triggered_#res; [L635] havoc is_transmit4_triggered_~__retres1~4; [L301] havoc is_transmit4_triggered_~__retres1~4; [L304] COND FALSE !(1 == ~t4_pc~0) [L314] is_transmit4_triggered_~__retres1~4 := 0; [L316] is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; [L635] activate_threads_#t~ret10 := is_transmit4_triggered_#res; [L635] activate_threads_~tmp___3~0 := activate_threads_#t~ret10; [L635] havoc activate_threads_#t~ret10; [L637-L641] COND FALSE !(0 != activate_threads_~tmp___3~0) [L545] COND FALSE !(1 == ~M_E~0) [L550] COND FALSE !(1 == ~T1_E~0) [L555] COND FALSE !(1 == ~T2_E~0) [L560] COND FALSE !(1 == ~T3_E~0) [L565] COND FALSE !(1 == ~T4_E~0) [L570] COND FALSE !(1 == ~E_1~0) [L575] COND FALSE !(1 == ~E_2~0) [L580] COND FALSE !(1 == ~E_3~0) [L585] COND FALSE !(1 == ~E_4~0) [L766-L803] COND FALSE !(false) [L769] start_simulation_~kernel_st~0 := 1; [L770] havoc eval_#t~ret0, eval_#t~nondet1, eval_~tmp_ndt_1~0, eval_#t~nondet2, eval_~tmp_ndt_2~0, eval_#t~nondet3, eval_~tmp_ndt_3~0, eval_#t~nondet4, eval_~tmp_ndt_4~0, eval_#t~nondet5, eval_~tmp_ndt_5~0, eval_~tmp~0; [L397] havoc eval_~tmp~0; [L15] ~m_pc~0 := 0; [L16] ~t1_pc~0 := 0; [L17] ~t2_pc~0 := 0; [L18] ~t3_pc~0 := 0; [L19] ~t4_pc~0 := 0; [L20] ~m_st~0 := 0; [L21] ~t1_st~0 := 0; [L22] ~t2_st~0 := 0; [L23] ~t3_st~0 := 0; [L24] ~t4_st~0 := 0; [L25] ~m_i~0 := 0; [L26] ~t1_i~0 := 0; [L27] ~t2_i~0 := 0; [L28] ~t3_i~0 := 0; [L29] ~t4_i~0 := 0; [L30] ~M_E~0 := 2; [L31] ~T1_E~0 := 2; [L32] ~T2_E~0 := 2; [L33] ~T3_E~0 := 2; [L34] ~T4_E~0 := 2; [L35] ~E_1~0 := 2; [L36] ~E_2~0 := 2; [L37] ~E_3~0 := 2; [L38] ~E_4~0 := 2; [L811] havoc ~__retres1~6; [L723] ~m_i~0 := 1; [L724] ~t1_i~0 := 1; [L725] ~t2_i~0 := 1; [L726] ~t3_i~0 := 1; [L727] ~t4_i~0 := 1; [L752] havoc ~kernel_st~0; [L753] havoc ~tmp~3; [L754] havoc ~tmp___0~1; [L758] ~kernel_st~0 := 0; [L331] COND TRUE 1 == ~m_i~0 [L332] ~m_st~0 := 0; [L336] COND TRUE 1 == ~t1_i~0 [L337] ~t1_st~0 := 0; [L341] COND TRUE 1 == ~t2_i~0 [L342] ~t2_st~0 := 0; [L346] COND TRUE 1 == ~t3_i~0 [L347] ~t3_st~0 := 0; [L351] COND TRUE 1 == ~t4_i~0 [L352] ~t4_st~0 := 0; [L492] COND FALSE !(0 == ~M_E~0) [L497] COND FALSE !(0 == ~T1_E~0) [L502] COND FALSE !(0 == ~T2_E~0) [L507] COND FALSE !(0 == ~T3_E~0) [L512] COND FALSE !(0 == ~T4_E~0) [L517] COND FALSE !(0 == ~E_1~0) [L522] COND FALSE !(0 == ~E_2~0) [L527] COND FALSE !(0 == ~E_3~0) [L532] COND FALSE !(0 == ~E_4~0) [L595] havoc ~tmp~1; [L596] havoc ~tmp___0~0; [L597] havoc ~tmp___1~0; [L598] havoc ~tmp___2~0; [L599] havoc ~tmp___3~0; [L225] havoc ~__retres1~0; [L228] COND FALSE !(1 == ~m_pc~0) [L238] ~__retres1~0 := 0; [L240] #res := ~__retres1~0; [L603] ~tmp~1 := #t~ret6; [L603] havoc #t~ret6; [L605-L609] COND FALSE !(0 != ~tmp~1) [L244] havoc ~__retres1~1; [L247] COND FALSE !(1 == ~t1_pc~0) [L257] ~__retres1~1 := 0; [L259] #res := ~__retres1~1; [L611] ~tmp___0~0 := #t~ret7; [L611] havoc #t~ret7; [L613-L617] COND FALSE !(0 != ~tmp___0~0) [L263] havoc ~__retres1~2; [L266] COND FALSE !(1 == ~t2_pc~0) [L276] ~__retres1~2 := 0; [L278] #res := ~__retres1~2; [L619] ~tmp___1~0 := #t~ret8; [L619] havoc #t~ret8; [L621-L625] COND FALSE !(0 != ~tmp___1~0) [L282] havoc ~__retres1~3; [L285] COND FALSE !(1 == ~t3_pc~0) [L295] ~__retres1~3 := 0; [L297] #res := ~__retres1~3; [L627] ~tmp___2~0 := #t~ret9; [L627] havoc #t~ret9; [L629-L633] COND FALSE !(0 != ~tmp___2~0) [L301] havoc ~__retres1~4; [L304] COND FALSE !(1 == ~t4_pc~0) [L314] ~__retres1~4 := 0; [L316] #res := ~__retres1~4; [L635] ~tmp___3~0 := #t~ret10; [L635] havoc #t~ret10; [L637-L641] COND FALSE !(0 != ~tmp___3~0) [L545] COND FALSE !(1 == ~M_E~0) [L550] COND FALSE !(1 == ~T1_E~0) [L555] COND FALSE !(1 == ~T2_E~0) [L560] COND FALSE !(1 == ~T3_E~0) [L565] COND FALSE !(1 == ~T4_E~0) [L570] COND FALSE !(1 == ~E_1~0) [L575] COND FALSE !(1 == ~E_2~0) [L580] COND FALSE !(1 == ~E_3~0) [L585] COND FALSE !(1 == ~E_4~0) [L766-L803] COND FALSE !(false) [L769] ~kernel_st~0 := 1; [L397] havoc ~tmp~0; ----- ----- class de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.CACSL2BoogieBacktranslator [L15] ~m_pc~0 := 0; [L16] ~t1_pc~0 := 0; [L17] ~t2_pc~0 := 0; [L18] ~t3_pc~0 := 0; [L19] ~t4_pc~0 := 0; [L20] ~m_st~0 := 0; [L21] ~t1_st~0 := 0; [L22] ~t2_st~0 := 0; [L23] ~t3_st~0 := 0; [L24] ~t4_st~0 := 0; [L25] ~m_i~0 := 0; [L26] ~t1_i~0 := 0; [L27] ~t2_i~0 := 0; [L28] ~t3_i~0 := 0; [L29] ~t4_i~0 := 0; [L30] ~M_E~0 := 2; [L31] ~T1_E~0 := 2; [L32] ~T2_E~0 := 2; [L33] ~T3_E~0 := 2; [L34] ~T4_E~0 := 2; [L35] ~E_1~0 := 2; [L36] ~E_2~0 := 2; [L37] ~E_3~0 := 2; [L38] ~E_4~0 := 2; [L811] havoc ~__retres1~6; [L723] ~m_i~0 := 1; [L724] ~t1_i~0 := 1; [L725] ~t2_i~0 := 1; [L726] ~t3_i~0 := 1; [L727] ~t4_i~0 := 1; [L752] havoc ~kernel_st~0; [L753] havoc ~tmp~3; [L754] havoc ~tmp___0~1; [L758] ~kernel_st~0 := 0; [L331] COND TRUE 1 == ~m_i~0 [L332] ~m_st~0 := 0; [L336] COND TRUE 1 == ~t1_i~0 [L337] ~t1_st~0 := 0; [L341] COND TRUE 1 == ~t2_i~0 [L342] ~t2_st~0 := 0; [L346] COND TRUE 1 == ~t3_i~0 [L347] ~t3_st~0 := 0; [L351] COND TRUE 1 == ~t4_i~0 [L352] ~t4_st~0 := 0; [L492] COND FALSE !(0 == ~M_E~0) [L497] COND FALSE !(0 == ~T1_E~0) [L502] COND FALSE !(0 == ~T2_E~0) [L507] COND FALSE !(0 == ~T3_E~0) [L512] COND FALSE !(0 == ~T4_E~0) [L517] COND FALSE !(0 == ~E_1~0) [L522] COND FALSE !(0 == ~E_2~0) [L527] COND FALSE !(0 == ~E_3~0) [L532] COND FALSE !(0 == ~E_4~0) [L595] havoc ~tmp~1; [L596] havoc ~tmp___0~0; [L597] havoc ~tmp___1~0; [L598] havoc ~tmp___2~0; [L599] havoc ~tmp___3~0; [L225] havoc ~__retres1~0; [L228] COND FALSE !(1 == ~m_pc~0) [L238] ~__retres1~0 := 0; [L240] #res := ~__retres1~0; [L603] ~tmp~1 := #t~ret6; [L603] havoc #t~ret6; [L605-L609] COND FALSE !(0 != ~tmp~1) [L244] havoc ~__retres1~1; [L247] COND FALSE !(1 == ~t1_pc~0) [L257] ~__retres1~1 := 0; [L259] #res := ~__retres1~1; [L611] ~tmp___0~0 := #t~ret7; [L611] havoc #t~ret7; [L613-L617] COND FALSE !(0 != ~tmp___0~0) [L263] havoc ~__retres1~2; [L266] COND FALSE !(1 == ~t2_pc~0) [L276] ~__retres1~2 := 0; [L278] #res := ~__retres1~2; [L619] ~tmp___1~0 := #t~ret8; [L619] havoc #t~ret8; [L621-L625] COND FALSE !(0 != ~tmp___1~0) [L282] havoc ~__retres1~3; [L285] COND FALSE !(1 == ~t3_pc~0) [L295] ~__retres1~3 := 0; [L297] #res := ~__retres1~3; [L627] ~tmp___2~0 := #t~ret9; [L627] havoc #t~ret9; [L629-L633] COND FALSE !(0 != ~tmp___2~0) [L301] havoc ~__retres1~4; [L304] COND FALSE !(1 == ~t4_pc~0) [L314] ~__retres1~4 := 0; [L316] #res := ~__retres1~4; [L635] ~tmp___3~0 := #t~ret10; [L635] havoc #t~ret10; [L637-L641] COND FALSE !(0 != ~tmp___3~0) [L545] COND FALSE !(1 == ~M_E~0) [L550] COND FALSE !(1 == ~T1_E~0) [L555] COND FALSE !(1 == ~T2_E~0) [L560] COND FALSE !(1 == ~T3_E~0) [L565] COND FALSE !(1 == ~T4_E~0) [L570] COND FALSE !(1 == ~E_1~0) [L575] COND FALSE !(1 == ~E_2~0) [L580] COND FALSE !(1 == ~E_3~0) [L585] COND FALSE !(1 == ~E_4~0) [L766-L803] COND FALSE !(false) [L769] ~kernel_st~0 := 1; [L397] havoc ~tmp~0; [L15] int m_pc = 0; [L16] int t1_pc = 0; [L17] int t2_pc = 0; [L18] int t3_pc = 0; [L19] int t4_pc = 0; [L20] int m_st ; [L21] int t1_st ; [L22] int t2_st ; [L23] int t3_st ; [L24] int t4_st ; [L25] int m_i ; [L26] int t1_i ; [L27] int t2_i ; [L28] int t3_i ; [L29] int t4_i ; [L30] int M_E = 2; [L31] int T1_E = 2; [L32] int T2_E = 2; [L33] int T3_E = 2; [L34] int T4_E = 2; [L35] int E_1 = 2; [L36] int E_2 = 2; [L37] int E_3 = 2; [L38] int E_4 = 2; [L811] int __retres1 ; [L723] m_i = 1 [L724] t1_i = 1 [L725] t2_i = 1 [L726] t3_i = 1 [L727] t4_i = 1 [L752] int kernel_st ; [L753] int tmp ; [L754] int tmp___0 ; [L758] kernel_st = 0 [L331] COND TRUE m_i == 1 [L332] m_st = 0 [L336] COND TRUE t1_i == 1 [L337] t1_st = 0 [L341] COND TRUE t2_i == 1 [L342] t2_st = 0 [L346] COND TRUE t3_i == 1 [L347] t3_st = 0 [L351] COND TRUE t4_i == 1 [L352] t4_st = 0 [L492] COND FALSE !(M_E == 0) [L497] COND FALSE !(T1_E == 0) [L502] COND FALSE !(T2_E == 0) [L507] COND FALSE !(T3_E == 0) [L512] COND FALSE !(T4_E == 0) [L517] COND FALSE !(E_1 == 0) [L522] COND FALSE !(E_2 == 0) [L527] COND FALSE !(E_3 == 0) [L532] COND FALSE !(E_4 == 0) [L595] int tmp ; [L596] int tmp___0 ; [L597] int tmp___1 ; [L598] int tmp___2 ; [L599] int tmp___3 ; [L225] int __retres1 ; [L228] COND FALSE !(m_pc == 1) [L238] __retres1 = 0 [L240] return (__retres1); [L603] tmp = is_master_triggered() [L605] COND FALSE !(\read(tmp)) [L244] int __retres1 ; [L247] COND FALSE !(t1_pc == 1) [L257] __retres1 = 0 [L259] return (__retres1); [L611] tmp___0 = is_transmit1_triggered() [L613] COND FALSE !(\read(tmp___0)) [L263] int __retres1 ; [L266] COND FALSE !(t2_pc == 1) [L276] __retres1 = 0 [L278] return (__retres1); [L619] tmp___1 = is_transmit2_triggered() [L621] COND FALSE !(\read(tmp___1)) [L282] int __retres1 ; [L285] COND FALSE !(t3_pc == 1) [L295] __retres1 = 0 [L297] return (__retres1); [L627] tmp___2 = is_transmit3_triggered() [L629] COND FALSE !(\read(tmp___2)) [L301] int __retres1 ; [L304] COND FALSE !(t4_pc == 1) [L314] __retres1 = 0 [L316] return (__retres1); [L635] tmp___3 = is_transmit4_triggered() [L637] COND FALSE !(\read(tmp___3)) [L545] COND FALSE !(M_E == 1) [L550] COND FALSE !(T1_E == 1) [L555] COND FALSE !(T2_E == 1) [L560] COND FALSE !(T3_E == 1) [L565] COND FALSE !(T4_E == 1) [L570] COND FALSE !(E_1 == 1) [L575] COND FALSE !(E_2 == 1) [L580] COND FALSE !(E_3 == 1) [L585] COND FALSE !(E_4 == 1) [L766] COND TRUE 1 [L769] kernel_st = 1 [L397] int tmp ; ----- ----- class de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder.RCFGBacktranslator [?] assume !false; [?] havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; [?] assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; [?] exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; [?] eval_#t~ret0 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret0;havoc eval_#t~ret0; [?] assume 0 != eval_~tmp~0; [?] assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0;eval_~tmp_ndt_1~0 := eval_#t~nondet1;havoc eval_#t~nondet1; [?] assume !(0 != eval_~tmp_ndt_1~0); [?] assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0;eval_~tmp_ndt_2~0 := eval_#t~nondet2;havoc eval_#t~nondet2; [?] assume !(0 != eval_~tmp_ndt_2~0); [?] assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0;eval_~tmp_ndt_3~0 := eval_#t~nondet3;havoc eval_#t~nondet3; [?] assume !(0 != eval_~tmp_ndt_3~0); [?] assume 0 == ~t3_st~0;havoc eval_~tmp_ndt_4~0;eval_~tmp_ndt_4~0 := eval_#t~nondet4;havoc eval_#t~nondet4; [?] assume !(0 != eval_~tmp_ndt_4~0); [?] assume 0 == ~t4_st~0;havoc eval_~tmp_ndt_5~0;eval_~tmp_ndt_5~0 := eval_#t~nondet5;havoc eval_#t~nondet5; [?] assume !(0 != eval_~tmp_ndt_5~0); [L401-L481] assume !false; [L404] havoc exists_runnable_thread_#res; [L404] havoc exists_runnable_thread_~__retres1~5; [L361] havoc exists_runnable_thread_~__retres1~5; [L364-L389] assume 0 == ~m_st~0; [L365] exists_runnable_thread_~__retres1~5 := 1; [L392] exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; [L404] eval_#t~ret0 := exists_runnable_thread_#res; [L404] eval_~tmp~0 := eval_#t~ret0; [L404] havoc eval_#t~ret0; [L406-L410] assume 0 != eval_~tmp~0; [L411-L424] assume 0 == ~m_st~0; [L412] havoc eval_~tmp_ndt_1~0; [L413] eval_~tmp_ndt_1~0 := eval_#t~nondet1; [L413] havoc eval_#t~nondet1; [L414-L421] assume !(0 != eval_~tmp_ndt_1~0); [L425-L438] assume 0 == ~t1_st~0; [L426] havoc eval_~tmp_ndt_2~0; [L427] eval_~tmp_ndt_2~0 := eval_#t~nondet2; [L427] havoc eval_#t~nondet2; [L428-L435] assume !(0 != eval_~tmp_ndt_2~0); [L439-L452] assume 0 == ~t2_st~0; [L440] havoc eval_~tmp_ndt_3~0; [L441] eval_~tmp_ndt_3~0 := eval_#t~nondet3; [L441] havoc eval_#t~nondet3; [L442-L449] assume !(0 != eval_~tmp_ndt_3~0); [L453-L466] assume 0 == ~t3_st~0; [L454] havoc eval_~tmp_ndt_4~0; [L455] eval_~tmp_ndt_4~0 := eval_#t~nondet4; [L455] havoc eval_#t~nondet4; [L456-L463] assume !(0 != eval_~tmp_ndt_4~0); [L467-L480] assume 0 == ~t4_st~0; [L468] havoc eval_~tmp_ndt_5~0; [L469] eval_~tmp_ndt_5~0 := eval_#t~nondet5; [L469] havoc eval_#t~nondet5; [L470-L477] assume !(0 != eval_~tmp_ndt_5~0); ----- ----- class de.uni_freiburg.informatik.ultimate.boogie.preprocessor.BoogiePreprocessorBacktranslator [L401-L481] assume !false; [L404] havoc exists_runnable_thread_#res; [L404] havoc exists_runnable_thread_~__retres1~5; [L361] havoc exists_runnable_thread_~__retres1~5; [L364-L389] assume 0 == ~m_st~0; [L365] exists_runnable_thread_~__retres1~5 := 1; [L392] exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; [L404] eval_#t~ret0 := exists_runnable_thread_#res; [L404] eval_~tmp~0 := eval_#t~ret0; [L404] havoc eval_#t~ret0; [L406-L410] assume 0 != eval_~tmp~0; [L411-L424] assume 0 == ~m_st~0; [L412] havoc eval_~tmp_ndt_1~0; [L413] eval_~tmp_ndt_1~0 := eval_#t~nondet1; [L413] havoc eval_#t~nondet1; [L414-L421] assume !(0 != eval_~tmp_ndt_1~0); [L425-L438] assume 0 == ~t1_st~0; [L426] havoc eval_~tmp_ndt_2~0; [L427] eval_~tmp_ndt_2~0 := eval_#t~nondet2; [L427] havoc eval_#t~nondet2; [L428-L435] assume !(0 != eval_~tmp_ndt_2~0); [L439-L452] assume 0 == ~t2_st~0; [L440] havoc eval_~tmp_ndt_3~0; [L441] eval_~tmp_ndt_3~0 := eval_#t~nondet3; [L441] havoc eval_#t~nondet3; [L442-L449] assume !(0 != eval_~tmp_ndt_3~0); [L453-L466] assume 0 == ~t3_st~0; [L454] havoc eval_~tmp_ndt_4~0; [L455] eval_~tmp_ndt_4~0 := eval_#t~nondet4; [L455] havoc eval_#t~nondet4; [L456-L463] assume !(0 != eval_~tmp_ndt_4~0); [L467-L480] assume 0 == ~t4_st~0; [L468] havoc eval_~tmp_ndt_5~0; [L469] eval_~tmp_ndt_5~0 := eval_#t~nondet5; [L469] havoc eval_#t~nondet5; [L470-L477] assume !(0 != eval_~tmp_ndt_5~0); [L401-L481] COND FALSE !(false) [L404] havoc exists_runnable_thread_#res; [L404] havoc exists_runnable_thread_~__retres1~5; [L361] havoc exists_runnable_thread_~__retres1~5; [L364] COND TRUE 0 == ~m_st~0 [L365] exists_runnable_thread_~__retres1~5 := 1; [L392] exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; [L404] eval_#t~ret0 := exists_runnable_thread_#res; [L404] eval_~tmp~0 := eval_#t~ret0; [L404] havoc eval_#t~ret0; [L406-L410] COND TRUE 0 != eval_~tmp~0 [L411] COND TRUE 0 == ~m_st~0 [L412] havoc eval_~tmp_ndt_1~0; [L413] eval_~tmp_ndt_1~0 := eval_#t~nondet1; [L413] havoc eval_#t~nondet1; [L414-L421] COND FALSE !(0 != eval_~tmp_ndt_1~0) [L425] COND TRUE 0 == ~t1_st~0 [L426] havoc eval_~tmp_ndt_2~0; [L427] eval_~tmp_ndt_2~0 := eval_#t~nondet2; [L427] havoc eval_#t~nondet2; [L428-L435] COND FALSE !(0 != eval_~tmp_ndt_2~0) [L439] COND TRUE 0 == ~t2_st~0 [L440] havoc eval_~tmp_ndt_3~0; [L441] eval_~tmp_ndt_3~0 := eval_#t~nondet3; [L441] havoc eval_#t~nondet3; [L442-L449] COND FALSE !(0 != eval_~tmp_ndt_3~0) [L453] COND TRUE 0 == ~t3_st~0 [L454] havoc eval_~tmp_ndt_4~0; [L455] eval_~tmp_ndt_4~0 := eval_#t~nondet4; [L455] havoc eval_#t~nondet4; [L456-L463] COND FALSE !(0 != eval_~tmp_ndt_4~0) [L467] COND TRUE 0 == ~t4_st~0 [L468] havoc eval_~tmp_ndt_5~0; [L469] eval_~tmp_ndt_5~0 := eval_#t~nondet5; [L469] havoc eval_#t~nondet5; [L470-L477] COND FALSE !(0 != eval_~tmp_ndt_5~0) ----- ----- class de.uni_freiburg.informatik.ultimate.boogie.procedureinliner.backtranslation.InlinerBacktranslator [L401-L481] COND FALSE !(false) [L404] havoc exists_runnable_thread_#res; [L404] havoc exists_runnable_thread_~__retres1~5; [L361] havoc exists_runnable_thread_~__retres1~5; [L364] COND TRUE 0 == ~m_st~0 [L365] exists_runnable_thread_~__retres1~5 := 1; [L392] exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; [L404] eval_#t~ret0 := exists_runnable_thread_#res; [L404] eval_~tmp~0 := eval_#t~ret0; [L404] havoc eval_#t~ret0; [L406-L410] COND TRUE 0 != eval_~tmp~0 [L411] COND TRUE 0 == ~m_st~0 [L412] havoc eval_~tmp_ndt_1~0; [L413] eval_~tmp_ndt_1~0 := eval_#t~nondet1; [L413] havoc eval_#t~nondet1; [L414-L421] COND FALSE !(0 != eval_~tmp_ndt_1~0) [L425] COND TRUE 0 == ~t1_st~0 [L426] havoc eval_~tmp_ndt_2~0; [L427] eval_~tmp_ndt_2~0 := eval_#t~nondet2; [L427] havoc eval_#t~nondet2; [L428-L435] COND FALSE !(0 != eval_~tmp_ndt_2~0) [L439] COND TRUE 0 == ~t2_st~0 [L440] havoc eval_~tmp_ndt_3~0; [L441] eval_~tmp_ndt_3~0 := eval_#t~nondet3; [L441] havoc eval_#t~nondet3; [L442-L449] COND FALSE !(0 != eval_~tmp_ndt_3~0) [L453] COND TRUE 0 == ~t3_st~0 [L454] havoc eval_~tmp_ndt_4~0; [L455] eval_~tmp_ndt_4~0 := eval_#t~nondet4; [L455] havoc eval_#t~nondet4; [L456-L463] COND FALSE !(0 != eval_~tmp_ndt_4~0) [L467] COND TRUE 0 == ~t4_st~0 [L468] havoc eval_~tmp_ndt_5~0; [L469] eval_~tmp_ndt_5~0 := eval_#t~nondet5; [L469] havoc eval_#t~nondet5; [L470-L477] COND FALSE !(0 != eval_~tmp_ndt_5~0) [L401-L481] COND FALSE !(false) [L361] havoc ~__retres1~5; [L364] COND TRUE 0 == ~m_st~0 [L365] ~__retres1~5 := 1; [L392] #res := ~__retres1~5; [L404] ~tmp~0 := #t~ret0; [L404] havoc #t~ret0; [L406-L410] COND TRUE 0 != ~tmp~0 [L411] COND TRUE 0 == ~m_st~0 [L412] havoc ~tmp_ndt_1~0; [L413] ~tmp_ndt_1~0 := #t~nondet1; [L413] havoc #t~nondet1; [L414-L421] COND FALSE !(0 != ~tmp_ndt_1~0) [L425] COND TRUE 0 == ~t1_st~0 [L426] havoc ~tmp_ndt_2~0; [L427] ~tmp_ndt_2~0 := #t~nondet2; [L427] havoc #t~nondet2; [L428-L435] COND FALSE !(0 != ~tmp_ndt_2~0) [L439] COND TRUE 0 == ~t2_st~0 [L440] havoc ~tmp_ndt_3~0; [L441] ~tmp_ndt_3~0 := #t~nondet3; [L441] havoc #t~nondet3; [L442-L449] COND FALSE !(0 != ~tmp_ndt_3~0) [L453] COND TRUE 0 == ~t3_st~0 [L454] havoc ~tmp_ndt_4~0; [L455] ~tmp_ndt_4~0 := #t~nondet4; [L455] havoc #t~nondet4; [L456-L463] COND FALSE !(0 != ~tmp_ndt_4~0) [L467] COND TRUE 0 == ~t4_st~0 [L468] havoc ~tmp_ndt_5~0; [L469] ~tmp_ndt_5~0 := #t~nondet5; [L469] havoc #t~nondet5; [L470-L477] COND FALSE !(0 != ~tmp_ndt_5~0) ----- ----- class de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.CACSL2BoogieBacktranslator [L401-L481] COND FALSE !(false) [L361] havoc ~__retres1~5; [L364] COND TRUE 0 == ~m_st~0 [L365] ~__retres1~5 := 1; [L392] #res := ~__retres1~5; [L404] ~tmp~0 := #t~ret0; [L404] havoc #t~ret0; [L406-L410] COND TRUE 0 != ~tmp~0 [L411] COND TRUE 0 == ~m_st~0 [L412] havoc ~tmp_ndt_1~0; [L413] ~tmp_ndt_1~0 := #t~nondet1; [L413] havoc #t~nondet1; [L414-L421] COND FALSE !(0 != ~tmp_ndt_1~0) [L425] COND TRUE 0 == ~t1_st~0 [L426] havoc ~tmp_ndt_2~0; [L427] ~tmp_ndt_2~0 := #t~nondet2; [L427] havoc #t~nondet2; [L428-L435] COND FALSE !(0 != ~tmp_ndt_2~0) [L439] COND TRUE 0 == ~t2_st~0 [L440] havoc ~tmp_ndt_3~0; [L441] ~tmp_ndt_3~0 := #t~nondet3; [L441] havoc #t~nondet3; [L442-L449] COND FALSE !(0 != ~tmp_ndt_3~0) [L453] COND TRUE 0 == ~t3_st~0 [L454] havoc ~tmp_ndt_4~0; [L455] ~tmp_ndt_4~0 := #t~nondet4; [L455] havoc #t~nondet4; [L456-L463] COND FALSE !(0 != ~tmp_ndt_4~0) [L467] COND TRUE 0 == ~t4_st~0 [L468] havoc ~tmp_ndt_5~0; [L469] ~tmp_ndt_5~0 := #t~nondet5; [L469] havoc #t~nondet5; [L470-L477] COND FALSE !(0 != ~tmp_ndt_5~0) [L401] COND TRUE 1 [L361] int __retres1 ; [L364] COND TRUE m_st == 0 [L365] __retres1 = 1 [L392] return (__retres1); [L404] tmp = exists_runnable_thread() [L406] COND TRUE \read(tmp) [L411] COND TRUE m_st == 0 [L412] int tmp_ndt_1; [L413] tmp_ndt_1 = __VERIFIER_nondet_int() [L414] COND FALSE !(\read(tmp_ndt_1)) [L425] COND TRUE t1_st == 0 [L426] int tmp_ndt_2; [L427] tmp_ndt_2 = __VERIFIER_nondet_int() [L428] COND FALSE !(\read(tmp_ndt_2)) [L439] COND TRUE t2_st == 0 [L440] int tmp_ndt_3; [L441] tmp_ndt_3 = __VERIFIER_nondet_int() [L442] COND FALSE !(\read(tmp_ndt_3)) [L453] COND TRUE t3_st == 0 [L454] int tmp_ndt_4; [L455] tmp_ndt_4 = __VERIFIER_nondet_int() [L456] COND FALSE !(\read(tmp_ndt_4)) [L467] COND TRUE t4_st == 0 [L468] int tmp_ndt_5; [L469] tmp_ndt_5 = __VERIFIER_nondet_int() [L470] COND FALSE !(\read(tmp_ndt_5)) ----- Found a nonterminating execution for the following lasso shaped sequence of statements. Stem: [L15] int m_pc = 0; [L16] int t1_pc = 0; [L17] int t2_pc = 0; [L18] int t3_pc = 0; [L19] int t4_pc = 0; [L20] int m_st ; [L21] int t1_st ; [L22] int t2_st ; [L23] int t3_st ; [L24] int t4_st ; [L25] int m_i ; [L26] int t1_i ; [L27] int t2_i ; [L28] int t3_i ; [L29] int t4_i ; [L30] int M_E = 2; [L31] int T1_E = 2; [L32] int T2_E = 2; [L33] int T3_E = 2; [L34] int T4_E = 2; [L35] int E_1 = 2; [L36] int E_2 = 2; [L37] int E_3 = 2; [L38] int E_4 = 2; [L811] int __retres1 ; [L723] m_i = 1 [L724] t1_i = 1 [L725] t2_i = 1 [L726] t3_i = 1 [L727] t4_i = 1 [L752] int kernel_st ; [L753] int tmp ; [L754] int tmp___0 ; [L758] kernel_st = 0 [L331] COND TRUE m_i == 1 [L332] m_st = 0 [L336] COND TRUE t1_i == 1 [L337] t1_st = 0 [L341] COND TRUE t2_i == 1 [L342] t2_st = 0 [L346] COND TRUE t3_i == 1 [L347] t3_st = 0 [L351] COND TRUE t4_i == 1 [L352] t4_st = 0 [L492] COND FALSE !(M_E == 0) [L497] COND FALSE !(T1_E == 0) [L502] COND FALSE !(T2_E == 0) [L507] COND FALSE !(T3_E == 0) [L512] COND FALSE !(T4_E == 0) [L517] COND FALSE !(E_1 == 0) [L522] COND FALSE !(E_2 == 0) [L527] COND FALSE !(E_3 == 0) [L532] COND FALSE !(E_4 == 0) [L595] int tmp ; [L596] int tmp___0 ; [L597] int tmp___1 ; [L598] int tmp___2 ; [L599] int tmp___3 ; [L225] int __retres1 ; [L228] COND FALSE !(m_pc == 1) [L238] __retres1 = 0 [L240] return (__retres1); [L603] tmp = is_master_triggered() [L605] COND FALSE !(\read(tmp)) [L244] int __retres1 ; [L247] COND FALSE !(t1_pc == 1) [L257] __retres1 = 0 [L259] return (__retres1); [L611] tmp___0 = is_transmit1_triggered() [L613] COND FALSE !(\read(tmp___0)) [L263] int __retres1 ; [L266] COND FALSE !(t2_pc == 1) [L276] __retres1 = 0 [L278] return (__retres1); [L619] tmp___1 = is_transmit2_triggered() [L621] COND FALSE !(\read(tmp___1)) [L282] int __retres1 ; [L285] COND FALSE !(t3_pc == 1) [L295] __retres1 = 0 [L297] return (__retres1); [L627] tmp___2 = is_transmit3_triggered() [L629] COND FALSE !(\read(tmp___2)) [L301] int __retres1 ; [L304] COND FALSE !(t4_pc == 1) [L314] __retres1 = 0 [L316] return (__retres1); [L635] tmp___3 = is_transmit4_triggered() [L637] COND FALSE !(\read(tmp___3)) [L545] COND FALSE !(M_E == 1) [L550] COND FALSE !(T1_E == 1) [L555] COND FALSE !(T2_E == 1) [L560] COND FALSE !(T3_E == 1) [L565] COND FALSE !(T4_E == 1) [L570] COND FALSE !(E_1 == 1) [L575] COND FALSE !(E_2 == 1) [L580] COND FALSE !(E_3 == 1) [L585] COND FALSE !(E_4 == 1) [L766] COND TRUE 1 [L769] kernel_st = 1 [L397] int tmp ; Loop: [L401] COND TRUE 1 [L361] int __retres1 ; [L364] COND TRUE m_st == 0 [L365] __retres1 = 1 [L392] return (__retres1); [L404] tmp = exists_runnable_thread() [L406] COND TRUE \read(tmp) [L411] COND TRUE m_st == 0 [L412] int tmp_ndt_1; [L413] tmp_ndt_1 = __VERIFIER_nondet_int() [L414] COND FALSE !(\read(tmp_ndt_1)) [L425] COND TRUE t1_st == 0 [L426] int tmp_ndt_2; [L427] tmp_ndt_2 = __VERIFIER_nondet_int() [L428] COND FALSE !(\read(tmp_ndt_2)) [L439] COND TRUE t2_st == 0 [L440] int tmp_ndt_3; [L441] tmp_ndt_3 = __VERIFIER_nondet_int() [L442] COND FALSE !(\read(tmp_ndt_3)) [L453] COND TRUE t3_st == 0 [L454] int tmp_ndt_4; [L455] tmp_ndt_4 = __VERIFIER_nondet_int() [L456] COND FALSE !(\read(tmp_ndt_4)) [L467] COND TRUE t4_st == 0 [L468] int tmp_ndt_5; [L469] tmp_ndt_5 = __VERIFIER_nondet_int() [L470] COND FALSE !(\read(tmp_ndt_5)) End of lasso representation. RESULT: Ultimate proved your program to be incorrect! Received shutdown request...