./Ultimate.py --spec ../../sv-benchmarks/c/properties/termination.prp --file ../../sv-benchmarks/c/systemc/transmitter.08_false-unreach-call_false-termination.cil.c --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for termination Using default analysis Version aa418289 Calling Ultimate with: java -Dosgi.configuration.area=/tmp/vcloud-vcloud-master/worker/working_dir_c1610823-20be-413b-8144-c2fdf28119b5/bin-2019/uautomizer/data/config -Xmx12G -Xms1G -jar /tmp/vcloud-vcloud-master/worker/working_dir_c1610823-20be-413b-8144-c2fdf28119b5/bin-2019/uautomizer/plugins/org.eclipse.equinox.launcher_1.3.100.v20150511-1540.jar -data @noDefault -ultimatedata /tmp/vcloud-vcloud-master/worker/working_dir_c1610823-20be-413b-8144-c2fdf28119b5/bin-2019/uautomizer/data -tc /tmp/vcloud-vcloud-master/worker/working_dir_c1610823-20be-413b-8144-c2fdf28119b5/bin-2019/uautomizer/config/AutomizerTermination.xml -i ../../sv-benchmarks/c/systemc/transmitter.08_false-unreach-call_false-termination.cil.c -s /tmp/vcloud-vcloud-master/worker/working_dir_c1610823-20be-413b-8144-c2fdf28119b5/bin-2019/uautomizer/config/svcomp-Termination-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud-vcloud-master/worker/working_dir_c1610823-20be-413b-8144-c2fdf28119b5/bin-2019/uautomizer --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash 0273045f436e57bbaf687c13388f6f87c9f85e85 ............................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................. Execution finished normally Writing output log to file Ultimate.log Writing human readable error path to file UltimateCounterExample.errorpath Result: FALSE(TERM) --- Real Ultimate output --- This is Ultimate 0.1.23-aa41828 [2018-11-22 21:21:30,870 INFO L170 SettingsManager]: Resetting all preferences to default values... [2018-11-22 21:21:30,871 INFO L174 SettingsManager]: Resetting UltimateCore preferences to default values [2018-11-22 21:21:30,877 INFO L177 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2018-11-22 21:21:30,877 INFO L174 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2018-11-22 21:21:30,878 INFO L174 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2018-11-22 21:21:30,878 INFO L174 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2018-11-22 21:21:30,879 INFO L174 SettingsManager]: Resetting LassoRanker preferences to default values [2018-11-22 21:21:30,880 INFO L174 SettingsManager]: Resetting Reaching Definitions preferences to default values [2018-11-22 21:21:30,880 INFO L174 SettingsManager]: Resetting SyntaxChecker preferences to default values [2018-11-22 21:21:30,881 INFO L177 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2018-11-22 21:21:30,881 INFO L174 SettingsManager]: Resetting LTL2Aut preferences to default values [2018-11-22 21:21:30,881 INFO L174 SettingsManager]: Resetting PEA to Boogie preferences to default values [2018-11-22 21:21:30,882 INFO L174 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2018-11-22 21:21:30,883 INFO L174 SettingsManager]: Resetting ChcToBoogie preferences to default values [2018-11-22 21:21:30,883 INFO L174 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2018-11-22 21:21:30,884 INFO L174 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2018-11-22 21:21:30,885 INFO L174 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2018-11-22 21:21:30,886 INFO L174 SettingsManager]: Resetting CodeCheck preferences to default values [2018-11-22 21:21:30,887 INFO L174 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2018-11-22 21:21:30,887 INFO L174 SettingsManager]: Resetting RCFGBuilder preferences to default values [2018-11-22 21:21:30,888 INFO L174 SettingsManager]: Resetting TraceAbstraction preferences to default values [2018-11-22 21:21:30,889 INFO L177 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2018-11-22 21:21:30,890 INFO L177 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2018-11-22 21:21:30,890 INFO L174 SettingsManager]: Resetting TreeAutomizer preferences to default values [2018-11-22 21:21:30,890 INFO L174 SettingsManager]: Resetting IcfgTransformer preferences to default values [2018-11-22 21:21:30,891 INFO L174 SettingsManager]: Resetting Boogie Printer preferences to default values [2018-11-22 21:21:30,892 INFO L174 SettingsManager]: Resetting ReqPrinter preferences to default values [2018-11-22 21:21:30,892 INFO L174 SettingsManager]: Resetting Witness Printer preferences to default values [2018-11-22 21:21:30,893 INFO L177 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2018-11-22 21:21:30,893 INFO L174 SettingsManager]: Resetting CDTParser preferences to default values [2018-11-22 21:21:30,894 INFO L177 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2018-11-22 21:21:30,894 INFO L177 SettingsManager]: ReqParser provides no preferences, ignoring... [2018-11-22 21:21:30,894 INFO L174 SettingsManager]: Resetting SmtParser preferences to default values [2018-11-22 21:21:30,895 INFO L174 SettingsManager]: Resetting Witness Parser preferences to default values [2018-11-22 21:21:30,895 INFO L181 SettingsManager]: Finished resetting all preferences to default values... [2018-11-22 21:21:30,896 INFO L98 SettingsManager]: Beginning loading settings from /tmp/vcloud-vcloud-master/worker/working_dir_c1610823-20be-413b-8144-c2fdf28119b5/bin-2019/uautomizer/config/svcomp-Termination-32bit-Automizer_Default.epf [2018-11-22 21:21:30,905 INFO L110 SettingsManager]: Loading preferences was successful [2018-11-22 21:21:30,905 INFO L112 SettingsManager]: Preferences different from defaults after loading the file: [2018-11-22 21:21:30,906 INFO L131 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2018-11-22 21:21:30,906 INFO L133 SettingsManager]: * Create parallel compositions if possible=false [2018-11-22 21:21:30,906 INFO L133 SettingsManager]: * Use SBE=true [2018-11-22 21:21:30,906 INFO L131 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: [2018-11-22 21:21:30,907 INFO L133 SettingsManager]: * NCSB implementation=INTSET_LAZY3 [2018-11-22 21:21:30,907 INFO L133 SettingsManager]: * Use old map elimination=false [2018-11-22 21:21:30,907 INFO L133 SettingsManager]: * Use external solver (rank synthesis)=false [2018-11-22 21:21:30,907 INFO L133 SettingsManager]: * Use only trivial implications for array writes=true [2018-11-22 21:21:30,907 INFO L133 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES [2018-11-22 21:21:30,907 INFO L131 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2018-11-22 21:21:30,907 INFO L133 SettingsManager]: * sizeof long=4 [2018-11-22 21:21:30,907 INFO L133 SettingsManager]: * Check unreachability of error function in SV-COMP mode=false [2018-11-22 21:21:30,908 INFO L133 SettingsManager]: * Overapproximate operations on floating types=true [2018-11-22 21:21:30,908 INFO L133 SettingsManager]: * sizeof POINTER=4 [2018-11-22 21:21:30,908 INFO L133 SettingsManager]: * Check division by zero=IGNORE [2018-11-22 21:21:30,908 INFO L133 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME [2018-11-22 21:21:30,908 INFO L133 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME [2018-11-22 21:21:30,908 INFO L133 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME [2018-11-22 21:21:30,908 INFO L133 SettingsManager]: * sizeof long double=12 [2018-11-22 21:21:30,908 INFO L133 SettingsManager]: * Check if freed pointer was valid=false [2018-11-22 21:21:30,909 INFO L133 SettingsManager]: * Assume nondeterminstic values are in range=false [2018-11-22 21:21:30,909 INFO L133 SettingsManager]: * Use constant arrays=true [2018-11-22 21:21:30,909 INFO L133 SettingsManager]: * Pointer base address is valid at dereference=ASSUME [2018-11-22 21:21:30,909 INFO L131 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2018-11-22 21:21:30,909 INFO L133 SettingsManager]: * Size of a code block=SequenceOfStatements [2018-11-22 21:21:30,909 INFO L133 SettingsManager]: * To the following directory=/home/matthias/ultimate/dump [2018-11-22 21:21:30,909 INFO L131 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2018-11-22 21:21:30,910 INFO L133 SettingsManager]: * Trace refinement strategy=CAMEL [2018-11-22 21:21:30,910 INFO L133 SettingsManager]: * Dump automata to the following directory=/home/matthias/ultimate/dump/auto [2018-11-22 21:21:30,910 INFO L131 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2018-11-22 21:21:30,911 INFO L133 SettingsManager]: * TransformationType=MODULO_NEIGHBOR Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud-vcloud-master/worker/working_dir_c1610823-20be-413b-8144-c2fdf28119b5/bin-2019/uautomizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> 0273045f436e57bbaf687c13388f6f87c9f85e85 [2018-11-22 21:21:30,935 INFO L81 nceAwareModelManager]: Repository-Root is: /tmp [2018-11-22 21:21:30,944 INFO L258 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2018-11-22 21:21:30,947 INFO L214 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2018-11-22 21:21:30,948 INFO L271 PluginConnector]: Initializing CDTParser... [2018-11-22 21:21:30,948 INFO L276 PluginConnector]: CDTParser initialized [2018-11-22 21:21:30,949 INFO L418 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud-vcloud-master/worker/working_dir_c1610823-20be-413b-8144-c2fdf28119b5/bin-2019/uautomizer/../../sv-benchmarks/c/systemc/transmitter.08_false-unreach-call_false-termination.cil.c [2018-11-22 21:21:30,991 INFO L221 CDTParser]: Created temporary CDT project at /tmp/vcloud-vcloud-master/worker/working_dir_c1610823-20be-413b-8144-c2fdf28119b5/bin-2019/uautomizer/data/883734590/61433dfc6a244620aaec1ea7b94e2118/FLAG0feea78a4 [2018-11-22 21:21:31,410 INFO L307 CDTParser]: Found 1 translation units. [2018-11-22 21:21:31,411 INFO L161 CDTParser]: Scanning /tmp/vcloud-vcloud-master/worker/working_dir_c1610823-20be-413b-8144-c2fdf28119b5/sv-benchmarks/c/systemc/transmitter.08_false-unreach-call_false-termination.cil.c [2018-11-22 21:21:31,420 INFO L355 CDTParser]: About to delete temporary CDT project at /tmp/vcloud-vcloud-master/worker/working_dir_c1610823-20be-413b-8144-c2fdf28119b5/bin-2019/uautomizer/data/883734590/61433dfc6a244620aaec1ea7b94e2118/FLAG0feea78a4 [2018-11-22 21:21:31,431 INFO L363 CDTParser]: Successfully deleted /tmp/vcloud-vcloud-master/worker/working_dir_c1610823-20be-413b-8144-c2fdf28119b5/bin-2019/uautomizer/data/883734590/61433dfc6a244620aaec1ea7b94e2118 [2018-11-22 21:21:31,434 INFO L296 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2018-11-22 21:21:31,435 INFO L131 ToolchainWalker]: Walking toolchain with 6 elements. [2018-11-22 21:21:31,436 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2018-11-22 21:21:31,436 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2018-11-22 21:21:31,438 INFO L276 PluginConnector]: CACSL2BoogieTranslator initialized [2018-11-22 21:21:31,438 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 22.11 09:21:31" (1/1) ... [2018-11-22 21:21:31,440 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@51ac0340 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 22.11 09:21:31, skipping insertion in model container [2018-11-22 21:21:31,440 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 22.11 09:21:31" (1/1) ... [2018-11-22 21:21:31,446 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2018-11-22 21:21:31,475 INFO L176 MainTranslator]: Built tables and reachable declarations [2018-11-22 21:21:31,651 INFO L201 PostProcessor]: Analyzing one entry point: main [2018-11-22 21:21:31,656 INFO L191 MainTranslator]: Completed pre-run [2018-11-22 21:21:31,703 INFO L201 PostProcessor]: Analyzing one entry point: main [2018-11-22 21:21:31,719 INFO L195 MainTranslator]: Completed translation [2018-11-22 21:21:31,719 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 22.11 09:21:31 WrapperNode [2018-11-22 21:21:31,719 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2018-11-22 21:21:31,720 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2018-11-22 21:21:31,720 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2018-11-22 21:21:31,720 INFO L276 PluginConnector]: Boogie Procedure Inliner initialized [2018-11-22 21:21:31,725 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 22.11 09:21:31" (1/1) ... [2018-11-22 21:21:31,773 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 22.11 09:21:31" (1/1) ... [2018-11-22 21:21:31,817 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2018-11-22 21:21:31,817 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2018-11-22 21:21:31,817 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2018-11-22 21:21:31,817 INFO L276 PluginConnector]: Boogie Preprocessor initialized [2018-11-22 21:21:31,826 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 22.11 09:21:31" (1/1) ... [2018-11-22 21:21:31,826 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 22.11 09:21:31" (1/1) ... [2018-11-22 21:21:31,830 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 22.11 09:21:31" (1/1) ... [2018-11-22 21:21:31,831 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 22.11 09:21:31" (1/1) ... [2018-11-22 21:21:31,846 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 22.11 09:21:31" (1/1) ... [2018-11-22 21:21:31,869 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 22.11 09:21:31" (1/1) ... [2018-11-22 21:21:31,873 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 22.11 09:21:31" (1/1) ... [2018-11-22 21:21:31,879 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2018-11-22 21:21:31,880 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2018-11-22 21:21:31,880 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2018-11-22 21:21:31,880 INFO L276 PluginConnector]: RCFGBuilder initialized [2018-11-22 21:21:31,880 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 22.11 09:21:31" (1/1) ... No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_c1610823-20be-413b-8144-c2fdf28119b5/bin-2019/uautomizer/z3 Starting monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2018-11-22 21:21:31,931 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2018-11-22 21:21:31,931 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2018-11-22 21:21:33,069 INFO L275 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2018-11-22 21:21:33,069 INFO L280 CfgBuilder]: Removed 304 assue(true) statements. [2018-11-22 21:21:33,069 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 22.11 09:21:33 BoogieIcfgContainer [2018-11-22 21:21:33,069 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2018-11-22 21:21:33,070 INFO L113 PluginConnector]: ------------------------BuchiAutomizer---------------------------- [2018-11-22 21:21:33,070 INFO L271 PluginConnector]: Initializing BuchiAutomizer... [2018-11-22 21:21:33,073 INFO L276 PluginConnector]: BuchiAutomizer initialized [2018-11-22 21:21:33,074 INFO L102 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2018-11-22 21:21:33,074 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 22.11 09:21:31" (1/3) ... [2018-11-22 21:21:33,075 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@7904ae7b and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 22.11 09:21:33, skipping insertion in model container [2018-11-22 21:21:33,075 INFO L102 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2018-11-22 21:21:33,075 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 22.11 09:21:31" (2/3) ... [2018-11-22 21:21:33,075 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@7904ae7b and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 22.11 09:21:33, skipping insertion in model container [2018-11-22 21:21:33,075 INFO L102 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2018-11-22 21:21:33,075 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 22.11 09:21:33" (3/3) ... [2018-11-22 21:21:33,077 INFO L375 chiAutomizerObserver]: Analyzing ICFG transmitter.08_false-unreach-call_false-termination.cil.c [2018-11-22 21:21:33,117 INFO L133 ementStrategyFactory]: Using default assertion order modulation [2018-11-22 21:21:33,118 INFO L374 BuchiCegarLoop]: Interprodecural is true [2018-11-22 21:21:33,118 INFO L375 BuchiCegarLoop]: Hoare is false [2018-11-22 21:21:33,118 INFO L376 BuchiCegarLoop]: Compute interpolants for ForwardPredicates [2018-11-22 21:21:33,118 INFO L377 BuchiCegarLoop]: Backedges is STRAIGHT_LINE [2018-11-22 21:21:33,118 INFO L378 BuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2018-11-22 21:21:33,118 INFO L379 BuchiCegarLoop]: Difference is false [2018-11-22 21:21:33,118 INFO L380 BuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2018-11-22 21:21:33,118 INFO L383 BuchiCegarLoop]: ======== Iteration 0==of CEGAR loop == BuchiCegarLoop======== [2018-11-22 21:21:33,145 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 905 states. [2018-11-22 21:21:33,183 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 792 [2018-11-22 21:21:33,184 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-22 21:21:33,184 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-22 21:21:33,193 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-22 21:21:33,193 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-22 21:21:33,193 INFO L442 BuchiCegarLoop]: ======== Iteration 1============ [2018-11-22 21:21:33,193 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 905 states. [2018-11-22 21:21:33,203 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 792 [2018-11-22 21:21:33,203 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-22 21:21:33,203 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-22 21:21:33,206 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-22 21:21:33,206 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-22 21:21:33,214 INFO L794 eck$LassoCheckResult]: Stem: 290#ULTIMATE.startENTRYtrue ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2; 214#L-1true havoc main_#res;havoc main_~__retres1~10;havoc main_~__retres1~10;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 633#L1225true havoc start_simulation_#t~ret20, start_simulation_#t~ret21, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 643#L564true assume !(1 == ~m_i~0);~m_st~0 := 2; 235#L571-1true assume 1 == ~t1_i~0;~t1_st~0 := 0; 44#L576-1true assume !(1 == ~t2_i~0);~t2_st~0 := 2; 855#L581-1true assume !(1 == ~t3_i~0);~t3_st~0 := 2; 644#L586-1true assume !(1 == ~t4_i~0);~t4_st~0 := 2; 397#L591-1true assume !(1 == ~t5_i~0);~t5_st~0 := 2; 108#L596-1true assume !(1 == ~t6_i~0);~t6_st~0 := 2; 823#L601-1true assume !(1 == ~t7_i~0);~t7_st~0 := 2; 625#L606-1true assume !(1 == ~t8_i~0);~t8_st~0 := 2; 500#L611-1true assume 0 == ~M_E~0;~M_E~0 := 1; 656#L828-1true assume !(0 == ~T1_E~0); 310#L833-1true assume !(0 == ~T2_E~0); 116#L838-1true assume !(0 == ~T3_E~0); 847#L843-1true assume !(0 == ~T4_E~0); 736#L848-1true assume !(0 == ~T5_E~0); 510#L853-1true assume !(0 == ~T6_E~0); 298#L858-1true assume !(0 == ~T7_E~0); 6#L863-1true assume 0 == ~T8_E~0;~T8_E~0 := 1; 697#L868-1true assume !(0 == ~E_1~0); 467#L873-1true assume !(0 == ~E_2~0); 365#L878-1true assume !(0 == ~E_3~0); 192#L883-1true assume !(0 == ~E_4~0); 779#L888-1true assume !(0 == ~E_5~0); 589#L893-1true assume !(0 == ~E_6~0); 339#L898-1true assume !(0 == ~E_7~0); 279#L903-1true assume 0 == ~E_8~0;~E_8~0 := 1; 78#L908-1true havoc activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 324#L392true assume 1 == ~m_pc~0; 384#L393true assume 1 == ~M_E~0;is_master_triggered_~__retres1~0 := 1; 806#L403true is_master_triggered_#res := is_master_triggered_~__retres1~0; 886#L404true activate_threads_#t~ret10 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 599#L1025true assume !(0 != activate_threads_~tmp~1); 602#L1025-2true havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 456#L411true assume !(1 == ~t1_pc~0); 436#L411-2true is_transmit1_triggered_~__retres1~1 := 0; 34#L422true is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 95#L423true activate_threads_#t~ret11 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 242#L1033true assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 243#L1033-2true havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 614#L430true assume 1 == ~t2_pc~0; 576#L431true assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 135#L441true is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 109#L442true activate_threads_#t~ret12 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 851#L1041true assume !(0 != activate_threads_~tmp___1~0); 854#L1041-2true havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 861#L449true assume !(1 == ~t3_pc~0); 865#L449-2true is_transmit3_triggered_~__retres1~3 := 0; 348#L460true is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 225#L461true activate_threads_#t~ret13 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 629#L1049true assume !(0 != activate_threads_~tmp___2~0); 630#L1049-2true havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 56#L468true assume 1 == ~t4_pc~0; 827#L469true assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 508#L479true is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 332#L480true activate_threads_#t~ret14 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 285#L1057true assume !(0 != activate_threads_~tmp___3~0); 288#L1057-2true havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 182#L487true assume !(1 == ~t5_pc~0); 184#L487-2true is_transmit5_triggered_~__retres1~5 := 0; 647#L498true is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 449#L499true activate_threads_#t~ret15 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 876#L1065true assume !(0 != activate_threads_~tmp___4~0); 877#L1065-2true havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 297#L506true assume 1 == ~t6_pc~0; 152#L507true assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6 := 1; 765#L517true is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 627#L518true activate_threads_#t~ret16 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 534#L1073true assume !(0 != activate_threads_~tmp___5~0); 536#L1073-2true havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 399#L525true assume 1 == ~t7_pc~0; 345#L526true assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7 := 1; 902#L536true is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 856#L537true activate_threads_#t~ret17 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 196#L1081true assume !(0 != activate_threads_~tmp___6~0); 197#L1081-2true havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 416#L544true assume !(1 == ~t8_pc~0); 548#L544-2true is_transmit8_triggered_~__retres1~8 := 0; 3#L555true is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 71#L556true activate_threads_#t~ret18 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 673#L1089true assume 0 != activate_threads_~tmp___7~0;~t8_st~0 := 0; 674#L1089-2true assume !(1 == ~M_E~0); 306#L921-1true assume !(1 == ~T1_E~0); 114#L926-1true assume !(1 == ~T2_E~0); 841#L931-1true assume !(1 == ~T3_E~0); 734#L936-1true assume 1 == ~T4_E~0;~T4_E~0 := 2; 522#L941-1true assume !(1 == ~T5_E~0); 303#L946-1true assume !(1 == ~T6_E~0); 10#L951-1true assume !(1 == ~T7_E~0); 706#L956-1true assume !(1 == ~T8_E~0); 632#L961-1true assume !(1 == ~E_1~0); 372#L966-1true assume !(1 == ~E_2~0); 200#L971-1true assume !(1 == ~E_3~0); 787#L976-1true assume 1 == ~E_4~0;~E_4~0 := 2; 585#L981-1true assume !(1 == ~E_5~0); 337#L986-1true assume !(1 == ~E_6~0); 274#L991-1true assume !(1 == ~E_7~0); 75#L996-1true assume !(1 == ~E_8~0); 792#L1262-1true [2018-11-22 21:21:33,220 INFO L796 eck$LassoCheckResult]: Loop: 792#L1262-1true assume !false; 898#L1263true start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret0, eval_#t~nondet1, eval_~tmp_ndt_1~0, eval_#t~nondet2, eval_~tmp_ndt_2~0, eval_#t~nondet3, eval_~tmp_ndt_3~0, eval_#t~nondet4, eval_~tmp_ndt_4~0, eval_#t~nondet5, eval_~tmp_ndt_5~0, eval_#t~nondet6, eval_~tmp_ndt_6~0, eval_#t~nondet7, eval_~tmp_ndt_7~0, eval_#t~nondet8, eval_~tmp_ndt_8~0, eval_#t~nondet9, eval_~tmp_ndt_9~0, eval_~tmp~0;havoc eval_~tmp~0; 769#L803true assume false; 46#L818true start_simulation_~kernel_st~0 := 2; 645#L564-1true start_simulation_~kernel_st~0 := 3; 657#L828-2true assume 0 == ~M_E~0;~M_E~0 := 1; 651#L828-4true assume 0 == ~T1_E~0;~T1_E~0 := 1; 406#L833-3true assume 0 == ~T2_E~0;~T2_E~0 := 1; 111#L838-3true assume 0 == ~T3_E~0;~T3_E~0 := 1; 831#L843-3true assume !(0 == ~T4_E~0); 730#L848-3true assume 0 == ~T5_E~0;~T5_E~0 := 1; 515#L853-3true assume 0 == ~T6_E~0;~T6_E~0 := 1; 300#L858-3true assume 0 == ~T7_E~0;~T7_E~0 := 1; 8#L863-3true assume 0 == ~T8_E~0;~T8_E~0 := 1; 700#L868-3true assume 0 == ~E_1~0;~E_1~0 := 1; 469#L873-3true assume 0 == ~E_2~0;~E_2~0 := 1; 367#L878-3true assume 0 == ~E_3~0;~E_3~0 := 1; 194#L883-3true assume !(0 == ~E_4~0); 780#L888-3true assume 0 == ~E_5~0;~E_5~0 := 1; 593#L893-3true assume 0 == ~E_6~0;~E_6~0 := 1; 340#L898-3true assume 0 == ~E_7~0;~E_7~0 := 1; 263#L903-3true assume 0 == ~E_8~0;~E_8~0 := 1; 74#L908-3true havoc activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 400#L392-27true assume !(1 == ~m_pc~0); 402#L392-29true is_master_triggered_~__retres1~0 := 0; 801#L403-9true is_master_triggered_#res := is_master_triggered_~__retres1~0; 884#L404-9true activate_threads_#t~ret10 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 667#L1025-27true assume !(0 != activate_threads_~tmp~1); 658#L1025-29true havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 417#L411-27true assume 1 == ~t1_pc~0; 531#L412-9true assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 13#L422-9true is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 79#L423-9true activate_threads_#t~ret11 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 208#L1033-27true assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 212#L1033-29true havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 570#L430-27true assume 1 == ~t2_pc~0; 666#L431-9true assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 133#L441-9true is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 204#L442-9true activate_threads_#t~ret12 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 799#L1041-27true assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 783#L1041-29true havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 694#L449-27true assume !(1 == ~t3_pc~0); 682#L449-29true is_transmit3_triggered_~__retres1~3 := 0; 247#L460-9true is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 207#L461-9true activate_threads_#t~ret13 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 429#L1049-27true assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 432#L1049-29true havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 821#L468-27true assume !(1 == ~t4_pc~0); 825#L468-29true is_transmit4_triggered_~__retres1~4 := 0; 481#L479-9true is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 319#L480-9true activate_threads_#t~ret14 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 132#L1057-27true assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 117#L1057-29true havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 42#L487-27true assume !(1 == ~t5_pc~0); 43#L487-29true is_transmit5_triggered_~__retres1~5 := 0; 634#L498-9true is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 448#L499-9true activate_threads_#t~ret15 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 710#L1065-27true assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 712#L1065-29true havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 272#L506-27true assume 1 == ~t6_pc~0; 129#L507-9true assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6 := 1; 746#L517-9true is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 607#L518-9true activate_threads_#t~ret16 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 482#L1073-27true assume 0 != activate_threads_~tmp___5~0;~t6_st~0 := 0; 342#L1073-29true havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 355#L525-27true assume 1 == ~t7_pc~0; 261#L526-9true assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7 := 1; 900#L536-9true is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 727#L537-9true activate_threads_#t~ret17 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 164#L1081-27true assume 0 != activate_threads_~tmp___6~0;~t7_st~0 := 0; 167#L1081-29true havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 519#L544-27true assume !(1 == ~t8_pc~0); 499#L544-29true is_transmit8_triggered_~__retres1~8 := 0; 88#L555-9true is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 52#L556-9true activate_threads_#t~ret18 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 749#L1089-27true assume 0 != activate_threads_~tmp___7~0;~t8_st~0 := 0; 737#L1089-29true assume !(1 == ~M_E~0); 309#L921-3true assume 1 == ~T1_E~0;~T1_E~0 := 2; 115#L926-3true assume 1 == ~T2_E~0;~T2_E~0 := 2; 846#L931-3true assume 1 == ~T3_E~0;~T3_E~0 := 2; 735#L936-3true assume 1 == ~T4_E~0;~T4_E~0 := 2; 528#L941-3true assume 1 == ~T5_E~0;~T5_E~0 := 2; 304#L946-3true assume 1 == ~T6_E~0;~T6_E~0 := 2; 5#L951-3true assume 1 == ~T7_E~0;~T7_E~0 := 2; 696#L956-3true assume !(1 == ~T8_E~0); 466#L961-3true assume 1 == ~E_1~0;~E_1~0 := 2; 363#L966-3true assume 1 == ~E_2~0;~E_2~0 := 2; 191#L971-3true assume 1 == ~E_3~0;~E_3~0 := 2; 778#L976-3true assume 1 == ~E_4~0;~E_4~0 := 2; 588#L981-3true assume 1 == ~E_5~0;~E_5~0 := 2; 338#L986-3true assume 1 == ~E_6~0;~E_6~0 := 2; 277#L991-3true assume 1 == ~E_7~0;~E_7~0 := 2; 76#L996-3true assume !(1 == ~E_8~0); 777#L1001-3true havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~9;havoc exists_runnable_thread_~__retres1~9; 907#L624-1true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9 := 1; 762#L671-1true exists_runnable_thread_#res := exists_runnable_thread_~__retres1~9; 733#L672-1true start_simulation_#t~ret20 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret20;havoc start_simulation_#t~ret20; 22#L1281true assume !(0 == start_simulation_~tmp~3); 27#L1281-1true havoc stop_simulation_#res;havoc stop_simulation_#t~ret19, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~9;havoc exists_runnable_thread_~__retres1~9; 901#L624-2true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9 := 1; 763#L671-2true exists_runnable_thread_#res := exists_runnable_thread_~__retres1~9; 623#L672-2true stop_simulation_#t~ret19 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret19;havoc stop_simulation_#t~ret19; 162#L1236true assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 679#L1243true stop_simulation_#res := stop_simulation_~__retres2~0; 747#L1244true start_simulation_#t~ret21 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret21;havoc start_simulation_#t~ret21; 475#L1294true assume !(0 != start_simulation_~tmp___0~1); 792#L1262-1true [2018-11-22 21:21:33,225 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-22 21:21:33,226 INFO L82 PathProgramCache]: Analyzing trace with hash -659050580, now seen corresponding path program 1 times [2018-11-22 21:21:33,227 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-22 21:21:33,228 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-22 21:21:33,258 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-22 21:21:33,259 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-22 21:21:33,259 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-22 21:21:33,290 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-22 21:21:33,362 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-22 21:21:33,364 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-22 21:21:33,365 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-22 21:21:33,369 INFO L799 eck$LassoCheckResult]: stem already infeasible [2018-11-22 21:21:33,369 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-22 21:21:33,370 INFO L82 PathProgramCache]: Analyzing trace with hash -60762341, now seen corresponding path program 1 times [2018-11-22 21:21:33,370 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-22 21:21:33,370 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-22 21:21:33,371 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-22 21:21:33,371 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-22 21:21:33,371 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-22 21:21:33,377 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-22 21:21:33,398 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-22 21:21:33,399 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-22 21:21:33,399 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2018-11-22 21:21:33,400 INFO L811 eck$LassoCheckResult]: loop already infeasible [2018-11-22 21:21:33,414 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-22 21:21:33,415 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-22 21:21:33,417 INFO L87 Difference]: Start difference. First operand 905 states. Second operand 3 states. [2018-11-22 21:21:33,473 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-22 21:21:33,473 INFO L93 Difference]: Finished difference Result 905 states and 1360 transitions. [2018-11-22 21:21:33,474 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-22 21:21:33,476 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 905 states and 1360 transitions. [2018-11-22 21:21:33,481 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 791 [2018-11-22 21:21:33,490 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 905 states to 900 states and 1355 transitions. [2018-11-22 21:21:33,491 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 900 [2018-11-22 21:21:33,492 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 900 [2018-11-22 21:21:33,493 INFO L73 IsDeterministic]: Start isDeterministic. Operand 900 states and 1355 transitions. [2018-11-22 21:21:33,497 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-22 21:21:33,497 INFO L705 BuchiCegarLoop]: Abstraction has 900 states and 1355 transitions. [2018-11-22 21:21:33,512 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 900 states and 1355 transitions. [2018-11-22 21:21:33,541 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 900 to 900. [2018-11-22 21:21:33,541 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 900 states. [2018-11-22 21:21:33,544 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 900 states to 900 states and 1355 transitions. [2018-11-22 21:21:33,545 INFO L728 BuchiCegarLoop]: Abstraction has 900 states and 1355 transitions. [2018-11-22 21:21:33,545 INFO L608 BuchiCegarLoop]: Abstraction has 900 states and 1355 transitions. [2018-11-22 21:21:33,545 INFO L442 BuchiCegarLoop]: ======== Iteration 2============ [2018-11-22 21:21:33,545 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 900 states and 1355 transitions. [2018-11-22 21:21:33,548 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 791 [2018-11-22 21:21:33,548 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-22 21:21:33,549 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-22 21:21:33,551 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-22 21:21:33,551 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-22 21:21:33,552 INFO L794 eck$LassoCheckResult]: Stem: 2257#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2; 2160#L-1 havoc main_#res;havoc main_~__retres1~10;havoc main_~__retres1~10;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 2161#L1225 havoc start_simulation_#t~ret20, start_simulation_#t~ret21, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 2585#L564 assume 1 == ~m_i~0;~m_st~0 := 0; 2194#L571-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1907#L576-1 assume !(1 == ~t2_i~0);~t2_st~0 := 2; 1908#L581-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 2587#L586-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 2373#L591-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 2007#L596-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 2008#L601-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 2579#L606-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 2495#L611-1 assume 0 == ~M_E~0;~M_E~0 := 1; 2496#L828-1 assume !(0 == ~T1_E~0); 2277#L833-1 assume !(0 == ~T2_E~0); 2022#L838-1 assume !(0 == ~T3_E~0); 2023#L843-1 assume !(0 == ~T4_E~0); 2655#L848-1 assume !(0 == ~T5_E~0); 2504#L853-1 assume !(0 == ~T6_E~0); 2261#L858-1 assume !(0 == ~T7_E~0); 1825#L863-1 assume 0 == ~T8_E~0;~T8_E~0 := 1; 1826#L868-1 assume !(0 == ~E_1~0); 2460#L873-1 assume !(0 == ~E_2~0); 2346#L878-1 assume !(0 == ~E_3~0); 2131#L883-1 assume !(0 == ~E_4~0); 2132#L888-1 assume !(0 == ~E_5~0); 2556#L893-1 assume !(0 == ~E_6~0); 2315#L898-1 assume !(0 == ~E_7~0); 2248#L903-1 assume 0 == ~E_8~0;~E_8~0 := 1; 1969#L908-1 havoc activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 1970#L392 assume 1 == ~m_pc~0; 2298#L393 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0 := 1; 2302#L403 is_master_triggered_#res := is_master_triggered_~__retres1~0; 2687#L404 activate_threads_#t~ret10 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 2563#L1025 assume !(0 != activate_threads_~tmp~1); 2564#L1025-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 2447#L411 assume !(1 == ~t1_pc~0); 2415#L411-2 is_transmit1_triggered_~__retres1~1 := 0; 1889#L422 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 1890#L423 activate_threads_#t~ret11 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 1988#L1033 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 2200#L1033-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 2201#L430 assume 1 == ~t2_pc~0; 2542#L431 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 2054#L441 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 2009#L442 activate_threads_#t~ret12 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 2010#L1041 assume !(0 != activate_threads_~tmp___1~0); 2705#L1041-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 2706#L449 assume !(1 == ~t3_pc~0); 2621#L449-2 is_transmit3_triggered_~__retres1~3 := 0; 2329#L460 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 2178#L461 activate_threads_#t~ret13 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 2179#L1049 assume !(0 != activate_threads_~tmp___2~0); 2583#L1049-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 1925#L468 assume 1 == ~t4_pc~0; 1926#L469 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 1934#L479 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 2308#L480 activate_threads_#t~ret14 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 2253#L1057 assume !(0 != activate_threads_~tmp___3~0); 2254#L1057-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 2117#L487 assume !(1 == ~t5_pc~0); 1885#L487-2 is_transmit5_triggered_~__retres1~5 := 0; 1884#L498 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 2435#L499 activate_threads_#t~ret15 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 2436#L1065 assume !(0 != activate_threads_~tmp___4~0); 2718#L1065-2 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 2260#L506 assume 1 == ~t6_pc~0; 2083#L507 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6 := 1; 2084#L517 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 2581#L518 activate_threads_#t~ret16 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 2517#L1073 assume !(0 != activate_threads_~tmp___5~0); 2518#L1073-2 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 2374#L525 assume 1 == ~t7_pc~0; 2323#L526 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7 := 1; 2324#L536 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 2707#L537 activate_threads_#t~ret17 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 2137#L1081 assume !(0 != activate_threads_~tmp___6~0); 2138#L1081-2 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 2139#L544 assume !(1 == ~t8_pc~0); 2386#L544-2 is_transmit8_triggered_~__retres1~8 := 0; 1819#L555 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 1820#L556 activate_threads_#t~ret18 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 1958#L1089 assume 0 != activate_threads_~tmp___7~0;~t8_st~0 := 0; 2605#L1089-2 assume !(1 == ~M_E~0); 2271#L921-1 assume !(1 == ~T1_E~0); 2018#L926-1 assume !(1 == ~T2_E~0); 2019#L931-1 assume !(1 == ~T3_E~0); 2653#L936-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 2512#L941-1 assume !(1 == ~T5_E~0); 2267#L946-1 assume !(1 == ~T6_E~0); 1835#L951-1 assume !(1 == ~T7_E~0); 1836#L956-1 assume !(1 == ~T8_E~0); 2584#L961-1 assume !(1 == ~E_1~0); 2351#L966-1 assume !(1 == ~E_2~0); 2143#L971-1 assume !(1 == ~E_3~0); 2144#L976-1 assume 1 == ~E_4~0;~E_4~0 := 2; 2552#L981-1 assume !(1 == ~E_5~0); 2313#L986-1 assume !(1 == ~E_6~0); 2243#L991-1 assume !(1 == ~E_7~0); 1964#L996-1 assume !(1 == ~E_8~0); 1965#L1262-1 [2018-11-22 21:21:33,552 INFO L796 eck$LassoCheckResult]: Loop: 1965#L1262-1 assume !false; 2675#L1263 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret0, eval_#t~nondet1, eval_~tmp_ndt_1~0, eval_#t~nondet2, eval_~tmp_ndt_2~0, eval_#t~nondet3, eval_~tmp_ndt_3~0, eval_#t~nondet4, eval_~tmp_ndt_4~0, eval_#t~nondet5, eval_~tmp_ndt_5~0, eval_#t~nondet6, eval_~tmp_ndt_6~0, eval_#t~nondet7, eval_~tmp_ndt_7~0, eval_#t~nondet8, eval_~tmp_ndt_8~0, eval_#t~nondet9, eval_~tmp_ndt_9~0, eval_~tmp~0;havoc eval_~tmp~0; 2279#L803 assume !false; 2264#L682 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~9;havoc exists_runnable_thread_~__retres1~9; 2265#L624 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9 := 1; 1950#L671 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~9; 2651#L672 eval_#t~ret0 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret0;havoc eval_#t~ret0; 1901#L686 assume !(0 != eval_~tmp~0); 1903#L818 start_simulation_~kernel_st~0 := 2; 1909#L564-1 start_simulation_~kernel_st~0 := 3; 2588#L828-2 assume 0 == ~M_E~0;~M_E~0 := 1; 2589#L828-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 2377#L833-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 2014#L838-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 2015#L843-3 assume !(0 == ~T4_E~0); 2649#L848-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 2508#L853-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 2263#L858-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 1830#L863-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 1831#L868-3 assume 0 == ~E_1~0;~E_1~0 := 1; 2461#L873-3 assume 0 == ~E_2~0;~E_2~0 := 1; 2347#L878-3 assume 0 == ~E_3~0;~E_3~0 := 1; 2134#L883-3 assume !(0 == ~E_4~0); 2135#L888-3 assume 0 == ~E_5~0;~E_5~0 := 1; 2560#L893-3 assume 0 == ~E_6~0;~E_6~0 := 1; 2316#L898-3 assume 0 == ~E_7~0;~E_7~0 := 1; 2234#L903-3 assume 0 == ~E_8~0;~E_8~0 := 1; 1962#L908-3 havoc activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 1963#L392-27 assume 1 == ~m_pc~0; 2361#L393-9 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0 := 1; 2362#L403-9 is_master_triggered_#res := is_master_triggered_~__retres1~0; 2685#L404-9 activate_threads_#t~ret10 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 2599#L1025-27 assume !(0 != activate_threads_~tmp~1); 2594#L1025-29 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 2388#L411-27 assume 1 == ~t1_pc~0; 2389#L412-9 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 1842#L422-9 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 1843#L423-9 activate_threads_#t~ret11 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 1971#L1033-27 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 2154#L1033-29 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 2158#L430-27 assume !(1 == ~t2_pc~0); 2536#L430-29 is_transmit2_triggered_~__retres1~2 := 0; 2050#L441-9 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 2051#L442-9 activate_threads_#t~ret12 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 2148#L1041-27 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 2668#L1041-29 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 2630#L449-27 assume 1 == ~t3_pc~0; 2600#L450-9 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 2206#L460-9 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 2152#L461-9 activate_threads_#t~ret13 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 2153#L1049-27 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 2407#L1049-29 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 2412#L468-27 assume 1 == ~t4_pc~0; 2680#L469-9 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 2475#L479-9 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 2293#L480-9 activate_threads_#t~ret14 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 2049#L1057-27 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 2024#L1057-29 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 1906#L487-27 assume 1 == ~t5_pc~0; 1879#L488-9 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 1880#L498-9 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 2433#L499-9 activate_threads_#t~ret15 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 2434#L1065-27 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 2636#L1065-29 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 2242#L506-27 assume 1 == ~t6_pc~0; 2041#L507-9 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6 := 1; 2042#L517-9 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 2566#L518-9 activate_threads_#t~ret16 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 2476#L1073-27 assume 0 != activate_threads_~tmp___5~0;~t6_st~0 := 0; 2318#L1073-29 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 2319#L525-27 assume 1 == ~t7_pc~0; 2229#L526-9 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7 := 1; 2230#L536-9 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 2647#L537-9 activate_threads_#t~ret17 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 2096#L1081-27 assume 0 != activate_threads_~tmp___6~0;~t7_st~0 := 0; 2097#L1081-29 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 2100#L544-27 assume 1 == ~t8_pc~0; 2470#L545-9 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8 := 1; 1981#L555-9 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 1917#L556-9 activate_threads_#t~ret18 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 1918#L1089-27 assume 0 != activate_threads_~tmp___7~0;~t8_st~0 := 0; 2656#L1089-29 assume !(1 == ~M_E~0); 2276#L921-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 2020#L926-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 2021#L931-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 2654#L936-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 2514#L941-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 2268#L946-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 1823#L951-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 1824#L956-3 assume !(1 == ~T8_E~0); 2459#L961-3 assume 1 == ~E_1~0;~E_1~0 := 2; 2344#L966-3 assume 1 == ~E_2~0;~E_2~0 := 2; 2129#L971-3 assume 1 == ~E_3~0;~E_3~0 := 2; 2130#L976-3 assume 1 == ~E_4~0;~E_4~0 := 2; 2555#L981-3 assume 1 == ~E_5~0;~E_5~0 := 2; 2314#L986-3 assume 1 == ~E_6~0;~E_6~0 := 2; 2247#L991-3 assume 1 == ~E_7~0;~E_7~0 := 2; 1966#L996-3 assume !(1 == ~E_8~0); 1967#L1001-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~9;havoc exists_runnable_thread_~__retres1~9; 2667#L624-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9 := 1; 1954#L671-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~9; 2652#L672-1 start_simulation_#t~ret20 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret20;havoc start_simulation_#t~ret20; 1863#L1281 assume !(0 == start_simulation_~tmp~3); 1864#L1281-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret19, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~9;havoc exists_runnable_thread_~__retres1~9; 1876#L624-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9 := 1; 1957#L671-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~9; 2577#L672-2 stop_simulation_#t~ret19 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret19;havoc stop_simulation_#t~ret19; 2093#L1236 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 2094#L1243 stop_simulation_#res := stop_simulation_~__retres2~0; 2614#L1244 start_simulation_#t~ret21 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret21;havoc start_simulation_#t~ret21; 2468#L1294 assume !(0 != start_simulation_~tmp___0~1); 1965#L1262-1 [2018-11-22 21:21:33,553 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-22 21:21:33,553 INFO L82 PathProgramCache]: Analyzing trace with hash 2034845610, now seen corresponding path program 1 times [2018-11-22 21:21:33,554 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-22 21:21:33,554 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-22 21:21:33,554 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-22 21:21:33,555 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-22 21:21:33,555 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-22 21:21:33,563 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-22 21:21:33,600 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-22 21:21:33,600 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-22 21:21:33,600 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-22 21:21:33,600 INFO L799 eck$LassoCheckResult]: stem already infeasible [2018-11-22 21:21:33,601 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-22 21:21:33,601 INFO L82 PathProgramCache]: Analyzing trace with hash 1856687306, now seen corresponding path program 1 times [2018-11-22 21:21:33,601 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-22 21:21:33,601 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-22 21:21:33,602 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-22 21:21:33,602 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-22 21:21:33,602 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-22 21:21:33,622 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-22 21:21:33,676 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-22 21:21:33,676 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-22 21:21:33,677 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-22 21:21:33,677 INFO L811 eck$LassoCheckResult]: loop already infeasible [2018-11-22 21:21:33,677 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-22 21:21:33,677 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-22 21:21:33,678 INFO L87 Difference]: Start difference. First operand 900 states and 1355 transitions. cyclomatic complexity: 456 Second operand 3 states. [2018-11-22 21:21:33,691 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-22 21:21:33,691 INFO L93 Difference]: Finished difference Result 900 states and 1354 transitions. [2018-11-22 21:21:33,692 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-22 21:21:33,692 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 900 states and 1354 transitions. [2018-11-22 21:21:33,696 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 791 [2018-11-22 21:21:33,699 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 900 states to 900 states and 1354 transitions. [2018-11-22 21:21:33,699 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 900 [2018-11-22 21:21:33,700 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 900 [2018-11-22 21:21:33,700 INFO L73 IsDeterministic]: Start isDeterministic. Operand 900 states and 1354 transitions. [2018-11-22 21:21:33,701 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-22 21:21:33,702 INFO L705 BuchiCegarLoop]: Abstraction has 900 states and 1354 transitions. [2018-11-22 21:21:33,702 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 900 states and 1354 transitions. [2018-11-22 21:21:33,712 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 900 to 900. [2018-11-22 21:21:33,712 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 900 states. [2018-11-22 21:21:33,713 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 900 states to 900 states and 1354 transitions. [2018-11-22 21:21:33,714 INFO L728 BuchiCegarLoop]: Abstraction has 900 states and 1354 transitions. [2018-11-22 21:21:33,714 INFO L608 BuchiCegarLoop]: Abstraction has 900 states and 1354 transitions. [2018-11-22 21:21:33,714 INFO L442 BuchiCegarLoop]: ======== Iteration 3============ [2018-11-22 21:21:33,714 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 900 states and 1354 transitions. [2018-11-22 21:21:33,716 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 791 [2018-11-22 21:21:33,717 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-22 21:21:33,717 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-22 21:21:33,718 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-22 21:21:33,719 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-22 21:21:33,719 INFO L794 eck$LassoCheckResult]: Stem: 4064#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2; 3967#L-1 havoc main_#res;havoc main_~__retres1~10;havoc main_~__retres1~10;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 3968#L1225 havoc start_simulation_#t~ret20, start_simulation_#t~ret21, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 4392#L564 assume 1 == ~m_i~0;~m_st~0 := 0; 4001#L571-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 3714#L576-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 3715#L581-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 4394#L586-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 4180#L591-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 3814#L596-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 3815#L601-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 4386#L606-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 4302#L611-1 assume 0 == ~M_E~0;~M_E~0 := 1; 4303#L828-1 assume !(0 == ~T1_E~0); 4084#L833-1 assume !(0 == ~T2_E~0); 3829#L838-1 assume !(0 == ~T3_E~0); 3830#L843-1 assume !(0 == ~T4_E~0); 4462#L848-1 assume !(0 == ~T5_E~0); 4311#L853-1 assume !(0 == ~T6_E~0); 4068#L858-1 assume !(0 == ~T7_E~0); 3632#L863-1 assume 0 == ~T8_E~0;~T8_E~0 := 1; 3633#L868-1 assume !(0 == ~E_1~0); 4267#L873-1 assume !(0 == ~E_2~0); 4153#L878-1 assume !(0 == ~E_3~0); 3938#L883-1 assume !(0 == ~E_4~0); 3939#L888-1 assume !(0 == ~E_5~0); 4363#L893-1 assume !(0 == ~E_6~0); 4122#L898-1 assume !(0 == ~E_7~0); 4055#L903-1 assume 0 == ~E_8~0;~E_8~0 := 1; 3776#L908-1 havoc activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 3777#L392 assume 1 == ~m_pc~0; 4105#L393 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0 := 1; 4109#L403 is_master_triggered_#res := is_master_triggered_~__retres1~0; 4494#L404 activate_threads_#t~ret10 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 4370#L1025 assume !(0 != activate_threads_~tmp~1); 4371#L1025-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 4254#L411 assume !(1 == ~t1_pc~0); 4222#L411-2 is_transmit1_triggered_~__retres1~1 := 0; 3696#L422 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 3697#L423 activate_threads_#t~ret11 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 3795#L1033 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 4007#L1033-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 4008#L430 assume 1 == ~t2_pc~0; 4349#L431 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 3861#L441 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 3816#L442 activate_threads_#t~ret12 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 3817#L1041 assume !(0 != activate_threads_~tmp___1~0); 4512#L1041-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 4513#L449 assume !(1 == ~t3_pc~0); 4428#L449-2 is_transmit3_triggered_~__retres1~3 := 0; 4136#L460 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 3985#L461 activate_threads_#t~ret13 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 3986#L1049 assume !(0 != activate_threads_~tmp___2~0); 4390#L1049-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 3732#L468 assume 1 == ~t4_pc~0; 3733#L469 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 3741#L479 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 4115#L480 activate_threads_#t~ret14 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 4060#L1057 assume !(0 != activate_threads_~tmp___3~0); 4061#L1057-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 3924#L487 assume !(1 == ~t5_pc~0); 3692#L487-2 is_transmit5_triggered_~__retres1~5 := 0; 3691#L498 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 4242#L499 activate_threads_#t~ret15 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 4243#L1065 assume !(0 != activate_threads_~tmp___4~0); 4525#L1065-2 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 4067#L506 assume 1 == ~t6_pc~0; 3890#L507 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6 := 1; 3891#L517 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 4388#L518 activate_threads_#t~ret16 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 4324#L1073 assume !(0 != activate_threads_~tmp___5~0); 4325#L1073-2 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 4181#L525 assume 1 == ~t7_pc~0; 4130#L526 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7 := 1; 4131#L536 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 4514#L537 activate_threads_#t~ret17 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 3944#L1081 assume !(0 != activate_threads_~tmp___6~0); 3945#L1081-2 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 3946#L544 assume !(1 == ~t8_pc~0); 4193#L544-2 is_transmit8_triggered_~__retres1~8 := 0; 3626#L555 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 3627#L556 activate_threads_#t~ret18 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 3765#L1089 assume 0 != activate_threads_~tmp___7~0;~t8_st~0 := 0; 4412#L1089-2 assume !(1 == ~M_E~0); 4078#L921-1 assume !(1 == ~T1_E~0); 3825#L926-1 assume !(1 == ~T2_E~0); 3826#L931-1 assume !(1 == ~T3_E~0); 4460#L936-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 4319#L941-1 assume !(1 == ~T5_E~0); 4074#L946-1 assume !(1 == ~T6_E~0); 3642#L951-1 assume !(1 == ~T7_E~0); 3643#L956-1 assume !(1 == ~T8_E~0); 4391#L961-1 assume !(1 == ~E_1~0); 4158#L966-1 assume !(1 == ~E_2~0); 3950#L971-1 assume !(1 == ~E_3~0); 3951#L976-1 assume 1 == ~E_4~0;~E_4~0 := 2; 4359#L981-1 assume !(1 == ~E_5~0); 4120#L986-1 assume !(1 == ~E_6~0); 4050#L991-1 assume !(1 == ~E_7~0); 3771#L996-1 assume !(1 == ~E_8~0); 3772#L1262-1 [2018-11-22 21:21:33,719 INFO L796 eck$LassoCheckResult]: Loop: 3772#L1262-1 assume !false; 4482#L1263 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret0, eval_#t~nondet1, eval_~tmp_ndt_1~0, eval_#t~nondet2, eval_~tmp_ndt_2~0, eval_#t~nondet3, eval_~tmp_ndt_3~0, eval_#t~nondet4, eval_~tmp_ndt_4~0, eval_#t~nondet5, eval_~tmp_ndt_5~0, eval_#t~nondet6, eval_~tmp_ndt_6~0, eval_#t~nondet7, eval_~tmp_ndt_7~0, eval_#t~nondet8, eval_~tmp_ndt_8~0, eval_#t~nondet9, eval_~tmp_ndt_9~0, eval_~tmp~0;havoc eval_~tmp~0; 4086#L803 assume !false; 4071#L682 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~9;havoc exists_runnable_thread_~__retres1~9; 4072#L624 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9 := 1; 3757#L671 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~9; 4458#L672 eval_#t~ret0 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret0;havoc eval_#t~ret0; 3708#L686 assume !(0 != eval_~tmp~0); 3710#L818 start_simulation_~kernel_st~0 := 2; 3716#L564-1 start_simulation_~kernel_st~0 := 3; 4395#L828-2 assume 0 == ~M_E~0;~M_E~0 := 1; 4396#L828-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 4184#L833-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 3821#L838-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 3822#L843-3 assume !(0 == ~T4_E~0); 4456#L848-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 4315#L853-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 4070#L858-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 3637#L863-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 3638#L868-3 assume 0 == ~E_1~0;~E_1~0 := 1; 4268#L873-3 assume 0 == ~E_2~0;~E_2~0 := 1; 4154#L878-3 assume 0 == ~E_3~0;~E_3~0 := 1; 3941#L883-3 assume !(0 == ~E_4~0); 3942#L888-3 assume 0 == ~E_5~0;~E_5~0 := 1; 4367#L893-3 assume 0 == ~E_6~0;~E_6~0 := 1; 4123#L898-3 assume 0 == ~E_7~0;~E_7~0 := 1; 4041#L903-3 assume 0 == ~E_8~0;~E_8~0 := 1; 3769#L908-3 havoc activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 3770#L392-27 assume 1 == ~m_pc~0; 4168#L393-9 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0 := 1; 4169#L403-9 is_master_triggered_#res := is_master_triggered_~__retres1~0; 4492#L404-9 activate_threads_#t~ret10 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 4406#L1025-27 assume !(0 != activate_threads_~tmp~1); 4401#L1025-29 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 4195#L411-27 assume 1 == ~t1_pc~0; 4196#L412-9 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 3649#L422-9 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 3650#L423-9 activate_threads_#t~ret11 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 3778#L1033-27 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 3961#L1033-29 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 3965#L430-27 assume !(1 == ~t2_pc~0); 4343#L430-29 is_transmit2_triggered_~__retres1~2 := 0; 3857#L441-9 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 3858#L442-9 activate_threads_#t~ret12 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 3955#L1041-27 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 4475#L1041-29 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 4437#L449-27 assume 1 == ~t3_pc~0; 4407#L450-9 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 4013#L460-9 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 3959#L461-9 activate_threads_#t~ret13 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 3960#L1049-27 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 4214#L1049-29 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 4219#L468-27 assume 1 == ~t4_pc~0; 4487#L469-9 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 4282#L479-9 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 4100#L480-9 activate_threads_#t~ret14 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 3856#L1057-27 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 3831#L1057-29 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 3713#L487-27 assume 1 == ~t5_pc~0; 3686#L488-9 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 3687#L498-9 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 4240#L499-9 activate_threads_#t~ret15 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 4241#L1065-27 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 4443#L1065-29 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 4049#L506-27 assume 1 == ~t6_pc~0; 3848#L507-9 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6 := 1; 3849#L517-9 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 4373#L518-9 activate_threads_#t~ret16 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 4283#L1073-27 assume 0 != activate_threads_~tmp___5~0;~t6_st~0 := 0; 4125#L1073-29 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 4126#L525-27 assume 1 == ~t7_pc~0; 4036#L526-9 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7 := 1; 4037#L536-9 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 4454#L537-9 activate_threads_#t~ret17 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 3903#L1081-27 assume 0 != activate_threads_~tmp___6~0;~t7_st~0 := 0; 3904#L1081-29 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 3907#L544-27 assume 1 == ~t8_pc~0; 4277#L545-9 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8 := 1; 3788#L555-9 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 3724#L556-9 activate_threads_#t~ret18 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 3725#L1089-27 assume 0 != activate_threads_~tmp___7~0;~t8_st~0 := 0; 4463#L1089-29 assume !(1 == ~M_E~0); 4083#L921-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 3827#L926-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 3828#L931-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 4461#L936-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 4321#L941-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 4075#L946-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 3630#L951-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 3631#L956-3 assume !(1 == ~T8_E~0); 4266#L961-3 assume 1 == ~E_1~0;~E_1~0 := 2; 4151#L966-3 assume 1 == ~E_2~0;~E_2~0 := 2; 3936#L971-3 assume 1 == ~E_3~0;~E_3~0 := 2; 3937#L976-3 assume 1 == ~E_4~0;~E_4~0 := 2; 4362#L981-3 assume 1 == ~E_5~0;~E_5~0 := 2; 4121#L986-3 assume 1 == ~E_6~0;~E_6~0 := 2; 4054#L991-3 assume 1 == ~E_7~0;~E_7~0 := 2; 3773#L996-3 assume !(1 == ~E_8~0); 3774#L1001-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~9;havoc exists_runnable_thread_~__retres1~9; 4474#L624-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9 := 1; 3761#L671-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~9; 4459#L672-1 start_simulation_#t~ret20 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret20;havoc start_simulation_#t~ret20; 3670#L1281 assume !(0 == start_simulation_~tmp~3); 3671#L1281-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret19, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~9;havoc exists_runnable_thread_~__retres1~9; 3683#L624-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9 := 1; 3764#L671-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~9; 4384#L672-2 stop_simulation_#t~ret19 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret19;havoc stop_simulation_#t~ret19; 3900#L1236 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 3901#L1243 stop_simulation_#res := stop_simulation_~__retres2~0; 4421#L1244 start_simulation_#t~ret21 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret21;havoc start_simulation_#t~ret21; 4275#L1294 assume !(0 != start_simulation_~tmp___0~1); 3772#L1262-1 [2018-11-22 21:21:33,725 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-22 21:21:33,725 INFO L82 PathProgramCache]: Analyzing trace with hash 683460392, now seen corresponding path program 1 times [2018-11-22 21:21:33,725 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-22 21:21:33,725 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-22 21:21:33,726 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-22 21:21:33,726 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-22 21:21:33,726 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-22 21:21:33,735 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-22 21:21:33,762 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-22 21:21:33,762 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-22 21:21:33,762 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-22 21:21:33,763 INFO L799 eck$LassoCheckResult]: stem already infeasible [2018-11-22 21:21:33,763 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-22 21:21:33,763 INFO L82 PathProgramCache]: Analyzing trace with hash 1856687306, now seen corresponding path program 2 times [2018-11-22 21:21:33,763 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-22 21:21:33,763 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-22 21:21:33,764 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-22 21:21:33,764 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-22 21:21:33,764 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-22 21:21:33,773 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-22 21:21:33,824 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-22 21:21:33,824 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-22 21:21:33,825 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-22 21:21:33,825 INFO L811 eck$LassoCheckResult]: loop already infeasible [2018-11-22 21:21:33,825 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-22 21:21:33,825 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-22 21:21:33,825 INFO L87 Difference]: Start difference. First operand 900 states and 1354 transitions. cyclomatic complexity: 455 Second operand 3 states. [2018-11-22 21:21:33,835 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-22 21:21:33,835 INFO L93 Difference]: Finished difference Result 900 states and 1353 transitions. [2018-11-22 21:21:33,835 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-22 21:21:33,835 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 900 states and 1353 transitions. [2018-11-22 21:21:33,838 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 791 [2018-11-22 21:21:33,841 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 900 states to 900 states and 1353 transitions. [2018-11-22 21:21:33,841 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 900 [2018-11-22 21:21:33,841 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 900 [2018-11-22 21:21:33,841 INFO L73 IsDeterministic]: Start isDeterministic. Operand 900 states and 1353 transitions. [2018-11-22 21:21:33,842 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-22 21:21:33,842 INFO L705 BuchiCegarLoop]: Abstraction has 900 states and 1353 transitions. [2018-11-22 21:21:33,843 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 900 states and 1353 transitions. [2018-11-22 21:21:33,849 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 900 to 900. [2018-11-22 21:21:33,849 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 900 states. [2018-11-22 21:21:33,851 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 900 states to 900 states and 1353 transitions. [2018-11-22 21:21:33,851 INFO L728 BuchiCegarLoop]: Abstraction has 900 states and 1353 transitions. [2018-11-22 21:21:33,851 INFO L608 BuchiCegarLoop]: Abstraction has 900 states and 1353 transitions. [2018-11-22 21:21:33,851 INFO L442 BuchiCegarLoop]: ======== Iteration 4============ [2018-11-22 21:21:33,851 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 900 states and 1353 transitions. [2018-11-22 21:21:33,854 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 791 [2018-11-22 21:21:33,854 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-22 21:21:33,854 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-22 21:21:33,855 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-22 21:21:33,855 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-22 21:21:33,856 INFO L794 eck$LassoCheckResult]: Stem: 5871#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2; 5774#L-1 havoc main_#res;havoc main_~__retres1~10;havoc main_~__retres1~10;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 5775#L1225 havoc start_simulation_#t~ret20, start_simulation_#t~ret21, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 6199#L564 assume 1 == ~m_i~0;~m_st~0 := 0; 5808#L571-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 5521#L576-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 5522#L581-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 6201#L586-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 5987#L591-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 5621#L596-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 5622#L601-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 6193#L606-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 6109#L611-1 assume 0 == ~M_E~0;~M_E~0 := 1; 6110#L828-1 assume !(0 == ~T1_E~0); 5891#L833-1 assume !(0 == ~T2_E~0); 5636#L838-1 assume !(0 == ~T3_E~0); 5637#L843-1 assume !(0 == ~T4_E~0); 6269#L848-1 assume !(0 == ~T5_E~0); 6118#L853-1 assume !(0 == ~T6_E~0); 5875#L858-1 assume !(0 == ~T7_E~0); 5439#L863-1 assume 0 == ~T8_E~0;~T8_E~0 := 1; 5440#L868-1 assume !(0 == ~E_1~0); 6074#L873-1 assume !(0 == ~E_2~0); 5960#L878-1 assume !(0 == ~E_3~0); 5745#L883-1 assume !(0 == ~E_4~0); 5746#L888-1 assume !(0 == ~E_5~0); 6170#L893-1 assume !(0 == ~E_6~0); 5929#L898-1 assume !(0 == ~E_7~0); 5862#L903-1 assume 0 == ~E_8~0;~E_8~0 := 1; 5583#L908-1 havoc activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 5584#L392 assume 1 == ~m_pc~0; 5912#L393 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0 := 1; 5916#L403 is_master_triggered_#res := is_master_triggered_~__retres1~0; 6301#L404 activate_threads_#t~ret10 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 6177#L1025 assume !(0 != activate_threads_~tmp~1); 6178#L1025-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 6061#L411 assume !(1 == ~t1_pc~0); 6029#L411-2 is_transmit1_triggered_~__retres1~1 := 0; 5503#L422 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 5504#L423 activate_threads_#t~ret11 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 5602#L1033 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 5814#L1033-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 5815#L430 assume 1 == ~t2_pc~0; 6156#L431 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 5668#L441 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 5623#L442 activate_threads_#t~ret12 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 5624#L1041 assume !(0 != activate_threads_~tmp___1~0); 6319#L1041-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 6320#L449 assume !(1 == ~t3_pc~0); 6235#L449-2 is_transmit3_triggered_~__retres1~3 := 0; 5943#L460 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 5792#L461 activate_threads_#t~ret13 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 5793#L1049 assume !(0 != activate_threads_~tmp___2~0); 6197#L1049-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 5539#L468 assume 1 == ~t4_pc~0; 5540#L469 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 5548#L479 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 5922#L480 activate_threads_#t~ret14 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 5867#L1057 assume !(0 != activate_threads_~tmp___3~0); 5868#L1057-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 5731#L487 assume !(1 == ~t5_pc~0); 5499#L487-2 is_transmit5_triggered_~__retres1~5 := 0; 5498#L498 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 6049#L499 activate_threads_#t~ret15 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 6050#L1065 assume !(0 != activate_threads_~tmp___4~0); 6332#L1065-2 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 5874#L506 assume 1 == ~t6_pc~0; 5697#L507 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6 := 1; 5698#L517 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 6195#L518 activate_threads_#t~ret16 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 6131#L1073 assume !(0 != activate_threads_~tmp___5~0); 6132#L1073-2 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 5988#L525 assume 1 == ~t7_pc~0; 5937#L526 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7 := 1; 5938#L536 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 6321#L537 activate_threads_#t~ret17 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 5751#L1081 assume !(0 != activate_threads_~tmp___6~0); 5752#L1081-2 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 5753#L544 assume !(1 == ~t8_pc~0); 6000#L544-2 is_transmit8_triggered_~__retres1~8 := 0; 5433#L555 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 5434#L556 activate_threads_#t~ret18 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 5572#L1089 assume 0 != activate_threads_~tmp___7~0;~t8_st~0 := 0; 6219#L1089-2 assume !(1 == ~M_E~0); 5885#L921-1 assume !(1 == ~T1_E~0); 5632#L926-1 assume !(1 == ~T2_E~0); 5633#L931-1 assume !(1 == ~T3_E~0); 6267#L936-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 6126#L941-1 assume !(1 == ~T5_E~0); 5881#L946-1 assume !(1 == ~T6_E~0); 5449#L951-1 assume !(1 == ~T7_E~0); 5450#L956-1 assume !(1 == ~T8_E~0); 6198#L961-1 assume !(1 == ~E_1~0); 5965#L966-1 assume !(1 == ~E_2~0); 5757#L971-1 assume !(1 == ~E_3~0); 5758#L976-1 assume 1 == ~E_4~0;~E_4~0 := 2; 6166#L981-1 assume !(1 == ~E_5~0); 5927#L986-1 assume !(1 == ~E_6~0); 5857#L991-1 assume !(1 == ~E_7~0); 5578#L996-1 assume !(1 == ~E_8~0); 5579#L1262-1 [2018-11-22 21:21:33,856 INFO L796 eck$LassoCheckResult]: Loop: 5579#L1262-1 assume !false; 6289#L1263 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret0, eval_#t~nondet1, eval_~tmp_ndt_1~0, eval_#t~nondet2, eval_~tmp_ndt_2~0, eval_#t~nondet3, eval_~tmp_ndt_3~0, eval_#t~nondet4, eval_~tmp_ndt_4~0, eval_#t~nondet5, eval_~tmp_ndt_5~0, eval_#t~nondet6, eval_~tmp_ndt_6~0, eval_#t~nondet7, eval_~tmp_ndt_7~0, eval_#t~nondet8, eval_~tmp_ndt_8~0, eval_#t~nondet9, eval_~tmp_ndt_9~0, eval_~tmp~0;havoc eval_~tmp~0; 5893#L803 assume !false; 5878#L682 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~9;havoc exists_runnable_thread_~__retres1~9; 5879#L624 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9 := 1; 5564#L671 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~9; 6265#L672 eval_#t~ret0 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret0;havoc eval_#t~ret0; 5515#L686 assume !(0 != eval_~tmp~0); 5517#L818 start_simulation_~kernel_st~0 := 2; 5523#L564-1 start_simulation_~kernel_st~0 := 3; 6202#L828-2 assume 0 == ~M_E~0;~M_E~0 := 1; 6203#L828-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 5991#L833-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 5628#L838-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 5629#L843-3 assume !(0 == ~T4_E~0); 6263#L848-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 6122#L853-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 5877#L858-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 5444#L863-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 5445#L868-3 assume 0 == ~E_1~0;~E_1~0 := 1; 6075#L873-3 assume 0 == ~E_2~0;~E_2~0 := 1; 5961#L878-3 assume 0 == ~E_3~0;~E_3~0 := 1; 5748#L883-3 assume !(0 == ~E_4~0); 5749#L888-3 assume 0 == ~E_5~0;~E_5~0 := 1; 6174#L893-3 assume 0 == ~E_6~0;~E_6~0 := 1; 5930#L898-3 assume 0 == ~E_7~0;~E_7~0 := 1; 5848#L903-3 assume 0 == ~E_8~0;~E_8~0 := 1; 5576#L908-3 havoc activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 5577#L392-27 assume 1 == ~m_pc~0; 5975#L393-9 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0 := 1; 5976#L403-9 is_master_triggered_#res := is_master_triggered_~__retres1~0; 6299#L404-9 activate_threads_#t~ret10 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 6213#L1025-27 assume !(0 != activate_threads_~tmp~1); 6208#L1025-29 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 6002#L411-27 assume 1 == ~t1_pc~0; 6003#L412-9 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 5456#L422-9 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 5457#L423-9 activate_threads_#t~ret11 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 5585#L1033-27 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 5768#L1033-29 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 5772#L430-27 assume !(1 == ~t2_pc~0); 6150#L430-29 is_transmit2_triggered_~__retres1~2 := 0; 5664#L441-9 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 5665#L442-9 activate_threads_#t~ret12 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 5762#L1041-27 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 6282#L1041-29 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 6244#L449-27 assume 1 == ~t3_pc~0; 6214#L450-9 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 5820#L460-9 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 5766#L461-9 activate_threads_#t~ret13 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 5767#L1049-27 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 6021#L1049-29 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 6026#L468-27 assume 1 == ~t4_pc~0; 6294#L469-9 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 6089#L479-9 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 5907#L480-9 activate_threads_#t~ret14 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 5663#L1057-27 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 5638#L1057-29 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 5520#L487-27 assume 1 == ~t5_pc~0; 5493#L488-9 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 5494#L498-9 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 6047#L499-9 activate_threads_#t~ret15 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 6048#L1065-27 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 6250#L1065-29 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 5856#L506-27 assume 1 == ~t6_pc~0; 5655#L507-9 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6 := 1; 5656#L517-9 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 6180#L518-9 activate_threads_#t~ret16 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 6090#L1073-27 assume 0 != activate_threads_~tmp___5~0;~t6_st~0 := 0; 5932#L1073-29 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 5933#L525-27 assume 1 == ~t7_pc~0; 5843#L526-9 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7 := 1; 5844#L536-9 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 6261#L537-9 activate_threads_#t~ret17 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 5710#L1081-27 assume 0 != activate_threads_~tmp___6~0;~t7_st~0 := 0; 5711#L1081-29 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 5714#L544-27 assume 1 == ~t8_pc~0; 6084#L545-9 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8 := 1; 5595#L555-9 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 5531#L556-9 activate_threads_#t~ret18 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 5532#L1089-27 assume 0 != activate_threads_~tmp___7~0;~t8_st~0 := 0; 6270#L1089-29 assume !(1 == ~M_E~0); 5890#L921-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 5634#L926-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 5635#L931-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 6268#L936-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 6128#L941-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 5882#L946-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 5437#L951-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 5438#L956-3 assume !(1 == ~T8_E~0); 6073#L961-3 assume 1 == ~E_1~0;~E_1~0 := 2; 5958#L966-3 assume 1 == ~E_2~0;~E_2~0 := 2; 5743#L971-3 assume 1 == ~E_3~0;~E_3~0 := 2; 5744#L976-3 assume 1 == ~E_4~0;~E_4~0 := 2; 6169#L981-3 assume 1 == ~E_5~0;~E_5~0 := 2; 5928#L986-3 assume 1 == ~E_6~0;~E_6~0 := 2; 5861#L991-3 assume 1 == ~E_7~0;~E_7~0 := 2; 5580#L996-3 assume !(1 == ~E_8~0); 5581#L1001-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~9;havoc exists_runnable_thread_~__retres1~9; 6281#L624-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9 := 1; 5568#L671-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~9; 6266#L672-1 start_simulation_#t~ret20 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret20;havoc start_simulation_#t~ret20; 5477#L1281 assume !(0 == start_simulation_~tmp~3); 5478#L1281-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret19, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~9;havoc exists_runnable_thread_~__retres1~9; 5490#L624-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9 := 1; 5571#L671-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~9; 6191#L672-2 stop_simulation_#t~ret19 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret19;havoc stop_simulation_#t~ret19; 5707#L1236 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 5708#L1243 stop_simulation_#res := stop_simulation_~__retres2~0; 6228#L1244 start_simulation_#t~ret21 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret21;havoc start_simulation_#t~ret21; 6082#L1294 assume !(0 != start_simulation_~tmp___0~1); 5579#L1262-1 [2018-11-22 21:21:33,856 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-22 21:21:33,856 INFO L82 PathProgramCache]: Analyzing trace with hash -1992531990, now seen corresponding path program 1 times [2018-11-22 21:21:33,856 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-22 21:21:33,856 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-22 21:21:33,857 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-22 21:21:33,857 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-22 21:21:33,857 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-22 21:21:33,863 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-22 21:21:33,886 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-22 21:21:33,887 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-22 21:21:33,887 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-22 21:21:33,887 INFO L799 eck$LassoCheckResult]: stem already infeasible [2018-11-22 21:21:33,887 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-22 21:21:33,887 INFO L82 PathProgramCache]: Analyzing trace with hash 1856687306, now seen corresponding path program 3 times [2018-11-22 21:21:33,887 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-22 21:21:33,888 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-22 21:21:33,888 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-22 21:21:33,888 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-22 21:21:33,888 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-22 21:21:33,897 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-22 21:21:33,928 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-22 21:21:33,928 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-22 21:21:33,928 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-22 21:21:33,928 INFO L811 eck$LassoCheckResult]: loop already infeasible [2018-11-22 21:21:33,929 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-22 21:21:33,929 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-22 21:21:33,929 INFO L87 Difference]: Start difference. First operand 900 states and 1353 transitions. cyclomatic complexity: 454 Second operand 3 states. [2018-11-22 21:21:33,941 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-22 21:21:33,942 INFO L93 Difference]: Finished difference Result 900 states and 1352 transitions. [2018-11-22 21:21:33,942 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-22 21:21:33,942 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 900 states and 1352 transitions. [2018-11-22 21:21:33,945 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 791 [2018-11-22 21:21:33,948 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 900 states to 900 states and 1352 transitions. [2018-11-22 21:21:33,948 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 900 [2018-11-22 21:21:33,948 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 900 [2018-11-22 21:21:33,948 INFO L73 IsDeterministic]: Start isDeterministic. Operand 900 states and 1352 transitions. [2018-11-22 21:21:33,949 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-22 21:21:33,949 INFO L705 BuchiCegarLoop]: Abstraction has 900 states and 1352 transitions. [2018-11-22 21:21:33,950 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 900 states and 1352 transitions. [2018-11-22 21:21:33,956 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 900 to 900. [2018-11-22 21:21:33,957 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 900 states. [2018-11-22 21:21:33,958 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 900 states to 900 states and 1352 transitions. [2018-11-22 21:21:33,958 INFO L728 BuchiCegarLoop]: Abstraction has 900 states and 1352 transitions. [2018-11-22 21:21:33,958 INFO L608 BuchiCegarLoop]: Abstraction has 900 states and 1352 transitions. [2018-11-22 21:21:33,958 INFO L442 BuchiCegarLoop]: ======== Iteration 5============ [2018-11-22 21:21:33,959 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 900 states and 1352 transitions. [2018-11-22 21:21:33,961 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 791 [2018-11-22 21:21:33,961 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-22 21:21:33,961 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-22 21:21:33,962 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-22 21:21:33,962 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-22 21:21:33,963 INFO L794 eck$LassoCheckResult]: Stem: 7678#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2; 7581#L-1 havoc main_#res;havoc main_~__retres1~10;havoc main_~__retres1~10;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 7582#L1225 havoc start_simulation_#t~ret20, start_simulation_#t~ret21, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 8006#L564 assume 1 == ~m_i~0;~m_st~0 := 0; 7615#L571-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 7328#L576-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 7329#L581-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 8008#L586-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 7794#L591-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 7428#L596-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 7429#L601-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 8000#L606-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 7916#L611-1 assume 0 == ~M_E~0;~M_E~0 := 1; 7917#L828-1 assume !(0 == ~T1_E~0); 7698#L833-1 assume !(0 == ~T2_E~0); 7443#L838-1 assume !(0 == ~T3_E~0); 7444#L843-1 assume !(0 == ~T4_E~0); 8076#L848-1 assume !(0 == ~T5_E~0); 7925#L853-1 assume !(0 == ~T6_E~0); 7682#L858-1 assume !(0 == ~T7_E~0); 7246#L863-1 assume 0 == ~T8_E~0;~T8_E~0 := 1; 7247#L868-1 assume !(0 == ~E_1~0); 7881#L873-1 assume !(0 == ~E_2~0); 7767#L878-1 assume !(0 == ~E_3~0); 7552#L883-1 assume !(0 == ~E_4~0); 7553#L888-1 assume !(0 == ~E_5~0); 7977#L893-1 assume !(0 == ~E_6~0); 7736#L898-1 assume !(0 == ~E_7~0); 7669#L903-1 assume 0 == ~E_8~0;~E_8~0 := 1; 7390#L908-1 havoc activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 7391#L392 assume 1 == ~m_pc~0; 7719#L393 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0 := 1; 7723#L403 is_master_triggered_#res := is_master_triggered_~__retres1~0; 8108#L404 activate_threads_#t~ret10 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 7984#L1025 assume !(0 != activate_threads_~tmp~1); 7985#L1025-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 7868#L411 assume !(1 == ~t1_pc~0); 7836#L411-2 is_transmit1_triggered_~__retres1~1 := 0; 7310#L422 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 7311#L423 activate_threads_#t~ret11 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 7409#L1033 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 7621#L1033-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 7622#L430 assume 1 == ~t2_pc~0; 7963#L431 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 7475#L441 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 7430#L442 activate_threads_#t~ret12 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 7431#L1041 assume !(0 != activate_threads_~tmp___1~0); 8126#L1041-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 8127#L449 assume !(1 == ~t3_pc~0); 8042#L449-2 is_transmit3_triggered_~__retres1~3 := 0; 7750#L460 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 7599#L461 activate_threads_#t~ret13 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 7600#L1049 assume !(0 != activate_threads_~tmp___2~0); 8004#L1049-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 7346#L468 assume 1 == ~t4_pc~0; 7347#L469 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 7355#L479 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 7729#L480 activate_threads_#t~ret14 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 7674#L1057 assume !(0 != activate_threads_~tmp___3~0); 7675#L1057-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 7538#L487 assume !(1 == ~t5_pc~0); 7306#L487-2 is_transmit5_triggered_~__retres1~5 := 0; 7305#L498 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 7856#L499 activate_threads_#t~ret15 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 7857#L1065 assume !(0 != activate_threads_~tmp___4~0); 8139#L1065-2 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 7681#L506 assume 1 == ~t6_pc~0; 7504#L507 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6 := 1; 7505#L517 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 8002#L518 activate_threads_#t~ret16 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 7938#L1073 assume !(0 != activate_threads_~tmp___5~0); 7939#L1073-2 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 7795#L525 assume 1 == ~t7_pc~0; 7744#L526 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7 := 1; 7745#L536 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 8128#L537 activate_threads_#t~ret17 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 7558#L1081 assume !(0 != activate_threads_~tmp___6~0); 7559#L1081-2 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 7560#L544 assume !(1 == ~t8_pc~0); 7807#L544-2 is_transmit8_triggered_~__retres1~8 := 0; 7240#L555 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 7241#L556 activate_threads_#t~ret18 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 7379#L1089 assume 0 != activate_threads_~tmp___7~0;~t8_st~0 := 0; 8026#L1089-2 assume !(1 == ~M_E~0); 7692#L921-1 assume !(1 == ~T1_E~0); 7439#L926-1 assume !(1 == ~T2_E~0); 7440#L931-1 assume !(1 == ~T3_E~0); 8074#L936-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 7933#L941-1 assume !(1 == ~T5_E~0); 7688#L946-1 assume !(1 == ~T6_E~0); 7256#L951-1 assume !(1 == ~T7_E~0); 7257#L956-1 assume !(1 == ~T8_E~0); 8005#L961-1 assume !(1 == ~E_1~0); 7772#L966-1 assume !(1 == ~E_2~0); 7564#L971-1 assume !(1 == ~E_3~0); 7565#L976-1 assume 1 == ~E_4~0;~E_4~0 := 2; 7973#L981-1 assume !(1 == ~E_5~0); 7734#L986-1 assume !(1 == ~E_6~0); 7664#L991-1 assume !(1 == ~E_7~0); 7385#L996-1 assume !(1 == ~E_8~0); 7386#L1262-1 [2018-11-22 21:21:33,963 INFO L796 eck$LassoCheckResult]: Loop: 7386#L1262-1 assume !false; 8096#L1263 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret0, eval_#t~nondet1, eval_~tmp_ndt_1~0, eval_#t~nondet2, eval_~tmp_ndt_2~0, eval_#t~nondet3, eval_~tmp_ndt_3~0, eval_#t~nondet4, eval_~tmp_ndt_4~0, eval_#t~nondet5, eval_~tmp_ndt_5~0, eval_#t~nondet6, eval_~tmp_ndt_6~0, eval_#t~nondet7, eval_~tmp_ndt_7~0, eval_#t~nondet8, eval_~tmp_ndt_8~0, eval_#t~nondet9, eval_~tmp_ndt_9~0, eval_~tmp~0;havoc eval_~tmp~0; 7700#L803 assume !false; 7685#L682 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~9;havoc exists_runnable_thread_~__retres1~9; 7686#L624 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9 := 1; 7371#L671 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~9; 8072#L672 eval_#t~ret0 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret0;havoc eval_#t~ret0; 7322#L686 assume !(0 != eval_~tmp~0); 7324#L818 start_simulation_~kernel_st~0 := 2; 7330#L564-1 start_simulation_~kernel_st~0 := 3; 8009#L828-2 assume 0 == ~M_E~0;~M_E~0 := 1; 8010#L828-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 7798#L833-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 7435#L838-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 7436#L843-3 assume !(0 == ~T4_E~0); 8070#L848-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 7929#L853-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 7684#L858-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 7251#L863-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 7252#L868-3 assume 0 == ~E_1~0;~E_1~0 := 1; 7882#L873-3 assume 0 == ~E_2~0;~E_2~0 := 1; 7768#L878-3 assume 0 == ~E_3~0;~E_3~0 := 1; 7555#L883-3 assume !(0 == ~E_4~0); 7556#L888-3 assume 0 == ~E_5~0;~E_5~0 := 1; 7981#L893-3 assume 0 == ~E_6~0;~E_6~0 := 1; 7737#L898-3 assume 0 == ~E_7~0;~E_7~0 := 1; 7655#L903-3 assume 0 == ~E_8~0;~E_8~0 := 1; 7383#L908-3 havoc activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 7384#L392-27 assume 1 == ~m_pc~0; 7782#L393-9 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0 := 1; 7783#L403-9 is_master_triggered_#res := is_master_triggered_~__retres1~0; 8106#L404-9 activate_threads_#t~ret10 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 8020#L1025-27 assume !(0 != activate_threads_~tmp~1); 8015#L1025-29 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 7809#L411-27 assume 1 == ~t1_pc~0; 7810#L412-9 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 7263#L422-9 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 7264#L423-9 activate_threads_#t~ret11 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 7392#L1033-27 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 7575#L1033-29 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 7579#L430-27 assume !(1 == ~t2_pc~0); 7957#L430-29 is_transmit2_triggered_~__retres1~2 := 0; 7471#L441-9 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 7472#L442-9 activate_threads_#t~ret12 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 7569#L1041-27 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 8089#L1041-29 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 8051#L449-27 assume 1 == ~t3_pc~0; 8021#L450-9 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 7627#L460-9 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 7573#L461-9 activate_threads_#t~ret13 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 7574#L1049-27 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 7828#L1049-29 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 7833#L468-27 assume 1 == ~t4_pc~0; 8101#L469-9 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 7896#L479-9 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 7714#L480-9 activate_threads_#t~ret14 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 7470#L1057-27 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 7445#L1057-29 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 7327#L487-27 assume 1 == ~t5_pc~0; 7300#L488-9 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 7301#L498-9 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 7854#L499-9 activate_threads_#t~ret15 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 7855#L1065-27 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 8057#L1065-29 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 7663#L506-27 assume 1 == ~t6_pc~0; 7462#L507-9 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6 := 1; 7463#L517-9 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 7987#L518-9 activate_threads_#t~ret16 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 7897#L1073-27 assume 0 != activate_threads_~tmp___5~0;~t6_st~0 := 0; 7739#L1073-29 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 7740#L525-27 assume 1 == ~t7_pc~0; 7650#L526-9 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7 := 1; 7651#L536-9 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 8068#L537-9 activate_threads_#t~ret17 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 7517#L1081-27 assume 0 != activate_threads_~tmp___6~0;~t7_st~0 := 0; 7518#L1081-29 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 7521#L544-27 assume 1 == ~t8_pc~0; 7891#L545-9 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8 := 1; 7402#L555-9 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 7338#L556-9 activate_threads_#t~ret18 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 7339#L1089-27 assume 0 != activate_threads_~tmp___7~0;~t8_st~0 := 0; 8077#L1089-29 assume !(1 == ~M_E~0); 7697#L921-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 7441#L926-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 7442#L931-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 8075#L936-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 7935#L941-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 7689#L946-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 7244#L951-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 7245#L956-3 assume !(1 == ~T8_E~0); 7880#L961-3 assume 1 == ~E_1~0;~E_1~0 := 2; 7765#L966-3 assume 1 == ~E_2~0;~E_2~0 := 2; 7550#L971-3 assume 1 == ~E_3~0;~E_3~0 := 2; 7551#L976-3 assume 1 == ~E_4~0;~E_4~0 := 2; 7976#L981-3 assume 1 == ~E_5~0;~E_5~0 := 2; 7735#L986-3 assume 1 == ~E_6~0;~E_6~0 := 2; 7668#L991-3 assume 1 == ~E_7~0;~E_7~0 := 2; 7387#L996-3 assume !(1 == ~E_8~0); 7388#L1001-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~9;havoc exists_runnable_thread_~__retres1~9; 8088#L624-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9 := 1; 7375#L671-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~9; 8073#L672-1 start_simulation_#t~ret20 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret20;havoc start_simulation_#t~ret20; 7284#L1281 assume !(0 == start_simulation_~tmp~3); 7285#L1281-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret19, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~9;havoc exists_runnable_thread_~__retres1~9; 7297#L624-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9 := 1; 7378#L671-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~9; 7998#L672-2 stop_simulation_#t~ret19 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret19;havoc stop_simulation_#t~ret19; 7514#L1236 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 7515#L1243 stop_simulation_#res := stop_simulation_~__retres2~0; 8035#L1244 start_simulation_#t~ret21 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret21;havoc start_simulation_#t~ret21; 7889#L1294 assume !(0 != start_simulation_~tmp___0~1); 7386#L1262-1 [2018-11-22 21:21:33,963 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-22 21:21:33,964 INFO L82 PathProgramCache]: Analyzing trace with hash -1109023000, now seen corresponding path program 1 times [2018-11-22 21:21:33,964 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-22 21:21:33,964 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-22 21:21:33,964 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-22 21:21:33,964 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-22 21:21:33,964 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-22 21:21:33,969 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-22 21:21:33,994 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-22 21:21:33,994 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-22 21:21:33,995 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-22 21:21:33,995 INFO L799 eck$LassoCheckResult]: stem already infeasible [2018-11-22 21:21:33,995 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-22 21:21:33,995 INFO L82 PathProgramCache]: Analyzing trace with hash 1856687306, now seen corresponding path program 4 times [2018-11-22 21:21:33,995 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-22 21:21:33,995 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-22 21:21:33,996 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-22 21:21:33,996 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-22 21:21:33,996 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-22 21:21:34,003 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-22 21:21:34,037 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-22 21:21:34,037 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-22 21:21:34,037 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-22 21:21:34,038 INFO L811 eck$LassoCheckResult]: loop already infeasible [2018-11-22 21:21:34,038 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-22 21:21:34,038 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-22 21:21:34,038 INFO L87 Difference]: Start difference. First operand 900 states and 1352 transitions. cyclomatic complexity: 453 Second operand 3 states. [2018-11-22 21:21:34,061 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-22 21:21:34,061 INFO L93 Difference]: Finished difference Result 900 states and 1351 transitions. [2018-11-22 21:21:34,062 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-22 21:21:34,062 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 900 states and 1351 transitions. [2018-11-22 21:21:34,066 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 791 [2018-11-22 21:21:34,069 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 900 states to 900 states and 1351 transitions. [2018-11-22 21:21:34,070 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 900 [2018-11-22 21:21:34,070 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 900 [2018-11-22 21:21:34,071 INFO L73 IsDeterministic]: Start isDeterministic. Operand 900 states and 1351 transitions. [2018-11-22 21:21:34,072 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-22 21:21:34,072 INFO L705 BuchiCegarLoop]: Abstraction has 900 states and 1351 transitions. [2018-11-22 21:21:34,073 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 900 states and 1351 transitions. [2018-11-22 21:21:34,082 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 900 to 900. [2018-11-22 21:21:34,083 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 900 states. [2018-11-22 21:21:34,084 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 900 states to 900 states and 1351 transitions. [2018-11-22 21:21:34,085 INFO L728 BuchiCegarLoop]: Abstraction has 900 states and 1351 transitions. [2018-11-22 21:21:34,085 INFO L608 BuchiCegarLoop]: Abstraction has 900 states and 1351 transitions. [2018-11-22 21:21:34,085 INFO L442 BuchiCegarLoop]: ======== Iteration 6============ [2018-11-22 21:21:34,085 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 900 states and 1351 transitions. [2018-11-22 21:21:34,088 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 791 [2018-11-22 21:21:34,088 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-22 21:21:34,089 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-22 21:21:34,090 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-22 21:21:34,090 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-22 21:21:34,090 INFO L794 eck$LassoCheckResult]: Stem: 9485#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2; 9388#L-1 havoc main_#res;havoc main_~__retres1~10;havoc main_~__retres1~10;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 9389#L1225 havoc start_simulation_#t~ret20, start_simulation_#t~ret21, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 9813#L564 assume 1 == ~m_i~0;~m_st~0 := 0; 9422#L571-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 9135#L576-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 9136#L581-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 9815#L586-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 9601#L591-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 9235#L596-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 9236#L601-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 9807#L606-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 9723#L611-1 assume 0 == ~M_E~0;~M_E~0 := 1; 9724#L828-1 assume !(0 == ~T1_E~0); 9505#L833-1 assume !(0 == ~T2_E~0); 9250#L838-1 assume !(0 == ~T3_E~0); 9251#L843-1 assume !(0 == ~T4_E~0); 9883#L848-1 assume !(0 == ~T5_E~0); 9733#L853-1 assume !(0 == ~T6_E~0); 9489#L858-1 assume !(0 == ~T7_E~0); 9053#L863-1 assume 0 == ~T8_E~0;~T8_E~0 := 1; 9054#L868-1 assume !(0 == ~E_1~0); 9688#L873-1 assume !(0 == ~E_2~0); 9574#L878-1 assume !(0 == ~E_3~0); 9359#L883-1 assume !(0 == ~E_4~0); 9360#L888-1 assume !(0 == ~E_5~0); 9786#L893-1 assume !(0 == ~E_6~0); 9543#L898-1 assume !(0 == ~E_7~0); 9477#L903-1 assume 0 == ~E_8~0;~E_8~0 := 1; 9197#L908-1 havoc activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 9198#L392 assume 1 == ~m_pc~0; 9526#L393 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0 := 1; 9530#L403 is_master_triggered_#res := is_master_triggered_~__retres1~0; 9915#L404 activate_threads_#t~ret10 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 9791#L1025 assume !(0 != activate_threads_~tmp~1); 9792#L1025-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 9675#L411 assume !(1 == ~t1_pc~0); 9644#L411-2 is_transmit1_triggered_~__retres1~1 := 0; 9120#L422 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 9121#L423 activate_threads_#t~ret11 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 9217#L1033 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 9428#L1033-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 9429#L430 assume 1 == ~t2_pc~0; 9770#L431 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 9282#L441 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 9237#L442 activate_threads_#t~ret12 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 9238#L1041 assume !(0 != activate_threads_~tmp___1~0); 9933#L1041-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 9934#L449 assume !(1 == ~t3_pc~0); 9849#L449-2 is_transmit3_triggered_~__retres1~3 := 0; 9557#L460 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 9406#L461 activate_threads_#t~ret13 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 9407#L1049 assume !(0 != activate_threads_~tmp___2~0); 9811#L1049-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 9153#L468 assume 1 == ~t4_pc~0; 9154#L469 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 9162#L479 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 9536#L480 activate_threads_#t~ret14 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 9481#L1057 assume !(0 != activate_threads_~tmp___3~0); 9482#L1057-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 9345#L487 assume !(1 == ~t5_pc~0); 9113#L487-2 is_transmit5_triggered_~__retres1~5 := 0; 9112#L498 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 9663#L499 activate_threads_#t~ret15 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 9664#L1065 assume !(0 != activate_threads_~tmp___4~0); 9946#L1065-2 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 9488#L506 assume 1 == ~t6_pc~0; 9311#L507 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6 := 1; 9312#L517 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 9809#L518 activate_threads_#t~ret16 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 9745#L1073 assume !(0 != activate_threads_~tmp___5~0); 9746#L1073-2 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 9602#L525 assume 1 == ~t7_pc~0; 9551#L526 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7 := 1; 9552#L536 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 9935#L537 activate_threads_#t~ret17 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 9365#L1081 assume !(0 != activate_threads_~tmp___6~0); 9366#L1081-2 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 9367#L544 assume !(1 == ~t8_pc~0); 9614#L544-2 is_transmit8_triggered_~__retres1~8 := 0; 9047#L555 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 9048#L556 activate_threads_#t~ret18 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 9186#L1089 assume 0 != activate_threads_~tmp___7~0;~t8_st~0 := 0; 9833#L1089-2 assume !(1 == ~M_E~0); 9499#L921-1 assume !(1 == ~T1_E~0); 9246#L926-1 assume !(1 == ~T2_E~0); 9247#L931-1 assume !(1 == ~T3_E~0); 9881#L936-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 9740#L941-1 assume !(1 == ~T5_E~0); 9495#L946-1 assume !(1 == ~T6_E~0); 9063#L951-1 assume !(1 == ~T7_E~0); 9064#L956-1 assume !(1 == ~T8_E~0); 9812#L961-1 assume !(1 == ~E_1~0); 9579#L966-1 assume !(1 == ~E_2~0); 9371#L971-1 assume !(1 == ~E_3~0); 9372#L976-1 assume 1 == ~E_4~0;~E_4~0 := 2; 9780#L981-1 assume !(1 == ~E_5~0); 9541#L986-1 assume !(1 == ~E_6~0); 9471#L991-1 assume !(1 == ~E_7~0); 9192#L996-1 assume !(1 == ~E_8~0); 9193#L1262-1 [2018-11-22 21:21:34,091 INFO L796 eck$LassoCheckResult]: Loop: 9193#L1262-1 assume !false; 9903#L1263 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret0, eval_#t~nondet1, eval_~tmp_ndt_1~0, eval_#t~nondet2, eval_~tmp_ndt_2~0, eval_#t~nondet3, eval_~tmp_ndt_3~0, eval_#t~nondet4, eval_~tmp_ndt_4~0, eval_#t~nondet5, eval_~tmp_ndt_5~0, eval_#t~nondet6, eval_~tmp_ndt_6~0, eval_#t~nondet7, eval_~tmp_ndt_7~0, eval_#t~nondet8, eval_~tmp_ndt_8~0, eval_#t~nondet9, eval_~tmp_ndt_9~0, eval_~tmp~0;havoc eval_~tmp~0; 9507#L803 assume !false; 9492#L682 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~9;havoc exists_runnable_thread_~__retres1~9; 9493#L624 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9 := 1; 9178#L671 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~9; 9879#L672 eval_#t~ret0 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret0;havoc eval_#t~ret0; 9129#L686 assume !(0 != eval_~tmp~0); 9131#L818 start_simulation_~kernel_st~0 := 2; 9137#L564-1 start_simulation_~kernel_st~0 := 3; 9816#L828-2 assume 0 == ~M_E~0;~M_E~0 := 1; 9817#L828-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 9605#L833-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 9242#L838-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 9243#L843-3 assume !(0 == ~T4_E~0); 9877#L848-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 9736#L853-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 9491#L858-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 9058#L863-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 9059#L868-3 assume 0 == ~E_1~0;~E_1~0 := 1; 9689#L873-3 assume 0 == ~E_2~0;~E_2~0 := 1; 9575#L878-3 assume 0 == ~E_3~0;~E_3~0 := 1; 9362#L883-3 assume !(0 == ~E_4~0); 9363#L888-3 assume 0 == ~E_5~0;~E_5~0 := 1; 9788#L893-3 assume 0 == ~E_6~0;~E_6~0 := 1; 9544#L898-3 assume 0 == ~E_7~0;~E_7~0 := 1; 9462#L903-3 assume 0 == ~E_8~0;~E_8~0 := 1; 9190#L908-3 havoc activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 9191#L392-27 assume 1 == ~m_pc~0; 9589#L393-9 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0 := 1; 9590#L403-9 is_master_triggered_#res := is_master_triggered_~__retres1~0; 9913#L404-9 activate_threads_#t~ret10 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 9827#L1025-27 assume !(0 != activate_threads_~tmp~1); 9822#L1025-29 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 9616#L411-27 assume 1 == ~t1_pc~0; 9617#L412-9 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 9070#L422-9 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 9071#L423-9 activate_threads_#t~ret11 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 9199#L1033-27 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 9382#L1033-29 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 9386#L430-27 assume !(1 == ~t2_pc~0); 9764#L430-29 is_transmit2_triggered_~__retres1~2 := 0; 9278#L441-9 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 9279#L442-9 activate_threads_#t~ret12 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 9376#L1041-27 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 9896#L1041-29 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 9858#L449-27 assume 1 == ~t3_pc~0; 9828#L450-9 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 9434#L460-9 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 9380#L461-9 activate_threads_#t~ret13 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 9381#L1049-27 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 9635#L1049-29 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 9640#L468-27 assume 1 == ~t4_pc~0; 9908#L469-9 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 9703#L479-9 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 9521#L480-9 activate_threads_#t~ret14 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 9277#L1057-27 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 9252#L1057-29 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 9134#L487-27 assume 1 == ~t5_pc~0; 9107#L488-9 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 9108#L498-9 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 9661#L499-9 activate_threads_#t~ret15 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 9662#L1065-27 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 9864#L1065-29 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 9470#L506-27 assume 1 == ~t6_pc~0; 9269#L507-9 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6 := 1; 9270#L517-9 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 9794#L518-9 activate_threads_#t~ret16 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 9704#L1073-27 assume 0 != activate_threads_~tmp___5~0;~t6_st~0 := 0; 9546#L1073-29 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 9547#L525-27 assume 1 == ~t7_pc~0; 9457#L526-9 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7 := 1; 9458#L536-9 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 9875#L537-9 activate_threads_#t~ret17 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 9324#L1081-27 assume 0 != activate_threads_~tmp___6~0;~t7_st~0 := 0; 9325#L1081-29 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 9328#L544-27 assume 1 == ~t8_pc~0; 9698#L545-9 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8 := 1; 9209#L555-9 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 9145#L556-9 activate_threads_#t~ret18 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 9146#L1089-27 assume 0 != activate_threads_~tmp___7~0;~t8_st~0 := 0; 9884#L1089-29 assume !(1 == ~M_E~0); 9504#L921-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 9248#L926-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 9249#L931-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 9882#L936-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 9742#L941-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 9496#L946-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 9051#L951-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 9052#L956-3 assume !(1 == ~T8_E~0); 9687#L961-3 assume 1 == ~E_1~0;~E_1~0 := 2; 9572#L966-3 assume 1 == ~E_2~0;~E_2~0 := 2; 9357#L971-3 assume 1 == ~E_3~0;~E_3~0 := 2; 9358#L976-3 assume 1 == ~E_4~0;~E_4~0 := 2; 9783#L981-3 assume 1 == ~E_5~0;~E_5~0 := 2; 9542#L986-3 assume 1 == ~E_6~0;~E_6~0 := 2; 9475#L991-3 assume 1 == ~E_7~0;~E_7~0 := 2; 9194#L996-3 assume !(1 == ~E_8~0); 9195#L1001-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~9;havoc exists_runnable_thread_~__retres1~9; 9895#L624-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9 := 1; 9182#L671-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~9; 9880#L672-1 start_simulation_#t~ret20 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret20;havoc start_simulation_#t~ret20; 9091#L1281 assume !(0 == start_simulation_~tmp~3); 9092#L1281-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret19, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~9;havoc exists_runnable_thread_~__retres1~9; 9104#L624-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9 := 1; 9185#L671-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~9; 9805#L672-2 stop_simulation_#t~ret19 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret19;havoc stop_simulation_#t~ret19; 9321#L1236 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 9322#L1243 stop_simulation_#res := stop_simulation_~__retres2~0; 9842#L1244 start_simulation_#t~ret21 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret21;havoc start_simulation_#t~ret21; 9696#L1294 assume !(0 != start_simulation_~tmp___0~1); 9193#L1262-1 [2018-11-22 21:21:34,091 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-22 21:21:34,091 INFO L82 PathProgramCache]: Analyzing trace with hash -1080522710, now seen corresponding path program 1 times [2018-11-22 21:21:34,091 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-22 21:21:34,091 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-22 21:21:34,092 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-22 21:21:34,092 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-22 21:21:34,092 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-22 21:21:34,096 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-22 21:21:34,123 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-22 21:21:34,123 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-22 21:21:34,124 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-22 21:21:34,124 INFO L799 eck$LassoCheckResult]: stem already infeasible [2018-11-22 21:21:34,124 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-22 21:21:34,124 INFO L82 PathProgramCache]: Analyzing trace with hash 1856687306, now seen corresponding path program 5 times [2018-11-22 21:21:34,124 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-22 21:21:34,124 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-22 21:21:34,125 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-22 21:21:34,125 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-22 21:21:34,125 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-22 21:21:34,133 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-22 21:21:34,171 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-22 21:21:34,171 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-22 21:21:34,171 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-22 21:21:34,172 INFO L811 eck$LassoCheckResult]: loop already infeasible [2018-11-22 21:21:34,172 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-22 21:21:34,172 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-22 21:21:34,172 INFO L87 Difference]: Start difference. First operand 900 states and 1351 transitions. cyclomatic complexity: 452 Second operand 3 states. [2018-11-22 21:21:34,186 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-22 21:21:34,186 INFO L93 Difference]: Finished difference Result 900 states and 1350 transitions. [2018-11-22 21:21:34,187 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-22 21:21:34,187 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 900 states and 1350 transitions. [2018-11-22 21:21:34,192 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 791 [2018-11-22 21:21:34,195 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 900 states to 900 states and 1350 transitions. [2018-11-22 21:21:34,196 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 900 [2018-11-22 21:21:34,196 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 900 [2018-11-22 21:21:34,197 INFO L73 IsDeterministic]: Start isDeterministic. Operand 900 states and 1350 transitions. [2018-11-22 21:21:34,198 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-22 21:21:34,198 INFO L705 BuchiCegarLoop]: Abstraction has 900 states and 1350 transitions. [2018-11-22 21:21:34,199 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 900 states and 1350 transitions. [2018-11-22 21:21:34,209 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 900 to 900. [2018-11-22 21:21:34,209 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 900 states. [2018-11-22 21:21:34,211 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 900 states to 900 states and 1350 transitions. [2018-11-22 21:21:34,211 INFO L728 BuchiCegarLoop]: Abstraction has 900 states and 1350 transitions. [2018-11-22 21:21:34,211 INFO L608 BuchiCegarLoop]: Abstraction has 900 states and 1350 transitions. [2018-11-22 21:21:34,211 INFO L442 BuchiCegarLoop]: ======== Iteration 7============ [2018-11-22 21:21:34,211 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 900 states and 1350 transitions. [2018-11-22 21:21:34,215 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 791 [2018-11-22 21:21:34,215 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-22 21:21:34,215 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-22 21:21:34,216 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-22 21:21:34,216 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-22 21:21:34,216 INFO L794 eck$LassoCheckResult]: Stem: 11292#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2; 11195#L-1 havoc main_#res;havoc main_~__retres1~10;havoc main_~__retres1~10;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 11196#L1225 havoc start_simulation_#t~ret20, start_simulation_#t~ret21, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 11620#L564 assume 1 == ~m_i~0;~m_st~0 := 0; 11229#L571-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 10942#L576-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 10943#L581-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 11622#L586-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 11408#L591-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 11042#L596-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 11043#L601-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 11614#L606-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 11530#L611-1 assume 0 == ~M_E~0;~M_E~0 := 1; 11531#L828-1 assume !(0 == ~T1_E~0); 11312#L833-1 assume !(0 == ~T2_E~0); 11057#L838-1 assume !(0 == ~T3_E~0); 11058#L843-1 assume !(0 == ~T4_E~0); 11690#L848-1 assume !(0 == ~T5_E~0); 11540#L853-1 assume !(0 == ~T6_E~0); 11296#L858-1 assume !(0 == ~T7_E~0); 10860#L863-1 assume 0 == ~T8_E~0;~T8_E~0 := 1; 10861#L868-1 assume !(0 == ~E_1~0); 11495#L873-1 assume !(0 == ~E_2~0); 11381#L878-1 assume !(0 == ~E_3~0); 11166#L883-1 assume !(0 == ~E_4~0); 11167#L888-1 assume !(0 == ~E_5~0); 11593#L893-1 assume !(0 == ~E_6~0); 11350#L898-1 assume !(0 == ~E_7~0); 11284#L903-1 assume 0 == ~E_8~0;~E_8~0 := 1; 11004#L908-1 havoc activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 11005#L392 assume 1 == ~m_pc~0; 11333#L393 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0 := 1; 11337#L403 is_master_triggered_#res := is_master_triggered_~__retres1~0; 11722#L404 activate_threads_#t~ret10 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 11598#L1025 assume !(0 != activate_threads_~tmp~1); 11599#L1025-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 11482#L411 assume !(1 == ~t1_pc~0); 11451#L411-2 is_transmit1_triggered_~__retres1~1 := 0; 10927#L422 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 10928#L423 activate_threads_#t~ret11 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 11024#L1033 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 11235#L1033-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 11236#L430 assume 1 == ~t2_pc~0; 11577#L431 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 11092#L441 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 11044#L442 activate_threads_#t~ret12 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 11045#L1041 assume !(0 != activate_threads_~tmp___1~0); 11740#L1041-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 11741#L449 assume !(1 == ~t3_pc~0); 11656#L449-2 is_transmit3_triggered_~__retres1~3 := 0; 11367#L460 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 11215#L461 activate_threads_#t~ret13 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 11216#L1049 assume !(0 != activate_threads_~tmp___2~0); 11618#L1049-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 10960#L468 assume 1 == ~t4_pc~0; 10961#L469 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 10969#L479 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 11343#L480 activate_threads_#t~ret14 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 11288#L1057 assume !(0 != activate_threads_~tmp___3~0); 11289#L1057-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 11152#L487 assume !(1 == ~t5_pc~0); 10920#L487-2 is_transmit5_triggered_~__retres1~5 := 0; 10919#L498 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 11470#L499 activate_threads_#t~ret15 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 11471#L1065 assume !(0 != activate_threads_~tmp___4~0); 11753#L1065-2 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 11295#L506 assume 1 == ~t6_pc~0; 11118#L507 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6 := 1; 11119#L517 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 11616#L518 activate_threads_#t~ret16 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 11552#L1073 assume !(0 != activate_threads_~tmp___5~0); 11553#L1073-2 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 11409#L525 assume 1 == ~t7_pc~0; 11358#L526 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7 := 1; 11359#L536 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 11742#L537 activate_threads_#t~ret17 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 11172#L1081 assume !(0 != activate_threads_~tmp___6~0); 11173#L1081-2 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 11174#L544 assume !(1 == ~t8_pc~0); 11424#L544-2 is_transmit8_triggered_~__retres1~8 := 0; 10854#L555 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 10855#L556 activate_threads_#t~ret18 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 10993#L1089 assume 0 != activate_threads_~tmp___7~0;~t8_st~0 := 0; 11640#L1089-2 assume !(1 == ~M_E~0); 11306#L921-1 assume !(1 == ~T1_E~0); 11053#L926-1 assume !(1 == ~T2_E~0); 11054#L931-1 assume !(1 == ~T3_E~0); 11688#L936-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 11547#L941-1 assume !(1 == ~T5_E~0); 11302#L946-1 assume !(1 == ~T6_E~0); 10870#L951-1 assume !(1 == ~T7_E~0); 10871#L956-1 assume !(1 == ~T8_E~0); 11619#L961-1 assume !(1 == ~E_1~0); 11386#L966-1 assume !(1 == ~E_2~0); 11178#L971-1 assume !(1 == ~E_3~0); 11179#L976-1 assume 1 == ~E_4~0;~E_4~0 := 2; 11587#L981-1 assume !(1 == ~E_5~0); 11348#L986-1 assume !(1 == ~E_6~0); 11278#L991-1 assume !(1 == ~E_7~0); 10999#L996-1 assume !(1 == ~E_8~0); 11000#L1262-1 [2018-11-22 21:21:34,217 INFO L796 eck$LassoCheckResult]: Loop: 11000#L1262-1 assume !false; 11710#L1263 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret0, eval_#t~nondet1, eval_~tmp_ndt_1~0, eval_#t~nondet2, eval_~tmp_ndt_2~0, eval_#t~nondet3, eval_~tmp_ndt_3~0, eval_#t~nondet4, eval_~tmp_ndt_4~0, eval_#t~nondet5, eval_~tmp_ndt_5~0, eval_#t~nondet6, eval_~tmp_ndt_6~0, eval_#t~nondet7, eval_~tmp_ndt_7~0, eval_#t~nondet8, eval_~tmp_ndt_8~0, eval_#t~nondet9, eval_~tmp_ndt_9~0, eval_~tmp~0;havoc eval_~tmp~0; 11314#L803 assume !false; 11299#L682 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~9;havoc exists_runnable_thread_~__retres1~9; 11300#L624 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9 := 1; 10985#L671 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~9; 11686#L672 eval_#t~ret0 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret0;havoc eval_#t~ret0; 10936#L686 assume !(0 != eval_~tmp~0); 10938#L818 start_simulation_~kernel_st~0 := 2; 10945#L564-1 start_simulation_~kernel_st~0 := 3; 11623#L828-2 assume 0 == ~M_E~0;~M_E~0 := 1; 11624#L828-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 11412#L833-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 11049#L838-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 11050#L843-3 assume !(0 == ~T4_E~0); 11684#L848-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 11543#L853-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 11298#L858-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 10865#L863-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 10866#L868-3 assume 0 == ~E_1~0;~E_1~0 := 1; 11496#L873-3 assume 0 == ~E_2~0;~E_2~0 := 1; 11382#L878-3 assume 0 == ~E_3~0;~E_3~0 := 1; 11169#L883-3 assume !(0 == ~E_4~0); 11170#L888-3 assume 0 == ~E_5~0;~E_5~0 := 1; 11595#L893-3 assume 0 == ~E_6~0;~E_6~0 := 1; 11351#L898-3 assume 0 == ~E_7~0;~E_7~0 := 1; 11269#L903-3 assume 0 == ~E_8~0;~E_8~0 := 1; 10997#L908-3 havoc activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 10998#L392-27 assume 1 == ~m_pc~0; 11396#L393-9 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0 := 1; 11397#L403-9 is_master_triggered_#res := is_master_triggered_~__retres1~0; 11720#L404-9 activate_threads_#t~ret10 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 11634#L1025-27 assume !(0 != activate_threads_~tmp~1); 11629#L1025-29 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 11421#L411-27 assume 1 == ~t1_pc~0; 11422#L412-9 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 10877#L422-9 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 10878#L423-9 activate_threads_#t~ret11 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 11006#L1033-27 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 11189#L1033-29 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 11193#L430-27 assume !(1 == ~t2_pc~0); 11571#L430-29 is_transmit2_triggered_~__retres1~2 := 0; 11085#L441-9 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 11086#L442-9 activate_threads_#t~ret12 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 11183#L1041-27 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 11703#L1041-29 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 11665#L449-27 assume 1 == ~t3_pc~0; 11635#L450-9 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 11241#L460-9 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 11187#L461-9 activate_threads_#t~ret13 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 11188#L1049-27 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 11441#L1049-29 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 11447#L468-27 assume 1 == ~t4_pc~0; 11714#L469-9 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 11510#L479-9 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 11328#L480-9 activate_threads_#t~ret14 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 11084#L1057-27 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 11059#L1057-29 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 10941#L487-27 assume 1 == ~t5_pc~0; 10914#L488-9 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 10915#L498-9 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 11468#L499-9 activate_threads_#t~ret15 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 11469#L1065-27 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 11671#L1065-29 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 11277#L506-27 assume 1 == ~t6_pc~0; 11076#L507-9 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6 := 1; 11077#L517-9 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 11601#L518-9 activate_threads_#t~ret16 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 11511#L1073-27 assume 0 != activate_threads_~tmp___5~0;~t6_st~0 := 0; 11353#L1073-29 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 11354#L525-27 assume 1 == ~t7_pc~0; 11264#L526-9 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7 := 1; 11265#L536-9 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 11682#L537-9 activate_threads_#t~ret17 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 11131#L1081-27 assume 0 != activate_threads_~tmp___6~0;~t7_st~0 := 0; 11132#L1081-29 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 11135#L544-27 assume 1 == ~t8_pc~0; 11505#L545-9 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8 := 1; 11016#L555-9 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 10952#L556-9 activate_threads_#t~ret18 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 10953#L1089-27 assume 0 != activate_threads_~tmp___7~0;~t8_st~0 := 0; 11691#L1089-29 assume !(1 == ~M_E~0); 11308#L921-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 11055#L926-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 11056#L931-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 11689#L936-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 11549#L941-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 11303#L946-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 10858#L951-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 10859#L956-3 assume !(1 == ~T8_E~0); 11494#L961-3 assume 1 == ~E_1~0;~E_1~0 := 2; 11379#L966-3 assume 1 == ~E_2~0;~E_2~0 := 2; 11164#L971-3 assume 1 == ~E_3~0;~E_3~0 := 2; 11165#L976-3 assume 1 == ~E_4~0;~E_4~0 := 2; 11590#L981-3 assume 1 == ~E_5~0;~E_5~0 := 2; 11349#L986-3 assume 1 == ~E_6~0;~E_6~0 := 2; 11282#L991-3 assume 1 == ~E_7~0;~E_7~0 := 2; 11001#L996-3 assume !(1 == ~E_8~0); 11002#L1001-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~9;havoc exists_runnable_thread_~__retres1~9; 11702#L624-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9 := 1; 10989#L671-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~9; 11687#L672-1 start_simulation_#t~ret20 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret20;havoc start_simulation_#t~ret20; 10898#L1281 assume !(0 == start_simulation_~tmp~3); 10899#L1281-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret19, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~9;havoc exists_runnable_thread_~__retres1~9; 10911#L624-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9 := 1; 10992#L671-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~9; 11612#L672-2 stop_simulation_#t~ret19 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret19;havoc stop_simulation_#t~ret19; 11128#L1236 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 11129#L1243 stop_simulation_#res := stop_simulation_~__retres2~0; 11649#L1244 start_simulation_#t~ret21 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret21;havoc start_simulation_#t~ret21; 11503#L1294 assume !(0 != start_simulation_~tmp___0~1); 11000#L1262-1 [2018-11-22 21:21:34,217 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-22 21:21:34,217 INFO L82 PathProgramCache]: Analyzing trace with hash 860059304, now seen corresponding path program 1 times [2018-11-22 21:21:34,217 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-22 21:21:34,217 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-22 21:21:34,218 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-22 21:21:34,218 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-22 21:21:34,218 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-22 21:21:34,222 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-22 21:21:34,255 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-22 21:21:34,256 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-22 21:21:34,256 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-22 21:21:34,257 INFO L799 eck$LassoCheckResult]: stem already infeasible [2018-11-22 21:21:34,257 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-22 21:21:34,258 INFO L82 PathProgramCache]: Analyzing trace with hash 1856687306, now seen corresponding path program 6 times [2018-11-22 21:21:34,258 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-22 21:21:34,258 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-22 21:21:34,258 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-22 21:21:34,258 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-22 21:21:34,259 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-22 21:21:34,265 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-22 21:21:34,295 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-22 21:21:34,296 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-22 21:21:34,296 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-22 21:21:34,296 INFO L811 eck$LassoCheckResult]: loop already infeasible [2018-11-22 21:21:34,296 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-22 21:21:34,296 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-22 21:21:34,297 INFO L87 Difference]: Start difference. First operand 900 states and 1350 transitions. cyclomatic complexity: 451 Second operand 3 states. [2018-11-22 21:21:34,315 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-22 21:21:34,316 INFO L93 Difference]: Finished difference Result 900 states and 1349 transitions. [2018-11-22 21:21:34,317 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-22 21:21:34,317 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 900 states and 1349 transitions. [2018-11-22 21:21:34,321 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 791 [2018-11-22 21:21:34,324 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 900 states to 900 states and 1349 transitions. [2018-11-22 21:21:34,324 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 900 [2018-11-22 21:21:34,325 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 900 [2018-11-22 21:21:34,325 INFO L73 IsDeterministic]: Start isDeterministic. Operand 900 states and 1349 transitions. [2018-11-22 21:21:34,326 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-22 21:21:34,327 INFO L705 BuchiCegarLoop]: Abstraction has 900 states and 1349 transitions. [2018-11-22 21:21:34,328 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 900 states and 1349 transitions. [2018-11-22 21:21:34,337 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 900 to 900. [2018-11-22 21:21:34,337 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 900 states. [2018-11-22 21:21:34,339 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 900 states to 900 states and 1349 transitions. [2018-11-22 21:21:34,339 INFO L728 BuchiCegarLoop]: Abstraction has 900 states and 1349 transitions. [2018-11-22 21:21:34,339 INFO L608 BuchiCegarLoop]: Abstraction has 900 states and 1349 transitions. [2018-11-22 21:21:34,339 INFO L442 BuchiCegarLoop]: ======== Iteration 8============ [2018-11-22 21:21:34,340 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 900 states and 1349 transitions. [2018-11-22 21:21:34,343 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 791 [2018-11-22 21:21:34,343 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-22 21:21:34,343 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-22 21:21:34,344 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-22 21:21:34,345 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-22 21:21:34,345 INFO L794 eck$LassoCheckResult]: Stem: 13099#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2; 13002#L-1 havoc main_#res;havoc main_~__retres1~10;havoc main_~__retres1~10;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 13003#L1225 havoc start_simulation_#t~ret20, start_simulation_#t~ret21, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 13427#L564 assume 1 == ~m_i~0;~m_st~0 := 0; 13036#L571-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 12749#L576-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 12750#L581-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 13429#L586-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 13215#L591-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 12849#L596-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 12850#L601-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 13421#L606-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 13337#L611-1 assume 0 == ~M_E~0;~M_E~0 := 1; 13338#L828-1 assume !(0 == ~T1_E~0); 13119#L833-1 assume !(0 == ~T2_E~0); 12864#L838-1 assume !(0 == ~T3_E~0); 12865#L843-1 assume !(0 == ~T4_E~0); 13497#L848-1 assume !(0 == ~T5_E~0); 13347#L853-1 assume !(0 == ~T6_E~0); 13103#L858-1 assume !(0 == ~T7_E~0); 12667#L863-1 assume 0 == ~T8_E~0;~T8_E~0 := 1; 12668#L868-1 assume !(0 == ~E_1~0); 13302#L873-1 assume !(0 == ~E_2~0); 13188#L878-1 assume !(0 == ~E_3~0); 12973#L883-1 assume !(0 == ~E_4~0); 12974#L888-1 assume !(0 == ~E_5~0); 13398#L893-1 assume !(0 == ~E_6~0); 13157#L898-1 assume !(0 == ~E_7~0); 13090#L903-1 assume 0 == ~E_8~0;~E_8~0 := 1; 12811#L908-1 havoc activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 12812#L392 assume 1 == ~m_pc~0; 13140#L393 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0 := 1; 13144#L403 is_master_triggered_#res := is_master_triggered_~__retres1~0; 13529#L404 activate_threads_#t~ret10 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 13405#L1025 assume !(0 != activate_threads_~tmp~1); 13406#L1025-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 13289#L411 assume !(1 == ~t1_pc~0); 13257#L411-2 is_transmit1_triggered_~__retres1~1 := 0; 12731#L422 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 12732#L423 activate_threads_#t~ret11 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 12831#L1033 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 13042#L1033-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 13043#L430 assume 1 == ~t2_pc~0; 13384#L431 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 12899#L441 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 12851#L442 activate_threads_#t~ret12 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 12852#L1041 assume !(0 != activate_threads_~tmp___1~0); 13547#L1041-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 13548#L449 assume !(1 == ~t3_pc~0); 13463#L449-2 is_transmit3_triggered_~__retres1~3 := 0; 13174#L460 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 13020#L461 activate_threads_#t~ret13 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 13021#L1049 assume !(0 != activate_threads_~tmp___2~0); 13425#L1049-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 12767#L468 assume 1 == ~t4_pc~0; 12768#L469 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 12776#L479 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 13150#L480 activate_threads_#t~ret14 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 13095#L1057 assume !(0 != activate_threads_~tmp___3~0); 13096#L1057-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 12959#L487 assume !(1 == ~t5_pc~0); 12727#L487-2 is_transmit5_triggered_~__retres1~5 := 0; 12726#L498 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 13277#L499 activate_threads_#t~ret15 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 13278#L1065 assume !(0 != activate_threads_~tmp___4~0); 13560#L1065-2 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 13102#L506 assume 1 == ~t6_pc~0; 12925#L507 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6 := 1; 12926#L517 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 13423#L518 activate_threads_#t~ret16 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 13359#L1073 assume !(0 != activate_threads_~tmp___5~0); 13360#L1073-2 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 13216#L525 assume 1 == ~t7_pc~0; 13165#L526 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7 := 1; 13166#L536 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 13549#L537 activate_threads_#t~ret17 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 12979#L1081 assume !(0 != activate_threads_~tmp___6~0); 12980#L1081-2 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 12981#L544 assume !(1 == ~t8_pc~0); 13228#L544-2 is_transmit8_triggered_~__retres1~8 := 0; 12661#L555 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 12662#L556 activate_threads_#t~ret18 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 12800#L1089 assume 0 != activate_threads_~tmp___7~0;~t8_st~0 := 0; 13447#L1089-2 assume !(1 == ~M_E~0); 13113#L921-1 assume !(1 == ~T1_E~0); 12860#L926-1 assume !(1 == ~T2_E~0); 12861#L931-1 assume !(1 == ~T3_E~0); 13495#L936-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 13354#L941-1 assume !(1 == ~T5_E~0); 13109#L946-1 assume !(1 == ~T6_E~0); 12677#L951-1 assume !(1 == ~T7_E~0); 12678#L956-1 assume !(1 == ~T8_E~0); 13426#L961-1 assume !(1 == ~E_1~0); 13193#L966-1 assume !(1 == ~E_2~0); 12985#L971-1 assume !(1 == ~E_3~0); 12986#L976-1 assume 1 == ~E_4~0;~E_4~0 := 2; 13394#L981-1 assume !(1 == ~E_5~0); 13155#L986-1 assume !(1 == ~E_6~0); 13085#L991-1 assume !(1 == ~E_7~0); 12806#L996-1 assume !(1 == ~E_8~0); 12807#L1262-1 [2018-11-22 21:21:34,345 INFO L796 eck$LassoCheckResult]: Loop: 12807#L1262-1 assume !false; 13517#L1263 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret0, eval_#t~nondet1, eval_~tmp_ndt_1~0, eval_#t~nondet2, eval_~tmp_ndt_2~0, eval_#t~nondet3, eval_~tmp_ndt_3~0, eval_#t~nondet4, eval_~tmp_ndt_4~0, eval_#t~nondet5, eval_~tmp_ndt_5~0, eval_#t~nondet6, eval_~tmp_ndt_6~0, eval_#t~nondet7, eval_~tmp_ndt_7~0, eval_#t~nondet8, eval_~tmp_ndt_8~0, eval_#t~nondet9, eval_~tmp_ndt_9~0, eval_~tmp~0;havoc eval_~tmp~0; 13121#L803 assume !false; 13106#L682 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~9;havoc exists_runnable_thread_~__retres1~9; 13107#L624 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9 := 1; 12792#L671 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~9; 13493#L672 eval_#t~ret0 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret0;havoc eval_#t~ret0; 12743#L686 assume !(0 != eval_~tmp~0); 12745#L818 start_simulation_~kernel_st~0 := 2; 12752#L564-1 start_simulation_~kernel_st~0 := 3; 13430#L828-2 assume 0 == ~M_E~0;~M_E~0 := 1; 13431#L828-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 13219#L833-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 12856#L838-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 12857#L843-3 assume !(0 == ~T4_E~0); 13491#L848-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 13350#L853-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 13105#L858-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 12672#L863-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 12673#L868-3 assume 0 == ~E_1~0;~E_1~0 := 1; 13303#L873-3 assume 0 == ~E_2~0;~E_2~0 := 1; 13189#L878-3 assume 0 == ~E_3~0;~E_3~0 := 1; 12976#L883-3 assume !(0 == ~E_4~0); 12977#L888-3 assume 0 == ~E_5~0;~E_5~0 := 1; 13402#L893-3 assume 0 == ~E_6~0;~E_6~0 := 1; 13158#L898-3 assume 0 == ~E_7~0;~E_7~0 := 1; 13076#L903-3 assume 0 == ~E_8~0;~E_8~0 := 1; 12804#L908-3 havoc activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 12805#L392-27 assume 1 == ~m_pc~0; 13204#L393-9 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0 := 1; 13205#L403-9 is_master_triggered_#res := is_master_triggered_~__retres1~0; 13527#L404-9 activate_threads_#t~ret10 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 13441#L1025-27 assume !(0 != activate_threads_~tmp~1); 13436#L1025-29 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 13230#L411-27 assume !(1 == ~t1_pc~0); 13232#L411-29 is_transmit1_triggered_~__retres1~1 := 0; 12684#L422-9 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 12685#L423-9 activate_threads_#t~ret11 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 12815#L1033-27 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 12998#L1033-29 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 13000#L430-27 assume !(1 == ~t2_pc~0); 13378#L430-29 is_transmit2_triggered_~__retres1~2 := 0; 12892#L441-9 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 12893#L442-9 activate_threads_#t~ret12 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 12990#L1041-27 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 13511#L1041-29 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 13472#L449-27 assume 1 == ~t3_pc~0; 13442#L450-9 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 13048#L460-9 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 12994#L461-9 activate_threads_#t~ret13 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 12995#L1049-27 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 13248#L1049-29 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 13254#L468-27 assume 1 == ~t4_pc~0; 13521#L469-9 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 13317#L479-9 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 13135#L480-9 activate_threads_#t~ret14 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 12891#L1057-27 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 12866#L1057-29 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 12748#L487-27 assume !(1 == ~t5_pc~0); 12721#L487-29 is_transmit5_triggered_~__retres1~5 := 0; 12720#L498-9 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 13274#L499-9 activate_threads_#t~ret15 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 13275#L1065-27 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 13478#L1065-29 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 13084#L506-27 assume 1 == ~t6_pc~0; 12881#L507-9 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6 := 1; 12882#L517-9 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 13408#L518-9 activate_threads_#t~ret16 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 13318#L1073-27 assume 0 != activate_threads_~tmp___5~0;~t6_st~0 := 0; 13160#L1073-29 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 13161#L525-27 assume !(1 == ~t7_pc~0); 13072#L525-29 is_transmit7_triggered_~__retres1~7 := 0; 13071#L536-9 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 13489#L537-9 activate_threads_#t~ret17 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 12938#L1081-27 assume 0 != activate_threads_~tmp___6~0;~t7_st~0 := 0; 12939#L1081-29 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 12942#L544-27 assume !(1 == ~t8_pc~0); 13312#L544-29 is_transmit8_triggered_~__retres1~8 := 0; 12822#L555-9 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 12759#L556-9 activate_threads_#t~ret18 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 12760#L1089-27 assume 0 != activate_threads_~tmp___7~0;~t8_st~0 := 0; 13498#L1089-29 assume !(1 == ~M_E~0); 13115#L921-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 12862#L926-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 12863#L931-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 13496#L936-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 13356#L941-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 13110#L946-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 12665#L951-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 12666#L956-3 assume !(1 == ~T8_E~0); 13300#L961-3 assume 1 == ~E_1~0;~E_1~0 := 2; 13186#L966-3 assume 1 == ~E_2~0;~E_2~0 := 2; 12971#L971-3 assume 1 == ~E_3~0;~E_3~0 := 2; 12972#L976-3 assume 1 == ~E_4~0;~E_4~0 := 2; 13397#L981-3 assume 1 == ~E_5~0;~E_5~0 := 2; 13156#L986-3 assume 1 == ~E_6~0;~E_6~0 := 2; 13089#L991-3 assume 1 == ~E_7~0;~E_7~0 := 2; 12808#L996-3 assume !(1 == ~E_8~0); 12809#L1001-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~9;havoc exists_runnable_thread_~__retres1~9; 13509#L624-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9 := 1; 12796#L671-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~9; 13494#L672-1 start_simulation_#t~ret20 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret20;havoc start_simulation_#t~ret20; 12705#L1281 assume !(0 == start_simulation_~tmp~3); 12706#L1281-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret19, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~9;havoc exists_runnable_thread_~__retres1~9; 12718#L624-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9 := 1; 12799#L671-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~9; 13419#L672-2 stop_simulation_#t~ret19 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret19;havoc stop_simulation_#t~ret19; 12935#L1236 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 12936#L1243 stop_simulation_#res := stop_simulation_~__retres2~0; 13456#L1244 start_simulation_#t~ret21 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret21;havoc start_simulation_#t~ret21; 13310#L1294 assume !(0 != start_simulation_~tmp___0~1); 12807#L1262-1 [2018-11-22 21:21:34,345 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-22 21:21:34,345 INFO L82 PathProgramCache]: Analyzing trace with hash -1017003926, now seen corresponding path program 1 times [2018-11-22 21:21:34,346 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-22 21:21:34,346 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-22 21:21:34,346 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-22 21:21:34,346 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-22 21:21:34,346 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-22 21:21:34,350 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-22 21:21:34,384 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-22 21:21:34,385 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-22 21:21:34,385 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-22 21:21:34,385 INFO L799 eck$LassoCheckResult]: stem already infeasible [2018-11-22 21:21:34,385 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-22 21:21:34,385 INFO L82 PathProgramCache]: Analyzing trace with hash 306869390, now seen corresponding path program 1 times [2018-11-22 21:21:34,385 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-22 21:21:34,385 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-22 21:21:34,386 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-22 21:21:34,386 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-22 21:21:34,386 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-22 21:21:34,392 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-22 21:21:34,430 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-22 21:21:34,430 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-22 21:21:34,430 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-22 21:21:34,431 INFO L811 eck$LassoCheckResult]: loop already infeasible [2018-11-22 21:21:34,431 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-22 21:21:34,431 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-22 21:21:34,431 INFO L87 Difference]: Start difference. First operand 900 states and 1349 transitions. cyclomatic complexity: 450 Second operand 3 states. [2018-11-22 21:21:34,446 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-22 21:21:34,447 INFO L93 Difference]: Finished difference Result 900 states and 1348 transitions. [2018-11-22 21:21:34,447 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-22 21:21:34,448 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 900 states and 1348 transitions. [2018-11-22 21:21:34,451 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 791 [2018-11-22 21:21:34,455 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 900 states to 900 states and 1348 transitions. [2018-11-22 21:21:34,455 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 900 [2018-11-22 21:21:34,456 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 900 [2018-11-22 21:21:34,456 INFO L73 IsDeterministic]: Start isDeterministic. Operand 900 states and 1348 transitions. [2018-11-22 21:21:34,457 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-22 21:21:34,457 INFO L705 BuchiCegarLoop]: Abstraction has 900 states and 1348 transitions. [2018-11-22 21:21:34,458 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 900 states and 1348 transitions. [2018-11-22 21:21:34,467 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 900 to 900. [2018-11-22 21:21:34,467 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 900 states. [2018-11-22 21:21:34,469 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 900 states to 900 states and 1348 transitions. [2018-11-22 21:21:34,469 INFO L728 BuchiCegarLoop]: Abstraction has 900 states and 1348 transitions. [2018-11-22 21:21:34,469 INFO L608 BuchiCegarLoop]: Abstraction has 900 states and 1348 transitions. [2018-11-22 21:21:34,469 INFO L442 BuchiCegarLoop]: ======== Iteration 9============ [2018-11-22 21:21:34,469 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 900 states and 1348 transitions. [2018-11-22 21:21:34,472 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 791 [2018-11-22 21:21:34,473 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-22 21:21:34,473 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-22 21:21:34,474 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-22 21:21:34,474 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-22 21:21:34,474 INFO L794 eck$LassoCheckResult]: Stem: 14906#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2; 14809#L-1 havoc main_#res;havoc main_~__retres1~10;havoc main_~__retres1~10;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 14810#L1225 havoc start_simulation_#t~ret20, start_simulation_#t~ret21, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 15234#L564 assume 1 == ~m_i~0;~m_st~0 := 0; 14843#L571-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 14556#L576-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 14557#L581-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 15236#L586-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 15022#L591-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 14656#L596-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 14657#L601-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 15228#L606-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 15144#L611-1 assume 0 == ~M_E~0;~M_E~0 := 1; 15145#L828-1 assume !(0 == ~T1_E~0); 14926#L833-1 assume !(0 == ~T2_E~0); 14671#L838-1 assume !(0 == ~T3_E~0); 14672#L843-1 assume !(0 == ~T4_E~0); 15304#L848-1 assume !(0 == ~T5_E~0); 15153#L853-1 assume !(0 == ~T6_E~0); 14910#L858-1 assume !(0 == ~T7_E~0); 14474#L863-1 assume 0 == ~T8_E~0;~T8_E~0 := 1; 14475#L868-1 assume !(0 == ~E_1~0); 15109#L873-1 assume !(0 == ~E_2~0); 14995#L878-1 assume !(0 == ~E_3~0); 14780#L883-1 assume !(0 == ~E_4~0); 14781#L888-1 assume !(0 == ~E_5~0); 15205#L893-1 assume !(0 == ~E_6~0); 14964#L898-1 assume !(0 == ~E_7~0); 14897#L903-1 assume 0 == ~E_8~0;~E_8~0 := 1; 14618#L908-1 havoc activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 14619#L392 assume 1 == ~m_pc~0; 14947#L393 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0 := 1; 14951#L403 is_master_triggered_#res := is_master_triggered_~__retres1~0; 15336#L404 activate_threads_#t~ret10 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 15212#L1025 assume !(0 != activate_threads_~tmp~1); 15213#L1025-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 15096#L411 assume !(1 == ~t1_pc~0); 15064#L411-2 is_transmit1_triggered_~__retres1~1 := 0; 14538#L422 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 14539#L423 activate_threads_#t~ret11 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 14637#L1033 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 14849#L1033-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 14850#L430 assume 1 == ~t2_pc~0; 15191#L431 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 14703#L441 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 14658#L442 activate_threads_#t~ret12 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 14659#L1041 assume !(0 != activate_threads_~tmp___1~0); 15354#L1041-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 15355#L449 assume !(1 == ~t3_pc~0); 15270#L449-2 is_transmit3_triggered_~__retres1~3 := 0; 14978#L460 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 14827#L461 activate_threads_#t~ret13 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 14828#L1049 assume !(0 != activate_threads_~tmp___2~0); 15232#L1049-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 14574#L468 assume 1 == ~t4_pc~0; 14575#L469 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 14583#L479 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 14957#L480 activate_threads_#t~ret14 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 14902#L1057 assume !(0 != activate_threads_~tmp___3~0); 14903#L1057-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 14766#L487 assume !(1 == ~t5_pc~0); 14534#L487-2 is_transmit5_triggered_~__retres1~5 := 0; 14533#L498 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 15084#L499 activate_threads_#t~ret15 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 15085#L1065 assume !(0 != activate_threads_~tmp___4~0); 15367#L1065-2 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 14909#L506 assume 1 == ~t6_pc~0; 14732#L507 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6 := 1; 14733#L517 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 15230#L518 activate_threads_#t~ret16 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 15166#L1073 assume !(0 != activate_threads_~tmp___5~0); 15167#L1073-2 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 15023#L525 assume 1 == ~t7_pc~0; 14972#L526 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7 := 1; 14973#L536 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 15356#L537 activate_threads_#t~ret17 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 14786#L1081 assume !(0 != activate_threads_~tmp___6~0); 14787#L1081-2 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 14788#L544 assume !(1 == ~t8_pc~0); 15035#L544-2 is_transmit8_triggered_~__retres1~8 := 0; 14468#L555 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 14469#L556 activate_threads_#t~ret18 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 14607#L1089 assume 0 != activate_threads_~tmp___7~0;~t8_st~0 := 0; 15254#L1089-2 assume !(1 == ~M_E~0); 14920#L921-1 assume !(1 == ~T1_E~0); 14667#L926-1 assume !(1 == ~T2_E~0); 14668#L931-1 assume !(1 == ~T3_E~0); 15302#L936-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 15161#L941-1 assume !(1 == ~T5_E~0); 14916#L946-1 assume !(1 == ~T6_E~0); 14484#L951-1 assume !(1 == ~T7_E~0); 14485#L956-1 assume !(1 == ~T8_E~0); 15233#L961-1 assume !(1 == ~E_1~0); 15000#L966-1 assume !(1 == ~E_2~0); 14792#L971-1 assume !(1 == ~E_3~0); 14793#L976-1 assume 1 == ~E_4~0;~E_4~0 := 2; 15201#L981-1 assume !(1 == ~E_5~0); 14962#L986-1 assume !(1 == ~E_6~0); 14892#L991-1 assume !(1 == ~E_7~0); 14613#L996-1 assume !(1 == ~E_8~0); 14614#L1262-1 [2018-11-22 21:21:34,474 INFO L796 eck$LassoCheckResult]: Loop: 14614#L1262-1 assume !false; 15324#L1263 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret0, eval_#t~nondet1, eval_~tmp_ndt_1~0, eval_#t~nondet2, eval_~tmp_ndt_2~0, eval_#t~nondet3, eval_~tmp_ndt_3~0, eval_#t~nondet4, eval_~tmp_ndt_4~0, eval_#t~nondet5, eval_~tmp_ndt_5~0, eval_#t~nondet6, eval_~tmp_ndt_6~0, eval_#t~nondet7, eval_~tmp_ndt_7~0, eval_#t~nondet8, eval_~tmp_ndt_8~0, eval_#t~nondet9, eval_~tmp_ndt_9~0, eval_~tmp~0;havoc eval_~tmp~0; 14928#L803 assume !false; 14913#L682 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~9;havoc exists_runnable_thread_~__retres1~9; 14914#L624 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9 := 1; 14599#L671 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~9; 15300#L672 eval_#t~ret0 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret0;havoc eval_#t~ret0; 14550#L686 assume !(0 != eval_~tmp~0); 14552#L818 start_simulation_~kernel_st~0 := 2; 14558#L564-1 start_simulation_~kernel_st~0 := 3; 15237#L828-2 assume 0 == ~M_E~0;~M_E~0 := 1; 15238#L828-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 15026#L833-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 14663#L838-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 14664#L843-3 assume !(0 == ~T4_E~0); 15298#L848-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 15157#L853-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 14912#L858-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 14479#L863-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 14480#L868-3 assume 0 == ~E_1~0;~E_1~0 := 1; 15110#L873-3 assume 0 == ~E_2~0;~E_2~0 := 1; 14996#L878-3 assume 0 == ~E_3~0;~E_3~0 := 1; 14783#L883-3 assume !(0 == ~E_4~0); 14784#L888-3 assume 0 == ~E_5~0;~E_5~0 := 1; 15209#L893-3 assume 0 == ~E_6~0;~E_6~0 := 1; 14965#L898-3 assume 0 == ~E_7~0;~E_7~0 := 1; 14883#L903-3 assume 0 == ~E_8~0;~E_8~0 := 1; 14611#L908-3 havoc activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 14612#L392-27 assume 1 == ~m_pc~0; 15011#L393-9 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0 := 1; 15012#L403-9 is_master_triggered_#res := is_master_triggered_~__retres1~0; 15334#L404-9 activate_threads_#t~ret10 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 15248#L1025-27 assume !(0 != activate_threads_~tmp~1); 15243#L1025-29 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 15037#L411-27 assume 1 == ~t1_pc~0; 15038#L412-9 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 14491#L422-9 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 14492#L423-9 activate_threads_#t~ret11 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 14622#L1033-27 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 14805#L1033-29 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 14807#L430-27 assume !(1 == ~t2_pc~0); 15185#L430-29 is_transmit2_triggered_~__retres1~2 := 0; 14699#L441-9 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 14700#L442-9 activate_threads_#t~ret12 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 14797#L1041-27 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 15318#L1041-29 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 15279#L449-27 assume 1 == ~t3_pc~0; 15249#L450-9 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 14855#L460-9 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 14801#L461-9 activate_threads_#t~ret13 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 14802#L1049-27 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 15056#L1049-29 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 15061#L468-27 assume 1 == ~t4_pc~0; 15329#L469-9 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 15124#L479-9 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 14942#L480-9 activate_threads_#t~ret14 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 14698#L1057-27 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 14673#L1057-29 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 14555#L487-27 assume 1 == ~t5_pc~0; 14528#L488-9 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 14529#L498-9 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 15082#L499-9 activate_threads_#t~ret15 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 15083#L1065-27 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 15285#L1065-29 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 14891#L506-27 assume 1 == ~t6_pc~0; 14690#L507-9 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6 := 1; 14691#L517-9 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 15215#L518-9 activate_threads_#t~ret16 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 15125#L1073-27 assume 0 != activate_threads_~tmp___5~0;~t6_st~0 := 0; 14967#L1073-29 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 14968#L525-27 assume !(1 == ~t7_pc~0); 14880#L525-29 is_transmit7_triggered_~__retres1~7 := 0; 14879#L536-9 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 15296#L537-9 activate_threads_#t~ret17 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 14745#L1081-27 assume 0 != activate_threads_~tmp___6~0;~t7_st~0 := 0; 14746#L1081-29 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 14749#L544-27 assume 1 == ~t8_pc~0; 15118#L545-9 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8 := 1; 14629#L555-9 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 14566#L556-9 activate_threads_#t~ret18 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 14567#L1089-27 assume 0 != activate_threads_~tmp___7~0;~t8_st~0 := 0; 15305#L1089-29 assume !(1 == ~M_E~0); 14922#L921-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 14669#L926-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 14670#L931-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 15303#L936-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 15163#L941-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 14917#L946-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 14472#L951-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 14473#L956-3 assume !(1 == ~T8_E~0); 15107#L961-3 assume 1 == ~E_1~0;~E_1~0 := 2; 14993#L966-3 assume 1 == ~E_2~0;~E_2~0 := 2; 14778#L971-3 assume 1 == ~E_3~0;~E_3~0 := 2; 14779#L976-3 assume 1 == ~E_4~0;~E_4~0 := 2; 15204#L981-3 assume 1 == ~E_5~0;~E_5~0 := 2; 14963#L986-3 assume 1 == ~E_6~0;~E_6~0 := 2; 14896#L991-3 assume 1 == ~E_7~0;~E_7~0 := 2; 14615#L996-3 assume !(1 == ~E_8~0); 14616#L1001-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~9;havoc exists_runnable_thread_~__retres1~9; 15316#L624-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9 := 1; 14603#L671-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~9; 15301#L672-1 start_simulation_#t~ret20 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret20;havoc start_simulation_#t~ret20; 14512#L1281 assume !(0 == start_simulation_~tmp~3); 14513#L1281-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret19, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~9;havoc exists_runnable_thread_~__retres1~9; 14525#L624-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9 := 1; 14606#L671-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~9; 15226#L672-2 stop_simulation_#t~ret19 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret19;havoc stop_simulation_#t~ret19; 14742#L1236 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 14743#L1243 stop_simulation_#res := stop_simulation_~__retres2~0; 15263#L1244 start_simulation_#t~ret21 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret21;havoc start_simulation_#t~ret21; 15117#L1294 assume !(0 != start_simulation_~tmp___0~1); 14614#L1262-1 [2018-11-22 21:21:34,475 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-22 21:21:34,475 INFO L82 PathProgramCache]: Analyzing trace with hash -246270360, now seen corresponding path program 1 times [2018-11-22 21:21:34,475 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-22 21:21:34,475 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-22 21:21:34,475 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-22 21:21:34,476 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-22 21:21:34,476 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-22 21:21:34,480 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-22 21:21:34,513 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-22 21:21:34,514 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-22 21:21:34,514 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2018-11-22 21:21:34,514 INFO L799 eck$LassoCheckResult]: stem already infeasible [2018-11-22 21:21:34,514 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-22 21:21:34,514 INFO L82 PathProgramCache]: Analyzing trace with hash 1371512587, now seen corresponding path program 1 times [2018-11-22 21:21:34,514 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-22 21:21:34,514 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-22 21:21:34,515 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-22 21:21:34,515 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-22 21:21:34,515 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-22 21:21:34,521 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-22 21:21:34,549 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-22 21:21:34,549 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-22 21:21:34,549 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-22 21:21:34,550 INFO L811 eck$LassoCheckResult]: loop already infeasible [2018-11-22 21:21:34,550 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-22 21:21:34,550 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-22 21:21:34,550 INFO L87 Difference]: Start difference. First operand 900 states and 1348 transitions. cyclomatic complexity: 449 Second operand 3 states. [2018-11-22 21:21:34,657 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-22 21:21:34,658 INFO L93 Difference]: Finished difference Result 1627 states and 2419 transitions. [2018-11-22 21:21:34,658 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-22 21:21:34,658 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1627 states and 2419 transitions. [2018-11-22 21:21:34,665 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1518 [2018-11-22 21:21:34,671 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1627 states to 1627 states and 2419 transitions. [2018-11-22 21:21:34,671 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1627 [2018-11-22 21:21:34,672 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1627 [2018-11-22 21:21:34,673 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1627 states and 2419 transitions. [2018-11-22 21:21:34,675 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-22 21:21:34,675 INFO L705 BuchiCegarLoop]: Abstraction has 1627 states and 2419 transitions. [2018-11-22 21:21:34,677 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1627 states and 2419 transitions. [2018-11-22 21:21:34,694 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1627 to 1627. [2018-11-22 21:21:34,694 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1627 states. [2018-11-22 21:21:34,698 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1627 states to 1627 states and 2419 transitions. [2018-11-22 21:21:34,698 INFO L728 BuchiCegarLoop]: Abstraction has 1627 states and 2419 transitions. [2018-11-22 21:21:34,698 INFO L608 BuchiCegarLoop]: Abstraction has 1627 states and 2419 transitions. [2018-11-22 21:21:34,698 INFO L442 BuchiCegarLoop]: ======== Iteration 10============ [2018-11-22 21:21:34,698 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1627 states and 2419 transitions. [2018-11-22 21:21:34,703 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1518 [2018-11-22 21:21:34,703 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-22 21:21:34,703 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-22 21:21:34,705 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-22 21:21:34,705 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-22 21:21:34,705 INFO L794 eck$LassoCheckResult]: Stem: 17445#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2; 17347#L-1 havoc main_#res;havoc main_~__retres1~10;havoc main_~__retres1~10;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 17348#L1225 havoc start_simulation_#t~ret20, start_simulation_#t~ret21, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 17782#L564 assume 1 == ~m_i~0;~m_st~0 := 0; 17381#L571-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 17091#L576-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 17092#L581-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 17785#L586-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 17560#L591-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 17191#L596-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 17192#L601-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 17776#L606-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 17688#L611-1 assume !(0 == ~M_E~0); 17689#L828-1 assume !(0 == ~T1_E~0); 17465#L833-1 assume !(0 == ~T2_E~0); 17206#L838-1 assume !(0 == ~T3_E~0); 17207#L843-1 assume !(0 == ~T4_E~0); 17862#L848-1 assume !(0 == ~T5_E~0); 17698#L853-1 assume !(0 == ~T6_E~0); 17449#L858-1 assume !(0 == ~T7_E~0); 17008#L863-1 assume 0 == ~T8_E~0;~T8_E~0 := 1; 17009#L868-1 assume !(0 == ~E_1~0); 17651#L873-1 assume !(0 == ~E_2~0); 17534#L878-1 assume !(0 == ~E_3~0); 17317#L883-1 assume !(0 == ~E_4~0); 17318#L888-1 assume !(0 == ~E_5~0); 17755#L893-1 assume !(0 == ~E_6~0); 17503#L898-1 assume !(0 == ~E_7~0); 17437#L903-1 assume 0 == ~E_8~0;~E_8~0 := 1; 17153#L908-1 havoc activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 17154#L392 assume !(1 == ~m_pc~0); 17487#L392-2 is_master_triggered_~__retres1~0 := 0; 17490#L403 is_master_triggered_#res := is_master_triggered_~__retres1~0; 17900#L404 activate_threads_#t~ret10 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 17760#L1025 assume !(0 != activate_threads_~tmp~1); 17761#L1025-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 17638#L411 assume !(1 == ~t1_pc~0); 17607#L411-2 is_transmit1_triggered_~__retres1~1 := 0; 17075#L422 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 17076#L423 activate_threads_#t~ret11 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 17173#L1033 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 17387#L1033-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 17388#L430 assume 1 == ~t2_pc~0; 17738#L431 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 17241#L441 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 17193#L442 activate_threads_#t~ret12 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 17194#L1041 assume !(0 != activate_threads_~tmp___1~0); 17918#L1041-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 17919#L449 assume !(1 == ~t3_pc~0); 17824#L449-2 is_transmit3_triggered_~__retres1~3 := 0; 17520#L460 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 17367#L461 activate_threads_#t~ret13 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 17368#L1049 assume !(0 != activate_threads_~tmp___2~0); 17780#L1049-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 17109#L468 assume 1 == ~t4_pc~0; 17110#L469 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 17118#L479 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 17496#L480 activate_threads_#t~ret14 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 17441#L1057 assume !(0 != activate_threads_~tmp___3~0); 17442#L1057-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 17303#L487 assume !(1 == ~t5_pc~0); 17068#L487-2 is_transmit5_triggered_~__retres1~5 := 0; 17067#L498 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 17626#L499 activate_threads_#t~ret15 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 17627#L1065 assume !(0 != activate_threads_~tmp___4~0); 17932#L1065-2 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 17448#L506 assume 1 == ~t6_pc~0; 17267#L507 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6 := 1; 17268#L517 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 17778#L518 activate_threads_#t~ret16 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 17713#L1073 assume !(0 != activate_threads_~tmp___5~0); 17714#L1073-2 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 17561#L525 assume 1 == ~t7_pc~0; 17511#L526 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7 := 1; 17512#L536 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 17920#L537 activate_threads_#t~ret17 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 17323#L1081 assume !(0 != activate_threads_~tmp___6~0); 17324#L1081-2 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 17325#L544 assume !(1 == ~t8_pc~0); 17580#L544-2 is_transmit8_triggered_~__retres1~8 := 0; 17002#L555 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 17003#L556 activate_threads_#t~ret18 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 17142#L1089 assume 0 != activate_threads_~tmp___7~0;~t8_st~0 := 0; 17807#L1089-2 assume !(1 == ~M_E~0); 17459#L921-1 assume !(1 == ~T1_E~0); 17202#L926-1 assume !(1 == ~T2_E~0); 17203#L931-1 assume !(1 == ~T3_E~0); 17860#L936-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 17705#L941-1 assume !(1 == ~T5_E~0); 17455#L946-1 assume !(1 == ~T6_E~0); 17018#L951-1 assume !(1 == ~T7_E~0); 17019#L956-1 assume !(1 == ~T8_E~0); 17781#L961-1 assume !(1 == ~E_1~0); 17539#L966-1 assume !(1 == ~E_2~0); 17330#L971-1 assume !(1 == ~E_3~0); 17331#L976-1 assume 1 == ~E_4~0;~E_4~0 := 2; 17749#L981-1 assume !(1 == ~E_5~0); 17501#L986-1 assume !(1 == ~E_6~0); 17431#L991-1 assume !(1 == ~E_7~0); 17148#L996-1 assume !(1 == ~E_8~0); 17149#L1262-1 [2018-11-22 21:21:34,705 INFO L796 eck$LassoCheckResult]: Loop: 17149#L1262-1 assume !false; 17887#L1263 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret0, eval_#t~nondet1, eval_~tmp_ndt_1~0, eval_#t~nondet2, eval_~tmp_ndt_2~0, eval_#t~nondet3, eval_~tmp_ndt_3~0, eval_#t~nondet4, eval_~tmp_ndt_4~0, eval_#t~nondet5, eval_~tmp_ndt_5~0, eval_#t~nondet6, eval_~tmp_ndt_6~0, eval_#t~nondet7, eval_~tmp_ndt_7~0, eval_#t~nondet8, eval_~tmp_ndt_8~0, eval_#t~nondet9, eval_~tmp_ndt_9~0, eval_~tmp~0;havoc eval_~tmp~0; 17467#L803 assume !false; 17452#L682 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~9;havoc exists_runnable_thread_~__retres1~9; 17453#L624 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9 := 1; 17134#L671 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~9; 17876#L672 eval_#t~ret0 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret0;havoc eval_#t~ret0; 17937#L686 assume !(0 != eval_~tmp~0); 17936#L818 start_simulation_~kernel_st~0 := 2; 17935#L564-1 start_simulation_~kernel_st~0 := 3; 17792#L828-2 assume !(0 == ~M_E~0); 17787#L828-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 17566#L833-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 17198#L838-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 17199#L843-3 assume !(0 == ~T4_E~0); 17856#L848-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 17701#L853-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 17451#L858-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 17013#L863-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 17014#L868-3 assume 0 == ~E_1~0;~E_1~0 := 1; 17652#L873-3 assume 0 == ~E_2~0;~E_2~0 := 1; 17535#L878-3 assume 0 == ~E_3~0;~E_3~0 := 1; 17320#L883-3 assume !(0 == ~E_4~0); 17321#L888-3 assume 0 == ~E_5~0;~E_5~0 := 1; 17757#L893-3 assume 0 == ~E_6~0;~E_6~0 := 1; 17504#L898-3 assume 0 == ~E_7~0;~E_7~0 := 1; 17422#L903-3 assume 0 == ~E_8~0;~E_8~0 := 1; 17146#L908-3 havoc activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 17147#L392-27 assume !(1 == ~m_pc~0); 17547#L392-29 is_master_triggered_~__retres1~0 := 0; 17562#L403-9 is_master_triggered_#res := is_master_triggered_~__retres1~0; 17897#L404-9 activate_threads_#t~ret10 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 17800#L1025-27 assume !(0 != activate_threads_~tmp~1); 17793#L1025-29 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 17577#L411-27 assume 1 == ~t1_pc~0; 17578#L412-9 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 17025#L422-9 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 17026#L423-9 activate_threads_#t~ret11 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 17155#L1033-27 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 17341#L1033-29 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 17345#L430-27 assume !(1 == ~t2_pc~0); 17732#L430-29 is_transmit2_triggered_~__retres1~2 := 0; 17234#L441-9 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 17235#L442-9 activate_threads_#t~ret12 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 17335#L1041-27 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 17880#L1041-29 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 17833#L449-27 assume 1 == ~t3_pc~0; 17801#L450-9 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 17393#L460-9 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 17339#L461-9 activate_threads_#t~ret13 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 17340#L1049-27 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 17598#L1049-29 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 17603#L468-27 assume 1 == ~t4_pc~0; 17892#L469-9 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 17668#L479-9 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 17481#L480-9 activate_threads_#t~ret14 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 17233#L1057-27 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 17208#L1057-29 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 17090#L487-27 assume 1 == ~t5_pc~0; 17062#L488-9 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 17063#L498-9 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 17624#L499-9 activate_threads_#t~ret15 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 17625#L1065-27 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 17841#L1065-29 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 17430#L506-27 assume 1 == ~t6_pc~0; 17225#L507-9 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6 := 1; 17226#L517-9 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 17763#L518-9 activate_threads_#t~ret16 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 17669#L1073-27 assume 0 != activate_threads_~tmp___5~0;~t6_st~0 := 0; 17506#L1073-29 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 17507#L525-27 assume 1 == ~t7_pc~0; 17417#L526-9 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7 := 1; 17418#L536-9 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 17854#L537-9 activate_threads_#t~ret17 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 17281#L1081-27 assume 0 != activate_threads_~tmp___6~0;~t7_st~0 := 0; 17282#L1081-29 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 17285#L544-27 assume 1 == ~t8_pc~0; 17662#L545-9 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8 := 1; 17165#L555-9 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 17101#L556-9 activate_threads_#t~ret18 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 17102#L1089-27 assume 0 != activate_threads_~tmp___7~0;~t8_st~0 := 0; 17863#L1089-29 assume !(1 == ~M_E~0); 17864#L921-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 18602#L926-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 18601#L931-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 18600#L936-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 18599#L941-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 18598#L946-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 18597#L951-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 18596#L956-3 assume !(1 == ~T8_E~0); 18595#L961-3 assume 1 == ~E_1~0;~E_1~0 := 2; 18594#L966-3 assume 1 == ~E_2~0;~E_2~0 := 2; 18593#L971-3 assume 1 == ~E_3~0;~E_3~0 := 2; 18592#L976-3 assume 1 == ~E_4~0;~E_4~0 := 2; 18591#L981-3 assume 1 == ~E_5~0;~E_5~0 := 2; 18590#L986-3 assume 1 == ~E_6~0;~E_6~0 := 2; 18589#L991-3 assume 1 == ~E_7~0;~E_7~0 := 2; 18588#L996-3 assume !(1 == ~E_8~0); 17878#L1001-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~9;havoc exists_runnable_thread_~__retres1~9; 17879#L624-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9 := 1; 17138#L671-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~9; 17872#L672-1 start_simulation_#t~ret20 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret20;havoc start_simulation_#t~ret20; 18267#L1281 assume !(0 == start_simulation_~tmp~3); 18266#L1281-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret19, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~9;havoc exists_runnable_thread_~__retres1~9; 18011#L624-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9 := 1; 18002#L671-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~9; 18000#L672-2 stop_simulation_#t~ret19 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret19;havoc stop_simulation_#t~ret19; 17985#L1236 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 17816#L1243 stop_simulation_#res := stop_simulation_~__retres2~0; 17817#L1244 start_simulation_#t~ret21 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret21;havoc start_simulation_#t~ret21; 17660#L1294 assume !(0 != start_simulation_~tmp___0~1); 17149#L1262-1 [2018-11-22 21:21:34,705 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-22 21:21:34,705 INFO L82 PathProgramCache]: Analyzing trace with hash -334207611, now seen corresponding path program 1 times [2018-11-22 21:21:34,706 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-22 21:21:34,706 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-22 21:21:34,706 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-22 21:21:34,706 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-22 21:21:34,706 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-22 21:21:34,710 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-22 21:21:34,741 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-22 21:21:34,741 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-22 21:21:34,741 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2018-11-22 21:21:34,742 INFO L799 eck$LassoCheckResult]: stem already infeasible [2018-11-22 21:21:34,742 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-22 21:21:34,742 INFO L82 PathProgramCache]: Analyzing trace with hash -850602803, now seen corresponding path program 1 times [2018-11-22 21:21:34,742 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-22 21:21:34,742 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-22 21:21:34,743 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-22 21:21:34,743 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-22 21:21:34,743 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-22 21:21:34,748 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-22 21:21:34,770 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-22 21:21:34,770 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-22 21:21:34,770 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-22 21:21:34,770 INFO L811 eck$LassoCheckResult]: loop already infeasible [2018-11-22 21:21:34,770 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-22 21:21:34,770 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-22 21:21:34,771 INFO L87 Difference]: Start difference. First operand 1627 states and 2419 transitions. cyclomatic complexity: 793 Second operand 3 states. [2018-11-22 21:21:34,809 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-22 21:21:34,809 INFO L93 Difference]: Finished difference Result 1627 states and 2411 transitions. [2018-11-22 21:21:34,810 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-22 21:21:34,810 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1627 states and 2411 transitions. [2018-11-22 21:21:34,815 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1518 [2018-11-22 21:21:34,822 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1627 states to 1627 states and 2411 transitions. [2018-11-22 21:21:34,822 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1627 [2018-11-22 21:21:34,823 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1627 [2018-11-22 21:21:34,823 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1627 states and 2411 transitions. [2018-11-22 21:21:34,826 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-22 21:21:34,826 INFO L705 BuchiCegarLoop]: Abstraction has 1627 states and 2411 transitions. [2018-11-22 21:21:34,828 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1627 states and 2411 transitions. [2018-11-22 21:21:34,845 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1627 to 1627. [2018-11-22 21:21:34,845 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1627 states. [2018-11-22 21:21:34,849 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1627 states to 1627 states and 2411 transitions. [2018-11-22 21:21:34,849 INFO L728 BuchiCegarLoop]: Abstraction has 1627 states and 2411 transitions. [2018-11-22 21:21:34,849 INFO L608 BuchiCegarLoop]: Abstraction has 1627 states and 2411 transitions. [2018-11-22 21:21:34,849 INFO L442 BuchiCegarLoop]: ======== Iteration 11============ [2018-11-22 21:21:34,849 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1627 states and 2411 transitions. [2018-11-22 21:21:34,854 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1518 [2018-11-22 21:21:34,854 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-22 21:21:34,854 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-22 21:21:34,855 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-22 21:21:34,856 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-22 21:21:34,856 INFO L794 eck$LassoCheckResult]: Stem: 20703#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2; 20606#L-1 havoc main_#res;havoc main_~__retres1~10;havoc main_~__retres1~10;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 20607#L1225 havoc start_simulation_#t~ret20, start_simulation_#t~ret21, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 21036#L564 assume 1 == ~m_i~0;~m_st~0 := 0; 20640#L571-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 20352#L576-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 20353#L581-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 21039#L586-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 20816#L591-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 20452#L596-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 20453#L601-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 21030#L606-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 20943#L611-1 assume !(0 == ~M_E~0); 20944#L828-1 assume !(0 == ~T1_E~0); 20723#L833-1 assume !(0 == ~T2_E~0); 20467#L838-1 assume !(0 == ~T3_E~0); 20468#L843-1 assume !(0 == ~T4_E~0); 21111#L848-1 assume !(0 == ~T5_E~0); 20952#L853-1 assume !(0 == ~T6_E~0); 20707#L858-1 assume !(0 == ~T7_E~0); 20269#L863-1 assume !(0 == ~T8_E~0); 20270#L868-1 assume !(0 == ~E_1~0); 20908#L873-1 assume !(0 == ~E_2~0); 20792#L878-1 assume !(0 == ~E_3~0); 20576#L883-1 assume !(0 == ~E_4~0); 20577#L888-1 assume !(0 == ~E_5~0); 21005#L893-1 assume !(0 == ~E_6~0); 20761#L898-1 assume !(0 == ~E_7~0); 20694#L903-1 assume 0 == ~E_8~0;~E_8~0 := 1; 20414#L908-1 havoc activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 20415#L392 assume !(1 == ~m_pc~0); 20745#L392-2 is_master_triggered_~__retres1~0 := 0; 20748#L403 is_master_triggered_#res := is_master_triggered_~__retres1~0; 21147#L404 activate_threads_#t~ret10 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 21013#L1025 assume !(0 != activate_threads_~tmp~1); 21014#L1025-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 20894#L411 assume !(1 == ~t1_pc~0); 20862#L411-2 is_transmit1_triggered_~__retres1~1 := 0; 20333#L422 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 20334#L423 activate_threads_#t~ret11 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 20433#L1033 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 20646#L1033-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 20647#L430 assume 1 == ~t2_pc~0; 20991#L431 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 20499#L441 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 20454#L442 activate_threads_#t~ret12 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 20455#L1041 assume !(0 != activate_threads_~tmp___1~0); 21165#L1041-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 21166#L449 assume !(1 == ~t3_pc~0); 21075#L449-2 is_transmit3_triggered_~__retres1~3 := 0; 20775#L460 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 20624#L461 activate_threads_#t~ret13 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 20625#L1049 assume !(0 != activate_threads_~tmp___2~0); 21034#L1049-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 20370#L468 assume 1 == ~t4_pc~0; 20371#L469 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 20379#L479 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 20754#L480 activate_threads_#t~ret14 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 20699#L1057 assume !(0 != activate_threads_~tmp___3~0); 20700#L1057-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 20562#L487 assume !(1 == ~t5_pc~0); 20329#L487-2 is_transmit5_triggered_~__retres1~5 := 0; 20328#L498 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 20882#L499 activate_threads_#t~ret15 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 20883#L1065 assume !(0 != activate_threads_~tmp___4~0); 21178#L1065-2 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 20706#L506 assume 1 == ~t6_pc~0; 20528#L507 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6 := 1; 20529#L517 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 21032#L518 activate_threads_#t~ret16 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 20966#L1073 assume !(0 != activate_threads_~tmp___5~0); 20967#L1073-2 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 20818#L525 assume 1 == ~t7_pc~0; 20769#L526 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7 := 1; 20770#L536 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 21167#L537 activate_threads_#t~ret17 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 20582#L1081 assume !(0 != activate_threads_~tmp___6~0); 20583#L1081-2 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 20584#L544 assume !(1 == ~t8_pc~0); 20833#L544-2 is_transmit8_triggered_~__retres1~8 := 0; 20263#L555 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 20264#L556 activate_threads_#t~ret18 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 20403#L1089 assume 0 != activate_threads_~tmp___7~0;~t8_st~0 := 0; 21058#L1089-2 assume !(1 == ~M_E~0); 20717#L921-1 assume !(1 == ~T1_E~0); 20463#L926-1 assume !(1 == ~T2_E~0); 20464#L931-1 assume !(1 == ~T3_E~0); 21109#L936-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 20960#L941-1 assume !(1 == ~T5_E~0); 20713#L946-1 assume !(1 == ~T6_E~0); 20279#L951-1 assume !(1 == ~T7_E~0); 20280#L956-1 assume !(1 == ~T8_E~0); 21035#L961-1 assume !(1 == ~E_1~0); 20797#L966-1 assume !(1 == ~E_2~0); 20589#L971-1 assume !(1 == ~E_3~0); 20590#L976-1 assume 1 == ~E_4~0;~E_4~0 := 2; 21001#L981-1 assume !(1 == ~E_5~0); 20759#L986-1 assume !(1 == ~E_6~0); 20689#L991-1 assume !(1 == ~E_7~0); 20409#L996-1 assume !(1 == ~E_8~0); 20410#L1262-1 [2018-11-22 21:21:34,856 INFO L796 eck$LassoCheckResult]: Loop: 20410#L1262-1 assume !false; 21135#L1263 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret0, eval_#t~nondet1, eval_~tmp_ndt_1~0, eval_#t~nondet2, eval_~tmp_ndt_2~0, eval_#t~nondet3, eval_~tmp_ndt_3~0, eval_#t~nondet4, eval_~tmp_ndt_4~0, eval_#t~nondet5, eval_~tmp_ndt_5~0, eval_#t~nondet6, eval_~tmp_ndt_6~0, eval_#t~nondet7, eval_~tmp_ndt_7~0, eval_#t~nondet8, eval_~tmp_ndt_8~0, eval_#t~nondet9, eval_~tmp_ndt_9~0, eval_~tmp~0;havoc eval_~tmp~0; 20725#L803 assume !false; 20710#L682 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~9;havoc exists_runnable_thread_~__retres1~9; 20711#L624 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9 := 1; 20395#L671 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~9; 21123#L672 eval_#t~ret0 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret0;havoc eval_#t~ret0; 21186#L686 assume !(0 != eval_~tmp~0); 21185#L818 start_simulation_~kernel_st~0 := 2; 21184#L564-1 start_simulation_~kernel_st~0 := 3; 21046#L828-2 assume !(0 == ~M_E~0); 21041#L828-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 20823#L833-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 20459#L838-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 20460#L843-3 assume !(0 == ~T4_E~0); 21105#L848-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 20956#L853-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 20709#L858-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 20274#L863-3 assume !(0 == ~T8_E~0); 20275#L868-3 assume 0 == ~E_1~0;~E_1~0 := 1; 20909#L873-3 assume 0 == ~E_2~0;~E_2~0 := 1; 20793#L878-3 assume 0 == ~E_3~0;~E_3~0 := 1; 20579#L883-3 assume !(0 == ~E_4~0); 20580#L888-3 assume 0 == ~E_5~0;~E_5~0 := 1; 21010#L893-3 assume 0 == ~E_6~0;~E_6~0 := 1; 20762#L898-3 assume 0 == ~E_7~0;~E_7~0 := 1; 20680#L903-3 assume 0 == ~E_8~0;~E_8~0 := 1; 20407#L908-3 havoc activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 20408#L392-27 assume !(1 == ~m_pc~0); 20806#L392-29 is_master_triggered_~__retres1~0 := 0; 20819#L403-9 is_master_triggered_#res := is_master_triggered_~__retres1~0; 21145#L404-9 activate_threads_#t~ret10 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 21052#L1025-27 assume !(0 != activate_threads_~tmp~1); 21047#L1025-29 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 20835#L411-27 assume 1 == ~t1_pc~0; 20836#L412-9 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 20286#L422-9 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 20287#L423-9 activate_threads_#t~ret11 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 20416#L1033-27 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 20600#L1033-29 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 20604#L430-27 assume !(1 == ~t2_pc~0); 20985#L430-29 is_transmit2_triggered_~__retres1~2 := 0; 20495#L441-9 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 20496#L442-9 activate_threads_#t~ret12 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 20594#L1041-27 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 21127#L1041-29 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 21086#L449-27 assume 1 == ~t3_pc~0; 21053#L450-9 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 20652#L460-9 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 20598#L461-9 activate_threads_#t~ret13 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 20599#L1049-27 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 20854#L1049-29 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 20859#L468-27 assume 1 == ~t4_pc~0; 21140#L469-9 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 20923#L479-9 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 20739#L480-9 activate_threads_#t~ret14 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 20494#L1057-27 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 20469#L1057-29 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 20351#L487-27 assume 1 == ~t5_pc~0; 20323#L488-9 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 20324#L498-9 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 20880#L499-9 activate_threads_#t~ret15 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 20881#L1065-27 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 21092#L1065-29 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 20688#L506-27 assume 1 == ~t6_pc~0; 20486#L507-9 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6 := 1; 20487#L517-9 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 21017#L518-9 activate_threads_#t~ret16 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 20924#L1073-27 assume 0 != activate_threads_~tmp___5~0;~t6_st~0 := 0; 20764#L1073-29 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 20765#L525-27 assume 1 == ~t7_pc~0; 20675#L526-9 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7 := 1; 20676#L536-9 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 21103#L537-9 activate_threads_#t~ret17 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 20541#L1081-27 assume 0 != activate_threads_~tmp___6~0;~t7_st~0 := 0; 20542#L1081-29 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 20545#L544-27 assume 1 == ~t8_pc~0; 20918#L545-9 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8 := 1; 20426#L555-9 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 20362#L556-9 activate_threads_#t~ret18 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 20363#L1089-27 assume 0 != activate_threads_~tmp___7~0;~t8_st~0 := 0; 21112#L1089-29 assume !(1 == ~M_E~0); 20722#L921-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 20465#L926-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 20466#L931-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 21110#L936-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 20962#L941-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 20714#L946-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 20267#L951-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 20268#L956-3 assume !(1 == ~T8_E~0); 20907#L961-3 assume 1 == ~E_1~0;~E_1~0 := 2; 20790#L966-3 assume 1 == ~E_2~0;~E_2~0 := 2; 20574#L971-3 assume 1 == ~E_3~0;~E_3~0 := 2; 20575#L976-3 assume 1 == ~E_4~0;~E_4~0 := 2; 21004#L981-3 assume 1 == ~E_5~0;~E_5~0 := 2; 20760#L986-3 assume 1 == ~E_6~0;~E_6~0 := 2; 20693#L991-3 assume 1 == ~E_7~0;~E_7~0 := 2; 20411#L996-3 assume !(1 == ~E_8~0); 20412#L1001-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~9;havoc exists_runnable_thread_~__retres1~9; 21455#L624-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9 := 1; 21445#L671-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~9; 21440#L672-1 start_simulation_#t~ret20 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret20;havoc start_simulation_#t~ret20; 21437#L1281 assume !(0 == start_simulation_~tmp~3); 21435#L1281-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret19, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~9;havoc exists_runnable_thread_~__retres1~9; 21260#L624-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9 := 1; 21251#L671-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~9; 21249#L672-2 stop_simulation_#t~ret19 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret19;havoc stop_simulation_#t~ret19; 21234#L1236 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 21067#L1243 stop_simulation_#res := stop_simulation_~__retres2~0; 21068#L1244 start_simulation_#t~ret21 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret21;havoc start_simulation_#t~ret21; 20916#L1294 assume !(0 != start_simulation_~tmp___0~1); 20410#L1262-1 [2018-11-22 21:21:34,856 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-22 21:21:34,856 INFO L82 PathProgramCache]: Analyzing trace with hash -1476710077, now seen corresponding path program 1 times [2018-11-22 21:21:34,857 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-22 21:21:34,857 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-22 21:21:34,857 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-22 21:21:34,857 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-22 21:21:34,857 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-22 21:21:34,861 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-22 21:21:34,883 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-22 21:21:34,883 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-22 21:21:34,884 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2018-11-22 21:21:34,884 INFO L799 eck$LassoCheckResult]: stem already infeasible [2018-11-22 21:21:34,884 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-22 21:21:34,884 INFO L82 PathProgramCache]: Analyzing trace with hash -1734111793, now seen corresponding path program 1 times [2018-11-22 21:21:34,884 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-22 21:21:34,884 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-22 21:21:34,885 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-22 21:21:34,885 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-22 21:21:34,885 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-22 21:21:34,890 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-22 21:21:34,918 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-22 21:21:34,918 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-22 21:21:34,918 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-22 21:21:34,919 INFO L811 eck$LassoCheckResult]: loop already infeasible [2018-11-22 21:21:34,919 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-22 21:21:34,919 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-22 21:21:34,919 INFO L87 Difference]: Start difference. First operand 1627 states and 2411 transitions. cyclomatic complexity: 785 Second operand 3 states. [2018-11-22 21:21:34,970 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-22 21:21:34,970 INFO L93 Difference]: Finished difference Result 1627 states and 2385 transitions. [2018-11-22 21:21:34,971 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-22 21:21:34,972 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1627 states and 2385 transitions. [2018-11-22 21:21:34,977 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1518 [2018-11-22 21:21:34,983 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1627 states to 1627 states and 2385 transitions. [2018-11-22 21:21:34,984 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1627 [2018-11-22 21:21:34,985 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1627 [2018-11-22 21:21:34,985 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1627 states and 2385 transitions. [2018-11-22 21:21:34,987 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-22 21:21:34,987 INFO L705 BuchiCegarLoop]: Abstraction has 1627 states and 2385 transitions. [2018-11-22 21:21:34,989 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1627 states and 2385 transitions. [2018-11-22 21:21:35,036 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1627 to 1627. [2018-11-22 21:21:35,036 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1627 states. [2018-11-22 21:21:35,039 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1627 states to 1627 states and 2385 transitions. [2018-11-22 21:21:35,039 INFO L728 BuchiCegarLoop]: Abstraction has 1627 states and 2385 transitions. [2018-11-22 21:21:35,040 INFO L608 BuchiCegarLoop]: Abstraction has 1627 states and 2385 transitions. [2018-11-22 21:21:35,040 INFO L442 BuchiCegarLoop]: ======== Iteration 12============ [2018-11-22 21:21:35,040 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1627 states and 2385 transitions. [2018-11-22 21:21:35,044 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1518 [2018-11-22 21:21:35,044 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-22 21:21:35,044 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-22 21:21:35,045 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-22 21:21:35,046 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-22 21:21:35,046 INFO L794 eck$LassoCheckResult]: Stem: 23969#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2; 23870#L-1 havoc main_#res;havoc main_~__retres1~10;havoc main_~__retres1~10;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 23871#L1225 havoc start_simulation_#t~ret20, start_simulation_#t~ret21, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 24302#L564 assume 1 == ~m_i~0;~m_st~0 := 0; 23905#L571-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 23613#L576-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 23614#L581-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 24304#L586-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 24083#L591-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 23715#L596-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 23716#L601-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 24296#L606-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 24210#L611-1 assume !(0 == ~M_E~0); 24211#L828-1 assume !(0 == ~T1_E~0); 23989#L833-1 assume !(0 == ~T2_E~0); 23730#L838-1 assume !(0 == ~T3_E~0); 23731#L843-1 assume !(0 == ~T4_E~0); 24381#L848-1 assume !(0 == ~T5_E~0); 24219#L853-1 assume !(0 == ~T6_E~0); 23973#L858-1 assume !(0 == ~T7_E~0); 23530#L863-1 assume !(0 == ~T8_E~0); 23531#L868-1 assume !(0 == ~E_1~0); 24173#L873-1 assume !(0 == ~E_2~0); 24059#L878-1 assume !(0 == ~E_3~0); 23839#L883-1 assume !(0 == ~E_4~0); 23840#L888-1 assume !(0 == ~E_5~0); 24271#L893-1 assume !(0 == ~E_6~0); 24027#L898-1 assume !(0 == ~E_7~0); 23960#L903-1 assume !(0 == ~E_8~0); 23675#L908-1 havoc activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 23676#L392 assume !(1 == ~m_pc~0); 24011#L392-2 is_master_triggered_~__retres1~0 := 0; 24014#L403 is_master_triggered_#res := is_master_triggered_~__retres1~0; 24420#L404 activate_threads_#t~ret10 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 24279#L1025 assume !(0 != activate_threads_~tmp~1); 24280#L1025-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 24160#L411 assume !(1 == ~t1_pc~0); 24128#L411-2 is_transmit1_triggered_~__retres1~1 := 0; 23594#L422 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 23595#L423 activate_threads_#t~ret11 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 23695#L1033 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 23911#L1033-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 23912#L430 assume 1 == ~t2_pc~0; 24257#L431 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 23762#L441 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 23717#L442 activate_threads_#t~ret12 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 23718#L1041 assume !(0 != activate_threads_~tmp___1~0); 24440#L1041-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 24441#L449 assume !(1 == ~t3_pc~0); 24341#L449-2 is_transmit3_triggered_~__retres1~3 := 0; 24042#L460 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 23889#L461 activate_threads_#t~ret13 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 23890#L1049 assume !(0 != activate_threads_~tmp___2~0); 24300#L1049-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 23631#L468 assume 1 == ~t4_pc~0; 23632#L469 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 23640#L479 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 24020#L480 activate_threads_#t~ret14 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 23965#L1057 assume !(0 != activate_threads_~tmp___3~0); 23966#L1057-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 23825#L487 assume !(1 == ~t5_pc~0); 23590#L487-2 is_transmit5_triggered_~__retres1~5 := 0; 23589#L498 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 24148#L499 activate_threads_#t~ret15 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 24149#L1065 assume !(0 != activate_threads_~tmp___4~0); 24453#L1065-2 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 23972#L506 assume 1 == ~t6_pc~0; 23791#L507 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6 := 1; 23792#L517 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 24298#L518 activate_threads_#t~ret16 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 24232#L1073 assume !(0 != activate_threads_~tmp___5~0); 24233#L1073-2 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 24085#L525 assume 1 == ~t7_pc~0; 24036#L526 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7 := 1; 24037#L536 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 24442#L537 activate_threads_#t~ret17 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 23846#L1081 assume !(0 != activate_threads_~tmp___6~0); 23847#L1081-2 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 23848#L544 assume !(1 == ~t8_pc~0); 24099#L544-2 is_transmit8_triggered_~__retres1~8 := 0; 23524#L555 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 23525#L556 activate_threads_#t~ret18 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 23664#L1089 assume 0 != activate_threads_~tmp___7~0;~t8_st~0 := 0; 24324#L1089-2 assume !(1 == ~M_E~0); 23983#L921-1 assume !(1 == ~T1_E~0); 23726#L926-1 assume !(1 == ~T2_E~0); 23727#L931-1 assume !(1 == ~T3_E~0); 24379#L936-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 24227#L941-1 assume !(1 == ~T5_E~0); 23979#L946-1 assume !(1 == ~T6_E~0); 23540#L951-1 assume !(1 == ~T7_E~0); 23541#L956-1 assume !(1 == ~T8_E~0); 24301#L961-1 assume !(1 == ~E_1~0); 24064#L966-1 assume !(1 == ~E_2~0); 23853#L971-1 assume !(1 == ~E_3~0); 23854#L976-1 assume 1 == ~E_4~0;~E_4~0 := 2; 24267#L981-1 assume !(1 == ~E_5~0); 24025#L986-1 assume !(1 == ~E_6~0); 23954#L991-1 assume !(1 == ~E_7~0); 23670#L996-1 assume !(1 == ~E_8~0); 23671#L1262-1 [2018-11-22 21:21:35,046 INFO L796 eck$LassoCheckResult]: Loop: 23671#L1262-1 assume !false; 24408#L1263 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret0, eval_#t~nondet1, eval_~tmp_ndt_1~0, eval_#t~nondet2, eval_~tmp_ndt_2~0, eval_#t~nondet3, eval_~tmp_ndt_3~0, eval_#t~nondet4, eval_~tmp_ndt_4~0, eval_#t~nondet5, eval_~tmp_ndt_5~0, eval_#t~nondet6, eval_~tmp_ndt_6~0, eval_#t~nondet7, eval_~tmp_ndt_7~0, eval_#t~nondet8, eval_~tmp_ndt_8~0, eval_#t~nondet9, eval_~tmp_ndt_9~0, eval_~tmp~0;havoc eval_~tmp~0; 23991#L803 assume !false; 23976#L682 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~9;havoc exists_runnable_thread_~__retres1~9; 23977#L624 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9 := 1; 23656#L671 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~9; 24395#L672 eval_#t~ret0 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret0;havoc eval_#t~ret0; 24461#L686 assume !(0 != eval_~tmp~0); 24460#L818 start_simulation_~kernel_st~0 := 2; 24459#L564-1 start_simulation_~kernel_st~0 := 3; 24311#L828-2 assume !(0 == ~M_E~0); 24306#L828-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 24089#L833-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 23722#L838-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 23723#L843-3 assume !(0 == ~T4_E~0); 24375#L848-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 24223#L853-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 23975#L858-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 23535#L863-3 assume !(0 == ~T8_E~0); 23536#L868-3 assume 0 == ~E_1~0;~E_1~0 := 1; 24174#L873-3 assume 0 == ~E_2~0;~E_2~0 := 1; 24060#L878-3 assume 0 == ~E_3~0;~E_3~0 := 1; 23843#L883-3 assume !(0 == ~E_4~0); 23844#L888-3 assume 0 == ~E_5~0;~E_5~0 := 1; 24276#L893-3 assume 0 == ~E_6~0;~E_6~0 := 1; 24028#L898-3 assume 0 == ~E_7~0;~E_7~0 := 1; 24029#L903-3 assume !(0 == ~E_8~0); 25114#L908-3 havoc activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 25113#L392-27 assume !(1 == ~m_pc~0); 25111#L392-29 is_master_triggered_~__retres1~0 := 0; 25110#L403-9 is_master_triggered_#res := is_master_triggered_~__retres1~0; 25109#L404-9 activate_threads_#t~ret10 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 25108#L1025-27 assume !(0 != activate_threads_~tmp~1); 25107#L1025-29 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 25106#L411-27 assume 1 == ~t1_pc~0; 25104#L412-9 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 25103#L422-9 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 25102#L423-9 activate_threads_#t~ret11 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 25101#L1033-27 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 25100#L1033-29 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 25099#L430-27 assume 1 == ~t2_pc~0; 25097#L431-9 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 25096#L441-9 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 25095#L442-9 activate_threads_#t~ret12 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 25094#L1041-27 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 25093#L1041-29 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 25092#L449-27 assume 1 == ~t3_pc~0; 25090#L450-9 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 25089#L460-9 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 25088#L461-9 activate_threads_#t~ret13 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 25087#L1049-27 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 25086#L1049-29 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 25085#L468-27 assume !(1 == ~t4_pc~0); 25083#L468-29 is_transmit4_triggered_~__retres1~4 := 0; 25082#L479-9 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 25081#L480-9 activate_threads_#t~ret14 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 25080#L1057-27 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 25079#L1057-29 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 25078#L487-27 assume 1 == ~t5_pc~0; 25076#L488-9 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 25075#L498-9 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 25074#L499-9 activate_threads_#t~ret15 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 25072#L1065-27 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 25069#L1065-29 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 25068#L506-27 assume !(1 == ~t6_pc~0); 25066#L506-29 is_transmit6_triggered_~__retres1~6 := 0; 24925#L517-9 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 24924#L518-9 activate_threads_#t~ret16 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 24855#L1073-27 assume 0 != activate_threads_~tmp___5~0;~t6_st~0 := 0; 24852#L1073-29 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 24850#L525-27 assume !(1 == ~t7_pc~0); 24848#L525-29 is_transmit7_triggered_~__retres1~7 := 0; 24845#L536-9 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 24843#L537-9 activate_threads_#t~ret17 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 24841#L1081-27 assume 0 != activate_threads_~tmp___6~0;~t7_st~0 := 0; 24838#L1081-29 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 24836#L544-27 assume !(1 == ~t8_pc~0); 24833#L544-29 is_transmit8_triggered_~__retres1~8 := 0; 24831#L555-9 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 24829#L556-9 activate_threads_#t~ret18 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 24827#L1089-27 assume 0 != activate_threads_~tmp___7~0;~t8_st~0 := 0; 24824#L1089-29 assume !(1 == ~M_E~0); 24383#L921-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 24821#L926-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 24816#L931-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 24815#L936-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 24813#L941-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 24811#L946-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 24809#L951-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 24353#L956-3 assume !(1 == ~T8_E~0); 24172#L961-3 assume 1 == ~E_1~0;~E_1~0 := 2; 24057#L966-3 assume 1 == ~E_2~0;~E_2~0 := 2; 23837#L971-3 assume 1 == ~E_3~0;~E_3~0 := 2; 23838#L976-3 assume 1 == ~E_4~0;~E_4~0 := 2; 24270#L981-3 assume 1 == ~E_5~0;~E_5~0 := 2; 24026#L986-3 assume 1 == ~E_6~0;~E_6~0 := 2; 23958#L991-3 assume 1 == ~E_7~0;~E_7~0 := 2; 23672#L996-3 assume !(1 == ~E_8~0); 23673#L1001-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~9;havoc exists_runnable_thread_~__retres1~9; 24397#L624-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9 := 1; 23660#L671-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~9; 24391#L672-1 start_simulation_#t~ret20 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret20;havoc start_simulation_#t~ret20; 24628#L1281 assume !(0 == start_simulation_~tmp~3); 24626#L1281-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret19, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~9;havoc exists_runnable_thread_~__retres1~9; 24536#L624-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9 := 1; 24527#L671-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~9; 24525#L672-2 stop_simulation_#t~ret19 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret19;havoc stop_simulation_#t~ret19; 24510#L1236 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 24333#L1243 stop_simulation_#res := stop_simulation_~__retres2~0; 24334#L1244 start_simulation_#t~ret21 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret21;havoc start_simulation_#t~ret21; 24182#L1294 assume !(0 != start_simulation_~tmp___0~1); 23671#L1262-1 [2018-11-22 21:21:35,046 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-22 21:21:35,046 INFO L82 PathProgramCache]: Analyzing trace with hash -1399809279, now seen corresponding path program 1 times [2018-11-22 21:21:35,046 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-22 21:21:35,046 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-22 21:21:35,047 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-22 21:21:35,047 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-22 21:21:35,047 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-22 21:21:35,051 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-22 21:21:35,081 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-22 21:21:35,082 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-22 21:21:35,082 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2018-11-22 21:21:35,082 INFO L799 eck$LassoCheckResult]: stem already infeasible [2018-11-22 21:21:35,082 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-22 21:21:35,082 INFO L82 PathProgramCache]: Analyzing trace with hash -260806380, now seen corresponding path program 1 times [2018-11-22 21:21:35,082 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-22 21:21:35,082 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-22 21:21:35,083 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-22 21:21:35,083 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-22 21:21:35,083 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-22 21:21:35,089 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-22 21:21:35,118 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-22 21:21:35,119 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-22 21:21:35,119 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-11-22 21:21:35,119 INFO L811 eck$LassoCheckResult]: loop already infeasible [2018-11-22 21:21:35,119 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-22 21:21:35,119 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-22 21:21:35,119 INFO L87 Difference]: Start difference. First operand 1627 states and 2385 transitions. cyclomatic complexity: 759 Second operand 3 states. [2018-11-22 21:21:35,177 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-22 21:21:35,179 INFO L93 Difference]: Finished difference Result 2999 states and 4372 transitions. [2018-11-22 21:21:35,180 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-22 21:21:35,180 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2999 states and 4372 transitions. [2018-11-22 21:21:35,192 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 2887 [2018-11-22 21:21:35,205 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2999 states to 2999 states and 4372 transitions. [2018-11-22 21:21:35,206 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2999 [2018-11-22 21:21:35,210 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2999 [2018-11-22 21:21:35,210 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2999 states and 4372 transitions. [2018-11-22 21:21:35,215 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-22 21:21:35,216 INFO L705 BuchiCegarLoop]: Abstraction has 2999 states and 4372 transitions. [2018-11-22 21:21:35,219 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2999 states and 4372 transitions. [2018-11-22 21:21:35,255 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2999 to 2995. [2018-11-22 21:21:35,256 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2995 states. [2018-11-22 21:21:35,263 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2995 states to 2995 states and 4368 transitions. [2018-11-22 21:21:35,263 INFO L728 BuchiCegarLoop]: Abstraction has 2995 states and 4368 transitions. [2018-11-22 21:21:35,263 INFO L608 BuchiCegarLoop]: Abstraction has 2995 states and 4368 transitions. [2018-11-22 21:21:35,264 INFO L442 BuchiCegarLoop]: ======== Iteration 13============ [2018-11-22 21:21:35,264 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2995 states and 4368 transitions. [2018-11-22 21:21:35,276 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 2883 [2018-11-22 21:21:35,276 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-22 21:21:35,276 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-22 21:21:35,277 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-22 21:21:35,278 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-22 21:21:35,278 INFO L794 eck$LassoCheckResult]: Stem: 28604#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2; 28504#L-1 havoc main_#res;havoc main_~__retres1~10;havoc main_~__retres1~10;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 28505#L1225 havoc start_simulation_#t~ret20, start_simulation_#t~ret21, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 28945#L564 assume 1 == ~m_i~0;~m_st~0 := 0; 28538#L571-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 28247#L576-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 28248#L581-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 28948#L586-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 28724#L591-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 28349#L596-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 28350#L601-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 28939#L606-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 28849#L611-1 assume !(0 == ~M_E~0); 28850#L828-1 assume !(0 == ~T1_E~0); 28625#L833-1 assume !(0 == ~T2_E~0); 28364#L838-1 assume !(0 == ~T3_E~0); 28365#L843-1 assume !(0 == ~T4_E~0); 29028#L848-1 assume !(0 == ~T5_E~0); 28858#L853-1 assume !(0 == ~T6_E~0); 28608#L858-1 assume !(0 == ~T7_E~0); 28165#L863-1 assume !(0 == ~T8_E~0); 28166#L868-1 assume !(0 == ~E_1~0); 28812#L873-1 assume !(0 == ~E_2~0); 28697#L878-1 assume !(0 == ~E_3~0); 28474#L883-1 assume !(0 == ~E_4~0); 28475#L888-1 assume !(0 == ~E_5~0); 28910#L893-1 assume !(0 == ~E_6~0); 28666#L898-1 assume !(0 == ~E_7~0); 28594#L903-1 assume !(0 == ~E_8~0); 28310#L908-1 havoc activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 28311#L392 assume !(1 == ~m_pc~0); 28649#L392-2 is_master_triggered_~__retres1~0 := 0; 28653#L403 is_master_triggered_#res := is_master_triggered_~__retres1~0; 29068#L404 activate_threads_#t~ret10 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 28917#L1025 assume !(0 != activate_threads_~tmp~1); 28918#L1025-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 28799#L411 assume !(1 == ~t1_pc~0); 28767#L411-2 is_transmit1_triggered_~__retres1~1 := 0; 28229#L422 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 28230#L423 activate_threads_#t~ret11 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 28330#L1033 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 28544#L1033-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 28545#L430 assume !(1 == ~t2_pc~0); 28929#L430-2 is_transmit2_triggered_~__retres1~2 := 0; 28396#L441 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 28351#L442 activate_threads_#t~ret12 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 28352#L1041 assume !(0 != activate_threads_~tmp___1~0); 29087#L1041-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 29088#L449 assume !(1 == ~t3_pc~0); 28992#L449-2 is_transmit3_triggered_~__retres1~3 := 0; 28680#L460 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 28522#L461 activate_threads_#t~ret13 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 28523#L1049 assume !(0 != activate_threads_~tmp___2~0); 28943#L1049-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 28266#L468 assume 1 == ~t4_pc~0; 28267#L469 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 28275#L479 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 28659#L480 activate_threads_#t~ret14 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 28600#L1057 assume !(0 != activate_threads_~tmp___3~0); 28601#L1057-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 28460#L487 assume !(1 == ~t5_pc~0); 28225#L487-2 is_transmit5_triggered_~__retres1~5 := 0; 28224#L498 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 28787#L499 activate_threads_#t~ret15 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 28788#L1065 assume !(0 != activate_threads_~tmp___4~0); 29100#L1065-2 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 28607#L506 assume 1 == ~t6_pc~0; 28425#L507 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6 := 1; 28426#L517 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 28941#L518 activate_threads_#t~ret16 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 28871#L1073 assume !(0 != activate_threads_~tmp___5~0); 28872#L1073-2 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 28726#L525 assume 1 == ~t7_pc~0; 28674#L526 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7 := 1; 28675#L536 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 29089#L537 activate_threads_#t~ret17 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 28480#L1081 assume !(0 != activate_threads_~tmp___6~0); 28481#L1081-2 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 28482#L544 assume !(1 == ~t8_pc~0); 28738#L544-2 is_transmit8_triggered_~__retres1~8 := 0; 28159#L555 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 28160#L556 activate_threads_#t~ret18 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 28299#L1089 assume 0 != activate_threads_~tmp___7~0;~t8_st~0 := 0; 28976#L1089-2 assume !(1 == ~M_E~0); 28619#L921-1 assume !(1 == ~T1_E~0); 28360#L926-1 assume !(1 == ~T2_E~0); 28361#L931-1 assume !(1 == ~T3_E~0); 29026#L936-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 28866#L941-1 assume !(1 == ~T5_E~0); 28614#L946-1 assume !(1 == ~T6_E~0); 28175#L951-1 assume !(1 == ~T7_E~0); 28176#L956-1 assume !(1 == ~T8_E~0); 28944#L961-1 assume !(1 == ~E_1~0); 28702#L966-1 assume !(1 == ~E_2~0); 28487#L971-1 assume !(1 == ~E_3~0); 28488#L976-1 assume 1 == ~E_4~0;~E_4~0 := 2; 28905#L981-1 assume !(1 == ~E_5~0); 28664#L986-1 assume !(1 == ~E_6~0); 28589#L991-1 assume !(1 == ~E_7~0); 28305#L996-1 assume !(1 == ~E_8~0); 28306#L1262-1 [2018-11-22 21:21:35,278 INFO L796 eck$LassoCheckResult]: Loop: 28306#L1262-1 assume !false; 29964#L1263 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret0, eval_#t~nondet1, eval_~tmp_ndt_1~0, eval_#t~nondet2, eval_~tmp_ndt_2~0, eval_#t~nondet3, eval_~tmp_ndt_3~0, eval_#t~nondet4, eval_~tmp_ndt_4~0, eval_#t~nondet5, eval_~tmp_ndt_5~0, eval_#t~nondet6, eval_~tmp_ndt_6~0, eval_#t~nondet7, eval_~tmp_ndt_7~0, eval_#t~nondet8, eval_~tmp_ndt_8~0, eval_#t~nondet9, eval_~tmp_ndt_9~0, eval_~tmp~0;havoc eval_~tmp~0; 29962#L803 assume !false; 29960#L682 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~9;havoc exists_runnable_thread_~__retres1~9; 29946#L624 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9 := 1; 29940#L671 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~9; 29938#L672 eval_#t~ret0 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret0;havoc eval_#t~ret0; 29935#L686 assume !(0 != eval_~tmp~0); 29936#L818 start_simulation_~kernel_st~0 := 2; 30549#L564-1 start_simulation_~kernel_st~0 := 3; 30547#L828-2 assume !(0 == ~M_E~0); 30545#L828-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 30543#L833-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 30541#L838-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 30539#L843-3 assume !(0 == ~T4_E~0); 30537#L848-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 30535#L853-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 30533#L858-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 30531#L863-3 assume !(0 == ~T8_E~0); 30529#L868-3 assume 0 == ~E_1~0;~E_1~0 := 1; 30527#L873-3 assume 0 == ~E_2~0;~E_2~0 := 1; 30525#L878-3 assume 0 == ~E_3~0;~E_3~0 := 1; 30523#L883-3 assume !(0 == ~E_4~0); 30521#L888-3 assume 0 == ~E_5~0;~E_5~0 := 1; 30519#L893-3 assume 0 == ~E_6~0;~E_6~0 := 1; 30517#L898-3 assume 0 == ~E_7~0;~E_7~0 := 1; 30515#L903-3 assume !(0 == ~E_8~0); 30513#L908-3 havoc activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 30511#L392-27 assume !(1 == ~m_pc~0); 30508#L392-29 is_master_triggered_~__retres1~0 := 0; 30505#L403-9 is_master_triggered_#res := is_master_triggered_~__retres1~0; 30503#L404-9 activate_threads_#t~ret10 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 30501#L1025-27 assume !(0 != activate_threads_~tmp~1); 30499#L1025-29 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 30497#L411-27 assume 1 == ~t1_pc~0; 30494#L412-9 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 30491#L422-9 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 30489#L423-9 activate_threads_#t~ret11 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 30487#L1033-27 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 30485#L1033-29 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 30483#L430-27 assume !(1 == ~t2_pc~0); 30481#L430-29 is_transmit2_triggered_~__retres1~2 := 0; 30479#L441-9 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 30477#L442-9 activate_threads_#t~ret12 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 30475#L1041-27 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 30473#L1041-29 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 30471#L449-27 assume 1 == ~t3_pc~0; 30468#L450-9 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 30465#L460-9 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 30463#L461-9 activate_threads_#t~ret13 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 30461#L1049-27 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 30459#L1049-29 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 30457#L468-27 assume !(1 == ~t4_pc~0); 30454#L468-29 is_transmit4_triggered_~__retres1~4 := 0; 30451#L479-9 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 30449#L480-9 activate_threads_#t~ret14 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 30447#L1057-27 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 30445#L1057-29 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 30443#L487-27 assume 1 == ~t5_pc~0; 30440#L488-9 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 30437#L498-9 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 30435#L499-9 activate_threads_#t~ret15 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 30433#L1065-27 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 30431#L1065-29 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 30429#L506-27 assume !(1 == ~t6_pc~0); 30426#L506-29 is_transmit6_triggered_~__retres1~6 := 0; 30423#L517-9 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 30421#L518-9 activate_threads_#t~ret16 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 30419#L1073-27 assume 0 != activate_threads_~tmp___5~0;~t6_st~0 := 0; 30417#L1073-29 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 30415#L525-27 assume 1 == ~t7_pc~0; 30412#L526-9 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7 := 1; 30409#L536-9 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 30407#L537-9 activate_threads_#t~ret17 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 30405#L1081-27 assume 0 != activate_threads_~tmp___6~0;~t7_st~0 := 0; 30403#L1081-29 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 30401#L544-27 assume !(1 == ~t8_pc~0); 30397#L544-29 is_transmit8_triggered_~__retres1~8 := 0; 30395#L555-9 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 30393#L556-9 activate_threads_#t~ret18 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 30391#L1089-27 assume 0 != activate_threads_~tmp___7~0;~t8_st~0 := 0; 30387#L1089-29 assume !(1 == ~M_E~0); 30386#L921-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 30385#L926-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 30384#L931-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 30383#L936-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 30382#L941-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 30381#L946-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 30380#L951-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 30379#L956-3 assume !(1 == ~T8_E~0); 30378#L961-3 assume 1 == ~E_1~0;~E_1~0 := 2; 30377#L966-3 assume 1 == ~E_2~0;~E_2~0 := 2; 30376#L971-3 assume 1 == ~E_3~0;~E_3~0 := 2; 30375#L976-3 assume 1 == ~E_4~0;~E_4~0 := 2; 30373#L981-3 assume 1 == ~E_5~0;~E_5~0 := 2; 30371#L986-3 assume 1 == ~E_6~0;~E_6~0 := 2; 30369#L991-3 assume 1 == ~E_7~0;~E_7~0 := 2; 30367#L996-3 assume !(1 == ~E_8~0); 30364#L1001-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~9;havoc exists_runnable_thread_~__retres1~9; 30354#L624-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9 := 1; 30346#L671-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~9; 30344#L672-1 start_simulation_#t~ret20 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret20;havoc start_simulation_#t~ret20; 30288#L1281 assume !(0 == start_simulation_~tmp~3); 30286#L1281-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret19, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~9;havoc exists_runnable_thread_~__retres1~9; 30278#L624-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9 := 1; 30269#L671-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~9; 30267#L672-2 stop_simulation_#t~ret19 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret19;havoc stop_simulation_#t~ret19; 30266#L1236 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 30265#L1243 stop_simulation_#res := stop_simulation_~__retres2~0; 30264#L1244 start_simulation_#t~ret21 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret21;havoc start_simulation_#t~ret21; 30263#L1294 assume !(0 != start_simulation_~tmp___0~1); 28306#L1262-1 [2018-11-22 21:21:35,278 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-22 21:21:35,278 INFO L82 PathProgramCache]: Analyzing trace with hash 1753510624, now seen corresponding path program 1 times [2018-11-22 21:21:35,279 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-22 21:21:35,279 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-22 21:21:35,279 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-22 21:21:35,279 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-22 21:21:35,279 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-22 21:21:35,284 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-22 21:21:35,311 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-22 21:21:35,311 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-22 21:21:35,312 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2018-11-22 21:21:35,312 INFO L799 eck$LassoCheckResult]: stem already infeasible [2018-11-22 21:21:35,312 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-22 21:21:35,312 INFO L82 PathProgramCache]: Analyzing trace with hash -1730952876, now seen corresponding path program 1 times [2018-11-22 21:21:35,312 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-22 21:21:35,312 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-22 21:21:35,313 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-22 21:21:35,313 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-22 21:21:35,313 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-22 21:21:35,320 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-22 21:21:35,350 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-22 21:21:35,350 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-22 21:21:35,350 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-11-22 21:21:35,350 INFO L811 eck$LassoCheckResult]: loop already infeasible [2018-11-22 21:21:35,350 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-22 21:21:35,351 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-22 21:21:35,351 INFO L87 Difference]: Start difference. First operand 2995 states and 4368 transitions. cyclomatic complexity: 1375 Second operand 3 states. [2018-11-22 21:21:35,472 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-22 21:21:35,472 INFO L93 Difference]: Finished difference Result 5595 states and 8121 transitions. [2018-11-22 21:21:35,474 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-22 21:21:35,474 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 5595 states and 8121 transitions. [2018-11-22 21:21:35,495 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 5472 [2018-11-22 21:21:35,522 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 5595 states to 5595 states and 8121 transitions. [2018-11-22 21:21:35,522 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 5595 [2018-11-22 21:21:35,527 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 5595 [2018-11-22 21:21:35,528 INFO L73 IsDeterministic]: Start isDeterministic. Operand 5595 states and 8121 transitions. [2018-11-22 21:21:35,535 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-22 21:21:35,535 INFO L705 BuchiCegarLoop]: Abstraction has 5595 states and 8121 transitions. [2018-11-22 21:21:35,540 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 5595 states and 8121 transitions. [2018-11-22 21:21:35,599 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 5595 to 5587. [2018-11-22 21:21:35,599 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 5587 states. [2018-11-22 21:21:35,609 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 5587 states to 5587 states and 8113 transitions. [2018-11-22 21:21:35,609 INFO L728 BuchiCegarLoop]: Abstraction has 5587 states and 8113 transitions. [2018-11-22 21:21:35,610 INFO L608 BuchiCegarLoop]: Abstraction has 5587 states and 8113 transitions. [2018-11-22 21:21:35,610 INFO L442 BuchiCegarLoop]: ======== Iteration 14============ [2018-11-22 21:21:35,610 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 5587 states and 8113 transitions. [2018-11-22 21:21:35,626 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 5464 [2018-11-22 21:21:35,626 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-22 21:21:35,626 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-22 21:21:35,628 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-22 21:21:35,628 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-22 21:21:35,628 INFO L794 eck$LassoCheckResult]: Stem: 37198#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2; 37099#L-1 havoc main_#res;havoc main_~__retres1~10;havoc main_~__retres1~10;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 37100#L1225 havoc start_simulation_#t~ret20, start_simulation_#t~ret21, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 37537#L564 assume 1 == ~m_i~0;~m_st~0 := 0; 37135#L571-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 36846#L576-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 36847#L581-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 37540#L586-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 37312#L591-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 36943#L596-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 36944#L601-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 37531#L606-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 37442#L611-1 assume !(0 == ~M_E~0); 37443#L828-1 assume !(0 == ~T1_E~0); 37218#L833-1 assume !(0 == ~T2_E~0); 36958#L838-1 assume !(0 == ~T3_E~0); 36959#L843-1 assume !(0 == ~T4_E~0); 37620#L848-1 assume !(0 == ~T5_E~0); 37452#L853-1 assume !(0 == ~T6_E~0); 37202#L858-1 assume !(0 == ~T7_E~0); 36764#L863-1 assume !(0 == ~T8_E~0); 36765#L868-1 assume !(0 == ~E_1~0); 37406#L873-1 assume !(0 == ~E_2~0); 37287#L878-1 assume !(0 == ~E_3~0); 37067#L883-1 assume !(0 == ~E_4~0); 37068#L888-1 assume !(0 == ~E_5~0); 37508#L893-1 assume !(0 == ~E_6~0); 37256#L898-1 assume !(0 == ~E_7~0); 37190#L903-1 assume !(0 == ~E_8~0); 36905#L908-1 havoc activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 36906#L392 assume !(1 == ~m_pc~0); 37240#L392-2 is_master_triggered_~__retres1~0 := 0; 37243#L403 is_master_triggered_#res := is_master_triggered_~__retres1~0; 37671#L404 activate_threads_#t~ret10 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 37513#L1025 assume !(0 != activate_threads_~tmp~1); 37514#L1025-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 37393#L411 assume !(1 == ~t1_pc~0); 37361#L411-2 is_transmit1_triggered_~__retres1~1 := 0; 36831#L422 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 36832#L423 activate_threads_#t~ret11 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 36925#L1033 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 37141#L1033-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 37142#L430 assume !(1 == ~t2_pc~0); 37522#L430-2 is_transmit2_triggered_~__retres1~2 := 0; 36993#L441 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 36945#L442 activate_threads_#t~ret12 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 36946#L1041 assume !(0 != activate_threads_~tmp___1~0); 37702#L1041-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 37703#L449 assume !(1 == ~t3_pc~0); 37583#L449-2 is_transmit3_triggered_~__retres1~3 := 0; 37273#L460 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 37119#L461 activate_threads_#t~ret13 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 37120#L1049 assume !(0 != activate_threads_~tmp___2~0); 37535#L1049-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 36865#L468 assume !(1 == ~t4_pc~0); 36866#L468-2 is_transmit4_triggered_~__retres1~4 := 0; 36871#L479 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 37249#L480 activate_threads_#t~ret14 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 37194#L1057 assume !(0 != activate_threads_~tmp___3~0); 37195#L1057-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 37053#L487 assume !(1 == ~t5_pc~0); 36824#L487-2 is_transmit5_triggered_~__retres1~5 := 0; 36823#L498 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 37381#L499 activate_threads_#t~ret15 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 37382#L1065 assume !(0 != activate_threads_~tmp___4~0); 37716#L1065-2 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 37201#L506 assume 1 == ~t6_pc~0; 37019#L507 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6 := 1; 37020#L517 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 37533#L518 activate_threads_#t~ret16 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 37465#L1073 assume !(0 != activate_threads_~tmp___5~0); 37466#L1073-2 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 37313#L525 assume 1 == ~t7_pc~0; 37264#L526 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7 := 1; 37265#L536 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 37704#L537 activate_threads_#t~ret17 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 37073#L1081 assume !(0 != activate_threads_~tmp___6~0); 37074#L1081-2 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 37075#L544 assume !(1 == ~t8_pc~0); 37332#L544-2 is_transmit8_triggered_~__retres1~8 := 0; 36758#L555 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 36759#L556 activate_threads_#t~ret18 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 36894#L1089 assume 0 != activate_threads_~tmp___7~0;~t8_st~0 := 0; 37566#L1089-2 assume !(1 == ~M_E~0); 37212#L921-1 assume !(1 == ~T1_E~0); 36954#L926-1 assume !(1 == ~T2_E~0); 36955#L931-1 assume !(1 == ~T3_E~0); 37618#L936-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 37460#L941-1 assume !(1 == ~T5_E~0); 37208#L946-1 assume !(1 == ~T6_E~0); 36774#L951-1 assume !(1 == ~T7_E~0); 36775#L956-1 assume !(1 == ~T8_E~0); 37536#L961-1 assume !(1 == ~E_1~0); 37292#L966-1 assume !(1 == ~E_2~0); 37080#L971-1 assume !(1 == ~E_3~0); 37081#L976-1 assume 1 == ~E_4~0;~E_4~0 := 2; 37501#L981-1 assume !(1 == ~E_5~0); 37254#L986-1 assume !(1 == ~E_6~0); 37184#L991-1 assume !(1 == ~E_7~0); 36900#L996-1 assume !(1 == ~E_8~0); 36901#L1262-1 [2018-11-22 21:21:35,629 INFO L796 eck$LassoCheckResult]: Loop: 36901#L1262-1 assume !false; 37648#L1263 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret0, eval_#t~nondet1, eval_~tmp_ndt_1~0, eval_#t~nondet2, eval_~tmp_ndt_2~0, eval_#t~nondet3, eval_~tmp_ndt_3~0, eval_#t~nondet4, eval_~tmp_ndt_4~0, eval_#t~nondet5, eval_~tmp_ndt_5~0, eval_#t~nondet6, eval_~tmp_ndt_6~0, eval_#t~nondet7, eval_~tmp_ndt_7~0, eval_#t~nondet8, eval_~tmp_ndt_8~0, eval_#t~nondet9, eval_~tmp_ndt_9~0, eval_~tmp~0;havoc eval_~tmp~0; 37220#L803 assume !false; 37205#L682 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~9;havoc exists_runnable_thread_~__retres1~9; 37206#L624 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9 := 1; 36886#L671 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~9; 37615#L672 eval_#t~ret0 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret0;havoc eval_#t~ret0; 36840#L686 assume !(0 != eval_~tmp~0); 36842#L818 start_simulation_~kernel_st~0 := 2; 42283#L564-1 start_simulation_~kernel_st~0 := 3; 42282#L828-2 assume !(0 == ~M_E~0); 42281#L828-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 42280#L833-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 42277#L838-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 42275#L843-3 assume !(0 == ~T4_E~0); 42273#L848-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 42148#L853-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 42147#L858-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 42146#L863-3 assume !(0 == ~T8_E~0); 42145#L868-3 assume 0 == ~E_1~0;~E_1~0 := 1; 42144#L873-3 assume 0 == ~E_2~0;~E_2~0 := 1; 42143#L878-3 assume 0 == ~E_3~0;~E_3~0 := 1; 42142#L883-3 assume !(0 == ~E_4~0); 42141#L888-3 assume 0 == ~E_5~0;~E_5~0 := 1; 42140#L893-3 assume 0 == ~E_6~0;~E_6~0 := 1; 42139#L898-3 assume 0 == ~E_7~0;~E_7~0 := 1; 42138#L903-3 assume !(0 == ~E_8~0); 42137#L908-3 havoc activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 42136#L392-27 assume !(1 == ~m_pc~0); 42134#L392-29 is_master_triggered_~__retres1~0 := 0; 42133#L403-9 is_master_triggered_#res := is_master_triggered_~__retres1~0; 42132#L404-9 activate_threads_#t~ret10 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 42131#L1025-27 assume !(0 != activate_threads_~tmp~1); 42130#L1025-29 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 42129#L411-27 assume !(1 == ~t1_pc~0); 42128#L411-29 is_transmit1_triggered_~__retres1~1 := 0; 42126#L422-9 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 42125#L423-9 activate_threads_#t~ret11 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 42124#L1033-27 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 42123#L1033-29 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 37487#L430-27 assume !(1 == ~t2_pc~0); 37488#L430-29 is_transmit2_triggered_~__retres1~2 := 0; 36986#L441-9 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 36987#L442-9 activate_threads_#t~ret12 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 37085#L1041-27 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 37638#L1041-29 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 37592#L449-27 assume 1 == ~t3_pc~0; 37561#L450-9 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 37147#L460-9 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 37089#L461-9 activate_threads_#t~ret13 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 37090#L1049-27 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 37350#L1049-29 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 37356#L468-27 assume !(1 == ~t4_pc~0); 37690#L468-29 is_transmit4_triggered_~__retres1~4 := 0; 37421#L479-9 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 37234#L480-9 activate_threads_#t~ret14 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 36985#L1057-27 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 36960#L1057-29 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 36845#L487-27 assume 1 == ~t5_pc~0; 36816#L488-9 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 36817#L498-9 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 37378#L499-9 activate_threads_#t~ret15 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 37379#L1065-27 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 37599#L1065-29 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 37183#L506-27 assume !(1 == ~t6_pc~0); 36977#L506-29 is_transmit6_triggered_~__retres1~6 := 0; 36976#L517-9 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 37517#L518-9 activate_threads_#t~ret16 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 37422#L1073-27 assume 0 != activate_threads_~tmp___5~0;~t6_st~0 := 0; 37259#L1073-29 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 37260#L525-27 assume 1 == ~t7_pc~0; 37169#L526-9 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7 := 1; 37170#L536-9 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 37611#L537-9 activate_threads_#t~ret17 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 37032#L1081-27 assume 0 != activate_threads_~tmp___6~0;~t7_st~0 := 0; 37033#L1081-29 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 37036#L544-27 assume !(1 == ~t8_pc~0); 37416#L544-29 is_transmit8_triggered_~__retres1~8 := 0; 36916#L555-9 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 36856#L556-9 activate_threads_#t~ret18 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 36857#L1089-27 assume 0 != activate_threads_~tmp___7~0;~t8_st~0 := 0; 37621#L1089-29 assume !(1 == ~M_E~0); 37214#L921-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 36956#L926-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 36957#L931-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 37619#L936-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 37462#L941-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 37209#L946-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 36762#L951-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 36763#L956-3 assume !(1 == ~T8_E~0); 37404#L961-3 assume 1 == ~E_1~0;~E_1~0 := 2; 37285#L966-3 assume 1 == ~E_2~0;~E_2~0 := 2; 37065#L971-3 assume 1 == ~E_3~0;~E_3~0 := 2; 37066#L976-3 assume 1 == ~E_4~0;~E_4~0 := 2; 37505#L981-3 assume 1 == ~E_5~0;~E_5~0 := 2; 37506#L986-3 assume 1 == ~E_6~0;~E_6~0 := 2; 42050#L991-3 assume 1 == ~E_7~0;~E_7~0 := 2; 42046#L996-3 assume !(1 == ~E_8~0); 42043#L1001-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~9;havoc exists_runnable_thread_~__retres1~9; 41990#L624-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9 := 1; 41983#L671-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~9; 41982#L672-1 start_simulation_#t~ret20 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret20;havoc start_simulation_#t~ret20; 36802#L1281 assume !(0 == start_simulation_~tmp~3); 36803#L1281-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret19, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~9;havoc exists_runnable_thread_~__retres1~9; 36815#L624-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9 := 1; 36893#L671-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~9; 37529#L672-2 stop_simulation_#t~ret19 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret19;havoc stop_simulation_#t~ret19; 37029#L1236 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 37030#L1243 stop_simulation_#res := stop_simulation_~__retres2~0; 37576#L1244 start_simulation_#t~ret21 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret21;havoc start_simulation_#t~ret21; 37414#L1294 assume !(0 != start_simulation_~tmp___0~1); 36901#L1262-1 [2018-11-22 21:21:35,629 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-22 21:21:35,629 INFO L82 PathProgramCache]: Analyzing trace with hash 445505855, now seen corresponding path program 1 times [2018-11-22 21:21:35,629 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-22 21:21:35,629 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-22 21:21:35,630 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-22 21:21:35,630 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-22 21:21:35,630 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-22 21:21:35,635 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-22 21:21:35,667 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-22 21:21:35,667 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-22 21:21:35,668 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2018-11-22 21:21:35,668 INFO L799 eck$LassoCheckResult]: stem already infeasible [2018-11-22 21:21:35,668 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-22 21:21:35,668 INFO L82 PathProgramCache]: Analyzing trace with hash 721700629, now seen corresponding path program 1 times [2018-11-22 21:21:35,668 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-22 21:21:35,668 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-22 21:21:35,669 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-22 21:21:35,669 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-22 21:21:35,669 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-22 21:21:35,675 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-22 21:21:35,696 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-22 21:21:35,697 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-22 21:21:35,697 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-11-22 21:21:35,697 INFO L811 eck$LassoCheckResult]: loop already infeasible [2018-11-22 21:21:35,698 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-22 21:21:35,698 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-22 21:21:35,698 INFO L87 Difference]: Start difference. First operand 5587 states and 8113 transitions. cyclomatic complexity: 2530 Second operand 3 states. [2018-11-22 21:21:35,811 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-22 21:21:35,811 INFO L93 Difference]: Finished difference Result 10502 states and 15186 transitions. [2018-11-22 21:21:35,811 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-22 21:21:35,811 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 10502 states and 15186 transitions. [2018-11-22 21:21:35,845 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 10348 [2018-11-22 21:21:35,877 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 10502 states to 10502 states and 15186 transitions. [2018-11-22 21:21:35,877 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 10502 [2018-11-22 21:21:35,883 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 10502 [2018-11-22 21:21:35,883 INFO L73 IsDeterministic]: Start isDeterministic. Operand 10502 states and 15186 transitions. [2018-11-22 21:21:35,897 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-22 21:21:35,897 INFO L705 BuchiCegarLoop]: Abstraction has 10502 states and 15186 transitions. [2018-11-22 21:21:35,904 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 10502 states and 15186 transitions. [2018-11-22 21:21:36,050 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 10502 to 10486. [2018-11-22 21:21:36,050 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 10486 states. [2018-11-22 21:21:36,067 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 10486 states to 10486 states and 15170 transitions. [2018-11-22 21:21:36,068 INFO L728 BuchiCegarLoop]: Abstraction has 10486 states and 15170 transitions. [2018-11-22 21:21:36,068 INFO L608 BuchiCegarLoop]: Abstraction has 10486 states and 15170 transitions. [2018-11-22 21:21:36,068 INFO L442 BuchiCegarLoop]: ======== Iteration 15============ [2018-11-22 21:21:36,068 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 10486 states and 15170 transitions. [2018-11-22 21:21:36,095 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 10332 [2018-11-22 21:21:36,095 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-22 21:21:36,095 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-22 21:21:36,097 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-22 21:21:36,097 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-22 21:21:36,097 INFO L794 eck$LassoCheckResult]: Stem: 53298#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2; 53198#L-1 havoc main_#res;havoc main_~__retres1~10;havoc main_~__retres1~10;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 53199#L1225 havoc start_simulation_#t~ret20, start_simulation_#t~ret21, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 53655#L564 assume 1 == ~m_i~0;~m_st~0 := 0; 53232#L571-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 52945#L576-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 52946#L581-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 53659#L586-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 53418#L591-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 53043#L596-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 53044#L601-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 53649#L606-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 53559#L611-1 assume !(0 == ~M_E~0); 53560#L828-1 assume !(0 == ~T1_E~0); 53323#L833-1 assume !(0 == ~T2_E~0); 53058#L838-1 assume !(0 == ~T3_E~0); 53059#L843-1 assume !(0 == ~T4_E~0); 53741#L848-1 assume !(0 == ~T5_E~0); 53569#L853-1 assume !(0 == ~T6_E~0); 53305#L858-1 assume !(0 == ~T7_E~0); 52862#L863-1 assume !(0 == ~T8_E~0); 52863#L868-1 assume !(0 == ~E_1~0); 53519#L873-1 assume !(0 == ~E_2~0); 53393#L878-1 assume !(0 == ~E_3~0); 53167#L883-1 assume !(0 == ~E_4~0); 53168#L888-1 assume !(0 == ~E_5~0); 53625#L893-1 assume !(0 == ~E_6~0); 53362#L898-1 assume !(0 == ~E_7~0); 53289#L903-1 assume !(0 == ~E_8~0); 53005#L908-1 havoc activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 53006#L392 assume !(1 == ~m_pc~0); 53346#L392-2 is_master_triggered_~__retres1~0 := 0; 53349#L403 is_master_triggered_#res := is_master_triggered_~__retres1~0; 53783#L404 activate_threads_#t~ret10 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 53630#L1025 assume !(0 != activate_threads_~tmp~1); 53631#L1025-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 53506#L411 assume !(1 == ~t1_pc~0); 53474#L411-2 is_transmit1_triggered_~__retres1~1 := 0; 52930#L422 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 52931#L423 activate_threads_#t~ret11 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 53025#L1033 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 53240#L1033-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 53241#L430 assume !(1 == ~t2_pc~0); 53640#L430-2 is_transmit2_triggered_~__retres1~2 := 0; 53094#L441 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 53045#L442 activate_threads_#t~ret12 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 53046#L1041 assume !(0 != activate_threads_~tmp___1~0); 53809#L1041-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 53810#L449 assume !(1 == ~t3_pc~0); 53703#L449-2 is_transmit3_triggered_~__retres1~3 := 0; 53379#L460 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 53218#L461 activate_threads_#t~ret13 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 53219#L1049 assume !(0 != activate_threads_~tmp___2~0); 53653#L1049-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 52963#L468 assume !(1 == ~t4_pc~0); 52964#L468-2 is_transmit4_triggered_~__retres1~4 := 0; 52971#L479 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 53355#L480 activate_threads_#t~ret14 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 53293#L1057 assume !(0 != activate_threads_~tmp___3~0); 53294#L1057-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 53153#L487 assume !(1 == ~t5_pc~0); 52923#L487-2 is_transmit5_triggered_~__retres1~5 := 0; 52922#L498 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 53493#L499 activate_threads_#t~ret15 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 53494#L1065 assume !(0 != activate_threads_~tmp___4~0); 53822#L1065-2 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 53304#L506 assume !(1 == ~t6_pc~0); 53301#L506-2 is_transmit6_triggered_~__retres1~6 := 0; 53302#L517 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 53651#L518 activate_threads_#t~ret16 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 53583#L1073 assume !(0 != activate_threads_~tmp___5~0); 53584#L1073-2 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 53420#L525 assume 1 == ~t7_pc~0; 53370#L526 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7 := 1; 53371#L536 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 53811#L537 activate_threads_#t~ret17 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 53173#L1081 assume !(0 != activate_threads_~tmp___6~0); 53174#L1081-2 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 53175#L544 assume !(1 == ~t8_pc~0); 53441#L544-2 is_transmit8_triggered_~__retres1~8 := 0; 52856#L555 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 52857#L556 activate_threads_#t~ret18 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 52994#L1089 assume 0 != activate_threads_~tmp___7~0;~t8_st~0 := 0; 53685#L1089-2 assume !(1 == ~M_E~0); 53316#L921-1 assume !(1 == ~T1_E~0); 53054#L926-1 assume !(1 == ~T2_E~0); 53055#L931-1 assume !(1 == ~T3_E~0); 53739#L936-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 53577#L941-1 assume !(1 == ~T5_E~0); 53311#L946-1 assume !(1 == ~T6_E~0); 52872#L951-1 assume !(1 == ~T7_E~0); 52873#L956-1 assume !(1 == ~T8_E~0); 53654#L961-1 assume !(1 == ~E_1~0); 53398#L966-1 assume !(1 == ~E_2~0); 53179#L971-1 assume !(1 == ~E_3~0); 53180#L976-1 assume 1 == ~E_4~0;~E_4~0 := 2; 53619#L981-1 assume !(1 == ~E_5~0); 53360#L986-1 assume !(1 == ~E_6~0); 53283#L991-1 assume !(1 == ~E_7~0); 53000#L996-1 assume !(1 == ~E_8~0); 53001#L1262-1 [2018-11-22 21:21:36,098 INFO L796 eck$LassoCheckResult]: Loop: 53001#L1262-1 assume !false; 57274#L1263 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret0, eval_#t~nondet1, eval_~tmp_ndt_1~0, eval_#t~nondet2, eval_~tmp_ndt_2~0, eval_#t~nondet3, eval_~tmp_ndt_3~0, eval_#t~nondet4, eval_~tmp_ndt_4~0, eval_#t~nondet5, eval_~tmp_ndt_5~0, eval_#t~nondet6, eval_~tmp_ndt_6~0, eval_#t~nondet7, eval_~tmp_ndt_7~0, eval_#t~nondet8, eval_~tmp_ndt_8~0, eval_#t~nondet9, eval_~tmp_ndt_9~0, eval_~tmp~0;havoc eval_~tmp~0; 57271#L803 assume !false; 57267#L682 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~9;havoc exists_runnable_thread_~__retres1~9; 57144#L624 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9 := 1; 57134#L671 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~9; 57127#L672 eval_#t~ret0 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret0;havoc eval_#t~ret0; 57119#L686 assume !(0 != eval_~tmp~0); 57120#L818 start_simulation_~kernel_st~0 := 2; 57623#L564-1 start_simulation_~kernel_st~0 := 3; 57617#L828-2 assume !(0 == ~M_E~0); 57611#L828-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 57604#L833-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 57598#L838-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 57591#L843-3 assume !(0 == ~T4_E~0); 57587#L848-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 57584#L853-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 57581#L858-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 57580#L863-3 assume !(0 == ~T8_E~0); 57579#L868-3 assume 0 == ~E_1~0;~E_1~0 := 1; 57577#L873-3 assume 0 == ~E_2~0;~E_2~0 := 1; 57575#L878-3 assume 0 == ~E_3~0;~E_3~0 := 1; 57573#L883-3 assume !(0 == ~E_4~0); 57571#L888-3 assume 0 == ~E_5~0;~E_5~0 := 1; 57569#L893-3 assume 0 == ~E_6~0;~E_6~0 := 1; 57567#L898-3 assume 0 == ~E_7~0;~E_7~0 := 1; 57565#L903-3 assume !(0 == ~E_8~0); 57563#L908-3 havoc activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 57559#L392-27 assume !(1 == ~m_pc~0); 57556#L392-29 is_master_triggered_~__retres1~0 := 0; 57554#L403-9 is_master_triggered_#res := is_master_triggered_~__retres1~0; 57552#L404-9 activate_threads_#t~ret10 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 57550#L1025-27 assume !(0 != activate_threads_~tmp~1); 57548#L1025-29 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 57546#L411-27 assume 1 == ~t1_pc~0; 57543#L412-9 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 57541#L422-9 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 57539#L423-9 activate_threads_#t~ret11 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 57537#L1033-27 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 57535#L1033-29 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 57532#L430-27 assume !(1 == ~t2_pc~0); 57530#L430-29 is_transmit2_triggered_~__retres1~2 := 0; 57528#L441-9 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 57526#L442-9 activate_threads_#t~ret12 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 57524#L1041-27 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 57522#L1041-29 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 57521#L449-27 assume !(1 == ~t3_pc~0); 57520#L449-29 is_transmit3_triggered_~__retres1~3 := 0; 57516#L460-9 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 57514#L461-9 activate_threads_#t~ret13 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 57512#L1049-27 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 57510#L1049-29 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 57508#L468-27 assume !(1 == ~t4_pc~0); 57506#L468-29 is_transmit4_triggered_~__retres1~4 := 0; 57504#L479-9 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 57502#L480-9 activate_threads_#t~ret14 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 57500#L1057-27 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 57498#L1057-29 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 57496#L487-27 assume 1 == ~t5_pc~0; 57493#L488-9 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 57490#L498-9 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 57488#L499-9 activate_threads_#t~ret15 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 57486#L1065-27 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 57484#L1065-29 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 57482#L506-27 assume !(1 == ~t6_pc~0); 57480#L506-29 is_transmit6_triggered_~__retres1~6 := 0; 57478#L517-9 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 57476#L518-9 activate_threads_#t~ret16 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 57474#L1073-27 assume 0 != activate_threads_~tmp___5~0;~t6_st~0 := 0; 57472#L1073-29 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 57470#L525-27 assume 1 == ~t7_pc~0; 57467#L526-9 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7 := 1; 57464#L536-9 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 57462#L537-9 activate_threads_#t~ret17 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 57460#L1081-27 assume 0 != activate_threads_~tmp___6~0;~t7_st~0 := 0; 57458#L1081-29 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 57456#L544-27 assume !(1 == ~t8_pc~0); 57453#L544-29 is_transmit8_triggered_~__retres1~8 := 0; 57451#L555-9 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 57449#L556-9 activate_threads_#t~ret18 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 57447#L1089-27 assume 0 != activate_threads_~tmp___7~0;~t8_st~0 := 0; 57417#L1089-29 assume !(1 == ~M_E~0); 57415#L921-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 57413#L926-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 57411#L931-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 57409#L936-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 57407#L941-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 57404#L946-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 57402#L951-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 57400#L956-3 assume !(1 == ~T8_E~0); 57398#L961-3 assume 1 == ~E_1~0;~E_1~0 := 2; 57396#L966-3 assume 1 == ~E_2~0;~E_2~0 := 2; 57394#L971-3 assume 1 == ~E_3~0;~E_3~0 := 2; 57391#L976-3 assume 1 == ~E_4~0;~E_4~0 := 2; 57389#L981-3 assume 1 == ~E_5~0;~E_5~0 := 2; 57387#L986-3 assume 1 == ~E_6~0;~E_6~0 := 2; 57385#L991-3 assume 1 == ~E_7~0;~E_7~0 := 2; 57384#L996-3 assume !(1 == ~E_8~0); 57380#L1001-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~9;havoc exists_runnable_thread_~__retres1~9; 57375#L624-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9 := 1; 57367#L671-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~9; 57365#L672-1 start_simulation_#t~ret20 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret20;havoc start_simulation_#t~ret20; 57361#L1281 assume !(0 == start_simulation_~tmp~3); 57357#L1281-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret19, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~9;havoc exists_runnable_thread_~__retres1~9; 57321#L624-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9 := 1; 57313#L671-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~9; 57311#L672-2 stop_simulation_#t~ret19 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret19;havoc stop_simulation_#t~ret19; 57309#L1236 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 57307#L1243 stop_simulation_#res := stop_simulation_~__retres2~0; 57297#L1244 start_simulation_#t~ret21 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret21;havoc start_simulation_#t~ret21; 57289#L1294 assume !(0 != start_simulation_~tmp___0~1); 53001#L1262-1 [2018-11-22 21:21:36,098 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-22 21:21:36,098 INFO L82 PathProgramCache]: Analyzing trace with hash -1183144418, now seen corresponding path program 1 times [2018-11-22 21:21:36,098 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-22 21:21:36,098 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-22 21:21:36,099 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-22 21:21:36,099 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-22 21:21:36,099 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-22 21:21:36,104 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-22 21:21:36,125 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-22 21:21:36,126 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-22 21:21:36,126 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2018-11-22 21:21:36,126 INFO L799 eck$LassoCheckResult]: stem already infeasible [2018-11-22 21:21:36,126 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-22 21:21:36,126 INFO L82 PathProgramCache]: Analyzing trace with hash -1353310059, now seen corresponding path program 1 times [2018-11-22 21:21:36,126 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-22 21:21:36,127 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-22 21:21:36,127 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-22 21:21:36,127 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-22 21:21:36,127 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-22 21:21:36,132 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-22 21:21:36,151 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-22 21:21:36,151 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-22 21:21:36,151 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-11-22 21:21:36,151 INFO L811 eck$LassoCheckResult]: loop already infeasible [2018-11-22 21:21:36,153 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-22 21:21:36,154 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-22 21:21:36,155 INFO L87 Difference]: Start difference. First operand 10486 states and 15170 transitions. cyclomatic complexity: 4692 Second operand 3 states. [2018-11-22 21:21:36,273 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-22 21:21:36,273 INFO L93 Difference]: Finished difference Result 19753 states and 28455 transitions. [2018-11-22 21:21:36,274 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-22 21:21:36,275 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 19753 states and 28455 transitions. [2018-11-22 21:21:36,341 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 19520 [2018-11-22 21:21:36,394 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 19753 states to 19753 states and 28455 transitions. [2018-11-22 21:21:36,394 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 19753 [2018-11-22 21:21:36,406 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 19753 [2018-11-22 21:21:36,406 INFO L73 IsDeterministic]: Start isDeterministic. Operand 19753 states and 28455 transitions. [2018-11-22 21:21:36,420 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-22 21:21:36,420 INFO L705 BuchiCegarLoop]: Abstraction has 19753 states and 28455 transitions. [2018-11-22 21:21:36,435 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 19753 states and 28455 transitions. [2018-11-22 21:21:36,601 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 19753 to 19721. [2018-11-22 21:21:36,601 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 19721 states. [2018-11-22 21:21:36,632 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 19721 states to 19721 states and 28423 transitions. [2018-11-22 21:21:36,632 INFO L728 BuchiCegarLoop]: Abstraction has 19721 states and 28423 transitions. [2018-11-22 21:21:36,632 INFO L608 BuchiCegarLoop]: Abstraction has 19721 states and 28423 transitions. [2018-11-22 21:21:36,632 INFO L442 BuchiCegarLoop]: ======== Iteration 16============ [2018-11-22 21:21:36,633 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 19721 states and 28423 transitions. [2018-11-22 21:21:36,681 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 19488 [2018-11-22 21:21:36,681 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-22 21:21:36,682 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-22 21:21:36,683 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-22 21:21:36,683 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-22 21:21:36,683 INFO L794 eck$LassoCheckResult]: Stem: 83558#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2; 83453#L-1 havoc main_#res;havoc main_~__retres1~10;havoc main_~__retres1~10;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 83454#L1225 havoc start_simulation_#t~ret20, start_simulation_#t~ret21, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 83923#L564 assume 1 == ~m_i~0;~m_st~0 := 0; 83488#L571-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 83193#L576-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 83194#L581-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 83927#L586-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 83685#L591-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 83294#L596-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 83295#L601-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 83916#L606-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 83821#L611-1 assume !(0 == ~M_E~0); 83822#L828-1 assume !(0 == ~T1_E~0); 83582#L833-1 assume !(0 == ~T2_E~0); 83309#L838-1 assume !(0 == ~T3_E~0); 83310#L843-1 assume !(0 == ~T4_E~0); 84012#L848-1 assume !(0 == ~T5_E~0); 83831#L853-1 assume !(0 == ~T6_E~0); 83566#L858-1 assume !(0 == ~T7_E~0); 83110#L863-1 assume !(0 == ~T8_E~0); 83111#L868-1 assume !(0 == ~E_1~0); 83784#L873-1 assume !(0 == ~E_2~0); 83654#L878-1 assume !(0 == ~E_3~0); 83423#L883-1 assume !(0 == ~E_4~0); 83424#L888-1 assume !(0 == ~E_5~0); 83888#L893-1 assume !(0 == ~E_6~0); 83621#L898-1 assume !(0 == ~E_7~0); 83546#L903-1 assume !(0 == ~E_8~0); 83254#L908-1 havoc activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 83255#L392 assume !(1 == ~m_pc~0); 83605#L392-2 is_master_triggered_~__retres1~0 := 0; 83608#L403 is_master_triggered_#res := is_master_triggered_~__retres1~0; 84058#L404 activate_threads_#t~ret10 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 83895#L1025 assume !(0 != activate_threads_~tmp~1); 83896#L1025-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 83770#L411 assume !(1 == ~t1_pc~0); 83736#L411-2 is_transmit1_triggered_~__retres1~1 := 0; 83178#L422 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 83179#L423 activate_threads_#t~ret11 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 83275#L1033 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 83496#L1033-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 83497#L430 assume !(1 == ~t2_pc~0); 83907#L430-2 is_transmit2_triggered_~__retres1~2 := 0; 83348#L441 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 83296#L442 activate_threads_#t~ret12 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 83297#L1041 assume !(0 != activate_threads_~tmp___1~0); 84084#L1041-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 84085#L449 assume !(1 == ~t3_pc~0); 83976#L449-2 is_transmit3_triggered_~__retres1~3 := 0; 83637#L460 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 83473#L461 activate_threads_#t~ret13 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 83474#L1049 assume !(0 != activate_threads_~tmp___2~0); 83921#L1049-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 83213#L468 assume !(1 == ~t4_pc~0); 83214#L468-2 is_transmit4_triggered_~__retres1~4 := 0; 83219#L479 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 83614#L480 activate_threads_#t~ret14 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 83552#L1057 assume !(0 != activate_threads_~tmp___3~0); 83553#L1057-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 83409#L487 assume !(1 == ~t5_pc~0); 83171#L487-2 is_transmit5_triggered_~__retres1~5 := 0; 83170#L498 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 83758#L499 activate_threads_#t~ret15 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 83759#L1065 assume !(0 != activate_threads_~tmp___4~0); 84098#L1065-2 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 83565#L506 assume !(1 == ~t6_pc~0); 83562#L506-2 is_transmit6_triggered_~__retres1~6 := 0; 83563#L517 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 83918#L518 activate_threads_#t~ret16 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 83846#L1073 assume !(0 != activate_threads_~tmp___5~0); 83847#L1073-2 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 83687#L525 assume !(1 == ~t7_pc~0); 83688#L525-2 is_transmit7_triggered_~__retres1~7 := 0; 83690#L536 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 84086#L537 activate_threads_#t~ret17 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 83429#L1081 assume !(0 != activate_threads_~tmp___6~0); 83430#L1081-2 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 83431#L544 assume !(1 == ~t8_pc~0); 83709#L544-2 is_transmit8_triggered_~__retres1~8 := 0; 83104#L555 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 83105#L556 activate_threads_#t~ret18 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 83243#L1089 assume 0 != activate_threads_~tmp___7~0;~t8_st~0 := 0; 83958#L1089-2 assume !(1 == ~M_E~0); 83576#L921-1 assume !(1 == ~T1_E~0); 83305#L926-1 assume !(1 == ~T2_E~0); 83306#L931-1 assume !(1 == ~T3_E~0); 84010#L936-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 83838#L941-1 assume !(1 == ~T5_E~0); 83572#L946-1 assume !(1 == ~T6_E~0); 83120#L951-1 assume !(1 == ~T7_E~0); 83121#L956-1 assume !(1 == ~T8_E~0); 83922#L961-1 assume !(1 == ~E_1~0); 83660#L966-1 assume !(1 == ~E_2~0); 83435#L971-1 assume !(1 == ~E_3~0); 83436#L976-1 assume 1 == ~E_4~0;~E_4~0 := 2; 83883#L981-1 assume !(1 == ~E_5~0); 83619#L986-1 assume !(1 == ~E_6~0); 83540#L991-1 assume !(1 == ~E_7~0); 83249#L996-1 assume !(1 == ~E_8~0); 83250#L1262-1 [2018-11-22 21:21:36,684 INFO L796 eck$LassoCheckResult]: Loop: 83250#L1262-1 assume !false; 90761#L1263 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret0, eval_#t~nondet1, eval_~tmp_ndt_1~0, eval_#t~nondet2, eval_~tmp_ndt_2~0, eval_#t~nondet3, eval_~tmp_ndt_3~0, eval_#t~nondet4, eval_~tmp_ndt_4~0, eval_#t~nondet5, eval_~tmp_ndt_5~0, eval_#t~nondet6, eval_~tmp_ndt_6~0, eval_#t~nondet7, eval_~tmp_ndt_7~0, eval_#t~nondet8, eval_~tmp_ndt_8~0, eval_#t~nondet9, eval_~tmp_ndt_9~0, eval_~tmp~0;havoc eval_~tmp~0; 90760#L803 assume !false; 90759#L682 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~9;havoc exists_runnable_thread_~__retres1~9; 90754#L624 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9 := 1; 90749#L671 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~9; 90748#L672 eval_#t~ret0 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret0;havoc eval_#t~ret0; 90746#L686 assume !(0 != eval_~tmp~0); 90745#L818 start_simulation_~kernel_st~0 := 2; 90744#L564-1 start_simulation_~kernel_st~0 := 3; 90742#L828-2 assume !(0 == ~M_E~0); 90740#L828-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 90738#L833-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 90736#L838-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 90734#L843-3 assume !(0 == ~T4_E~0); 90732#L848-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 90730#L853-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 90728#L858-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 90726#L863-3 assume !(0 == ~T8_E~0); 90724#L868-3 assume 0 == ~E_1~0;~E_1~0 := 1; 90722#L873-3 assume 0 == ~E_2~0;~E_2~0 := 1; 90720#L878-3 assume 0 == ~E_3~0;~E_3~0 := 1; 90718#L883-3 assume !(0 == ~E_4~0); 90716#L888-3 assume 0 == ~E_5~0;~E_5~0 := 1; 90714#L893-3 assume 0 == ~E_6~0;~E_6~0 := 1; 90712#L898-3 assume 0 == ~E_7~0;~E_7~0 := 1; 90710#L903-3 assume !(0 == ~E_8~0); 90708#L908-3 havoc activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 90706#L392-27 assume !(1 == ~m_pc~0); 90703#L392-29 is_master_triggered_~__retres1~0 := 0; 90700#L403-9 is_master_triggered_#res := is_master_triggered_~__retres1~0; 90698#L404-9 activate_threads_#t~ret10 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 90696#L1025-27 assume !(0 != activate_threads_~tmp~1); 90694#L1025-29 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 90692#L411-27 assume 1 == ~t1_pc~0; 90689#L412-9 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 90686#L422-9 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 90684#L423-9 activate_threads_#t~ret11 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 90682#L1033-27 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 90680#L1033-29 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 90678#L430-27 assume !(1 == ~t2_pc~0); 90676#L430-29 is_transmit2_triggered_~__retres1~2 := 0; 90674#L441-9 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 90672#L442-9 activate_threads_#t~ret12 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 90670#L1041-27 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 90668#L1041-29 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 90666#L449-27 assume 1 == ~t3_pc~0; 90663#L450-9 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 90660#L460-9 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 90658#L461-9 activate_threads_#t~ret13 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 90656#L1049-27 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 90654#L1049-29 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 90652#L468-27 assume !(1 == ~t4_pc~0); 90650#L468-29 is_transmit4_triggered_~__retres1~4 := 0; 90648#L479-9 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 90646#L480-9 activate_threads_#t~ret14 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 90644#L1057-27 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 90642#L1057-29 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 90640#L487-27 assume 1 == ~t5_pc~0; 90637#L488-9 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 90634#L498-9 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 90632#L499-9 activate_threads_#t~ret15 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 90630#L1065-27 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 90628#L1065-29 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 90626#L506-27 assume !(1 == ~t6_pc~0); 90624#L506-29 is_transmit6_triggered_~__retres1~6 := 0; 90622#L517-9 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 90620#L518-9 activate_threads_#t~ret16 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 90618#L1073-27 assume 0 != activate_threads_~tmp___5~0;~t6_st~0 := 0; 90616#L1073-29 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 90614#L525-27 assume !(1 == ~t7_pc~0); 90612#L525-29 is_transmit7_triggered_~__retres1~7 := 0; 90610#L536-9 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 90608#L537-9 activate_threads_#t~ret17 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 90606#L1081-27 assume 0 != activate_threads_~tmp___6~0;~t7_st~0 := 0; 90604#L1081-29 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 90602#L544-27 assume !(1 == ~t8_pc~0); 90598#L544-29 is_transmit8_triggered_~__retres1~8 := 0; 90596#L555-9 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 90594#L556-9 activate_threads_#t~ret18 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 90592#L1089-27 assume 0 != activate_threads_~tmp___7~0;~t8_st~0 := 0; 90590#L1089-29 assume !(1 == ~M_E~0); 90588#L921-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 90586#L926-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 90584#L931-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 90582#L936-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 90580#L941-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 90578#L946-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 90576#L951-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 90574#L956-3 assume !(1 == ~T8_E~0); 90572#L961-3 assume 1 == ~E_1~0;~E_1~0 := 2; 90570#L966-3 assume 1 == ~E_2~0;~E_2~0 := 2; 90568#L971-3 assume 1 == ~E_3~0;~E_3~0 := 2; 90566#L976-3 assume 1 == ~E_4~0;~E_4~0 := 2; 90564#L981-3 assume 1 == ~E_5~0;~E_5~0 := 2; 90562#L986-3 assume 1 == ~E_6~0;~E_6~0 := 2; 90560#L991-3 assume 1 == ~E_7~0;~E_7~0 := 2; 90558#L996-3 assume !(1 == ~E_8~0); 90556#L1001-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~9;havoc exists_runnable_thread_~__retres1~9; 90549#L624-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9 := 1; 90540#L671-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~9; 90538#L672-1 start_simulation_#t~ret20 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret20;havoc start_simulation_#t~ret20; 90535#L1281 assume !(0 == start_simulation_~tmp~3); 90536#L1281-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret19, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~9;havoc exists_runnable_thread_~__retres1~9; 90854#L624-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9 := 1; 90846#L671-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~9; 90844#L672-2 stop_simulation_#t~ret19 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret19;havoc stop_simulation_#t~ret19; 90842#L1236 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 90840#L1243 stop_simulation_#res := stop_simulation_~__retres2~0; 90838#L1244 start_simulation_#t~ret21 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret21;havoc start_simulation_#t~ret21; 90836#L1294 assume !(0 != start_simulation_~tmp___0~1); 83250#L1262-1 [2018-11-22 21:21:36,684 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-22 21:21:36,684 INFO L82 PathProgramCache]: Analyzing trace with hash -1491583427, now seen corresponding path program 1 times [2018-11-22 21:21:36,684 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-22 21:21:36,684 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-22 21:21:36,685 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-22 21:21:36,685 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-22 21:21:36,685 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-22 21:21:36,690 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-22 21:21:36,722 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-22 21:21:36,722 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-22 21:21:36,722 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2018-11-22 21:21:36,723 INFO L799 eck$LassoCheckResult]: stem already infeasible [2018-11-22 21:21:36,723 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-22 21:21:36,723 INFO L82 PathProgramCache]: Analyzing trace with hash 2078839701, now seen corresponding path program 1 times [2018-11-22 21:21:36,723 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-22 21:21:36,723 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-22 21:21:36,728 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-22 21:21:36,728 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-22 21:21:36,728 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-22 21:21:36,733 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-22 21:21:36,773 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-22 21:21:36,774 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-22 21:21:36,774 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-11-22 21:21:36,774 INFO L811 eck$LassoCheckResult]: loop already infeasible [2018-11-22 21:21:36,774 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-22 21:21:36,774 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-22 21:21:36,775 INFO L87 Difference]: Start difference. First operand 19721 states and 28423 transitions. cyclomatic complexity: 8718 Second operand 3 states. [2018-11-22 21:21:36,833 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-22 21:21:36,833 INFO L93 Difference]: Finished difference Result 19721 states and 28325 transitions. [2018-11-22 21:21:36,834 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-22 21:21:36,834 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 19721 states and 28325 transitions. [2018-11-22 21:21:36,894 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 19488 [2018-11-22 21:21:36,956 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 19721 states to 19721 states and 28325 transitions. [2018-11-22 21:21:36,956 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 19721 [2018-11-22 21:21:36,968 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 19721 [2018-11-22 21:21:36,968 INFO L73 IsDeterministic]: Start isDeterministic. Operand 19721 states and 28325 transitions. [2018-11-22 21:21:36,980 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-22 21:21:36,981 INFO L705 BuchiCegarLoop]: Abstraction has 19721 states and 28325 transitions. [2018-11-22 21:21:36,991 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 19721 states and 28325 transitions. [2018-11-22 21:21:37,193 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 19721 to 19721. [2018-11-22 21:21:37,193 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 19721 states. [2018-11-22 21:21:37,212 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 19721 states to 19721 states and 28325 transitions. [2018-11-22 21:21:37,213 INFO L728 BuchiCegarLoop]: Abstraction has 19721 states and 28325 transitions. [2018-11-22 21:21:37,213 INFO L608 BuchiCegarLoop]: Abstraction has 19721 states and 28325 transitions. [2018-11-22 21:21:37,213 INFO L442 BuchiCegarLoop]: ======== Iteration 17============ [2018-11-22 21:21:37,213 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 19721 states and 28325 transitions. [2018-11-22 21:21:37,250 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 19488 [2018-11-22 21:21:37,250 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-22 21:21:37,250 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-22 21:21:37,251 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-22 21:21:37,252 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-22 21:21:37,252 INFO L794 eck$LassoCheckResult]: Stem: 123006#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2; 122899#L-1 havoc main_#res;havoc main_~__retres1~10;havoc main_~__retres1~10;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 122900#L1225 havoc start_simulation_#t~ret20, start_simulation_#t~ret21, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 123371#L564 assume 1 == ~m_i~0;~m_st~0 := 0; 122933#L571-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 122644#L576-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 122645#L581-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 123379#L586-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 123132#L591-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 122744#L596-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 122745#L601-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 123365#L606-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 123266#L611-1 assume !(0 == ~M_E~0); 123267#L828-1 assume !(0 == ~T1_E~0); 123029#L833-1 assume !(0 == ~T2_E~0); 122759#L838-1 assume !(0 == ~T3_E~0); 122760#L843-1 assume !(0 == ~T4_E~0); 123463#L848-1 assume !(0 == ~T5_E~0); 123275#L853-1 assume !(0 == ~T6_E~0); 123013#L858-1 assume !(0 == ~T7_E~0); 122561#L863-1 assume !(0 == ~T8_E~0); 122562#L868-1 assume !(0 == ~E_1~0); 123229#L873-1 assume !(0 == ~E_2~0); 123099#L878-1 assume !(0 == ~E_3~0); 122869#L883-1 assume !(0 == ~E_4~0); 122870#L888-1 assume !(0 == ~E_5~0); 123334#L893-1 assume !(0 == ~E_6~0); 123069#L898-1 assume !(0 == ~E_7~0); 122994#L903-1 assume !(0 == ~E_8~0); 122705#L908-1 havoc activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 122706#L392 assume !(1 == ~m_pc~0); 123051#L392-2 is_master_triggered_~__retres1~0 := 0; 123055#L403 is_master_triggered_#res := is_master_triggered_~__retres1~0; 123511#L404 activate_threads_#t~ret10 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 123344#L1025 assume !(0 != activate_threads_~tmp~1); 123345#L1025-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 123215#L411 assume !(1 == ~t1_pc~0); 123182#L411-2 is_transmit1_triggered_~__retres1~1 := 0; 122626#L422 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 122627#L423 activate_threads_#t~ret11 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 122724#L1033 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 122942#L1033-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 122943#L430 assume !(1 == ~t2_pc~0); 123355#L430-2 is_transmit2_triggered_~__retres1~2 := 0; 122792#L441 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 122746#L442 activate_threads_#t~ret12 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 122747#L1041 assume !(0 != activate_threads_~tmp___1~0); 123546#L1041-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 123547#L449 assume !(1 == ~t3_pc~0); 123426#L449-2 is_transmit3_triggered_~__retres1~3 := 0; 123080#L460 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 122917#L461 activate_threads_#t~ret13 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 122918#L1049 assume !(0 != activate_threads_~tmp___2~0); 123369#L1049-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 122662#L468 assume !(1 == ~t4_pc~0); 122663#L468-2 is_transmit4_triggered_~__retres1~4 := 0; 122670#L479 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 123062#L480 activate_threads_#t~ret14 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 123001#L1057 assume !(0 != activate_threads_~tmp___3~0); 123002#L1057-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 122855#L487 assume !(1 == ~t5_pc~0); 122622#L487-2 is_transmit5_triggered_~__retres1~5 := 0; 122621#L498 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 123202#L499 activate_threads_#t~ret15 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 123203#L1065 assume !(0 != activate_threads_~tmp___4~0); 123563#L1065-2 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 123012#L506 assume !(1 == ~t6_pc~0); 123009#L506-2 is_transmit6_triggered_~__retres1~6 := 0; 123010#L517 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 123367#L518 activate_threads_#t~ret16 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 123288#L1073 assume !(0 != activate_threads_~tmp___5~0); 123289#L1073-2 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 123133#L525 assume !(1 == ~t7_pc~0); 123134#L525-2 is_transmit7_triggered_~__retres1~7 := 0; 123135#L536 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 123548#L537 activate_threads_#t~ret17 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 122875#L1081 assume !(0 != activate_threads_~tmp___6~0); 122876#L1081-2 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 122877#L544 assume !(1 == ~t8_pc~0); 123150#L544-2 is_transmit8_triggered_~__retres1~8 := 0; 122555#L555 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 122556#L556 activate_threads_#t~ret18 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 122694#L1089 assume 0 != activate_threads_~tmp___7~0;~t8_st~0 := 0; 123408#L1089-2 assume !(1 == ~M_E~0); 123023#L921-1 assume !(1 == ~T1_E~0); 122755#L926-1 assume !(1 == ~T2_E~0); 122756#L931-1 assume !(1 == ~T3_E~0); 123461#L936-1 assume !(1 == ~T4_E~0); 123283#L941-1 assume !(1 == ~T5_E~0); 123019#L946-1 assume !(1 == ~T6_E~0); 122571#L951-1 assume !(1 == ~T7_E~0); 122572#L956-1 assume !(1 == ~T8_E~0); 123370#L961-1 assume !(1 == ~E_1~0); 123107#L966-1 assume !(1 == ~E_2~0); 122881#L971-1 assume !(1 == ~E_3~0); 122882#L976-1 assume 1 == ~E_4~0;~E_4~0 := 2; 123329#L981-1 assume !(1 == ~E_5~0); 123067#L986-1 assume !(1 == ~E_6~0); 122987#L991-1 assume !(1 == ~E_7~0); 122700#L996-1 assume !(1 == ~E_8~0); 122701#L1262-1 [2018-11-22 21:21:37,252 INFO L796 eck$LassoCheckResult]: Loop: 122701#L1262-1 assume !false; 131591#L1263 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret0, eval_#t~nondet1, eval_~tmp_ndt_1~0, eval_#t~nondet2, eval_~tmp_ndt_2~0, eval_#t~nondet3, eval_~tmp_ndt_3~0, eval_#t~nondet4, eval_~tmp_ndt_4~0, eval_#t~nondet5, eval_~tmp_ndt_5~0, eval_#t~nondet6, eval_~tmp_ndt_6~0, eval_#t~nondet7, eval_~tmp_ndt_7~0, eval_#t~nondet8, eval_~tmp_ndt_8~0, eval_#t~nondet9, eval_~tmp_ndt_9~0, eval_~tmp~0;havoc eval_~tmp~0; 131589#L803 assume !false; 131587#L682 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~9;havoc exists_runnable_thread_~__retres1~9; 131569#L624 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9 := 1; 131564#L671 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~9; 131563#L672 eval_#t~ret0 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret0;havoc eval_#t~ret0; 131558#L686 assume !(0 != eval_~tmp~0); 131559#L818 start_simulation_~kernel_st~0 := 2; 133001#L564-1 start_simulation_~kernel_st~0 := 3; 133000#L828-2 assume !(0 == ~M_E~0); 132999#L828-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 132998#L833-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 132997#L838-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 132996#L843-3 assume !(0 == ~T4_E~0); 132995#L848-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 132994#L853-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 132991#L858-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 132989#L863-3 assume !(0 == ~T8_E~0); 132987#L868-3 assume 0 == ~E_1~0;~E_1~0 := 1; 132985#L873-3 assume 0 == ~E_2~0;~E_2~0 := 1; 132983#L878-3 assume 0 == ~E_3~0;~E_3~0 := 1; 132981#L883-3 assume !(0 == ~E_4~0); 132979#L888-3 assume 0 == ~E_5~0;~E_5~0 := 1; 132976#L893-3 assume 0 == ~E_6~0;~E_6~0 := 1; 132974#L898-3 assume 0 == ~E_7~0;~E_7~0 := 1; 132972#L903-3 assume !(0 == ~E_8~0); 132970#L908-3 havoc activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 132968#L392-27 assume !(1 == ~m_pc~0); 132965#L392-29 is_master_triggered_~__retres1~0 := 0; 132962#L403-9 is_master_triggered_#res := is_master_triggered_~__retres1~0; 132960#L404-9 activate_threads_#t~ret10 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 132958#L1025-27 assume !(0 != activate_threads_~tmp~1); 132956#L1025-29 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 132954#L411-27 assume 1 == ~t1_pc~0; 132951#L412-9 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 132948#L422-9 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 132946#L423-9 activate_threads_#t~ret11 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 132944#L1033-27 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 132942#L1033-29 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 132940#L430-27 assume !(1 == ~t2_pc~0); 132938#L430-29 is_transmit2_triggered_~__retres1~2 := 0; 132935#L441-9 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 132933#L442-9 activate_threads_#t~ret12 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 132931#L1041-27 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 132929#L1041-29 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 132927#L449-27 assume 1 == ~t3_pc~0; 132924#L450-9 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 132921#L460-9 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 132919#L461-9 activate_threads_#t~ret13 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 132917#L1049-27 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 132915#L1049-29 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 132913#L468-27 assume !(1 == ~t4_pc~0); 132911#L468-29 is_transmit4_triggered_~__retres1~4 := 0; 132908#L479-9 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 132906#L480-9 activate_threads_#t~ret14 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 132904#L1057-27 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 132902#L1057-29 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 132900#L487-27 assume !(1 == ~t5_pc~0); 132898#L487-29 is_transmit5_triggered_~__retres1~5 := 0; 132894#L498-9 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 132892#L499-9 activate_threads_#t~ret15 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 132890#L1065-27 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 132888#L1065-29 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 132886#L506-27 assume !(1 == ~t6_pc~0); 132883#L506-29 is_transmit6_triggered_~__retres1~6 := 0; 132881#L517-9 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 132879#L518-9 activate_threads_#t~ret16 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 132877#L1073-27 assume 0 != activate_threads_~tmp___5~0;~t6_st~0 := 0; 132875#L1073-29 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 132874#L525-27 assume !(1 == ~t7_pc~0); 132870#L525-29 is_transmit7_triggered_~__retres1~7 := 0; 132151#L536-9 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 132150#L537-9 activate_threads_#t~ret17 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 132149#L1081-27 assume 0 != activate_threads_~tmp___6~0;~t7_st~0 := 0; 132148#L1081-29 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 132147#L544-27 assume !(1 == ~t8_pc~0); 132144#L544-29 is_transmit8_triggered_~__retres1~8 := 0; 132142#L555-9 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 132139#L556-9 activate_threads_#t~ret18 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 132137#L1089-27 assume 0 != activate_threads_~tmp___7~0;~t8_st~0 := 0; 132132#L1089-29 assume !(1 == ~M_E~0); 132130#L921-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 132128#L926-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 132125#L931-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 132123#L936-3 assume !(1 == ~T4_E~0); 132003#L941-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 132002#L946-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 132001#L951-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 132000#L956-3 assume !(1 == ~T8_E~0); 131998#L961-3 assume 1 == ~E_1~0;~E_1~0 := 2; 131996#L966-3 assume 1 == ~E_2~0;~E_2~0 := 2; 131994#L971-3 assume 1 == ~E_3~0;~E_3~0 := 2; 131991#L976-3 assume 1 == ~E_4~0;~E_4~0 := 2; 131989#L981-3 assume 1 == ~E_5~0;~E_5~0 := 2; 131987#L986-3 assume 1 == ~E_6~0;~E_6~0 := 2; 131985#L991-3 assume 1 == ~E_7~0;~E_7~0 := 2; 131983#L996-3 assume !(1 == ~E_8~0); 131858#L1001-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~9;havoc exists_runnable_thread_~__retres1~9; 131772#L624-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9 := 1; 131764#L671-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~9; 131762#L672-1 start_simulation_#t~ret20 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret20;havoc start_simulation_#t~ret20; 131744#L1281 assume !(0 == start_simulation_~tmp~3); 131742#L1281-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret19, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~9;havoc exists_runnable_thread_~__retres1~9; 131726#L624-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9 := 1; 131718#L671-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~9; 131715#L672-2 stop_simulation_#t~ret19 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret19;havoc stop_simulation_#t~ret19; 131713#L1236 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 131711#L1243 stop_simulation_#res := stop_simulation_~__retres2~0; 131709#L1244 start_simulation_#t~ret21 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret21;havoc start_simulation_#t~ret21; 131707#L1294 assume !(0 != start_simulation_~tmp___0~1); 122701#L1262-1 [2018-11-22 21:21:37,252 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-22 21:21:37,253 INFO L82 PathProgramCache]: Analyzing trace with hash -2078389441, now seen corresponding path program 1 times [2018-11-22 21:21:37,253 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-22 21:21:37,253 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-22 21:21:37,253 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-22 21:21:37,254 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-22 21:21:37,254 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-22 21:21:37,259 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-22 21:21:37,288 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-22 21:21:37,288 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-22 21:21:37,288 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2018-11-22 21:21:37,288 INFO L799 eck$LassoCheckResult]: stem already infeasible [2018-11-22 21:21:37,289 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-22 21:21:37,289 INFO L82 PathProgramCache]: Analyzing trace with hash 1867100820, now seen corresponding path program 1 times [2018-11-22 21:21:37,289 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-22 21:21:37,289 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-22 21:21:37,289 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-22 21:21:37,290 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-22 21:21:37,290 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-22 21:21:37,295 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-22 21:21:37,320 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-22 21:21:37,321 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-22 21:21:37,321 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-11-22 21:21:37,321 INFO L811 eck$LassoCheckResult]: loop already infeasible [2018-11-22 21:21:37,321 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-22 21:21:37,321 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-22 21:21:37,321 INFO L87 Difference]: Start difference. First operand 19721 states and 28325 transitions. cyclomatic complexity: 8620 Second operand 3 states. [2018-11-22 21:21:37,374 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-22 21:21:37,374 INFO L93 Difference]: Finished difference Result 19721 states and 28115 transitions. [2018-11-22 21:21:37,376 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-22 21:21:37,376 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 19721 states and 28115 transitions. [2018-11-22 21:21:37,422 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 19488 [2018-11-22 21:21:37,467 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 19721 states to 19721 states and 28115 transitions. [2018-11-22 21:21:37,467 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 19721 [2018-11-22 21:21:37,478 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 19721 [2018-11-22 21:21:37,479 INFO L73 IsDeterministic]: Start isDeterministic. Operand 19721 states and 28115 transitions. [2018-11-22 21:21:37,490 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-22 21:21:37,490 INFO L705 BuchiCegarLoop]: Abstraction has 19721 states and 28115 transitions. [2018-11-22 21:21:37,501 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 19721 states and 28115 transitions. [2018-11-22 21:21:37,612 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 19721 to 19721. [2018-11-22 21:21:37,612 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 19721 states. [2018-11-22 21:21:37,627 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 19721 states to 19721 states and 28115 transitions. [2018-11-22 21:21:37,627 INFO L728 BuchiCegarLoop]: Abstraction has 19721 states and 28115 transitions. [2018-11-22 21:21:37,627 INFO L608 BuchiCegarLoop]: Abstraction has 19721 states and 28115 transitions. [2018-11-22 21:21:37,627 INFO L442 BuchiCegarLoop]: ======== Iteration 18============ [2018-11-22 21:21:37,627 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 19721 states and 28115 transitions. [2018-11-22 21:21:37,659 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 19488 [2018-11-22 21:21:37,659 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-22 21:21:37,660 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-22 21:21:37,661 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-22 21:21:37,661 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-22 21:21:37,661 INFO L794 eck$LassoCheckResult]: Stem: 162450#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2; 162349#L-1 havoc main_#res;havoc main_~__retres1~10;havoc main_~__retres1~10;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 162350#L1225 havoc start_simulation_#t~ret20, start_simulation_#t~ret21, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 162820#L564 assume 1 == ~m_i~0;~m_st~0 := 0; 162383#L571-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 162095#L576-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 162096#L581-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 162823#L586-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 162576#L591-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 162194#L596-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 162195#L601-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 162813#L606-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 162715#L611-1 assume !(0 == ~M_E~0); 162716#L828-1 assume !(0 == ~T1_E~0); 162475#L833-1 assume !(0 == ~T2_E~0); 162209#L838-1 assume !(0 == ~T3_E~0); 162210#L843-1 assume !(0 == ~T4_E~0); 162903#L848-1 assume !(0 == ~T5_E~0); 162724#L853-1 assume !(0 == ~T6_E~0); 162457#L858-1 assume !(0 == ~T7_E~0); 162012#L863-1 assume !(0 == ~T8_E~0); 162013#L868-1 assume !(0 == ~E_1~0); 162675#L873-1 assume !(0 == ~E_2~0); 162548#L878-1 assume !(0 == ~E_3~0); 162318#L883-1 assume !(0 == ~E_4~0); 162319#L888-1 assume !(0 == ~E_5~0); 162782#L893-1 assume !(0 == ~E_6~0); 162517#L898-1 assume !(0 == ~E_7~0); 162440#L903-1 assume !(0 == ~E_8~0); 162156#L908-1 havoc activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 162157#L392 assume !(1 == ~m_pc~0); 162499#L392-2 is_master_triggered_~__retres1~0 := 0; 162502#L403 is_master_triggered_#res := is_master_triggered_~__retres1~0; 162950#L404 activate_threads_#t~ret10 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 162790#L1025 assume !(0 != activate_threads_~tmp~1); 162791#L1025-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 162661#L411 assume !(1 == ~t1_pc~0); 162628#L411-2 is_transmit1_triggered_~__retres1~1 := 0; 162077#L422 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 162078#L423 activate_threads_#t~ret11 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 162175#L1033 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 162391#L1033-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 162392#L430 assume !(1 == ~t2_pc~0); 162802#L430-2 is_transmit2_triggered_~__retres1~2 := 0; 162241#L441 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 162196#L442 activate_threads_#t~ret12 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 162197#L1041 assume !(0 != activate_threads_~tmp___1~0); 162977#L1041-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 162978#L449 assume !(1 == ~t3_pc~0); 162867#L449-2 is_transmit3_triggered_~__retres1~3 := 0; 162528#L460 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 162367#L461 activate_threads_#t~ret13 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 162368#L1049 assume !(0 != activate_threads_~tmp___2~0); 162817#L1049-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 162113#L468 assume !(1 == ~t4_pc~0); 162114#L468-2 is_transmit4_triggered_~__retres1~4 := 0; 162121#L479 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 162508#L480 activate_threads_#t~ret14 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 162445#L1057 assume !(0 != activate_threads_~tmp___3~0); 162446#L1057-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 162303#L487 assume !(1 == ~t5_pc~0); 162073#L487-2 is_transmit5_triggered_~__retres1~5 := 0; 162072#L498 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 162648#L499 activate_threads_#t~ret15 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 162649#L1065 assume !(0 != activate_threads_~tmp___4~0); 162992#L1065-2 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 162456#L506 assume !(1 == ~t6_pc~0); 162453#L506-2 is_transmit6_triggered_~__retres1~6 := 0; 162454#L517 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 162815#L518 activate_threads_#t~ret16 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 162739#L1073 assume !(0 != activate_threads_~tmp___5~0); 162740#L1073-2 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 162579#L525 assume !(1 == ~t7_pc~0); 162580#L525-2 is_transmit7_triggered_~__retres1~7 := 0; 162581#L536 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 162979#L537 activate_threads_#t~ret17 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 162324#L1081 assume !(0 != activate_threads_~tmp___6~0); 162325#L1081-2 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 162326#L544 assume !(1 == ~t8_pc~0); 162598#L544-2 is_transmit8_triggered_~__retres1~8 := 0; 162006#L555 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 162007#L556 activate_threads_#t~ret18 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 162145#L1089 assume 0 != activate_threads_~tmp___7~0;~t8_st~0 := 0; 162850#L1089-2 assume !(1 == ~M_E~0); 162468#L921-1 assume !(1 == ~T1_E~0); 162205#L926-1 assume !(1 == ~T2_E~0); 162206#L931-1 assume !(1 == ~T3_E~0); 162901#L936-1 assume !(1 == ~T4_E~0); 162732#L941-1 assume !(1 == ~T5_E~0); 162464#L946-1 assume !(1 == ~T6_E~0); 162022#L951-1 assume !(1 == ~T7_E~0); 162023#L956-1 assume !(1 == ~T8_E~0); 162819#L961-1 assume !(1 == ~E_1~0); 162556#L966-1 assume !(1 == ~E_2~0); 162330#L971-1 assume !(1 == ~E_3~0); 162331#L976-1 assume !(1 == ~E_4~0); 162777#L981-1 assume !(1 == ~E_5~0); 162515#L986-1 assume !(1 == ~E_6~0); 162435#L991-1 assume !(1 == ~E_7~0); 162151#L996-1 assume !(1 == ~E_8~0); 162152#L1262-1 [2018-11-22 21:21:37,661 INFO L796 eck$LassoCheckResult]: Loop: 162152#L1262-1 assume !false; 169490#L1263 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret0, eval_#t~nondet1, eval_~tmp_ndt_1~0, eval_#t~nondet2, eval_~tmp_ndt_2~0, eval_#t~nondet3, eval_~tmp_ndt_3~0, eval_#t~nondet4, eval_~tmp_ndt_4~0, eval_#t~nondet5, eval_~tmp_ndt_5~0, eval_#t~nondet6, eval_~tmp_ndt_6~0, eval_#t~nondet7, eval_~tmp_ndt_7~0, eval_#t~nondet8, eval_~tmp_ndt_8~0, eval_#t~nondet9, eval_~tmp_ndt_9~0, eval_~tmp~0;havoc eval_~tmp~0; 169488#L803 assume !false; 169486#L682 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~9;havoc exists_runnable_thread_~__retres1~9; 169472#L624 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9 := 1; 169467#L671 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~9; 169466#L672 eval_#t~ret0 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret0;havoc eval_#t~ret0; 169464#L686 assume !(0 != eval_~tmp~0); 169465#L818 start_simulation_~kernel_st~0 := 2; 170682#L564-1 start_simulation_~kernel_st~0 := 3; 170680#L828-2 assume !(0 == ~M_E~0); 170678#L828-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 170676#L833-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 170675#L838-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 170674#L843-3 assume !(0 == ~T4_E~0); 170673#L848-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 170672#L853-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 170671#L858-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 170661#L863-3 assume !(0 == ~T8_E~0); 170659#L868-3 assume 0 == ~E_1~0;~E_1~0 := 1; 170657#L873-3 assume 0 == ~E_2~0;~E_2~0 := 1; 170655#L878-3 assume 0 == ~E_3~0;~E_3~0 := 1; 170653#L883-3 assume !(0 == ~E_4~0); 170651#L888-3 assume 0 == ~E_5~0;~E_5~0 := 1; 170649#L893-3 assume 0 == ~E_6~0;~E_6~0 := 1; 170647#L898-3 assume 0 == ~E_7~0;~E_7~0 := 1; 170646#L903-3 assume !(0 == ~E_8~0); 170645#L908-3 havoc activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 170644#L392-27 assume !(1 == ~m_pc~0); 170642#L392-29 is_master_triggered_~__retres1~0 := 0; 170639#L403-9 is_master_triggered_#res := is_master_triggered_~__retres1~0; 170638#L404-9 activate_threads_#t~ret10 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 170637#L1025-27 assume !(0 != activate_threads_~tmp~1); 170635#L1025-29 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 170633#L411-27 assume 1 == ~t1_pc~0; 170626#L412-9 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 170624#L422-9 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 170622#L423-9 activate_threads_#t~ret11 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 170621#L1033-27 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 170620#L1033-29 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 170619#L430-27 assume !(1 == ~t2_pc~0); 170618#L430-29 is_transmit2_triggered_~__retres1~2 := 0; 170617#L441-9 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 170616#L442-9 activate_threads_#t~ret12 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 170606#L1041-27 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 170604#L1041-29 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 170602#L449-27 assume 1 == ~t3_pc~0; 170598#L450-9 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 170596#L460-9 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 170594#L461-9 activate_threads_#t~ret13 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 170592#L1049-27 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 170590#L1049-29 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 170588#L468-27 assume !(1 == ~t4_pc~0); 170586#L468-29 is_transmit4_triggered_~__retres1~4 := 0; 170584#L479-9 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 170582#L480-9 activate_threads_#t~ret14 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 170580#L1057-27 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 170578#L1057-29 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 170576#L487-27 assume !(1 == ~t5_pc~0); 170574#L487-29 is_transmit5_triggered_~__retres1~5 := 0; 170571#L498-9 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 170569#L499-9 activate_threads_#t~ret15 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 170567#L1065-27 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 170565#L1065-29 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 170563#L506-27 assume !(1 == ~t6_pc~0); 170561#L506-29 is_transmit6_triggered_~__retres1~6 := 0; 170559#L517-9 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 170557#L518-9 activate_threads_#t~ret16 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 170554#L1073-27 assume 0 != activate_threads_~tmp___5~0;~t6_st~0 := 0; 170552#L1073-29 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 170550#L525-27 assume !(1 == ~t7_pc~0); 170548#L525-29 is_transmit7_triggered_~__retres1~7 := 0; 170546#L536-9 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 170544#L537-9 activate_threads_#t~ret17 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 170542#L1081-27 assume 0 != activate_threads_~tmp___6~0;~t7_st~0 := 0; 170539#L1081-29 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 170537#L544-27 assume !(1 == ~t8_pc~0); 170534#L544-29 is_transmit8_triggered_~__retres1~8 := 0; 170532#L555-9 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 170530#L556-9 activate_threads_#t~ret18 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 170528#L1089-27 assume 0 != activate_threads_~tmp___7~0;~t8_st~0 := 0; 169744#L1089-29 assume !(1 == ~M_E~0); 169741#L921-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 169739#L926-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 169737#L931-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 169735#L936-3 assume !(1 == ~T4_E~0); 169733#L941-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 169731#L946-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 169729#L951-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 169727#L956-3 assume !(1 == ~T8_E~0); 169725#L961-3 assume 1 == ~E_1~0;~E_1~0 := 2; 169723#L966-3 assume 1 == ~E_2~0;~E_2~0 := 2; 169721#L971-3 assume 1 == ~E_3~0;~E_3~0 := 2; 169719#L976-3 assume !(1 == ~E_4~0); 169717#L981-3 assume 1 == ~E_5~0;~E_5~0 := 2; 169715#L986-3 assume 1 == ~E_6~0;~E_6~0 := 2; 169713#L991-3 assume 1 == ~E_7~0;~E_7~0 := 2; 169711#L996-3 assume !(1 == ~E_8~0); 169709#L1001-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~9;havoc exists_runnable_thread_~__retres1~9; 169700#L624-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9 := 1; 169691#L671-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~9; 169689#L672-1 start_simulation_#t~ret20 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret20;havoc start_simulation_#t~ret20; 169660#L1281 assume !(0 == start_simulation_~tmp~3); 169658#L1281-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret19, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~9;havoc exists_runnable_thread_~__retres1~9; 169648#L624-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9 := 1; 169640#L671-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~9; 169638#L672-2 stop_simulation_#t~ret19 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret19;havoc stop_simulation_#t~ret19; 169635#L1236 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 169633#L1243 stop_simulation_#res := stop_simulation_~__retres2~0; 169631#L1244 start_simulation_#t~ret21 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret21;havoc start_simulation_#t~ret21; 169629#L1294 assume !(0 != start_simulation_~tmp___0~1); 162152#L1262-1 [2018-11-22 21:21:37,661 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-22 21:21:37,661 INFO L82 PathProgramCache]: Analyzing trace with hash -2076542399, now seen corresponding path program 1 times [2018-11-22 21:21:37,661 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-22 21:21:37,661 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-22 21:21:37,662 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-22 21:21:37,662 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-22 21:21:37,662 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-22 21:21:37,669 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-22 21:21:37,752 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-22 21:21:37,752 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-22 21:21:37,752 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-11-22 21:21:37,752 INFO L799 eck$LassoCheckResult]: stem already infeasible [2018-11-22 21:21:37,752 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-22 21:21:37,752 INFO L82 PathProgramCache]: Analyzing trace with hash -127043886, now seen corresponding path program 1 times [2018-11-22 21:21:37,753 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-22 21:21:37,753 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-22 21:21:37,753 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-22 21:21:37,753 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-22 21:21:37,753 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-22 21:21:37,758 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-22 21:21:37,793 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-22 21:21:37,794 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-22 21:21:37,794 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-11-22 21:21:37,794 INFO L811 eck$LassoCheckResult]: loop already infeasible [2018-11-22 21:21:37,794 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-11-22 21:21:37,794 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-11-22 21:21:37,794 INFO L87 Difference]: Start difference. First operand 19721 states and 28115 transitions. cyclomatic complexity: 8410 Second operand 5 states. [2018-11-22 21:21:38,392 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-22 21:21:38,392 INFO L93 Difference]: Finished difference Result 55240 states and 78338 transitions. [2018-11-22 21:21:38,394 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2018-11-22 21:21:38,395 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 55240 states and 78338 transitions. [2018-11-22 21:21:38,573 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 54624 [2018-11-22 21:21:38,691 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 55240 states to 55240 states and 78338 transitions. [2018-11-22 21:21:38,691 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 55240 [2018-11-22 21:21:38,724 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 55240 [2018-11-22 21:21:38,724 INFO L73 IsDeterministic]: Start isDeterministic. Operand 55240 states and 78338 transitions. [2018-11-22 21:21:38,756 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-22 21:21:38,756 INFO L705 BuchiCegarLoop]: Abstraction has 55240 states and 78338 transitions. [2018-11-22 21:21:38,785 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 55240 states and 78338 transitions. [2018-11-22 21:21:38,992 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 55240 to 20444. [2018-11-22 21:21:38,992 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 20444 states. [2018-11-22 21:21:39,019 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 20444 states to 20444 states and 28838 transitions. [2018-11-22 21:21:39,019 INFO L728 BuchiCegarLoop]: Abstraction has 20444 states and 28838 transitions. [2018-11-22 21:21:39,019 INFO L608 BuchiCegarLoop]: Abstraction has 20444 states and 28838 transitions. [2018-11-22 21:21:39,019 INFO L442 BuchiCegarLoop]: ======== Iteration 19============ [2018-11-22 21:21:39,020 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 20444 states and 28838 transitions. [2018-11-22 21:21:39,071 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 20208 [2018-11-22 21:21:39,072 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-22 21:21:39,072 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-22 21:21:39,073 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-22 21:21:39,073 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-22 21:21:39,073 INFO L794 eck$LassoCheckResult]: Stem: 237441#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2; 237333#L-1 havoc main_#res;havoc main_~__retres1~10;havoc main_~__retres1~10;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 237334#L1225 havoc start_simulation_#t~ret20, start_simulation_#t~ret21, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 237835#L564 assume 1 == ~m_i~0;~m_st~0 := 0; 237370#L571-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 237072#L576-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 237073#L581-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 237838#L586-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 237569#L591-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 237179#L596-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 237180#L601-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 237829#L606-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 237714#L611-1 assume !(0 == ~M_E~0); 237715#L828-1 assume !(0 == ~T1_E~0); 237467#L833-1 assume !(0 == ~T2_E~0); 237194#L838-1 assume !(0 == ~T3_E~0); 237195#L843-1 assume !(0 == ~T4_E~0); 237922#L848-1 assume !(0 == ~T5_E~0); 237723#L853-1 assume !(0 == ~T6_E~0); 237451#L858-1 assume !(0 == ~T7_E~0); 236988#L863-1 assume !(0 == ~T8_E~0); 236989#L868-1 assume !(0 == ~E_1~0); 237677#L873-1 assume !(0 == ~E_2~0); 237537#L878-1 assume !(0 == ~E_3~0); 237302#L883-1 assume !(0 == ~E_4~0); 237303#L888-1 assume !(0 == ~E_5~0); 237799#L893-1 assume !(0 == ~E_6~0); 237508#L898-1 assume !(0 == ~E_7~0); 237430#L903-1 assume !(0 == ~E_8~0); 237133#L908-1 havoc activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 237134#L392 assume !(1 == ~m_pc~0); 237491#L392-2 is_master_triggered_~__retres1~0 := 0; 237495#L403 is_master_triggered_#res := is_master_triggered_~__retres1~0; 237961#L404 activate_threads_#t~ret10 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 237809#L1025 assume !(0 != activate_threads_~tmp~1); 237810#L1025-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 237663#L411 assume !(1 == ~t1_pc~0); 237627#L411-2 is_transmit1_triggered_~__retres1~1 := 0; 237053#L422 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 237054#L423 activate_threads_#t~ret11 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 237378#L1033 assume !(0 != activate_threads_~tmp___0~0); 237379#L1033-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 237380#L430 assume !(1 == ~t2_pc~0); 237820#L430-2 is_transmit2_triggered_~__retres1~2 := 0; 237226#L441 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 237181#L442 activate_threads_#t~ret12 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 237182#L1041 assume !(0 != activate_threads_~tmp___1~0); 237990#L1041-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 237991#L449 assume !(1 == ~t3_pc~0); 237887#L449-2 is_transmit3_triggered_~__retres1~3 := 0; 237519#L460 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 237353#L461 activate_threads_#t~ret13 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 237354#L1049 assume !(0 != activate_threads_~tmp___2~0); 237833#L1049-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 237091#L468 assume !(1 == ~t4_pc~0); 237092#L468-2 is_transmit4_triggered_~__retres1~4 := 0; 237099#L479 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 237501#L480 activate_threads_#t~ret14 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 237435#L1057 assume !(0 != activate_threads_~tmp___3~0); 237436#L1057-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 237288#L487 assume !(1 == ~t5_pc~0); 237049#L487-2 is_transmit5_triggered_~__retres1~5 := 0; 237048#L498 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 237651#L499 activate_threads_#t~ret15 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 237652#L1065 assume !(0 != activate_threads_~tmp___4~0); 238003#L1065-2 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 237450#L506 assume !(1 == ~t6_pc~0); 237445#L506-2 is_transmit6_triggered_~__retres1~6 := 0; 237446#L517 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 237831#L518 activate_threads_#t~ret16 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 237743#L1073 assume !(0 != activate_threads_~tmp___5~0); 237744#L1073-2 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 237572#L525 assume !(1 == ~t7_pc~0); 237573#L525-2 is_transmit7_triggered_~__retres1~7 := 0; 237574#L536 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 237992#L537 activate_threads_#t~ret17 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 237308#L1081 assume !(0 != activate_threads_~tmp___6~0); 237309#L1081-2 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 237310#L544 assume !(1 == ~t8_pc~0); 237591#L544-2 is_transmit8_triggered_~__retres1~8 := 0; 236982#L555 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 236983#L556 activate_threads_#t~ret18 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 237122#L1089 assume 0 != activate_threads_~tmp___7~0;~t8_st~0 := 0; 237871#L1089-2 assume !(1 == ~M_E~0); 237461#L921-1 assume !(1 == ~T1_E~0); 237190#L926-1 assume !(1 == ~T2_E~0); 237191#L931-1 assume !(1 == ~T3_E~0); 237920#L936-1 assume !(1 == ~T4_E~0); 237732#L941-1 assume !(1 == ~T5_E~0); 237457#L946-1 assume !(1 == ~T6_E~0); 236998#L951-1 assume !(1 == ~T7_E~0); 236999#L956-1 assume !(1 == ~T8_E~0); 237834#L961-1 assume !(1 == ~E_1~0); 237544#L966-1 assume !(1 == ~E_2~0); 237314#L971-1 assume !(1 == ~E_3~0); 237315#L976-1 assume !(1 == ~E_4~0); 237794#L981-1 assume !(1 == ~E_5~0); 237506#L986-1 assume !(1 == ~E_6~0); 237424#L991-1 assume !(1 == ~E_7~0); 237128#L996-1 assume !(1 == ~E_8~0); 237129#L1262-1 [2018-11-22 21:21:39,073 INFO L796 eck$LassoCheckResult]: Loop: 237129#L1262-1 assume !false; 247016#L1263 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret0, eval_#t~nondet1, eval_~tmp_ndt_1~0, eval_#t~nondet2, eval_~tmp_ndt_2~0, eval_#t~nondet3, eval_~tmp_ndt_3~0, eval_#t~nondet4, eval_~tmp_ndt_4~0, eval_#t~nondet5, eval_~tmp_ndt_5~0, eval_#t~nondet6, eval_~tmp_ndt_6~0, eval_#t~nondet7, eval_~tmp_ndt_7~0, eval_#t~nondet8, eval_~tmp_ndt_8~0, eval_#t~nondet9, eval_~tmp_ndt_9~0, eval_~tmp~0;havoc eval_~tmp~0; 246979#L803 assume !false; 246975#L682 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~9;havoc exists_runnable_thread_~__retres1~9; 246879#L624 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9 := 1; 246870#L671 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~9; 246865#L672 eval_#t~ret0 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret0;havoc eval_#t~ret0; 246859#L686 assume !(0 != eval_~tmp~0); 246860#L818 start_simulation_~kernel_st~0 := 2; 249430#L564-1 start_simulation_~kernel_st~0 := 3; 249426#L828-2 assume !(0 == ~M_E~0); 249423#L828-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 249420#L833-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 249417#L838-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 249414#L843-3 assume !(0 == ~T4_E~0); 249411#L848-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 249408#L853-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 249405#L858-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 249402#L863-3 assume !(0 == ~T8_E~0); 249399#L868-3 assume 0 == ~E_1~0;~E_1~0 := 1; 249395#L873-3 assume 0 == ~E_2~0;~E_2~0 := 1; 249392#L878-3 assume 0 == ~E_3~0;~E_3~0 := 1; 249388#L883-3 assume !(0 == ~E_4~0); 249385#L888-3 assume 0 == ~E_5~0;~E_5~0 := 1; 249382#L893-3 assume 0 == ~E_6~0;~E_6~0 := 1; 249378#L898-3 assume 0 == ~E_7~0;~E_7~0 := 1; 249375#L903-3 assume !(0 == ~E_8~0); 249372#L908-3 havoc activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 249371#L392-27 assume !(1 == ~m_pc~0); 249369#L392-29 is_master_triggered_~__retres1~0 := 0; 249368#L403-9 is_master_triggered_#res := is_master_triggered_~__retres1~0; 249367#L404-9 activate_threads_#t~ret10 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 249366#L1025-27 assume !(0 != activate_threads_~tmp~1); 249365#L1025-29 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 249364#L411-27 assume !(1 == ~t1_pc~0); 249363#L411-29 is_transmit1_triggered_~__retres1~1 := 0; 249361#L422-9 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 249359#L423-9 activate_threads_#t~ret11 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 249357#L1033-27 assume !(0 != activate_threads_~tmp___0~0); 249352#L1033-29 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 249349#L430-27 assume !(1 == ~t2_pc~0); 249344#L430-29 is_transmit2_triggered_~__retres1~2 := 0; 249341#L441-9 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 249333#L442-9 activate_threads_#t~ret12 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 249327#L1041-27 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 249314#L1041-29 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 249267#L449-27 assume !(1 == ~t3_pc~0); 249255#L449-29 is_transmit3_triggered_~__retres1~3 := 0; 249250#L460-9 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 249230#L461-9 activate_threads_#t~ret13 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 249225#L1049-27 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 249221#L1049-29 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 249217#L468-27 assume !(1 == ~t4_pc~0); 249212#L468-29 is_transmit4_triggered_~__retres1~4 := 0; 249208#L479-9 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 249204#L480-9 activate_threads_#t~ret14 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 249200#L1057-27 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 249196#L1057-29 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 249191#L487-27 assume !(1 == ~t5_pc~0); 249186#L487-29 is_transmit5_triggered_~__retres1~5 := 0; 249181#L498-9 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 249177#L499-9 activate_threads_#t~ret15 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 249173#L1065-27 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 249169#L1065-29 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 249165#L506-27 assume !(1 == ~t6_pc~0); 249161#L506-29 is_transmit6_triggered_~__retres1~6 := 0; 249157#L517-9 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 249153#L518-9 activate_threads_#t~ret16 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 249133#L1073-27 assume 0 != activate_threads_~tmp___5~0;~t6_st~0 := 0; 249128#L1073-29 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 249106#L525-27 assume !(1 == ~t7_pc~0); 249100#L525-29 is_transmit7_triggered_~__retres1~7 := 0; 249094#L536-9 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 249088#L537-9 activate_threads_#t~ret17 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 249083#L1081-27 assume 0 != activate_threads_~tmp___6~0;~t7_st~0 := 0; 249076#L1081-29 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 247406#L544-27 assume !(1 == ~t8_pc~0); 247403#L544-29 is_transmit8_triggered_~__retres1~8 := 0; 247401#L555-9 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 247399#L556-9 activate_threads_#t~ret18 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 247397#L1089-27 assume 0 != activate_threads_~tmp___7~0;~t8_st~0 := 0; 247336#L1089-29 assume !(1 == ~M_E~0); 247334#L921-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 247332#L926-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 247330#L931-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 247328#L936-3 assume !(1 == ~T4_E~0); 247325#L941-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 247323#L946-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 247321#L951-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 247319#L956-3 assume !(1 == ~T8_E~0); 247317#L961-3 assume 1 == ~E_1~0;~E_1~0 := 2; 247314#L966-3 assume 1 == ~E_2~0;~E_2~0 := 2; 247312#L971-3 assume 1 == ~E_3~0;~E_3~0 := 2; 247310#L976-3 assume !(1 == ~E_4~0); 247308#L981-3 assume 1 == ~E_5~0;~E_5~0 := 2; 247306#L986-3 assume 1 == ~E_6~0;~E_6~0 := 2; 247304#L991-3 assume 1 == ~E_7~0;~E_7~0 := 2; 247302#L996-3 assume !(1 == ~E_8~0); 247300#L1001-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~9;havoc exists_runnable_thread_~__retres1~9; 247292#L624-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9 := 1; 247284#L671-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~9; 247282#L672-1 start_simulation_#t~ret20 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret20;havoc start_simulation_#t~ret20; 247278#L1281 assume !(0 == start_simulation_~tmp~3); 247277#L1281-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret19, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~9;havoc exists_runnable_thread_~__retres1~9; 247154#L624-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9 := 1; 247146#L671-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~9; 247056#L672-2 stop_simulation_#t~ret19 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret19;havoc stop_simulation_#t~ret19; 247046#L1236 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 247041#L1243 stop_simulation_#res := stop_simulation_~__retres2~0; 247036#L1244 start_simulation_#t~ret21 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret21;havoc start_simulation_#t~ret21; 247030#L1294 assume !(0 != start_simulation_~tmp___0~1); 237129#L1262-1 [2018-11-22 21:21:39,073 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-22 21:21:39,073 INFO L82 PathProgramCache]: Analyzing trace with hash -1874718465, now seen corresponding path program 1 times [2018-11-22 21:21:39,073 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-22 21:21:39,073 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-22 21:21:39,074 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-22 21:21:39,074 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-22 21:21:39,074 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-22 21:21:39,079 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-22 21:21:39,142 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-22 21:21:39,142 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-22 21:21:39,143 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-11-22 21:21:39,143 INFO L799 eck$LassoCheckResult]: stem already infeasible [2018-11-22 21:21:39,143 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-22 21:21:39,143 INFO L82 PathProgramCache]: Analyzing trace with hash 792209878, now seen corresponding path program 1 times [2018-11-22 21:21:39,143 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-22 21:21:39,143 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-22 21:21:39,144 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-22 21:21:39,144 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-22 21:21:39,144 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-22 21:21:39,149 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-22 21:21:39,183 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-22 21:21:39,183 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-22 21:21:39,183 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-11-22 21:21:39,183 INFO L811 eck$LassoCheckResult]: loop already infeasible [2018-11-22 21:21:39,184 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-11-22 21:21:39,184 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-11-22 21:21:39,184 INFO L87 Difference]: Start difference. First operand 20444 states and 28838 transitions. cyclomatic complexity: 8410 Second operand 5 states. [2018-11-22 21:21:39,388 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-22 21:21:39,388 INFO L93 Difference]: Finished difference Result 30396 states and 42785 transitions. [2018-11-22 21:21:39,388 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2018-11-22 21:21:39,388 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 30396 states and 42785 transitions. [2018-11-22 21:21:39,472 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 30064 [2018-11-22 21:21:39,530 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 30396 states to 30396 states and 42785 transitions. [2018-11-22 21:21:39,530 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 30396 [2018-11-22 21:21:39,548 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 30396 [2018-11-22 21:21:39,548 INFO L73 IsDeterministic]: Start isDeterministic. Operand 30396 states and 42785 transitions. [2018-11-22 21:21:39,564 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-22 21:21:39,564 INFO L705 BuchiCegarLoop]: Abstraction has 30396 states and 42785 transitions. [2018-11-22 21:21:39,584 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 30396 states and 42785 transitions. [2018-11-22 21:21:39,728 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 30396 to 20492. [2018-11-22 21:21:39,728 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 20492 states. [2018-11-22 21:21:39,891 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 20492 states to 20492 states and 28661 transitions. [2018-11-22 21:21:39,891 INFO L728 BuchiCegarLoop]: Abstraction has 20492 states and 28661 transitions. [2018-11-22 21:21:39,891 INFO L608 BuchiCegarLoop]: Abstraction has 20492 states and 28661 transitions. [2018-11-22 21:21:39,891 INFO L442 BuchiCegarLoop]: ======== Iteration 20============ [2018-11-22 21:21:39,891 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 20492 states and 28661 transitions. [2018-11-22 21:21:39,918 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 20256 [2018-11-22 21:21:39,918 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-22 21:21:39,919 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-22 21:21:39,920 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-22 21:21:39,920 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-22 21:21:39,920 INFO L794 eck$LassoCheckResult]: Stem: 288299#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2; 288185#L-1 havoc main_#res;havoc main_~__retres1~10;havoc main_~__retres1~10;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 288186#L1225 havoc start_simulation_#t~ret20, start_simulation_#t~ret21, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 288679#L564 assume 1 == ~m_i~0;~m_st~0 := 0; 288220#L571-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 287925#L576-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 287926#L581-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 288685#L586-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 288423#L591-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 288027#L596-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 288028#L601-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 288672#L606-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 288555#L611-1 assume !(0 == ~M_E~0); 288556#L828-1 assume !(0 == ~T1_E~0); 288323#L833-1 assume !(0 == ~T2_E~0); 288042#L838-1 assume !(0 == ~T3_E~0); 288043#L843-1 assume !(0 == ~T4_E~0); 288774#L848-1 assume !(0 == ~T5_E~0); 288565#L853-1 assume !(0 == ~T6_E~0); 288306#L858-1 assume !(0 == ~T7_E~0); 287843#L863-1 assume !(0 == ~T8_E~0); 287844#L868-1 assume !(0 == ~E_1~0); 288515#L873-1 assume !(0 == ~E_2~0); 288393#L878-1 assume !(0 == ~E_3~0); 288151#L883-1 assume !(0 == ~E_4~0); 288152#L888-1 assume !(0 == ~E_5~0); 288644#L893-1 assume !(0 == ~E_6~0); 288362#L898-1 assume !(0 == ~E_7~0); 288287#L903-1 assume !(0 == ~E_8~0); 287984#L908-1 havoc activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 287985#L392 assume !(1 == ~m_pc~0); 288346#L392-2 is_master_triggered_~__retres1~0 := 0; 288349#L403 is_master_triggered_#res := is_master_triggered_~__retres1~0; 288838#L404 activate_threads_#t~ret10 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 288650#L1025 assume !(0 != activate_threads_~tmp~1); 288651#L1025-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 288502#L411 assume !(1 == ~t1_pc~0); 288471#L411-2 is_transmit1_triggered_~__retres1~1 := 0; 287910#L422 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 287911#L423 activate_threads_#t~ret11 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 288009#L1033 assume !(0 != activate_threads_~tmp___0~0); 288227#L1033-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 288228#L430 assume !(1 == ~t2_pc~0); 288661#L430-2 is_transmit2_triggered_~__retres1~2 := 0; 288077#L441 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 288029#L442 activate_threads_#t~ret12 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 288030#L1041 assume !(0 != activate_threads_~tmp___1~0); 288865#L1041-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 288866#L449 assume !(1 == ~t3_pc~0); 288737#L449-2 is_transmit3_triggered_~__retres1~3 := 0; 288377#L460 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 288206#L461 activate_threads_#t~ret13 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 288207#L1049 assume !(0 != activate_threads_~tmp___2~0); 288677#L1049-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 287945#L468 assume !(1 == ~t4_pc~0); 287946#L468-2 is_transmit4_triggered_~__retres1~4 := 0; 287951#L479 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 288355#L480 activate_threads_#t~ret14 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 288294#L1057 assume !(0 != activate_threads_~tmp___3~0); 288295#L1057-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 288137#L487 assume !(1 == ~t5_pc~0); 287903#L487-2 is_transmit5_triggered_~__retres1~5 := 0; 287902#L498 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 288490#L499 activate_threads_#t~ret15 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 288491#L1065 assume !(0 != activate_threads_~tmp___4~0); 288881#L1065-2 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 288305#L506 assume !(1 == ~t6_pc~0); 288302#L506-2 is_transmit6_triggered_~__retres1~6 := 0; 288303#L517 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 288674#L518 activate_threads_#t~ret16 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 288590#L1073 assume !(0 != activate_threads_~tmp___5~0); 288591#L1073-2 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 288424#L525 assume !(1 == ~t7_pc~0); 288425#L525-2 is_transmit7_triggered_~__retres1~7 := 0; 288426#L536 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 288867#L537 activate_threads_#t~ret17 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 288158#L1081 assume !(0 != activate_threads_~tmp___6~0); 288159#L1081-2 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 288160#L544 assume !(1 == ~t8_pc~0); 288442#L544-2 is_transmit8_triggered_~__retres1~8 := 0; 287837#L555 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 287838#L556 activate_threads_#t~ret18 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 287973#L1089 assume !(0 != activate_threads_~tmp___7~0); 288718#L1089-2 assume !(1 == ~M_E~0); 288316#L921-1 assume !(1 == ~T1_E~0); 288038#L926-1 assume !(1 == ~T2_E~0); 288039#L931-1 assume !(1 == ~T3_E~0); 288772#L936-1 assume !(1 == ~T4_E~0); 288581#L941-1 assume !(1 == ~T5_E~0); 288312#L946-1 assume !(1 == ~T6_E~0); 287853#L951-1 assume !(1 == ~T7_E~0); 287854#L956-1 assume !(1 == ~T8_E~0); 288678#L961-1 assume !(1 == ~E_1~0); 288398#L966-1 assume !(1 == ~E_2~0); 288165#L971-1 assume !(1 == ~E_3~0); 288166#L976-1 assume !(1 == ~E_4~0); 288638#L981-1 assume !(1 == ~E_5~0); 288360#L986-1 assume !(1 == ~E_6~0); 288279#L991-1 assume !(1 == ~E_7~0); 287979#L996-1 assume !(1 == ~E_8~0); 287980#L1262-1 [2018-11-22 21:21:39,921 INFO L796 eck$LassoCheckResult]: Loop: 287980#L1262-1 assume !false; 292530#L1263 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret0, eval_#t~nondet1, eval_~tmp_ndt_1~0, eval_#t~nondet2, eval_~tmp_ndt_2~0, eval_#t~nondet3, eval_~tmp_ndt_3~0, eval_#t~nondet4, eval_~tmp_ndt_4~0, eval_#t~nondet5, eval_~tmp_ndt_5~0, eval_#t~nondet6, eval_~tmp_ndt_6~0, eval_#t~nondet7, eval_~tmp_ndt_7~0, eval_#t~nondet8, eval_~tmp_ndt_8~0, eval_#t~nondet9, eval_~tmp_ndt_9~0, eval_~tmp~0;havoc eval_~tmp~0; 292529#L803 assume !false; 292528#L682 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~9;havoc exists_runnable_thread_~__retres1~9; 292523#L624 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9 := 1; 292518#L671 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~9; 292517#L672 eval_#t~ret0 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret0;havoc eval_#t~ret0; 292515#L686 assume !(0 != eval_~tmp~0); 292516#L818 start_simulation_~kernel_st~0 := 2; 292961#L564-1 start_simulation_~kernel_st~0 := 3; 292959#L828-2 assume !(0 == ~M_E~0); 292957#L828-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 292955#L833-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 292953#L838-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 292951#L843-3 assume !(0 == ~T4_E~0); 292949#L848-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 292946#L853-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 292944#L858-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 292942#L863-3 assume !(0 == ~T8_E~0); 292940#L868-3 assume 0 == ~E_1~0;~E_1~0 := 1; 292938#L873-3 assume 0 == ~E_2~0;~E_2~0 := 1; 292936#L878-3 assume 0 == ~E_3~0;~E_3~0 := 1; 292934#L883-3 assume !(0 == ~E_4~0); 292932#L888-3 assume 0 == ~E_5~0;~E_5~0 := 1; 292930#L893-3 assume 0 == ~E_6~0;~E_6~0 := 1; 292928#L898-3 assume 0 == ~E_7~0;~E_7~0 := 1; 292926#L903-3 assume !(0 == ~E_8~0); 292924#L908-3 havoc activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 292921#L392-27 assume !(1 == ~m_pc~0); 292918#L392-29 is_master_triggered_~__retres1~0 := 0; 292916#L403-9 is_master_triggered_#res := is_master_triggered_~__retres1~0; 292914#L404-9 activate_threads_#t~ret10 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 292912#L1025-27 assume !(0 != activate_threads_~tmp~1); 292910#L1025-29 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 292908#L411-27 assume !(1 == ~t1_pc~0); 292904#L411-29 is_transmit1_triggered_~__retres1~1 := 0; 292902#L422-9 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 292900#L423-9 activate_threads_#t~ret11 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 292898#L1033-27 assume !(0 != activate_threads_~tmp___0~0); 292895#L1033-29 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 292893#L430-27 assume !(1 == ~t2_pc~0); 292891#L430-29 is_transmit2_triggered_~__retres1~2 := 0; 292889#L441-9 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 292887#L442-9 activate_threads_#t~ret12 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 292885#L1041-27 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 292882#L1041-29 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 292880#L449-27 assume 1 == ~t3_pc~0; 292877#L450-9 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 292875#L460-9 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 292873#L461-9 activate_threads_#t~ret13 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 292872#L1049-27 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 292868#L1049-29 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 292866#L468-27 assume !(1 == ~t4_pc~0); 292861#L468-29 is_transmit4_triggered_~__retres1~4 := 0; 292857#L479-9 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 292853#L480-9 activate_threads_#t~ret14 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 292852#L1057-27 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 292851#L1057-29 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 292850#L487-27 assume !(1 == ~t5_pc~0); 292848#L487-29 is_transmit5_triggered_~__retres1~5 := 0; 292845#L498-9 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 292839#L499-9 activate_threads_#t~ret15 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 292837#L1065-27 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 292835#L1065-29 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 292834#L506-27 assume !(1 == ~t6_pc~0); 292833#L506-29 is_transmit6_triggered_~__retres1~6 := 0; 292832#L517-9 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 292831#L518-9 activate_threads_#t~ret16 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 292830#L1073-27 assume 0 != activate_threads_~tmp___5~0;~t6_st~0 := 0; 292829#L1073-29 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 292819#L525-27 assume !(1 == ~t7_pc~0); 292817#L525-29 is_transmit7_triggered_~__retres1~7 := 0; 292815#L536-9 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 292812#L537-9 activate_threads_#t~ret17 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 292810#L1081-27 assume 0 != activate_threads_~tmp___6~0;~t7_st~0 := 0; 292808#L1081-29 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 292806#L544-27 assume !(1 == ~t8_pc~0); 292803#L544-29 is_transmit8_triggered_~__retres1~8 := 0; 292801#L555-9 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 292799#L556-9 activate_threads_#t~ret18 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 292797#L1089-27 assume !(0 != activate_threads_~tmp___7~0); 292642#L1089-29 assume !(1 == ~M_E~0); 292640#L921-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 292638#L926-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 292636#L931-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 292634#L936-3 assume !(1 == ~T4_E~0); 292632#L941-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 292630#L946-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 292628#L951-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 292626#L956-3 assume !(1 == ~T8_E~0); 292624#L961-3 assume 1 == ~E_1~0;~E_1~0 := 2; 292621#L966-3 assume 1 == ~E_2~0;~E_2~0 := 2; 292619#L971-3 assume 1 == ~E_3~0;~E_3~0 := 2; 292617#L976-3 assume !(1 == ~E_4~0); 292615#L981-3 assume 1 == ~E_5~0;~E_5~0 := 2; 292613#L986-3 assume 1 == ~E_6~0;~E_6~0 := 2; 292610#L991-3 assume 1 == ~E_7~0;~E_7~0 := 2; 292608#L996-3 assume !(1 == ~E_8~0); 292606#L1001-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~9;havoc exists_runnable_thread_~__retres1~9; 292598#L624-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9 := 1; 292590#L671-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~9; 292588#L672-1 start_simulation_#t~ret20 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret20;havoc start_simulation_#t~ret20; 292575#L1281 assume !(0 == start_simulation_~tmp~3); 292573#L1281-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret19, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~9;havoc exists_runnable_thread_~__retres1~9; 292557#L624-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9 := 1; 292549#L671-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~9; 292547#L672-2 stop_simulation_#t~ret19 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret19;havoc stop_simulation_#t~ret19; 292545#L1236 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 292543#L1243 stop_simulation_#res := stop_simulation_~__retres2~0; 292541#L1244 start_simulation_#t~ret21 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret21;havoc start_simulation_#t~ret21; 292539#L1294 assume !(0 != start_simulation_~tmp___0~1); 287980#L1262-1 [2018-11-22 21:21:39,921 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-22 21:21:39,921 INFO L82 PathProgramCache]: Analyzing trace with hash 426104125, now seen corresponding path program 1 times [2018-11-22 21:21:39,921 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-22 21:21:39,921 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-22 21:21:39,922 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-22 21:21:39,922 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-22 21:21:39,922 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-22 21:21:39,929 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-22 21:21:39,937 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-22 21:21:39,973 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-22 21:21:39,974 INFO L82 PathProgramCache]: Analyzing trace with hash 1116166935, now seen corresponding path program 1 times [2018-11-22 21:21:39,974 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-22 21:21:39,974 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-22 21:21:39,974 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-22 21:21:39,975 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-22 21:21:39,975 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-22 21:21:39,980 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-22 21:21:40,003 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-22 21:21:40,003 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-22 21:21:40,003 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-11-22 21:21:40,004 INFO L811 eck$LassoCheckResult]: loop already infeasible [2018-11-22 21:21:40,004 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-11-22 21:21:40,004 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-11-22 21:21:40,004 INFO L87 Difference]: Start difference. First operand 20492 states and 28661 transitions. cyclomatic complexity: 8185 Second operand 5 states. [2018-11-22 21:21:40,131 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-22 21:21:40,131 INFO L93 Difference]: Finished difference Result 37260 states and 51509 transitions. [2018-11-22 21:21:40,132 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2018-11-22 21:21:40,132 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 37260 states and 51509 transitions. [2018-11-22 21:21:40,221 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 36896 [2018-11-22 21:21:40,278 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 37260 states to 37260 states and 51509 transitions. [2018-11-22 21:21:40,278 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 37260 [2018-11-22 21:21:40,295 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 37260 [2018-11-22 21:21:40,295 INFO L73 IsDeterministic]: Start isDeterministic. Operand 37260 states and 51509 transitions. [2018-11-22 21:21:40,311 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-22 21:21:40,311 INFO L705 BuchiCegarLoop]: Abstraction has 37260 states and 51509 transitions. [2018-11-22 21:21:40,328 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 37260 states and 51509 transitions. [2018-11-22 21:21:40,455 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 37260 to 20588. [2018-11-22 21:21:40,455 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 20588 states. [2018-11-22 21:21:40,472 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 20588 states to 20588 states and 28757 transitions. [2018-11-22 21:21:40,472 INFO L728 BuchiCegarLoop]: Abstraction has 20588 states and 28757 transitions. [2018-11-22 21:21:40,472 INFO L608 BuchiCegarLoop]: Abstraction has 20588 states and 28757 transitions. [2018-11-22 21:21:40,472 INFO L442 BuchiCegarLoop]: ======== Iteration 21============ [2018-11-22 21:21:40,472 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 20588 states and 28757 transitions. [2018-11-22 21:21:40,509 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 20352 [2018-11-22 21:21:40,510 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-22 21:21:40,510 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-22 21:21:40,511 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-22 21:21:40,511 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-22 21:21:40,511 INFO L794 eck$LassoCheckResult]: Stem: 346067#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2; 345960#L-1 havoc main_#res;havoc main_~__retres1~10;havoc main_~__retres1~10;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 345961#L1225 havoc start_simulation_#t~ret20, start_simulation_#t~ret21, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 346458#L564 assume 1 == ~m_i~0;~m_st~0 := 0; 345996#L571-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 345695#L576-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 345696#L581-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 346463#L586-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 346203#L591-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 345800#L596-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 345801#L601-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 346452#L606-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 346343#L611-1 assume !(0 == ~M_E~0); 346344#L828-1 assume !(0 == ~T1_E~0); 346095#L833-1 assume !(0 == ~T2_E~0); 345815#L838-1 assume !(0 == ~T3_E~0); 345816#L843-1 assume !(0 == ~T4_E~0); 346552#L848-1 assume !(0 == ~T5_E~0); 346354#L853-1 assume !(0 == ~T6_E~0); 346078#L858-1 assume !(0 == ~T7_E~0); 345611#L863-1 assume !(0 == ~T8_E~0); 345612#L868-1 assume !(0 == ~E_1~0); 346301#L873-1 assume !(0 == ~E_2~0); 346171#L878-1 assume !(0 == ~E_3~0); 345927#L883-1 assume !(0 == ~E_4~0); 345928#L888-1 assume !(0 == ~E_5~0); 346426#L893-1 assume !(0 == ~E_6~0); 346138#L898-1 assume !(0 == ~E_7~0); 346056#L903-1 assume !(0 == ~E_8~0); 345757#L908-1 havoc activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 345758#L392 assume !(1 == ~m_pc~0); 346119#L392-2 is_master_triggered_~__retres1~0 := 0; 346122#L403 is_master_triggered_#res := is_master_triggered_~__retres1~0; 346607#L404 activate_threads_#t~ret10 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 346432#L1025 assume !(0 != activate_threads_~tmp~1); 346433#L1025-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 346287#L411 assume !(1 == ~t1_pc~0); 346255#L411-2 is_transmit1_triggered_~__retres1~1 := 0; 345679#L422 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 345680#L423 activate_threads_#t~ret11 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 345782#L1033 assume !(0 != activate_threads_~tmp___0~0); 346002#L1033-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 346003#L430 assume !(1 == ~t2_pc~0); 346443#L430-2 is_transmit2_triggered_~__retres1~2 := 0; 345851#L441 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 345802#L442 activate_threads_#t~ret12 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 345803#L1041 assume !(0 != activate_threads_~tmp___1~0); 346638#L1041-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 346639#L449 assume !(1 == ~t3_pc~0); 346515#L449-2 is_transmit3_triggered_~__retres1~3 := 0; 346154#L460 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 345981#L461 activate_threads_#t~ret13 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 345982#L1049 assume !(0 != activate_threads_~tmp___2~0); 346456#L1049-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 345716#L468 assume !(1 == ~t4_pc~0); 345717#L468-2 is_transmit4_triggered_~__retres1~4 := 0; 345722#L479 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 346129#L480 activate_threads_#t~ret14 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 346061#L1057 assume !(0 != activate_threads_~tmp___3~0); 346062#L1057-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 345913#L487 assume !(1 == ~t5_pc~0); 345672#L487-2 is_transmit5_triggered_~__retres1~5 := 0; 345671#L498 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 346274#L499 activate_threads_#t~ret15 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 346275#L1065 assume !(0 != activate_threads_~tmp___4~0); 346651#L1065-2 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 346077#L506 assume !(1 == ~t6_pc~0); 346072#L506-2 is_transmit6_triggered_~__retres1~6 := 0; 346073#L517 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 346454#L518 activate_threads_#t~ret16 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 346372#L1073 assume !(0 != activate_threads_~tmp___5~0); 346373#L1073-2 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 346204#L525 assume !(1 == ~t7_pc~0); 346205#L525-2 is_transmit7_triggered_~__retres1~7 := 0; 346208#L536 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 346640#L537 activate_threads_#t~ret17 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 345933#L1081 assume !(0 != activate_threads_~tmp___6~0); 345934#L1081-2 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 345935#L544 assume !(1 == ~t8_pc~0); 346225#L544-2 is_transmit8_triggered_~__retres1~8 := 0; 345605#L555 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 345606#L556 activate_threads_#t~ret18 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 345746#L1089 assume !(0 != activate_threads_~tmp___7~0); 346499#L1089-2 assume !(1 == ~M_E~0); 346088#L921-1 assume !(1 == ~T1_E~0); 345811#L926-1 assume !(1 == ~T2_E~0); 345812#L931-1 assume !(1 == ~T3_E~0); 346549#L936-1 assume !(1 == ~T4_E~0); 346362#L941-1 assume !(1 == ~T5_E~0); 346084#L946-1 assume !(1 == ~T6_E~0); 345621#L951-1 assume !(1 == ~T7_E~0); 345622#L956-1 assume !(1 == ~T8_E~0); 346457#L961-1 assume !(1 == ~E_1~0); 346176#L966-1 assume !(1 == ~E_2~0); 345939#L971-1 assume !(1 == ~E_3~0); 345940#L976-1 assume !(1 == ~E_4~0); 346419#L981-1 assume !(1 == ~E_5~0); 346135#L986-1 assume !(1 == ~E_6~0); 346048#L991-1 assume !(1 == ~E_7~0); 345752#L996-1 assume !(1 == ~E_8~0); 345753#L1262-1 [2018-11-22 21:21:40,511 INFO L796 eck$LassoCheckResult]: Loop: 345753#L1262-1 assume !false; 357226#L1263 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret0, eval_#t~nondet1, eval_~tmp_ndt_1~0, eval_#t~nondet2, eval_~tmp_ndt_2~0, eval_#t~nondet3, eval_~tmp_ndt_3~0, eval_#t~nondet4, eval_~tmp_ndt_4~0, eval_#t~nondet5, eval_~tmp_ndt_5~0, eval_#t~nondet6, eval_~tmp_ndt_6~0, eval_#t~nondet7, eval_~tmp_ndt_7~0, eval_#t~nondet8, eval_~tmp_ndt_8~0, eval_#t~nondet9, eval_~tmp_ndt_9~0, eval_~tmp~0;havoc eval_~tmp~0; 357167#L803 assume !false; 356326#L682 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~9;havoc exists_runnable_thread_~__retres1~9; 356215#L624 assume !(0 == ~m_st~0); 356216#L628 assume !(0 == ~t1_st~0); 356219#L632 assume !(0 == ~t2_st~0); 356213#L636 assume !(0 == ~t3_st~0); 356214#L640 assume !(0 == ~t4_st~0); 356218#L644 assume !(0 == ~t5_st~0); 356211#L648 assume !(0 == ~t6_st~0); 356212#L652 assume !(0 == ~t7_st~0); 356217#L656 assume !(0 == ~t8_st~0);exists_runnable_thread_~__retres1~9 := 0; 356196#L671 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~9; 352137#L672 eval_#t~ret0 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret0;havoc eval_#t~ret0; 352138#L686 assume !(0 != eval_~tmp~0); 356132#L818 start_simulation_~kernel_st~0 := 2; 356131#L564-1 start_simulation_~kernel_st~0 := 3; 356130#L828-2 assume !(0 == ~M_E~0); 356129#L828-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 356128#L833-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 356127#L838-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 356126#L843-3 assume !(0 == ~T4_E~0); 356125#L848-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 356124#L853-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 356123#L858-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 356122#L863-3 assume !(0 == ~T8_E~0); 356121#L868-3 assume 0 == ~E_1~0;~E_1~0 := 1; 356120#L873-3 assume 0 == ~E_2~0;~E_2~0 := 1; 356119#L878-3 assume 0 == ~E_3~0;~E_3~0 := 1; 356118#L883-3 assume !(0 == ~E_4~0); 356117#L888-3 assume 0 == ~E_5~0;~E_5~0 := 1; 356116#L893-3 assume 0 == ~E_6~0;~E_6~0 := 1; 356115#L898-3 assume 0 == ~E_7~0;~E_7~0 := 1; 356114#L903-3 assume !(0 == ~E_8~0); 356113#L908-3 havoc activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 356112#L392-27 assume !(1 == ~m_pc~0); 356110#L392-29 is_master_triggered_~__retres1~0 := 0; 356109#L403-9 is_master_triggered_#res := is_master_triggered_~__retres1~0; 356108#L404-9 activate_threads_#t~ret10 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 356107#L1025-27 assume !(0 != activate_threads_~tmp~1); 356106#L1025-29 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 356105#L411-27 assume 1 == ~t1_pc~0; 356103#L412-9 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 356101#L422-9 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 356099#L423-9 activate_threads_#t~ret11 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 356097#L1033-27 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 356096#L1033-29 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 356095#L430-27 assume !(1 == ~t2_pc~0); 356094#L430-29 is_transmit2_triggered_~__retres1~2 := 0; 356093#L441-9 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 356092#L442-9 activate_threads_#t~ret12 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 356091#L1041-27 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 356090#L1041-29 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 356089#L449-27 assume 1 == ~t3_pc~0; 356087#L450-9 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 356086#L460-9 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 356085#L461-9 activate_threads_#t~ret13 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 356084#L1049-27 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 356083#L1049-29 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 356082#L468-27 assume !(1 == ~t4_pc~0); 356081#L468-29 is_transmit4_triggered_~__retres1~4 := 0; 356080#L479-9 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 356079#L480-9 activate_threads_#t~ret14 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 356078#L1057-27 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 356077#L1057-29 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 356076#L487-27 assume !(1 == ~t5_pc~0); 356075#L487-29 is_transmit5_triggered_~__retres1~5 := 0; 356073#L498-9 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 356072#L499-9 activate_threads_#t~ret15 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 356071#L1065-27 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 356070#L1065-29 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 356069#L506-27 assume !(1 == ~t6_pc~0); 356068#L506-29 is_transmit6_triggered_~__retres1~6 := 0; 356067#L517-9 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 356066#L518-9 activate_threads_#t~ret16 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 356065#L1073-27 assume 0 != activate_threads_~tmp___5~0;~t6_st~0 := 0; 356064#L1073-29 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 356063#L525-27 assume !(1 == ~t7_pc~0); 356062#L525-29 is_transmit7_triggered_~__retres1~7 := 0; 356061#L536-9 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 356060#L537-9 activate_threads_#t~ret17 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 356059#L1081-27 assume 0 != activate_threads_~tmp___6~0;~t7_st~0 := 0; 356058#L1081-29 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 356057#L544-27 assume !(1 == ~t8_pc~0); 356055#L544-29 is_transmit8_triggered_~__retres1~8 := 0; 356054#L555-9 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 356053#L556-9 activate_threads_#t~ret18 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 356052#L1089-27 assume !(0 != activate_threads_~tmp___7~0); 356051#L1089-29 assume !(1 == ~M_E~0); 354567#L921-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 356050#L926-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 356049#L931-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 356048#L936-3 assume !(1 == ~T4_E~0); 356047#L941-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 356046#L946-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 356045#L951-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 356044#L956-3 assume !(1 == ~T8_E~0); 356043#L961-3 assume 1 == ~E_1~0;~E_1~0 := 2; 356042#L966-3 assume 1 == ~E_2~0;~E_2~0 := 2; 356041#L971-3 assume 1 == ~E_3~0;~E_3~0 := 2; 356040#L976-3 assume !(1 == ~E_4~0); 356039#L981-3 assume 1 == ~E_5~0;~E_5~0 := 2; 356038#L986-3 assume 1 == ~E_6~0;~E_6~0 := 2; 356037#L991-3 assume 1 == ~E_7~0;~E_7~0 := 2; 356036#L996-3 assume !(1 == ~E_8~0); 356035#L1001-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~9;havoc exists_runnable_thread_~__retres1~9; 356032#L624-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9 := 1; 356021#L671-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~9; 356018#L672-1 start_simulation_#t~ret20 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret20;havoc start_simulation_#t~ret20; 356015#L1281 assume !(0 == start_simulation_~tmp~3); 356016#L1281-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret19, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~9;havoc exists_runnable_thread_~__retres1~9; 357714#L624-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9 := 1; 357706#L671-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~9; 357704#L672-2 stop_simulation_#t~ret19 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret19;havoc stop_simulation_#t~ret19; 357702#L1236 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 357700#L1243 stop_simulation_#res := stop_simulation_~__retres2~0; 357697#L1244 start_simulation_#t~ret21 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret21;havoc start_simulation_#t~ret21; 357695#L1294 assume !(0 != start_simulation_~tmp___0~1); 345753#L1262-1 [2018-11-22 21:21:40,512 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-22 21:21:40,512 INFO L82 PathProgramCache]: Analyzing trace with hash 426104125, now seen corresponding path program 2 times [2018-11-22 21:21:40,512 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-22 21:21:40,512 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-22 21:21:40,513 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-22 21:21:40,513 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-22 21:21:40,513 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-22 21:21:40,519 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-22 21:21:40,525 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-22 21:21:40,548 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-22 21:21:40,548 INFO L82 PathProgramCache]: Analyzing trace with hash -82788118, now seen corresponding path program 1 times [2018-11-22 21:21:40,548 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-22 21:21:40,549 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-22 21:21:40,549 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-22 21:21:40,549 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-22 21:21:40,549 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-22 21:21:40,554 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-22 21:21:40,583 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-22 21:21:40,583 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-22 21:21:40,583 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-22 21:21:40,583 INFO L811 eck$LassoCheckResult]: loop already infeasible [2018-11-22 21:21:40,584 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-22 21:21:40,584 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-22 21:21:40,584 INFO L87 Difference]: Start difference. First operand 20588 states and 28757 transitions. cyclomatic complexity: 8185 Second operand 3 states. [2018-11-22 21:21:40,685 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-22 21:21:40,685 INFO L93 Difference]: Finished difference Result 39020 states and 53733 transitions. [2018-11-22 21:21:40,685 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-22 21:21:40,685 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 39020 states and 53733 transitions. [2018-11-22 21:21:40,781 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 38656 [2018-11-22 21:21:40,842 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 39020 states to 39020 states and 53733 transitions. [2018-11-22 21:21:40,842 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 39020 [2018-11-22 21:21:40,860 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 39020 [2018-11-22 21:21:40,860 INFO L73 IsDeterministic]: Start isDeterministic. Operand 39020 states and 53733 transitions. [2018-11-22 21:21:40,876 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-22 21:21:40,876 INFO L705 BuchiCegarLoop]: Abstraction has 39020 states and 53733 transitions. [2018-11-22 21:21:40,893 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 39020 states and 53733 transitions. [2018-11-22 21:21:41,291 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 39020 to 37100. [2018-11-22 21:21:41,291 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 37100 states. [2018-11-22 21:21:41,326 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 37100 states to 37100 states and 51253 transitions. [2018-11-22 21:21:41,326 INFO L728 BuchiCegarLoop]: Abstraction has 37100 states and 51253 transitions. [2018-11-22 21:21:41,326 INFO L608 BuchiCegarLoop]: Abstraction has 37100 states and 51253 transitions. [2018-11-22 21:21:41,326 INFO L442 BuchiCegarLoop]: ======== Iteration 22============ [2018-11-22 21:21:41,326 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 37100 states and 51253 transitions. [2018-11-22 21:21:41,397 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 36736 [2018-11-22 21:21:41,397 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-22 21:21:41,397 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-22 21:21:41,399 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-22 21:21:41,399 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-22 21:21:41,399 INFO L794 eck$LassoCheckResult]: Stem: 405670#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2; 405567#L-1 havoc main_#res;havoc main_~__retres1~10;havoc main_~__retres1~10;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 405568#L1225 havoc start_simulation_#t~ret20, start_simulation_#t~ret21, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 406054#L564 assume 1 == ~m_i~0;~m_st~0 := 0; 405602#L571-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 405306#L576-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 405307#L581-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 406057#L586-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 405803#L591-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 405409#L596-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 405410#L601-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 406048#L606-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 405942#L611-1 assume !(0 == ~M_E~0); 405943#L828-1 assume !(0 == ~T1_E~0); 405695#L833-1 assume !(0 == ~T2_E~0); 405424#L838-1 assume !(0 == ~T3_E~0); 405425#L843-1 assume !(0 == ~T4_E~0); 406148#L848-1 assume !(0 == ~T5_E~0); 405952#L853-1 assume !(0 == ~T6_E~0); 405677#L858-1 assume !(0 == ~T7_E~0); 405225#L863-1 assume !(0 == ~T8_E~0); 405226#L868-1 assume !(0 == ~E_1~0); 405899#L873-1 assume !(0 == ~E_2~0); 405772#L878-1 assume !(0 == ~E_3~0); 405535#L883-1 assume !(0 == ~E_4~0); 405536#L888-1 assume !(0 == ~E_5~0); 406023#L893-1 assume !(0 == ~E_6~0); 405736#L898-1 assume !(0 == ~E_7~0); 405661#L903-1 assume !(0 == ~E_8~0); 405371#L908-1 havoc activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 405372#L392 assume !(1 == ~m_pc~0); 405717#L392-2 is_master_triggered_~__retres1~0 := 0; 405720#L403 is_master_triggered_#res := is_master_triggered_~__retres1~0; 406193#L404 activate_threads_#t~ret10 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 406029#L1025 assume !(0 != activate_threads_~tmp~1); 406030#L1025-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 405885#L411 assume !(1 == ~t1_pc~0); 405853#L411-2 is_transmit1_triggered_~__retres1~1 := 0; 405292#L422 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 405293#L423 activate_threads_#t~ret11 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 405391#L1033 assume !(0 != activate_threads_~tmp___0~0); 405609#L1033-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 405610#L430 assume !(1 == ~t2_pc~0); 406039#L430-2 is_transmit2_triggered_~__retres1~2 := 0; 405460#L441 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 405411#L442 activate_threads_#t~ret12 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 405412#L1041 assume !(0 != activate_threads_~tmp___1~0); 406218#L1041-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 406219#L449 assume !(1 == ~t3_pc~0); 406110#L449-2 is_transmit3_triggered_~__retres1~3 := 0; 405753#L460 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 405587#L461 activate_threads_#t~ret13 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 405588#L1049 assume !(0 != activate_threads_~tmp___2~0); 406052#L1049-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 405327#L468 assume !(1 == ~t4_pc~0); 405328#L468-2 is_transmit4_triggered_~__retres1~4 := 0; 405335#L479 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 405728#L480 activate_threads_#t~ret14 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 405665#L1057 assume !(0 != activate_threads_~tmp___3~0); 405666#L1057-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 405521#L487 assume !(1 == ~t5_pc~0); 405285#L487-2 is_transmit5_triggered_~__retres1~5 := 0; 405284#L498 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 405872#L499 activate_threads_#t~ret15 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 405873#L1065 assume !(0 != activate_threads_~tmp___4~0); 406237#L1065-2 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 405676#L506 assume !(1 == ~t6_pc~0); 405673#L506-2 is_transmit6_triggered_~__retres1~6 := 0; 405674#L517 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 406050#L518 activate_threads_#t~ret16 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 405969#L1073 assume !(0 != activate_threads_~tmp___5~0); 405970#L1073-2 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 405805#L525 assume !(1 == ~t7_pc~0); 405806#L525-2 is_transmit7_triggered_~__retres1~7 := 0; 405808#L536 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 406220#L537 activate_threads_#t~ret17 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 405541#L1081 assume !(0 != activate_threads_~tmp___6~0); 405542#L1081-2 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 405543#L544 assume !(1 == ~t8_pc~0); 405826#L544-2 is_transmit8_triggered_~__retres1~8 := 0; 405219#L555 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 405220#L556 activate_threads_#t~ret18 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 405359#L1089 assume !(0 != activate_threads_~tmp___7~0); 406093#L1089-2 assume !(1 == ~M_E~0); 405689#L921-1 assume !(1 == ~T1_E~0); 405420#L926-1 assume !(1 == ~T2_E~0); 405421#L931-1 assume !(1 == ~T3_E~0); 406146#L936-1 assume !(1 == ~T4_E~0); 405960#L941-1 assume !(1 == ~T5_E~0); 405685#L946-1 assume !(1 == ~T6_E~0); 405235#L951-1 assume !(1 == ~T7_E~0); 405236#L956-1 assume !(1 == ~T8_E~0); 406053#L961-1 assume !(1 == ~E_1~0); 405780#L966-1 assume !(1 == ~E_2~0); 405547#L971-1 assume !(1 == ~E_3~0); 405548#L976-1 assume !(1 == ~E_4~0); 406017#L981-1 assume !(1 == ~E_5~0); 405734#L986-1 assume !(1 == ~E_6~0); 405655#L991-1 assume !(1 == ~E_7~0); 405366#L996-1 assume !(1 == ~E_8~0); 405367#L1262-1 [2018-11-22 21:21:41,399 INFO L796 eck$LassoCheckResult]: Loop: 405367#L1262-1 assume !false; 420856#L1263 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret0, eval_#t~nondet1, eval_~tmp_ndt_1~0, eval_#t~nondet2, eval_~tmp_ndt_2~0, eval_#t~nondet3, eval_~tmp_ndt_3~0, eval_#t~nondet4, eval_~tmp_ndt_4~0, eval_#t~nondet5, eval_~tmp_ndt_5~0, eval_#t~nondet6, eval_~tmp_ndt_6~0, eval_#t~nondet7, eval_~tmp_ndt_7~0, eval_#t~nondet8, eval_~tmp_ndt_8~0, eval_#t~nondet9, eval_~tmp_ndt_9~0, eval_~tmp~0;havoc eval_~tmp~0; 420855#L803 assume !false; 420854#L682 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~9;havoc exists_runnable_thread_~__retres1~9; 420852#L624 assume !(0 == ~m_st~0); 419592#L628 assume !(0 == ~t1_st~0); 419590#L632 assume !(0 == ~t2_st~0); 419588#L636 assume !(0 == ~t3_st~0); 419586#L640 assume !(0 == ~t4_st~0); 419584#L644 assume !(0 == ~t5_st~0); 419582#L648 assume !(0 == ~t6_st~0); 419580#L652 assume !(0 == ~t7_st~0); 419575#L656 assume !(0 == ~t8_st~0);exists_runnable_thread_~__retres1~9 := 0; 419573#L671 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~9; 419571#L672 eval_#t~ret0 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret0;havoc eval_#t~ret0; 419569#L686 assume !(0 != eval_~tmp~0); 419561#L818 start_simulation_~kernel_st~0 := 2; 419559#L564-1 start_simulation_~kernel_st~0 := 3; 419557#L828-2 assume !(0 == ~M_E~0); 419555#L828-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 419553#L833-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 419551#L838-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 419549#L843-3 assume !(0 == ~T4_E~0); 419547#L848-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 419546#L853-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 419545#L858-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 419544#L863-3 assume !(0 == ~T8_E~0); 419543#L868-3 assume 0 == ~E_1~0;~E_1~0 := 1; 419541#L873-3 assume 0 == ~E_2~0;~E_2~0 := 1; 419539#L878-3 assume 0 == ~E_3~0;~E_3~0 := 1; 419534#L883-3 assume !(0 == ~E_4~0); 419532#L888-3 assume 0 == ~E_5~0;~E_5~0 := 1; 419530#L893-3 assume 0 == ~E_6~0;~E_6~0 := 1; 419528#L898-3 assume 0 == ~E_7~0;~E_7~0 := 1; 419527#L903-3 assume !(0 == ~E_8~0); 419525#L908-3 havoc activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 419523#L392-27 assume !(1 == ~m_pc~0); 419520#L392-29 is_master_triggered_~__retres1~0 := 0; 419518#L403-9 is_master_triggered_#res := is_master_triggered_~__retres1~0; 419516#L404-9 activate_threads_#t~ret10 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 419513#L1025-27 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 419510#L1025-29 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 419508#L411-27 assume 1 == ~t1_pc~0; 419506#L412-9 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 419507#L422-9 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 419742#L423-9 activate_threads_#t~ret11 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 419497#L1033-27 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 419495#L1033-29 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 419493#L430-27 assume !(1 == ~t2_pc~0); 419491#L430-29 is_transmit2_triggered_~__retres1~2 := 0; 419489#L441-9 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 419487#L442-9 activate_threads_#t~ret12 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 419485#L1041-27 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 419483#L1041-29 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 419481#L449-27 assume 1 == ~t3_pc~0; 419478#L450-9 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 419476#L460-9 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 419474#L461-9 activate_threads_#t~ret13 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 419472#L1049-27 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 419470#L1049-29 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 419468#L468-27 assume !(1 == ~t4_pc~0); 419466#L468-29 is_transmit4_triggered_~__retres1~4 := 0; 419464#L479-9 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 419462#L480-9 activate_threads_#t~ret14 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 419460#L1057-27 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 419458#L1057-29 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 419455#L487-27 assume 1 == ~t5_pc~0; 419452#L488-9 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 419450#L498-9 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 419447#L499-9 activate_threads_#t~ret15 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 419445#L1065-27 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 419441#L1065-29 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 419439#L506-27 assume !(1 == ~t6_pc~0); 419437#L506-29 is_transmit6_triggered_~__retres1~6 := 0; 419435#L517-9 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 419432#L518-9 activate_threads_#t~ret16 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 419430#L1073-27 assume 0 != activate_threads_~tmp___5~0;~t6_st~0 := 0; 419428#L1073-29 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 419426#L525-27 assume !(1 == ~t7_pc~0); 419424#L525-29 is_transmit7_triggered_~__retres1~7 := 0; 419422#L536-9 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 419420#L537-9 activate_threads_#t~ret17 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 419418#L1081-27 assume 0 != activate_threads_~tmp___6~0;~t7_st~0 := 0; 419416#L1081-29 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 419413#L544-27 assume !(1 == ~t8_pc~0); 419410#L544-29 is_transmit8_triggered_~__retres1~8 := 0; 419408#L555-9 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 419406#L556-9 activate_threads_#t~ret18 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 419404#L1089-27 assume !(0 != activate_threads_~tmp___7~0); 419402#L1089-29 assume !(1 == ~M_E~0); 419340#L921-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 419399#L926-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 419397#L931-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 419395#L936-3 assume !(1 == ~T4_E~0); 419393#L941-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 419391#L946-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 419388#L951-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 419386#L956-3 assume !(1 == ~T8_E~0); 419384#L961-3 assume 1 == ~E_1~0;~E_1~0 := 2; 419382#L966-3 assume 1 == ~E_2~0;~E_2~0 := 2; 419380#L971-3 assume 1 == ~E_3~0;~E_3~0 := 2; 419378#L976-3 assume !(1 == ~E_4~0); 419376#L981-3 assume 1 == ~E_5~0;~E_5~0 := 2; 419374#L986-3 assume 1 == ~E_6~0;~E_6~0 := 2; 419372#L991-3 assume 1 == ~E_7~0;~E_7~0 := 2; 419370#L996-3 assume !(1 == ~E_8~0); 419368#L1001-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~9;havoc exists_runnable_thread_~__retres1~9; 419365#L624-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9 := 1; 419363#L671-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~9; 419361#L672-1 start_simulation_#t~ret20 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret20;havoc start_simulation_#t~ret20; 419358#L1281 assume !(0 == start_simulation_~tmp~3); 419359#L1281-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret19, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~9;havoc exists_runnable_thread_~__retres1~9; 434544#L624-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9 := 1; 434542#L671-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~9; 434541#L672-2 stop_simulation_#t~ret19 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret19;havoc stop_simulation_#t~ret19; 434540#L1236 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 434539#L1243 stop_simulation_#res := stop_simulation_~__retres2~0; 434538#L1244 start_simulation_#t~ret21 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret21;havoc start_simulation_#t~ret21; 434537#L1294 assume !(0 != start_simulation_~tmp___0~1); 405367#L1262-1 [2018-11-22 21:21:41,399 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-22 21:21:41,400 INFO L82 PathProgramCache]: Analyzing trace with hash 426104125, now seen corresponding path program 3 times [2018-11-22 21:21:41,400 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-22 21:21:41,400 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-22 21:21:41,401 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-22 21:21:41,401 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-22 21:21:41,401 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-22 21:21:41,415 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-22 21:21:41,420 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-22 21:21:41,442 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-22 21:21:41,443 INFO L82 PathProgramCache]: Analyzing trace with hash -49249369, now seen corresponding path program 1 times [2018-11-22 21:21:41,443 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-22 21:21:41,443 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-22 21:21:41,444 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-22 21:21:41,444 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-22 21:21:41,444 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-22 21:21:41,450 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-22 21:21:41,509 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-22 21:21:41,509 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-22 21:21:41,510 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-11-22 21:21:41,510 INFO L811 eck$LassoCheckResult]: loop already infeasible [2018-11-22 21:21:41,510 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-11-22 21:21:41,510 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-11-22 21:21:41,510 INFO L87 Difference]: Start difference. First operand 37100 states and 51253 transitions. cyclomatic complexity: 14169 Second operand 5 states. [2018-11-22 21:21:41,816 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-22 21:21:41,816 INFO L93 Difference]: Finished difference Result 70692 states and 98696 transitions. [2018-11-22 21:21:41,816 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2018-11-22 21:21:41,817 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 70692 states and 98696 transitions. [2018-11-22 21:21:41,993 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 69816 [2018-11-22 21:21:42,104 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 70692 states to 70692 states and 98696 transitions. [2018-11-22 21:21:42,105 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 70692 [2018-11-22 21:21:42,141 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 70692 [2018-11-22 21:21:42,141 INFO L73 IsDeterministic]: Start isDeterministic. Operand 70692 states and 98696 transitions. [2018-11-22 21:21:42,167 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-22 21:21:42,167 INFO L705 BuchiCegarLoop]: Abstraction has 70692 states and 98696 transitions. [2018-11-22 21:21:42,198 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 70692 states and 98696 transitions. [2018-11-22 21:21:42,441 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 70692 to 36844. [2018-11-22 21:21:42,441 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 36844 states. [2018-11-22 21:21:42,475 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 36844 states to 36844 states and 50524 transitions. [2018-11-22 21:21:42,476 INFO L728 BuchiCegarLoop]: Abstraction has 36844 states and 50524 transitions. [2018-11-22 21:21:42,476 INFO L608 BuchiCegarLoop]: Abstraction has 36844 states and 50524 transitions. [2018-11-22 21:21:42,476 INFO L442 BuchiCegarLoop]: ======== Iteration 23============ [2018-11-22 21:21:42,476 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 36844 states and 50524 transitions. [2018-11-22 21:21:42,541 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 36480 [2018-11-22 21:21:42,541 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-22 21:21:42,541 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-22 21:21:42,543 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-22 21:21:42,543 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-22 21:21:42,543 INFO L794 eck$LassoCheckResult]: Stem: 513479#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2; 513368#L-1 havoc main_#res;havoc main_~__retres1~10;havoc main_~__retres1~10;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 513369#L1225 havoc start_simulation_#t~ret20, start_simulation_#t~ret21, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 513855#L564 assume 1 == ~m_i~0;~m_st~0 := 0; 513404#L571-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 513112#L576-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 513113#L581-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 513859#L586-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 513599#L591-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 513212#L596-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 513213#L601-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 513849#L606-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 513743#L611-1 assume !(0 == ~M_E~0); 513744#L828-1 assume !(0 == ~T1_E~0); 513506#L833-1 assume !(0 == ~T2_E~0); 513227#L838-1 assume !(0 == ~T3_E~0); 513228#L843-1 assume !(0 == ~T4_E~0); 513951#L848-1 assume !(0 == ~T5_E~0); 513752#L853-1 assume !(0 == ~T6_E~0); 513488#L858-1 assume !(0 == ~T7_E~0); 513030#L863-1 assume !(0 == ~T8_E~0); 513031#L868-1 assume !(0 == ~E_1~0); 513702#L873-1 assume !(0 == ~E_2~0); 513574#L878-1 assume !(0 == ~E_3~0); 513336#L883-1 assume !(0 == ~E_4~0); 513337#L888-1 assume !(0 == ~E_5~0); 513819#L893-1 assume !(0 == ~E_6~0); 513546#L898-1 assume !(0 == ~E_7~0); 513465#L903-1 assume !(0 == ~E_8~0); 513173#L908-1 havoc activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 513174#L392 assume !(1 == ~m_pc~0); 513529#L392-2 is_master_triggered_~__retres1~0 := 0; 513532#L403 is_master_triggered_#res := is_master_triggered_~__retres1~0; 514006#L404 activate_threads_#t~ret10 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 513827#L1025 assume !(0 != activate_threads_~tmp~1); 513828#L1025-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 513687#L411 assume !(1 == ~t1_pc~0); 513652#L411-2 is_transmit1_triggered_~__retres1~1 := 0; 513095#L422 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 513096#L423 activate_threads_#t~ret11 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 513192#L1033 assume !(0 != activate_threads_~tmp___0~0); 513412#L1033-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 513413#L430 assume !(1 == ~t2_pc~0); 513839#L430-2 is_transmit2_triggered_~__retres1~2 := 0; 513259#L441 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 513214#L442 activate_threads_#t~ret12 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 513215#L1041 assume !(0 != activate_threads_~tmp___1~0); 514038#L1041-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 514040#L449 assume !(1 == ~t3_pc~0); 513908#L449-2 is_transmit3_triggered_~__retres1~3 := 0; 513557#L460 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 513387#L461 activate_threads_#t~ret13 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 513388#L1049 assume !(0 != activate_threads_~tmp___2~0); 513853#L1049-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 513130#L468 assume !(1 == ~t4_pc~0); 513131#L468-2 is_transmit4_triggered_~__retres1~4 := 0; 513138#L479 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 513538#L480 activate_threads_#t~ret14 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 513472#L1057 assume !(0 != activate_threads_~tmp___3~0); 513473#L1057-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 513321#L487 assume !(1 == ~t5_pc~0); 513091#L487-2 is_transmit5_triggered_~__retres1~5 := 0; 513090#L498 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 513674#L499 activate_threads_#t~ret15 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 513675#L1065 assume !(0 != activate_threads_~tmp___4~0); 514056#L1065-2 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 513487#L506 assume !(1 == ~t6_pc~0); 513483#L506-2 is_transmit6_triggered_~__retres1~6 := 0; 513484#L517 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 513851#L518 activate_threads_#t~ret16 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 513770#L1073 assume !(0 != activate_threads_~tmp___5~0); 513771#L1073-2 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 513601#L525 assume !(1 == ~t7_pc~0); 513602#L525-2 is_transmit7_triggered_~__retres1~7 := 0; 513604#L536 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 514041#L537 activate_threads_#t~ret17 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 513342#L1081 assume !(0 != activate_threads_~tmp___6~0); 513343#L1081-2 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 513344#L544 assume !(1 == ~t8_pc~0); 513621#L544-2 is_transmit8_triggered_~__retres1~8 := 0; 513024#L555 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 513025#L556 activate_threads_#t~ret18 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 513162#L1089 assume !(0 != activate_threads_~tmp___7~0); 513890#L1089-2 assume !(1 == ~M_E~0); 513499#L921-1 assume !(1 == ~T1_E~0); 513223#L926-1 assume !(1 == ~T2_E~0); 513224#L931-1 assume !(1 == ~T3_E~0); 513949#L936-1 assume !(1 == ~T4_E~0); 513760#L941-1 assume !(1 == ~T5_E~0); 513494#L946-1 assume !(1 == ~T6_E~0); 513040#L951-1 assume !(1 == ~T7_E~0); 513041#L956-1 assume !(1 == ~T8_E~0); 513854#L961-1 assume !(1 == ~E_1~0); 513579#L966-1 assume !(1 == ~E_2~0); 513348#L971-1 assume !(1 == ~E_3~0); 513349#L976-1 assume !(1 == ~E_4~0); 513815#L981-1 assume !(1 == ~E_5~0); 513544#L986-1 assume !(1 == ~E_6~0); 513459#L991-1 assume !(1 == ~E_7~0); 513168#L996-1 assume !(1 == ~E_8~0); 513169#L1262-1 [2018-11-22 21:21:42,544 INFO L796 eck$LassoCheckResult]: Loop: 513169#L1262-1 assume !false; 517299#L1263 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret0, eval_#t~nondet1, eval_~tmp_ndt_1~0, eval_#t~nondet2, eval_~tmp_ndt_2~0, eval_#t~nondet3, eval_~tmp_ndt_3~0, eval_#t~nondet4, eval_~tmp_ndt_4~0, eval_#t~nondet5, eval_~tmp_ndt_5~0, eval_#t~nondet6, eval_~tmp_ndt_6~0, eval_#t~nondet7, eval_~tmp_ndt_7~0, eval_#t~nondet8, eval_~tmp_ndt_8~0, eval_#t~nondet9, eval_~tmp_ndt_9~0, eval_~tmp~0;havoc eval_~tmp~0; 517297#L803 assume !false; 517295#L682 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~9;havoc exists_runnable_thread_~__retres1~9; 517293#L624 assume !(0 == ~m_st~0); 517294#L628 assume !(0 == ~t1_st~0); 526374#L632 assume !(0 == ~t2_st~0); 526373#L636 assume !(0 == ~t3_st~0); 526370#L640 assume !(0 == ~t4_st~0); 526301#L644 assume !(0 == ~t5_st~0); 526232#L648 assume !(0 == ~t6_st~0); 526228#L652 assume !(0 == ~t7_st~0); 526158#L656 assume !(0 == ~t8_st~0);exists_runnable_thread_~__retres1~9 := 0; 526152#L671 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~9; 526131#L672 eval_#t~ret0 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret0;havoc eval_#t~ret0; 526127#L686 assume !(0 != eval_~tmp~0); 526058#L818 start_simulation_~kernel_st~0 := 2; 526022#L564-1 start_simulation_~kernel_st~0 := 3; 525878#L828-2 assume !(0 == ~M_E~0); 525868#L828-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 525860#L833-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 525852#L838-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 525844#L843-3 assume !(0 == ~T4_E~0); 525837#L848-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 525833#L853-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 525822#L858-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 525820#L863-3 assume !(0 == ~T8_E~0); 525472#L868-3 assume 0 == ~E_1~0;~E_1~0 := 1; 525458#L873-3 assume 0 == ~E_2~0;~E_2~0 := 1; 525452#L878-3 assume 0 == ~E_3~0;~E_3~0 := 1; 525435#L883-3 assume !(0 == ~E_4~0); 525430#L888-3 assume 0 == ~E_5~0;~E_5~0 := 1; 525425#L893-3 assume 0 == ~E_6~0;~E_6~0 := 1; 525342#L898-3 assume 0 == ~E_7~0;~E_7~0 := 1; 525330#L903-3 assume !(0 == ~E_8~0); 525323#L908-3 havoc activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 525322#L392-27 assume !(1 == ~m_pc~0); 525320#L392-29 is_master_triggered_~__retres1~0 := 0; 525319#L403-9 is_master_triggered_#res := is_master_triggered_~__retres1~0; 525318#L404-9 activate_threads_#t~ret10 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 525317#L1025-27 assume !(0 != activate_threads_~tmp~1); 525316#L1025-29 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 525315#L411-27 assume 1 == ~t1_pc~0; 525313#L412-9 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 525311#L422-9 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 525309#L423-9 activate_threads_#t~ret11 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 525307#L1033-27 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 525306#L1033-29 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 525305#L430-27 assume !(1 == ~t2_pc~0); 525304#L430-29 is_transmit2_triggered_~__retres1~2 := 0; 525303#L441-9 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 525302#L442-9 activate_threads_#t~ret12 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 525301#L1041-27 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 525300#L1041-29 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 525299#L449-27 assume 1 == ~t3_pc~0; 525297#L450-9 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 525296#L460-9 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 525295#L461-9 activate_threads_#t~ret13 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 525294#L1049-27 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 525293#L1049-29 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 525292#L468-27 assume !(1 == ~t4_pc~0); 525291#L468-29 is_transmit4_triggered_~__retres1~4 := 0; 525290#L479-9 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 525289#L480-9 activate_threads_#t~ret14 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 525288#L1057-27 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 525287#L1057-29 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 525286#L487-27 assume 1 == ~t5_pc~0; 525284#L488-9 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 525283#L498-9 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 525282#L499-9 activate_threads_#t~ret15 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 525281#L1065-27 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 525280#L1065-29 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 525279#L506-27 assume !(1 == ~t6_pc~0); 525278#L506-29 is_transmit6_triggered_~__retres1~6 := 0; 525277#L517-9 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 525276#L518-9 activate_threads_#t~ret16 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 525275#L1073-27 assume 0 != activate_threads_~tmp___5~0;~t6_st~0 := 0; 525274#L1073-29 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 525273#L525-27 assume !(1 == ~t7_pc~0); 525272#L525-29 is_transmit7_triggered_~__retres1~7 := 0; 525271#L536-9 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 525270#L537-9 activate_threads_#t~ret17 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 525269#L1081-27 assume 0 != activate_threads_~tmp___6~0;~t7_st~0 := 0; 525268#L1081-29 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 525267#L544-27 assume !(1 == ~t8_pc~0); 525265#L544-29 is_transmit8_triggered_~__retres1~8 := 0; 525264#L555-9 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 525263#L556-9 activate_threads_#t~ret18 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 525262#L1089-27 assume !(0 != activate_threads_~tmp___7~0); 525261#L1089-29 assume !(1 == ~M_E~0); 524205#L921-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 525260#L926-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 525259#L931-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 525258#L936-3 assume !(1 == ~T4_E~0); 525257#L941-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 525256#L946-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 525255#L951-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 525254#L956-3 assume !(1 == ~T8_E~0); 525253#L961-3 assume 1 == ~E_1~0;~E_1~0 := 2; 525252#L966-3 assume 1 == ~E_2~0;~E_2~0 := 2; 525251#L971-3 assume 1 == ~E_3~0;~E_3~0 := 2; 525250#L976-3 assume !(1 == ~E_4~0); 525249#L981-3 assume 1 == ~E_5~0;~E_5~0 := 2; 525248#L986-3 assume 1 == ~E_6~0;~E_6~0 := 2; 525247#L991-3 assume 1 == ~E_7~0;~E_7~0 := 2; 525246#L996-3 assume !(1 == ~E_8~0); 525245#L1001-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~9;havoc exists_runnable_thread_~__retres1~9; 525244#L624-1 assume !(0 == ~m_st~0); 517346#L628-1 assume 0 == ~t1_st~0;exists_runnable_thread_~__retres1~9 := 1; 524087#L671-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~9; 524072#L672-1 start_simulation_#t~ret20 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret20;havoc start_simulation_#t~ret20; 524062#L1281 assume 0 == start_simulation_~tmp~3;start_simulation_~kernel_st~0 := 4;~M_E~0 := 1; 523975#L1115 havoc activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 524057#L392-30 assume 1 == ~m_pc~0; 524055#L393-10 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0 := 1; 524056#L403-10 is_master_triggered_#res := is_master_triggered_~__retres1~0; 524050#L404-10 activate_threads_#t~ret10 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 524051#L1025-30 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 524798#L1025-32 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 524797#L411-30 assume !(1 == ~t1_pc~0); 524794#L411-32 is_transmit1_triggered_~__retres1~1 := 0; 524792#L422-10 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 524791#L423-10 activate_threads_#t~ret11 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 524790#L1033-30 assume !(0 != activate_threads_~tmp___0~0); 524787#L1033-32 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 524785#L430-30 assume !(1 == ~t2_pc~0); 524784#L430-32 is_transmit2_triggered_~__retres1~2 := 0; 524783#L441-10 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 517555#L442-10 activate_threads_#t~ret12 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 517553#L1041-30 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 517549#L1041-32 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 517547#L449-30 assume !(1 == ~t3_pc~0); 517545#L449-32 is_transmit3_triggered_~__retres1~3 := 0; 517542#L460-10 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 517538#L461-10 activate_threads_#t~ret13 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 517536#L1049-30 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 517531#L1049-32 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 517527#L468-30 assume !(1 == ~t4_pc~0); 517526#L468-32 is_transmit4_triggered_~__retres1~4 := 0; 517525#L479-10 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 517523#L480-10 activate_threads_#t~ret14 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 517521#L1057-30 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 517515#L1057-32 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 517513#L487-30 assume !(1 == ~t5_pc~0); 517511#L487-32 is_transmit5_triggered_~__retres1~5 := 0; 517507#L498-10 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 517505#L499-10 activate_threads_#t~ret15 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 517503#L1065-30 assume !(0 != activate_threads_~tmp___4~0); 517501#L1065-32 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 517498#L506-30 assume !(1 == ~t6_pc~0); 517495#L506-32 is_transmit6_triggered_~__retres1~6 := 0; 517493#L517-10 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 517491#L518-10 activate_threads_#t~ret16 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 517489#L1073-30 assume 0 != activate_threads_~tmp___5~0;~t6_st~0 := 0; 517487#L1073-32 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 517485#L525-30 assume !(1 == ~t7_pc~0); 517483#L525-32 is_transmit7_triggered_~__retres1~7 := 0; 517481#L536-10 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 517479#L537-10 activate_threads_#t~ret17 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 517476#L1081-30 assume 0 != activate_threads_~tmp___6~0;~t7_st~0 := 0; 517474#L1081-32 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 517472#L544-30 assume !(1 == ~t8_pc~0); 517468#L544-32 is_transmit8_triggered_~__retres1~8 := 0; 517466#L555-10 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 517464#L556-10 activate_threads_#t~ret18 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 517462#L1089-30 assume !(0 != activate_threads_~tmp___7~0); 517459#L1089-32 assume 1 == ~M_E~0;~M_E~0 := 2; 517457#L1122-1 assume 1 == ~T1_E~0;~T1_E~0 := 2; 517455#L1127-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 517453#L1132-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 517451#L1137-1 assume !(1 == ~T4_E~0); 517449#L1142-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 517447#L1147-1 assume !(1 == ~T6_E~0); 517445#L1152-1 assume 1 == ~T7_E~0;~T7_E~0 := 2; 517443#L1157-1 assume !(1 == ~T8_E~0); 517441#L1162-1 assume 1 == ~E_1~0;~E_1~0 := 2; 517439#L1167-1 assume 1 == ~E_2~0;~E_2~0 := 2; 517437#L1172-1 assume 1 == ~E_3~0;~E_3~0 := 2; 517435#L1177-1 assume !(1 == ~E_4~0); 517433#L1182-1 assume 1 == ~E_5~0;~E_5~0 := 2; 517431#L1187-1 assume !(1 == ~E_6~0); 517429#L1192-1 assume 1 == ~E_7~0;~E_7~0 := 2; 517342#L1197-1 assume !(1 == ~E_8~0); 517337#L1281-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret19, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~9;havoc exists_runnable_thread_~__retres1~9; 517334#L624-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9 := 1; 517332#L671-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~9; 517329#L672-2 stop_simulation_#t~ret19 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret19;havoc stop_simulation_#t~ret19; 517327#L1236 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 517325#L1243 stop_simulation_#res := stop_simulation_~__retres2~0; 517323#L1244 start_simulation_#t~ret21 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret21;havoc start_simulation_#t~ret21; 517321#L1294 assume !(0 != start_simulation_~tmp___0~1); 513169#L1262-1 [2018-11-22 21:21:42,544 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-22 21:21:42,544 INFO L82 PathProgramCache]: Analyzing trace with hash 426104125, now seen corresponding path program 4 times [2018-11-22 21:21:42,544 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-22 21:21:42,544 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-22 21:21:42,545 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-22 21:21:42,545 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-22 21:21:42,545 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-22 21:21:42,551 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-22 21:21:42,556 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-22 21:21:42,580 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-22 21:21:42,581 INFO L82 PathProgramCache]: Analyzing trace with hash -659774967, now seen corresponding path program 1 times [2018-11-22 21:21:42,581 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-22 21:21:42,581 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-22 21:21:42,581 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-22 21:21:42,581 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-22 21:21:42,581 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-22 21:21:42,587 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-22 21:21:42,657 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-22 21:21:42,657 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-22 21:21:42,657 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-22 21:21:42,660 INFO L811 eck$LassoCheckResult]: loop already infeasible [2018-11-22 21:21:42,660 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-22 21:21:42,660 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-22 21:21:42,660 INFO L87 Difference]: Start difference. First operand 36844 states and 50524 transitions. cyclomatic complexity: 13696 Second operand 3 states. [2018-11-22 21:21:43,043 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-22 21:21:43,043 INFO L93 Difference]: Finished difference Result 68699 states and 93754 transitions. [2018-11-22 21:21:43,044 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-22 21:21:43,044 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 68699 states and 93754 transitions. [2018-11-22 21:21:43,220 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 68080 [2018-11-22 21:21:43,307 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 68699 states to 68699 states and 93754 transitions. [2018-11-22 21:21:43,308 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 68699 [2018-11-22 21:21:43,327 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 68699 [2018-11-22 21:21:43,327 INFO L73 IsDeterministic]: Start isDeterministic. Operand 68699 states and 93754 transitions. [2018-11-22 21:21:43,346 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-22 21:21:43,346 INFO L705 BuchiCegarLoop]: Abstraction has 68699 states and 93754 transitions. [2018-11-22 21:21:43,364 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 68699 states and 93754 transitions. [2018-11-22 21:21:43,677 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 68699 to 68635. [2018-11-22 21:21:43,677 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 68635 states. [2018-11-22 21:21:43,744 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 68635 states to 68635 states and 93690 transitions. [2018-11-22 21:21:43,744 INFO L728 BuchiCegarLoop]: Abstraction has 68635 states and 93690 transitions. [2018-11-22 21:21:43,744 INFO L608 BuchiCegarLoop]: Abstraction has 68635 states and 93690 transitions. [2018-11-22 21:21:43,744 INFO L442 BuchiCegarLoop]: ======== Iteration 24============ [2018-11-22 21:21:43,744 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 68635 states and 93690 transitions. [2018-11-22 21:21:43,869 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 68016 [2018-11-22 21:21:43,870 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-22 21:21:43,870 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-22 21:21:43,873 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-22 21:21:43,873 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-22 21:21:43,873 INFO L794 eck$LassoCheckResult]: Stem: 619024#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2; 618917#L-1 havoc main_#res;havoc main_~__retres1~10;havoc main_~__retres1~10;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 618918#L1225 havoc start_simulation_#t~ret20, start_simulation_#t~ret21, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 619410#L564 assume 1 == ~m_i~0;~m_st~0 := 0; 618951#L571-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 618659#L576-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 618660#L581-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 619412#L586-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 619153#L591-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 618761#L596-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 618762#L601-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 619402#L606-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 619294#L611-1 assume !(0 == ~M_E~0); 619295#L828-1 assume !(0 == ~T1_E~0); 619048#L833-1 assume !(0 == ~T2_E~0); 618776#L838-1 assume !(0 == ~T3_E~0); 618777#L843-1 assume !(0 == ~T4_E~0); 619499#L848-1 assume !(0 == ~T5_E~0); 619303#L853-1 assume !(0 == ~T6_E~0); 619034#L858-1 assume !(0 == ~T7_E~0); 618579#L863-1 assume !(0 == ~T8_E~0); 618580#L868-1 assume !(0 == ~E_1~0); 619256#L873-1 assume !(0 == ~E_2~0); 619115#L878-1 assume !(0 == ~E_3~0); 618887#L883-1 assume !(0 == ~E_4~0); 618888#L888-1 assume !(0 == ~E_5~0); 619372#L893-1 assume !(0 == ~E_6~0); 619083#L898-1 assume !(0 == ~E_7~0); 619011#L903-1 assume !(0 == ~E_8~0); 618720#L908-1 havoc activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 618721#L392 assume !(1 == ~m_pc~0); 619066#L392-2 is_master_triggered_~__retres1~0 := 0; 619070#L403 is_master_triggered_#res := is_master_triggered_~__retres1~0; 619549#L404 activate_threads_#t~ret10 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 619381#L1025 assume !(0 != activate_threads_~tmp~1); 619382#L1025-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 619242#L411 assume !(1 == ~t1_pc~0); 619207#L411-2 is_transmit1_triggered_~__retres1~1 := 0; 618643#L422 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 618644#L423 activate_threads_#t~ret11 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 618741#L1033 assume !(0 != activate_threads_~tmp___0~0); 618958#L1033-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 618959#L430 assume !(1 == ~t2_pc~0); 619392#L430-2 is_transmit2_triggered_~__retres1~2 := 0; 618808#L441 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 618763#L442 activate_threads_#t~ret12 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 618764#L1041 assume !(0 != activate_threads_~tmp___1~0); 619578#L1041-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 619579#L449 assume !(1 == ~t3_pc~0); 619460#L449-2 is_transmit3_triggered_~__retres1~3 := 0; 619094#L460 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 618935#L461 activate_threads_#t~ret13 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 618936#L1049 assume !(0 != activate_threads_~tmp___2~0); 619407#L1049-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 618677#L468 assume !(1 == ~t4_pc~0); 618678#L468-2 is_transmit4_triggered_~__retres1~4 := 0; 618685#L479 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 619075#L480 activate_threads_#t~ret14 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 619018#L1057 assume !(0 != activate_threads_~tmp___3~0); 619019#L1057-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 618873#L487 assume !(1 == ~t5_pc~0); 618639#L487-2 is_transmit5_triggered_~__retres1~5 := 0; 618638#L498 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 619229#L499 activate_threads_#t~ret15 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 619230#L1065 assume !(0 != activate_threads_~tmp___4~0); 619592#L1065-2 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 619033#L506 assume !(1 == ~t6_pc~0); 619029#L506-2 is_transmit6_triggered_~__retres1~6 := 0; 619030#L517 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 619404#L518 activate_threads_#t~ret16 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 619321#L1073 assume !(0 != activate_threads_~tmp___5~0); 619322#L1073-2 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 619156#L525 assume !(1 == ~t7_pc~0); 619157#L525-2 is_transmit7_triggered_~__retres1~7 := 0; 619159#L536 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 619580#L537 activate_threads_#t~ret17 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 618893#L1081 assume !(0 != activate_threads_~tmp___6~0); 618894#L1081-2 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 618895#L544 assume !(1 == ~t8_pc~0); 619177#L544-2 is_transmit8_triggered_~__retres1~8 := 0; 618573#L555 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 618574#L556 activate_threads_#t~ret18 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 618708#L1089 assume !(0 != activate_threads_~tmp___7~0); 619445#L1089-2 assume !(1 == ~M_E~0); 619043#L921-1 assume !(1 == ~T1_E~0); 618772#L926-1 assume !(1 == ~T2_E~0); 618773#L931-1 assume !(1 == ~T3_E~0); 619497#L936-1 assume !(1 == ~T4_E~0); 619311#L941-1 assume !(1 == ~T5_E~0); 619040#L946-1 assume !(1 == ~T6_E~0); 618589#L951-1 assume !(1 == ~T7_E~0); 618590#L956-1 assume !(1 == ~T8_E~0); 619409#L961-1 assume !(1 == ~E_1~0); 619120#L966-1 assume !(1 == ~E_2~0); 618899#L971-1 assume !(1 == ~E_3~0); 618900#L976-1 assume !(1 == ~E_4~0); 619367#L981-1 assume !(1 == ~E_5~0); 619081#L986-1 assume !(1 == ~E_6~0); 619005#L991-1 assume !(1 == ~E_7~0); 618714#L996-1 assume !(1 == ~E_8~0); 618715#L1262-1 [2018-11-22 21:21:43,874 INFO L796 eck$LassoCheckResult]: Loop: 618715#L1262-1 assume !false; 624444#L1263 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret0, eval_#t~nondet1, eval_~tmp_ndt_1~0, eval_#t~nondet2, eval_~tmp_ndt_2~0, eval_#t~nondet3, eval_~tmp_ndt_3~0, eval_#t~nondet4, eval_~tmp_ndt_4~0, eval_#t~nondet5, eval_~tmp_ndt_5~0, eval_#t~nondet6, eval_~tmp_ndt_6~0, eval_#t~nondet7, eval_~tmp_ndt_7~0, eval_#t~nondet8, eval_~tmp_ndt_8~0, eval_#t~nondet9, eval_~tmp_ndt_9~0, eval_~tmp~0;havoc eval_~tmp~0; 624439#L803 assume !false; 624433#L682 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~9;havoc exists_runnable_thread_~__retres1~9; 624427#L624 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9 := 1; 624422#L671 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~9; 624416#L672 eval_#t~ret0 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret0;havoc eval_#t~ret0; 624410#L686 assume 0 != eval_~tmp~0; 624402#L686-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0;eval_~tmp_ndt_1~0 := eval_#t~nondet1;havoc eval_#t~nondet1; 624395#L694 assume 0 != eval_~tmp_ndt_1~0;~m_st~0 := 1; 624389#L73 assume 0 == ~m_pc~0; 623777#L100 assume !false; 624379#L85 ~E_1~0 := 1;havoc activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 624374#L392-3 assume !(1 == ~m_pc~0); 624367#L392-5 is_master_triggered_~__retres1~0 := 0; 624362#L403-1 is_master_triggered_#res := is_master_triggered_~__retres1~0; 624357#L404-1 activate_threads_#t~ret10 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 624350#L1025-3 assume !(0 != activate_threads_~tmp~1); 624345#L1025-5 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 624327#L411-3 assume !(1 == ~t1_pc~0); 624323#L411-5 is_transmit1_triggered_~__retres1~1 := 0; 624321#L422-1 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 624319#L423-1 activate_threads_#t~ret11 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 624317#L1033-3 assume !(0 != activate_threads_~tmp___0~0); 624314#L1033-5 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 624312#L430-3 assume !(1 == ~t2_pc~0); 624309#L430-5 is_transmit2_triggered_~__retres1~2 := 0; 624307#L441-1 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 624305#L442-1 activate_threads_#t~ret12 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 624303#L1041-3 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 624301#L1041-5 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 624300#L449-3 assume 1 == ~t3_pc~0; 624289#L450-1 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 624279#L460-1 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 624270#L461-1 activate_threads_#t~ret13 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 624266#L1049-3 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 624261#L1049-5 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 624256#L468-3 assume !(1 == ~t4_pc~0); 624251#L468-5 is_transmit4_triggered_~__retres1~4 := 0; 624246#L479-1 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 624239#L480-1 activate_threads_#t~ret14 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 624233#L1057-3 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 624228#L1057-5 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 624224#L487-3 assume !(1 == ~t5_pc~0); 624219#L487-5 is_transmit5_triggered_~__retres1~5 := 0; 624214#L498-1 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 624211#L499-1 activate_threads_#t~ret15 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 624207#L1065-3 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 624202#L1065-5 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 624197#L506-3 assume !(1 == ~t6_pc~0); 624193#L506-5 is_transmit6_triggered_~__retres1~6 := 0; 624186#L517-1 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 624182#L518-1 activate_threads_#t~ret16 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 624162#L1073-3 assume !(0 != activate_threads_~tmp___5~0); 624150#L1073-5 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 624145#L525-3 assume !(1 == ~t7_pc~0); 624139#L525-5 is_transmit7_triggered_~__retres1~7 := 0; 624133#L536-1 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 624127#L537-1 activate_threads_#t~ret17 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 624120#L1081-3 assume 0 != activate_threads_~tmp___6~0;~t7_st~0 := 0; 624115#L1081-5 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 624101#L544-3 assume !(1 == ~t8_pc~0); 624090#L544-5 is_transmit8_triggered_~__retres1~8 := 0; 624085#L555-1 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 624081#L556-1 activate_threads_#t~ret18 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 624076#L1089-3 assume !(0 != activate_threads_~tmp___7~0); 623775#L1089-5 ~E_1~0 := 2; 623289#L77 assume !false; 622202#L93 ~m_pc~0 := 1;~m_st~0 := 2; 622191#L691 assume !(0 == ~t1_st~0); 622183#L705 assume !(0 == ~t2_st~0); 622172#L719 assume !(0 == ~t3_st~0); 622165#L733 assume !(0 == ~t4_st~0); 622159#L747 assume !(0 == ~t5_st~0); 622152#L761 assume !(0 == ~t6_st~0); 622145#L775 assume !(0 == ~t7_st~0); 624095#L789 assume !(0 == ~t8_st~0); 624086#L803 assume !false; 624082#L682 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~9;havoc exists_runnable_thread_~__retres1~9; 624077#L624 assume !(0 == ~m_st~0); 623357#L628 assume !(0 == ~t1_st~0); 623786#L632 assume !(0 == ~t2_st~0); 623782#L636 assume !(0 == ~t3_st~0); 623783#L640 assume !(0 == ~t4_st~0); 623785#L644 assume !(0 == ~t5_st~0); 623780#L648 assume !(0 == ~t6_st~0); 623781#L652 assume !(0 == ~t7_st~0); 623784#L656 assume !(0 == ~t8_st~0);exists_runnable_thread_~__retres1~9 := 0; 623787#L671 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~9; 623788#L672 eval_#t~ret0 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret0;havoc eval_#t~ret0; 623709#L686 assume !(0 != eval_~tmp~0); 623706#L818 start_simulation_~kernel_st~0 := 2; 623703#L564-1 start_simulation_~kernel_st~0 := 3; 623700#L828-2 assume !(0 == ~M_E~0); 623696#L828-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 623693#L833-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 623690#L838-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 623687#L843-3 assume !(0 == ~T4_E~0); 623683#L848-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 623680#L853-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 623677#L858-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 623674#L863-3 assume !(0 == ~T8_E~0); 623671#L868-3 assume 0 == ~E_1~0;~E_1~0 := 1; 623668#L873-3 assume 0 == ~E_2~0;~E_2~0 := 1; 623665#L878-3 assume 0 == ~E_3~0;~E_3~0 := 1; 623661#L883-3 assume !(0 == ~E_4~0); 623658#L888-3 assume 0 == ~E_5~0;~E_5~0 := 1; 623655#L893-3 assume 0 == ~E_6~0;~E_6~0 := 1; 623652#L898-3 assume 0 == ~E_7~0;~E_7~0 := 1; 623649#L903-3 assume !(0 == ~E_8~0); 623644#L908-3 havoc activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 623640#L392-27 assume 1 == ~m_pc~0; 623638#L393-9 assume !(1 == ~M_E~0); 623637#L392-29 is_master_triggered_~__retres1~0 := 0; 623636#L403-9 is_master_triggered_#res := is_master_triggered_~__retres1~0; 623635#L404-9 activate_threads_#t~ret10 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 623634#L1025-27 assume !(0 != activate_threads_~tmp~1); 623633#L1025-29 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 623632#L411-27 assume 1 == ~t1_pc~0; 623631#L412-9 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 623629#L422-9 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 623101#L423-9 activate_threads_#t~ret11 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 623099#L1033-27 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 623098#L1033-29 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 623097#L430-27 assume !(1 == ~t2_pc~0); 623096#L430-29 is_transmit2_triggered_~__retres1~2 := 0; 623095#L441-9 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 623094#L442-9 activate_threads_#t~ret12 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 623091#L1041-27 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 623089#L1041-29 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 623087#L449-27 assume !(1 == ~t3_pc~0); 623085#L449-29 is_transmit3_triggered_~__retres1~3 := 0; 623082#L460-9 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 623080#L461-9 activate_threads_#t~ret13 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 623076#L1049-27 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 623073#L1049-29 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 623070#L468-27 assume !(1 == ~t4_pc~0); 623067#L468-29 is_transmit4_triggered_~__retres1~4 := 0; 623065#L479-9 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 623063#L480-9 activate_threads_#t~ret14 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 623059#L1057-27 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 623056#L1057-29 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 623054#L487-27 assume 1 == ~t5_pc~0; 623051#L488-9 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 623049#L498-9 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 623047#L499-9 activate_threads_#t~ret15 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 623045#L1065-27 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 623043#L1065-29 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 623041#L506-27 assume !(1 == ~t6_pc~0); 623039#L506-29 is_transmit6_triggered_~__retres1~6 := 0; 623033#L517-9 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 623027#L518-9 activate_threads_#t~ret16 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 623022#L1073-27 assume 0 != activate_threads_~tmp___5~0;~t6_st~0 := 0; 623017#L1073-29 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 623012#L525-27 assume !(1 == ~t7_pc~0); 623009#L525-29 is_transmit7_triggered_~__retres1~7 := 0; 623006#L536-9 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 623002#L537-9 activate_threads_#t~ret17 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 622998#L1081-27 assume 0 != activate_threads_~tmp___6~0;~t7_st~0 := 0; 622994#L1081-29 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 622990#L544-27 assume !(1 == ~t8_pc~0); 622986#L544-29 is_transmit8_triggered_~__retres1~8 := 0; 622984#L555-9 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 622981#L556-9 activate_threads_#t~ret18 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 622979#L1089-27 assume !(0 != activate_threads_~tmp___7~0); 622977#L1089-29 assume !(1 == ~M_E~0); 622507#L921-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 622971#L926-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 622968#L931-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 622964#L936-3 assume !(1 == ~T4_E~0); 622961#L941-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 622958#L946-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 622955#L951-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 622952#L956-3 assume !(1 == ~T8_E~0); 622948#L961-3 assume 1 == ~E_1~0;~E_1~0 := 2; 622944#L966-3 assume 1 == ~E_2~0;~E_2~0 := 2; 622940#L971-3 assume 1 == ~E_3~0;~E_3~0 := 2; 622936#L976-3 assume !(1 == ~E_4~0); 622933#L981-3 assume 1 == ~E_5~0;~E_5~0 := 2; 622931#L986-3 assume 1 == ~E_6~0;~E_6~0 := 2; 622929#L991-3 assume 1 == ~E_7~0;~E_7~0 := 2; 622927#L996-3 assume !(1 == ~E_8~0); 622925#L1001-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~9;havoc exists_runnable_thread_~__retres1~9; 622923#L624-1 assume !(0 == ~m_st~0); 621412#L628-1 assume 0 == ~t1_st~0;exists_runnable_thread_~__retres1~9 := 1; 622625#L671-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~9; 622622#L672-1 start_simulation_#t~ret20 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret20;havoc start_simulation_#t~ret20; 621413#L1281 assume 0 == start_simulation_~tmp~3;start_simulation_~kernel_st~0 := 4;~M_E~0 := 1; 621410#L1115 havoc activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 621407#L392-30 assume 1 == ~m_pc~0; 621404#L393-10 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0 := 1; 621401#L403-10 is_master_triggered_#res := is_master_triggered_~__retres1~0; 621400#L404-10 activate_threads_#t~ret10 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 621388#L1025-30 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 621387#L1025-32 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 621386#L411-30 assume 1 == ~t1_pc~0; 621385#L412-10 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 621383#L422-10 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 621381#L423-10 activate_threads_#t~ret11 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 621378#L1033-30 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 621377#L1033-32 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 621375#L430-30 assume !(1 == ~t2_pc~0); 621374#L430-32 is_transmit2_triggered_~__retres1~2 := 0; 621373#L441-10 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 621370#L442-10 activate_threads_#t~ret12 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 621367#L1041-30 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 621365#L1041-32 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 621363#L449-30 assume 1 == ~t3_pc~0; 621361#L450-10 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 621360#L460-10 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 621357#L461-10 activate_threads_#t~ret13 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 621354#L1049-30 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 621352#L1049-32 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 621350#L468-30 assume !(1 == ~t4_pc~0); 621348#L468-32 is_transmit4_triggered_~__retres1~4 := 0; 621344#L479-10 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 621342#L480-10 activate_threads_#t~ret14 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 621338#L1057-30 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 621336#L1057-32 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 621334#L487-30 assume 1 == ~t5_pc~0; 621331#L488-10 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 621328#L498-10 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 621326#L499-10 activate_threads_#t~ret15 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 621324#L1065-30 assume !(0 != activate_threads_~tmp___4~0); 621322#L1065-32 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 621320#L506-30 assume !(1 == ~t6_pc~0); 621318#L506-32 is_transmit6_triggered_~__retres1~6 := 0; 621316#L517-10 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 621314#L518-10 activate_threads_#t~ret16 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 621312#L1073-30 assume 0 != activate_threads_~tmp___5~0;~t6_st~0 := 0; 621309#L1073-32 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 621307#L525-30 assume !(1 == ~t7_pc~0); 621305#L525-32 is_transmit7_triggered_~__retres1~7 := 0; 621303#L536-10 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 621301#L537-10 activate_threads_#t~ret17 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 621299#L1081-30 assume 0 != activate_threads_~tmp___6~0;~t7_st~0 := 0; 621297#L1081-32 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 621295#L544-30 assume !(1 == ~t8_pc~0); 621292#L544-32 is_transmit8_triggered_~__retres1~8 := 0; 621290#L555-10 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 621288#L556-10 activate_threads_#t~ret18 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 621286#L1089-30 assume !(0 != activate_threads_~tmp___7~0); 621282#L1089-32 assume !(1 == ~M_E~0); 621280#L1122-1 assume 1 == ~T1_E~0;~T1_E~0 := 2; 621278#L1127-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 621276#L1132-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 621274#L1137-1 assume !(1 == ~T4_E~0); 621272#L1142-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 621270#L1147-1 assume !(1 == ~T6_E~0); 621268#L1152-1 assume 1 == ~T7_E~0;~T7_E~0 := 2; 621266#L1157-1 assume !(1 == ~T8_E~0); 621264#L1162-1 assume 1 == ~E_1~0;~E_1~0 := 2; 621262#L1167-1 assume 1 == ~E_2~0;~E_2~0 := 2; 621260#L1172-1 assume 1 == ~E_3~0;~E_3~0 := 2; 621258#L1177-1 assume !(1 == ~E_4~0); 621256#L1182-1 assume 1 == ~E_5~0;~E_5~0 := 2; 621254#L1187-1 assume !(1 == ~E_6~0); 621252#L1192-1 assume 1 == ~E_7~0;~E_7~0 := 2; 621250#L1197-1 assume !(1 == ~E_8~0); 621245#L1281-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret19, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~9;havoc exists_runnable_thread_~__retres1~9; 621242#L624-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9 := 1; 621240#L671-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~9; 621238#L672-2 stop_simulation_#t~ret19 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret19;havoc stop_simulation_#t~ret19; 621236#L1236 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 621235#L1243 stop_simulation_#res := stop_simulation_~__retres2~0; 621234#L1244 start_simulation_#t~ret21 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret21;havoc start_simulation_#t~ret21; 621233#L1294 assume !(0 != start_simulation_~tmp___0~1); 621231#L1262-1 assume !false; 621202#L1263 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret0, eval_#t~nondet1, eval_~tmp_ndt_1~0, eval_#t~nondet2, eval_~tmp_ndt_2~0, eval_#t~nondet3, eval_~tmp_ndt_3~0, eval_#t~nondet4, eval_~tmp_ndt_4~0, eval_#t~nondet5, eval_~tmp_ndt_5~0, eval_#t~nondet6, eval_~tmp_ndt_6~0, eval_#t~nondet7, eval_~tmp_ndt_7~0, eval_#t~nondet8, eval_~tmp_ndt_8~0, eval_#t~nondet9, eval_~tmp_ndt_9~0, eval_~tmp~0;havoc eval_~tmp~0; 621200#L803 assume !false; 621197#L682 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~9;havoc exists_runnable_thread_~__retres1~9; 621194#L624 assume !(0 == ~m_st~0); 621195#L628 assume !(0 == ~t1_st~0); 622357#L632 assume !(0 == ~t2_st~0); 622354#L636 assume !(0 == ~t3_st~0); 622355#L640 assume !(0 == ~t4_st~0); 622356#L644 assume !(0 == ~t5_st~0); 622352#L648 assume !(0 == ~t6_st~0); 622353#L652 assume !(0 == ~t7_st~0); 622351#L656 assume !(0 == ~t8_st~0);exists_runnable_thread_~__retres1~9 := 0; 622346#L671 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~9; 622341#L672 eval_#t~ret0 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret0;havoc eval_#t~ret0; 622336#L686 assume !(0 != eval_~tmp~0); 622330#L818 start_simulation_~kernel_st~0 := 2; 622323#L564-1 start_simulation_~kernel_st~0 := 3; 622317#L828-2 assume 0 == ~M_E~0;~M_E~0 := 1; 622311#L828-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 622305#L833-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 622299#L838-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 622294#L843-3 assume !(0 == ~T4_E~0); 622288#L848-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 622282#L853-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 622276#L858-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 622270#L863-3 assume !(0 == ~T8_E~0); 622265#L868-3 assume 0 == ~E_1~0;~E_1~0 := 1; 622260#L873-3 assume 0 == ~E_2~0;~E_2~0 := 1; 622255#L878-3 assume 0 == ~E_3~0;~E_3~0 := 1; 622250#L883-3 assume !(0 == ~E_4~0); 622245#L888-3 assume 0 == ~E_5~0;~E_5~0 := 1; 622239#L893-3 assume 0 == ~E_6~0;~E_6~0 := 1; 622234#L898-3 assume 0 == ~E_7~0;~E_7~0 := 1; 622228#L903-3 assume !(0 == ~E_8~0); 622222#L908-3 havoc activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 622216#L392-27 assume 1 == ~m_pc~0; 622208#L393-9 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0 := 1; 622200#L403-9 is_master_triggered_#res := is_master_triggered_~__retres1~0; 622188#L404-9 activate_threads_#t~ret10 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 622179#L1025-27 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 622169#L1025-29 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 622162#L411-27 assume 1 == ~t1_pc~0; 622155#L412-9 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 622150#L422-9 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 622142#L423-9 activate_threads_#t~ret11 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 622137#L1033-27 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 622132#L1033-29 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 622128#L430-27 assume !(1 == ~t2_pc~0); 622125#L430-29 is_transmit2_triggered_~__retres1~2 := 0; 622122#L441-9 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 622119#L442-9 activate_threads_#t~ret12 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 622116#L1041-27 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 622113#L1041-29 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 622110#L449-27 assume !(1 == ~t3_pc~0); 622107#L449-29 is_transmit3_triggered_~__retres1~3 := 0; 622103#L460-9 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 622099#L461-9 activate_threads_#t~ret13 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 622096#L1049-27 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 622093#L1049-29 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 622090#L468-27 assume !(1 == ~t4_pc~0); 622087#L468-29 is_transmit4_triggered_~__retres1~4 := 0; 622084#L479-9 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 622081#L480-9 activate_threads_#t~ret14 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 622077#L1057-27 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 622074#L1057-29 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 622071#L487-27 assume 1 == ~t5_pc~0; 622067#L488-9 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 622065#L498-9 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 621637#L499-9 activate_threads_#t~ret15 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 621583#L1065-27 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 621480#L1065-29 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 621473#L506-27 assume !(1 == ~t6_pc~0); 621472#L506-29 is_transmit6_triggered_~__retres1~6 := 0; 621471#L517-9 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 621470#L518-9 activate_threads_#t~ret16 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 621469#L1073-27 assume 0 != activate_threads_~tmp___5~0;~t6_st~0 := 0; 621468#L1073-29 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 621467#L525-27 assume !(1 == ~t7_pc~0); 621465#L525-29 is_transmit7_triggered_~__retres1~7 := 0; 621463#L536-9 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 621461#L537-9 activate_threads_#t~ret17 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 621459#L1081-27 assume 0 != activate_threads_~tmp___6~0;~t7_st~0 := 0; 621457#L1081-29 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 621455#L544-27 assume !(1 == ~t8_pc~0); 621452#L544-29 is_transmit8_triggered_~__retres1~8 := 0; 621450#L555-9 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 621448#L556-9 activate_threads_#t~ret18 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 621446#L1089-27 assume !(0 != activate_threads_~tmp___7~0); 621443#L1089-29 assume 1 == ~M_E~0;~M_E~0 := 2; 621441#L921-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 621439#L926-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 621437#L931-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 621435#L936-3 assume !(1 == ~T4_E~0); 621433#L941-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 621430#L946-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 621428#L951-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 621426#L956-3 assume !(1 == ~T8_E~0); 621425#L961-3 assume 1 == ~E_1~0;~E_1~0 := 2; 621424#L966-3 assume 1 == ~E_2~0;~E_2~0 := 2; 621423#L971-3 assume 1 == ~E_3~0;~E_3~0 := 2; 621422#L976-3 assume !(1 == ~E_4~0); 621421#L981-3 assume 1 == ~E_5~0;~E_5~0 := 2; 621419#L986-3 assume 1 == ~E_6~0;~E_6~0 := 2; 621418#L991-3 assume 1 == ~E_7~0;~E_7~0 := 2; 621417#L996-3 assume !(1 == ~E_8~0); 621415#L1001-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~9;havoc exists_runnable_thread_~__retres1~9; 621411#L624-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9 := 1; 621409#L671-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~9; 621406#L672-1 start_simulation_#t~ret20 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret20;havoc start_simulation_#t~ret20; 621402#L1281 assume 0 == start_simulation_~tmp~3;start_simulation_~kernel_st~0 := 4;~M_E~0 := 1; 621249#L1115 havoc activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 621398#L392-30 assume !(1 == ~m_pc~0); 621399#L392-32 is_master_triggered_~__retres1~0 := 0; 624167#L403-10 is_master_triggered_#res := is_master_triggered_~__retres1~0; 624165#L404-10 activate_threads_#t~ret10 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 624163#L1025-30 assume !(0 != activate_threads_~tmp~1); 624151#L1025-32 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 624146#L411-30 assume !(1 == ~t1_pc~0); 624141#L411-32 is_transmit1_triggered_~__retres1~1 := 0; 624135#L422-10 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 624129#L423-10 activate_threads_#t~ret11 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 624122#L1033-30 assume !(0 != activate_threads_~tmp___0~0); 624116#L1033-32 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 624111#L430-30 assume !(1 == ~t2_pc~0); 624110#L430-32 is_transmit2_triggered_~__retres1~2 := 0; 624109#L441-10 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 624107#L442-10 activate_threads_#t~ret12 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 624097#L1041-30 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 624087#L1041-32 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 624083#L449-30 assume !(1 == ~t3_pc~0); 624079#L449-32 is_transmit3_triggered_~__retres1~3 := 0; 624074#L460-10 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 624073#L461-10 activate_threads_#t~ret13 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 624072#L1049-30 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 624071#L1049-32 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 624070#L468-30 assume !(1 == ~t4_pc~0); 624069#L468-32 is_transmit4_triggered_~__retres1~4 := 0; 624068#L479-10 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 624066#L480-10 activate_threads_#t~ret14 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 624065#L1057-30 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 624064#L1057-32 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 624063#L487-30 assume 1 == ~t5_pc~0; 624061#L488-10 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 624059#L498-10 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 624058#L499-10 activate_threads_#t~ret15 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 624056#L1065-30 assume !(0 != activate_threads_~tmp___4~0); 624054#L1065-32 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 624052#L506-30 assume !(1 == ~t6_pc~0); 624050#L506-32 is_transmit6_triggered_~__retres1~6 := 0; 624046#L517-10 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 624044#L518-10 activate_threads_#t~ret16 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 624042#L1073-30 assume 0 != activate_threads_~tmp___5~0;~t6_st~0 := 0; 624040#L1073-32 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 624037#L525-30 assume !(1 == ~t7_pc~0); 624035#L525-32 is_transmit7_triggered_~__retres1~7 := 0; 624033#L536-10 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 624031#L537-10 activate_threads_#t~ret17 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 624029#L1081-30 assume 0 != activate_threads_~tmp___6~0;~t7_st~0 := 0; 624027#L1081-32 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 624025#L544-30 assume !(1 == ~t8_pc~0); 624022#L544-32 is_transmit8_triggered_~__retres1~8 := 0; 624020#L555-10 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 624019#L556-10 activate_threads_#t~ret18 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 624018#L1089-30 assume !(0 != activate_threads_~tmp___7~0); 624016#L1089-32 assume 1 == ~M_E~0;~M_E~0 := 2; 624017#L1122-1 assume 1 == ~T1_E~0;~T1_E~0 := 2; 624564#L1127-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 624562#L1132-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 624560#L1137-1 assume !(1 == ~T4_E~0); 624558#L1142-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 624556#L1147-1 assume !(1 == ~T6_E~0); 624554#L1152-1 assume 1 == ~T7_E~0;~T7_E~0 := 2; 624551#L1157-1 assume !(1 == ~T8_E~0); 624549#L1162-1 assume 1 == ~E_1~0;~E_1~0 := 2; 624547#L1167-1 assume 1 == ~E_2~0;~E_2~0 := 2; 624546#L1172-1 assume 1 == ~E_3~0;~E_3~0 := 2; 624543#L1177-1 assume !(1 == ~E_4~0); 624541#L1182-1 assume 1 == ~E_5~0;~E_5~0 := 2; 624539#L1187-1 assume !(1 == ~E_6~0); 624537#L1192-1 assume 1 == ~E_7~0;~E_7~0 := 2; 624535#L1197-1 assume !(1 == ~E_8~0); 624533#L1281-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret19, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~9;havoc exists_runnable_thread_~__retres1~9; 624530#L624-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9 := 1; 624528#L671-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~9; 624526#L672-2 stop_simulation_#t~ret19 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret19;havoc stop_simulation_#t~ret19; 624487#L1236 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 624478#L1243 stop_simulation_#res := stop_simulation_~__retres2~0; 624470#L1244 start_simulation_#t~ret21 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret21;havoc start_simulation_#t~ret21; 624461#L1294 assume !(0 != start_simulation_~tmp___0~1); 618715#L1262-1 [2018-11-22 21:21:43,874 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-22 21:21:43,875 INFO L82 PathProgramCache]: Analyzing trace with hash 426104125, now seen corresponding path program 5 times [2018-11-22 21:21:43,875 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-22 21:21:43,875 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-22 21:21:43,876 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-22 21:21:43,876 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-22 21:21:43,876 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-22 21:21:43,881 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-22 21:21:43,886 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-22 21:21:43,910 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-22 21:21:43,910 INFO L82 PathProgramCache]: Analyzing trace with hash -1294799793, now seen corresponding path program 1 times [2018-11-22 21:21:43,910 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-22 21:21:43,910 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-22 21:21:43,911 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-22 21:21:43,911 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-22 21:21:43,911 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-22 21:21:43,920 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-22 21:21:44,279 INFO L134 CoverageAnalysis]: Checked inductivity of 199 backedges. 14 proven. 0 refuted. 0 times theorem prover too weak. 185 trivial. 0 not checked. [2018-11-22 21:21:44,279 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-22 21:21:44,280 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-11-22 21:21:44,280 INFO L811 eck$LassoCheckResult]: loop already infeasible [2018-11-22 21:21:44,280 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-11-22 21:21:44,280 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-11-22 21:21:44,281 INFO L87 Difference]: Start difference. First operand 68635 states and 93690 transitions. cyclomatic complexity: 25087 Second operand 5 states. [2018-11-22 21:21:44,619 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-22 21:21:44,620 INFO L93 Difference]: Finished difference Result 130379 states and 177745 transitions. [2018-11-22 21:21:44,620 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2018-11-22 21:21:44,620 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 130379 states and 177745 transitions. [2018-11-22 21:21:44,948 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 129376 [2018-11-22 21:21:45,153 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 130379 states to 130379 states and 177745 transitions. [2018-11-22 21:21:45,153 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 130379 [2018-11-22 21:21:45,211 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 130379 [2018-11-22 21:21:45,211 INFO L73 IsDeterministic]: Start isDeterministic. Operand 130379 states and 177745 transitions. [2018-11-22 21:21:45,260 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-22 21:21:45,260 INFO L705 BuchiCegarLoop]: Abstraction has 130379 states and 177745 transitions. [2018-11-22 21:21:45,314 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 130379 states and 177745 transitions. [2018-11-22 21:21:45,756 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 130379 to 69955. [2018-11-22 21:21:45,756 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 69955 states. [2018-11-22 21:21:45,823 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 69955 states to 69955 states and 94633 transitions. [2018-11-22 21:21:45,824 INFO L728 BuchiCegarLoop]: Abstraction has 69955 states and 94633 transitions. [2018-11-22 21:21:45,824 INFO L608 BuchiCegarLoop]: Abstraction has 69955 states and 94633 transitions. [2018-11-22 21:21:45,824 INFO L442 BuchiCegarLoop]: ======== Iteration 25============ [2018-11-22 21:21:45,824 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 69955 states and 94633 transitions. [2018-11-22 21:21:45,954 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 69336 [2018-11-22 21:21:45,954 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-22 21:21:45,954 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-22 21:21:45,957 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-22 21:21:45,957 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-22 21:21:45,957 INFO L794 eck$LassoCheckResult]: Stem: 818074#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2; 817959#L-1 havoc main_#res;havoc main_~__retres1~10;havoc main_~__retres1~10;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 817960#L1225 havoc start_simulation_#t~ret20, start_simulation_#t~ret21, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 818503#L564 assume 1 == ~m_i~0;~m_st~0 := 0; 817998#L571-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 817689#L576-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 817690#L581-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 818507#L586-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 818207#L591-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 817796#L596-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 817797#L601-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 818495#L606-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 818361#L611-1 assume !(0 == ~M_E~0); 818362#L828-1 assume !(0 == ~T1_E~0); 818100#L833-1 assume !(0 == ~T2_E~0); 817811#L838-1 assume !(0 == ~T3_E~0); 817812#L843-1 assume !(0 == ~T4_E~0); 818593#L848-1 assume !(0 == ~T5_E~0); 818371#L853-1 assume !(0 == ~T6_E~0); 818084#L858-1 assume !(0 == ~T7_E~0); 817607#L863-1 assume !(0 == ~T8_E~0); 817608#L868-1 assume !(0 == ~E_1~0); 818319#L873-1 assume !(0 == ~E_2~0); 818171#L878-1 assume !(0 == ~E_3~0); 817924#L883-1 assume !(0 == ~E_4~0); 817925#L888-1 assume !(0 == ~E_5~0); 818454#L893-1 assume !(0 == ~E_6~0); 818138#L898-1 assume !(0 == ~E_7~0); 818064#L903-1 assume !(0 == ~E_8~0); 817751#L908-1 havoc activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 817752#L392 assume !(1 == ~m_pc~0); 818121#L392-2 is_master_triggered_~__retres1~0 := 0; 818124#L403 is_master_triggered_#res := is_master_triggered_~__retres1~0; 818642#L404 activate_threads_#t~ret10 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 818469#L1025 assume !(0 != activate_threads_~tmp~1); 818470#L1025-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 818305#L411 assume !(1 == ~t1_pc~0); 818271#L411-2 is_transmit1_triggered_~__retres1~1 := 0; 817674#L422 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 817675#L423 activate_threads_#t~ret11 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 817776#L1033 assume !(0 != activate_threads_~tmp___0~0); 818006#L1033-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 818007#L430 assume !(1 == ~t2_pc~0); 818483#L430-2 is_transmit2_triggered_~__retres1~2 := 0; 817847#L441 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 817798#L442 activate_threads_#t~ret12 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 817799#L1041 assume !(0 != activate_threads_~tmp___1~0); 818674#L1041-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 818675#L449 assume !(1 == ~t3_pc~0); 818556#L449-2 is_transmit3_triggered_~__retres1~3 := 0; 818153#L460 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 817980#L461 activate_threads_#t~ret13 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 817981#L1049 assume !(0 != activate_threads_~tmp___2~0); 818500#L1049-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 817710#L468 assume !(1 == ~t4_pc~0); 817711#L468-2 is_transmit4_triggered_~__retres1~4 := 0; 817716#L479 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 818130#L480 activate_threads_#t~ret14 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 818069#L1057 assume !(0 != activate_threads_~tmp___3~0); 818070#L1057-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 817910#L487 assume !(1 == ~t5_pc~0); 817667#L487-2 is_transmit5_triggered_~__retres1~5 := 0; 817666#L498 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 818292#L499 activate_threads_#t~ret15 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 818293#L1065 assume !(0 != activate_threads_~tmp___4~0); 818688#L1065-2 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 818083#L506 assume !(1 == ~t6_pc~0); 818079#L506-2 is_transmit6_triggered_~__retres1~6 := 0; 818080#L517 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 818497#L518 activate_threads_#t~ret16 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 818391#L1073 assume !(0 != activate_threads_~tmp___5~0); 818392#L1073-2 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 818210#L525 assume !(1 == ~t7_pc~0); 818211#L525-2 is_transmit7_triggered_~__retres1~7 := 0; 818214#L536 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 818676#L537 activate_threads_#t~ret17 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 817930#L1081 assume !(0 != activate_threads_~tmp___6~0); 817931#L1081-2 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 817932#L544 assume !(1 == ~t8_pc~0); 818238#L544-2 is_transmit8_triggered_~__retres1~8 := 0; 817601#L555 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 817602#L556 activate_threads_#t~ret18 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 817739#L1089 assume !(0 != activate_threads_~tmp___7~0); 818539#L1089-2 assume !(1 == ~M_E~0); 818095#L921-1 assume !(1 == ~T1_E~0); 817807#L926-1 assume !(1 == ~T2_E~0); 817808#L931-1 assume !(1 == ~T3_E~0); 818591#L936-1 assume !(1 == ~T4_E~0); 818379#L941-1 assume !(1 == ~T5_E~0); 818092#L946-1 assume !(1 == ~T6_E~0); 817617#L951-1 assume !(1 == ~T7_E~0); 817618#L956-1 assume !(1 == ~T8_E~0); 818502#L961-1 assume !(1 == ~E_1~0); 818176#L966-1 assume !(1 == ~E_2~0); 817936#L971-1 assume !(1 == ~E_3~0); 817937#L976-1 assume !(1 == ~E_4~0); 818450#L981-1 assume !(1 == ~E_5~0); 818136#L986-1 assume !(1 == ~E_6~0); 818056#L991-1 assume !(1 == ~E_7~0); 817745#L996-1 assume !(1 == ~E_8~0); 817746#L1262-1 [2018-11-22 21:21:45,958 INFO L796 eck$LassoCheckResult]: Loop: 817746#L1262-1 assume !false; 828699#L1263 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret0, eval_#t~nondet1, eval_~tmp_ndt_1~0, eval_#t~nondet2, eval_~tmp_ndt_2~0, eval_#t~nondet3, eval_~tmp_ndt_3~0, eval_#t~nondet4, eval_~tmp_ndt_4~0, eval_#t~nondet5, eval_~tmp_ndt_5~0, eval_#t~nondet6, eval_~tmp_ndt_6~0, eval_#t~nondet7, eval_~tmp_ndt_7~0, eval_#t~nondet8, eval_~tmp_ndt_8~0, eval_#t~nondet9, eval_~tmp_ndt_9~0, eval_~tmp~0;havoc eval_~tmp~0; 828697#L803 assume !false; 828695#L682 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~9;havoc exists_runnable_thread_~__retres1~9; 828692#L624 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9 := 1; 828690#L671 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~9; 828688#L672 eval_#t~ret0 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret0;havoc eval_#t~ret0; 828686#L686 assume 0 != eval_~tmp~0; 828683#L686-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0;eval_~tmp_ndt_1~0 := eval_#t~nondet1;havoc eval_#t~nondet1; 828681#L694 assume 0 != eval_~tmp_ndt_1~0;~m_st~0 := 1; 828678#L73 assume 0 == ~m_pc~0; 828174#L100 assume !false; 828640#L85 ~E_1~0 := 1;havoc activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 828632#L392-3 assume !(1 == ~m_pc~0); 828627#L392-5 is_master_triggered_~__retres1~0 := 0; 828428#L403-1 is_master_triggered_#res := is_master_triggered_~__retres1~0; 828423#L404-1 activate_threads_#t~ret10 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 828422#L1025-3 assume !(0 != activate_threads_~tmp~1); 828421#L1025-5 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 828420#L411-3 assume !(1 == ~t1_pc~0); 828417#L411-5 is_transmit1_triggered_~__retres1~1 := 0; 828415#L422-1 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 828414#L423-1 activate_threads_#t~ret11 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 828413#L1033-3 assume !(0 != activate_threads_~tmp___0~0); 828410#L1033-5 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 828408#L430-3 assume !(1 == ~t2_pc~0); 828406#L430-5 is_transmit2_triggered_~__retres1~2 := 0; 828404#L441-1 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 828402#L442-1 activate_threads_#t~ret12 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 828400#L1041-3 assume !(0 != activate_threads_~tmp___1~0); 828398#L1041-5 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 828396#L449-3 assume !(1 == ~t3_pc~0); 828393#L449-5 is_transmit3_triggered_~__retres1~3 := 0; 828391#L460-1 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 828389#L461-1 activate_threads_#t~ret13 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 828387#L1049-3 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 828385#L1049-5 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 828383#L468-3 assume !(1 == ~t4_pc~0); 828381#L468-5 is_transmit4_triggered_~__retres1~4 := 0; 828380#L479-1 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 828378#L480-1 activate_threads_#t~ret14 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 828377#L1057-3 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 828369#L1057-5 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 828367#L487-3 assume !(1 == ~t5_pc~0); 828364#L487-5 is_transmit5_triggered_~__retres1~5 := 0; 828362#L498-1 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 828360#L499-1 activate_threads_#t~ret15 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 828358#L1065-3 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 828211#L1065-5 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 828210#L506-3 assume !(1 == ~t6_pc~0); 828209#L506-5 is_transmit6_triggered_~__retres1~6 := 0; 828208#L517-1 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 828207#L518-1 activate_threads_#t~ret16 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 828206#L1073-3 assume !(0 != activate_threads_~tmp___5~0); 828205#L1073-5 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 828203#L525-3 assume !(1 == ~t7_pc~0); 828201#L525-5 is_transmit7_triggered_~__retres1~7 := 0; 828200#L536-1 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 828199#L537-1 activate_threads_#t~ret17 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 828198#L1081-3 assume 0 != activate_threads_~tmp___6~0;~t7_st~0 := 0; 828196#L1081-5 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 828194#L544-3 assume !(1 == ~t8_pc~0); 828191#L544-5 is_transmit8_triggered_~__retres1~8 := 0; 828190#L555-1 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 828188#L556-1 activate_threads_#t~ret18 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 828186#L1089-3 assume !(0 != activate_threads_~tmp___7~0); 828172#L1089-5 ~E_1~0 := 2; 828170#L77 assume !false; 828168#L93 ~m_pc~0 := 1;~m_st~0 := 2; 827947#L691 assume !(0 == ~t1_st~0); 828085#L705 assume !(0 == ~t2_st~0); 828075#L719 assume !(0 == ~t3_st~0); 828055#L733 assume !(0 == ~t4_st~0); 828044#L747 assume !(0 == ~t5_st~0); 828041#L761 assume !(0 == ~t6_st~0); 828032#L775 assume !(0 == ~t7_st~0); 828031#L789 assume !(0 == ~t8_st~0); 828052#L803 assume !false; 828038#L682 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~9;havoc exists_runnable_thread_~__retres1~9; 824462#L624 assume !(0 == ~m_st~0); 824461#L628 assume !(0 == ~t1_st~0); 824460#L632 assume !(0 == ~t2_st~0); 824459#L636 assume !(0 == ~t3_st~0); 824456#L640 assume !(0 == ~t4_st~0); 824453#L644 assume !(0 == ~t5_st~0); 824451#L648 assume !(0 == ~t6_st~0); 824449#L652 assume !(0 == ~t7_st~0); 824447#L656 assume !(0 == ~t8_st~0);exists_runnable_thread_~__retres1~9 := 0; 824446#L671 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~9; 824444#L672 eval_#t~ret0 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret0;havoc eval_#t~ret0; 824442#L686 assume !(0 != eval_~tmp~0); 824441#L818 start_simulation_~kernel_st~0 := 2; 824439#L564-1 start_simulation_~kernel_st~0 := 3; 824436#L828-2 assume !(0 == ~M_E~0); 824434#L828-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 824432#L833-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 824430#L838-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 824426#L843-3 assume !(0 == ~T4_E~0); 824424#L848-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 824420#L853-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 824418#L858-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 824416#L863-3 assume !(0 == ~T8_E~0); 824414#L868-3 assume 0 == ~E_1~0;~E_1~0 := 1; 824411#L873-3 assume 0 == ~E_2~0;~E_2~0 := 1; 824409#L878-3 assume 0 == ~E_3~0;~E_3~0 := 1; 824407#L883-3 assume !(0 == ~E_4~0); 824405#L888-3 assume 0 == ~E_5~0;~E_5~0 := 1; 824403#L893-3 assume 0 == ~E_6~0;~E_6~0 := 1; 824401#L898-3 assume 0 == ~E_7~0;~E_7~0 := 1; 824399#L903-3 assume !(0 == ~E_8~0); 824397#L908-3 havoc activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 824394#L392-27 assume 1 == ~m_pc~0; 824391#L393-9 assume !(1 == ~M_E~0); 824389#L392-29 is_master_triggered_~__retres1~0 := 0; 824387#L403-9 is_master_triggered_#res := is_master_triggered_~__retres1~0; 824385#L404-9 activate_threads_#t~ret10 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 824383#L1025-27 assume !(0 != activate_threads_~tmp~1); 824381#L1025-29 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 824379#L411-27 assume 1 == ~t1_pc~0; 824377#L412-9 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 824378#L422-9 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 824464#L423-9 activate_threads_#t~ret11 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 824368#L1033-27 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 824366#L1033-29 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 824363#L430-27 assume !(1 == ~t2_pc~0); 824361#L430-29 is_transmit2_triggered_~__retres1~2 := 0; 824359#L441-9 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 824357#L442-9 activate_threads_#t~ret12 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 824355#L1041-27 assume !(0 != activate_threads_~tmp___1~0); 824353#L1041-29 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 824351#L449-27 assume 1 == ~t3_pc~0; 824276#L450-9 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 824268#L460-9 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 824262#L461-9 activate_threads_#t~ret13 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 824254#L1049-27 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 824253#L1049-29 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 824252#L468-27 assume !(1 == ~t4_pc~0); 824251#L468-29 is_transmit4_triggered_~__retres1~4 := 0; 824250#L479-9 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 824249#L480-9 activate_threads_#t~ret14 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 824248#L1057-27 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 824247#L1057-29 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 824246#L487-27 assume 1 == ~t5_pc~0; 824244#L488-9 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 824242#L498-9 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 824241#L499-9 activate_threads_#t~ret15 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 824240#L1065-27 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 824239#L1065-29 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 824237#L506-27 assume !(1 == ~t6_pc~0); 824235#L506-29 is_transmit6_triggered_~__retres1~6 := 0; 824233#L517-9 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 824232#L518-9 activate_threads_#t~ret16 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 824228#L1073-27 assume 0 != activate_threads_~tmp___5~0;~t6_st~0 := 0; 824226#L1073-29 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 824224#L525-27 assume !(1 == ~t7_pc~0); 824222#L525-29 is_transmit7_triggered_~__retres1~7 := 0; 824219#L536-9 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 824217#L537-9 activate_threads_#t~ret17 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 824215#L1081-27 assume 0 != activate_threads_~tmp___6~0;~t7_st~0 := 0; 824213#L1081-29 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 824211#L544-27 assume !(1 == ~t8_pc~0); 824208#L544-29 is_transmit8_triggered_~__retres1~8 := 0; 824206#L555-9 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 824204#L556-9 activate_threads_#t~ret18 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 824202#L1089-27 assume !(0 != activate_threads_~tmp___7~0); 824069#L1089-29 assume !(1 == ~M_E~0); 824066#L921-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 824065#L926-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 824062#L931-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 824060#L936-3 assume !(1 == ~T4_E~0); 824058#L941-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 824056#L946-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 824054#L951-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 824052#L956-3 assume !(1 == ~T8_E~0); 824050#L961-3 assume 1 == ~E_1~0;~E_1~0 := 2; 824048#L966-3 assume 1 == ~E_2~0;~E_2~0 := 2; 824046#L971-3 assume 1 == ~E_3~0;~E_3~0 := 2; 824045#L976-3 assume !(1 == ~E_4~0); 824044#L981-3 assume 1 == ~E_5~0;~E_5~0 := 2; 824043#L986-3 assume 1 == ~E_6~0;~E_6~0 := 2; 824042#L991-3 assume 1 == ~E_7~0;~E_7~0 := 2; 824041#L996-3 assume !(1 == ~E_8~0); 824040#L1001-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~9;havoc exists_runnable_thread_~__retres1~9; 824039#L624-1 assume !(0 == ~m_st~0); 822824#L628-1 assume 0 == ~t1_st~0;exists_runnable_thread_~__retres1~9 := 1; 824029#L671-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~9; 824030#L672-1 start_simulation_#t~ret20 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret20;havoc start_simulation_#t~ret20; 822892#L1281 assume 0 == start_simulation_~tmp~3;start_simulation_~kernel_st~0 := 4;~M_E~0 := 1; 822890#L1115 havoc activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 822884#L392-30 assume 1 == ~m_pc~0; 822879#L393-10 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0 := 1; 822878#L403-10 is_master_triggered_#res := is_master_triggered_~__retres1~0; 822877#L404-10 activate_threads_#t~ret10 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 822797#L1025-30 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 822795#L1025-32 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 822793#L411-30 assume !(1 == ~t1_pc~0); 822789#L411-32 is_transmit1_triggered_~__retres1~1 := 0; 822787#L422-10 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 822786#L423-10 activate_threads_#t~ret11 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 822785#L1033-30 assume !(0 != activate_threads_~tmp___0~0); 822780#L1033-32 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 822778#L430-30 assume !(1 == ~t2_pc~0); 822773#L430-32 is_transmit2_triggered_~__retres1~2 := 0; 822770#L441-10 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 822767#L442-10 activate_threads_#t~ret12 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 822766#L1041-30 assume !(0 != activate_threads_~tmp___1~0); 822765#L1041-32 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 822764#L449-30 assume 1 == ~t3_pc~0; 822761#L450-10 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 822759#L460-10 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 822753#L461-10 activate_threads_#t~ret13 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 822751#L1049-30 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 822749#L1049-32 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 822746#L468-30 assume !(1 == ~t4_pc~0); 822744#L468-32 is_transmit4_triggered_~__retres1~4 := 0; 822742#L479-10 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 822740#L480-10 activate_threads_#t~ret14 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 822737#L1057-30 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 822734#L1057-32 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 822733#L487-30 assume !(1 == ~t5_pc~0); 822732#L487-32 is_transmit5_triggered_~__retres1~5 := 0; 822728#L498-10 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 822727#L499-10 activate_threads_#t~ret15 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 822725#L1065-30 assume !(0 != activate_threads_~tmp___4~0); 822723#L1065-32 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 822721#L506-30 assume !(1 == ~t6_pc~0); 822719#L506-32 is_transmit6_triggered_~__retres1~6 := 0; 822717#L517-10 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 822715#L518-10 activate_threads_#t~ret16 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 822713#L1073-30 assume 0 != activate_threads_~tmp___5~0;~t6_st~0 := 0; 822709#L1073-32 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 822707#L525-30 assume !(1 == ~t7_pc~0); 822705#L525-32 is_transmit7_triggered_~__retres1~7 := 0; 822703#L536-10 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 822700#L537-10 activate_threads_#t~ret17 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 822698#L1081-30 assume 0 != activate_threads_~tmp___6~0;~t7_st~0 := 0; 822696#L1081-32 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 822694#L544-30 assume !(1 == ~t8_pc~0); 822691#L544-32 is_transmit8_triggered_~__retres1~8 := 0; 822689#L555-10 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 822687#L556-10 activate_threads_#t~ret18 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 822685#L1089-30 assume !(0 != activate_threads_~tmp___7~0); 822682#L1089-32 assume !(1 == ~M_E~0); 822679#L1122-1 assume 1 == ~T1_E~0;~T1_E~0 := 2; 822677#L1127-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 822675#L1132-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 822673#L1137-1 assume !(1 == ~T4_E~0); 822671#L1142-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 822669#L1147-1 assume !(1 == ~T6_E~0); 822667#L1152-1 assume 1 == ~T7_E~0;~T7_E~0 := 2; 822665#L1157-1 assume !(1 == ~T8_E~0); 822663#L1162-1 assume 1 == ~E_1~0;~E_1~0 := 2; 822661#L1167-1 assume 1 == ~E_2~0;~E_2~0 := 2; 822659#L1172-1 assume 1 == ~E_3~0;~E_3~0 := 2; 822657#L1177-1 assume !(1 == ~E_4~0); 822654#L1182-1 assume 1 == ~E_5~0;~E_5~0 := 2; 822652#L1187-1 assume !(1 == ~E_6~0); 822650#L1192-1 assume 1 == ~E_7~0;~E_7~0 := 2; 822648#L1197-1 assume !(1 == ~E_8~0); 822644#L1281-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret19, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~9;havoc exists_runnable_thread_~__retres1~9; 822641#L624-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9 := 1; 822639#L671-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~9; 822637#L672-2 stop_simulation_#t~ret19 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret19;havoc stop_simulation_#t~ret19; 822635#L1236 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 822594#L1243 stop_simulation_#res := stop_simulation_~__retres2~0; 822585#L1244 start_simulation_#t~ret21 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret21;havoc start_simulation_#t~ret21; 822572#L1294 assume !(0 != start_simulation_~tmp___0~1); 822562#L1262-1 assume !false; 822550#L1263 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret0, eval_#t~nondet1, eval_~tmp_ndt_1~0, eval_#t~nondet2, eval_~tmp_ndt_2~0, eval_#t~nondet3, eval_~tmp_ndt_3~0, eval_#t~nondet4, eval_~tmp_ndt_4~0, eval_#t~nondet5, eval_~tmp_ndt_5~0, eval_#t~nondet6, eval_~tmp_ndt_6~0, eval_#t~nondet7, eval_~tmp_ndt_7~0, eval_#t~nondet8, eval_~tmp_ndt_8~0, eval_#t~nondet9, eval_~tmp_ndt_9~0, eval_~tmp~0;havoc eval_~tmp~0; 822543#L803 assume !false; 822535#L682 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~9;havoc exists_runnable_thread_~__retres1~9; 822528#L624 assume !(0 == ~m_st~0); 822529#L628 assume !(0 == ~t1_st~0); 824545#L632 assume !(0 == ~t2_st~0); 824137#L636 assume !(0 == ~t3_st~0); 823984#L640 assume !(0 == ~t4_st~0); 823979#L644 assume !(0 == ~t5_st~0); 823973#L648 assume !(0 == ~t6_st~0); 823968#L652 assume !(0 == ~t7_st~0); 823962#L656 assume !(0 == ~t8_st~0);exists_runnable_thread_~__retres1~9 := 0; 823957#L671 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~9; 823954#L672 eval_#t~ret0 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret0;havoc eval_#t~ret0; 823950#L686 assume !(0 != eval_~tmp~0); 823946#L818 start_simulation_~kernel_st~0 := 2; 823940#L564-1 start_simulation_~kernel_st~0 := 3; 823934#L828-2 assume 0 == ~M_E~0;~M_E~0 := 1; 823927#L828-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 823922#L833-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 823917#L838-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 823911#L843-3 assume !(0 == ~T4_E~0); 823905#L848-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 823899#L853-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 823892#L858-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 823887#L863-3 assume !(0 == ~T8_E~0); 823881#L868-3 assume 0 == ~E_1~0;~E_1~0 := 1; 823873#L873-3 assume 0 == ~E_2~0;~E_2~0 := 1; 823867#L878-3 assume 0 == ~E_3~0;~E_3~0 := 1; 823861#L883-3 assume !(0 == ~E_4~0); 823857#L888-3 assume 0 == ~E_5~0;~E_5~0 := 1; 823853#L893-3 assume 0 == ~E_6~0;~E_6~0 := 1; 823848#L898-3 assume 0 == ~E_7~0;~E_7~0 := 1; 823842#L903-3 assume !(0 == ~E_8~0); 823838#L908-3 havoc activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 823833#L392-27 assume 1 == ~m_pc~0; 823828#L393-9 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0 := 1; 823824#L403-9 is_master_triggered_#res := is_master_triggered_~__retres1~0; 823819#L404-9 activate_threads_#t~ret10 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 823814#L1025-27 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 823810#L1025-29 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 823805#L411-27 assume !(1 == ~t1_pc~0); 823800#L411-29 is_transmit1_triggered_~__retres1~1 := 0; 823794#L422-9 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 823789#L423-9 activate_threads_#t~ret11 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 823782#L1033-27 assume !(0 != activate_threads_~tmp___0~0); 823775#L1033-29 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 823769#L430-27 assume !(1 == ~t2_pc~0); 823762#L430-29 is_transmit2_triggered_~__retres1~2 := 0; 823756#L441-9 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 823750#L442-9 activate_threads_#t~ret12 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 823745#L1041-27 assume !(0 != activate_threads_~tmp___1~0); 823740#L1041-29 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 823735#L449-27 assume 1 == ~t3_pc~0; 823729#L450-9 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 823724#L460-9 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 823717#L461-9 activate_threads_#t~ret13 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 823711#L1049-27 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 823704#L1049-29 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 823698#L468-27 assume !(1 == ~t4_pc~0); 823693#L468-29 is_transmit4_triggered_~__retres1~4 := 0; 823688#L479-9 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 823682#L480-9 activate_threads_#t~ret14 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 823677#L1057-27 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 823672#L1057-29 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 823667#L487-27 assume 1 == ~t5_pc~0; 823661#L488-9 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 823655#L498-9 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 823649#L499-9 activate_threads_#t~ret15 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 823644#L1065-27 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 823638#L1065-29 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 823633#L506-27 assume !(1 == ~t6_pc~0); 823628#L506-29 is_transmit6_triggered_~__retres1~6 := 0; 823624#L517-9 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 823618#L518-9 activate_threads_#t~ret16 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 823612#L1073-27 assume 0 != activate_threads_~tmp___5~0;~t6_st~0 := 0; 823606#L1073-29 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 823600#L525-27 assume !(1 == ~t7_pc~0); 823595#L525-29 is_transmit7_triggered_~__retres1~7 := 0; 823590#L536-9 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 823584#L537-9 activate_threads_#t~ret17 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 823580#L1081-27 assume 0 != activate_threads_~tmp___6~0;~t7_st~0 := 0; 823575#L1081-29 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 822874#L544-27 assume !(1 == ~t8_pc~0); 822871#L544-29 is_transmit8_triggered_~__retres1~8 := 0; 822869#L555-9 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 822867#L556-9 activate_threads_#t~ret18 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 822865#L1089-27 assume !(0 != activate_threads_~tmp___7~0); 822861#L1089-29 assume !(1 == ~M_E~0); 822862#L921-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 823333#L926-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 823326#L931-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 823320#L936-3 assume !(1 == ~T4_E~0); 823319#L941-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 823318#L946-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 823309#L951-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 823298#L956-3 assume !(1 == ~T8_E~0); 823295#L961-3 assume 1 == ~E_1~0;~E_1~0 := 2; 823293#L966-3 assume 1 == ~E_2~0;~E_2~0 := 2; 823291#L971-3 assume 1 == ~E_3~0;~E_3~0 := 2; 823289#L976-3 assume !(1 == ~E_4~0); 823287#L981-3 assume 1 == ~E_5~0;~E_5~0 := 2; 823285#L986-3 assume 1 == ~E_6~0;~E_6~0 := 2; 823283#L991-3 assume 1 == ~E_7~0;~E_7~0 := 2; 823281#L996-3 assume !(1 == ~E_8~0); 823279#L1001-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~9;havoc exists_runnable_thread_~__retres1~9; 823276#L624-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9 := 1; 823274#L671-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~9; 823272#L672-1 start_simulation_#t~ret20 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret20;havoc start_simulation_#t~ret20; 822646#L1281 assume 0 == start_simulation_~tmp~3;start_simulation_~kernel_st~0 := 4;~M_E~0 := 1; 822647#L1115 havoc activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 822812#L392-30 assume !(1 == ~m_pc~0); 822813#L392-32 is_master_triggered_~__retres1~0 := 0; 823208#L403-10 is_master_triggered_#res := is_master_triggered_~__retres1~0; 823206#L404-10 activate_threads_#t~ret10 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 823203#L1025-30 assume !(0 != activate_threads_~tmp~1); 823201#L1025-32 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 823199#L411-30 assume 1 == ~t1_pc~0; 823197#L412-10 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 823195#L422-10 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 823193#L423-10 activate_threads_#t~ret11 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 823083#L1033-30 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 823081#L1033-32 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 823079#L430-30 assume !(1 == ~t2_pc~0); 823077#L430-32 is_transmit2_triggered_~__retres1~2 := 0; 823075#L441-10 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 823073#L442-10 activate_threads_#t~ret12 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 823071#L1041-30 assume !(0 != activate_threads_~tmp___1~0); 823069#L1041-32 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 823067#L449-30 assume 1 == ~t3_pc~0; 823064#L450-10 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 823062#L460-10 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 823059#L461-10 activate_threads_#t~ret13 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 823057#L1049-30 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 823055#L1049-32 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 823053#L468-30 assume !(1 == ~t4_pc~0); 823051#L468-32 is_transmit4_triggered_~__retres1~4 := 0; 823049#L479-10 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 823047#L480-10 activate_threads_#t~ret14 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 823045#L1057-30 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 823043#L1057-32 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 823041#L487-30 assume 1 == ~t5_pc~0; 823038#L488-10 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 823036#L498-10 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 823034#L499-10 activate_threads_#t~ret15 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 823032#L1065-30 assume !(0 != activate_threads_~tmp___4~0); 823030#L1065-32 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 823028#L506-30 assume !(1 == ~t6_pc~0); 823026#L506-32 is_transmit6_triggered_~__retres1~6 := 0; 823023#L517-10 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 823021#L518-10 activate_threads_#t~ret16 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 823019#L1073-30 assume 0 != activate_threads_~tmp___5~0;~t6_st~0 := 0; 823017#L1073-32 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 823015#L525-30 assume !(1 == ~t7_pc~0); 823014#L525-32 is_transmit7_triggered_~__retres1~7 := 0; 823010#L536-10 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 823008#L537-10 activate_threads_#t~ret17 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 823003#L1081-30 assume 0 != activate_threads_~tmp___6~0;~t7_st~0 := 0; 823001#L1081-32 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 822999#L544-30 assume !(1 == ~t8_pc~0); 822996#L544-32 is_transmit8_triggered_~__retres1~8 := 0; 822994#L555-10 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 822992#L556-10 activate_threads_#t~ret18 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 822990#L1089-30 assume !(0 != activate_threads_~tmp___7~0); 822985#L1089-32 assume 1 == ~M_E~0;~M_E~0 := 2; 822986#L1122-1 assume 1 == ~T1_E~0;~T1_E~0 := 2; 828886#L1127-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 828879#L1132-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 828872#L1137-1 assume !(1 == ~T4_E~0); 828865#L1142-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 828859#L1147-1 assume !(1 == ~T6_E~0); 828852#L1152-1 assume 1 == ~T7_E~0;~T7_E~0 := 2; 828846#L1157-1 assume !(1 == ~T8_E~0); 828840#L1162-1 assume 1 == ~E_1~0;~E_1~0 := 2; 828834#L1167-1 assume 1 == ~E_2~0;~E_2~0 := 2; 828827#L1172-1 assume 1 == ~E_3~0;~E_3~0 := 2; 828820#L1177-1 assume !(1 == ~E_4~0); 828813#L1182-1 assume 1 == ~E_5~0;~E_5~0 := 2; 828807#L1187-1 assume !(1 == ~E_6~0); 828802#L1192-1 assume 1 == ~E_7~0;~E_7~0 := 2; 828781#L1197-1 assume !(1 == ~E_8~0); 828774#L1281-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret19, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~9;havoc exists_runnable_thread_~__retres1~9; 828767#L624-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9 := 1; 828762#L671-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~9; 828756#L672-2 stop_simulation_#t~ret19 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret19;havoc stop_simulation_#t~ret19; 828749#L1236 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 828742#L1243 stop_simulation_#res := stop_simulation_~__retres2~0; 828736#L1244 start_simulation_#t~ret21 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret21;havoc start_simulation_#t~ret21; 828729#L1294 assume !(0 != start_simulation_~tmp___0~1); 817746#L1262-1 [2018-11-22 21:21:45,958 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-22 21:21:45,959 INFO L82 PathProgramCache]: Analyzing trace with hash 426104125, now seen corresponding path program 6 times [2018-11-22 21:21:45,959 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-22 21:21:45,959 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-22 21:21:45,959 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-22 21:21:45,959 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-22 21:21:45,960 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-22 21:21:45,964 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-22 21:21:45,970 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-22 21:21:45,992 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-22 21:21:45,992 INFO L82 PathProgramCache]: Analyzing trace with hash -337948057, now seen corresponding path program 1 times [2018-11-22 21:21:45,993 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-22 21:21:45,993 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-22 21:21:45,993 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-22 21:21:45,993 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-22 21:21:45,993 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-22 21:21:46,001 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-22 21:21:46,275 INFO L134 CoverageAnalysis]: Checked inductivity of 198 backedges. 14 proven. 0 refuted. 0 times theorem prover too weak. 184 trivial. 0 not checked. [2018-11-22 21:21:46,275 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-22 21:21:46,275 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-11-22 21:21:46,276 INFO L811 eck$LassoCheckResult]: loop already infeasible [2018-11-22 21:21:46,276 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-11-22 21:21:46,276 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-11-22 21:21:46,276 INFO L87 Difference]: Start difference. First operand 69955 states and 94633 transitions. cyclomatic complexity: 24710 Second operand 5 states. [2018-11-22 21:21:46,670 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-22 21:21:46,670 INFO L93 Difference]: Finished difference Result 181784 states and 246316 transitions. [2018-11-22 21:21:46,671 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2018-11-22 21:21:46,671 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 181784 states and 246316 transitions. [2018-11-22 21:21:47,139 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 180040 [2018-11-22 21:21:47,425 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 181784 states to 181784 states and 246316 transitions. [2018-11-22 21:21:47,425 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 181784 [2018-11-22 21:21:47,504 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 181784 [2018-11-22 21:21:47,504 INFO L73 IsDeterministic]: Start isDeterministic. Operand 181784 states and 246316 transitions. [2018-11-22 21:21:47,569 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-22 21:21:47,569 INFO L705 BuchiCegarLoop]: Abstraction has 181784 states and 246316 transitions. [2018-11-22 21:21:47,642 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 181784 states and 246316 transitions. [2018-11-22 21:21:48,210 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 181784 to 72406. [2018-11-22 21:21:48,210 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 72406 states. [2018-11-22 21:21:51,100 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 72406 states to 72406 states and 97084 transitions. [2018-11-22 21:21:51,100 INFO L728 BuchiCegarLoop]: Abstraction has 72406 states and 97084 transitions. [2018-11-22 21:21:51,100 INFO L608 BuchiCegarLoop]: Abstraction has 72406 states and 97084 transitions. [2018-11-22 21:21:51,100 INFO L442 BuchiCegarLoop]: ======== Iteration 26============ [2018-11-22 21:21:51,101 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 72406 states and 97084 transitions. [2018-11-22 21:21:51,184 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 71784 [2018-11-22 21:21:51,184 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-22 21:21:51,184 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-22 21:21:51,187 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-22 21:21:51,187 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-22 21:21:51,187 INFO L794 eck$LassoCheckResult]: Stem: 1069824#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2; 1069707#L-1 havoc main_#res;havoc main_~__retres1~10;havoc main_~__retres1~10;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 1069708#L1225 havoc start_simulation_#t~ret20, start_simulation_#t~ret21, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 1070255#L564 assume 1 == ~m_i~0;~m_st~0 := 0; 1069745#L571-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1069441#L576-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1069442#L581-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 1070259#L586-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 1069970#L591-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 1069551#L596-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 1069552#L601-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 1070246#L606-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 1070123#L611-1 assume !(0 == ~M_E~0); 1070124#L828-1 assume !(0 == ~T1_E~0); 1069848#L833-1 assume !(0 == ~T2_E~0); 1069566#L838-1 assume !(0 == ~T3_E~0); 1069567#L843-1 assume !(0 == ~T4_E~0); 1070378#L848-1 assume !(0 == ~T5_E~0); 1070132#L853-1 assume !(0 == ~T6_E~0); 1069833#L858-1 assume !(0 == ~T7_E~0); 1069360#L863-1 assume !(0 == ~T8_E~0); 1069361#L868-1 assume !(0 == ~E_1~0); 1070084#L873-1 assume !(0 == ~E_2~0); 1069924#L878-1 assume !(0 == ~E_3~0); 1069675#L883-1 assume !(0 == ~E_4~0); 1069676#L888-1 assume !(0 == ~E_5~0); 1070214#L893-1 assume !(0 == ~E_6~0); 1069886#L898-1 assume !(0 == ~E_7~0); 1069811#L903-1 assume !(0 == ~E_8~0); 1069507#L908-1 havoc activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 1069508#L392 assume !(1 == ~m_pc~0); 1069869#L392-2 is_master_triggered_~__retres1~0 := 0; 1069872#L403 is_master_triggered_#res := is_master_triggered_~__retres1~0; 1070428#L404 activate_threads_#t~ret10 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 1070223#L1025 assume !(0 != activate_threads_~tmp~1); 1070224#L1025-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 1070069#L411 assume !(1 == ~t1_pc~0); 1070031#L411-2 is_transmit1_triggered_~__retres1~1 := 0; 1069424#L422 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 1069425#L423 activate_threads_#t~ret11 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 1069532#L1033 assume !(0 != activate_threads_~tmp___0~0); 1069753#L1033-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 1069754#L430 assume !(1 == ~t2_pc~0); 1070235#L430-2 is_transmit2_triggered_~__retres1~2 := 0; 1069598#L441 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 1069553#L442 activate_threads_#t~ret12 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 1069554#L1041 assume !(0 != activate_threads_~tmp___1~0); 1070459#L1041-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 1070461#L449 assume !(1 == ~t3_pc~0); 1070317#L449-2 is_transmit3_triggered_~__retres1~3 := 0; 1069902#L460 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 1069903#L461 activate_threads_#t~ret13 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 1070251#L1049 assume !(0 != activate_threads_~tmp___2~0); 1070252#L1049-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 1069464#L468 assume !(1 == ~t4_pc~0); 1069465#L468-2 is_transmit4_triggered_~__retres1~4 := 0; 1069470#L479 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 1069878#L480 activate_threads_#t~ret14 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 1069818#L1057 assume !(0 != activate_threads_~tmp___3~0); 1069819#L1057-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 1069660#L487 assume !(1 == ~t5_pc~0); 1069420#L487-2 is_transmit5_triggered_~__retres1~5 := 0; 1069419#L498 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 1070055#L499 activate_threads_#t~ret15 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 1070056#L1065 assume !(0 != activate_threads_~tmp___4~0); 1070474#L1065-2 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 1069832#L506 assume !(1 == ~t6_pc~0); 1069828#L506-2 is_transmit6_triggered_~__retres1~6 := 0; 1069829#L517 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 1070248#L518 activate_threads_#t~ret16 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 1070153#L1073 assume !(0 != activate_threads_~tmp___5~0); 1070154#L1073-2 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 1069973#L525 assume !(1 == ~t7_pc~0); 1069974#L525-2 is_transmit7_triggered_~__retres1~7 := 0; 1069976#L536 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 1070462#L537 activate_threads_#t~ret17 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 1069681#L1081 assume !(0 != activate_threads_~tmp___6~0); 1069682#L1081-2 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 1069683#L544 assume !(1 == ~t8_pc~0); 1069998#L544-2 is_transmit8_triggered_~__retres1~8 := 0; 1069354#L555 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 1069355#L556 activate_threads_#t~ret18 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 1069494#L1089 assume !(0 != activate_threads_~tmp___7~0); 1070297#L1089-2 assume !(1 == ~M_E~0); 1069843#L921-1 assume !(1 == ~T1_E~0); 1069562#L926-1 assume !(1 == ~T2_E~0); 1069563#L931-1 assume !(1 == ~T3_E~0); 1070376#L936-1 assume !(1 == ~T4_E~0); 1070143#L941-1 assume !(1 == ~T5_E~0); 1069840#L946-1 assume !(1 == ~T6_E~0); 1069370#L951-1 assume !(1 == ~T7_E~0); 1069371#L956-1 assume !(1 == ~T8_E~0); 1070254#L961-1 assume !(1 == ~E_1~0); 1069934#L966-1 assume !(1 == ~E_2~0); 1069687#L971-1 assume !(1 == ~E_3~0); 1069688#L976-1 assume !(1 == ~E_4~0); 1070209#L981-1 assume !(1 == ~E_5~0); 1069884#L986-1 assume !(1 == ~E_6~0); 1069804#L991-1 assume !(1 == ~E_7~0); 1069501#L996-1 assume !(1 == ~E_8~0); 1069502#L1262-1 [2018-11-22 21:21:51,188 INFO L796 eck$LassoCheckResult]: Loop: 1069502#L1262-1 assume !false; 1079176#L1263 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret0, eval_#t~nondet1, eval_~tmp_ndt_1~0, eval_#t~nondet2, eval_~tmp_ndt_2~0, eval_#t~nondet3, eval_~tmp_ndt_3~0, eval_#t~nondet4, eval_~tmp_ndt_4~0, eval_#t~nondet5, eval_~tmp_ndt_5~0, eval_#t~nondet6, eval_~tmp_ndt_6~0, eval_#t~nondet7, eval_~tmp_ndt_7~0, eval_#t~nondet8, eval_~tmp_ndt_8~0, eval_#t~nondet9, eval_~tmp_ndt_9~0, eval_~tmp~0;havoc eval_~tmp~0; 1079174#L803 assume !false; 1079172#L682 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~9;havoc exists_runnable_thread_~__retres1~9; 1079169#L624 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9 := 1; 1079167#L671 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~9; 1079165#L672 eval_#t~ret0 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret0;havoc eval_#t~ret0; 1079163#L686 assume 0 != eval_~tmp~0; 1079151#L686-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0;eval_~tmp_ndt_1~0 := eval_#t~nondet1;havoc eval_#t~nondet1; 1079143#L694 assume 0 != eval_~tmp_ndt_1~0;~m_st~0 := 1; 1079032#L73 assume 0 == ~m_pc~0; 1078758#L100 assume !false; 1078969#L85 ~E_1~0 := 1;havoc activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 1078968#L392-3 assume !(1 == ~m_pc~0); 1078967#L392-5 is_master_triggered_~__retres1~0 := 0; 1078966#L403-1 is_master_triggered_#res := is_master_triggered_~__retres1~0; 1078965#L404-1 activate_threads_#t~ret10 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 1078963#L1025-3 assume !(0 != activate_threads_~tmp~1); 1078962#L1025-5 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 1078961#L411-3 assume !(1 == ~t1_pc~0); 1078960#L411-5 is_transmit1_triggered_~__retres1~1 := 0; 1078958#L422-1 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 1078956#L423-1 activate_threads_#t~ret11 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 1078954#L1033-3 assume !(0 != activate_threads_~tmp___0~0); 1078952#L1033-5 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 1078951#L430-3 assume !(1 == ~t2_pc~0); 1078950#L430-5 is_transmit2_triggered_~__retres1~2 := 0; 1078949#L441-1 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 1078945#L442-1 activate_threads_#t~ret12 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 1078944#L1041-3 assume !(0 != activate_threads_~tmp___1~0); 1078938#L1041-5 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 1078937#L449-3 assume 1 == ~t3_pc~0; 1078935#L450-1 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 1078933#L460-1 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 1078931#L461-1 activate_threads_#t~ret13 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 1078929#L1049-3 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 1078927#L1049-5 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 1078924#L468-3 assume !(1 == ~t4_pc~0); 1078922#L468-5 is_transmit4_triggered_~__retres1~4 := 0; 1078819#L479-1 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 1078817#L480-1 activate_threads_#t~ret14 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 1078815#L1057-3 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 1078813#L1057-5 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 1078811#L487-3 assume !(1 == ~t5_pc~0); 1078807#L487-5 is_transmit5_triggered_~__retres1~5 := 0; 1078805#L498-1 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 1078803#L499-1 activate_threads_#t~ret15 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 1078800#L1065-3 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 1078798#L1065-5 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 1078796#L506-3 assume !(1 == ~t6_pc~0); 1078794#L506-5 is_transmit6_triggered_~__retres1~6 := 0; 1078792#L517-1 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 1078790#L518-1 activate_threads_#t~ret16 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 1078788#L1073-3 assume !(0 != activate_threads_~tmp___5~0); 1078786#L1073-5 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 1078784#L525-3 assume !(1 == ~t7_pc~0); 1078782#L525-5 is_transmit7_triggered_~__retres1~7 := 0; 1078780#L536-1 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 1078778#L537-1 activate_threads_#t~ret17 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 1078776#L1081-3 assume 0 != activate_threads_~tmp___6~0;~t7_st~0 := 0; 1078774#L1081-5 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 1078772#L544-3 assume !(1 == ~t8_pc~0); 1078769#L544-5 is_transmit8_triggered_~__retres1~8 := 0; 1078767#L555-1 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 1078764#L556-1 activate_threads_#t~ret18 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 1078762#L1089-3 assume !(0 != activate_threads_~tmp___7~0); 1078756#L1089-5 ~E_1~0 := 2; 1078755#L77 assume !false; 1078751#L93 ~m_pc~0 := 1;~m_st~0 := 2; 1078456#L691 assume !(0 == ~t1_st~0); 1078742#L705 assume !(0 == ~t2_st~0); 1078157#L719 assume !(0 == ~t3_st~0); 1078151#L733 assume !(0 == ~t4_st~0); 1078104#L747 assume !(0 == ~t5_st~0); 1078096#L761 assume !(0 == ~t6_st~0); 1078090#L775 assume !(0 == ~t7_st~0); 1080587#L789 assume !(0 == ~t8_st~0); 1081886#L803 assume !false; 1081884#L682 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~9;havoc exists_runnable_thread_~__retres1~9; 1081882#L624 assume !(0 == ~m_st~0); 1078464#L628 assume !(0 == ~t1_st~0); 1081879#L632 assume !(0 == ~t2_st~0); 1081877#L636 assume !(0 == ~t3_st~0); 1081875#L640 assume !(0 == ~t4_st~0); 1081873#L644 assume !(0 == ~t5_st~0); 1081843#L648 assume !(0 == ~t6_st~0); 1081840#L652 assume !(0 == ~t7_st~0); 1081836#L656 assume !(0 == ~t8_st~0);exists_runnable_thread_~__retres1~9 := 0; 1081833#L671 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~9; 1081830#L672 eval_#t~ret0 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret0;havoc eval_#t~ret0; 1081826#L686 assume !(0 != eval_~tmp~0); 1081823#L818 start_simulation_~kernel_st~0 := 2; 1081820#L564-1 start_simulation_~kernel_st~0 := 3; 1081817#L828-2 assume !(0 == ~M_E~0); 1081813#L828-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 1081808#L833-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 1081774#L838-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 1081771#L843-3 assume !(0 == ~T4_E~0); 1081768#L848-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 1081765#L853-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 1081762#L858-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 1081759#L863-3 assume !(0 == ~T8_E~0); 1081756#L868-3 assume 0 == ~E_1~0;~E_1~0 := 1; 1081754#L873-3 assume 0 == ~E_2~0;~E_2~0 := 1; 1081752#L878-3 assume 0 == ~E_3~0;~E_3~0 := 1; 1081750#L883-3 assume !(0 == ~E_4~0); 1081745#L888-3 assume 0 == ~E_5~0;~E_5~0 := 1; 1081742#L893-3 assume 0 == ~E_6~0;~E_6~0 := 1; 1081706#L898-3 assume 0 == ~E_7~0;~E_7~0 := 1; 1081702#L903-3 assume !(0 == ~E_8~0); 1081698#L908-3 havoc activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 1081696#L392-27 assume 1 == ~m_pc~0; 1081695#L393-9 assume !(1 == ~M_E~0); 1081694#L392-29 is_master_triggered_~__retres1~0 := 0; 1081693#L403-9 is_master_triggered_#res := is_master_triggered_~__retres1~0; 1081692#L404-9 activate_threads_#t~ret10 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 1081691#L1025-27 assume !(0 != activate_threads_~tmp~1); 1081690#L1025-29 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 1081689#L411-27 assume 1 == ~t1_pc~0; 1081687#L412-9 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 1081685#L422-9 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 1081683#L423-9 activate_threads_#t~ret11 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 1081681#L1033-27 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 1081680#L1033-29 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 1081679#L430-27 assume !(1 == ~t2_pc~0); 1081678#L430-29 is_transmit2_triggered_~__retres1~2 := 0; 1081677#L441-9 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 1081676#L442-9 activate_threads_#t~ret12 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 1081675#L1041-27 assume !(0 != activate_threads_~tmp___1~0); 1081674#L1041-29 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 1081673#L449-27 assume 1 == ~t3_pc~0; 1081671#L450-9 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 1081669#L460-9 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 1081667#L461-9 activate_threads_#t~ret13 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 1081665#L1049-27 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 1081660#L1049-29 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 1081656#L468-27 assume !(1 == ~t4_pc~0); 1081652#L468-29 is_transmit4_triggered_~__retres1~4 := 0; 1081648#L479-9 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 1081644#L480-9 activate_threads_#t~ret14 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 1081639#L1057-27 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 1081634#L1057-29 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 1081630#L487-27 assume 1 == ~t5_pc~0; 1081625#L488-9 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 1081621#L498-9 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 1081618#L499-9 activate_threads_#t~ret15 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 1081564#L1065-27 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 1081561#L1065-29 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 1081559#L506-27 assume !(1 == ~t6_pc~0); 1081557#L506-29 is_transmit6_triggered_~__retres1~6 := 0; 1081555#L517-9 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 1081553#L518-9 activate_threads_#t~ret16 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 1081551#L1073-27 assume 0 != activate_threads_~tmp___5~0;~t6_st~0 := 0; 1081549#L1073-29 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 1081547#L525-27 assume !(1 == ~t7_pc~0); 1081545#L525-29 is_transmit7_triggered_~__retres1~7 := 0; 1081543#L536-9 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 1081541#L537-9 activate_threads_#t~ret17 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 1081539#L1081-27 assume 0 != activate_threads_~tmp___6~0;~t7_st~0 := 0; 1081537#L1081-29 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 1081535#L544-27 assume !(1 == ~t8_pc~0); 1081532#L544-29 is_transmit8_triggered_~__retres1~8 := 0; 1081530#L555-9 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 1081528#L556-9 activate_threads_#t~ret18 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 1081525#L1089-27 assume !(0 != activate_threads_~tmp___7~0); 1081516#L1089-29 assume !(1 == ~M_E~0); 1081514#L921-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 1081512#L926-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 1081510#L931-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 1081508#L936-3 assume !(1 == ~T4_E~0); 1081506#L941-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 1081504#L946-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 1081502#L951-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 1081500#L956-3 assume !(1 == ~T8_E~0); 1081498#L961-3 assume 1 == ~E_1~0;~E_1~0 := 2; 1081496#L966-3 assume 1 == ~E_2~0;~E_2~0 := 2; 1081494#L971-3 assume 1 == ~E_3~0;~E_3~0 := 2; 1081492#L976-3 assume !(1 == ~E_4~0); 1081481#L981-3 assume 1 == ~E_5~0;~E_5~0 := 2; 1081478#L986-3 assume 1 == ~E_6~0;~E_6~0 := 2; 1081424#L991-3 assume 1 == ~E_7~0;~E_7~0 := 2; 1081422#L996-3 assume !(1 == ~E_8~0); 1081420#L1001-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~9;havoc exists_runnable_thread_~__retres1~9; 1081418#L624-1 assume !(0 == ~m_st~0); 1076382#L628-1 assume 0 == ~t1_st~0;exists_runnable_thread_~__retres1~9 := 1; 1081403#L671-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~9; 1081396#L672-1 start_simulation_#t~ret20 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret20;havoc start_simulation_#t~ret20; 1076731#L1281 assume 0 == start_simulation_~tmp~3;start_simulation_~kernel_st~0 := 4;~M_E~0 := 1; 1076730#L1115 havoc activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 1076728#L392-30 assume 1 == ~m_pc~0; 1076726#L393-10 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0 := 1; 1076725#L403-10 is_master_triggered_#res := is_master_triggered_~__retres1~0; 1076724#L404-10 activate_threads_#t~ret10 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 1076714#L1025-30 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 1076713#L1025-32 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 1076712#L411-30 assume 1 == ~t1_pc~0; 1076710#L412-10 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 1076708#L422-10 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 1076706#L423-10 activate_threads_#t~ret11 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 1076704#L1033-30 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 1076703#L1033-32 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 1076702#L430-30 assume !(1 == ~t2_pc~0); 1076701#L430-32 is_transmit2_triggered_~__retres1~2 := 0; 1076700#L441-10 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 1076699#L442-10 activate_threads_#t~ret12 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 1076698#L1041-30 assume !(0 != activate_threads_~tmp___1~0); 1076697#L1041-32 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 1076696#L449-30 assume 1 == ~t3_pc~0; 1076694#L450-10 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 1076692#L460-10 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 1076690#L461-10 activate_threads_#t~ret13 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 1076688#L1049-30 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 1076686#L1049-32 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 1076684#L468-30 assume !(1 == ~t4_pc~0); 1076682#L468-32 is_transmit4_triggered_~__retres1~4 := 0; 1076680#L479-10 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 1076678#L480-10 activate_threads_#t~ret14 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 1076676#L1057-30 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 1076673#L1057-32 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 1076671#L487-30 assume 1 == ~t5_pc~0; 1076668#L488-10 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 1076666#L498-10 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 1076664#L499-10 activate_threads_#t~ret15 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 1076661#L1065-30 assume !(0 != activate_threads_~tmp___4~0); 1076659#L1065-32 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 1076657#L506-30 assume !(1 == ~t6_pc~0); 1076655#L506-32 is_transmit6_triggered_~__retres1~6 := 0; 1076653#L517-10 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 1076634#L518-10 activate_threads_#t~ret16 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 1076624#L1073-30 assume 0 != activate_threads_~tmp___5~0;~t6_st~0 := 0; 1076618#L1073-32 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 1076612#L525-30 assume !(1 == ~t7_pc~0); 1076607#L525-32 is_transmit7_triggered_~__retres1~7 := 0; 1076390#L536-10 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 1074831#L537-10 activate_threads_#t~ret17 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 1074828#L1081-30 assume 0 != activate_threads_~tmp___6~0;~t7_st~0 := 0; 1074827#L1081-32 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 1074513#L544-30 assume !(1 == ~t8_pc~0); 1074510#L544-32 is_transmit8_triggered_~__retres1~8 := 0; 1074508#L555-10 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 1074506#L556-10 activate_threads_#t~ret18 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 1074504#L1089-30 assume !(0 != activate_threads_~tmp___7~0); 1074501#L1089-32 assume !(1 == ~M_E~0); 1074499#L1122-1 assume 1 == ~T1_E~0;~T1_E~0 := 2; 1074497#L1127-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 1074495#L1132-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 1074492#L1137-1 assume !(1 == ~T4_E~0); 1074490#L1142-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 1074488#L1147-1 assume !(1 == ~T6_E~0); 1074486#L1152-1 assume 1 == ~T7_E~0;~T7_E~0 := 2; 1074484#L1157-1 assume !(1 == ~T8_E~0); 1074482#L1162-1 assume 1 == ~E_1~0;~E_1~0 := 2; 1074479#L1167-1 assume 1 == ~E_2~0;~E_2~0 := 2; 1074477#L1172-1 assume 1 == ~E_3~0;~E_3~0 := 2; 1074475#L1177-1 assume !(1 == ~E_4~0); 1074473#L1182-1 assume 1 == ~E_5~0;~E_5~0 := 2; 1074471#L1187-1 assume !(1 == ~E_6~0); 1074469#L1192-1 assume 1 == ~E_7~0;~E_7~0 := 2; 1074466#L1197-1 assume !(1 == ~E_8~0); 1074462#L1281-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret19, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~9;havoc exists_runnable_thread_~__retres1~9; 1074459#L624-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9 := 1; 1074457#L671-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~9; 1074455#L672-2 stop_simulation_#t~ret19 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret19;havoc stop_simulation_#t~ret19; 1074451#L1236 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 1074449#L1243 stop_simulation_#res := stop_simulation_~__retres2~0; 1074447#L1244 start_simulation_#t~ret21 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret21;havoc start_simulation_#t~ret21; 1074445#L1294 assume !(0 != start_simulation_~tmp___0~1); 1074442#L1262-1 assume !false; 1074216#L1263 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret0, eval_#t~nondet1, eval_~tmp_ndt_1~0, eval_#t~nondet2, eval_~tmp_ndt_2~0, eval_#t~nondet3, eval_~tmp_ndt_3~0, eval_#t~nondet4, eval_~tmp_ndt_4~0, eval_#t~nondet5, eval_~tmp_ndt_5~0, eval_#t~nondet6, eval_~tmp_ndt_6~0, eval_#t~nondet7, eval_~tmp_ndt_7~0, eval_#t~nondet8, eval_~tmp_ndt_8~0, eval_#t~nondet9, eval_~tmp_ndt_9~0, eval_~tmp~0;havoc eval_~tmp~0; 1074214#L803 assume !false; 1074212#L682 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~9;havoc exists_runnable_thread_~__retres1~9; 1074208#L624 assume !(0 == ~m_st~0); 1074209#L628 assume !(0 == ~t1_st~0); 1081122#L632 assume !(0 == ~t2_st~0); 1081120#L636 assume !(0 == ~t3_st~0); 1081118#L640 assume !(0 == ~t4_st~0); 1081104#L644 assume !(0 == ~t5_st~0); 1081099#L648 assume !(0 == ~t6_st~0); 1081093#L652 assume !(0 == ~t7_st~0); 1081041#L656 assume !(0 == ~t8_st~0);exists_runnable_thread_~__retres1~9 := 0; 1081038#L671 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~9; 1081036#L672 eval_#t~ret0 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret0;havoc eval_#t~ret0; 1081034#L686 assume !(0 != eval_~tmp~0); 1081032#L818 start_simulation_~kernel_st~0 := 2; 1081030#L564-1 start_simulation_~kernel_st~0 := 3; 1081027#L828-2 assume 0 == ~M_E~0;~M_E~0 := 1; 1081016#L828-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 1081007#L833-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 1080998#L838-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 1080990#L843-3 assume !(0 == ~T4_E~0); 1080989#L848-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 1080988#L853-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 1080937#L858-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 1080929#L863-3 assume !(0 == ~T8_E~0); 1080922#L868-3 assume 0 == ~E_1~0;~E_1~0 := 1; 1080919#L873-3 assume 0 == ~E_2~0;~E_2~0 := 1; 1080916#L878-3 assume 0 == ~E_3~0;~E_3~0 := 1; 1080913#L883-3 assume !(0 == ~E_4~0); 1080911#L888-3 assume 0 == ~E_5~0;~E_5~0 := 1; 1080908#L893-3 assume 0 == ~E_6~0;~E_6~0 := 1; 1080905#L898-3 assume 0 == ~E_7~0;~E_7~0 := 1; 1077613#L903-3 assume !(0 == ~E_8~0); 1077609#L908-3 havoc activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 1077607#L392-27 assume 1 == ~m_pc~0; 1077605#L393-9 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0 := 1; 1077604#L403-9 is_master_triggered_#res := is_master_triggered_~__retres1~0; 1077603#L404-9 activate_threads_#t~ret10 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 1077601#L1025-27 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 1077600#L1025-29 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 1077599#L411-27 assume 1 == ~t1_pc~0; 1077597#L412-9 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 1077595#L422-9 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 1077593#L423-9 activate_threads_#t~ret11 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 1077591#L1033-27 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 1077590#L1033-29 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 1077589#L430-27 assume !(1 == ~t2_pc~0); 1077588#L430-29 is_transmit2_triggered_~__retres1~2 := 0; 1077587#L441-9 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 1077586#L442-9 activate_threads_#t~ret12 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 1077585#L1041-27 assume !(0 != activate_threads_~tmp___1~0); 1077584#L1041-29 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 1077583#L449-27 assume 1 == ~t3_pc~0; 1077581#L450-9 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 1077579#L460-9 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 1077577#L461-9 activate_threads_#t~ret13 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 1077575#L1049-27 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 1077569#L1049-29 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 1077530#L468-27 assume !(1 == ~t4_pc~0); 1077525#L468-29 is_transmit4_triggered_~__retres1~4 := 0; 1077493#L479-9 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 1077488#L480-9 activate_threads_#t~ret14 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 1077483#L1057-27 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 1077478#L1057-29 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 1077474#L487-27 assume 1 == ~t5_pc~0; 1077469#L488-9 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 1077465#L498-9 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 1077432#L499-9 activate_threads_#t~ret15 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 1077428#L1065-27 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 1077425#L1065-29 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 1077422#L506-27 assume !(1 == ~t6_pc~0); 1077381#L506-29 is_transmit6_triggered_~__retres1~6 := 0; 1077305#L517-9 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 1077300#L518-9 activate_threads_#t~ret16 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 1077294#L1073-27 assume 0 != activate_threads_~tmp___5~0;~t6_st~0 := 0; 1077290#L1073-29 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 1077286#L525-27 assume !(1 == ~t7_pc~0); 1077249#L525-29 is_transmit7_triggered_~__retres1~7 := 0; 1076768#L536-9 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 1076758#L537-9 activate_threads_#t~ret17 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 1076745#L1081-27 assume 0 != activate_threads_~tmp___6~0;~t7_st~0 := 0; 1076733#L1081-29 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 1076675#L544-27 assume !(1 == ~t8_pc~0); 1076672#L544-29 is_transmit8_triggered_~__retres1~8 := 0; 1076670#L555-9 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 1076667#L556-9 activate_threads_#t~ret18 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 1076665#L1089-27 assume !(0 != activate_threads_~tmp___7~0); 1076662#L1089-29 assume 1 == ~M_E~0;~M_E~0 := 2; 1076660#L921-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 1076658#L926-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 1076656#L931-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 1076654#L936-3 assume !(1 == ~T4_E~0); 1076652#L941-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 1076633#L946-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 1076623#L951-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 1076617#L956-3 assume !(1 == ~T8_E~0); 1076611#L961-3 assume 1 == ~E_1~0;~E_1~0 := 2; 1076606#L966-3 assume 1 == ~E_2~0;~E_2~0 := 2; 1076389#L971-3 assume 1 == ~E_3~0;~E_3~0 := 2; 1076388#L976-3 assume !(1 == ~E_4~0); 1076387#L981-3 assume 1 == ~E_5~0;~E_5~0 := 2; 1076386#L986-3 assume 1 == ~E_6~0;~E_6~0 := 2; 1076385#L991-3 assume 1 == ~E_7~0;~E_7~0 := 2; 1076384#L996-3 assume !(1 == ~E_8~0); 1076383#L1001-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~9;havoc exists_runnable_thread_~__retres1~9; 1076381#L624-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9 := 1; 1076380#L671-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~9; 1076379#L672-1 start_simulation_#t~ret20 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret20;havoc start_simulation_#t~ret20; 1076377#L1281 assume 0 == start_simulation_~tmp~3;start_simulation_~kernel_st~0 := 4;~M_E~0 := 1; 1074465#L1115 havoc activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 1076375#L392-30 assume !(1 == ~m_pc~0); 1076374#L392-32 is_master_triggered_~__retres1~0 := 0; 1076373#L403-10 is_master_triggered_#res := is_master_triggered_~__retres1~0; 1076372#L404-10 activate_threads_#t~ret10 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 1076371#L1025-30 assume !(0 != activate_threads_~tmp~1); 1076370#L1025-32 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 1076369#L411-30 assume !(1 == ~t1_pc~0); 1076368#L411-32 is_transmit1_triggered_~__retres1~1 := 0; 1076366#L422-10 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 1076364#L423-10 activate_threads_#t~ret11 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 1076362#L1033-30 assume !(0 != activate_threads_~tmp___0~0); 1076360#L1033-32 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 1076359#L430-30 assume !(1 == ~t2_pc~0); 1076358#L430-32 is_transmit2_triggered_~__retres1~2 := 0; 1076357#L441-10 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 1076356#L442-10 activate_threads_#t~ret12 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 1076355#L1041-30 assume !(0 != activate_threads_~tmp___1~0); 1076354#L1041-32 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 1076353#L449-30 assume !(1 == ~t3_pc~0); 1076352#L449-32 is_transmit3_triggered_~__retres1~3 := 0; 1076350#L460-10 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 1076348#L461-10 activate_threads_#t~ret13 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 1076346#L1049-30 assume !(0 != activate_threads_~tmp___2~0); 1076343#L1049-32 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 1076341#L468-30 assume !(1 == ~t4_pc~0); 1076339#L468-32 is_transmit4_triggered_~__retres1~4 := 0; 1076337#L479-10 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 1076335#L480-10 activate_threads_#t~ret14 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 1076333#L1057-30 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 1076330#L1057-32 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 1076328#L487-30 assume 1 == ~t5_pc~0; 1076325#L488-10 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 1076323#L498-10 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 1076321#L499-10 activate_threads_#t~ret15 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 1076319#L1065-30 assume !(0 != activate_threads_~tmp___4~0); 1076318#L1065-32 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 1076317#L506-30 assume !(1 == ~t6_pc~0); 1076085#L506-32 is_transmit6_triggered_~__retres1~6 := 0; 1076073#L517-10 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 1076064#L518-10 activate_threads_#t~ret16 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 1076053#L1073-30 assume 0 != activate_threads_~tmp___5~0;~t6_st~0 := 0; 1076044#L1073-32 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 1076007#L525-30 assume !(1 == ~t7_pc~0); 1075998#L525-32 is_transmit7_triggered_~__retres1~7 := 0; 1075993#L536-10 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 1075988#L537-10 activate_threads_#t~ret17 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 1075950#L1081-30 assume 0 != activate_threads_~tmp___6~0;~t7_st~0 := 0; 1075946#L1081-32 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 1075942#L544-30 assume !(1 == ~t8_pc~0); 1075937#L544-32 is_transmit8_triggered_~__retres1~8 := 0; 1075931#L555-10 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 1075924#L556-10 activate_threads_#t~ret18 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 1075918#L1089-30 assume !(0 != activate_threads_~tmp___7~0); 1075913#L1089-32 assume 1 == ~M_E~0;~M_E~0 := 2; 1075914#L1122-1 assume 1 == ~T1_E~0;~T1_E~0 := 2; 1079625#L1127-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 1079623#L1132-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 1079621#L1137-1 assume !(1 == ~T4_E~0); 1079619#L1142-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 1079617#L1147-1 assume !(1 == ~T6_E~0); 1079615#L1152-1 assume 1 == ~T7_E~0;~T7_E~0 := 2; 1079613#L1157-1 assume !(1 == ~T8_E~0); 1079611#L1162-1 assume 1 == ~E_1~0;~E_1~0 := 2; 1079609#L1167-1 assume 1 == ~E_2~0;~E_2~0 := 2; 1079607#L1172-1 assume 1 == ~E_3~0;~E_3~0 := 2; 1079605#L1177-1 assume !(1 == ~E_4~0); 1079603#L1182-1 assume 1 == ~E_5~0;~E_5~0 := 2; 1079601#L1187-1 assume !(1 == ~E_6~0); 1079599#L1192-1 assume 1 == ~E_7~0;~E_7~0 := 2; 1079597#L1197-1 assume !(1 == ~E_8~0); 1079563#L1281-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret19, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~9;havoc exists_runnable_thread_~__retres1~9; 1079242#L624-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9 := 1; 1079232#L671-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~9; 1079222#L672-2 stop_simulation_#t~ret19 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret19;havoc stop_simulation_#t~ret19; 1079214#L1236 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 1079208#L1243 stop_simulation_#res := stop_simulation_~__retres2~0; 1079202#L1244 start_simulation_#t~ret21 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret21;havoc start_simulation_#t~ret21; 1079197#L1294 assume !(0 != start_simulation_~tmp___0~1); 1069502#L1262-1 [2018-11-22 21:21:51,188 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-22 21:21:51,189 INFO L82 PathProgramCache]: Analyzing trace with hash 426104125, now seen corresponding path program 7 times [2018-11-22 21:21:51,189 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-22 21:21:51,189 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-22 21:21:51,189 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-22 21:21:51,190 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-22 21:21:51,190 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-22 21:21:51,194 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-22 21:21:51,198 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-22 21:21:51,218 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-22 21:21:51,218 INFO L82 PathProgramCache]: Analyzing trace with hash -433175833, now seen corresponding path program 1 times [2018-11-22 21:21:51,218 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-22 21:21:51,218 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-22 21:21:51,219 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-22 21:21:51,219 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-22 21:21:51,219 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-22 21:21:51,226 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-22 21:21:51,336 INFO L134 CoverageAnalysis]: Checked inductivity of 199 backedges. 14 proven. 0 refuted. 0 times theorem prover too weak. 185 trivial. 0 not checked. [2018-11-22 21:21:51,337 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-22 21:21:51,337 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-11-22 21:21:51,337 INFO L811 eck$LassoCheckResult]: loop already infeasible [2018-11-22 21:21:51,337 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-11-22 21:21:51,337 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-11-22 21:21:51,338 INFO L87 Difference]: Start difference. First operand 72406 states and 97084 transitions. cyclomatic complexity: 24710 Second operand 5 states. [2018-11-22 21:21:51,637 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-22 21:21:51,637 INFO L93 Difference]: Finished difference Result 100222 states and 134103 transitions. [2018-11-22 21:21:51,638 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2018-11-22 21:21:51,638 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 100222 states and 134103 transitions. [2018-11-22 21:21:51,895 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 99216 [2018-11-22 21:21:52,062 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 100222 states to 100222 states and 134103 transitions. [2018-11-22 21:21:52,062 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 100222 [2018-11-22 21:21:52,106 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 100222 [2018-11-22 21:21:52,106 INFO L73 IsDeterministic]: Start isDeterministic. Operand 100222 states and 134103 transitions. [2018-11-22 21:21:52,144 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-22 21:21:52,144 INFO L705 BuchiCegarLoop]: Abstraction has 100222 states and 134103 transitions. [2018-11-22 21:21:52,186 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 100222 states and 134103 transitions. [2018-11-22 21:21:52,568 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 100222 to 72598. [2018-11-22 21:21:52,568 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 72598 states. [2018-11-22 21:21:52,637 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 72598 states to 72598 states and 96523 transitions. [2018-11-22 21:21:52,637 INFO L728 BuchiCegarLoop]: Abstraction has 72598 states and 96523 transitions. [2018-11-22 21:21:52,637 INFO L608 BuchiCegarLoop]: Abstraction has 72598 states and 96523 transitions. [2018-11-22 21:21:52,637 INFO L442 BuchiCegarLoop]: ======== Iteration 27============ [2018-11-22 21:21:52,637 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 72598 states and 96523 transitions. [2018-11-22 21:21:52,774 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 71976 [2018-11-22 21:21:52,774 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-22 21:21:52,774 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-22 21:21:52,776 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-22 21:21:52,776 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-22 21:21:52,777 INFO L794 eck$LassoCheckResult]: Stem: 1242477#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2; 1242364#L-1 havoc main_#res;havoc main_~__retres1~10;havoc main_~__retres1~10;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 1242365#L1225 havoc start_simulation_#t~ret20, start_simulation_#t~ret21, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 1242892#L564 assume 1 == ~m_i~0;~m_st~0 := 0; 1242398#L571-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1242084#L576-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1242085#L581-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 1242903#L586-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 1242618#L591-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 1242193#L596-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 1242194#L601-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 1242883#L606-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 1242765#L611-1 assume !(0 == ~M_E~0); 1242766#L828-1 assume !(0 == ~T1_E~0); 1242500#L833-1 assume !(0 == ~T2_E~0); 1242208#L838-1 assume !(0 == ~T3_E~0); 1242209#L843-1 assume !(0 == ~T4_E~0); 1243007#L848-1 assume !(0 == ~T5_E~0); 1242775#L853-1 assume !(0 == ~T6_E~0); 1242486#L858-1 assume !(0 == ~T7_E~0); 1242002#L863-1 assume !(0 == ~T8_E~0); 1242003#L868-1 assume !(0 == ~E_1~0); 1242723#L873-1 assume !(0 == ~E_2~0); 1242572#L878-1 assume !(0 == ~E_3~0); 1242329#L883-1 assume !(0 == ~E_4~0); 1242330#L888-1 assume !(0 == ~E_5~0); 1242851#L893-1 assume !(0 == ~E_6~0); 1242539#L898-1 assume !(0 == ~E_7~0); 1242464#L903-1 assume !(0 == ~E_8~0); 1242150#L908-1 havoc activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 1242151#L392 assume !(1 == ~m_pc~0); 1242520#L392-2 is_master_triggered_~__retres1~0 := 0; 1242524#L403 is_master_triggered_#res := is_master_triggered_~__retres1~0; 1243068#L404 activate_threads_#t~ret10 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 1242861#L1025 assume !(0 != activate_threads_~tmp~1); 1242862#L1025-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 1242707#L411 assume !(1 == ~t1_pc~0); 1242672#L411-2 is_transmit1_triggered_~__retres1~1 := 0; 1242067#L422 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 1242068#L423 activate_threads_#t~ret11 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 1242172#L1033 assume !(0 != activate_threads_~tmp___0~0); 1242406#L1033-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 1242407#L430 assume !(1 == ~t2_pc~0); 1242871#L430-2 is_transmit2_triggered_~__retres1~2 := 0; 1242244#L441 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 1242195#L442 activate_threads_#t~ret12 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 1242196#L1041 assume !(0 != activate_threads_~tmp___1~0); 1243101#L1041-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 1243103#L449 assume !(1 == ~t3_pc~0); 1242959#L449-2 is_transmit3_triggered_~__retres1~3 := 0; 1243115#L460 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 1243137#L461 activate_threads_#t~ret13 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 1242888#L1049 assume !(0 != activate_threads_~tmp___2~0); 1242889#L1049-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 1242105#L468 assume !(1 == ~t4_pc~0); 1242106#L468-2 is_transmit4_triggered_~__retres1~4 := 0; 1242113#L479 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 1242530#L480 activate_threads_#t~ret14 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 1242471#L1057 assume !(0 != activate_threads_~tmp___3~0); 1242472#L1057-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 1242315#L487 assume !(1 == ~t5_pc~0); 1242063#L487-2 is_transmit5_triggered_~__retres1~5 := 0; 1242062#L498 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 1242694#L499 activate_threads_#t~ret15 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 1242695#L1065 assume !(0 != activate_threads_~tmp___4~0); 1243124#L1065-2 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 1242485#L506 assume !(1 == ~t6_pc~0); 1242481#L506-2 is_transmit6_triggered_~__retres1~6 := 0; 1242482#L517 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 1242885#L518 activate_threads_#t~ret16 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 1242796#L1073 assume !(0 != activate_threads_~tmp___5~0); 1242797#L1073-2 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 1242621#L525 assume !(1 == ~t7_pc~0); 1242622#L525-2 is_transmit7_triggered_~__retres1~7 := 0; 1242624#L536 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 1243104#L537 activate_threads_#t~ret17 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 1242335#L1081 assume !(0 != activate_threads_~tmp___6~0); 1242336#L1081-2 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 1242337#L544 assume !(1 == ~t8_pc~0); 1242640#L544-2 is_transmit8_triggered_~__retres1~8 := 0; 1241996#L555 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 1241997#L556 activate_threads_#t~ret18 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 1242137#L1089 assume !(0 != activate_threads_~tmp___7~0); 1242941#L1089-2 assume !(1 == ~M_E~0); 1242495#L921-1 assume !(1 == ~T1_E~0); 1242204#L926-1 assume !(1 == ~T2_E~0); 1242205#L931-1 assume !(1 == ~T3_E~0); 1243005#L936-1 assume !(1 == ~T4_E~0); 1242784#L941-1 assume !(1 == ~T5_E~0); 1242492#L946-1 assume !(1 == ~T6_E~0); 1242012#L951-1 assume !(1 == ~T7_E~0); 1242013#L956-1 assume !(1 == ~T8_E~0); 1242891#L961-1 assume !(1 == ~E_1~0); 1242581#L966-1 assume !(1 == ~E_2~0); 1242342#L971-1 assume !(1 == ~E_3~0); 1242343#L976-1 assume !(1 == ~E_4~0); 1242846#L981-1 assume !(1 == ~E_5~0); 1242537#L986-1 assume !(1 == ~E_6~0); 1242457#L991-1 assume !(1 == ~E_7~0); 1242144#L996-1 assume !(1 == ~E_8~0); 1242145#L1262-1 [2018-11-22 21:21:52,777 INFO L796 eck$LassoCheckResult]: Loop: 1242145#L1262-1 assume !false; 1247852#L1263 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret0, eval_#t~nondet1, eval_~tmp_ndt_1~0, eval_#t~nondet2, eval_~tmp_ndt_2~0, eval_#t~nondet3, eval_~tmp_ndt_3~0, eval_#t~nondet4, eval_~tmp_ndt_4~0, eval_#t~nondet5, eval_~tmp_ndt_5~0, eval_#t~nondet6, eval_~tmp_ndt_6~0, eval_#t~nondet7, eval_~tmp_ndt_7~0, eval_#t~nondet8, eval_~tmp_ndt_8~0, eval_#t~nondet9, eval_~tmp_ndt_9~0, eval_~tmp~0;havoc eval_~tmp~0; 1247849#L803 assume !false; 1247846#L682 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~9;havoc exists_runnable_thread_~__retres1~9; 1247843#L624 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9 := 1; 1247842#L671 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~9; 1247841#L672 eval_#t~ret0 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret0;havoc eval_#t~ret0; 1247837#L686 assume 0 != eval_~tmp~0; 1247833#L686-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0;eval_~tmp_ndt_1~0 := eval_#t~nondet1;havoc eval_#t~nondet1; 1247830#L694 assume 0 != eval_~tmp_ndt_1~0;~m_st~0 := 1; 1247827#L73 assume 0 == ~m_pc~0; 1247570#L100 assume !false; 1247821#L85 ~E_1~0 := 1;havoc activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 1247818#L392-3 assume !(1 == ~m_pc~0); 1247815#L392-5 is_master_triggered_~__retres1~0 := 0; 1247811#L403-1 is_master_triggered_#res := is_master_triggered_~__retres1~0; 1247807#L404-1 activate_threads_#t~ret10 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 1247803#L1025-3 assume !(0 != activate_threads_~tmp~1); 1247799#L1025-5 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 1247795#L411-3 assume !(1 == ~t1_pc~0); 1247791#L411-5 is_transmit1_triggered_~__retres1~1 := 0; 1247786#L422-1 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 1247781#L423-1 activate_threads_#t~ret11 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 1247777#L1033-3 assume !(0 != activate_threads_~tmp___0~0); 1247773#L1033-5 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 1247770#L430-3 assume !(1 == ~t2_pc~0); 1247766#L430-5 is_transmit2_triggered_~__retres1~2 := 0; 1247761#L441-1 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 1247756#L442-1 activate_threads_#t~ret12 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 1247751#L1041-3 assume !(0 != activate_threads_~tmp___1~0); 1247746#L1041-5 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 1247741#L449-3 assume 1 == ~t3_pc~0; 1247735#L450-1 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 1247729#L460-1 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 1247723#L461-1 activate_threads_#t~ret13 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 1247718#L1049-3 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 1247714#L1049-5 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 1247710#L468-3 assume !(1 == ~t4_pc~0); 1247706#L468-5 is_transmit4_triggered_~__retres1~4 := 0; 1247701#L479-1 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 1247697#L480-1 activate_threads_#t~ret14 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 1247694#L1057-3 assume !(0 != activate_threads_~tmp___3~0); 1247690#L1057-5 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 1247687#L487-3 assume 1 == ~t5_pc~0; 1247685#L488-1 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 1247682#L498-1 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 1247680#L499-1 activate_threads_#t~ret15 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 1247678#L1065-3 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 1247676#L1065-5 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 1247675#L506-3 assume !(1 == ~t6_pc~0); 1247665#L506-5 is_transmit6_triggered_~__retres1~6 := 0; 1247661#L517-1 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 1247657#L518-1 activate_threads_#t~ret16 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 1247653#L1073-3 assume !(0 != activate_threads_~tmp___5~0); 1247649#L1073-5 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 1247645#L525-3 assume !(1 == ~t7_pc~0); 1247640#L525-5 is_transmit7_triggered_~__retres1~7 := 0; 1247633#L536-1 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 1247623#L537-1 activate_threads_#t~ret17 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 1247618#L1081-3 assume 0 != activate_threads_~tmp___6~0;~t7_st~0 := 0; 1247599#L1081-5 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 1247596#L544-3 assume !(1 == ~t8_pc~0); 1247593#L544-5 is_transmit8_triggered_~__retres1~8 := 0; 1247591#L555-1 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 1247590#L556-1 activate_threads_#t~ret18 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 1247576#L1089-3 assume !(0 != activate_threads_~tmp___7~0); 1247568#L1089-5 ~E_1~0 := 2; 1247487#L77 assume !false; 1247457#L93 ~m_pc~0 := 1;~m_st~0 := 2; 1246783#L691 assume !(0 == ~t1_st~0); 1247436#L705 assume !(0 == ~t2_st~0); 1247386#L719 assume !(0 == ~t3_st~0); 1247377#L733 assume !(0 == ~t4_st~0); 1247368#L747 assume !(0 == ~t5_st~0); 1247171#L761 assume !(0 == ~t6_st~0); 1247170#L775 assume !(0 == ~t7_st~0); 1247631#L789 assume !(0 == ~t8_st~0); 1247622#L803 assume !false; 1247617#L682 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~9;havoc exists_runnable_thread_~__retres1~9; 1247614#L624 assume !(0 == ~m_st~0); 1246815#L628 assume !(0 == ~t1_st~0); 1247588#L632 assume !(0 == ~t2_st~0); 1247584#L636 assume !(0 == ~t3_st~0); 1247585#L640 assume !(0 == ~t4_st~0); 1247587#L644 assume !(0 == ~t5_st~0); 1247582#L648 assume !(0 == ~t6_st~0); 1247583#L652 assume !(0 == ~t7_st~0); 1247586#L656 assume !(0 == ~t8_st~0);exists_runnable_thread_~__retres1~9 := 0; 1247589#L671 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~9; 1247606#L672 eval_#t~ret0 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret0;havoc eval_#t~ret0; 1247424#L686 assume !(0 != eval_~tmp~0); 1247421#L818 start_simulation_~kernel_st~0 := 2; 1247419#L564-1 start_simulation_~kernel_st~0 := 3; 1247417#L828-2 assume !(0 == ~M_E~0); 1247415#L828-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 1247413#L833-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 1247411#L838-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 1247409#L843-3 assume !(0 == ~T4_E~0); 1247407#L848-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 1247405#L853-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 1247402#L858-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 1247400#L863-3 assume !(0 == ~T8_E~0); 1247397#L868-3 assume 0 == ~E_1~0;~E_1~0 := 1; 1247395#L873-3 assume 0 == ~E_2~0;~E_2~0 := 1; 1247393#L878-3 assume 0 == ~E_3~0;~E_3~0 := 1; 1247381#L883-3 assume !(0 == ~E_4~0); 1247372#L888-3 assume 0 == ~E_5~0;~E_5~0 := 1; 1247364#L893-3 assume 0 == ~E_6~0;~E_6~0 := 1; 1247360#L898-3 assume 0 == ~E_7~0;~E_7~0 := 1; 1247355#L903-3 assume !(0 == ~E_8~0); 1247234#L908-3 havoc activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 1247232#L392-27 assume 1 == ~m_pc~0; 1247231#L393-9 assume !(1 == ~M_E~0); 1247230#L392-29 is_master_triggered_~__retres1~0 := 0; 1247228#L403-9 is_master_triggered_#res := is_master_triggered_~__retres1~0; 1247227#L404-9 activate_threads_#t~ret10 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 1247226#L1025-27 assume !(0 != activate_threads_~tmp~1); 1247224#L1025-29 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 1247223#L411-27 assume 1 == ~t1_pc~0; 1247222#L412-9 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 1247220#L422-9 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 1247218#L423-9 activate_threads_#t~ret11 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 1247215#L1033-27 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 1247214#L1033-29 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 1247213#L430-27 assume !(1 == ~t2_pc~0); 1247212#L430-29 is_transmit2_triggered_~__retres1~2 := 0; 1247210#L441-9 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 1247209#L442-9 activate_threads_#t~ret12 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 1247207#L1041-27 assume !(0 != activate_threads_~tmp___1~0); 1247205#L1041-29 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 1247203#L449-27 assume 1 == ~t3_pc~0; 1247201#L450-9 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 1247202#L460-9 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 1247225#L461-9 activate_threads_#t~ret13 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 1247190#L1049-27 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 1247188#L1049-29 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 1247185#L468-27 assume !(1 == ~t4_pc~0); 1247183#L468-29 is_transmit4_triggered_~__retres1~4 := 0; 1247181#L479-9 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 1247179#L480-9 activate_threads_#t~ret14 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 1247177#L1057-27 assume !(0 != activate_threads_~tmp___3~0); 1247175#L1057-29 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 1247174#L487-27 assume !(1 == ~t5_pc~0); 1247173#L487-29 is_transmit5_triggered_~__retres1~5 := 0; 1246243#L498-9 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 1246242#L499-9 activate_threads_#t~ret15 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 1246240#L1065-27 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 1246237#L1065-29 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 1246235#L506-27 assume !(1 == ~t6_pc~0); 1246233#L506-29 is_transmit6_triggered_~__retres1~6 := 0; 1246231#L517-9 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 1246229#L518-9 activate_threads_#t~ret16 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 1246227#L1073-27 assume 0 != activate_threads_~tmp___5~0;~t6_st~0 := 0; 1246225#L1073-29 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 1246223#L525-27 assume !(1 == ~t7_pc~0); 1246221#L525-29 is_transmit7_triggered_~__retres1~7 := 0; 1246219#L536-9 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 1246217#L537-9 activate_threads_#t~ret17 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 1246214#L1081-27 assume 0 != activate_threads_~tmp___6~0;~t7_st~0 := 0; 1246212#L1081-29 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 1246210#L544-27 assume !(1 == ~t8_pc~0); 1246207#L544-29 is_transmit8_triggered_~__retres1~8 := 0; 1246205#L555-9 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 1246204#L556-9 activate_threads_#t~ret18 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 1246200#L1089-27 assume !(0 != activate_threads_~tmp___7~0); 1245757#L1089-29 assume !(1 == ~M_E~0); 1245755#L921-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 1245751#L926-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 1245749#L931-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 1245747#L936-3 assume !(1 == ~T4_E~0); 1245745#L941-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 1245742#L946-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 1245740#L951-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 1245738#L956-3 assume !(1 == ~T8_E~0); 1245736#L961-3 assume 1 == ~E_1~0;~E_1~0 := 2; 1245734#L966-3 assume 1 == ~E_2~0;~E_2~0 := 2; 1245732#L971-3 assume 1 == ~E_3~0;~E_3~0 := 2; 1245730#L976-3 assume !(1 == ~E_4~0); 1245728#L981-3 assume 1 == ~E_5~0;~E_5~0 := 2; 1245724#L986-3 assume 1 == ~E_6~0;~E_6~0 := 2; 1245722#L991-3 assume 1 == ~E_7~0;~E_7~0 := 2; 1245720#L996-3 assume !(1 == ~E_8~0); 1245718#L1001-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~9;havoc exists_runnable_thread_~__retres1~9; 1245715#L624-1 assume !(0 == ~m_st~0); 1245169#L628-1 assume 0 == ~t1_st~0;exists_runnable_thread_~__retres1~9 := 1; 1245665#L671-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~9; 1245661#L672-1 start_simulation_#t~ret20 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret20;havoc start_simulation_#t~ret20; 1244819#L1281 assume 0 == start_simulation_~tmp~3;start_simulation_~kernel_st~0 := 4;~M_E~0 := 1; 1244817#L1115 havoc activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 1244815#L392-30 assume 1 == ~m_pc~0; 1244813#L393-10 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0 := 1; 1244811#L403-10 is_master_triggered_#res := is_master_triggered_~__retres1~0; 1244810#L404-10 activate_threads_#t~ret10 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 1244760#L1025-30 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 1244758#L1025-32 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 1244756#L411-30 assume 1 == ~t1_pc~0; 1244754#L412-10 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 1244755#L422-10 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 1244818#L423-10 activate_threads_#t~ret11 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 1244744#L1033-30 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 1244742#L1033-32 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 1244740#L430-30 assume !(1 == ~t2_pc~0); 1244738#L430-32 is_transmit2_triggered_~__retres1~2 := 0; 1244736#L441-10 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 1244734#L442-10 activate_threads_#t~ret12 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 1244730#L1041-30 assume !(0 != activate_threads_~tmp___1~0); 1244728#L1041-32 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 1244726#L449-30 assume 1 == ~t3_pc~0; 1244723#L450-10 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 1244720#L460-10 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 1244718#L461-10 activate_threads_#t~ret13 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 1244694#L1049-30 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 1244692#L1049-32 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 1244689#L468-30 assume !(1 == ~t4_pc~0); 1244687#L468-32 is_transmit4_triggered_~__retres1~4 := 0; 1244685#L479-10 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 1244683#L480-10 activate_threads_#t~ret14 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 1244681#L1057-30 assume !(0 != activate_threads_~tmp___3~0); 1244679#L1057-32 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 1244677#L487-30 assume 1 == ~t5_pc~0; 1244674#L488-10 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 1244672#L498-10 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 1244670#L499-10 activate_threads_#t~ret15 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 1244668#L1065-30 assume !(0 != activate_threads_~tmp___4~0); 1244666#L1065-32 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 1244664#L506-30 assume !(1 == ~t6_pc~0); 1244662#L506-32 is_transmit6_triggered_~__retres1~6 := 0; 1244660#L517-10 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 1244658#L518-10 activate_threads_#t~ret16 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 1244656#L1073-30 assume 0 != activate_threads_~tmp___5~0;~t6_st~0 := 0; 1244653#L1073-32 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 1244651#L525-30 assume !(1 == ~t7_pc~0); 1244649#L525-32 is_transmit7_triggered_~__retres1~7 := 0; 1244647#L536-10 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 1244645#L537-10 activate_threads_#t~ret17 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 1244642#L1081-30 assume 0 != activate_threads_~tmp___6~0;~t7_st~0 := 0; 1244640#L1081-32 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 1244638#L544-30 assume !(1 == ~t8_pc~0); 1244635#L544-32 is_transmit8_triggered_~__retres1~8 := 0; 1244633#L555-10 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 1244631#L556-10 activate_threads_#t~ret18 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 1244629#L1089-30 assume !(0 != activate_threads_~tmp___7~0); 1244626#L1089-32 assume !(1 == ~M_E~0); 1244624#L1122-1 assume 1 == ~T1_E~0;~T1_E~0 := 2; 1244622#L1127-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 1244620#L1132-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 1244618#L1137-1 assume !(1 == ~T4_E~0); 1244616#L1142-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 1244614#L1147-1 assume !(1 == ~T6_E~0); 1244612#L1152-1 assume 1 == ~T7_E~0;~T7_E~0 := 2; 1244610#L1157-1 assume !(1 == ~T8_E~0); 1244608#L1162-1 assume 1 == ~E_1~0;~E_1~0 := 2; 1244606#L1167-1 assume 1 == ~E_2~0;~E_2~0 := 2; 1244603#L1172-1 assume 1 == ~E_3~0;~E_3~0 := 2; 1244601#L1177-1 assume !(1 == ~E_4~0); 1244599#L1182-1 assume 1 == ~E_5~0;~E_5~0 := 2; 1244598#L1187-1 assume !(1 == ~E_6~0); 1244597#L1192-1 assume 1 == ~E_7~0;~E_7~0 := 2; 1244594#L1197-1 assume !(1 == ~E_8~0); 1244591#L1281-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret19, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~9;havoc exists_runnable_thread_~__retres1~9; 1244589#L624-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9 := 1; 1244587#L671-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~9; 1244586#L672-2 stop_simulation_#t~ret19 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret19;havoc stop_simulation_#t~ret19; 1244585#L1236 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 1244581#L1243 stop_simulation_#res := stop_simulation_~__retres2~0; 1244579#L1244 start_simulation_#t~ret21 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret21;havoc start_simulation_#t~ret21; 1244577#L1294 assume !(0 != start_simulation_~tmp___0~1); 1244575#L1262-1 assume !false; 1244478#L1263 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret0, eval_#t~nondet1, eval_~tmp_ndt_1~0, eval_#t~nondet2, eval_~tmp_ndt_2~0, eval_#t~nondet3, eval_~tmp_ndt_3~0, eval_#t~nondet4, eval_~tmp_ndt_4~0, eval_#t~nondet5, eval_~tmp_ndt_5~0, eval_#t~nondet6, eval_~tmp_ndt_6~0, eval_#t~nondet7, eval_~tmp_ndt_7~0, eval_#t~nondet8, eval_~tmp_ndt_8~0, eval_#t~nondet9, eval_~tmp_ndt_9~0, eval_~tmp~0;havoc eval_~tmp~0; 1244471#L803 assume !false; 1244464#L682 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~9;havoc exists_runnable_thread_~__retres1~9; 1244455#L624 assume !(0 == ~m_st~0); 1244456#L628 assume !(0 == ~t1_st~0); 1245386#L632 assume !(0 == ~t2_st~0); 1245382#L636 assume !(0 == ~t3_st~0); 1245383#L640 assume !(0 == ~t4_st~0); 1245385#L644 assume !(0 == ~t5_st~0); 1245380#L648 assume !(0 == ~t6_st~0); 1245381#L652 assume !(0 == ~t7_st~0); 1245384#L656 assume !(0 == ~t8_st~0);exists_runnable_thread_~__retres1~9 := 0; 1245377#L671 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~9; 1245371#L672 eval_#t~ret0 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret0;havoc eval_#t~ret0; 1245364#L686 assume !(0 != eval_~tmp~0); 1245358#L818 start_simulation_~kernel_st~0 := 2; 1245353#L564-1 start_simulation_~kernel_st~0 := 3; 1245348#L828-2 assume 0 == ~M_E~0;~M_E~0 := 1; 1245342#L828-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 1245337#L833-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 1245331#L838-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 1245325#L843-3 assume !(0 == ~T4_E~0); 1245318#L848-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 1245313#L853-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 1245308#L858-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 1245301#L863-3 assume !(0 == ~T8_E~0); 1245294#L868-3 assume 0 == ~E_1~0;~E_1~0 := 1; 1245288#L873-3 assume 0 == ~E_2~0;~E_2~0 := 1; 1245284#L878-3 assume 0 == ~E_3~0;~E_3~0 := 1; 1245280#L883-3 assume !(0 == ~E_4~0); 1245276#L888-3 assume 0 == ~E_5~0;~E_5~0 := 1; 1245272#L893-3 assume 0 == ~E_6~0;~E_6~0 := 1; 1245267#L898-3 assume 0 == ~E_7~0;~E_7~0 := 1; 1245261#L903-3 assume !(0 == ~E_8~0); 1245255#L908-3 havoc activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 1245249#L392-27 assume 1 == ~m_pc~0; 1245244#L393-9 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0 := 1; 1245238#L403-9 is_master_triggered_#res := is_master_triggered_~__retres1~0; 1245231#L404-9 activate_threads_#t~ret10 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 1245223#L1025-27 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 1245216#L1025-29 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 1245210#L411-27 assume 1 == ~t1_pc~0; 1245203#L412-9 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 1245196#L422-9 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 1245188#L423-9 activate_threads_#t~ret11 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 1245179#L1033-27 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 1245173#L1033-29 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 1245167#L430-27 assume !(1 == ~t2_pc~0); 1245162#L430-29 is_transmit2_triggered_~__retres1~2 := 0; 1245156#L441-9 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 1245148#L442-9 activate_threads_#t~ret12 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 1245142#L1041-27 assume !(0 != activate_threads_~tmp___1~0); 1245134#L1041-29 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 1245129#L449-27 assume 1 == ~t3_pc~0; 1245123#L450-9 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 1245118#L460-9 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 1245112#L461-9 activate_threads_#t~ret13 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 1245106#L1049-27 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 1245101#L1049-29 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 1245100#L468-27 assume !(1 == ~t4_pc~0); 1245099#L468-29 is_transmit4_triggered_~__retres1~4 := 0; 1245098#L479-9 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 1245097#L480-9 activate_threads_#t~ret14 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 1245095#L1057-27 assume !(0 != activate_threads_~tmp___3~0); 1244696#L1057-29 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 1244693#L487-27 assume 1 == ~t5_pc~0; 1244690#L488-9 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 1244688#L498-9 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 1244686#L499-9 activate_threads_#t~ret15 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 1244684#L1065-27 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 1244682#L1065-29 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 1244680#L506-27 assume !(1 == ~t6_pc~0); 1244678#L506-29 is_transmit6_triggered_~__retres1~6 := 0; 1244676#L517-9 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 1244673#L518-9 activate_threads_#t~ret16 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 1244671#L1073-27 assume 0 != activate_threads_~tmp___5~0;~t6_st~0 := 0; 1244669#L1073-29 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 1244667#L525-27 assume !(1 == ~t7_pc~0); 1244665#L525-29 is_transmit7_triggered_~__retres1~7 := 0; 1244663#L536-9 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 1244661#L537-9 activate_threads_#t~ret17 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 1244659#L1081-27 assume 0 != activate_threads_~tmp___6~0;~t7_st~0 := 0; 1244657#L1081-29 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 1244655#L544-27 assume !(1 == ~t8_pc~0); 1244652#L544-29 is_transmit8_triggered_~__retres1~8 := 0; 1244650#L555-9 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 1244648#L556-9 activate_threads_#t~ret18 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 1244646#L1089-27 assume !(0 != activate_threads_~tmp___7~0); 1244643#L1089-29 assume !(1 == ~M_E~0); 1244641#L921-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 1244639#L926-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 1244636#L931-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 1244634#L936-3 assume !(1 == ~T4_E~0); 1244632#L941-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 1244630#L946-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 1244628#L951-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 1244625#L956-3 assume !(1 == ~T8_E~0); 1244623#L961-3 assume 1 == ~E_1~0;~E_1~0 := 2; 1244621#L966-3 assume 1 == ~E_2~0;~E_2~0 := 2; 1244619#L971-3 assume 1 == ~E_3~0;~E_3~0 := 2; 1244617#L976-3 assume !(1 == ~E_4~0); 1244615#L981-3 assume 1 == ~E_5~0;~E_5~0 := 2; 1244613#L986-3 assume 1 == ~E_6~0;~E_6~0 := 2; 1244611#L991-3 assume 1 == ~E_7~0;~E_7~0 := 2; 1244609#L996-3 assume !(1 == ~E_8~0); 1244607#L1001-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~9;havoc exists_runnable_thread_~__retres1~9; 1244604#L624-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9 := 1; 1244602#L671-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~9; 1244600#L672-1 start_simulation_#t~ret20 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret20;havoc start_simulation_#t~ret20; 1244592#L1281 assume 0 == start_simulation_~tmp~3;start_simulation_~kernel_st~0 := 4;~M_E~0 := 1; 1244593#L1115 havoc activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 1245135#L392-30 assume !(1 == ~m_pc~0); 1245136#L392-32 is_master_triggered_~__retres1~0 := 0; 1245660#L403-10 is_master_triggered_#res := is_master_triggered_~__retres1~0; 1245656#L404-10 activate_threads_#t~ret10 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 1245653#L1025-30 assume !(0 != activate_threads_~tmp~1); 1245647#L1025-32 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 1245646#L411-30 assume 1 == ~t1_pc~0; 1245645#L412-10 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 1245643#L422-10 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 1245641#L423-10 activate_threads_#t~ret11 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 1245638#L1033-30 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 1245637#L1033-32 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 1245636#L430-30 assume !(1 == ~t2_pc~0); 1245635#L430-32 is_transmit2_triggered_~__retres1~2 := 0; 1245634#L441-10 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 1245633#L442-10 activate_threads_#t~ret12 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 1245631#L1041-30 assume !(0 != activate_threads_~tmp___1~0); 1245630#L1041-32 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 1245629#L449-30 assume !(1 == ~t3_pc~0); 1245627#L449-32 is_transmit3_triggered_~__retres1~3 := 0; 1245625#L460-10 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 1245623#L461-10 activate_threads_#t~ret13 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 1245622#L1049-30 assume !(0 != activate_threads_~tmp___2~0); 1245617#L1049-32 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 1245615#L468-30 assume !(1 == ~t4_pc~0); 1245613#L468-32 is_transmit4_triggered_~__retres1~4 := 0; 1245611#L479-10 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 1245608#L480-10 activate_threads_#t~ret14 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 1245606#L1057-30 assume !(0 != activate_threads_~tmp___3~0); 1245604#L1057-32 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 1245602#L487-30 assume !(1 == ~t5_pc~0); 1245600#L487-32 is_transmit5_triggered_~__retres1~5 := 0; 1245597#L498-10 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 1245595#L499-10 activate_threads_#t~ret15 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 1245593#L1065-30 assume !(0 != activate_threads_~tmp___4~0); 1245591#L1065-32 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 1245590#L506-30 assume !(1 == ~t6_pc~0); 1245587#L506-32 is_transmit6_triggered_~__retres1~6 := 0; 1245585#L517-10 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 1245583#L518-10 activate_threads_#t~ret16 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 1245581#L1073-30 assume 0 != activate_threads_~tmp___5~0;~t6_st~0 := 0; 1245579#L1073-32 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 1245577#L525-30 assume !(1 == ~t7_pc~0); 1245575#L525-32 is_transmit7_triggered_~__retres1~7 := 0; 1245573#L536-10 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 1245571#L537-10 activate_threads_#t~ret17 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 1245569#L1081-30 assume 0 != activate_threads_~tmp___6~0;~t7_st~0 := 0; 1245567#L1081-32 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 1245565#L544-30 assume !(1 == ~t8_pc~0); 1245562#L544-32 is_transmit8_triggered_~__retres1~8 := 0; 1245560#L555-10 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 1245558#L556-10 activate_threads_#t~ret18 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 1245556#L1089-30 assume !(0 != activate_threads_~tmp___7~0); 1245553#L1089-32 assume 1 == ~M_E~0;~M_E~0 := 2; 1245554#L1122-1 assume 1 == ~T1_E~0;~T1_E~0 := 2; 1247981#L1127-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 1247976#L1132-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 1247970#L1137-1 assume !(1 == ~T4_E~0); 1247966#L1142-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 1247955#L1147-1 assume !(1 == ~T6_E~0); 1247938#L1152-1 assume 1 == ~T7_E~0;~T7_E~0 := 2; 1247935#L1157-1 assume !(1 == ~T8_E~0); 1247933#L1162-1 assume 1 == ~E_1~0;~E_1~0 := 2; 1247931#L1167-1 assume 1 == ~E_2~0;~E_2~0 := 2; 1247929#L1172-1 assume 1 == ~E_3~0;~E_3~0 := 2; 1247927#L1177-1 assume !(1 == ~E_4~0); 1247925#L1182-1 assume 1 == ~E_5~0;~E_5~0 := 2; 1247923#L1187-1 assume !(1 == ~E_6~0); 1247921#L1192-1 assume 1 == ~E_7~0;~E_7~0 := 2; 1247919#L1197-1 assume !(1 == ~E_8~0); 1247916#L1281-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret19, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~9;havoc exists_runnable_thread_~__retres1~9; 1247913#L624-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9 := 1; 1247905#L671-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~9; 1247897#L672-2 stop_simulation_#t~ret19 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret19;havoc stop_simulation_#t~ret19; 1247887#L1236 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 1247880#L1243 stop_simulation_#res := stop_simulation_~__retres2~0; 1247872#L1244 start_simulation_#t~ret21 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret21;havoc start_simulation_#t~ret21; 1247865#L1294 assume !(0 != start_simulation_~tmp___0~1); 1242145#L1262-1 [2018-11-22 21:21:52,777 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-22 21:21:52,778 INFO L82 PathProgramCache]: Analyzing trace with hash 426104125, now seen corresponding path program 8 times [2018-11-22 21:21:52,778 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-22 21:21:52,778 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-22 21:21:52,778 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-22 21:21:52,778 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-22 21:21:52,778 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-22 21:21:52,783 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-22 21:21:52,788 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-22 21:21:52,812 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-22 21:21:52,813 INFO L82 PathProgramCache]: Analyzing trace with hash -1356175929, now seen corresponding path program 1 times [2018-11-22 21:21:52,813 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-22 21:21:52,813 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-22 21:21:52,813 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-22 21:21:52,814 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-22 21:21:52,814 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-22 21:21:52,821 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-22 21:21:52,944 INFO L134 CoverageAnalysis]: Checked inductivity of 198 backedges. 14 proven. 0 refuted. 0 times theorem prover too weak. 184 trivial. 0 not checked. [2018-11-22 21:21:52,944 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-22 21:21:52,944 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-11-22 21:21:52,944 INFO L811 eck$LassoCheckResult]: loop already infeasible [2018-11-22 21:21:52,944 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-11-22 21:21:52,945 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-11-22 21:21:52,945 INFO L87 Difference]: Start difference. First operand 72598 states and 96523 transitions. cyclomatic complexity: 23957 Second operand 5 states. [2018-11-22 21:21:53,419 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-22 21:21:53,419 INFO L93 Difference]: Finished difference Result 121870 states and 162450 transitions. [2018-11-22 21:21:53,419 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2018-11-22 21:21:53,419 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 121870 states and 162450 transitions. [2018-11-22 21:21:53,710 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 120864 [2018-11-22 21:21:53,884 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 121870 states to 121870 states and 162450 transitions. [2018-11-22 21:21:53,884 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 121870 [2018-11-22 21:21:53,928 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 121870 [2018-11-22 21:21:53,928 INFO L73 IsDeterministic]: Start isDeterministic. Operand 121870 states and 162450 transitions. [2018-11-22 21:21:53,969 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-22 21:21:53,969 INFO L705 BuchiCegarLoop]: Abstraction has 121870 states and 162450 transitions. [2018-11-22 21:21:54,015 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 121870 states and 162450 transitions. [2018-11-22 21:21:54,471 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 121870 to 73918. [2018-11-22 21:21:54,471 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 73918 states. [2018-11-22 21:21:54,541 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 73918 states to 73918 states and 97466 transitions. [2018-11-22 21:21:54,541 INFO L728 BuchiCegarLoop]: Abstraction has 73918 states and 97466 transitions. [2018-11-22 21:21:54,541 INFO L608 BuchiCegarLoop]: Abstraction has 73918 states and 97466 transitions. [2018-11-22 21:21:54,541 INFO L442 BuchiCegarLoop]: ======== Iteration 28============ [2018-11-22 21:21:54,541 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 73918 states and 97466 transitions. [2018-11-22 21:21:54,680 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 73296 [2018-11-22 21:21:54,680 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-22 21:21:54,680 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-22 21:21:54,683 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-22 21:21:54,683 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-22 21:21:54,683 INFO L794 eck$LassoCheckResult]: Stem: 1436959#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2; 1436838#L-1 havoc main_#res;havoc main_~__retres1~10;havoc main_~__retres1~10;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 1436839#L1225 havoc start_simulation_#t~ret20, start_simulation_#t~ret21, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 1437415#L564 assume 1 == ~m_i~0;~m_st~0 := 0; 1436873#L571-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1436565#L576-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1436566#L581-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 1437419#L586-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 1437119#L591-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 1436672#L596-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 1436673#L601-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 1437406#L606-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 1437279#L611-1 assume !(0 == ~M_E~0); 1437280#L828-1 assume !(0 == ~T1_E~0); 1436985#L833-1 assume !(0 == ~T2_E~0); 1436687#L838-1 assume !(0 == ~T3_E~0); 1436688#L843-1 assume !(0 == ~T4_E~0); 1437530#L848-1 assume !(0 == ~T5_E~0); 1437289#L853-1 assume !(0 == ~T6_E~0); 1436969#L858-1 assume !(0 == ~T7_E~0); 1436484#L863-1 assume !(0 == ~T8_E~0); 1436485#L868-1 assume !(0 == ~E_1~0); 1437228#L873-1 assume !(0 == ~E_2~0); 1437065#L878-1 assume !(0 == ~E_3~0); 1436807#L883-1 assume !(0 == ~E_4~0); 1436808#L888-1 assume !(0 == ~E_5~0); 1437370#L893-1 assume !(0 == ~E_6~0); 1437026#L898-1 assume !(0 == ~E_7~0); 1436943#L903-1 assume !(0 == ~E_8~0); 1436630#L908-1 havoc activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 1436631#L392 assume !(1 == ~m_pc~0); 1437009#L392-2 is_master_triggered_~__retres1~0 := 0; 1437012#L403 is_master_triggered_#res := is_master_triggered_~__retres1~0; 1437586#L404 activate_threads_#t~ret10 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 1437380#L1025 assume !(0 != activate_threads_~tmp~1); 1437381#L1025-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 1437214#L411 assume !(1 == ~t1_pc~0); 1437176#L411-2 is_transmit1_triggered_~__retres1~1 := 0; 1436549#L422 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 1436550#L423 activate_threads_#t~ret11 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 1436653#L1033 assume !(0 != activate_threads_~tmp___0~0); 1436883#L1033-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 1436884#L430 assume !(1 == ~t2_pc~0); 1437393#L430-2 is_transmit2_triggered_~__retres1~2 := 0; 1436719#L441 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 1436674#L442 activate_threads_#t~ret12 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 1436675#L1041 assume !(0 != activate_threads_~tmp___1~0); 1437624#L1041-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 1437627#L449 assume !(1 == ~t3_pc~0); 1437475#L449-2 is_transmit3_triggered_~__retres1~3 := 0; 1437639#L460 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 1437674#L461 activate_threads_#t~ret13 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 1437411#L1049 assume !(0 != activate_threads_~tmp___2~0); 1437412#L1049-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 1436586#L468 assume !(1 == ~t4_pc~0); 1436587#L468-2 is_transmit4_triggered_~__retres1~4 := 0; 1436594#L479 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 1437017#L480 activate_threads_#t~ret14 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 1436953#L1057 assume !(0 != activate_threads_~tmp___3~0); 1436954#L1057-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 1436792#L487 assume !(1 == ~t5_pc~0); 1436545#L487-2 is_transmit5_triggered_~__retres1~5 := 0; 1436544#L498 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 1437200#L499 activate_threads_#t~ret15 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 1437201#L1065 assume !(0 != activate_threads_~tmp___4~0); 1437649#L1065-2 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 1436968#L506 assume !(1 == ~t6_pc~0); 1436964#L506-2 is_transmit6_triggered_~__retres1~6 := 0; 1436965#L517 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 1437408#L518 activate_threads_#t~ret16 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 1437310#L1073 assume !(0 != activate_threads_~tmp___5~0); 1437311#L1073-2 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 1437122#L525 assume !(1 == ~t7_pc~0); 1437123#L525-2 is_transmit7_triggered_~__retres1~7 := 0; 1437125#L536 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 1437628#L537 activate_threads_#t~ret17 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 1436813#L1081 assume !(0 != activate_threads_~tmp___6~0); 1436814#L1081-2 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 1436815#L544 assume !(1 == ~t8_pc~0); 1437146#L544-2 is_transmit8_triggered_~__retres1~8 := 0; 1436478#L555 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 1436479#L556 activate_threads_#t~ret18 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 1436618#L1089 assume !(0 != activate_threads_~tmp___7~0); 1437453#L1089-2 assume !(1 == ~M_E~0); 1436979#L921-1 assume !(1 == ~T1_E~0); 1436683#L926-1 assume !(1 == ~T2_E~0); 1436684#L931-1 assume !(1 == ~T3_E~0); 1437528#L936-1 assume !(1 == ~T4_E~0); 1437301#L941-1 assume !(1 == ~T5_E~0); 1436975#L946-1 assume !(1 == ~T6_E~0); 1436494#L951-1 assume !(1 == ~T7_E~0); 1436495#L956-1 assume !(1 == ~T8_E~0); 1437414#L961-1 assume !(1 == ~E_1~0); 1437075#L966-1 assume !(1 == ~E_2~0); 1436819#L971-1 assume !(1 == ~E_3~0); 1436820#L976-1 assume !(1 == ~E_4~0); 1437365#L981-1 assume !(1 == ~E_5~0); 1437024#L986-1 assume !(1 == ~E_6~0); 1436936#L991-1 assume !(1 == ~E_7~0); 1436624#L996-1 assume !(1 == ~E_8~0); 1436625#L1262-1 [2018-11-22 21:21:54,684 INFO L796 eck$LassoCheckResult]: Loop: 1436625#L1262-1 assume !false; 1455329#L1263 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret0, eval_#t~nondet1, eval_~tmp_ndt_1~0, eval_#t~nondet2, eval_~tmp_ndt_2~0, eval_#t~nondet3, eval_~tmp_ndt_3~0, eval_#t~nondet4, eval_~tmp_ndt_4~0, eval_#t~nondet5, eval_~tmp_ndt_5~0, eval_#t~nondet6, eval_~tmp_ndt_6~0, eval_#t~nondet7, eval_~tmp_ndt_7~0, eval_#t~nondet8, eval_~tmp_ndt_8~0, eval_#t~nondet9, eval_~tmp_ndt_9~0, eval_~tmp~0;havoc eval_~tmp~0; 1455327#L803 assume !false; 1455325#L682 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~9;havoc exists_runnable_thread_~__retres1~9; 1455276#L624 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9 := 1; 1455269#L671 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~9; 1455261#L672 eval_#t~ret0 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret0;havoc eval_#t~ret0; 1455256#L686 assume 0 != eval_~tmp~0; 1455244#L686-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0;eval_~tmp_ndt_1~0 := eval_#t~nondet1;havoc eval_#t~nondet1; 1455236#L694 assume 0 != eval_~tmp_ndt_1~0;~m_st~0 := 1; 1455237#L73 assume 0 == ~m_pc~0; 1455889#L100 assume !false; 1456202#L85 ~E_1~0 := 1;havoc activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 1456196#L392-3 assume !(1 == ~m_pc~0); 1456191#L392-5 is_master_triggered_~__retres1~0 := 0; 1456186#L403-1 is_master_triggered_#res := is_master_triggered_~__retres1~0; 1456179#L404-1 activate_threads_#t~ret10 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 1456173#L1025-3 assume !(0 != activate_threads_~tmp~1); 1456168#L1025-5 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 1456155#L411-3 assume !(1 == ~t1_pc~0); 1456151#L411-5 is_transmit1_triggered_~__retres1~1 := 0; 1456148#L422-1 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 1456146#L423-1 activate_threads_#t~ret11 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 1456144#L1033-3 assume !(0 != activate_threads_~tmp___0~0); 1456141#L1033-5 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 1456139#L430-3 assume !(1 == ~t2_pc~0); 1456137#L430-5 is_transmit2_triggered_~__retres1~2 := 0; 1456135#L441-1 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 1456133#L442-1 activate_threads_#t~ret12 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 1456131#L1041-3 assume !(0 != activate_threads_~tmp___1~0); 1456129#L1041-5 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 1456127#L449-3 assume 1 == ~t3_pc~0; 1456124#L450-1 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 1456122#L460-1 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 1456105#L461-1 activate_threads_#t~ret13 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 1456098#L1049-3 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 1456092#L1049-5 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 1456086#L468-3 assume !(1 == ~t4_pc~0); 1456083#L468-5 is_transmit4_triggered_~__retres1~4 := 0; 1456076#L479-1 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 1456070#L480-1 activate_threads_#t~ret14 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 1456064#L1057-3 assume !(0 != activate_threads_~tmp___3~0); 1456058#L1057-5 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 1456052#L487-3 assume !(1 == ~t5_pc~0); 1456044#L487-5 is_transmit5_triggered_~__retres1~5 := 0; 1456038#L498-1 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 1456031#L499-1 activate_threads_#t~ret15 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 1456022#L1065-3 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 1456014#L1065-5 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 1456006#L506-3 assume !(1 == ~t6_pc~0); 1455998#L506-5 is_transmit6_triggered_~__retres1~6 := 0; 1455992#L517-1 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 1455985#L518-1 activate_threads_#t~ret16 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 1455976#L1073-3 assume !(0 != activate_threads_~tmp___5~0); 1455968#L1073-5 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 1455960#L525-3 assume !(1 == ~t7_pc~0); 1455953#L525-5 is_transmit7_triggered_~__retres1~7 := 0; 1455947#L536-1 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 1455940#L537-1 activate_threads_#t~ret17 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 1455932#L1081-3 assume !(0 != activate_threads_~tmp___6~0); 1455924#L1081-5 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 1455915#L544-3 assume !(1 == ~t8_pc~0); 1455907#L544-5 is_transmit8_triggered_~__retres1~8 := 0; 1455903#L555-1 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 1455898#L556-1 activate_threads_#t~ret18 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 1455893#L1089-3 assume !(0 != activate_threads_~tmp___7~0); 1455887#L1089-5 ~E_1~0 := 2; 1455881#L77 assume !false; 1453930#L93 ~m_pc~0 := 1;~m_st~0 := 2; 1447654#L691 assume !(0 == ~t1_st~0); 1451999#L705 assume !(0 == ~t2_st~0); 1451931#L719 assume !(0 == ~t3_st~0); 1451922#L733 assume !(0 == ~t4_st~0); 1451902#L747 assume !(0 == ~t5_st~0); 1451892#L761 assume !(0 == ~t6_st~0); 1451884#L775 assume !(0 == ~t7_st~0); 1458747#L789 assume !(0 == ~t8_st~0); 1458742#L803 assume !false; 1458739#L682 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~9;havoc exists_runnable_thread_~__retres1~9; 1458737#L624 assume !(0 == ~m_st~0); 1447664#L628 assume !(0 == ~t1_st~0); 1458734#L632 assume !(0 == ~t2_st~0); 1458732#L636 assume !(0 == ~t3_st~0); 1458731#L640 assume !(0 == ~t4_st~0); 1458727#L644 assume !(0 == ~t5_st~0); 1458725#L648 assume !(0 == ~t6_st~0); 1458721#L652 assume !(0 == ~t7_st~0); 1458717#L656 assume !(0 == ~t8_st~0);exists_runnable_thread_~__retres1~9 := 0; 1458713#L671 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~9; 1458712#L672 eval_#t~ret0 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret0;havoc eval_#t~ret0; 1458711#L686 assume !(0 != eval_~tmp~0); 1458709#L818 start_simulation_~kernel_st~0 := 2; 1458707#L564-1 start_simulation_~kernel_st~0 := 3; 1458701#L828-2 assume !(0 == ~M_E~0); 1458699#L828-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 1458697#L833-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 1458695#L838-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 1458694#L843-3 assume !(0 == ~T4_E~0); 1458692#L848-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 1458690#L853-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 1458688#L858-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 1458686#L863-3 assume !(0 == ~T8_E~0); 1458684#L868-3 assume 0 == ~E_1~0;~E_1~0 := 1; 1458682#L873-3 assume 0 == ~E_2~0;~E_2~0 := 1; 1458679#L878-3 assume 0 == ~E_3~0;~E_3~0 := 1; 1458677#L883-3 assume !(0 == ~E_4~0); 1458675#L888-3 assume 0 == ~E_5~0;~E_5~0 := 1; 1458673#L893-3 assume 0 == ~E_6~0;~E_6~0 := 1; 1458671#L898-3 assume 0 == ~E_7~0;~E_7~0 := 1; 1458669#L903-3 assume !(0 == ~E_8~0); 1458667#L908-3 havoc activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 1458664#L392-27 assume 1 == ~m_pc~0; 1458662#L393-9 assume !(1 == ~M_E~0); 1458660#L392-29 is_master_triggered_~__retres1~0 := 0; 1458658#L403-9 is_master_triggered_#res := is_master_triggered_~__retres1~0; 1458656#L404-9 activate_threads_#t~ret10 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 1458654#L1025-27 assume !(0 != activate_threads_~tmp~1); 1458652#L1025-29 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 1458650#L411-27 assume !(1 == ~t1_pc~0); 1458646#L411-29 is_transmit1_triggered_~__retres1~1 := 0; 1458644#L422-9 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 1458642#L423-9 activate_threads_#t~ret11 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 1458640#L1033-27 assume !(0 != activate_threads_~tmp___0~0); 1458637#L1033-29 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 1458635#L430-27 assume !(1 == ~t2_pc~0); 1458394#L430-29 is_transmit2_triggered_~__retres1~2 := 0; 1458389#L441-9 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 1458386#L442-9 activate_threads_#t~ret12 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 1458383#L1041-27 assume !(0 != activate_threads_~tmp___1~0); 1458380#L1041-29 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 1458377#L449-27 assume !(1 == ~t3_pc~0); 1458374#L449-29 is_transmit3_triggered_~__retres1~3 := 0; 1458369#L460-9 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 1458364#L461-9 activate_threads_#t~ret13 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 1458358#L1049-27 assume !(0 != activate_threads_~tmp___2~0); 1458351#L1049-29 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 1458346#L468-27 assume !(1 == ~t4_pc~0); 1458342#L468-29 is_transmit4_triggered_~__retres1~4 := 0; 1458338#L479-9 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 1458334#L480-9 activate_threads_#t~ret14 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 1458329#L1057-27 assume !(0 != activate_threads_~tmp___3~0); 1458322#L1057-29 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 1458317#L487-27 assume 1 == ~t5_pc~0; 1458311#L488-9 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 1458305#L498-9 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 1458299#L499-9 activate_threads_#t~ret15 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 1458292#L1065-27 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 1458286#L1065-29 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 1458281#L506-27 assume !(1 == ~t6_pc~0); 1458275#L506-29 is_transmit6_triggered_~__retres1~6 := 0; 1458268#L517-9 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 1458261#L518-9 activate_threads_#t~ret16 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 1458255#L1073-27 assume 0 != activate_threads_~tmp___5~0;~t6_st~0 := 0; 1458250#L1073-29 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 1458244#L525-27 assume !(1 == ~t7_pc~0); 1458238#L525-29 is_transmit7_triggered_~__retres1~7 := 0; 1458231#L536-9 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 1458226#L537-9 activate_threads_#t~ret17 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 1458219#L1081-27 assume !(0 != activate_threads_~tmp___6~0); 1458213#L1081-29 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 1458207#L544-27 assume !(1 == ~t8_pc~0); 1458200#L544-29 is_transmit8_triggered_~__retres1~8 := 0; 1458194#L555-9 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 1458188#L556-9 activate_threads_#t~ret18 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 1458181#L1089-27 assume !(0 != activate_threads_~tmp___7~0); 1458174#L1089-29 assume !(1 == ~M_E~0); 1456390#L921-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 1458163#L926-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 1458157#L931-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 1458151#L936-3 assume !(1 == ~T4_E~0); 1458144#L941-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 1458137#L946-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 1458132#L951-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 1458126#L956-3 assume !(1 == ~T8_E~0); 1458121#L961-3 assume 1 == ~E_1~0;~E_1~0 := 2; 1458117#L966-3 assume 1 == ~E_2~0;~E_2~0 := 2; 1458112#L971-3 assume 1 == ~E_3~0;~E_3~0 := 2; 1458103#L976-3 assume !(1 == ~E_4~0); 1457997#L981-3 assume 1 == ~E_5~0;~E_5~0 := 2; 1457989#L986-3 assume 1 == ~E_6~0;~E_6~0 := 2; 1457983#L991-3 assume 1 == ~E_7~0;~E_7~0 := 2; 1457918#L996-3 assume !(1 == ~E_8~0); 1457879#L1001-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~9;havoc exists_runnable_thread_~__retres1~9; 1457873#L624-1 assume !(0 == ~m_st~0); 1447774#L628-1 assume 0 == ~t1_st~0;exists_runnable_thread_~__retres1~9 := 1; 1457593#L671-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~9; 1457585#L672-1 start_simulation_#t~ret20 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret20;havoc start_simulation_#t~ret20; 1447991#L1281 assume 0 == start_simulation_~tmp~3;start_simulation_~kernel_st~0 := 4;~M_E~0 := 1; 1447987#L1115 havoc activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 1447984#L392-30 assume 1 == ~m_pc~0; 1447981#L393-10 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0 := 1; 1447979#L403-10 is_master_triggered_#res := is_master_triggered_~__retres1~0; 1447976#L404-10 activate_threads_#t~ret10 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 1447846#L1025-30 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 1447844#L1025-32 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 1447842#L411-30 assume 1 == ~t1_pc~0; 1447840#L412-10 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 1447841#L422-10 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 1448017#L423-10 activate_threads_#t~ret11 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 1447831#L1033-30 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 1447829#L1033-32 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 1447827#L430-30 assume !(1 == ~t2_pc~0); 1447824#L430-32 is_transmit2_triggered_~__retres1~2 := 0; 1447822#L441-10 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 1447820#L442-10 activate_threads_#t~ret12 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 1447818#L1041-30 assume !(0 != activate_threads_~tmp___1~0); 1447816#L1041-32 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 1447813#L449-30 assume 1 == ~t3_pc~0; 1447811#L450-10 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 1447812#L460-10 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 1448020#L461-10 activate_threads_#t~ret13 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 1447802#L1049-30 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 1447800#L1049-32 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 1447798#L468-30 assume !(1 == ~t4_pc~0); 1447796#L468-32 is_transmit4_triggered_~__retres1~4 := 0; 1447794#L479-10 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 1447792#L480-10 activate_threads_#t~ret14 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 1447790#L1057-30 assume !(0 != activate_threads_~tmp___3~0); 1447788#L1057-32 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 1447786#L487-30 assume 1 == ~t5_pc~0; 1447783#L488-10 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 1447781#L498-10 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 1447779#L499-10 activate_threads_#t~ret15 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 1447777#L1065-30 assume !(0 != activate_threads_~tmp___4~0); 1447775#L1065-32 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 1447772#L506-30 assume !(1 == ~t6_pc~0); 1447770#L506-32 is_transmit6_triggered_~__retres1~6 := 0; 1447768#L517-10 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 1447767#L518-10 activate_threads_#t~ret16 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 1447766#L1073-30 assume 0 != activate_threads_~tmp___5~0;~t6_st~0 := 0; 1447764#L1073-32 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 1447763#L525-30 assume !(1 == ~t7_pc~0); 1447762#L525-32 is_transmit7_triggered_~__retres1~7 := 0; 1447761#L536-10 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 1447759#L537-10 activate_threads_#t~ret17 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 1447758#L1081-30 assume !(0 != activate_threads_~tmp___6~0); 1447757#L1081-32 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 1447756#L544-30 assume !(1 == ~t8_pc~0); 1447751#L544-32 is_transmit8_triggered_~__retres1~8 := 0; 1447749#L555-10 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 1447747#L556-10 activate_threads_#t~ret18 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 1447745#L1089-30 assume !(0 != activate_threads_~tmp___7~0); 1447741#L1089-32 assume !(1 == ~M_E~0); 1447742#L1122-1 assume 1 == ~T1_E~0;~T1_E~0 := 2; 1449036#L1127-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 1449034#L1132-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 1449032#L1137-1 assume !(1 == ~T4_E~0); 1449030#L1142-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 1449028#L1147-1 assume !(1 == ~T6_E~0); 1449026#L1152-1 assume 1 == ~T7_E~0;~T7_E~0 := 2; 1449024#L1157-1 assume !(1 == ~T8_E~0); 1449020#L1162-1 assume 1 == ~E_1~0;~E_1~0 := 2; 1449018#L1167-1 assume 1 == ~E_2~0;~E_2~0 := 2; 1449016#L1172-1 assume 1 == ~E_3~0;~E_3~0 := 2; 1449014#L1177-1 assume !(1 == ~E_4~0); 1449011#L1182-1 assume 1 == ~E_5~0;~E_5~0 := 2; 1449009#L1187-1 assume !(1 == ~E_6~0); 1449005#L1192-1 assume 1 == ~E_7~0;~E_7~0 := 2; 1449003#L1197-1 assume !(1 == ~E_8~0); 1447865#L1281-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret19, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~9;havoc exists_runnable_thread_~__retres1~9; 1448999#L624-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9 := 1; 1448996#L671-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~9; 1448994#L672-2 stop_simulation_#t~ret19 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret19;havoc stop_simulation_#t~ret19; 1448992#L1236 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 1448989#L1243 stop_simulation_#res := stop_simulation_~__retres2~0; 1448987#L1244 start_simulation_#t~ret21 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret21;havoc start_simulation_#t~ret21; 1448985#L1294 assume !(0 != start_simulation_~tmp___0~1); 1448984#L1262-1 assume !false; 1448974#L1263 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret0, eval_#t~nondet1, eval_~tmp_ndt_1~0, eval_#t~nondet2, eval_~tmp_ndt_2~0, eval_#t~nondet3, eval_~tmp_ndt_3~0, eval_#t~nondet4, eval_~tmp_ndt_4~0, eval_#t~nondet5, eval_~tmp_ndt_5~0, eval_#t~nondet6, eval_~tmp_ndt_6~0, eval_#t~nondet7, eval_~tmp_ndt_7~0, eval_#t~nondet8, eval_~tmp_ndt_8~0, eval_#t~nondet9, eval_~tmp_ndt_9~0, eval_~tmp~0;havoc eval_~tmp~0; 1448972#L803 assume !false; 1448970#L682 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~9;havoc exists_runnable_thread_~__retres1~9; 1448967#L624 assume !(0 == ~m_st~0); 1448968#L628 assume !(0 == ~t1_st~0); 1456077#L632 assume !(0 == ~t2_st~0); 1456071#L636 assume !(0 == ~t3_st~0); 1456065#L640 assume !(0 == ~t4_st~0); 1456059#L644 assume !(0 == ~t5_st~0); 1456053#L648 assume !(0 == ~t6_st~0); 1456046#L652 assume !(0 == ~t7_st~0); 1456039#L656 assume !(0 == ~t8_st~0);exists_runnable_thread_~__retres1~9 := 0; 1456032#L671 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~9; 1456023#L672 eval_#t~ret0 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret0;havoc eval_#t~ret0; 1456015#L686 assume !(0 != eval_~tmp~0); 1456007#L818 start_simulation_~kernel_st~0 := 2; 1455999#L564-1 start_simulation_~kernel_st~0 := 3; 1455993#L828-2 assume 0 == ~M_E~0;~M_E~0 := 1; 1455986#L828-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 1455977#L833-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 1455969#L838-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 1455961#L843-3 assume !(0 == ~T4_E~0); 1455954#L848-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 1455948#L853-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 1455941#L858-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 1455933#L863-3 assume !(0 == ~T8_E~0); 1455925#L868-3 assume 0 == ~E_1~0;~E_1~0 := 1; 1455916#L873-3 assume 0 == ~E_2~0;~E_2~0 := 1; 1455908#L878-3 assume 0 == ~E_3~0;~E_3~0 := 1; 1453907#L883-3 assume !(0 == ~E_4~0); 1453906#L888-3 assume 0 == ~E_5~0;~E_5~0 := 1; 1453905#L893-3 assume 0 == ~E_6~0;~E_6~0 := 1; 1453904#L898-3 assume 0 == ~E_7~0;~E_7~0 := 1; 1453902#L903-3 assume !(0 == ~E_8~0); 1453901#L908-3 havoc activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 1453899#L392-27 assume 1 == ~m_pc~0; 1453897#L393-9 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0 := 1; 1453895#L403-9 is_master_triggered_#res := is_master_triggered_~__retres1~0; 1453893#L404-9 activate_threads_#t~ret10 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 1453890#L1025-27 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 1453888#L1025-29 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 1453886#L411-27 assume 1 == ~t1_pc~0; 1453884#L412-9 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 1453885#L422-9 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 1453903#L423-9 activate_threads_#t~ret11 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 1453875#L1033-27 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 1453873#L1033-29 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 1453871#L430-27 assume !(1 == ~t2_pc~0); 1453869#L430-29 is_transmit2_triggered_~__retres1~2 := 0; 1453867#L441-9 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 1453865#L442-9 activate_threads_#t~ret12 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 1453863#L1041-27 assume !(0 != activate_threads_~tmp___1~0); 1452161#L1041-29 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 1447905#L449-27 assume 1 == ~t3_pc~0; 1447903#L450-9 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 1447904#L460-9 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 1447909#L461-9 activate_threads_#t~ret13 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 1447894#L1049-27 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 1447892#L1049-29 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 1447890#L468-27 assume !(1 == ~t4_pc~0); 1447887#L468-29 is_transmit4_triggered_~__retres1~4 := 0; 1447885#L479-9 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 1447883#L480-9 activate_threads_#t~ret14 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 1447882#L1057-27 assume !(0 != activate_threads_~tmp___3~0); 1447874#L1057-29 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 1447872#L487-27 assume 1 == ~t5_pc~0; 1447868#L488-9 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 1447866#L498-9 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 1447863#L499-9 activate_threads_#t~ret15 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 1447862#L1065-27 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 1447859#L1065-29 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 1447856#L506-27 assume !(1 == ~t6_pc~0); 1447854#L506-29 is_transmit6_triggered_~__retres1~6 := 0; 1447852#L517-9 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 1447850#L518-9 activate_threads_#t~ret16 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 1447845#L1073-27 assume 0 != activate_threads_~tmp___5~0;~t6_st~0 := 0; 1447843#L1073-29 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 1447839#L525-27 assume !(1 == ~t7_pc~0); 1447837#L525-29 is_transmit7_triggered_~__retres1~7 := 0; 1447835#L536-9 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 1447833#L537-9 activate_threads_#t~ret17 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 1447830#L1081-27 assume !(0 != activate_threads_~tmp___6~0); 1447828#L1081-29 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 1447826#L544-27 assume !(1 == ~t8_pc~0); 1447823#L544-29 is_transmit8_triggered_~__retres1~8 := 0; 1447821#L555-9 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 1447819#L556-9 activate_threads_#t~ret18 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 1447817#L1089-27 assume !(0 != activate_threads_~tmp___7~0); 1447814#L1089-29 assume !(1 == ~M_E~0); 1447815#L921-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 1454197#L926-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 1454195#L931-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 1454193#L936-3 assume !(1 == ~T4_E~0); 1454191#L941-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 1454190#L946-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 1454143#L951-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 1453927#L956-3 assume !(1 == ~T8_E~0); 1453926#L961-3 assume 1 == ~E_1~0;~E_1~0 := 2; 1453925#L966-3 assume 1 == ~E_2~0;~E_2~0 := 2; 1453924#L971-3 assume 1 == ~E_3~0;~E_3~0 := 2; 1453923#L976-3 assume !(1 == ~E_4~0); 1453920#L981-3 assume 1 == ~E_5~0;~E_5~0 := 2; 1453918#L986-3 assume 1 == ~E_6~0;~E_6~0 := 2; 1453916#L991-3 assume 1 == ~E_7~0;~E_7~0 := 2; 1453914#L996-3 assume !(1 == ~E_8~0); 1453912#L1001-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~9;havoc exists_runnable_thread_~__retres1~9; 1452158#L624-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9 := 1; 1447870#L671-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~9; 1447867#L672-1 start_simulation_#t~ret20 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret20;havoc start_simulation_#t~ret20; 1447864#L1281 assume 0 == start_simulation_~tmp~3;start_simulation_~kernel_st~0 := 4;~M_E~0 := 1; 1447705#L1115 havoc activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 1447860#L392-30 assume !(1 == ~m_pc~0); 1447861#L392-32 is_master_triggered_~__retres1~0 := 0; 1449994#L403-10 is_master_triggered_#res := is_master_triggered_~__retres1~0; 1449993#L404-10 activate_threads_#t~ret10 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 1449992#L1025-30 assume !(0 != activate_threads_~tmp~1); 1449991#L1025-32 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 1449990#L411-30 assume 1 == ~t1_pc~0; 1449988#L412-10 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 1449989#L422-10 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 1449987#L423-10 activate_threads_#t~ret11 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 1449981#L1033-30 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 1449980#L1033-32 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 1449979#L430-30 assume !(1 == ~t2_pc~0); 1449978#L430-32 is_transmit2_triggered_~__retres1~2 := 0; 1449977#L441-10 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 1449975#L442-10 activate_threads_#t~ret12 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 1449974#L1041-30 assume !(0 != activate_threads_~tmp___1~0); 1449973#L1041-32 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 1449972#L449-30 assume 1 == ~t3_pc~0; 1449971#L450-10 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 1449970#L460-10 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 1449968#L461-10 activate_threads_#t~ret13 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 1449964#L1049-30 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 1449962#L1049-32 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 1449960#L468-30 assume !(1 == ~t4_pc~0); 1449958#L468-32 is_transmit4_triggered_~__retres1~4 := 0; 1449957#L479-10 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 1449953#L480-10 activate_threads_#t~ret14 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 1449951#L1057-30 assume !(0 != activate_threads_~tmp___3~0); 1449949#L1057-32 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 1449947#L487-30 assume 1 == ~t5_pc~0; 1449943#L488-10 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 1449941#L498-10 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 1449939#L499-10 activate_threads_#t~ret15 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 1449937#L1065-30 assume !(0 != activate_threads_~tmp___4~0); 1449935#L1065-32 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 1449933#L506-30 assume !(1 == ~t6_pc~0); 1449931#L506-32 is_transmit6_triggered_~__retres1~6 := 0; 1449929#L517-10 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 1449925#L518-10 activate_threads_#t~ret16 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 1449923#L1073-30 assume 0 != activate_threads_~tmp___5~0;~t6_st~0 := 0; 1449921#L1073-32 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 1449919#L525-30 assume !(1 == ~t7_pc~0); 1449916#L525-32 is_transmit7_triggered_~__retres1~7 := 0; 1449914#L536-10 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 1449912#L537-10 activate_threads_#t~ret17 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 1449910#L1081-30 assume !(0 != activate_threads_~tmp___6~0); 1449908#L1081-32 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 1449906#L544-30 assume !(1 == ~t8_pc~0); 1449903#L544-32 is_transmit8_triggered_~__retres1~8 := 0; 1449901#L555-10 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 1449899#L556-10 activate_threads_#t~ret18 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 1449896#L1089-30 assume !(0 != activate_threads_~tmp___7~0); 1449893#L1089-32 assume 1 == ~M_E~0;~M_E~0 := 2; 1449894#L1122-1 assume 1 == ~T1_E~0;~T1_E~0 := 2; 1455660#L1127-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 1455657#L1132-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 1455655#L1137-1 assume !(1 == ~T4_E~0); 1455654#L1142-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 1455650#L1147-1 assume !(1 == ~T6_E~0); 1455648#L1152-1 assume 1 == ~T7_E~0;~T7_E~0 := 2; 1455646#L1157-1 assume !(1 == ~T8_E~0); 1455644#L1162-1 assume 1 == ~E_1~0;~E_1~0 := 2; 1455641#L1167-1 assume 1 == ~E_2~0;~E_2~0 := 2; 1455639#L1172-1 assume 1 == ~E_3~0;~E_3~0 := 2; 1455635#L1177-1 assume !(1 == ~E_4~0); 1455633#L1182-1 assume 1 == ~E_5~0;~E_5~0 := 2; 1455631#L1187-1 assume !(1 == ~E_6~0); 1455629#L1192-1 assume 1 == ~E_7~0;~E_7~0 := 2; 1455626#L1197-1 assume !(1 == ~E_8~0); 1455624#L1281-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret19, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~9;havoc exists_runnable_thread_~__retres1~9; 1455621#L624-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9 := 1; 1455619#L671-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~9; 1455617#L672-2 stop_simulation_#t~ret19 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret19;havoc stop_simulation_#t~ret19; 1455615#L1236 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 1455613#L1243 stop_simulation_#res := stop_simulation_~__retres2~0; 1455611#L1244 start_simulation_#t~ret21 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret21;havoc start_simulation_#t~ret21; 1455609#L1294 assume !(0 != start_simulation_~tmp___0~1); 1436625#L1262-1 [2018-11-22 21:21:54,684 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-22 21:21:54,684 INFO L82 PathProgramCache]: Analyzing trace with hash 426104125, now seen corresponding path program 9 times [2018-11-22 21:21:54,684 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-22 21:21:54,684 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-22 21:21:54,685 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-22 21:21:54,685 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-22 21:21:54,685 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-22 21:21:54,688 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-22 21:21:54,699 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-22 21:21:54,718 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-22 21:21:54,718 INFO L82 PathProgramCache]: Analyzing trace with hash 1811700649, now seen corresponding path program 1 times [2018-11-22 21:21:54,719 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-22 21:21:54,719 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-22 21:21:54,719 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-22 21:21:54,719 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-22 21:21:54,719 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-22 21:21:54,726 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-22 21:21:54,831 INFO L134 CoverageAnalysis]: Checked inductivity of 199 backedges. 14 proven. 0 refuted. 0 times theorem prover too weak. 185 trivial. 0 not checked. [2018-11-22 21:21:54,831 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-22 21:21:54,831 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-11-22 21:21:54,831 INFO L811 eck$LassoCheckResult]: loop already infeasible [2018-11-22 21:21:54,832 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-11-22 21:21:54,832 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-11-22 21:21:54,832 INFO L87 Difference]: Start difference. First operand 73918 states and 97466 transitions. cyclomatic complexity: 23580 Second operand 5 states. [2018-11-22 21:21:55,193 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-22 21:21:55,193 INFO L93 Difference]: Finished difference Result 179953 states and 238073 transitions. [2018-11-22 21:21:55,193 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2018-11-22 21:21:55,194 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 179953 states and 238073 transitions. [2018-11-22 21:21:55,650 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 178232 [2018-11-22 21:21:56,214 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 179953 states to 179953 states and 238073 transitions. [2018-11-22 21:21:56,215 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 179953 [2018-11-22 21:21:56,263 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 179953 [2018-11-22 21:21:56,263 INFO L73 IsDeterministic]: Start isDeterministic. Operand 179953 states and 238073 transitions. [2018-11-22 21:21:56,313 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-22 21:21:56,313 INFO L705 BuchiCegarLoop]: Abstraction has 179953 states and 238073 transitions. [2018-11-22 21:21:56,365 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 179953 states and 238073 transitions. [2018-11-22 21:21:56,950 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 179953 to 76369. [2018-11-22 21:21:56,950 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 76369 states. [2018-11-22 21:21:57,026 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 76369 states to 76369 states and 99917 transitions. [2018-11-22 21:21:57,026 INFO L728 BuchiCegarLoop]: Abstraction has 76369 states and 99917 transitions. [2018-11-22 21:21:57,026 INFO L608 BuchiCegarLoop]: Abstraction has 76369 states and 99917 transitions. [2018-11-22 21:21:57,026 INFO L442 BuchiCegarLoop]: ======== Iteration 29============ [2018-11-22 21:21:57,026 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 76369 states and 99917 transitions. [2018-11-22 21:21:57,174 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 75744 [2018-11-22 21:21:57,174 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-22 21:21:57,174 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-22 21:21:57,177 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-22 21:21:57,177 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-22 21:21:57,177 INFO L794 eck$LassoCheckResult]: Stem: 1690884#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2; 1690757#L-1 havoc main_#res;havoc main_~__retres1~10;havoc main_~__retres1~10;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 1690758#L1225 havoc start_simulation_#t~ret20, start_simulation_#t~ret21, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 1691372#L564 assume 1 == ~m_i~0;~m_st~0 := 0; 1690796#L571-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1690457#L576-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1690458#L581-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 1691387#L586-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 1691042#L591-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 1690572#L596-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 1690573#L601-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 1691364#L606-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 1691210#L611-1 assume !(0 == ~M_E~0); 1691211#L828-1 assume !(0 == ~T1_E~0); 1690911#L833-1 assume !(0 == ~T2_E~0); 1690587#L838-1 assume !(0 == ~T3_E~0); 1690588#L843-1 assume !(0 == ~T4_E~0); 1691523#L848-1 assume !(0 == ~T5_E~0); 1691222#L853-1 assume !(0 == ~T6_E~0); 1690894#L858-1 assume !(0 == ~T7_E~0); 1690369#L863-1 assume !(0 == ~T8_E~0); 1690370#L868-1 assume !(0 == ~E_1~0); 1691165#L873-1 assume !(0 == ~E_2~0); 1690990#L878-1 assume !(0 == ~E_3~0); 1690726#L883-1 assume !(0 == ~E_4~0); 1690727#L888-1 assume !(0 == ~E_5~0); 1691322#L893-1 assume !(0 == ~E_6~0); 1690954#L898-1 assume !(0 == ~E_7~0); 1690872#L903-1 assume !(0 == ~E_8~0); 1690525#L908-1 havoc activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 1690526#L392 assume !(1 == ~m_pc~0); 1690933#L392-2 is_master_triggered_~__retres1~0 := 0; 1690938#L403 is_master_triggered_#res := is_master_triggered_~__retres1~0; 1691586#L404 activate_threads_#t~ret10 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 1691335#L1025 assume !(0 != activate_threads_~tmp~1); 1691336#L1025-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 1691145#L411 assume !(1 == ~t1_pc~0); 1691111#L411-2 is_transmit1_triggered_~__retres1~1 := 0; 1690440#L422 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 1690441#L423 activate_threads_#t~ret11 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 1690551#L1033 assume !(0 != activate_threads_~tmp___0~0); 1690807#L1033-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 1690808#L430 assume !(1 == ~t2_pc~0); 1691351#L430-2 is_transmit2_triggered_~__retres1~2 := 0; 1690628#L441 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 1690574#L442 activate_threads_#t~ret12 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 1690575#L1041 assume !(0 != activate_threads_~tmp___1~0); 1691641#L1041-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 1691644#L449 assume !(1 == ~t3_pc~0); 1691454#L449-2 is_transmit3_triggered_~__retres1~3 := 0; 1690970#L460 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 1690971#L461 activate_threads_#t~ret13 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 1691368#L1049 assume !(0 != activate_threads_~tmp___2~0); 1691369#L1049-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 1690483#L468 assume !(1 == ~t4_pc~0); 1690484#L468-2 is_transmit4_triggered_~__retres1~4 := 0; 1690489#L479 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 1690946#L480 activate_threads_#t~ret14 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 1690878#L1057 assume !(0 != activate_threads_~tmp___3~0); 1690879#L1057-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 1690710#L487 assume !(1 == ~t5_pc~0); 1690432#L487-2 is_transmit5_triggered_~__retres1~5 := 0; 1690712#L498 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 1691392#L499 activate_threads_#t~ret15 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 1691664#L1065 assume !(0 != activate_threads_~tmp___4~0); 1691665#L1065-2 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 1690893#L506 assume !(1 == ~t6_pc~0); 1690889#L506-2 is_transmit6_triggered_~__retres1~6 := 0; 1690890#L517 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 1691366#L518 activate_threads_#t~ret16 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 1691242#L1073 assume !(0 != activate_threads_~tmp___5~0); 1691243#L1073-2 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 1691044#L525 assume !(1 == ~t7_pc~0); 1691045#L525-2 is_transmit7_triggered_~__retres1~7 := 0; 1691047#L536 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 1691645#L537 activate_threads_#t~ret17 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 1690732#L1081 assume !(0 != activate_threads_~tmp___6~0); 1690733#L1081-2 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 1690734#L544 assume !(1 == ~t8_pc~0); 1691072#L544-2 is_transmit8_triggered_~__retres1~8 := 0; 1690363#L555 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 1690364#L556 activate_threads_#t~ret18 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 1690513#L1089 assume !(0 != activate_threads_~tmp___7~0); 1691433#L1089-2 assume !(1 == ~M_E~0); 1690905#L921-1 assume !(1 == ~T1_E~0); 1690583#L926-1 assume !(1 == ~T2_E~0); 1690584#L931-1 assume !(1 == ~T3_E~0); 1691521#L936-1 assume !(1 == ~T4_E~0); 1691233#L941-1 assume !(1 == ~T5_E~0); 1690901#L946-1 assume !(1 == ~T6_E~0); 1690379#L951-1 assume !(1 == ~T7_E~0); 1690380#L956-1 assume !(1 == ~T8_E~0); 1691371#L961-1 assume !(1 == ~E_1~0); 1690998#L966-1 assume !(1 == ~E_2~0); 1690738#L971-1 assume !(1 == ~E_3~0); 1690739#L976-1 assume !(1 == ~E_4~0); 1691314#L981-1 assume !(1 == ~E_5~0); 1690952#L986-1 assume !(1 == ~E_6~0); 1690863#L991-1 assume !(1 == ~E_7~0); 1690519#L996-1 assume !(1 == ~E_8~0); 1690520#L1262-1 [2018-11-22 21:21:57,178 INFO L796 eck$LassoCheckResult]: Loop: 1690520#L1262-1 assume !false; 1713003#L1263 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret0, eval_#t~nondet1, eval_~tmp_ndt_1~0, eval_#t~nondet2, eval_~tmp_ndt_2~0, eval_#t~nondet3, eval_~tmp_ndt_3~0, eval_#t~nondet4, eval_~tmp_ndt_4~0, eval_#t~nondet5, eval_~tmp_ndt_5~0, eval_#t~nondet6, eval_~tmp_ndt_6~0, eval_#t~nondet7, eval_~tmp_ndt_7~0, eval_#t~nondet8, eval_~tmp_ndt_8~0, eval_#t~nondet9, eval_~tmp_ndt_9~0, eval_~tmp~0;havoc eval_~tmp~0; 1713001#L803 assume !false; 1712999#L682 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~9;havoc exists_runnable_thread_~__retres1~9; 1712996#L624 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9 := 1; 1712994#L671 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~9; 1712992#L672 eval_#t~ret0 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret0;havoc eval_#t~ret0; 1712990#L686 assume 0 != eval_~tmp~0; 1712930#L686-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0;eval_~tmp_ndt_1~0 := eval_#t~nondet1;havoc eval_#t~nondet1; 1712919#L694 assume 0 != eval_~tmp_ndt_1~0;~m_st~0 := 1; 1712920#L73 assume 0 == ~m_pc~0; 1712670#L100 assume !false; 1713133#L85 ~E_1~0 := 1;havoc activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 1713132#L392-3 assume !(1 == ~m_pc~0); 1713131#L392-5 is_master_triggered_~__retres1~0 := 0; 1713130#L403-1 is_master_triggered_#res := is_master_triggered_~__retres1~0; 1713129#L404-1 activate_threads_#t~ret10 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 1713128#L1025-3 assume !(0 != activate_threads_~tmp~1); 1713127#L1025-5 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 1713126#L411-3 assume 1 == ~t1_pc~0; 1713124#L412-1 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 1713122#L422-1 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 1713120#L423-1 activate_threads_#t~ret11 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 1713118#L1033-3 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 1713117#L1033-5 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 1713116#L430-3 assume !(1 == ~t2_pc~0); 1713115#L430-5 is_transmit2_triggered_~__retres1~2 := 0; 1713114#L441-1 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 1713113#L442-1 activate_threads_#t~ret12 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 1713112#L1041-3 assume !(0 != activate_threads_~tmp___1~0); 1713111#L1041-5 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 1713110#L449-3 assume 1 == ~t3_pc~0; 1713108#L450-1 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 1713106#L460-1 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 1713104#L461-1 activate_threads_#t~ret13 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 1713102#L1049-3 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 1713101#L1049-5 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 1713100#L468-3 assume !(1 == ~t4_pc~0); 1713099#L468-5 is_transmit4_triggered_~__retres1~4 := 0; 1713098#L479-1 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 1713097#L480-1 activate_threads_#t~ret14 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 1713096#L1057-3 assume !(0 != activate_threads_~tmp___3~0); 1713095#L1057-5 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 1713094#L487-3 assume 1 == ~t5_pc~0; 1713092#L488-1 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 1713090#L498-1 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 1713088#L499-1 activate_threads_#t~ret15 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 1713086#L1065-3 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 1713014#L1065-5 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 1713012#L506-3 assume !(1 == ~t6_pc~0); 1713010#L506-5 is_transmit6_triggered_~__retres1~6 := 0; 1713008#L517-1 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 1713002#L518-1 activate_threads_#t~ret16 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 1713000#L1073-3 assume !(0 != activate_threads_~tmp___5~0); 1712998#L1073-5 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 1712995#L525-3 assume !(1 == ~t7_pc~0); 1712993#L525-5 is_transmit7_triggered_~__retres1~7 := 0; 1712991#L536-1 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 1712989#L537-1 activate_threads_#t~ret17 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 1712931#L1081-3 assume !(0 != activate_threads_~tmp___6~0); 1712921#L1081-5 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 1712830#L544-3 assume !(1 == ~t8_pc~0); 1712827#L544-5 is_transmit8_triggered_~__retres1~8 := 0; 1712817#L555-1 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 1712732#L556-1 activate_threads_#t~ret18 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 1712677#L1089-3 assume !(0 != activate_threads_~tmp___7~0); 1712668#L1089-5 ~E_1~0 := 2; 1712662#L77 assume !false; 1712650#L93 ~m_pc~0 := 1;~m_st~0 := 2; 1707290#L691 assume !(0 == ~t1_st~0); 1712633#L705 assume !(0 == ~t2_st~0); 1712626#L719 assume !(0 == ~t3_st~0); 1714444#L733 assume !(0 == ~t4_st~0); 1714438#L747 assume !(0 == ~t5_st~0); 1714431#L761 assume !(0 == ~t6_st~0); 1714423#L775 assume !(0 == ~t7_st~0); 1714409#L789 assume !(0 == ~t8_st~0); 1714404#L803 assume !false; 1714402#L682 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~9;havoc exists_runnable_thread_~__retres1~9; 1699863#L624 assume !(0 == ~m_st~0); 1699857#L628 assume !(0 == ~t1_st~0); 1699851#L632 assume !(0 == ~t2_st~0); 1699845#L636 assume !(0 == ~t3_st~0); 1699793#L640 assume !(0 == ~t4_st~0); 1699787#L644 assume !(0 == ~t5_st~0); 1699782#L648 assume !(0 == ~t6_st~0); 1699781#L652 assume !(0 == ~t7_st~0); 1699779#L656 assume !(0 == ~t8_st~0);exists_runnable_thread_~__retres1~9 := 0; 1699778#L671 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~9; 1699728#L672 eval_#t~ret0 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret0;havoc eval_#t~ret0; 1699725#L686 assume !(0 != eval_~tmp~0); 1699723#L818 start_simulation_~kernel_st~0 := 2; 1699721#L564-1 start_simulation_~kernel_st~0 := 3; 1699719#L828-2 assume !(0 == ~M_E~0); 1699717#L828-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 1699715#L833-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 1699713#L838-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 1699711#L843-3 assume !(0 == ~T4_E~0); 1699709#L848-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 1699707#L853-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 1699705#L858-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 1699703#L863-3 assume !(0 == ~T8_E~0); 1699701#L868-3 assume 0 == ~E_1~0;~E_1~0 := 1; 1699698#L873-3 assume 0 == ~E_2~0;~E_2~0 := 1; 1699696#L878-3 assume 0 == ~E_3~0;~E_3~0 := 1; 1699694#L883-3 assume !(0 == ~E_4~0); 1699692#L888-3 assume 0 == ~E_5~0;~E_5~0 := 1; 1699690#L893-3 assume 0 == ~E_6~0;~E_6~0 := 1; 1699687#L898-3 assume 0 == ~E_7~0;~E_7~0 := 1; 1699685#L903-3 assume !(0 == ~E_8~0); 1699683#L908-3 havoc activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 1699681#L392-27 assume 1 == ~m_pc~0; 1699680#L393-9 assume !(1 == ~M_E~0); 1699679#L392-29 is_master_triggered_~__retres1~0 := 0; 1699678#L403-9 is_master_triggered_#res := is_master_triggered_~__retres1~0; 1699677#L404-9 activate_threads_#t~ret10 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 1699676#L1025-27 assume !(0 != activate_threads_~tmp~1); 1699675#L1025-29 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 1699674#L411-27 assume !(1 == ~t1_pc~0); 1699673#L411-29 is_transmit1_triggered_~__retres1~1 := 0; 1699671#L422-9 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 1699669#L423-9 activate_threads_#t~ret11 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 1699667#L1033-27 assume !(0 != activate_threads_~tmp___0~0); 1699665#L1033-29 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 1699664#L430-27 assume !(1 == ~t2_pc~0); 1699663#L430-29 is_transmit2_triggered_~__retres1~2 := 0; 1699662#L441-9 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 1699661#L442-9 activate_threads_#t~ret12 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 1699660#L1041-27 assume !(0 != activate_threads_~tmp___1~0); 1699659#L1041-29 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 1699658#L449-27 assume !(1 == ~t3_pc~0); 1699657#L449-29 is_transmit3_triggered_~__retres1~3 := 0; 1699655#L460-9 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 1699653#L461-9 activate_threads_#t~ret13 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 1699651#L1049-27 assume !(0 != activate_threads_~tmp___2~0); 1699649#L1049-29 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 1699648#L468-27 assume !(1 == ~t4_pc~0); 1699647#L468-29 is_transmit4_triggered_~__retres1~4 := 0; 1699646#L479-9 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 1699645#L480-9 activate_threads_#t~ret14 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 1699644#L1057-27 assume !(0 != activate_threads_~tmp___3~0); 1699643#L1057-29 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 1699642#L487-27 assume !(1 == ~t5_pc~0); 1699641#L487-29 is_transmit5_triggered_~__retres1~5 := 0; 1699639#L498-9 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 1699637#L499-9 activate_threads_#t~ret15 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 1699635#L1065-27 assume !(0 != activate_threads_~tmp___4~0); 1699632#L1065-29 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 1699630#L506-27 assume !(1 == ~t6_pc~0); 1699628#L506-29 is_transmit6_triggered_~__retres1~6 := 0; 1699626#L517-9 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 1699624#L518-9 activate_threads_#t~ret16 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 1699622#L1073-27 assume 0 != activate_threads_~tmp___5~0;~t6_st~0 := 0; 1699620#L1073-29 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 1699618#L525-27 assume !(1 == ~t7_pc~0); 1699616#L525-29 is_transmit7_triggered_~__retres1~7 := 0; 1699614#L536-9 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 1699612#L537-9 activate_threads_#t~ret17 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 1699610#L1081-27 assume !(0 != activate_threads_~tmp___6~0); 1699608#L1081-29 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 1699606#L544-27 assume !(1 == ~t8_pc~0); 1699603#L544-29 is_transmit8_triggered_~__retres1~8 := 0; 1699600#L555-9 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 1699598#L556-9 activate_threads_#t~ret18 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 1699597#L1089-27 assume !(0 != activate_threads_~tmp___7~0); 1699502#L1089-29 assume !(1 == ~M_E~0); 1699500#L921-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 1699498#L926-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 1699496#L931-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 1699494#L936-3 assume !(1 == ~T4_E~0); 1699491#L941-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 1699489#L946-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 1699487#L951-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 1699484#L956-3 assume !(1 == ~T8_E~0); 1699482#L961-3 assume 1 == ~E_1~0;~E_1~0 := 2; 1699480#L966-3 assume 1 == ~E_2~0;~E_2~0 := 2; 1699478#L971-3 assume 1 == ~E_3~0;~E_3~0 := 2; 1699476#L976-3 assume !(1 == ~E_4~0); 1699474#L981-3 assume 1 == ~E_5~0;~E_5~0 := 2; 1699472#L986-3 assume 1 == ~E_6~0;~E_6~0 := 2; 1699470#L991-3 assume 1 == ~E_7~0;~E_7~0 := 2; 1699468#L996-3 assume !(1 == ~E_8~0); 1699466#L1001-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~9;havoc exists_runnable_thread_~__retres1~9; 1699464#L624-1 assume !(0 == ~m_st~0); 1698421#L628-1 assume 0 == ~t1_st~0;exists_runnable_thread_~__retres1~9 := 1; 1699391#L671-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~9; 1699383#L672-1 start_simulation_#t~ret20 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret20;havoc start_simulation_#t~ret20; 1699373#L1281 assume 0 == start_simulation_~tmp~3;start_simulation_~kernel_st~0 := 4;~M_E~0 := 1; 1698812#L1115 havoc activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 1699363#L392-30 assume 1 == ~m_pc~0; 1699361#L393-10 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0 := 1; 1699360#L403-10 is_master_triggered_#res := is_master_triggered_~__retres1~0; 1699359#L404-10 activate_threads_#t~ret10 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 1699349#L1025-30 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 1699348#L1025-32 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 1699347#L411-30 assume 1 == ~t1_pc~0; 1699345#L412-10 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 1699343#L422-10 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 1699341#L423-10 activate_threads_#t~ret11 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 1699339#L1033-30 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 1699338#L1033-32 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 1699337#L430-30 assume !(1 == ~t2_pc~0); 1699336#L430-32 is_transmit2_triggered_~__retres1~2 := 0; 1699335#L441-10 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 1699334#L442-10 activate_threads_#t~ret12 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 1699333#L1041-30 assume !(0 != activate_threads_~tmp___1~0); 1699332#L1041-32 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 1699331#L449-30 assume 1 == ~t3_pc~0; 1699329#L450-10 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 1699327#L460-10 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 1699325#L461-10 activate_threads_#t~ret13 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 1699323#L1049-30 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 1699322#L1049-32 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 1699321#L468-30 assume !(1 == ~t4_pc~0); 1699320#L468-32 is_transmit4_triggered_~__retres1~4 := 0; 1699319#L479-10 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 1699318#L480-10 activate_threads_#t~ret14 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 1699317#L1057-30 assume !(0 != activate_threads_~tmp___3~0); 1699316#L1057-32 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 1699315#L487-30 assume !(1 == ~t5_pc~0); 1699313#L487-32 is_transmit5_triggered_~__retres1~5 := 0; 1699311#L498-10 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 1699309#L499-10 activate_threads_#t~ret15 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 1699307#L1065-30 assume !(0 != activate_threads_~tmp___4~0); 1697626#L1065-32 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 1697622#L506-30 assume !(1 == ~t6_pc~0); 1697620#L506-32 is_transmit6_triggered_~__retres1~6 := 0; 1697616#L517-10 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 1697614#L518-10 activate_threads_#t~ret16 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 1697612#L1073-30 assume 0 != activate_threads_~tmp___5~0;~t6_st~0 := 0; 1697610#L1073-32 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 1697607#L525-30 assume !(1 == ~t7_pc~0); 1697605#L525-32 is_transmit7_triggered_~__retres1~7 := 0; 1697604#L536-10 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 1697600#L537-10 activate_threads_#t~ret17 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 1697598#L1081-30 assume !(0 != activate_threads_~tmp___6~0); 1697596#L1081-32 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 1697594#L544-30 assume !(1 == ~t8_pc~0); 1697590#L544-32 is_transmit8_triggered_~__retres1~8 := 0; 1697588#L555-10 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 1697584#L556-10 activate_threads_#t~ret18 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 1697582#L1089-30 assume !(0 != activate_threads_~tmp___7~0); 1697579#L1089-32 assume !(1 == ~M_E~0); 1697577#L1122-1 assume 1 == ~T1_E~0;~T1_E~0 := 2; 1697574#L1127-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 1697572#L1132-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 1697570#L1137-1 assume !(1 == ~T4_E~0); 1697568#L1142-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 1697566#L1147-1 assume !(1 == ~T6_E~0); 1697564#L1152-1 assume 1 == ~T7_E~0;~T7_E~0 := 2; 1697562#L1157-1 assume !(1 == ~T8_E~0); 1697560#L1162-1 assume 1 == ~E_1~0;~E_1~0 := 2; 1697558#L1167-1 assume 1 == ~E_2~0;~E_2~0 := 2; 1697555#L1172-1 assume 1 == ~E_3~0;~E_3~0 := 2; 1697553#L1177-1 assume !(1 == ~E_4~0); 1697551#L1182-1 assume 1 == ~E_5~0;~E_5~0 := 2; 1697548#L1187-1 assume !(1 == ~E_6~0); 1697546#L1192-1 assume 1 == ~E_7~0;~E_7~0 := 2; 1697544#L1197-1 assume !(1 == ~E_8~0); 1697540#L1281-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret19, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~9;havoc exists_runnable_thread_~__retres1~9; 1697537#L624-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9 := 1; 1697535#L671-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~9; 1697533#L672-2 stop_simulation_#t~ret19 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret19;havoc stop_simulation_#t~ret19; 1697531#L1236 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 1697529#L1243 stop_simulation_#res := stop_simulation_~__retres2~0; 1697527#L1244 start_simulation_#t~ret21 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret21;havoc start_simulation_#t~ret21; 1697525#L1294 assume !(0 != start_simulation_~tmp___0~1); 1697523#L1262-1 assume !false; 1697318#L1263 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret0, eval_#t~nondet1, eval_~tmp_ndt_1~0, eval_#t~nondet2, eval_~tmp_ndt_2~0, eval_#t~nondet3, eval_~tmp_ndt_3~0, eval_#t~nondet4, eval_~tmp_ndt_4~0, eval_#t~nondet5, eval_~tmp_ndt_5~0, eval_#t~nondet6, eval_~tmp_ndt_6~0, eval_#t~nondet7, eval_~tmp_ndt_7~0, eval_#t~nondet8, eval_~tmp_ndt_8~0, eval_#t~nondet9, eval_~tmp_ndt_9~0, eval_~tmp~0;havoc eval_~tmp~0; 1697316#L803 assume !false; 1697313#L682 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~9;havoc exists_runnable_thread_~__retres1~9; 1697308#L624 assume !(0 == ~m_st~0); 1697309#L628 assume !(0 == ~t1_st~0); 1698754#L632 assume !(0 == ~t2_st~0); 1698753#L636 assume !(0 == ~t3_st~0); 1698752#L640 assume !(0 == ~t4_st~0); 1698751#L644 assume !(0 == ~t5_st~0); 1698750#L648 assume !(0 == ~t6_st~0); 1698749#L652 assume !(0 == ~t7_st~0); 1698608#L656 assume !(0 == ~t8_st~0);exists_runnable_thread_~__retres1~9 := 0; 1698606#L671 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~9; 1698604#L672 eval_#t~ret0 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret0;havoc eval_#t~ret0; 1698602#L686 assume !(0 != eval_~tmp~0); 1698600#L818 start_simulation_~kernel_st~0 := 2; 1698598#L564-1 start_simulation_~kernel_st~0 := 3; 1698596#L828-2 assume 0 == ~M_E~0;~M_E~0 := 1; 1698594#L828-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 1698592#L833-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 1698590#L838-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 1698588#L843-3 assume !(0 == ~T4_E~0); 1698586#L848-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 1698584#L853-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 1698582#L858-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 1698579#L863-3 assume !(0 == ~T8_E~0); 1698577#L868-3 assume 0 == ~E_1~0;~E_1~0 := 1; 1698575#L873-3 assume 0 == ~E_2~0;~E_2~0 := 1; 1698573#L878-3 assume 0 == ~E_3~0;~E_3~0 := 1; 1698571#L883-3 assume !(0 == ~E_4~0); 1698570#L888-3 assume 0 == ~E_5~0;~E_5~0 := 1; 1698566#L893-3 assume 0 == ~E_6~0;~E_6~0 := 1; 1698564#L898-3 assume 0 == ~E_7~0;~E_7~0 := 1; 1698559#L903-3 assume !(0 == ~E_8~0); 1698556#L908-3 havoc activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 1698554#L392-27 assume 1 == ~m_pc~0; 1698552#L393-9 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0 := 1; 1698551#L403-9 is_master_triggered_#res := is_master_triggered_~__retres1~0; 1698550#L404-9 activate_threads_#t~ret10 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 1698548#L1025-27 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 1698547#L1025-29 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 1698546#L411-27 assume !(1 == ~t1_pc~0); 1698545#L411-29 is_transmit1_triggered_~__retres1~1 := 0; 1698543#L422-9 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 1698541#L423-9 activate_threads_#t~ret11 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 1698539#L1033-27 assume !(0 != activate_threads_~tmp___0~0); 1698537#L1033-29 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 1698536#L430-27 assume !(1 == ~t2_pc~0); 1698535#L430-29 is_transmit2_triggered_~__retres1~2 := 0; 1698534#L441-9 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 1698533#L442-9 activate_threads_#t~ret12 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 1698532#L1041-27 assume !(0 != activate_threads_~tmp___1~0); 1698531#L1041-29 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 1698530#L449-27 assume !(1 == ~t3_pc~0); 1698529#L449-29 is_transmit3_triggered_~__retres1~3 := 0; 1698527#L460-9 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 1698525#L461-9 activate_threads_#t~ret13 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 1698523#L1049-27 assume !(0 != activate_threads_~tmp___2~0); 1698521#L1049-29 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 1698520#L468-27 assume !(1 == ~t4_pc~0); 1698519#L468-29 is_transmit4_triggered_~__retres1~4 := 0; 1698518#L479-9 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 1698517#L480-9 activate_threads_#t~ret14 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 1698516#L1057-27 assume !(0 != activate_threads_~tmp___3~0); 1698515#L1057-29 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 1698514#L487-27 assume !(1 == ~t5_pc~0); 1698513#L487-29 is_transmit5_triggered_~__retres1~5 := 0; 1698511#L498-9 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 1698509#L499-9 activate_threads_#t~ret15 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 1698507#L1065-27 assume !(0 != activate_threads_~tmp___4~0); 1698504#L1065-29 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 1698502#L506-27 assume !(1 == ~t6_pc~0); 1698500#L506-29 is_transmit6_triggered_~__retres1~6 := 0; 1698498#L517-9 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 1698495#L518-9 activate_threads_#t~ret16 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 1698493#L1073-27 assume 0 != activate_threads_~tmp___5~0;~t6_st~0 := 0; 1698491#L1073-29 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 1698489#L525-27 assume !(1 == ~t7_pc~0); 1698487#L525-29 is_transmit7_triggered_~__retres1~7 := 0; 1698484#L536-9 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 1698482#L537-9 activate_threads_#t~ret17 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 1698480#L1081-27 assume !(0 != activate_threads_~tmp___6~0); 1698478#L1081-29 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 1698476#L544-27 assume !(1 == ~t8_pc~0); 1698473#L544-29 is_transmit8_triggered_~__retres1~8 := 0; 1698471#L555-9 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 1698469#L556-9 activate_threads_#t~ret18 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 1698467#L1089-27 assume !(0 != activate_threads_~tmp___7~0); 1698464#L1089-29 assume 1 == ~M_E~0;~M_E~0 := 2; 1698462#L921-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 1698460#L926-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 1698458#L931-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 1698456#L936-3 assume !(1 == ~T4_E~0); 1698454#L941-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 1698452#L946-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 1698448#L951-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 1698446#L956-3 assume !(1 == ~T8_E~0); 1698444#L961-3 assume 1 == ~E_1~0;~E_1~0 := 2; 1698443#L966-3 assume 1 == ~E_2~0;~E_2~0 := 2; 1698435#L971-3 assume 1 == ~E_3~0;~E_3~0 := 2; 1698433#L976-3 assume !(1 == ~E_4~0); 1698431#L981-3 assume 1 == ~E_5~0;~E_5~0 := 2; 1698429#L986-3 assume 1 == ~E_6~0;~E_6~0 := 2; 1698427#L991-3 assume 1 == ~E_7~0;~E_7~0 := 2; 1698425#L996-3 assume !(1 == ~E_8~0); 1698423#L1001-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~9;havoc exists_runnable_thread_~__retres1~9; 1698420#L624-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9 := 1; 1698419#L671-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~9; 1698418#L672-1 start_simulation_#t~ret20 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret20;havoc start_simulation_#t~ret20; 1698416#L1281 assume 0 == start_simulation_~tmp~3;start_simulation_~kernel_st~0 := 4;~M_E~0 := 1; 1697543#L1115 havoc activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 1698414#L392-30 assume !(1 == ~m_pc~0); 1698413#L392-32 is_master_triggered_~__retres1~0 := 0; 1698412#L403-10 is_master_triggered_#res := is_master_triggered_~__retres1~0; 1698411#L404-10 activate_threads_#t~ret10 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 1698410#L1025-30 assume !(0 != activate_threads_~tmp~1); 1698409#L1025-32 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 1698408#L411-30 assume !(1 == ~t1_pc~0); 1698407#L411-32 is_transmit1_triggered_~__retres1~1 := 0; 1698405#L422-10 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 1698403#L423-10 activate_threads_#t~ret11 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 1698401#L1033-30 assume !(0 != activate_threads_~tmp___0~0); 1698399#L1033-32 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 1698398#L430-30 assume !(1 == ~t2_pc~0); 1698397#L430-32 is_transmit2_triggered_~__retres1~2 := 0; 1698396#L441-10 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 1698395#L442-10 activate_threads_#t~ret12 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 1698394#L1041-30 assume !(0 != activate_threads_~tmp___1~0); 1698393#L1041-32 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 1698392#L449-30 assume !(1 == ~t3_pc~0); 1698391#L449-32 is_transmit3_triggered_~__retres1~3 := 0; 1698389#L460-10 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 1698387#L461-10 activate_threads_#t~ret13 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 1698385#L1049-30 assume !(0 != activate_threads_~tmp___2~0); 1698383#L1049-32 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 1698382#L468-30 assume !(1 == ~t4_pc~0); 1698381#L468-32 is_transmit4_triggered_~__retres1~4 := 0; 1698380#L479-10 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 1698379#L480-10 activate_threads_#t~ret14 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 1698378#L1057-30 assume !(0 != activate_threads_~tmp___3~0); 1698377#L1057-32 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 1698376#L487-30 assume 1 == ~t5_pc~0; 1698375#L488-10 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 1698373#L498-10 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 1698371#L499-10 activate_threads_#t~ret15 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 1698369#L1065-30 assume !(0 != activate_threads_~tmp___4~0); 1698366#L1065-32 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 1698363#L506-30 assume !(1 == ~t6_pc~0); 1698359#L506-32 is_transmit6_triggered_~__retres1~6 := 0; 1698358#L517-10 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 1698357#L518-10 activate_threads_#t~ret16 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 1698355#L1073-30 assume 0 != activate_threads_~tmp___5~0;~t6_st~0 := 0; 1698353#L1073-32 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 1698347#L525-30 assume !(1 == ~t7_pc~0); 1698345#L525-32 is_transmit7_triggered_~__retres1~7 := 0; 1698343#L536-10 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 1698341#L537-10 activate_threads_#t~ret17 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 1698340#L1081-30 assume !(0 != activate_threads_~tmp___6~0); 1698338#L1081-32 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 1698336#L544-30 assume !(1 == ~t8_pc~0); 1698333#L544-32 is_transmit8_triggered_~__retres1~8 := 0; 1698331#L555-10 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 1698329#L556-10 activate_threads_#t~ret18 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 1698327#L1089-30 assume !(0 != activate_threads_~tmp___7~0); 1698323#L1089-32 assume 1 == ~M_E~0;~M_E~0 := 2; 1698324#L1122-1 assume 1 == ~T1_E~0;~T1_E~0 := 2; 1713806#L1127-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 1713803#L1132-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 1713749#L1137-1 assume !(1 == ~T4_E~0); 1713748#L1142-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 1713747#L1147-1 assume !(1 == ~T6_E~0); 1713745#L1152-1 assume 1 == ~T7_E~0;~T7_E~0 := 2; 1713744#L1157-1 assume !(1 == ~T8_E~0); 1713694#L1162-1 assume 1 == ~E_1~0;~E_1~0 := 2; 1713692#L1167-1 assume 1 == ~E_2~0;~E_2~0 := 2; 1713680#L1172-1 assume 1 == ~E_3~0;~E_3~0 := 2; 1713673#L1177-1 assume !(1 == ~E_4~0); 1713667#L1182-1 assume 1 == ~E_5~0;~E_5~0 := 2; 1713661#L1187-1 assume !(1 == ~E_6~0); 1713656#L1192-1 assume 1 == ~E_7~0;~E_7~0 := 2; 1713548#L1197-1 assume !(1 == ~E_8~0); 1713541#L1281-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret19, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~9;havoc exists_runnable_thread_~__retres1~9; 1713501#L624-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9 := 1; 1713492#L671-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~9; 1713484#L672-2 stop_simulation_#t~ret19 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret19;havoc stop_simulation_#t~ret19; 1713151#L1236 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 1713144#L1243 stop_simulation_#res := stop_simulation_~__retres2~0; 1713141#L1244 start_simulation_#t~ret21 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret21;havoc start_simulation_#t~ret21; 1713139#L1294 assume !(0 != start_simulation_~tmp___0~1); 1690520#L1262-1 [2018-11-22 21:21:57,178 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-22 21:21:57,178 INFO L82 PathProgramCache]: Analyzing trace with hash 426104125, now seen corresponding path program 10 times [2018-11-22 21:21:57,178 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-22 21:21:57,179 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-22 21:21:57,179 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-22 21:21:57,179 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-22 21:21:57,179 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-22 21:21:57,183 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-22 21:21:57,191 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-22 21:21:57,221 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-22 21:21:57,222 INFO L82 PathProgramCache]: Analyzing trace with hash 928777438, now seen corresponding path program 1 times [2018-11-22 21:21:57,222 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-22 21:21:57,222 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-22 21:21:57,222 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-22 21:21:57,223 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-22 21:21:57,223 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-22 21:21:57,231 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-22 21:21:57,319 INFO L134 CoverageAnalysis]: Checked inductivity of 198 backedges. 14 proven. 0 refuted. 0 times theorem prover too weak. 184 trivial. 0 not checked. [2018-11-22 21:21:57,319 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-22 21:21:57,319 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-22 21:21:57,319 INFO L811 eck$LassoCheckResult]: loop already infeasible [2018-11-22 21:21:57,319 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-22 21:21:57,320 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-22 21:21:57,320 INFO L87 Difference]: Start difference. First operand 76369 states and 99917 transitions. cyclomatic complexity: 23580 Second operand 3 states. [2018-11-22 21:21:57,601 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-22 21:21:57,601 INFO L93 Difference]: Finished difference Result 146125 states and 189492 transitions. [2018-11-22 21:21:57,601 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-22 21:21:57,602 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 146125 states and 189492 transitions. [2018-11-22 21:21:57,971 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 144880 [2018-11-22 21:21:58,201 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 146125 states to 146125 states and 189492 transitions. [2018-11-22 21:21:58,202 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 146125 [2018-11-22 21:21:58,264 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 146125 [2018-11-22 21:21:58,264 INFO L73 IsDeterministic]: Start isDeterministic. Operand 146125 states and 189492 transitions. [2018-11-22 21:21:58,315 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-22 21:21:58,316 INFO L705 BuchiCegarLoop]: Abstraction has 146125 states and 189492 transitions. [2018-11-22 21:21:58,377 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 146125 states and 189492 transitions. [2018-11-22 21:21:59,130 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 146125 to 138573. [2018-11-22 21:21:59,130 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 138573 states. [2018-11-22 21:21:59,817 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 138573 states to 138573 states and 180340 transitions. [2018-11-22 21:21:59,817 INFO L728 BuchiCegarLoop]: Abstraction has 138573 states and 180340 transitions. [2018-11-22 21:21:59,817 INFO L608 BuchiCegarLoop]: Abstraction has 138573 states and 180340 transitions. [2018-11-22 21:21:59,818 INFO L442 BuchiCegarLoop]: ======== Iteration 30============ [2018-11-22 21:21:59,818 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 138573 states and 180340 transitions. [2018-11-22 21:22:00,006 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 137328 [2018-11-22 21:22:00,006 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-22 21:22:00,006 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-22 21:22:00,009 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-22 21:22:00,009 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-22 21:22:00,009 INFO L794 eck$LassoCheckResult]: Stem: 1913355#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2; 1913232#L-1 havoc main_#res;havoc main_~__retres1~10;havoc main_~__retres1~10;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 1913233#L1225 havoc start_simulation_#t~ret20, start_simulation_#t~ret21, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 1913827#L564 assume 1 == ~m_i~0;~m_st~0 := 0; 1913267#L571-1 assume !(1 == ~t1_i~0);~t1_st~0 := 2; 1913268#L576-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1914058#L581-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 1914059#L586-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 1913512#L591-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 1913513#L596-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 1914038#L601-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 1914039#L606-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 1913673#L611-1 assume !(0 == ~M_E~0); 1913674#L828-1 assume !(0 == ~T1_E~0); 1913379#L833-1 assume !(0 == ~T2_E~0); 1913380#L838-1 assume !(0 == ~T3_E~0); 1914049#L843-1 assume !(0 == ~T4_E~0); 1914050#L848-1 assume !(0 == ~T5_E~0); 1913685#L853-1 assume !(0 == ~T6_E~0); 1913686#L858-1 assume !(0 == ~T7_E~0); 1912869#L863-1 assume !(0 == ~T8_E~0); 1912870#L868-1 assume !(0 == ~E_1~0); 1913628#L873-1 assume !(0 == ~E_2~0); 1913629#L878-1 assume !(0 == ~E_3~0); 1913199#L883-1 assume !(0 == ~E_4~0); 1913200#L888-1 assume !(0 == ~E_5~0); 1913772#L893-1 assume !(0 == ~E_6~0); 1913773#L898-1 assume !(0 == ~E_7~0); 1913340#L903-1 assume !(0 == ~E_8~0); 1913341#L908-1 havoc activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 1913402#L392 assume !(1 == ~m_pc~0); 1913403#L392-2 is_master_triggered_~__retres1~0 := 0; 1914018#L403 is_master_triggered_#res := is_master_triggered_~__retres1~0; 1914019#L404 activate_threads_#t~ret10 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 1913783#L1025 assume !(0 != activate_threads_~tmp~1); 1913784#L1025-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 1913611#L411 assume !(1 == ~t1_pc~0); 1913612#L411-2 is_transmit1_triggered_~__retres1~1 := 0; 1912937#L422 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 1912938#L423 activate_threads_#t~ret11 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 1913276#L1033 assume !(0 != activate_threads_~tmp___0~0); 1913277#L1033-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 1913800#L430 assume !(1 == ~t2_pc~0); 1913801#L430-2 is_transmit2_triggered_~__retres1~2 := 0; 1913115#L441 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 1913116#L442 activate_threads_#t~ret12 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 1914054#L1041 assume !(0 != activate_threads_~tmp___1~0); 1914055#L1041-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 1914070#L449 assume !(1 == ~t3_pc~0); 1914071#L449-2 is_transmit3_triggered_~__retres1~3 := 0; 1914108#L460 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 1914109#L461 activate_threads_#t~ret13 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 1913822#L1049 assume !(0 != activate_threads_~tmp___2~0); 1913823#L1049-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 1912978#L468 assume !(1 == ~t4_pc~0); 1912979#L468-2 is_transmit4_triggered_~__retres1~4 := 0; 1913682#L479 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 1913683#L480 activate_threads_#t~ret14 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 1913348#L1057 assume !(0 != activate_threads_~tmp___3~0); 1913349#L1057-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 1913181#L487 assume !(1 == ~t5_pc~0); 1913182#L487-2 is_transmit5_triggered_~__retres1~5 := 0; 1914113#L498 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 1914114#L499 activate_threads_#t~ret15 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 1914086#L1065 assume !(0 != activate_threads_~tmp___4~0); 1914087#L1065-2 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 1913362#L506 assume !(1 == ~t6_pc~0); 1913363#L506-2 is_transmit6_triggered_~__retres1~6 := 0; 1913977#L517 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 1913978#L518 activate_threads_#t~ret16 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 1913709#L1073 assume !(0 != activate_threads_~tmp___5~0); 1913710#L1073-2 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 1913515#L525 assume !(1 == ~t7_pc~0); 1913516#L525-2 is_transmit7_triggered_~__retres1~7 := 0; 1914101#L536 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 1914102#L537 activate_threads_#t~ret17 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 1913205#L1081 assume !(0 != activate_threads_~tmp___6~0); 1913206#L1081-2 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 1913543#L544 assume !(1 == ~t8_pc~0); 1913544#L544-2 is_transmit8_triggered_~__retres1~8 := 0; 1912863#L555 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 1912864#L556 activate_threads_#t~ret18 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 1913008#L1089 assume !(0 != activate_threads_~tmp___7~0); 1913877#L1089-2 assume !(1 == ~M_E~0); 1913374#L921-1 assume !(1 == ~T1_E~0); 1913074#L926-1 assume !(1 == ~T2_E~0); 1913075#L931-1 assume !(1 == ~T3_E~0); 1913956#L936-1 assume !(1 == ~T4_E~0); 1913696#L941-1 assume !(1 == ~T5_E~0); 1913371#L946-1 assume !(1 == ~T6_E~0); 1912879#L951-1 assume !(1 == ~T7_E~0); 1912880#L956-1 assume !(1 == ~T8_E~0); 1913826#L961-1 assume !(1 == ~E_1~0); 1913472#L966-1 assume !(1 == ~E_2~0); 1913212#L971-1 assume !(1 == ~E_3~0); 1913213#L976-1 assume !(1 == ~E_4~0); 1913765#L981-1 assume !(1 == ~E_5~0); 1913420#L986-1 assume !(1 == ~E_6~0); 1913333#L991-1 assume !(1 == ~E_7~0); 1913334#L996-1 assume !(1 == ~E_8~0); 1928950#L1262-1 [2018-11-22 21:22:00,010 INFO L796 eck$LassoCheckResult]: Loop: 1928950#L1262-1 assume !false; 1928880#L1263 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret0, eval_#t~nondet1, eval_~tmp_ndt_1~0, eval_#t~nondet2, eval_~tmp_ndt_2~0, eval_#t~nondet3, eval_~tmp_ndt_3~0, eval_#t~nondet4, eval_~tmp_ndt_4~0, eval_#t~nondet5, eval_~tmp_ndt_5~0, eval_#t~nondet6, eval_~tmp_ndt_6~0, eval_#t~nondet7, eval_~tmp_ndt_7~0, eval_#t~nondet8, eval_~tmp_ndt_8~0, eval_#t~nondet9, eval_~tmp_ndt_9~0, eval_~tmp~0;havoc eval_~tmp~0; 1928879#L803 assume !false; 1928878#L682 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~9;havoc exists_runnable_thread_~__retres1~9; 1928876#L624 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9 := 1; 1928875#L671 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~9; 1928873#L672 eval_#t~ret0 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret0;havoc eval_#t~ret0; 1928872#L686 assume 0 != eval_~tmp~0; 1928870#L686-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0;eval_~tmp_ndt_1~0 := eval_#t~nondet1;havoc eval_#t~nondet1; 1928868#L694 assume 0 != eval_~tmp_ndt_1~0;~m_st~0 := 1; 1928864#L73 assume 0 == ~m_pc~0; 1928724#L100 assume !false; 1928863#L85 ~E_1~0 := 1;havoc activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 1928862#L392-3 assume !(1 == ~m_pc~0); 1928860#L392-5 is_master_triggered_~__retres1~0 := 0; 1928859#L403-1 is_master_triggered_#res := is_master_triggered_~__retres1~0; 1928858#L404-1 activate_threads_#t~ret10 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 1928856#L1025-3 assume !(0 != activate_threads_~tmp~1); 1928855#L1025-5 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 1928854#L411-3 assume 1 == ~t1_pc~0; 1928853#L412-1 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 1928849#L422-1 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 1928846#L423-1 activate_threads_#t~ret11 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 1928847#L1033-3 assume !(0 != activate_threads_~tmp___0~0); 1928842#L1033-5 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 1928840#L430-3 assume !(1 == ~t2_pc~0); 1928838#L430-5 is_transmit2_triggered_~__retres1~2 := 0; 1928836#L441-1 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 1928834#L442-1 activate_threads_#t~ret12 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 1928830#L1041-3 assume !(0 != activate_threads_~tmp___1~0); 1928828#L1041-5 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 1928823#L449-3 assume 1 == ~t3_pc~0; 1928824#L450-1 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 1928825#L460-1 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 1928861#L461-1 activate_threads_#t~ret13 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 1928813#L1049-3 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 1928811#L1049-5 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 1928809#L468-3 assume !(1 == ~t4_pc~0); 1928807#L468-5 is_transmit4_triggered_~__retres1~4 := 0; 1928805#L479-1 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 1928803#L480-1 activate_threads_#t~ret14 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 1928800#L1057-3 assume !(0 != activate_threads_~tmp___3~0); 1928798#L1057-5 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 1928796#L487-3 assume 1 == ~t5_pc~0; 1928794#L488-1 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 1928795#L498-1 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 1928874#L499-1 activate_threads_#t~ret15 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 1928783#L1065-3 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 1928781#L1065-5 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 1928779#L506-3 assume !(1 == ~t6_pc~0); 1928777#L506-5 is_transmit6_triggered_~__retres1~6 := 0; 1928775#L517-1 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 1928773#L518-1 activate_threads_#t~ret16 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 1928771#L1073-3 assume !(0 != activate_threads_~tmp___5~0); 1928769#L1073-5 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 1928766#L525-3 assume !(1 == ~t7_pc~0); 1928764#L525-5 is_transmit7_triggered_~__retres1~7 := 0; 1928762#L536-1 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 1928759#L537-1 activate_threads_#t~ret17 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 1928757#L1081-3 assume !(0 != activate_threads_~tmp___6~0); 1928755#L1081-5 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 1928753#L544-3 assume !(1 == ~t8_pc~0); 1928749#L544-5 is_transmit8_triggered_~__retres1~8 := 0; 1928747#L555-1 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 1928745#L556-1 activate_threads_#t~ret18 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 1928742#L1089-3 assume !(0 != activate_threads_~tmp___7~0); 1928722#L1089-5 ~E_1~0 := 2; 1928720#L77 assume !false; 1928718#L93 ~m_pc~0 := 1;~m_st~0 := 2; 1928717#L691 assume !(0 == ~t1_st~0); 1929083#L705 assume !(0 == ~t2_st~0); 1928931#L719 assume !(0 == ~t3_st~0); 1928928#L733 assume !(0 == ~t4_st~0); 1928905#L747 assume !(0 == ~t5_st~0); 1928212#L761 assume !(0 == ~t6_st~0); 1928209#L775 assume !(0 == ~t7_st~0); 1928193#L789 assume !(0 == ~t8_st~0); 1928180#L803 assume !false; 1928164#L682 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~9;havoc exists_runnable_thread_~__retres1~9; 1928152#L624 assume !(0 == ~m_st~0); 1928150#L628 assume !(0 == ~t1_st~0); 1928149#L632 assume !(0 == ~t2_st~0); 1928148#L636 assume !(0 == ~t3_st~0); 1928147#L640 assume !(0 == ~t4_st~0); 1928146#L644 assume !(0 == ~t5_st~0); 1928145#L648 assume !(0 == ~t6_st~0); 1928144#L652 assume !(0 == ~t7_st~0); 1928142#L656 assume !(0 == ~t8_st~0);exists_runnable_thread_~__retres1~9 := 0; 1928141#L671 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~9; 1928140#L672 eval_#t~ret0 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret0;havoc eval_#t~ret0; 1928138#L686 assume !(0 != eval_~tmp~0); 1928137#L818 start_simulation_~kernel_st~0 := 2; 1928136#L564-1 start_simulation_~kernel_st~0 := 3; 1928135#L828-2 assume !(0 == ~M_E~0); 1928134#L828-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 1928133#L833-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 1928132#L838-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 1928131#L843-3 assume !(0 == ~T4_E~0); 1928130#L848-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 1928129#L853-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 1928128#L858-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 1928127#L863-3 assume !(0 == ~T8_E~0); 1928126#L868-3 assume 0 == ~E_1~0;~E_1~0 := 1; 1928125#L873-3 assume 0 == ~E_2~0;~E_2~0 := 1; 1928124#L878-3 assume 0 == ~E_3~0;~E_3~0 := 1; 1928123#L883-3 assume !(0 == ~E_4~0); 1928122#L888-3 assume 0 == ~E_5~0;~E_5~0 := 1; 1928121#L893-3 assume 0 == ~E_6~0;~E_6~0 := 1; 1928120#L898-3 assume 0 == ~E_7~0;~E_7~0 := 1; 1928119#L903-3 assume !(0 == ~E_8~0); 1928118#L908-3 havoc activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 1928116#L392-27 assume 1 == ~m_pc~0; 1928115#L393-9 assume !(1 == ~M_E~0); 1928114#L392-29 is_master_triggered_~__retres1~0 := 0; 1928113#L403-9 is_master_triggered_#res := is_master_triggered_~__retres1~0; 1928112#L404-9 activate_threads_#t~ret10 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 1928111#L1025-27 assume !(0 != activate_threads_~tmp~1); 1928110#L1025-29 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 1928109#L411-27 assume 1 == ~t1_pc~0; 1928108#L412-9 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 1928099#L422-9 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 1927931#L423-9 activate_threads_#t~ret11 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 1927932#L1033-27 assume !(0 != activate_threads_~tmp___0~0); 1927000#L1033-29 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 1926998#L430-27 assume !(1 == ~t2_pc~0); 1926996#L430-29 is_transmit2_triggered_~__retres1~2 := 0; 1926993#L441-9 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 1926991#L442-9 activate_threads_#t~ret12 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 1926989#L1041-27 assume !(0 != activate_threads_~tmp___1~0); 1926987#L1041-29 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 1926985#L449-27 assume !(1 == ~t3_pc~0); 1926980#L449-29 is_transmit3_triggered_~__retres1~3 := 0; 1926978#L460-9 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 1926976#L461-9 activate_threads_#t~ret13 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 1926974#L1049-27 assume !(0 != activate_threads_~tmp___2~0); 1926971#L1049-29 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 1926969#L468-27 assume !(1 == ~t4_pc~0); 1926967#L468-29 is_transmit4_triggered_~__retres1~4 := 0; 1926965#L479-9 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 1926963#L480-9 activate_threads_#t~ret14 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 1926961#L1057-27 assume !(0 != activate_threads_~tmp___3~0); 1926959#L1057-29 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 1926957#L487-27 assume !(1 == ~t5_pc~0); 1926955#L487-29 is_transmit5_triggered_~__retres1~5 := 0; 1927165#L498-9 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 1926899#L499-9 activate_threads_#t~ret15 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 1926896#L1065-27 assume !(0 != activate_threads_~tmp___4~0); 1926893#L1065-29 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 1926891#L506-27 assume !(1 == ~t6_pc~0); 1926889#L506-29 is_transmit6_triggered_~__retres1~6 := 0; 1926887#L517-9 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 1926885#L518-9 activate_threads_#t~ret16 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 1926883#L1073-27 assume 0 != activate_threads_~tmp___5~0;~t6_st~0 := 0; 1926881#L1073-29 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 1926879#L525-27 assume !(1 == ~t7_pc~0); 1926876#L525-29 is_transmit7_triggered_~__retres1~7 := 0; 1926874#L536-9 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 1926872#L537-9 activate_threads_#t~ret17 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 1926869#L1081-27 assume !(0 != activate_threads_~tmp___6~0); 1926867#L1081-29 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 1926865#L544-27 assume !(1 == ~t8_pc~0); 1926862#L544-29 is_transmit8_triggered_~__retres1~8 := 0; 1926860#L555-9 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 1926858#L556-9 activate_threads_#t~ret18 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 1926856#L1089-27 assume !(0 != activate_threads_~tmp___7~0); 1926854#L1089-29 assume !(1 == ~M_E~0); 1926119#L921-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 1926851#L926-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 1926849#L931-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 1926847#L936-3 assume !(1 == ~T4_E~0); 1926845#L941-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 1926843#L946-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 1926840#L951-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 1926838#L956-3 assume !(1 == ~T8_E~0); 1926836#L961-3 assume 1 == ~E_1~0;~E_1~0 := 2; 1926834#L966-3 assume 1 == ~E_2~0;~E_2~0 := 2; 1926784#L971-3 assume 1 == ~E_3~0;~E_3~0 := 2; 1926763#L976-3 assume !(1 == ~E_4~0); 1926757#L981-3 assume 1 == ~E_5~0;~E_5~0 := 2; 1926751#L986-3 assume 1 == ~E_6~0;~E_6~0 := 2; 1926744#L991-3 assume 1 == ~E_7~0;~E_7~0 := 2; 1926736#L996-3 assume !(1 == ~E_8~0); 1926725#L1001-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~9;havoc exists_runnable_thread_~__retres1~9; 1926720#L624-1 assume !(0 == ~m_st~0); 1925303#L628-1 assume !(0 == ~t1_st~0); 1926709#L632-1 assume 0 == ~t2_st~0;exists_runnable_thread_~__retres1~9 := 1; 1926706#L671-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~9; 1926215#L672-1 start_simulation_#t~ret20 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret20;havoc start_simulation_#t~ret20; 1925713#L1281 assume 0 == start_simulation_~tmp~3;start_simulation_~kernel_st~0 := 4;~M_E~0 := 1; 1925710#L1115 havoc activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 1925707#L392-30 assume 1 == ~m_pc~0; 1925704#L393-10 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0 := 1; 1925703#L403-10 is_master_triggered_#res := is_master_triggered_~__retres1~0; 1925702#L404-10 activate_threads_#t~ret10 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 1925692#L1025-30 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 1925690#L1025-32 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 1925689#L411-30 assume !(1 == ~t1_pc~0); 1925687#L411-32 is_transmit1_triggered_~__retres1~1 := 0; 1925884#L422-10 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 1925882#L423-10 activate_threads_#t~ret11 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 1921042#L1033-30 assume !(0 != activate_threads_~tmp___0~0); 1921035#L1033-32 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 1921027#L430-30 assume !(1 == ~t2_pc~0); 1921020#L430-32 is_transmit2_triggered_~__retres1~2 := 0; 1921013#L441-10 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 1921004#L442-10 activate_threads_#t~ret12 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 1920998#L1041-30 assume !(0 != activate_threads_~tmp___1~0); 1920992#L1041-32 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 1920984#L449-30 assume !(1 == ~t3_pc~0); 1920979#L449-32 is_transmit3_triggered_~__retres1~3 := 0; 1921101#L460-10 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 1921095#L461-10 activate_threads_#t~ret13 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 1919641#L1049-30 assume !(0 != activate_threads_~tmp___2~0); 1919636#L1049-32 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 1919634#L468-30 assume !(1 == ~t4_pc~0); 1919632#L468-32 is_transmit4_triggered_~__retres1~4 := 0; 1919630#L479-10 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 1919627#L480-10 activate_threads_#t~ret14 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 1919625#L1057-30 assume !(0 != activate_threads_~tmp___3~0); 1919622#L1057-32 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 1919620#L487-30 assume 1 == ~t5_pc~0; 1919617#L488-10 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 1919615#L498-10 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 1919613#L499-10 activate_threads_#t~ret15 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 1919611#L1065-30 assume !(0 != activate_threads_~tmp___4~0); 1919608#L1065-32 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 1919606#L506-30 assume !(1 == ~t6_pc~0); 1919604#L506-32 is_transmit6_triggered_~__retres1~6 := 0; 1919602#L517-10 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 1919600#L518-10 activate_threads_#t~ret16 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 1919598#L1073-30 assume 0 != activate_threads_~tmp___5~0;~t6_st~0 := 0; 1919596#L1073-32 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 1919594#L525-30 assume !(1 == ~t7_pc~0); 1919591#L525-32 is_transmit7_triggered_~__retres1~7 := 0; 1919589#L536-10 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 1919587#L537-10 activate_threads_#t~ret17 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 1919585#L1081-30 assume !(0 != activate_threads_~tmp___6~0); 1919583#L1081-32 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 1919580#L544-30 assume !(1 == ~t8_pc~0); 1919577#L544-32 is_transmit8_triggered_~__retres1~8 := 0; 1919575#L555-10 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 1919573#L556-10 activate_threads_#t~ret18 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 1919571#L1089-30 assume !(0 != activate_threads_~tmp___7~0); 1919568#L1089-32 assume !(1 == ~M_E~0); 1919566#L1122-1 assume 1 == ~T1_E~0;~T1_E~0 := 2; 1919564#L1127-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 1919562#L1132-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 1919560#L1137-1 assume !(1 == ~T4_E~0); 1919558#L1142-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 1919556#L1147-1 assume !(1 == ~T6_E~0); 1919554#L1152-1 assume 1 == ~T7_E~0;~T7_E~0 := 2; 1919552#L1157-1 assume !(1 == ~T8_E~0); 1919550#L1162-1 assume 1 == ~E_1~0;~E_1~0 := 2; 1919548#L1167-1 assume 1 == ~E_2~0;~E_2~0 := 2; 1919546#L1172-1 assume 1 == ~E_3~0;~E_3~0 := 2; 1919544#L1177-1 assume !(1 == ~E_4~0); 1919541#L1182-1 assume 1 == ~E_5~0;~E_5~0 := 2; 1919539#L1187-1 assume !(1 == ~E_6~0); 1919537#L1192-1 assume 1 == ~E_7~0;~E_7~0 := 2; 1919536#L1197-1 assume !(1 == ~E_8~0); 1919533#L1281-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret19, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~9;havoc exists_runnable_thread_~__retres1~9; 1919530#L624-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9 := 1; 1919528#L671-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~9; 1919526#L672-2 stop_simulation_#t~ret19 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret19;havoc stop_simulation_#t~ret19; 1919524#L1236 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 1919522#L1243 stop_simulation_#res := stop_simulation_~__retres2~0; 1919520#L1244 start_simulation_#t~ret21 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret21;havoc start_simulation_#t~ret21; 1919518#L1294 assume !(0 != start_simulation_~tmp___0~1); 1919516#L1262-1 assume !false; 1919499#L1263 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret0, eval_#t~nondet1, eval_~tmp_ndt_1~0, eval_#t~nondet2, eval_~tmp_ndt_2~0, eval_#t~nondet3, eval_~tmp_ndt_3~0, eval_#t~nondet4, eval_~tmp_ndt_4~0, eval_#t~nondet5, eval_~tmp_ndt_5~0, eval_#t~nondet6, eval_~tmp_ndt_6~0, eval_#t~nondet7, eval_~tmp_ndt_7~0, eval_#t~nondet8, eval_~tmp_ndt_8~0, eval_#t~nondet9, eval_~tmp_ndt_9~0, eval_~tmp~0;havoc eval_~tmp~0; 1919497#L803 assume !false; 1919495#L682 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~9;havoc exists_runnable_thread_~__retres1~9; 1919492#L624 assume !(0 == ~m_st~0); 1919493#L628 assume !(0 == ~t1_st~0); 1926012#L632 assume !(0 == ~t2_st~0); 1926010#L636 assume !(0 == ~t3_st~0); 1926008#L640 assume !(0 == ~t4_st~0); 1926006#L644 assume !(0 == ~t5_st~0); 1926004#L648 assume !(0 == ~t6_st~0); 1926002#L652 assume !(0 == ~t7_st~0); 1925999#L656 assume !(0 == ~t8_st~0);exists_runnable_thread_~__retres1~9 := 0; 1925997#L671 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~9; 1925993#L672 eval_#t~ret0 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret0;havoc eval_#t~ret0; 1925991#L686 assume !(0 != eval_~tmp~0); 1925989#L818 start_simulation_~kernel_st~0 := 2; 1925987#L564-1 start_simulation_~kernel_st~0 := 3; 1925984#L828-2 assume 0 == ~M_E~0;~M_E~0 := 1; 1925982#L828-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 1925980#L833-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 1925978#L838-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 1925976#L843-3 assume !(0 == ~T4_E~0); 1925974#L848-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 1925972#L853-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 1925970#L858-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 1925968#L863-3 assume !(0 == ~T8_E~0); 1925965#L868-3 assume 0 == ~E_1~0;~E_1~0 := 1; 1925963#L873-3 assume 0 == ~E_2~0;~E_2~0 := 1; 1925961#L878-3 assume 0 == ~E_3~0;~E_3~0 := 1; 1925958#L883-3 assume !(0 == ~E_4~0); 1925956#L888-3 assume 0 == ~E_5~0;~E_5~0 := 1; 1925954#L893-3 assume 0 == ~E_6~0;~E_6~0 := 1; 1925951#L898-3 assume 0 == ~E_7~0;~E_7~0 := 1; 1925949#L903-3 assume !(0 == ~E_8~0); 1925947#L908-3 havoc activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 1925944#L392-27 assume 1 == ~m_pc~0; 1925941#L393-9 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0 := 1; 1925939#L403-9 is_master_triggered_#res := is_master_triggered_~__retres1~0; 1925937#L404-9 activate_threads_#t~ret10 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 1925934#L1025-27 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 1925932#L1025-29 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 1925930#L411-27 assume !(1 == ~t1_pc~0); 1925928#L411-29 is_transmit1_triggered_~__retres1~1 := 0; 1927994#L422-9 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 1927991#L423-9 activate_threads_#t~ret11 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 1919688#L1033-27 assume !(0 != activate_threads_~tmp___0~0); 1919686#L1033-29 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 1919684#L430-27 assume !(1 == ~t2_pc~0); 1919682#L430-29 is_transmit2_triggered_~__retres1~2 := 0; 1919680#L441-9 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 1919678#L442-9 activate_threads_#t~ret12 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 1919676#L1041-27 assume !(0 != activate_threads_~tmp___1~0); 1919674#L1041-29 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 1919672#L449-27 assume !(1 == ~t3_pc~0); 1919668#L449-29 is_transmit3_triggered_~__retres1~3 := 0; 1919665#L460-9 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 1919663#L461-9 activate_threads_#t~ret13 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 1919661#L1049-27 assume !(0 != activate_threads_~tmp___2~0); 1919658#L1049-29 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 1919656#L468-27 assume !(1 == ~t4_pc~0); 1919655#L468-29 is_transmit4_triggered_~__retres1~4 := 0; 1919654#L479-9 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 1919653#L480-9 activate_threads_#t~ret14 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 1919652#L1057-27 assume !(0 != activate_threads_~tmp___3~0); 1919651#L1057-29 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 1919649#L487-27 assume !(1 == ~t5_pc~0); 1919647#L487-29 is_transmit5_triggered_~__retres1~5 := 0; 1920865#L498-9 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 1920854#L499-9 activate_threads_#t~ret15 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 1919624#L1065-27 assume !(0 != activate_threads_~tmp___4~0); 1919621#L1065-29 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 1919619#L506-27 assume !(1 == ~t6_pc~0); 1919616#L506-29 is_transmit6_triggered_~__retres1~6 := 0; 1919614#L517-9 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 1919612#L518-9 activate_threads_#t~ret16 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 1919609#L1073-27 assume 0 != activate_threads_~tmp___5~0;~t6_st~0 := 0; 1919607#L1073-29 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 1919605#L525-27 assume !(1 == ~t7_pc~0); 1919603#L525-29 is_transmit7_triggered_~__retres1~7 := 0; 1919601#L536-9 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 1919599#L537-9 activate_threads_#t~ret17 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 1919597#L1081-27 assume !(0 != activate_threads_~tmp___6~0); 1919595#L1081-29 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 1919593#L544-27 assume !(1 == ~t8_pc~0); 1919590#L544-29 is_transmit8_triggered_~__retres1~8 := 0; 1919588#L555-9 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 1919586#L556-9 activate_threads_#t~ret18 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 1919584#L1089-27 assume !(0 != activate_threads_~tmp___7~0); 1919581#L1089-29 assume 1 == ~M_E~0;~M_E~0 := 2; 1919582#L921-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 1925342#L926-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 1925339#L931-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 1925337#L936-3 assume !(1 == ~T4_E~0); 1925335#L941-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 1925333#L946-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 1925331#L951-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 1925327#L956-3 assume !(1 == ~T8_E~0); 1925325#L961-3 assume 1 == ~E_1~0;~E_1~0 := 2; 1925323#L966-3 assume 1 == ~E_2~0;~E_2~0 := 2; 1925321#L971-3 assume 1 == ~E_3~0;~E_3~0 := 2; 1925318#L976-3 assume !(1 == ~E_4~0); 1925316#L981-3 assume 1 == ~E_5~0;~E_5~0 := 2; 1925312#L986-3 assume 1 == ~E_6~0;~E_6~0 := 2; 1925310#L991-3 assume 1 == ~E_7~0;~E_7~0 := 2; 1925308#L996-3 assume !(1 == ~E_8~0); 1925306#L1001-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~9;havoc exists_runnable_thread_~__retres1~9; 1925302#L624-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9 := 1; 1925301#L671-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~9; 1925300#L672-1 start_simulation_#t~ret20 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret20;havoc start_simulation_#t~ret20; 1925297#L1281 assume 0 == start_simulation_~tmp~3;start_simulation_~kernel_st~0 := 4;~M_E~0 := 1; 1919535#L1115 havoc activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 1925293#L392-30 assume !(1 == ~m_pc~0); 1925290#L392-32 is_master_triggered_~__retres1~0 := 0; 1925288#L403-10 is_master_triggered_#res := is_master_triggered_~__retres1~0; 1925286#L404-10 activate_threads_#t~ret10 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 1925284#L1025-30 assume !(0 != activate_threads_~tmp~1); 1925282#L1025-32 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 1925280#L411-30 assume 1 == ~t1_pc~0; 1925277#L412-10 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 1925274#L422-10 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 1925272#L423-10 activate_threads_#t~ret11 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 1924880#L1033-30 assume !(0 != activate_threads_~tmp___0~0); 1922313#L1033-32 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 1922311#L430-30 assume !(1 == ~t2_pc~0); 1922310#L430-32 is_transmit2_triggered_~__retres1~2 := 0; 1922309#L441-10 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 1922307#L442-10 activate_threads_#t~ret12 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 1922305#L1041-30 assume !(0 != activate_threads_~tmp___1~0); 1922304#L1041-32 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 1921736#L449-30 assume !(1 == ~t3_pc~0); 1921732#L449-32 is_transmit3_triggered_~__retres1~3 := 0; 1921730#L460-10 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 1921728#L461-10 activate_threads_#t~ret13 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 1921725#L1049-30 assume !(0 != activate_threads_~tmp___2~0); 1921722#L1049-32 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 1921721#L468-30 assume !(1 == ~t4_pc~0); 1921684#L468-32 is_transmit4_triggered_~__retres1~4 := 0; 1921676#L479-10 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 1921643#L480-10 activate_threads_#t~ret14 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 1921642#L1057-30 assume !(0 != activate_threads_~tmp___3~0); 1921641#L1057-32 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 1921640#L487-30 assume !(1 == ~t5_pc~0); 1921639#L487-32 is_transmit5_triggered_~__retres1~5 := 0; 1921637#L498-10 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 1921635#L499-10 activate_threads_#t~ret15 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 1921632#L1065-30 assume !(0 != activate_threads_~tmp___4~0); 1921631#L1065-32 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 1921619#L506-30 assume !(1 == ~t6_pc~0); 1921610#L506-32 is_transmit6_triggered_~__retres1~6 := 0; 1921601#L517-10 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 1921587#L518-10 activate_threads_#t~ret16 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 1921576#L1073-30 assume 0 != activate_threads_~tmp___5~0;~t6_st~0 := 0; 1921557#L1073-32 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 1921553#L525-30 assume !(1 == ~t7_pc~0); 1921551#L525-32 is_transmit7_triggered_~__retres1~7 := 0; 1921549#L536-10 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 1921547#L537-10 activate_threads_#t~ret17 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 1921540#L1081-30 assume !(0 != activate_threads_~tmp___6~0); 1920288#L1081-32 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 1920284#L544-30 assume !(1 == ~t8_pc~0); 1920281#L544-32 is_transmit8_triggered_~__retres1~8 := 0; 1920279#L555-10 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 1920277#L556-10 activate_threads_#t~ret18 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 1920274#L1089-30 assume !(0 != activate_threads_~tmp___7~0); 1920271#L1089-32 assume 1 == ~M_E~0;~M_E~0 := 2; 1920272#L1122-1 assume 1 == ~T1_E~0;~T1_E~0 := 2; 1929253#L1127-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 1929249#L1132-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 1929246#L1137-1 assume !(1 == ~T4_E~0); 1929242#L1142-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 1929239#L1147-1 assume !(1 == ~T6_E~0); 1929236#L1152-1 assume 1 == ~T7_E~0;~T7_E~0 := 2; 1929233#L1157-1 assume !(1 == ~T8_E~0); 1929230#L1162-1 assume 1 == ~E_1~0;~E_1~0 := 2; 1929226#L1167-1 assume 1 == ~E_2~0;~E_2~0 := 2; 1929222#L1172-1 assume 1 == ~E_3~0;~E_3~0 := 2; 1929218#L1177-1 assume !(1 == ~E_4~0); 1929214#L1182-1 assume 1 == ~E_5~0;~E_5~0 := 2; 1929210#L1187-1 assume !(1 == ~E_6~0); 1929206#L1192-1 assume 1 == ~E_7~0;~E_7~0 := 2; 1929203#L1197-1 assume !(1 == ~E_8~0); 1929199#L1281-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret19, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~9;havoc exists_runnable_thread_~__retres1~9; 1929187#L624-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9 := 1; 1929148#L671-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~9; 1929145#L672-2 stop_simulation_#t~ret19 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret19;havoc stop_simulation_#t~ret19; 1929142#L1236 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 1929138#L1243 stop_simulation_#res := stop_simulation_~__retres2~0; 1929133#L1244 start_simulation_#t~ret21 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret21;havoc start_simulation_#t~ret21; 1928951#L1294 assume !(0 != start_simulation_~tmp___0~1); 1928950#L1262-1 [2018-11-22 21:22:00,010 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-22 21:22:00,010 INFO L82 PathProgramCache]: Analyzing trace with hash -630627077, now seen corresponding path program 1 times [2018-11-22 21:22:00,010 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-22 21:22:00,010 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-22 21:22:00,011 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-22 21:22:00,011 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-22 21:22:00,011 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-22 21:22:00,013 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-22 21:22:00,055 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-22 21:22:00,055 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-22 21:22:00,055 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-22 21:22:00,055 INFO L799 eck$LassoCheckResult]: stem already infeasible [2018-11-22 21:22:00,055 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-22 21:22:00,056 INFO L82 PathProgramCache]: Analyzing trace with hash 1157806488, now seen corresponding path program 1 times [2018-11-22 21:22:00,056 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-22 21:22:00,056 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-22 21:22:00,056 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-22 21:22:00,056 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-22 21:22:00,056 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-22 21:22:00,060 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-22 21:22:00,149 INFO L134 CoverageAnalysis]: Checked inductivity of 198 backedges. 14 proven. 0 refuted. 0 times theorem prover too weak. 184 trivial. 0 not checked. [2018-11-22 21:22:00,149 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-22 21:22:00,149 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2018-11-22 21:22:00,149 INFO L811 eck$LassoCheckResult]: loop already infeasible [2018-11-22 21:22:00,149 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-22 21:22:00,149 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-22 21:22:00,150 INFO L87 Difference]: Start difference. First operand 138573 states and 180340 transitions. cyclomatic complexity: 41799 Second operand 3 states. [2018-11-22 21:22:00,395 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-22 21:22:00,395 INFO L93 Difference]: Finished difference Result 138465 states and 180196 transitions. [2018-11-22 21:22:00,395 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-22 21:22:00,395 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 138465 states and 180196 transitions. [2018-11-22 21:22:00,741 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 137328 [2018-11-22 21:22:00,983 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 138465 states to 138465 states and 180196 transitions. [2018-11-22 21:22:00,984 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 138465 [2018-11-22 21:22:01,049 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 138465 [2018-11-22 21:22:01,049 INFO L73 IsDeterministic]: Start isDeterministic. Operand 138465 states and 180196 transitions. [2018-11-22 21:22:01,100 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-22 21:22:01,100 INFO L705 BuchiCegarLoop]: Abstraction has 138465 states and 180196 transitions. [2018-11-22 21:22:01,157 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 138465 states and 180196 transitions. [2018-11-22 21:22:01,778 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 138465 to 138465. [2018-11-22 21:22:01,779 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 138465 states. [2018-11-22 21:22:01,919 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 138465 states to 138465 states and 180196 transitions. [2018-11-22 21:22:01,919 INFO L728 BuchiCegarLoop]: Abstraction has 138465 states and 180196 transitions. [2018-11-22 21:22:01,919 INFO L608 BuchiCegarLoop]: Abstraction has 138465 states and 180196 transitions. [2018-11-22 21:22:01,919 INFO L442 BuchiCegarLoop]: ======== Iteration 31============ [2018-11-22 21:22:01,919 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 138465 states and 180196 transitions. [2018-11-22 21:22:02,187 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 137328 [2018-11-22 21:22:02,187 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-22 21:22:02,187 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-22 21:22:02,191 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-22 21:22:02,191 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-22 21:22:02,191 INFO L794 eck$LassoCheckResult]: Stem: 2190379#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2; 2190270#L-1 havoc main_#res;havoc main_~__retres1~10;havoc main_~__retres1~10;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 2190271#L1225 havoc start_simulation_#t~ret20, start_simulation_#t~ret21, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 2190795#L564 assume 1 == ~m_i~0;~m_st~0 := 0; 2190305#L571-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 2190001#L576-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 2190002#L581-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 2190798#L586-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 2190518#L591-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 2190107#L596-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 2190108#L601-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 2190787#L606-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 2190663#L611-1 assume !(0 == ~M_E~0); 2190664#L828-1 assume !(0 == ~T1_E~0); 2190402#L833-1 assume !(0 == ~T2_E~0); 2190122#L838-1 assume !(0 == ~T3_E~0); 2190123#L843-1 assume !(0 == ~T4_E~0); 2190900#L848-1 assume !(0 == ~T5_E~0); 2190673#L853-1 assume !(0 == ~T6_E~0); 2190388#L858-1 assume !(0 == ~T7_E~0); 2189917#L863-1 assume !(0 == ~T8_E~0); 2189918#L868-1 assume !(0 == ~E_1~0); 2190623#L873-1 assume !(0 == ~E_2~0); 2190469#L878-1 assume !(0 == ~E_3~0); 2190238#L883-1 assume !(0 == ~E_4~0); 2190239#L888-1 assume !(0 == ~E_5~0); 2190753#L893-1 assume !(0 == ~E_6~0); 2190436#L898-1 assume !(0 == ~E_7~0); 2190371#L903-1 assume !(0 == ~E_8~0); 2190065#L908-1 havoc activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 2190066#L392 assume !(1 == ~m_pc~0); 2190420#L392-2 is_master_triggered_~__retres1~0 := 0; 2190423#L403 is_master_triggered_#res := is_master_triggered_~__retres1~0; 2190953#L404 activate_threads_#t~ret10 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 2190761#L1025 assume !(0 != activate_threads_~tmp~1); 2190762#L1025-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 2190609#L411 assume !(1 == ~t1_pc~0); 2190576#L411-2 is_transmit1_triggered_~__retres1~1 := 0; 2189985#L422 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 2189986#L423 activate_threads_#t~ret11 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 2190089#L1033 assume !(0 != activate_threads_~tmp___0~0); 2190313#L1033-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 2190314#L430 assume !(1 == ~t2_pc~0); 2190773#L430-2 is_transmit2_triggered_~__retres1~2 := 0; 2190158#L441 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 2190109#L442 activate_threads_#t~ret12 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 2190110#L1041 assume !(0 != activate_threads_~tmp___1~0); 2190985#L1041-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 2190986#L449 assume !(1 == ~t3_pc~0); 2190854#L449-2 is_transmit3_triggered_~__retres1~3 := 0; 2190995#L460 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 2191010#L461 activate_threads_#t~ret13 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 2190792#L1049 assume !(0 != activate_threads_~tmp___2~0); 2190793#L1049-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 2190022#L468 assume !(1 == ~t4_pc~0); 2190023#L468-2 is_transmit4_triggered_~__retres1~4 := 0; 2190028#L479 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 2190428#L480 activate_threads_#t~ret14 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 2190375#L1057 assume !(0 != activate_threads_~tmp___3~0); 2190376#L1057-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 2190222#L487 assume !(1 == ~t5_pc~0); 2189977#L487-2 is_transmit5_triggered_~__retres1~5 := 0; 2190224#L498 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 2190597#L499 activate_threads_#t~ret15 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 2190598#L1065 assume !(0 != activate_threads_~tmp___4~0); 2191004#L1065-2 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 2190387#L506 assume !(1 == ~t6_pc~0); 2190383#L506-2 is_transmit6_triggered_~__retres1~6 := 0; 2190384#L517 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 2190790#L518 activate_threads_#t~ret16 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 2190690#L1073 assume !(0 != activate_threads_~tmp___5~0); 2190691#L1073-2 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 2190521#L525 assume !(1 == ~t7_pc~0); 2190522#L525-2 is_transmit7_triggered_~__retres1~7 := 0; 2190524#L536 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 2190987#L537 activate_threads_#t~ret17 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 2190245#L1081 assume !(0 != activate_threads_~tmp___6~0); 2190246#L1081-2 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 2190247#L544 assume !(1 == ~t8_pc~0); 2190544#L544-2 is_transmit8_triggered_~__retres1~8 := 0; 2189911#L555 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 2189912#L556 activate_threads_#t~ret18 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 2190052#L1089 assume !(0 != activate_threads_~tmp___7~0); 2190835#L1089-2 assume !(1 == ~M_E~0); 2190397#L921-1 assume !(1 == ~T1_E~0); 2190118#L926-1 assume !(1 == ~T2_E~0); 2190119#L931-1 assume !(1 == ~T3_E~0); 2190898#L936-1 assume !(1 == ~T4_E~0); 2190681#L941-1 assume !(1 == ~T5_E~0); 2190394#L946-1 assume !(1 == ~T6_E~0); 2189927#L951-1 assume !(1 == ~T7_E~0); 2189928#L956-1 assume !(1 == ~T8_E~0); 2190794#L961-1 assume !(1 == ~E_1~0); 2190477#L966-1 assume !(1 == ~E_2~0); 2190251#L971-1 assume !(1 == ~E_3~0); 2190252#L976-1 assume !(1 == ~E_4~0); 2190745#L981-1 assume !(1 == ~E_5~0); 2190434#L986-1 assume !(1 == ~E_6~0); 2190364#L991-1 assume !(1 == ~E_7~0); 2190059#L996-1 assume !(1 == ~E_8~0); 2190060#L1262-1 [2018-11-22 21:22:02,192 INFO L796 eck$LassoCheckResult]: Loop: 2190060#L1262-1 assume !false; 2206104#L1263 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret0, eval_#t~nondet1, eval_~tmp_ndt_1~0, eval_#t~nondet2, eval_~tmp_ndt_2~0, eval_#t~nondet3, eval_~tmp_ndt_3~0, eval_#t~nondet4, eval_~tmp_ndt_4~0, eval_#t~nondet5, eval_~tmp_ndt_5~0, eval_#t~nondet6, eval_~tmp_ndt_6~0, eval_#t~nondet7, eval_~tmp_ndt_7~0, eval_#t~nondet8, eval_~tmp_ndt_8~0, eval_#t~nondet9, eval_~tmp_ndt_9~0, eval_~tmp~0;havoc eval_~tmp~0; 2206102#L803 assume !false; 2206100#L682 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~9;havoc exists_runnable_thread_~__retres1~9; 2206098#L624 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9 := 1; 2206096#L671 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~9; 2206094#L672 eval_#t~ret0 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret0;havoc eval_#t~ret0; 2206091#L686 assume 0 != eval_~tmp~0; 2206088#L686-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0;eval_~tmp_ndt_1~0 := eval_#t~nondet1;havoc eval_#t~nondet1; 2206085#L694 assume 0 != eval_~tmp_ndt_1~0;~m_st~0 := 1; 2206078#L73 assume 0 == ~m_pc~0; 2205939#L100 assume !false; 2206075#L85 ~E_1~0 := 1;havoc activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 2206073#L392-3 assume !(1 == ~m_pc~0); 2206071#L392-5 is_master_triggered_~__retres1~0 := 0; 2206069#L403-1 is_master_triggered_#res := is_master_triggered_~__retres1~0; 2206067#L404-1 activate_threads_#t~ret10 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 2206063#L1025-3 assume !(0 != activate_threads_~tmp~1); 2206061#L1025-5 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 2206059#L411-3 assume !(1 == ~t1_pc~0); 2206055#L411-5 is_transmit1_triggered_~__retres1~1 := 0; 2206052#L422-1 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 2206050#L423-1 activate_threads_#t~ret11 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 2206048#L1033-3 assume !(0 != activate_threads_~tmp___0~0); 2206044#L1033-5 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 2206042#L430-3 assume !(1 == ~t2_pc~0); 2206040#L430-5 is_transmit2_triggered_~__retres1~2 := 0; 2206038#L441-1 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 2206036#L442-1 activate_threads_#t~ret12 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 2206034#L1041-3 assume !(0 != activate_threads_~tmp___1~0); 2206031#L1041-5 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 2206026#L449-3 assume !(1 == ~t3_pc~0); 2206023#L449-5 is_transmit3_triggered_~__retres1~3 := 0; 2206021#L460-1 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 2206019#L461-1 activate_threads_#t~ret13 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 2206017#L1049-3 assume !(0 != activate_threads_~tmp___2~0); 2206014#L1049-5 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 2206012#L468-3 assume !(1 == ~t4_pc~0); 2206010#L468-5 is_transmit4_triggered_~__retres1~4 := 0; 2206008#L479-1 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 2206006#L480-1 activate_threads_#t~ret14 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 2206004#L1057-3 assume !(0 != activate_threads_~tmp___3~0); 2206002#L1057-5 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 2206000#L487-3 assume !(1 == ~t5_pc~0); 2205996#L487-5 is_transmit5_triggered_~__retres1~5 := 0; 2205994#L498-1 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 2205991#L499-1 activate_threads_#t~ret15 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 2205989#L1065-3 assume !(0 != activate_threads_~tmp___4~0); 2205986#L1065-5 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 2205984#L506-3 assume !(1 == ~t6_pc~0); 2205982#L506-5 is_transmit6_triggered_~__retres1~6 := 0; 2205981#L517-1 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 2205977#L518-1 activate_threads_#t~ret16 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 2205975#L1073-3 assume !(0 != activate_threads_~tmp___5~0); 2205970#L1073-5 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 2205966#L525-3 assume !(1 == ~t7_pc~0); 2205962#L525-5 is_transmit7_triggered_~__retres1~7 := 0; 2205961#L536-1 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 2205960#L537-1 activate_threads_#t~ret17 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 2205958#L1081-3 assume !(0 != activate_threads_~tmp___6~0); 2205956#L1081-5 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 2205950#L544-3 assume !(1 == ~t8_pc~0); 2205947#L544-5 is_transmit8_triggered_~__retres1~8 := 0; 2205945#L555-1 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 2205943#L556-1 activate_threads_#t~ret18 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 2205942#L1089-3 assume !(0 != activate_threads_~tmp___7~0); 2205937#L1089-5 ~E_1~0 := 2; 2205936#L77 assume !false; 2205935#L93 ~m_pc~0 := 1;~m_st~0 := 2; 2204479#L691 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0;eval_~tmp_ndt_2~0 := eval_#t~nondet2;havoc eval_#t~nondet2; 2205799#L708 assume 0 != eval_~tmp_ndt_2~0;~t1_st~0 := 1; 2205803#L114 assume 0 == ~t1_pc~0; 2205801#L125-1 assume !false; 2205800#L126 ~t1_pc~0 := 1;~t1_st~0 := 2; 2205795#L705 assume !(0 == ~t2_st~0); 2205790#L719 assume !(0 == ~t3_st~0); 2205784#L733 assume !(0 == ~t4_st~0); 2205779#L747 assume !(0 == ~t5_st~0); 2205776#L761 assume !(0 == ~t6_st~0); 2205773#L775 assume !(0 == ~t7_st~0); 2205768#L789 assume !(0 == ~t8_st~0); 2205762#L803 assume !false; 2203819#L682 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~9;havoc exists_runnable_thread_~__retres1~9; 2203818#L624 assume !(0 == ~m_st~0); 2203816#L628 assume !(0 == ~t1_st~0); 2203815#L632 assume !(0 == ~t2_st~0); 2203814#L636 assume !(0 == ~t3_st~0); 2203813#L640 assume !(0 == ~t4_st~0); 2203812#L644 assume !(0 == ~t5_st~0); 2203811#L648 assume !(0 == ~t6_st~0); 2203810#L652 assume !(0 == ~t7_st~0); 2203808#L656 assume !(0 == ~t8_st~0);exists_runnable_thread_~__retres1~9 := 0; 2203807#L671 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~9; 2203806#L672 eval_#t~ret0 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret0;havoc eval_#t~ret0; 2203804#L686 assume !(0 != eval_~tmp~0); 2203803#L818 start_simulation_~kernel_st~0 := 2; 2203802#L564-1 start_simulation_~kernel_st~0 := 3; 2203801#L828-2 assume !(0 == ~M_E~0); 2203800#L828-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 2203799#L833-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 2203798#L838-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 2203797#L843-3 assume !(0 == ~T4_E~0); 2203796#L848-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 2203795#L853-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 2203794#L858-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 2203793#L863-3 assume !(0 == ~T8_E~0); 2203792#L868-3 assume 0 == ~E_1~0;~E_1~0 := 1; 2203791#L873-3 assume 0 == ~E_2~0;~E_2~0 := 1; 2203790#L878-3 assume 0 == ~E_3~0;~E_3~0 := 1; 2203789#L883-3 assume !(0 == ~E_4~0); 2203788#L888-3 assume 0 == ~E_5~0;~E_5~0 := 1; 2203787#L893-3 assume 0 == ~E_6~0;~E_6~0 := 1; 2203786#L898-3 assume 0 == ~E_7~0;~E_7~0 := 1; 2203785#L903-3 assume !(0 == ~E_8~0); 2203784#L908-3 havoc activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 2203782#L392-27 assume 1 == ~m_pc~0; 2203781#L393-9 assume !(1 == ~M_E~0); 2203780#L392-29 is_master_triggered_~__retres1~0 := 0; 2203779#L403-9 is_master_triggered_#res := is_master_triggered_~__retres1~0; 2203778#L404-9 activate_threads_#t~ret10 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 2203777#L1025-27 assume !(0 != activate_threads_~tmp~1); 2203776#L1025-29 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 2203775#L411-27 assume 1 == ~t1_pc~0; 2203772#L412-9 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 2203773#L422-9 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 2203764#L423-9 activate_threads_#t~ret11 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 2203765#L1033-27 assume !(0 != activate_threads_~tmp___0~0); 2203762#L1033-29 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 2203761#L430-27 assume !(1 == ~t2_pc~0); 2203760#L430-29 is_transmit2_triggered_~__retres1~2 := 0; 2203759#L441-9 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 2203758#L442-9 activate_threads_#t~ret12 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 2203757#L1041-27 assume !(0 != activate_threads_~tmp___1~0); 2203756#L1041-29 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 2203755#L449-27 assume 1 == ~t3_pc~0; 2203753#L450-9 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 2203751#L460-9 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 2203749#L461-9 activate_threads_#t~ret13 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 2203747#L1049-27 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 2203746#L1049-29 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 2203745#L468-27 assume !(1 == ~t4_pc~0); 2203744#L468-29 is_transmit4_triggered_~__retres1~4 := 0; 2203743#L479-9 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 2203742#L480-9 activate_threads_#t~ret14 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 2203741#L1057-27 assume !(0 != activate_threads_~tmp___3~0); 2203740#L1057-29 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 2203739#L487-27 assume 1 == ~t5_pc~0; 2203737#L488-9 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 2203735#L498-9 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 2203733#L499-9 activate_threads_#t~ret15 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 2203731#L1065-27 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 2203730#L1065-29 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 2203729#L506-27 assume !(1 == ~t6_pc~0); 2203728#L506-29 is_transmit6_triggered_~__retres1~6 := 0; 2203727#L517-9 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 2203726#L518-9 activate_threads_#t~ret16 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 2203725#L1073-27 assume 0 != activate_threads_~tmp___5~0;~t6_st~0 := 0; 2203724#L1073-29 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 2203723#L525-27 assume !(1 == ~t7_pc~0); 2203722#L525-29 is_transmit7_triggered_~__retres1~7 := 0; 2203721#L536-9 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 2203720#L537-9 activate_threads_#t~ret17 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 2203719#L1081-27 assume !(0 != activate_threads_~tmp___6~0); 2203718#L1081-29 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 2203717#L544-27 assume !(1 == ~t8_pc~0); 2203715#L544-29 is_transmit8_triggered_~__retres1~8 := 0; 2203714#L555-9 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 2203713#L556-9 activate_threads_#t~ret18 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 2203712#L1089-27 assume !(0 != activate_threads_~tmp___7~0); 2203711#L1089-29 assume !(1 == ~M_E~0); 2201515#L921-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 2203710#L926-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 2203709#L931-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 2203708#L936-3 assume !(1 == ~T4_E~0); 2203707#L941-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 2203706#L946-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 2203705#L951-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 2203704#L956-3 assume !(1 == ~T8_E~0); 2203703#L961-3 assume 1 == ~E_1~0;~E_1~0 := 2; 2203702#L966-3 assume 1 == ~E_2~0;~E_2~0 := 2; 2203701#L971-3 assume 1 == ~E_3~0;~E_3~0 := 2; 2203700#L976-3 assume !(1 == ~E_4~0); 2203699#L981-3 assume 1 == ~E_5~0;~E_5~0 := 2; 2203698#L986-3 assume 1 == ~E_6~0;~E_6~0 := 2; 2203697#L991-3 assume 1 == ~E_7~0;~E_7~0 := 2; 2203696#L996-3 assume !(1 == ~E_8~0); 2203694#L1001-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~9;havoc exists_runnable_thread_~__retres1~9; 2203692#L624-1 assume !(0 == ~m_st~0); 2199018#L628-1 assume !(0 == ~t1_st~0); 2203685#L632-1 assume 0 == ~t2_st~0;exists_runnable_thread_~__retres1~9 := 1; 2203684#L671-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~9; 2203683#L672-1 start_simulation_#t~ret20 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret20;havoc start_simulation_#t~ret20; 2199083#L1281 assume 0 == start_simulation_~tmp~3;start_simulation_~kernel_st~0 := 4;~M_E~0 := 1; 2199081#L1115 havoc activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 2199078#L392-30 assume 1 == ~m_pc~0; 2199075#L393-10 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0 := 1; 2199073#L403-10 is_master_triggered_#res := is_master_triggered_~__retres1~0; 2199071#L404-10 activate_threads_#t~ret10 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 2198994#L1025-30 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 2198992#L1025-32 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 2198990#L411-30 assume 1 == ~t1_pc~0; 2198987#L412-10 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 2198984#L422-10 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 2198982#L423-10 activate_threads_#t~ret11 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 2198887#L1033-30 assume !(0 != activate_threads_~tmp___0~0); 2197516#L1033-32 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 2197515#L430-30 assume !(1 == ~t2_pc~0); 2197513#L430-32 is_transmit2_triggered_~__retres1~2 := 0; 2197512#L441-10 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 2197511#L442-10 activate_threads_#t~ret12 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 2197510#L1041-30 assume !(0 != activate_threads_~tmp___1~0); 2197509#L1041-32 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 2197508#L449-30 assume 1 == ~t3_pc~0; 2197507#L450-10 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 2197505#L460-10 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 2197503#L461-10 activate_threads_#t~ret13 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 2197500#L1049-30 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 2197499#L1049-32 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 2197497#L468-30 assume !(1 == ~t4_pc~0); 2197496#L468-32 is_transmit4_triggered_~__retres1~4 := 0; 2197495#L479-10 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 2197494#L480-10 activate_threads_#t~ret14 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 2197492#L1057-30 assume !(0 != activate_threads_~tmp___3~0); 2197491#L1057-32 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 2197489#L487-30 assume !(1 == ~t5_pc~0); 2197485#L487-32 is_transmit5_triggered_~__retres1~5 := 0; 2197483#L498-10 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 2197481#L499-10 activate_threads_#t~ret15 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 2197477#L1065-30 assume !(0 != activate_threads_~tmp___4~0); 2197475#L1065-32 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 2197473#L506-30 assume !(1 == ~t6_pc~0); 2197471#L506-32 is_transmit6_triggered_~__retres1~6 := 0; 2197469#L517-10 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 2197466#L518-10 activate_threads_#t~ret16 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 2197464#L1073-30 assume 0 != activate_threads_~tmp___5~0;~t6_st~0 := 0; 2197462#L1073-32 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 2197460#L525-30 assume !(1 == ~t7_pc~0); 2197458#L525-32 is_transmit7_triggered_~__retres1~7 := 0; 2197456#L536-10 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 2197455#L537-10 activate_threads_#t~ret17 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 2197452#L1081-30 assume !(0 != activate_threads_~tmp___6~0); 2197448#L1081-32 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 2197447#L544-30 assume !(1 == ~t8_pc~0); 2197442#L544-32 is_transmit8_triggered_~__retres1~8 := 0; 2197440#L555-10 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 2197438#L556-10 activate_threads_#t~ret18 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 2197436#L1089-30 assume !(0 != activate_threads_~tmp___7~0); 2197432#L1089-32 assume !(1 == ~M_E~0); 2197430#L1122-1 assume 1 == ~T1_E~0;~T1_E~0 := 2; 2197428#L1127-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 2197426#L1132-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 2197424#L1137-1 assume !(1 == ~T4_E~0); 2197422#L1142-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 2197420#L1147-1 assume !(1 == ~T6_E~0); 2197418#L1152-1 assume 1 == ~T7_E~0;~T7_E~0 := 2; 2197416#L1157-1 assume !(1 == ~T8_E~0); 2197414#L1162-1 assume 1 == ~E_1~0;~E_1~0 := 2; 2197412#L1167-1 assume 1 == ~E_2~0;~E_2~0 := 2; 2197410#L1172-1 assume 1 == ~E_3~0;~E_3~0 := 2; 2197408#L1177-1 assume !(1 == ~E_4~0); 2197406#L1182-1 assume 1 == ~E_5~0;~E_5~0 := 2; 2197403#L1187-1 assume !(1 == ~E_6~0); 2197401#L1192-1 assume 1 == ~E_7~0;~E_7~0 := 2; 2197399#L1197-1 assume !(1 == ~E_8~0); 2197395#L1281-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret19, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~9;havoc exists_runnable_thread_~__retres1~9; 2197392#L624-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9 := 1; 2197391#L671-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~9; 2197390#L672-2 stop_simulation_#t~ret19 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret19;havoc stop_simulation_#t~ret19; 2197389#L1236 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 2197387#L1243 stop_simulation_#res := stop_simulation_~__retres2~0; 2197385#L1244 start_simulation_#t~ret21 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret21;havoc start_simulation_#t~ret21; 2197381#L1294 assume !(0 != start_simulation_~tmp___0~1); 2197380#L1262-1 assume !false; 2197128#L1263 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret0, eval_#t~nondet1, eval_~tmp_ndt_1~0, eval_#t~nondet2, eval_~tmp_ndt_2~0, eval_#t~nondet3, eval_~tmp_ndt_3~0, eval_#t~nondet4, eval_~tmp_ndt_4~0, eval_#t~nondet5, eval_~tmp_ndt_5~0, eval_#t~nondet6, eval_~tmp_ndt_6~0, eval_#t~nondet7, eval_~tmp_ndt_7~0, eval_#t~nondet8, eval_~tmp_ndt_8~0, eval_#t~nondet9, eval_~tmp_ndt_9~0, eval_~tmp~0;havoc eval_~tmp~0; 2197125#L803 assume !false; 2197124#L682 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~9;havoc exists_runnable_thread_~__retres1~9; 2197121#L624 assume !(0 == ~m_st~0); 2197122#L628 assume !(0 == ~t1_st~0); 2201328#L632 assume !(0 == ~t2_st~0); 2201325#L636 assume !(0 == ~t3_st~0); 2201323#L640 assume !(0 == ~t4_st~0); 2201321#L644 assume !(0 == ~t5_st~0); 2201318#L648 assume !(0 == ~t6_st~0); 2201316#L652 assume !(0 == ~t7_st~0); 2201313#L656 assume !(0 == ~t8_st~0);exists_runnable_thread_~__retres1~9 := 0; 2201311#L671 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~9; 2201309#L672 eval_#t~ret0 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret0;havoc eval_#t~ret0; 2201307#L686 assume !(0 != eval_~tmp~0); 2201305#L818 start_simulation_~kernel_st~0 := 2; 2201303#L564-1 start_simulation_~kernel_st~0 := 3; 2201302#L828-2 assume 0 == ~M_E~0;~M_E~0 := 1; 2201301#L828-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 2201299#L833-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 2201298#L838-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 2201297#L843-3 assume !(0 == ~T4_E~0); 2201296#L848-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 2201294#L853-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 2201293#L858-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 2201292#L863-3 assume !(0 == ~T8_E~0); 2201290#L868-3 assume 0 == ~E_1~0;~E_1~0 := 1; 2201289#L873-3 assume 0 == ~E_2~0;~E_2~0 := 1; 2201288#L878-3 assume 0 == ~E_3~0;~E_3~0 := 1; 2201287#L883-3 assume !(0 == ~E_4~0); 2201285#L888-3 assume 0 == ~E_5~0;~E_5~0 := 1; 2201283#L893-3 assume 0 == ~E_6~0;~E_6~0 := 1; 2201281#L898-3 assume 0 == ~E_7~0;~E_7~0 := 1; 2201280#L903-3 assume !(0 == ~E_8~0); 2201276#L908-3 havoc activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 2201273#L392-27 assume 1 == ~m_pc~0; 2201270#L393-9 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0 := 1; 2201268#L403-9 is_master_triggered_#res := is_master_triggered_~__retres1~0; 2201265#L404-9 activate_threads_#t~ret10 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 2201262#L1025-27 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 2201261#L1025-29 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 2201257#L411-27 assume !(1 == ~t1_pc~0); 2201255#L411-29 is_transmit1_triggered_~__retres1~1 := 0; 2203651#L422-9 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 2203649#L423-9 activate_threads_#t~ret11 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 2197660#L1033-27 assume !(0 != activate_threads_~tmp___0~0); 2197658#L1033-29 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 2197654#L430-27 assume !(1 == ~t2_pc~0); 2197652#L430-29 is_transmit2_triggered_~__retres1~2 := 0; 2197650#L441-9 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 2197648#L442-9 activate_threads_#t~ret12 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 2197645#L1041-27 assume !(0 != activate_threads_~tmp___1~0); 2197643#L1041-29 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 2197641#L449-27 assume !(1 == ~t3_pc~0); 2197637#L449-29 is_transmit3_triggered_~__retres1~3 := 0; 2197635#L460-9 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 2197633#L461-9 activate_threads_#t~ret13 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 2197631#L1049-27 assume !(0 != activate_threads_~tmp___2~0); 2197628#L1049-29 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 2197624#L468-27 assume !(1 == ~t4_pc~0); 2197622#L468-29 is_transmit4_triggered_~__retres1~4 := 0; 2197620#L479-9 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 2197618#L480-9 activate_threads_#t~ret14 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 2197615#L1057-27 assume !(0 != activate_threads_~tmp___3~0); 2197613#L1057-29 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 2197611#L487-27 assume !(1 == ~t5_pc~0); 2197607#L487-29 is_transmit5_triggered_~__retres1~5 := 0; 2197605#L498-9 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 2197603#L499-9 activate_threads_#t~ret15 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 2197601#L1065-27 assume !(0 != activate_threads_~tmp___4~0); 2197598#L1065-29 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 2197596#L506-27 assume !(1 == ~t6_pc~0); 2197594#L506-29 is_transmit6_triggered_~__retres1~6 := 0; 2197592#L517-9 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 2197590#L518-9 activate_threads_#t~ret16 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 2197588#L1073-27 assume 0 != activate_threads_~tmp___5~0;~t6_st~0 := 0; 2197586#L1073-29 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 2197583#L525-27 assume !(1 == ~t7_pc~0); 2197581#L525-29 is_transmit7_triggered_~__retres1~7 := 0; 2197579#L536-9 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 2197577#L537-9 activate_threads_#t~ret17 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 2197575#L1081-27 assume !(0 != activate_threads_~tmp___6~0); 2197573#L1081-29 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 2197572#L544-27 assume !(1 == ~t8_pc~0); 2197569#L544-29 is_transmit8_triggered_~__retres1~8 := 0; 2197567#L555-9 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 2197565#L556-9 activate_threads_#t~ret18 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 2197563#L1089-27 assume !(0 != activate_threads_~tmp___7~0); 2197560#L1089-29 assume !(1 == ~M_E~0); 2197558#L921-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 2197556#L926-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 2197554#L931-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 2197552#L936-3 assume !(1 == ~T4_E~0); 2197550#L941-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 2197548#L946-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 2197546#L951-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 2197544#L956-3 assume !(1 == ~T8_E~0); 2197542#L961-3 assume 1 == ~E_1~0;~E_1~0 := 2; 2197540#L966-3 assume 1 == ~E_2~0;~E_2~0 := 2; 2197538#L971-3 assume 1 == ~E_3~0;~E_3~0 := 2; 2197536#L976-3 assume !(1 == ~E_4~0); 2197534#L981-3 assume 1 == ~E_5~0;~E_5~0 := 2; 2197533#L986-3 assume 1 == ~E_6~0;~E_6~0 := 2; 2197532#L991-3 assume 1 == ~E_7~0;~E_7~0 := 2; 2197531#L996-3 assume !(1 == ~E_8~0); 2197530#L1001-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~9;havoc exists_runnable_thread_~__retres1~9; 2197528#L624-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9 := 1; 2197527#L671-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~9; 2197519#L672-1 start_simulation_#t~ret20 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret20;havoc start_simulation_#t~ret20; 2197397#L1281 assume 0 == start_simulation_~tmp~3;start_simulation_~kernel_st~0 := 4;~M_E~0 := 1; 2197398#L1115 havoc activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 2199006#L392-30 assume !(1 == ~m_pc~0); 2199007#L392-32 is_master_triggered_~__retres1~0 := 0; 2199321#L403-10 is_master_triggered_#res := is_master_triggered_~__retres1~0; 2199319#L404-10 activate_threads_#t~ret10 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 2199318#L1025-30 assume !(0 != activate_threads_~tmp~1); 2199316#L1025-32 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 2199314#L411-30 assume 1 == ~t1_pc~0; 2199311#L412-10 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 2199309#L422-10 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 2199307#L423-10 activate_threads_#t~ret11 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 2199274#L1033-30 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 2199271#L1033-32 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 2199268#L430-30 assume !(1 == ~t2_pc~0); 2199266#L430-32 is_transmit2_triggered_~__retres1~2 := 0; 2199264#L441-10 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 2199262#L442-10 activate_threads_#t~ret12 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 2199260#L1041-30 assume !(0 != activate_threads_~tmp___1~0); 2199258#L1041-32 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 2199256#L449-30 assume !(1 == ~t3_pc~0); 2199252#L449-32 is_transmit3_triggered_~__retres1~3 := 0; 2199250#L460-10 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 2199248#L461-10 activate_threads_#t~ret13 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 2199246#L1049-30 assume !(0 != activate_threads_~tmp___2~0); 2199243#L1049-32 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 2199241#L468-30 assume !(1 == ~t4_pc~0); 2199239#L468-32 is_transmit4_triggered_~__retres1~4 := 0; 2199236#L479-10 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 2199234#L480-10 activate_threads_#t~ret14 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 2199232#L1057-30 assume !(0 != activate_threads_~tmp___3~0); 2199230#L1057-32 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 2199228#L487-30 assume 1 == ~t5_pc~0; 2199225#L488-10 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 2199224#L498-10 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 2199222#L499-10 activate_threads_#t~ret15 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 2199219#L1065-30 assume !(0 != activate_threads_~tmp___4~0); 2199216#L1065-32 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 2199214#L506-30 assume !(1 == ~t6_pc~0); 2199212#L506-32 is_transmit6_triggered_~__retres1~6 := 0; 2199209#L517-10 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 2199207#L518-10 activate_threads_#t~ret16 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 2199204#L1073-30 assume 0 != activate_threads_~tmp___5~0;~t6_st~0 := 0; 2199201#L1073-32 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 2199199#L525-30 assume !(1 == ~t7_pc~0); 2199197#L525-32 is_transmit7_triggered_~__retres1~7 := 0; 2199192#L536-10 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 2199190#L537-10 activate_threads_#t~ret17 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 2199188#L1081-30 assume !(0 != activate_threads_~tmp___6~0); 2199185#L1081-32 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 2199183#L544-30 assume !(1 == ~t8_pc~0); 2199180#L544-32 is_transmit8_triggered_~__retres1~8 := 0; 2199179#L555-10 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 2199178#L556-10 activate_threads_#t~ret18 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 2199176#L1089-30 assume !(0 != activate_threads_~tmp___7~0); 2199174#L1089-32 assume 1 == ~M_E~0;~M_E~0 := 2; 2199175#L1122-1 assume 1 == ~T1_E~0;~T1_E~0 := 2; 2206251#L1127-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 2206249#L1132-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 2206247#L1137-1 assume !(1 == ~T4_E~0); 2206245#L1142-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 2206243#L1147-1 assume !(1 == ~T6_E~0); 2206240#L1152-1 assume 1 == ~T7_E~0;~T7_E~0 := 2; 2206238#L1157-1 assume !(1 == ~T8_E~0); 2206236#L1162-1 assume 1 == ~E_1~0;~E_1~0 := 2; 2206231#L1167-1 assume 1 == ~E_2~0;~E_2~0 := 2; 2206229#L1172-1 assume 1 == ~E_3~0;~E_3~0 := 2; 2206227#L1177-1 assume !(1 == ~E_4~0); 2206225#L1182-1 assume 1 == ~E_5~0;~E_5~0 := 2; 2206223#L1187-1 assume !(1 == ~E_6~0); 2206221#L1192-1 assume 1 == ~E_7~0;~E_7~0 := 2; 2206219#L1197-1 assume !(1 == ~E_8~0); 2206217#L1281-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret19, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~9;havoc exists_runnable_thread_~__retres1~9; 2206212#L624-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9 := 1; 2206210#L671-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~9; 2206208#L672-2 stop_simulation_#t~ret19 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret19;havoc stop_simulation_#t~ret19; 2206206#L1236 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 2206203#L1243 stop_simulation_#res := stop_simulation_~__retres2~0; 2206201#L1244 start_simulation_#t~ret21 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret21;havoc start_simulation_#t~ret21; 2206199#L1294 assume !(0 != start_simulation_~tmp___0~1); 2190060#L1262-1 [2018-11-22 21:22:02,192 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-22 21:22:02,192 INFO L82 PathProgramCache]: Analyzing trace with hash 426104125, now seen corresponding path program 11 times [2018-11-22 21:22:02,192 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-22 21:22:02,192 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-22 21:22:02,193 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-22 21:22:02,193 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-22 21:22:02,193 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-22 21:22:02,196 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-22 21:22:02,200 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-22 21:22:02,228 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-22 21:22:02,228 INFO L82 PathProgramCache]: Analyzing trace with hash 328635038, now seen corresponding path program 1 times [2018-11-22 21:22:02,228 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-22 21:22:02,228 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-22 21:22:02,229 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-22 21:22:02,229 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-22 21:22:02,229 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-22 21:22:02,237 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-22 21:22:02,342 INFO L134 CoverageAnalysis]: Checked inductivity of 196 backedges. 40 proven. 0 refuted. 0 times theorem prover too weak. 156 trivial. 0 not checked. [2018-11-22 21:22:02,342 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-22 21:22:02,342 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-22 21:22:02,342 INFO L811 eck$LassoCheckResult]: loop already infeasible [2018-11-22 21:22:02,342 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-22 21:22:02,342 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-22 21:22:02,342 INFO L87 Difference]: Start difference. First operand 138465 states and 180196 transitions. cyclomatic complexity: 41763 Second operand 3 states. [2018-11-22 21:22:03,011 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-22 21:22:03,012 INFO L93 Difference]: Finished difference Result 125856 states and 161487 transitions. [2018-11-22 21:22:03,012 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-22 21:22:03,012 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 125856 states and 161487 transitions. [2018-11-22 21:22:03,328 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 124720 [2018-11-22 21:22:03,536 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 125856 states to 125856 states and 161487 transitions. [2018-11-22 21:22:03,536 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 125856 [2018-11-22 21:22:03,590 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 125856 [2018-11-22 21:22:03,591 INFO L73 IsDeterministic]: Start isDeterministic. Operand 125856 states and 161487 transitions. [2018-11-22 21:22:03,636 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-22 21:22:03,637 INFO L705 BuchiCegarLoop]: Abstraction has 125856 states and 161487 transitions. [2018-11-22 21:22:03,691 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 125856 states and 161487 transitions. [2018-11-22 21:22:04,310 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 125856 to 125856. [2018-11-22 21:22:04,310 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 125856 states. [2018-11-22 21:22:04,439 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 125856 states to 125856 states and 161487 transitions. [2018-11-22 21:22:04,439 INFO L728 BuchiCegarLoop]: Abstraction has 125856 states and 161487 transitions. [2018-11-22 21:22:04,440 INFO L608 BuchiCegarLoop]: Abstraction has 125856 states and 161487 transitions. [2018-11-22 21:22:04,440 INFO L442 BuchiCegarLoop]: ======== Iteration 32============ [2018-11-22 21:22:04,440 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 125856 states and 161487 transitions. [2018-11-22 21:22:04,683 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 124720 [2018-11-22 21:22:04,684 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-22 21:22:04,684 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-22 21:22:04,685 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-22 21:22:04,685 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-22 21:22:04,685 INFO L794 eck$LassoCheckResult]: Stem: 2454695#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2; 2454592#L-1 havoc main_#res;havoc main_~__retres1~10;havoc main_~__retres1~10;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 2454593#L1225 havoc start_simulation_#t~ret20, start_simulation_#t~ret21, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 2455097#L564 assume 1 == ~m_i~0;~m_st~0 := 0; 2454627#L571-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 2454328#L576-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 2454329#L581-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 2455101#L586-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 2454843#L591-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 2454431#L596-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 2454432#L601-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 2455088#L606-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 2454988#L611-1 assume !(0 == ~M_E~0); 2454989#L828-1 assume !(0 == ~T1_E~0); 2454717#L833-1 assume !(0 == ~T2_E~0); 2454446#L838-1 assume !(0 == ~T3_E~0); 2454447#L843-1 assume !(0 == ~T4_E~0); 2455204#L848-1 assume !(0 == ~T5_E~0); 2454998#L853-1 assume !(0 == ~T6_E~0); 2454703#L858-1 assume !(0 == ~T7_E~0); 2454244#L863-1 assume !(0 == ~T8_E~0); 2454245#L868-1 assume !(0 == ~E_1~0); 2454947#L873-1 assume !(0 == ~E_2~0); 2454790#L878-1 assume !(0 == ~E_3~0); 2454561#L883-1 assume !(0 == ~E_4~0); 2454562#L888-1 assume !(0 == ~E_5~0); 2455057#L893-1 assume !(0 == ~E_6~0); 2454752#L898-1 assume !(0 == ~E_7~0); 2454686#L903-1 assume !(0 == ~E_8~0); 2454392#L908-1 havoc activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 2454393#L392 assume !(1 == ~m_pc~0); 2454736#L392-2 is_master_triggered_~__retres1~0 := 0; 2454739#L403 is_master_triggered_#res := is_master_triggered_~__retres1~0; 2455255#L404 activate_threads_#t~ret10 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 2455064#L1025 assume !(0 != activate_threads_~tmp~1); 2455065#L1025-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 2454933#L411 assume !(1 == ~t1_pc~0); 2454900#L411-2 is_transmit1_triggered_~__retres1~1 := 0; 2454312#L422 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 2454313#L423 activate_threads_#t~ret11 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 2454413#L1033 assume !(0 != activate_threads_~tmp___0~0); 2454633#L1033-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 2454634#L430 assume !(1 == ~t2_pc~0); 2455074#L430-2 is_transmit2_triggered_~__retres1~2 := 0; 2454482#L441 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 2454433#L442 activate_threads_#t~ret12 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 2454434#L1041 assume !(0 != activate_threads_~tmp___1~0); 2455282#L1041-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 2455283#L449 assume !(1 == ~t3_pc~0); 2455155#L449-2 is_transmit3_triggered_~__retres1~3 := 0; 2455292#L460 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 2455305#L461 activate_threads_#t~ret13 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 2455093#L1049 assume !(0 != activate_threads_~tmp___2~0); 2455094#L1049-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 2454351#L468 assume !(1 == ~t4_pc~0); 2454352#L468-2 is_transmit4_triggered_~__retres1~4 := 0; 2454357#L479 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 2454744#L480 activate_threads_#t~ret14 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 2454690#L1057 assume !(0 != activate_threads_~tmp___3~0); 2454691#L1057-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 2454546#L487 assume !(1 == ~t5_pc~0); 2454304#L487-2 is_transmit5_triggered_~__retres1~5 := 0; 2454548#L498 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 2454920#L499 activate_threads_#t~ret15 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 2454921#L1065 assume !(0 != activate_threads_~tmp___4~0); 2455297#L1065-2 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 2454702#L506 assume !(1 == ~t6_pc~0); 2454698#L506-2 is_transmit6_triggered_~__retres1~6 := 0; 2454699#L517 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 2455091#L518 activate_threads_#t~ret16 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 2455011#L1073 assume !(0 != activate_threads_~tmp___5~0); 2455012#L1073-2 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 2454845#L525 assume !(1 == ~t7_pc~0); 2454846#L525-2 is_transmit7_triggered_~__retres1~7 := 0; 2454848#L536 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 2455284#L537 activate_threads_#t~ret17 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 2454567#L1081 assume !(0 != activate_threads_~tmp___6~0); 2454568#L1081-2 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 2454569#L544 assume !(1 == ~t8_pc~0); 2454869#L544-2 is_transmit8_triggered_~__retres1~8 := 0; 2454238#L555 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 2454239#L556 activate_threads_#t~ret18 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 2454380#L1089 assume !(0 != activate_threads_~tmp___7~0); 2455136#L1089-2 assume !(1 == ~M_E~0); 2454712#L921-1 assume !(1 == ~T1_E~0); 2454442#L926-1 assume !(1 == ~T2_E~0); 2454443#L931-1 assume !(1 == ~T3_E~0); 2455202#L936-1 assume !(1 == ~T4_E~0); 2455005#L941-1 assume !(1 == ~T5_E~0); 2454709#L946-1 assume !(1 == ~T6_E~0); 2454254#L951-1 assume !(1 == ~T7_E~0); 2454255#L956-1 assume !(1 == ~T8_E~0); 2455096#L961-1 assume !(1 == ~E_1~0); 2454797#L966-1 assume !(1 == ~E_2~0); 2454573#L971-1 assume !(1 == ~E_3~0); 2454574#L976-1 assume !(1 == ~E_4~0); 2455051#L981-1 assume !(1 == ~E_5~0); 2454750#L986-1 assume !(1 == ~E_6~0); 2454680#L991-1 assume !(1 == ~E_7~0); 2454386#L996-1 assume !(1 == ~E_8~0); 2454387#L1262-1 assume !false; 2468141#L1263 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret0, eval_#t~nondet1, eval_~tmp_ndt_1~0, eval_#t~nondet2, eval_~tmp_ndt_2~0, eval_#t~nondet3, eval_~tmp_ndt_3~0, eval_#t~nondet4, eval_~tmp_ndt_4~0, eval_#t~nondet5, eval_~tmp_ndt_5~0, eval_#t~nondet6, eval_~tmp_ndt_6~0, eval_#t~nondet7, eval_~tmp_ndt_7~0, eval_#t~nondet8, eval_~tmp_ndt_8~0, eval_#t~nondet9, eval_~tmp_ndt_9~0, eval_~tmp~0;havoc eval_~tmp~0; 2468139#L803 [2018-11-22 21:22:04,685 INFO L796 eck$LassoCheckResult]: Loop: 2468139#L803 assume !false; 2468136#L682 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~9;havoc exists_runnable_thread_~__retres1~9; 2468133#L624 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9 := 1; 2468131#L671 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~9; 2468129#L672 eval_#t~ret0 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret0;havoc eval_#t~ret0; 2468127#L686 assume 0 != eval_~tmp~0; 2468125#L686-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0;eval_~tmp_ndt_1~0 := eval_#t~nondet1;havoc eval_#t~nondet1; 2468123#L694 assume !(0 != eval_~tmp_ndt_1~0); 2468121#L691 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0;eval_~tmp_ndt_2~0 := eval_#t~nondet2;havoc eval_#t~nondet2; 2468007#L708 assume !(0 != eval_~tmp_ndt_2~0); 2468120#L705 assume !(0 == ~t2_st~0); 2468284#L719 assume !(0 == ~t3_st~0); 2468281#L733 assume !(0 == ~t4_st~0); 2468163#L747 assume !(0 == ~t5_st~0); 2468159#L761 assume !(0 == ~t6_st~0); 2468155#L775 assume !(0 == ~t7_st~0); 2468144#L789 assume !(0 == ~t8_st~0); 2468139#L803 [2018-11-22 21:22:04,685 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-22 21:22:04,686 INFO L82 PathProgramCache]: Analyzing trace with hash 1464186463, now seen corresponding path program 1 times [2018-11-22 21:22:04,686 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-22 21:22:04,686 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-22 21:22:04,686 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-22 21:22:04,687 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-22 21:22:04,687 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-22 21:22:04,691 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-22 21:22:04,696 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-22 21:22:04,713 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-22 21:22:04,714 INFO L82 PathProgramCache]: Analyzing trace with hash -1917499725, now seen corresponding path program 1 times [2018-11-22 21:22:04,714 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-22 21:22:04,714 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-22 21:22:04,714 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-22 21:22:04,715 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-22 21:22:04,715 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-22 21:22:04,716 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-22 21:22:04,717 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-22 21:22:04,719 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-22 21:22:04,720 INFO L82 PathProgramCache]: Analyzing trace with hash -312256491, now seen corresponding path program 1 times [2018-11-22 21:22:04,720 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-22 21:22:04,720 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-22 21:22:04,721 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-22 21:22:04,721 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-22 21:22:04,721 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-22 21:22:04,725 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-22 21:22:04,777 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-22 21:22:04,777 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-22 21:22:04,777 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-22 21:22:04,840 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-22 21:22:04,840 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-22 21:22:04,840 INFO L87 Difference]: Start difference. First operand 125856 states and 161487 transitions. cyclomatic complexity: 35663 Second operand 3 states. [2018-11-22 21:22:05,114 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-22 21:22:05,115 INFO L93 Difference]: Finished difference Result 149264 states and 190639 transitions. [2018-11-22 21:22:05,115 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-22 21:22:05,115 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 149264 states and 190639 transitions. [2018-11-22 21:22:05,482 INFO L131 ngComponentsAnalysis]: Automaton has 40 accepting balls. 146928 [2018-11-22 21:22:05,698 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 149264 states to 149264 states and 190639 transitions. [2018-11-22 21:22:05,698 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 149264 [2018-11-22 21:22:05,758 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 149264 [2018-11-22 21:22:05,759 INFO L73 IsDeterministic]: Start isDeterministic. Operand 149264 states and 190639 transitions. [2018-11-22 21:22:05,810 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-22 21:22:05,811 INFO L705 BuchiCegarLoop]: Abstraction has 149264 states and 190639 transitions. [2018-11-22 21:22:05,871 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 149264 states and 190639 transitions. [2018-11-22 21:22:06,536 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 149264 to 142736. [2018-11-22 21:22:06,537 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 142736 states. [2018-11-22 21:22:06,684 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 142736 states to 142736 states and 182703 transitions. [2018-11-22 21:22:06,684 INFO L728 BuchiCegarLoop]: Abstraction has 142736 states and 182703 transitions. [2018-11-22 21:22:06,684 INFO L608 BuchiCegarLoop]: Abstraction has 142736 states and 182703 transitions. [2018-11-22 21:22:06,684 INFO L442 BuchiCegarLoop]: ======== Iteration 33============ [2018-11-22 21:22:06,684 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 142736 states and 182703 transitions. [2018-11-22 21:22:06,973 INFO L131 ngComponentsAnalysis]: Automaton has 40 accepting balls. 140400 [2018-11-22 21:22:06,973 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-22 21:22:06,973 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-22 21:22:06,973 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-22 21:22:06,973 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-22 21:22:06,974 INFO L794 eck$LassoCheckResult]: Stem: 2729848#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2; 2729737#L-1 havoc main_#res;havoc main_~__retres1~10;havoc main_~__retres1~10;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 2729738#L1225 havoc start_simulation_#t~ret20, start_simulation_#t~ret21, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 2730277#L564 assume 1 == ~m_i~0;~m_st~0 := 0; 2729773#L571-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 2729459#L576-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 2729460#L581-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 2730282#L586-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 2729993#L591-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 2729565#L596-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 2729566#L601-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 2730268#L606-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 2730147#L611-1 assume !(0 == ~M_E~0); 2730148#L828-1 assume !(0 == ~T1_E~0); 2729870#L833-1 assume !(0 == ~T2_E~0); 2729582#L838-1 assume !(0 == ~T3_E~0); 2729583#L843-1 assume !(0 == ~T4_E~0); 2730387#L848-1 assume !(0 == ~T5_E~0); 2730157#L853-1 assume !(0 == ~T6_E~0); 2729856#L858-1 assume !(0 == ~T7_E~0); 2729372#L863-1 assume !(0 == ~T8_E~0); 2729373#L868-1 assume !(0 == ~E_1~0); 2730103#L873-1 assume !(0 == ~E_2~0); 2729946#L878-1 assume !(0 == ~E_3~0); 2729702#L883-1 assume !(0 == ~E_4~0); 2729703#L888-1 assume !(0 == ~E_5~0); 2730230#L893-1 assume !(0 == ~E_6~0); 2729912#L898-1 assume !(0 == ~E_7~0); 2729838#L903-1 assume !(0 == ~E_8~0); 2729523#L908-1 havoc activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 2729524#L392 assume !(1 == ~m_pc~0); 2729892#L392-2 is_master_triggered_~__retres1~0 := 0; 2729896#L403 is_master_triggered_#res := is_master_triggered_~__retres1~0; 2730437#L404 activate_threads_#t~ret10 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 2730240#L1025 assume !(0 != activate_threads_~tmp~1); 2730241#L1025-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 2730089#L411 assume !(1 == ~t1_pc~0); 2730055#L411-2 is_transmit1_triggered_~__retres1~1 := 0; 2729441#L422 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 2729442#L423 activate_threads_#t~ret11 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 2729547#L1033 assume !(0 != activate_threads_~tmp___0~0); 2729781#L1033-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 2729782#L430 assume !(1 == ~t2_pc~0); 2730254#L430-2 is_transmit2_triggered_~__retres1~2 := 0; 2729618#L441 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 2729567#L442 activate_threads_#t~ret12 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 2729568#L1041 assume !(0 != activate_threads_~tmp___1~0); 2730469#L1041-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 2730470#L449 assume !(1 == ~t3_pc~0); 2730333#L449-2 is_transmit3_triggered_~__retres1~3 := 0; 2730479#L460 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 2730499#L461 activate_threads_#t~ret13 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 2730273#L1049 assume !(0 != activate_threads_~tmp___2~0); 2730274#L1049-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 2729482#L468 assume !(1 == ~t4_pc~0); 2729483#L468-2 is_transmit4_triggered_~__retres1~4 := 0; 2729488#L479 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 2729901#L480 activate_threads_#t~ret14 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 2729843#L1057 assume !(0 != activate_threads_~tmp___3~0); 2729844#L1057-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 2729687#L487 assume !(1 == ~t5_pc~0); 2729433#L487-2 is_transmit5_triggered_~__retres1~5 := 0; 2729689#L498 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 2730076#L499 activate_threads_#t~ret15 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 2730077#L1065 assume !(0 != activate_threads_~tmp___4~0); 2730488#L1065-2 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 2729855#L506 assume !(1 == ~t6_pc~0); 2729852#L506-2 is_transmit6_triggered_~__retres1~6 := 0; 2729853#L517 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 2730271#L518 activate_threads_#t~ret16 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 2730174#L1073 assume !(0 != activate_threads_~tmp___5~0); 2730175#L1073-2 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 2729996#L525 assume !(1 == ~t7_pc~0); 2729997#L525-2 is_transmit7_triggered_~__retres1~7 := 0; 2729999#L536 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 2730471#L537 activate_threads_#t~ret17 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 2729708#L1081 assume !(0 != activate_threads_~tmp___6~0); 2729709#L1081-2 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 2729710#L544 assume !(1 == ~t8_pc~0); 2730023#L544-2 is_transmit8_triggered_~__retres1~8 := 0; 2729366#L555 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 2729367#L556 activate_threads_#t~ret18 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 2729511#L1089 assume !(0 != activate_threads_~tmp___7~0); 2730315#L1089-2 assume !(1 == ~M_E~0); 2729865#L921-1 assume !(1 == ~T1_E~0); 2729578#L926-1 assume !(1 == ~T2_E~0); 2729579#L931-1 assume !(1 == ~T3_E~0); 2730385#L936-1 assume !(1 == ~T4_E~0); 2730166#L941-1 assume !(1 == ~T5_E~0); 2729862#L946-1 assume !(1 == ~T6_E~0); 2729382#L951-1 assume !(1 == ~T7_E~0); 2729383#L956-1 assume !(1 == ~T8_E~0); 2730276#L961-1 assume !(1 == ~E_1~0); 2729954#L966-1 assume !(1 == ~E_2~0); 2729714#L971-1 assume !(1 == ~E_3~0); 2729715#L976-1 assume !(1 == ~E_4~0); 2730223#L981-1 assume !(1 == ~E_5~0); 2729910#L986-1 assume !(1 == ~E_6~0); 2729830#L991-1 assume !(1 == ~E_7~0); 2729517#L996-1 assume !(1 == ~E_8~0); 2729518#L1262-1 assume !false; 2741871#L1263 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret0, eval_#t~nondet1, eval_~tmp_ndt_1~0, eval_#t~nondet2, eval_~tmp_ndt_2~0, eval_#t~nondet3, eval_~tmp_ndt_3~0, eval_#t~nondet4, eval_~tmp_ndt_4~0, eval_#t~nondet5, eval_~tmp_ndt_5~0, eval_#t~nondet6, eval_~tmp_ndt_6~0, eval_#t~nondet7, eval_~tmp_ndt_7~0, eval_#t~nondet8, eval_~tmp_ndt_8~0, eval_#t~nondet9, eval_~tmp_ndt_9~0, eval_~tmp~0;havoc eval_~tmp~0; 2741869#L803 [2018-11-22 21:22:06,974 INFO L796 eck$LassoCheckResult]: Loop: 2741869#L803 assume !false; 2741867#L682 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~9;havoc exists_runnable_thread_~__retres1~9; 2741864#L624 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9 := 1; 2741862#L671 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~9; 2741860#L672 eval_#t~ret0 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret0;havoc eval_#t~ret0; 2741857#L686 assume 0 != eval_~tmp~0; 2741858#L686-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0;eval_~tmp_ndt_1~0 := eval_#t~nondet1;havoc eval_#t~nondet1; 2758484#L694 assume !(0 != eval_~tmp_ndt_1~0); 2758482#L691 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0;eval_~tmp_ndt_2~0 := eval_#t~nondet2;havoc eval_#t~nondet2; 2758454#L708 assume !(0 != eval_~tmp_ndt_2~0); 2741934#L705 assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0;eval_~tmp_ndt_3~0 := eval_#t~nondet3;havoc eval_#t~nondet3; 2741929#L722 assume !(0 != eval_~tmp_ndt_3~0); 2741930#L719 assume !(0 == ~t3_st~0); 2777900#L733 assume !(0 == ~t4_st~0); 2741886#L747 assume !(0 == ~t5_st~0); 2741884#L761 assume !(0 == ~t6_st~0); 2758559#L775 assume !(0 == ~t7_st~0); 2741874#L789 assume !(0 == ~t8_st~0); 2741869#L803 [2018-11-22 21:22:06,974 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-22 21:22:06,974 INFO L82 PathProgramCache]: Analyzing trace with hash 1464186463, now seen corresponding path program 2 times [2018-11-22 21:22:06,974 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-22 21:22:06,974 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-22 21:22:06,975 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-22 21:22:06,975 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-22 21:22:06,975 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-22 21:22:06,978 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-22 21:22:06,982 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-22 21:22:07,004 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-22 21:22:07,004 INFO L82 PathProgramCache]: Analyzing trace with hash -1823753845, now seen corresponding path program 1 times [2018-11-22 21:22:07,005 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-22 21:22:07,005 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-22 21:22:07,005 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-22 21:22:07,005 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-22 21:22:07,005 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-22 21:22:07,007 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-22 21:22:07,008 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-22 21:22:07,009 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-22 21:22:07,010 INFO L82 PathProgramCache]: Analyzing trace with hash 694146153, now seen corresponding path program 1 times [2018-11-22 21:22:07,010 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-22 21:22:07,010 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-22 21:22:07,011 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-22 21:22:07,011 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-22 21:22:07,011 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-22 21:22:07,015 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-22 21:22:07,051 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-22 21:22:07,051 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-22 21:22:07,052 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-22 21:22:07,116 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-22 21:22:07,116 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-22 21:22:07,116 INFO L87 Difference]: Start difference. First operand 142736 states and 182703 transitions. cyclomatic complexity: 40007 Second operand 3 states. [2018-11-22 21:22:07,871 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-22 21:22:07,872 INFO L93 Difference]: Finished difference Result 271376 states and 346399 transitions. [2018-11-22 21:22:07,872 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-22 21:22:07,872 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 271376 states and 346399 transitions. [2018-11-22 21:22:08,537 INFO L131 ngComponentsAnalysis]: Automaton has 40 accepting balls. 266816 [2018-11-22 21:22:08,926 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 271376 states to 271376 states and 346399 transitions. [2018-11-22 21:22:08,926 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 271376 [2018-11-22 21:22:09,027 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 271376 [2018-11-22 21:22:09,027 INFO L73 IsDeterministic]: Start isDeterministic. Operand 271376 states and 346399 transitions. [2018-11-22 21:22:09,115 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-22 21:22:09,115 INFO L705 BuchiCegarLoop]: Abstraction has 271376 states and 346399 transitions. [2018-11-22 21:22:09,218 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 271376 states and 346399 transitions. [2018-11-22 21:22:10,524 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 271376 to 258456. [2018-11-22 21:22:10,524 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 258456 states. [2018-11-22 21:22:10,815 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 258456 states to 258456 states and 330743 transitions. [2018-11-22 21:22:10,815 INFO L728 BuchiCegarLoop]: Abstraction has 258456 states and 330743 transitions. [2018-11-22 21:22:10,815 INFO L608 BuchiCegarLoop]: Abstraction has 258456 states and 330743 transitions. [2018-11-22 21:22:10,815 INFO L442 BuchiCegarLoop]: ======== Iteration 34============ [2018-11-22 21:22:10,815 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 258456 states and 330743 transitions. [2018-11-22 21:22:11,340 INFO L131 ngComponentsAnalysis]: Automaton has 40 accepting balls. 253896 [2018-11-22 21:22:11,340 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-22 21:22:11,340 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-22 21:22:11,341 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-22 21:22:11,341 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-22 21:22:11,341 INFO L794 eck$LassoCheckResult]: Stem: 3143965#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2; 3143855#L-1 havoc main_#res;havoc main_~__retres1~10;havoc main_~__retres1~10;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 3143856#L1225 havoc start_simulation_#t~ret20, start_simulation_#t~ret21, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 3144402#L564 assume 1 == ~m_i~0;~m_st~0 := 0; 3143889#L571-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 3143579#L576-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 3143580#L581-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 3144409#L586-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 3144117#L591-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 3143689#L596-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 3143690#L601-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 3144394#L606-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 3144274#L611-1 assume !(0 == ~M_E~0); 3144275#L828-1 assume !(0 == ~T1_E~0); 3143989#L833-1 assume !(0 == ~T2_E~0); 3143706#L838-1 assume !(0 == ~T3_E~0); 3143707#L843-1 assume !(0 == ~T4_E~0); 3144533#L848-1 assume !(0 == ~T5_E~0); 3144283#L853-1 assume !(0 == ~T6_E~0); 3143974#L858-1 assume !(0 == ~T7_E~0); 3143492#L863-1 assume !(0 == ~T8_E~0); 3143493#L868-1 assume !(0 == ~E_1~0); 3144230#L873-1 assume !(0 == ~E_2~0); 3144067#L878-1 assume !(0 == ~E_3~0); 3143824#L883-1 assume !(0 == ~E_4~0); 3143825#L888-1 assume !(0 == ~E_5~0); 3144353#L893-1 assume !(0 == ~E_6~0); 3144027#L898-1 assume !(0 == ~E_7~0); 3143955#L903-1 assume !(0 == ~E_8~0); 3143645#L908-1 havoc activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 3143646#L392 assume !(1 == ~m_pc~0); 3144010#L392-2 is_master_triggered_~__retres1~0 := 0; 3144013#L403 is_master_triggered_#res := is_master_triggered_~__retres1~0; 3144589#L404 activate_threads_#t~ret10 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 3144365#L1025 assume !(0 != activate_threads_~tmp~1); 3144366#L1025-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 3144216#L411 assume !(1 == ~t1_pc~0); 3144180#L411-2 is_transmit1_triggered_~__retres1~1 := 0; 3143558#L422 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 3143559#L423 activate_threads_#t~ret11 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 3143668#L1033 assume !(0 != activate_threads_~tmp___0~0); 3143897#L1033-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 3143898#L430 assume !(1 == ~t2_pc~0); 3144380#L430-2 is_transmit2_triggered_~__retres1~2 := 0; 3143740#L441 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 3143691#L442 activate_threads_#t~ret12 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 3143692#L1041 assume !(0 != activate_threads_~tmp___1~0); 3144614#L1041-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 3144615#L449 assume !(1 == ~t3_pc~0); 3144472#L449-2 is_transmit3_triggered_~__retres1~3 := 0; 3144627#L460 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 3144653#L461 activate_threads_#t~ret13 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 3144399#L1049 assume !(0 != activate_threads_~tmp___2~0); 3144400#L1049-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 3143601#L468 assume !(1 == ~t4_pc~0); 3143602#L468-2 is_transmit4_triggered_~__retres1~4 := 0; 3143609#L479 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 3144018#L480 activate_threads_#t~ret14 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 3143961#L1057 assume !(0 != activate_threads_~tmp___3~0); 3143962#L1057-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 3143809#L487 assume !(1 == ~t5_pc~0); 3143553#L487-2 is_transmit5_triggered_~__retres1~5 := 0; 3143811#L498 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 3144202#L499 activate_threads_#t~ret15 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 3144203#L1065 assume !(0 != activate_threads_~tmp___4~0); 3144638#L1065-2 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 3143973#L506 assume !(1 == ~t6_pc~0); 3143969#L506-2 is_transmit6_triggered_~__retres1~6 := 0; 3143970#L517 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 3144397#L518 activate_threads_#t~ret16 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 3144300#L1073 assume !(0 != activate_threads_~tmp___5~0); 3144301#L1073-2 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 3144120#L525 assume !(1 == ~t7_pc~0); 3144121#L525-2 is_transmit7_triggered_~__retres1~7 := 0; 3144124#L536 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 3144616#L537 activate_threads_#t~ret17 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 3143830#L1081 assume !(0 != activate_threads_~tmp___6~0); 3143831#L1081-2 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 3143832#L544 assume !(1 == ~t8_pc~0); 3144147#L544-2 is_transmit8_triggered_~__retres1~8 := 0; 3143486#L555 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 3143487#L556 activate_threads_#t~ret18 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 3143633#L1089 assume !(0 != activate_threads_~tmp___7~0); 3144450#L1089-2 assume !(1 == ~M_E~0); 3143984#L921-1 assume !(1 == ~T1_E~0); 3143702#L926-1 assume !(1 == ~T2_E~0); 3143703#L931-1 assume !(1 == ~T3_E~0); 3144531#L936-1 assume !(1 == ~T4_E~0); 3144293#L941-1 assume !(1 == ~T5_E~0); 3143980#L946-1 assume !(1 == ~T6_E~0); 3143502#L951-1 assume !(1 == ~T7_E~0); 3143503#L956-1 assume !(1 == ~T8_E~0); 3144401#L961-1 assume !(1 == ~E_1~0); 3144077#L966-1 assume !(1 == ~E_2~0); 3143836#L971-1 assume !(1 == ~E_3~0); 3143837#L976-1 assume !(1 == ~E_4~0); 3144347#L981-1 assume !(1 == ~E_5~0); 3144025#L986-1 assume !(1 == ~E_6~0); 3143948#L991-1 assume !(1 == ~E_7~0); 3143639#L996-1 assume !(1 == ~E_8~0); 3143640#L1262-1 assume !false; 3175520#L1263 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret0, eval_#t~nondet1, eval_~tmp_ndt_1~0, eval_#t~nondet2, eval_~tmp_ndt_2~0, eval_#t~nondet3, eval_~tmp_ndt_3~0, eval_#t~nondet4, eval_~tmp_ndt_4~0, eval_#t~nondet5, eval_~tmp_ndt_5~0, eval_#t~nondet6, eval_~tmp_ndt_6~0, eval_#t~nondet7, eval_~tmp_ndt_7~0, eval_#t~nondet8, eval_~tmp_ndt_8~0, eval_#t~nondet9, eval_~tmp_ndt_9~0, eval_~tmp~0;havoc eval_~tmp~0; 3175514#L803 [2018-11-22 21:22:11,341 INFO L796 eck$LassoCheckResult]: Loop: 3175514#L803 assume !false; 3175504#L682 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~9;havoc exists_runnable_thread_~__retres1~9; 3175497#L624 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9 := 1; 3175490#L671 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~9; 3175483#L672 eval_#t~ret0 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret0;havoc eval_#t~ret0; 3175477#L686 assume 0 != eval_~tmp~0; 3175471#L686-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0;eval_~tmp_ndt_1~0 := eval_#t~nondet1;havoc eval_#t~nondet1; 3175463#L694 assume !(0 != eval_~tmp_ndt_1~0); 3175457#L691 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0;eval_~tmp_ndt_2~0 := eval_#t~nondet2;havoc eval_#t~nondet2; 3175424#L708 assume !(0 != eval_~tmp_ndt_2~0); 3175450#L705 assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0;eval_~tmp_ndt_3~0 := eval_#t~nondet3;havoc eval_#t~nondet3; 3175575#L722 assume !(0 != eval_~tmp_ndt_3~0); 3175568#L719 assume 0 == ~t3_st~0;havoc eval_~tmp_ndt_4~0;eval_~tmp_ndt_4~0 := eval_#t~nondet4;havoc eval_#t~nondet4; 3172159#L736 assume !(0 != eval_~tmp_ndt_4~0); 3175555#L733 assume !(0 == ~t4_st~0); 3175547#L747 assume !(0 == ~t5_st~0); 3175540#L761 assume !(0 == ~t6_st~0); 3175531#L775 assume !(0 == ~t7_st~0); 3175523#L789 assume !(0 == ~t8_st~0); 3175514#L803 [2018-11-22 21:22:11,342 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-22 21:22:11,342 INFO L82 PathProgramCache]: Analyzing trace with hash 1464186463, now seen corresponding path program 3 times [2018-11-22 21:22:11,342 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-22 21:22:11,342 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-22 21:22:11,343 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-22 21:22:11,343 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-22 21:22:11,343 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-22 21:22:11,346 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-22 21:22:11,349 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-22 21:22:11,367 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-22 21:22:11,368 INFO L82 PathProgramCache]: Analyzing trace with hash -1336968407, now seen corresponding path program 1 times [2018-11-22 21:22:11,368 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-22 21:22:11,368 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-22 21:22:11,368 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-22 21:22:11,369 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-22 21:22:11,369 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-22 21:22:11,370 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-22 21:22:11,371 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-22 21:22:11,373 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-22 21:22:11,373 INFO L82 PathProgramCache]: Analyzing trace with hash -591479797, now seen corresponding path program 1 times [2018-11-22 21:22:11,373 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-22 21:22:11,373 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-22 21:22:11,374 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-22 21:22:11,374 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-22 21:22:11,374 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-22 21:22:11,378 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-22 21:22:11,412 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-22 21:22:11,412 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-22 21:22:11,412 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-22 21:22:11,488 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-22 21:22:11,488 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-22 21:22:11,488 INFO L87 Difference]: Start difference. First operand 258456 states and 330743 transitions. cyclomatic complexity: 72327 Second operand 3 states. [2018-11-22 21:22:12,023 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-22 21:22:12,024 INFO L93 Difference]: Finished difference Result 288312 states and 366823 transitions. [2018-11-22 21:22:12,024 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-22 21:22:12,024 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 288312 states and 366823 transitions. [2018-11-22 21:22:13,207 INFO L131 ngComponentsAnalysis]: Automaton has 44 accepting balls. 279920 [2018-11-22 21:22:13,570 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 288312 states to 288312 states and 366823 transitions. [2018-11-22 21:22:13,571 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 288312 [2018-11-22 21:22:13,654 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 288312 [2018-11-22 21:22:13,655 INFO L73 IsDeterministic]: Start isDeterministic. Operand 288312 states and 366823 transitions. [2018-11-22 21:22:13,733 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-22 21:22:13,733 INFO L705 BuchiCegarLoop]: Abstraction has 288312 states and 366823 transitions. [2018-11-22 21:22:13,827 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 288312 states and 366823 transitions. [2018-11-22 21:22:15,245 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 288312 to 288312. [2018-11-22 21:22:15,245 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 288312 states. [2018-11-22 21:22:15,557 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 288312 states to 288312 states and 366823 transitions. [2018-11-22 21:22:15,557 INFO L728 BuchiCegarLoop]: Abstraction has 288312 states and 366823 transitions. [2018-11-22 21:22:15,558 INFO L608 BuchiCegarLoop]: Abstraction has 288312 states and 366823 transitions. [2018-11-22 21:22:15,558 INFO L442 BuchiCegarLoop]: ======== Iteration 35============ [2018-11-22 21:22:15,558 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 288312 states and 366823 transitions. [2018-11-22 21:22:16,130 INFO L131 ngComponentsAnalysis]: Automaton has 44 accepting balls. 279920 [2018-11-22 21:22:16,130 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-22 21:22:16,130 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-22 21:22:16,131 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-22 21:22:16,131 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-22 21:22:16,131 INFO L794 eck$LassoCheckResult]: Stem: 3690730#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2; 3690622#L-1 havoc main_#res;havoc main_~__retres1~10;havoc main_~__retres1~10;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 3690623#L1225 havoc start_simulation_#t~ret20, start_simulation_#t~ret21, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 3691156#L564 assume 1 == ~m_i~0;~m_st~0 := 0; 3690656#L571-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 3690354#L576-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 3690355#L581-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 3691159#L586-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 3690880#L591-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 3690458#L596-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 3690459#L601-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 3691147#L606-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 3691034#L611-1 assume !(0 == ~M_E~0); 3691035#L828-1 assume !(0 == ~T1_E~0); 3690754#L833-1 assume !(0 == ~T2_E~0); 3690475#L838-1 assume !(0 == ~T3_E~0); 3690476#L843-1 assume !(0 == ~T4_E~0); 3691267#L848-1 assume !(0 == ~T5_E~0); 3691044#L853-1 assume !(0 == ~T6_E~0); 3690737#L858-1 assume !(0 == ~T7_E~0); 3690268#L863-1 assume !(0 == ~T8_E~0); 3690269#L868-1 assume !(0 == ~E_1~0); 3690991#L873-1 assume !(0 == ~E_2~0); 3690832#L878-1 assume !(0 == ~E_3~0); 3690590#L883-1 assume !(0 == ~E_4~0); 3690591#L888-1 assume !(0 == ~E_5~0); 3691110#L893-1 assume !(0 == ~E_6~0); 3690794#L898-1 assume !(0 == ~E_7~0); 3690720#L903-1 assume !(0 == ~E_8~0); 3690416#L908-1 havoc activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 3690417#L392 assume !(1 == ~m_pc~0); 3690774#L392-2 is_master_triggered_~__retres1~0 := 0; 3690778#L403 is_master_triggered_#res := is_master_triggered_~__retres1~0; 3691327#L404 activate_threads_#t~ret10 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 3691121#L1025 assume !(0 != activate_threads_~tmp~1); 3691122#L1025-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 3690977#L411 assume !(1 == ~t1_pc~0); 3690942#L411-2 is_transmit1_triggered_~__retres1~1 := 0; 3690334#L422 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 3690335#L423 activate_threads_#t~ret11 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 3690437#L1033 assume !(0 != activate_threads_~tmp___0~0); 3690665#L1033-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 3690666#L430 assume !(1 == ~t2_pc~0); 3691135#L430-2 is_transmit2_triggered_~__retres1~2 := 0; 3690508#L441 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 3690460#L442 activate_threads_#t~ret12 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 3690461#L1041 assume !(0 != activate_threads_~tmp___1~0); 3691357#L1041-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 3691358#L449 assume !(1 == ~t3_pc~0); 3691211#L449-2 is_transmit3_triggered_~__retres1~3 := 0; 3691366#L460 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 3691385#L461 activate_threads_#t~ret13 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 3691152#L1049 assume !(0 != activate_threads_~tmp___2~0); 3691153#L1049-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 3690376#L468 assume !(1 == ~t4_pc~0); 3690377#L468-2 is_transmit4_triggered_~__retres1~4 := 0; 3690382#L479 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 3690784#L480 activate_threads_#t~ret14 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 3690725#L1057 assume !(0 != activate_threads_~tmp___3~0); 3690726#L1057-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 3690575#L487 assume !(1 == ~t5_pc~0); 3690329#L487-2 is_transmit5_triggered_~__retres1~5 := 0; 3690577#L498 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 3690964#L499 activate_threads_#t~ret15 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 3690965#L1065 assume !(0 != activate_threads_~tmp___4~0); 3691375#L1065-2 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 3690736#L506 assume !(1 == ~t6_pc~0); 3690732#L506-2 is_transmit6_triggered_~__retres1~6 := 0; 3690733#L517 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 3691150#L518 activate_threads_#t~ret16 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 3691061#L1073 assume !(0 != activate_threads_~tmp___5~0); 3691062#L1073-2 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 3690883#L525 assume !(1 == ~t7_pc~0); 3690884#L525-2 is_transmit7_triggered_~__retres1~7 := 0; 3690887#L536 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 3691359#L537 activate_threads_#t~ret17 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 3690596#L1081 assume !(0 != activate_threads_~tmp___6~0); 3690597#L1081-2 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 3690598#L544 assume !(1 == ~t8_pc~0); 3690909#L544-2 is_transmit8_triggered_~__retres1~8 := 0; 3690262#L555 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 3690263#L556 activate_threads_#t~ret18 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 3690405#L1089 assume !(0 != activate_threads_~tmp___7~0); 3691190#L1089-2 assume !(1 == ~M_E~0); 3690747#L921-1 assume !(1 == ~T1_E~0); 3690471#L926-1 assume !(1 == ~T2_E~0); 3690472#L931-1 assume !(1 == ~T3_E~0); 3691265#L936-1 assume !(1 == ~T4_E~0); 3691054#L941-1 assume !(1 == ~T5_E~0); 3690743#L946-1 assume !(1 == ~T6_E~0); 3690278#L951-1 assume !(1 == ~T7_E~0); 3690279#L956-1 assume !(1 == ~T8_E~0); 3691155#L961-1 assume !(1 == ~E_1~0); 3690841#L966-1 assume !(1 == ~E_2~0); 3690602#L971-1 assume !(1 == ~E_3~0); 3690603#L976-1 assume !(1 == ~E_4~0); 3691105#L981-1 assume !(1 == ~E_5~0); 3690792#L986-1 assume !(1 == ~E_6~0); 3690715#L991-1 assume !(1 == ~E_7~0); 3690411#L996-1 assume !(1 == ~E_8~0); 3690412#L1262-1 assume !false; 3803067#L1263 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret0, eval_#t~nondet1, eval_~tmp_ndt_1~0, eval_#t~nondet2, eval_~tmp_ndt_2~0, eval_#t~nondet3, eval_~tmp_ndt_3~0, eval_#t~nondet4, eval_~tmp_ndt_4~0, eval_#t~nondet5, eval_~tmp_ndt_5~0, eval_#t~nondet6, eval_~tmp_ndt_6~0, eval_#t~nondet7, eval_~tmp_ndt_7~0, eval_#t~nondet8, eval_~tmp_ndt_8~0, eval_#t~nondet9, eval_~tmp_ndt_9~0, eval_~tmp~0;havoc eval_~tmp~0; 3803062#L803 [2018-11-22 21:22:16,131 INFO L796 eck$LassoCheckResult]: Loop: 3803062#L803 assume !false; 3803060#L682 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~9;havoc exists_runnable_thread_~__retres1~9; 3803057#L624 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9 := 1; 3803055#L671 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~9; 3803053#L672 eval_#t~ret0 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret0;havoc eval_#t~ret0; 3803052#L686 assume 0 != eval_~tmp~0; 3803049#L686-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0;eval_~tmp_ndt_1~0 := eval_#t~nondet1;havoc eval_#t~nondet1; 3803047#L694 assume !(0 != eval_~tmp_ndt_1~0); 3767816#L691 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0;eval_~tmp_ndt_2~0 := eval_#t~nondet2;havoc eval_#t~nondet2; 3767812#L708 assume !(0 != eval_~tmp_ndt_2~0); 3767810#L705 assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0;eval_~tmp_ndt_3~0 := eval_#t~nondet3;havoc eval_#t~nondet3; 3767807#L722 assume !(0 != eval_~tmp_ndt_3~0); 3767805#L719 assume 0 == ~t3_st~0;havoc eval_~tmp_ndt_4~0;eval_~tmp_ndt_4~0 := eval_#t~nondet4;havoc eval_#t~nondet4; 3767710#L736 assume !(0 != eval_~tmp_ndt_4~0); 3767803#L733 assume 0 == ~t4_st~0;havoc eval_~tmp_ndt_5~0;eval_~tmp_ndt_5~0 := eval_#t~nondet5;havoc eval_#t~nondet5; 3811688#L750 assume !(0 != eval_~tmp_ndt_5~0); 3791162#L747 assume !(0 == ~t5_st~0); 3791158#L761 assume !(0 == ~t6_st~0); 3791154#L775 assume !(0 == ~t7_st~0); 3791152#L789 assume !(0 == ~t8_st~0); 3803062#L803 [2018-11-22 21:22:16,131 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-22 21:22:16,131 INFO L82 PathProgramCache]: Analyzing trace with hash 1464186463, now seen corresponding path program 4 times [2018-11-22 21:22:16,131 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-22 21:22:16,131 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-22 21:22:16,132 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-22 21:22:16,132 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-22 21:22:16,132 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-22 21:22:16,136 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-22 21:22:16,139 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-22 21:22:16,155 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-22 21:22:16,155 INFO L82 PathProgramCache]: Analyzing trace with hash -1426322155, now seen corresponding path program 1 times [2018-11-22 21:22:16,155 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-22 21:22:16,155 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-22 21:22:16,156 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-22 21:22:16,156 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-22 21:22:16,156 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-22 21:22:16,157 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-22 21:22:16,159 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-22 21:22:16,160 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-22 21:22:16,161 INFO L82 PathProgramCache]: Analyzing trace with hash 208988275, now seen corresponding path program 1 times [2018-11-22 21:22:16,161 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-22 21:22:16,161 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-22 21:22:16,161 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-22 21:22:16,162 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-22 21:22:16,162 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-22 21:22:16,166 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-22 21:22:16,206 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-22 21:22:16,206 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-22 21:22:16,206 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-22 21:22:16,290 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-22 21:22:16,290 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-22 21:22:16,291 INFO L87 Difference]: Start difference. First operand 288312 states and 366823 transitions. cyclomatic complexity: 78555 Second operand 3 states. [2018-11-22 21:22:17,878 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-22 21:22:17,878 INFO L93 Difference]: Finished difference Result 533944 states and 678711 transitions. [2018-11-22 21:22:17,879 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-22 21:22:17,879 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 533944 states and 678711 transitions. [2018-11-22 21:22:19,249 INFO L131 ngComponentsAnalysis]: Automaton has 44 accepting balls. 517272 [2018-11-22 21:22:20,006 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 533944 states to 533944 states and 678711 transitions. [2018-11-22 21:22:20,006 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 533944 [2018-11-22 21:22:20,176 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 533944 [2018-11-22 21:22:20,177 INFO L73 IsDeterministic]: Start isDeterministic. Operand 533944 states and 678711 transitions. [2018-11-22 21:22:20,328 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-22 21:22:20,328 INFO L705 BuchiCegarLoop]: Abstraction has 533944 states and 678711 transitions. [2018-11-22 21:22:20,517 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 533944 states and 678711 transitions. [2018-11-22 21:22:29,761 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 533944 to 515520. [2018-11-22 21:22:29,761 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 515520 states. [2018-11-22 21:22:30,427 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 515520 states to 515520 states and 656903 transitions. [2018-11-22 21:22:30,427 INFO L728 BuchiCegarLoop]: Abstraction has 515520 states and 656903 transitions. [2018-11-22 21:22:30,427 INFO L608 BuchiCegarLoop]: Abstraction has 515520 states and 656903 transitions. [2018-11-22 21:22:30,427 INFO L442 BuchiCegarLoop]: ======== Iteration 36============ [2018-11-22 21:22:30,428 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 515520 states and 656903 transitions. [2018-11-22 21:22:31,559 INFO L131 ngComponentsAnalysis]: Automaton has 44 accepting balls. 498848 [2018-11-22 21:22:31,559 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-22 21:22:31,559 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-22 21:22:31,560 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-22 21:22:31,560 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-22 21:22:31,561 INFO L794 eck$LassoCheckResult]: Stem: 4513019#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2; 4512910#L-1 havoc main_#res;havoc main_~__retres1~10;havoc main_~__retres1~10;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 4512911#L1225 havoc start_simulation_#t~ret20, start_simulation_#t~ret21, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 4513467#L564 assume 1 == ~m_i~0;~m_st~0 := 0; 4512944#L571-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 4512622#L576-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 4512623#L581-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 4513474#L586-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 4513174#L591-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 4512731#L596-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 4512732#L601-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 4513459#L606-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 4513333#L611-1 assume !(0 == ~M_E~0); 4513334#L828-1 assume !(0 == ~T1_E~0); 4513044#L833-1 assume !(0 == ~T2_E~0); 4512748#L838-1 assume !(0 == ~T3_E~0); 4512749#L843-1 assume !(0 == ~T4_E~0); 4513610#L848-1 assume !(0 == ~T5_E~0); 4513343#L853-1 assume !(0 == ~T6_E~0); 4513027#L858-1 assume !(0 == ~T7_E~0); 4512532#L863-1 assume !(0 == ~T8_E~0); 4512533#L868-1 assume !(0 == ~E_1~0); 4513290#L873-1 assume !(0 == ~E_2~0); 4513127#L878-1 assume !(0 == ~E_3~0); 4512877#L883-1 assume !(0 == ~E_4~0); 4512878#L888-1 assume !(0 == ~E_5~0); 4513419#L893-1 assume !(0 == ~E_6~0); 4513087#L898-1 assume !(0 == ~E_7~0); 4513010#L903-1 assume !(0 == ~E_8~0); 4512686#L908-1 havoc activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 4512687#L392 assume !(1 == ~m_pc~0); 4513066#L392-2 is_master_triggered_~__retres1~0 := 0; 4513069#L403 is_master_triggered_#res := is_master_triggered_~__retres1~0; 4513677#L404 activate_threads_#t~ret10 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 4513429#L1025 assume !(0 != activate_threads_~tmp~1); 4513430#L1025-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 4513274#L411 assume !(1 == ~t1_pc~0); 4513238#L411-2 is_transmit1_triggered_~__retres1~1 := 0; 4512604#L422 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 4512605#L423 activate_threads_#t~ret11 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 4512710#L1033 assume !(0 != activate_threads_~tmp___0~0); 4512952#L1033-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 4512953#L430 assume !(1 == ~t2_pc~0); 4513446#L430-2 is_transmit2_triggered_~__retres1~2 := 0; 4512786#L441 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 4512733#L442 activate_threads_#t~ret12 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 4512734#L1041 assume !(0 != activate_threads_~tmp___1~0); 4513708#L1041-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 4513710#L449 assume !(1 == ~t3_pc~0); 4513538#L449-2 is_transmit3_triggered_~__retres1~3 := 0; 4513720#L460 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 4513746#L461 activate_threads_#t~ret13 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 4513464#L1049 assume !(0 != activate_threads_~tmp___2~0); 4513465#L1049-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 4512648#L468 assume !(1 == ~t4_pc~0); 4512649#L468-2 is_transmit4_triggered_~__retres1~4 := 0; 4512654#L479 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 4513075#L480 activate_threads_#t~ret14 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 4513014#L1057 assume !(0 != activate_threads_~tmp___3~0); 4513015#L1057-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 4512862#L487 assume !(1 == ~t5_pc~0); 4512595#L487-2 is_transmit5_triggered_~__retres1~5 := 0; 4512864#L498 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 4513259#L499 activate_threads_#t~ret15 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 4513260#L1065 assume !(0 != activate_threads_~tmp___4~0); 4513731#L1065-2 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 4513026#L506 assume !(1 == ~t6_pc~0); 4513023#L506-2 is_transmit6_triggered_~__retres1~6 := 0; 4513024#L517 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 4513462#L518 activate_threads_#t~ret16 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 4513360#L1073 assume !(0 != activate_threads_~tmp___5~0); 4513361#L1073-2 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 4513177#L525 assume !(1 == ~t7_pc~0); 4513178#L525-2 is_transmit7_triggered_~__retres1~7 := 0; 4513180#L536 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 4513711#L537 activate_threads_#t~ret17 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 4512883#L1081 assume !(0 != activate_threads_~tmp___6~0); 4512884#L1081-2 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 4512885#L544 assume !(1 == ~t8_pc~0); 4513204#L544-2 is_transmit8_triggered_~__retres1~8 := 0; 4512526#L555 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 4512527#L556 activate_threads_#t~ret18 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 4512675#L1089 assume !(0 != activate_threads_~tmp___7~0); 4513517#L1089-2 assume !(1 == ~M_E~0); 4513039#L921-1 assume !(1 == ~T1_E~0); 4512744#L926-1 assume !(1 == ~T2_E~0); 4512745#L931-1 assume !(1 == ~T3_E~0); 4513608#L936-1 assume !(1 == ~T4_E~0); 4513353#L941-1 assume !(1 == ~T5_E~0); 4513035#L946-1 assume !(1 == ~T6_E~0); 4512542#L951-1 assume !(1 == ~T7_E~0); 4512543#L956-1 assume !(1 == ~T8_E~0); 4513466#L961-1 assume !(1 == ~E_1~0); 4513137#L966-1 assume !(1 == ~E_2~0); 4512889#L971-1 assume !(1 == ~E_3~0); 4512890#L976-1 assume !(1 == ~E_4~0); 4513412#L981-1 assume !(1 == ~E_5~0); 4513085#L986-1 assume !(1 == ~E_6~0); 4513004#L991-1 assume !(1 == ~E_7~0); 4512681#L996-1 assume !(1 == ~E_8~0); 4512682#L1262-1 assume !false; 4573551#L1263 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret0, eval_#t~nondet1, eval_~tmp_ndt_1~0, eval_#t~nondet2, eval_~tmp_ndt_2~0, eval_#t~nondet3, eval_~tmp_ndt_3~0, eval_#t~nondet4, eval_~tmp_ndt_4~0, eval_#t~nondet5, eval_~tmp_ndt_5~0, eval_#t~nondet6, eval_~tmp_ndt_6~0, eval_#t~nondet7, eval_~tmp_ndt_7~0, eval_#t~nondet8, eval_~tmp_ndt_8~0, eval_#t~nondet9, eval_~tmp_ndt_9~0, eval_~tmp~0;havoc eval_~tmp~0; 4573549#L803 [2018-11-22 21:22:31,561 INFO L796 eck$LassoCheckResult]: Loop: 4573549#L803 assume !false; 4573546#L682 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~9;havoc exists_runnable_thread_~__retres1~9; 4573543#L624 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9 := 1; 4573542#L671 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~9; 4573539#L672 eval_#t~ret0 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret0;havoc eval_#t~ret0; 4573537#L686 assume 0 != eval_~tmp~0; 4573534#L686-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0;eval_~tmp_ndt_1~0 := eval_#t~nondet1;havoc eval_#t~nondet1; 4573531#L694 assume !(0 != eval_~tmp_ndt_1~0); 4573532#L691 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0;eval_~tmp_ndt_2~0 := eval_#t~nondet2;havoc eval_#t~nondet2; 4595362#L708 assume !(0 != eval_~tmp_ndt_2~0); 4595526#L705 assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0;eval_~tmp_ndt_3~0 := eval_#t~nondet3;havoc eval_#t~nondet3; 4589301#L722 assume !(0 != eval_~tmp_ndt_3~0); 4573839#L719 assume 0 == ~t3_st~0;havoc eval_~tmp_ndt_4~0;eval_~tmp_ndt_4~0 := eval_#t~nondet4;havoc eval_#t~nondet4; 4573836#L736 assume !(0 != eval_~tmp_ndt_4~0); 4573834#L733 assume 0 == ~t4_st~0;havoc eval_~tmp_ndt_5~0;eval_~tmp_ndt_5~0 := eval_#t~nondet5;havoc eval_#t~nondet5; 4573831#L750 assume !(0 != eval_~tmp_ndt_5~0); 4573578#L747 assume 0 == ~t5_st~0;havoc eval_~tmp_ndt_6~0;eval_~tmp_ndt_6~0 := eval_#t~nondet6;havoc eval_#t~nondet6; 4573575#L764 assume !(0 != eval_~tmp_ndt_6~0); 4573573#L761 assume !(0 == ~t6_st~0); 4573566#L775 assume !(0 == ~t7_st~0); 4573554#L789 assume !(0 == ~t8_st~0); 4573549#L803 [2018-11-22 21:22:31,561 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-22 21:22:31,561 INFO L82 PathProgramCache]: Analyzing trace with hash 1464186463, now seen corresponding path program 5 times [2018-11-22 21:22:31,561 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-22 21:22:31,561 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-22 21:22:31,562 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-22 21:22:31,562 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-22 21:22:31,562 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-22 21:22:31,567 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-22 21:22:31,571 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-22 21:22:31,589 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-22 21:22:31,589 INFO L82 PathProgramCache]: Analyzing trace with hash -1499367521, now seen corresponding path program 1 times [2018-11-22 21:22:31,589 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-22 21:22:31,589 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-22 21:22:31,590 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-22 21:22:31,590 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-22 21:22:31,590 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-22 21:22:31,591 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-22 21:22:31,593 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-22 21:22:31,595 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-22 21:22:31,595 INFO L82 PathProgramCache]: Analyzing trace with hash 1950615553, now seen corresponding path program 1 times [2018-11-22 21:22:31,595 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-22 21:22:31,595 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-22 21:22:31,596 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-22 21:22:31,596 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-22 21:22:31,596 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-22 21:22:31,600 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-22 21:22:31,650 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-22 21:22:31,650 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-22 21:22:31,650 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-22 21:22:32,451 WARN L180 SmtUtils]: Spent 799.00 ms on a formula simplification. DAG size of input: 56 DAG size of output: 54 [2018-11-22 21:22:32,483 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-22 21:22:32,483 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-22 21:22:32,483 INFO L87 Difference]: Start difference. First operand 515520 states and 656903 transitions. cyclomatic complexity: 141427 Second operand 3 states. [2018-11-22 21:22:33,813 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-22 21:22:33,813 INFO L93 Difference]: Finished difference Result 639776 states and 812991 transitions. [2018-11-22 21:22:33,813 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-22 21:22:33,814 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 639776 states and 812991 transitions. [2018-11-22 21:22:35,642 INFO L131 ngComponentsAnalysis]: Automaton has 46 accepting balls. 611376 [2018-11-22 21:22:37,751 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 639776 states to 639776 states and 812991 transitions. [2018-11-22 21:22:37,751 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 639776 [2018-11-22 21:22:37,934 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 639776 [2018-11-22 21:22:37,934 INFO L73 IsDeterministic]: Start isDeterministic. Operand 639776 states and 812991 transitions. [2018-11-22 21:22:38,102 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-22 21:22:38,103 INFO L705 BuchiCegarLoop]: Abstraction has 639776 states and 812991 transitions. [2018-11-22 21:22:38,307 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 639776 states and 812991 transitions. [2018-11-22 21:22:49,269 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 639776 to 626240. [2018-11-22 21:22:49,269 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 626240 states. [2018-11-22 21:22:50,585 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 626240 states to 626240 states and 797575 transitions. [2018-11-22 21:22:50,585 INFO L728 BuchiCegarLoop]: Abstraction has 626240 states and 797575 transitions. [2018-11-22 21:22:50,585 INFO L608 BuchiCegarLoop]: Abstraction has 626240 states and 797575 transitions. [2018-11-22 21:22:50,585 INFO L442 BuchiCegarLoop]: ======== Iteration 37============ [2018-11-22 21:22:50,586 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 626240 states and 797575 transitions. [2018-11-22 21:22:51,824 INFO L131 ngComponentsAnalysis]: Automaton has 46 accepting balls. 597840 [2018-11-22 21:22:51,825 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-22 21:22:51,825 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-22 21:22:51,825 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-22 21:22:51,826 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-22 21:22:51,826 INFO L794 eck$LassoCheckResult]: Stem: 5668313#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2; 5668207#L-1 havoc main_#res;havoc main_~__retres1~10;havoc main_~__retres1~10;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 5668208#L1225 havoc start_simulation_#t~ret20, start_simulation_#t~ret21, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 5668776#L564 assume 1 == ~m_i~0;~m_st~0 := 0; 5668241#L571-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 5667927#L576-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 5667928#L581-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 5668784#L586-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 5668477#L591-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 5668037#L596-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 5668038#L601-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 5668767#L606-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 5668642#L611-1 assume !(0 == ~M_E~0); 5668643#L828-1 assume !(0 == ~T1_E~0); 5668337#L833-1 assume !(0 == ~T2_E~0); 5668055#L838-1 assume !(0 == ~T3_E~0); 5668056#L843-1 assume !(0 == ~T4_E~0); 5668923#L848-1 assume !(0 == ~T5_E~0); 5668653#L853-1 assume !(0 == ~T6_E~0); 5668321#L858-1 assume !(0 == ~T7_E~0); 5667836#L863-1 assume !(0 == ~T8_E~0); 5667837#L868-1 assume !(0 == ~E_1~0); 5668594#L873-1 assume !(0 == ~E_2~0); 5668422#L878-1 assume !(0 == ~E_3~0); 5668175#L883-1 assume !(0 == ~E_4~0); 5668176#L888-1 assume !(0 == ~E_5~0); 5668730#L893-1 assume !(0 == ~E_6~0); 5668383#L898-1 assume !(0 == ~E_7~0); 5668301#L903-1 assume !(0 == ~E_8~0); 5667996#L908-1 havoc activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 5667997#L392 assume !(1 == ~m_pc~0); 5668361#L392-2 is_master_triggered_~__retres1~0 := 0; 5668366#L403 is_master_triggered_#res := is_master_triggered_~__retres1~0; 5668991#L404 activate_threads_#t~ret10 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 5668739#L1025 assume !(0 != activate_threads_~tmp~1); 5668740#L1025-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 5668579#L411 assume !(1 == ~t1_pc~0); 5668545#L411-2 is_transmit1_triggered_~__retres1~1 := 0; 5667906#L422 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 5667907#L423 activate_threads_#t~ret11 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 5668018#L1033 assume !(0 != activate_threads_~tmp___0~0); 5668250#L1033-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 5668251#L430 assume !(1 == ~t2_pc~0); 5668753#L430-2 is_transmit2_triggered_~__retres1~2 := 0; 5668091#L441 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 5668039#L442 activate_threads_#t~ret12 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 5668040#L1041 assume !(0 != activate_threads_~tmp___1~0); 5669029#L1041-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 5669030#L449 assume !(1 == ~t3_pc~0); 5668847#L449-2 is_transmit3_triggered_~__retres1~3 := 0; 5669042#L460 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 5669077#L461 activate_threads_#t~ret13 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 5668772#L1049 assume !(0 != activate_threads_~tmp___2~0); 5668773#L1049-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 5667956#L468 assume !(1 == ~t4_pc~0); 5667957#L468-2 is_transmit4_triggered_~__retres1~4 := 0; 5667962#L479 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 5668372#L480 activate_threads_#t~ret14 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 5668309#L1057 assume !(0 != activate_threads_~tmp___3~0); 5668310#L1057-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 5668160#L487 assume !(1 == ~t5_pc~0); 5667897#L487-2 is_transmit5_triggered_~__retres1~5 := 0; 5668162#L498 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 5668565#L499 activate_threads_#t~ret15 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 5668566#L1065 assume !(0 != activate_threads_~tmp___4~0); 5669054#L1065-2 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 5668320#L506 assume !(1 == ~t6_pc~0); 5668317#L506-2 is_transmit6_triggered_~__retres1~6 := 0; 5668318#L517 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 5668770#L518 activate_threads_#t~ret16 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 5668673#L1073 assume !(0 != activate_threads_~tmp___5~0); 5668674#L1073-2 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 5668480#L525 assume !(1 == ~t7_pc~0); 5668481#L525-2 is_transmit7_triggered_~__retres1~7 := 0; 5668483#L536 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 5669031#L537 activate_threads_#t~ret17 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 5668181#L1081 assume !(0 != activate_threads_~tmp___6~0); 5668182#L1081-2 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 5668183#L544 assume !(1 == ~t8_pc~0); 5668508#L544-2 is_transmit8_triggered_~__retres1~8 := 0; 5667830#L555 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 5667831#L556 activate_threads_#t~ret18 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 5667984#L1089 assume !(0 != activate_threads_~tmp___7~0); 5668825#L1089-2 assume !(1 == ~M_E~0); 5668330#L921-1 assume !(1 == ~T1_E~0); 5668051#L926-1 assume !(1 == ~T2_E~0); 5668052#L931-1 assume !(1 == ~T3_E~0); 5668921#L936-1 assume !(1 == ~T4_E~0); 5668666#L941-1 assume !(1 == ~T5_E~0); 5668327#L946-1 assume !(1 == ~T6_E~0); 5667846#L951-1 assume !(1 == ~T7_E~0); 5667847#L956-1 assume !(1 == ~T8_E~0); 5668775#L961-1 assume !(1 == ~E_1~0); 5668434#L966-1 assume !(1 == ~E_2~0); 5668187#L971-1 assume !(1 == ~E_3~0); 5668188#L976-1 assume !(1 == ~E_4~0); 5668723#L981-1 assume !(1 == ~E_5~0); 5668381#L986-1 assume !(1 == ~E_6~0); 5668295#L991-1 assume !(1 == ~E_7~0); 5667991#L996-1 assume !(1 == ~E_8~0); 5667992#L1262-1 assume !false; 5786551#L1263 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret0, eval_#t~nondet1, eval_~tmp_ndt_1~0, eval_#t~nondet2, eval_~tmp_ndt_2~0, eval_#t~nondet3, eval_~tmp_ndt_3~0, eval_#t~nondet4, eval_~tmp_ndt_4~0, eval_#t~nondet5, eval_~tmp_ndt_5~0, eval_#t~nondet6, eval_~tmp_ndt_6~0, eval_#t~nondet7, eval_~tmp_ndt_7~0, eval_#t~nondet8, eval_~tmp_ndt_8~0, eval_#t~nondet9, eval_~tmp_ndt_9~0, eval_~tmp~0;havoc eval_~tmp~0; 5786549#L803 [2018-11-22 21:22:51,826 INFO L796 eck$LassoCheckResult]: Loop: 5786549#L803 assume !false; 5786547#L682 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~9;havoc exists_runnable_thread_~__retres1~9; 5786544#L624 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9 := 1; 5786542#L671 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~9; 5786540#L672 eval_#t~ret0 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret0;havoc eval_#t~ret0; 5786538#L686 assume 0 != eval_~tmp~0; 5786535#L686-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0;eval_~tmp_ndt_1~0 := eval_#t~nondet1;havoc eval_#t~nondet1; 5786531#L694 assume !(0 != eval_~tmp_ndt_1~0); 5777509#L691 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0;eval_~tmp_ndt_2~0 := eval_#t~nondet2;havoc eval_#t~nondet2; 5777506#L708 assume !(0 != eval_~tmp_ndt_2~0); 5777502#L705 assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0;eval_~tmp_ndt_3~0 := eval_#t~nondet3;havoc eval_#t~nondet3; 5777499#L722 assume !(0 != eval_~tmp_ndt_3~0); 5774995#L719 assume 0 == ~t3_st~0;havoc eval_~tmp_ndt_4~0;eval_~tmp_ndt_4~0 := eval_#t~nondet4;havoc eval_#t~nondet4; 5774993#L736 assume !(0 != eval_~tmp_ndt_4~0); 5774992#L733 assume 0 == ~t4_st~0;havoc eval_~tmp_ndt_5~0;eval_~tmp_ndt_5~0 := eval_#t~nondet5;havoc eval_#t~nondet5; 5774990#L750 assume !(0 != eval_~tmp_ndt_5~0); 5762320#L747 assume 0 == ~t5_st~0;havoc eval_~tmp_ndt_6~0;eval_~tmp_ndt_6~0 := eval_#t~nondet6;havoc eval_#t~nondet6; 5750222#L764 assume !(0 != eval_~tmp_ndt_6~0); 5762317#L761 assume 0 == ~t6_st~0;havoc eval_~tmp_ndt_7~0;eval_~tmp_ndt_7~0 := eval_#t~nondet7;havoc eval_#t~nondet7; 5786568#L778 assume !(0 != eval_~tmp_ndt_7~0); 5786566#L775 assume !(0 == ~t7_st~0); 5786554#L789 assume !(0 == ~t8_st~0); 5786549#L803 [2018-11-22 21:22:51,826 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-22 21:22:51,826 INFO L82 PathProgramCache]: Analyzing trace with hash 1464186463, now seen corresponding path program 6 times [2018-11-22 21:22:51,827 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-22 21:22:51,827 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-22 21:22:51,827 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-22 21:22:51,828 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-22 21:22:51,828 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-22 21:22:51,832 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-22 21:22:51,836 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-22 21:22:51,846 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-22 21:22:51,846 INFO L82 PathProgramCache]: Analyzing trace with hash 756738207, now seen corresponding path program 1 times [2018-11-22 21:22:51,846 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-22 21:22:51,846 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-22 21:22:51,847 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-22 21:22:51,847 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-22 21:22:51,847 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-22 21:22:51,848 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-22 21:22:51,849 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-22 21:22:51,851 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-22 21:22:51,852 INFO L82 PathProgramCache]: Analyzing trace with hash 332031101, now seen corresponding path program 1 times [2018-11-22 21:22:51,852 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-22 21:22:51,852 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-22 21:22:51,852 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-22 21:22:51,852 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-22 21:22:51,852 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-22 21:22:51,856 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-22 21:22:51,890 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-22 21:22:51,890 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-22 21:22:51,890 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-22 21:22:51,989 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-22 21:22:51,989 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-22 21:22:51,990 INFO L87 Difference]: Start difference. First operand 626240 states and 797575 transitions. cyclomatic complexity: 171381 Second operand 3 states. [2018-11-22 21:22:54,632 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-22 21:22:54,633 INFO L93 Difference]: Finished difference Result 802558 states and 1020553 transitions. [2018-11-22 21:22:54,633 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-22 21:22:54,633 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 802558 states and 1020553 transitions. [2018-11-22 21:23:04,484 INFO L131 ngComponentsAnalysis]: Automaton has 47 accepting balls. 756262 [2018-11-22 21:23:06,100 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 802558 states to 802558 states and 1020553 transitions. [2018-11-22 21:23:06,100 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 802558 [2018-11-22 21:23:06,494 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 802558 [2018-11-22 21:23:06,494 INFO L73 IsDeterministic]: Start isDeterministic. Operand 802558 states and 1020553 transitions. [2018-11-22 21:23:06,787 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-22 21:23:06,787 INFO L705 BuchiCegarLoop]: Abstraction has 802558 states and 1020553 transitions. [2018-11-22 21:23:07,151 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 802558 states and 1020553 transitions. [2018-11-22 21:23:12,155 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 802558 to 789974. [2018-11-22 21:23:12,155 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 789974 states. [2018-11-22 21:23:13,357 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 789974 states to 789974 states and 1005065 transitions. [2018-11-22 21:23:13,357 INFO L728 BuchiCegarLoop]: Abstraction has 789974 states and 1005065 transitions. [2018-11-22 21:23:13,357 INFO L608 BuchiCegarLoop]: Abstraction has 789974 states and 1005065 transitions. [2018-11-22 21:23:13,357 INFO L442 BuchiCegarLoop]: ======== Iteration 38============ [2018-11-22 21:23:13,357 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 789974 states and 1005065 transitions. [2018-11-22 21:23:15,879 INFO L131 ngComponentsAnalysis]: Automaton has 47 accepting balls. 743678 [2018-11-22 21:23:15,879 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-22 21:23:15,879 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-22 21:23:15,880 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-22 21:23:15,880 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-22 21:23:15,880 INFO L794 eck$LassoCheckResult]: Stem: 7097113#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2; 7097005#L-1 havoc main_#res;havoc main_~__retres1~10;havoc main_~__retres1~10;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 7097006#L1225 havoc start_simulation_#t~ret20, start_simulation_#t~ret21, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 7097560#L564 assume 1 == ~m_i~0;~m_st~0 := 0; 7097039#L571-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 7096730#L576-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 7096731#L581-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 7097568#L586-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 7097270#L591-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 7096838#L596-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 7096839#L601-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 7097551#L606-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 7097427#L611-1 assume !(0 == ~M_E~0); 7097428#L828-1 assume !(0 == ~T1_E~0); 7097138#L833-1 assume !(0 == ~T2_E~0); 7096855#L838-1 assume !(0 == ~T3_E~0); 7096856#L843-1 assume !(0 == ~T4_E~0); 7097706#L848-1 assume !(0 == ~T5_E~0); 7097439#L853-1 assume !(0 == ~T6_E~0); 7097121#L858-1 assume !(0 == ~T7_E~0); 7096642#L863-1 assume !(0 == ~T8_E~0); 7096643#L868-1 assume !(0 == ~E_1~0); 7097382#L873-1 assume !(0 == ~E_2~0); 7097222#L878-1 assume !(0 == ~E_3~0); 7096975#L883-1 assume !(0 == ~E_4~0); 7096976#L888-1 assume !(0 == ~E_5~0); 7097516#L893-1 assume !(0 == ~E_6~0); 7097182#L898-1 assume !(0 == ~E_7~0); 7097102#L903-1 assume !(0 == ~E_8~0); 7096794#L908-1 havoc activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 7096795#L392 assume !(1 == ~m_pc~0); 7097160#L392-2 is_master_triggered_~__retres1~0 := 0; 7097163#L403 is_master_triggered_#res := is_master_triggered_~__retres1~0; 7097776#L404 activate_threads_#t~ret10 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 7097525#L1025 assume !(0 != activate_threads_~tmp~1); 7097526#L1025-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 7097369#L411 assume !(1 == ~t1_pc~0); 7097332#L411-2 is_transmit1_triggered_~__retres1~1 := 0; 7096708#L422 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 7096709#L423 activate_threads_#t~ret11 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 7096817#L1033 assume !(0 != activate_threads_~tmp___0~0); 7097047#L1033-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 7097048#L430 assume !(1 == ~t2_pc~0); 7097539#L430-2 is_transmit2_triggered_~__retres1~2 := 0; 7096890#L441 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 7096840#L442 activate_threads_#t~ret12 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 7096841#L1041 assume !(0 != activate_threads_~tmp___1~0); 7097810#L1041-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 7097811#L449 assume !(1 == ~t3_pc~0); 7097630#L449-2 is_transmit3_triggered_~__retres1~3 := 0; 7097820#L460 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 7097841#L461 activate_threads_#t~ret13 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 7097556#L1049 assume !(0 != activate_threads_~tmp___2~0); 7097557#L1049-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 7096753#L468 assume !(1 == ~t4_pc~0); 7096754#L468-2 is_transmit4_triggered_~__retres1~4 := 0; 7096761#L479 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 7097169#L480 activate_threads_#t~ret14 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 7097107#L1057 assume !(0 != activate_threads_~tmp___3~0); 7097108#L1057-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 7096960#L487 assume !(1 == ~t5_pc~0); 7096702#L487-2 is_transmit5_triggered_~__retres1~5 := 0; 7096962#L498 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 7097354#L499 activate_threads_#t~ret15 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 7097355#L1065 assume !(0 != activate_threads_~tmp___4~0); 7097827#L1065-2 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 7097120#L506 assume !(1 == ~t6_pc~0); 7097115#L506-2 is_transmit6_triggered_~__retres1~6 := 0; 7097116#L517 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 7097554#L518 activate_threads_#t~ret16 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 7097461#L1073 assume !(0 != activate_threads_~tmp___5~0); 7097462#L1073-2 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 7097273#L525 assume !(1 == ~t7_pc~0); 7097274#L525-2 is_transmit7_triggered_~__retres1~7 := 0; 7097277#L536 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 7097812#L537 activate_threads_#t~ret17 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 7096981#L1081 assume !(0 != activate_threads_~tmp___6~0); 7096982#L1081-2 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 7096983#L544 assume !(1 == ~t8_pc~0); 7097299#L544-2 is_transmit8_triggered_~__retres1~8 := 0; 7096636#L555 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 7096637#L556 activate_threads_#t~ret18 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 7096782#L1089 assume !(0 != activate_threads_~tmp___7~0); 7097608#L1089-2 assume !(1 == ~M_E~0); 7097132#L921-1 assume !(1 == ~T1_E~0); 7096851#L926-1 assume !(1 == ~T2_E~0); 7096852#L931-1 assume !(1 == ~T3_E~0); 7097703#L936-1 assume !(1 == ~T4_E~0); 7097451#L941-1 assume !(1 == ~T5_E~0); 7097129#L946-1 assume !(1 == ~T6_E~0); 7096651#L951-1 assume !(1 == ~T7_E~0); 7096652#L956-1 assume !(1 == ~T8_E~0); 7097559#L961-1 assume !(1 == ~E_1~0); 7097234#L966-1 assume !(1 == ~E_2~0); 7096987#L971-1 assume !(1 == ~E_3~0); 7096988#L976-1 assume !(1 == ~E_4~0); 7097510#L981-1 assume !(1 == ~E_5~0); 7097179#L986-1 assume !(1 == ~E_6~0); 7097096#L991-1 assume !(1 == ~E_7~0); 7096789#L996-1 assume !(1 == ~E_8~0); 7096790#L1262-1 assume !false; 7359869#L1263 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret0, eval_#t~nondet1, eval_~tmp_ndt_1~0, eval_#t~nondet2, eval_~tmp_ndt_2~0, eval_#t~nondet3, eval_~tmp_ndt_3~0, eval_#t~nondet4, eval_~tmp_ndt_4~0, eval_#t~nondet5, eval_~tmp_ndt_5~0, eval_#t~nondet6, eval_~tmp_ndt_6~0, eval_#t~nondet7, eval_~tmp_ndt_7~0, eval_#t~nondet8, eval_~tmp_ndt_8~0, eval_#t~nondet9, eval_~tmp_ndt_9~0, eval_~tmp~0;havoc eval_~tmp~0; 7359867#L803 [2018-11-22 21:23:15,880 INFO L796 eck$LassoCheckResult]: Loop: 7359867#L803 assume !false; 7359865#L682 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~9;havoc exists_runnable_thread_~__retres1~9; 7359861#L624 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9 := 1; 7359858#L671 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~9; 7359857#L672 eval_#t~ret0 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret0;havoc eval_#t~ret0; 7359854#L686 assume 0 != eval_~tmp~0; 7359851#L686-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0;eval_~tmp_ndt_1~0 := eval_#t~nondet1;havoc eval_#t~nondet1; 7359848#L694 assume !(0 != eval_~tmp_ndt_1~0); 7359849#L691 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0;eval_~tmp_ndt_2~0 := eval_#t~nondet2;havoc eval_#t~nondet2; 7360753#L708 assume !(0 != eval_~tmp_ndt_2~0); 7360788#L705 assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0;eval_~tmp_ndt_3~0 := eval_#t~nondet3;havoc eval_#t~nondet3; 7363637#L722 assume !(0 != eval_~tmp_ndt_3~0); 7360755#L719 assume 0 == ~t3_st~0;havoc eval_~tmp_ndt_4~0;eval_~tmp_ndt_4~0 := eval_#t~nondet4;havoc eval_#t~nondet4; 7360751#L736 assume !(0 != eval_~tmp_ndt_4~0); 7360749#L733 assume 0 == ~t4_st~0;havoc eval_~tmp_ndt_5~0;eval_~tmp_ndt_5~0 := eval_#t~nondet5;havoc eval_#t~nondet5; 7360745#L750 assume !(0 != eval_~tmp_ndt_5~0); 7359897#L747 assume 0 == ~t5_st~0;havoc eval_~tmp_ndt_6~0;eval_~tmp_ndt_6~0 := eval_#t~nondet6;havoc eval_#t~nondet6; 7359893#L764 assume !(0 != eval_~tmp_ndt_6~0); 7359892#L761 assume 0 == ~t6_st~0;havoc eval_~tmp_ndt_7~0;eval_~tmp_ndt_7~0 := eval_#t~nondet7;havoc eval_#t~nondet7; 7359890#L778 assume !(0 != eval_~tmp_ndt_7~0); 7359888#L775 assume 0 == ~t7_st~0;havoc eval_~tmp_ndt_8~0;eval_~tmp_ndt_8~0 := eval_#t~nondet8;havoc eval_#t~nondet8; 7359885#L792 assume !(0 != eval_~tmp_ndt_8~0); 7359872#L789 assume !(0 == ~t8_st~0); 7359867#L803 [2018-11-22 21:23:15,881 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-22 21:23:15,881 INFO L82 PathProgramCache]: Analyzing trace with hash 1464186463, now seen corresponding path program 7 times [2018-11-22 21:23:15,881 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-22 21:23:15,881 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-22 21:23:15,881 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-22 21:23:15,881 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-22 21:23:15,881 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-22 21:23:15,884 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-22 21:23:15,887 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-22 21:23:15,901 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-22 21:23:15,901 INFO L82 PathProgramCache]: Analyzing trace with hash 1983814677, now seen corresponding path program 1 times [2018-11-22 21:23:15,901 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-22 21:23:15,901 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-22 21:23:15,902 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-22 21:23:15,902 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-22 21:23:15,902 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-22 21:23:15,904 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-22 21:23:15,905 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-22 21:23:15,907 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-22 21:23:15,907 INFO L82 PathProgramCache]: Analyzing trace with hash 1702796279, now seen corresponding path program 1 times [2018-11-22 21:23:15,907 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-22 21:23:15,907 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-22 21:23:15,908 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-22 21:23:15,908 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-22 21:23:15,908 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-22 21:23:15,913 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-22 21:23:15,956 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-22 21:23:15,956 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-22 21:23:15,957 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2018-11-22 21:23:16,080 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-22 21:23:16,080 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-22 21:23:16,080 INFO L87 Difference]: Start difference. First operand 789974 states and 1005065 transitions. cyclomatic complexity: 215138 Second operand 3 states. [2018-11-22 21:23:20,541 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-22 21:23:20,541 INFO L93 Difference]: Finished difference Result 1526889 states and 1934437 transitions. [2018-11-22 21:23:20,541 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-22 21:23:20,541 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1526889 states and 1934437 transitions. [2018-11-22 21:23:35,203 INFO L131 ngComponentsAnalysis]: Automaton has 47 accepting balls. 1434409 [2018-11-22 21:23:37,772 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1526889 states to 1526889 states and 1934437 transitions. [2018-11-22 21:23:37,772 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1526889 [2018-11-22 21:23:38,075 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1526889 [2018-11-22 21:23:38,075 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1526889 states and 1934437 transitions. [2018-11-22 21:23:38,389 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-22 21:23:38,389 INFO L705 BuchiCegarLoop]: Abstraction has 1526889 states and 1934437 transitions. [2018-11-22 21:23:38,910 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1526889 states and 1934437 transitions. [2018-11-22 21:23:48,507 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1526889 to 1526889. [2018-11-22 21:23:48,507 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1526889 states. [2018-11-22 21:24:08,884 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1526889 states to 1526889 states and 1934437 transitions. [2018-11-22 21:24:08,884 INFO L728 BuchiCegarLoop]: Abstraction has 1526889 states and 1934437 transitions. [2018-11-22 21:24:08,884 INFO L608 BuchiCegarLoop]: Abstraction has 1526889 states and 1934437 transitions. [2018-11-22 21:24:08,884 INFO L442 BuchiCegarLoop]: ======== Iteration 39============ [2018-11-22 21:24:08,884 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1526889 states and 1934437 transitions. [2018-11-22 21:24:12,847 INFO L131 ngComponentsAnalysis]: Automaton has 47 accepting balls. 1434409 [2018-11-22 21:24:12,847 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-22 21:24:12,847 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-22 21:24:12,848 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-22 21:24:12,848 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-22 21:24:12,848 INFO L794 eck$LassoCheckResult]: Stem: 9413983#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2; 9413877#L-1 havoc main_#res;havoc main_~__retres1~10;havoc main_~__retres1~10;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 9413878#L1225 havoc start_simulation_#t~ret20, start_simulation_#t~ret21, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 9414459#L564 assume 1 == ~m_i~0;~m_st~0 := 0; 9413912#L571-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 9413600#L576-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 9413601#L581-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 9414464#L586-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 9414152#L591-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 9413704#L596-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 9413705#L601-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 9414450#L606-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 9414317#L611-1 assume !(0 == ~M_E~0); 9414318#L828-1 assume !(0 == ~T1_E~0); 9414008#L833-1 assume !(0 == ~T2_E~0); 9413722#L838-1 assume !(0 == ~T3_E~0); 9413723#L843-1 assume !(0 == ~T4_E~0); 9414585#L848-1 assume !(0 == ~T5_E~0); 9414328#L853-1 assume !(0 == ~T6_E~0); 9413989#L858-1 assume !(0 == ~T7_E~0); 9413513#L863-1 assume !(0 == ~T8_E~0); 9413514#L868-1 assume !(0 == ~E_1~0); 9414273#L873-1 assume !(0 == ~E_2~0); 9414094#L878-1 assume !(0 == ~E_3~0); 9413846#L883-1 assume !(0 == ~E_4~0); 9413847#L888-1 assume !(0 == ~E_5~0); 9414411#L893-1 assume !(0 == ~E_6~0); 9414050#L898-1 assume !(0 == ~E_7~0); 9413972#L903-1 assume !(0 == ~E_8~0); 9413663#L908-1 havoc activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 9413664#L392 assume !(1 == ~m_pc~0); 9414028#L392-2 is_master_triggered_~__retres1~0 := 0; 9414031#L403 is_master_triggered_#res := is_master_triggered_~__retres1~0; 9414641#L404 activate_threads_#t~ret10 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 9414423#L1025 assume !(0 != activate_threads_~tmp~1); 9414424#L1025-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 9414255#L411 assume !(1 == ~t1_pc~0); 9414219#L411-2 is_transmit1_triggered_~__retres1~1 := 0; 9413582#L422 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 9413583#L423 activate_threads_#t~ret11 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 9413685#L1033 assume !(0 != activate_threads_~tmp___0~0); 9413919#L1033-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 9413920#L430 assume !(1 == ~t2_pc~0); 9414438#L430-2 is_transmit2_triggered_~__retres1~2 := 0; 9413757#L441 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 9413706#L442 activate_threads_#t~ret12 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 9413707#L1041 assume !(0 != activate_threads_~tmp___1~0); 9414677#L1041-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 9414678#L449 assume !(1 == ~t3_pc~0); 9414519#L449-2 is_transmit3_triggered_~__retres1~3 := 0; 9414690#L460 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 9414723#L461 activate_threads_#t~ret13 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 9414455#L1049 assume !(0 != activate_threads_~tmp___2~0); 9414456#L1049-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 9413624#L468 assume !(1 == ~t4_pc~0); 9413625#L468-2 is_transmit4_triggered_~__retres1~4 := 0; 9413630#L479 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 9414039#L480 activate_threads_#t~ret14 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 9413976#L1057 assume !(0 != activate_threads_~tmp___3~0); 9413977#L1057-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 9413829#L487 assume !(1 == ~t5_pc~0); 9413573#L487-2 is_transmit5_triggered_~__retres1~5 := 0; 9413831#L498 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 9414240#L499 activate_threads_#t~ret15 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 9414241#L1065 assume !(0 != activate_threads_~tmp___4~0); 9414700#L1065-2 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 9413988#L506 assume !(1 == ~t6_pc~0); 9413985#L506-2 is_transmit6_triggered_~__retres1~6 := 0; 9413986#L517 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 9414453#L518 activate_threads_#t~ret16 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 9414348#L1073 assume !(0 != activate_threads_~tmp___5~0); 9414349#L1073-2 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 9414155#L525 assume !(1 == ~t7_pc~0); 9414156#L525-2 is_transmit7_triggered_~__retres1~7 := 0; 9414158#L536 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 9414679#L537 activate_threads_#t~ret17 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 9413853#L1081 assume !(0 != activate_threads_~tmp___6~0); 9413854#L1081-2 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 9413855#L544 assume !(1 == ~t8_pc~0); 9414185#L544-2 is_transmit8_triggered_~__retres1~8 := 0; 9413507#L555 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 9413508#L556 activate_threads_#t~ret18 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 9413651#L1089 assume !(0 != activate_threads_~tmp___7~0); 9414500#L1089-2 assume !(1 == ~M_E~0); 9414002#L921-1 assume !(1 == ~T1_E~0); 9413718#L926-1 assume !(1 == ~T2_E~0); 9413719#L931-1 assume !(1 == ~T3_E~0); 9414583#L936-1 assume !(1 == ~T4_E~0); 9414339#L941-1 assume !(1 == ~T5_E~0); 9413998#L946-1 assume !(1 == ~T6_E~0); 9413522#L951-1 assume !(1 == ~T7_E~0); 9413523#L956-1 assume !(1 == ~T8_E~0); 9414458#L961-1 assume !(1 == ~E_1~0); 9414105#L966-1 assume !(1 == ~E_2~0); 9413859#L971-1 assume !(1 == ~E_3~0); 9413860#L976-1 assume !(1 == ~E_4~0); 9414402#L981-1 assume !(1 == ~E_5~0); 9414048#L986-1 assume !(1 == ~E_6~0); 9413966#L991-1 assume !(1 == ~E_7~0); 9413657#L996-1 assume !(1 == ~E_8~0); 9413658#L1262-1 assume !false; 9760438#L1263 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret0, eval_#t~nondet1, eval_~tmp_ndt_1~0, eval_#t~nondet2, eval_~tmp_ndt_2~0, eval_#t~nondet3, eval_~tmp_ndt_3~0, eval_#t~nondet4, eval_~tmp_ndt_4~0, eval_#t~nondet5, eval_~tmp_ndt_5~0, eval_#t~nondet6, eval_~tmp_ndt_6~0, eval_#t~nondet7, eval_~tmp_ndt_7~0, eval_#t~nondet8, eval_~tmp_ndt_8~0, eval_#t~nondet9, eval_~tmp_ndt_9~0, eval_~tmp~0;havoc eval_~tmp~0; 9760436#L803 [2018-11-22 21:24:12,848 INFO L796 eck$LassoCheckResult]: Loop: 9760436#L803 assume !false; 9760433#L682 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~9;havoc exists_runnable_thread_~__retres1~9; 9760430#L624 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9 := 1; 9760428#L671 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~9; 9760426#L672 eval_#t~ret0 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret0;havoc eval_#t~ret0; 9760424#L686 assume 0 != eval_~tmp~0; 9760421#L686-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0;eval_~tmp_ndt_1~0 := eval_#t~nondet1;havoc eval_#t~nondet1; 9760418#L694 assume !(0 != eval_~tmp_ndt_1~0); 9760416#L691 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0;eval_~tmp_ndt_2~0 := eval_#t~nondet2;havoc eval_#t~nondet2; 9760413#L708 assume !(0 != eval_~tmp_ndt_2~0); 9760410#L705 assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0;eval_~tmp_ndt_3~0 := eval_#t~nondet3;havoc eval_#t~nondet3; 9760407#L722 assume !(0 != eval_~tmp_ndt_3~0); 9760405#L719 assume 0 == ~t3_st~0;havoc eval_~tmp_ndt_4~0;eval_~tmp_ndt_4~0 := eval_#t~nondet4;havoc eval_#t~nondet4; 9760353#L736 assume !(0 != eval_~tmp_ndt_4~0); 9760402#L733 assume 0 == ~t4_st~0;havoc eval_~tmp_ndt_5~0;eval_~tmp_ndt_5~0 := eval_#t~nondet5;havoc eval_#t~nondet5; 9760461#L750 assume !(0 != eval_~tmp_ndt_5~0); 9760459#L747 assume 0 == ~t5_st~0;havoc eval_~tmp_ndt_6~0;eval_~tmp_ndt_6~0 := eval_#t~nondet6;havoc eval_#t~nondet6; 9760456#L764 assume !(0 != eval_~tmp_ndt_6~0); 9760454#L761 assume 0 == ~t6_st~0;havoc eval_~tmp_ndt_7~0;eval_~tmp_ndt_7~0 := eval_#t~nondet7;havoc eval_#t~nondet7; 9760451#L778 assume !(0 != eval_~tmp_ndt_7~0); 9760449#L775 assume 0 == ~t7_st~0;havoc eval_~tmp_ndt_8~0;eval_~tmp_ndt_8~0 := eval_#t~nondet8;havoc eval_#t~nondet8; 9760444#L792 assume !(0 != eval_~tmp_ndt_8~0); 9760442#L789 assume 0 == ~t8_st~0;havoc eval_~tmp_ndt_9~0;eval_~tmp_ndt_9~0 := eval_#t~nondet9;havoc eval_#t~nondet9; 9760439#L806 assume !(0 != eval_~tmp_ndt_9~0); 9760436#L803 [2018-11-22 21:24:12,848 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-22 21:24:12,848 INFO L82 PathProgramCache]: Analyzing trace with hash 1464186463, now seen corresponding path program 8 times [2018-11-22 21:24:12,848 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-22 21:24:12,848 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-22 21:24:12,849 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-22 21:24:12,849 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-22 21:24:12,849 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-22 21:24:12,852 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-22 21:24:12,855 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-22 21:24:12,869 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-22 21:24:12,869 INFO L82 PathProgramCache]: Analyzing trace with hash 1368714281, now seen corresponding path program 1 times [2018-11-22 21:24:12,869 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-22 21:24:12,869 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-22 21:24:12,869 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-22 21:24:12,870 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-22 21:24:12,870 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-22 21:24:12,871 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-22 21:24:12,872 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-22 21:24:12,873 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-22 21:24:12,873 INFO L82 PathProgramCache]: Analyzing trace with hash 1247078535, now seen corresponding path program 1 times [2018-11-22 21:24:12,873 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-22 21:24:12,874 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-22 21:24:12,874 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-22 21:24:12,874 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-22 21:24:12,874 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-22 21:24:12,878 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-22 21:24:12,884 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-22 21:24:13,645 WARN L180 SmtUtils]: Spent 607.00 ms on a formula simplification. DAG size of input: 281 DAG size of output: 186 [2018-11-22 21:24:13,794 WARN L180 SmtUtils]: Spent 141.00 ms on a formula simplification that was a NOOP. DAG size: 148 ----- class de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder.RCFGBacktranslator [?] ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2; [?] havoc main_#res;havoc main_~__retres1~10;havoc main_~__retres1~10;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; [?] havoc start_simulation_#t~ret20, start_simulation_#t~ret21, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; [?] assume 1 == ~m_i~0;~m_st~0 := 0; [?] assume 1 == ~t1_i~0;~t1_st~0 := 0; [?] assume 1 == ~t2_i~0;~t2_st~0 := 0; [?] assume 1 == ~t3_i~0;~t3_st~0 := 0; [?] assume 1 == ~t4_i~0;~t4_st~0 := 0; [?] assume 1 == ~t5_i~0;~t5_st~0 := 0; [?] assume 1 == ~t6_i~0;~t6_st~0 := 0; [?] assume 1 == ~t7_i~0;~t7_st~0 := 0; [?] assume 1 == ~t8_i~0;~t8_st~0 := 0; [?] assume !(0 == ~M_E~0); [?] assume !(0 == ~T1_E~0); [?] assume !(0 == ~T2_E~0); [?] assume !(0 == ~T3_E~0); [?] assume !(0 == ~T4_E~0); [?] assume !(0 == ~T5_E~0); [?] assume !(0 == ~T6_E~0); [?] assume !(0 == ~T7_E~0); [?] assume !(0 == ~T8_E~0); [?] assume !(0 == ~E_1~0); [?] assume !(0 == ~E_2~0); [?] assume !(0 == ~E_3~0); [?] assume !(0 == ~E_4~0); [?] assume !(0 == ~E_5~0); [?] assume !(0 == ~E_6~0); [?] assume !(0 == ~E_7~0); [?] assume !(0 == ~E_8~0); [?] havoc activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; [?] assume !(1 == ~m_pc~0); [?] is_master_triggered_~__retres1~0 := 0; [?] is_master_triggered_#res := is_master_triggered_~__retres1~0; [?] activate_threads_#t~ret10 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; [?] assume !(0 != activate_threads_~tmp~1); [?] havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; [?] assume !(1 == ~t1_pc~0); [?] is_transmit1_triggered_~__retres1~1 := 0; [?] is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; [?] activate_threads_#t~ret11 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; [?] assume !(0 != activate_threads_~tmp___0~0); [?] havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; [?] assume !(1 == ~t2_pc~0); [?] is_transmit2_triggered_~__retres1~2 := 0; [?] is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; [?] activate_threads_#t~ret12 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; [?] assume !(0 != activate_threads_~tmp___1~0); [?] havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; [?] assume !(1 == ~t3_pc~0); [?] is_transmit3_triggered_~__retres1~3 := 0; [?] is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; [?] activate_threads_#t~ret13 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; [?] assume !(0 != activate_threads_~tmp___2~0); [?] havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; [?] assume !(1 == ~t4_pc~0); [?] is_transmit4_triggered_~__retres1~4 := 0; [?] is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; [?] activate_threads_#t~ret14 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; [?] assume !(0 != activate_threads_~tmp___3~0); [?] havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; [?] assume !(1 == ~t5_pc~0); [?] is_transmit5_triggered_~__retres1~5 := 0; [?] is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; [?] activate_threads_#t~ret15 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; [?] assume !(0 != activate_threads_~tmp___4~0); [?] havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; [?] assume !(1 == ~t6_pc~0); [?] is_transmit6_triggered_~__retres1~6 := 0; [?] is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; [?] activate_threads_#t~ret16 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; [?] assume !(0 != activate_threads_~tmp___5~0); [?] havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; [?] assume !(1 == ~t7_pc~0); [?] is_transmit7_triggered_~__retres1~7 := 0; [?] is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; [?] activate_threads_#t~ret17 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; [?] assume !(0 != activate_threads_~tmp___6~0); [?] havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; [?] assume !(1 == ~t8_pc~0); [?] is_transmit8_triggered_~__retres1~8 := 0; [?] is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; [?] activate_threads_#t~ret18 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; [?] assume !(0 != activate_threads_~tmp___7~0); [?] assume !(1 == ~M_E~0); [?] assume !(1 == ~T1_E~0); [?] assume !(1 == ~T2_E~0); [?] assume !(1 == ~T3_E~0); [?] assume !(1 == ~T4_E~0); [?] assume !(1 == ~T5_E~0); [?] assume !(1 == ~T6_E~0); [?] assume !(1 == ~T7_E~0); [?] assume !(1 == ~T8_E~0); [?] assume !(1 == ~E_1~0); [?] assume !(1 == ~E_2~0); [?] assume !(1 == ~E_3~0); [?] assume !(1 == ~E_4~0); [?] assume !(1 == ~E_5~0); [?] assume !(1 == ~E_6~0); [?] assume !(1 == ~E_7~0); [?] assume !(1 == ~E_8~0); [?] assume !false; [?] start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret0, eval_#t~nondet1, eval_~tmp_ndt_1~0, eval_#t~nondet2, eval_~tmp_ndt_2~0, eval_#t~nondet3, eval_~tmp_ndt_3~0, eval_#t~nondet4, eval_~tmp_ndt_4~0, eval_#t~nondet5, eval_~tmp_ndt_5~0, eval_#t~nondet6, eval_~tmp_ndt_6~0, eval_#t~nondet7, eval_~tmp_ndt_7~0, eval_#t~nondet8, eval_~tmp_ndt_8~0, eval_#t~nondet9, eval_~tmp_ndt_9~0, eval_~tmp~0;havoc eval_~tmp~0; [L15] ~m_pc~0 := 0; [L16] ~t1_pc~0 := 0; [L17] ~t2_pc~0 := 0; [L18] ~t3_pc~0 := 0; [L19] ~t4_pc~0 := 0; [L20] ~t5_pc~0 := 0; [L21] ~t6_pc~0 := 0; [L22] ~t7_pc~0 := 0; [L23] ~t8_pc~0 := 0; [L24] ~m_st~0 := 0; [L25] ~t1_st~0 := 0; [L26] ~t2_st~0 := 0; [L27] ~t3_st~0 := 0; [L28] ~t4_st~0 := 0; [L29] ~t5_st~0 := 0; [L30] ~t6_st~0 := 0; [L31] ~t7_st~0 := 0; [L32] ~t8_st~0 := 0; [L33] ~m_i~0 := 0; [L34] ~t1_i~0 := 0; [L35] ~t2_i~0 := 0; [L36] ~t3_i~0 := 0; [L37] ~t4_i~0 := 0; [L38] ~t5_i~0 := 0; [L39] ~t6_i~0 := 0; [L40] ~t7_i~0 := 0; [L41] ~t8_i~0 := 0; [L42] ~M_E~0 := 2; [L43] ~T1_E~0 := 2; [L44] ~T2_E~0 := 2; [L45] ~T3_E~0 := 2; [L46] ~T4_E~0 := 2; [L47] ~T5_E~0 := 2; [L48] ~T6_E~0 := 2; [L49] ~T7_E~0 := 2; [L50] ~T8_E~0 := 2; [L51] ~E_1~0 := 2; [L52] ~E_2~0 := 2; [L53] ~E_3~0 := 2; [L54] ~E_4~0 := 2; [L55] ~E_5~0 := 2; [L56] ~E_6~0 := 2; [L57] ~E_7~0 := 2; [L58] ~E_8~0 := 2; [?] havoc main_#res; [?] havoc main_~__retres1~10; [L1307] havoc main_~__retres1~10; [L1215] ~m_i~0 := 1; [L1216] ~t1_i~0 := 1; [L1217] ~t2_i~0 := 1; [L1218] ~t3_i~0 := 1; [L1219] ~t4_i~0 := 1; [L1220] ~t5_i~0 := 1; [L1221] ~t6_i~0 := 1; [L1222] ~t7_i~0 := 1; [L1223] ~t8_i~0 := 1; [L1312] havoc start_simulation_#t~ret20, start_simulation_#t~ret21, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1; [L1248] havoc start_simulation_~kernel_st~0; [L1249] havoc start_simulation_~tmp~3; [L1250] havoc start_simulation_~tmp___0~1; [L1254] start_simulation_~kernel_st~0 := 0; [L571-L575] assume 1 == ~m_i~0; [L572] ~m_st~0 := 0; [L576-L580] assume 1 == ~t1_i~0; [L577] ~t1_st~0 := 0; [L581-L585] assume 1 == ~t2_i~0; [L582] ~t2_st~0 := 0; [L586-L590] assume 1 == ~t3_i~0; [L587] ~t3_st~0 := 0; [L591-L595] assume 1 == ~t4_i~0; [L592] ~t4_st~0 := 0; [L596-L600] assume 1 == ~t5_i~0; [L597] ~t5_st~0 := 0; [L601-L605] assume 1 == ~t6_i~0; [L602] ~t6_st~0 := 0; [L606-L610] assume 1 == ~t7_i~0; [L607] ~t7_st~0 := 0; [L611-L615] assume 1 == ~t8_i~0; [L612] ~t8_st~0 := 0; [L828-L832] assume !(0 == ~M_E~0); [L833-L837] assume !(0 == ~T1_E~0); [L838-L842] assume !(0 == ~T2_E~0); [L843-L847] assume !(0 == ~T3_E~0); [L848-L852] assume !(0 == ~T4_E~0); [L853-L857] assume !(0 == ~T5_E~0); [L858-L862] assume !(0 == ~T6_E~0); [L863-L867] assume !(0 == ~T7_E~0); [L868-L872] assume !(0 == ~T8_E~0); [L873-L877] assume !(0 == ~E_1~0); [L878-L882] assume !(0 == ~E_2~0); [L883-L887] assume !(0 == ~E_3~0); [L888-L892] assume !(0 == ~E_4~0); [L893-L897] assume !(0 == ~E_5~0); [L898-L902] assume !(0 == ~E_6~0); [L903-L907] assume !(0 == ~E_7~0); [L908-L912] assume !(0 == ~E_8~0); [L1258] havoc activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0; [L1011] havoc activate_threads_~tmp~1; [L1012] havoc activate_threads_~tmp___0~0; [L1013] havoc activate_threads_~tmp___1~0; [L1014] havoc activate_threads_~tmp___2~0; [L1015] havoc activate_threads_~tmp___3~0; [L1016] havoc activate_threads_~tmp___4~0; [L1017] havoc activate_threads_~tmp___5~0; [L1018] havoc activate_threads_~tmp___6~0; [L1019] havoc activate_threads_~tmp___7~0; [L1023] havoc is_master_triggered_#res; [L1023] havoc is_master_triggered_~__retres1~0; [L389] havoc is_master_triggered_~__retres1~0; [L392-L401] assume !(1 == ~m_pc~0); [L402] is_master_triggered_~__retres1~0 := 0; [L404] is_master_triggered_#res := is_master_triggered_~__retres1~0; [L1023] activate_threads_#t~ret10 := is_master_triggered_#res; [L1023] activate_threads_~tmp~1 := activate_threads_#t~ret10; [L1023] havoc activate_threads_#t~ret10; [L1025-L1029] assume !(0 != activate_threads_~tmp~1); [L1031] havoc is_transmit1_triggered_#res; [L1031] havoc is_transmit1_triggered_~__retres1~1; [L408] havoc is_transmit1_triggered_~__retres1~1; [L411-L420] assume !(1 == ~t1_pc~0); [L421] is_transmit1_triggered_~__retres1~1 := 0; [L423] is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; [L1031] activate_threads_#t~ret11 := is_transmit1_triggered_#res; [L1031] activate_threads_~tmp___0~0 := activate_threads_#t~ret11; [L1031] havoc activate_threads_#t~ret11; [L1033-L1037] assume !(0 != activate_threads_~tmp___0~0); [L1039] havoc is_transmit2_triggered_#res; [L1039] havoc is_transmit2_triggered_~__retres1~2; [L427] havoc is_transmit2_triggered_~__retres1~2; [L430-L439] assume !(1 == ~t2_pc~0); [L440] is_transmit2_triggered_~__retres1~2 := 0; [L442] is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; [L1039] activate_threads_#t~ret12 := is_transmit2_triggered_#res; [L1039] activate_threads_~tmp___1~0 := activate_threads_#t~ret12; [L1039] havoc activate_threads_#t~ret12; [L1041-L1045] assume !(0 != activate_threads_~tmp___1~0); [L1047] havoc is_transmit3_triggered_#res; [L1047] havoc is_transmit3_triggered_~__retres1~3; [L446] havoc is_transmit3_triggered_~__retres1~3; [L449-L458] assume !(1 == ~t3_pc~0); [L459] is_transmit3_triggered_~__retres1~3 := 0; [L461] is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; [L1047] activate_threads_#t~ret13 := is_transmit3_triggered_#res; [L1047] activate_threads_~tmp___2~0 := activate_threads_#t~ret13; [L1047] havoc activate_threads_#t~ret13; [L1049-L1053] assume !(0 != activate_threads_~tmp___2~0); [L1055] havoc is_transmit4_triggered_#res; [L1055] havoc is_transmit4_triggered_~__retres1~4; [L465] havoc is_transmit4_triggered_~__retres1~4; [L468-L477] assume !(1 == ~t4_pc~0); [L478] is_transmit4_triggered_~__retres1~4 := 0; [L480] is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; [L1055] activate_threads_#t~ret14 := is_transmit4_triggered_#res; [L1055] activate_threads_~tmp___3~0 := activate_threads_#t~ret14; [L1055] havoc activate_threads_#t~ret14; [L1057-L1061] assume !(0 != activate_threads_~tmp___3~0); [L1063] havoc is_transmit5_triggered_#res; [L1063] havoc is_transmit5_triggered_~__retres1~5; [L484] havoc is_transmit5_triggered_~__retres1~5; [L487-L496] assume !(1 == ~t5_pc~0); [L497] is_transmit5_triggered_~__retres1~5 := 0; [L499] is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; [L1063] activate_threads_#t~ret15 := is_transmit5_triggered_#res; [L1063] activate_threads_~tmp___4~0 := activate_threads_#t~ret15; [L1063] havoc activate_threads_#t~ret15; [L1065-L1069] assume !(0 != activate_threads_~tmp___4~0); [L1071] havoc is_transmit6_triggered_#res; [L1071] havoc is_transmit6_triggered_~__retres1~6; [L503] havoc is_transmit6_triggered_~__retres1~6; [L506-L515] assume !(1 == ~t6_pc~0); [L516] is_transmit6_triggered_~__retres1~6 := 0; [L518] is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; [L1071] activate_threads_#t~ret16 := is_transmit6_triggered_#res; [L1071] activate_threads_~tmp___5~0 := activate_threads_#t~ret16; [L1071] havoc activate_threads_#t~ret16; [L1073-L1077] assume !(0 != activate_threads_~tmp___5~0); [L1079] havoc is_transmit7_triggered_#res; [L1079] havoc is_transmit7_triggered_~__retres1~7; [L522] havoc is_transmit7_triggered_~__retres1~7; [L525-L534] assume !(1 == ~t7_pc~0); [L535] is_transmit7_triggered_~__retres1~7 := 0; [L537] is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; [L1079] activate_threads_#t~ret17 := is_transmit7_triggered_#res; [L1079] activate_threads_~tmp___6~0 := activate_threads_#t~ret17; [L1079] havoc activate_threads_#t~ret17; [L1081-L1085] assume !(0 != activate_threads_~tmp___6~0); [L1087] havoc is_transmit8_triggered_#res; [L1087] havoc is_transmit8_triggered_~__retres1~8; [L541] havoc is_transmit8_triggered_~__retres1~8; [L544-L553] assume !(1 == ~t8_pc~0); [L554] is_transmit8_triggered_~__retres1~8 := 0; [L556] is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; [L1087] activate_threads_#t~ret18 := is_transmit8_triggered_#res; [L1087] activate_threads_~tmp___7~0 := activate_threads_#t~ret18; [L1087] havoc activate_threads_#t~ret18; [L1089-L1093] assume !(0 != activate_threads_~tmp___7~0); [L921-L925] assume !(1 == ~M_E~0); [L926-L930] assume !(1 == ~T1_E~0); [L931-L935] assume !(1 == ~T2_E~0); [L936-L940] assume !(1 == ~T3_E~0); [L941-L945] assume !(1 == ~T4_E~0); [L946-L950] assume !(1 == ~T5_E~0); [L951-L955] assume !(1 == ~T6_E~0); [L956-L960] assume !(1 == ~T7_E~0); [L961-L965] assume !(1 == ~T8_E~0); [L966-L970] assume !(1 == ~E_1~0); [L971-L975] assume !(1 == ~E_2~0); [L976-L980] assume !(1 == ~E_3~0); [L981-L985] assume !(1 == ~E_4~0); [L986-L990] assume !(1 == ~E_5~0); [L991-L995] assume !(1 == ~E_6~0); [L996-L1000] assume !(1 == ~E_7~0); [L1001-L1005] assume !(1 == ~E_8~0); [L1262-L1299] assume !false; [L1265] start_simulation_~kernel_st~0 := 1; [L1266] havoc eval_#t~ret0, eval_#t~nondet1, eval_~tmp_ndt_1~0, eval_#t~nondet2, eval_~tmp_ndt_2~0, eval_#t~nondet3, eval_~tmp_ndt_3~0, eval_#t~nondet4, eval_~tmp_ndt_4~0, eval_#t~nondet5, eval_~tmp_ndt_5~0, eval_#t~nondet6, eval_~tmp_ndt_6~0, eval_#t~nondet7, eval_~tmp_ndt_7~0, eval_#t~nondet8, eval_~tmp_ndt_8~0, eval_#t~nondet9, eval_~tmp_ndt_9~0, eval_~tmp~0; [L677] havoc eval_~tmp~0; ----- ----- class de.uni_freiburg.informatik.ultimate.boogie.preprocessor.BoogiePreprocessorBacktranslator [L15] ~m_pc~0 := 0; [L16] ~t1_pc~0 := 0; [L17] ~t2_pc~0 := 0; [L18] ~t3_pc~0 := 0; [L19] ~t4_pc~0 := 0; [L20] ~t5_pc~0 := 0; [L21] ~t6_pc~0 := 0; [L22] ~t7_pc~0 := 0; [L23] ~t8_pc~0 := 0; [L24] ~m_st~0 := 0; [L25] ~t1_st~0 := 0; [L26] ~t2_st~0 := 0; [L27] ~t3_st~0 := 0; [L28] ~t4_st~0 := 0; [L29] ~t5_st~0 := 0; [L30] ~t6_st~0 := 0; [L31] ~t7_st~0 := 0; [L32] ~t8_st~0 := 0; [L33] ~m_i~0 := 0; [L34] ~t1_i~0 := 0; [L35] ~t2_i~0 := 0; [L36] ~t3_i~0 := 0; [L37] ~t4_i~0 := 0; [L38] ~t5_i~0 := 0; [L39] ~t6_i~0 := 0; [L40] ~t7_i~0 := 0; [L41] ~t8_i~0 := 0; [L42] ~M_E~0 := 2; [L43] ~T1_E~0 := 2; [L44] ~T2_E~0 := 2; [L45] ~T3_E~0 := 2; [L46] ~T4_E~0 := 2; [L47] ~T5_E~0 := 2; [L48] ~T6_E~0 := 2; [L49] ~T7_E~0 := 2; [L50] ~T8_E~0 := 2; [L51] ~E_1~0 := 2; [L52] ~E_2~0 := 2; [L53] ~E_3~0 := 2; [L54] ~E_4~0 := 2; [L55] ~E_5~0 := 2; [L56] ~E_6~0 := 2; [L57] ~E_7~0 := 2; [L58] ~E_8~0 := 2; [?] havoc main_#res; [?] havoc main_~__retres1~10; [L1307] havoc main_~__retres1~10; [L1215] ~m_i~0 := 1; [L1216] ~t1_i~0 := 1; [L1217] ~t2_i~0 := 1; [L1218] ~t3_i~0 := 1; [L1219] ~t4_i~0 := 1; [L1220] ~t5_i~0 := 1; [L1221] ~t6_i~0 := 1; [L1222] ~t7_i~0 := 1; [L1223] ~t8_i~0 := 1; [L1312] havoc start_simulation_#t~ret20, start_simulation_#t~ret21, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1; [L1248] havoc start_simulation_~kernel_st~0; [L1249] havoc start_simulation_~tmp~3; [L1250] havoc start_simulation_~tmp___0~1; [L1254] start_simulation_~kernel_st~0 := 0; [L571-L575] assume 1 == ~m_i~0; [L572] ~m_st~0 := 0; [L576-L580] assume 1 == ~t1_i~0; [L577] ~t1_st~0 := 0; [L581-L585] assume 1 == ~t2_i~0; [L582] ~t2_st~0 := 0; [L586-L590] assume 1 == ~t3_i~0; [L587] ~t3_st~0 := 0; [L591-L595] assume 1 == ~t4_i~0; [L592] ~t4_st~0 := 0; [L596-L600] assume 1 == ~t5_i~0; [L597] ~t5_st~0 := 0; [L601-L605] assume 1 == ~t6_i~0; [L602] ~t6_st~0 := 0; [L606-L610] assume 1 == ~t7_i~0; [L607] ~t7_st~0 := 0; [L611-L615] assume 1 == ~t8_i~0; [L612] ~t8_st~0 := 0; [L828-L832] assume !(0 == ~M_E~0); [L833-L837] assume !(0 == ~T1_E~0); [L838-L842] assume !(0 == ~T2_E~0); [L843-L847] assume !(0 == ~T3_E~0); [L848-L852] assume !(0 == ~T4_E~0); [L853-L857] assume !(0 == ~T5_E~0); [L858-L862] assume !(0 == ~T6_E~0); [L863-L867] assume !(0 == ~T7_E~0); [L868-L872] assume !(0 == ~T8_E~0); [L873-L877] assume !(0 == ~E_1~0); [L878-L882] assume !(0 == ~E_2~0); [L883-L887] assume !(0 == ~E_3~0); [L888-L892] assume !(0 == ~E_4~0); [L893-L897] assume !(0 == ~E_5~0); [L898-L902] assume !(0 == ~E_6~0); [L903-L907] assume !(0 == ~E_7~0); [L908-L912] assume !(0 == ~E_8~0); [L1258] havoc activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0; [L1011] havoc activate_threads_~tmp~1; [L1012] havoc activate_threads_~tmp___0~0; [L1013] havoc activate_threads_~tmp___1~0; [L1014] havoc activate_threads_~tmp___2~0; [L1015] havoc activate_threads_~tmp___3~0; [L1016] havoc activate_threads_~tmp___4~0; [L1017] havoc activate_threads_~tmp___5~0; [L1018] havoc activate_threads_~tmp___6~0; [L1019] havoc activate_threads_~tmp___7~0; [L1023] havoc is_master_triggered_#res; [L1023] havoc is_master_triggered_~__retres1~0; [L389] havoc is_master_triggered_~__retres1~0; [L392-L401] assume !(1 == ~m_pc~0); [L402] is_master_triggered_~__retres1~0 := 0; [L404] is_master_triggered_#res := is_master_triggered_~__retres1~0; [L1023] activate_threads_#t~ret10 := is_master_triggered_#res; [L1023] activate_threads_~tmp~1 := activate_threads_#t~ret10; [L1023] havoc activate_threads_#t~ret10; [L1025-L1029] assume !(0 != activate_threads_~tmp~1); [L1031] havoc is_transmit1_triggered_#res; [L1031] havoc is_transmit1_triggered_~__retres1~1; [L408] havoc is_transmit1_triggered_~__retres1~1; [L411-L420] assume !(1 == ~t1_pc~0); [L421] is_transmit1_triggered_~__retres1~1 := 0; [L423] is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; [L1031] activate_threads_#t~ret11 := is_transmit1_triggered_#res; [L1031] activate_threads_~tmp___0~0 := activate_threads_#t~ret11; [L1031] havoc activate_threads_#t~ret11; [L1033-L1037] assume !(0 != activate_threads_~tmp___0~0); [L1039] havoc is_transmit2_triggered_#res; [L1039] havoc is_transmit2_triggered_~__retres1~2; [L427] havoc is_transmit2_triggered_~__retres1~2; [L430-L439] assume !(1 == ~t2_pc~0); [L440] is_transmit2_triggered_~__retres1~2 := 0; [L442] is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; [L1039] activate_threads_#t~ret12 := is_transmit2_triggered_#res; [L1039] activate_threads_~tmp___1~0 := activate_threads_#t~ret12; [L1039] havoc activate_threads_#t~ret12; [L1041-L1045] assume !(0 != activate_threads_~tmp___1~0); [L1047] havoc is_transmit3_triggered_#res; [L1047] havoc is_transmit3_triggered_~__retres1~3; [L446] havoc is_transmit3_triggered_~__retres1~3; [L449-L458] assume !(1 == ~t3_pc~0); [L459] is_transmit3_triggered_~__retres1~3 := 0; [L461] is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; [L1047] activate_threads_#t~ret13 := is_transmit3_triggered_#res; [L1047] activate_threads_~tmp___2~0 := activate_threads_#t~ret13; [L1047] havoc activate_threads_#t~ret13; [L1049-L1053] assume !(0 != activate_threads_~tmp___2~0); [L1055] havoc is_transmit4_triggered_#res; [L1055] havoc is_transmit4_triggered_~__retres1~4; [L465] havoc is_transmit4_triggered_~__retres1~4; [L468-L477] assume !(1 == ~t4_pc~0); [L478] is_transmit4_triggered_~__retres1~4 := 0; [L480] is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; [L1055] activate_threads_#t~ret14 := is_transmit4_triggered_#res; [L1055] activate_threads_~tmp___3~0 := activate_threads_#t~ret14; [L1055] havoc activate_threads_#t~ret14; [L1057-L1061] assume !(0 != activate_threads_~tmp___3~0); [L1063] havoc is_transmit5_triggered_#res; [L1063] havoc is_transmit5_triggered_~__retres1~5; [L484] havoc is_transmit5_triggered_~__retres1~5; [L487-L496] assume !(1 == ~t5_pc~0); [L497] is_transmit5_triggered_~__retres1~5 := 0; [L499] is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; [L1063] activate_threads_#t~ret15 := is_transmit5_triggered_#res; [L1063] activate_threads_~tmp___4~0 := activate_threads_#t~ret15; [L1063] havoc activate_threads_#t~ret15; [L1065-L1069] assume !(0 != activate_threads_~tmp___4~0); [L1071] havoc is_transmit6_triggered_#res; [L1071] havoc is_transmit6_triggered_~__retres1~6; [L503] havoc is_transmit6_triggered_~__retres1~6; [L506-L515] assume !(1 == ~t6_pc~0); [L516] is_transmit6_triggered_~__retres1~6 := 0; [L518] is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; [L1071] activate_threads_#t~ret16 := is_transmit6_triggered_#res; [L1071] activate_threads_~tmp___5~0 := activate_threads_#t~ret16; [L1071] havoc activate_threads_#t~ret16; [L1073-L1077] assume !(0 != activate_threads_~tmp___5~0); [L1079] havoc is_transmit7_triggered_#res; [L1079] havoc is_transmit7_triggered_~__retres1~7; [L522] havoc is_transmit7_triggered_~__retres1~7; [L525-L534] assume !(1 == ~t7_pc~0); [L535] is_transmit7_triggered_~__retres1~7 := 0; [L537] is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; [L1079] activate_threads_#t~ret17 := is_transmit7_triggered_#res; [L1079] activate_threads_~tmp___6~0 := activate_threads_#t~ret17; [L1079] havoc activate_threads_#t~ret17; [L1081-L1085] assume !(0 != activate_threads_~tmp___6~0); [L1087] havoc is_transmit8_triggered_#res; [L1087] havoc is_transmit8_triggered_~__retres1~8; [L541] havoc is_transmit8_triggered_~__retres1~8; [L544-L553] assume !(1 == ~t8_pc~0); [L554] is_transmit8_triggered_~__retres1~8 := 0; [L556] is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; [L1087] activate_threads_#t~ret18 := is_transmit8_triggered_#res; [L1087] activate_threads_~tmp___7~0 := activate_threads_#t~ret18; [L1087] havoc activate_threads_#t~ret18; [L1089-L1093] assume !(0 != activate_threads_~tmp___7~0); [L921-L925] assume !(1 == ~M_E~0); [L926-L930] assume !(1 == ~T1_E~0); [L931-L935] assume !(1 == ~T2_E~0); [L936-L940] assume !(1 == ~T3_E~0); [L941-L945] assume !(1 == ~T4_E~0); [L946-L950] assume !(1 == ~T5_E~0); [L951-L955] assume !(1 == ~T6_E~0); [L956-L960] assume !(1 == ~T7_E~0); [L961-L965] assume !(1 == ~T8_E~0); [L966-L970] assume !(1 == ~E_1~0); [L971-L975] assume !(1 == ~E_2~0); [L976-L980] assume !(1 == ~E_3~0); [L981-L985] assume !(1 == ~E_4~0); [L986-L990] assume !(1 == ~E_5~0); [L991-L995] assume !(1 == ~E_6~0); [L996-L1000] assume !(1 == ~E_7~0); [L1001-L1005] assume !(1 == ~E_8~0); [L1262-L1299] assume !false; [L1265] start_simulation_~kernel_st~0 := 1; [L1266] havoc eval_#t~ret0, eval_#t~nondet1, eval_~tmp_ndt_1~0, eval_#t~nondet2, eval_~tmp_ndt_2~0, eval_#t~nondet3, eval_~tmp_ndt_3~0, eval_#t~nondet4, eval_~tmp_ndt_4~0, eval_#t~nondet5, eval_~tmp_ndt_5~0, eval_#t~nondet6, eval_~tmp_ndt_6~0, eval_#t~nondet7, eval_~tmp_ndt_7~0, eval_#t~nondet8, eval_~tmp_ndt_8~0, eval_#t~nondet9, eval_~tmp_ndt_9~0, eval_~tmp~0; [L677] havoc eval_~tmp~0; [L15] ~m_pc~0 := 0; [L16] ~t1_pc~0 := 0; [L17] ~t2_pc~0 := 0; [L18] ~t3_pc~0 := 0; [L19] ~t4_pc~0 := 0; [L20] ~t5_pc~0 := 0; [L21] ~t6_pc~0 := 0; [L22] ~t7_pc~0 := 0; [L23] ~t8_pc~0 := 0; [L24] ~m_st~0 := 0; [L25] ~t1_st~0 := 0; [L26] ~t2_st~0 := 0; [L27] ~t3_st~0 := 0; [L28] ~t4_st~0 := 0; [L29] ~t5_st~0 := 0; [L30] ~t6_st~0 := 0; [L31] ~t7_st~0 := 0; [L32] ~t8_st~0 := 0; [L33] ~m_i~0 := 0; [L34] ~t1_i~0 := 0; [L35] ~t2_i~0 := 0; [L36] ~t3_i~0 := 0; [L37] ~t4_i~0 := 0; [L38] ~t5_i~0 := 0; [L39] ~t6_i~0 := 0; [L40] ~t7_i~0 := 0; [L41] ~t8_i~0 := 0; [L42] ~M_E~0 := 2; [L43] ~T1_E~0 := 2; [L44] ~T2_E~0 := 2; [L45] ~T3_E~0 := 2; [L46] ~T4_E~0 := 2; [L47] ~T5_E~0 := 2; [L48] ~T6_E~0 := 2; [L49] ~T7_E~0 := 2; [L50] ~T8_E~0 := 2; [L51] ~E_1~0 := 2; [L52] ~E_2~0 := 2; [L53] ~E_3~0 := 2; [L54] ~E_4~0 := 2; [L55] ~E_5~0 := 2; [L56] ~E_6~0 := 2; [L57] ~E_7~0 := 2; [L58] ~E_8~0 := 2; [?] havoc main_#res; [?] havoc main_~__retres1~10; [L1307] havoc main_~__retres1~10; [L1215] ~m_i~0 := 1; [L1216] ~t1_i~0 := 1; [L1217] ~t2_i~0 := 1; [L1218] ~t3_i~0 := 1; [L1219] ~t4_i~0 := 1; [L1220] ~t5_i~0 := 1; [L1221] ~t6_i~0 := 1; [L1222] ~t7_i~0 := 1; [L1223] ~t8_i~0 := 1; [L1312] havoc start_simulation_#t~ret20, start_simulation_#t~ret21, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1; [L1248] havoc start_simulation_~kernel_st~0; [L1249] havoc start_simulation_~tmp~3; [L1250] havoc start_simulation_~tmp___0~1; [L1254] start_simulation_~kernel_st~0 := 0; [L571] COND TRUE 1 == ~m_i~0 [L572] ~m_st~0 := 0; [L576] COND TRUE 1 == ~t1_i~0 [L577] ~t1_st~0 := 0; [L581] COND TRUE 1 == ~t2_i~0 [L582] ~t2_st~0 := 0; [L586] COND TRUE 1 == ~t3_i~0 [L587] ~t3_st~0 := 0; [L591] COND TRUE 1 == ~t4_i~0 [L592] ~t4_st~0 := 0; [L596] COND TRUE 1 == ~t5_i~0 [L597] ~t5_st~0 := 0; [L601] COND TRUE 1 == ~t6_i~0 [L602] ~t6_st~0 := 0; [L606] COND TRUE 1 == ~t7_i~0 [L607] ~t7_st~0 := 0; [L611] COND TRUE 1 == ~t8_i~0 [L612] ~t8_st~0 := 0; [L828] COND FALSE !(0 == ~M_E~0) [L833] COND FALSE !(0 == ~T1_E~0) [L838] COND FALSE !(0 == ~T2_E~0) [L843] COND FALSE !(0 == ~T3_E~0) [L848] COND FALSE !(0 == ~T4_E~0) [L853] COND FALSE !(0 == ~T5_E~0) [L858] COND FALSE !(0 == ~T6_E~0) [L863] COND FALSE !(0 == ~T7_E~0) [L868] COND FALSE !(0 == ~T8_E~0) [L873] COND FALSE !(0 == ~E_1~0) [L878] COND FALSE !(0 == ~E_2~0) [L883] COND FALSE !(0 == ~E_3~0) [L888] COND FALSE !(0 == ~E_4~0) [L893] COND FALSE !(0 == ~E_5~0) [L898] COND FALSE !(0 == ~E_6~0) [L903] COND FALSE !(0 == ~E_7~0) [L908] COND FALSE !(0 == ~E_8~0) [L1258] havoc activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0; [L1011] havoc activate_threads_~tmp~1; [L1012] havoc activate_threads_~tmp___0~0; [L1013] havoc activate_threads_~tmp___1~0; [L1014] havoc activate_threads_~tmp___2~0; [L1015] havoc activate_threads_~tmp___3~0; [L1016] havoc activate_threads_~tmp___4~0; [L1017] havoc activate_threads_~tmp___5~0; [L1018] havoc activate_threads_~tmp___6~0; [L1019] havoc activate_threads_~tmp___7~0; [L1023] havoc is_master_triggered_#res; [L1023] havoc is_master_triggered_~__retres1~0; [L389] havoc is_master_triggered_~__retres1~0; [L392] COND FALSE !(1 == ~m_pc~0) [L402] is_master_triggered_~__retres1~0 := 0; [L404] is_master_triggered_#res := is_master_triggered_~__retres1~0; [L1023] activate_threads_#t~ret10 := is_master_triggered_#res; [L1023] activate_threads_~tmp~1 := activate_threads_#t~ret10; [L1023] havoc activate_threads_#t~ret10; [L1025-L1029] COND FALSE !(0 != activate_threads_~tmp~1) [L1031] havoc is_transmit1_triggered_#res; [L1031] havoc is_transmit1_triggered_~__retres1~1; [L408] havoc is_transmit1_triggered_~__retres1~1; [L411] COND FALSE !(1 == ~t1_pc~0) [L421] is_transmit1_triggered_~__retres1~1 := 0; [L423] is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; [L1031] activate_threads_#t~ret11 := is_transmit1_triggered_#res; [L1031] activate_threads_~tmp___0~0 := activate_threads_#t~ret11; [L1031] havoc activate_threads_#t~ret11; [L1033-L1037] COND FALSE !(0 != activate_threads_~tmp___0~0) [L1039] havoc is_transmit2_triggered_#res; [L1039] havoc is_transmit2_triggered_~__retres1~2; [L427] havoc is_transmit2_triggered_~__retres1~2; [L430] COND FALSE !(1 == ~t2_pc~0) [L440] is_transmit2_triggered_~__retres1~2 := 0; [L442] is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; [L1039] activate_threads_#t~ret12 := is_transmit2_triggered_#res; [L1039] activate_threads_~tmp___1~0 := activate_threads_#t~ret12; [L1039] havoc activate_threads_#t~ret12; [L1041-L1045] COND FALSE !(0 != activate_threads_~tmp___1~0) [L1047] havoc is_transmit3_triggered_#res; [L1047] havoc is_transmit3_triggered_~__retres1~3; [L446] havoc is_transmit3_triggered_~__retres1~3; [L449] COND FALSE !(1 == ~t3_pc~0) [L459] is_transmit3_triggered_~__retres1~3 := 0; [L461] is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; [L1047] activate_threads_#t~ret13 := is_transmit3_triggered_#res; [L1047] activate_threads_~tmp___2~0 := activate_threads_#t~ret13; [L1047] havoc activate_threads_#t~ret13; [L1049-L1053] COND FALSE !(0 != activate_threads_~tmp___2~0) [L1055] havoc is_transmit4_triggered_#res; [L1055] havoc is_transmit4_triggered_~__retres1~4; [L465] havoc is_transmit4_triggered_~__retres1~4; [L468] COND FALSE !(1 == ~t4_pc~0) [L478] is_transmit4_triggered_~__retres1~4 := 0; [L480] is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; [L1055] activate_threads_#t~ret14 := is_transmit4_triggered_#res; [L1055] activate_threads_~tmp___3~0 := activate_threads_#t~ret14; [L1055] havoc activate_threads_#t~ret14; [L1057-L1061] COND FALSE !(0 != activate_threads_~tmp___3~0) [L1063] havoc is_transmit5_triggered_#res; [L1063] havoc is_transmit5_triggered_~__retres1~5; [L484] havoc is_transmit5_triggered_~__retres1~5; [L487] COND FALSE !(1 == ~t5_pc~0) [L497] is_transmit5_triggered_~__retres1~5 := 0; [L499] is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; [L1063] activate_threads_#t~ret15 := is_transmit5_triggered_#res; [L1063] activate_threads_~tmp___4~0 := activate_threads_#t~ret15; [L1063] havoc activate_threads_#t~ret15; [L1065-L1069] COND FALSE !(0 != activate_threads_~tmp___4~0) [L1071] havoc is_transmit6_triggered_#res; [L1071] havoc is_transmit6_triggered_~__retres1~6; [L503] havoc is_transmit6_triggered_~__retres1~6; [L506] COND FALSE !(1 == ~t6_pc~0) [L516] is_transmit6_triggered_~__retres1~6 := 0; [L518] is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; [L1071] activate_threads_#t~ret16 := is_transmit6_triggered_#res; [L1071] activate_threads_~tmp___5~0 := activate_threads_#t~ret16; [L1071] havoc activate_threads_#t~ret16; [L1073-L1077] COND FALSE !(0 != activate_threads_~tmp___5~0) [L1079] havoc is_transmit7_triggered_#res; [L1079] havoc is_transmit7_triggered_~__retres1~7; [L522] havoc is_transmit7_triggered_~__retres1~7; [L525] COND FALSE !(1 == ~t7_pc~0) [L535] is_transmit7_triggered_~__retres1~7 := 0; [L537] is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; [L1079] activate_threads_#t~ret17 := is_transmit7_triggered_#res; [L1079] activate_threads_~tmp___6~0 := activate_threads_#t~ret17; [L1079] havoc activate_threads_#t~ret17; [L1081-L1085] COND FALSE !(0 != activate_threads_~tmp___6~0) [L1087] havoc is_transmit8_triggered_#res; [L1087] havoc is_transmit8_triggered_~__retres1~8; [L541] havoc is_transmit8_triggered_~__retres1~8; [L544] COND FALSE !(1 == ~t8_pc~0) [L554] is_transmit8_triggered_~__retres1~8 := 0; [L556] is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; [L1087] activate_threads_#t~ret18 := is_transmit8_triggered_#res; [L1087] activate_threads_~tmp___7~0 := activate_threads_#t~ret18; [L1087] havoc activate_threads_#t~ret18; [L1089-L1093] COND FALSE !(0 != activate_threads_~tmp___7~0) [L921] COND FALSE !(1 == ~M_E~0) [L926] COND FALSE !(1 == ~T1_E~0) [L931] COND FALSE !(1 == ~T2_E~0) [L936] COND FALSE !(1 == ~T3_E~0) [L941] COND FALSE !(1 == ~T4_E~0) [L946] COND FALSE !(1 == ~T5_E~0) [L951] COND FALSE !(1 == ~T6_E~0) [L956] COND FALSE !(1 == ~T7_E~0) [L961] COND FALSE !(1 == ~T8_E~0) [L966] COND FALSE !(1 == ~E_1~0) [L971] COND FALSE !(1 == ~E_2~0) [L976] COND FALSE !(1 == ~E_3~0) [L981] COND FALSE !(1 == ~E_4~0) [L986] COND FALSE !(1 == ~E_5~0) [L991] COND FALSE !(1 == ~E_6~0) [L996] COND FALSE !(1 == ~E_7~0) [L1001] COND FALSE !(1 == ~E_8~0) [L1262-L1299] COND FALSE !(false) [L1265] start_simulation_~kernel_st~0 := 1; [L1266] havoc eval_#t~ret0, eval_#t~nondet1, eval_~tmp_ndt_1~0, eval_#t~nondet2, eval_~tmp_ndt_2~0, eval_#t~nondet3, eval_~tmp_ndt_3~0, eval_#t~nondet4, eval_~tmp_ndt_4~0, eval_#t~nondet5, eval_~tmp_ndt_5~0, eval_#t~nondet6, eval_~tmp_ndt_6~0, eval_#t~nondet7, eval_~tmp_ndt_7~0, eval_#t~nondet8, eval_~tmp_ndt_8~0, eval_#t~nondet9, eval_~tmp_ndt_9~0, eval_~tmp~0; [L677] havoc eval_~tmp~0; ----- ----- class de.uni_freiburg.informatik.ultimate.boogie.procedureinliner.backtranslation.InlinerBacktranslator [L15] ~m_pc~0 := 0; [L16] ~t1_pc~0 := 0; [L17] ~t2_pc~0 := 0; [L18] ~t3_pc~0 := 0; [L19] ~t4_pc~0 := 0; [L20] ~t5_pc~0 := 0; [L21] ~t6_pc~0 := 0; [L22] ~t7_pc~0 := 0; [L23] ~t8_pc~0 := 0; [L24] ~m_st~0 := 0; [L25] ~t1_st~0 := 0; [L26] ~t2_st~0 := 0; [L27] ~t3_st~0 := 0; [L28] ~t4_st~0 := 0; [L29] ~t5_st~0 := 0; [L30] ~t6_st~0 := 0; [L31] ~t7_st~0 := 0; [L32] ~t8_st~0 := 0; [L33] ~m_i~0 := 0; [L34] ~t1_i~0 := 0; [L35] ~t2_i~0 := 0; [L36] ~t3_i~0 := 0; [L37] ~t4_i~0 := 0; [L38] ~t5_i~0 := 0; [L39] ~t6_i~0 := 0; [L40] ~t7_i~0 := 0; [L41] ~t8_i~0 := 0; [L42] ~M_E~0 := 2; [L43] ~T1_E~0 := 2; [L44] ~T2_E~0 := 2; [L45] ~T3_E~0 := 2; [L46] ~T4_E~0 := 2; [L47] ~T5_E~0 := 2; [L48] ~T6_E~0 := 2; [L49] ~T7_E~0 := 2; [L50] ~T8_E~0 := 2; [L51] ~E_1~0 := 2; [L52] ~E_2~0 := 2; [L53] ~E_3~0 := 2; [L54] ~E_4~0 := 2; [L55] ~E_5~0 := 2; [L56] ~E_6~0 := 2; [L57] ~E_7~0 := 2; [L58] ~E_8~0 := 2; [?] havoc main_#res; [?] havoc main_~__retres1~10; [L1307] havoc main_~__retres1~10; [L1215] ~m_i~0 := 1; [L1216] ~t1_i~0 := 1; [L1217] ~t2_i~0 := 1; [L1218] ~t3_i~0 := 1; [L1219] ~t4_i~0 := 1; [L1220] ~t5_i~0 := 1; [L1221] ~t6_i~0 := 1; [L1222] ~t7_i~0 := 1; [L1223] ~t8_i~0 := 1; [L1312] havoc start_simulation_#t~ret20, start_simulation_#t~ret21, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1; [L1248] havoc start_simulation_~kernel_st~0; [L1249] havoc start_simulation_~tmp~3; [L1250] havoc start_simulation_~tmp___0~1; [L1254] start_simulation_~kernel_st~0 := 0; [L571] COND TRUE 1 == ~m_i~0 [L572] ~m_st~0 := 0; [L576] COND TRUE 1 == ~t1_i~0 [L577] ~t1_st~0 := 0; [L581] COND TRUE 1 == ~t2_i~0 [L582] ~t2_st~0 := 0; [L586] COND TRUE 1 == ~t3_i~0 [L587] ~t3_st~0 := 0; [L591] COND TRUE 1 == ~t4_i~0 [L592] ~t4_st~0 := 0; [L596] COND TRUE 1 == ~t5_i~0 [L597] ~t5_st~0 := 0; [L601] COND TRUE 1 == ~t6_i~0 [L602] ~t6_st~0 := 0; [L606] COND TRUE 1 == ~t7_i~0 [L607] ~t7_st~0 := 0; [L611] COND TRUE 1 == ~t8_i~0 [L612] ~t8_st~0 := 0; [L828] COND FALSE !(0 == ~M_E~0) [L833] COND FALSE !(0 == ~T1_E~0) [L838] COND FALSE !(0 == ~T2_E~0) [L843] COND FALSE !(0 == ~T3_E~0) [L848] COND FALSE !(0 == ~T4_E~0) [L853] COND FALSE !(0 == ~T5_E~0) [L858] COND FALSE !(0 == ~T6_E~0) [L863] COND FALSE !(0 == ~T7_E~0) [L868] COND FALSE !(0 == ~T8_E~0) [L873] COND FALSE !(0 == ~E_1~0) [L878] COND FALSE !(0 == ~E_2~0) [L883] COND FALSE !(0 == ~E_3~0) [L888] COND FALSE !(0 == ~E_4~0) [L893] COND FALSE !(0 == ~E_5~0) [L898] COND FALSE !(0 == ~E_6~0) [L903] COND FALSE !(0 == ~E_7~0) [L908] COND FALSE !(0 == ~E_8~0) [L1258] havoc activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0; [L1011] havoc activate_threads_~tmp~1; [L1012] havoc activate_threads_~tmp___0~0; [L1013] havoc activate_threads_~tmp___1~0; [L1014] havoc activate_threads_~tmp___2~0; [L1015] havoc activate_threads_~tmp___3~0; [L1016] havoc activate_threads_~tmp___4~0; [L1017] havoc activate_threads_~tmp___5~0; [L1018] havoc activate_threads_~tmp___6~0; [L1019] havoc activate_threads_~tmp___7~0; [L1023] havoc is_master_triggered_#res; [L1023] havoc is_master_triggered_~__retres1~0; [L389] havoc is_master_triggered_~__retres1~0; [L392] COND FALSE !(1 == ~m_pc~0) [L402] is_master_triggered_~__retres1~0 := 0; [L404] is_master_triggered_#res := is_master_triggered_~__retres1~0; [L1023] activate_threads_#t~ret10 := is_master_triggered_#res; [L1023] activate_threads_~tmp~1 := activate_threads_#t~ret10; [L1023] havoc activate_threads_#t~ret10; [L1025-L1029] COND FALSE !(0 != activate_threads_~tmp~1) [L1031] havoc is_transmit1_triggered_#res; [L1031] havoc is_transmit1_triggered_~__retres1~1; [L408] havoc is_transmit1_triggered_~__retres1~1; [L411] COND FALSE !(1 == ~t1_pc~0) [L421] is_transmit1_triggered_~__retres1~1 := 0; [L423] is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; [L1031] activate_threads_#t~ret11 := is_transmit1_triggered_#res; [L1031] activate_threads_~tmp___0~0 := activate_threads_#t~ret11; [L1031] havoc activate_threads_#t~ret11; [L1033-L1037] COND FALSE !(0 != activate_threads_~tmp___0~0) [L1039] havoc is_transmit2_triggered_#res; [L1039] havoc is_transmit2_triggered_~__retres1~2; [L427] havoc is_transmit2_triggered_~__retres1~2; [L430] COND FALSE !(1 == ~t2_pc~0) [L440] is_transmit2_triggered_~__retres1~2 := 0; [L442] is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; [L1039] activate_threads_#t~ret12 := is_transmit2_triggered_#res; [L1039] activate_threads_~tmp___1~0 := activate_threads_#t~ret12; [L1039] havoc activate_threads_#t~ret12; [L1041-L1045] COND FALSE !(0 != activate_threads_~tmp___1~0) [L1047] havoc is_transmit3_triggered_#res; [L1047] havoc is_transmit3_triggered_~__retres1~3; [L446] havoc is_transmit3_triggered_~__retres1~3; [L449] COND FALSE !(1 == ~t3_pc~0) [L459] is_transmit3_triggered_~__retres1~3 := 0; [L461] is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; [L1047] activate_threads_#t~ret13 := is_transmit3_triggered_#res; [L1047] activate_threads_~tmp___2~0 := activate_threads_#t~ret13; [L1047] havoc activate_threads_#t~ret13; [L1049-L1053] COND FALSE !(0 != activate_threads_~tmp___2~0) [L1055] havoc is_transmit4_triggered_#res; [L1055] havoc is_transmit4_triggered_~__retres1~4; [L465] havoc is_transmit4_triggered_~__retres1~4; [L468] COND FALSE !(1 == ~t4_pc~0) [L478] is_transmit4_triggered_~__retres1~4 := 0; [L480] is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; [L1055] activate_threads_#t~ret14 := is_transmit4_triggered_#res; [L1055] activate_threads_~tmp___3~0 := activate_threads_#t~ret14; [L1055] havoc activate_threads_#t~ret14; [L1057-L1061] COND FALSE !(0 != activate_threads_~tmp___3~0) [L1063] havoc is_transmit5_triggered_#res; [L1063] havoc is_transmit5_triggered_~__retres1~5; [L484] havoc is_transmit5_triggered_~__retres1~5; [L487] COND FALSE !(1 == ~t5_pc~0) [L497] is_transmit5_triggered_~__retres1~5 := 0; [L499] is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; [L1063] activate_threads_#t~ret15 := is_transmit5_triggered_#res; [L1063] activate_threads_~tmp___4~0 := activate_threads_#t~ret15; [L1063] havoc activate_threads_#t~ret15; [L1065-L1069] COND FALSE !(0 != activate_threads_~tmp___4~0) [L1071] havoc is_transmit6_triggered_#res; [L1071] havoc is_transmit6_triggered_~__retres1~6; [L503] havoc is_transmit6_triggered_~__retres1~6; [L506] COND FALSE !(1 == ~t6_pc~0) [L516] is_transmit6_triggered_~__retres1~6 := 0; [L518] is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; [L1071] activate_threads_#t~ret16 := is_transmit6_triggered_#res; [L1071] activate_threads_~tmp___5~0 := activate_threads_#t~ret16; [L1071] havoc activate_threads_#t~ret16; [L1073-L1077] COND FALSE !(0 != activate_threads_~tmp___5~0) [L1079] havoc is_transmit7_triggered_#res; [L1079] havoc is_transmit7_triggered_~__retres1~7; [L522] havoc is_transmit7_triggered_~__retres1~7; [L525] COND FALSE !(1 == ~t7_pc~0) [L535] is_transmit7_triggered_~__retres1~7 := 0; [L537] is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; [L1079] activate_threads_#t~ret17 := is_transmit7_triggered_#res; [L1079] activate_threads_~tmp___6~0 := activate_threads_#t~ret17; [L1079] havoc activate_threads_#t~ret17; [L1081-L1085] COND FALSE !(0 != activate_threads_~tmp___6~0) [L1087] havoc is_transmit8_triggered_#res; [L1087] havoc is_transmit8_triggered_~__retres1~8; [L541] havoc is_transmit8_triggered_~__retres1~8; [L544] COND FALSE !(1 == ~t8_pc~0) [L554] is_transmit8_triggered_~__retres1~8 := 0; [L556] is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; [L1087] activate_threads_#t~ret18 := is_transmit8_triggered_#res; [L1087] activate_threads_~tmp___7~0 := activate_threads_#t~ret18; [L1087] havoc activate_threads_#t~ret18; [L1089-L1093] COND FALSE !(0 != activate_threads_~tmp___7~0) [L921] COND FALSE !(1 == ~M_E~0) [L926] COND FALSE !(1 == ~T1_E~0) [L931] COND FALSE !(1 == ~T2_E~0) [L936] COND FALSE !(1 == ~T3_E~0) [L941] COND FALSE !(1 == ~T4_E~0) [L946] COND FALSE !(1 == ~T5_E~0) [L951] COND FALSE !(1 == ~T6_E~0) [L956] COND FALSE !(1 == ~T7_E~0) [L961] COND FALSE !(1 == ~T8_E~0) [L966] COND FALSE !(1 == ~E_1~0) [L971] COND FALSE !(1 == ~E_2~0) [L976] COND FALSE !(1 == ~E_3~0) [L981] COND FALSE !(1 == ~E_4~0) [L986] COND FALSE !(1 == ~E_5~0) [L991] COND FALSE !(1 == ~E_6~0) [L996] COND FALSE !(1 == ~E_7~0) [L1001] COND FALSE !(1 == ~E_8~0) [L1262-L1299] COND FALSE !(false) [L1265] start_simulation_~kernel_st~0 := 1; [L1266] havoc eval_#t~ret0, eval_#t~nondet1, eval_~tmp_ndt_1~0, eval_#t~nondet2, eval_~tmp_ndt_2~0, eval_#t~nondet3, eval_~tmp_ndt_3~0, eval_#t~nondet4, eval_~tmp_ndt_4~0, eval_#t~nondet5, eval_~tmp_ndt_5~0, eval_#t~nondet6, eval_~tmp_ndt_6~0, eval_#t~nondet7, eval_~tmp_ndt_7~0, eval_#t~nondet8, eval_~tmp_ndt_8~0, eval_#t~nondet9, eval_~tmp_ndt_9~0, eval_~tmp~0; [L677] havoc eval_~tmp~0; [L15] ~m_pc~0 := 0; [L16] ~t1_pc~0 := 0; [L17] ~t2_pc~0 := 0; [L18] ~t3_pc~0 := 0; [L19] ~t4_pc~0 := 0; [L20] ~t5_pc~0 := 0; [L21] ~t6_pc~0 := 0; [L22] ~t7_pc~0 := 0; [L23] ~t8_pc~0 := 0; [L24] ~m_st~0 := 0; [L25] ~t1_st~0 := 0; [L26] ~t2_st~0 := 0; [L27] ~t3_st~0 := 0; [L28] ~t4_st~0 := 0; [L29] ~t5_st~0 := 0; [L30] ~t6_st~0 := 0; [L31] ~t7_st~0 := 0; [L32] ~t8_st~0 := 0; [L33] ~m_i~0 := 0; [L34] ~t1_i~0 := 0; [L35] ~t2_i~0 := 0; [L36] ~t3_i~0 := 0; [L37] ~t4_i~0 := 0; [L38] ~t5_i~0 := 0; [L39] ~t6_i~0 := 0; [L40] ~t7_i~0 := 0; [L41] ~t8_i~0 := 0; [L42] ~M_E~0 := 2; [L43] ~T1_E~0 := 2; [L44] ~T2_E~0 := 2; [L45] ~T3_E~0 := 2; [L46] ~T4_E~0 := 2; [L47] ~T5_E~0 := 2; [L48] ~T6_E~0 := 2; [L49] ~T7_E~0 := 2; [L50] ~T8_E~0 := 2; [L51] ~E_1~0 := 2; [L52] ~E_2~0 := 2; [L53] ~E_3~0 := 2; [L54] ~E_4~0 := 2; [L55] ~E_5~0 := 2; [L56] ~E_6~0 := 2; [L57] ~E_7~0 := 2; [L58] ~E_8~0 := 2; [L1307] havoc ~__retres1~10; [L1215] ~m_i~0 := 1; [L1216] ~t1_i~0 := 1; [L1217] ~t2_i~0 := 1; [L1218] ~t3_i~0 := 1; [L1219] ~t4_i~0 := 1; [L1220] ~t5_i~0 := 1; [L1221] ~t6_i~0 := 1; [L1222] ~t7_i~0 := 1; [L1223] ~t8_i~0 := 1; [L1248] havoc ~kernel_st~0; [L1249] havoc ~tmp~3; [L1250] havoc ~tmp___0~1; [L1254] ~kernel_st~0 := 0; [L571] COND TRUE 1 == ~m_i~0 [L572] ~m_st~0 := 0; [L576] COND TRUE 1 == ~t1_i~0 [L577] ~t1_st~0 := 0; [L581] COND TRUE 1 == ~t2_i~0 [L582] ~t2_st~0 := 0; [L586] COND TRUE 1 == ~t3_i~0 [L587] ~t3_st~0 := 0; [L591] COND TRUE 1 == ~t4_i~0 [L592] ~t4_st~0 := 0; [L596] COND TRUE 1 == ~t5_i~0 [L597] ~t5_st~0 := 0; [L601] COND TRUE 1 == ~t6_i~0 [L602] ~t6_st~0 := 0; [L606] COND TRUE 1 == ~t7_i~0 [L607] ~t7_st~0 := 0; [L611] COND TRUE 1 == ~t8_i~0 [L612] ~t8_st~0 := 0; [L828] COND FALSE !(0 == ~M_E~0) [L833] COND FALSE !(0 == ~T1_E~0) [L838] COND FALSE !(0 == ~T2_E~0) [L843] COND FALSE !(0 == ~T3_E~0) [L848] COND FALSE !(0 == ~T4_E~0) [L853] COND FALSE !(0 == ~T5_E~0) [L858] COND FALSE !(0 == ~T6_E~0) [L863] COND FALSE !(0 == ~T7_E~0) [L868] COND FALSE !(0 == ~T8_E~0) [L873] COND FALSE !(0 == ~E_1~0) [L878] COND FALSE !(0 == ~E_2~0) [L883] COND FALSE !(0 == ~E_3~0) [L888] COND FALSE !(0 == ~E_4~0) [L893] COND FALSE !(0 == ~E_5~0) [L898] COND FALSE !(0 == ~E_6~0) [L903] COND FALSE !(0 == ~E_7~0) [L908] COND FALSE !(0 == ~E_8~0) [L1011] havoc ~tmp~1; [L1012] havoc ~tmp___0~0; [L1013] havoc ~tmp___1~0; [L1014] havoc ~tmp___2~0; [L1015] havoc ~tmp___3~0; [L1016] havoc ~tmp___4~0; [L1017] havoc ~tmp___5~0; [L1018] havoc ~tmp___6~0; [L1019] havoc ~tmp___7~0; [L389] havoc ~__retres1~0; [L392] COND FALSE !(1 == ~m_pc~0) [L402] ~__retres1~0 := 0; [L404] #res := ~__retres1~0; [L1023] ~tmp~1 := #t~ret10; [L1023] havoc #t~ret10; [L1025-L1029] COND FALSE !(0 != ~tmp~1) [L408] havoc ~__retres1~1; [L411] COND FALSE !(1 == ~t1_pc~0) [L421] ~__retres1~1 := 0; [L423] #res := ~__retres1~1; [L1031] ~tmp___0~0 := #t~ret11; [L1031] havoc #t~ret11; [L1033-L1037] COND FALSE !(0 != ~tmp___0~0) [L427] havoc ~__retres1~2; [L430] COND FALSE !(1 == ~t2_pc~0) [L440] ~__retres1~2 := 0; [L442] #res := ~__retres1~2; [L1039] ~tmp___1~0 := #t~ret12; [L1039] havoc #t~ret12; [L1041-L1045] COND FALSE !(0 != ~tmp___1~0) [L446] havoc ~__retres1~3; [L449] COND FALSE !(1 == ~t3_pc~0) [L459] ~__retres1~3 := 0; [L461] #res := ~__retres1~3; [L1047] ~tmp___2~0 := #t~ret13; [L1047] havoc #t~ret13; [L1049-L1053] COND FALSE !(0 != ~tmp___2~0) [L465] havoc ~__retres1~4; [L468] COND FALSE !(1 == ~t4_pc~0) [L478] ~__retres1~4 := 0; [L480] #res := ~__retres1~4; [L1055] ~tmp___3~0 := #t~ret14; [L1055] havoc #t~ret14; [L1057-L1061] COND FALSE !(0 != ~tmp___3~0) [L484] havoc ~__retres1~5; [L487] COND FALSE !(1 == ~t5_pc~0) [L497] ~__retres1~5 := 0; [L499] #res := ~__retres1~5; [L1063] ~tmp___4~0 := #t~ret15; [L1063] havoc #t~ret15; [L1065-L1069] COND FALSE !(0 != ~tmp___4~0) [L503] havoc ~__retres1~6; [L506] COND FALSE !(1 == ~t6_pc~0) [L516] ~__retres1~6 := 0; [L518] #res := ~__retres1~6; [L1071] ~tmp___5~0 := #t~ret16; [L1071] havoc #t~ret16; [L1073-L1077] COND FALSE !(0 != ~tmp___5~0) [L522] havoc ~__retres1~7; [L525] COND FALSE !(1 == ~t7_pc~0) [L535] ~__retres1~7 := 0; [L537] #res := ~__retres1~7; [L1079] ~tmp___6~0 := #t~ret17; [L1079] havoc #t~ret17; [L1081-L1085] COND FALSE !(0 != ~tmp___6~0) [L541] havoc ~__retres1~8; [L544] COND FALSE !(1 == ~t8_pc~0) [L554] ~__retres1~8 := 0; [L556] #res := ~__retres1~8; [L1087] ~tmp___7~0 := #t~ret18; [L1087] havoc #t~ret18; [L1089-L1093] COND FALSE !(0 != ~tmp___7~0) [L921] COND FALSE !(1 == ~M_E~0) [L926] COND FALSE !(1 == ~T1_E~0) [L931] COND FALSE !(1 == ~T2_E~0) [L936] COND FALSE !(1 == ~T3_E~0) [L941] COND FALSE !(1 == ~T4_E~0) [L946] COND FALSE !(1 == ~T5_E~0) [L951] COND FALSE !(1 == ~T6_E~0) [L956] COND FALSE !(1 == ~T7_E~0) [L961] COND FALSE !(1 == ~T8_E~0) [L966] COND FALSE !(1 == ~E_1~0) [L971] COND FALSE !(1 == ~E_2~0) [L976] COND FALSE !(1 == ~E_3~0) [L981] COND FALSE !(1 == ~E_4~0) [L986] COND FALSE !(1 == ~E_5~0) [L991] COND FALSE !(1 == ~E_6~0) [L996] COND FALSE !(1 == ~E_7~0) [L1001] COND FALSE !(1 == ~E_8~0) [L1262-L1299] COND FALSE !(false) [L1265] ~kernel_st~0 := 1; [L677] havoc ~tmp~0; ----- ----- class de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.CACSL2BoogieBacktranslator [L15] ~m_pc~0 := 0; [L16] ~t1_pc~0 := 0; [L17] ~t2_pc~0 := 0; [L18] ~t3_pc~0 := 0; [L19] ~t4_pc~0 := 0; [L20] ~t5_pc~0 := 0; [L21] ~t6_pc~0 := 0; [L22] ~t7_pc~0 := 0; [L23] ~t8_pc~0 := 0; [L24] ~m_st~0 := 0; [L25] ~t1_st~0 := 0; [L26] ~t2_st~0 := 0; [L27] ~t3_st~0 := 0; [L28] ~t4_st~0 := 0; [L29] ~t5_st~0 := 0; [L30] ~t6_st~0 := 0; [L31] ~t7_st~0 := 0; [L32] ~t8_st~0 := 0; [L33] ~m_i~0 := 0; [L34] ~t1_i~0 := 0; [L35] ~t2_i~0 := 0; [L36] ~t3_i~0 := 0; [L37] ~t4_i~0 := 0; [L38] ~t5_i~0 := 0; [L39] ~t6_i~0 := 0; [L40] ~t7_i~0 := 0; [L41] ~t8_i~0 := 0; [L42] ~M_E~0 := 2; [L43] ~T1_E~0 := 2; [L44] ~T2_E~0 := 2; [L45] ~T3_E~0 := 2; [L46] ~T4_E~0 := 2; [L47] ~T5_E~0 := 2; [L48] ~T6_E~0 := 2; [L49] ~T7_E~0 := 2; [L50] ~T8_E~0 := 2; [L51] ~E_1~0 := 2; [L52] ~E_2~0 := 2; [L53] ~E_3~0 := 2; [L54] ~E_4~0 := 2; [L55] ~E_5~0 := 2; [L56] ~E_6~0 := 2; [L57] ~E_7~0 := 2; [L58] ~E_8~0 := 2; [L1307] havoc ~__retres1~10; [L1215] ~m_i~0 := 1; [L1216] ~t1_i~0 := 1; [L1217] ~t2_i~0 := 1; [L1218] ~t3_i~0 := 1; [L1219] ~t4_i~0 := 1; [L1220] ~t5_i~0 := 1; [L1221] ~t6_i~0 := 1; [L1222] ~t7_i~0 := 1; [L1223] ~t8_i~0 := 1; [L1248] havoc ~kernel_st~0; [L1249] havoc ~tmp~3; [L1250] havoc ~tmp___0~1; [L1254] ~kernel_st~0 := 0; [L571] COND TRUE 1 == ~m_i~0 [L572] ~m_st~0 := 0; [L576] COND TRUE 1 == ~t1_i~0 [L577] ~t1_st~0 := 0; [L581] COND TRUE 1 == ~t2_i~0 [L582] ~t2_st~0 := 0; [L586] COND TRUE 1 == ~t3_i~0 [L587] ~t3_st~0 := 0; [L591] COND TRUE 1 == ~t4_i~0 [L592] ~t4_st~0 := 0; [L596] COND TRUE 1 == ~t5_i~0 [L597] ~t5_st~0 := 0; [L601] COND TRUE 1 == ~t6_i~0 [L602] ~t6_st~0 := 0; [L606] COND TRUE 1 == ~t7_i~0 [L607] ~t7_st~0 := 0; [L611] COND TRUE 1 == ~t8_i~0 [L612] ~t8_st~0 := 0; [L828] COND FALSE !(0 == ~M_E~0) [L833] COND FALSE !(0 == ~T1_E~0) [L838] COND FALSE !(0 == ~T2_E~0) [L843] COND FALSE !(0 == ~T3_E~0) [L848] COND FALSE !(0 == ~T4_E~0) [L853] COND FALSE !(0 == ~T5_E~0) [L858] COND FALSE !(0 == ~T6_E~0) [L863] COND FALSE !(0 == ~T7_E~0) [L868] COND FALSE !(0 == ~T8_E~0) [L873] COND FALSE !(0 == ~E_1~0) [L878] COND FALSE !(0 == ~E_2~0) [L883] COND FALSE !(0 == ~E_3~0) [L888] COND FALSE !(0 == ~E_4~0) [L893] COND FALSE !(0 == ~E_5~0) [L898] COND FALSE !(0 == ~E_6~0) [L903] COND FALSE !(0 == ~E_7~0) [L908] COND FALSE !(0 == ~E_8~0) [L1011] havoc ~tmp~1; [L1012] havoc ~tmp___0~0; [L1013] havoc ~tmp___1~0; [L1014] havoc ~tmp___2~0; [L1015] havoc ~tmp___3~0; [L1016] havoc ~tmp___4~0; [L1017] havoc ~tmp___5~0; [L1018] havoc ~tmp___6~0; [L1019] havoc ~tmp___7~0; [L389] havoc ~__retres1~0; [L392] COND FALSE !(1 == ~m_pc~0) [L402] ~__retres1~0 := 0; [L404] #res := ~__retres1~0; [L1023] ~tmp~1 := #t~ret10; [L1023] havoc #t~ret10; [L1025-L1029] COND FALSE !(0 != ~tmp~1) [L408] havoc ~__retres1~1; [L411] COND FALSE !(1 == ~t1_pc~0) [L421] ~__retres1~1 := 0; [L423] #res := ~__retres1~1; [L1031] ~tmp___0~0 := #t~ret11; [L1031] havoc #t~ret11; [L1033-L1037] COND FALSE !(0 != ~tmp___0~0) [L427] havoc ~__retres1~2; [L430] COND FALSE !(1 == ~t2_pc~0) [L440] ~__retres1~2 := 0; [L442] #res := ~__retres1~2; [L1039] ~tmp___1~0 := #t~ret12; [L1039] havoc #t~ret12; [L1041-L1045] COND FALSE !(0 != ~tmp___1~0) [L446] havoc ~__retres1~3; [L449] COND FALSE !(1 == ~t3_pc~0) [L459] ~__retres1~3 := 0; [L461] #res := ~__retres1~3; [L1047] ~tmp___2~0 := #t~ret13; [L1047] havoc #t~ret13; [L1049-L1053] COND FALSE !(0 != ~tmp___2~0) [L465] havoc ~__retres1~4; [L468] COND FALSE !(1 == ~t4_pc~0) [L478] ~__retres1~4 := 0; [L480] #res := ~__retres1~4; [L1055] ~tmp___3~0 := #t~ret14; [L1055] havoc #t~ret14; [L1057-L1061] COND FALSE !(0 != ~tmp___3~0) [L484] havoc ~__retres1~5; [L487] COND FALSE !(1 == ~t5_pc~0) [L497] ~__retres1~5 := 0; [L499] #res := ~__retres1~5; [L1063] ~tmp___4~0 := #t~ret15; [L1063] havoc #t~ret15; [L1065-L1069] COND FALSE !(0 != ~tmp___4~0) [L503] havoc ~__retres1~6; [L506] COND FALSE !(1 == ~t6_pc~0) [L516] ~__retres1~6 := 0; [L518] #res := ~__retres1~6; [L1071] ~tmp___5~0 := #t~ret16; [L1071] havoc #t~ret16; [L1073-L1077] COND FALSE !(0 != ~tmp___5~0) [L522] havoc ~__retres1~7; [L525] COND FALSE !(1 == ~t7_pc~0) [L535] ~__retres1~7 := 0; [L537] #res := ~__retres1~7; [L1079] ~tmp___6~0 := #t~ret17; [L1079] havoc #t~ret17; [L1081-L1085] COND FALSE !(0 != ~tmp___6~0) [L541] havoc ~__retres1~8; [L544] COND FALSE !(1 == ~t8_pc~0) [L554] ~__retres1~8 := 0; [L556] #res := ~__retres1~8; [L1087] ~tmp___7~0 := #t~ret18; [L1087] havoc #t~ret18; [L1089-L1093] COND FALSE !(0 != ~tmp___7~0) [L921] COND FALSE !(1 == ~M_E~0) [L926] COND FALSE !(1 == ~T1_E~0) [L931] COND FALSE !(1 == ~T2_E~0) [L936] COND FALSE !(1 == ~T3_E~0) [L941] COND FALSE !(1 == ~T4_E~0) [L946] COND FALSE !(1 == ~T5_E~0) [L951] COND FALSE !(1 == ~T6_E~0) [L956] COND FALSE !(1 == ~T7_E~0) [L961] COND FALSE !(1 == ~T8_E~0) [L966] COND FALSE !(1 == ~E_1~0) [L971] COND FALSE !(1 == ~E_2~0) [L976] COND FALSE !(1 == ~E_3~0) [L981] COND FALSE !(1 == ~E_4~0) [L986] COND FALSE !(1 == ~E_5~0) [L991] COND FALSE !(1 == ~E_6~0) [L996] COND FALSE !(1 == ~E_7~0) [L1001] COND FALSE !(1 == ~E_8~0) [L1262-L1299] COND FALSE !(false) [L1265] ~kernel_st~0 := 1; [L677] havoc ~tmp~0; [L15] int m_pc = 0; [L16] int t1_pc = 0; [L17] int t2_pc = 0; [L18] int t3_pc = 0; [L19] int t4_pc = 0; [L20] int t5_pc = 0; [L21] int t6_pc = 0; [L22] int t7_pc = 0; [L23] int t8_pc = 0; [L24] int m_st ; [L25] int t1_st ; [L26] int t2_st ; [L27] int t3_st ; [L28] int t4_st ; [L29] int t5_st ; [L30] int t6_st ; [L31] int t7_st ; [L32] int t8_st ; [L33] int m_i ; [L34] int t1_i ; [L35] int t2_i ; [L36] int t3_i ; [L37] int t4_i ; [L38] int t5_i ; [L39] int t6_i ; [L40] int t7_i ; [L41] int t8_i ; [L42] int M_E = 2; [L43] int T1_E = 2; [L44] int T2_E = 2; [L45] int T3_E = 2; [L46] int T4_E = 2; [L47] int T5_E = 2; [L48] int T6_E = 2; [L49] int T7_E = 2; [L50] int T8_E = 2; [L51] int E_1 = 2; [L52] int E_2 = 2; [L53] int E_3 = 2; [L54] int E_4 = 2; [L55] int E_5 = 2; [L56] int E_6 = 2; [L57] int E_7 = 2; [L58] int E_8 = 2; [L1307] int __retres1 ; [L1215] m_i = 1 [L1216] t1_i = 1 [L1217] t2_i = 1 [L1218] t3_i = 1 [L1219] t4_i = 1 [L1220] t5_i = 1 [L1221] t6_i = 1 [L1222] t7_i = 1 [L1223] t8_i = 1 [L1248] int kernel_st ; [L1249] int tmp ; [L1250] int tmp___0 ; [L1254] kernel_st = 0 [L571] COND TRUE m_i == 1 [L572] m_st = 0 [L576] COND TRUE t1_i == 1 [L577] t1_st = 0 [L581] COND TRUE t2_i == 1 [L582] t2_st = 0 [L586] COND TRUE t3_i == 1 [L587] t3_st = 0 [L591] COND TRUE t4_i == 1 [L592] t4_st = 0 [L596] COND TRUE t5_i == 1 [L597] t5_st = 0 [L601] COND TRUE t6_i == 1 [L602] t6_st = 0 [L606] COND TRUE t7_i == 1 [L607] t7_st = 0 [L611] COND TRUE t8_i == 1 [L612] t8_st = 0 [L828] COND FALSE !(M_E == 0) [L833] COND FALSE !(T1_E == 0) [L838] COND FALSE !(T2_E == 0) [L843] COND FALSE !(T3_E == 0) [L848] COND FALSE !(T4_E == 0) [L853] COND FALSE !(T5_E == 0) [L858] COND FALSE !(T6_E == 0) [L863] COND FALSE !(T7_E == 0) [L868] COND FALSE !(T8_E == 0) [L873] COND FALSE !(E_1 == 0) [L878] COND FALSE !(E_2 == 0) [L883] COND FALSE !(E_3 == 0) [L888] COND FALSE !(E_4 == 0) [L893] COND FALSE !(E_5 == 0) [L898] COND FALSE !(E_6 == 0) [L903] COND FALSE !(E_7 == 0) [L908] COND FALSE !(E_8 == 0) [L1011] int tmp ; [L1012] int tmp___0 ; [L1013] int tmp___1 ; [L1014] int tmp___2 ; [L1015] int tmp___3 ; [L1016] int tmp___4 ; [L1017] int tmp___5 ; [L1018] int tmp___6 ; [L1019] int tmp___7 ; [L389] int __retres1 ; [L392] COND FALSE !(m_pc == 1) [L402] __retres1 = 0 [L404] return (__retres1); [L1023] tmp = is_master_triggered() [L1025] COND FALSE !(\read(tmp)) [L408] int __retres1 ; [L411] COND FALSE !(t1_pc == 1) [L421] __retres1 = 0 [L423] return (__retres1); [L1031] tmp___0 = is_transmit1_triggered() [L1033] COND FALSE !(\read(tmp___0)) [L427] int __retres1 ; [L430] COND FALSE !(t2_pc == 1) [L440] __retres1 = 0 [L442] return (__retres1); [L1039] tmp___1 = is_transmit2_triggered() [L1041] COND FALSE !(\read(tmp___1)) [L446] int __retres1 ; [L449] COND FALSE !(t3_pc == 1) [L459] __retres1 = 0 [L461] return (__retres1); [L1047] tmp___2 = is_transmit3_triggered() [L1049] COND FALSE !(\read(tmp___2)) [L465] int __retres1 ; [L468] COND FALSE !(t4_pc == 1) [L478] __retres1 = 0 [L480] return (__retres1); [L1055] tmp___3 = is_transmit4_triggered() [L1057] COND FALSE !(\read(tmp___3)) [L484] int __retres1 ; [L487] COND FALSE !(t5_pc == 1) [L497] __retres1 = 0 [L499] return (__retres1); [L1063] tmp___4 = is_transmit5_triggered() [L1065] COND FALSE !(\read(tmp___4)) [L503] int __retres1 ; [L506] COND FALSE !(t6_pc == 1) [L516] __retres1 = 0 [L518] return (__retres1); [L1071] tmp___5 = is_transmit6_triggered() [L1073] COND FALSE !(\read(tmp___5)) [L522] int __retres1 ; [L525] COND FALSE !(t7_pc == 1) [L535] __retres1 = 0 [L537] return (__retres1); [L1079] tmp___6 = is_transmit7_triggered() [L1081] COND FALSE !(\read(tmp___6)) [L541] int __retres1 ; [L544] COND FALSE !(t8_pc == 1) [L554] __retres1 = 0 [L556] return (__retres1); [L1087] tmp___7 = is_transmit8_triggered() [L1089] COND FALSE !(\read(tmp___7)) [L921] COND FALSE !(M_E == 1) [L926] COND FALSE !(T1_E == 1) [L931] COND FALSE !(T2_E == 1) [L936] COND FALSE !(T3_E == 1) [L941] COND FALSE !(T4_E == 1) [L946] COND FALSE !(T5_E == 1) [L951] COND FALSE !(T6_E == 1) [L956] COND FALSE !(T7_E == 1) [L961] COND FALSE !(T8_E == 1) [L966] COND FALSE !(E_1 == 1) [L971] COND FALSE !(E_2 == 1) [L976] COND FALSE !(E_3 == 1) [L981] COND FALSE !(E_4 == 1) [L986] COND FALSE !(E_5 == 1) [L991] COND FALSE !(E_6 == 1) [L996] COND FALSE !(E_7 == 1) [L1001] COND FALSE !(E_8 == 1) [L1262] COND TRUE 1 [L1265] kernel_st = 1 [L677] int tmp ; ----- ----- class de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder.RCFGBacktranslator [?] assume !false; [?] havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~9;havoc exists_runnable_thread_~__retres1~9; [?] assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9 := 1; [?] exists_runnable_thread_#res := exists_runnable_thread_~__retres1~9; [?] eval_#t~ret0 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret0;havoc eval_#t~ret0; [?] assume 0 != eval_~tmp~0; [?] assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0;eval_~tmp_ndt_1~0 := eval_#t~nondet1;havoc eval_#t~nondet1; [?] assume !(0 != eval_~tmp_ndt_1~0); [?] assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0;eval_~tmp_ndt_2~0 := eval_#t~nondet2;havoc eval_#t~nondet2; [?] assume !(0 != eval_~tmp_ndt_2~0); [?] assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0;eval_~tmp_ndt_3~0 := eval_#t~nondet3;havoc eval_#t~nondet3; [?] assume !(0 != eval_~tmp_ndt_3~0); [?] assume 0 == ~t3_st~0;havoc eval_~tmp_ndt_4~0;eval_~tmp_ndt_4~0 := eval_#t~nondet4;havoc eval_#t~nondet4; [?] assume !(0 != eval_~tmp_ndt_4~0); [?] assume 0 == ~t4_st~0;havoc eval_~tmp_ndt_5~0;eval_~tmp_ndt_5~0 := eval_#t~nondet5;havoc eval_#t~nondet5; [?] assume !(0 != eval_~tmp_ndt_5~0); [?] assume 0 == ~t5_st~0;havoc eval_~tmp_ndt_6~0;eval_~tmp_ndt_6~0 := eval_#t~nondet6;havoc eval_#t~nondet6; [?] assume !(0 != eval_~tmp_ndt_6~0); [?] assume 0 == ~t6_st~0;havoc eval_~tmp_ndt_7~0;eval_~tmp_ndt_7~0 := eval_#t~nondet7;havoc eval_#t~nondet7; [?] assume !(0 != eval_~tmp_ndt_7~0); [?] assume 0 == ~t7_st~0;havoc eval_~tmp_ndt_8~0;eval_~tmp_ndt_8~0 := eval_#t~nondet8;havoc eval_#t~nondet8; [?] assume !(0 != eval_~tmp_ndt_8~0); [?] assume 0 == ~t8_st~0;havoc eval_~tmp_ndt_9~0;eval_~tmp_ndt_9~0 := eval_#t~nondet9;havoc eval_#t~nondet9; [?] assume !(0 != eval_~tmp_ndt_9~0); [L681-L817] assume !false; [L684] havoc exists_runnable_thread_#res; [L684] havoc exists_runnable_thread_~__retres1~9; [L621] havoc exists_runnable_thread_~__retres1~9; [L624-L669] assume 0 == ~m_st~0; [L625] exists_runnable_thread_~__retres1~9 := 1; [L672] exists_runnable_thread_#res := exists_runnable_thread_~__retres1~9; [L684] eval_#t~ret0 := exists_runnable_thread_#res; [L684] eval_~tmp~0 := eval_#t~ret0; [L684] havoc eval_#t~ret0; [L686-L690] assume 0 != eval_~tmp~0; [L691-L704] assume 0 == ~m_st~0; [L692] havoc eval_~tmp_ndt_1~0; [L693] eval_~tmp_ndt_1~0 := eval_#t~nondet1; [L693] havoc eval_#t~nondet1; [L694-L701] assume !(0 != eval_~tmp_ndt_1~0); [L705-L718] assume 0 == ~t1_st~0; [L706] havoc eval_~tmp_ndt_2~0; [L707] eval_~tmp_ndt_2~0 := eval_#t~nondet2; [L707] havoc eval_#t~nondet2; [L708-L715] assume !(0 != eval_~tmp_ndt_2~0); [L719-L732] assume 0 == ~t2_st~0; [L720] havoc eval_~tmp_ndt_3~0; [L721] eval_~tmp_ndt_3~0 := eval_#t~nondet3; [L721] havoc eval_#t~nondet3; [L722-L729] assume !(0 != eval_~tmp_ndt_3~0); [L733-L746] assume 0 == ~t3_st~0; [L734] havoc eval_~tmp_ndt_4~0; [L735] eval_~tmp_ndt_4~0 := eval_#t~nondet4; [L735] havoc eval_#t~nondet4; [L736-L743] assume !(0 != eval_~tmp_ndt_4~0); [L747-L760] assume 0 == ~t4_st~0; [L748] havoc eval_~tmp_ndt_5~0; [L749] eval_~tmp_ndt_5~0 := eval_#t~nondet5; [L749] havoc eval_#t~nondet5; [L750-L757] assume !(0 != eval_~tmp_ndt_5~0); [L761-L774] assume 0 == ~t5_st~0; [L762] havoc eval_~tmp_ndt_6~0; [L763] eval_~tmp_ndt_6~0 := eval_#t~nondet6; [L763] havoc eval_#t~nondet6; [L764-L771] assume !(0 != eval_~tmp_ndt_6~0); [L775-L788] assume 0 == ~t6_st~0; [L776] havoc eval_~tmp_ndt_7~0; [L777] eval_~tmp_ndt_7~0 := eval_#t~nondet7; [L777] havoc eval_#t~nondet7; [L778-L785] assume !(0 != eval_~tmp_ndt_7~0); [L789-L802] assume 0 == ~t7_st~0; [L790] havoc eval_~tmp_ndt_8~0; [L791] eval_~tmp_ndt_8~0 := eval_#t~nondet8; [L791] havoc eval_#t~nondet8; [L792-L799] assume !(0 != eval_~tmp_ndt_8~0); [L803-L816] assume 0 == ~t8_st~0; [L804] havoc eval_~tmp_ndt_9~0; [L805] eval_~tmp_ndt_9~0 := eval_#t~nondet9; [L805] havoc eval_#t~nondet9; [L806-L813] assume !(0 != eval_~tmp_ndt_9~0); ----- ----- class de.uni_freiburg.informatik.ultimate.boogie.preprocessor.BoogiePreprocessorBacktranslator [L681-L817] assume !false; [L684] havoc exists_runnable_thread_#res; [L684] havoc exists_runnable_thread_~__retres1~9; [L621] havoc exists_runnable_thread_~__retres1~9; [L624-L669] assume 0 == ~m_st~0; [L625] exists_runnable_thread_~__retres1~9 := 1; [L672] exists_runnable_thread_#res := exists_runnable_thread_~__retres1~9; [L684] eval_#t~ret0 := exists_runnable_thread_#res; [L684] eval_~tmp~0 := eval_#t~ret0; [L684] havoc eval_#t~ret0; [L686-L690] assume 0 != eval_~tmp~0; [L691-L704] assume 0 == ~m_st~0; [L692] havoc eval_~tmp_ndt_1~0; [L693] eval_~tmp_ndt_1~0 := eval_#t~nondet1; [L693] havoc eval_#t~nondet1; [L694-L701] assume !(0 != eval_~tmp_ndt_1~0); [L705-L718] assume 0 == ~t1_st~0; [L706] havoc eval_~tmp_ndt_2~0; [L707] eval_~tmp_ndt_2~0 := eval_#t~nondet2; [L707] havoc eval_#t~nondet2; [L708-L715] assume !(0 != eval_~tmp_ndt_2~0); [L719-L732] assume 0 == ~t2_st~0; [L720] havoc eval_~tmp_ndt_3~0; [L721] eval_~tmp_ndt_3~0 := eval_#t~nondet3; [L721] havoc eval_#t~nondet3; [L722-L729] assume !(0 != eval_~tmp_ndt_3~0); [L733-L746] assume 0 == ~t3_st~0; [L734] havoc eval_~tmp_ndt_4~0; [L735] eval_~tmp_ndt_4~0 := eval_#t~nondet4; [L735] havoc eval_#t~nondet4; [L736-L743] assume !(0 != eval_~tmp_ndt_4~0); [L747-L760] assume 0 == ~t4_st~0; [L748] havoc eval_~tmp_ndt_5~0; [L749] eval_~tmp_ndt_5~0 := eval_#t~nondet5; [L749] havoc eval_#t~nondet5; [L750-L757] assume !(0 != eval_~tmp_ndt_5~0); [L761-L774] assume 0 == ~t5_st~0; [L762] havoc eval_~tmp_ndt_6~0; [L763] eval_~tmp_ndt_6~0 := eval_#t~nondet6; [L763] havoc eval_#t~nondet6; [L764-L771] assume !(0 != eval_~tmp_ndt_6~0); [L775-L788] assume 0 == ~t6_st~0; [L776] havoc eval_~tmp_ndt_7~0; [L777] eval_~tmp_ndt_7~0 := eval_#t~nondet7; [L777] havoc eval_#t~nondet7; [L778-L785] assume !(0 != eval_~tmp_ndt_7~0); [L789-L802] assume 0 == ~t7_st~0; [L790] havoc eval_~tmp_ndt_8~0; [L791] eval_~tmp_ndt_8~0 := eval_#t~nondet8; [L791] havoc eval_#t~nondet8; [L792-L799] assume !(0 != eval_~tmp_ndt_8~0); [L803-L816] assume 0 == ~t8_st~0; [L804] havoc eval_~tmp_ndt_9~0; [L805] eval_~tmp_ndt_9~0 := eval_#t~nondet9; [L805] havoc eval_#t~nondet9; [L806-L813] assume !(0 != eval_~tmp_ndt_9~0); [L681-L817] COND FALSE !(false) [L684] havoc exists_runnable_thread_#res; [L684] havoc exists_runnable_thread_~__retres1~9; [L621] havoc exists_runnable_thread_~__retres1~9; [L624] COND TRUE 0 == ~m_st~0 [L625] exists_runnable_thread_~__retres1~9 := 1; [L672] exists_runnable_thread_#res := exists_runnable_thread_~__retres1~9; [L684] eval_#t~ret0 := exists_runnable_thread_#res; [L684] eval_~tmp~0 := eval_#t~ret0; [L684] havoc eval_#t~ret0; [L686-L690] COND TRUE 0 != eval_~tmp~0 [L691] COND TRUE 0 == ~m_st~0 [L692] havoc eval_~tmp_ndt_1~0; [L693] eval_~tmp_ndt_1~0 := eval_#t~nondet1; [L693] havoc eval_#t~nondet1; [L694-L701] COND FALSE !(0 != eval_~tmp_ndt_1~0) [L705] COND TRUE 0 == ~t1_st~0 [L706] havoc eval_~tmp_ndt_2~0; [L707] eval_~tmp_ndt_2~0 := eval_#t~nondet2; [L707] havoc eval_#t~nondet2; [L708-L715] COND FALSE !(0 != eval_~tmp_ndt_2~0) [L719] COND TRUE 0 == ~t2_st~0 [L720] havoc eval_~tmp_ndt_3~0; [L721] eval_~tmp_ndt_3~0 := eval_#t~nondet3; [L721] havoc eval_#t~nondet3; [L722-L729] COND FALSE !(0 != eval_~tmp_ndt_3~0) [L733] COND TRUE 0 == ~t3_st~0 [L734] havoc eval_~tmp_ndt_4~0; [L735] eval_~tmp_ndt_4~0 := eval_#t~nondet4; [L735] havoc eval_#t~nondet4; [L736-L743] COND FALSE !(0 != eval_~tmp_ndt_4~0) [L747] COND TRUE 0 == ~t4_st~0 [L748] havoc eval_~tmp_ndt_5~0; [L749] eval_~tmp_ndt_5~0 := eval_#t~nondet5; [L749] havoc eval_#t~nondet5; [L750-L757] COND FALSE !(0 != eval_~tmp_ndt_5~0) [L761] COND TRUE 0 == ~t5_st~0 [L762] havoc eval_~tmp_ndt_6~0; [L763] eval_~tmp_ndt_6~0 := eval_#t~nondet6; [L763] havoc eval_#t~nondet6; [L764-L771] COND FALSE !(0 != eval_~tmp_ndt_6~0) [L775] COND TRUE 0 == ~t6_st~0 [L776] havoc eval_~tmp_ndt_7~0; [L777] eval_~tmp_ndt_7~0 := eval_#t~nondet7; [L777] havoc eval_#t~nondet7; [L778-L785] COND FALSE !(0 != eval_~tmp_ndt_7~0) [L789] COND TRUE 0 == ~t7_st~0 [L790] havoc eval_~tmp_ndt_8~0; [L791] eval_~tmp_ndt_8~0 := eval_#t~nondet8; [L791] havoc eval_#t~nondet8; [L792-L799] COND FALSE !(0 != eval_~tmp_ndt_8~0) [L803] COND TRUE 0 == ~t8_st~0 [L804] havoc eval_~tmp_ndt_9~0; [L805] eval_~tmp_ndt_9~0 := eval_#t~nondet9; [L805] havoc eval_#t~nondet9; [L806-L813] COND FALSE !(0 != eval_~tmp_ndt_9~0) ----- ----- class de.uni_freiburg.informatik.ultimate.boogie.procedureinliner.backtranslation.InlinerBacktranslator [L681-L817] COND FALSE !(false) [L684] havoc exists_runnable_thread_#res; [L684] havoc exists_runnable_thread_~__retres1~9; [L621] havoc exists_runnable_thread_~__retres1~9; [L624] COND TRUE 0 == ~m_st~0 [L625] exists_runnable_thread_~__retres1~9 := 1; [L672] exists_runnable_thread_#res := exists_runnable_thread_~__retres1~9; [L684] eval_#t~ret0 := exists_runnable_thread_#res; [L684] eval_~tmp~0 := eval_#t~ret0; [L684] havoc eval_#t~ret0; [L686-L690] COND TRUE 0 != eval_~tmp~0 [L691] COND TRUE 0 == ~m_st~0 [L692] havoc eval_~tmp_ndt_1~0; [L693] eval_~tmp_ndt_1~0 := eval_#t~nondet1; [L693] havoc eval_#t~nondet1; [L694-L701] COND FALSE !(0 != eval_~tmp_ndt_1~0) [L705] COND TRUE 0 == ~t1_st~0 [L706] havoc eval_~tmp_ndt_2~0; [L707] eval_~tmp_ndt_2~0 := eval_#t~nondet2; [L707] havoc eval_#t~nondet2; [L708-L715] COND FALSE !(0 != eval_~tmp_ndt_2~0) [L719] COND TRUE 0 == ~t2_st~0 [L720] havoc eval_~tmp_ndt_3~0; [L721] eval_~tmp_ndt_3~0 := eval_#t~nondet3; [L721] havoc eval_#t~nondet3; [L722-L729] COND FALSE !(0 != eval_~tmp_ndt_3~0) [L733] COND TRUE 0 == ~t3_st~0 [L734] havoc eval_~tmp_ndt_4~0; [L735] eval_~tmp_ndt_4~0 := eval_#t~nondet4; [L735] havoc eval_#t~nondet4; [L736-L743] COND FALSE !(0 != eval_~tmp_ndt_4~0) [L747] COND TRUE 0 == ~t4_st~0 [L748] havoc eval_~tmp_ndt_5~0; [L749] eval_~tmp_ndt_5~0 := eval_#t~nondet5; [L749] havoc eval_#t~nondet5; [L750-L757] COND FALSE !(0 != eval_~tmp_ndt_5~0) [L761] COND TRUE 0 == ~t5_st~0 [L762] havoc eval_~tmp_ndt_6~0; [L763] eval_~tmp_ndt_6~0 := eval_#t~nondet6; [L763] havoc eval_#t~nondet6; [L764-L771] COND FALSE !(0 != eval_~tmp_ndt_6~0) [L775] COND TRUE 0 == ~t6_st~0 [L776] havoc eval_~tmp_ndt_7~0; [L777] eval_~tmp_ndt_7~0 := eval_#t~nondet7; [L777] havoc eval_#t~nondet7; [L778-L785] COND FALSE !(0 != eval_~tmp_ndt_7~0) [L789] COND TRUE 0 == ~t7_st~0 [L790] havoc eval_~tmp_ndt_8~0; [L791] eval_~tmp_ndt_8~0 := eval_#t~nondet8; [L791] havoc eval_#t~nondet8; [L792-L799] COND FALSE !(0 != eval_~tmp_ndt_8~0) [L803] COND TRUE 0 == ~t8_st~0 [L804] havoc eval_~tmp_ndt_9~0; [L805] eval_~tmp_ndt_9~0 := eval_#t~nondet9; [L805] havoc eval_#t~nondet9; [L806-L813] COND FALSE !(0 != eval_~tmp_ndt_9~0) [L681-L817] COND FALSE !(false) [L621] havoc ~__retres1~9; [L624] COND TRUE 0 == ~m_st~0 [L625] ~__retres1~9 := 1; [L672] #res := ~__retres1~9; [L684] ~tmp~0 := #t~ret0; [L684] havoc #t~ret0; [L686-L690] COND TRUE 0 != ~tmp~0 [L691] COND TRUE 0 == ~m_st~0 [L692] havoc ~tmp_ndt_1~0; [L693] ~tmp_ndt_1~0 := #t~nondet1; [L693] havoc #t~nondet1; [L694-L701] COND FALSE !(0 != ~tmp_ndt_1~0) [L705] COND TRUE 0 == ~t1_st~0 [L706] havoc ~tmp_ndt_2~0; [L707] ~tmp_ndt_2~0 := #t~nondet2; [L707] havoc #t~nondet2; [L708-L715] COND FALSE !(0 != ~tmp_ndt_2~0) [L719] COND TRUE 0 == ~t2_st~0 [L720] havoc ~tmp_ndt_3~0; [L721] ~tmp_ndt_3~0 := #t~nondet3; [L721] havoc #t~nondet3; [L722-L729] COND FALSE !(0 != ~tmp_ndt_3~0) [L733] COND TRUE 0 == ~t3_st~0 [L734] havoc ~tmp_ndt_4~0; [L735] ~tmp_ndt_4~0 := #t~nondet4; [L735] havoc #t~nondet4; [L736-L743] COND FALSE !(0 != ~tmp_ndt_4~0) [L747] COND TRUE 0 == ~t4_st~0 [L748] havoc ~tmp_ndt_5~0; [L749] ~tmp_ndt_5~0 := #t~nondet5; [L749] havoc #t~nondet5; [L750-L757] COND FALSE !(0 != ~tmp_ndt_5~0) [L761] COND TRUE 0 == ~t5_st~0 [L762] havoc ~tmp_ndt_6~0; [L763] ~tmp_ndt_6~0 := #t~nondet6; [L763] havoc #t~nondet6; [L764-L771] COND FALSE !(0 != ~tmp_ndt_6~0) [L775] COND TRUE 0 == ~t6_st~0 [L776] havoc ~tmp_ndt_7~0; [L777] ~tmp_ndt_7~0 := #t~nondet7; [L777] havoc #t~nondet7; [L778-L785] COND FALSE !(0 != ~tmp_ndt_7~0) [L789] COND TRUE 0 == ~t7_st~0 [L790] havoc ~tmp_ndt_8~0; [L791] ~tmp_ndt_8~0 := #t~nondet8; [L791] havoc #t~nondet8; [L792-L799] COND FALSE !(0 != ~tmp_ndt_8~0) [L803] COND TRUE 0 == ~t8_st~0 [L804] havoc ~tmp_ndt_9~0; [L805] ~tmp_ndt_9~0 := #t~nondet9; [L805] havoc #t~nondet9; [L806-L813] COND FALSE !(0 != ~tmp_ndt_9~0) ----- ----- class de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.CACSL2BoogieBacktranslator [L681-L817] COND FALSE !(false) [L621] havoc ~__retres1~9; [L624] COND TRUE 0 == ~m_st~0 [L625] ~__retres1~9 := 1; [L672] #res := ~__retres1~9; [L684] ~tmp~0 := #t~ret0; [L684] havoc #t~ret0; [L686-L690] COND TRUE 0 != ~tmp~0 [L691] COND TRUE 0 == ~m_st~0 [L692] havoc ~tmp_ndt_1~0; [L693] ~tmp_ndt_1~0 := #t~nondet1; [L693] havoc #t~nondet1; [L694-L701] COND FALSE !(0 != ~tmp_ndt_1~0) [L705] COND TRUE 0 == ~t1_st~0 [L706] havoc ~tmp_ndt_2~0; [L707] ~tmp_ndt_2~0 := #t~nondet2; [L707] havoc #t~nondet2; [L708-L715] COND FALSE !(0 != ~tmp_ndt_2~0) [L719] COND TRUE 0 == ~t2_st~0 [L720] havoc ~tmp_ndt_3~0; [L721] ~tmp_ndt_3~0 := #t~nondet3; [L721] havoc #t~nondet3; [L722-L729] COND FALSE !(0 != ~tmp_ndt_3~0) [L733] COND TRUE 0 == ~t3_st~0 [L734] havoc ~tmp_ndt_4~0; [L735] ~tmp_ndt_4~0 := #t~nondet4; [L735] havoc #t~nondet4; [L736-L743] COND FALSE !(0 != ~tmp_ndt_4~0) [L747] COND TRUE 0 == ~t4_st~0 [L748] havoc ~tmp_ndt_5~0; [L749] ~tmp_ndt_5~0 := #t~nondet5; [L749] havoc #t~nondet5; [L750-L757] COND FALSE !(0 != ~tmp_ndt_5~0) [L761] COND TRUE 0 == ~t5_st~0 [L762] havoc ~tmp_ndt_6~0; [L763] ~tmp_ndt_6~0 := #t~nondet6; [L763] havoc #t~nondet6; [L764-L771] COND FALSE !(0 != ~tmp_ndt_6~0) [L775] COND TRUE 0 == ~t6_st~0 [L776] havoc ~tmp_ndt_7~0; [L777] ~tmp_ndt_7~0 := #t~nondet7; [L777] havoc #t~nondet7; [L778-L785] COND FALSE !(0 != ~tmp_ndt_7~0) [L789] COND TRUE 0 == ~t7_st~0 [L790] havoc ~tmp_ndt_8~0; [L791] ~tmp_ndt_8~0 := #t~nondet8; [L791] havoc #t~nondet8; [L792-L799] COND FALSE !(0 != ~tmp_ndt_8~0) [L803] COND TRUE 0 == ~t8_st~0 [L804] havoc ~tmp_ndt_9~0; [L805] ~tmp_ndt_9~0 := #t~nondet9; [L805] havoc #t~nondet9; [L806-L813] COND FALSE !(0 != ~tmp_ndt_9~0) [L681] COND TRUE 1 [L621] int __retres1 ; [L624] COND TRUE m_st == 0 [L625] __retres1 = 1 [L672] return (__retres1); [L684] tmp = exists_runnable_thread() [L686] COND TRUE \read(tmp) [L691] COND TRUE m_st == 0 [L692] int tmp_ndt_1; [L693] tmp_ndt_1 = __VERIFIER_nondet_int() [L694] COND FALSE !(\read(tmp_ndt_1)) [L705] COND TRUE t1_st == 0 [L706] int tmp_ndt_2; [L707] tmp_ndt_2 = __VERIFIER_nondet_int() [L708] COND FALSE !(\read(tmp_ndt_2)) [L719] COND TRUE t2_st == 0 [L720] int tmp_ndt_3; [L721] tmp_ndt_3 = __VERIFIER_nondet_int() [L722] COND FALSE !(\read(tmp_ndt_3)) [L733] COND TRUE t3_st == 0 [L734] int tmp_ndt_4; [L735] tmp_ndt_4 = __VERIFIER_nondet_int() [L736] COND FALSE !(\read(tmp_ndt_4)) [L747] COND TRUE t4_st == 0 [L748] int tmp_ndt_5; [L749] tmp_ndt_5 = __VERIFIER_nondet_int() [L750] COND FALSE !(\read(tmp_ndt_5)) [L761] COND TRUE t5_st == 0 [L762] int tmp_ndt_6; [L763] tmp_ndt_6 = __VERIFIER_nondet_int() [L764] COND FALSE !(\read(tmp_ndt_6)) [L775] COND TRUE t6_st == 0 [L776] int tmp_ndt_7; [L777] tmp_ndt_7 = __VERIFIER_nondet_int() [L778] COND FALSE !(\read(tmp_ndt_7)) [L789] COND TRUE t7_st == 0 [L790] int tmp_ndt_8; [L791] tmp_ndt_8 = __VERIFIER_nondet_int() [L792] COND FALSE !(\read(tmp_ndt_8)) [L803] COND TRUE t8_st == 0 [L804] int tmp_ndt_9; [L805] tmp_ndt_9 = __VERIFIER_nondet_int() [L806] COND FALSE !(\read(tmp_ndt_9)) ----- [2018-11-22 21:24:15,287 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer CFG 22.11 09:24:15 BoogieIcfgContainer [2018-11-22 21:24:15,379 INFO L132 PluginConnector]: ------------------------ END BuchiAutomizer---------------------------- [2018-11-22 21:24:15,379 INFO L113 PluginConnector]: ------------------------Witness Printer---------------------------- [2018-11-22 21:24:15,379 INFO L271 PluginConnector]: Initializing Witness Printer... [2018-11-22 21:24:15,379 INFO L276 PluginConnector]: Witness Printer initialized [2018-11-22 21:24:15,380 INFO L185 PluginConnector]: Executing the observer RCFGCatcher from plugin Witness Printer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 22.11 09:21:33" (3/4) ... [2018-11-22 21:24:15,382 INFO L141 WitnessPrinter]: Generating witness for non-termination counterexample ----- class de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder.RCFGBacktranslator [?] ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2; [?] havoc main_#res;havoc main_~__retres1~10;havoc main_~__retres1~10;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; [?] havoc start_simulation_#t~ret20, start_simulation_#t~ret21, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; [?] assume 1 == ~m_i~0;~m_st~0 := 0; [?] assume 1 == ~t1_i~0;~t1_st~0 := 0; [?] assume 1 == ~t2_i~0;~t2_st~0 := 0; [?] assume 1 == ~t3_i~0;~t3_st~0 := 0; [?] assume 1 == ~t4_i~0;~t4_st~0 := 0; [?] assume 1 == ~t5_i~0;~t5_st~0 := 0; [?] assume 1 == ~t6_i~0;~t6_st~0 := 0; [?] assume 1 == ~t7_i~0;~t7_st~0 := 0; [?] assume 1 == ~t8_i~0;~t8_st~0 := 0; [?] assume !(0 == ~M_E~0); [?] assume !(0 == ~T1_E~0); [?] assume !(0 == ~T2_E~0); [?] assume !(0 == ~T3_E~0); [?] assume !(0 == ~T4_E~0); [?] assume !(0 == ~T5_E~0); [?] assume !(0 == ~T6_E~0); [?] assume !(0 == ~T7_E~0); [?] assume !(0 == ~T8_E~0); [?] assume !(0 == ~E_1~0); [?] assume !(0 == ~E_2~0); [?] assume !(0 == ~E_3~0); [?] assume !(0 == ~E_4~0); [?] assume !(0 == ~E_5~0); [?] assume !(0 == ~E_6~0); [?] assume !(0 == ~E_7~0); [?] assume !(0 == ~E_8~0); [?] havoc activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; [?] assume !(1 == ~m_pc~0); [?] is_master_triggered_~__retres1~0 := 0; [?] is_master_triggered_#res := is_master_triggered_~__retres1~0; [?] activate_threads_#t~ret10 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; [?] assume !(0 != activate_threads_~tmp~1); [?] havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; [?] assume !(1 == ~t1_pc~0); [?] is_transmit1_triggered_~__retres1~1 := 0; [?] is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; [?] activate_threads_#t~ret11 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; [?] assume !(0 != activate_threads_~tmp___0~0); [?] havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; [?] assume !(1 == ~t2_pc~0); [?] is_transmit2_triggered_~__retres1~2 := 0; [?] is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; [?] activate_threads_#t~ret12 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; [?] assume !(0 != activate_threads_~tmp___1~0); [?] havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; [?] assume !(1 == ~t3_pc~0); [?] is_transmit3_triggered_~__retres1~3 := 0; [?] is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; [?] activate_threads_#t~ret13 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; [?] assume !(0 != activate_threads_~tmp___2~0); [?] havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; [?] assume !(1 == ~t4_pc~0); [?] is_transmit4_triggered_~__retres1~4 := 0; [?] is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; [?] activate_threads_#t~ret14 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; [?] assume !(0 != activate_threads_~tmp___3~0); [?] havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; [?] assume !(1 == ~t5_pc~0); [?] is_transmit5_triggered_~__retres1~5 := 0; [?] is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; [?] activate_threads_#t~ret15 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; [?] assume !(0 != activate_threads_~tmp___4~0); [?] havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; [?] assume !(1 == ~t6_pc~0); [?] is_transmit6_triggered_~__retres1~6 := 0; [?] is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; [?] activate_threads_#t~ret16 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; [?] assume !(0 != activate_threads_~tmp___5~0); [?] havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; [?] assume !(1 == ~t7_pc~0); [?] is_transmit7_triggered_~__retres1~7 := 0; [?] is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; [?] activate_threads_#t~ret17 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; [?] assume !(0 != activate_threads_~tmp___6~0); [?] havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; [?] assume !(1 == ~t8_pc~0); [?] is_transmit8_triggered_~__retres1~8 := 0; [?] is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; [?] activate_threads_#t~ret18 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; [?] assume !(0 != activate_threads_~tmp___7~0); [?] assume !(1 == ~M_E~0); [?] assume !(1 == ~T1_E~0); [?] assume !(1 == ~T2_E~0); [?] assume !(1 == ~T3_E~0); [?] assume !(1 == ~T4_E~0); [?] assume !(1 == ~T5_E~0); [?] assume !(1 == ~T6_E~0); [?] assume !(1 == ~T7_E~0); [?] assume !(1 == ~T8_E~0); [?] assume !(1 == ~E_1~0); [?] assume !(1 == ~E_2~0); [?] assume !(1 == ~E_3~0); [?] assume !(1 == ~E_4~0); [?] assume !(1 == ~E_5~0); [?] assume !(1 == ~E_6~0); [?] assume !(1 == ~E_7~0); [?] assume !(1 == ~E_8~0); [?] assume !false; [?] start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret0, eval_#t~nondet1, eval_~tmp_ndt_1~0, eval_#t~nondet2, eval_~tmp_ndt_2~0, eval_#t~nondet3, eval_~tmp_ndt_3~0, eval_#t~nondet4, eval_~tmp_ndt_4~0, eval_#t~nondet5, eval_~tmp_ndt_5~0, eval_#t~nondet6, eval_~tmp_ndt_6~0, eval_#t~nondet7, eval_~tmp_ndt_7~0, eval_#t~nondet8, eval_~tmp_ndt_8~0, eval_#t~nondet9, eval_~tmp_ndt_9~0, eval_~tmp~0;havoc eval_~tmp~0; [L15] ~m_pc~0 := 0; [L16] ~t1_pc~0 := 0; [L17] ~t2_pc~0 := 0; [L18] ~t3_pc~0 := 0; [L19] ~t4_pc~0 := 0; [L20] ~t5_pc~0 := 0; [L21] ~t6_pc~0 := 0; [L22] ~t7_pc~0 := 0; [L23] ~t8_pc~0 := 0; [L24] ~m_st~0 := 0; [L25] ~t1_st~0 := 0; [L26] ~t2_st~0 := 0; [L27] ~t3_st~0 := 0; [L28] ~t4_st~0 := 0; [L29] ~t5_st~0 := 0; [L30] ~t6_st~0 := 0; [L31] ~t7_st~0 := 0; [L32] ~t8_st~0 := 0; [L33] ~m_i~0 := 0; [L34] ~t1_i~0 := 0; [L35] ~t2_i~0 := 0; [L36] ~t3_i~0 := 0; [L37] ~t4_i~0 := 0; [L38] ~t5_i~0 := 0; [L39] ~t6_i~0 := 0; [L40] ~t7_i~0 := 0; [L41] ~t8_i~0 := 0; [L42] ~M_E~0 := 2; [L43] ~T1_E~0 := 2; [L44] ~T2_E~0 := 2; [L45] ~T3_E~0 := 2; [L46] ~T4_E~0 := 2; [L47] ~T5_E~0 := 2; [L48] ~T6_E~0 := 2; [L49] ~T7_E~0 := 2; [L50] ~T8_E~0 := 2; [L51] ~E_1~0 := 2; [L52] ~E_2~0 := 2; [L53] ~E_3~0 := 2; [L54] ~E_4~0 := 2; [L55] ~E_5~0 := 2; [L56] ~E_6~0 := 2; [L57] ~E_7~0 := 2; [L58] ~E_8~0 := 2; [?] havoc main_#res; [?] havoc main_~__retres1~10; [L1307] havoc main_~__retres1~10; [L1215] ~m_i~0 := 1; [L1216] ~t1_i~0 := 1; [L1217] ~t2_i~0 := 1; [L1218] ~t3_i~0 := 1; [L1219] ~t4_i~0 := 1; [L1220] ~t5_i~0 := 1; [L1221] ~t6_i~0 := 1; [L1222] ~t7_i~0 := 1; [L1223] ~t8_i~0 := 1; [L1312] havoc start_simulation_#t~ret20, start_simulation_#t~ret21, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1; [L1248] havoc start_simulation_~kernel_st~0; [L1249] havoc start_simulation_~tmp~3; [L1250] havoc start_simulation_~tmp___0~1; [L1254] start_simulation_~kernel_st~0 := 0; [L571-L575] assume 1 == ~m_i~0; [L572] ~m_st~0 := 0; [L576-L580] assume 1 == ~t1_i~0; [L577] ~t1_st~0 := 0; [L581-L585] assume 1 == ~t2_i~0; [L582] ~t2_st~0 := 0; [L586-L590] assume 1 == ~t3_i~0; [L587] ~t3_st~0 := 0; [L591-L595] assume 1 == ~t4_i~0; [L592] ~t4_st~0 := 0; [L596-L600] assume 1 == ~t5_i~0; [L597] ~t5_st~0 := 0; [L601-L605] assume 1 == ~t6_i~0; [L602] ~t6_st~0 := 0; [L606-L610] assume 1 == ~t7_i~0; [L607] ~t7_st~0 := 0; [L611-L615] assume 1 == ~t8_i~0; [L612] ~t8_st~0 := 0; [L828-L832] assume !(0 == ~M_E~0); [L833-L837] assume !(0 == ~T1_E~0); [L838-L842] assume !(0 == ~T2_E~0); [L843-L847] assume !(0 == ~T3_E~0); [L848-L852] assume !(0 == ~T4_E~0); [L853-L857] assume !(0 == ~T5_E~0); [L858-L862] assume !(0 == ~T6_E~0); [L863-L867] assume !(0 == ~T7_E~0); [L868-L872] assume !(0 == ~T8_E~0); [L873-L877] assume !(0 == ~E_1~0); [L878-L882] assume !(0 == ~E_2~0); [L883-L887] assume !(0 == ~E_3~0); [L888-L892] assume !(0 == ~E_4~0); [L893-L897] assume !(0 == ~E_5~0); [L898-L902] assume !(0 == ~E_6~0); [L903-L907] assume !(0 == ~E_7~0); [L908-L912] assume !(0 == ~E_8~0); [L1258] havoc activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0; [L1011] havoc activate_threads_~tmp~1; [L1012] havoc activate_threads_~tmp___0~0; [L1013] havoc activate_threads_~tmp___1~0; [L1014] havoc activate_threads_~tmp___2~0; [L1015] havoc activate_threads_~tmp___3~0; [L1016] havoc activate_threads_~tmp___4~0; [L1017] havoc activate_threads_~tmp___5~0; [L1018] havoc activate_threads_~tmp___6~0; [L1019] havoc activate_threads_~tmp___7~0; [L1023] havoc is_master_triggered_#res; [L1023] havoc is_master_triggered_~__retres1~0; [L389] havoc is_master_triggered_~__retres1~0; [L392-L401] assume !(1 == ~m_pc~0); [L402] is_master_triggered_~__retres1~0 := 0; [L404] is_master_triggered_#res := is_master_triggered_~__retres1~0; [L1023] activate_threads_#t~ret10 := is_master_triggered_#res; [L1023] activate_threads_~tmp~1 := activate_threads_#t~ret10; [L1023] havoc activate_threads_#t~ret10; [L1025-L1029] assume !(0 != activate_threads_~tmp~1); [L1031] havoc is_transmit1_triggered_#res; [L1031] havoc is_transmit1_triggered_~__retres1~1; [L408] havoc is_transmit1_triggered_~__retres1~1; [L411-L420] assume !(1 == ~t1_pc~0); [L421] is_transmit1_triggered_~__retres1~1 := 0; [L423] is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; [L1031] activate_threads_#t~ret11 := is_transmit1_triggered_#res; [L1031] activate_threads_~tmp___0~0 := activate_threads_#t~ret11; [L1031] havoc activate_threads_#t~ret11; [L1033-L1037] assume !(0 != activate_threads_~tmp___0~0); [L1039] havoc is_transmit2_triggered_#res; [L1039] havoc is_transmit2_triggered_~__retres1~2; [L427] havoc is_transmit2_triggered_~__retres1~2; [L430-L439] assume !(1 == ~t2_pc~0); [L440] is_transmit2_triggered_~__retres1~2 := 0; [L442] is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; [L1039] activate_threads_#t~ret12 := is_transmit2_triggered_#res; [L1039] activate_threads_~tmp___1~0 := activate_threads_#t~ret12; [L1039] havoc activate_threads_#t~ret12; [L1041-L1045] assume !(0 != activate_threads_~tmp___1~0); [L1047] havoc is_transmit3_triggered_#res; [L1047] havoc is_transmit3_triggered_~__retres1~3; [L446] havoc is_transmit3_triggered_~__retres1~3; [L449-L458] assume !(1 == ~t3_pc~0); [L459] is_transmit3_triggered_~__retres1~3 := 0; [L461] is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; [L1047] activate_threads_#t~ret13 := is_transmit3_triggered_#res; [L1047] activate_threads_~tmp___2~0 := activate_threads_#t~ret13; [L1047] havoc activate_threads_#t~ret13; [L1049-L1053] assume !(0 != activate_threads_~tmp___2~0); [L1055] havoc is_transmit4_triggered_#res; [L1055] havoc is_transmit4_triggered_~__retres1~4; [L465] havoc is_transmit4_triggered_~__retres1~4; [L468-L477] assume !(1 == ~t4_pc~0); [L478] is_transmit4_triggered_~__retres1~4 := 0; [L480] is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; [L1055] activate_threads_#t~ret14 := is_transmit4_triggered_#res; [L1055] activate_threads_~tmp___3~0 := activate_threads_#t~ret14; [L1055] havoc activate_threads_#t~ret14; [L1057-L1061] assume !(0 != activate_threads_~tmp___3~0); [L1063] havoc is_transmit5_triggered_#res; [L1063] havoc is_transmit5_triggered_~__retres1~5; [L484] havoc is_transmit5_triggered_~__retres1~5; [L487-L496] assume !(1 == ~t5_pc~0); [L497] is_transmit5_triggered_~__retres1~5 := 0; [L499] is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; [L1063] activate_threads_#t~ret15 := is_transmit5_triggered_#res; [L1063] activate_threads_~tmp___4~0 := activate_threads_#t~ret15; [L1063] havoc activate_threads_#t~ret15; [L1065-L1069] assume !(0 != activate_threads_~tmp___4~0); [L1071] havoc is_transmit6_triggered_#res; [L1071] havoc is_transmit6_triggered_~__retres1~6; [L503] havoc is_transmit6_triggered_~__retres1~6; [L506-L515] assume !(1 == ~t6_pc~0); [L516] is_transmit6_triggered_~__retres1~6 := 0; [L518] is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; [L1071] activate_threads_#t~ret16 := is_transmit6_triggered_#res; [L1071] activate_threads_~tmp___5~0 := activate_threads_#t~ret16; [L1071] havoc activate_threads_#t~ret16; [L1073-L1077] assume !(0 != activate_threads_~tmp___5~0); [L1079] havoc is_transmit7_triggered_#res; [L1079] havoc is_transmit7_triggered_~__retres1~7; [L522] havoc is_transmit7_triggered_~__retres1~7; [L525-L534] assume !(1 == ~t7_pc~0); [L535] is_transmit7_triggered_~__retres1~7 := 0; [L537] is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; [L1079] activate_threads_#t~ret17 := is_transmit7_triggered_#res; [L1079] activate_threads_~tmp___6~0 := activate_threads_#t~ret17; [L1079] havoc activate_threads_#t~ret17; [L1081-L1085] assume !(0 != activate_threads_~tmp___6~0); [L1087] havoc is_transmit8_triggered_#res; [L1087] havoc is_transmit8_triggered_~__retres1~8; [L541] havoc is_transmit8_triggered_~__retres1~8; [L544-L553] assume !(1 == ~t8_pc~0); [L554] is_transmit8_triggered_~__retres1~8 := 0; [L556] is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; [L1087] activate_threads_#t~ret18 := is_transmit8_triggered_#res; [L1087] activate_threads_~tmp___7~0 := activate_threads_#t~ret18; [L1087] havoc activate_threads_#t~ret18; [L1089-L1093] assume !(0 != activate_threads_~tmp___7~0); [L921-L925] assume !(1 == ~M_E~0); [L926-L930] assume !(1 == ~T1_E~0); [L931-L935] assume !(1 == ~T2_E~0); [L936-L940] assume !(1 == ~T3_E~0); [L941-L945] assume !(1 == ~T4_E~0); [L946-L950] assume !(1 == ~T5_E~0); [L951-L955] assume !(1 == ~T6_E~0); [L956-L960] assume !(1 == ~T7_E~0); [L961-L965] assume !(1 == ~T8_E~0); [L966-L970] assume !(1 == ~E_1~0); [L971-L975] assume !(1 == ~E_2~0); [L976-L980] assume !(1 == ~E_3~0); [L981-L985] assume !(1 == ~E_4~0); [L986-L990] assume !(1 == ~E_5~0); [L991-L995] assume !(1 == ~E_6~0); [L996-L1000] assume !(1 == ~E_7~0); [L1001-L1005] assume !(1 == ~E_8~0); [L1262-L1299] assume !false; [L1265] start_simulation_~kernel_st~0 := 1; [L1266] havoc eval_#t~ret0, eval_#t~nondet1, eval_~tmp_ndt_1~0, eval_#t~nondet2, eval_~tmp_ndt_2~0, eval_#t~nondet3, eval_~tmp_ndt_3~0, eval_#t~nondet4, eval_~tmp_ndt_4~0, eval_#t~nondet5, eval_~tmp_ndt_5~0, eval_#t~nondet6, eval_~tmp_ndt_6~0, eval_#t~nondet7, eval_~tmp_ndt_7~0, eval_#t~nondet8, eval_~tmp_ndt_8~0, eval_#t~nondet9, eval_~tmp_ndt_9~0, eval_~tmp~0; [L677] havoc eval_~tmp~0; ----- ----- class de.uni_freiburg.informatik.ultimate.boogie.preprocessor.BoogiePreprocessorBacktranslator [L15] ~m_pc~0 := 0; [L16] ~t1_pc~0 := 0; [L17] ~t2_pc~0 := 0; [L18] ~t3_pc~0 := 0; [L19] ~t4_pc~0 := 0; [L20] ~t5_pc~0 := 0; [L21] ~t6_pc~0 := 0; [L22] ~t7_pc~0 := 0; [L23] ~t8_pc~0 := 0; [L24] ~m_st~0 := 0; [L25] ~t1_st~0 := 0; [L26] ~t2_st~0 := 0; [L27] ~t3_st~0 := 0; [L28] ~t4_st~0 := 0; [L29] ~t5_st~0 := 0; [L30] ~t6_st~0 := 0; [L31] ~t7_st~0 := 0; [L32] ~t8_st~0 := 0; [L33] ~m_i~0 := 0; [L34] ~t1_i~0 := 0; [L35] ~t2_i~0 := 0; [L36] ~t3_i~0 := 0; [L37] ~t4_i~0 := 0; [L38] ~t5_i~0 := 0; [L39] ~t6_i~0 := 0; [L40] ~t7_i~0 := 0; [L41] ~t8_i~0 := 0; [L42] ~M_E~0 := 2; [L43] ~T1_E~0 := 2; [L44] ~T2_E~0 := 2; [L45] ~T3_E~0 := 2; [L46] ~T4_E~0 := 2; [L47] ~T5_E~0 := 2; [L48] ~T6_E~0 := 2; [L49] ~T7_E~0 := 2; [L50] ~T8_E~0 := 2; [L51] ~E_1~0 := 2; [L52] ~E_2~0 := 2; [L53] ~E_3~0 := 2; [L54] ~E_4~0 := 2; [L55] ~E_5~0 := 2; [L56] ~E_6~0 := 2; [L57] ~E_7~0 := 2; [L58] ~E_8~0 := 2; [?] havoc main_#res; [?] havoc main_~__retres1~10; [L1307] havoc main_~__retres1~10; [L1215] ~m_i~0 := 1; [L1216] ~t1_i~0 := 1; [L1217] ~t2_i~0 := 1; [L1218] ~t3_i~0 := 1; [L1219] ~t4_i~0 := 1; [L1220] ~t5_i~0 := 1; [L1221] ~t6_i~0 := 1; [L1222] ~t7_i~0 := 1; [L1223] ~t8_i~0 := 1; [L1312] havoc start_simulation_#t~ret20, start_simulation_#t~ret21, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1; [L1248] havoc start_simulation_~kernel_st~0; [L1249] havoc start_simulation_~tmp~3; [L1250] havoc start_simulation_~tmp___0~1; [L1254] start_simulation_~kernel_st~0 := 0; [L571-L575] assume 1 == ~m_i~0; [L572] ~m_st~0 := 0; [L576-L580] assume 1 == ~t1_i~0; [L577] ~t1_st~0 := 0; [L581-L585] assume 1 == ~t2_i~0; [L582] ~t2_st~0 := 0; [L586-L590] assume 1 == ~t3_i~0; [L587] ~t3_st~0 := 0; [L591-L595] assume 1 == ~t4_i~0; [L592] ~t4_st~0 := 0; [L596-L600] assume 1 == ~t5_i~0; [L597] ~t5_st~0 := 0; [L601-L605] assume 1 == ~t6_i~0; [L602] ~t6_st~0 := 0; [L606-L610] assume 1 == ~t7_i~0; [L607] ~t7_st~0 := 0; [L611-L615] assume 1 == ~t8_i~0; [L612] ~t8_st~0 := 0; [L828-L832] assume !(0 == ~M_E~0); [L833-L837] assume !(0 == ~T1_E~0); [L838-L842] assume !(0 == ~T2_E~0); [L843-L847] assume !(0 == ~T3_E~0); [L848-L852] assume !(0 == ~T4_E~0); [L853-L857] assume !(0 == ~T5_E~0); [L858-L862] assume !(0 == ~T6_E~0); [L863-L867] assume !(0 == ~T7_E~0); [L868-L872] assume !(0 == ~T8_E~0); [L873-L877] assume !(0 == ~E_1~0); [L878-L882] assume !(0 == ~E_2~0); [L883-L887] assume !(0 == ~E_3~0); [L888-L892] assume !(0 == ~E_4~0); [L893-L897] assume !(0 == ~E_5~0); [L898-L902] assume !(0 == ~E_6~0); [L903-L907] assume !(0 == ~E_7~0); [L908-L912] assume !(0 == ~E_8~0); [L1258] havoc activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0; [L1011] havoc activate_threads_~tmp~1; [L1012] havoc activate_threads_~tmp___0~0; [L1013] havoc activate_threads_~tmp___1~0; [L1014] havoc activate_threads_~tmp___2~0; [L1015] havoc activate_threads_~tmp___3~0; [L1016] havoc activate_threads_~tmp___4~0; [L1017] havoc activate_threads_~tmp___5~0; [L1018] havoc activate_threads_~tmp___6~0; [L1019] havoc activate_threads_~tmp___7~0; [L1023] havoc is_master_triggered_#res; [L1023] havoc is_master_triggered_~__retres1~0; [L389] havoc is_master_triggered_~__retres1~0; [L392-L401] assume !(1 == ~m_pc~0); [L402] is_master_triggered_~__retres1~0 := 0; [L404] is_master_triggered_#res := is_master_triggered_~__retres1~0; [L1023] activate_threads_#t~ret10 := is_master_triggered_#res; [L1023] activate_threads_~tmp~1 := activate_threads_#t~ret10; [L1023] havoc activate_threads_#t~ret10; [L1025-L1029] assume !(0 != activate_threads_~tmp~1); [L1031] havoc is_transmit1_triggered_#res; [L1031] havoc is_transmit1_triggered_~__retres1~1; [L408] havoc is_transmit1_triggered_~__retres1~1; [L411-L420] assume !(1 == ~t1_pc~0); [L421] is_transmit1_triggered_~__retres1~1 := 0; [L423] is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; [L1031] activate_threads_#t~ret11 := is_transmit1_triggered_#res; [L1031] activate_threads_~tmp___0~0 := activate_threads_#t~ret11; [L1031] havoc activate_threads_#t~ret11; [L1033-L1037] assume !(0 != activate_threads_~tmp___0~0); [L1039] havoc is_transmit2_triggered_#res; [L1039] havoc is_transmit2_triggered_~__retres1~2; [L427] havoc is_transmit2_triggered_~__retres1~2; [L430-L439] assume !(1 == ~t2_pc~0); [L440] is_transmit2_triggered_~__retres1~2 := 0; [L442] is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; [L1039] activate_threads_#t~ret12 := is_transmit2_triggered_#res; [L1039] activate_threads_~tmp___1~0 := activate_threads_#t~ret12; [L1039] havoc activate_threads_#t~ret12; [L1041-L1045] assume !(0 != activate_threads_~tmp___1~0); [L1047] havoc is_transmit3_triggered_#res; [L1047] havoc is_transmit3_triggered_~__retres1~3; [L446] havoc is_transmit3_triggered_~__retres1~3; [L449-L458] assume !(1 == ~t3_pc~0); [L459] is_transmit3_triggered_~__retres1~3 := 0; [L461] is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; [L1047] activate_threads_#t~ret13 := is_transmit3_triggered_#res; [L1047] activate_threads_~tmp___2~0 := activate_threads_#t~ret13; [L1047] havoc activate_threads_#t~ret13; [L1049-L1053] assume !(0 != activate_threads_~tmp___2~0); [L1055] havoc is_transmit4_triggered_#res; [L1055] havoc is_transmit4_triggered_~__retres1~4; [L465] havoc is_transmit4_triggered_~__retres1~4; [L468-L477] assume !(1 == ~t4_pc~0); [L478] is_transmit4_triggered_~__retres1~4 := 0; [L480] is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; [L1055] activate_threads_#t~ret14 := is_transmit4_triggered_#res; [L1055] activate_threads_~tmp___3~0 := activate_threads_#t~ret14; [L1055] havoc activate_threads_#t~ret14; [L1057-L1061] assume !(0 != activate_threads_~tmp___3~0); [L1063] havoc is_transmit5_triggered_#res; [L1063] havoc is_transmit5_triggered_~__retres1~5; [L484] havoc is_transmit5_triggered_~__retres1~5; [L487-L496] assume !(1 == ~t5_pc~0); [L497] is_transmit5_triggered_~__retres1~5 := 0; [L499] is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; [L1063] activate_threads_#t~ret15 := is_transmit5_triggered_#res; [L1063] activate_threads_~tmp___4~0 := activate_threads_#t~ret15; [L1063] havoc activate_threads_#t~ret15; [L1065-L1069] assume !(0 != activate_threads_~tmp___4~0); [L1071] havoc is_transmit6_triggered_#res; [L1071] havoc is_transmit6_triggered_~__retres1~6; [L503] havoc is_transmit6_triggered_~__retres1~6; [L506-L515] assume !(1 == ~t6_pc~0); [L516] is_transmit6_triggered_~__retres1~6 := 0; [L518] is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; [L1071] activate_threads_#t~ret16 := is_transmit6_triggered_#res; [L1071] activate_threads_~tmp___5~0 := activate_threads_#t~ret16; [L1071] havoc activate_threads_#t~ret16; [L1073-L1077] assume !(0 != activate_threads_~tmp___5~0); [L1079] havoc is_transmit7_triggered_#res; [L1079] havoc is_transmit7_triggered_~__retres1~7; [L522] havoc is_transmit7_triggered_~__retres1~7; [L525-L534] assume !(1 == ~t7_pc~0); [L535] is_transmit7_triggered_~__retres1~7 := 0; [L537] is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; [L1079] activate_threads_#t~ret17 := is_transmit7_triggered_#res; [L1079] activate_threads_~tmp___6~0 := activate_threads_#t~ret17; [L1079] havoc activate_threads_#t~ret17; [L1081-L1085] assume !(0 != activate_threads_~tmp___6~0); [L1087] havoc is_transmit8_triggered_#res; [L1087] havoc is_transmit8_triggered_~__retres1~8; [L541] havoc is_transmit8_triggered_~__retres1~8; [L544-L553] assume !(1 == ~t8_pc~0); [L554] is_transmit8_triggered_~__retres1~8 := 0; [L556] is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; [L1087] activate_threads_#t~ret18 := is_transmit8_triggered_#res; [L1087] activate_threads_~tmp___7~0 := activate_threads_#t~ret18; [L1087] havoc activate_threads_#t~ret18; [L1089-L1093] assume !(0 != activate_threads_~tmp___7~0); [L921-L925] assume !(1 == ~M_E~0); [L926-L930] assume !(1 == ~T1_E~0); [L931-L935] assume !(1 == ~T2_E~0); [L936-L940] assume !(1 == ~T3_E~0); [L941-L945] assume !(1 == ~T4_E~0); [L946-L950] assume !(1 == ~T5_E~0); [L951-L955] assume !(1 == ~T6_E~0); [L956-L960] assume !(1 == ~T7_E~0); [L961-L965] assume !(1 == ~T8_E~0); [L966-L970] assume !(1 == ~E_1~0); [L971-L975] assume !(1 == ~E_2~0); [L976-L980] assume !(1 == ~E_3~0); [L981-L985] assume !(1 == ~E_4~0); [L986-L990] assume !(1 == ~E_5~0); [L991-L995] assume !(1 == ~E_6~0); [L996-L1000] assume !(1 == ~E_7~0); [L1001-L1005] assume !(1 == ~E_8~0); [L1262-L1299] assume !false; [L1265] start_simulation_~kernel_st~0 := 1; [L1266] havoc eval_#t~ret0, eval_#t~nondet1, eval_~tmp_ndt_1~0, eval_#t~nondet2, eval_~tmp_ndt_2~0, eval_#t~nondet3, eval_~tmp_ndt_3~0, eval_#t~nondet4, eval_~tmp_ndt_4~0, eval_#t~nondet5, eval_~tmp_ndt_5~0, eval_#t~nondet6, eval_~tmp_ndt_6~0, eval_#t~nondet7, eval_~tmp_ndt_7~0, eval_#t~nondet8, eval_~tmp_ndt_8~0, eval_#t~nondet9, eval_~tmp_ndt_9~0, eval_~tmp~0; [L677] havoc eval_~tmp~0; [L15] ~m_pc~0 := 0; [L16] ~t1_pc~0 := 0; [L17] ~t2_pc~0 := 0; [L18] ~t3_pc~0 := 0; [L19] ~t4_pc~0 := 0; [L20] ~t5_pc~0 := 0; [L21] ~t6_pc~0 := 0; [L22] ~t7_pc~0 := 0; [L23] ~t8_pc~0 := 0; [L24] ~m_st~0 := 0; [L25] ~t1_st~0 := 0; [L26] ~t2_st~0 := 0; [L27] ~t3_st~0 := 0; [L28] ~t4_st~0 := 0; [L29] ~t5_st~0 := 0; [L30] ~t6_st~0 := 0; [L31] ~t7_st~0 := 0; [L32] ~t8_st~0 := 0; [L33] ~m_i~0 := 0; [L34] ~t1_i~0 := 0; [L35] ~t2_i~0 := 0; [L36] ~t3_i~0 := 0; [L37] ~t4_i~0 := 0; [L38] ~t5_i~0 := 0; [L39] ~t6_i~0 := 0; [L40] ~t7_i~0 := 0; [L41] ~t8_i~0 := 0; [L42] ~M_E~0 := 2; [L43] ~T1_E~0 := 2; [L44] ~T2_E~0 := 2; [L45] ~T3_E~0 := 2; [L46] ~T4_E~0 := 2; [L47] ~T5_E~0 := 2; [L48] ~T6_E~0 := 2; [L49] ~T7_E~0 := 2; [L50] ~T8_E~0 := 2; [L51] ~E_1~0 := 2; [L52] ~E_2~0 := 2; [L53] ~E_3~0 := 2; [L54] ~E_4~0 := 2; [L55] ~E_5~0 := 2; [L56] ~E_6~0 := 2; [L57] ~E_7~0 := 2; [L58] ~E_8~0 := 2; [?] havoc main_#res; [?] havoc main_~__retres1~10; [L1307] havoc main_~__retres1~10; [L1215] ~m_i~0 := 1; [L1216] ~t1_i~0 := 1; [L1217] ~t2_i~0 := 1; [L1218] ~t3_i~0 := 1; [L1219] ~t4_i~0 := 1; [L1220] ~t5_i~0 := 1; [L1221] ~t6_i~0 := 1; [L1222] ~t7_i~0 := 1; [L1223] ~t8_i~0 := 1; [L1312] havoc start_simulation_#t~ret20, start_simulation_#t~ret21, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1; [L1248] havoc start_simulation_~kernel_st~0; [L1249] havoc start_simulation_~tmp~3; [L1250] havoc start_simulation_~tmp___0~1; [L1254] start_simulation_~kernel_st~0 := 0; [L571] COND TRUE 1 == ~m_i~0 [L572] ~m_st~0 := 0; [L576] COND TRUE 1 == ~t1_i~0 [L577] ~t1_st~0 := 0; [L581] COND TRUE 1 == ~t2_i~0 [L582] ~t2_st~0 := 0; [L586] COND TRUE 1 == ~t3_i~0 [L587] ~t3_st~0 := 0; [L591] COND TRUE 1 == ~t4_i~0 [L592] ~t4_st~0 := 0; [L596] COND TRUE 1 == ~t5_i~0 [L597] ~t5_st~0 := 0; [L601] COND TRUE 1 == ~t6_i~0 [L602] ~t6_st~0 := 0; [L606] COND TRUE 1 == ~t7_i~0 [L607] ~t7_st~0 := 0; [L611] COND TRUE 1 == ~t8_i~0 [L612] ~t8_st~0 := 0; [L828] COND FALSE !(0 == ~M_E~0) [L833] COND FALSE !(0 == ~T1_E~0) [L838] COND FALSE !(0 == ~T2_E~0) [L843] COND FALSE !(0 == ~T3_E~0) [L848] COND FALSE !(0 == ~T4_E~0) [L853] COND FALSE !(0 == ~T5_E~0) [L858] COND FALSE !(0 == ~T6_E~0) [L863] COND FALSE !(0 == ~T7_E~0) [L868] COND FALSE !(0 == ~T8_E~0) [L873] COND FALSE !(0 == ~E_1~0) [L878] COND FALSE !(0 == ~E_2~0) [L883] COND FALSE !(0 == ~E_3~0) [L888] COND FALSE !(0 == ~E_4~0) [L893] COND FALSE !(0 == ~E_5~0) [L898] COND FALSE !(0 == ~E_6~0) [L903] COND FALSE !(0 == ~E_7~0) [L908] COND FALSE !(0 == ~E_8~0) [L1258] havoc activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0; [L1011] havoc activate_threads_~tmp~1; [L1012] havoc activate_threads_~tmp___0~0; [L1013] havoc activate_threads_~tmp___1~0; [L1014] havoc activate_threads_~tmp___2~0; [L1015] havoc activate_threads_~tmp___3~0; [L1016] havoc activate_threads_~tmp___4~0; [L1017] havoc activate_threads_~tmp___5~0; [L1018] havoc activate_threads_~tmp___6~0; [L1019] havoc activate_threads_~tmp___7~0; [L1023] havoc is_master_triggered_#res; [L1023] havoc is_master_triggered_~__retres1~0; [L389] havoc is_master_triggered_~__retres1~0; [L392] COND FALSE !(1 == ~m_pc~0) [L402] is_master_triggered_~__retres1~0 := 0; [L404] is_master_triggered_#res := is_master_triggered_~__retres1~0; [L1023] activate_threads_#t~ret10 := is_master_triggered_#res; [L1023] activate_threads_~tmp~1 := activate_threads_#t~ret10; [L1023] havoc activate_threads_#t~ret10; [L1025-L1029] COND FALSE !(0 != activate_threads_~tmp~1) [L1031] havoc is_transmit1_triggered_#res; [L1031] havoc is_transmit1_triggered_~__retres1~1; [L408] havoc is_transmit1_triggered_~__retres1~1; [L411] COND FALSE !(1 == ~t1_pc~0) [L421] is_transmit1_triggered_~__retres1~1 := 0; [L423] is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; [L1031] activate_threads_#t~ret11 := is_transmit1_triggered_#res; [L1031] activate_threads_~tmp___0~0 := activate_threads_#t~ret11; [L1031] havoc activate_threads_#t~ret11; [L1033-L1037] COND FALSE !(0 != activate_threads_~tmp___0~0) [L1039] havoc is_transmit2_triggered_#res; [L1039] havoc is_transmit2_triggered_~__retres1~2; [L427] havoc is_transmit2_triggered_~__retres1~2; [L430] COND FALSE !(1 == ~t2_pc~0) [L440] is_transmit2_triggered_~__retres1~2 := 0; [L442] is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; [L1039] activate_threads_#t~ret12 := is_transmit2_triggered_#res; [L1039] activate_threads_~tmp___1~0 := activate_threads_#t~ret12; [L1039] havoc activate_threads_#t~ret12; [L1041-L1045] COND FALSE !(0 != activate_threads_~tmp___1~0) [L1047] havoc is_transmit3_triggered_#res; [L1047] havoc is_transmit3_triggered_~__retres1~3; [L446] havoc is_transmit3_triggered_~__retres1~3; [L449] COND FALSE !(1 == ~t3_pc~0) [L459] is_transmit3_triggered_~__retres1~3 := 0; [L461] is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; [L1047] activate_threads_#t~ret13 := is_transmit3_triggered_#res; [L1047] activate_threads_~tmp___2~0 := activate_threads_#t~ret13; [L1047] havoc activate_threads_#t~ret13; [L1049-L1053] COND FALSE !(0 != activate_threads_~tmp___2~0) [L1055] havoc is_transmit4_triggered_#res; [L1055] havoc is_transmit4_triggered_~__retres1~4; [L465] havoc is_transmit4_triggered_~__retres1~4; [L468] COND FALSE !(1 == ~t4_pc~0) [L478] is_transmit4_triggered_~__retres1~4 := 0; [L480] is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; [L1055] activate_threads_#t~ret14 := is_transmit4_triggered_#res; [L1055] activate_threads_~tmp___3~0 := activate_threads_#t~ret14; [L1055] havoc activate_threads_#t~ret14; [L1057-L1061] COND FALSE !(0 != activate_threads_~tmp___3~0) [L1063] havoc is_transmit5_triggered_#res; [L1063] havoc is_transmit5_triggered_~__retres1~5; [L484] havoc is_transmit5_triggered_~__retres1~5; [L487] COND FALSE !(1 == ~t5_pc~0) [L497] is_transmit5_triggered_~__retres1~5 := 0; [L499] is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; [L1063] activate_threads_#t~ret15 := is_transmit5_triggered_#res; [L1063] activate_threads_~tmp___4~0 := activate_threads_#t~ret15; [L1063] havoc activate_threads_#t~ret15; [L1065-L1069] COND FALSE !(0 != activate_threads_~tmp___4~0) [L1071] havoc is_transmit6_triggered_#res; [L1071] havoc is_transmit6_triggered_~__retres1~6; [L503] havoc is_transmit6_triggered_~__retres1~6; [L506] COND FALSE !(1 == ~t6_pc~0) [L516] is_transmit6_triggered_~__retres1~6 := 0; [L518] is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; [L1071] activate_threads_#t~ret16 := is_transmit6_triggered_#res; [L1071] activate_threads_~tmp___5~0 := activate_threads_#t~ret16; [L1071] havoc activate_threads_#t~ret16; [L1073-L1077] COND FALSE !(0 != activate_threads_~tmp___5~0) [L1079] havoc is_transmit7_triggered_#res; [L1079] havoc is_transmit7_triggered_~__retres1~7; [L522] havoc is_transmit7_triggered_~__retres1~7; [L525] COND FALSE !(1 == ~t7_pc~0) [L535] is_transmit7_triggered_~__retres1~7 := 0; [L537] is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; [L1079] activate_threads_#t~ret17 := is_transmit7_triggered_#res; [L1079] activate_threads_~tmp___6~0 := activate_threads_#t~ret17; [L1079] havoc activate_threads_#t~ret17; [L1081-L1085] COND FALSE !(0 != activate_threads_~tmp___6~0) [L1087] havoc is_transmit8_triggered_#res; [L1087] havoc is_transmit8_triggered_~__retres1~8; [L541] havoc is_transmit8_triggered_~__retres1~8; [L544] COND FALSE !(1 == ~t8_pc~0) [L554] is_transmit8_triggered_~__retres1~8 := 0; [L556] is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; [L1087] activate_threads_#t~ret18 := is_transmit8_triggered_#res; [L1087] activate_threads_~tmp___7~0 := activate_threads_#t~ret18; [L1087] havoc activate_threads_#t~ret18; [L1089-L1093] COND FALSE !(0 != activate_threads_~tmp___7~0) [L921] COND FALSE !(1 == ~M_E~0) [L926] COND FALSE !(1 == ~T1_E~0) [L931] COND FALSE !(1 == ~T2_E~0) [L936] COND FALSE !(1 == ~T3_E~0) [L941] COND FALSE !(1 == ~T4_E~0) [L946] COND FALSE !(1 == ~T5_E~0) [L951] COND FALSE !(1 == ~T6_E~0) [L956] COND FALSE !(1 == ~T7_E~0) [L961] COND FALSE !(1 == ~T8_E~0) [L966] COND FALSE !(1 == ~E_1~0) [L971] COND FALSE !(1 == ~E_2~0) [L976] COND FALSE !(1 == ~E_3~0) [L981] COND FALSE !(1 == ~E_4~0) [L986] COND FALSE !(1 == ~E_5~0) [L991] COND FALSE !(1 == ~E_6~0) [L996] COND FALSE !(1 == ~E_7~0) [L1001] COND FALSE !(1 == ~E_8~0) [L1262-L1299] COND FALSE !(false) [L1265] start_simulation_~kernel_st~0 := 1; [L1266] havoc eval_#t~ret0, eval_#t~nondet1, eval_~tmp_ndt_1~0, eval_#t~nondet2, eval_~tmp_ndt_2~0, eval_#t~nondet3, eval_~tmp_ndt_3~0, eval_#t~nondet4, eval_~tmp_ndt_4~0, eval_#t~nondet5, eval_~tmp_ndt_5~0, eval_#t~nondet6, eval_~tmp_ndt_6~0, eval_#t~nondet7, eval_~tmp_ndt_7~0, eval_#t~nondet8, eval_~tmp_ndt_8~0, eval_#t~nondet9, eval_~tmp_ndt_9~0, eval_~tmp~0; [L677] havoc eval_~tmp~0; ----- ----- class de.uni_freiburg.informatik.ultimate.boogie.procedureinliner.backtranslation.InlinerBacktranslator [L15] ~m_pc~0 := 0; [L16] ~t1_pc~0 := 0; [L17] ~t2_pc~0 := 0; [L18] ~t3_pc~0 := 0; [L19] ~t4_pc~0 := 0; [L20] ~t5_pc~0 := 0; [L21] ~t6_pc~0 := 0; [L22] ~t7_pc~0 := 0; [L23] ~t8_pc~0 := 0; [L24] ~m_st~0 := 0; [L25] ~t1_st~0 := 0; [L26] ~t2_st~0 := 0; [L27] ~t3_st~0 := 0; [L28] ~t4_st~0 := 0; [L29] ~t5_st~0 := 0; [L30] ~t6_st~0 := 0; [L31] ~t7_st~0 := 0; [L32] ~t8_st~0 := 0; [L33] ~m_i~0 := 0; [L34] ~t1_i~0 := 0; [L35] ~t2_i~0 := 0; [L36] ~t3_i~0 := 0; [L37] ~t4_i~0 := 0; [L38] ~t5_i~0 := 0; [L39] ~t6_i~0 := 0; [L40] ~t7_i~0 := 0; [L41] ~t8_i~0 := 0; [L42] ~M_E~0 := 2; [L43] ~T1_E~0 := 2; [L44] ~T2_E~0 := 2; [L45] ~T3_E~0 := 2; [L46] ~T4_E~0 := 2; [L47] ~T5_E~0 := 2; [L48] ~T6_E~0 := 2; [L49] ~T7_E~0 := 2; [L50] ~T8_E~0 := 2; [L51] ~E_1~0 := 2; [L52] ~E_2~0 := 2; [L53] ~E_3~0 := 2; [L54] ~E_4~0 := 2; [L55] ~E_5~0 := 2; [L56] ~E_6~0 := 2; [L57] ~E_7~0 := 2; [L58] ~E_8~0 := 2; [?] havoc main_#res; [?] havoc main_~__retres1~10; [L1307] havoc main_~__retres1~10; [L1215] ~m_i~0 := 1; [L1216] ~t1_i~0 := 1; [L1217] ~t2_i~0 := 1; [L1218] ~t3_i~0 := 1; [L1219] ~t4_i~0 := 1; [L1220] ~t5_i~0 := 1; [L1221] ~t6_i~0 := 1; [L1222] ~t7_i~0 := 1; [L1223] ~t8_i~0 := 1; [L1312] havoc start_simulation_#t~ret20, start_simulation_#t~ret21, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1; [L1248] havoc start_simulation_~kernel_st~0; [L1249] havoc start_simulation_~tmp~3; [L1250] havoc start_simulation_~tmp___0~1; [L1254] start_simulation_~kernel_st~0 := 0; [L571] COND TRUE 1 == ~m_i~0 [L572] ~m_st~0 := 0; [L576] COND TRUE 1 == ~t1_i~0 [L577] ~t1_st~0 := 0; [L581] COND TRUE 1 == ~t2_i~0 [L582] ~t2_st~0 := 0; [L586] COND TRUE 1 == ~t3_i~0 [L587] ~t3_st~0 := 0; [L591] COND TRUE 1 == ~t4_i~0 [L592] ~t4_st~0 := 0; [L596] COND TRUE 1 == ~t5_i~0 [L597] ~t5_st~0 := 0; [L601] COND TRUE 1 == ~t6_i~0 [L602] ~t6_st~0 := 0; [L606] COND TRUE 1 == ~t7_i~0 [L607] ~t7_st~0 := 0; [L611] COND TRUE 1 == ~t8_i~0 [L612] ~t8_st~0 := 0; [L828] COND FALSE !(0 == ~M_E~0) [L833] COND FALSE !(0 == ~T1_E~0) [L838] COND FALSE !(0 == ~T2_E~0) [L843] COND FALSE !(0 == ~T3_E~0) [L848] COND FALSE !(0 == ~T4_E~0) [L853] COND FALSE !(0 == ~T5_E~0) [L858] COND FALSE !(0 == ~T6_E~0) [L863] COND FALSE !(0 == ~T7_E~0) [L868] COND FALSE !(0 == ~T8_E~0) [L873] COND FALSE !(0 == ~E_1~0) [L878] COND FALSE !(0 == ~E_2~0) [L883] COND FALSE !(0 == ~E_3~0) [L888] COND FALSE !(0 == ~E_4~0) [L893] COND FALSE !(0 == ~E_5~0) [L898] COND FALSE !(0 == ~E_6~0) [L903] COND FALSE !(0 == ~E_7~0) [L908] COND FALSE !(0 == ~E_8~0) [L1258] havoc activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0; [L1011] havoc activate_threads_~tmp~1; [L1012] havoc activate_threads_~tmp___0~0; [L1013] havoc activate_threads_~tmp___1~0; [L1014] havoc activate_threads_~tmp___2~0; [L1015] havoc activate_threads_~tmp___3~0; [L1016] havoc activate_threads_~tmp___4~0; [L1017] havoc activate_threads_~tmp___5~0; [L1018] havoc activate_threads_~tmp___6~0; [L1019] havoc activate_threads_~tmp___7~0; [L1023] havoc is_master_triggered_#res; [L1023] havoc is_master_triggered_~__retres1~0; [L389] havoc is_master_triggered_~__retres1~0; [L392] COND FALSE !(1 == ~m_pc~0) [L402] is_master_triggered_~__retres1~0 := 0; [L404] is_master_triggered_#res := is_master_triggered_~__retres1~0; [L1023] activate_threads_#t~ret10 := is_master_triggered_#res; [L1023] activate_threads_~tmp~1 := activate_threads_#t~ret10; [L1023] havoc activate_threads_#t~ret10; [L1025-L1029] COND FALSE !(0 != activate_threads_~tmp~1) [L1031] havoc is_transmit1_triggered_#res; [L1031] havoc is_transmit1_triggered_~__retres1~1; [L408] havoc is_transmit1_triggered_~__retres1~1; [L411] COND FALSE !(1 == ~t1_pc~0) [L421] is_transmit1_triggered_~__retres1~1 := 0; [L423] is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; [L1031] activate_threads_#t~ret11 := is_transmit1_triggered_#res; [L1031] activate_threads_~tmp___0~0 := activate_threads_#t~ret11; [L1031] havoc activate_threads_#t~ret11; [L1033-L1037] COND FALSE !(0 != activate_threads_~tmp___0~0) [L1039] havoc is_transmit2_triggered_#res; [L1039] havoc is_transmit2_triggered_~__retres1~2; [L427] havoc is_transmit2_triggered_~__retres1~2; [L430] COND FALSE !(1 == ~t2_pc~0) [L440] is_transmit2_triggered_~__retres1~2 := 0; [L442] is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; [L1039] activate_threads_#t~ret12 := is_transmit2_triggered_#res; [L1039] activate_threads_~tmp___1~0 := activate_threads_#t~ret12; [L1039] havoc activate_threads_#t~ret12; [L1041-L1045] COND FALSE !(0 != activate_threads_~tmp___1~0) [L1047] havoc is_transmit3_triggered_#res; [L1047] havoc is_transmit3_triggered_~__retres1~3; [L446] havoc is_transmit3_triggered_~__retres1~3; [L449] COND FALSE !(1 == ~t3_pc~0) [L459] is_transmit3_triggered_~__retres1~3 := 0; [L461] is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; [L1047] activate_threads_#t~ret13 := is_transmit3_triggered_#res; [L1047] activate_threads_~tmp___2~0 := activate_threads_#t~ret13; [L1047] havoc activate_threads_#t~ret13; [L1049-L1053] COND FALSE !(0 != activate_threads_~tmp___2~0) [L1055] havoc is_transmit4_triggered_#res; [L1055] havoc is_transmit4_triggered_~__retres1~4; [L465] havoc is_transmit4_triggered_~__retres1~4; [L468] COND FALSE !(1 == ~t4_pc~0) [L478] is_transmit4_triggered_~__retres1~4 := 0; [L480] is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; [L1055] activate_threads_#t~ret14 := is_transmit4_triggered_#res; [L1055] activate_threads_~tmp___3~0 := activate_threads_#t~ret14; [L1055] havoc activate_threads_#t~ret14; [L1057-L1061] COND FALSE !(0 != activate_threads_~tmp___3~0) [L1063] havoc is_transmit5_triggered_#res; [L1063] havoc is_transmit5_triggered_~__retres1~5; [L484] havoc is_transmit5_triggered_~__retres1~5; [L487] COND FALSE !(1 == ~t5_pc~0) [L497] is_transmit5_triggered_~__retres1~5 := 0; [L499] is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; [L1063] activate_threads_#t~ret15 := is_transmit5_triggered_#res; [L1063] activate_threads_~tmp___4~0 := activate_threads_#t~ret15; [L1063] havoc activate_threads_#t~ret15; [L1065-L1069] COND FALSE !(0 != activate_threads_~tmp___4~0) [L1071] havoc is_transmit6_triggered_#res; [L1071] havoc is_transmit6_triggered_~__retres1~6; [L503] havoc is_transmit6_triggered_~__retres1~6; [L506] COND FALSE !(1 == ~t6_pc~0) [L516] is_transmit6_triggered_~__retres1~6 := 0; [L518] is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; [L1071] activate_threads_#t~ret16 := is_transmit6_triggered_#res; [L1071] activate_threads_~tmp___5~0 := activate_threads_#t~ret16; [L1071] havoc activate_threads_#t~ret16; [L1073-L1077] COND FALSE !(0 != activate_threads_~tmp___5~0) [L1079] havoc is_transmit7_triggered_#res; [L1079] havoc is_transmit7_triggered_~__retres1~7; [L522] havoc is_transmit7_triggered_~__retres1~7; [L525] COND FALSE !(1 == ~t7_pc~0) [L535] is_transmit7_triggered_~__retres1~7 := 0; [L537] is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; [L1079] activate_threads_#t~ret17 := is_transmit7_triggered_#res; [L1079] activate_threads_~tmp___6~0 := activate_threads_#t~ret17; [L1079] havoc activate_threads_#t~ret17; [L1081-L1085] COND FALSE !(0 != activate_threads_~tmp___6~0) [L1087] havoc is_transmit8_triggered_#res; [L1087] havoc is_transmit8_triggered_~__retres1~8; [L541] havoc is_transmit8_triggered_~__retres1~8; [L544] COND FALSE !(1 == ~t8_pc~0) [L554] is_transmit8_triggered_~__retres1~8 := 0; [L556] is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; [L1087] activate_threads_#t~ret18 := is_transmit8_triggered_#res; [L1087] activate_threads_~tmp___7~0 := activate_threads_#t~ret18; [L1087] havoc activate_threads_#t~ret18; [L1089-L1093] COND FALSE !(0 != activate_threads_~tmp___7~0) [L921] COND FALSE !(1 == ~M_E~0) [L926] COND FALSE !(1 == ~T1_E~0) [L931] COND FALSE !(1 == ~T2_E~0) [L936] COND FALSE !(1 == ~T3_E~0) [L941] COND FALSE !(1 == ~T4_E~0) [L946] COND FALSE !(1 == ~T5_E~0) [L951] COND FALSE !(1 == ~T6_E~0) [L956] COND FALSE !(1 == ~T7_E~0) [L961] COND FALSE !(1 == ~T8_E~0) [L966] COND FALSE !(1 == ~E_1~0) [L971] COND FALSE !(1 == ~E_2~0) [L976] COND FALSE !(1 == ~E_3~0) [L981] COND FALSE !(1 == ~E_4~0) [L986] COND FALSE !(1 == ~E_5~0) [L991] COND FALSE !(1 == ~E_6~0) [L996] COND FALSE !(1 == ~E_7~0) [L1001] COND FALSE !(1 == ~E_8~0) [L1262-L1299] COND FALSE !(false) [L1265] start_simulation_~kernel_st~0 := 1; [L1266] havoc eval_#t~ret0, eval_#t~nondet1, eval_~tmp_ndt_1~0, eval_#t~nondet2, eval_~tmp_ndt_2~0, eval_#t~nondet3, eval_~tmp_ndt_3~0, eval_#t~nondet4, eval_~tmp_ndt_4~0, eval_#t~nondet5, eval_~tmp_ndt_5~0, eval_#t~nondet6, eval_~tmp_ndt_6~0, eval_#t~nondet7, eval_~tmp_ndt_7~0, eval_#t~nondet8, eval_~tmp_ndt_8~0, eval_#t~nondet9, eval_~tmp_ndt_9~0, eval_~tmp~0; [L677] havoc eval_~tmp~0; [L15] ~m_pc~0 := 0; [L16] ~t1_pc~0 := 0; [L17] ~t2_pc~0 := 0; [L18] ~t3_pc~0 := 0; [L19] ~t4_pc~0 := 0; [L20] ~t5_pc~0 := 0; [L21] ~t6_pc~0 := 0; [L22] ~t7_pc~0 := 0; [L23] ~t8_pc~0 := 0; [L24] ~m_st~0 := 0; [L25] ~t1_st~0 := 0; [L26] ~t2_st~0 := 0; [L27] ~t3_st~0 := 0; [L28] ~t4_st~0 := 0; [L29] ~t5_st~0 := 0; [L30] ~t6_st~0 := 0; [L31] ~t7_st~0 := 0; [L32] ~t8_st~0 := 0; [L33] ~m_i~0 := 0; [L34] ~t1_i~0 := 0; [L35] ~t2_i~0 := 0; [L36] ~t3_i~0 := 0; [L37] ~t4_i~0 := 0; [L38] ~t5_i~0 := 0; [L39] ~t6_i~0 := 0; [L40] ~t7_i~0 := 0; [L41] ~t8_i~0 := 0; [L42] ~M_E~0 := 2; [L43] ~T1_E~0 := 2; [L44] ~T2_E~0 := 2; [L45] ~T3_E~0 := 2; [L46] ~T4_E~0 := 2; [L47] ~T5_E~0 := 2; [L48] ~T6_E~0 := 2; [L49] ~T7_E~0 := 2; [L50] ~T8_E~0 := 2; [L51] ~E_1~0 := 2; [L52] ~E_2~0 := 2; [L53] ~E_3~0 := 2; [L54] ~E_4~0 := 2; [L55] ~E_5~0 := 2; [L56] ~E_6~0 := 2; [L57] ~E_7~0 := 2; [L58] ~E_8~0 := 2; [L1307] havoc ~__retres1~10; [L1215] ~m_i~0 := 1; [L1216] ~t1_i~0 := 1; [L1217] ~t2_i~0 := 1; [L1218] ~t3_i~0 := 1; [L1219] ~t4_i~0 := 1; [L1220] ~t5_i~0 := 1; [L1221] ~t6_i~0 := 1; [L1222] ~t7_i~0 := 1; [L1223] ~t8_i~0 := 1; [L1248] havoc ~kernel_st~0; [L1249] havoc ~tmp~3; [L1250] havoc ~tmp___0~1; [L1254] ~kernel_st~0 := 0; [L571] COND TRUE 1 == ~m_i~0 [L572] ~m_st~0 := 0; [L576] COND TRUE 1 == ~t1_i~0 [L577] ~t1_st~0 := 0; [L581] COND TRUE 1 == ~t2_i~0 [L582] ~t2_st~0 := 0; [L586] COND TRUE 1 == ~t3_i~0 [L587] ~t3_st~0 := 0; [L591] COND TRUE 1 == ~t4_i~0 [L592] ~t4_st~0 := 0; [L596] COND TRUE 1 == ~t5_i~0 [L597] ~t5_st~0 := 0; [L601] COND TRUE 1 == ~t6_i~0 [L602] ~t6_st~0 := 0; [L606] COND TRUE 1 == ~t7_i~0 [L607] ~t7_st~0 := 0; [L611] COND TRUE 1 == ~t8_i~0 [L612] ~t8_st~0 := 0; [L828] COND FALSE !(0 == ~M_E~0) [L833] COND FALSE !(0 == ~T1_E~0) [L838] COND FALSE !(0 == ~T2_E~0) [L843] COND FALSE !(0 == ~T3_E~0) [L848] COND FALSE !(0 == ~T4_E~0) [L853] COND FALSE !(0 == ~T5_E~0) [L858] COND FALSE !(0 == ~T6_E~0) [L863] COND FALSE !(0 == ~T7_E~0) [L868] COND FALSE !(0 == ~T8_E~0) [L873] COND FALSE !(0 == ~E_1~0) [L878] COND FALSE !(0 == ~E_2~0) [L883] COND FALSE !(0 == ~E_3~0) [L888] COND FALSE !(0 == ~E_4~0) [L893] COND FALSE !(0 == ~E_5~0) [L898] COND FALSE !(0 == ~E_6~0) [L903] COND FALSE !(0 == ~E_7~0) [L908] COND FALSE !(0 == ~E_8~0) [L1011] havoc ~tmp~1; [L1012] havoc ~tmp___0~0; [L1013] havoc ~tmp___1~0; [L1014] havoc ~tmp___2~0; [L1015] havoc ~tmp___3~0; [L1016] havoc ~tmp___4~0; [L1017] havoc ~tmp___5~0; [L1018] havoc ~tmp___6~0; [L1019] havoc ~tmp___7~0; [L389] havoc ~__retres1~0; [L392] COND FALSE !(1 == ~m_pc~0) [L402] ~__retres1~0 := 0; [L404] #res := ~__retres1~0; [L1023] ~tmp~1 := #t~ret10; [L1023] havoc #t~ret10; [L1025-L1029] COND FALSE !(0 != ~tmp~1) [L408] havoc ~__retres1~1; [L411] COND FALSE !(1 == ~t1_pc~0) [L421] ~__retres1~1 := 0; [L423] #res := ~__retres1~1; [L1031] ~tmp___0~0 := #t~ret11; [L1031] havoc #t~ret11; [L1033-L1037] COND FALSE !(0 != ~tmp___0~0) [L427] havoc ~__retres1~2; [L430] COND FALSE !(1 == ~t2_pc~0) [L440] ~__retres1~2 := 0; [L442] #res := ~__retres1~2; [L1039] ~tmp___1~0 := #t~ret12; [L1039] havoc #t~ret12; [L1041-L1045] COND FALSE !(0 != ~tmp___1~0) [L446] havoc ~__retres1~3; [L449] COND FALSE !(1 == ~t3_pc~0) [L459] ~__retres1~3 := 0; [L461] #res := ~__retres1~3; [L1047] ~tmp___2~0 := #t~ret13; [L1047] havoc #t~ret13; [L1049-L1053] COND FALSE !(0 != ~tmp___2~0) [L465] havoc ~__retres1~4; [L468] COND FALSE !(1 == ~t4_pc~0) [L478] ~__retres1~4 := 0; [L480] #res := ~__retres1~4; [L1055] ~tmp___3~0 := #t~ret14; [L1055] havoc #t~ret14; [L1057-L1061] COND FALSE !(0 != ~tmp___3~0) [L484] havoc ~__retres1~5; [L487] COND FALSE !(1 == ~t5_pc~0) [L497] ~__retres1~5 := 0; [L499] #res := ~__retres1~5; [L1063] ~tmp___4~0 := #t~ret15; [L1063] havoc #t~ret15; [L1065-L1069] COND FALSE !(0 != ~tmp___4~0) [L503] havoc ~__retres1~6; [L506] COND FALSE !(1 == ~t6_pc~0) [L516] ~__retres1~6 := 0; [L518] #res := ~__retres1~6; [L1071] ~tmp___5~0 := #t~ret16; [L1071] havoc #t~ret16; [L1073-L1077] COND FALSE !(0 != ~tmp___5~0) [L522] havoc ~__retres1~7; [L525] COND FALSE !(1 == ~t7_pc~0) [L535] ~__retres1~7 := 0; [L537] #res := ~__retres1~7; [L1079] ~tmp___6~0 := #t~ret17; [L1079] havoc #t~ret17; [L1081-L1085] COND FALSE !(0 != ~tmp___6~0) [L541] havoc ~__retres1~8; [L544] COND FALSE !(1 == ~t8_pc~0) [L554] ~__retres1~8 := 0; [L556] #res := ~__retres1~8; [L1087] ~tmp___7~0 := #t~ret18; [L1087] havoc #t~ret18; [L1089-L1093] COND FALSE !(0 != ~tmp___7~0) [L921] COND FALSE !(1 == ~M_E~0) [L926] COND FALSE !(1 == ~T1_E~0) [L931] COND FALSE !(1 == ~T2_E~0) [L936] COND FALSE !(1 == ~T3_E~0) [L941] COND FALSE !(1 == ~T4_E~0) [L946] COND FALSE !(1 == ~T5_E~0) [L951] COND FALSE !(1 == ~T6_E~0) [L956] COND FALSE !(1 == ~T7_E~0) [L961] COND FALSE !(1 == ~T8_E~0) [L966] COND FALSE !(1 == ~E_1~0) [L971] COND FALSE !(1 == ~E_2~0) [L976] COND FALSE !(1 == ~E_3~0) [L981] COND FALSE !(1 == ~E_4~0) [L986] COND FALSE !(1 == ~E_5~0) [L991] COND FALSE !(1 == ~E_6~0) [L996] COND FALSE !(1 == ~E_7~0) [L1001] COND FALSE !(1 == ~E_8~0) [L1262-L1299] COND FALSE !(false) [L1265] ~kernel_st~0 := 1; [L677] havoc ~tmp~0; ----- ----- class de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.CACSL2BoogieBacktranslator [L15] ~m_pc~0 := 0; [L16] ~t1_pc~0 := 0; [L17] ~t2_pc~0 := 0; [L18] ~t3_pc~0 := 0; [L19] ~t4_pc~0 := 0; [L20] ~t5_pc~0 := 0; [L21] ~t6_pc~0 := 0; [L22] ~t7_pc~0 := 0; [L23] ~t8_pc~0 := 0; [L24] ~m_st~0 := 0; [L25] ~t1_st~0 := 0; [L26] ~t2_st~0 := 0; [L27] ~t3_st~0 := 0; [L28] ~t4_st~0 := 0; [L29] ~t5_st~0 := 0; [L30] ~t6_st~0 := 0; [L31] ~t7_st~0 := 0; [L32] ~t8_st~0 := 0; [L33] ~m_i~0 := 0; [L34] ~t1_i~0 := 0; [L35] ~t2_i~0 := 0; [L36] ~t3_i~0 := 0; [L37] ~t4_i~0 := 0; [L38] ~t5_i~0 := 0; [L39] ~t6_i~0 := 0; [L40] ~t7_i~0 := 0; [L41] ~t8_i~0 := 0; [L42] ~M_E~0 := 2; [L43] ~T1_E~0 := 2; [L44] ~T2_E~0 := 2; [L45] ~T3_E~0 := 2; [L46] ~T4_E~0 := 2; [L47] ~T5_E~0 := 2; [L48] ~T6_E~0 := 2; [L49] ~T7_E~0 := 2; [L50] ~T8_E~0 := 2; [L51] ~E_1~0 := 2; [L52] ~E_2~0 := 2; [L53] ~E_3~0 := 2; [L54] ~E_4~0 := 2; [L55] ~E_5~0 := 2; [L56] ~E_6~0 := 2; [L57] ~E_7~0 := 2; [L58] ~E_8~0 := 2; [L1307] havoc ~__retres1~10; [L1215] ~m_i~0 := 1; [L1216] ~t1_i~0 := 1; [L1217] ~t2_i~0 := 1; [L1218] ~t3_i~0 := 1; [L1219] ~t4_i~0 := 1; [L1220] ~t5_i~0 := 1; [L1221] ~t6_i~0 := 1; [L1222] ~t7_i~0 := 1; [L1223] ~t8_i~0 := 1; [L1248] havoc ~kernel_st~0; [L1249] havoc ~tmp~3; [L1250] havoc ~tmp___0~1; [L1254] ~kernel_st~0 := 0; [L571] COND TRUE 1 == ~m_i~0 [L572] ~m_st~0 := 0; [L576] COND TRUE 1 == ~t1_i~0 [L577] ~t1_st~0 := 0; [L581] COND TRUE 1 == ~t2_i~0 [L582] ~t2_st~0 := 0; [L586] COND TRUE 1 == ~t3_i~0 [L587] ~t3_st~0 := 0; [L591] COND TRUE 1 == ~t4_i~0 [L592] ~t4_st~0 := 0; [L596] COND TRUE 1 == ~t5_i~0 [L597] ~t5_st~0 := 0; [L601] COND TRUE 1 == ~t6_i~0 [L602] ~t6_st~0 := 0; [L606] COND TRUE 1 == ~t7_i~0 [L607] ~t7_st~0 := 0; [L611] COND TRUE 1 == ~t8_i~0 [L612] ~t8_st~0 := 0; [L828] COND FALSE !(0 == ~M_E~0) [L833] COND FALSE !(0 == ~T1_E~0) [L838] COND FALSE !(0 == ~T2_E~0) [L843] COND FALSE !(0 == ~T3_E~0) [L848] COND FALSE !(0 == ~T4_E~0) [L853] COND FALSE !(0 == ~T5_E~0) [L858] COND FALSE !(0 == ~T6_E~0) [L863] COND FALSE !(0 == ~T7_E~0) [L868] COND FALSE !(0 == ~T8_E~0) [L873] COND FALSE !(0 == ~E_1~0) [L878] COND FALSE !(0 == ~E_2~0) [L883] COND FALSE !(0 == ~E_3~0) [L888] COND FALSE !(0 == ~E_4~0) [L893] COND FALSE !(0 == ~E_5~0) [L898] COND FALSE !(0 == ~E_6~0) [L903] COND FALSE !(0 == ~E_7~0) [L908] COND FALSE !(0 == ~E_8~0) [L1011] havoc ~tmp~1; [L1012] havoc ~tmp___0~0; [L1013] havoc ~tmp___1~0; [L1014] havoc ~tmp___2~0; [L1015] havoc ~tmp___3~0; [L1016] havoc ~tmp___4~0; [L1017] havoc ~tmp___5~0; [L1018] havoc ~tmp___6~0; [L1019] havoc ~tmp___7~0; [L389] havoc ~__retres1~0; [L392] COND FALSE !(1 == ~m_pc~0) [L402] ~__retres1~0 := 0; [L404] #res := ~__retres1~0; [L1023] ~tmp~1 := #t~ret10; [L1023] havoc #t~ret10; [L1025-L1029] COND FALSE !(0 != ~tmp~1) [L408] havoc ~__retres1~1; [L411] COND FALSE !(1 == ~t1_pc~0) [L421] ~__retres1~1 := 0; [L423] #res := ~__retres1~1; [L1031] ~tmp___0~0 := #t~ret11; [L1031] havoc #t~ret11; [L1033-L1037] COND FALSE !(0 != ~tmp___0~0) [L427] havoc ~__retres1~2; [L430] COND FALSE !(1 == ~t2_pc~0) [L440] ~__retres1~2 := 0; [L442] #res := ~__retres1~2; [L1039] ~tmp___1~0 := #t~ret12; [L1039] havoc #t~ret12; [L1041-L1045] COND FALSE !(0 != ~tmp___1~0) [L446] havoc ~__retres1~3; [L449] COND FALSE !(1 == ~t3_pc~0) [L459] ~__retres1~3 := 0; [L461] #res := ~__retres1~3; [L1047] ~tmp___2~0 := #t~ret13; [L1047] havoc #t~ret13; [L1049-L1053] COND FALSE !(0 != ~tmp___2~0) [L465] havoc ~__retres1~4; [L468] COND FALSE !(1 == ~t4_pc~0) [L478] ~__retres1~4 := 0; [L480] #res := ~__retres1~4; [L1055] ~tmp___3~0 := #t~ret14; [L1055] havoc #t~ret14; [L1057-L1061] COND FALSE !(0 != ~tmp___3~0) [L484] havoc ~__retres1~5; [L487] COND FALSE !(1 == ~t5_pc~0) [L497] ~__retres1~5 := 0; [L499] #res := ~__retres1~5; [L1063] ~tmp___4~0 := #t~ret15; [L1063] havoc #t~ret15; [L1065-L1069] COND FALSE !(0 != ~tmp___4~0) [L503] havoc ~__retres1~6; [L506] COND FALSE !(1 == ~t6_pc~0) [L516] ~__retres1~6 := 0; [L518] #res := ~__retres1~6; [L1071] ~tmp___5~0 := #t~ret16; [L1071] havoc #t~ret16; [L1073-L1077] COND FALSE !(0 != ~tmp___5~0) [L522] havoc ~__retres1~7; [L525] COND FALSE !(1 == ~t7_pc~0) [L535] ~__retres1~7 := 0; [L537] #res := ~__retres1~7; [L1079] ~tmp___6~0 := #t~ret17; [L1079] havoc #t~ret17; [L1081-L1085] COND FALSE !(0 != ~tmp___6~0) [L541] havoc ~__retres1~8; [L544] COND FALSE !(1 == ~t8_pc~0) [L554] ~__retres1~8 := 0; [L556] #res := ~__retres1~8; [L1087] ~tmp___7~0 := #t~ret18; [L1087] havoc #t~ret18; [L1089-L1093] COND FALSE !(0 != ~tmp___7~0) [L921] COND FALSE !(1 == ~M_E~0) [L926] COND FALSE !(1 == ~T1_E~0) [L931] COND FALSE !(1 == ~T2_E~0) [L936] COND FALSE !(1 == ~T3_E~0) [L941] COND FALSE !(1 == ~T4_E~0) [L946] COND FALSE !(1 == ~T5_E~0) [L951] COND FALSE !(1 == ~T6_E~0) [L956] COND FALSE !(1 == ~T7_E~0) [L961] COND FALSE !(1 == ~T8_E~0) [L966] COND FALSE !(1 == ~E_1~0) [L971] COND FALSE !(1 == ~E_2~0) [L976] COND FALSE !(1 == ~E_3~0) [L981] COND FALSE !(1 == ~E_4~0) [L986] COND FALSE !(1 == ~E_5~0) [L991] COND FALSE !(1 == ~E_6~0) [L996] COND FALSE !(1 == ~E_7~0) [L1001] COND FALSE !(1 == ~E_8~0) [L1262-L1299] COND FALSE !(false) [L1265] ~kernel_st~0 := 1; [L677] havoc ~tmp~0; [L15] int m_pc = 0; [L16] int t1_pc = 0; [L17] int t2_pc = 0; [L18] int t3_pc = 0; [L19] int t4_pc = 0; [L20] int t5_pc = 0; [L21] int t6_pc = 0; [L22] int t7_pc = 0; [L23] int t8_pc = 0; [L24] int m_st ; [L25] int t1_st ; [L26] int t2_st ; [L27] int t3_st ; [L28] int t4_st ; [L29] int t5_st ; [L30] int t6_st ; [L31] int t7_st ; [L32] int t8_st ; [L33] int m_i ; [L34] int t1_i ; [L35] int t2_i ; [L36] int t3_i ; [L37] int t4_i ; [L38] int t5_i ; [L39] int t6_i ; [L40] int t7_i ; [L41] int t8_i ; [L42] int M_E = 2; [L43] int T1_E = 2; [L44] int T2_E = 2; [L45] int T3_E = 2; [L46] int T4_E = 2; [L47] int T5_E = 2; [L48] int T6_E = 2; [L49] int T7_E = 2; [L50] int T8_E = 2; [L51] int E_1 = 2; [L52] int E_2 = 2; [L53] int E_3 = 2; [L54] int E_4 = 2; [L55] int E_5 = 2; [L56] int E_6 = 2; [L57] int E_7 = 2; [L58] int E_8 = 2; [L1307] int __retres1 ; [L1215] m_i = 1 [L1216] t1_i = 1 [L1217] t2_i = 1 [L1218] t3_i = 1 [L1219] t4_i = 1 [L1220] t5_i = 1 [L1221] t6_i = 1 [L1222] t7_i = 1 [L1223] t8_i = 1 [L1248] int kernel_st ; [L1249] int tmp ; [L1250] int tmp___0 ; [L1254] kernel_st = 0 [L571] COND TRUE m_i == 1 [L572] m_st = 0 [L576] COND TRUE t1_i == 1 [L577] t1_st = 0 [L581] COND TRUE t2_i == 1 [L582] t2_st = 0 [L586] COND TRUE t3_i == 1 [L587] t3_st = 0 [L591] COND TRUE t4_i == 1 [L592] t4_st = 0 [L596] COND TRUE t5_i == 1 [L597] t5_st = 0 [L601] COND TRUE t6_i == 1 [L602] t6_st = 0 [L606] COND TRUE t7_i == 1 [L607] t7_st = 0 [L611] COND TRUE t8_i == 1 [L612] t8_st = 0 [L828] COND FALSE !(M_E == 0) [L833] COND FALSE !(T1_E == 0) [L838] COND FALSE !(T2_E == 0) [L843] COND FALSE !(T3_E == 0) [L848] COND FALSE !(T4_E == 0) [L853] COND FALSE !(T5_E == 0) [L858] COND FALSE !(T6_E == 0) [L863] COND FALSE !(T7_E == 0) [L868] COND FALSE !(T8_E == 0) [L873] COND FALSE !(E_1 == 0) [L878] COND FALSE !(E_2 == 0) [L883] COND FALSE !(E_3 == 0) [L888] COND FALSE !(E_4 == 0) [L893] COND FALSE !(E_5 == 0) [L898] COND FALSE !(E_6 == 0) [L903] COND FALSE !(E_7 == 0) [L908] COND FALSE !(E_8 == 0) [L1011] int tmp ; [L1012] int tmp___0 ; [L1013] int tmp___1 ; [L1014] int tmp___2 ; [L1015] int tmp___3 ; [L1016] int tmp___4 ; [L1017] int tmp___5 ; [L1018] int tmp___6 ; [L1019] int tmp___7 ; [L389] int __retres1 ; [L392] COND FALSE !(m_pc == 1) [L402] __retres1 = 0 [L404] return (__retres1); [L1023] tmp = is_master_triggered() [L1025] COND FALSE !(\read(tmp)) [L408] int __retres1 ; [L411] COND FALSE !(t1_pc == 1) [L421] __retres1 = 0 [L423] return (__retres1); [L1031] tmp___0 = is_transmit1_triggered() [L1033] COND FALSE !(\read(tmp___0)) [L427] int __retres1 ; [L430] COND FALSE !(t2_pc == 1) [L440] __retres1 = 0 [L442] return (__retres1); [L1039] tmp___1 = is_transmit2_triggered() [L1041] COND FALSE !(\read(tmp___1)) [L446] int __retres1 ; [L449] COND FALSE !(t3_pc == 1) [L459] __retres1 = 0 [L461] return (__retres1); [L1047] tmp___2 = is_transmit3_triggered() [L1049] COND FALSE !(\read(tmp___2)) [L465] int __retres1 ; [L468] COND FALSE !(t4_pc == 1) [L478] __retres1 = 0 [L480] return (__retres1); [L1055] tmp___3 = is_transmit4_triggered() [L1057] COND FALSE !(\read(tmp___3)) [L484] int __retres1 ; [L487] COND FALSE !(t5_pc == 1) [L497] __retres1 = 0 [L499] return (__retres1); [L1063] tmp___4 = is_transmit5_triggered() [L1065] COND FALSE !(\read(tmp___4)) [L503] int __retres1 ; [L506] COND FALSE !(t6_pc == 1) [L516] __retres1 = 0 [L518] return (__retres1); [L1071] tmp___5 = is_transmit6_triggered() [L1073] COND FALSE !(\read(tmp___5)) [L522] int __retres1 ; [L525] COND FALSE !(t7_pc == 1) [L535] __retres1 = 0 [L537] return (__retres1); [L1079] tmp___6 = is_transmit7_triggered() [L1081] COND FALSE !(\read(tmp___6)) [L541] int __retres1 ; [L544] COND FALSE !(t8_pc == 1) [L554] __retres1 = 0 [L556] return (__retres1); [L1087] tmp___7 = is_transmit8_triggered() [L1089] COND FALSE !(\read(tmp___7)) [L921] COND FALSE !(M_E == 1) [L926] COND FALSE !(T1_E == 1) [L931] COND FALSE !(T2_E == 1) [L936] COND FALSE !(T3_E == 1) [L941] COND FALSE !(T4_E == 1) [L946] COND FALSE !(T5_E == 1) [L951] COND FALSE !(T6_E == 1) [L956] COND FALSE !(T7_E == 1) [L961] COND FALSE !(T8_E == 1) [L966] COND FALSE !(E_1 == 1) [L971] COND FALSE !(E_2 == 1) [L976] COND FALSE !(E_3 == 1) [L981] COND FALSE !(E_4 == 1) [L986] COND FALSE !(E_5 == 1) [L991] COND FALSE !(E_6 == 1) [L996] COND FALSE !(E_7 == 1) [L1001] COND FALSE !(E_8 == 1) [L1262] COND TRUE 1 [L1265] kernel_st = 1 [L677] int tmp ; ----- ----- class de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder.RCFGBacktranslator [?] assume !false; [?] havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~9;havoc exists_runnable_thread_~__retres1~9; [?] assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9 := 1; [?] exists_runnable_thread_#res := exists_runnable_thread_~__retres1~9; [?] eval_#t~ret0 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret0;havoc eval_#t~ret0; [?] assume 0 != eval_~tmp~0; [?] assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0;eval_~tmp_ndt_1~0 := eval_#t~nondet1;havoc eval_#t~nondet1; [?] assume !(0 != eval_~tmp_ndt_1~0); [?] assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0;eval_~tmp_ndt_2~0 := eval_#t~nondet2;havoc eval_#t~nondet2; [?] assume !(0 != eval_~tmp_ndt_2~0); [?] assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0;eval_~tmp_ndt_3~0 := eval_#t~nondet3;havoc eval_#t~nondet3; [?] assume !(0 != eval_~tmp_ndt_3~0); [?] assume 0 == ~t3_st~0;havoc eval_~tmp_ndt_4~0;eval_~tmp_ndt_4~0 := eval_#t~nondet4;havoc eval_#t~nondet4; [?] assume !(0 != eval_~tmp_ndt_4~0); [?] assume 0 == ~t4_st~0;havoc eval_~tmp_ndt_5~0;eval_~tmp_ndt_5~0 := eval_#t~nondet5;havoc eval_#t~nondet5; [?] assume !(0 != eval_~tmp_ndt_5~0); [?] assume 0 == ~t5_st~0;havoc eval_~tmp_ndt_6~0;eval_~tmp_ndt_6~0 := eval_#t~nondet6;havoc eval_#t~nondet6; [?] assume !(0 != eval_~tmp_ndt_6~0); [?] assume 0 == ~t6_st~0;havoc eval_~tmp_ndt_7~0;eval_~tmp_ndt_7~0 := eval_#t~nondet7;havoc eval_#t~nondet7; [?] assume !(0 != eval_~tmp_ndt_7~0); [?] assume 0 == ~t7_st~0;havoc eval_~tmp_ndt_8~0;eval_~tmp_ndt_8~0 := eval_#t~nondet8;havoc eval_#t~nondet8; [?] assume !(0 != eval_~tmp_ndt_8~0); [?] assume 0 == ~t8_st~0;havoc eval_~tmp_ndt_9~0;eval_~tmp_ndt_9~0 := eval_#t~nondet9;havoc eval_#t~nondet9; [?] assume !(0 != eval_~tmp_ndt_9~0); [L681-L817] assume !false; [L684] havoc exists_runnable_thread_#res; [L684] havoc exists_runnable_thread_~__retres1~9; [L621] havoc exists_runnable_thread_~__retres1~9; [L624-L669] assume 0 == ~m_st~0; [L625] exists_runnable_thread_~__retres1~9 := 1; [L672] exists_runnable_thread_#res := exists_runnable_thread_~__retres1~9; [L684] eval_#t~ret0 := exists_runnable_thread_#res; [L684] eval_~tmp~0 := eval_#t~ret0; [L684] havoc eval_#t~ret0; [L686-L690] assume 0 != eval_~tmp~0; [L691-L704] assume 0 == ~m_st~0; [L692] havoc eval_~tmp_ndt_1~0; [L693] eval_~tmp_ndt_1~0 := eval_#t~nondet1; [L693] havoc eval_#t~nondet1; [L694-L701] assume !(0 != eval_~tmp_ndt_1~0); [L705-L718] assume 0 == ~t1_st~0; [L706] havoc eval_~tmp_ndt_2~0; [L707] eval_~tmp_ndt_2~0 := eval_#t~nondet2; [L707] havoc eval_#t~nondet2; [L708-L715] assume !(0 != eval_~tmp_ndt_2~0); [L719-L732] assume 0 == ~t2_st~0; [L720] havoc eval_~tmp_ndt_3~0; [L721] eval_~tmp_ndt_3~0 := eval_#t~nondet3; [L721] havoc eval_#t~nondet3; [L722-L729] assume !(0 != eval_~tmp_ndt_3~0); [L733-L746] assume 0 == ~t3_st~0; [L734] havoc eval_~tmp_ndt_4~0; [L735] eval_~tmp_ndt_4~0 := eval_#t~nondet4; [L735] havoc eval_#t~nondet4; [L736-L743] assume !(0 != eval_~tmp_ndt_4~0); [L747-L760] assume 0 == ~t4_st~0; [L748] havoc eval_~tmp_ndt_5~0; [L749] eval_~tmp_ndt_5~0 := eval_#t~nondet5; [L749] havoc eval_#t~nondet5; [L750-L757] assume !(0 != eval_~tmp_ndt_5~0); [L761-L774] assume 0 == ~t5_st~0; [L762] havoc eval_~tmp_ndt_6~0; [L763] eval_~tmp_ndt_6~0 := eval_#t~nondet6; [L763] havoc eval_#t~nondet6; [L764-L771] assume !(0 != eval_~tmp_ndt_6~0); [L775-L788] assume 0 == ~t6_st~0; [L776] havoc eval_~tmp_ndt_7~0; [L777] eval_~tmp_ndt_7~0 := eval_#t~nondet7; [L777] havoc eval_#t~nondet7; [L778-L785] assume !(0 != eval_~tmp_ndt_7~0); [L789-L802] assume 0 == ~t7_st~0; [L790] havoc eval_~tmp_ndt_8~0; [L791] eval_~tmp_ndt_8~0 := eval_#t~nondet8; [L791] havoc eval_#t~nondet8; [L792-L799] assume !(0 != eval_~tmp_ndt_8~0); [L803-L816] assume 0 == ~t8_st~0; [L804] havoc eval_~tmp_ndt_9~0; [L805] eval_~tmp_ndt_9~0 := eval_#t~nondet9; [L805] havoc eval_#t~nondet9; [L806-L813] assume !(0 != eval_~tmp_ndt_9~0); ----- ----- class de.uni_freiburg.informatik.ultimate.boogie.preprocessor.BoogiePreprocessorBacktranslator [L681-L817] assume !false; [L684] havoc exists_runnable_thread_#res; [L684] havoc exists_runnable_thread_~__retres1~9; [L621] havoc exists_runnable_thread_~__retres1~9; [L624-L669] assume 0 == ~m_st~0; [L625] exists_runnable_thread_~__retres1~9 := 1; [L672] exists_runnable_thread_#res := exists_runnable_thread_~__retres1~9; [L684] eval_#t~ret0 := exists_runnable_thread_#res; [L684] eval_~tmp~0 := eval_#t~ret0; [L684] havoc eval_#t~ret0; [L686-L690] assume 0 != eval_~tmp~0; [L691-L704] assume 0 == ~m_st~0; [L692] havoc eval_~tmp_ndt_1~0; [L693] eval_~tmp_ndt_1~0 := eval_#t~nondet1; [L693] havoc eval_#t~nondet1; [L694-L701] assume !(0 != eval_~tmp_ndt_1~0); [L705-L718] assume 0 == ~t1_st~0; [L706] havoc eval_~tmp_ndt_2~0; [L707] eval_~tmp_ndt_2~0 := eval_#t~nondet2; [L707] havoc eval_#t~nondet2; [L708-L715] assume !(0 != eval_~tmp_ndt_2~0); [L719-L732] assume 0 == ~t2_st~0; [L720] havoc eval_~tmp_ndt_3~0; [L721] eval_~tmp_ndt_3~0 := eval_#t~nondet3; [L721] havoc eval_#t~nondet3; [L722-L729] assume !(0 != eval_~tmp_ndt_3~0); [L733-L746] assume 0 == ~t3_st~0; [L734] havoc eval_~tmp_ndt_4~0; [L735] eval_~tmp_ndt_4~0 := eval_#t~nondet4; [L735] havoc eval_#t~nondet4; [L736-L743] assume !(0 != eval_~tmp_ndt_4~0); [L747-L760] assume 0 == ~t4_st~0; [L748] havoc eval_~tmp_ndt_5~0; [L749] eval_~tmp_ndt_5~0 := eval_#t~nondet5; [L749] havoc eval_#t~nondet5; [L750-L757] assume !(0 != eval_~tmp_ndt_5~0); [L761-L774] assume 0 == ~t5_st~0; [L762] havoc eval_~tmp_ndt_6~0; [L763] eval_~tmp_ndt_6~0 := eval_#t~nondet6; [L763] havoc eval_#t~nondet6; [L764-L771] assume !(0 != eval_~tmp_ndt_6~0); [L775-L788] assume 0 == ~t6_st~0; [L776] havoc eval_~tmp_ndt_7~0; [L777] eval_~tmp_ndt_7~0 := eval_#t~nondet7; [L777] havoc eval_#t~nondet7; [L778-L785] assume !(0 != eval_~tmp_ndt_7~0); [L789-L802] assume 0 == ~t7_st~0; [L790] havoc eval_~tmp_ndt_8~0; [L791] eval_~tmp_ndt_8~0 := eval_#t~nondet8; [L791] havoc eval_#t~nondet8; [L792-L799] assume !(0 != eval_~tmp_ndt_8~0); [L803-L816] assume 0 == ~t8_st~0; [L804] havoc eval_~tmp_ndt_9~0; [L805] eval_~tmp_ndt_9~0 := eval_#t~nondet9; [L805] havoc eval_#t~nondet9; [L806-L813] assume !(0 != eval_~tmp_ndt_9~0); [L681-L817] COND FALSE !(false) [L684] havoc exists_runnable_thread_#res; [L684] havoc exists_runnable_thread_~__retres1~9; [L621] havoc exists_runnable_thread_~__retres1~9; [L624] COND TRUE 0 == ~m_st~0 [L625] exists_runnable_thread_~__retres1~9 := 1; [L672] exists_runnable_thread_#res := exists_runnable_thread_~__retres1~9; [L684] eval_#t~ret0 := exists_runnable_thread_#res; [L684] eval_~tmp~0 := eval_#t~ret0; [L684] havoc eval_#t~ret0; [L686-L690] COND TRUE 0 != eval_~tmp~0 [L691] COND TRUE 0 == ~m_st~0 [L692] havoc eval_~tmp_ndt_1~0; [L693] eval_~tmp_ndt_1~0 := eval_#t~nondet1; [L693] havoc eval_#t~nondet1; [L694-L701] COND FALSE !(0 != eval_~tmp_ndt_1~0) [L705] COND TRUE 0 == ~t1_st~0 [L706] havoc eval_~tmp_ndt_2~0; [L707] eval_~tmp_ndt_2~0 := eval_#t~nondet2; [L707] havoc eval_#t~nondet2; [L708-L715] COND FALSE !(0 != eval_~tmp_ndt_2~0) [L719] COND TRUE 0 == ~t2_st~0 [L720] havoc eval_~tmp_ndt_3~0; [L721] eval_~tmp_ndt_3~0 := eval_#t~nondet3; [L721] havoc eval_#t~nondet3; [L722-L729] COND FALSE !(0 != eval_~tmp_ndt_3~0) [L733] COND TRUE 0 == ~t3_st~0 [L734] havoc eval_~tmp_ndt_4~0; [L735] eval_~tmp_ndt_4~0 := eval_#t~nondet4; [L735] havoc eval_#t~nondet4; [L736-L743] COND FALSE !(0 != eval_~tmp_ndt_4~0) [L747] COND TRUE 0 == ~t4_st~0 [L748] havoc eval_~tmp_ndt_5~0; [L749] eval_~tmp_ndt_5~0 := eval_#t~nondet5; [L749] havoc eval_#t~nondet5; [L750-L757] COND FALSE !(0 != eval_~tmp_ndt_5~0) [L761] COND TRUE 0 == ~t5_st~0 [L762] havoc eval_~tmp_ndt_6~0; [L763] eval_~tmp_ndt_6~0 := eval_#t~nondet6; [L763] havoc eval_#t~nondet6; [L764-L771] COND FALSE !(0 != eval_~tmp_ndt_6~0) [L775] COND TRUE 0 == ~t6_st~0 [L776] havoc eval_~tmp_ndt_7~0; [L777] eval_~tmp_ndt_7~0 := eval_#t~nondet7; [L777] havoc eval_#t~nondet7; [L778-L785] COND FALSE !(0 != eval_~tmp_ndt_7~0) [L789] COND TRUE 0 == ~t7_st~0 [L790] havoc eval_~tmp_ndt_8~0; [L791] eval_~tmp_ndt_8~0 := eval_#t~nondet8; [L791] havoc eval_#t~nondet8; [L792-L799] COND FALSE !(0 != eval_~tmp_ndt_8~0) [L803] COND TRUE 0 == ~t8_st~0 [L804] havoc eval_~tmp_ndt_9~0; [L805] eval_~tmp_ndt_9~0 := eval_#t~nondet9; [L805] havoc eval_#t~nondet9; [L806-L813] COND FALSE !(0 != eval_~tmp_ndt_9~0) ----- ----- class de.uni_freiburg.informatik.ultimate.boogie.procedureinliner.backtranslation.InlinerBacktranslator [L681-L817] COND FALSE !(false) [L684] havoc exists_runnable_thread_#res; [L684] havoc exists_runnable_thread_~__retres1~9; [L621] havoc exists_runnable_thread_~__retres1~9; [L624] COND TRUE 0 == ~m_st~0 [L625] exists_runnable_thread_~__retres1~9 := 1; [L672] exists_runnable_thread_#res := exists_runnable_thread_~__retres1~9; [L684] eval_#t~ret0 := exists_runnable_thread_#res; [L684] eval_~tmp~0 := eval_#t~ret0; [L684] havoc eval_#t~ret0; [L686-L690] COND TRUE 0 != eval_~tmp~0 [L691] COND TRUE 0 == ~m_st~0 [L692] havoc eval_~tmp_ndt_1~0; [L693] eval_~tmp_ndt_1~0 := eval_#t~nondet1; [L693] havoc eval_#t~nondet1; [L694-L701] COND FALSE !(0 != eval_~tmp_ndt_1~0) [L705] COND TRUE 0 == ~t1_st~0 [L706] havoc eval_~tmp_ndt_2~0; [L707] eval_~tmp_ndt_2~0 := eval_#t~nondet2; [L707] havoc eval_#t~nondet2; [L708-L715] COND FALSE !(0 != eval_~tmp_ndt_2~0) [L719] COND TRUE 0 == ~t2_st~0 [L720] havoc eval_~tmp_ndt_3~0; [L721] eval_~tmp_ndt_3~0 := eval_#t~nondet3; [L721] havoc eval_#t~nondet3; [L722-L729] COND FALSE !(0 != eval_~tmp_ndt_3~0) [L733] COND TRUE 0 == ~t3_st~0 [L734] havoc eval_~tmp_ndt_4~0; [L735] eval_~tmp_ndt_4~0 := eval_#t~nondet4; [L735] havoc eval_#t~nondet4; [L736-L743] COND FALSE !(0 != eval_~tmp_ndt_4~0) [L747] COND TRUE 0 == ~t4_st~0 [L748] havoc eval_~tmp_ndt_5~0; [L749] eval_~tmp_ndt_5~0 := eval_#t~nondet5; [L749] havoc eval_#t~nondet5; [L750-L757] COND FALSE !(0 != eval_~tmp_ndt_5~0) [L761] COND TRUE 0 == ~t5_st~0 [L762] havoc eval_~tmp_ndt_6~0; [L763] eval_~tmp_ndt_6~0 := eval_#t~nondet6; [L763] havoc eval_#t~nondet6; [L764-L771] COND FALSE !(0 != eval_~tmp_ndt_6~0) [L775] COND TRUE 0 == ~t6_st~0 [L776] havoc eval_~tmp_ndt_7~0; [L777] eval_~tmp_ndt_7~0 := eval_#t~nondet7; [L777] havoc eval_#t~nondet7; [L778-L785] COND FALSE !(0 != eval_~tmp_ndt_7~0) [L789] COND TRUE 0 == ~t7_st~0 [L790] havoc eval_~tmp_ndt_8~0; [L791] eval_~tmp_ndt_8~0 := eval_#t~nondet8; [L791] havoc eval_#t~nondet8; [L792-L799] COND FALSE !(0 != eval_~tmp_ndt_8~0) [L803] COND TRUE 0 == ~t8_st~0 [L804] havoc eval_~tmp_ndt_9~0; [L805] eval_~tmp_ndt_9~0 := eval_#t~nondet9; [L805] havoc eval_#t~nondet9; [L806-L813] COND FALSE !(0 != eval_~tmp_ndt_9~0) [L681-L817] COND FALSE !(false) [L621] havoc ~__retres1~9; [L624] COND TRUE 0 == ~m_st~0 [L625] ~__retres1~9 := 1; [L672] #res := ~__retres1~9; [L684] ~tmp~0 := #t~ret0; [L684] havoc #t~ret0; [L686-L690] COND TRUE 0 != ~tmp~0 [L691] COND TRUE 0 == ~m_st~0 [L692] havoc ~tmp_ndt_1~0; [L693] ~tmp_ndt_1~0 := #t~nondet1; [L693] havoc #t~nondet1; [L694-L701] COND FALSE !(0 != ~tmp_ndt_1~0) [L705] COND TRUE 0 == ~t1_st~0 [L706] havoc ~tmp_ndt_2~0; [L707] ~tmp_ndt_2~0 := #t~nondet2; [L707] havoc #t~nondet2; [L708-L715] COND FALSE !(0 != ~tmp_ndt_2~0) [L719] COND TRUE 0 == ~t2_st~0 [L720] havoc ~tmp_ndt_3~0; [L721] ~tmp_ndt_3~0 := #t~nondet3; [L721] havoc #t~nondet3; [L722-L729] COND FALSE !(0 != ~tmp_ndt_3~0) [L733] COND TRUE 0 == ~t3_st~0 [L734] havoc ~tmp_ndt_4~0; [L735] ~tmp_ndt_4~0 := #t~nondet4; [L735] havoc #t~nondet4; [L736-L743] COND FALSE !(0 != ~tmp_ndt_4~0) [L747] COND TRUE 0 == ~t4_st~0 [L748] havoc ~tmp_ndt_5~0; [L749] ~tmp_ndt_5~0 := #t~nondet5; [L749] havoc #t~nondet5; [L750-L757] COND FALSE !(0 != ~tmp_ndt_5~0) [L761] COND TRUE 0 == ~t5_st~0 [L762] havoc ~tmp_ndt_6~0; [L763] ~tmp_ndt_6~0 := #t~nondet6; [L763] havoc #t~nondet6; [L764-L771] COND FALSE !(0 != ~tmp_ndt_6~0) [L775] COND TRUE 0 == ~t6_st~0 [L776] havoc ~tmp_ndt_7~0; [L777] ~tmp_ndt_7~0 := #t~nondet7; [L777] havoc #t~nondet7; [L778-L785] COND FALSE !(0 != ~tmp_ndt_7~0) [L789] COND TRUE 0 == ~t7_st~0 [L790] havoc ~tmp_ndt_8~0; [L791] ~tmp_ndt_8~0 := #t~nondet8; [L791] havoc #t~nondet8; [L792-L799] COND FALSE !(0 != ~tmp_ndt_8~0) [L803] COND TRUE 0 == ~t8_st~0 [L804] havoc ~tmp_ndt_9~0; [L805] ~tmp_ndt_9~0 := #t~nondet9; [L805] havoc #t~nondet9; [L806-L813] COND FALSE !(0 != ~tmp_ndt_9~0) ----- ----- class de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.CACSL2BoogieBacktranslator [L681-L817] COND FALSE !(false) [L621] havoc ~__retres1~9; [L624] COND TRUE 0 == ~m_st~0 [L625] ~__retres1~9 := 1; [L672] #res := ~__retres1~9; [L684] ~tmp~0 := #t~ret0; [L684] havoc #t~ret0; [L686-L690] COND TRUE 0 != ~tmp~0 [L691] COND TRUE 0 == ~m_st~0 [L692] havoc ~tmp_ndt_1~0; [L693] ~tmp_ndt_1~0 := #t~nondet1; [L693] havoc #t~nondet1; [L694-L701] COND FALSE !(0 != ~tmp_ndt_1~0) [L705] COND TRUE 0 == ~t1_st~0 [L706] havoc ~tmp_ndt_2~0; [L707] ~tmp_ndt_2~0 := #t~nondet2; [L707] havoc #t~nondet2; [L708-L715] COND FALSE !(0 != ~tmp_ndt_2~0) [L719] COND TRUE 0 == ~t2_st~0 [L720] havoc ~tmp_ndt_3~0; [L721] ~tmp_ndt_3~0 := #t~nondet3; [L721] havoc #t~nondet3; [L722-L729] COND FALSE !(0 != ~tmp_ndt_3~0) [L733] COND TRUE 0 == ~t3_st~0 [L734] havoc ~tmp_ndt_4~0; [L735] ~tmp_ndt_4~0 := #t~nondet4; [L735] havoc #t~nondet4; [L736-L743] COND FALSE !(0 != ~tmp_ndt_4~0) [L747] COND TRUE 0 == ~t4_st~0 [L748] havoc ~tmp_ndt_5~0; [L749] ~tmp_ndt_5~0 := #t~nondet5; [L749] havoc #t~nondet5; [L750-L757] COND FALSE !(0 != ~tmp_ndt_5~0) [L761] COND TRUE 0 == ~t5_st~0 [L762] havoc ~tmp_ndt_6~0; [L763] ~tmp_ndt_6~0 := #t~nondet6; [L763] havoc #t~nondet6; [L764-L771] COND FALSE !(0 != ~tmp_ndt_6~0) [L775] COND TRUE 0 == ~t6_st~0 [L776] havoc ~tmp_ndt_7~0; [L777] ~tmp_ndt_7~0 := #t~nondet7; [L777] havoc #t~nondet7; [L778-L785] COND FALSE !(0 != ~tmp_ndt_7~0) [L789] COND TRUE 0 == ~t7_st~0 [L790] havoc ~tmp_ndt_8~0; [L791] ~tmp_ndt_8~0 := #t~nondet8; [L791] havoc #t~nondet8; [L792-L799] COND FALSE !(0 != ~tmp_ndt_8~0) [L803] COND TRUE 0 == ~t8_st~0 [L804] havoc ~tmp_ndt_9~0; [L805] ~tmp_ndt_9~0 := #t~nondet9; [L805] havoc #t~nondet9; [L806-L813] COND FALSE !(0 != ~tmp_ndt_9~0) [L681] COND TRUE 1 [L621] int __retres1 ; [L624] COND TRUE m_st == 0 [L625] __retres1 = 1 [L672] return (__retres1); [L684] tmp = exists_runnable_thread() [L686] COND TRUE \read(tmp) [L691] COND TRUE m_st == 0 [L692] int tmp_ndt_1; [L693] tmp_ndt_1 = __VERIFIER_nondet_int() [L694] COND FALSE !(\read(tmp_ndt_1)) [L705] COND TRUE t1_st == 0 [L706] int tmp_ndt_2; [L707] tmp_ndt_2 = __VERIFIER_nondet_int() [L708] COND FALSE !(\read(tmp_ndt_2)) [L719] COND TRUE t2_st == 0 [L720] int tmp_ndt_3; [L721] tmp_ndt_3 = __VERIFIER_nondet_int() [L722] COND FALSE !(\read(tmp_ndt_3)) [L733] COND TRUE t3_st == 0 [L734] int tmp_ndt_4; [L735] tmp_ndt_4 = __VERIFIER_nondet_int() [L736] COND FALSE !(\read(tmp_ndt_4)) [L747] COND TRUE t4_st == 0 [L748] int tmp_ndt_5; [L749] tmp_ndt_5 = __VERIFIER_nondet_int() [L750] COND FALSE !(\read(tmp_ndt_5)) [L761] COND TRUE t5_st == 0 [L762] int tmp_ndt_6; [L763] tmp_ndt_6 = __VERIFIER_nondet_int() [L764] COND FALSE !(\read(tmp_ndt_6)) [L775] COND TRUE t6_st == 0 [L776] int tmp_ndt_7; [L777] tmp_ndt_7 = __VERIFIER_nondet_int() [L778] COND FALSE !(\read(tmp_ndt_7)) [L789] COND TRUE t7_st == 0 [L790] int tmp_ndt_8; [L791] tmp_ndt_8 = __VERIFIER_nondet_int() [L792] COND FALSE !(\read(tmp_ndt_8)) [L803] COND TRUE t8_st == 0 [L804] int tmp_ndt_9; [L805] tmp_ndt_9 = __VERIFIER_nondet_int() [L806] COND FALSE !(\read(tmp_ndt_9)) ----- [2018-11-22 21:24:18,922 INFO L145 WitnessManager]: Wrote witness to /tmp/vcloud-vcloud-master/worker/working_dir_c1610823-20be-413b-8144-c2fdf28119b5/bin-2019/uautomizer/witness.graphml [2018-11-22 21:24:18,965 INFO L132 PluginConnector]: ------------------------ END Witness Printer---------------------------- [2018-11-22 21:24:18,966 INFO L168 Benchmark]: Toolchain (without parser) took 167531.78 ms. Allocated memory was 1.0 GB in the beginning and 11.5 GB in the end (delta: 10.4 GB). Free memory was 959.2 MB in the beginning and 3.3 GB in the end (delta: -2.3 GB). Peak memory consumption was 8.1 GB. Max. memory is 11.5 GB. [2018-11-22 21:24:18,967 INFO L168 Benchmark]: CDTParser took 0.16 ms. Allocated memory is still 1.0 GB. Free memory is still 985.5 MB. There was no memory consumed. Max. memory is 11.5 GB. [2018-11-22 21:24:18,967 INFO L168 Benchmark]: CACSL2BoogieTranslator took 283.97 ms. Allocated memory is still 1.0 GB. Free memory was 959.2 MB in the beginning and 935.1 MB in the end (delta: 24.2 MB). Peak memory consumption was 24.2 MB. Max. memory is 11.5 GB. [2018-11-22 21:24:18,967 INFO L168 Benchmark]: Boogie Procedure Inliner took 97.27 ms. Allocated memory was 1.0 GB in the beginning and 1.2 GB in the end (delta: 146.3 MB). Free memory was 935.1 MB in the beginning and 1.1 GB in the end (delta: -202.8 MB). Peak memory consumption was 15.3 MB. Max. memory is 11.5 GB. [2018-11-22 21:24:18,968 INFO L168 Benchmark]: Boogie Preprocessor took 62.15 ms. Allocated memory is still 1.2 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 8.1 MB). Peak memory consumption was 8.1 MB. Max. memory is 11.5 GB. [2018-11-22 21:24:18,968 INFO L168 Benchmark]: RCFGBuilder took 1189.94 ms. Allocated memory is still 1.2 GB. Free memory was 1.1 GB in the beginning and 940.5 MB in the end (delta: 189.3 MB). Peak memory consumption was 189.3 MB. Max. memory is 11.5 GB. [2018-11-22 21:24:18,968 INFO L168 Benchmark]: BuchiAutomizer took 162308.76 ms. Allocated memory was 1.2 GB in the beginning and 11.5 GB in the end (delta: 10.3 GB). Free memory was 940.5 MB in the beginning and 3.3 GB in the end (delta: -2.3 GB). Peak memory consumption was 7.9 GB. Max. memory is 11.5 GB. [2018-11-22 21:24:18,968 INFO L168 Benchmark]: Witness Printer took 3586.67 ms. Allocated memory is still 11.5 GB. Free memory was 3.3 GB in the beginning and 3.3 GB in the end (delta: 28.6 MB). Peak memory consumption was 28.6 MB. Max. memory is 11.5 GB. [2018-11-22 21:24:18,970 INFO L336 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.16 ms. Allocated memory is still 1.0 GB. Free memory is still 985.5 MB. There was no memory consumed. Max. memory is 11.5 GB. * CACSL2BoogieTranslator took 283.97 ms. Allocated memory is still 1.0 GB. Free memory was 959.2 MB in the beginning and 935.1 MB in the end (delta: 24.2 MB). Peak memory consumption was 24.2 MB. Max. memory is 11.5 GB. * Boogie Procedure Inliner took 97.27 ms. Allocated memory was 1.0 GB in the beginning and 1.2 GB in the end (delta: 146.3 MB). Free memory was 935.1 MB in the beginning and 1.1 GB in the end (delta: -202.8 MB). Peak memory consumption was 15.3 MB. Max. memory is 11.5 GB. * Boogie Preprocessor took 62.15 ms. Allocated memory is still 1.2 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 8.1 MB). Peak memory consumption was 8.1 MB. Max. memory is 11.5 GB. * RCFGBuilder took 1189.94 ms. Allocated memory is still 1.2 GB. Free memory was 1.1 GB in the beginning and 940.5 MB in the end (delta: 189.3 MB). Peak memory consumption was 189.3 MB. Max. memory is 11.5 GB. * BuchiAutomizer took 162308.76 ms. Allocated memory was 1.2 GB in the beginning and 11.5 GB in the end (delta: 10.3 GB). Free memory was 940.5 MB in the beginning and 3.3 GB in the end (delta: -2.3 GB). Peak memory consumption was 7.9 GB. Max. memory is 11.5 GB. * Witness Printer took 3586.67 ms. Allocated memory is still 11.5 GB. Free memory was 3.3 GB in the beginning and 3.3 GB in the end (delta: 28.6 MB). Peak memory consumption was 28.6 MB. Max. memory is 11.5 GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - StatisticsResult: Constructed decomposition of program Your program was decomposed into 38 terminating modules (38 trivial, 0 deterministic, 0 nondeterministic) and one nonterminating remainder module.38 modules have a trivial ranking function, the largest among these consists of 5 locations. The remainder module has 1526889 locations. - StatisticsResult: Timing statistics BüchiAutomizer plugin needed 160.7s and 39 iterations. TraceHistogramMax:3. Analysis of lassos took 6.5s. Construction of modules took 1.7s. Büchi inclusion checks took 15.5s. Highest rank in rank-based complementation 0. Minimization of det autom 38. Minimization of nondet autom 0. Automata minimization 76.0s AutomataMinimizationTime, 38 MinimizatonAttempts, 517770 StatesRemovedByMinimization, 21 NontrivialMinimizations. Non-live state removal took 44.7s Buchi closure took 1.9s. Biggest automaton had 1526889 states and ocurred in iteration 38. Nontrivial modules had stage [0, 0, 0, 0, 0]. InterpolantCoveringCapabilityFinite: 0/0 InterpolantCoveringCapabilityBuchi: 0/0 HoareTripleCheckerStatistics: 53475 SDtfs, 64049 SDslu, 56643 SDs, 0 SdLazy, 1463 SolverSat, 710 SolverUnsat, 0 SolverUnknown, 0 SolverNotchecked, 1.7s Time LassoAnalysisResults: nont1 unkn0 SFLI11 SFLT0 conc7 concLT0 SILN0 SILU0 SILI20 SILT0 lasso0 LassoPreprocessingBenchmarks: LassoTerminationAnalysisBenchmarks: not availableLassoTerminationAnalysisBenchmarks: LassoNonterminationAnalysisSatFixpoint: 0 LassoNonterminationAnalysisSatUnbounded: 0 LassoNonterminationAnalysisUnsat: 0 LassoNonterminationAnalysisUnknown: 0 LassoNonterminationAnalysisTime: 0.0s - TerminationAnalysisResult: Nontermination possible Buchi Automizer proved that your program is nonterminating for some inputs - FixpointNonTerminationResult [Line: 681]: Nontermination argument in form of an infinite program execution. Nontermination argument in form of an infinite execution State at position 0 is {} State at position 1 is {E_7=2, t3_st=0, __retres1=0, t5_i=1, __retres1=0, kernel_st=1, \result=0, E_3=2, T6_E=2, t7_i=1, tmp_ndt_8=0, tmp_ndt_4=0, \result=0, __retres1=0, m_st=0, t6_pc=0, tmp___2=0, t3_pc=0, \result=0, m_pc=0, tmp___6=0, T8_E=2, t6_st=0, E_6=2, __retres1=0, \result=0, T2_E=2, t8_i=1, t5_st=0, __retres1=1, E_2=2, t7_pc=0, tmp=0, M_E=2, tmp_ndt_3=0, __retres1=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@5eb6cee6=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@44110af=0, T4_E=2, t4_st=0, t3_i=1, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@6ce8222a=0, t8_pc=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@3d46499e=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@64201cd=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@3c02a6c2=0, t5_pc=0, t7_st=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@30ca0c1c=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@1d1e84e7=0, \result=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@121b3583=0, tmp_ndt_7=0, tmp___3=0, t1_i=1, tmp___7=0, __retres1=0, T7_E=2, tmp=1, t2_st=0, t4_i=1, t8_st=0, t4_pc=0, E_5=2, \result=0, E_1=2, tmp_ndt_2=0, \result=0, __retres1=0, tmp_ndt_6=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@3777fea7=0, tmp___0=0, tmp=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@430d3173=0, t6_i=1, tmp___4=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@3803e2d1=0, \result=0, __retres1=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@3cd59822=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@2ae536a9=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@37325188=0, \result=0, E_8=2, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@53caf50a=0, tmp___0=0, t1_pc=0, E_4=2, T1_E=2, tmp_ndt_1=0, T5_E=2, t2_i=1, tmp_ndt_9=0, m_i=1, t1_st=0, tmp_ndt_5=0, __retres1=0, t2_pc=0, __retres1=0, tmp___1=0, \result=0, T3_E=2, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@35300776=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@61bb5a9b=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@6708df85=0, \result=1, tmp___5=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@283f6eb4=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@6c983c94=0} - StatisticsResult: NonterminationArgumentStatistics Fixpoint - NonterminatingLassoResult [Line: 681]: Nonterminating execution ----- class de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder.RCFGBacktranslator [?] ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2; [?] havoc main_#res;havoc main_~__retres1~10;havoc main_~__retres1~10;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; [?] havoc start_simulation_#t~ret20, start_simulation_#t~ret21, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; [?] assume 1 == ~m_i~0;~m_st~0 := 0; [?] assume 1 == ~t1_i~0;~t1_st~0 := 0; [?] assume 1 == ~t2_i~0;~t2_st~0 := 0; [?] assume 1 == ~t3_i~0;~t3_st~0 := 0; [?] assume 1 == ~t4_i~0;~t4_st~0 := 0; [?] assume 1 == ~t5_i~0;~t5_st~0 := 0; [?] assume 1 == ~t6_i~0;~t6_st~0 := 0; [?] assume 1 == ~t7_i~0;~t7_st~0 := 0; [?] assume 1 == ~t8_i~0;~t8_st~0 := 0; [?] assume !(0 == ~M_E~0); [?] assume !(0 == ~T1_E~0); [?] assume !(0 == ~T2_E~0); [?] assume !(0 == ~T3_E~0); [?] assume !(0 == ~T4_E~0); [?] assume !(0 == ~T5_E~0); [?] assume !(0 == ~T6_E~0); [?] assume !(0 == ~T7_E~0); [?] assume !(0 == ~T8_E~0); [?] assume !(0 == ~E_1~0); [?] assume !(0 == ~E_2~0); [?] assume !(0 == ~E_3~0); [?] assume !(0 == ~E_4~0); [?] assume !(0 == ~E_5~0); [?] assume !(0 == ~E_6~0); [?] assume !(0 == ~E_7~0); [?] assume !(0 == ~E_8~0); [?] havoc activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; [?] assume !(1 == ~m_pc~0); [?] is_master_triggered_~__retres1~0 := 0; [?] is_master_triggered_#res := is_master_triggered_~__retres1~0; [?] activate_threads_#t~ret10 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; [?] assume !(0 != activate_threads_~tmp~1); [?] havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; [?] assume !(1 == ~t1_pc~0); [?] is_transmit1_triggered_~__retres1~1 := 0; [?] is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; [?] activate_threads_#t~ret11 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; [?] assume !(0 != activate_threads_~tmp___0~0); [?] havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; [?] assume !(1 == ~t2_pc~0); [?] is_transmit2_triggered_~__retres1~2 := 0; [?] is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; [?] activate_threads_#t~ret12 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; [?] assume !(0 != activate_threads_~tmp___1~0); [?] havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; [?] assume !(1 == ~t3_pc~0); [?] is_transmit3_triggered_~__retres1~3 := 0; [?] is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; [?] activate_threads_#t~ret13 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; [?] assume !(0 != activate_threads_~tmp___2~0); [?] havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; [?] assume !(1 == ~t4_pc~0); [?] is_transmit4_triggered_~__retres1~4 := 0; [?] is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; [?] activate_threads_#t~ret14 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; [?] assume !(0 != activate_threads_~tmp___3~0); [?] havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; [?] assume !(1 == ~t5_pc~0); [?] is_transmit5_triggered_~__retres1~5 := 0; [?] is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; [?] activate_threads_#t~ret15 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; [?] assume !(0 != activate_threads_~tmp___4~0); [?] havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; [?] assume !(1 == ~t6_pc~0); [?] is_transmit6_triggered_~__retres1~6 := 0; [?] is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; [?] activate_threads_#t~ret16 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; [?] assume !(0 != activate_threads_~tmp___5~0); [?] havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; [?] assume !(1 == ~t7_pc~0); [?] is_transmit7_triggered_~__retres1~7 := 0; [?] is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; [?] activate_threads_#t~ret17 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; [?] assume !(0 != activate_threads_~tmp___6~0); [?] havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; [?] assume !(1 == ~t8_pc~0); [?] is_transmit8_triggered_~__retres1~8 := 0; [?] is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; [?] activate_threads_#t~ret18 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; [?] assume !(0 != activate_threads_~tmp___7~0); [?] assume !(1 == ~M_E~0); [?] assume !(1 == ~T1_E~0); [?] assume !(1 == ~T2_E~0); [?] assume !(1 == ~T3_E~0); [?] assume !(1 == ~T4_E~0); [?] assume !(1 == ~T5_E~0); [?] assume !(1 == ~T6_E~0); [?] assume !(1 == ~T7_E~0); [?] assume !(1 == ~T8_E~0); [?] assume !(1 == ~E_1~0); [?] assume !(1 == ~E_2~0); [?] assume !(1 == ~E_3~0); [?] assume !(1 == ~E_4~0); [?] assume !(1 == ~E_5~0); [?] assume !(1 == ~E_6~0); [?] assume !(1 == ~E_7~0); [?] assume !(1 == ~E_8~0); [?] assume !false; [?] start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret0, eval_#t~nondet1, eval_~tmp_ndt_1~0, eval_#t~nondet2, eval_~tmp_ndt_2~0, eval_#t~nondet3, eval_~tmp_ndt_3~0, eval_#t~nondet4, eval_~tmp_ndt_4~0, eval_#t~nondet5, eval_~tmp_ndt_5~0, eval_#t~nondet6, eval_~tmp_ndt_6~0, eval_#t~nondet7, eval_~tmp_ndt_7~0, eval_#t~nondet8, eval_~tmp_ndt_8~0, eval_#t~nondet9, eval_~tmp_ndt_9~0, eval_~tmp~0;havoc eval_~tmp~0; [L15] ~m_pc~0 := 0; [L16] ~t1_pc~0 := 0; [L17] ~t2_pc~0 := 0; [L18] ~t3_pc~0 := 0; [L19] ~t4_pc~0 := 0; [L20] ~t5_pc~0 := 0; [L21] ~t6_pc~0 := 0; [L22] ~t7_pc~0 := 0; [L23] ~t8_pc~0 := 0; [L24] ~m_st~0 := 0; [L25] ~t1_st~0 := 0; [L26] ~t2_st~0 := 0; [L27] ~t3_st~0 := 0; [L28] ~t4_st~0 := 0; [L29] ~t5_st~0 := 0; [L30] ~t6_st~0 := 0; [L31] ~t7_st~0 := 0; [L32] ~t8_st~0 := 0; [L33] ~m_i~0 := 0; [L34] ~t1_i~0 := 0; [L35] ~t2_i~0 := 0; [L36] ~t3_i~0 := 0; [L37] ~t4_i~0 := 0; [L38] ~t5_i~0 := 0; [L39] ~t6_i~0 := 0; [L40] ~t7_i~0 := 0; [L41] ~t8_i~0 := 0; [L42] ~M_E~0 := 2; [L43] ~T1_E~0 := 2; [L44] ~T2_E~0 := 2; [L45] ~T3_E~0 := 2; [L46] ~T4_E~0 := 2; [L47] ~T5_E~0 := 2; [L48] ~T6_E~0 := 2; [L49] ~T7_E~0 := 2; [L50] ~T8_E~0 := 2; [L51] ~E_1~0 := 2; [L52] ~E_2~0 := 2; [L53] ~E_3~0 := 2; [L54] ~E_4~0 := 2; [L55] ~E_5~0 := 2; [L56] ~E_6~0 := 2; [L57] ~E_7~0 := 2; [L58] ~E_8~0 := 2; [?] havoc main_#res; [?] havoc main_~__retres1~10; [L1307] havoc main_~__retres1~10; [L1215] ~m_i~0 := 1; [L1216] ~t1_i~0 := 1; [L1217] ~t2_i~0 := 1; [L1218] ~t3_i~0 := 1; [L1219] ~t4_i~0 := 1; [L1220] ~t5_i~0 := 1; [L1221] ~t6_i~0 := 1; [L1222] ~t7_i~0 := 1; [L1223] ~t8_i~0 := 1; [L1312] havoc start_simulation_#t~ret20, start_simulation_#t~ret21, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1; [L1248] havoc start_simulation_~kernel_st~0; [L1249] havoc start_simulation_~tmp~3; [L1250] havoc start_simulation_~tmp___0~1; [L1254] start_simulation_~kernel_st~0 := 0; [L571-L575] assume 1 == ~m_i~0; [L572] ~m_st~0 := 0; [L576-L580] assume 1 == ~t1_i~0; [L577] ~t1_st~0 := 0; [L581-L585] assume 1 == ~t2_i~0; [L582] ~t2_st~0 := 0; [L586-L590] assume 1 == ~t3_i~0; [L587] ~t3_st~0 := 0; [L591-L595] assume 1 == ~t4_i~0; [L592] ~t4_st~0 := 0; [L596-L600] assume 1 == ~t5_i~0; [L597] ~t5_st~0 := 0; [L601-L605] assume 1 == ~t6_i~0; [L602] ~t6_st~0 := 0; [L606-L610] assume 1 == ~t7_i~0; [L607] ~t7_st~0 := 0; [L611-L615] assume 1 == ~t8_i~0; [L612] ~t8_st~0 := 0; [L828-L832] assume !(0 == ~M_E~0); [L833-L837] assume !(0 == ~T1_E~0); [L838-L842] assume !(0 == ~T2_E~0); [L843-L847] assume !(0 == ~T3_E~0); [L848-L852] assume !(0 == ~T4_E~0); [L853-L857] assume !(0 == ~T5_E~0); [L858-L862] assume !(0 == ~T6_E~0); [L863-L867] assume !(0 == ~T7_E~0); [L868-L872] assume !(0 == ~T8_E~0); [L873-L877] assume !(0 == ~E_1~0); [L878-L882] assume !(0 == ~E_2~0); [L883-L887] assume !(0 == ~E_3~0); [L888-L892] assume !(0 == ~E_4~0); [L893-L897] assume !(0 == ~E_5~0); [L898-L902] assume !(0 == ~E_6~0); [L903-L907] assume !(0 == ~E_7~0); [L908-L912] assume !(0 == ~E_8~0); [L1258] havoc activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0; [L1011] havoc activate_threads_~tmp~1; [L1012] havoc activate_threads_~tmp___0~0; [L1013] havoc activate_threads_~tmp___1~0; [L1014] havoc activate_threads_~tmp___2~0; [L1015] havoc activate_threads_~tmp___3~0; [L1016] havoc activate_threads_~tmp___4~0; [L1017] havoc activate_threads_~tmp___5~0; [L1018] havoc activate_threads_~tmp___6~0; [L1019] havoc activate_threads_~tmp___7~0; [L1023] havoc is_master_triggered_#res; [L1023] havoc is_master_triggered_~__retres1~0; [L389] havoc is_master_triggered_~__retres1~0; [L392-L401] assume !(1 == ~m_pc~0); [L402] is_master_triggered_~__retres1~0 := 0; [L404] is_master_triggered_#res := is_master_triggered_~__retres1~0; [L1023] activate_threads_#t~ret10 := is_master_triggered_#res; [L1023] activate_threads_~tmp~1 := activate_threads_#t~ret10; [L1023] havoc activate_threads_#t~ret10; [L1025-L1029] assume !(0 != activate_threads_~tmp~1); [L1031] havoc is_transmit1_triggered_#res; [L1031] havoc is_transmit1_triggered_~__retres1~1; [L408] havoc is_transmit1_triggered_~__retres1~1; [L411-L420] assume !(1 == ~t1_pc~0); [L421] is_transmit1_triggered_~__retres1~1 := 0; [L423] is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; [L1031] activate_threads_#t~ret11 := is_transmit1_triggered_#res; [L1031] activate_threads_~tmp___0~0 := activate_threads_#t~ret11; [L1031] havoc activate_threads_#t~ret11; [L1033-L1037] assume !(0 != activate_threads_~tmp___0~0); [L1039] havoc is_transmit2_triggered_#res; [L1039] havoc is_transmit2_triggered_~__retres1~2; [L427] havoc is_transmit2_triggered_~__retres1~2; [L430-L439] assume !(1 == ~t2_pc~0); [L440] is_transmit2_triggered_~__retres1~2 := 0; [L442] is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; [L1039] activate_threads_#t~ret12 := is_transmit2_triggered_#res; [L1039] activate_threads_~tmp___1~0 := activate_threads_#t~ret12; [L1039] havoc activate_threads_#t~ret12; [L1041-L1045] assume !(0 != activate_threads_~tmp___1~0); [L1047] havoc is_transmit3_triggered_#res; [L1047] havoc is_transmit3_triggered_~__retres1~3; [L446] havoc is_transmit3_triggered_~__retres1~3; [L449-L458] assume !(1 == ~t3_pc~0); [L459] is_transmit3_triggered_~__retres1~3 := 0; [L461] is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; [L1047] activate_threads_#t~ret13 := is_transmit3_triggered_#res; [L1047] activate_threads_~tmp___2~0 := activate_threads_#t~ret13; [L1047] havoc activate_threads_#t~ret13; [L1049-L1053] assume !(0 != activate_threads_~tmp___2~0); [L1055] havoc is_transmit4_triggered_#res; [L1055] havoc is_transmit4_triggered_~__retres1~4; [L465] havoc is_transmit4_triggered_~__retres1~4; [L468-L477] assume !(1 == ~t4_pc~0); [L478] is_transmit4_triggered_~__retres1~4 := 0; [L480] is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; [L1055] activate_threads_#t~ret14 := is_transmit4_triggered_#res; [L1055] activate_threads_~tmp___3~0 := activate_threads_#t~ret14; [L1055] havoc activate_threads_#t~ret14; [L1057-L1061] assume !(0 != activate_threads_~tmp___3~0); [L1063] havoc is_transmit5_triggered_#res; [L1063] havoc is_transmit5_triggered_~__retres1~5; [L484] havoc is_transmit5_triggered_~__retres1~5; [L487-L496] assume !(1 == ~t5_pc~0); [L497] is_transmit5_triggered_~__retres1~5 := 0; [L499] is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; [L1063] activate_threads_#t~ret15 := is_transmit5_triggered_#res; [L1063] activate_threads_~tmp___4~0 := activate_threads_#t~ret15; [L1063] havoc activate_threads_#t~ret15; [L1065-L1069] assume !(0 != activate_threads_~tmp___4~0); [L1071] havoc is_transmit6_triggered_#res; [L1071] havoc is_transmit6_triggered_~__retres1~6; [L503] havoc is_transmit6_triggered_~__retres1~6; [L506-L515] assume !(1 == ~t6_pc~0); [L516] is_transmit6_triggered_~__retres1~6 := 0; [L518] is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; [L1071] activate_threads_#t~ret16 := is_transmit6_triggered_#res; [L1071] activate_threads_~tmp___5~0 := activate_threads_#t~ret16; [L1071] havoc activate_threads_#t~ret16; [L1073-L1077] assume !(0 != activate_threads_~tmp___5~0); [L1079] havoc is_transmit7_triggered_#res; [L1079] havoc is_transmit7_triggered_~__retres1~7; [L522] havoc is_transmit7_triggered_~__retres1~7; [L525-L534] assume !(1 == ~t7_pc~0); [L535] is_transmit7_triggered_~__retres1~7 := 0; [L537] is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; [L1079] activate_threads_#t~ret17 := is_transmit7_triggered_#res; [L1079] activate_threads_~tmp___6~0 := activate_threads_#t~ret17; [L1079] havoc activate_threads_#t~ret17; [L1081-L1085] assume !(0 != activate_threads_~tmp___6~0); [L1087] havoc is_transmit8_triggered_#res; [L1087] havoc is_transmit8_triggered_~__retres1~8; [L541] havoc is_transmit8_triggered_~__retres1~8; [L544-L553] assume !(1 == ~t8_pc~0); [L554] is_transmit8_triggered_~__retres1~8 := 0; [L556] is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; [L1087] activate_threads_#t~ret18 := is_transmit8_triggered_#res; [L1087] activate_threads_~tmp___7~0 := activate_threads_#t~ret18; [L1087] havoc activate_threads_#t~ret18; [L1089-L1093] assume !(0 != activate_threads_~tmp___7~0); [L921-L925] assume !(1 == ~M_E~0); [L926-L930] assume !(1 == ~T1_E~0); [L931-L935] assume !(1 == ~T2_E~0); [L936-L940] assume !(1 == ~T3_E~0); [L941-L945] assume !(1 == ~T4_E~0); [L946-L950] assume !(1 == ~T5_E~0); [L951-L955] assume !(1 == ~T6_E~0); [L956-L960] assume !(1 == ~T7_E~0); [L961-L965] assume !(1 == ~T8_E~0); [L966-L970] assume !(1 == ~E_1~0); [L971-L975] assume !(1 == ~E_2~0); [L976-L980] assume !(1 == ~E_3~0); [L981-L985] assume !(1 == ~E_4~0); [L986-L990] assume !(1 == ~E_5~0); [L991-L995] assume !(1 == ~E_6~0); [L996-L1000] assume !(1 == ~E_7~0); [L1001-L1005] assume !(1 == ~E_8~0); [L1262-L1299] assume !false; [L1265] start_simulation_~kernel_st~0 := 1; [L1266] havoc eval_#t~ret0, eval_#t~nondet1, eval_~tmp_ndt_1~0, eval_#t~nondet2, eval_~tmp_ndt_2~0, eval_#t~nondet3, eval_~tmp_ndt_3~0, eval_#t~nondet4, eval_~tmp_ndt_4~0, eval_#t~nondet5, eval_~tmp_ndt_5~0, eval_#t~nondet6, eval_~tmp_ndt_6~0, eval_#t~nondet7, eval_~tmp_ndt_7~0, eval_#t~nondet8, eval_~tmp_ndt_8~0, eval_#t~nondet9, eval_~tmp_ndt_9~0, eval_~tmp~0; [L677] havoc eval_~tmp~0; ----- ----- class de.uni_freiburg.informatik.ultimate.boogie.preprocessor.BoogiePreprocessorBacktranslator [L15] ~m_pc~0 := 0; [L16] ~t1_pc~0 := 0; [L17] ~t2_pc~0 := 0; [L18] ~t3_pc~0 := 0; [L19] ~t4_pc~0 := 0; [L20] ~t5_pc~0 := 0; [L21] ~t6_pc~0 := 0; [L22] ~t7_pc~0 := 0; [L23] ~t8_pc~0 := 0; [L24] ~m_st~0 := 0; [L25] ~t1_st~0 := 0; [L26] ~t2_st~0 := 0; [L27] ~t3_st~0 := 0; [L28] ~t4_st~0 := 0; [L29] ~t5_st~0 := 0; [L30] ~t6_st~0 := 0; [L31] ~t7_st~0 := 0; [L32] ~t8_st~0 := 0; [L33] ~m_i~0 := 0; [L34] ~t1_i~0 := 0; [L35] ~t2_i~0 := 0; [L36] ~t3_i~0 := 0; [L37] ~t4_i~0 := 0; [L38] ~t5_i~0 := 0; [L39] ~t6_i~0 := 0; [L40] ~t7_i~0 := 0; [L41] ~t8_i~0 := 0; [L42] ~M_E~0 := 2; [L43] ~T1_E~0 := 2; [L44] ~T2_E~0 := 2; [L45] ~T3_E~0 := 2; [L46] ~T4_E~0 := 2; [L47] ~T5_E~0 := 2; [L48] ~T6_E~0 := 2; [L49] ~T7_E~0 := 2; [L50] ~T8_E~0 := 2; [L51] ~E_1~0 := 2; [L52] ~E_2~0 := 2; [L53] ~E_3~0 := 2; [L54] ~E_4~0 := 2; [L55] ~E_5~0 := 2; [L56] ~E_6~0 := 2; [L57] ~E_7~0 := 2; [L58] ~E_8~0 := 2; [?] havoc main_#res; [?] havoc main_~__retres1~10; [L1307] havoc main_~__retres1~10; [L1215] ~m_i~0 := 1; [L1216] ~t1_i~0 := 1; [L1217] ~t2_i~0 := 1; [L1218] ~t3_i~0 := 1; [L1219] ~t4_i~0 := 1; [L1220] ~t5_i~0 := 1; [L1221] ~t6_i~0 := 1; [L1222] ~t7_i~0 := 1; [L1223] ~t8_i~0 := 1; [L1312] havoc start_simulation_#t~ret20, start_simulation_#t~ret21, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1; [L1248] havoc start_simulation_~kernel_st~0; [L1249] havoc start_simulation_~tmp~3; [L1250] havoc start_simulation_~tmp___0~1; [L1254] start_simulation_~kernel_st~0 := 0; [L571-L575] assume 1 == ~m_i~0; [L572] ~m_st~0 := 0; [L576-L580] assume 1 == ~t1_i~0; [L577] ~t1_st~0 := 0; [L581-L585] assume 1 == ~t2_i~0; [L582] ~t2_st~0 := 0; [L586-L590] assume 1 == ~t3_i~0; [L587] ~t3_st~0 := 0; [L591-L595] assume 1 == ~t4_i~0; [L592] ~t4_st~0 := 0; [L596-L600] assume 1 == ~t5_i~0; [L597] ~t5_st~0 := 0; [L601-L605] assume 1 == ~t6_i~0; [L602] ~t6_st~0 := 0; [L606-L610] assume 1 == ~t7_i~0; [L607] ~t7_st~0 := 0; [L611-L615] assume 1 == ~t8_i~0; [L612] ~t8_st~0 := 0; [L828-L832] assume !(0 == ~M_E~0); [L833-L837] assume !(0 == ~T1_E~0); [L838-L842] assume !(0 == ~T2_E~0); [L843-L847] assume !(0 == ~T3_E~0); [L848-L852] assume !(0 == ~T4_E~0); [L853-L857] assume !(0 == ~T5_E~0); [L858-L862] assume !(0 == ~T6_E~0); [L863-L867] assume !(0 == ~T7_E~0); [L868-L872] assume !(0 == ~T8_E~0); [L873-L877] assume !(0 == ~E_1~0); [L878-L882] assume !(0 == ~E_2~0); [L883-L887] assume !(0 == ~E_3~0); [L888-L892] assume !(0 == ~E_4~0); [L893-L897] assume !(0 == ~E_5~0); [L898-L902] assume !(0 == ~E_6~0); [L903-L907] assume !(0 == ~E_7~0); [L908-L912] assume !(0 == ~E_8~0); [L1258] havoc activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0; [L1011] havoc activate_threads_~tmp~1; [L1012] havoc activate_threads_~tmp___0~0; [L1013] havoc activate_threads_~tmp___1~0; [L1014] havoc activate_threads_~tmp___2~0; [L1015] havoc activate_threads_~tmp___3~0; [L1016] havoc activate_threads_~tmp___4~0; [L1017] havoc activate_threads_~tmp___5~0; [L1018] havoc activate_threads_~tmp___6~0; [L1019] havoc activate_threads_~tmp___7~0; [L1023] havoc is_master_triggered_#res; [L1023] havoc is_master_triggered_~__retres1~0; [L389] havoc is_master_triggered_~__retres1~0; [L392-L401] assume !(1 == ~m_pc~0); [L402] is_master_triggered_~__retres1~0 := 0; [L404] is_master_triggered_#res := is_master_triggered_~__retres1~0; [L1023] activate_threads_#t~ret10 := is_master_triggered_#res; [L1023] activate_threads_~tmp~1 := activate_threads_#t~ret10; [L1023] havoc activate_threads_#t~ret10; [L1025-L1029] assume !(0 != activate_threads_~tmp~1); [L1031] havoc is_transmit1_triggered_#res; [L1031] havoc is_transmit1_triggered_~__retres1~1; [L408] havoc is_transmit1_triggered_~__retres1~1; [L411-L420] assume !(1 == ~t1_pc~0); [L421] is_transmit1_triggered_~__retres1~1 := 0; [L423] is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; [L1031] activate_threads_#t~ret11 := is_transmit1_triggered_#res; [L1031] activate_threads_~tmp___0~0 := activate_threads_#t~ret11; [L1031] havoc activate_threads_#t~ret11; [L1033-L1037] assume !(0 != activate_threads_~tmp___0~0); [L1039] havoc is_transmit2_triggered_#res; [L1039] havoc is_transmit2_triggered_~__retres1~2; [L427] havoc is_transmit2_triggered_~__retres1~2; [L430-L439] assume !(1 == ~t2_pc~0); [L440] is_transmit2_triggered_~__retres1~2 := 0; [L442] is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; [L1039] activate_threads_#t~ret12 := is_transmit2_triggered_#res; [L1039] activate_threads_~tmp___1~0 := activate_threads_#t~ret12; [L1039] havoc activate_threads_#t~ret12; [L1041-L1045] assume !(0 != activate_threads_~tmp___1~0); [L1047] havoc is_transmit3_triggered_#res; [L1047] havoc is_transmit3_triggered_~__retres1~3; [L446] havoc is_transmit3_triggered_~__retres1~3; [L449-L458] assume !(1 == ~t3_pc~0); [L459] is_transmit3_triggered_~__retres1~3 := 0; [L461] is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; [L1047] activate_threads_#t~ret13 := is_transmit3_triggered_#res; [L1047] activate_threads_~tmp___2~0 := activate_threads_#t~ret13; [L1047] havoc activate_threads_#t~ret13; [L1049-L1053] assume !(0 != activate_threads_~tmp___2~0); [L1055] havoc is_transmit4_triggered_#res; [L1055] havoc is_transmit4_triggered_~__retres1~4; [L465] havoc is_transmit4_triggered_~__retres1~4; [L468-L477] assume !(1 == ~t4_pc~0); [L478] is_transmit4_triggered_~__retres1~4 := 0; [L480] is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; [L1055] activate_threads_#t~ret14 := is_transmit4_triggered_#res; [L1055] activate_threads_~tmp___3~0 := activate_threads_#t~ret14; [L1055] havoc activate_threads_#t~ret14; [L1057-L1061] assume !(0 != activate_threads_~tmp___3~0); [L1063] havoc is_transmit5_triggered_#res; [L1063] havoc is_transmit5_triggered_~__retres1~5; [L484] havoc is_transmit5_triggered_~__retres1~5; [L487-L496] assume !(1 == ~t5_pc~0); [L497] is_transmit5_triggered_~__retres1~5 := 0; [L499] is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; [L1063] activate_threads_#t~ret15 := is_transmit5_triggered_#res; [L1063] activate_threads_~tmp___4~0 := activate_threads_#t~ret15; [L1063] havoc activate_threads_#t~ret15; [L1065-L1069] assume !(0 != activate_threads_~tmp___4~0); [L1071] havoc is_transmit6_triggered_#res; [L1071] havoc is_transmit6_triggered_~__retres1~6; [L503] havoc is_transmit6_triggered_~__retres1~6; [L506-L515] assume !(1 == ~t6_pc~0); [L516] is_transmit6_triggered_~__retres1~6 := 0; [L518] is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; [L1071] activate_threads_#t~ret16 := is_transmit6_triggered_#res; [L1071] activate_threads_~tmp___5~0 := activate_threads_#t~ret16; [L1071] havoc activate_threads_#t~ret16; [L1073-L1077] assume !(0 != activate_threads_~tmp___5~0); [L1079] havoc is_transmit7_triggered_#res; [L1079] havoc is_transmit7_triggered_~__retres1~7; [L522] havoc is_transmit7_triggered_~__retres1~7; [L525-L534] assume !(1 == ~t7_pc~0); [L535] is_transmit7_triggered_~__retres1~7 := 0; [L537] is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; [L1079] activate_threads_#t~ret17 := is_transmit7_triggered_#res; [L1079] activate_threads_~tmp___6~0 := activate_threads_#t~ret17; [L1079] havoc activate_threads_#t~ret17; [L1081-L1085] assume !(0 != activate_threads_~tmp___6~0); [L1087] havoc is_transmit8_triggered_#res; [L1087] havoc is_transmit8_triggered_~__retres1~8; [L541] havoc is_transmit8_triggered_~__retres1~8; [L544-L553] assume !(1 == ~t8_pc~0); [L554] is_transmit8_triggered_~__retres1~8 := 0; [L556] is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; [L1087] activate_threads_#t~ret18 := is_transmit8_triggered_#res; [L1087] activate_threads_~tmp___7~0 := activate_threads_#t~ret18; [L1087] havoc activate_threads_#t~ret18; [L1089-L1093] assume !(0 != activate_threads_~tmp___7~0); [L921-L925] assume !(1 == ~M_E~0); [L926-L930] assume !(1 == ~T1_E~0); [L931-L935] assume !(1 == ~T2_E~0); [L936-L940] assume !(1 == ~T3_E~0); [L941-L945] assume !(1 == ~T4_E~0); [L946-L950] assume !(1 == ~T5_E~0); [L951-L955] assume !(1 == ~T6_E~0); [L956-L960] assume !(1 == ~T7_E~0); [L961-L965] assume !(1 == ~T8_E~0); [L966-L970] assume !(1 == ~E_1~0); [L971-L975] assume !(1 == ~E_2~0); [L976-L980] assume !(1 == ~E_3~0); [L981-L985] assume !(1 == ~E_4~0); [L986-L990] assume !(1 == ~E_5~0); [L991-L995] assume !(1 == ~E_6~0); [L996-L1000] assume !(1 == ~E_7~0); [L1001-L1005] assume !(1 == ~E_8~0); [L1262-L1299] assume !false; [L1265] start_simulation_~kernel_st~0 := 1; [L1266] havoc eval_#t~ret0, eval_#t~nondet1, eval_~tmp_ndt_1~0, eval_#t~nondet2, eval_~tmp_ndt_2~0, eval_#t~nondet3, eval_~tmp_ndt_3~0, eval_#t~nondet4, eval_~tmp_ndt_4~0, eval_#t~nondet5, eval_~tmp_ndt_5~0, eval_#t~nondet6, eval_~tmp_ndt_6~0, eval_#t~nondet7, eval_~tmp_ndt_7~0, eval_#t~nondet8, eval_~tmp_ndt_8~0, eval_#t~nondet9, eval_~tmp_ndt_9~0, eval_~tmp~0; [L677] havoc eval_~tmp~0; [L15] ~m_pc~0 := 0; [L16] ~t1_pc~0 := 0; [L17] ~t2_pc~0 := 0; [L18] ~t3_pc~0 := 0; [L19] ~t4_pc~0 := 0; [L20] ~t5_pc~0 := 0; [L21] ~t6_pc~0 := 0; [L22] ~t7_pc~0 := 0; [L23] ~t8_pc~0 := 0; [L24] ~m_st~0 := 0; [L25] ~t1_st~0 := 0; [L26] ~t2_st~0 := 0; [L27] ~t3_st~0 := 0; [L28] ~t4_st~0 := 0; [L29] ~t5_st~0 := 0; [L30] ~t6_st~0 := 0; [L31] ~t7_st~0 := 0; [L32] ~t8_st~0 := 0; [L33] ~m_i~0 := 0; [L34] ~t1_i~0 := 0; [L35] ~t2_i~0 := 0; [L36] ~t3_i~0 := 0; [L37] ~t4_i~0 := 0; [L38] ~t5_i~0 := 0; [L39] ~t6_i~0 := 0; [L40] ~t7_i~0 := 0; [L41] ~t8_i~0 := 0; [L42] ~M_E~0 := 2; [L43] ~T1_E~0 := 2; [L44] ~T2_E~0 := 2; [L45] ~T3_E~0 := 2; [L46] ~T4_E~0 := 2; [L47] ~T5_E~0 := 2; [L48] ~T6_E~0 := 2; [L49] ~T7_E~0 := 2; [L50] ~T8_E~0 := 2; [L51] ~E_1~0 := 2; [L52] ~E_2~0 := 2; [L53] ~E_3~0 := 2; [L54] ~E_4~0 := 2; [L55] ~E_5~0 := 2; [L56] ~E_6~0 := 2; [L57] ~E_7~0 := 2; [L58] ~E_8~0 := 2; [?] havoc main_#res; [?] havoc main_~__retres1~10; [L1307] havoc main_~__retres1~10; [L1215] ~m_i~0 := 1; [L1216] ~t1_i~0 := 1; [L1217] ~t2_i~0 := 1; [L1218] ~t3_i~0 := 1; [L1219] ~t4_i~0 := 1; [L1220] ~t5_i~0 := 1; [L1221] ~t6_i~0 := 1; [L1222] ~t7_i~0 := 1; [L1223] ~t8_i~0 := 1; [L1312] havoc start_simulation_#t~ret20, start_simulation_#t~ret21, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1; [L1248] havoc start_simulation_~kernel_st~0; [L1249] havoc start_simulation_~tmp~3; [L1250] havoc start_simulation_~tmp___0~1; [L1254] start_simulation_~kernel_st~0 := 0; [L571] COND TRUE 1 == ~m_i~0 [L572] ~m_st~0 := 0; [L576] COND TRUE 1 == ~t1_i~0 [L577] ~t1_st~0 := 0; [L581] COND TRUE 1 == ~t2_i~0 [L582] ~t2_st~0 := 0; [L586] COND TRUE 1 == ~t3_i~0 [L587] ~t3_st~0 := 0; [L591] COND TRUE 1 == ~t4_i~0 [L592] ~t4_st~0 := 0; [L596] COND TRUE 1 == ~t5_i~0 [L597] ~t5_st~0 := 0; [L601] COND TRUE 1 == ~t6_i~0 [L602] ~t6_st~0 := 0; [L606] COND TRUE 1 == ~t7_i~0 [L607] ~t7_st~0 := 0; [L611] COND TRUE 1 == ~t8_i~0 [L612] ~t8_st~0 := 0; [L828] COND FALSE !(0 == ~M_E~0) [L833] COND FALSE !(0 == ~T1_E~0) [L838] COND FALSE !(0 == ~T2_E~0) [L843] COND FALSE !(0 == ~T3_E~0) [L848] COND FALSE !(0 == ~T4_E~0) [L853] COND FALSE !(0 == ~T5_E~0) [L858] COND FALSE !(0 == ~T6_E~0) [L863] COND FALSE !(0 == ~T7_E~0) [L868] COND FALSE !(0 == ~T8_E~0) [L873] COND FALSE !(0 == ~E_1~0) [L878] COND FALSE !(0 == ~E_2~0) [L883] COND FALSE !(0 == ~E_3~0) [L888] COND FALSE !(0 == ~E_4~0) [L893] COND FALSE !(0 == ~E_5~0) [L898] COND FALSE !(0 == ~E_6~0) [L903] COND FALSE !(0 == ~E_7~0) [L908] COND FALSE !(0 == ~E_8~0) [L1258] havoc activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0; [L1011] havoc activate_threads_~tmp~1; [L1012] havoc activate_threads_~tmp___0~0; [L1013] havoc activate_threads_~tmp___1~0; [L1014] havoc activate_threads_~tmp___2~0; [L1015] havoc activate_threads_~tmp___3~0; [L1016] havoc activate_threads_~tmp___4~0; [L1017] havoc activate_threads_~tmp___5~0; [L1018] havoc activate_threads_~tmp___6~0; [L1019] havoc activate_threads_~tmp___7~0; [L1023] havoc is_master_triggered_#res; [L1023] havoc is_master_triggered_~__retres1~0; [L389] havoc is_master_triggered_~__retres1~0; [L392] COND FALSE !(1 == ~m_pc~0) [L402] is_master_triggered_~__retres1~0 := 0; [L404] is_master_triggered_#res := is_master_triggered_~__retres1~0; [L1023] activate_threads_#t~ret10 := is_master_triggered_#res; [L1023] activate_threads_~tmp~1 := activate_threads_#t~ret10; [L1023] havoc activate_threads_#t~ret10; [L1025-L1029] COND FALSE !(0 != activate_threads_~tmp~1) [L1031] havoc is_transmit1_triggered_#res; [L1031] havoc is_transmit1_triggered_~__retres1~1; [L408] havoc is_transmit1_triggered_~__retres1~1; [L411] COND FALSE !(1 == ~t1_pc~0) [L421] is_transmit1_triggered_~__retres1~1 := 0; [L423] is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; [L1031] activate_threads_#t~ret11 := is_transmit1_triggered_#res; [L1031] activate_threads_~tmp___0~0 := activate_threads_#t~ret11; [L1031] havoc activate_threads_#t~ret11; [L1033-L1037] COND FALSE !(0 != activate_threads_~tmp___0~0) [L1039] havoc is_transmit2_triggered_#res; [L1039] havoc is_transmit2_triggered_~__retres1~2; [L427] havoc is_transmit2_triggered_~__retres1~2; [L430] COND FALSE !(1 == ~t2_pc~0) [L440] is_transmit2_triggered_~__retres1~2 := 0; [L442] is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; [L1039] activate_threads_#t~ret12 := is_transmit2_triggered_#res; [L1039] activate_threads_~tmp___1~0 := activate_threads_#t~ret12; [L1039] havoc activate_threads_#t~ret12; [L1041-L1045] COND FALSE !(0 != activate_threads_~tmp___1~0) [L1047] havoc is_transmit3_triggered_#res; [L1047] havoc is_transmit3_triggered_~__retres1~3; [L446] havoc is_transmit3_triggered_~__retres1~3; [L449] COND FALSE !(1 == ~t3_pc~0) [L459] is_transmit3_triggered_~__retres1~3 := 0; [L461] is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; [L1047] activate_threads_#t~ret13 := is_transmit3_triggered_#res; [L1047] activate_threads_~tmp___2~0 := activate_threads_#t~ret13; [L1047] havoc activate_threads_#t~ret13; [L1049-L1053] COND FALSE !(0 != activate_threads_~tmp___2~0) [L1055] havoc is_transmit4_triggered_#res; [L1055] havoc is_transmit4_triggered_~__retres1~4; [L465] havoc is_transmit4_triggered_~__retres1~4; [L468] COND FALSE !(1 == ~t4_pc~0) [L478] is_transmit4_triggered_~__retres1~4 := 0; [L480] is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; [L1055] activate_threads_#t~ret14 := is_transmit4_triggered_#res; [L1055] activate_threads_~tmp___3~0 := activate_threads_#t~ret14; [L1055] havoc activate_threads_#t~ret14; [L1057-L1061] COND FALSE !(0 != activate_threads_~tmp___3~0) [L1063] havoc is_transmit5_triggered_#res; [L1063] havoc is_transmit5_triggered_~__retres1~5; [L484] havoc is_transmit5_triggered_~__retres1~5; [L487] COND FALSE !(1 == ~t5_pc~0) [L497] is_transmit5_triggered_~__retres1~5 := 0; [L499] is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; [L1063] activate_threads_#t~ret15 := is_transmit5_triggered_#res; [L1063] activate_threads_~tmp___4~0 := activate_threads_#t~ret15; [L1063] havoc activate_threads_#t~ret15; [L1065-L1069] COND FALSE !(0 != activate_threads_~tmp___4~0) [L1071] havoc is_transmit6_triggered_#res; [L1071] havoc is_transmit6_triggered_~__retres1~6; [L503] havoc is_transmit6_triggered_~__retres1~6; [L506] COND FALSE !(1 == ~t6_pc~0) [L516] is_transmit6_triggered_~__retres1~6 := 0; [L518] is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; [L1071] activate_threads_#t~ret16 := is_transmit6_triggered_#res; [L1071] activate_threads_~tmp___5~0 := activate_threads_#t~ret16; [L1071] havoc activate_threads_#t~ret16; [L1073-L1077] COND FALSE !(0 != activate_threads_~tmp___5~0) [L1079] havoc is_transmit7_triggered_#res; [L1079] havoc is_transmit7_triggered_~__retres1~7; [L522] havoc is_transmit7_triggered_~__retres1~7; [L525] COND FALSE !(1 == ~t7_pc~0) [L535] is_transmit7_triggered_~__retres1~7 := 0; [L537] is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; [L1079] activate_threads_#t~ret17 := is_transmit7_triggered_#res; [L1079] activate_threads_~tmp___6~0 := activate_threads_#t~ret17; [L1079] havoc activate_threads_#t~ret17; [L1081-L1085] COND FALSE !(0 != activate_threads_~tmp___6~0) [L1087] havoc is_transmit8_triggered_#res; [L1087] havoc is_transmit8_triggered_~__retres1~8; [L541] havoc is_transmit8_triggered_~__retres1~8; [L544] COND FALSE !(1 == ~t8_pc~0) [L554] is_transmit8_triggered_~__retres1~8 := 0; [L556] is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; [L1087] activate_threads_#t~ret18 := is_transmit8_triggered_#res; [L1087] activate_threads_~tmp___7~0 := activate_threads_#t~ret18; [L1087] havoc activate_threads_#t~ret18; [L1089-L1093] COND FALSE !(0 != activate_threads_~tmp___7~0) [L921] COND FALSE !(1 == ~M_E~0) [L926] COND FALSE !(1 == ~T1_E~0) [L931] COND FALSE !(1 == ~T2_E~0) [L936] COND FALSE !(1 == ~T3_E~0) [L941] COND FALSE !(1 == ~T4_E~0) [L946] COND FALSE !(1 == ~T5_E~0) [L951] COND FALSE !(1 == ~T6_E~0) [L956] COND FALSE !(1 == ~T7_E~0) [L961] COND FALSE !(1 == ~T8_E~0) [L966] COND FALSE !(1 == ~E_1~0) [L971] COND FALSE !(1 == ~E_2~0) [L976] COND FALSE !(1 == ~E_3~0) [L981] COND FALSE !(1 == ~E_4~0) [L986] COND FALSE !(1 == ~E_5~0) [L991] COND FALSE !(1 == ~E_6~0) [L996] COND FALSE !(1 == ~E_7~0) [L1001] COND FALSE !(1 == ~E_8~0) [L1262-L1299] COND FALSE !(false) [L1265] start_simulation_~kernel_st~0 := 1; [L1266] havoc eval_#t~ret0, eval_#t~nondet1, eval_~tmp_ndt_1~0, eval_#t~nondet2, eval_~tmp_ndt_2~0, eval_#t~nondet3, eval_~tmp_ndt_3~0, eval_#t~nondet4, eval_~tmp_ndt_4~0, eval_#t~nondet5, eval_~tmp_ndt_5~0, eval_#t~nondet6, eval_~tmp_ndt_6~0, eval_#t~nondet7, eval_~tmp_ndt_7~0, eval_#t~nondet8, eval_~tmp_ndt_8~0, eval_#t~nondet9, eval_~tmp_ndt_9~0, eval_~tmp~0; [L677] havoc eval_~tmp~0; ----- ----- class de.uni_freiburg.informatik.ultimate.boogie.procedureinliner.backtranslation.InlinerBacktranslator [L15] ~m_pc~0 := 0; [L16] ~t1_pc~0 := 0; [L17] ~t2_pc~0 := 0; [L18] ~t3_pc~0 := 0; [L19] ~t4_pc~0 := 0; [L20] ~t5_pc~0 := 0; [L21] ~t6_pc~0 := 0; [L22] ~t7_pc~0 := 0; [L23] ~t8_pc~0 := 0; [L24] ~m_st~0 := 0; [L25] ~t1_st~0 := 0; [L26] ~t2_st~0 := 0; [L27] ~t3_st~0 := 0; [L28] ~t4_st~0 := 0; [L29] ~t5_st~0 := 0; [L30] ~t6_st~0 := 0; [L31] ~t7_st~0 := 0; [L32] ~t8_st~0 := 0; [L33] ~m_i~0 := 0; [L34] ~t1_i~0 := 0; [L35] ~t2_i~0 := 0; [L36] ~t3_i~0 := 0; [L37] ~t4_i~0 := 0; [L38] ~t5_i~0 := 0; [L39] ~t6_i~0 := 0; [L40] ~t7_i~0 := 0; [L41] ~t8_i~0 := 0; [L42] ~M_E~0 := 2; [L43] ~T1_E~0 := 2; [L44] ~T2_E~0 := 2; [L45] ~T3_E~0 := 2; [L46] ~T4_E~0 := 2; [L47] ~T5_E~0 := 2; [L48] ~T6_E~0 := 2; [L49] ~T7_E~0 := 2; [L50] ~T8_E~0 := 2; [L51] ~E_1~0 := 2; [L52] ~E_2~0 := 2; [L53] ~E_3~0 := 2; [L54] ~E_4~0 := 2; [L55] ~E_5~0 := 2; [L56] ~E_6~0 := 2; [L57] ~E_7~0 := 2; [L58] ~E_8~0 := 2; [?] havoc main_#res; [?] havoc main_~__retres1~10; [L1307] havoc main_~__retres1~10; [L1215] ~m_i~0 := 1; [L1216] ~t1_i~0 := 1; [L1217] ~t2_i~0 := 1; [L1218] ~t3_i~0 := 1; [L1219] ~t4_i~0 := 1; [L1220] ~t5_i~0 := 1; [L1221] ~t6_i~0 := 1; [L1222] ~t7_i~0 := 1; [L1223] ~t8_i~0 := 1; [L1312] havoc start_simulation_#t~ret20, start_simulation_#t~ret21, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1; [L1248] havoc start_simulation_~kernel_st~0; [L1249] havoc start_simulation_~tmp~3; [L1250] havoc start_simulation_~tmp___0~1; [L1254] start_simulation_~kernel_st~0 := 0; [L571] COND TRUE 1 == ~m_i~0 [L572] ~m_st~0 := 0; [L576] COND TRUE 1 == ~t1_i~0 [L577] ~t1_st~0 := 0; [L581] COND TRUE 1 == ~t2_i~0 [L582] ~t2_st~0 := 0; [L586] COND TRUE 1 == ~t3_i~0 [L587] ~t3_st~0 := 0; [L591] COND TRUE 1 == ~t4_i~0 [L592] ~t4_st~0 := 0; [L596] COND TRUE 1 == ~t5_i~0 [L597] ~t5_st~0 := 0; [L601] COND TRUE 1 == ~t6_i~0 [L602] ~t6_st~0 := 0; [L606] COND TRUE 1 == ~t7_i~0 [L607] ~t7_st~0 := 0; [L611] COND TRUE 1 == ~t8_i~0 [L612] ~t8_st~0 := 0; [L828] COND FALSE !(0 == ~M_E~0) [L833] COND FALSE !(0 == ~T1_E~0) [L838] COND FALSE !(0 == ~T2_E~0) [L843] COND FALSE !(0 == ~T3_E~0) [L848] COND FALSE !(0 == ~T4_E~0) [L853] COND FALSE !(0 == ~T5_E~0) [L858] COND FALSE !(0 == ~T6_E~0) [L863] COND FALSE !(0 == ~T7_E~0) [L868] COND FALSE !(0 == ~T8_E~0) [L873] COND FALSE !(0 == ~E_1~0) [L878] COND FALSE !(0 == ~E_2~0) [L883] COND FALSE !(0 == ~E_3~0) [L888] COND FALSE !(0 == ~E_4~0) [L893] COND FALSE !(0 == ~E_5~0) [L898] COND FALSE !(0 == ~E_6~0) [L903] COND FALSE !(0 == ~E_7~0) [L908] COND FALSE !(0 == ~E_8~0) [L1258] havoc activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0; [L1011] havoc activate_threads_~tmp~1; [L1012] havoc activate_threads_~tmp___0~0; [L1013] havoc activate_threads_~tmp___1~0; [L1014] havoc activate_threads_~tmp___2~0; [L1015] havoc activate_threads_~tmp___3~0; [L1016] havoc activate_threads_~tmp___4~0; [L1017] havoc activate_threads_~tmp___5~0; [L1018] havoc activate_threads_~tmp___6~0; [L1019] havoc activate_threads_~tmp___7~0; [L1023] havoc is_master_triggered_#res; [L1023] havoc is_master_triggered_~__retres1~0; [L389] havoc is_master_triggered_~__retres1~0; [L392] COND FALSE !(1 == ~m_pc~0) [L402] is_master_triggered_~__retres1~0 := 0; [L404] is_master_triggered_#res := is_master_triggered_~__retres1~0; [L1023] activate_threads_#t~ret10 := is_master_triggered_#res; [L1023] activate_threads_~tmp~1 := activate_threads_#t~ret10; [L1023] havoc activate_threads_#t~ret10; [L1025-L1029] COND FALSE !(0 != activate_threads_~tmp~1) [L1031] havoc is_transmit1_triggered_#res; [L1031] havoc is_transmit1_triggered_~__retres1~1; [L408] havoc is_transmit1_triggered_~__retres1~1; [L411] COND FALSE !(1 == ~t1_pc~0) [L421] is_transmit1_triggered_~__retres1~1 := 0; [L423] is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; [L1031] activate_threads_#t~ret11 := is_transmit1_triggered_#res; [L1031] activate_threads_~tmp___0~0 := activate_threads_#t~ret11; [L1031] havoc activate_threads_#t~ret11; [L1033-L1037] COND FALSE !(0 != activate_threads_~tmp___0~0) [L1039] havoc is_transmit2_triggered_#res; [L1039] havoc is_transmit2_triggered_~__retres1~2; [L427] havoc is_transmit2_triggered_~__retres1~2; [L430] COND FALSE !(1 == ~t2_pc~0) [L440] is_transmit2_triggered_~__retres1~2 := 0; [L442] is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; [L1039] activate_threads_#t~ret12 := is_transmit2_triggered_#res; [L1039] activate_threads_~tmp___1~0 := activate_threads_#t~ret12; [L1039] havoc activate_threads_#t~ret12; [L1041-L1045] COND FALSE !(0 != activate_threads_~tmp___1~0) [L1047] havoc is_transmit3_triggered_#res; [L1047] havoc is_transmit3_triggered_~__retres1~3; [L446] havoc is_transmit3_triggered_~__retres1~3; [L449] COND FALSE !(1 == ~t3_pc~0) [L459] is_transmit3_triggered_~__retres1~3 := 0; [L461] is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; [L1047] activate_threads_#t~ret13 := is_transmit3_triggered_#res; [L1047] activate_threads_~tmp___2~0 := activate_threads_#t~ret13; [L1047] havoc activate_threads_#t~ret13; [L1049-L1053] COND FALSE !(0 != activate_threads_~tmp___2~0) [L1055] havoc is_transmit4_triggered_#res; [L1055] havoc is_transmit4_triggered_~__retres1~4; [L465] havoc is_transmit4_triggered_~__retres1~4; [L468] COND FALSE !(1 == ~t4_pc~0) [L478] is_transmit4_triggered_~__retres1~4 := 0; [L480] is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; [L1055] activate_threads_#t~ret14 := is_transmit4_triggered_#res; [L1055] activate_threads_~tmp___3~0 := activate_threads_#t~ret14; [L1055] havoc activate_threads_#t~ret14; [L1057-L1061] COND FALSE !(0 != activate_threads_~tmp___3~0) [L1063] havoc is_transmit5_triggered_#res; [L1063] havoc is_transmit5_triggered_~__retres1~5; [L484] havoc is_transmit5_triggered_~__retres1~5; [L487] COND FALSE !(1 == ~t5_pc~0) [L497] is_transmit5_triggered_~__retres1~5 := 0; [L499] is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; [L1063] activate_threads_#t~ret15 := is_transmit5_triggered_#res; [L1063] activate_threads_~tmp___4~0 := activate_threads_#t~ret15; [L1063] havoc activate_threads_#t~ret15; [L1065-L1069] COND FALSE !(0 != activate_threads_~tmp___4~0) [L1071] havoc is_transmit6_triggered_#res; [L1071] havoc is_transmit6_triggered_~__retres1~6; [L503] havoc is_transmit6_triggered_~__retres1~6; [L506] COND FALSE !(1 == ~t6_pc~0) [L516] is_transmit6_triggered_~__retres1~6 := 0; [L518] is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; [L1071] activate_threads_#t~ret16 := is_transmit6_triggered_#res; [L1071] activate_threads_~tmp___5~0 := activate_threads_#t~ret16; [L1071] havoc activate_threads_#t~ret16; [L1073-L1077] COND FALSE !(0 != activate_threads_~tmp___5~0) [L1079] havoc is_transmit7_triggered_#res; [L1079] havoc is_transmit7_triggered_~__retres1~7; [L522] havoc is_transmit7_triggered_~__retres1~7; [L525] COND FALSE !(1 == ~t7_pc~0) [L535] is_transmit7_triggered_~__retres1~7 := 0; [L537] is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; [L1079] activate_threads_#t~ret17 := is_transmit7_triggered_#res; [L1079] activate_threads_~tmp___6~0 := activate_threads_#t~ret17; [L1079] havoc activate_threads_#t~ret17; [L1081-L1085] COND FALSE !(0 != activate_threads_~tmp___6~0) [L1087] havoc is_transmit8_triggered_#res; [L1087] havoc is_transmit8_triggered_~__retres1~8; [L541] havoc is_transmit8_triggered_~__retres1~8; [L544] COND FALSE !(1 == ~t8_pc~0) [L554] is_transmit8_triggered_~__retres1~8 := 0; [L556] is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; [L1087] activate_threads_#t~ret18 := is_transmit8_triggered_#res; [L1087] activate_threads_~tmp___7~0 := activate_threads_#t~ret18; [L1087] havoc activate_threads_#t~ret18; [L1089-L1093] COND FALSE !(0 != activate_threads_~tmp___7~0) [L921] COND FALSE !(1 == ~M_E~0) [L926] COND FALSE !(1 == ~T1_E~0) [L931] COND FALSE !(1 == ~T2_E~0) [L936] COND FALSE !(1 == ~T3_E~0) [L941] COND FALSE !(1 == ~T4_E~0) [L946] COND FALSE !(1 == ~T5_E~0) [L951] COND FALSE !(1 == ~T6_E~0) [L956] COND FALSE !(1 == ~T7_E~0) [L961] COND FALSE !(1 == ~T8_E~0) [L966] COND FALSE !(1 == ~E_1~0) [L971] COND FALSE !(1 == ~E_2~0) [L976] COND FALSE !(1 == ~E_3~0) [L981] COND FALSE !(1 == ~E_4~0) [L986] COND FALSE !(1 == ~E_5~0) [L991] COND FALSE !(1 == ~E_6~0) [L996] COND FALSE !(1 == ~E_7~0) [L1001] COND FALSE !(1 == ~E_8~0) [L1262-L1299] COND FALSE !(false) [L1265] start_simulation_~kernel_st~0 := 1; [L1266] havoc eval_#t~ret0, eval_#t~nondet1, eval_~tmp_ndt_1~0, eval_#t~nondet2, eval_~tmp_ndt_2~0, eval_#t~nondet3, eval_~tmp_ndt_3~0, eval_#t~nondet4, eval_~tmp_ndt_4~0, eval_#t~nondet5, eval_~tmp_ndt_5~0, eval_#t~nondet6, eval_~tmp_ndt_6~0, eval_#t~nondet7, eval_~tmp_ndt_7~0, eval_#t~nondet8, eval_~tmp_ndt_8~0, eval_#t~nondet9, eval_~tmp_ndt_9~0, eval_~tmp~0; [L677] havoc eval_~tmp~0; [L15] ~m_pc~0 := 0; [L16] ~t1_pc~0 := 0; [L17] ~t2_pc~0 := 0; [L18] ~t3_pc~0 := 0; [L19] ~t4_pc~0 := 0; [L20] ~t5_pc~0 := 0; [L21] ~t6_pc~0 := 0; [L22] ~t7_pc~0 := 0; [L23] ~t8_pc~0 := 0; [L24] ~m_st~0 := 0; [L25] ~t1_st~0 := 0; [L26] ~t2_st~0 := 0; [L27] ~t3_st~0 := 0; [L28] ~t4_st~0 := 0; [L29] ~t5_st~0 := 0; [L30] ~t6_st~0 := 0; [L31] ~t7_st~0 := 0; [L32] ~t8_st~0 := 0; [L33] ~m_i~0 := 0; [L34] ~t1_i~0 := 0; [L35] ~t2_i~0 := 0; [L36] ~t3_i~0 := 0; [L37] ~t4_i~0 := 0; [L38] ~t5_i~0 := 0; [L39] ~t6_i~0 := 0; [L40] ~t7_i~0 := 0; [L41] ~t8_i~0 := 0; [L42] ~M_E~0 := 2; [L43] ~T1_E~0 := 2; [L44] ~T2_E~0 := 2; [L45] ~T3_E~0 := 2; [L46] ~T4_E~0 := 2; [L47] ~T5_E~0 := 2; [L48] ~T6_E~0 := 2; [L49] ~T7_E~0 := 2; [L50] ~T8_E~0 := 2; [L51] ~E_1~0 := 2; [L52] ~E_2~0 := 2; [L53] ~E_3~0 := 2; [L54] ~E_4~0 := 2; [L55] ~E_5~0 := 2; [L56] ~E_6~0 := 2; [L57] ~E_7~0 := 2; [L58] ~E_8~0 := 2; [L1307] havoc ~__retres1~10; [L1215] ~m_i~0 := 1; [L1216] ~t1_i~0 := 1; [L1217] ~t2_i~0 := 1; [L1218] ~t3_i~0 := 1; [L1219] ~t4_i~0 := 1; [L1220] ~t5_i~0 := 1; [L1221] ~t6_i~0 := 1; [L1222] ~t7_i~0 := 1; [L1223] ~t8_i~0 := 1; [L1248] havoc ~kernel_st~0; [L1249] havoc ~tmp~3; [L1250] havoc ~tmp___0~1; [L1254] ~kernel_st~0 := 0; [L571] COND TRUE 1 == ~m_i~0 [L572] ~m_st~0 := 0; [L576] COND TRUE 1 == ~t1_i~0 [L577] ~t1_st~0 := 0; [L581] COND TRUE 1 == ~t2_i~0 [L582] ~t2_st~0 := 0; [L586] COND TRUE 1 == ~t3_i~0 [L587] ~t3_st~0 := 0; [L591] COND TRUE 1 == ~t4_i~0 [L592] ~t4_st~0 := 0; [L596] COND TRUE 1 == ~t5_i~0 [L597] ~t5_st~0 := 0; [L601] COND TRUE 1 == ~t6_i~0 [L602] ~t6_st~0 := 0; [L606] COND TRUE 1 == ~t7_i~0 [L607] ~t7_st~0 := 0; [L611] COND TRUE 1 == ~t8_i~0 [L612] ~t8_st~0 := 0; [L828] COND FALSE !(0 == ~M_E~0) [L833] COND FALSE !(0 == ~T1_E~0) [L838] COND FALSE !(0 == ~T2_E~0) [L843] COND FALSE !(0 == ~T3_E~0) [L848] COND FALSE !(0 == ~T4_E~0) [L853] COND FALSE !(0 == ~T5_E~0) [L858] COND FALSE !(0 == ~T6_E~0) [L863] COND FALSE !(0 == ~T7_E~0) [L868] COND FALSE !(0 == ~T8_E~0) [L873] COND FALSE !(0 == ~E_1~0) [L878] COND FALSE !(0 == ~E_2~0) [L883] COND FALSE !(0 == ~E_3~0) [L888] COND FALSE !(0 == ~E_4~0) [L893] COND FALSE !(0 == ~E_5~0) [L898] COND FALSE !(0 == ~E_6~0) [L903] COND FALSE !(0 == ~E_7~0) [L908] COND FALSE !(0 == ~E_8~0) [L1011] havoc ~tmp~1; [L1012] havoc ~tmp___0~0; [L1013] havoc ~tmp___1~0; [L1014] havoc ~tmp___2~0; [L1015] havoc ~tmp___3~0; [L1016] havoc ~tmp___4~0; [L1017] havoc ~tmp___5~0; [L1018] havoc ~tmp___6~0; [L1019] havoc ~tmp___7~0; [L389] havoc ~__retres1~0; [L392] COND FALSE !(1 == ~m_pc~0) [L402] ~__retres1~0 := 0; [L404] #res := ~__retres1~0; [L1023] ~tmp~1 := #t~ret10; [L1023] havoc #t~ret10; [L1025-L1029] COND FALSE !(0 != ~tmp~1) [L408] havoc ~__retres1~1; [L411] COND FALSE !(1 == ~t1_pc~0) [L421] ~__retres1~1 := 0; [L423] #res := ~__retres1~1; [L1031] ~tmp___0~0 := #t~ret11; [L1031] havoc #t~ret11; [L1033-L1037] COND FALSE !(0 != ~tmp___0~0) [L427] havoc ~__retres1~2; [L430] COND FALSE !(1 == ~t2_pc~0) [L440] ~__retres1~2 := 0; [L442] #res := ~__retres1~2; [L1039] ~tmp___1~0 := #t~ret12; [L1039] havoc #t~ret12; [L1041-L1045] COND FALSE !(0 != ~tmp___1~0) [L446] havoc ~__retres1~3; [L449] COND FALSE !(1 == ~t3_pc~0) [L459] ~__retres1~3 := 0; [L461] #res := ~__retres1~3; [L1047] ~tmp___2~0 := #t~ret13; [L1047] havoc #t~ret13; [L1049-L1053] COND FALSE !(0 != ~tmp___2~0) [L465] havoc ~__retres1~4; [L468] COND FALSE !(1 == ~t4_pc~0) [L478] ~__retres1~4 := 0; [L480] #res := ~__retres1~4; [L1055] ~tmp___3~0 := #t~ret14; [L1055] havoc #t~ret14; [L1057-L1061] COND FALSE !(0 != ~tmp___3~0) [L484] havoc ~__retres1~5; [L487] COND FALSE !(1 == ~t5_pc~0) [L497] ~__retres1~5 := 0; [L499] #res := ~__retres1~5; [L1063] ~tmp___4~0 := #t~ret15; [L1063] havoc #t~ret15; [L1065-L1069] COND FALSE !(0 != ~tmp___4~0) [L503] havoc ~__retres1~6; [L506] COND FALSE !(1 == ~t6_pc~0) [L516] ~__retres1~6 := 0; [L518] #res := ~__retres1~6; [L1071] ~tmp___5~0 := #t~ret16; [L1071] havoc #t~ret16; [L1073-L1077] COND FALSE !(0 != ~tmp___5~0) [L522] havoc ~__retres1~7; [L525] COND FALSE !(1 == ~t7_pc~0) [L535] ~__retres1~7 := 0; [L537] #res := ~__retres1~7; [L1079] ~tmp___6~0 := #t~ret17; [L1079] havoc #t~ret17; [L1081-L1085] COND FALSE !(0 != ~tmp___6~0) [L541] havoc ~__retres1~8; [L544] COND FALSE !(1 == ~t8_pc~0) [L554] ~__retres1~8 := 0; [L556] #res := ~__retres1~8; [L1087] ~tmp___7~0 := #t~ret18; [L1087] havoc #t~ret18; [L1089-L1093] COND FALSE !(0 != ~tmp___7~0) [L921] COND FALSE !(1 == ~M_E~0) [L926] COND FALSE !(1 == ~T1_E~0) [L931] COND FALSE !(1 == ~T2_E~0) [L936] COND FALSE !(1 == ~T3_E~0) [L941] COND FALSE !(1 == ~T4_E~0) [L946] COND FALSE !(1 == ~T5_E~0) [L951] COND FALSE !(1 == ~T6_E~0) [L956] COND FALSE !(1 == ~T7_E~0) [L961] COND FALSE !(1 == ~T8_E~0) [L966] COND FALSE !(1 == ~E_1~0) [L971] COND FALSE !(1 == ~E_2~0) [L976] COND FALSE !(1 == ~E_3~0) [L981] COND FALSE !(1 == ~E_4~0) [L986] COND FALSE !(1 == ~E_5~0) [L991] COND FALSE !(1 == ~E_6~0) [L996] COND FALSE !(1 == ~E_7~0) [L1001] COND FALSE !(1 == ~E_8~0) [L1262-L1299] COND FALSE !(false) [L1265] ~kernel_st~0 := 1; [L677] havoc ~tmp~0; ----- ----- class de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.CACSL2BoogieBacktranslator [L15] ~m_pc~0 := 0; [L16] ~t1_pc~0 := 0; [L17] ~t2_pc~0 := 0; [L18] ~t3_pc~0 := 0; [L19] ~t4_pc~0 := 0; [L20] ~t5_pc~0 := 0; [L21] ~t6_pc~0 := 0; [L22] ~t7_pc~0 := 0; [L23] ~t8_pc~0 := 0; [L24] ~m_st~0 := 0; [L25] ~t1_st~0 := 0; [L26] ~t2_st~0 := 0; [L27] ~t3_st~0 := 0; [L28] ~t4_st~0 := 0; [L29] ~t5_st~0 := 0; [L30] ~t6_st~0 := 0; [L31] ~t7_st~0 := 0; [L32] ~t8_st~0 := 0; [L33] ~m_i~0 := 0; [L34] ~t1_i~0 := 0; [L35] ~t2_i~0 := 0; [L36] ~t3_i~0 := 0; [L37] ~t4_i~0 := 0; [L38] ~t5_i~0 := 0; [L39] ~t6_i~0 := 0; [L40] ~t7_i~0 := 0; [L41] ~t8_i~0 := 0; [L42] ~M_E~0 := 2; [L43] ~T1_E~0 := 2; [L44] ~T2_E~0 := 2; [L45] ~T3_E~0 := 2; [L46] ~T4_E~0 := 2; [L47] ~T5_E~0 := 2; [L48] ~T6_E~0 := 2; [L49] ~T7_E~0 := 2; [L50] ~T8_E~0 := 2; [L51] ~E_1~0 := 2; [L52] ~E_2~0 := 2; [L53] ~E_3~0 := 2; [L54] ~E_4~0 := 2; [L55] ~E_5~0 := 2; [L56] ~E_6~0 := 2; [L57] ~E_7~0 := 2; [L58] ~E_8~0 := 2; [L1307] havoc ~__retres1~10; [L1215] ~m_i~0 := 1; [L1216] ~t1_i~0 := 1; [L1217] ~t2_i~0 := 1; [L1218] ~t3_i~0 := 1; [L1219] ~t4_i~0 := 1; [L1220] ~t5_i~0 := 1; [L1221] ~t6_i~0 := 1; [L1222] ~t7_i~0 := 1; [L1223] ~t8_i~0 := 1; [L1248] havoc ~kernel_st~0; [L1249] havoc ~tmp~3; [L1250] havoc ~tmp___0~1; [L1254] ~kernel_st~0 := 0; [L571] COND TRUE 1 == ~m_i~0 [L572] ~m_st~0 := 0; [L576] COND TRUE 1 == ~t1_i~0 [L577] ~t1_st~0 := 0; [L581] COND TRUE 1 == ~t2_i~0 [L582] ~t2_st~0 := 0; [L586] COND TRUE 1 == ~t3_i~0 [L587] ~t3_st~0 := 0; [L591] COND TRUE 1 == ~t4_i~0 [L592] ~t4_st~0 := 0; [L596] COND TRUE 1 == ~t5_i~0 [L597] ~t5_st~0 := 0; [L601] COND TRUE 1 == ~t6_i~0 [L602] ~t6_st~0 := 0; [L606] COND TRUE 1 == ~t7_i~0 [L607] ~t7_st~0 := 0; [L611] COND TRUE 1 == ~t8_i~0 [L612] ~t8_st~0 := 0; [L828] COND FALSE !(0 == ~M_E~0) [L833] COND FALSE !(0 == ~T1_E~0) [L838] COND FALSE !(0 == ~T2_E~0) [L843] COND FALSE !(0 == ~T3_E~0) [L848] COND FALSE !(0 == ~T4_E~0) [L853] COND FALSE !(0 == ~T5_E~0) [L858] COND FALSE !(0 == ~T6_E~0) [L863] COND FALSE !(0 == ~T7_E~0) [L868] COND FALSE !(0 == ~T8_E~0) [L873] COND FALSE !(0 == ~E_1~0) [L878] COND FALSE !(0 == ~E_2~0) [L883] COND FALSE !(0 == ~E_3~0) [L888] COND FALSE !(0 == ~E_4~0) [L893] COND FALSE !(0 == ~E_5~0) [L898] COND FALSE !(0 == ~E_6~0) [L903] COND FALSE !(0 == ~E_7~0) [L908] COND FALSE !(0 == ~E_8~0) [L1011] havoc ~tmp~1; [L1012] havoc ~tmp___0~0; [L1013] havoc ~tmp___1~0; [L1014] havoc ~tmp___2~0; [L1015] havoc ~tmp___3~0; [L1016] havoc ~tmp___4~0; [L1017] havoc ~tmp___5~0; [L1018] havoc ~tmp___6~0; [L1019] havoc ~tmp___7~0; [L389] havoc ~__retres1~0; [L392] COND FALSE !(1 == ~m_pc~0) [L402] ~__retres1~0 := 0; [L404] #res := ~__retres1~0; [L1023] ~tmp~1 := #t~ret10; [L1023] havoc #t~ret10; [L1025-L1029] COND FALSE !(0 != ~tmp~1) [L408] havoc ~__retres1~1; [L411] COND FALSE !(1 == ~t1_pc~0) [L421] ~__retres1~1 := 0; [L423] #res := ~__retres1~1; [L1031] ~tmp___0~0 := #t~ret11; [L1031] havoc #t~ret11; [L1033-L1037] COND FALSE !(0 != ~tmp___0~0) [L427] havoc ~__retres1~2; [L430] COND FALSE !(1 == ~t2_pc~0) [L440] ~__retres1~2 := 0; [L442] #res := ~__retres1~2; [L1039] ~tmp___1~0 := #t~ret12; [L1039] havoc #t~ret12; [L1041-L1045] COND FALSE !(0 != ~tmp___1~0) [L446] havoc ~__retres1~3; [L449] COND FALSE !(1 == ~t3_pc~0) [L459] ~__retres1~3 := 0; [L461] #res := ~__retres1~3; [L1047] ~tmp___2~0 := #t~ret13; [L1047] havoc #t~ret13; [L1049-L1053] COND FALSE !(0 != ~tmp___2~0) [L465] havoc ~__retres1~4; [L468] COND FALSE !(1 == ~t4_pc~0) [L478] ~__retres1~4 := 0; [L480] #res := ~__retres1~4; [L1055] ~tmp___3~0 := #t~ret14; [L1055] havoc #t~ret14; [L1057-L1061] COND FALSE !(0 != ~tmp___3~0) [L484] havoc ~__retres1~5; [L487] COND FALSE !(1 == ~t5_pc~0) [L497] ~__retres1~5 := 0; [L499] #res := ~__retres1~5; [L1063] ~tmp___4~0 := #t~ret15; [L1063] havoc #t~ret15; [L1065-L1069] COND FALSE !(0 != ~tmp___4~0) [L503] havoc ~__retres1~6; [L506] COND FALSE !(1 == ~t6_pc~0) [L516] ~__retres1~6 := 0; [L518] #res := ~__retres1~6; [L1071] ~tmp___5~0 := #t~ret16; [L1071] havoc #t~ret16; [L1073-L1077] COND FALSE !(0 != ~tmp___5~0) [L522] havoc ~__retres1~7; [L525] COND FALSE !(1 == ~t7_pc~0) [L535] ~__retres1~7 := 0; [L537] #res := ~__retres1~7; [L1079] ~tmp___6~0 := #t~ret17; [L1079] havoc #t~ret17; [L1081-L1085] COND FALSE !(0 != ~tmp___6~0) [L541] havoc ~__retres1~8; [L544] COND FALSE !(1 == ~t8_pc~0) [L554] ~__retres1~8 := 0; [L556] #res := ~__retres1~8; [L1087] ~tmp___7~0 := #t~ret18; [L1087] havoc #t~ret18; [L1089-L1093] COND FALSE !(0 != ~tmp___7~0) [L921] COND FALSE !(1 == ~M_E~0) [L926] COND FALSE !(1 == ~T1_E~0) [L931] COND FALSE !(1 == ~T2_E~0) [L936] COND FALSE !(1 == ~T3_E~0) [L941] COND FALSE !(1 == ~T4_E~0) [L946] COND FALSE !(1 == ~T5_E~0) [L951] COND FALSE !(1 == ~T6_E~0) [L956] COND FALSE !(1 == ~T7_E~0) [L961] COND FALSE !(1 == ~T8_E~0) [L966] COND FALSE !(1 == ~E_1~0) [L971] COND FALSE !(1 == ~E_2~0) [L976] COND FALSE !(1 == ~E_3~0) [L981] COND FALSE !(1 == ~E_4~0) [L986] COND FALSE !(1 == ~E_5~0) [L991] COND FALSE !(1 == ~E_6~0) [L996] COND FALSE !(1 == ~E_7~0) [L1001] COND FALSE !(1 == ~E_8~0) [L1262-L1299] COND FALSE !(false) [L1265] ~kernel_st~0 := 1; [L677] havoc ~tmp~0; [L15] int m_pc = 0; [L16] int t1_pc = 0; [L17] int t2_pc = 0; [L18] int t3_pc = 0; [L19] int t4_pc = 0; [L20] int t5_pc = 0; [L21] int t6_pc = 0; [L22] int t7_pc = 0; [L23] int t8_pc = 0; [L24] int m_st ; [L25] int t1_st ; [L26] int t2_st ; [L27] int t3_st ; [L28] int t4_st ; [L29] int t5_st ; [L30] int t6_st ; [L31] int t7_st ; [L32] int t8_st ; [L33] int m_i ; [L34] int t1_i ; [L35] int t2_i ; [L36] int t3_i ; [L37] int t4_i ; [L38] int t5_i ; [L39] int t6_i ; [L40] int t7_i ; [L41] int t8_i ; [L42] int M_E = 2; [L43] int T1_E = 2; [L44] int T2_E = 2; [L45] int T3_E = 2; [L46] int T4_E = 2; [L47] int T5_E = 2; [L48] int T6_E = 2; [L49] int T7_E = 2; [L50] int T8_E = 2; [L51] int E_1 = 2; [L52] int E_2 = 2; [L53] int E_3 = 2; [L54] int E_4 = 2; [L55] int E_5 = 2; [L56] int E_6 = 2; [L57] int E_7 = 2; [L58] int E_8 = 2; [L1307] int __retres1 ; [L1215] m_i = 1 [L1216] t1_i = 1 [L1217] t2_i = 1 [L1218] t3_i = 1 [L1219] t4_i = 1 [L1220] t5_i = 1 [L1221] t6_i = 1 [L1222] t7_i = 1 [L1223] t8_i = 1 [L1248] int kernel_st ; [L1249] int tmp ; [L1250] int tmp___0 ; [L1254] kernel_st = 0 [L571] COND TRUE m_i == 1 [L572] m_st = 0 [L576] COND TRUE t1_i == 1 [L577] t1_st = 0 [L581] COND TRUE t2_i == 1 [L582] t2_st = 0 [L586] COND TRUE t3_i == 1 [L587] t3_st = 0 [L591] COND TRUE t4_i == 1 [L592] t4_st = 0 [L596] COND TRUE t5_i == 1 [L597] t5_st = 0 [L601] COND TRUE t6_i == 1 [L602] t6_st = 0 [L606] COND TRUE t7_i == 1 [L607] t7_st = 0 [L611] COND TRUE t8_i == 1 [L612] t8_st = 0 [L828] COND FALSE !(M_E == 0) [L833] COND FALSE !(T1_E == 0) [L838] COND FALSE !(T2_E == 0) [L843] COND FALSE !(T3_E == 0) [L848] COND FALSE !(T4_E == 0) [L853] COND FALSE !(T5_E == 0) [L858] COND FALSE !(T6_E == 0) [L863] COND FALSE !(T7_E == 0) [L868] COND FALSE !(T8_E == 0) [L873] COND FALSE !(E_1 == 0) [L878] COND FALSE !(E_2 == 0) [L883] COND FALSE !(E_3 == 0) [L888] COND FALSE !(E_4 == 0) [L893] COND FALSE !(E_5 == 0) [L898] COND FALSE !(E_6 == 0) [L903] COND FALSE !(E_7 == 0) [L908] COND FALSE !(E_8 == 0) [L1011] int tmp ; [L1012] int tmp___0 ; [L1013] int tmp___1 ; [L1014] int tmp___2 ; [L1015] int tmp___3 ; [L1016] int tmp___4 ; [L1017] int tmp___5 ; [L1018] int tmp___6 ; [L1019] int tmp___7 ; [L389] int __retres1 ; [L392] COND FALSE !(m_pc == 1) [L402] __retres1 = 0 [L404] return (__retres1); [L1023] tmp = is_master_triggered() [L1025] COND FALSE !(\read(tmp)) [L408] int __retres1 ; [L411] COND FALSE !(t1_pc == 1) [L421] __retres1 = 0 [L423] return (__retres1); [L1031] tmp___0 = is_transmit1_triggered() [L1033] COND FALSE !(\read(tmp___0)) [L427] int __retres1 ; [L430] COND FALSE !(t2_pc == 1) [L440] __retres1 = 0 [L442] return (__retres1); [L1039] tmp___1 = is_transmit2_triggered() [L1041] COND FALSE !(\read(tmp___1)) [L446] int __retres1 ; [L449] COND FALSE !(t3_pc == 1) [L459] __retres1 = 0 [L461] return (__retres1); [L1047] tmp___2 = is_transmit3_triggered() [L1049] COND FALSE !(\read(tmp___2)) [L465] int __retres1 ; [L468] COND FALSE !(t4_pc == 1) [L478] __retres1 = 0 [L480] return (__retres1); [L1055] tmp___3 = is_transmit4_triggered() [L1057] COND FALSE !(\read(tmp___3)) [L484] int __retres1 ; [L487] COND FALSE !(t5_pc == 1) [L497] __retres1 = 0 [L499] return (__retres1); [L1063] tmp___4 = is_transmit5_triggered() [L1065] COND FALSE !(\read(tmp___4)) [L503] int __retres1 ; [L506] COND FALSE !(t6_pc == 1) [L516] __retres1 = 0 [L518] return (__retres1); [L1071] tmp___5 = is_transmit6_triggered() [L1073] COND FALSE !(\read(tmp___5)) [L522] int __retres1 ; [L525] COND FALSE !(t7_pc == 1) [L535] __retres1 = 0 [L537] return (__retres1); [L1079] tmp___6 = is_transmit7_triggered() [L1081] COND FALSE !(\read(tmp___6)) [L541] int __retres1 ; [L544] COND FALSE !(t8_pc == 1) [L554] __retres1 = 0 [L556] return (__retres1); [L1087] tmp___7 = is_transmit8_triggered() [L1089] COND FALSE !(\read(tmp___7)) [L921] COND FALSE !(M_E == 1) [L926] COND FALSE !(T1_E == 1) [L931] COND FALSE !(T2_E == 1) [L936] COND FALSE !(T3_E == 1) [L941] COND FALSE !(T4_E == 1) [L946] COND FALSE !(T5_E == 1) [L951] COND FALSE !(T6_E == 1) [L956] COND FALSE !(T7_E == 1) [L961] COND FALSE !(T8_E == 1) [L966] COND FALSE !(E_1 == 1) [L971] COND FALSE !(E_2 == 1) [L976] COND FALSE !(E_3 == 1) [L981] COND FALSE !(E_4 == 1) [L986] COND FALSE !(E_5 == 1) [L991] COND FALSE !(E_6 == 1) [L996] COND FALSE !(E_7 == 1) [L1001] COND FALSE !(E_8 == 1) [L1262] COND TRUE 1 [L1265] kernel_st = 1 [L677] int tmp ; ----- ----- class de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder.RCFGBacktranslator [?] assume !false; [?] havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~9;havoc exists_runnable_thread_~__retres1~9; [?] assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9 := 1; [?] exists_runnable_thread_#res := exists_runnable_thread_~__retres1~9; [?] eval_#t~ret0 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret0;havoc eval_#t~ret0; [?] assume 0 != eval_~tmp~0; [?] assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0;eval_~tmp_ndt_1~0 := eval_#t~nondet1;havoc eval_#t~nondet1; [?] assume !(0 != eval_~tmp_ndt_1~0); [?] assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0;eval_~tmp_ndt_2~0 := eval_#t~nondet2;havoc eval_#t~nondet2; [?] assume !(0 != eval_~tmp_ndt_2~0); [?] assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0;eval_~tmp_ndt_3~0 := eval_#t~nondet3;havoc eval_#t~nondet3; [?] assume !(0 != eval_~tmp_ndt_3~0); [?] assume 0 == ~t3_st~0;havoc eval_~tmp_ndt_4~0;eval_~tmp_ndt_4~0 := eval_#t~nondet4;havoc eval_#t~nondet4; [?] assume !(0 != eval_~tmp_ndt_4~0); [?] assume 0 == ~t4_st~0;havoc eval_~tmp_ndt_5~0;eval_~tmp_ndt_5~0 := eval_#t~nondet5;havoc eval_#t~nondet5; [?] assume !(0 != eval_~tmp_ndt_5~0); [?] assume 0 == ~t5_st~0;havoc eval_~tmp_ndt_6~0;eval_~tmp_ndt_6~0 := eval_#t~nondet6;havoc eval_#t~nondet6; [?] assume !(0 != eval_~tmp_ndt_6~0); [?] assume 0 == ~t6_st~0;havoc eval_~tmp_ndt_7~0;eval_~tmp_ndt_7~0 := eval_#t~nondet7;havoc eval_#t~nondet7; [?] assume !(0 != eval_~tmp_ndt_7~0); [?] assume 0 == ~t7_st~0;havoc eval_~tmp_ndt_8~0;eval_~tmp_ndt_8~0 := eval_#t~nondet8;havoc eval_#t~nondet8; [?] assume !(0 != eval_~tmp_ndt_8~0); [?] assume 0 == ~t8_st~0;havoc eval_~tmp_ndt_9~0;eval_~tmp_ndt_9~0 := eval_#t~nondet9;havoc eval_#t~nondet9; [?] assume !(0 != eval_~tmp_ndt_9~0); [L681-L817] assume !false; [L684] havoc exists_runnable_thread_#res; [L684] havoc exists_runnable_thread_~__retres1~9; [L621] havoc exists_runnable_thread_~__retres1~9; [L624-L669] assume 0 == ~m_st~0; [L625] exists_runnable_thread_~__retres1~9 := 1; [L672] exists_runnable_thread_#res := exists_runnable_thread_~__retres1~9; [L684] eval_#t~ret0 := exists_runnable_thread_#res; [L684] eval_~tmp~0 := eval_#t~ret0; [L684] havoc eval_#t~ret0; [L686-L690] assume 0 != eval_~tmp~0; [L691-L704] assume 0 == ~m_st~0; [L692] havoc eval_~tmp_ndt_1~0; [L693] eval_~tmp_ndt_1~0 := eval_#t~nondet1; [L693] havoc eval_#t~nondet1; [L694-L701] assume !(0 != eval_~tmp_ndt_1~0); [L705-L718] assume 0 == ~t1_st~0; [L706] havoc eval_~tmp_ndt_2~0; [L707] eval_~tmp_ndt_2~0 := eval_#t~nondet2; [L707] havoc eval_#t~nondet2; [L708-L715] assume !(0 != eval_~tmp_ndt_2~0); [L719-L732] assume 0 == ~t2_st~0; [L720] havoc eval_~tmp_ndt_3~0; [L721] eval_~tmp_ndt_3~0 := eval_#t~nondet3; [L721] havoc eval_#t~nondet3; [L722-L729] assume !(0 != eval_~tmp_ndt_3~0); [L733-L746] assume 0 == ~t3_st~0; [L734] havoc eval_~tmp_ndt_4~0; [L735] eval_~tmp_ndt_4~0 := eval_#t~nondet4; [L735] havoc eval_#t~nondet4; [L736-L743] assume !(0 != eval_~tmp_ndt_4~0); [L747-L760] assume 0 == ~t4_st~0; [L748] havoc eval_~tmp_ndt_5~0; [L749] eval_~tmp_ndt_5~0 := eval_#t~nondet5; [L749] havoc eval_#t~nondet5; [L750-L757] assume !(0 != eval_~tmp_ndt_5~0); [L761-L774] assume 0 == ~t5_st~0; [L762] havoc eval_~tmp_ndt_6~0; [L763] eval_~tmp_ndt_6~0 := eval_#t~nondet6; [L763] havoc eval_#t~nondet6; [L764-L771] assume !(0 != eval_~tmp_ndt_6~0); [L775-L788] assume 0 == ~t6_st~0; [L776] havoc eval_~tmp_ndt_7~0; [L777] eval_~tmp_ndt_7~0 := eval_#t~nondet7; [L777] havoc eval_#t~nondet7; [L778-L785] assume !(0 != eval_~tmp_ndt_7~0); [L789-L802] assume 0 == ~t7_st~0; [L790] havoc eval_~tmp_ndt_8~0; [L791] eval_~tmp_ndt_8~0 := eval_#t~nondet8; [L791] havoc eval_#t~nondet8; [L792-L799] assume !(0 != eval_~tmp_ndt_8~0); [L803-L816] assume 0 == ~t8_st~0; [L804] havoc eval_~tmp_ndt_9~0; [L805] eval_~tmp_ndt_9~0 := eval_#t~nondet9; [L805] havoc eval_#t~nondet9; [L806-L813] assume !(0 != eval_~tmp_ndt_9~0); ----- ----- class de.uni_freiburg.informatik.ultimate.boogie.preprocessor.BoogiePreprocessorBacktranslator [L681-L817] assume !false; [L684] havoc exists_runnable_thread_#res; [L684] havoc exists_runnable_thread_~__retres1~9; [L621] havoc exists_runnable_thread_~__retres1~9; [L624-L669] assume 0 == ~m_st~0; [L625] exists_runnable_thread_~__retres1~9 := 1; [L672] exists_runnable_thread_#res := exists_runnable_thread_~__retres1~9; [L684] eval_#t~ret0 := exists_runnable_thread_#res; [L684] eval_~tmp~0 := eval_#t~ret0; [L684] havoc eval_#t~ret0; [L686-L690] assume 0 != eval_~tmp~0; [L691-L704] assume 0 == ~m_st~0; [L692] havoc eval_~tmp_ndt_1~0; [L693] eval_~tmp_ndt_1~0 := eval_#t~nondet1; [L693] havoc eval_#t~nondet1; [L694-L701] assume !(0 != eval_~tmp_ndt_1~0); [L705-L718] assume 0 == ~t1_st~0; [L706] havoc eval_~tmp_ndt_2~0; [L707] eval_~tmp_ndt_2~0 := eval_#t~nondet2; [L707] havoc eval_#t~nondet2; [L708-L715] assume !(0 != eval_~tmp_ndt_2~0); [L719-L732] assume 0 == ~t2_st~0; [L720] havoc eval_~tmp_ndt_3~0; [L721] eval_~tmp_ndt_3~0 := eval_#t~nondet3; [L721] havoc eval_#t~nondet3; [L722-L729] assume !(0 != eval_~tmp_ndt_3~0); [L733-L746] assume 0 == ~t3_st~0; [L734] havoc eval_~tmp_ndt_4~0; [L735] eval_~tmp_ndt_4~0 := eval_#t~nondet4; [L735] havoc eval_#t~nondet4; [L736-L743] assume !(0 != eval_~tmp_ndt_4~0); [L747-L760] assume 0 == ~t4_st~0; [L748] havoc eval_~tmp_ndt_5~0; [L749] eval_~tmp_ndt_5~0 := eval_#t~nondet5; [L749] havoc eval_#t~nondet5; [L750-L757] assume !(0 != eval_~tmp_ndt_5~0); [L761-L774] assume 0 == ~t5_st~0; [L762] havoc eval_~tmp_ndt_6~0; [L763] eval_~tmp_ndt_6~0 := eval_#t~nondet6; [L763] havoc eval_#t~nondet6; [L764-L771] assume !(0 != eval_~tmp_ndt_6~0); [L775-L788] assume 0 == ~t6_st~0; [L776] havoc eval_~tmp_ndt_7~0; [L777] eval_~tmp_ndt_7~0 := eval_#t~nondet7; [L777] havoc eval_#t~nondet7; [L778-L785] assume !(0 != eval_~tmp_ndt_7~0); [L789-L802] assume 0 == ~t7_st~0; [L790] havoc eval_~tmp_ndt_8~0; [L791] eval_~tmp_ndt_8~0 := eval_#t~nondet8; [L791] havoc eval_#t~nondet8; [L792-L799] assume !(0 != eval_~tmp_ndt_8~0); [L803-L816] assume 0 == ~t8_st~0; [L804] havoc eval_~tmp_ndt_9~0; [L805] eval_~tmp_ndt_9~0 := eval_#t~nondet9; [L805] havoc eval_#t~nondet9; [L806-L813] assume !(0 != eval_~tmp_ndt_9~0); [L681-L817] COND FALSE !(false) [L684] havoc exists_runnable_thread_#res; [L684] havoc exists_runnable_thread_~__retres1~9; [L621] havoc exists_runnable_thread_~__retres1~9; [L624] COND TRUE 0 == ~m_st~0 [L625] exists_runnable_thread_~__retres1~9 := 1; [L672] exists_runnable_thread_#res := exists_runnable_thread_~__retres1~9; [L684] eval_#t~ret0 := exists_runnable_thread_#res; [L684] eval_~tmp~0 := eval_#t~ret0; [L684] havoc eval_#t~ret0; [L686-L690] COND TRUE 0 != eval_~tmp~0 [L691] COND TRUE 0 == ~m_st~0 [L692] havoc eval_~tmp_ndt_1~0; [L693] eval_~tmp_ndt_1~0 := eval_#t~nondet1; [L693] havoc eval_#t~nondet1; [L694-L701] COND FALSE !(0 != eval_~tmp_ndt_1~0) [L705] COND TRUE 0 == ~t1_st~0 [L706] havoc eval_~tmp_ndt_2~0; [L707] eval_~tmp_ndt_2~0 := eval_#t~nondet2; [L707] havoc eval_#t~nondet2; [L708-L715] COND FALSE !(0 != eval_~tmp_ndt_2~0) [L719] COND TRUE 0 == ~t2_st~0 [L720] havoc eval_~tmp_ndt_3~0; [L721] eval_~tmp_ndt_3~0 := eval_#t~nondet3; [L721] havoc eval_#t~nondet3; [L722-L729] COND FALSE !(0 != eval_~tmp_ndt_3~0) [L733] COND TRUE 0 == ~t3_st~0 [L734] havoc eval_~tmp_ndt_4~0; [L735] eval_~tmp_ndt_4~0 := eval_#t~nondet4; [L735] havoc eval_#t~nondet4; [L736-L743] COND FALSE !(0 != eval_~tmp_ndt_4~0) [L747] COND TRUE 0 == ~t4_st~0 [L748] havoc eval_~tmp_ndt_5~0; [L749] eval_~tmp_ndt_5~0 := eval_#t~nondet5; [L749] havoc eval_#t~nondet5; [L750-L757] COND FALSE !(0 != eval_~tmp_ndt_5~0) [L761] COND TRUE 0 == ~t5_st~0 [L762] havoc eval_~tmp_ndt_6~0; [L763] eval_~tmp_ndt_6~0 := eval_#t~nondet6; [L763] havoc eval_#t~nondet6; [L764-L771] COND FALSE !(0 != eval_~tmp_ndt_6~0) [L775] COND TRUE 0 == ~t6_st~0 [L776] havoc eval_~tmp_ndt_7~0; [L777] eval_~tmp_ndt_7~0 := eval_#t~nondet7; [L777] havoc eval_#t~nondet7; [L778-L785] COND FALSE !(0 != eval_~tmp_ndt_7~0) [L789] COND TRUE 0 == ~t7_st~0 [L790] havoc eval_~tmp_ndt_8~0; [L791] eval_~tmp_ndt_8~0 := eval_#t~nondet8; [L791] havoc eval_#t~nondet8; [L792-L799] COND FALSE !(0 != eval_~tmp_ndt_8~0) [L803] COND TRUE 0 == ~t8_st~0 [L804] havoc eval_~tmp_ndt_9~0; [L805] eval_~tmp_ndt_9~0 := eval_#t~nondet9; [L805] havoc eval_#t~nondet9; [L806-L813] COND FALSE !(0 != eval_~tmp_ndt_9~0) ----- ----- class de.uni_freiburg.informatik.ultimate.boogie.procedureinliner.backtranslation.InlinerBacktranslator [L681-L817] COND FALSE !(false) [L684] havoc exists_runnable_thread_#res; [L684] havoc exists_runnable_thread_~__retres1~9; [L621] havoc exists_runnable_thread_~__retres1~9; [L624] COND TRUE 0 == ~m_st~0 [L625] exists_runnable_thread_~__retres1~9 := 1; [L672] exists_runnable_thread_#res := exists_runnable_thread_~__retres1~9; [L684] eval_#t~ret0 := exists_runnable_thread_#res; [L684] eval_~tmp~0 := eval_#t~ret0; [L684] havoc eval_#t~ret0; [L686-L690] COND TRUE 0 != eval_~tmp~0 [L691] COND TRUE 0 == ~m_st~0 [L692] havoc eval_~tmp_ndt_1~0; [L693] eval_~tmp_ndt_1~0 := eval_#t~nondet1; [L693] havoc eval_#t~nondet1; [L694-L701] COND FALSE !(0 != eval_~tmp_ndt_1~0) [L705] COND TRUE 0 == ~t1_st~0 [L706] havoc eval_~tmp_ndt_2~0; [L707] eval_~tmp_ndt_2~0 := eval_#t~nondet2; [L707] havoc eval_#t~nondet2; [L708-L715] COND FALSE !(0 != eval_~tmp_ndt_2~0) [L719] COND TRUE 0 == ~t2_st~0 [L720] havoc eval_~tmp_ndt_3~0; [L721] eval_~tmp_ndt_3~0 := eval_#t~nondet3; [L721] havoc eval_#t~nondet3; [L722-L729] COND FALSE !(0 != eval_~tmp_ndt_3~0) [L733] COND TRUE 0 == ~t3_st~0 [L734] havoc eval_~tmp_ndt_4~0; [L735] eval_~tmp_ndt_4~0 := eval_#t~nondet4; [L735] havoc eval_#t~nondet4; [L736-L743] COND FALSE !(0 != eval_~tmp_ndt_4~0) [L747] COND TRUE 0 == ~t4_st~0 [L748] havoc eval_~tmp_ndt_5~0; [L749] eval_~tmp_ndt_5~0 := eval_#t~nondet5; [L749] havoc eval_#t~nondet5; [L750-L757] COND FALSE !(0 != eval_~tmp_ndt_5~0) [L761] COND TRUE 0 == ~t5_st~0 [L762] havoc eval_~tmp_ndt_6~0; [L763] eval_~tmp_ndt_6~0 := eval_#t~nondet6; [L763] havoc eval_#t~nondet6; [L764-L771] COND FALSE !(0 != eval_~tmp_ndt_6~0) [L775] COND TRUE 0 == ~t6_st~0 [L776] havoc eval_~tmp_ndt_7~0; [L777] eval_~tmp_ndt_7~0 := eval_#t~nondet7; [L777] havoc eval_#t~nondet7; [L778-L785] COND FALSE !(0 != eval_~tmp_ndt_7~0) [L789] COND TRUE 0 == ~t7_st~0 [L790] havoc eval_~tmp_ndt_8~0; [L791] eval_~tmp_ndt_8~0 := eval_#t~nondet8; [L791] havoc eval_#t~nondet8; [L792-L799] COND FALSE !(0 != eval_~tmp_ndt_8~0) [L803] COND TRUE 0 == ~t8_st~0 [L804] havoc eval_~tmp_ndt_9~0; [L805] eval_~tmp_ndt_9~0 := eval_#t~nondet9; [L805] havoc eval_#t~nondet9; [L806-L813] COND FALSE !(0 != eval_~tmp_ndt_9~0) [L681-L817] COND FALSE !(false) [L621] havoc ~__retres1~9; [L624] COND TRUE 0 == ~m_st~0 [L625] ~__retres1~9 := 1; [L672] #res := ~__retres1~9; [L684] ~tmp~0 := #t~ret0; [L684] havoc #t~ret0; [L686-L690] COND TRUE 0 != ~tmp~0 [L691] COND TRUE 0 == ~m_st~0 [L692] havoc ~tmp_ndt_1~0; [L693] ~tmp_ndt_1~0 := #t~nondet1; [L693] havoc #t~nondet1; [L694-L701] COND FALSE !(0 != ~tmp_ndt_1~0) [L705] COND TRUE 0 == ~t1_st~0 [L706] havoc ~tmp_ndt_2~0; [L707] ~tmp_ndt_2~0 := #t~nondet2; [L707] havoc #t~nondet2; [L708-L715] COND FALSE !(0 != ~tmp_ndt_2~0) [L719] COND TRUE 0 == ~t2_st~0 [L720] havoc ~tmp_ndt_3~0; [L721] ~tmp_ndt_3~0 := #t~nondet3; [L721] havoc #t~nondet3; [L722-L729] COND FALSE !(0 != ~tmp_ndt_3~0) [L733] COND TRUE 0 == ~t3_st~0 [L734] havoc ~tmp_ndt_4~0; [L735] ~tmp_ndt_4~0 := #t~nondet4; [L735] havoc #t~nondet4; [L736-L743] COND FALSE !(0 != ~tmp_ndt_4~0) [L747] COND TRUE 0 == ~t4_st~0 [L748] havoc ~tmp_ndt_5~0; [L749] ~tmp_ndt_5~0 := #t~nondet5; [L749] havoc #t~nondet5; [L750-L757] COND FALSE !(0 != ~tmp_ndt_5~0) [L761] COND TRUE 0 == ~t5_st~0 [L762] havoc ~tmp_ndt_6~0; [L763] ~tmp_ndt_6~0 := #t~nondet6; [L763] havoc #t~nondet6; [L764-L771] COND FALSE !(0 != ~tmp_ndt_6~0) [L775] COND TRUE 0 == ~t6_st~0 [L776] havoc ~tmp_ndt_7~0; [L777] ~tmp_ndt_7~0 := #t~nondet7; [L777] havoc #t~nondet7; [L778-L785] COND FALSE !(0 != ~tmp_ndt_7~0) [L789] COND TRUE 0 == ~t7_st~0 [L790] havoc ~tmp_ndt_8~0; [L791] ~tmp_ndt_8~0 := #t~nondet8; [L791] havoc #t~nondet8; [L792-L799] COND FALSE !(0 != ~tmp_ndt_8~0) [L803] COND TRUE 0 == ~t8_st~0 [L804] havoc ~tmp_ndt_9~0; [L805] ~tmp_ndt_9~0 := #t~nondet9; [L805] havoc #t~nondet9; [L806-L813] COND FALSE !(0 != ~tmp_ndt_9~0) ----- ----- class de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.CACSL2BoogieBacktranslator [L681-L817] COND FALSE !(false) [L621] havoc ~__retres1~9; [L624] COND TRUE 0 == ~m_st~0 [L625] ~__retres1~9 := 1; [L672] #res := ~__retres1~9; [L684] ~tmp~0 := #t~ret0; [L684] havoc #t~ret0; [L686-L690] COND TRUE 0 != ~tmp~0 [L691] COND TRUE 0 == ~m_st~0 [L692] havoc ~tmp_ndt_1~0; [L693] ~tmp_ndt_1~0 := #t~nondet1; [L693] havoc #t~nondet1; [L694-L701] COND FALSE !(0 != ~tmp_ndt_1~0) [L705] COND TRUE 0 == ~t1_st~0 [L706] havoc ~tmp_ndt_2~0; [L707] ~tmp_ndt_2~0 := #t~nondet2; [L707] havoc #t~nondet2; [L708-L715] COND FALSE !(0 != ~tmp_ndt_2~0) [L719] COND TRUE 0 == ~t2_st~0 [L720] havoc ~tmp_ndt_3~0; [L721] ~tmp_ndt_3~0 := #t~nondet3; [L721] havoc #t~nondet3; [L722-L729] COND FALSE !(0 != ~tmp_ndt_3~0) [L733] COND TRUE 0 == ~t3_st~0 [L734] havoc ~tmp_ndt_4~0; [L735] ~tmp_ndt_4~0 := #t~nondet4; [L735] havoc #t~nondet4; [L736-L743] COND FALSE !(0 != ~tmp_ndt_4~0) [L747] COND TRUE 0 == ~t4_st~0 [L748] havoc ~tmp_ndt_5~0; [L749] ~tmp_ndt_5~0 := #t~nondet5; [L749] havoc #t~nondet5; [L750-L757] COND FALSE !(0 != ~tmp_ndt_5~0) [L761] COND TRUE 0 == ~t5_st~0 [L762] havoc ~tmp_ndt_6~0; [L763] ~tmp_ndt_6~0 := #t~nondet6; [L763] havoc #t~nondet6; [L764-L771] COND FALSE !(0 != ~tmp_ndt_6~0) [L775] COND TRUE 0 == ~t6_st~0 [L776] havoc ~tmp_ndt_7~0; [L777] ~tmp_ndt_7~0 := #t~nondet7; [L777] havoc #t~nondet7; [L778-L785] COND FALSE !(0 != ~tmp_ndt_7~0) [L789] COND TRUE 0 == ~t7_st~0 [L790] havoc ~tmp_ndt_8~0; [L791] ~tmp_ndt_8~0 := #t~nondet8; [L791] havoc #t~nondet8; [L792-L799] COND FALSE !(0 != ~tmp_ndt_8~0) [L803] COND TRUE 0 == ~t8_st~0 [L804] havoc ~tmp_ndt_9~0; [L805] ~tmp_ndt_9~0 := #t~nondet9; [L805] havoc #t~nondet9; [L806-L813] COND FALSE !(0 != ~tmp_ndt_9~0) [L681] COND TRUE 1 [L621] int __retres1 ; [L624] COND TRUE m_st == 0 [L625] __retres1 = 1 [L672] return (__retres1); [L684] tmp = exists_runnable_thread() [L686] COND TRUE \read(tmp) [L691] COND TRUE m_st == 0 [L692] int tmp_ndt_1; [L693] tmp_ndt_1 = __VERIFIER_nondet_int() [L694] COND FALSE !(\read(tmp_ndt_1)) [L705] COND TRUE t1_st == 0 [L706] int tmp_ndt_2; [L707] tmp_ndt_2 = __VERIFIER_nondet_int() [L708] COND FALSE !(\read(tmp_ndt_2)) [L719] COND TRUE t2_st == 0 [L720] int tmp_ndt_3; [L721] tmp_ndt_3 = __VERIFIER_nondet_int() [L722] COND FALSE !(\read(tmp_ndt_3)) [L733] COND TRUE t3_st == 0 [L734] int tmp_ndt_4; [L735] tmp_ndt_4 = __VERIFIER_nondet_int() [L736] COND FALSE !(\read(tmp_ndt_4)) [L747] COND TRUE t4_st == 0 [L748] int tmp_ndt_5; [L749] tmp_ndt_5 = __VERIFIER_nondet_int() [L750] COND FALSE !(\read(tmp_ndt_5)) [L761] COND TRUE t5_st == 0 [L762] int tmp_ndt_6; [L763] tmp_ndt_6 = __VERIFIER_nondet_int() [L764] COND FALSE !(\read(tmp_ndt_6)) [L775] COND TRUE t6_st == 0 [L776] int tmp_ndt_7; [L777] tmp_ndt_7 = __VERIFIER_nondet_int() [L778] COND FALSE !(\read(tmp_ndt_7)) [L789] COND TRUE t7_st == 0 [L790] int tmp_ndt_8; [L791] tmp_ndt_8 = __VERIFIER_nondet_int() [L792] COND FALSE !(\read(tmp_ndt_8)) [L803] COND TRUE t8_st == 0 [L804] int tmp_ndt_9; [L805] tmp_ndt_9 = __VERIFIER_nondet_int() [L806] COND FALSE !(\read(tmp_ndt_9)) ----- ----- class de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder.RCFGBacktranslator [?] ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2; [?] havoc main_#res;havoc main_~__retres1~10;havoc main_~__retres1~10;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; [?] havoc start_simulation_#t~ret20, start_simulation_#t~ret21, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; [?] assume 1 == ~m_i~0;~m_st~0 := 0; [?] assume 1 == ~t1_i~0;~t1_st~0 := 0; [?] assume 1 == ~t2_i~0;~t2_st~0 := 0; [?] assume 1 == ~t3_i~0;~t3_st~0 := 0; [?] assume 1 == ~t4_i~0;~t4_st~0 := 0; [?] assume 1 == ~t5_i~0;~t5_st~0 := 0; [?] assume 1 == ~t6_i~0;~t6_st~0 := 0; [?] assume 1 == ~t7_i~0;~t7_st~0 := 0; [?] assume 1 == ~t8_i~0;~t8_st~0 := 0; [?] assume !(0 == ~M_E~0); [?] assume !(0 == ~T1_E~0); [?] assume !(0 == ~T2_E~0); [?] assume !(0 == ~T3_E~0); [?] assume !(0 == ~T4_E~0); [?] assume !(0 == ~T5_E~0); [?] assume !(0 == ~T6_E~0); [?] assume !(0 == ~T7_E~0); [?] assume !(0 == ~T8_E~0); [?] assume !(0 == ~E_1~0); [?] assume !(0 == ~E_2~0); [?] assume !(0 == ~E_3~0); [?] assume !(0 == ~E_4~0); [?] assume !(0 == ~E_5~0); [?] assume !(0 == ~E_6~0); [?] assume !(0 == ~E_7~0); [?] assume !(0 == ~E_8~0); [?] havoc activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; [?] assume !(1 == ~m_pc~0); [?] is_master_triggered_~__retres1~0 := 0; [?] is_master_triggered_#res := is_master_triggered_~__retres1~0; [?] activate_threads_#t~ret10 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; [?] assume !(0 != activate_threads_~tmp~1); [?] havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; [?] assume !(1 == ~t1_pc~0); [?] is_transmit1_triggered_~__retres1~1 := 0; [?] is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; [?] activate_threads_#t~ret11 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; [?] assume !(0 != activate_threads_~tmp___0~0); [?] havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; [?] assume !(1 == ~t2_pc~0); [?] is_transmit2_triggered_~__retres1~2 := 0; [?] is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; [?] activate_threads_#t~ret12 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; [?] assume !(0 != activate_threads_~tmp___1~0); [?] havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; [?] assume !(1 == ~t3_pc~0); [?] is_transmit3_triggered_~__retres1~3 := 0; [?] is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; [?] activate_threads_#t~ret13 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; [?] assume !(0 != activate_threads_~tmp___2~0); [?] havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; [?] assume !(1 == ~t4_pc~0); [?] is_transmit4_triggered_~__retres1~4 := 0; [?] is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; [?] activate_threads_#t~ret14 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; [?] assume !(0 != activate_threads_~tmp___3~0); [?] havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; [?] assume !(1 == ~t5_pc~0); [?] is_transmit5_triggered_~__retres1~5 := 0; [?] is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; [?] activate_threads_#t~ret15 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; [?] assume !(0 != activate_threads_~tmp___4~0); [?] havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; [?] assume !(1 == ~t6_pc~0); [?] is_transmit6_triggered_~__retres1~6 := 0; [?] is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; [?] activate_threads_#t~ret16 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; [?] assume !(0 != activate_threads_~tmp___5~0); [?] havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; [?] assume !(1 == ~t7_pc~0); [?] is_transmit7_triggered_~__retres1~7 := 0; [?] is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; [?] activate_threads_#t~ret17 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; [?] assume !(0 != activate_threads_~tmp___6~0); [?] havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; [?] assume !(1 == ~t8_pc~0); [?] is_transmit8_triggered_~__retres1~8 := 0; [?] is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; [?] activate_threads_#t~ret18 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; [?] assume !(0 != activate_threads_~tmp___7~0); [?] assume !(1 == ~M_E~0); [?] assume !(1 == ~T1_E~0); [?] assume !(1 == ~T2_E~0); [?] assume !(1 == ~T3_E~0); [?] assume !(1 == ~T4_E~0); [?] assume !(1 == ~T5_E~0); [?] assume !(1 == ~T6_E~0); [?] assume !(1 == ~T7_E~0); [?] assume !(1 == ~T8_E~0); [?] assume !(1 == ~E_1~0); [?] assume !(1 == ~E_2~0); [?] assume !(1 == ~E_3~0); [?] assume !(1 == ~E_4~0); [?] assume !(1 == ~E_5~0); [?] assume !(1 == ~E_6~0); [?] assume !(1 == ~E_7~0); [?] assume !(1 == ~E_8~0); [?] assume !false; [?] start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret0, eval_#t~nondet1, eval_~tmp_ndt_1~0, eval_#t~nondet2, eval_~tmp_ndt_2~0, eval_#t~nondet3, eval_~tmp_ndt_3~0, eval_#t~nondet4, eval_~tmp_ndt_4~0, eval_#t~nondet5, eval_~tmp_ndt_5~0, eval_#t~nondet6, eval_~tmp_ndt_6~0, eval_#t~nondet7, eval_~tmp_ndt_7~0, eval_#t~nondet8, eval_~tmp_ndt_8~0, eval_#t~nondet9, eval_~tmp_ndt_9~0, eval_~tmp~0;havoc eval_~tmp~0; [L15] ~m_pc~0 := 0; [L16] ~t1_pc~0 := 0; [L17] ~t2_pc~0 := 0; [L18] ~t3_pc~0 := 0; [L19] ~t4_pc~0 := 0; [L20] ~t5_pc~0 := 0; [L21] ~t6_pc~0 := 0; [L22] ~t7_pc~0 := 0; [L23] ~t8_pc~0 := 0; [L24] ~m_st~0 := 0; [L25] ~t1_st~0 := 0; [L26] ~t2_st~0 := 0; [L27] ~t3_st~0 := 0; [L28] ~t4_st~0 := 0; [L29] ~t5_st~0 := 0; [L30] ~t6_st~0 := 0; [L31] ~t7_st~0 := 0; [L32] ~t8_st~0 := 0; [L33] ~m_i~0 := 0; [L34] ~t1_i~0 := 0; [L35] ~t2_i~0 := 0; [L36] ~t3_i~0 := 0; [L37] ~t4_i~0 := 0; [L38] ~t5_i~0 := 0; [L39] ~t6_i~0 := 0; [L40] ~t7_i~0 := 0; [L41] ~t8_i~0 := 0; [L42] ~M_E~0 := 2; [L43] ~T1_E~0 := 2; [L44] ~T2_E~0 := 2; [L45] ~T3_E~0 := 2; [L46] ~T4_E~0 := 2; [L47] ~T5_E~0 := 2; [L48] ~T6_E~0 := 2; [L49] ~T7_E~0 := 2; [L50] ~T8_E~0 := 2; [L51] ~E_1~0 := 2; [L52] ~E_2~0 := 2; [L53] ~E_3~0 := 2; [L54] ~E_4~0 := 2; [L55] ~E_5~0 := 2; [L56] ~E_6~0 := 2; [L57] ~E_7~0 := 2; [L58] ~E_8~0 := 2; [?] havoc main_#res; [?] havoc main_~__retres1~10; [L1307] havoc main_~__retres1~10; [L1215] ~m_i~0 := 1; [L1216] ~t1_i~0 := 1; [L1217] ~t2_i~0 := 1; [L1218] ~t3_i~0 := 1; [L1219] ~t4_i~0 := 1; [L1220] ~t5_i~0 := 1; [L1221] ~t6_i~0 := 1; [L1222] ~t7_i~0 := 1; [L1223] ~t8_i~0 := 1; [L1312] havoc start_simulation_#t~ret20, start_simulation_#t~ret21, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1; [L1248] havoc start_simulation_~kernel_st~0; [L1249] havoc start_simulation_~tmp~3; [L1250] havoc start_simulation_~tmp___0~1; [L1254] start_simulation_~kernel_st~0 := 0; [L571-L575] assume 1 == ~m_i~0; [L572] ~m_st~0 := 0; [L576-L580] assume 1 == ~t1_i~0; [L577] ~t1_st~0 := 0; [L581-L585] assume 1 == ~t2_i~0; [L582] ~t2_st~0 := 0; [L586-L590] assume 1 == ~t3_i~0; [L587] ~t3_st~0 := 0; [L591-L595] assume 1 == ~t4_i~0; [L592] ~t4_st~0 := 0; [L596-L600] assume 1 == ~t5_i~0; [L597] ~t5_st~0 := 0; [L601-L605] assume 1 == ~t6_i~0; [L602] ~t6_st~0 := 0; [L606-L610] assume 1 == ~t7_i~0; [L607] ~t7_st~0 := 0; [L611-L615] assume 1 == ~t8_i~0; [L612] ~t8_st~0 := 0; [L828-L832] assume !(0 == ~M_E~0); [L833-L837] assume !(0 == ~T1_E~0); [L838-L842] assume !(0 == ~T2_E~0); [L843-L847] assume !(0 == ~T3_E~0); [L848-L852] assume !(0 == ~T4_E~0); [L853-L857] assume !(0 == ~T5_E~0); [L858-L862] assume !(0 == ~T6_E~0); [L863-L867] assume !(0 == ~T7_E~0); [L868-L872] assume !(0 == ~T8_E~0); [L873-L877] assume !(0 == ~E_1~0); [L878-L882] assume !(0 == ~E_2~0); [L883-L887] assume !(0 == ~E_3~0); [L888-L892] assume !(0 == ~E_4~0); [L893-L897] assume !(0 == ~E_5~0); [L898-L902] assume !(0 == ~E_6~0); [L903-L907] assume !(0 == ~E_7~0); [L908-L912] assume !(0 == ~E_8~0); [L1258] havoc activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0; [L1011] havoc activate_threads_~tmp~1; [L1012] havoc activate_threads_~tmp___0~0; [L1013] havoc activate_threads_~tmp___1~0; [L1014] havoc activate_threads_~tmp___2~0; [L1015] havoc activate_threads_~tmp___3~0; [L1016] havoc activate_threads_~tmp___4~0; [L1017] havoc activate_threads_~tmp___5~0; [L1018] havoc activate_threads_~tmp___6~0; [L1019] havoc activate_threads_~tmp___7~0; [L1023] havoc is_master_triggered_#res; [L1023] havoc is_master_triggered_~__retres1~0; [L389] havoc is_master_triggered_~__retres1~0; [L392-L401] assume !(1 == ~m_pc~0); [L402] is_master_triggered_~__retres1~0 := 0; [L404] is_master_triggered_#res := is_master_triggered_~__retres1~0; [L1023] activate_threads_#t~ret10 := is_master_triggered_#res; [L1023] activate_threads_~tmp~1 := activate_threads_#t~ret10; [L1023] havoc activate_threads_#t~ret10; [L1025-L1029] assume !(0 != activate_threads_~tmp~1); [L1031] havoc is_transmit1_triggered_#res; [L1031] havoc is_transmit1_triggered_~__retres1~1; [L408] havoc is_transmit1_triggered_~__retres1~1; [L411-L420] assume !(1 == ~t1_pc~0); [L421] is_transmit1_triggered_~__retres1~1 := 0; [L423] is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; [L1031] activate_threads_#t~ret11 := is_transmit1_triggered_#res; [L1031] activate_threads_~tmp___0~0 := activate_threads_#t~ret11; [L1031] havoc activate_threads_#t~ret11; [L1033-L1037] assume !(0 != activate_threads_~tmp___0~0); [L1039] havoc is_transmit2_triggered_#res; [L1039] havoc is_transmit2_triggered_~__retres1~2; [L427] havoc is_transmit2_triggered_~__retres1~2; [L430-L439] assume !(1 == ~t2_pc~0); [L440] is_transmit2_triggered_~__retres1~2 := 0; [L442] is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; [L1039] activate_threads_#t~ret12 := is_transmit2_triggered_#res; [L1039] activate_threads_~tmp___1~0 := activate_threads_#t~ret12; [L1039] havoc activate_threads_#t~ret12; [L1041-L1045] assume !(0 != activate_threads_~tmp___1~0); [L1047] havoc is_transmit3_triggered_#res; [L1047] havoc is_transmit3_triggered_~__retres1~3; [L446] havoc is_transmit3_triggered_~__retres1~3; [L449-L458] assume !(1 == ~t3_pc~0); [L459] is_transmit3_triggered_~__retres1~3 := 0; [L461] is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; [L1047] activate_threads_#t~ret13 := is_transmit3_triggered_#res; [L1047] activate_threads_~tmp___2~0 := activate_threads_#t~ret13; [L1047] havoc activate_threads_#t~ret13; [L1049-L1053] assume !(0 != activate_threads_~tmp___2~0); [L1055] havoc is_transmit4_triggered_#res; [L1055] havoc is_transmit4_triggered_~__retres1~4; [L465] havoc is_transmit4_triggered_~__retres1~4; [L468-L477] assume !(1 == ~t4_pc~0); [L478] is_transmit4_triggered_~__retres1~4 := 0; [L480] is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; [L1055] activate_threads_#t~ret14 := is_transmit4_triggered_#res; [L1055] activate_threads_~tmp___3~0 := activate_threads_#t~ret14; [L1055] havoc activate_threads_#t~ret14; [L1057-L1061] assume !(0 != activate_threads_~tmp___3~0); [L1063] havoc is_transmit5_triggered_#res; [L1063] havoc is_transmit5_triggered_~__retres1~5; [L484] havoc is_transmit5_triggered_~__retres1~5; [L487-L496] assume !(1 == ~t5_pc~0); [L497] is_transmit5_triggered_~__retres1~5 := 0; [L499] is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; [L1063] activate_threads_#t~ret15 := is_transmit5_triggered_#res; [L1063] activate_threads_~tmp___4~0 := activate_threads_#t~ret15; [L1063] havoc activate_threads_#t~ret15; [L1065-L1069] assume !(0 != activate_threads_~tmp___4~0); [L1071] havoc is_transmit6_triggered_#res; [L1071] havoc is_transmit6_triggered_~__retres1~6; [L503] havoc is_transmit6_triggered_~__retres1~6; [L506-L515] assume !(1 == ~t6_pc~0); [L516] is_transmit6_triggered_~__retres1~6 := 0; [L518] is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; [L1071] activate_threads_#t~ret16 := is_transmit6_triggered_#res; [L1071] activate_threads_~tmp___5~0 := activate_threads_#t~ret16; [L1071] havoc activate_threads_#t~ret16; [L1073-L1077] assume !(0 != activate_threads_~tmp___5~0); [L1079] havoc is_transmit7_triggered_#res; [L1079] havoc is_transmit7_triggered_~__retres1~7; [L522] havoc is_transmit7_triggered_~__retres1~7; [L525-L534] assume !(1 == ~t7_pc~0); [L535] is_transmit7_triggered_~__retres1~7 := 0; [L537] is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; [L1079] activate_threads_#t~ret17 := is_transmit7_triggered_#res; [L1079] activate_threads_~tmp___6~0 := activate_threads_#t~ret17; [L1079] havoc activate_threads_#t~ret17; [L1081-L1085] assume !(0 != activate_threads_~tmp___6~0); [L1087] havoc is_transmit8_triggered_#res; [L1087] havoc is_transmit8_triggered_~__retres1~8; [L541] havoc is_transmit8_triggered_~__retres1~8; [L544-L553] assume !(1 == ~t8_pc~0); [L554] is_transmit8_triggered_~__retres1~8 := 0; [L556] is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; [L1087] activate_threads_#t~ret18 := is_transmit8_triggered_#res; [L1087] activate_threads_~tmp___7~0 := activate_threads_#t~ret18; [L1087] havoc activate_threads_#t~ret18; [L1089-L1093] assume !(0 != activate_threads_~tmp___7~0); [L921-L925] assume !(1 == ~M_E~0); [L926-L930] assume !(1 == ~T1_E~0); [L931-L935] assume !(1 == ~T2_E~0); [L936-L940] assume !(1 == ~T3_E~0); [L941-L945] assume !(1 == ~T4_E~0); [L946-L950] assume !(1 == ~T5_E~0); [L951-L955] assume !(1 == ~T6_E~0); [L956-L960] assume !(1 == ~T7_E~0); [L961-L965] assume !(1 == ~T8_E~0); [L966-L970] assume !(1 == ~E_1~0); [L971-L975] assume !(1 == ~E_2~0); [L976-L980] assume !(1 == ~E_3~0); [L981-L985] assume !(1 == ~E_4~0); [L986-L990] assume !(1 == ~E_5~0); [L991-L995] assume !(1 == ~E_6~0); [L996-L1000] assume !(1 == ~E_7~0); [L1001-L1005] assume !(1 == ~E_8~0); [L1262-L1299] assume !false; [L1265] start_simulation_~kernel_st~0 := 1; [L1266] havoc eval_#t~ret0, eval_#t~nondet1, eval_~tmp_ndt_1~0, eval_#t~nondet2, eval_~tmp_ndt_2~0, eval_#t~nondet3, eval_~tmp_ndt_3~0, eval_#t~nondet4, eval_~tmp_ndt_4~0, eval_#t~nondet5, eval_~tmp_ndt_5~0, eval_#t~nondet6, eval_~tmp_ndt_6~0, eval_#t~nondet7, eval_~tmp_ndt_7~0, eval_#t~nondet8, eval_~tmp_ndt_8~0, eval_#t~nondet9, eval_~tmp_ndt_9~0, eval_~tmp~0; [L677] havoc eval_~tmp~0; ----- ----- class de.uni_freiburg.informatik.ultimate.boogie.preprocessor.BoogiePreprocessorBacktranslator [L15] ~m_pc~0 := 0; [L16] ~t1_pc~0 := 0; [L17] ~t2_pc~0 := 0; [L18] ~t3_pc~0 := 0; [L19] ~t4_pc~0 := 0; [L20] ~t5_pc~0 := 0; [L21] ~t6_pc~0 := 0; [L22] ~t7_pc~0 := 0; [L23] ~t8_pc~0 := 0; [L24] ~m_st~0 := 0; [L25] ~t1_st~0 := 0; [L26] ~t2_st~0 := 0; [L27] ~t3_st~0 := 0; [L28] ~t4_st~0 := 0; [L29] ~t5_st~0 := 0; [L30] ~t6_st~0 := 0; [L31] ~t7_st~0 := 0; [L32] ~t8_st~0 := 0; [L33] ~m_i~0 := 0; [L34] ~t1_i~0 := 0; [L35] ~t2_i~0 := 0; [L36] ~t3_i~0 := 0; [L37] ~t4_i~0 := 0; [L38] ~t5_i~0 := 0; [L39] ~t6_i~0 := 0; [L40] ~t7_i~0 := 0; [L41] ~t8_i~0 := 0; [L42] ~M_E~0 := 2; [L43] ~T1_E~0 := 2; [L44] ~T2_E~0 := 2; [L45] ~T3_E~0 := 2; [L46] ~T4_E~0 := 2; [L47] ~T5_E~0 := 2; [L48] ~T6_E~0 := 2; [L49] ~T7_E~0 := 2; [L50] ~T8_E~0 := 2; [L51] ~E_1~0 := 2; [L52] ~E_2~0 := 2; [L53] ~E_3~0 := 2; [L54] ~E_4~0 := 2; [L55] ~E_5~0 := 2; [L56] ~E_6~0 := 2; [L57] ~E_7~0 := 2; [L58] ~E_8~0 := 2; [?] havoc main_#res; [?] havoc main_~__retres1~10; [L1307] havoc main_~__retres1~10; [L1215] ~m_i~0 := 1; [L1216] ~t1_i~0 := 1; [L1217] ~t2_i~0 := 1; [L1218] ~t3_i~0 := 1; [L1219] ~t4_i~0 := 1; [L1220] ~t5_i~0 := 1; [L1221] ~t6_i~0 := 1; [L1222] ~t7_i~0 := 1; [L1223] ~t8_i~0 := 1; [L1312] havoc start_simulation_#t~ret20, start_simulation_#t~ret21, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1; [L1248] havoc start_simulation_~kernel_st~0; [L1249] havoc start_simulation_~tmp~3; [L1250] havoc start_simulation_~tmp___0~1; [L1254] start_simulation_~kernel_st~0 := 0; [L571-L575] assume 1 == ~m_i~0; [L572] ~m_st~0 := 0; [L576-L580] assume 1 == ~t1_i~0; [L577] ~t1_st~0 := 0; [L581-L585] assume 1 == ~t2_i~0; [L582] ~t2_st~0 := 0; [L586-L590] assume 1 == ~t3_i~0; [L587] ~t3_st~0 := 0; [L591-L595] assume 1 == ~t4_i~0; [L592] ~t4_st~0 := 0; [L596-L600] assume 1 == ~t5_i~0; [L597] ~t5_st~0 := 0; [L601-L605] assume 1 == ~t6_i~0; [L602] ~t6_st~0 := 0; [L606-L610] assume 1 == ~t7_i~0; [L607] ~t7_st~0 := 0; [L611-L615] assume 1 == ~t8_i~0; [L612] ~t8_st~0 := 0; [L828-L832] assume !(0 == ~M_E~0); [L833-L837] assume !(0 == ~T1_E~0); [L838-L842] assume !(0 == ~T2_E~0); [L843-L847] assume !(0 == ~T3_E~0); [L848-L852] assume !(0 == ~T4_E~0); [L853-L857] assume !(0 == ~T5_E~0); [L858-L862] assume !(0 == ~T6_E~0); [L863-L867] assume !(0 == ~T7_E~0); [L868-L872] assume !(0 == ~T8_E~0); [L873-L877] assume !(0 == ~E_1~0); [L878-L882] assume !(0 == ~E_2~0); [L883-L887] assume !(0 == ~E_3~0); [L888-L892] assume !(0 == ~E_4~0); [L893-L897] assume !(0 == ~E_5~0); [L898-L902] assume !(0 == ~E_6~0); [L903-L907] assume !(0 == ~E_7~0); [L908-L912] assume !(0 == ~E_8~0); [L1258] havoc activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0; [L1011] havoc activate_threads_~tmp~1; [L1012] havoc activate_threads_~tmp___0~0; [L1013] havoc activate_threads_~tmp___1~0; [L1014] havoc activate_threads_~tmp___2~0; [L1015] havoc activate_threads_~tmp___3~0; [L1016] havoc activate_threads_~tmp___4~0; [L1017] havoc activate_threads_~tmp___5~0; [L1018] havoc activate_threads_~tmp___6~0; [L1019] havoc activate_threads_~tmp___7~0; [L1023] havoc is_master_triggered_#res; [L1023] havoc is_master_triggered_~__retres1~0; [L389] havoc is_master_triggered_~__retres1~0; [L392-L401] assume !(1 == ~m_pc~0); [L402] is_master_triggered_~__retres1~0 := 0; [L404] is_master_triggered_#res := is_master_triggered_~__retres1~0; [L1023] activate_threads_#t~ret10 := is_master_triggered_#res; [L1023] activate_threads_~tmp~1 := activate_threads_#t~ret10; [L1023] havoc activate_threads_#t~ret10; [L1025-L1029] assume !(0 != activate_threads_~tmp~1); [L1031] havoc is_transmit1_triggered_#res; [L1031] havoc is_transmit1_triggered_~__retres1~1; [L408] havoc is_transmit1_triggered_~__retres1~1; [L411-L420] assume !(1 == ~t1_pc~0); [L421] is_transmit1_triggered_~__retres1~1 := 0; [L423] is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; [L1031] activate_threads_#t~ret11 := is_transmit1_triggered_#res; [L1031] activate_threads_~tmp___0~0 := activate_threads_#t~ret11; [L1031] havoc activate_threads_#t~ret11; [L1033-L1037] assume !(0 != activate_threads_~tmp___0~0); [L1039] havoc is_transmit2_triggered_#res; [L1039] havoc is_transmit2_triggered_~__retres1~2; [L427] havoc is_transmit2_triggered_~__retres1~2; [L430-L439] assume !(1 == ~t2_pc~0); [L440] is_transmit2_triggered_~__retres1~2 := 0; [L442] is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; [L1039] activate_threads_#t~ret12 := is_transmit2_triggered_#res; [L1039] activate_threads_~tmp___1~0 := activate_threads_#t~ret12; [L1039] havoc activate_threads_#t~ret12; [L1041-L1045] assume !(0 != activate_threads_~tmp___1~0); [L1047] havoc is_transmit3_triggered_#res; [L1047] havoc is_transmit3_triggered_~__retres1~3; [L446] havoc is_transmit3_triggered_~__retres1~3; [L449-L458] assume !(1 == ~t3_pc~0); [L459] is_transmit3_triggered_~__retres1~3 := 0; [L461] is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; [L1047] activate_threads_#t~ret13 := is_transmit3_triggered_#res; [L1047] activate_threads_~tmp___2~0 := activate_threads_#t~ret13; [L1047] havoc activate_threads_#t~ret13; [L1049-L1053] assume !(0 != activate_threads_~tmp___2~0); [L1055] havoc is_transmit4_triggered_#res; [L1055] havoc is_transmit4_triggered_~__retres1~4; [L465] havoc is_transmit4_triggered_~__retres1~4; [L468-L477] assume !(1 == ~t4_pc~0); [L478] is_transmit4_triggered_~__retres1~4 := 0; [L480] is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; [L1055] activate_threads_#t~ret14 := is_transmit4_triggered_#res; [L1055] activate_threads_~tmp___3~0 := activate_threads_#t~ret14; [L1055] havoc activate_threads_#t~ret14; [L1057-L1061] assume !(0 != activate_threads_~tmp___3~0); [L1063] havoc is_transmit5_triggered_#res; [L1063] havoc is_transmit5_triggered_~__retres1~5; [L484] havoc is_transmit5_triggered_~__retres1~5; [L487-L496] assume !(1 == ~t5_pc~0); [L497] is_transmit5_triggered_~__retres1~5 := 0; [L499] is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; [L1063] activate_threads_#t~ret15 := is_transmit5_triggered_#res; [L1063] activate_threads_~tmp___4~0 := activate_threads_#t~ret15; [L1063] havoc activate_threads_#t~ret15; [L1065-L1069] assume !(0 != activate_threads_~tmp___4~0); [L1071] havoc is_transmit6_triggered_#res; [L1071] havoc is_transmit6_triggered_~__retres1~6; [L503] havoc is_transmit6_triggered_~__retres1~6; [L506-L515] assume !(1 == ~t6_pc~0); [L516] is_transmit6_triggered_~__retres1~6 := 0; [L518] is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; [L1071] activate_threads_#t~ret16 := is_transmit6_triggered_#res; [L1071] activate_threads_~tmp___5~0 := activate_threads_#t~ret16; [L1071] havoc activate_threads_#t~ret16; [L1073-L1077] assume !(0 != activate_threads_~tmp___5~0); [L1079] havoc is_transmit7_triggered_#res; [L1079] havoc is_transmit7_triggered_~__retres1~7; [L522] havoc is_transmit7_triggered_~__retres1~7; [L525-L534] assume !(1 == ~t7_pc~0); [L535] is_transmit7_triggered_~__retres1~7 := 0; [L537] is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; [L1079] activate_threads_#t~ret17 := is_transmit7_triggered_#res; [L1079] activate_threads_~tmp___6~0 := activate_threads_#t~ret17; [L1079] havoc activate_threads_#t~ret17; [L1081-L1085] assume !(0 != activate_threads_~tmp___6~0); [L1087] havoc is_transmit8_triggered_#res; [L1087] havoc is_transmit8_triggered_~__retres1~8; [L541] havoc is_transmit8_triggered_~__retres1~8; [L544-L553] assume !(1 == ~t8_pc~0); [L554] is_transmit8_triggered_~__retres1~8 := 0; [L556] is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; [L1087] activate_threads_#t~ret18 := is_transmit8_triggered_#res; [L1087] activate_threads_~tmp___7~0 := activate_threads_#t~ret18; [L1087] havoc activate_threads_#t~ret18; [L1089-L1093] assume !(0 != activate_threads_~tmp___7~0); [L921-L925] assume !(1 == ~M_E~0); [L926-L930] assume !(1 == ~T1_E~0); [L931-L935] assume !(1 == ~T2_E~0); [L936-L940] assume !(1 == ~T3_E~0); [L941-L945] assume !(1 == ~T4_E~0); [L946-L950] assume !(1 == ~T5_E~0); [L951-L955] assume !(1 == ~T6_E~0); [L956-L960] assume !(1 == ~T7_E~0); [L961-L965] assume !(1 == ~T8_E~0); [L966-L970] assume !(1 == ~E_1~0); [L971-L975] assume !(1 == ~E_2~0); [L976-L980] assume !(1 == ~E_3~0); [L981-L985] assume !(1 == ~E_4~0); [L986-L990] assume !(1 == ~E_5~0); [L991-L995] assume !(1 == ~E_6~0); [L996-L1000] assume !(1 == ~E_7~0); [L1001-L1005] assume !(1 == ~E_8~0); [L1262-L1299] assume !false; [L1265] start_simulation_~kernel_st~0 := 1; [L1266] havoc eval_#t~ret0, eval_#t~nondet1, eval_~tmp_ndt_1~0, eval_#t~nondet2, eval_~tmp_ndt_2~0, eval_#t~nondet3, eval_~tmp_ndt_3~0, eval_#t~nondet4, eval_~tmp_ndt_4~0, eval_#t~nondet5, eval_~tmp_ndt_5~0, eval_#t~nondet6, eval_~tmp_ndt_6~0, eval_#t~nondet7, eval_~tmp_ndt_7~0, eval_#t~nondet8, eval_~tmp_ndt_8~0, eval_#t~nondet9, eval_~tmp_ndt_9~0, eval_~tmp~0; [L677] havoc eval_~tmp~0; [L15] ~m_pc~0 := 0; [L16] ~t1_pc~0 := 0; [L17] ~t2_pc~0 := 0; [L18] ~t3_pc~0 := 0; [L19] ~t4_pc~0 := 0; [L20] ~t5_pc~0 := 0; [L21] ~t6_pc~0 := 0; [L22] ~t7_pc~0 := 0; [L23] ~t8_pc~0 := 0; [L24] ~m_st~0 := 0; [L25] ~t1_st~0 := 0; [L26] ~t2_st~0 := 0; [L27] ~t3_st~0 := 0; [L28] ~t4_st~0 := 0; [L29] ~t5_st~0 := 0; [L30] ~t6_st~0 := 0; [L31] ~t7_st~0 := 0; [L32] ~t8_st~0 := 0; [L33] ~m_i~0 := 0; [L34] ~t1_i~0 := 0; [L35] ~t2_i~0 := 0; [L36] ~t3_i~0 := 0; [L37] ~t4_i~0 := 0; [L38] ~t5_i~0 := 0; [L39] ~t6_i~0 := 0; [L40] ~t7_i~0 := 0; [L41] ~t8_i~0 := 0; [L42] ~M_E~0 := 2; [L43] ~T1_E~0 := 2; [L44] ~T2_E~0 := 2; [L45] ~T3_E~0 := 2; [L46] ~T4_E~0 := 2; [L47] ~T5_E~0 := 2; [L48] ~T6_E~0 := 2; [L49] ~T7_E~0 := 2; [L50] ~T8_E~0 := 2; [L51] ~E_1~0 := 2; [L52] ~E_2~0 := 2; [L53] ~E_3~0 := 2; [L54] ~E_4~0 := 2; [L55] ~E_5~0 := 2; [L56] ~E_6~0 := 2; [L57] ~E_7~0 := 2; [L58] ~E_8~0 := 2; [?] havoc main_#res; [?] havoc main_~__retres1~10; [L1307] havoc main_~__retres1~10; [L1215] ~m_i~0 := 1; [L1216] ~t1_i~0 := 1; [L1217] ~t2_i~0 := 1; [L1218] ~t3_i~0 := 1; [L1219] ~t4_i~0 := 1; [L1220] ~t5_i~0 := 1; [L1221] ~t6_i~0 := 1; [L1222] ~t7_i~0 := 1; [L1223] ~t8_i~0 := 1; [L1312] havoc start_simulation_#t~ret20, start_simulation_#t~ret21, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1; [L1248] havoc start_simulation_~kernel_st~0; [L1249] havoc start_simulation_~tmp~3; [L1250] havoc start_simulation_~tmp___0~1; [L1254] start_simulation_~kernel_st~0 := 0; [L571] COND TRUE 1 == ~m_i~0 [L572] ~m_st~0 := 0; [L576] COND TRUE 1 == ~t1_i~0 [L577] ~t1_st~0 := 0; [L581] COND TRUE 1 == ~t2_i~0 [L582] ~t2_st~0 := 0; [L586] COND TRUE 1 == ~t3_i~0 [L587] ~t3_st~0 := 0; [L591] COND TRUE 1 == ~t4_i~0 [L592] ~t4_st~0 := 0; [L596] COND TRUE 1 == ~t5_i~0 [L597] ~t5_st~0 := 0; [L601] COND TRUE 1 == ~t6_i~0 [L602] ~t6_st~0 := 0; [L606] COND TRUE 1 == ~t7_i~0 [L607] ~t7_st~0 := 0; [L611] COND TRUE 1 == ~t8_i~0 [L612] ~t8_st~0 := 0; [L828] COND FALSE !(0 == ~M_E~0) [L833] COND FALSE !(0 == ~T1_E~0) [L838] COND FALSE !(0 == ~T2_E~0) [L843] COND FALSE !(0 == ~T3_E~0) [L848] COND FALSE !(0 == ~T4_E~0) [L853] COND FALSE !(0 == ~T5_E~0) [L858] COND FALSE !(0 == ~T6_E~0) [L863] COND FALSE !(0 == ~T7_E~0) [L868] COND FALSE !(0 == ~T8_E~0) [L873] COND FALSE !(0 == ~E_1~0) [L878] COND FALSE !(0 == ~E_2~0) [L883] COND FALSE !(0 == ~E_3~0) [L888] COND FALSE !(0 == ~E_4~0) [L893] COND FALSE !(0 == ~E_5~0) [L898] COND FALSE !(0 == ~E_6~0) [L903] COND FALSE !(0 == ~E_7~0) [L908] COND FALSE !(0 == ~E_8~0) [L1258] havoc activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0; [L1011] havoc activate_threads_~tmp~1; [L1012] havoc activate_threads_~tmp___0~0; [L1013] havoc activate_threads_~tmp___1~0; [L1014] havoc activate_threads_~tmp___2~0; [L1015] havoc activate_threads_~tmp___3~0; [L1016] havoc activate_threads_~tmp___4~0; [L1017] havoc activate_threads_~tmp___5~0; [L1018] havoc activate_threads_~tmp___6~0; [L1019] havoc activate_threads_~tmp___7~0; [L1023] havoc is_master_triggered_#res; [L1023] havoc is_master_triggered_~__retres1~0; [L389] havoc is_master_triggered_~__retres1~0; [L392] COND FALSE !(1 == ~m_pc~0) [L402] is_master_triggered_~__retres1~0 := 0; [L404] is_master_triggered_#res := is_master_triggered_~__retres1~0; [L1023] activate_threads_#t~ret10 := is_master_triggered_#res; [L1023] activate_threads_~tmp~1 := activate_threads_#t~ret10; [L1023] havoc activate_threads_#t~ret10; [L1025-L1029] COND FALSE !(0 != activate_threads_~tmp~1) [L1031] havoc is_transmit1_triggered_#res; [L1031] havoc is_transmit1_triggered_~__retres1~1; [L408] havoc is_transmit1_triggered_~__retres1~1; [L411] COND FALSE !(1 == ~t1_pc~0) [L421] is_transmit1_triggered_~__retres1~1 := 0; [L423] is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; [L1031] activate_threads_#t~ret11 := is_transmit1_triggered_#res; [L1031] activate_threads_~tmp___0~0 := activate_threads_#t~ret11; [L1031] havoc activate_threads_#t~ret11; [L1033-L1037] COND FALSE !(0 != activate_threads_~tmp___0~0) [L1039] havoc is_transmit2_triggered_#res; [L1039] havoc is_transmit2_triggered_~__retres1~2; [L427] havoc is_transmit2_triggered_~__retres1~2; [L430] COND FALSE !(1 == ~t2_pc~0) [L440] is_transmit2_triggered_~__retres1~2 := 0; [L442] is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; [L1039] activate_threads_#t~ret12 := is_transmit2_triggered_#res; [L1039] activate_threads_~tmp___1~0 := activate_threads_#t~ret12; [L1039] havoc activate_threads_#t~ret12; [L1041-L1045] COND FALSE !(0 != activate_threads_~tmp___1~0) [L1047] havoc is_transmit3_triggered_#res; [L1047] havoc is_transmit3_triggered_~__retres1~3; [L446] havoc is_transmit3_triggered_~__retres1~3; [L449] COND FALSE !(1 == ~t3_pc~0) [L459] is_transmit3_triggered_~__retres1~3 := 0; [L461] is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; [L1047] activate_threads_#t~ret13 := is_transmit3_triggered_#res; [L1047] activate_threads_~tmp___2~0 := activate_threads_#t~ret13; [L1047] havoc activate_threads_#t~ret13; [L1049-L1053] COND FALSE !(0 != activate_threads_~tmp___2~0) [L1055] havoc is_transmit4_triggered_#res; [L1055] havoc is_transmit4_triggered_~__retres1~4; [L465] havoc is_transmit4_triggered_~__retres1~4; [L468] COND FALSE !(1 == ~t4_pc~0) [L478] is_transmit4_triggered_~__retres1~4 := 0; [L480] is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; [L1055] activate_threads_#t~ret14 := is_transmit4_triggered_#res; [L1055] activate_threads_~tmp___3~0 := activate_threads_#t~ret14; [L1055] havoc activate_threads_#t~ret14; [L1057-L1061] COND FALSE !(0 != activate_threads_~tmp___3~0) [L1063] havoc is_transmit5_triggered_#res; [L1063] havoc is_transmit5_triggered_~__retres1~5; [L484] havoc is_transmit5_triggered_~__retres1~5; [L487] COND FALSE !(1 == ~t5_pc~0) [L497] is_transmit5_triggered_~__retres1~5 := 0; [L499] is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; [L1063] activate_threads_#t~ret15 := is_transmit5_triggered_#res; [L1063] activate_threads_~tmp___4~0 := activate_threads_#t~ret15; [L1063] havoc activate_threads_#t~ret15; [L1065-L1069] COND FALSE !(0 != activate_threads_~tmp___4~0) [L1071] havoc is_transmit6_triggered_#res; [L1071] havoc is_transmit6_triggered_~__retres1~6; [L503] havoc is_transmit6_triggered_~__retres1~6; [L506] COND FALSE !(1 == ~t6_pc~0) [L516] is_transmit6_triggered_~__retres1~6 := 0; [L518] is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; [L1071] activate_threads_#t~ret16 := is_transmit6_triggered_#res; [L1071] activate_threads_~tmp___5~0 := activate_threads_#t~ret16; [L1071] havoc activate_threads_#t~ret16; [L1073-L1077] COND FALSE !(0 != activate_threads_~tmp___5~0) [L1079] havoc is_transmit7_triggered_#res; [L1079] havoc is_transmit7_triggered_~__retres1~7; [L522] havoc is_transmit7_triggered_~__retres1~7; [L525] COND FALSE !(1 == ~t7_pc~0) [L535] is_transmit7_triggered_~__retres1~7 := 0; [L537] is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; [L1079] activate_threads_#t~ret17 := is_transmit7_triggered_#res; [L1079] activate_threads_~tmp___6~0 := activate_threads_#t~ret17; [L1079] havoc activate_threads_#t~ret17; [L1081-L1085] COND FALSE !(0 != activate_threads_~tmp___6~0) [L1087] havoc is_transmit8_triggered_#res; [L1087] havoc is_transmit8_triggered_~__retres1~8; [L541] havoc is_transmit8_triggered_~__retres1~8; [L544] COND FALSE !(1 == ~t8_pc~0) [L554] is_transmit8_triggered_~__retres1~8 := 0; [L556] is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; [L1087] activate_threads_#t~ret18 := is_transmit8_triggered_#res; [L1087] activate_threads_~tmp___7~0 := activate_threads_#t~ret18; [L1087] havoc activate_threads_#t~ret18; [L1089-L1093] COND FALSE !(0 != activate_threads_~tmp___7~0) [L921] COND FALSE !(1 == ~M_E~0) [L926] COND FALSE !(1 == ~T1_E~0) [L931] COND FALSE !(1 == ~T2_E~0) [L936] COND FALSE !(1 == ~T3_E~0) [L941] COND FALSE !(1 == ~T4_E~0) [L946] COND FALSE !(1 == ~T5_E~0) [L951] COND FALSE !(1 == ~T6_E~0) [L956] COND FALSE !(1 == ~T7_E~0) [L961] COND FALSE !(1 == ~T8_E~0) [L966] COND FALSE !(1 == ~E_1~0) [L971] COND FALSE !(1 == ~E_2~0) [L976] COND FALSE !(1 == ~E_3~0) [L981] COND FALSE !(1 == ~E_4~0) [L986] COND FALSE !(1 == ~E_5~0) [L991] COND FALSE !(1 == ~E_6~0) [L996] COND FALSE !(1 == ~E_7~0) [L1001] COND FALSE !(1 == ~E_8~0) [L1262-L1299] COND FALSE !(false) [L1265] start_simulation_~kernel_st~0 := 1; [L1266] havoc eval_#t~ret0, eval_#t~nondet1, eval_~tmp_ndt_1~0, eval_#t~nondet2, eval_~tmp_ndt_2~0, eval_#t~nondet3, eval_~tmp_ndt_3~0, eval_#t~nondet4, eval_~tmp_ndt_4~0, eval_#t~nondet5, eval_~tmp_ndt_5~0, eval_#t~nondet6, eval_~tmp_ndt_6~0, eval_#t~nondet7, eval_~tmp_ndt_7~0, eval_#t~nondet8, eval_~tmp_ndt_8~0, eval_#t~nondet9, eval_~tmp_ndt_9~0, eval_~tmp~0; [L677] havoc eval_~tmp~0; ----- ----- class de.uni_freiburg.informatik.ultimate.boogie.procedureinliner.backtranslation.InlinerBacktranslator [L15] ~m_pc~0 := 0; [L16] ~t1_pc~0 := 0; [L17] ~t2_pc~0 := 0; [L18] ~t3_pc~0 := 0; [L19] ~t4_pc~0 := 0; [L20] ~t5_pc~0 := 0; [L21] ~t6_pc~0 := 0; [L22] ~t7_pc~0 := 0; [L23] ~t8_pc~0 := 0; [L24] ~m_st~0 := 0; [L25] ~t1_st~0 := 0; [L26] ~t2_st~0 := 0; [L27] ~t3_st~0 := 0; [L28] ~t4_st~0 := 0; [L29] ~t5_st~0 := 0; [L30] ~t6_st~0 := 0; [L31] ~t7_st~0 := 0; [L32] ~t8_st~0 := 0; [L33] ~m_i~0 := 0; [L34] ~t1_i~0 := 0; [L35] ~t2_i~0 := 0; [L36] ~t3_i~0 := 0; [L37] ~t4_i~0 := 0; [L38] ~t5_i~0 := 0; [L39] ~t6_i~0 := 0; [L40] ~t7_i~0 := 0; [L41] ~t8_i~0 := 0; [L42] ~M_E~0 := 2; [L43] ~T1_E~0 := 2; [L44] ~T2_E~0 := 2; [L45] ~T3_E~0 := 2; [L46] ~T4_E~0 := 2; [L47] ~T5_E~0 := 2; [L48] ~T6_E~0 := 2; [L49] ~T7_E~0 := 2; [L50] ~T8_E~0 := 2; [L51] ~E_1~0 := 2; [L52] ~E_2~0 := 2; [L53] ~E_3~0 := 2; [L54] ~E_4~0 := 2; [L55] ~E_5~0 := 2; [L56] ~E_6~0 := 2; [L57] ~E_7~0 := 2; [L58] ~E_8~0 := 2; [?] havoc main_#res; [?] havoc main_~__retres1~10; [L1307] havoc main_~__retres1~10; [L1215] ~m_i~0 := 1; [L1216] ~t1_i~0 := 1; [L1217] ~t2_i~0 := 1; [L1218] ~t3_i~0 := 1; [L1219] ~t4_i~0 := 1; [L1220] ~t5_i~0 := 1; [L1221] ~t6_i~0 := 1; [L1222] ~t7_i~0 := 1; [L1223] ~t8_i~0 := 1; [L1312] havoc start_simulation_#t~ret20, start_simulation_#t~ret21, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1; [L1248] havoc start_simulation_~kernel_st~0; [L1249] havoc start_simulation_~tmp~3; [L1250] havoc start_simulation_~tmp___0~1; [L1254] start_simulation_~kernel_st~0 := 0; [L571] COND TRUE 1 == ~m_i~0 [L572] ~m_st~0 := 0; [L576] COND TRUE 1 == ~t1_i~0 [L577] ~t1_st~0 := 0; [L581] COND TRUE 1 == ~t2_i~0 [L582] ~t2_st~0 := 0; [L586] COND TRUE 1 == ~t3_i~0 [L587] ~t3_st~0 := 0; [L591] COND TRUE 1 == ~t4_i~0 [L592] ~t4_st~0 := 0; [L596] COND TRUE 1 == ~t5_i~0 [L597] ~t5_st~0 := 0; [L601] COND TRUE 1 == ~t6_i~0 [L602] ~t6_st~0 := 0; [L606] COND TRUE 1 == ~t7_i~0 [L607] ~t7_st~0 := 0; [L611] COND TRUE 1 == ~t8_i~0 [L612] ~t8_st~0 := 0; [L828] COND FALSE !(0 == ~M_E~0) [L833] COND FALSE !(0 == ~T1_E~0) [L838] COND FALSE !(0 == ~T2_E~0) [L843] COND FALSE !(0 == ~T3_E~0) [L848] COND FALSE !(0 == ~T4_E~0) [L853] COND FALSE !(0 == ~T5_E~0) [L858] COND FALSE !(0 == ~T6_E~0) [L863] COND FALSE !(0 == ~T7_E~0) [L868] COND FALSE !(0 == ~T8_E~0) [L873] COND FALSE !(0 == ~E_1~0) [L878] COND FALSE !(0 == ~E_2~0) [L883] COND FALSE !(0 == ~E_3~0) [L888] COND FALSE !(0 == ~E_4~0) [L893] COND FALSE !(0 == ~E_5~0) [L898] COND FALSE !(0 == ~E_6~0) [L903] COND FALSE !(0 == ~E_7~0) [L908] COND FALSE !(0 == ~E_8~0) [L1258] havoc activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0; [L1011] havoc activate_threads_~tmp~1; [L1012] havoc activate_threads_~tmp___0~0; [L1013] havoc activate_threads_~tmp___1~0; [L1014] havoc activate_threads_~tmp___2~0; [L1015] havoc activate_threads_~tmp___3~0; [L1016] havoc activate_threads_~tmp___4~0; [L1017] havoc activate_threads_~tmp___5~0; [L1018] havoc activate_threads_~tmp___6~0; [L1019] havoc activate_threads_~tmp___7~0; [L1023] havoc is_master_triggered_#res; [L1023] havoc is_master_triggered_~__retres1~0; [L389] havoc is_master_triggered_~__retres1~0; [L392] COND FALSE !(1 == ~m_pc~0) [L402] is_master_triggered_~__retres1~0 := 0; [L404] is_master_triggered_#res := is_master_triggered_~__retres1~0; [L1023] activate_threads_#t~ret10 := is_master_triggered_#res; [L1023] activate_threads_~tmp~1 := activate_threads_#t~ret10; [L1023] havoc activate_threads_#t~ret10; [L1025-L1029] COND FALSE !(0 != activate_threads_~tmp~1) [L1031] havoc is_transmit1_triggered_#res; [L1031] havoc is_transmit1_triggered_~__retres1~1; [L408] havoc is_transmit1_triggered_~__retres1~1; [L411] COND FALSE !(1 == ~t1_pc~0) [L421] is_transmit1_triggered_~__retres1~1 := 0; [L423] is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; [L1031] activate_threads_#t~ret11 := is_transmit1_triggered_#res; [L1031] activate_threads_~tmp___0~0 := activate_threads_#t~ret11; [L1031] havoc activate_threads_#t~ret11; [L1033-L1037] COND FALSE !(0 != activate_threads_~tmp___0~0) [L1039] havoc is_transmit2_triggered_#res; [L1039] havoc is_transmit2_triggered_~__retres1~2; [L427] havoc is_transmit2_triggered_~__retres1~2; [L430] COND FALSE !(1 == ~t2_pc~0) [L440] is_transmit2_triggered_~__retres1~2 := 0; [L442] is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; [L1039] activate_threads_#t~ret12 := is_transmit2_triggered_#res; [L1039] activate_threads_~tmp___1~0 := activate_threads_#t~ret12; [L1039] havoc activate_threads_#t~ret12; [L1041-L1045] COND FALSE !(0 != activate_threads_~tmp___1~0) [L1047] havoc is_transmit3_triggered_#res; [L1047] havoc is_transmit3_triggered_~__retres1~3; [L446] havoc is_transmit3_triggered_~__retres1~3; [L449] COND FALSE !(1 == ~t3_pc~0) [L459] is_transmit3_triggered_~__retres1~3 := 0; [L461] is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; [L1047] activate_threads_#t~ret13 := is_transmit3_triggered_#res; [L1047] activate_threads_~tmp___2~0 := activate_threads_#t~ret13; [L1047] havoc activate_threads_#t~ret13; [L1049-L1053] COND FALSE !(0 != activate_threads_~tmp___2~0) [L1055] havoc is_transmit4_triggered_#res; [L1055] havoc is_transmit4_triggered_~__retres1~4; [L465] havoc is_transmit4_triggered_~__retres1~4; [L468] COND FALSE !(1 == ~t4_pc~0) [L478] is_transmit4_triggered_~__retres1~4 := 0; [L480] is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; [L1055] activate_threads_#t~ret14 := is_transmit4_triggered_#res; [L1055] activate_threads_~tmp___3~0 := activate_threads_#t~ret14; [L1055] havoc activate_threads_#t~ret14; [L1057-L1061] COND FALSE !(0 != activate_threads_~tmp___3~0) [L1063] havoc is_transmit5_triggered_#res; [L1063] havoc is_transmit5_triggered_~__retres1~5; [L484] havoc is_transmit5_triggered_~__retres1~5; [L487] COND FALSE !(1 == ~t5_pc~0) [L497] is_transmit5_triggered_~__retres1~5 := 0; [L499] is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; [L1063] activate_threads_#t~ret15 := is_transmit5_triggered_#res; [L1063] activate_threads_~tmp___4~0 := activate_threads_#t~ret15; [L1063] havoc activate_threads_#t~ret15; [L1065-L1069] COND FALSE !(0 != activate_threads_~tmp___4~0) [L1071] havoc is_transmit6_triggered_#res; [L1071] havoc is_transmit6_triggered_~__retres1~6; [L503] havoc is_transmit6_triggered_~__retres1~6; [L506] COND FALSE !(1 == ~t6_pc~0) [L516] is_transmit6_triggered_~__retres1~6 := 0; [L518] is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; [L1071] activate_threads_#t~ret16 := is_transmit6_triggered_#res; [L1071] activate_threads_~tmp___5~0 := activate_threads_#t~ret16; [L1071] havoc activate_threads_#t~ret16; [L1073-L1077] COND FALSE !(0 != activate_threads_~tmp___5~0) [L1079] havoc is_transmit7_triggered_#res; [L1079] havoc is_transmit7_triggered_~__retres1~7; [L522] havoc is_transmit7_triggered_~__retres1~7; [L525] COND FALSE !(1 == ~t7_pc~0) [L535] is_transmit7_triggered_~__retres1~7 := 0; [L537] is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; [L1079] activate_threads_#t~ret17 := is_transmit7_triggered_#res; [L1079] activate_threads_~tmp___6~0 := activate_threads_#t~ret17; [L1079] havoc activate_threads_#t~ret17; [L1081-L1085] COND FALSE !(0 != activate_threads_~tmp___6~0) [L1087] havoc is_transmit8_triggered_#res; [L1087] havoc is_transmit8_triggered_~__retres1~8; [L541] havoc is_transmit8_triggered_~__retres1~8; [L544] COND FALSE !(1 == ~t8_pc~0) [L554] is_transmit8_triggered_~__retres1~8 := 0; [L556] is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; [L1087] activate_threads_#t~ret18 := is_transmit8_triggered_#res; [L1087] activate_threads_~tmp___7~0 := activate_threads_#t~ret18; [L1087] havoc activate_threads_#t~ret18; [L1089-L1093] COND FALSE !(0 != activate_threads_~tmp___7~0) [L921] COND FALSE !(1 == ~M_E~0) [L926] COND FALSE !(1 == ~T1_E~0) [L931] COND FALSE !(1 == ~T2_E~0) [L936] COND FALSE !(1 == ~T3_E~0) [L941] COND FALSE !(1 == ~T4_E~0) [L946] COND FALSE !(1 == ~T5_E~0) [L951] COND FALSE !(1 == ~T6_E~0) [L956] COND FALSE !(1 == ~T7_E~0) [L961] COND FALSE !(1 == ~T8_E~0) [L966] COND FALSE !(1 == ~E_1~0) [L971] COND FALSE !(1 == ~E_2~0) [L976] COND FALSE !(1 == ~E_3~0) [L981] COND FALSE !(1 == ~E_4~0) [L986] COND FALSE !(1 == ~E_5~0) [L991] COND FALSE !(1 == ~E_6~0) [L996] COND FALSE !(1 == ~E_7~0) [L1001] COND FALSE !(1 == ~E_8~0) [L1262-L1299] COND FALSE !(false) [L1265] start_simulation_~kernel_st~0 := 1; [L1266] havoc eval_#t~ret0, eval_#t~nondet1, eval_~tmp_ndt_1~0, eval_#t~nondet2, eval_~tmp_ndt_2~0, eval_#t~nondet3, eval_~tmp_ndt_3~0, eval_#t~nondet4, eval_~tmp_ndt_4~0, eval_#t~nondet5, eval_~tmp_ndt_5~0, eval_#t~nondet6, eval_~tmp_ndt_6~0, eval_#t~nondet7, eval_~tmp_ndt_7~0, eval_#t~nondet8, eval_~tmp_ndt_8~0, eval_#t~nondet9, eval_~tmp_ndt_9~0, eval_~tmp~0; [L677] havoc eval_~tmp~0; [L15] ~m_pc~0 := 0; [L16] ~t1_pc~0 := 0; [L17] ~t2_pc~0 := 0; [L18] ~t3_pc~0 := 0; [L19] ~t4_pc~0 := 0; [L20] ~t5_pc~0 := 0; [L21] ~t6_pc~0 := 0; [L22] ~t7_pc~0 := 0; [L23] ~t8_pc~0 := 0; [L24] ~m_st~0 := 0; [L25] ~t1_st~0 := 0; [L26] ~t2_st~0 := 0; [L27] ~t3_st~0 := 0; [L28] ~t4_st~0 := 0; [L29] ~t5_st~0 := 0; [L30] ~t6_st~0 := 0; [L31] ~t7_st~0 := 0; [L32] ~t8_st~0 := 0; [L33] ~m_i~0 := 0; [L34] ~t1_i~0 := 0; [L35] ~t2_i~0 := 0; [L36] ~t3_i~0 := 0; [L37] ~t4_i~0 := 0; [L38] ~t5_i~0 := 0; [L39] ~t6_i~0 := 0; [L40] ~t7_i~0 := 0; [L41] ~t8_i~0 := 0; [L42] ~M_E~0 := 2; [L43] ~T1_E~0 := 2; [L44] ~T2_E~0 := 2; [L45] ~T3_E~0 := 2; [L46] ~T4_E~0 := 2; [L47] ~T5_E~0 := 2; [L48] ~T6_E~0 := 2; [L49] ~T7_E~0 := 2; [L50] ~T8_E~0 := 2; [L51] ~E_1~0 := 2; [L52] ~E_2~0 := 2; [L53] ~E_3~0 := 2; [L54] ~E_4~0 := 2; [L55] ~E_5~0 := 2; [L56] ~E_6~0 := 2; [L57] ~E_7~0 := 2; [L58] ~E_8~0 := 2; [L1307] havoc ~__retres1~10; [L1215] ~m_i~0 := 1; [L1216] ~t1_i~0 := 1; [L1217] ~t2_i~0 := 1; [L1218] ~t3_i~0 := 1; [L1219] ~t4_i~0 := 1; [L1220] ~t5_i~0 := 1; [L1221] ~t6_i~0 := 1; [L1222] ~t7_i~0 := 1; [L1223] ~t8_i~0 := 1; [L1248] havoc ~kernel_st~0; [L1249] havoc ~tmp~3; [L1250] havoc ~tmp___0~1; [L1254] ~kernel_st~0 := 0; [L571] COND TRUE 1 == ~m_i~0 [L572] ~m_st~0 := 0; [L576] COND TRUE 1 == ~t1_i~0 [L577] ~t1_st~0 := 0; [L581] COND TRUE 1 == ~t2_i~0 [L582] ~t2_st~0 := 0; [L586] COND TRUE 1 == ~t3_i~0 [L587] ~t3_st~0 := 0; [L591] COND TRUE 1 == ~t4_i~0 [L592] ~t4_st~0 := 0; [L596] COND TRUE 1 == ~t5_i~0 [L597] ~t5_st~0 := 0; [L601] COND TRUE 1 == ~t6_i~0 [L602] ~t6_st~0 := 0; [L606] COND TRUE 1 == ~t7_i~0 [L607] ~t7_st~0 := 0; [L611] COND TRUE 1 == ~t8_i~0 [L612] ~t8_st~0 := 0; [L828] COND FALSE !(0 == ~M_E~0) [L833] COND FALSE !(0 == ~T1_E~0) [L838] COND FALSE !(0 == ~T2_E~0) [L843] COND FALSE !(0 == ~T3_E~0) [L848] COND FALSE !(0 == ~T4_E~0) [L853] COND FALSE !(0 == ~T5_E~0) [L858] COND FALSE !(0 == ~T6_E~0) [L863] COND FALSE !(0 == ~T7_E~0) [L868] COND FALSE !(0 == ~T8_E~0) [L873] COND FALSE !(0 == ~E_1~0) [L878] COND FALSE !(0 == ~E_2~0) [L883] COND FALSE !(0 == ~E_3~0) [L888] COND FALSE !(0 == ~E_4~0) [L893] COND FALSE !(0 == ~E_5~0) [L898] COND FALSE !(0 == ~E_6~0) [L903] COND FALSE !(0 == ~E_7~0) [L908] COND FALSE !(0 == ~E_8~0) [L1011] havoc ~tmp~1; [L1012] havoc ~tmp___0~0; [L1013] havoc ~tmp___1~0; [L1014] havoc ~tmp___2~0; [L1015] havoc ~tmp___3~0; [L1016] havoc ~tmp___4~0; [L1017] havoc ~tmp___5~0; [L1018] havoc ~tmp___6~0; [L1019] havoc ~tmp___7~0; [L389] havoc ~__retres1~0; [L392] COND FALSE !(1 == ~m_pc~0) [L402] ~__retres1~0 := 0; [L404] #res := ~__retres1~0; [L1023] ~tmp~1 := #t~ret10; [L1023] havoc #t~ret10; [L1025-L1029] COND FALSE !(0 != ~tmp~1) [L408] havoc ~__retres1~1; [L411] COND FALSE !(1 == ~t1_pc~0) [L421] ~__retres1~1 := 0; [L423] #res := ~__retres1~1; [L1031] ~tmp___0~0 := #t~ret11; [L1031] havoc #t~ret11; [L1033-L1037] COND FALSE !(0 != ~tmp___0~0) [L427] havoc ~__retres1~2; [L430] COND FALSE !(1 == ~t2_pc~0) [L440] ~__retres1~2 := 0; [L442] #res := ~__retres1~2; [L1039] ~tmp___1~0 := #t~ret12; [L1039] havoc #t~ret12; [L1041-L1045] COND FALSE !(0 != ~tmp___1~0) [L446] havoc ~__retres1~3; [L449] COND FALSE !(1 == ~t3_pc~0) [L459] ~__retres1~3 := 0; [L461] #res := ~__retres1~3; [L1047] ~tmp___2~0 := #t~ret13; [L1047] havoc #t~ret13; [L1049-L1053] COND FALSE !(0 != ~tmp___2~0) [L465] havoc ~__retres1~4; [L468] COND FALSE !(1 == ~t4_pc~0) [L478] ~__retres1~4 := 0; [L480] #res := ~__retres1~4; [L1055] ~tmp___3~0 := #t~ret14; [L1055] havoc #t~ret14; [L1057-L1061] COND FALSE !(0 != ~tmp___3~0) [L484] havoc ~__retres1~5; [L487] COND FALSE !(1 == ~t5_pc~0) [L497] ~__retres1~5 := 0; [L499] #res := ~__retres1~5; [L1063] ~tmp___4~0 := #t~ret15; [L1063] havoc #t~ret15; [L1065-L1069] COND FALSE !(0 != ~tmp___4~0) [L503] havoc ~__retres1~6; [L506] COND FALSE !(1 == ~t6_pc~0) [L516] ~__retres1~6 := 0; [L518] #res := ~__retres1~6; [L1071] ~tmp___5~0 := #t~ret16; [L1071] havoc #t~ret16; [L1073-L1077] COND FALSE !(0 != ~tmp___5~0) [L522] havoc ~__retres1~7; [L525] COND FALSE !(1 == ~t7_pc~0) [L535] ~__retres1~7 := 0; [L537] #res := ~__retres1~7; [L1079] ~tmp___6~0 := #t~ret17; [L1079] havoc #t~ret17; [L1081-L1085] COND FALSE !(0 != ~tmp___6~0) [L541] havoc ~__retres1~8; [L544] COND FALSE !(1 == ~t8_pc~0) [L554] ~__retres1~8 := 0; [L556] #res := ~__retres1~8; [L1087] ~tmp___7~0 := #t~ret18; [L1087] havoc #t~ret18; [L1089-L1093] COND FALSE !(0 != ~tmp___7~0) [L921] COND FALSE !(1 == ~M_E~0) [L926] COND FALSE !(1 == ~T1_E~0) [L931] COND FALSE !(1 == ~T2_E~0) [L936] COND FALSE !(1 == ~T3_E~0) [L941] COND FALSE !(1 == ~T4_E~0) [L946] COND FALSE !(1 == ~T5_E~0) [L951] COND FALSE !(1 == ~T6_E~0) [L956] COND FALSE !(1 == ~T7_E~0) [L961] COND FALSE !(1 == ~T8_E~0) [L966] COND FALSE !(1 == ~E_1~0) [L971] COND FALSE !(1 == ~E_2~0) [L976] COND FALSE !(1 == ~E_3~0) [L981] COND FALSE !(1 == ~E_4~0) [L986] COND FALSE !(1 == ~E_5~0) [L991] COND FALSE !(1 == ~E_6~0) [L996] COND FALSE !(1 == ~E_7~0) [L1001] COND FALSE !(1 == ~E_8~0) [L1262-L1299] COND FALSE !(false) [L1265] ~kernel_st~0 := 1; [L677] havoc ~tmp~0; ----- ----- class de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.CACSL2BoogieBacktranslator [L15] ~m_pc~0 := 0; [L16] ~t1_pc~0 := 0; [L17] ~t2_pc~0 := 0; [L18] ~t3_pc~0 := 0; [L19] ~t4_pc~0 := 0; [L20] ~t5_pc~0 := 0; [L21] ~t6_pc~0 := 0; [L22] ~t7_pc~0 := 0; [L23] ~t8_pc~0 := 0; [L24] ~m_st~0 := 0; [L25] ~t1_st~0 := 0; [L26] ~t2_st~0 := 0; [L27] ~t3_st~0 := 0; [L28] ~t4_st~0 := 0; [L29] ~t5_st~0 := 0; [L30] ~t6_st~0 := 0; [L31] ~t7_st~0 := 0; [L32] ~t8_st~0 := 0; [L33] ~m_i~0 := 0; [L34] ~t1_i~0 := 0; [L35] ~t2_i~0 := 0; [L36] ~t3_i~0 := 0; [L37] ~t4_i~0 := 0; [L38] ~t5_i~0 := 0; [L39] ~t6_i~0 := 0; [L40] ~t7_i~0 := 0; [L41] ~t8_i~0 := 0; [L42] ~M_E~0 := 2; [L43] ~T1_E~0 := 2; [L44] ~T2_E~0 := 2; [L45] ~T3_E~0 := 2; [L46] ~T4_E~0 := 2; [L47] ~T5_E~0 := 2; [L48] ~T6_E~0 := 2; [L49] ~T7_E~0 := 2; [L50] ~T8_E~0 := 2; [L51] ~E_1~0 := 2; [L52] ~E_2~0 := 2; [L53] ~E_3~0 := 2; [L54] ~E_4~0 := 2; [L55] ~E_5~0 := 2; [L56] ~E_6~0 := 2; [L57] ~E_7~0 := 2; [L58] ~E_8~0 := 2; [L1307] havoc ~__retres1~10; [L1215] ~m_i~0 := 1; [L1216] ~t1_i~0 := 1; [L1217] ~t2_i~0 := 1; [L1218] ~t3_i~0 := 1; [L1219] ~t4_i~0 := 1; [L1220] ~t5_i~0 := 1; [L1221] ~t6_i~0 := 1; [L1222] ~t7_i~0 := 1; [L1223] ~t8_i~0 := 1; [L1248] havoc ~kernel_st~0; [L1249] havoc ~tmp~3; [L1250] havoc ~tmp___0~1; [L1254] ~kernel_st~0 := 0; [L571] COND TRUE 1 == ~m_i~0 [L572] ~m_st~0 := 0; [L576] COND TRUE 1 == ~t1_i~0 [L577] ~t1_st~0 := 0; [L581] COND TRUE 1 == ~t2_i~0 [L582] ~t2_st~0 := 0; [L586] COND TRUE 1 == ~t3_i~0 [L587] ~t3_st~0 := 0; [L591] COND TRUE 1 == ~t4_i~0 [L592] ~t4_st~0 := 0; [L596] COND TRUE 1 == ~t5_i~0 [L597] ~t5_st~0 := 0; [L601] COND TRUE 1 == ~t6_i~0 [L602] ~t6_st~0 := 0; [L606] COND TRUE 1 == ~t7_i~0 [L607] ~t7_st~0 := 0; [L611] COND TRUE 1 == ~t8_i~0 [L612] ~t8_st~0 := 0; [L828] COND FALSE !(0 == ~M_E~0) [L833] COND FALSE !(0 == ~T1_E~0) [L838] COND FALSE !(0 == ~T2_E~0) [L843] COND FALSE !(0 == ~T3_E~0) [L848] COND FALSE !(0 == ~T4_E~0) [L853] COND FALSE !(0 == ~T5_E~0) [L858] COND FALSE !(0 == ~T6_E~0) [L863] COND FALSE !(0 == ~T7_E~0) [L868] COND FALSE !(0 == ~T8_E~0) [L873] COND FALSE !(0 == ~E_1~0) [L878] COND FALSE !(0 == ~E_2~0) [L883] COND FALSE !(0 == ~E_3~0) [L888] COND FALSE !(0 == ~E_4~0) [L893] COND FALSE !(0 == ~E_5~0) [L898] COND FALSE !(0 == ~E_6~0) [L903] COND FALSE !(0 == ~E_7~0) [L908] COND FALSE !(0 == ~E_8~0) [L1011] havoc ~tmp~1; [L1012] havoc ~tmp___0~0; [L1013] havoc ~tmp___1~0; [L1014] havoc ~tmp___2~0; [L1015] havoc ~tmp___3~0; [L1016] havoc ~tmp___4~0; [L1017] havoc ~tmp___5~0; [L1018] havoc ~tmp___6~0; [L1019] havoc ~tmp___7~0; [L389] havoc ~__retres1~0; [L392] COND FALSE !(1 == ~m_pc~0) [L402] ~__retres1~0 := 0; [L404] #res := ~__retres1~0; [L1023] ~tmp~1 := #t~ret10; [L1023] havoc #t~ret10; [L1025-L1029] COND FALSE !(0 != ~tmp~1) [L408] havoc ~__retres1~1; [L411] COND FALSE !(1 == ~t1_pc~0) [L421] ~__retres1~1 := 0; [L423] #res := ~__retres1~1; [L1031] ~tmp___0~0 := #t~ret11; [L1031] havoc #t~ret11; [L1033-L1037] COND FALSE !(0 != ~tmp___0~0) [L427] havoc ~__retres1~2; [L430] COND FALSE !(1 == ~t2_pc~0) [L440] ~__retres1~2 := 0; [L442] #res := ~__retres1~2; [L1039] ~tmp___1~0 := #t~ret12; [L1039] havoc #t~ret12; [L1041-L1045] COND FALSE !(0 != ~tmp___1~0) [L446] havoc ~__retres1~3; [L449] COND FALSE !(1 == ~t3_pc~0) [L459] ~__retres1~3 := 0; [L461] #res := ~__retres1~3; [L1047] ~tmp___2~0 := #t~ret13; [L1047] havoc #t~ret13; [L1049-L1053] COND FALSE !(0 != ~tmp___2~0) [L465] havoc ~__retres1~4; [L468] COND FALSE !(1 == ~t4_pc~0) [L478] ~__retres1~4 := 0; [L480] #res := ~__retres1~4; [L1055] ~tmp___3~0 := #t~ret14; [L1055] havoc #t~ret14; [L1057-L1061] COND FALSE !(0 != ~tmp___3~0) [L484] havoc ~__retres1~5; [L487] COND FALSE !(1 == ~t5_pc~0) [L497] ~__retres1~5 := 0; [L499] #res := ~__retres1~5; [L1063] ~tmp___4~0 := #t~ret15; [L1063] havoc #t~ret15; [L1065-L1069] COND FALSE !(0 != ~tmp___4~0) [L503] havoc ~__retres1~6; [L506] COND FALSE !(1 == ~t6_pc~0) [L516] ~__retres1~6 := 0; [L518] #res := ~__retres1~6; [L1071] ~tmp___5~0 := #t~ret16; [L1071] havoc #t~ret16; [L1073-L1077] COND FALSE !(0 != ~tmp___5~0) [L522] havoc ~__retres1~7; [L525] COND FALSE !(1 == ~t7_pc~0) [L535] ~__retres1~7 := 0; [L537] #res := ~__retres1~7; [L1079] ~tmp___6~0 := #t~ret17; [L1079] havoc #t~ret17; [L1081-L1085] COND FALSE !(0 != ~tmp___6~0) [L541] havoc ~__retres1~8; [L544] COND FALSE !(1 == ~t8_pc~0) [L554] ~__retres1~8 := 0; [L556] #res := ~__retres1~8; [L1087] ~tmp___7~0 := #t~ret18; [L1087] havoc #t~ret18; [L1089-L1093] COND FALSE !(0 != ~tmp___7~0) [L921] COND FALSE !(1 == ~M_E~0) [L926] COND FALSE !(1 == ~T1_E~0) [L931] COND FALSE !(1 == ~T2_E~0) [L936] COND FALSE !(1 == ~T3_E~0) [L941] COND FALSE !(1 == ~T4_E~0) [L946] COND FALSE !(1 == ~T5_E~0) [L951] COND FALSE !(1 == ~T6_E~0) [L956] COND FALSE !(1 == ~T7_E~0) [L961] COND FALSE !(1 == ~T8_E~0) [L966] COND FALSE !(1 == ~E_1~0) [L971] COND FALSE !(1 == ~E_2~0) [L976] COND FALSE !(1 == ~E_3~0) [L981] COND FALSE !(1 == ~E_4~0) [L986] COND FALSE !(1 == ~E_5~0) [L991] COND FALSE !(1 == ~E_6~0) [L996] COND FALSE !(1 == ~E_7~0) [L1001] COND FALSE !(1 == ~E_8~0) [L1262-L1299] COND FALSE !(false) [L1265] ~kernel_st~0 := 1; [L677] havoc ~tmp~0; [L15] int m_pc = 0; [L16] int t1_pc = 0; [L17] int t2_pc = 0; [L18] int t3_pc = 0; [L19] int t4_pc = 0; [L20] int t5_pc = 0; [L21] int t6_pc = 0; [L22] int t7_pc = 0; [L23] int t8_pc = 0; [L24] int m_st ; [L25] int t1_st ; [L26] int t2_st ; [L27] int t3_st ; [L28] int t4_st ; [L29] int t5_st ; [L30] int t6_st ; [L31] int t7_st ; [L32] int t8_st ; [L33] int m_i ; [L34] int t1_i ; [L35] int t2_i ; [L36] int t3_i ; [L37] int t4_i ; [L38] int t5_i ; [L39] int t6_i ; [L40] int t7_i ; [L41] int t8_i ; [L42] int M_E = 2; [L43] int T1_E = 2; [L44] int T2_E = 2; [L45] int T3_E = 2; [L46] int T4_E = 2; [L47] int T5_E = 2; [L48] int T6_E = 2; [L49] int T7_E = 2; [L50] int T8_E = 2; [L51] int E_1 = 2; [L52] int E_2 = 2; [L53] int E_3 = 2; [L54] int E_4 = 2; [L55] int E_5 = 2; [L56] int E_6 = 2; [L57] int E_7 = 2; [L58] int E_8 = 2; [L1307] int __retres1 ; [L1215] m_i = 1 [L1216] t1_i = 1 [L1217] t2_i = 1 [L1218] t3_i = 1 [L1219] t4_i = 1 [L1220] t5_i = 1 [L1221] t6_i = 1 [L1222] t7_i = 1 [L1223] t8_i = 1 [L1248] int kernel_st ; [L1249] int tmp ; [L1250] int tmp___0 ; [L1254] kernel_st = 0 [L571] COND TRUE m_i == 1 [L572] m_st = 0 [L576] COND TRUE t1_i == 1 [L577] t1_st = 0 [L581] COND TRUE t2_i == 1 [L582] t2_st = 0 [L586] COND TRUE t3_i == 1 [L587] t3_st = 0 [L591] COND TRUE t4_i == 1 [L592] t4_st = 0 [L596] COND TRUE t5_i == 1 [L597] t5_st = 0 [L601] COND TRUE t6_i == 1 [L602] t6_st = 0 [L606] COND TRUE t7_i == 1 [L607] t7_st = 0 [L611] COND TRUE t8_i == 1 [L612] t8_st = 0 [L828] COND FALSE !(M_E == 0) [L833] COND FALSE !(T1_E == 0) [L838] COND FALSE !(T2_E == 0) [L843] COND FALSE !(T3_E == 0) [L848] COND FALSE !(T4_E == 0) [L853] COND FALSE !(T5_E == 0) [L858] COND FALSE !(T6_E == 0) [L863] COND FALSE !(T7_E == 0) [L868] COND FALSE !(T8_E == 0) [L873] COND FALSE !(E_1 == 0) [L878] COND FALSE !(E_2 == 0) [L883] COND FALSE !(E_3 == 0) [L888] COND FALSE !(E_4 == 0) [L893] COND FALSE !(E_5 == 0) [L898] COND FALSE !(E_6 == 0) [L903] COND FALSE !(E_7 == 0) [L908] COND FALSE !(E_8 == 0) [L1011] int tmp ; [L1012] int tmp___0 ; [L1013] int tmp___1 ; [L1014] int tmp___2 ; [L1015] int tmp___3 ; [L1016] int tmp___4 ; [L1017] int tmp___5 ; [L1018] int tmp___6 ; [L1019] int tmp___7 ; [L389] int __retres1 ; [L392] COND FALSE !(m_pc == 1) [L402] __retres1 = 0 [L404] return (__retres1); [L1023] tmp = is_master_triggered() [L1025] COND FALSE !(\read(tmp)) [L408] int __retres1 ; [L411] COND FALSE !(t1_pc == 1) [L421] __retres1 = 0 [L423] return (__retres1); [L1031] tmp___0 = is_transmit1_triggered() [L1033] COND FALSE !(\read(tmp___0)) [L427] int __retres1 ; [L430] COND FALSE !(t2_pc == 1) [L440] __retres1 = 0 [L442] return (__retres1); [L1039] tmp___1 = is_transmit2_triggered() [L1041] COND FALSE !(\read(tmp___1)) [L446] int __retres1 ; [L449] COND FALSE !(t3_pc == 1) [L459] __retres1 = 0 [L461] return (__retres1); [L1047] tmp___2 = is_transmit3_triggered() [L1049] COND FALSE !(\read(tmp___2)) [L465] int __retres1 ; [L468] COND FALSE !(t4_pc == 1) [L478] __retres1 = 0 [L480] return (__retres1); [L1055] tmp___3 = is_transmit4_triggered() [L1057] COND FALSE !(\read(tmp___3)) [L484] int __retres1 ; [L487] COND FALSE !(t5_pc == 1) [L497] __retres1 = 0 [L499] return (__retres1); [L1063] tmp___4 = is_transmit5_triggered() [L1065] COND FALSE !(\read(tmp___4)) [L503] int __retres1 ; [L506] COND FALSE !(t6_pc == 1) [L516] __retres1 = 0 [L518] return (__retres1); [L1071] tmp___5 = is_transmit6_triggered() [L1073] COND FALSE !(\read(tmp___5)) [L522] int __retres1 ; [L525] COND FALSE !(t7_pc == 1) [L535] __retres1 = 0 [L537] return (__retres1); [L1079] tmp___6 = is_transmit7_triggered() [L1081] COND FALSE !(\read(tmp___6)) [L541] int __retres1 ; [L544] COND FALSE !(t8_pc == 1) [L554] __retres1 = 0 [L556] return (__retres1); [L1087] tmp___7 = is_transmit8_triggered() [L1089] COND FALSE !(\read(tmp___7)) [L921] COND FALSE !(M_E == 1) [L926] COND FALSE !(T1_E == 1) [L931] COND FALSE !(T2_E == 1) [L936] COND FALSE !(T3_E == 1) [L941] COND FALSE !(T4_E == 1) [L946] COND FALSE !(T5_E == 1) [L951] COND FALSE !(T6_E == 1) [L956] COND FALSE !(T7_E == 1) [L961] COND FALSE !(T8_E == 1) [L966] COND FALSE !(E_1 == 1) [L971] COND FALSE !(E_2 == 1) [L976] COND FALSE !(E_3 == 1) [L981] COND FALSE !(E_4 == 1) [L986] COND FALSE !(E_5 == 1) [L991] COND FALSE !(E_6 == 1) [L996] COND FALSE !(E_7 == 1) [L1001] COND FALSE !(E_8 == 1) [L1262] COND TRUE 1 [L1265] kernel_st = 1 [L677] int tmp ; ----- ----- class de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder.RCFGBacktranslator [?] assume !false; [?] havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~9;havoc exists_runnable_thread_~__retres1~9; [?] assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9 := 1; [?] exists_runnable_thread_#res := exists_runnable_thread_~__retres1~9; [?] eval_#t~ret0 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret0;havoc eval_#t~ret0; [?] assume 0 != eval_~tmp~0; [?] assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0;eval_~tmp_ndt_1~0 := eval_#t~nondet1;havoc eval_#t~nondet1; [?] assume !(0 != eval_~tmp_ndt_1~0); [?] assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0;eval_~tmp_ndt_2~0 := eval_#t~nondet2;havoc eval_#t~nondet2; [?] assume !(0 != eval_~tmp_ndt_2~0); [?] assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0;eval_~tmp_ndt_3~0 := eval_#t~nondet3;havoc eval_#t~nondet3; [?] assume !(0 != eval_~tmp_ndt_3~0); [?] assume 0 == ~t3_st~0;havoc eval_~tmp_ndt_4~0;eval_~tmp_ndt_4~0 := eval_#t~nondet4;havoc eval_#t~nondet4; [?] assume !(0 != eval_~tmp_ndt_4~0); [?] assume 0 == ~t4_st~0;havoc eval_~tmp_ndt_5~0;eval_~tmp_ndt_5~0 := eval_#t~nondet5;havoc eval_#t~nondet5; [?] assume !(0 != eval_~tmp_ndt_5~0); [?] assume 0 == ~t5_st~0;havoc eval_~tmp_ndt_6~0;eval_~tmp_ndt_6~0 := eval_#t~nondet6;havoc eval_#t~nondet6; [?] assume !(0 != eval_~tmp_ndt_6~0); [?] assume 0 == ~t6_st~0;havoc eval_~tmp_ndt_7~0;eval_~tmp_ndt_7~0 := eval_#t~nondet7;havoc eval_#t~nondet7; [?] assume !(0 != eval_~tmp_ndt_7~0); [?] assume 0 == ~t7_st~0;havoc eval_~tmp_ndt_8~0;eval_~tmp_ndt_8~0 := eval_#t~nondet8;havoc eval_#t~nondet8; [?] assume !(0 != eval_~tmp_ndt_8~0); [?] assume 0 == ~t8_st~0;havoc eval_~tmp_ndt_9~0;eval_~tmp_ndt_9~0 := eval_#t~nondet9;havoc eval_#t~nondet9; [?] assume !(0 != eval_~tmp_ndt_9~0); [L681-L817] assume !false; [L684] havoc exists_runnable_thread_#res; [L684] havoc exists_runnable_thread_~__retres1~9; [L621] havoc exists_runnable_thread_~__retres1~9; [L624-L669] assume 0 == ~m_st~0; [L625] exists_runnable_thread_~__retres1~9 := 1; [L672] exists_runnable_thread_#res := exists_runnable_thread_~__retres1~9; [L684] eval_#t~ret0 := exists_runnable_thread_#res; [L684] eval_~tmp~0 := eval_#t~ret0; [L684] havoc eval_#t~ret0; [L686-L690] assume 0 != eval_~tmp~0; [L691-L704] assume 0 == ~m_st~0; [L692] havoc eval_~tmp_ndt_1~0; [L693] eval_~tmp_ndt_1~0 := eval_#t~nondet1; [L693] havoc eval_#t~nondet1; [L694-L701] assume !(0 != eval_~tmp_ndt_1~0); [L705-L718] assume 0 == ~t1_st~0; [L706] havoc eval_~tmp_ndt_2~0; [L707] eval_~tmp_ndt_2~0 := eval_#t~nondet2; [L707] havoc eval_#t~nondet2; [L708-L715] assume !(0 != eval_~tmp_ndt_2~0); [L719-L732] assume 0 == ~t2_st~0; [L720] havoc eval_~tmp_ndt_3~0; [L721] eval_~tmp_ndt_3~0 := eval_#t~nondet3; [L721] havoc eval_#t~nondet3; [L722-L729] assume !(0 != eval_~tmp_ndt_3~0); [L733-L746] assume 0 == ~t3_st~0; [L734] havoc eval_~tmp_ndt_4~0; [L735] eval_~tmp_ndt_4~0 := eval_#t~nondet4; [L735] havoc eval_#t~nondet4; [L736-L743] assume !(0 != eval_~tmp_ndt_4~0); [L747-L760] assume 0 == ~t4_st~0; [L748] havoc eval_~tmp_ndt_5~0; [L749] eval_~tmp_ndt_5~0 := eval_#t~nondet5; [L749] havoc eval_#t~nondet5; [L750-L757] assume !(0 != eval_~tmp_ndt_5~0); [L761-L774] assume 0 == ~t5_st~0; [L762] havoc eval_~tmp_ndt_6~0; [L763] eval_~tmp_ndt_6~0 := eval_#t~nondet6; [L763] havoc eval_#t~nondet6; [L764-L771] assume !(0 != eval_~tmp_ndt_6~0); [L775-L788] assume 0 == ~t6_st~0; [L776] havoc eval_~tmp_ndt_7~0; [L777] eval_~tmp_ndt_7~0 := eval_#t~nondet7; [L777] havoc eval_#t~nondet7; [L778-L785] assume !(0 != eval_~tmp_ndt_7~0); [L789-L802] assume 0 == ~t7_st~0; [L790] havoc eval_~tmp_ndt_8~0; [L791] eval_~tmp_ndt_8~0 := eval_#t~nondet8; [L791] havoc eval_#t~nondet8; [L792-L799] assume !(0 != eval_~tmp_ndt_8~0); [L803-L816] assume 0 == ~t8_st~0; [L804] havoc eval_~tmp_ndt_9~0; [L805] eval_~tmp_ndt_9~0 := eval_#t~nondet9; [L805] havoc eval_#t~nondet9; [L806-L813] assume !(0 != eval_~tmp_ndt_9~0); ----- ----- class de.uni_freiburg.informatik.ultimate.boogie.preprocessor.BoogiePreprocessorBacktranslator [L681-L817] assume !false; [L684] havoc exists_runnable_thread_#res; [L684] havoc exists_runnable_thread_~__retres1~9; [L621] havoc exists_runnable_thread_~__retres1~9; [L624-L669] assume 0 == ~m_st~0; [L625] exists_runnable_thread_~__retres1~9 := 1; [L672] exists_runnable_thread_#res := exists_runnable_thread_~__retres1~9; [L684] eval_#t~ret0 := exists_runnable_thread_#res; [L684] eval_~tmp~0 := eval_#t~ret0; [L684] havoc eval_#t~ret0; [L686-L690] assume 0 != eval_~tmp~0; [L691-L704] assume 0 == ~m_st~0; [L692] havoc eval_~tmp_ndt_1~0; [L693] eval_~tmp_ndt_1~0 := eval_#t~nondet1; [L693] havoc eval_#t~nondet1; [L694-L701] assume !(0 != eval_~tmp_ndt_1~0); [L705-L718] assume 0 == ~t1_st~0; [L706] havoc eval_~tmp_ndt_2~0; [L707] eval_~tmp_ndt_2~0 := eval_#t~nondet2; [L707] havoc eval_#t~nondet2; [L708-L715] assume !(0 != eval_~tmp_ndt_2~0); [L719-L732] assume 0 == ~t2_st~0; [L720] havoc eval_~tmp_ndt_3~0; [L721] eval_~tmp_ndt_3~0 := eval_#t~nondet3; [L721] havoc eval_#t~nondet3; [L722-L729] assume !(0 != eval_~tmp_ndt_3~0); [L733-L746] assume 0 == ~t3_st~0; [L734] havoc eval_~tmp_ndt_4~0; [L735] eval_~tmp_ndt_4~0 := eval_#t~nondet4; [L735] havoc eval_#t~nondet4; [L736-L743] assume !(0 != eval_~tmp_ndt_4~0); [L747-L760] assume 0 == ~t4_st~0; [L748] havoc eval_~tmp_ndt_5~0; [L749] eval_~tmp_ndt_5~0 := eval_#t~nondet5; [L749] havoc eval_#t~nondet5; [L750-L757] assume !(0 != eval_~tmp_ndt_5~0); [L761-L774] assume 0 == ~t5_st~0; [L762] havoc eval_~tmp_ndt_6~0; [L763] eval_~tmp_ndt_6~0 := eval_#t~nondet6; [L763] havoc eval_#t~nondet6; [L764-L771] assume !(0 != eval_~tmp_ndt_6~0); [L775-L788] assume 0 == ~t6_st~0; [L776] havoc eval_~tmp_ndt_7~0; [L777] eval_~tmp_ndt_7~0 := eval_#t~nondet7; [L777] havoc eval_#t~nondet7; [L778-L785] assume !(0 != eval_~tmp_ndt_7~0); [L789-L802] assume 0 == ~t7_st~0; [L790] havoc eval_~tmp_ndt_8~0; [L791] eval_~tmp_ndt_8~0 := eval_#t~nondet8; [L791] havoc eval_#t~nondet8; [L792-L799] assume !(0 != eval_~tmp_ndt_8~0); [L803-L816] assume 0 == ~t8_st~0; [L804] havoc eval_~tmp_ndt_9~0; [L805] eval_~tmp_ndt_9~0 := eval_#t~nondet9; [L805] havoc eval_#t~nondet9; [L806-L813] assume !(0 != eval_~tmp_ndt_9~0); [L681-L817] COND FALSE !(false) [L684] havoc exists_runnable_thread_#res; [L684] havoc exists_runnable_thread_~__retres1~9; [L621] havoc exists_runnable_thread_~__retres1~9; [L624] COND TRUE 0 == ~m_st~0 [L625] exists_runnable_thread_~__retres1~9 := 1; [L672] exists_runnable_thread_#res := exists_runnable_thread_~__retres1~9; [L684] eval_#t~ret0 := exists_runnable_thread_#res; [L684] eval_~tmp~0 := eval_#t~ret0; [L684] havoc eval_#t~ret0; [L686-L690] COND TRUE 0 != eval_~tmp~0 [L691] COND TRUE 0 == ~m_st~0 [L692] havoc eval_~tmp_ndt_1~0; [L693] eval_~tmp_ndt_1~0 := eval_#t~nondet1; [L693] havoc eval_#t~nondet1; [L694-L701] COND FALSE !(0 != eval_~tmp_ndt_1~0) [L705] COND TRUE 0 == ~t1_st~0 [L706] havoc eval_~tmp_ndt_2~0; [L707] eval_~tmp_ndt_2~0 := eval_#t~nondet2; [L707] havoc eval_#t~nondet2; [L708-L715] COND FALSE !(0 != eval_~tmp_ndt_2~0) [L719] COND TRUE 0 == ~t2_st~0 [L720] havoc eval_~tmp_ndt_3~0; [L721] eval_~tmp_ndt_3~0 := eval_#t~nondet3; [L721] havoc eval_#t~nondet3; [L722-L729] COND FALSE !(0 != eval_~tmp_ndt_3~0) [L733] COND TRUE 0 == ~t3_st~0 [L734] havoc eval_~tmp_ndt_4~0; [L735] eval_~tmp_ndt_4~0 := eval_#t~nondet4; [L735] havoc eval_#t~nondet4; [L736-L743] COND FALSE !(0 != eval_~tmp_ndt_4~0) [L747] COND TRUE 0 == ~t4_st~0 [L748] havoc eval_~tmp_ndt_5~0; [L749] eval_~tmp_ndt_5~0 := eval_#t~nondet5; [L749] havoc eval_#t~nondet5; [L750-L757] COND FALSE !(0 != eval_~tmp_ndt_5~0) [L761] COND TRUE 0 == ~t5_st~0 [L762] havoc eval_~tmp_ndt_6~0; [L763] eval_~tmp_ndt_6~0 := eval_#t~nondet6; [L763] havoc eval_#t~nondet6; [L764-L771] COND FALSE !(0 != eval_~tmp_ndt_6~0) [L775] COND TRUE 0 == ~t6_st~0 [L776] havoc eval_~tmp_ndt_7~0; [L777] eval_~tmp_ndt_7~0 := eval_#t~nondet7; [L777] havoc eval_#t~nondet7; [L778-L785] COND FALSE !(0 != eval_~tmp_ndt_7~0) [L789] COND TRUE 0 == ~t7_st~0 [L790] havoc eval_~tmp_ndt_8~0; [L791] eval_~tmp_ndt_8~0 := eval_#t~nondet8; [L791] havoc eval_#t~nondet8; [L792-L799] COND FALSE !(0 != eval_~tmp_ndt_8~0) [L803] COND TRUE 0 == ~t8_st~0 [L804] havoc eval_~tmp_ndt_9~0; [L805] eval_~tmp_ndt_9~0 := eval_#t~nondet9; [L805] havoc eval_#t~nondet9; [L806-L813] COND FALSE !(0 != eval_~tmp_ndt_9~0) ----- ----- class de.uni_freiburg.informatik.ultimate.boogie.procedureinliner.backtranslation.InlinerBacktranslator [L681-L817] COND FALSE !(false) [L684] havoc exists_runnable_thread_#res; [L684] havoc exists_runnable_thread_~__retres1~9; [L621] havoc exists_runnable_thread_~__retres1~9; [L624] COND TRUE 0 == ~m_st~0 [L625] exists_runnable_thread_~__retres1~9 := 1; [L672] exists_runnable_thread_#res := exists_runnable_thread_~__retres1~9; [L684] eval_#t~ret0 := exists_runnable_thread_#res; [L684] eval_~tmp~0 := eval_#t~ret0; [L684] havoc eval_#t~ret0; [L686-L690] COND TRUE 0 != eval_~tmp~0 [L691] COND TRUE 0 == ~m_st~0 [L692] havoc eval_~tmp_ndt_1~0; [L693] eval_~tmp_ndt_1~0 := eval_#t~nondet1; [L693] havoc eval_#t~nondet1; [L694-L701] COND FALSE !(0 != eval_~tmp_ndt_1~0) [L705] COND TRUE 0 == ~t1_st~0 [L706] havoc eval_~tmp_ndt_2~0; [L707] eval_~tmp_ndt_2~0 := eval_#t~nondet2; [L707] havoc eval_#t~nondet2; [L708-L715] COND FALSE !(0 != eval_~tmp_ndt_2~0) [L719] COND TRUE 0 == ~t2_st~0 [L720] havoc eval_~tmp_ndt_3~0; [L721] eval_~tmp_ndt_3~0 := eval_#t~nondet3; [L721] havoc eval_#t~nondet3; [L722-L729] COND FALSE !(0 != eval_~tmp_ndt_3~0) [L733] COND TRUE 0 == ~t3_st~0 [L734] havoc eval_~tmp_ndt_4~0; [L735] eval_~tmp_ndt_4~0 := eval_#t~nondet4; [L735] havoc eval_#t~nondet4; [L736-L743] COND FALSE !(0 != eval_~tmp_ndt_4~0) [L747] COND TRUE 0 == ~t4_st~0 [L748] havoc eval_~tmp_ndt_5~0; [L749] eval_~tmp_ndt_5~0 := eval_#t~nondet5; [L749] havoc eval_#t~nondet5; [L750-L757] COND FALSE !(0 != eval_~tmp_ndt_5~0) [L761] COND TRUE 0 == ~t5_st~0 [L762] havoc eval_~tmp_ndt_6~0; [L763] eval_~tmp_ndt_6~0 := eval_#t~nondet6; [L763] havoc eval_#t~nondet6; [L764-L771] COND FALSE !(0 != eval_~tmp_ndt_6~0) [L775] COND TRUE 0 == ~t6_st~0 [L776] havoc eval_~tmp_ndt_7~0; [L777] eval_~tmp_ndt_7~0 := eval_#t~nondet7; [L777] havoc eval_#t~nondet7; [L778-L785] COND FALSE !(0 != eval_~tmp_ndt_7~0) [L789] COND TRUE 0 == ~t7_st~0 [L790] havoc eval_~tmp_ndt_8~0; [L791] eval_~tmp_ndt_8~0 := eval_#t~nondet8; [L791] havoc eval_#t~nondet8; [L792-L799] COND FALSE !(0 != eval_~tmp_ndt_8~0) [L803] COND TRUE 0 == ~t8_st~0 [L804] havoc eval_~tmp_ndt_9~0; [L805] eval_~tmp_ndt_9~0 := eval_#t~nondet9; [L805] havoc eval_#t~nondet9; [L806-L813] COND FALSE !(0 != eval_~tmp_ndt_9~0) [L681-L817] COND FALSE !(false) [L621] havoc ~__retres1~9; [L624] COND TRUE 0 == ~m_st~0 [L625] ~__retres1~9 := 1; [L672] #res := ~__retres1~9; [L684] ~tmp~0 := #t~ret0; [L684] havoc #t~ret0; [L686-L690] COND TRUE 0 != ~tmp~0 [L691] COND TRUE 0 == ~m_st~0 [L692] havoc ~tmp_ndt_1~0; [L693] ~tmp_ndt_1~0 := #t~nondet1; [L693] havoc #t~nondet1; [L694-L701] COND FALSE !(0 != ~tmp_ndt_1~0) [L705] COND TRUE 0 == ~t1_st~0 [L706] havoc ~tmp_ndt_2~0; [L707] ~tmp_ndt_2~0 := #t~nondet2; [L707] havoc #t~nondet2; [L708-L715] COND FALSE !(0 != ~tmp_ndt_2~0) [L719] COND TRUE 0 == ~t2_st~0 [L720] havoc ~tmp_ndt_3~0; [L721] ~tmp_ndt_3~0 := #t~nondet3; [L721] havoc #t~nondet3; [L722-L729] COND FALSE !(0 != ~tmp_ndt_3~0) [L733] COND TRUE 0 == ~t3_st~0 [L734] havoc ~tmp_ndt_4~0; [L735] ~tmp_ndt_4~0 := #t~nondet4; [L735] havoc #t~nondet4; [L736-L743] COND FALSE !(0 != ~tmp_ndt_4~0) [L747] COND TRUE 0 == ~t4_st~0 [L748] havoc ~tmp_ndt_5~0; [L749] ~tmp_ndt_5~0 := #t~nondet5; [L749] havoc #t~nondet5; [L750-L757] COND FALSE !(0 != ~tmp_ndt_5~0) [L761] COND TRUE 0 == ~t5_st~0 [L762] havoc ~tmp_ndt_6~0; [L763] ~tmp_ndt_6~0 := #t~nondet6; [L763] havoc #t~nondet6; [L764-L771] COND FALSE !(0 != ~tmp_ndt_6~0) [L775] COND TRUE 0 == ~t6_st~0 [L776] havoc ~tmp_ndt_7~0; [L777] ~tmp_ndt_7~0 := #t~nondet7; [L777] havoc #t~nondet7; [L778-L785] COND FALSE !(0 != ~tmp_ndt_7~0) [L789] COND TRUE 0 == ~t7_st~0 [L790] havoc ~tmp_ndt_8~0; [L791] ~tmp_ndt_8~0 := #t~nondet8; [L791] havoc #t~nondet8; [L792-L799] COND FALSE !(0 != ~tmp_ndt_8~0) [L803] COND TRUE 0 == ~t8_st~0 [L804] havoc ~tmp_ndt_9~0; [L805] ~tmp_ndt_9~0 := #t~nondet9; [L805] havoc #t~nondet9; [L806-L813] COND FALSE !(0 != ~tmp_ndt_9~0) ----- ----- class de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.CACSL2BoogieBacktranslator [L681-L817] COND FALSE !(false) [L621] havoc ~__retres1~9; [L624] COND TRUE 0 == ~m_st~0 [L625] ~__retres1~9 := 1; [L672] #res := ~__retres1~9; [L684] ~tmp~0 := #t~ret0; [L684] havoc #t~ret0; [L686-L690] COND TRUE 0 != ~tmp~0 [L691] COND TRUE 0 == ~m_st~0 [L692] havoc ~tmp_ndt_1~0; [L693] ~tmp_ndt_1~0 := #t~nondet1; [L693] havoc #t~nondet1; [L694-L701] COND FALSE !(0 != ~tmp_ndt_1~0) [L705] COND TRUE 0 == ~t1_st~0 [L706] havoc ~tmp_ndt_2~0; [L707] ~tmp_ndt_2~0 := #t~nondet2; [L707] havoc #t~nondet2; [L708-L715] COND FALSE !(0 != ~tmp_ndt_2~0) [L719] COND TRUE 0 == ~t2_st~0 [L720] havoc ~tmp_ndt_3~0; [L721] ~tmp_ndt_3~0 := #t~nondet3; [L721] havoc #t~nondet3; [L722-L729] COND FALSE !(0 != ~tmp_ndt_3~0) [L733] COND TRUE 0 == ~t3_st~0 [L734] havoc ~tmp_ndt_4~0; [L735] ~tmp_ndt_4~0 := #t~nondet4; [L735] havoc #t~nondet4; [L736-L743] COND FALSE !(0 != ~tmp_ndt_4~0) [L747] COND TRUE 0 == ~t4_st~0 [L748] havoc ~tmp_ndt_5~0; [L749] ~tmp_ndt_5~0 := #t~nondet5; [L749] havoc #t~nondet5; [L750-L757] COND FALSE !(0 != ~tmp_ndt_5~0) [L761] COND TRUE 0 == ~t5_st~0 [L762] havoc ~tmp_ndt_6~0; [L763] ~tmp_ndt_6~0 := #t~nondet6; [L763] havoc #t~nondet6; [L764-L771] COND FALSE !(0 != ~tmp_ndt_6~0) [L775] COND TRUE 0 == ~t6_st~0 [L776] havoc ~tmp_ndt_7~0; [L777] ~tmp_ndt_7~0 := #t~nondet7; [L777] havoc #t~nondet7; [L778-L785] COND FALSE !(0 != ~tmp_ndt_7~0) [L789] COND TRUE 0 == ~t7_st~0 [L790] havoc ~tmp_ndt_8~0; [L791] ~tmp_ndt_8~0 := #t~nondet8; [L791] havoc #t~nondet8; [L792-L799] COND FALSE !(0 != ~tmp_ndt_8~0) [L803] COND TRUE 0 == ~t8_st~0 [L804] havoc ~tmp_ndt_9~0; [L805] ~tmp_ndt_9~0 := #t~nondet9; [L805] havoc #t~nondet9; [L806-L813] COND FALSE !(0 != ~tmp_ndt_9~0) [L681] COND TRUE 1 [L621] int __retres1 ; [L624] COND TRUE m_st == 0 [L625] __retres1 = 1 [L672] return (__retres1); [L684] tmp = exists_runnable_thread() [L686] COND TRUE \read(tmp) [L691] COND TRUE m_st == 0 [L692] int tmp_ndt_1; [L693] tmp_ndt_1 = __VERIFIER_nondet_int() [L694] COND FALSE !(\read(tmp_ndt_1)) [L705] COND TRUE t1_st == 0 [L706] int tmp_ndt_2; [L707] tmp_ndt_2 = __VERIFIER_nondet_int() [L708] COND FALSE !(\read(tmp_ndt_2)) [L719] COND TRUE t2_st == 0 [L720] int tmp_ndt_3; [L721] tmp_ndt_3 = __VERIFIER_nondet_int() [L722] COND FALSE !(\read(tmp_ndt_3)) [L733] COND TRUE t3_st == 0 [L734] int tmp_ndt_4; [L735] tmp_ndt_4 = __VERIFIER_nondet_int() [L736] COND FALSE !(\read(tmp_ndt_4)) [L747] COND TRUE t4_st == 0 [L748] int tmp_ndt_5; [L749] tmp_ndt_5 = __VERIFIER_nondet_int() [L750] COND FALSE !(\read(tmp_ndt_5)) [L761] COND TRUE t5_st == 0 [L762] int tmp_ndt_6; [L763] tmp_ndt_6 = __VERIFIER_nondet_int() [L764] COND FALSE !(\read(tmp_ndt_6)) [L775] COND TRUE t6_st == 0 [L776] int tmp_ndt_7; [L777] tmp_ndt_7 = __VERIFIER_nondet_int() [L778] COND FALSE !(\read(tmp_ndt_7)) [L789] COND TRUE t7_st == 0 [L790] int tmp_ndt_8; [L791] tmp_ndt_8 = __VERIFIER_nondet_int() [L792] COND FALSE !(\read(tmp_ndt_8)) [L803] COND TRUE t8_st == 0 [L804] int tmp_ndt_9; [L805] tmp_ndt_9 = __VERIFIER_nondet_int() [L806] COND FALSE !(\read(tmp_ndt_9)) ----- Found a nonterminating execution for the following lasso shaped sequence of statements. Stem: [L15] int m_pc = 0; [L16] int t1_pc = 0; [L17] int t2_pc = 0; [L18] int t3_pc = 0; [L19] int t4_pc = 0; [L20] int t5_pc = 0; [L21] int t6_pc = 0; [L22] int t7_pc = 0; [L23] int t8_pc = 0; [L24] int m_st ; [L25] int t1_st ; [L26] int t2_st ; [L27] int t3_st ; [L28] int t4_st ; [L29] int t5_st ; [L30] int t6_st ; [L31] int t7_st ; [L32] int t8_st ; [L33] int m_i ; [L34] int t1_i ; [L35] int t2_i ; [L36] int t3_i ; [L37] int t4_i ; [L38] int t5_i ; [L39] int t6_i ; [L40] int t7_i ; [L41] int t8_i ; [L42] int M_E = 2; [L43] int T1_E = 2; [L44] int T2_E = 2; [L45] int T3_E = 2; [L46] int T4_E = 2; [L47] int T5_E = 2; [L48] int T6_E = 2; [L49] int T7_E = 2; [L50] int T8_E = 2; [L51] int E_1 = 2; [L52] int E_2 = 2; [L53] int E_3 = 2; [L54] int E_4 = 2; [L55] int E_5 = 2; [L56] int E_6 = 2; [L57] int E_7 = 2; [L58] int E_8 = 2; [L1307] int __retres1 ; [L1215] m_i = 1 [L1216] t1_i = 1 [L1217] t2_i = 1 [L1218] t3_i = 1 [L1219] t4_i = 1 [L1220] t5_i = 1 [L1221] t6_i = 1 [L1222] t7_i = 1 [L1223] t8_i = 1 [L1248] int kernel_st ; [L1249] int tmp ; [L1250] int tmp___0 ; [L1254] kernel_st = 0 [L571] COND TRUE m_i == 1 [L572] m_st = 0 [L576] COND TRUE t1_i == 1 [L577] t1_st = 0 [L581] COND TRUE t2_i == 1 [L582] t2_st = 0 [L586] COND TRUE t3_i == 1 [L587] t3_st = 0 [L591] COND TRUE t4_i == 1 [L592] t4_st = 0 [L596] COND TRUE t5_i == 1 [L597] t5_st = 0 [L601] COND TRUE t6_i == 1 [L602] t6_st = 0 [L606] COND TRUE t7_i == 1 [L607] t7_st = 0 [L611] COND TRUE t8_i == 1 [L612] t8_st = 0 [L828] COND FALSE !(M_E == 0) [L833] COND FALSE !(T1_E == 0) [L838] COND FALSE !(T2_E == 0) [L843] COND FALSE !(T3_E == 0) [L848] COND FALSE !(T4_E == 0) [L853] COND FALSE !(T5_E == 0) [L858] COND FALSE !(T6_E == 0) [L863] COND FALSE !(T7_E == 0) [L868] COND FALSE !(T8_E == 0) [L873] COND FALSE !(E_1 == 0) [L878] COND FALSE !(E_2 == 0) [L883] COND FALSE !(E_3 == 0) [L888] COND FALSE !(E_4 == 0) [L893] COND FALSE !(E_5 == 0) [L898] COND FALSE !(E_6 == 0) [L903] COND FALSE !(E_7 == 0) [L908] COND FALSE !(E_8 == 0) [L1011] int tmp ; [L1012] int tmp___0 ; [L1013] int tmp___1 ; [L1014] int tmp___2 ; [L1015] int tmp___3 ; [L1016] int tmp___4 ; [L1017] int tmp___5 ; [L1018] int tmp___6 ; [L1019] int tmp___7 ; [L389] int __retres1 ; [L392] COND FALSE !(m_pc == 1) [L402] __retres1 = 0 [L404] return (__retres1); [L1023] tmp = is_master_triggered() [L1025] COND FALSE !(\read(tmp)) [L408] int __retres1 ; [L411] COND FALSE !(t1_pc == 1) [L421] __retres1 = 0 [L423] return (__retres1); [L1031] tmp___0 = is_transmit1_triggered() [L1033] COND FALSE !(\read(tmp___0)) [L427] int __retres1 ; [L430] COND FALSE !(t2_pc == 1) [L440] __retres1 = 0 [L442] return (__retres1); [L1039] tmp___1 = is_transmit2_triggered() [L1041] COND FALSE !(\read(tmp___1)) [L446] int __retres1 ; [L449] COND FALSE !(t3_pc == 1) [L459] __retres1 = 0 [L461] return (__retres1); [L1047] tmp___2 = is_transmit3_triggered() [L1049] COND FALSE !(\read(tmp___2)) [L465] int __retres1 ; [L468] COND FALSE !(t4_pc == 1) [L478] __retres1 = 0 [L480] return (__retres1); [L1055] tmp___3 = is_transmit4_triggered() [L1057] COND FALSE !(\read(tmp___3)) [L484] int __retres1 ; [L487] COND FALSE !(t5_pc == 1) [L497] __retres1 = 0 [L499] return (__retres1); [L1063] tmp___4 = is_transmit5_triggered() [L1065] COND FALSE !(\read(tmp___4)) [L503] int __retres1 ; [L506] COND FALSE !(t6_pc == 1) [L516] __retres1 = 0 [L518] return (__retres1); [L1071] tmp___5 = is_transmit6_triggered() [L1073] COND FALSE !(\read(tmp___5)) [L522] int __retres1 ; [L525] COND FALSE !(t7_pc == 1) [L535] __retres1 = 0 [L537] return (__retres1); [L1079] tmp___6 = is_transmit7_triggered() [L1081] COND FALSE !(\read(tmp___6)) [L541] int __retres1 ; [L544] COND FALSE !(t8_pc == 1) [L554] __retres1 = 0 [L556] return (__retres1); [L1087] tmp___7 = is_transmit8_triggered() [L1089] COND FALSE !(\read(tmp___7)) [L921] COND FALSE !(M_E == 1) [L926] COND FALSE !(T1_E == 1) [L931] COND FALSE !(T2_E == 1) [L936] COND FALSE !(T3_E == 1) [L941] COND FALSE !(T4_E == 1) [L946] COND FALSE !(T5_E == 1) [L951] COND FALSE !(T6_E == 1) [L956] COND FALSE !(T7_E == 1) [L961] COND FALSE !(T8_E == 1) [L966] COND FALSE !(E_1 == 1) [L971] COND FALSE !(E_2 == 1) [L976] COND FALSE !(E_3 == 1) [L981] COND FALSE !(E_4 == 1) [L986] COND FALSE !(E_5 == 1) [L991] COND FALSE !(E_6 == 1) [L996] COND FALSE !(E_7 == 1) [L1001] COND FALSE !(E_8 == 1) [L1262] COND TRUE 1 [L1265] kernel_st = 1 [L677] int tmp ; Loop: [L681] COND TRUE 1 [L621] int __retres1 ; [L624] COND TRUE m_st == 0 [L625] __retres1 = 1 [L672] return (__retres1); [L684] tmp = exists_runnable_thread() [L686] COND TRUE \read(tmp) [L691] COND TRUE m_st == 0 [L692] int tmp_ndt_1; [L693] tmp_ndt_1 = __VERIFIER_nondet_int() [L694] COND FALSE !(\read(tmp_ndt_1)) [L705] COND TRUE t1_st == 0 [L706] int tmp_ndt_2; [L707] tmp_ndt_2 = __VERIFIER_nondet_int() [L708] COND FALSE !(\read(tmp_ndt_2)) [L719] COND TRUE t2_st == 0 [L720] int tmp_ndt_3; [L721] tmp_ndt_3 = __VERIFIER_nondet_int() [L722] COND FALSE !(\read(tmp_ndt_3)) [L733] COND TRUE t3_st == 0 [L734] int tmp_ndt_4; [L735] tmp_ndt_4 = __VERIFIER_nondet_int() [L736] COND FALSE !(\read(tmp_ndt_4)) [L747] COND TRUE t4_st == 0 [L748] int tmp_ndt_5; [L749] tmp_ndt_5 = __VERIFIER_nondet_int() [L750] COND FALSE !(\read(tmp_ndt_5)) [L761] COND TRUE t5_st == 0 [L762] int tmp_ndt_6; [L763] tmp_ndt_6 = __VERIFIER_nondet_int() [L764] COND FALSE !(\read(tmp_ndt_6)) [L775] COND TRUE t6_st == 0 [L776] int tmp_ndt_7; [L777] tmp_ndt_7 = __VERIFIER_nondet_int() [L778] COND FALSE !(\read(tmp_ndt_7)) [L789] COND TRUE t7_st == 0 [L790] int tmp_ndt_8; [L791] tmp_ndt_8 = __VERIFIER_nondet_int() [L792] COND FALSE !(\read(tmp_ndt_8)) [L803] COND TRUE t8_st == 0 [L804] int tmp_ndt_9; [L805] tmp_ndt_9 = __VERIFIER_nondet_int() [L806] COND FALSE !(\read(tmp_ndt_9)) End of lasso representation. RESULT: Ultimate proved your program to be incorrect! Received shutdown request...