./Ultimate.py --spec ../../sv-benchmarks/c/properties/valid-memsafety.prp --file ../../sv-benchmarks/c/memsafety-ext3/getNumbers4_false-valid-deref.c --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for memory safety (deref-memtrack) Using default analysis Version 0cd3be1d Calling Ultimate with: java -Dosgi.configuration.area=/tmp/vcloud-vcloud-master/worker/working_dir_3d9fc5bc-d65d-4259-979e-2e9bddd7decc/bin-2019/uautomizer/data/config -Xmx12G -Xms1G -jar /tmp/vcloud-vcloud-master/worker/working_dir_3d9fc5bc-d65d-4259-979e-2e9bddd7decc/bin-2019/uautomizer/plugins/org.eclipse.equinox.launcher_1.3.100.v20150511-1540.jar -data @noDefault -ultimatedata /tmp/vcloud-vcloud-master/worker/working_dir_3d9fc5bc-d65d-4259-979e-2e9bddd7decc/bin-2019/uautomizer/data -tc /tmp/vcloud-vcloud-master/worker/working_dir_3d9fc5bc-d65d-4259-979e-2e9bddd7decc/bin-2019/uautomizer/config/AutomizerMemDerefMemtrack.xml -i ../../sv-benchmarks/c/memsafety-ext3/getNumbers4_false-valid-deref.c -s /tmp/vcloud-vcloud-master/worker/working_dir_3d9fc5bc-d65d-4259-979e-2e9bddd7decc/bin-2019/uautomizer/config/svcomp-DerefFreeMemtrack-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud-vcloud-master/worker/working_dir_3d9fc5bc-d65d-4259-979e-2e9bddd7decc/bin-2019/uautomizer --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(G valid-free) ) CHECK( init(main()), LTL(G valid-deref) ) CHECK( init(main()), LTL(G valid-memtrack) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash 440325a953e10d2173456ab8f8c8fc1313a6b958 ...................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................... Execution finished normally Writing output log to file Ultimate.log Writing human readable error path to file UltimateCounterExample.errorpath Result: FALSE(valid-deref) --- Real Ultimate output --- This is Ultimate 0.1.23-0cd3be1 [2018-11-28 11:42:43,931 INFO L170 SettingsManager]: Resetting all preferences to default values... [2018-11-28 11:42:43,932 INFO L174 SettingsManager]: Resetting UltimateCore preferences to default values [2018-11-28 11:42:43,940 INFO L177 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2018-11-28 11:42:43,940 INFO L174 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2018-11-28 11:42:43,941 INFO L174 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2018-11-28 11:42:43,941 INFO L174 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2018-11-28 11:42:43,943 INFO L174 SettingsManager]: Resetting LassoRanker preferences to default values [2018-11-28 11:42:43,944 INFO L174 SettingsManager]: Resetting Reaching Definitions preferences to default values [2018-11-28 11:42:43,944 INFO L174 SettingsManager]: Resetting SyntaxChecker preferences to default values [2018-11-28 11:42:43,945 INFO L177 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2018-11-28 11:42:43,945 INFO L174 SettingsManager]: Resetting LTL2Aut preferences to default values [2018-11-28 11:42:43,945 INFO L174 SettingsManager]: Resetting PEA to Boogie preferences to default values [2018-11-28 11:42:43,946 INFO L174 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2018-11-28 11:42:43,947 INFO L174 SettingsManager]: Resetting ChcToBoogie preferences to default values [2018-11-28 11:42:43,947 INFO L174 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2018-11-28 11:42:43,948 INFO L174 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2018-11-28 11:42:43,949 INFO L174 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2018-11-28 11:42:43,950 INFO L174 SettingsManager]: Resetting CodeCheck preferences to default values [2018-11-28 11:42:43,951 INFO L174 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2018-11-28 11:42:43,952 INFO L174 SettingsManager]: Resetting RCFGBuilder preferences to default values [2018-11-28 11:42:43,953 INFO L174 SettingsManager]: Resetting TraceAbstraction preferences to default values [2018-11-28 11:42:43,954 INFO L177 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2018-11-28 11:42:43,954 INFO L177 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2018-11-28 11:42:43,954 INFO L174 SettingsManager]: Resetting TreeAutomizer preferences to default values [2018-11-28 11:42:43,955 INFO L174 SettingsManager]: Resetting IcfgTransformer preferences to default values [2018-11-28 11:42:43,955 INFO L174 SettingsManager]: Resetting Boogie Printer preferences to default values [2018-11-28 11:42:43,956 INFO L174 SettingsManager]: Resetting ReqPrinter preferences to default values [2018-11-28 11:42:43,957 INFO L174 SettingsManager]: Resetting Witness Printer preferences to default values [2018-11-28 11:42:43,957 INFO L177 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2018-11-28 11:42:43,957 INFO L174 SettingsManager]: Resetting CDTParser preferences to default values [2018-11-28 11:42:43,958 INFO L177 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2018-11-28 11:42:43,958 INFO L177 SettingsManager]: ReqParser provides no preferences, ignoring... [2018-11-28 11:42:43,958 INFO L174 SettingsManager]: Resetting SmtParser preferences to default values [2018-11-28 11:42:43,959 INFO L174 SettingsManager]: Resetting Witness Parser preferences to default values [2018-11-28 11:42:43,959 INFO L181 SettingsManager]: Finished resetting all preferences to default values... [2018-11-28 11:42:43,959 INFO L98 SettingsManager]: Beginning loading settings from /tmp/vcloud-vcloud-master/worker/working_dir_3d9fc5bc-d65d-4259-979e-2e9bddd7decc/bin-2019/uautomizer/config/svcomp-DerefFreeMemtrack-32bit-Automizer_Default.epf [2018-11-28 11:42:43,967 INFO L110 SettingsManager]: Loading preferences was successful [2018-11-28 11:42:43,967 INFO L112 SettingsManager]: Preferences different from defaults after loading the file: [2018-11-28 11:42:43,968 INFO L131 SettingsManager]: Preferences of Boogie Procedure Inliner differ from their defaults: [2018-11-28 11:42:43,968 INFO L133 SettingsManager]: * ... calls to implemented procedures=ONLY_FOR_CONCURRENT_PROGRAMS [2018-11-28 11:42:43,968 INFO L131 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2018-11-28 11:42:43,968 INFO L133 SettingsManager]: * Create parallel compositions if possible=false [2018-11-28 11:42:43,969 INFO L133 SettingsManager]: * Use SBE=true [2018-11-28 11:42:43,969 INFO L131 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2018-11-28 11:42:43,969 INFO L133 SettingsManager]: * sizeof long=4 [2018-11-28 11:42:43,969 INFO L133 SettingsManager]: * Check unreachability of error function in SV-COMP mode=false [2018-11-28 11:42:43,969 INFO L133 SettingsManager]: * Overapproximate operations on floating types=true [2018-11-28 11:42:43,969 INFO L133 SettingsManager]: * sizeof POINTER=4 [2018-11-28 11:42:43,970 INFO L133 SettingsManager]: * Check division by zero=IGNORE [2018-11-28 11:42:43,970 INFO L133 SettingsManager]: * Check for the main procedure if all allocated memory was freed=true [2018-11-28 11:42:43,970 INFO L133 SettingsManager]: * Bitprecise bitfields=true [2018-11-28 11:42:43,970 INFO L133 SettingsManager]: * SV-COMP memtrack compatibility mode=true [2018-11-28 11:42:43,970 INFO L133 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=IGNORE [2018-11-28 11:42:43,970 INFO L133 SettingsManager]: * sizeof long double=12 [2018-11-28 11:42:43,970 INFO L133 SettingsManager]: * Use constant arrays=true [2018-11-28 11:42:43,971 INFO L131 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2018-11-28 11:42:43,971 INFO L133 SettingsManager]: * Size of a code block=SequenceOfStatements [2018-11-28 11:42:43,971 INFO L133 SettingsManager]: * To the following directory=./dump/ [2018-11-28 11:42:43,971 INFO L133 SettingsManager]: * SMT solver=External_DefaultMode [2018-11-28 11:42:43,971 INFO L133 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2018-11-28 11:42:43,971 INFO L131 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2018-11-28 11:42:43,972 INFO L133 SettingsManager]: * Compute Interpolants along a Counterexample=FPandBP [2018-11-28 11:42:43,972 INFO L133 SettingsManager]: * Trace refinement strategy=CAMEL [2018-11-28 11:42:43,972 INFO L133 SettingsManager]: * SMT solver=External_ModelsAndUnsatCoreMode [2018-11-28 11:42:43,972 INFO L133 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud-vcloud-master/worker/working_dir_3d9fc5bc-d65d-4259-979e-2e9bddd7decc/bin-2019/uautomizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(G valid-free) ) CHECK( init(main()), LTL(G valid-deref) ) CHECK( init(main()), LTL(G valid-memtrack) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> 440325a953e10d2173456ab8f8c8fc1313a6b958 [2018-11-28 11:42:43,996 INFO L81 nceAwareModelManager]: Repository-Root is: /tmp [2018-11-28 11:42:44,005 INFO L258 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2018-11-28 11:42:44,008 INFO L214 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2018-11-28 11:42:44,009 INFO L271 PluginConnector]: Initializing CDTParser... [2018-11-28 11:42:44,009 INFO L276 PluginConnector]: CDTParser initialized [2018-11-28 11:42:44,009 INFO L418 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud-vcloud-master/worker/working_dir_3d9fc5bc-d65d-4259-979e-2e9bddd7decc/bin-2019/uautomizer/../../sv-benchmarks/c/memsafety-ext3/getNumbers4_false-valid-deref.c [2018-11-28 11:42:44,047 INFO L221 CDTParser]: Created temporary CDT project at /tmp/vcloud-vcloud-master/worker/working_dir_3d9fc5bc-d65d-4259-979e-2e9bddd7decc/bin-2019/uautomizer/data/de79af8a7/5d6fe44074514459b98998970936fb8b/FLAG638bbe267 [2018-11-28 11:42:44,433 INFO L307 CDTParser]: Found 1 translation units. [2018-11-28 11:42:44,434 INFO L161 CDTParser]: Scanning /tmp/vcloud-vcloud-master/worker/working_dir_3d9fc5bc-d65d-4259-979e-2e9bddd7decc/sv-benchmarks/c/memsafety-ext3/getNumbers4_false-valid-deref.c [2018-11-28 11:42:44,437 INFO L355 CDTParser]: About to delete temporary CDT project at /tmp/vcloud-vcloud-master/worker/working_dir_3d9fc5bc-d65d-4259-979e-2e9bddd7decc/bin-2019/uautomizer/data/de79af8a7/5d6fe44074514459b98998970936fb8b/FLAG638bbe267 [2018-11-28 11:42:44,447 INFO L363 CDTParser]: Successfully deleted /tmp/vcloud-vcloud-master/worker/working_dir_3d9fc5bc-d65d-4259-979e-2e9bddd7decc/bin-2019/uautomizer/data/de79af8a7/5d6fe44074514459b98998970936fb8b [2018-11-28 11:42:44,449 INFO L296 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2018-11-28 11:42:44,450 INFO L131 ToolchainWalker]: Walking toolchain with 5 elements. [2018-11-28 11:42:44,451 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2018-11-28 11:42:44,451 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2018-11-28 11:42:44,453 INFO L276 PluginConnector]: CACSL2BoogieTranslator initialized [2018-11-28 11:42:44,453 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 28.11 11:42:44" (1/1) ... [2018-11-28 11:42:44,455 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@5e49336c and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 11:42:44, skipping insertion in model container [2018-11-28 11:42:44,455 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 28.11 11:42:44" (1/1) ... [2018-11-28 11:42:44,461 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2018-11-28 11:42:44,474 INFO L176 MainTranslator]: Built tables and reachable declarations [2018-11-28 11:42:44,570 INFO L203 PostProcessor]: Analyzing one entry point: main [2018-11-28 11:42:44,578 INFO L191 MainTranslator]: Completed pre-run [2018-11-28 11:42:44,591 INFO L203 PostProcessor]: Analyzing one entry point: main [2018-11-28 11:42:44,603 INFO L195 MainTranslator]: Completed translation [2018-11-28 11:42:44,603 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 11:42:44 WrapperNode [2018-11-28 11:42:44,603 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2018-11-28 11:42:44,604 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2018-11-28 11:42:44,604 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2018-11-28 11:42:44,604 INFO L276 PluginConnector]: Boogie Preprocessor initialized [2018-11-28 11:42:44,611 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 11:42:44" (1/1) ... [2018-11-28 11:42:44,611 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 11:42:44" (1/1) ... [2018-11-28 11:42:44,656 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 11:42:44" (1/1) ... [2018-11-28 11:42:44,656 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 11:42:44" (1/1) ... [2018-11-28 11:42:44,665 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 11:42:44" (1/1) ... [2018-11-28 11:42:44,670 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 11:42:44" (1/1) ... [2018-11-28 11:42:44,671 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 11:42:44" (1/1) ... [2018-11-28 11:42:44,673 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2018-11-28 11:42:44,674 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2018-11-28 11:42:44,674 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2018-11-28 11:42:44,674 INFO L276 PluginConnector]: RCFGBuilder initialized [2018-11-28 11:42:44,675 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 11:42:44" (1/1) ... No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_3d9fc5bc-d65d-4259-979e-2e9bddd7decc/bin-2019/uautomizer/z3 Starting monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2018-11-28 11:42:44,719 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.init [2018-11-28 11:42:44,719 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2018-11-28 11:42:44,719 INFO L138 BoogieDeclarations]: Found implementation of procedure getNumbers [2018-11-28 11:42:44,719 INFO L138 BoogieDeclarations]: Found implementation of procedure getNumbers2 [2018-11-28 11:42:44,719 INFO L138 BoogieDeclarations]: Found implementation of procedure getNumbers3 [2018-11-28 11:42:44,720 INFO L138 BoogieDeclarations]: Found implementation of procedure getNumbers4 [2018-11-28 11:42:44,720 INFO L138 BoogieDeclarations]: Found implementation of procedure main [2018-11-28 11:42:44,720 INFO L130 BoogieDeclarations]: Found specification of procedure printf [2018-11-28 11:42:44,720 INFO L130 BoogieDeclarations]: Found specification of procedure getNumbers [2018-11-28 11:42:44,720 INFO L130 BoogieDeclarations]: Found specification of procedure write~int [2018-11-28 11:42:44,720 INFO L130 BoogieDeclarations]: Found specification of procedure getNumbers2 [2018-11-28 11:42:44,720 INFO L130 BoogieDeclarations]: Found specification of procedure read~int [2018-11-28 11:42:44,720 INFO L130 BoogieDeclarations]: Found specification of procedure getNumbers3 [2018-11-28 11:42:44,720 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.alloc [2018-11-28 11:42:44,721 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.dealloc [2018-11-28 11:42:44,721 INFO L130 BoogieDeclarations]: Found specification of procedure getNumbers4 [2018-11-28 11:42:44,721 INFO L130 BoogieDeclarations]: Found specification of procedure main [2018-11-28 11:42:44,721 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.init [2018-11-28 11:42:44,721 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int [2018-11-28 11:42:44,721 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2018-11-28 11:42:45,040 INFO L275 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2018-11-28 11:42:45,040 INFO L280 CfgBuilder]: Removed 5 assue(true) statements. [2018-11-28 11:42:45,040 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 28.11 11:42:45 BoogieIcfgContainer [2018-11-28 11:42:45,040 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2018-11-28 11:42:45,041 INFO L113 PluginConnector]: ------------------------TraceAbstraction---------------------------- [2018-11-28 11:42:45,041 INFO L271 PluginConnector]: Initializing TraceAbstraction... [2018-11-28 11:42:45,043 INFO L276 PluginConnector]: TraceAbstraction initialized [2018-11-28 11:42:45,043 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "CDTParser AST 28.11 11:42:44" (1/3) ... [2018-11-28 11:42:45,044 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@1b579e42 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 28.11 11:42:45, skipping insertion in model container [2018-11-28 11:42:45,044 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 11:42:44" (2/3) ... [2018-11-28 11:42:45,044 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@1b579e42 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 28.11 11:42:45, skipping insertion in model container [2018-11-28 11:42:45,044 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 28.11 11:42:45" (3/3) ... [2018-11-28 11:42:45,045 INFO L112 eAbstractionObserver]: Analyzing ICFG getNumbers4_false-valid-deref.c [2018-11-28 11:42:45,051 INFO L156 ceAbstractionStarter]: Automizer settings: Hoare:false NWA Interpolation:FPandBP Determinization: PREDICATE_ABSTRACTION [2018-11-28 11:42:45,055 INFO L168 ceAbstractionStarter]: Appying trace abstraction to program that has 17 error locations. [2018-11-28 11:42:45,067 INFO L257 AbstractCegarLoop]: Starting to check reachability of 17 error locations. [2018-11-28 11:42:45,087 INFO L133 ementStrategyFactory]: Using default assertion order modulation [2018-11-28 11:42:45,088 INFO L382 AbstractCegarLoop]: Interprodecural is true [2018-11-28 11:42:45,088 INFO L383 AbstractCegarLoop]: Hoare is false [2018-11-28 11:42:45,088 INFO L384 AbstractCegarLoop]: Compute interpolants for FPandBP [2018-11-28 11:42:45,088 INFO L385 AbstractCegarLoop]: Backedges is STRAIGHT_LINE [2018-11-28 11:42:45,088 INFO L386 AbstractCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2018-11-28 11:42:45,088 INFO L387 AbstractCegarLoop]: Difference is false [2018-11-28 11:42:45,088 INFO L388 AbstractCegarLoop]: Minimize is MINIMIZE_SEVPA [2018-11-28 11:42:45,089 INFO L393 AbstractCegarLoop]: ======== Iteration 0==of CEGAR loop == AllErrorsAtOnce======== [2018-11-28 11:42:45,100 INFO L276 IsEmpty]: Start isEmpty. Operand 70 states. [2018-11-28 11:42:45,105 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 13 [2018-11-28 11:42:45,105 INFO L394 BasicCegarLoop]: Found error trace [2018-11-28 11:42:45,106 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-28 11:42:45,107 INFO L423 AbstractCegarLoop]: === Iteration 1 === [getNumbers3Err0REQUIRES_VIOLATION, getNumbers3Err2REQUIRES_VIOLATION, getNumbers3Err1REQUIRES_VIOLATION, getNumbers3Err3REQUIRES_VIOLATION, getNumbers2Err2REQUIRES_VIOLATION, getNumbers2Err1REQUIRES_VIOLATION, getNumbers2Err3REQUIRES_VIOLATION, getNumbers2Err0REQUIRES_VIOLATION, getNumbers4Err2REQUIRES_VIOLATION, getNumbers4Err1REQUIRES_VIOLATION, getNumbers4Err3REQUIRES_VIOLATION, getNumbers4Err0REQUIRES_VIOLATION, mainErr2ENSURES_VIOLATIONMEMORY_LEAK, mainErr1REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION, getNumbersErr1REQUIRES_VIOLATION, getNumbersErr0REQUIRES_VIOLATION]=== [2018-11-28 11:42:45,110 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-28 11:42:45,110 INFO L82 PathProgramCache]: Analyzing trace with hash 1833468390, now seen corresponding path program 1 times [2018-11-28 11:42:45,111 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-28 11:42:45,111 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-28 11:42:45,140 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 11:42:45,140 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-28 11:42:45,140 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 11:42:45,187 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-28 11:42:45,257 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-28 11:42:45,258 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-28 11:42:45,259 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2018-11-28 11:42:45,261 INFO L459 AbstractCegarLoop]: Interpolant automaton has 3 states [2018-11-28 11:42:45,268 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-28 11:42:45,269 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-28 11:42:45,270 INFO L87 Difference]: Start difference. First operand 70 states. Second operand 3 states. [2018-11-28 11:42:45,345 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-28 11:42:45,345 INFO L93 Difference]: Finished difference Result 69 states and 73 transitions. [2018-11-28 11:42:45,345 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-28 11:42:45,346 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 12 [2018-11-28 11:42:45,347 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-28 11:42:45,354 INFO L225 Difference]: With dead ends: 69 [2018-11-28 11:42:45,354 INFO L226 Difference]: Without dead ends: 66 [2018-11-28 11:42:45,356 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 5 GetRequests, 4 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-28 11:42:45,370 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 66 states. [2018-11-28 11:42:45,383 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 66 to 66. [2018-11-28 11:42:45,384 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 66 states. [2018-11-28 11:42:45,386 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 66 states to 66 states and 70 transitions. [2018-11-28 11:42:45,387 INFO L78 Accepts]: Start accepts. Automaton has 66 states and 70 transitions. Word has length 12 [2018-11-28 11:42:45,387 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-28 11:42:45,387 INFO L480 AbstractCegarLoop]: Abstraction has 66 states and 70 transitions. [2018-11-28 11:42:45,387 INFO L481 AbstractCegarLoop]: Interpolant automaton has 3 states. [2018-11-28 11:42:45,387 INFO L276 IsEmpty]: Start isEmpty. Operand 66 states and 70 transitions. [2018-11-28 11:42:45,387 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 13 [2018-11-28 11:42:45,388 INFO L394 BasicCegarLoop]: Found error trace [2018-11-28 11:42:45,388 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-28 11:42:45,388 INFO L423 AbstractCegarLoop]: === Iteration 2 === [getNumbers3Err0REQUIRES_VIOLATION, getNumbers3Err2REQUIRES_VIOLATION, getNumbers3Err1REQUIRES_VIOLATION, getNumbers3Err3REQUIRES_VIOLATION, getNumbers2Err2REQUIRES_VIOLATION, getNumbers2Err1REQUIRES_VIOLATION, getNumbers2Err3REQUIRES_VIOLATION, getNumbers2Err0REQUIRES_VIOLATION, getNumbers4Err2REQUIRES_VIOLATION, getNumbers4Err1REQUIRES_VIOLATION, getNumbers4Err3REQUIRES_VIOLATION, getNumbers4Err0REQUIRES_VIOLATION, mainErr2ENSURES_VIOLATIONMEMORY_LEAK, mainErr1REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION, getNumbersErr1REQUIRES_VIOLATION, getNumbersErr0REQUIRES_VIOLATION]=== [2018-11-28 11:42:45,388 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-28 11:42:45,388 INFO L82 PathProgramCache]: Analyzing trace with hash 1833468391, now seen corresponding path program 1 times [2018-11-28 11:42:45,388 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-28 11:42:45,388 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-28 11:42:45,389 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 11:42:45,389 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-28 11:42:45,389 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 11:42:45,409 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-28 11:42:45,520 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-28 11:42:45,521 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-28 11:42:45,521 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-28 11:42:45,522 INFO L459 AbstractCegarLoop]: Interpolant automaton has 4 states [2018-11-28 11:42:45,522 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2018-11-28 11:42:45,522 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=6, Invalid=6, Unknown=0, NotChecked=0, Total=12 [2018-11-28 11:42:45,522 INFO L87 Difference]: Start difference. First operand 66 states and 70 transitions. Second operand 4 states. [2018-11-28 11:42:45,607 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-28 11:42:45,607 INFO L93 Difference]: Finished difference Result 69 states and 73 transitions. [2018-11-28 11:42:45,608 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2018-11-28 11:42:45,608 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 12 [2018-11-28 11:42:45,608 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-28 11:42:45,609 INFO L225 Difference]: With dead ends: 69 [2018-11-28 11:42:45,609 INFO L226 Difference]: Without dead ends: 69 [2018-11-28 11:42:45,610 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 6 GetRequests, 3 SyntacticMatches, 1 SemanticMatches, 2 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=6, Invalid=6, Unknown=0, NotChecked=0, Total=12 [2018-11-28 11:42:45,610 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 69 states. [2018-11-28 11:42:45,614 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 69 to 68. [2018-11-28 11:42:45,614 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 68 states. [2018-11-28 11:42:45,615 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 68 states to 68 states and 72 transitions. [2018-11-28 11:42:45,615 INFO L78 Accepts]: Start accepts. Automaton has 68 states and 72 transitions. Word has length 12 [2018-11-28 11:42:45,615 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-28 11:42:45,615 INFO L480 AbstractCegarLoop]: Abstraction has 68 states and 72 transitions. [2018-11-28 11:42:45,615 INFO L481 AbstractCegarLoop]: Interpolant automaton has 4 states. [2018-11-28 11:42:45,616 INFO L276 IsEmpty]: Start isEmpty. Operand 68 states and 72 transitions. [2018-11-28 11:42:45,616 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 16 [2018-11-28 11:42:45,616 INFO L394 BasicCegarLoop]: Found error trace [2018-11-28 11:42:45,616 INFO L402 BasicCegarLoop]: trace histogram [2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-28 11:42:45,616 INFO L423 AbstractCegarLoop]: === Iteration 3 === [getNumbers3Err0REQUIRES_VIOLATION, getNumbers3Err2REQUIRES_VIOLATION, getNumbers3Err1REQUIRES_VIOLATION, getNumbers3Err3REQUIRES_VIOLATION, getNumbers2Err2REQUIRES_VIOLATION, getNumbers2Err1REQUIRES_VIOLATION, getNumbers2Err3REQUIRES_VIOLATION, getNumbers2Err0REQUIRES_VIOLATION, getNumbers4Err2REQUIRES_VIOLATION, getNumbers4Err1REQUIRES_VIOLATION, getNumbers4Err3REQUIRES_VIOLATION, getNumbers4Err0REQUIRES_VIOLATION, mainErr2ENSURES_VIOLATIONMEMORY_LEAK, mainErr1REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION, getNumbersErr1REQUIRES_VIOLATION, getNumbersErr0REQUIRES_VIOLATION]=== [2018-11-28 11:42:45,616 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-28 11:42:45,617 INFO L82 PathProgramCache]: Analyzing trace with hash 1757784526, now seen corresponding path program 1 times [2018-11-28 11:42:45,617 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-28 11:42:45,617 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-28 11:42:45,618 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 11:42:45,618 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-28 11:42:45,618 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 11:42:45,631 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-28 11:42:45,723 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-28 11:42:45,723 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-28 11:42:45,723 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_3d9fc5bc-d65d-4259-979e-2e9bddd7decc/bin-2019/uautomizer/z3 Starting monitored process 2 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 2 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-28 11:42:45,731 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-28 11:42:45,753 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-28 11:42:45,760 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-28 11:42:45,797 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 18 [2018-11-28 11:42:45,801 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:42:45,802 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 18 treesize of output 24 [2018-11-28 11:42:45,809 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:42:45,810 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:42:45,811 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 2 select indices, 2 select index equivalence classes, 3 disjoint index pairs (out of 1 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 20 treesize of output 34 [2018-11-28 11:42:45,835 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:42:45,836 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:42:45,837 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:42:45,837 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:42:45,838 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 3 select indices, 3 select index equivalence classes, 7 disjoint index pairs (out of 3 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 22 treesize of output 51 [2018-11-28 11:42:45,839 INFO L267 ElimStorePlain]: Start of recursive call 5: End of recursive call: and 1 xjuncts. [2018-11-28 11:42:45,855 INFO L267 ElimStorePlain]: Start of recursive call 4: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-28 11:42:45,870 INFO L267 ElimStorePlain]: Start of recursive call 3: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-28 11:42:45,875 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-28 11:42:45,889 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 43 treesize of output 39 [2018-11-28 11:42:45,901 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:42:45,907 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 2 select indices, 2 select index equivalence classes, 2 disjoint index pairs (out of 1 index pairs), introduced 1 new quantified variables, introduced 2 case distinctions, treesize of input 36 treesize of output 49 [2018-11-28 11:42:45,954 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:42:45,956 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:42:45,958 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:42:45,964 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 4 select indices, 4 select index equivalence classes, 5 disjoint index pairs (out of 6 index pairs), introduced 1 new quantified variables, introduced 2 case distinctions, treesize of input 36 treesize of output 57 [2018-11-28 11:42:46,015 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:42:46,016 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:42:46,017 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:42:46,018 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:42:46,019 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:42:46,020 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 4 select indices, 4 select index equivalence classes, 7 disjoint index pairs (out of 6 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 32 treesize of output 36 [2018-11-28 11:42:46,020 INFO L267 ElimStorePlain]: Start of recursive call 9: End of recursive call: and 1 xjuncts. [2018-11-28 11:42:46,045 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:42:46,047 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:42:46,048 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:42:46,050 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:42:46,051 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:42:46,052 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:42:46,053 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:42:46,054 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:42:46,055 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 5 select indices, 5 select index equivalence classes, 9 disjoint index pairs (out of 10 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 26 treesize of output 33 [2018-11-28 11:42:46,055 INFO L267 ElimStorePlain]: Start of recursive call 10: End of recursive call: and 1 xjuncts. [2018-11-28 11:42:46,067 INFO L267 ElimStorePlain]: Start of recursive call 8: 2 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-28 11:42:46,083 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:42:46,083 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:42:46,084 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 3 select indices, 3 select index equivalence classes, 4 disjoint index pairs (out of 3 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 31 treesize of output 44 [2018-11-28 11:42:46,111 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:42:46,111 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:42:46,112 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:42:46,113 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:42:46,113 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:42:46,114 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 4 select indices, 4 select index equivalence classes, 7 disjoint index pairs (out of 6 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 21 treesize of output 25 [2018-11-28 11:42:46,115 INFO L267 ElimStorePlain]: Start of recursive call 12: End of recursive call: and 1 xjuncts. [2018-11-28 11:42:46,123 INFO L267 ElimStorePlain]: Start of recursive call 11: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-28 11:42:46,130 INFO L267 ElimStorePlain]: Start of recursive call 7: 2 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-28 11:42:46,133 INFO L267 ElimStorePlain]: Start of recursive call 6: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-28 11:42:46,141 INFO L267 ElimStorePlain]: Start of recursive call 1: 3 dim-0 vars, 2 dim-1 vars, End of recursive call: 3 dim-0 vars, and 1 xjuncts. [2018-11-28 11:42:46,142 INFO L202 ElimStorePlain]: Needed 12 recursive calls to eliminate 5 variables, input treesize:61, output treesize:36 [2018-11-28 11:42:46,234 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-28 11:42:46,249 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-11-28 11:42:46,249 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [6, 4] total 9 [2018-11-28 11:42:46,249 INFO L459 AbstractCegarLoop]: Interpolant automaton has 10 states [2018-11-28 11:42:46,249 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 10 interpolants. [2018-11-28 11:42:46,250 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=32, Invalid=58, Unknown=0, NotChecked=0, Total=90 [2018-11-28 11:42:46,250 INFO L87 Difference]: Start difference. First operand 68 states and 72 transitions. Second operand 10 states. [2018-11-28 11:42:46,405 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-28 11:42:46,406 INFO L93 Difference]: Finished difference Result 72 states and 76 transitions. [2018-11-28 11:42:46,406 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 8 states. [2018-11-28 11:42:46,406 INFO L78 Accepts]: Start accepts. Automaton has 10 states. Word has length 15 [2018-11-28 11:42:46,406 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-28 11:42:46,407 INFO L225 Difference]: With dead ends: 72 [2018-11-28 11:42:46,407 INFO L226 Difference]: Without dead ends: 72 [2018-11-28 11:42:46,407 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 25 GetRequests, 14 SyntacticMatches, 1 SemanticMatches, 10 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 15 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=50, Invalid=82, Unknown=0, NotChecked=0, Total=132 [2018-11-28 11:42:46,407 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 72 states. [2018-11-28 11:42:46,410 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 72 to 72. [2018-11-28 11:42:46,410 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 72 states. [2018-11-28 11:42:46,411 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 72 states to 72 states and 76 transitions. [2018-11-28 11:42:46,411 INFO L78 Accepts]: Start accepts. Automaton has 72 states and 76 transitions. Word has length 15 [2018-11-28 11:42:46,411 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-28 11:42:46,411 INFO L480 AbstractCegarLoop]: Abstraction has 72 states and 76 transitions. [2018-11-28 11:42:46,411 INFO L481 AbstractCegarLoop]: Interpolant automaton has 10 states. [2018-11-28 11:42:46,412 INFO L276 IsEmpty]: Start isEmpty. Operand 72 states and 76 transitions. [2018-11-28 11:42:46,412 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 27 [2018-11-28 11:42:46,412 INFO L394 BasicCegarLoop]: Found error trace [2018-11-28 11:42:46,412 INFO L402 BasicCegarLoop]: trace histogram [3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-28 11:42:46,412 INFO L423 AbstractCegarLoop]: === Iteration 4 === [getNumbers3Err0REQUIRES_VIOLATION, getNumbers3Err2REQUIRES_VIOLATION, getNumbers3Err1REQUIRES_VIOLATION, getNumbers3Err3REQUIRES_VIOLATION, getNumbers2Err2REQUIRES_VIOLATION, getNumbers2Err1REQUIRES_VIOLATION, getNumbers2Err3REQUIRES_VIOLATION, getNumbers2Err0REQUIRES_VIOLATION, getNumbers4Err2REQUIRES_VIOLATION, getNumbers4Err1REQUIRES_VIOLATION, getNumbers4Err3REQUIRES_VIOLATION, getNumbers4Err0REQUIRES_VIOLATION, mainErr2ENSURES_VIOLATIONMEMORY_LEAK, mainErr1REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION, getNumbersErr1REQUIRES_VIOLATION, getNumbersErr0REQUIRES_VIOLATION]=== [2018-11-28 11:42:46,413 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-28 11:42:46,413 INFO L82 PathProgramCache]: Analyzing trace with hash -16477363, now seen corresponding path program 1 times [2018-11-28 11:42:46,413 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-28 11:42:46,413 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-28 11:42:46,414 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 11:42:46,414 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-28 11:42:46,414 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 11:42:46,425 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-28 11:42:46,482 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 5 proven. 0 refuted. 0 times theorem prover too weak. 7 trivial. 0 not checked. [2018-11-28 11:42:46,482 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-28 11:42:46,482 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-11-28 11:42:46,483 INFO L459 AbstractCegarLoop]: Interpolant automaton has 6 states [2018-11-28 11:42:46,483 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2018-11-28 11:42:46,483 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=10, Invalid=20, Unknown=0, NotChecked=0, Total=30 [2018-11-28 11:42:46,483 INFO L87 Difference]: Start difference. First operand 72 states and 76 transitions. Second operand 6 states. [2018-11-28 11:42:46,558 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-28 11:42:46,558 INFO L93 Difference]: Finished difference Result 71 states and 75 transitions. [2018-11-28 11:42:46,559 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2018-11-28 11:42:46,559 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 26 [2018-11-28 11:42:46,559 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-28 11:42:46,560 INFO L225 Difference]: With dead ends: 71 [2018-11-28 11:42:46,560 INFO L226 Difference]: Without dead ends: 71 [2018-11-28 11:42:46,560 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 7 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 6 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 3 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=18, Invalid=38, Unknown=0, NotChecked=0, Total=56 [2018-11-28 11:42:46,560 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 71 states. [2018-11-28 11:42:46,563 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 71 to 71. [2018-11-28 11:42:46,563 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 71 states. [2018-11-28 11:42:46,564 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 71 states to 71 states and 75 transitions. [2018-11-28 11:42:46,564 INFO L78 Accepts]: Start accepts. Automaton has 71 states and 75 transitions. Word has length 26 [2018-11-28 11:42:46,565 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-28 11:42:46,565 INFO L480 AbstractCegarLoop]: Abstraction has 71 states and 75 transitions. [2018-11-28 11:42:46,565 INFO L481 AbstractCegarLoop]: Interpolant automaton has 6 states. [2018-11-28 11:42:46,565 INFO L276 IsEmpty]: Start isEmpty. Operand 71 states and 75 transitions. [2018-11-28 11:42:46,565 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 27 [2018-11-28 11:42:46,566 INFO L394 BasicCegarLoop]: Found error trace [2018-11-28 11:42:46,566 INFO L402 BasicCegarLoop]: trace histogram [3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-28 11:42:46,568 INFO L423 AbstractCegarLoop]: === Iteration 5 === [getNumbers3Err0REQUIRES_VIOLATION, getNumbers3Err2REQUIRES_VIOLATION, getNumbers3Err1REQUIRES_VIOLATION, getNumbers3Err3REQUIRES_VIOLATION, getNumbers2Err2REQUIRES_VIOLATION, getNumbers2Err1REQUIRES_VIOLATION, getNumbers2Err3REQUIRES_VIOLATION, getNumbers2Err0REQUIRES_VIOLATION, getNumbers4Err2REQUIRES_VIOLATION, getNumbers4Err1REQUIRES_VIOLATION, getNumbers4Err3REQUIRES_VIOLATION, getNumbers4Err0REQUIRES_VIOLATION, mainErr2ENSURES_VIOLATIONMEMORY_LEAK, mainErr1REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION, getNumbersErr1REQUIRES_VIOLATION, getNumbersErr0REQUIRES_VIOLATION]=== [2018-11-28 11:42:46,568 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-28 11:42:46,568 INFO L82 PathProgramCache]: Analyzing trace with hash -16477362, now seen corresponding path program 1 times [2018-11-28 11:42:46,568 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-28 11:42:46,568 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-28 11:42:46,569 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 11:42:46,569 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-28 11:42:46,569 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 11:42:46,579 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-28 11:42:46,618 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 0 proven. 12 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-28 11:42:46,619 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-28 11:42:46,619 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_3d9fc5bc-d65d-4259-979e-2e9bddd7decc/bin-2019/uautomizer/z3 Starting monitored process 3 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 3 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-28 11:42:46,625 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-28 11:42:46,645 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-28 11:42:46,647 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-28 11:42:46,654 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 0 proven. 12 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-28 11:42:46,668 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-11-28 11:42:46,669 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [6, 6] total 7 [2018-11-28 11:42:46,669 INFO L459 AbstractCegarLoop]: Interpolant automaton has 7 states [2018-11-28 11:42:46,669 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2018-11-28 11:42:46,669 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=21, Invalid=21, Unknown=0, NotChecked=0, Total=42 [2018-11-28 11:42:46,669 INFO L87 Difference]: Start difference. First operand 71 states and 75 transitions. Second operand 7 states. [2018-11-28 11:42:46,685 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-28 11:42:46,685 INFO L93 Difference]: Finished difference Result 76 states and 80 transitions. [2018-11-28 11:42:46,692 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2018-11-28 11:42:46,692 INFO L78 Accepts]: Start accepts. Automaton has 7 states. Word has length 26 [2018-11-28 11:42:46,692 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-28 11:42:46,693 INFO L225 Difference]: With dead ends: 76 [2018-11-28 11:42:46,693 INFO L226 Difference]: Without dead ends: 76 [2018-11-28 11:42:46,693 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 31 GetRequests, 26 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 4 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=21, Invalid=21, Unknown=0, NotChecked=0, Total=42 [2018-11-28 11:42:46,694 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 76 states. [2018-11-28 11:42:46,696 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 76 to 74. [2018-11-28 11:42:46,697 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 74 states. [2018-11-28 11:42:46,697 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 74 states to 74 states and 78 transitions. [2018-11-28 11:42:46,698 INFO L78 Accepts]: Start accepts. Automaton has 74 states and 78 transitions. Word has length 26 [2018-11-28 11:42:46,698 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-28 11:42:46,698 INFO L480 AbstractCegarLoop]: Abstraction has 74 states and 78 transitions. [2018-11-28 11:42:46,698 INFO L481 AbstractCegarLoop]: Interpolant automaton has 7 states. [2018-11-28 11:42:46,698 INFO L276 IsEmpty]: Start isEmpty. Operand 74 states and 78 transitions. [2018-11-28 11:42:46,699 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 30 [2018-11-28 11:42:46,699 INFO L394 BasicCegarLoop]: Found error trace [2018-11-28 11:42:46,699 INFO L402 BasicCegarLoop]: trace histogram [4, 4, 4, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-28 11:42:46,699 INFO L423 AbstractCegarLoop]: === Iteration 6 === [getNumbers3Err0REQUIRES_VIOLATION, getNumbers3Err2REQUIRES_VIOLATION, getNumbers3Err1REQUIRES_VIOLATION, getNumbers3Err3REQUIRES_VIOLATION, getNumbers2Err2REQUIRES_VIOLATION, getNumbers2Err1REQUIRES_VIOLATION, getNumbers2Err3REQUIRES_VIOLATION, getNumbers2Err0REQUIRES_VIOLATION, getNumbers4Err2REQUIRES_VIOLATION, getNumbers4Err1REQUIRES_VIOLATION, getNumbers4Err3REQUIRES_VIOLATION, getNumbers4Err0REQUIRES_VIOLATION, mainErr2ENSURES_VIOLATIONMEMORY_LEAK, mainErr1REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION, getNumbersErr1REQUIRES_VIOLATION, getNumbersErr0REQUIRES_VIOLATION]=== [2018-11-28 11:42:46,699 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-28 11:42:46,699 INFO L82 PathProgramCache]: Analyzing trace with hash 502160117, now seen corresponding path program 2 times [2018-11-28 11:42:46,700 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-28 11:42:46,700 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-28 11:42:46,700 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 11:42:46,700 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-28 11:42:46,701 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 11:42:46,710 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-28 11:42:46,748 INFO L134 CoverageAnalysis]: Checked inductivity of 22 backedges. 0 proven. 22 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-28 11:42:46,748 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-28 11:42:46,748 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_3d9fc5bc-d65d-4259-979e-2e9bddd7decc/bin-2019/uautomizer/z3 Starting monitored process 4 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 4 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-28 11:42:46,779 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-11-28 11:42:46,800 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) [2018-11-28 11:42:46,800 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-11-28 11:42:46,802 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-28 11:42:46,808 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 18 [2018-11-28 11:42:46,810 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:42:46,811 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 18 treesize of output 24 [2018-11-28 11:42:46,815 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:42:46,815 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:42:46,816 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 2 select indices, 2 select index equivalence classes, 3 disjoint index pairs (out of 1 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 20 treesize of output 34 [2018-11-28 11:42:46,827 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:42:46,828 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:42:46,829 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:42:46,841 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:42:46,842 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 3 select indices, 3 select index equivalence classes, 7 disjoint index pairs (out of 3 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 22 treesize of output 51 [2018-11-28 11:42:46,842 INFO L267 ElimStorePlain]: Start of recursive call 5: End of recursive call: and 1 xjuncts. [2018-11-28 11:42:46,852 INFO L267 ElimStorePlain]: Start of recursive call 4: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-28 11:42:46,857 INFO L267 ElimStorePlain]: Start of recursive call 3: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-28 11:42:46,861 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-28 11:42:46,871 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 43 treesize of output 39 [2018-11-28 11:42:46,879 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:42:46,884 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 2 select indices, 2 select index equivalence classes, 2 disjoint index pairs (out of 1 index pairs), introduced 1 new quantified variables, introduced 2 case distinctions, treesize of input 36 treesize of output 49 [2018-11-28 11:42:46,915 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:42:46,917 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:42:46,919 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:42:46,923 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 4 select indices, 4 select index equivalence classes, 5 disjoint index pairs (out of 6 index pairs), introduced 1 new quantified variables, introduced 2 case distinctions, treesize of input 36 treesize of output 57 [2018-11-28 11:42:46,981 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:42:46,983 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:42:46,989 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:42:46,990 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:42:46,991 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:42:46,992 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:42:46,992 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:42:46,993 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 5 select indices, 5 select index equivalence classes, 9 disjoint index pairs (out of 10 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 34 treesize of output 33 [2018-11-28 11:42:46,993 INFO L267 ElimStorePlain]: Start of recursive call 9: End of recursive call: and 1 xjuncts. [2018-11-28 11:42:47,008 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:42:47,009 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:42:47,009 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:42:47,010 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:42:47,010 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:42:47,011 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:42:47,012 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 4 select indices, 4 select index equivalence classes, 8 disjoint index pairs (out of 6 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 25 treesize of output 29 [2018-11-28 11:42:47,012 INFO L267 ElimStorePlain]: Start of recursive call 10: End of recursive call: and 1 xjuncts. [2018-11-28 11:42:47,020 INFO L267 ElimStorePlain]: Start of recursive call 8: 2 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-28 11:42:47,032 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:42:47,033 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:42:47,033 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 3 select indices, 3 select index equivalence classes, 4 disjoint index pairs (out of 3 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 31 treesize of output 44 [2018-11-28 11:42:47,057 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:42:47,058 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:42:47,059 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:42:47,060 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:42:47,061 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:42:47,062 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 4 select indices, 4 select index equivalence classes, 7 disjoint index pairs (out of 6 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 21 treesize of output 25 [2018-11-28 11:42:47,063 INFO L267 ElimStorePlain]: Start of recursive call 12: End of recursive call: and 1 xjuncts. [2018-11-28 11:42:47,070 INFO L267 ElimStorePlain]: Start of recursive call 11: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-28 11:42:47,077 INFO L267 ElimStorePlain]: Start of recursive call 7: 2 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-28 11:42:47,082 INFO L267 ElimStorePlain]: Start of recursive call 6: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-28 11:42:47,093 INFO L267 ElimStorePlain]: Start of recursive call 1: 3 dim-0 vars, 2 dim-1 vars, End of recursive call: 3 dim-0 vars, and 1 xjuncts. [2018-11-28 11:42:47,093 INFO L202 ElimStorePlain]: Needed 12 recursive calls to eliminate 5 variables, input treesize:61, output treesize:36 [2018-11-28 11:42:47,230 INFO L134 CoverageAnalysis]: Checked inductivity of 22 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 22 trivial. 0 not checked. [2018-11-28 11:42:47,245 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 1 imperfect interpolant sequences. [2018-11-28 11:42:47,245 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [6] imperfect sequences [7] total 12 [2018-11-28 11:42:47,245 INFO L459 AbstractCegarLoop]: Interpolant automaton has 12 states [2018-11-28 11:42:47,245 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 12 interpolants. [2018-11-28 11:42:47,246 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=33, Invalid=99, Unknown=0, NotChecked=0, Total=132 [2018-11-28 11:42:47,246 INFO L87 Difference]: Start difference. First operand 74 states and 78 transitions. Second operand 12 states. [2018-11-28 11:42:47,488 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-28 11:42:47,488 INFO L93 Difference]: Finished difference Result 79 states and 83 transitions. [2018-11-28 11:42:47,489 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 12 states. [2018-11-28 11:42:47,489 INFO L78 Accepts]: Start accepts. Automaton has 12 states. Word has length 29 [2018-11-28 11:42:47,489 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-28 11:42:47,489 INFO L225 Difference]: With dead ends: 79 [2018-11-28 11:42:47,490 INFO L226 Difference]: Without dead ends: 79 [2018-11-28 11:42:47,490 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 43 GetRequests, 25 SyntacticMatches, 0 SemanticMatches, 18 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 57 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=87, Invalid=293, Unknown=0, NotChecked=0, Total=380 [2018-11-28 11:42:47,490 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 79 states. [2018-11-28 11:42:47,493 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 79 to 77. [2018-11-28 11:42:47,493 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 77 states. [2018-11-28 11:42:47,494 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 77 states to 77 states and 81 transitions. [2018-11-28 11:42:47,494 INFO L78 Accepts]: Start accepts. Automaton has 77 states and 81 transitions. Word has length 29 [2018-11-28 11:42:47,494 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-28 11:42:47,494 INFO L480 AbstractCegarLoop]: Abstraction has 77 states and 81 transitions. [2018-11-28 11:42:47,495 INFO L481 AbstractCegarLoop]: Interpolant automaton has 12 states. [2018-11-28 11:42:47,495 INFO L276 IsEmpty]: Start isEmpty. Operand 77 states and 81 transitions. [2018-11-28 11:42:47,495 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 34 [2018-11-28 11:42:47,495 INFO L394 BasicCegarLoop]: Found error trace [2018-11-28 11:42:47,495 INFO L402 BasicCegarLoop]: trace histogram [5, 5, 5, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-28 11:42:47,496 INFO L423 AbstractCegarLoop]: === Iteration 7 === [getNumbers3Err0REQUIRES_VIOLATION, getNumbers3Err2REQUIRES_VIOLATION, getNumbers3Err1REQUIRES_VIOLATION, getNumbers3Err3REQUIRES_VIOLATION, getNumbers2Err2REQUIRES_VIOLATION, getNumbers2Err1REQUIRES_VIOLATION, getNumbers2Err3REQUIRES_VIOLATION, getNumbers2Err0REQUIRES_VIOLATION, getNumbers4Err2REQUIRES_VIOLATION, getNumbers4Err1REQUIRES_VIOLATION, getNumbers4Err3REQUIRES_VIOLATION, getNumbers4Err0REQUIRES_VIOLATION, mainErr2ENSURES_VIOLATIONMEMORY_LEAK, mainErr1REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION, getNumbersErr1REQUIRES_VIOLATION, getNumbersErr0REQUIRES_VIOLATION]=== [2018-11-28 11:42:47,496 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-28 11:42:47,496 INFO L82 PathProgramCache]: Analyzing trace with hash 532455402, now seen corresponding path program 1 times [2018-11-28 11:42:47,496 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-28 11:42:47,496 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-28 11:42:47,497 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 11:42:47,497 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-28 11:42:47,497 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 11:42:47,506 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-28 11:42:47,540 INFO L134 CoverageAnalysis]: Checked inductivity of 35 backedges. 0 proven. 35 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-28 11:42:47,540 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-28 11:42:47,540 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_3d9fc5bc-d65d-4259-979e-2e9bddd7decc/bin-2019/uautomizer/z3 Starting monitored process 5 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 5 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-28 11:42:47,562 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-28 11:42:47,593 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-28 11:42:47,595 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-28 11:42:47,606 INFO L134 CoverageAnalysis]: Checked inductivity of 35 backedges. 0 proven. 35 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-28 11:42:47,621 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-11-28 11:42:47,621 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [8, 8] total 9 [2018-11-28 11:42:47,621 INFO L459 AbstractCegarLoop]: Interpolant automaton has 9 states [2018-11-28 11:42:47,622 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 9 interpolants. [2018-11-28 11:42:47,622 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=36, Invalid=36, Unknown=0, NotChecked=0, Total=72 [2018-11-28 11:42:47,622 INFO L87 Difference]: Start difference. First operand 77 states and 81 transitions. Second operand 9 states. [2018-11-28 11:42:47,649 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-28 11:42:47,649 INFO L93 Difference]: Finished difference Result 82 states and 86 transitions. [2018-11-28 11:42:47,650 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 8 states. [2018-11-28 11:42:47,650 INFO L78 Accepts]: Start accepts. Automaton has 9 states. Word has length 33 [2018-11-28 11:42:47,650 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-28 11:42:47,650 INFO L225 Difference]: With dead ends: 82 [2018-11-28 11:42:47,650 INFO L226 Difference]: Without dead ends: 82 [2018-11-28 11:42:47,651 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 40 GetRequests, 33 SyntacticMatches, 0 SemanticMatches, 7 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 8 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=36, Invalid=36, Unknown=0, NotChecked=0, Total=72 [2018-11-28 11:42:47,651 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 82 states. [2018-11-28 11:42:47,653 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 82 to 80. [2018-11-28 11:42:47,654 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 80 states. [2018-11-28 11:42:47,654 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 80 states to 80 states and 84 transitions. [2018-11-28 11:42:47,654 INFO L78 Accepts]: Start accepts. Automaton has 80 states and 84 transitions. Word has length 33 [2018-11-28 11:42:47,655 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-28 11:42:47,655 INFO L480 AbstractCegarLoop]: Abstraction has 80 states and 84 transitions. [2018-11-28 11:42:47,655 INFO L481 AbstractCegarLoop]: Interpolant automaton has 9 states. [2018-11-28 11:42:47,655 INFO L276 IsEmpty]: Start isEmpty. Operand 80 states and 84 transitions. [2018-11-28 11:42:47,655 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 37 [2018-11-28 11:42:47,655 INFO L394 BasicCegarLoop]: Found error trace [2018-11-28 11:42:47,655 INFO L402 BasicCegarLoop]: trace histogram [6, 6, 6, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-28 11:42:47,656 INFO L423 AbstractCegarLoop]: === Iteration 8 === [getNumbers3Err0REQUIRES_VIOLATION, getNumbers3Err2REQUIRES_VIOLATION, getNumbers3Err1REQUIRES_VIOLATION, getNumbers3Err3REQUIRES_VIOLATION, getNumbers2Err2REQUIRES_VIOLATION, getNumbers2Err1REQUIRES_VIOLATION, getNumbers2Err3REQUIRES_VIOLATION, getNumbers2Err0REQUIRES_VIOLATION, getNumbers4Err2REQUIRES_VIOLATION, getNumbers4Err1REQUIRES_VIOLATION, getNumbers4Err3REQUIRES_VIOLATION, getNumbers4Err0REQUIRES_VIOLATION, mainErr2ENSURES_VIOLATIONMEMORY_LEAK, mainErr1REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION, getNumbersErr1REQUIRES_VIOLATION, getNumbersErr0REQUIRES_VIOLATION]=== [2018-11-28 11:42:47,656 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-28 11:42:47,656 INFO L82 PathProgramCache]: Analyzing trace with hash -428261789, now seen corresponding path program 2 times [2018-11-28 11:42:47,656 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-28 11:42:47,656 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-28 11:42:47,657 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 11:42:47,657 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-28 11:42:47,657 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 11:42:47,666 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-28 11:42:47,712 INFO L134 CoverageAnalysis]: Checked inductivity of 51 backedges. 0 proven. 51 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-28 11:42:47,712 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-28 11:42:47,712 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_3d9fc5bc-d65d-4259-979e-2e9bddd7decc/bin-2019/uautomizer/z3 Starting monitored process 6 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 6 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-28 11:42:47,722 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-11-28 11:42:47,753 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) [2018-11-28 11:42:47,753 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-11-28 11:42:47,755 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-28 11:42:47,759 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 61 treesize of output 54 [2018-11-28 11:42:47,776 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:42:47,781 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 2 select indices, 2 select index equivalence classes, 2 disjoint index pairs (out of 1 index pairs), introduced 1 new quantified variables, introduced 2 case distinctions, treesize of input 51 treesize of output 61 [2018-11-28 11:42:47,832 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:42:47,835 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:42:47,837 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:42:47,844 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 4 select indices, 4 select index equivalence classes, 5 disjoint index pairs (out of 6 index pairs), introduced 1 new quantified variables, introduced 2 case distinctions, treesize of input 48 treesize of output 66 [2018-11-28 11:42:47,918 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:42:47,918 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:42:47,919 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:42:47,919 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:42:47,920 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:42:47,921 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 4 select indices, 4 select index equivalence classes, 7 disjoint index pairs (out of 6 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 41 treesize of output 64 [2018-11-28 11:42:47,923 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 4 select indices, 4 select index equivalence classes, 7 disjoint index pairs (out of 6 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 33 treesize of output 54 [2018-11-28 11:42:47,923 INFO L267 ElimStorePlain]: Start of recursive call 6: End of recursive call: and 1 xjuncts. [2018-11-28 11:42:47,935 INFO L267 ElimStorePlain]: Start of recursive call 5: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-28 11:42:47,963 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:42:47,964 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:42:47,965 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:42:47,966 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:42:47,967 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:42:47,967 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:42:47,969 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:42:47,973 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 5 select indices, 5 select index equivalence classes, 9 disjoint index pairs (out of 10 index pairs), introduced 1 new quantified variables, introduced 2 case distinctions, treesize of input 39 treesize of output 74 [2018-11-28 11:42:47,976 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 4 select indices, 4 select index equivalence classes, 7 disjoint index pairs (out of 6 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 68 treesize of output 62 [2018-11-28 11:42:47,977 INFO L267 ElimStorePlain]: Start of recursive call 8: End of recursive call: and 1 xjuncts. [2018-11-28 11:42:48,010 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:42:48,011 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:42:48,012 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:42:48,012 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:42:48,014 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:42:48,014 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:42:48,015 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:42:48,019 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 5 select indices, 5 select index equivalence classes, 10 disjoint index pairs (out of 10 index pairs), introduced 0 new quantified variables, introduced 2 case distinctions, treesize of input 40 treesize of output 72 [2018-11-28 11:42:48,020 INFO L267 ElimStorePlain]: Start of recursive call 9: End of recursive call: and 2 xjuncts. [2018-11-28 11:42:48,063 INFO L267 ElimStorePlain]: Start of recursive call 7: 2 dim-1 vars, End of recursive call: and 3 xjuncts. [2018-11-28 11:42:48,108 INFO L267 ElimStorePlain]: Start of recursive call 4: 2 dim-1 vars, End of recursive call: and 4 xjuncts. [2018-11-28 11:42:48,167 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:42:48,168 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:42:48,168 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 3 select indices, 3 select index equivalence classes, 4 disjoint index pairs (out of 3 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 46 treesize of output 56 [2018-11-28 11:42:48,195 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:42:48,196 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:42:48,196 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:42:48,197 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:42:48,198 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:42:48,198 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 4 select indices, 4 select index equivalence classes, 7 disjoint index pairs (out of 6 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 30 treesize of output 60 [2018-11-28 11:42:48,201 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 4 select indices, 4 select index equivalence classes, 7 disjoint index pairs (out of 6 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 33 treesize of output 54 [2018-11-28 11:42:48,202 INFO L267 ElimStorePlain]: Start of recursive call 12: End of recursive call: and 1 xjuncts. [2018-11-28 11:42:48,217 INFO L267 ElimStorePlain]: Start of recursive call 11: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-28 11:42:48,227 INFO L267 ElimStorePlain]: Start of recursive call 10: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-28 11:42:48,300 INFO L267 ElimStorePlain]: Start of recursive call 3: 2 dim-1 vars, End of recursive call: and 5 xjuncts. [2018-11-28 11:42:48,360 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 5 xjuncts. [2018-11-28 11:42:48,427 INFO L267 ElimStorePlain]: Start of recursive call 1: 3 dim-0 vars, 1 dim-1 vars, End of recursive call: 12 dim-0 vars, and 5 xjuncts. [2018-11-28 11:42:48,427 INFO L202 ElimStorePlain]: Needed 12 recursive calls to eliminate 4 variables, input treesize:61, output treesize:234 [2018-11-28 11:42:48,618 INFO L134 CoverageAnalysis]: Checked inductivity of 51 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 51 trivial. 0 not checked. [2018-11-28 11:42:48,633 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 1 imperfect interpolant sequences. [2018-11-28 11:42:48,633 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [9] total 10 [2018-11-28 11:42:48,634 INFO L459 AbstractCegarLoop]: Interpolant automaton has 10 states [2018-11-28 11:42:48,634 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 10 interpolants. [2018-11-28 11:42:48,634 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=38, Invalid=52, Unknown=0, NotChecked=0, Total=90 [2018-11-28 11:42:48,634 INFO L87 Difference]: Start difference. First operand 80 states and 84 transitions. Second operand 10 states. [2018-11-28 11:42:49,953 WARN L180 SmtUtils]: Spent 1.15 s on a formula simplification that was a NOOP. DAG size: 83 [2018-11-28 11:42:50,069 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-28 11:42:50,069 INFO L93 Difference]: Finished difference Result 84 states and 88 transitions. [2018-11-28 11:42:50,069 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 10 states. [2018-11-28 11:42:50,069 INFO L78 Accepts]: Start accepts. Automaton has 10 states. Word has length 36 [2018-11-28 11:42:50,070 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-28 11:42:50,070 INFO L225 Difference]: With dead ends: 84 [2018-11-28 11:42:50,070 INFO L226 Difference]: Without dead ends: 84 [2018-11-28 11:42:50,071 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 51 GetRequests, 33 SyntacticMatches, 3 SemanticMatches, 15 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 45 ImplicationChecksByTransitivity, 1.4s TimeCoverageRelationStatistics Valid=108, Invalid=164, Unknown=0, NotChecked=0, Total=272 [2018-11-28 11:42:50,071 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 84 states. [2018-11-28 11:42:50,073 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 84 to 82. [2018-11-28 11:42:50,073 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 82 states. [2018-11-28 11:42:50,074 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 82 states to 82 states and 86 transitions. [2018-11-28 11:42:50,074 INFO L78 Accepts]: Start accepts. Automaton has 82 states and 86 transitions. Word has length 36 [2018-11-28 11:42:50,074 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-28 11:42:50,075 INFO L480 AbstractCegarLoop]: Abstraction has 82 states and 86 transitions. [2018-11-28 11:42:50,075 INFO L481 AbstractCegarLoop]: Interpolant automaton has 10 states. [2018-11-28 11:42:50,075 INFO L276 IsEmpty]: Start isEmpty. Operand 82 states and 86 transitions. [2018-11-28 11:42:50,075 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 40 [2018-11-28 11:42:50,075 INFO L394 BasicCegarLoop]: Found error trace [2018-11-28 11:42:50,075 INFO L402 BasicCegarLoop]: trace histogram [7, 7, 7, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-28 11:42:50,076 INFO L423 AbstractCegarLoop]: === Iteration 9 === [getNumbers3Err0REQUIRES_VIOLATION, getNumbers3Err2REQUIRES_VIOLATION, getNumbers3Err1REQUIRES_VIOLATION, getNumbers3Err3REQUIRES_VIOLATION, getNumbers2Err2REQUIRES_VIOLATION, getNumbers2Err1REQUIRES_VIOLATION, getNumbers2Err3REQUIRES_VIOLATION, getNumbers2Err0REQUIRES_VIOLATION, getNumbers4Err2REQUIRES_VIOLATION, getNumbers4Err1REQUIRES_VIOLATION, getNumbers4Err3REQUIRES_VIOLATION, getNumbers4Err0REQUIRES_VIOLATION, mainErr2ENSURES_VIOLATIONMEMORY_LEAK, mainErr1REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION, getNumbersErr1REQUIRES_VIOLATION, getNumbersErr0REQUIRES_VIOLATION]=== [2018-11-28 11:42:50,076 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-28 11:42:50,076 INFO L82 PathProgramCache]: Analyzing trace with hash 507961675, now seen corresponding path program 1 times [2018-11-28 11:42:50,076 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-28 11:42:50,076 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-28 11:42:50,077 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 11:42:50,077 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-28 11:42:50,077 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 11:42:50,086 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-28 11:42:50,131 INFO L134 CoverageAnalysis]: Checked inductivity of 70 backedges. 0 proven. 70 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-28 11:42:50,131 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-28 11:42:50,132 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_3d9fc5bc-d65d-4259-979e-2e9bddd7decc/bin-2019/uautomizer/z3 Starting monitored process 7 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 7 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-28 11:42:50,140 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-28 11:42:50,161 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-28 11:42:50,163 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-28 11:42:50,170 INFO L134 CoverageAnalysis]: Checked inductivity of 70 backedges. 0 proven. 70 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-28 11:42:50,193 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-11-28 11:42:50,193 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [10, 10] total 11 [2018-11-28 11:42:50,193 INFO L459 AbstractCegarLoop]: Interpolant automaton has 11 states [2018-11-28 11:42:50,193 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 11 interpolants. [2018-11-28 11:42:50,193 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=55, Invalid=55, Unknown=0, NotChecked=0, Total=110 [2018-11-28 11:42:50,193 INFO L87 Difference]: Start difference. First operand 82 states and 86 transitions. Second operand 11 states. [2018-11-28 11:42:50,215 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-28 11:42:50,215 INFO L93 Difference]: Finished difference Result 87 states and 91 transitions. [2018-11-28 11:42:50,216 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 10 states. [2018-11-28 11:42:50,216 INFO L78 Accepts]: Start accepts. Automaton has 11 states. Word has length 39 [2018-11-28 11:42:50,216 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-28 11:42:50,216 INFO L225 Difference]: With dead ends: 87 [2018-11-28 11:42:50,216 INFO L226 Difference]: Without dead ends: 87 [2018-11-28 11:42:50,216 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 48 GetRequests, 39 SyntacticMatches, 0 SemanticMatches, 9 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 12 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=55, Invalid=55, Unknown=0, NotChecked=0, Total=110 [2018-11-28 11:42:50,216 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 87 states. [2018-11-28 11:42:50,218 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 87 to 85. [2018-11-28 11:42:50,218 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 85 states. [2018-11-28 11:42:50,218 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 85 states to 85 states and 89 transitions. [2018-11-28 11:42:50,218 INFO L78 Accepts]: Start accepts. Automaton has 85 states and 89 transitions. Word has length 39 [2018-11-28 11:42:50,219 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-28 11:42:50,219 INFO L480 AbstractCegarLoop]: Abstraction has 85 states and 89 transitions. [2018-11-28 11:42:50,219 INFO L481 AbstractCegarLoop]: Interpolant automaton has 11 states. [2018-11-28 11:42:50,219 INFO L276 IsEmpty]: Start isEmpty. Operand 85 states and 89 transitions. [2018-11-28 11:42:50,219 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 43 [2018-11-28 11:42:50,219 INFO L394 BasicCegarLoop]: Found error trace [2018-11-28 11:42:50,219 INFO L402 BasicCegarLoop]: trace histogram [8, 8, 8, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-28 11:42:50,219 INFO L423 AbstractCegarLoop]: === Iteration 10 === [getNumbers3Err0REQUIRES_VIOLATION, getNumbers3Err2REQUIRES_VIOLATION, getNumbers3Err1REQUIRES_VIOLATION, getNumbers3Err3REQUIRES_VIOLATION, getNumbers2Err2REQUIRES_VIOLATION, getNumbers2Err1REQUIRES_VIOLATION, getNumbers2Err3REQUIRES_VIOLATION, getNumbers2Err0REQUIRES_VIOLATION, getNumbers4Err2REQUIRES_VIOLATION, getNumbers4Err1REQUIRES_VIOLATION, getNumbers4Err3REQUIRES_VIOLATION, getNumbers4Err0REQUIRES_VIOLATION, mainErr2ENSURES_VIOLATIONMEMORY_LEAK, mainErr1REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION, getNumbersErr1REQUIRES_VIOLATION, getNumbersErr0REQUIRES_VIOLATION]=== [2018-11-28 11:42:50,219 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-28 11:42:50,219 INFO L82 PathProgramCache]: Analyzing trace with hash 23527684, now seen corresponding path program 2 times [2018-11-28 11:42:50,219 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-28 11:42:50,220 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-28 11:42:50,221 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 11:42:50,221 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-28 11:42:50,221 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 11:42:50,230 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-28 11:42:50,285 INFO L134 CoverageAnalysis]: Checked inductivity of 92 backedges. 0 proven. 92 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-28 11:42:50,285 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-28 11:42:50,285 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_3d9fc5bc-d65d-4259-979e-2e9bddd7decc/bin-2019/uautomizer/z3 Starting monitored process 8 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 8 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-28 11:42:50,292 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-11-28 11:42:50,309 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) [2018-11-28 11:42:50,310 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-11-28 11:42:50,312 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-28 11:42:50,321 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 18 [2018-11-28 11:42:50,345 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:42:50,346 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 18 treesize of output 24 [2018-11-28 11:42:50,353 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:42:50,361 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:42:50,362 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 2 select indices, 2 select index equivalence classes, 3 disjoint index pairs (out of 1 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 20 treesize of output 34 [2018-11-28 11:42:50,365 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:42:50,369 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:42:50,377 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:42:50,385 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:42:50,386 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 3 select indices, 3 select index equivalence classes, 7 disjoint index pairs (out of 3 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 22 treesize of output 51 [2018-11-28 11:42:50,386 INFO L267 ElimStorePlain]: Start of recursive call 5: End of recursive call: and 1 xjuncts. [2018-11-28 11:42:50,398 INFO L267 ElimStorePlain]: Start of recursive call 4: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-28 11:42:50,404 INFO L267 ElimStorePlain]: Start of recursive call 3: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-28 11:42:50,410 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-28 11:42:50,420 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 43 treesize of output 39 [2018-11-28 11:42:50,429 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:42:50,434 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 2 select indices, 2 select index equivalence classes, 2 disjoint index pairs (out of 1 index pairs), introduced 1 new quantified variables, introduced 2 case distinctions, treesize of input 36 treesize of output 49 [2018-11-28 11:42:50,469 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:42:50,471 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:42:50,472 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:42:50,477 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 4 select indices, 4 select index equivalence classes, 5 disjoint index pairs (out of 6 index pairs), introduced 1 new quantified variables, introduced 2 case distinctions, treesize of input 36 treesize of output 57 [2018-11-28 11:42:50,519 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:42:50,519 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:42:50,520 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:42:50,521 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:42:50,521 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:42:50,522 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 4 select indices, 4 select index equivalence classes, 7 disjoint index pairs (out of 6 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 32 treesize of output 36 [2018-11-28 11:42:50,522 INFO L267 ElimStorePlain]: Start of recursive call 9: End of recursive call: and 1 xjuncts. [2018-11-28 11:42:50,553 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:42:50,554 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:42:50,557 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:42:50,559 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:42:50,560 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:42:50,561 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:42:50,561 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:42:50,562 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:42:50,563 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 5 select indices, 5 select index equivalence classes, 9 disjoint index pairs (out of 10 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 26 treesize of output 33 [2018-11-28 11:42:50,563 INFO L267 ElimStorePlain]: Start of recursive call 10: End of recursive call: and 1 xjuncts. [2018-11-28 11:42:50,573 INFO L267 ElimStorePlain]: Start of recursive call 8: 2 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-28 11:42:50,586 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:42:50,587 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:42:50,588 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 3 select indices, 3 select index equivalence classes, 4 disjoint index pairs (out of 3 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 31 treesize of output 44 [2018-11-28 11:42:50,603 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:42:50,603 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:42:50,604 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:42:50,604 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:42:50,605 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:42:50,606 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 4 select indices, 4 select index equivalence classes, 7 disjoint index pairs (out of 6 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 21 treesize of output 25 [2018-11-28 11:42:50,606 INFO L267 ElimStorePlain]: Start of recursive call 12: End of recursive call: and 1 xjuncts. [2018-11-28 11:42:50,614 INFO L267 ElimStorePlain]: Start of recursive call 11: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-28 11:42:50,620 INFO L267 ElimStorePlain]: Start of recursive call 7: 2 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-28 11:42:50,624 INFO L267 ElimStorePlain]: Start of recursive call 6: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-28 11:42:50,632 INFO L267 ElimStorePlain]: Start of recursive call 1: 3 dim-0 vars, 2 dim-1 vars, End of recursive call: 3 dim-0 vars, and 1 xjuncts. [2018-11-28 11:42:50,632 INFO L202 ElimStorePlain]: Needed 12 recursive calls to eliminate 5 variables, input treesize:61, output treesize:36 [2018-11-28 11:42:50,702 INFO L134 CoverageAnalysis]: Checked inductivity of 92 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 92 trivial. 0 not checked. [2018-11-28 11:42:50,717 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 1 imperfect interpolant sequences. [2018-11-28 11:42:50,717 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [4] imperfect sequences [11] total 14 [2018-11-28 11:42:50,718 INFO L459 AbstractCegarLoop]: Interpolant automaton has 14 states [2018-11-28 11:42:50,718 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 14 interpolants. [2018-11-28 11:42:50,718 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=64, Invalid=118, Unknown=0, NotChecked=0, Total=182 [2018-11-28 11:42:50,718 INFO L87 Difference]: Start difference. First operand 85 states and 89 transitions. Second operand 14 states. [2018-11-28 11:42:50,939 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-28 11:42:50,940 INFO L93 Difference]: Finished difference Result 89 states and 93 transitions. [2018-11-28 11:42:50,940 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 14 states. [2018-11-28 11:42:50,940 INFO L78 Accepts]: Start accepts. Automaton has 14 states. Word has length 42 [2018-11-28 11:42:50,940 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-28 11:42:50,941 INFO L225 Difference]: With dead ends: 89 [2018-11-28 11:42:50,941 INFO L226 Difference]: Without dead ends: 89 [2018-11-28 11:42:50,941 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 61 GetRequests, 40 SyntacticMatches, 0 SemanticMatches, 21 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 69 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=172, Invalid=334, Unknown=0, NotChecked=0, Total=506 [2018-11-28 11:42:50,942 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 89 states. [2018-11-28 11:42:50,943 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 89 to 87. [2018-11-28 11:42:50,943 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 87 states. [2018-11-28 11:42:50,944 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 87 states to 87 states and 91 transitions. [2018-11-28 11:42:50,944 INFO L78 Accepts]: Start accepts. Automaton has 87 states and 91 transitions. Word has length 42 [2018-11-28 11:42:50,944 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-28 11:42:50,944 INFO L480 AbstractCegarLoop]: Abstraction has 87 states and 91 transitions. [2018-11-28 11:42:50,944 INFO L481 AbstractCegarLoop]: Interpolant automaton has 14 states. [2018-11-28 11:42:50,944 INFO L276 IsEmpty]: Start isEmpty. Operand 87 states and 91 transitions. [2018-11-28 11:42:50,949 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 55 [2018-11-28 11:42:50,949 INFO L394 BasicCegarLoop]: Found error trace [2018-11-28 11:42:50,950 INFO L402 BasicCegarLoop]: trace histogram [9, 9, 9, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-28 11:42:50,950 INFO L423 AbstractCegarLoop]: === Iteration 11 === [getNumbers3Err0REQUIRES_VIOLATION, getNumbers3Err2REQUIRES_VIOLATION, getNumbers3Err1REQUIRES_VIOLATION, getNumbers3Err3REQUIRES_VIOLATION, getNumbers2Err2REQUIRES_VIOLATION, getNumbers2Err1REQUIRES_VIOLATION, getNumbers2Err3REQUIRES_VIOLATION, getNumbers2Err0REQUIRES_VIOLATION, getNumbers4Err2REQUIRES_VIOLATION, getNumbers4Err1REQUIRES_VIOLATION, getNumbers4Err3REQUIRES_VIOLATION, getNumbers4Err0REQUIRES_VIOLATION, mainErr2ENSURES_VIOLATIONMEMORY_LEAK, mainErr1REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION, getNumbersErr1REQUIRES_VIOLATION, getNumbersErr0REQUIRES_VIOLATION]=== [2018-11-28 11:42:50,950 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-28 11:42:50,950 INFO L82 PathProgramCache]: Analyzing trace with hash -1213368515, now seen corresponding path program 1 times [2018-11-28 11:42:50,950 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-28 11:42:50,950 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-28 11:42:50,951 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 11:42:50,951 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-28 11:42:50,951 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 11:42:50,960 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-28 11:42:51,047 INFO L134 CoverageAnalysis]: Checked inductivity of 118 backedges. 0 proven. 117 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2018-11-28 11:42:51,047 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-28 11:42:51,047 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_3d9fc5bc-d65d-4259-979e-2e9bddd7decc/bin-2019/uautomizer/z3 Starting monitored process 9 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 9 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-28 11:42:51,062 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-28 11:42:51,085 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-28 11:42:51,087 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-28 11:42:51,105 INFO L134 CoverageAnalysis]: Checked inductivity of 118 backedges. 0 proven. 117 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2018-11-28 11:42:51,120 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-11-28 11:42:51,120 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [12, 12] total 13 [2018-11-28 11:42:51,120 INFO L459 AbstractCegarLoop]: Interpolant automaton has 13 states [2018-11-28 11:42:51,121 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 13 interpolants. [2018-11-28 11:42:51,121 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=78, Invalid=78, Unknown=0, NotChecked=0, Total=156 [2018-11-28 11:42:51,121 INFO L87 Difference]: Start difference. First operand 87 states and 91 transitions. Second operand 13 states. [2018-11-28 11:42:51,150 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-28 11:42:51,150 INFO L93 Difference]: Finished difference Result 90 states and 94 transitions. [2018-11-28 11:42:51,151 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 12 states. [2018-11-28 11:42:51,151 INFO L78 Accepts]: Start accepts. Automaton has 13 states. Word has length 54 [2018-11-28 11:42:51,151 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-28 11:42:51,152 INFO L225 Difference]: With dead ends: 90 [2018-11-28 11:42:51,152 INFO L226 Difference]: Without dead ends: 90 [2018-11-28 11:42:51,152 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 65 GetRequests, 54 SyntacticMatches, 0 SemanticMatches, 11 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 16 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=78, Invalid=78, Unknown=0, NotChecked=0, Total=156 [2018-11-28 11:42:51,152 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 90 states. [2018-11-28 11:42:51,154 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 90 to 90. [2018-11-28 11:42:51,154 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 90 states. [2018-11-28 11:42:51,155 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 90 states to 90 states and 94 transitions. [2018-11-28 11:42:51,155 INFO L78 Accepts]: Start accepts. Automaton has 90 states and 94 transitions. Word has length 54 [2018-11-28 11:42:51,155 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-28 11:42:51,155 INFO L480 AbstractCegarLoop]: Abstraction has 90 states and 94 transitions. [2018-11-28 11:42:51,155 INFO L481 AbstractCegarLoop]: Interpolant automaton has 13 states. [2018-11-28 11:42:51,155 INFO L276 IsEmpty]: Start isEmpty. Operand 90 states and 94 transitions. [2018-11-28 11:42:51,156 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 58 [2018-11-28 11:42:51,156 INFO L394 BasicCegarLoop]: Found error trace [2018-11-28 11:42:51,156 INFO L402 BasicCegarLoop]: trace histogram [10, 10, 10, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-28 11:42:51,156 INFO L423 AbstractCegarLoop]: === Iteration 12 === [getNumbers3Err0REQUIRES_VIOLATION, getNumbers3Err2REQUIRES_VIOLATION, getNumbers3Err1REQUIRES_VIOLATION, getNumbers3Err3REQUIRES_VIOLATION, getNumbers2Err2REQUIRES_VIOLATION, getNumbers2Err1REQUIRES_VIOLATION, getNumbers2Err3REQUIRES_VIOLATION, getNumbers2Err0REQUIRES_VIOLATION, getNumbers4Err2REQUIRES_VIOLATION, getNumbers4Err1REQUIRES_VIOLATION, getNumbers4Err3REQUIRES_VIOLATION, getNumbers4Err0REQUIRES_VIOLATION, mainErr2ENSURES_VIOLATIONMEMORY_LEAK, mainErr1REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION, getNumbersErr1REQUIRES_VIOLATION, getNumbersErr0REQUIRES_VIOLATION]=== [2018-11-28 11:42:51,157 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-28 11:42:51,157 INFO L82 PathProgramCache]: Analyzing trace with hash -590033308, now seen corresponding path program 2 times [2018-11-28 11:42:51,157 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-28 11:42:51,157 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-28 11:42:51,157 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 11:42:51,157 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-28 11:42:51,158 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 11:42:51,167 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-28 11:42:51,187 INFO L134 CoverageAnalysis]: Checked inductivity of 146 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 145 trivial. 0 not checked. [2018-11-28 11:42:51,187 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-28 11:42:51,187 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_3d9fc5bc-d65d-4259-979e-2e9bddd7decc/bin-2019/uautomizer/z3 Starting monitored process 10 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 10 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-28 11:42:51,202 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-11-28 11:42:51,220 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) [2018-11-28 11:42:51,220 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-11-28 11:42:51,222 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-28 11:42:51,241 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 61 treesize of output 54 [2018-11-28 11:42:51,253 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:42:51,260 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 2 select indices, 2 select index equivalence classes, 2 disjoint index pairs (out of 1 index pairs), introduced 1 new quantified variables, introduced 2 case distinctions, treesize of input 51 treesize of output 61 [2018-11-28 11:42:51,312 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:42:51,315 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:42:51,316 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:42:51,322 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 4 select indices, 4 select index equivalence classes, 5 disjoint index pairs (out of 6 index pairs), introduced 1 new quantified variables, introduced 2 case distinctions, treesize of input 48 treesize of output 66 [2018-11-28 11:42:51,381 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:42:51,382 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:42:51,383 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:42:51,384 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:42:51,386 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:42:51,387 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:42:51,388 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:42:51,394 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 5 select indices, 5 select index equivalence classes, 9 disjoint index pairs (out of 10 index pairs), introduced 1 new quantified variables, introduced 2 case distinctions, treesize of input 43 treesize of output 74 [2018-11-28 11:42:51,396 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 4 select indices, 4 select index equivalence classes, 7 disjoint index pairs (out of 6 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 68 treesize of output 62 [2018-11-28 11:42:51,397 INFO L267 ElimStorePlain]: Start of recursive call 6: End of recursive call: and 1 xjuncts. [2018-11-28 11:42:51,434 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:42:51,434 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:42:51,435 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:42:51,436 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:42:51,437 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:42:51,438 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:42:51,440 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:42:51,445 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 5 select indices, 5 select index equivalence classes, 10 disjoint index pairs (out of 10 index pairs), introduced 0 new quantified variables, introduced 2 case distinctions, treesize of input 40 treesize of output 72 [2018-11-28 11:42:51,446 INFO L267 ElimStorePlain]: Start of recursive call 7: End of recursive call: and 2 xjuncts. [2018-11-28 11:42:51,494 INFO L267 ElimStorePlain]: Start of recursive call 5: 2 dim-1 vars, End of recursive call: and 3 xjuncts. [2018-11-28 11:42:51,546 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:42:51,547 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:42:51,547 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:42:51,548 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:42:51,549 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:42:51,550 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 4 select indices, 4 select index equivalence classes, 7 disjoint index pairs (out of 6 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 37 treesize of output 60 [2018-11-28 11:42:51,553 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 4 select indices, 4 select index equivalence classes, 7 disjoint index pairs (out of 6 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 33 treesize of output 54 [2018-11-28 11:42:51,553 INFO L267 ElimStorePlain]: Start of recursive call 9: End of recursive call: and 1 xjuncts. [2018-11-28 11:42:51,566 INFO L267 ElimStorePlain]: Start of recursive call 8: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-28 11:42:51,613 INFO L267 ElimStorePlain]: Start of recursive call 4: 2 dim-1 vars, End of recursive call: and 4 xjuncts. [2018-11-28 11:42:51,675 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:42:51,676 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:42:51,677 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 3 select indices, 3 select index equivalence classes, 4 disjoint index pairs (out of 3 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 46 treesize of output 56 [2018-11-28 11:42:51,702 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:42:51,703 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:42:51,704 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:42:51,705 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:42:51,706 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:42:51,707 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 4 select indices, 4 select index equivalence classes, 7 disjoint index pairs (out of 6 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 30 treesize of output 60 [2018-11-28 11:42:51,709 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 4 select indices, 4 select index equivalence classes, 7 disjoint index pairs (out of 6 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 33 treesize of output 54 [2018-11-28 11:42:51,709 INFO L267 ElimStorePlain]: Start of recursive call 12: End of recursive call: and 1 xjuncts. [2018-11-28 11:42:51,720 INFO L267 ElimStorePlain]: Start of recursive call 11: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-28 11:42:51,732 INFO L267 ElimStorePlain]: Start of recursive call 10: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-28 11:42:51,781 INFO L267 ElimStorePlain]: Start of recursive call 3: 2 dim-1 vars, End of recursive call: and 5 xjuncts. [2018-11-28 11:42:51,832 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 5 xjuncts. [2018-11-28 11:42:51,888 INFO L267 ElimStorePlain]: Start of recursive call 1: 3 dim-0 vars, 1 dim-1 vars, End of recursive call: 12 dim-0 vars, and 5 xjuncts. [2018-11-28 11:42:51,888 INFO L202 ElimStorePlain]: Needed 12 recursive calls to eliminate 4 variables, input treesize:61, output treesize:234 [2018-11-28 11:42:52,196 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 4 select indices, 4 select index equivalence classes, 6 disjoint index pairs (out of 6 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 54 treesize of output 61 [2018-11-28 11:42:52,197 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-11-28 11:42:52,255 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 4 select indices, 4 select index equivalence classes, 6 disjoint index pairs (out of 6 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 51 treesize of output 54 [2018-11-28 11:42:52,256 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-11-28 11:42:52,306 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:42:52,308 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:42:52,309 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:42:52,311 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:42:52,313 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:42:52,318 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 5 select indices, 5 select index equivalence classes, 11 disjoint index pairs (out of 10 index pairs), introduced 0 new quantified variables, introduced 2 case distinctions, treesize of input 56 treesize of output 83 [2018-11-28 11:42:52,319 INFO L267 ElimStorePlain]: Start of recursive call 4: End of recursive call: and 2 xjuncts. [2018-11-28 11:42:52,400 INFO L267 ElimStorePlain]: Start of recursive call 1: 11 dim-0 vars, 3 dim-1 vars, End of recursive call: 14 dim-0 vars, and 4 xjuncts. [2018-11-28 11:42:52,400 INFO L202 ElimStorePlain]: Needed 4 recursive calls to eliminate 14 variables, input treesize:162, output treesize:225 [2018-11-28 11:42:52,545 INFO L134 CoverageAnalysis]: Checked inductivity of 146 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 146 trivial. 0 not checked. [2018-11-28 11:42:52,559 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 1 imperfect interpolant sequences. [2018-11-28 11:42:52,559 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [4] total 8 [2018-11-28 11:42:52,559 INFO L459 AbstractCegarLoop]: Interpolant automaton has 8 states [2018-11-28 11:42:52,560 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 8 interpolants. [2018-11-28 11:42:52,560 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=15, Invalid=41, Unknown=0, NotChecked=0, Total=56 [2018-11-28 11:42:52,560 INFO L87 Difference]: Start difference. First operand 90 states and 94 transitions. Second operand 8 states. [2018-11-28 11:42:52,896 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-28 11:42:52,897 INFO L93 Difference]: Finished difference Result 98 states and 102 transitions. [2018-11-28 11:42:52,897 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 8 states. [2018-11-28 11:42:52,897 INFO L78 Accepts]: Start accepts. Automaton has 8 states. Word has length 57 [2018-11-28 11:42:52,897 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-28 11:42:52,898 INFO L225 Difference]: With dead ends: 98 [2018-11-28 11:42:52,898 INFO L226 Difference]: Without dead ends: 98 [2018-11-28 11:42:52,898 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 64 GetRequests, 51 SyntacticMatches, 3 SemanticMatches, 10 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 15 ImplicationChecksByTransitivity, 0.5s TimeCoverageRelationStatistics Valid=33, Invalid=99, Unknown=0, NotChecked=0, Total=132 [2018-11-28 11:42:52,898 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 98 states. [2018-11-28 11:42:52,900 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 98 to 94. [2018-11-28 11:42:52,900 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 94 states. [2018-11-28 11:42:52,901 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 94 states to 94 states and 98 transitions. [2018-11-28 11:42:52,901 INFO L78 Accepts]: Start accepts. Automaton has 94 states and 98 transitions. Word has length 57 [2018-11-28 11:42:52,901 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-28 11:42:52,901 INFO L480 AbstractCegarLoop]: Abstraction has 94 states and 98 transitions. [2018-11-28 11:42:52,901 INFO L481 AbstractCegarLoop]: Interpolant automaton has 8 states. [2018-11-28 11:42:52,901 INFO L276 IsEmpty]: Start isEmpty. Operand 94 states and 98 transitions. [2018-11-28 11:42:52,902 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 63 [2018-11-28 11:42:52,902 INFO L394 BasicCegarLoop]: Found error trace [2018-11-28 11:42:52,902 INFO L402 BasicCegarLoop]: trace histogram [10, 10, 10, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-28 11:42:52,902 INFO L423 AbstractCegarLoop]: === Iteration 13 === [getNumbers3Err0REQUIRES_VIOLATION, getNumbers3Err2REQUIRES_VIOLATION, getNumbers3Err1REQUIRES_VIOLATION, getNumbers3Err3REQUIRES_VIOLATION, getNumbers2Err2REQUIRES_VIOLATION, getNumbers2Err1REQUIRES_VIOLATION, getNumbers2Err3REQUIRES_VIOLATION, getNumbers2Err0REQUIRES_VIOLATION, getNumbers4Err2REQUIRES_VIOLATION, getNumbers4Err1REQUIRES_VIOLATION, getNumbers4Err3REQUIRES_VIOLATION, getNumbers4Err0REQUIRES_VIOLATION, mainErr2ENSURES_VIOLATIONMEMORY_LEAK, mainErr1REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION, getNumbersErr1REQUIRES_VIOLATION, getNumbersErr0REQUIRES_VIOLATION]=== [2018-11-28 11:42:52,902 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-28 11:42:52,902 INFO L82 PathProgramCache]: Analyzing trace with hash -317183977, now seen corresponding path program 1 times [2018-11-28 11:42:52,903 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-28 11:42:52,903 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-28 11:42:52,903 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 11:42:52,903 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-28 11:42:52,903 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 11:42:52,913 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-28 11:42:52,948 INFO L134 CoverageAnalysis]: Checked inductivity of 152 backedges. 0 proven. 7 refuted. 0 times theorem prover too weak. 145 trivial. 0 not checked. [2018-11-28 11:42:52,948 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-28 11:42:52,948 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_3d9fc5bc-d65d-4259-979e-2e9bddd7decc/bin-2019/uautomizer/z3 Starting monitored process 11 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 11 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-28 11:42:52,957 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-28 11:42:52,982 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-28 11:42:52,984 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-28 11:42:52,991 INFO L134 CoverageAnalysis]: Checked inductivity of 152 backedges. 0 proven. 7 refuted. 0 times theorem prover too weak. 145 trivial. 0 not checked. [2018-11-28 11:42:53,005 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-11-28 11:42:53,005 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [5, 5] total 6 [2018-11-28 11:42:53,006 INFO L459 AbstractCegarLoop]: Interpolant automaton has 6 states [2018-11-28 11:42:53,006 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2018-11-28 11:42:53,006 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=15, Invalid=15, Unknown=0, NotChecked=0, Total=30 [2018-11-28 11:42:53,006 INFO L87 Difference]: Start difference. First operand 94 states and 98 transitions. Second operand 6 states. [2018-11-28 11:42:53,023 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-28 11:42:53,023 INFO L93 Difference]: Finished difference Result 103 states and 107 transitions. [2018-11-28 11:42:53,024 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2018-11-28 11:42:53,024 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 62 [2018-11-28 11:42:53,024 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-28 11:42:53,025 INFO L225 Difference]: With dead ends: 103 [2018-11-28 11:42:53,025 INFO L226 Difference]: Without dead ends: 103 [2018-11-28 11:42:53,025 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 66 GetRequests, 62 SyntacticMatches, 0 SemanticMatches, 4 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=15, Invalid=15, Unknown=0, NotChecked=0, Total=30 [2018-11-28 11:42:53,025 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 103 states. [2018-11-28 11:42:53,027 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 103 to 99. [2018-11-28 11:42:53,027 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 99 states. [2018-11-28 11:42:53,028 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 99 states to 99 states and 103 transitions. [2018-11-28 11:42:53,028 INFO L78 Accepts]: Start accepts. Automaton has 99 states and 103 transitions. Word has length 62 [2018-11-28 11:42:53,028 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-28 11:42:53,028 INFO L480 AbstractCegarLoop]: Abstraction has 99 states and 103 transitions. [2018-11-28 11:42:53,028 INFO L481 AbstractCegarLoop]: Interpolant automaton has 6 states. [2018-11-28 11:42:53,028 INFO L276 IsEmpty]: Start isEmpty. Operand 99 states and 103 transitions. [2018-11-28 11:42:53,033 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 68 [2018-11-28 11:42:53,033 INFO L394 BasicCegarLoop]: Found error trace [2018-11-28 11:42:53,033 INFO L402 BasicCegarLoop]: trace histogram [10, 10, 10, 3, 3, 3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-28 11:42:53,033 INFO L423 AbstractCegarLoop]: === Iteration 14 === [getNumbers3Err0REQUIRES_VIOLATION, getNumbers3Err2REQUIRES_VIOLATION, getNumbers3Err1REQUIRES_VIOLATION, getNumbers3Err3REQUIRES_VIOLATION, getNumbers2Err2REQUIRES_VIOLATION, getNumbers2Err1REQUIRES_VIOLATION, getNumbers2Err3REQUIRES_VIOLATION, getNumbers2Err0REQUIRES_VIOLATION, getNumbers4Err2REQUIRES_VIOLATION, getNumbers4Err1REQUIRES_VIOLATION, getNumbers4Err3REQUIRES_VIOLATION, getNumbers4Err0REQUIRES_VIOLATION, mainErr2ENSURES_VIOLATIONMEMORY_LEAK, mainErr1REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION, getNumbersErr1REQUIRES_VIOLATION, getNumbersErr0REQUIRES_VIOLATION]=== [2018-11-28 11:42:53,033 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-28 11:42:53,034 INFO L82 PathProgramCache]: Analyzing trace with hash -1648161371, now seen corresponding path program 2 times [2018-11-28 11:42:53,034 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-28 11:42:53,034 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-28 11:42:53,034 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 11:42:53,034 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-28 11:42:53,034 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 11:42:53,047 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-28 11:42:53,093 INFO L134 CoverageAnalysis]: Checked inductivity of 163 backedges. 0 proven. 18 refuted. 0 times theorem prover too weak. 145 trivial. 0 not checked. [2018-11-28 11:42:53,094 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-28 11:42:53,094 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_3d9fc5bc-d65d-4259-979e-2e9bddd7decc/bin-2019/uautomizer/z3 Starting monitored process 12 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 12 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-28 11:42:53,103 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-11-28 11:42:53,119 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) [2018-11-28 11:42:53,120 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-11-28 11:42:53,122 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-28 11:42:53,125 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 43 treesize of output 39 [2018-11-28 11:42:53,133 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:42:53,137 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 2 select indices, 2 select index equivalence classes, 2 disjoint index pairs (out of 1 index pairs), introduced 1 new quantified variables, introduced 2 case distinctions, treesize of input 36 treesize of output 49 [2018-11-28 11:42:53,168 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:42:53,170 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:42:53,172 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:42:53,177 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 4 select indices, 4 select index equivalence classes, 5 disjoint index pairs (out of 6 index pairs), introduced 1 new quantified variables, introduced 2 case distinctions, treesize of input 36 treesize of output 57 [2018-11-28 11:42:53,214 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:42:53,214 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:42:53,216 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:42:53,216 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:42:53,218 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:42:53,218 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:42:53,219 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:42:53,219 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 5 select indices, 5 select index equivalence classes, 9 disjoint index pairs (out of 10 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 34 treesize of output 33 [2018-11-28 11:42:53,220 INFO L267 ElimStorePlain]: Start of recursive call 5: End of recursive call: and 1 xjuncts. [2018-11-28 11:42:53,244 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:42:53,245 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:42:53,247 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:42:53,248 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:42:53,249 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:42:53,250 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 4 select indices, 4 select index equivalence classes, 8 disjoint index pairs (out of 6 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 29 treesize of output 29 [2018-11-28 11:42:53,250 INFO L267 ElimStorePlain]: Start of recursive call 6: End of recursive call: and 1 xjuncts. [2018-11-28 11:42:53,266 INFO L267 ElimStorePlain]: Start of recursive call 4: 2 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-28 11:42:53,282 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:42:53,283 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:42:53,283 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 3 select indices, 3 select index equivalence classes, 4 disjoint index pairs (out of 3 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 31 treesize of output 44 [2018-11-28 11:42:53,299 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:42:53,300 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:42:53,301 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:42:53,301 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:42:53,302 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:42:53,302 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 4 select indices, 4 select index equivalence classes, 7 disjoint index pairs (out of 6 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 21 treesize of output 25 [2018-11-28 11:42:53,303 INFO L267 ElimStorePlain]: Start of recursive call 8: End of recursive call: and 1 xjuncts. [2018-11-28 11:42:53,310 INFO L267 ElimStorePlain]: Start of recursive call 7: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-28 11:42:53,323 INFO L267 ElimStorePlain]: Start of recursive call 3: 2 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-28 11:42:53,331 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-28 11:42:53,341 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 3 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 18 [2018-11-28 11:42:53,342 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 5 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 18 treesize of output 24 [2018-11-28 11:42:53,344 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 2 select indices, 2 select index equivalence classes, 6 disjoint index pairs (out of 1 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 20 treesize of output 34 [2018-11-28 11:42:53,346 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:42:53,346 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 3 select indices, 3 select index equivalence classes, 7 disjoint index pairs (out of 3 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 22 treesize of output 51 [2018-11-28 11:42:53,346 INFO L267 ElimStorePlain]: Start of recursive call 12: End of recursive call: and 1 xjuncts. [2018-11-28 11:42:53,354 INFO L267 ElimStorePlain]: Start of recursive call 11: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-28 11:42:53,358 INFO L267 ElimStorePlain]: Start of recursive call 10: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-28 11:42:53,363 INFO L267 ElimStorePlain]: Start of recursive call 9: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-28 11:42:53,374 INFO L267 ElimStorePlain]: Start of recursive call 1: 3 dim-0 vars, 2 dim-1 vars, End of recursive call: 3 dim-0 vars, and 1 xjuncts. [2018-11-28 11:42:53,374 INFO L202 ElimStorePlain]: Needed 12 recursive calls to eliminate 5 variables, input treesize:61, output treesize:36 [2018-11-28 11:42:53,465 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:42:53,467 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:42:53,469 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:42:53,472 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:42:53,479 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 4 select indices, 4 select index equivalence classes, 7 disjoint index pairs (out of 6 index pairs), introduced 0 new quantified variables, introduced 2 case distinctions, treesize of input 27 treesize of output 54 [2018-11-28 11:42:53,479 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 2 xjuncts. [2018-11-28 11:42:53,547 INFO L267 ElimStorePlain]: Start of recursive call 1: 4 dim-0 vars, 1 dim-1 vars, End of recursive call: 7 dim-0 vars, and 2 xjuncts. [2018-11-28 11:42:53,548 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 5 variables, input treesize:45, output treesize:96 [2018-11-28 11:42:53,672 WARN L180 SmtUtils]: Spent 109.00 ms on a formula simplification. DAG size of input: 59 DAG size of output: 55 [2018-11-28 11:42:53,732 INFO L134 CoverageAnalysis]: Checked inductivity of 163 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 163 trivial. 0 not checked. [2018-11-28 11:42:53,746 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 1 imperfect interpolant sequences. [2018-11-28 11:42:53,746 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [6] imperfect sequences [6] total 11 [2018-11-28 11:42:53,747 INFO L459 AbstractCegarLoop]: Interpolant automaton has 11 states [2018-11-28 11:42:53,747 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 11 interpolants. [2018-11-28 11:42:53,747 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=27, Invalid=83, Unknown=0, NotChecked=0, Total=110 [2018-11-28 11:42:53,747 INFO L87 Difference]: Start difference. First operand 99 states and 103 transitions. Second operand 11 states. [2018-11-28 11:42:53,910 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-28 11:42:53,910 INFO L93 Difference]: Finished difference Result 108 states and 112 transitions. [2018-11-28 11:42:53,910 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 11 states. [2018-11-28 11:42:53,910 INFO L78 Accepts]: Start accepts. Automaton has 11 states. Word has length 67 [2018-11-28 11:42:53,910 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-28 11:42:53,911 INFO L225 Difference]: With dead ends: 108 [2018-11-28 11:42:53,911 INFO L226 Difference]: Without dead ends: 108 [2018-11-28 11:42:53,911 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 77 GetRequests, 63 SyntacticMatches, 0 SemanticMatches, 14 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 33 ImplicationChecksByTransitivity, 0.3s TimeCoverageRelationStatistics Valid=59, Invalid=181, Unknown=0, NotChecked=0, Total=240 [2018-11-28 11:42:53,911 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 108 states. [2018-11-28 11:42:53,913 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 108 to 104. [2018-11-28 11:42:53,913 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 104 states. [2018-11-28 11:42:53,913 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 104 states to 104 states and 108 transitions. [2018-11-28 11:42:53,914 INFO L78 Accepts]: Start accepts. Automaton has 104 states and 108 transitions. Word has length 67 [2018-11-28 11:42:53,914 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-28 11:42:53,914 INFO L480 AbstractCegarLoop]: Abstraction has 104 states and 108 transitions. [2018-11-28 11:42:53,914 INFO L481 AbstractCegarLoop]: Interpolant automaton has 11 states. [2018-11-28 11:42:53,914 INFO L276 IsEmpty]: Start isEmpty. Operand 104 states and 108 transitions. [2018-11-28 11:42:53,915 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 74 [2018-11-28 11:42:53,915 INFO L394 BasicCegarLoop]: Found error trace [2018-11-28 11:42:53,915 INFO L402 BasicCegarLoop]: trace histogram [10, 10, 10, 4, 4, 4, 4, 4, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-28 11:42:53,915 INFO L423 AbstractCegarLoop]: === Iteration 15 === [getNumbers3Err0REQUIRES_VIOLATION, getNumbers3Err2REQUIRES_VIOLATION, getNumbers3Err1REQUIRES_VIOLATION, getNumbers3Err3REQUIRES_VIOLATION, getNumbers2Err2REQUIRES_VIOLATION, getNumbers2Err1REQUIRES_VIOLATION, getNumbers2Err3REQUIRES_VIOLATION, getNumbers2Err0REQUIRES_VIOLATION, getNumbers4Err2REQUIRES_VIOLATION, getNumbers4Err1REQUIRES_VIOLATION, getNumbers4Err3REQUIRES_VIOLATION, getNumbers4Err0REQUIRES_VIOLATION, mainErr2ENSURES_VIOLATIONMEMORY_LEAK, mainErr1REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION, getNumbersErr1REQUIRES_VIOLATION, getNumbersErr0REQUIRES_VIOLATION]=== [2018-11-28 11:42:53,915 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-28 11:42:53,915 INFO L82 PathProgramCache]: Analyzing trace with hash 1853794825, now seen corresponding path program 1 times [2018-11-28 11:42:53,915 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-28 11:42:53,916 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-28 11:42:53,916 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 11:42:53,916 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-28 11:42:53,916 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 11:42:53,925 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-28 11:42:53,952 INFO L134 CoverageAnalysis]: Checked inductivity of 179 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 179 trivial. 0 not checked. [2018-11-28 11:42:53,952 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-28 11:42:53,952 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2018-11-28 11:42:53,953 INFO L459 AbstractCegarLoop]: Interpolant automaton has 3 states [2018-11-28 11:42:53,953 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-28 11:42:53,953 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-28 11:42:53,953 INFO L87 Difference]: Start difference. First operand 104 states and 108 transitions. Second operand 3 states. [2018-11-28 11:42:53,964 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-28 11:42:53,964 INFO L93 Difference]: Finished difference Result 103 states and 107 transitions. [2018-11-28 11:42:53,965 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-28 11:42:53,965 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 73 [2018-11-28 11:42:53,965 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-28 11:42:53,965 INFO L225 Difference]: With dead ends: 103 [2018-11-28 11:42:53,965 INFO L226 Difference]: Without dead ends: 103 [2018-11-28 11:42:53,965 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 2 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-28 11:42:53,965 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 103 states. [2018-11-28 11:42:53,966 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 103 to 103. [2018-11-28 11:42:53,966 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 103 states. [2018-11-28 11:42:53,967 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 103 states to 103 states and 107 transitions. [2018-11-28 11:42:53,967 INFO L78 Accepts]: Start accepts. Automaton has 103 states and 107 transitions. Word has length 73 [2018-11-28 11:42:53,967 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-28 11:42:53,967 INFO L480 AbstractCegarLoop]: Abstraction has 103 states and 107 transitions. [2018-11-28 11:42:53,967 INFO L481 AbstractCegarLoop]: Interpolant automaton has 3 states. [2018-11-28 11:42:53,967 INFO L276 IsEmpty]: Start isEmpty. Operand 103 states and 107 transitions. [2018-11-28 11:42:53,968 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 74 [2018-11-28 11:42:53,968 INFO L394 BasicCegarLoop]: Found error trace [2018-11-28 11:42:53,968 INFO L402 BasicCegarLoop]: trace histogram [10, 10, 10, 4, 4, 4, 4, 4, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-28 11:42:53,968 INFO L423 AbstractCegarLoop]: === Iteration 16 === [getNumbers3Err0REQUIRES_VIOLATION, getNumbers3Err2REQUIRES_VIOLATION, getNumbers3Err1REQUIRES_VIOLATION, getNumbers3Err3REQUIRES_VIOLATION, getNumbers2Err2REQUIRES_VIOLATION, getNumbers2Err1REQUIRES_VIOLATION, getNumbers2Err3REQUIRES_VIOLATION, getNumbers2Err0REQUIRES_VIOLATION, getNumbers4Err2REQUIRES_VIOLATION, getNumbers4Err1REQUIRES_VIOLATION, getNumbers4Err3REQUIRES_VIOLATION, getNumbers4Err0REQUIRES_VIOLATION, mainErr2ENSURES_VIOLATIONMEMORY_LEAK, mainErr1REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION, getNumbersErr1REQUIRES_VIOLATION, getNumbersErr0REQUIRES_VIOLATION]=== [2018-11-28 11:42:53,968 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-28 11:42:53,968 INFO L82 PathProgramCache]: Analyzing trace with hash 1853794826, now seen corresponding path program 1 times [2018-11-28 11:42:53,968 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-28 11:42:53,968 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-28 11:42:53,968 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 11:42:53,969 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-28 11:42:53,969 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 11:42:53,977 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-28 11:42:54,019 INFO L134 CoverageAnalysis]: Checked inductivity of 179 backedges. 0 proven. 34 refuted. 0 times theorem prover too weak. 145 trivial. 0 not checked. [2018-11-28 11:42:54,019 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-28 11:42:54,019 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_3d9fc5bc-d65d-4259-979e-2e9bddd7decc/bin-2019/uautomizer/z3 Starting monitored process 13 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 13 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-28 11:42:54,028 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-28 11:42:54,059 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-28 11:42:54,061 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-28 11:42:54,068 INFO L134 CoverageAnalysis]: Checked inductivity of 179 backedges. 0 proven. 34 refuted. 0 times theorem prover too weak. 145 trivial. 0 not checked. [2018-11-28 11:42:54,082 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-11-28 11:42:54,083 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [7, 7] total 8 [2018-11-28 11:42:54,083 INFO L459 AbstractCegarLoop]: Interpolant automaton has 8 states [2018-11-28 11:42:54,083 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 8 interpolants. [2018-11-28 11:42:54,083 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=28, Invalid=28, Unknown=0, NotChecked=0, Total=56 [2018-11-28 11:42:54,083 INFO L87 Difference]: Start difference. First operand 103 states and 107 transitions. Second operand 8 states. [2018-11-28 11:42:54,101 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-28 11:42:54,101 INFO L93 Difference]: Finished difference Result 112 states and 116 transitions. [2018-11-28 11:42:54,105 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2018-11-28 11:42:54,105 INFO L78 Accepts]: Start accepts. Automaton has 8 states. Word has length 73 [2018-11-28 11:42:54,105 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-28 11:42:54,106 INFO L225 Difference]: With dead ends: 112 [2018-11-28 11:42:54,106 INFO L226 Difference]: Without dead ends: 112 [2018-11-28 11:42:54,106 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 79 GetRequests, 73 SyntacticMatches, 0 SemanticMatches, 6 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 6 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=28, Invalid=28, Unknown=0, NotChecked=0, Total=56 [2018-11-28 11:42:54,106 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 112 states. [2018-11-28 11:42:54,108 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 112 to 108. [2018-11-28 11:42:54,108 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 108 states. [2018-11-28 11:42:54,109 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 108 states to 108 states and 112 transitions. [2018-11-28 11:42:54,109 INFO L78 Accepts]: Start accepts. Automaton has 108 states and 112 transitions. Word has length 73 [2018-11-28 11:42:54,109 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-28 11:42:54,109 INFO L480 AbstractCegarLoop]: Abstraction has 108 states and 112 transitions. [2018-11-28 11:42:54,109 INFO L481 AbstractCegarLoop]: Interpolant automaton has 8 states. [2018-11-28 11:42:54,109 INFO L276 IsEmpty]: Start isEmpty. Operand 108 states and 112 transitions. [2018-11-28 11:42:54,110 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 79 [2018-11-28 11:42:54,110 INFO L394 BasicCegarLoop]: Found error trace [2018-11-28 11:42:54,110 INFO L402 BasicCegarLoop]: trace histogram [10, 10, 10, 5, 5, 5, 5, 5, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-28 11:42:54,110 INFO L423 AbstractCegarLoop]: === Iteration 17 === [getNumbers3Err0REQUIRES_VIOLATION, getNumbers3Err2REQUIRES_VIOLATION, getNumbers3Err1REQUIRES_VIOLATION, getNumbers3Err3REQUIRES_VIOLATION, getNumbers2Err2REQUIRES_VIOLATION, getNumbers2Err1REQUIRES_VIOLATION, getNumbers2Err3REQUIRES_VIOLATION, getNumbers2Err0REQUIRES_VIOLATION, getNumbers4Err2REQUIRES_VIOLATION, getNumbers4Err1REQUIRES_VIOLATION, getNumbers4Err3REQUIRES_VIOLATION, getNumbers4Err0REQUIRES_VIOLATION, mainErr2ENSURES_VIOLATIONMEMORY_LEAK, mainErr1REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION, getNumbersErr1REQUIRES_VIOLATION, getNumbersErr0REQUIRES_VIOLATION]=== [2018-11-28 11:42:54,110 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-28 11:42:54,110 INFO L82 PathProgramCache]: Analyzing trace with hash -1123262532, now seen corresponding path program 2 times [2018-11-28 11:42:54,111 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-28 11:42:54,111 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-28 11:42:54,111 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 11:42:54,111 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-28 11:42:54,111 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 11:42:54,122 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-28 11:42:54,172 INFO L134 CoverageAnalysis]: Checked inductivity of 200 backedges. 0 proven. 55 refuted. 0 times theorem prover too weak. 145 trivial. 0 not checked. [2018-11-28 11:42:54,172 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-28 11:42:54,172 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_3d9fc5bc-d65d-4259-979e-2e9bddd7decc/bin-2019/uautomizer/z3 Starting monitored process 14 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 14 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-28 11:42:54,181 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-11-28 11:42:54,208 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) [2018-11-28 11:42:54,208 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-11-28 11:42:54,210 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-28 11:42:54,216 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 6 treesize of output 5 [2018-11-28 11:42:54,216 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-11-28 11:42:54,221 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-28 11:42:54,221 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 1 variables, input treesize:13, output treesize:12 [2018-11-28 11:42:54,278 INFO L134 CoverageAnalysis]: Checked inductivity of 200 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 200 trivial. 0 not checked. [2018-11-28 11:42:54,303 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 1 imperfect interpolant sequences. [2018-11-28 11:42:54,303 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [8] total 10 [2018-11-28 11:42:54,304 INFO L459 AbstractCegarLoop]: Interpolant automaton has 10 states [2018-11-28 11:42:54,304 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 10 interpolants. [2018-11-28 11:42:54,304 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=33, Invalid=57, Unknown=0, NotChecked=0, Total=90 [2018-11-28 11:42:54,304 INFO L87 Difference]: Start difference. First operand 108 states and 112 transitions. Second operand 10 states. [2018-11-28 11:42:54,358 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-28 11:42:54,358 INFO L93 Difference]: Finished difference Result 116 states and 120 transitions. [2018-11-28 11:42:54,358 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 10 states. [2018-11-28 11:42:54,358 INFO L78 Accepts]: Start accepts. Automaton has 10 states. Word has length 78 [2018-11-28 11:42:54,358 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-28 11:42:54,359 INFO L225 Difference]: With dead ends: 116 [2018-11-28 11:42:54,359 INFO L226 Difference]: Without dead ends: 116 [2018-11-28 11:42:54,359 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 85 GetRequests, 77 SyntacticMatches, 0 SemanticMatches, 8 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 10 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=33, Invalid=57, Unknown=0, NotChecked=0, Total=90 [2018-11-28 11:42:54,359 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 116 states. [2018-11-28 11:42:54,361 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 116 to 112. [2018-11-28 11:42:54,361 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 112 states. [2018-11-28 11:42:54,362 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 112 states to 112 states and 116 transitions. [2018-11-28 11:42:54,362 INFO L78 Accepts]: Start accepts. Automaton has 112 states and 116 transitions. Word has length 78 [2018-11-28 11:42:54,362 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-28 11:42:54,362 INFO L480 AbstractCegarLoop]: Abstraction has 112 states and 116 transitions. [2018-11-28 11:42:54,362 INFO L481 AbstractCegarLoop]: Interpolant automaton has 10 states. [2018-11-28 11:42:54,362 INFO L276 IsEmpty]: Start isEmpty. Operand 112 states and 116 transitions. [2018-11-28 11:42:54,363 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 93 [2018-11-28 11:42:54,363 INFO L394 BasicCegarLoop]: Found error trace [2018-11-28 11:42:54,363 INFO L402 BasicCegarLoop]: trace histogram [10, 10, 10, 6, 6, 6, 6, 6, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-28 11:42:54,363 INFO L423 AbstractCegarLoop]: === Iteration 18 === [getNumbers3Err0REQUIRES_VIOLATION, getNumbers3Err2REQUIRES_VIOLATION, getNumbers3Err1REQUIRES_VIOLATION, getNumbers3Err3REQUIRES_VIOLATION, getNumbers2Err2REQUIRES_VIOLATION, getNumbers2Err1REQUIRES_VIOLATION, getNumbers2Err3REQUIRES_VIOLATION, getNumbers2Err0REQUIRES_VIOLATION, getNumbers4Err2REQUIRES_VIOLATION, getNumbers4Err1REQUIRES_VIOLATION, getNumbers4Err3REQUIRES_VIOLATION, getNumbers4Err0REQUIRES_VIOLATION, mainErr2ENSURES_VIOLATIONMEMORY_LEAK, mainErr1REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION, getNumbersErr1REQUIRES_VIOLATION, getNumbersErr0REQUIRES_VIOLATION]=== [2018-11-28 11:42:54,363 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-28 11:42:54,363 INFO L82 PathProgramCache]: Analyzing trace with hash -1854312006, now seen corresponding path program 1 times [2018-11-28 11:42:54,363 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-28 11:42:54,363 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-28 11:42:54,364 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 11:42:54,364 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-28 11:42:54,364 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 11:42:54,372 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-28 11:42:54,444 INFO L134 CoverageAnalysis]: Checked inductivity of 227 backedges. 0 proven. 81 refuted. 0 times theorem prover too weak. 146 trivial. 0 not checked. [2018-11-28 11:42:54,445 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-28 11:42:54,445 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_3d9fc5bc-d65d-4259-979e-2e9bddd7decc/bin-2019/uautomizer/z3 Starting monitored process 15 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 15 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-28 11:42:54,452 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-28 11:42:54,481 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-28 11:42:54,482 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-28 11:42:54,504 INFO L134 CoverageAnalysis]: Checked inductivity of 227 backedges. 0 proven. 81 refuted. 0 times theorem prover too weak. 146 trivial. 0 not checked. [2018-11-28 11:42:54,529 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-11-28 11:42:54,529 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [9, 9] total 10 [2018-11-28 11:42:54,529 INFO L459 AbstractCegarLoop]: Interpolant automaton has 10 states [2018-11-28 11:42:54,529 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 10 interpolants. [2018-11-28 11:42:54,529 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=45, Invalid=45, Unknown=0, NotChecked=0, Total=90 [2018-11-28 11:42:54,530 INFO L87 Difference]: Start difference. First operand 112 states and 116 transitions. Second operand 10 states. [2018-11-28 11:42:54,559 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-28 11:42:54,559 INFO L93 Difference]: Finished difference Result 121 states and 125 transitions. [2018-11-28 11:42:54,560 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2018-11-28 11:42:54,560 INFO L78 Accepts]: Start accepts. Automaton has 10 states. Word has length 92 [2018-11-28 11:42:54,561 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-28 11:42:54,561 INFO L225 Difference]: With dead ends: 121 [2018-11-28 11:42:54,561 INFO L226 Difference]: Without dead ends: 121 [2018-11-28 11:42:54,561 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 100 GetRequests, 92 SyntacticMatches, 0 SemanticMatches, 8 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 10 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=45, Invalid=45, Unknown=0, NotChecked=0, Total=90 [2018-11-28 11:42:54,562 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 121 states. [2018-11-28 11:42:54,563 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 121 to 117. [2018-11-28 11:42:54,563 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 117 states. [2018-11-28 11:42:54,564 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 117 states to 117 states and 121 transitions. [2018-11-28 11:42:54,564 INFO L78 Accepts]: Start accepts. Automaton has 117 states and 121 transitions. Word has length 92 [2018-11-28 11:42:54,564 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-28 11:42:54,564 INFO L480 AbstractCegarLoop]: Abstraction has 117 states and 121 transitions. [2018-11-28 11:42:54,564 INFO L481 AbstractCegarLoop]: Interpolant automaton has 10 states. [2018-11-28 11:42:54,564 INFO L276 IsEmpty]: Start isEmpty. Operand 117 states and 121 transitions. [2018-11-28 11:42:54,568 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 98 [2018-11-28 11:42:54,568 INFO L394 BasicCegarLoop]: Found error trace [2018-11-28 11:42:54,568 INFO L402 BasicCegarLoop]: trace histogram [10, 10, 10, 7, 7, 7, 7, 7, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-28 11:42:54,569 INFO L423 AbstractCegarLoop]: === Iteration 19 === [getNumbers3Err0REQUIRES_VIOLATION, getNumbers3Err2REQUIRES_VIOLATION, getNumbers3Err1REQUIRES_VIOLATION, getNumbers3Err3REQUIRES_VIOLATION, getNumbers2Err2REQUIRES_VIOLATION, getNumbers2Err1REQUIRES_VIOLATION, getNumbers2Err3REQUIRES_VIOLATION, getNumbers2Err0REQUIRES_VIOLATION, getNumbers4Err2REQUIRES_VIOLATION, getNumbers4Err1REQUIRES_VIOLATION, getNumbers4Err3REQUIRES_VIOLATION, getNumbers4Err0REQUIRES_VIOLATION, mainErr2ENSURES_VIOLATIONMEMORY_LEAK, mainErr1REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION, getNumbersErr1REQUIRES_VIOLATION, getNumbersErr0REQUIRES_VIOLATION]=== [2018-11-28 11:42:54,569 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-28 11:42:54,569 INFO L82 PathProgramCache]: Analyzing trace with hash 283421384, now seen corresponding path program 2 times [2018-11-28 11:42:54,569 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-28 11:42:54,569 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-28 11:42:54,569 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 11:42:54,570 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-28 11:42:54,570 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 11:42:54,580 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-28 11:42:54,646 INFO L134 CoverageAnalysis]: Checked inductivity of 258 backedges. 0 proven. 112 refuted. 0 times theorem prover too weak. 146 trivial. 0 not checked. [2018-11-28 11:42:54,646 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-28 11:42:54,646 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_3d9fc5bc-d65d-4259-979e-2e9bddd7decc/bin-2019/uautomizer/z3 Starting monitored process 16 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 16 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-28 11:42:54,653 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-11-28 11:42:54,684 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2018-11-28 11:42:54,684 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-11-28 11:42:54,686 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-28 11:42:54,693 INFO L134 CoverageAnalysis]: Checked inductivity of 258 backedges. 0 proven. 112 refuted. 0 times theorem prover too weak. 146 trivial. 0 not checked. [2018-11-28 11:42:54,707 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-11-28 11:42:54,707 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [10, 10] total 11 [2018-11-28 11:42:54,708 INFO L459 AbstractCegarLoop]: Interpolant automaton has 11 states [2018-11-28 11:42:54,708 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 11 interpolants. [2018-11-28 11:42:54,708 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=55, Invalid=55, Unknown=0, NotChecked=0, Total=110 [2018-11-28 11:42:54,708 INFO L87 Difference]: Start difference. First operand 117 states and 121 transitions. Second operand 11 states. [2018-11-28 11:42:54,732 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-28 11:42:54,732 INFO L93 Difference]: Finished difference Result 126 states and 130 transitions. [2018-11-28 11:42:54,732 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 10 states. [2018-11-28 11:42:54,732 INFO L78 Accepts]: Start accepts. Automaton has 11 states. Word has length 97 [2018-11-28 11:42:54,733 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-28 11:42:54,733 INFO L225 Difference]: With dead ends: 126 [2018-11-28 11:42:54,733 INFO L226 Difference]: Without dead ends: 126 [2018-11-28 11:42:54,733 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 106 GetRequests, 97 SyntacticMatches, 0 SemanticMatches, 9 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 12 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=55, Invalid=55, Unknown=0, NotChecked=0, Total=110 [2018-11-28 11:42:54,734 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 126 states. [2018-11-28 11:42:54,735 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 126 to 122. [2018-11-28 11:42:54,735 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 122 states. [2018-11-28 11:42:54,736 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 122 states to 122 states and 126 transitions. [2018-11-28 11:42:54,736 INFO L78 Accepts]: Start accepts. Automaton has 122 states and 126 transitions. Word has length 97 [2018-11-28 11:42:54,736 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-28 11:42:54,736 INFO L480 AbstractCegarLoop]: Abstraction has 122 states and 126 transitions. [2018-11-28 11:42:54,736 INFO L481 AbstractCegarLoop]: Interpolant automaton has 11 states. [2018-11-28 11:42:54,737 INFO L276 IsEmpty]: Start isEmpty. Operand 122 states and 126 transitions. [2018-11-28 11:42:54,737 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 103 [2018-11-28 11:42:54,737 INFO L394 BasicCegarLoop]: Found error trace [2018-11-28 11:42:54,737 INFO L402 BasicCegarLoop]: trace histogram [10, 10, 10, 8, 8, 8, 8, 8, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-28 11:42:54,737 INFO L423 AbstractCegarLoop]: === Iteration 20 === [getNumbers3Err0REQUIRES_VIOLATION, getNumbers3Err2REQUIRES_VIOLATION, getNumbers3Err1REQUIRES_VIOLATION, getNumbers3Err3REQUIRES_VIOLATION, getNumbers2Err2REQUIRES_VIOLATION, getNumbers2Err1REQUIRES_VIOLATION, getNumbers2Err3REQUIRES_VIOLATION, getNumbers2Err0REQUIRES_VIOLATION, getNumbers4Err2REQUIRES_VIOLATION, getNumbers4Err1REQUIRES_VIOLATION, getNumbers4Err3REQUIRES_VIOLATION, getNumbers4Err0REQUIRES_VIOLATION, mainErr2ENSURES_VIOLATIONMEMORY_LEAK, mainErr1REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION, getNumbersErr1REQUIRES_VIOLATION, getNumbersErr0REQUIRES_VIOLATION]=== [2018-11-28 11:42:54,738 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-28 11:42:54,738 INFO L82 PathProgramCache]: Analyzing trace with hash -663164294, now seen corresponding path program 3 times [2018-11-28 11:42:54,738 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-28 11:42:54,738 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-28 11:42:54,738 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 11:42:54,738 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-28 11:42:54,738 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 11:42:54,750 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-28 11:42:54,810 INFO L134 CoverageAnalysis]: Checked inductivity of 294 backedges. 0 proven. 148 refuted. 0 times theorem prover too weak. 146 trivial. 0 not checked. [2018-11-28 11:42:54,810 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-28 11:42:54,810 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_3d9fc5bc-d65d-4259-979e-2e9bddd7decc/bin-2019/uautomizer/z3 Starting monitored process 17 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 17 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-28 11:42:54,816 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-11-28 11:42:54,839 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 2 check-sat command(s) [2018-11-28 11:42:54,839 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-11-28 11:42:54,840 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-28 11:42:54,855 INFO L134 CoverageAnalysis]: Checked inductivity of 294 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 293 trivial. 0 not checked. [2018-11-28 11:42:54,869 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-11-28 11:42:54,869 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [11, 4] total 13 [2018-11-28 11:42:54,869 INFO L459 AbstractCegarLoop]: Interpolant automaton has 13 states [2018-11-28 11:42:54,869 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 13 interpolants. [2018-11-28 11:42:54,869 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=60, Invalid=96, Unknown=0, NotChecked=0, Total=156 [2018-11-28 11:42:54,870 INFO L87 Difference]: Start difference. First operand 122 states and 126 transitions. Second operand 13 states. [2018-11-28 11:42:54,906 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-28 11:42:54,906 INFO L93 Difference]: Finished difference Result 140 states and 144 transitions. [2018-11-28 11:42:54,906 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 13 states. [2018-11-28 11:42:54,906 INFO L78 Accepts]: Start accepts. Automaton has 13 states. Word has length 102 [2018-11-28 11:42:54,907 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-28 11:42:54,907 INFO L225 Difference]: With dead ends: 140 [2018-11-28 11:42:54,907 INFO L226 Difference]: Without dead ends: 140 [2018-11-28 11:42:54,907 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 112 GetRequests, 101 SyntacticMatches, 0 SemanticMatches, 11 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 16 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=60, Invalid=96, Unknown=0, NotChecked=0, Total=156 [2018-11-28 11:42:54,908 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 140 states. [2018-11-28 11:42:54,909 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 140 to 132. [2018-11-28 11:42:54,909 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 132 states. [2018-11-28 11:42:54,909 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 132 states to 132 states and 136 transitions. [2018-11-28 11:42:54,909 INFO L78 Accepts]: Start accepts. Automaton has 132 states and 136 transitions. Word has length 102 [2018-11-28 11:42:54,909 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-28 11:42:54,909 INFO L480 AbstractCegarLoop]: Abstraction has 132 states and 136 transitions. [2018-11-28 11:42:54,910 INFO L481 AbstractCegarLoop]: Interpolant automaton has 13 states. [2018-11-28 11:42:54,910 INFO L276 IsEmpty]: Start isEmpty. Operand 132 states and 136 transitions. [2018-11-28 11:42:54,910 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 113 [2018-11-28 11:42:54,910 INFO L394 BasicCegarLoop]: Found error trace [2018-11-28 11:42:54,910 INFO L402 BasicCegarLoop]: trace histogram [10, 10, 10, 9, 9, 9, 9, 9, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-28 11:42:54,910 INFO L423 AbstractCegarLoop]: === Iteration 21 === [getNumbers3Err0REQUIRES_VIOLATION, getNumbers3Err2REQUIRES_VIOLATION, getNumbers3Err1REQUIRES_VIOLATION, getNumbers3Err3REQUIRES_VIOLATION, getNumbers2Err2REQUIRES_VIOLATION, getNumbers2Err1REQUIRES_VIOLATION, getNumbers2Err3REQUIRES_VIOLATION, getNumbers2Err0REQUIRES_VIOLATION, getNumbers4Err2REQUIRES_VIOLATION, getNumbers4Err1REQUIRES_VIOLATION, getNumbers4Err3REQUIRES_VIOLATION, getNumbers4Err0REQUIRES_VIOLATION, mainErr2ENSURES_VIOLATIONMEMORY_LEAK, mainErr1REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION, getNumbersErr1REQUIRES_VIOLATION, getNumbersErr0REQUIRES_VIOLATION]=== [2018-11-28 11:42:54,910 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-28 11:42:54,910 INFO L82 PathProgramCache]: Analyzing trace with hash -138503934, now seen corresponding path program 4 times [2018-11-28 11:42:54,910 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-28 11:42:54,910 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-28 11:42:54,911 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 11:42:54,911 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-28 11:42:54,911 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 11:42:54,922 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-28 11:42:55,000 INFO L134 CoverageAnalysis]: Checked inductivity of 341 backedges. 0 proven. 189 refuted. 0 times theorem prover too weak. 152 trivial. 0 not checked. [2018-11-28 11:42:55,001 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-28 11:42:55,001 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_3d9fc5bc-d65d-4259-979e-2e9bddd7decc/bin-2019/uautomizer/z3 Starting monitored process 18 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 18 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-28 11:42:55,010 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-11-28 11:42:55,046 INFO L249 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-11-28 11:42:55,046 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-11-28 11:42:55,049 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-28 11:42:55,071 INFO L134 CoverageAnalysis]: Checked inductivity of 341 backedges. 0 proven. 189 refuted. 0 times theorem prover too weak. 152 trivial. 0 not checked. [2018-11-28 11:42:55,086 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-11-28 11:42:55,086 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [12, 12] total 13 [2018-11-28 11:42:55,086 INFO L459 AbstractCegarLoop]: Interpolant automaton has 13 states [2018-11-28 11:42:55,086 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 13 interpolants. [2018-11-28 11:42:55,086 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=78, Invalid=78, Unknown=0, NotChecked=0, Total=156 [2018-11-28 11:42:55,086 INFO L87 Difference]: Start difference. First operand 132 states and 136 transitions. Second operand 13 states. [2018-11-28 11:42:55,135 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-28 11:42:55,135 INFO L93 Difference]: Finished difference Result 137 states and 141 transitions. [2018-11-28 11:42:55,135 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 12 states. [2018-11-28 11:42:55,135 INFO L78 Accepts]: Start accepts. Automaton has 13 states. Word has length 112 [2018-11-28 11:42:55,136 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-28 11:42:55,136 INFO L225 Difference]: With dead ends: 137 [2018-11-28 11:42:55,136 INFO L226 Difference]: Without dead ends: 137 [2018-11-28 11:42:55,136 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 123 GetRequests, 112 SyntacticMatches, 0 SemanticMatches, 11 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 16 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=78, Invalid=78, Unknown=0, NotChecked=0, Total=156 [2018-11-28 11:42:55,137 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 137 states. [2018-11-28 11:42:55,139 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 137 to 137. [2018-11-28 11:42:55,139 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 137 states. [2018-11-28 11:42:55,139 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 137 states to 137 states and 141 transitions. [2018-11-28 11:42:55,139 INFO L78 Accepts]: Start accepts. Automaton has 137 states and 141 transitions. Word has length 112 [2018-11-28 11:42:55,140 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-28 11:42:55,140 INFO L480 AbstractCegarLoop]: Abstraction has 137 states and 141 transitions. [2018-11-28 11:42:55,140 INFO L481 AbstractCegarLoop]: Interpolant automaton has 13 states. [2018-11-28 11:42:55,140 INFO L276 IsEmpty]: Start isEmpty. Operand 137 states and 141 transitions. [2018-11-28 11:42:55,140 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 118 [2018-11-28 11:42:55,140 INFO L394 BasicCegarLoop]: Found error trace [2018-11-28 11:42:55,140 INFO L402 BasicCegarLoop]: trace histogram [10, 10, 10, 10, 10, 10, 10, 10, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-28 11:42:55,141 INFO L423 AbstractCegarLoop]: === Iteration 22 === [getNumbers3Err0REQUIRES_VIOLATION, getNumbers3Err2REQUIRES_VIOLATION, getNumbers3Err1REQUIRES_VIOLATION, getNumbers3Err3REQUIRES_VIOLATION, getNumbers2Err2REQUIRES_VIOLATION, getNumbers2Err1REQUIRES_VIOLATION, getNumbers2Err3REQUIRES_VIOLATION, getNumbers2Err0REQUIRES_VIOLATION, getNumbers4Err2REQUIRES_VIOLATION, getNumbers4Err1REQUIRES_VIOLATION, getNumbers4Err3REQUIRES_VIOLATION, getNumbers4Err0REQUIRES_VIOLATION, mainErr2ENSURES_VIOLATIONMEMORY_LEAK, mainErr1REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION, getNumbersErr1REQUIRES_VIOLATION, getNumbersErr0REQUIRES_VIOLATION]=== [2018-11-28 11:42:55,141 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-28 11:42:55,141 INFO L82 PathProgramCache]: Analyzing trace with hash 1387314960, now seen corresponding path program 5 times [2018-11-28 11:42:55,141 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-28 11:42:55,141 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-28 11:42:55,141 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 11:42:55,142 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-28 11:42:55,142 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 11:42:55,154 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-28 11:42:55,204 INFO L134 CoverageAnalysis]: Checked inductivity of 387 backedges. 0 proven. 7 refuted. 0 times theorem prover too weak. 380 trivial. 0 not checked. [2018-11-28 11:42:55,204 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-28 11:42:55,205 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_3d9fc5bc-d65d-4259-979e-2e9bddd7decc/bin-2019/uautomizer/z3 Starting monitored process 19 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 19 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-28 11:42:55,219 INFO L103 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-11-28 11:42:57,357 INFO L249 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 11 check-sat command(s) [2018-11-28 11:42:57,357 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-11-28 11:42:57,362 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-28 11:42:57,383 INFO L134 CoverageAnalysis]: Checked inductivity of 387 backedges. 0 proven. 7 refuted. 0 times theorem prover too weak. 380 trivial. 0 not checked. [2018-11-28 11:42:57,412 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-11-28 11:42:57,412 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [5, 5] total 6 [2018-11-28 11:42:57,412 INFO L459 AbstractCegarLoop]: Interpolant automaton has 6 states [2018-11-28 11:42:57,412 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2018-11-28 11:42:57,412 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=15, Invalid=15, Unknown=0, NotChecked=0, Total=30 [2018-11-28 11:42:57,412 INFO L87 Difference]: Start difference. First operand 137 states and 141 transitions. Second operand 6 states. [2018-11-28 11:42:57,434 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-28 11:42:57,434 INFO L93 Difference]: Finished difference Result 146 states and 150 transitions. [2018-11-28 11:42:57,437 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2018-11-28 11:42:57,437 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 117 [2018-11-28 11:42:57,437 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-28 11:42:57,438 INFO L225 Difference]: With dead ends: 146 [2018-11-28 11:42:57,438 INFO L226 Difference]: Without dead ends: 146 [2018-11-28 11:42:57,438 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 121 GetRequests, 117 SyntacticMatches, 0 SemanticMatches, 4 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=15, Invalid=15, Unknown=0, NotChecked=0, Total=30 [2018-11-28 11:42:57,438 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 146 states. [2018-11-28 11:42:57,440 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 146 to 142. [2018-11-28 11:42:57,441 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 142 states. [2018-11-28 11:42:57,441 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 142 states to 142 states and 146 transitions. [2018-11-28 11:42:57,441 INFO L78 Accepts]: Start accepts. Automaton has 142 states and 146 transitions. Word has length 117 [2018-11-28 11:42:57,441 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-28 11:42:57,442 INFO L480 AbstractCegarLoop]: Abstraction has 142 states and 146 transitions. [2018-11-28 11:42:57,442 INFO L481 AbstractCegarLoop]: Interpolant automaton has 6 states. [2018-11-28 11:42:57,442 INFO L276 IsEmpty]: Start isEmpty. Operand 142 states and 146 transitions. [2018-11-28 11:42:57,442 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 123 [2018-11-28 11:42:57,442 INFO L394 BasicCegarLoop]: Found error trace [2018-11-28 11:42:57,442 INFO L402 BasicCegarLoop]: trace histogram [10, 10, 10, 10, 10, 10, 10, 10, 3, 3, 3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-28 11:42:57,443 INFO L423 AbstractCegarLoop]: === Iteration 23 === [getNumbers3Err0REQUIRES_VIOLATION, getNumbers3Err2REQUIRES_VIOLATION, getNumbers3Err1REQUIRES_VIOLATION, getNumbers3Err3REQUIRES_VIOLATION, getNumbers2Err2REQUIRES_VIOLATION, getNumbers2Err1REQUIRES_VIOLATION, getNumbers2Err3REQUIRES_VIOLATION, getNumbers2Err0REQUIRES_VIOLATION, getNumbers4Err2REQUIRES_VIOLATION, getNumbers4Err1REQUIRES_VIOLATION, getNumbers4Err3REQUIRES_VIOLATION, getNumbers4Err0REQUIRES_VIOLATION, mainErr2ENSURES_VIOLATIONMEMORY_LEAK, mainErr1REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION, getNumbersErr1REQUIRES_VIOLATION, getNumbersErr0REQUIRES_VIOLATION]=== [2018-11-28 11:42:57,443 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-28 11:42:57,443 INFO L82 PathProgramCache]: Analyzing trace with hash -575903494, now seen corresponding path program 6 times [2018-11-28 11:42:57,443 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-28 11:42:57,443 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-28 11:42:57,443 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 11:42:57,444 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-28 11:42:57,444 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 11:42:57,456 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-28 11:42:57,513 INFO L134 CoverageAnalysis]: Checked inductivity of 398 backedges. 0 proven. 18 refuted. 0 times theorem prover too weak. 380 trivial. 0 not checked. [2018-11-28 11:42:57,513 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-28 11:42:57,513 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_3d9fc5bc-d65d-4259-979e-2e9bddd7decc/bin-2019/uautomizer/z3 Starting monitored process 20 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 20 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-28 11:42:57,527 INFO L103 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-11-28 11:42:57,825 INFO L249 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 7 check-sat command(s) [2018-11-28 11:42:57,825 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-11-28 11:42:57,828 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-28 11:42:57,862 INFO L134 CoverageAnalysis]: Checked inductivity of 398 backedges. 0 proven. 18 refuted. 0 times theorem prover too weak. 380 trivial. 0 not checked. [2018-11-28 11:42:57,879 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-11-28 11:42:57,879 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [6, 6] total 7 [2018-11-28 11:42:57,879 INFO L459 AbstractCegarLoop]: Interpolant automaton has 7 states [2018-11-28 11:42:57,879 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2018-11-28 11:42:57,879 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=21, Invalid=21, Unknown=0, NotChecked=0, Total=42 [2018-11-28 11:42:57,879 INFO L87 Difference]: Start difference. First operand 142 states and 146 transitions. Second operand 7 states. [2018-11-28 11:42:57,898 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-28 11:42:57,898 INFO L93 Difference]: Finished difference Result 151 states and 155 transitions. [2018-11-28 11:42:57,898 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2018-11-28 11:42:57,898 INFO L78 Accepts]: Start accepts. Automaton has 7 states. Word has length 122 [2018-11-28 11:42:57,898 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-28 11:42:57,898 INFO L225 Difference]: With dead ends: 151 [2018-11-28 11:42:57,899 INFO L226 Difference]: Without dead ends: 151 [2018-11-28 11:42:57,899 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 127 GetRequests, 122 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 4 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=21, Invalid=21, Unknown=0, NotChecked=0, Total=42 [2018-11-28 11:42:57,899 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 151 states. [2018-11-28 11:42:57,900 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 151 to 147. [2018-11-28 11:42:57,900 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 147 states. [2018-11-28 11:42:57,901 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 147 states to 147 states and 151 transitions. [2018-11-28 11:42:57,901 INFO L78 Accepts]: Start accepts. Automaton has 147 states and 151 transitions. Word has length 122 [2018-11-28 11:42:57,901 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-28 11:42:57,901 INFO L480 AbstractCegarLoop]: Abstraction has 147 states and 151 transitions. [2018-11-28 11:42:57,901 INFO L481 AbstractCegarLoop]: Interpolant automaton has 7 states. [2018-11-28 11:42:57,901 INFO L276 IsEmpty]: Start isEmpty. Operand 147 states and 151 transitions. [2018-11-28 11:42:57,901 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 128 [2018-11-28 11:42:57,901 INFO L394 BasicCegarLoop]: Found error trace [2018-11-28 11:42:57,901 INFO L402 BasicCegarLoop]: trace histogram [10, 10, 10, 10, 10, 10, 10, 10, 4, 4, 4, 4, 4, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-28 11:42:57,901 INFO L423 AbstractCegarLoop]: === Iteration 24 === [getNumbers3Err0REQUIRES_VIOLATION, getNumbers3Err2REQUIRES_VIOLATION, getNumbers3Err1REQUIRES_VIOLATION, getNumbers3Err3REQUIRES_VIOLATION, getNumbers2Err2REQUIRES_VIOLATION, getNumbers2Err1REQUIRES_VIOLATION, getNumbers2Err3REQUIRES_VIOLATION, getNumbers2Err0REQUIRES_VIOLATION, getNumbers4Err2REQUIRES_VIOLATION, getNumbers4Err1REQUIRES_VIOLATION, getNumbers4Err3REQUIRES_VIOLATION, getNumbers4Err0REQUIRES_VIOLATION, mainErr2ENSURES_VIOLATIONMEMORY_LEAK, mainErr1REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION, getNumbersErr1REQUIRES_VIOLATION, getNumbersErr0REQUIRES_VIOLATION]=== [2018-11-28 11:42:57,902 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-28 11:42:57,902 INFO L82 PathProgramCache]: Analyzing trace with hash -371170992, now seen corresponding path program 7 times [2018-11-28 11:42:57,902 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-28 11:42:57,902 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-28 11:42:57,902 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 11:42:57,902 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-28 11:42:57,902 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 11:42:57,913 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-28 11:42:57,968 INFO L134 CoverageAnalysis]: Checked inductivity of 414 backedges. 0 proven. 34 refuted. 0 times theorem prover too weak. 380 trivial. 0 not checked. [2018-11-28 11:42:57,968 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-28 11:42:57,968 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_3d9fc5bc-d65d-4259-979e-2e9bddd7decc/bin-2019/uautomizer/z3 Starting monitored process 21 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 21 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-28 11:42:57,988 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-28 11:42:58,041 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-28 11:42:58,045 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-28 11:42:58,073 INFO L134 CoverageAnalysis]: Checked inductivity of 414 backedges. 0 proven. 34 refuted. 0 times theorem prover too weak. 380 trivial. 0 not checked. [2018-11-28 11:42:58,098 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-11-28 11:42:58,098 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [7, 7] total 8 [2018-11-28 11:42:58,098 INFO L459 AbstractCegarLoop]: Interpolant automaton has 8 states [2018-11-28 11:42:58,099 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 8 interpolants. [2018-11-28 11:42:58,099 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=28, Invalid=28, Unknown=0, NotChecked=0, Total=56 [2018-11-28 11:42:58,099 INFO L87 Difference]: Start difference. First operand 147 states and 151 transitions. Second operand 8 states. [2018-11-28 11:42:58,121 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-28 11:42:58,121 INFO L93 Difference]: Finished difference Result 156 states and 160 transitions. [2018-11-28 11:42:58,122 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2018-11-28 11:42:58,122 INFO L78 Accepts]: Start accepts. Automaton has 8 states. Word has length 127 [2018-11-28 11:42:58,122 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-28 11:42:58,123 INFO L225 Difference]: With dead ends: 156 [2018-11-28 11:42:58,123 INFO L226 Difference]: Without dead ends: 156 [2018-11-28 11:42:58,123 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 133 GetRequests, 127 SyntacticMatches, 0 SemanticMatches, 6 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 6 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=28, Invalid=28, Unknown=0, NotChecked=0, Total=56 [2018-11-28 11:42:58,123 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 156 states. [2018-11-28 11:42:58,125 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 156 to 152. [2018-11-28 11:42:58,125 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 152 states. [2018-11-28 11:42:58,126 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 152 states to 152 states and 156 transitions. [2018-11-28 11:42:58,126 INFO L78 Accepts]: Start accepts. Automaton has 152 states and 156 transitions. Word has length 127 [2018-11-28 11:42:58,126 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-28 11:42:58,126 INFO L480 AbstractCegarLoop]: Abstraction has 152 states and 156 transitions. [2018-11-28 11:42:58,126 INFO L481 AbstractCegarLoop]: Interpolant automaton has 8 states. [2018-11-28 11:42:58,126 INFO L276 IsEmpty]: Start isEmpty. Operand 152 states and 156 transitions. [2018-11-28 11:42:58,127 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 133 [2018-11-28 11:42:58,127 INFO L394 BasicCegarLoop]: Found error trace [2018-11-28 11:42:58,127 INFO L402 BasicCegarLoop]: trace histogram [10, 10, 10, 10, 10, 10, 10, 10, 5, 5, 5, 5, 5, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-28 11:42:58,127 INFO L423 AbstractCegarLoop]: === Iteration 25 === [getNumbers3Err0REQUIRES_VIOLATION, getNumbers3Err2REQUIRES_VIOLATION, getNumbers3Err1REQUIRES_VIOLATION, getNumbers3Err3REQUIRES_VIOLATION, getNumbers2Err2REQUIRES_VIOLATION, getNumbers2Err1REQUIRES_VIOLATION, getNumbers2Err3REQUIRES_VIOLATION, getNumbers2Err0REQUIRES_VIOLATION, getNumbers4Err2REQUIRES_VIOLATION, getNumbers4Err1REQUIRES_VIOLATION, getNumbers4Err3REQUIRES_VIOLATION, getNumbers4Err0REQUIRES_VIOLATION, mainErr2ENSURES_VIOLATIONMEMORY_LEAK, mainErr1REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION, getNumbersErr1REQUIRES_VIOLATION, getNumbersErr0REQUIRES_VIOLATION]=== [2018-11-28 11:42:58,127 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-28 11:42:58,127 INFO L82 PathProgramCache]: Analyzing trace with hash 1244147386, now seen corresponding path program 8 times [2018-11-28 11:42:58,127 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-28 11:42:58,128 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-28 11:42:58,128 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 11:42:58,128 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-28 11:42:58,128 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 11:42:58,144 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-28 11:42:58,216 INFO L134 CoverageAnalysis]: Checked inductivity of 435 backedges. 0 proven. 55 refuted. 0 times theorem prover too weak. 380 trivial. 0 not checked. [2018-11-28 11:42:58,216 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-28 11:42:58,216 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_3d9fc5bc-d65d-4259-979e-2e9bddd7decc/bin-2019/uautomizer/z3 Starting monitored process 22 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 22 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-28 11:42:58,226 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-11-28 11:42:58,284 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2018-11-28 11:42:58,284 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-11-28 11:42:58,288 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-28 11:42:58,298 INFO L134 CoverageAnalysis]: Checked inductivity of 435 backedges. 0 proven. 55 refuted. 0 times theorem prover too weak. 380 trivial. 0 not checked. [2018-11-28 11:42:58,314 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-11-28 11:42:58,314 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [8, 8] total 9 [2018-11-28 11:42:58,315 INFO L459 AbstractCegarLoop]: Interpolant automaton has 9 states [2018-11-28 11:42:58,315 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 9 interpolants. [2018-11-28 11:42:58,315 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=36, Invalid=36, Unknown=0, NotChecked=0, Total=72 [2018-11-28 11:42:58,315 INFO L87 Difference]: Start difference. First operand 152 states and 156 transitions. Second operand 9 states. [2018-11-28 11:42:58,353 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-28 11:42:58,353 INFO L93 Difference]: Finished difference Result 161 states and 165 transitions. [2018-11-28 11:42:58,354 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 8 states. [2018-11-28 11:42:58,354 INFO L78 Accepts]: Start accepts. Automaton has 9 states. Word has length 132 [2018-11-28 11:42:58,354 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-28 11:42:58,354 INFO L225 Difference]: With dead ends: 161 [2018-11-28 11:42:58,354 INFO L226 Difference]: Without dead ends: 161 [2018-11-28 11:42:58,354 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 139 GetRequests, 132 SyntacticMatches, 0 SemanticMatches, 7 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 8 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=36, Invalid=36, Unknown=0, NotChecked=0, Total=72 [2018-11-28 11:42:58,355 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 161 states. [2018-11-28 11:42:58,357 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 161 to 157. [2018-11-28 11:42:58,357 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 157 states. [2018-11-28 11:42:58,358 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 157 states to 157 states and 161 transitions. [2018-11-28 11:42:58,358 INFO L78 Accepts]: Start accepts. Automaton has 157 states and 161 transitions. Word has length 132 [2018-11-28 11:42:58,358 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-28 11:42:58,358 INFO L480 AbstractCegarLoop]: Abstraction has 157 states and 161 transitions. [2018-11-28 11:42:58,358 INFO L481 AbstractCegarLoop]: Interpolant automaton has 9 states. [2018-11-28 11:42:58,358 INFO L276 IsEmpty]: Start isEmpty. Operand 157 states and 161 transitions. [2018-11-28 11:42:58,359 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 138 [2018-11-28 11:42:58,359 INFO L394 BasicCegarLoop]: Found error trace [2018-11-28 11:42:58,359 INFO L402 BasicCegarLoop]: trace histogram [10, 10, 10, 10, 10, 10, 10, 10, 6, 6, 6, 6, 6, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-28 11:42:58,359 INFO L423 AbstractCegarLoop]: === Iteration 26 === [getNumbers3Err0REQUIRES_VIOLATION, getNumbers3Err2REQUIRES_VIOLATION, getNumbers3Err1REQUIRES_VIOLATION, getNumbers3Err3REQUIRES_VIOLATION, getNumbers2Err2REQUIRES_VIOLATION, getNumbers2Err1REQUIRES_VIOLATION, getNumbers2Err3REQUIRES_VIOLATION, getNumbers2Err0REQUIRES_VIOLATION, getNumbers4Err2REQUIRES_VIOLATION, getNumbers4Err1REQUIRES_VIOLATION, getNumbers4Err3REQUIRES_VIOLATION, getNumbers4Err0REQUIRES_VIOLATION, mainErr2ENSURES_VIOLATIONMEMORY_LEAK, mainErr1REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION, getNumbersErr1REQUIRES_VIOLATION, getNumbersErr0REQUIRES_VIOLATION]=== [2018-11-28 11:42:58,360 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-28 11:42:58,360 INFO L82 PathProgramCache]: Analyzing trace with hash -2070269040, now seen corresponding path program 9 times [2018-11-28 11:42:58,360 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-28 11:42:58,360 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-28 11:42:58,360 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 11:42:58,360 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-28 11:42:58,361 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 11:42:58,373 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-28 11:42:58,439 INFO L134 CoverageAnalysis]: Checked inductivity of 461 backedges. 0 proven. 81 refuted. 0 times theorem prover too weak. 380 trivial. 0 not checked. [2018-11-28 11:42:58,439 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-28 11:42:58,439 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_3d9fc5bc-d65d-4259-979e-2e9bddd7decc/bin-2019/uautomizer/z3 Starting monitored process 23 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 23 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-28 11:42:58,452 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-11-28 11:42:58,659 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 7 check-sat command(s) [2018-11-28 11:42:58,660 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-11-28 11:42:58,662 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-28 11:42:58,683 INFO L134 CoverageAnalysis]: Checked inductivity of 461 backedges. 0 proven. 81 refuted. 0 times theorem prover too weak. 380 trivial. 0 not checked. [2018-11-28 11:42:58,699 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-11-28 11:42:58,699 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [9, 9] total 10 [2018-11-28 11:42:58,699 INFO L459 AbstractCegarLoop]: Interpolant automaton has 10 states [2018-11-28 11:42:58,699 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 10 interpolants. [2018-11-28 11:42:58,699 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=45, Invalid=45, Unknown=0, NotChecked=0, Total=90 [2018-11-28 11:42:58,699 INFO L87 Difference]: Start difference. First operand 157 states and 161 transitions. Second operand 10 states. [2018-11-28 11:42:58,736 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-28 11:42:58,736 INFO L93 Difference]: Finished difference Result 166 states and 170 transitions. [2018-11-28 11:42:58,736 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2018-11-28 11:42:58,736 INFO L78 Accepts]: Start accepts. Automaton has 10 states. Word has length 137 [2018-11-28 11:42:58,736 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-28 11:42:58,737 INFO L225 Difference]: With dead ends: 166 [2018-11-28 11:42:58,737 INFO L226 Difference]: Without dead ends: 166 [2018-11-28 11:42:58,737 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 145 GetRequests, 137 SyntacticMatches, 0 SemanticMatches, 8 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 10 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=45, Invalid=45, Unknown=0, NotChecked=0, Total=90 [2018-11-28 11:42:58,738 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 166 states. [2018-11-28 11:42:58,740 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 166 to 162. [2018-11-28 11:42:58,740 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 162 states. [2018-11-28 11:42:58,741 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 162 states to 162 states and 166 transitions. [2018-11-28 11:42:58,741 INFO L78 Accepts]: Start accepts. Automaton has 162 states and 166 transitions. Word has length 137 [2018-11-28 11:42:58,741 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-28 11:42:58,741 INFO L480 AbstractCegarLoop]: Abstraction has 162 states and 166 transitions. [2018-11-28 11:42:58,741 INFO L481 AbstractCegarLoop]: Interpolant automaton has 10 states. [2018-11-28 11:42:58,741 INFO L276 IsEmpty]: Start isEmpty. Operand 162 states and 166 transitions. [2018-11-28 11:42:58,742 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 143 [2018-11-28 11:42:58,742 INFO L394 BasicCegarLoop]: Found error trace [2018-11-28 11:42:58,742 INFO L402 BasicCegarLoop]: trace histogram [10, 10, 10, 10, 10, 10, 10, 10, 7, 7, 7, 7, 7, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-28 11:42:58,742 INFO L423 AbstractCegarLoop]: === Iteration 27 === [getNumbers3Err0REQUIRES_VIOLATION, getNumbers3Err2REQUIRES_VIOLATION, getNumbers3Err1REQUIRES_VIOLATION, getNumbers3Err3REQUIRES_VIOLATION, getNumbers2Err2REQUIRES_VIOLATION, getNumbers2Err1REQUIRES_VIOLATION, getNumbers2Err3REQUIRES_VIOLATION, getNumbers2Err0REQUIRES_VIOLATION, getNumbers4Err2REQUIRES_VIOLATION, getNumbers4Err1REQUIRES_VIOLATION, getNumbers4Err3REQUIRES_VIOLATION, getNumbers4Err0REQUIRES_VIOLATION, mainErr2ENSURES_VIOLATIONMEMORY_LEAK, mainErr1REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION, getNumbersErr1REQUIRES_VIOLATION, getNumbersErr0REQUIRES_VIOLATION]=== [2018-11-28 11:42:58,742 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-28 11:42:58,742 INFO L82 PathProgramCache]: Analyzing trace with hash 1106756730, now seen corresponding path program 10 times [2018-11-28 11:42:58,742 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-28 11:42:58,743 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-28 11:42:58,743 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 11:42:58,743 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-28 11:42:58,743 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 11:42:58,754 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-28 11:42:58,817 INFO L134 CoverageAnalysis]: Checked inductivity of 492 backedges. 0 proven. 112 refuted. 0 times theorem prover too weak. 380 trivial. 0 not checked. [2018-11-28 11:42:58,817 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-28 11:42:58,817 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_3d9fc5bc-d65d-4259-979e-2e9bddd7decc/bin-2019/uautomizer/z3 Starting monitored process 24 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 24 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-28 11:42:58,826 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-11-28 11:42:59,683 INFO L249 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-11-28 11:42:59,683 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-11-28 11:42:59,687 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-28 11:42:59,699 INFO L134 CoverageAnalysis]: Checked inductivity of 492 backedges. 0 proven. 112 refuted. 0 times theorem prover too weak. 380 trivial. 0 not checked. [2018-11-28 11:42:59,715 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-11-28 11:42:59,715 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [10, 10] total 11 [2018-11-28 11:42:59,715 INFO L459 AbstractCegarLoop]: Interpolant automaton has 11 states [2018-11-28 11:42:59,715 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 11 interpolants. [2018-11-28 11:42:59,715 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=55, Invalid=55, Unknown=0, NotChecked=0, Total=110 [2018-11-28 11:42:59,716 INFO L87 Difference]: Start difference. First operand 162 states and 166 transitions. Second operand 11 states. [2018-11-28 11:42:59,749 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-28 11:42:59,749 INFO L93 Difference]: Finished difference Result 171 states and 175 transitions. [2018-11-28 11:42:59,750 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 10 states. [2018-11-28 11:42:59,750 INFO L78 Accepts]: Start accepts. Automaton has 11 states. Word has length 142 [2018-11-28 11:42:59,750 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-28 11:42:59,750 INFO L225 Difference]: With dead ends: 171 [2018-11-28 11:42:59,750 INFO L226 Difference]: Without dead ends: 171 [2018-11-28 11:42:59,750 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 151 GetRequests, 142 SyntacticMatches, 0 SemanticMatches, 9 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 12 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=55, Invalid=55, Unknown=0, NotChecked=0, Total=110 [2018-11-28 11:42:59,751 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 171 states. [2018-11-28 11:42:59,753 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 171 to 167. [2018-11-28 11:42:59,753 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 167 states. [2018-11-28 11:42:59,754 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 167 states to 167 states and 171 transitions. [2018-11-28 11:42:59,754 INFO L78 Accepts]: Start accepts. Automaton has 167 states and 171 transitions. Word has length 142 [2018-11-28 11:42:59,754 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-28 11:42:59,754 INFO L480 AbstractCegarLoop]: Abstraction has 167 states and 171 transitions. [2018-11-28 11:42:59,754 INFO L481 AbstractCegarLoop]: Interpolant automaton has 11 states. [2018-11-28 11:42:59,754 INFO L276 IsEmpty]: Start isEmpty. Operand 167 states and 171 transitions. [2018-11-28 11:42:59,755 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 148 [2018-11-28 11:42:59,755 INFO L394 BasicCegarLoop]: Found error trace [2018-11-28 11:42:59,755 INFO L402 BasicCegarLoop]: trace histogram [10, 10, 10, 10, 10, 10, 10, 10, 8, 8, 8, 8, 8, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-28 11:42:59,755 INFO L423 AbstractCegarLoop]: === Iteration 28 === [getNumbers3Err0REQUIRES_VIOLATION, getNumbers3Err2REQUIRES_VIOLATION, getNumbers3Err1REQUIRES_VIOLATION, getNumbers3Err3REQUIRES_VIOLATION, getNumbers2Err2REQUIRES_VIOLATION, getNumbers2Err1REQUIRES_VIOLATION, getNumbers2Err3REQUIRES_VIOLATION, getNumbers2Err0REQUIRES_VIOLATION, getNumbers4Err2REQUIRES_VIOLATION, getNumbers4Err1REQUIRES_VIOLATION, getNumbers4Err3REQUIRES_VIOLATION, getNumbers4Err0REQUIRES_VIOLATION, mainErr2ENSURES_VIOLATIONMEMORY_LEAK, mainErr1REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION, getNumbersErr1REQUIRES_VIOLATION, getNumbersErr0REQUIRES_VIOLATION]=== [2018-11-28 11:42:59,755 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-28 11:42:59,755 INFO L82 PathProgramCache]: Analyzing trace with hash -1612565040, now seen corresponding path program 11 times [2018-11-28 11:42:59,755 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-28 11:42:59,756 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-28 11:42:59,756 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 11:42:59,756 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-28 11:42:59,756 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 11:42:59,770 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-28 11:42:59,917 INFO L134 CoverageAnalysis]: Checked inductivity of 528 backedges. 0 proven. 148 refuted. 0 times theorem prover too weak. 380 trivial. 0 not checked. [2018-11-28 11:42:59,917 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-28 11:42:59,917 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_3d9fc5bc-d65d-4259-979e-2e9bddd7decc/bin-2019/uautomizer/z3 Starting monitored process 25 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 25 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-28 11:42:59,935 INFO L103 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-11-28 11:43:11,224 INFO L249 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 11 check-sat command(s) [2018-11-28 11:43:11,224 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-11-28 11:43:11,234 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-28 11:43:11,246 INFO L134 CoverageAnalysis]: Checked inductivity of 528 backedges. 0 proven. 148 refuted. 0 times theorem prover too weak. 380 trivial. 0 not checked. [2018-11-28 11:43:11,278 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-11-28 11:43:11,278 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [11, 11] total 12 [2018-11-28 11:43:11,278 INFO L459 AbstractCegarLoop]: Interpolant automaton has 12 states [2018-11-28 11:43:11,279 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 12 interpolants. [2018-11-28 11:43:11,279 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=66, Invalid=66, Unknown=0, NotChecked=0, Total=132 [2018-11-28 11:43:11,279 INFO L87 Difference]: Start difference. First operand 167 states and 171 transitions. Second operand 12 states. [2018-11-28 11:43:11,316 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-28 11:43:11,317 INFO L93 Difference]: Finished difference Result 176 states and 180 transitions. [2018-11-28 11:43:11,317 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 11 states. [2018-11-28 11:43:11,317 INFO L78 Accepts]: Start accepts. Automaton has 12 states. Word has length 147 [2018-11-28 11:43:11,317 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-28 11:43:11,318 INFO L225 Difference]: With dead ends: 176 [2018-11-28 11:43:11,318 INFO L226 Difference]: Without dead ends: 176 [2018-11-28 11:43:11,318 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 157 GetRequests, 147 SyntacticMatches, 0 SemanticMatches, 10 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 14 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=66, Invalid=66, Unknown=0, NotChecked=0, Total=132 [2018-11-28 11:43:11,318 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 176 states. [2018-11-28 11:43:11,321 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 176 to 172. [2018-11-28 11:43:11,321 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 172 states. [2018-11-28 11:43:11,321 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 172 states to 172 states and 176 transitions. [2018-11-28 11:43:11,322 INFO L78 Accepts]: Start accepts. Automaton has 172 states and 176 transitions. Word has length 147 [2018-11-28 11:43:11,322 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-28 11:43:11,322 INFO L480 AbstractCegarLoop]: Abstraction has 172 states and 176 transitions. [2018-11-28 11:43:11,322 INFO L481 AbstractCegarLoop]: Interpolant automaton has 12 states. [2018-11-28 11:43:11,322 INFO L276 IsEmpty]: Start isEmpty. Operand 172 states and 176 transitions. [2018-11-28 11:43:11,326 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 153 [2018-11-28 11:43:11,326 INFO L394 BasicCegarLoop]: Found error trace [2018-11-28 11:43:11,326 INFO L402 BasicCegarLoop]: trace histogram [10, 10, 10, 10, 10, 10, 10, 10, 9, 9, 9, 9, 9, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-28 11:43:11,327 INFO L423 AbstractCegarLoop]: === Iteration 29 === [getNumbers3Err0REQUIRES_VIOLATION, getNumbers3Err2REQUIRES_VIOLATION, getNumbers3Err1REQUIRES_VIOLATION, getNumbers3Err3REQUIRES_VIOLATION, getNumbers2Err2REQUIRES_VIOLATION, getNumbers2Err1REQUIRES_VIOLATION, getNumbers2Err3REQUIRES_VIOLATION, getNumbers2Err0REQUIRES_VIOLATION, getNumbers4Err2REQUIRES_VIOLATION, getNumbers4Err1REQUIRES_VIOLATION, getNumbers4Err3REQUIRES_VIOLATION, getNumbers4Err0REQUIRES_VIOLATION, mainErr2ENSURES_VIOLATIONMEMORY_LEAK, mainErr1REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION, getNumbersErr1REQUIRES_VIOLATION, getNumbersErr0REQUIRES_VIOLATION]=== [2018-11-28 11:43:11,327 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-28 11:43:11,327 INFO L82 PathProgramCache]: Analyzing trace with hash -896062918, now seen corresponding path program 12 times [2018-11-28 11:43:11,327 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-28 11:43:11,327 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-28 11:43:11,327 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 11:43:11,328 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-28 11:43:11,328 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 11:43:11,347 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-28 11:43:11,451 INFO L134 CoverageAnalysis]: Checked inductivity of 569 backedges. 0 proven. 189 refuted. 0 times theorem prover too weak. 380 trivial. 0 not checked. [2018-11-28 11:43:11,451 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-28 11:43:11,451 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_3d9fc5bc-d65d-4259-979e-2e9bddd7decc/bin-2019/uautomizer/z3 Starting monitored process 26 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 26 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-28 11:43:11,462 INFO L103 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-11-28 11:43:13,435 INFO L249 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 11 check-sat command(s) [2018-11-28 11:43:13,436 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-11-28 11:43:13,441 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-28 11:43:13,489 INFO L134 CoverageAnalysis]: Checked inductivity of 569 backedges. 0 proven. 264 refuted. 0 times theorem prover too weak. 305 trivial. 0 not checked. [2018-11-28 11:43:13,505 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-11-28 11:43:13,505 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [12, 15] total 16 [2018-11-28 11:43:13,505 INFO L459 AbstractCegarLoop]: Interpolant automaton has 16 states [2018-11-28 11:43:13,505 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 16 interpolants. [2018-11-28 11:43:13,505 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=84, Invalid=156, Unknown=0, NotChecked=0, Total=240 [2018-11-28 11:43:13,505 INFO L87 Difference]: Start difference. First operand 172 states and 176 transitions. Second operand 16 states. [2018-11-28 11:43:13,572 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-28 11:43:13,572 INFO L93 Difference]: Finished difference Result 177 states and 181 transitions. [2018-11-28 11:43:13,572 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 15 states. [2018-11-28 11:43:13,572 INFO L78 Accepts]: Start accepts. Automaton has 16 states. Word has length 152 [2018-11-28 11:43:13,573 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-28 11:43:13,573 INFO L225 Difference]: With dead ends: 177 [2018-11-28 11:43:13,573 INFO L226 Difference]: Without dead ends: 177 [2018-11-28 11:43:13,573 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 163 GetRequests, 149 SyntacticMatches, 0 SemanticMatches, 14 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 43 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=84, Invalid=156, Unknown=0, NotChecked=0, Total=240 [2018-11-28 11:43:13,573 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 177 states. [2018-11-28 11:43:13,575 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 177 to 177. [2018-11-28 11:43:13,575 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 177 states. [2018-11-28 11:43:13,576 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 177 states to 177 states and 181 transitions. [2018-11-28 11:43:13,576 INFO L78 Accepts]: Start accepts. Automaton has 177 states and 181 transitions. Word has length 152 [2018-11-28 11:43:13,576 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-28 11:43:13,576 INFO L480 AbstractCegarLoop]: Abstraction has 177 states and 181 transitions. [2018-11-28 11:43:13,576 INFO L481 AbstractCegarLoop]: Interpolant automaton has 16 states. [2018-11-28 11:43:13,576 INFO L276 IsEmpty]: Start isEmpty. Operand 177 states and 181 transitions. [2018-11-28 11:43:13,577 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 158 [2018-11-28 11:43:13,577 INFO L394 BasicCegarLoop]: Found error trace [2018-11-28 11:43:13,577 INFO L402 BasicCegarLoop]: trace histogram [10, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-28 11:43:13,577 INFO L423 AbstractCegarLoop]: === Iteration 30 === [getNumbers3Err0REQUIRES_VIOLATION, getNumbers3Err2REQUIRES_VIOLATION, getNumbers3Err1REQUIRES_VIOLATION, getNumbers3Err3REQUIRES_VIOLATION, getNumbers2Err2REQUIRES_VIOLATION, getNumbers2Err1REQUIRES_VIOLATION, getNumbers2Err3REQUIRES_VIOLATION, getNumbers2Err0REQUIRES_VIOLATION, getNumbers4Err2REQUIRES_VIOLATION, getNumbers4Err1REQUIRES_VIOLATION, getNumbers4Err3REQUIRES_VIOLATION, getNumbers4Err0REQUIRES_VIOLATION, mainErr2ENSURES_VIOLATIONMEMORY_LEAK, mainErr1REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION, getNumbersErr1REQUIRES_VIOLATION, getNumbersErr0REQUIRES_VIOLATION]=== [2018-11-28 11:43:13,577 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-28 11:43:13,578 INFO L82 PathProgramCache]: Analyzing trace with hash 1136420880, now seen corresponding path program 13 times [2018-11-28 11:43:13,578 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-28 11:43:13,578 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-28 11:43:13,578 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 11:43:13,578 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-28 11:43:13,578 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 11:43:13,725 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-28 11:43:13,847 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-28 11:43:13,887 INFO L469 BasicCegarLoop]: Counterexample might be feasible [2018-11-28 11:43:13,944 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction CFG 28.11 11:43:13 BoogieIcfgContainer [2018-11-28 11:43:13,944 INFO L132 PluginConnector]: ------------------------ END TraceAbstraction---------------------------- [2018-11-28 11:43:13,944 INFO L113 PluginConnector]: ------------------------Witness Printer---------------------------- [2018-11-28 11:43:13,944 INFO L271 PluginConnector]: Initializing Witness Printer... [2018-11-28 11:43:13,944 INFO L276 PluginConnector]: Witness Printer initialized [2018-11-28 11:43:13,947 INFO L185 PluginConnector]: Executing the observer RCFGCatcher from plugin Witness Printer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 28.11 11:42:45" (3/4) ... [2018-11-28 11:43:13,949 INFO L138 WitnessPrinter]: Generating witness for reachability counterexample [2018-11-28 11:43:14,003 INFO L145 WitnessManager]: Wrote witness to /tmp/vcloud-vcloud-master/worker/working_dir_3d9fc5bc-d65d-4259-979e-2e9bddd7decc/bin-2019/uautomizer/witness.graphml [2018-11-28 11:43:14,003 INFO L132 PluginConnector]: ------------------------ END Witness Printer---------------------------- [2018-11-28 11:43:14,004 INFO L168 Benchmark]: Toolchain (without parser) took 29554.19 ms. Allocated memory was 1.0 GB in the beginning and 1.5 GB in the end (delta: 461.4 MB). Free memory was 953.3 MB in the beginning and 1.3 GB in the end (delta: -307.3 MB). Peak memory consumption was 154.0 MB. Max. memory is 11.5 GB. [2018-11-28 11:43:14,004 INFO L168 Benchmark]: CDTParser took 0.14 ms. Allocated memory is still 1.0 GB. Free memory is still 979.6 MB. There was no memory consumed. Max. memory is 11.5 GB. [2018-11-28 11:43:14,004 INFO L168 Benchmark]: CACSL2BoogieTranslator took 152.61 ms. Allocated memory is still 1.0 GB. Free memory was 953.3 MB in the beginning and 942.5 MB in the end (delta: 10.8 MB). Peak memory consumption was 10.8 MB. Max. memory is 11.5 GB. [2018-11-28 11:43:14,004 INFO L168 Benchmark]: Boogie Preprocessor took 69.96 ms. Allocated memory was 1.0 GB in the beginning and 1.2 GB in the end (delta: 165.7 MB). Free memory was 942.5 MB in the beginning and 1.2 GB in the end (delta: -218.7 MB). Peak memory consumption was 15.6 MB. Max. memory is 11.5 GB. [2018-11-28 11:43:14,008 INFO L168 Benchmark]: RCFGBuilder took 366.83 ms. Allocated memory is still 1.2 GB. Free memory was 1.2 GB in the beginning and 1.1 GB in the end (delta: 27.5 MB). Peak memory consumption was 27.5 MB. Max. memory is 11.5 GB. [2018-11-28 11:43:14,008 INFO L168 Benchmark]: TraceAbstraction took 28902.66 ms. Allocated memory was 1.2 GB in the beginning and 1.5 GB in the end (delta: 295.7 MB). Free memory was 1.1 GB in the beginning and 1.3 GB in the end (delta: -138.1 MB). Peak memory consumption was 157.6 MB. Max. memory is 11.5 GB. [2018-11-28 11:43:14,008 INFO L168 Benchmark]: Witness Printer took 58.92 ms. Allocated memory is still 1.5 GB. Free memory was 1.3 GB in the beginning and 1.3 GB in the end (delta: 11.1 MB). Peak memory consumption was 11.1 MB. Max. memory is 11.5 GB. [2018-11-28 11:43:14,010 INFO L336 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.14 ms. Allocated memory is still 1.0 GB. Free memory is still 979.6 MB. There was no memory consumed. Max. memory is 11.5 GB. * CACSL2BoogieTranslator took 152.61 ms. Allocated memory is still 1.0 GB. Free memory was 953.3 MB in the beginning and 942.5 MB in the end (delta: 10.8 MB). Peak memory consumption was 10.8 MB. Max. memory is 11.5 GB. * Boogie Preprocessor took 69.96 ms. Allocated memory was 1.0 GB in the beginning and 1.2 GB in the end (delta: 165.7 MB). Free memory was 942.5 MB in the beginning and 1.2 GB in the end (delta: -218.7 MB). Peak memory consumption was 15.6 MB. Max. memory is 11.5 GB. * RCFGBuilder took 366.83 ms. Allocated memory is still 1.2 GB. Free memory was 1.2 GB in the beginning and 1.1 GB in the end (delta: 27.5 MB). Peak memory consumption was 27.5 MB. Max. memory is 11.5 GB. * TraceAbstraction took 28902.66 ms. Allocated memory was 1.2 GB in the beginning and 1.5 GB in the end (delta: 295.7 MB). Free memory was 1.1 GB in the beginning and 1.3 GB in the end (delta: -138.1 MB). Peak memory consumption was 157.6 MB. Max. memory is 11.5 GB. * Witness Printer took 58.92 ms. Allocated memory is still 1.5 GB. Free memory was 1.3 GB in the beginning and 1.3 GB in the end (delta: 11.1 MB). Peak memory consumption was 11.1 MB. Max. memory is 11.5 GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - CounterExampleResult [Line: 38]: pointer dereference may fail pointer dereference may fail We found a FailurePath: [L6] static int array[10]; [L17] static int numbers2[10]; [L36] static int numbers4[10]; [L45] CALL getNumbers4() VAL [array={108:0}, numbers2={105:0}, numbers4={112:0}] [L35] CALL, EXPR getNumbers3() VAL [array={108:0}, numbers2={105:0}, numbers4={112:0}] [L25] CALL, EXPR getNumbers2() VAL [array={108:0}, numbers2={105:0}, numbers4={112:0}] [L16] CALL, EXPR getNumbers() VAL [array={108:0}, numbers2={105:0}, numbers4={112:0}] [L8] int i = 0; VAL [array={108:0}, i=0, numbers2={105:0}, numbers4={112:0}] [L8] COND TRUE i < 10 VAL [array={108:0}, i=0, numbers2={105:0}, numbers4={112:0}] [L9] array[i] = i VAL [array={108:0}, i=0, numbers2={105:0}, numbers4={112:0}] [L8] ++i VAL [array={108:0}, i=1, numbers2={105:0}, numbers4={112:0}] [L8] COND TRUE i < 10 VAL [array={108:0}, i=1, numbers2={105:0}, numbers4={112:0}] [L9] array[i] = i VAL [array={108:0}, i=1, numbers2={105:0}, numbers4={112:0}] [L8] ++i VAL [array={108:0}, i=2, numbers2={105:0}, numbers4={112:0}] [L8] COND TRUE i < 10 VAL [array={108:0}, i=2, numbers2={105:0}, numbers4={112:0}] [L9] array[i] = i VAL [array={108:0}, i=2, numbers2={105:0}, numbers4={112:0}] [L8] ++i VAL [array={108:0}, i=3, numbers2={105:0}, numbers4={112:0}] [L8] COND TRUE i < 10 VAL [array={108:0}, i=3, numbers2={105:0}, numbers4={112:0}] [L9] array[i] = i VAL [array={108:0}, i=3, numbers2={105:0}, numbers4={112:0}] [L8] ++i VAL [array={108:0}, i=4, numbers2={105:0}, numbers4={112:0}] [L8] COND TRUE i < 10 VAL [array={108:0}, i=4, numbers2={105:0}, numbers4={112:0}] [L9] array[i] = i VAL [array={108:0}, i=4, numbers2={105:0}, numbers4={112:0}] [L8] ++i VAL [array={108:0}, i=5, numbers2={105:0}, numbers4={112:0}] [L8] COND TRUE i < 10 VAL [array={108:0}, i=5, numbers2={105:0}, numbers4={112:0}] [L9] array[i] = i VAL [array={108:0}, i=5, numbers2={105:0}, numbers4={112:0}] [L8] ++i VAL [array={108:0}, i=6, numbers2={105:0}, numbers4={112:0}] [L8] COND TRUE i < 10 VAL [array={108:0}, i=6, numbers2={105:0}, numbers4={112:0}] [L9] array[i] = i VAL [array={108:0}, i=6, numbers2={105:0}, numbers4={112:0}] [L8] ++i VAL [array={108:0}, i=7, numbers2={105:0}, numbers4={112:0}] [L8] COND TRUE i < 10 VAL [array={108:0}, i=7, numbers2={105:0}, numbers4={112:0}] [L9] array[i] = i VAL [array={108:0}, i=7, numbers2={105:0}, numbers4={112:0}] [L8] ++i VAL [array={108:0}, i=8, numbers2={105:0}, numbers4={112:0}] [L8] COND TRUE i < 10 VAL [array={108:0}, i=8, numbers2={105:0}, numbers4={112:0}] [L9] array[i] = i VAL [array={108:0}, i=8, numbers2={105:0}, numbers4={112:0}] [L8] ++i VAL [array={108:0}, i=9, numbers2={105:0}, numbers4={112:0}] [L8] COND TRUE i < 10 VAL [array={108:0}, i=9, numbers2={105:0}, numbers4={112:0}] [L9] array[i] = i VAL [array={108:0}, i=9, numbers2={105:0}, numbers4={112:0}] [L8] ++i VAL [array={108:0}, i=10, numbers2={105:0}, numbers4={112:0}] [L8] COND FALSE !(i < 10) VAL [array={108:0}, i=10, numbers2={105:0}, numbers4={112:0}] [L12] return array; VAL [\result={108:0}, array={108:0}, i=10, numbers2={105:0}, numbers4={112:0}] [L16] RET, EXPR getNumbers() VAL [array={108:0}, getNumbers()={108:0}, numbers2={105:0}, numbers4={112:0}] [L16] int* numbers = getNumbers(); [L18] int i = 0; VAL [array={108:0}, i=0, numbers={108:0}, numbers2={105:0}, numbers4={112:0}] [L18] COND TRUE i < 10 VAL [array={108:0}, i=0, numbers={108:0}, numbers2={105:0}, numbers4={112:0}] [L19] EXPR numbers[i] VAL [array={108:0}, i=0, numbers={108:0}, numbers2={105:0}, numbers4={112:0}, numbers[i]=0] [L19] numbers2[i] = numbers[i] VAL [array={108:0}, i=0, numbers={108:0}, numbers2={105:0}, numbers4={112:0}, numbers[i]=0] [L18] ++i VAL [array={108:0}, i=1, numbers={108:0}, numbers2={105:0}, numbers4={112:0}] [L18] COND TRUE i < 10 VAL [array={108:0}, i=1, numbers={108:0}, numbers2={105:0}, numbers4={112:0}] [L19] EXPR numbers[i] VAL [array={108:0}, i=1, numbers={108:0}, numbers2={105:0}, numbers4={112:0}, numbers[i]=1] [L19] numbers2[i] = numbers[i] VAL [array={108:0}, i=1, numbers={108:0}, numbers2={105:0}, numbers4={112:0}, numbers[i]=1] [L18] ++i VAL [array={108:0}, i=2, numbers={108:0}, numbers2={105:0}, numbers4={112:0}] [L18] COND TRUE i < 10 VAL [array={108:0}, i=2, numbers={108:0}, numbers2={105:0}, numbers4={112:0}] [L19] EXPR numbers[i] VAL [array={108:0}, i=2, numbers={108:0}, numbers2={105:0}, numbers4={112:0}, numbers[i]=2] [L19] numbers2[i] = numbers[i] VAL [array={108:0}, i=2, numbers={108:0}, numbers2={105:0}, numbers4={112:0}, numbers[i]=2] [L18] ++i VAL [array={108:0}, i=3, numbers={108:0}, numbers2={105:0}, numbers4={112:0}] [L18] COND TRUE i < 10 VAL [array={108:0}, i=3, numbers={108:0}, numbers2={105:0}, numbers4={112:0}] [L19] EXPR numbers[i] VAL [array={108:0}, i=3, numbers={108:0}, numbers2={105:0}, numbers4={112:0}, numbers[i]=3] [L19] numbers2[i] = numbers[i] VAL [array={108:0}, i=3, numbers={108:0}, numbers2={105:0}, numbers4={112:0}, numbers[i]=3] [L18] ++i VAL [array={108:0}, i=4, numbers={108:0}, numbers2={105:0}, numbers4={112:0}] [L18] COND TRUE i < 10 VAL [array={108:0}, i=4, numbers={108:0}, numbers2={105:0}, numbers4={112:0}] [L19] EXPR numbers[i] VAL [array={108:0}, i=4, numbers={108:0}, numbers2={105:0}, numbers4={112:0}, numbers[i]=4] [L19] numbers2[i] = numbers[i] VAL [array={108:0}, i=4, numbers={108:0}, numbers2={105:0}, numbers4={112:0}, numbers[i]=4] [L18] ++i VAL [array={108:0}, i=5, numbers={108:0}, numbers2={105:0}, numbers4={112:0}] [L18] COND TRUE i < 10 VAL [array={108:0}, i=5, numbers={108:0}, numbers2={105:0}, numbers4={112:0}] [L19] EXPR numbers[i] VAL [array={108:0}, i=5, numbers={108:0}, numbers2={105:0}, numbers4={112:0}, numbers[i]=5] [L19] numbers2[i] = numbers[i] VAL [array={108:0}, i=5, numbers={108:0}, numbers2={105:0}, numbers4={112:0}, numbers[i]=5] [L18] ++i VAL [array={108:0}, i=6, numbers={108:0}, numbers2={105:0}, numbers4={112:0}] [L18] COND TRUE i < 10 VAL [array={108:0}, i=6, numbers={108:0}, numbers2={105:0}, numbers4={112:0}] [L19] EXPR numbers[i] VAL [array={108:0}, i=6, numbers={108:0}, numbers2={105:0}, numbers4={112:0}, numbers[i]=6] [L19] numbers2[i] = numbers[i] VAL [array={108:0}, i=6, numbers={108:0}, numbers2={105:0}, numbers4={112:0}, numbers[i]=6] [L18] ++i VAL [array={108:0}, i=7, numbers={108:0}, numbers2={105:0}, numbers4={112:0}] [L18] COND TRUE i < 10 VAL [array={108:0}, i=7, numbers={108:0}, numbers2={105:0}, numbers4={112:0}] [L19] EXPR numbers[i] VAL [array={108:0}, i=7, numbers={108:0}, numbers2={105:0}, numbers4={112:0}, numbers[i]=7] [L19] numbers2[i] = numbers[i] VAL [array={108:0}, i=7, numbers={108:0}, numbers2={105:0}, numbers4={112:0}, numbers[i]=7] [L18] ++i VAL [array={108:0}, i=8, numbers={108:0}, numbers2={105:0}, numbers4={112:0}] [L18] COND TRUE i < 10 VAL [array={108:0}, i=8, numbers={108:0}, numbers2={105:0}, numbers4={112:0}] [L19] EXPR numbers[i] VAL [array={108:0}, i=8, numbers={108:0}, numbers2={105:0}, numbers4={112:0}, numbers[i]=8] [L19] numbers2[i] = numbers[i] VAL [array={108:0}, i=8, numbers={108:0}, numbers2={105:0}, numbers4={112:0}, numbers[i]=8] [L18] ++i VAL [array={108:0}, i=9, numbers={108:0}, numbers2={105:0}, numbers4={112:0}] [L18] COND TRUE i < 10 VAL [array={108:0}, i=9, numbers={108:0}, numbers2={105:0}, numbers4={112:0}] [L19] EXPR numbers[i] VAL [array={108:0}, i=9, numbers={108:0}, numbers2={105:0}, numbers4={112:0}, numbers[i]=9] [L19] numbers2[i] = numbers[i] VAL [array={108:0}, i=9, numbers={108:0}, numbers2={105:0}, numbers4={112:0}, numbers[i]=9] [L18] ++i VAL [array={108:0}, i=10, numbers={108:0}, numbers2={105:0}, numbers4={112:0}] [L18] COND FALSE !(i < 10) VAL [array={108:0}, i=10, numbers={108:0}, numbers2={105:0}, numbers4={112:0}] [L21] return numbers2; VAL [\result={105:0}, array={108:0}, i=10, numbers={108:0}, numbers2={105:0}, numbers4={112:0}] [L25] RET, EXPR getNumbers2() VAL [array={108:0}, getNumbers2()={105:0}, numbers2={105:0}, numbers4={112:0}] [L25] int* numbers = getNumbers2(); [L26] int numbers3[10]; [L27] int i = 0; VAL [array={108:0}, i=0, numbers={105:0}, numbers2={105:0}, numbers3={106:0}, numbers4={112:0}] [L27] COND TRUE i < 10 VAL [array={108:0}, i=0, numbers={105:0}, numbers2={105:0}, numbers3={106:0}, numbers4={112:0}] [L28] EXPR numbers[i] VAL [array={108:0}, i=0, numbers={105:0}, numbers2={105:0}, numbers3={106:0}, numbers4={112:0}, numbers[i]=0] [L28] numbers3[i] = numbers[i] VAL [array={108:0}, i=0, numbers={105:0}, numbers2={105:0}, numbers3={106:0}, numbers4={112:0}, numbers[i]=0] [L27] ++i VAL [array={108:0}, i=1, numbers={105:0}, numbers2={105:0}, numbers3={106:0}, numbers4={112:0}] [L27] COND TRUE i < 10 VAL [array={108:0}, i=1, numbers={105:0}, numbers2={105:0}, numbers3={106:0}, numbers4={112:0}] [L28] EXPR numbers[i] VAL [array={108:0}, i=1, numbers={105:0}, numbers2={105:0}, numbers3={106:0}, numbers4={112:0}, numbers[i]=1] [L28] numbers3[i] = numbers[i] VAL [array={108:0}, i=1, numbers={105:0}, numbers2={105:0}, numbers3={106:0}, numbers4={112:0}, numbers[i]=1] [L27] ++i VAL [array={108:0}, i=2, numbers={105:0}, numbers2={105:0}, numbers3={106:0}, numbers4={112:0}] [L27] COND TRUE i < 10 VAL [array={108:0}, i=2, numbers={105:0}, numbers2={105:0}, numbers3={106:0}, numbers4={112:0}] [L28] EXPR numbers[i] VAL [array={108:0}, i=2, numbers={105:0}, numbers2={105:0}, numbers3={106:0}, numbers4={112:0}, numbers[i]=2] [L28] numbers3[i] = numbers[i] VAL [array={108:0}, i=2, numbers={105:0}, numbers2={105:0}, numbers3={106:0}, numbers4={112:0}, numbers[i]=2] [L27] ++i VAL [array={108:0}, i=3, numbers={105:0}, numbers2={105:0}, numbers3={106:0}, numbers4={112:0}] [L27] COND TRUE i < 10 VAL [array={108:0}, i=3, numbers={105:0}, numbers2={105:0}, numbers3={106:0}, numbers4={112:0}] [L28] EXPR numbers[i] VAL [array={108:0}, i=3, numbers={105:0}, numbers2={105:0}, numbers3={106:0}, numbers4={112:0}, numbers[i]=3] [L28] numbers3[i] = numbers[i] VAL [array={108:0}, i=3, numbers={105:0}, numbers2={105:0}, numbers3={106:0}, numbers4={112:0}, numbers[i]=3] [L27] ++i VAL [array={108:0}, i=4, numbers={105:0}, numbers2={105:0}, numbers3={106:0}, numbers4={112:0}] [L27] COND TRUE i < 10 VAL [array={108:0}, i=4, numbers={105:0}, numbers2={105:0}, numbers3={106:0}, numbers4={112:0}] [L28] EXPR numbers[i] VAL [array={108:0}, i=4, numbers={105:0}, numbers2={105:0}, numbers3={106:0}, numbers4={112:0}, numbers[i]=4] [L28] numbers3[i] = numbers[i] VAL [array={108:0}, i=4, numbers={105:0}, numbers2={105:0}, numbers3={106:0}, numbers4={112:0}, numbers[i]=4] [L27] ++i VAL [array={108:0}, i=5, numbers={105:0}, numbers2={105:0}, numbers3={106:0}, numbers4={112:0}] [L27] COND TRUE i < 10 VAL [array={108:0}, i=5, numbers={105:0}, numbers2={105:0}, numbers3={106:0}, numbers4={112:0}] [L28] EXPR numbers[i] VAL [array={108:0}, i=5, numbers={105:0}, numbers2={105:0}, numbers3={106:0}, numbers4={112:0}, numbers[i]=5] [L28] numbers3[i] = numbers[i] VAL [array={108:0}, i=5, numbers={105:0}, numbers2={105:0}, numbers3={106:0}, numbers4={112:0}, numbers[i]=5] [L27] ++i VAL [array={108:0}, i=6, numbers={105:0}, numbers2={105:0}, numbers3={106:0}, numbers4={112:0}] [L27] COND TRUE i < 10 VAL [array={108:0}, i=6, numbers={105:0}, numbers2={105:0}, numbers3={106:0}, numbers4={112:0}] [L28] EXPR numbers[i] VAL [array={108:0}, i=6, numbers={105:0}, numbers2={105:0}, numbers3={106:0}, numbers4={112:0}, numbers[i]=6] [L28] numbers3[i] = numbers[i] VAL [array={108:0}, i=6, numbers={105:0}, numbers2={105:0}, numbers3={106:0}, numbers4={112:0}, numbers[i]=6] [L27] ++i VAL [array={108:0}, i=7, numbers={105:0}, numbers2={105:0}, numbers3={106:0}, numbers4={112:0}] [L27] COND TRUE i < 10 VAL [array={108:0}, i=7, numbers={105:0}, numbers2={105:0}, numbers3={106:0}, numbers4={112:0}] [L28] EXPR numbers[i] VAL [array={108:0}, i=7, numbers={105:0}, numbers2={105:0}, numbers3={106:0}, numbers4={112:0}, numbers[i]=7] [L28] numbers3[i] = numbers[i] VAL [array={108:0}, i=7, numbers={105:0}, numbers2={105:0}, numbers3={106:0}, numbers4={112:0}, numbers[i]=7] [L27] ++i VAL [array={108:0}, i=8, numbers={105:0}, numbers2={105:0}, numbers3={106:0}, numbers4={112:0}] [L27] COND TRUE i < 10 VAL [array={108:0}, i=8, numbers={105:0}, numbers2={105:0}, numbers3={106:0}, numbers4={112:0}] [L28] EXPR numbers[i] VAL [array={108:0}, i=8, numbers={105:0}, numbers2={105:0}, numbers3={106:0}, numbers4={112:0}, numbers[i]=8] [L28] numbers3[i] = numbers[i] VAL [array={108:0}, i=8, numbers={105:0}, numbers2={105:0}, numbers3={106:0}, numbers4={112:0}, numbers[i]=8] [L27] ++i VAL [array={108:0}, i=9, numbers={105:0}, numbers2={105:0}, numbers3={106:0}, numbers4={112:0}] [L27] COND TRUE i < 10 VAL [array={108:0}, i=9, numbers={105:0}, numbers2={105:0}, numbers3={106:0}, numbers4={112:0}] [L28] EXPR numbers[i] VAL [array={108:0}, i=9, numbers={105:0}, numbers2={105:0}, numbers3={106:0}, numbers4={112:0}, numbers[i]=9] [L28] numbers3[i] = numbers[i] VAL [array={108:0}, i=9, numbers={105:0}, numbers2={105:0}, numbers3={106:0}, numbers4={112:0}, numbers[i]=9] [L27] ++i VAL [array={108:0}, i=10, numbers={105:0}, numbers2={105:0}, numbers3={106:0}, numbers4={112:0}] [L27] COND FALSE !(i < 10) VAL [array={108:0}, i=10, numbers={105:0}, numbers2={105:0}, numbers3={106:0}, numbers4={112:0}] [L31] return numbers3; [L31] return numbers3; VAL [\result={106:0}, array={108:0}, i=10, numbers={105:0}, numbers2={105:0}, numbers4={112:0}] [L35] RET, EXPR getNumbers3() VAL [array={108:0}, getNumbers3()={106:0}, numbers2={105:0}, numbers4={112:0}] [L35] int* numbers = getNumbers3(); [L37] int i = 0; VAL [array={108:0}, i=0, numbers={106:0}, numbers2={105:0}, numbers4={112:0}] [L37] COND TRUE i < 10 VAL [array={108:0}, i=0, numbers={106:0}, numbers2={105:0}, numbers4={112:0}] [L38] numbers[i] - StatisticsResult: Ultimate Automizer benchmark data CFG has 7 procedures, 70 locations, 17 error locations. UNSAFE Result, 28.8s OverallTime, 30 OverallIterations, 10 TraceHistogramMax, 3.4s AutomataDifference, 0.0s DeadEndRemovalTime, 0.0s HoareAnnotationTime, HoareTripleCheckerStatistics: 1635 SDtfs, 877 SDslu, 8537 SDs, 0 SdLazy, 1947 SolverSat, 79 SolverUnsat, 0 SolverUnknown, 0 SolverNotchecked, 1.1s Time, PredicateUnifierStatistics: 0 DeclaredPredicates, 2332 GetRequests, 2074 SyntacticMatches, 8 SemanticMatches, 250 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 448 ImplicationChecksByTransitivity, 4.1s Time, 0.0s BasicInterpolantAutomatonTime, BiggestAbstraction: size=177occurred in iteration=29, traceCheckStatistics: No data available, InterpolantConsolidationStatistics: No data available, PathInvariantsStatistics: No data available, 0/0 InterpolantCoveringCapability, TotalInterpolationStatistics: No data available, 0.0s AbstIntTime, 0 AbstIntIterations, 0 AbstIntStrong, NaN AbsIntWeakeningRatio, NaN AbsIntAvgWeakeningVarsNumRemoved, NaN AbsIntAvgWeakenedConjuncts, 0.0s DumpTime, AutomataMinimizationStatistics: 0.1s AutomataMinimizationTime, 29 MinimizatonAttempts, 77 StatesRemovedByMinimization, 22 NontrivialMinimizations, HoareAnnotationStatistics: No data available, RefinementEngineStatistics: TraceCheckStatistics: 0.2s SsaConstructionTime, 17.5s SatisfiabilityAnalysisTime, 6.2s InterpolantComputationTime, 4460 NumberOfCodeBlocks, 4143 NumberOfCodeBlocksAsserted, 101 NumberOfCheckSat, 4249 ConstructedInterpolants, 234 QuantifiedInterpolants, 1571669 SizeOfPredicates, 64 NumberOfNonLiveVariables, 8730 ConjunctsInSsa, 285 ConjunctsInUnsatCore, 54 InterpolantComputations, 10 PerfectInterpolantSequences, 9214/12283 InterpolantCoveringCapability, InvariantSynthesisStatistics: No data available, InterpolantConsolidationStatistics: No data available, ReuseStatistics: No data available RESULT: Ultimate proved your program to be incorrect! Received shutdown request...