./Ultimate.py --spec ../../sv-benchmarks/c/properties/valid-memsafety.prp --file ../../sv-benchmarks/c/ldv-memsafety/memleaks_test22_1_false-valid-memtrack_true-termination.i --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for memory safety (deref-memtrack) Using default analysis Version 0cd3be1d Calling Ultimate with: java -Dosgi.configuration.area=/tmp/vcloud-vcloud-master/worker/working_dir_2ca7a644-5b0a-4f3d-9179-f30a2c52dfce/bin-2019/uautomizer/data/config -Xmx12G -Xms1G -jar /tmp/vcloud-vcloud-master/worker/working_dir_2ca7a644-5b0a-4f3d-9179-f30a2c52dfce/bin-2019/uautomizer/plugins/org.eclipse.equinox.launcher_1.3.100.v20150511-1540.jar -data @noDefault -ultimatedata /tmp/vcloud-vcloud-master/worker/working_dir_2ca7a644-5b0a-4f3d-9179-f30a2c52dfce/bin-2019/uautomizer/data -tc /tmp/vcloud-vcloud-master/worker/working_dir_2ca7a644-5b0a-4f3d-9179-f30a2c52dfce/bin-2019/uautomizer/config/AutomizerMemDerefMemtrack.xml -i ../../sv-benchmarks/c/ldv-memsafety/memleaks_test22_1_false-valid-memtrack_true-termination.i -s /tmp/vcloud-vcloud-master/worker/working_dir_2ca7a644-5b0a-4f3d-9179-f30a2c52dfce/bin-2019/uautomizer/config/svcomp-DerefFreeMemtrack-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud-vcloud-master/worker/working_dir_2ca7a644-5b0a-4f3d-9179-f30a2c52dfce/bin-2019/uautomizer --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(G valid-free) ) CHECK( init(main()), LTL(G valid-deref) ) CHECK( init(main()), LTL(G valid-memtrack) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash 4867b1d8e60a05de2199d52aa990071fe8bd647c ............................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................ Execution finished normally Using bit-precise analysis Retrying with bit-precise analysis Calling Ultimate with: java -Dosgi.configuration.area=/tmp/vcloud-vcloud-master/worker/working_dir_2ca7a644-5b0a-4f3d-9179-f30a2c52dfce/bin-2019/uautomizer/data/config -Xmx12G -Xms1G -jar /tmp/vcloud-vcloud-master/worker/working_dir_2ca7a644-5b0a-4f3d-9179-f30a2c52dfce/bin-2019/uautomizer/plugins/org.eclipse.equinox.launcher_1.3.100.v20150511-1540.jar -data @noDefault -ultimatedata /tmp/vcloud-vcloud-master/worker/working_dir_2ca7a644-5b0a-4f3d-9179-f30a2c52dfce/bin-2019/uautomizer/data -tc /tmp/vcloud-vcloud-master/worker/working_dir_2ca7a644-5b0a-4f3d-9179-f30a2c52dfce/bin-2019/uautomizer/config/AutomizerMemDerefMemtrack.xml -i ../../sv-benchmarks/c/ldv-memsafety/memleaks_test22_1_false-valid-memtrack_true-termination.i -s /tmp/vcloud-vcloud-master/worker/working_dir_2ca7a644-5b0a-4f3d-9179-f30a2c52dfce/bin-2019/uautomizer/config/svcomp-DerefFreeMemtrack-32bit-Automizer_Bitvector.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud-vcloud-master/worker/working_dir_2ca7a644-5b0a-4f3d-9179-f30a2c52dfce/bin-2019/uautomizer --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(G valid-free) ) CHECK( init(main()), LTL(G valid-deref) ) CHECK( init(main()), LTL(G valid-memtrack) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash 4867b1d8e60a05de2199d52aa990071fe8bd647c ........................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................... Execution finished normally Writing output log to file Ultimate.log Result: UNKNOWN: Overapproximated counterexample --- Real Ultimate output --- This is Ultimate 0.1.23-0cd3be1 [2018-11-28 11:25:36,952 INFO L170 SettingsManager]: Resetting all preferences to default values... [2018-11-28 11:25:36,954 INFO L174 SettingsManager]: Resetting UltimateCore preferences to default values [2018-11-28 11:25:36,962 INFO L177 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2018-11-28 11:25:36,962 INFO L174 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2018-11-28 11:25:36,963 INFO L174 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2018-11-28 11:25:36,964 INFO L174 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2018-11-28 11:25:36,965 INFO L174 SettingsManager]: Resetting LassoRanker preferences to default values [2018-11-28 11:25:36,966 INFO L174 SettingsManager]: Resetting Reaching Definitions preferences to default values [2018-11-28 11:25:36,967 INFO L174 SettingsManager]: Resetting SyntaxChecker preferences to default values [2018-11-28 11:25:36,968 INFO L177 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2018-11-28 11:25:36,968 INFO L174 SettingsManager]: Resetting LTL2Aut preferences to default values [2018-11-28 11:25:36,969 INFO L174 SettingsManager]: Resetting PEA to Boogie preferences to default values [2018-11-28 11:25:36,969 INFO L174 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2018-11-28 11:25:36,970 INFO L174 SettingsManager]: Resetting ChcToBoogie preferences to default values [2018-11-28 11:25:36,971 INFO L174 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2018-11-28 11:25:36,971 INFO L174 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2018-11-28 11:25:36,973 INFO L174 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2018-11-28 11:25:36,974 INFO L174 SettingsManager]: Resetting CodeCheck preferences to default values [2018-11-28 11:25:36,975 INFO L174 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2018-11-28 11:25:36,976 INFO L174 SettingsManager]: Resetting RCFGBuilder preferences to default values [2018-11-28 11:25:36,976 INFO L174 SettingsManager]: Resetting TraceAbstraction preferences to default values [2018-11-28 11:25:36,977 INFO L177 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2018-11-28 11:25:36,978 INFO L177 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2018-11-28 11:25:36,978 INFO L174 SettingsManager]: Resetting TreeAutomizer preferences to default values [2018-11-28 11:25:36,978 INFO L174 SettingsManager]: Resetting IcfgTransformer preferences to default values [2018-11-28 11:25:36,979 INFO L174 SettingsManager]: Resetting Boogie Printer preferences to default values [2018-11-28 11:25:36,979 INFO L174 SettingsManager]: Resetting ReqPrinter preferences to default values [2018-11-28 11:25:36,980 INFO L174 SettingsManager]: Resetting Witness Printer preferences to default values [2018-11-28 11:25:36,981 INFO L177 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2018-11-28 11:25:36,981 INFO L174 SettingsManager]: Resetting CDTParser preferences to default values [2018-11-28 11:25:36,981 INFO L177 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2018-11-28 11:25:36,981 INFO L177 SettingsManager]: ReqParser provides no preferences, ignoring... [2018-11-28 11:25:36,982 INFO L174 SettingsManager]: Resetting SmtParser preferences to default values [2018-11-28 11:25:36,982 INFO L174 SettingsManager]: Resetting Witness Parser preferences to default values [2018-11-28 11:25:36,983 INFO L181 SettingsManager]: Finished resetting all preferences to default values... [2018-11-28 11:25:36,983 INFO L98 SettingsManager]: Beginning loading settings from /tmp/vcloud-vcloud-master/worker/working_dir_2ca7a644-5b0a-4f3d-9179-f30a2c52dfce/bin-2019/uautomizer/config/svcomp-DerefFreeMemtrack-32bit-Automizer_Default.epf [2018-11-28 11:25:36,990 INFO L110 SettingsManager]: Loading preferences was successful [2018-11-28 11:25:36,990 INFO L112 SettingsManager]: Preferences different from defaults after loading the file: [2018-11-28 11:25:36,991 INFO L131 SettingsManager]: Preferences of Boogie Procedure Inliner differ from their defaults: [2018-11-28 11:25:36,991 INFO L133 SettingsManager]: * ... calls to implemented procedures=ONLY_FOR_CONCURRENT_PROGRAMS [2018-11-28 11:25:36,991 INFO L131 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2018-11-28 11:25:36,991 INFO L133 SettingsManager]: * Create parallel compositions if possible=false [2018-11-28 11:25:36,992 INFO L133 SettingsManager]: * Use SBE=true [2018-11-28 11:25:36,992 INFO L131 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2018-11-28 11:25:36,992 INFO L133 SettingsManager]: * sizeof long=4 [2018-11-28 11:25:36,992 INFO L133 SettingsManager]: * Check unreachability of error function in SV-COMP mode=false [2018-11-28 11:25:36,992 INFO L133 SettingsManager]: * Overapproximate operations on floating types=true [2018-11-28 11:25:36,992 INFO L133 SettingsManager]: * sizeof POINTER=4 [2018-11-28 11:25:36,993 INFO L133 SettingsManager]: * Check division by zero=IGNORE [2018-11-28 11:25:36,993 INFO L133 SettingsManager]: * Check for the main procedure if all allocated memory was freed=true [2018-11-28 11:25:36,993 INFO L133 SettingsManager]: * Bitprecise bitfields=true [2018-11-28 11:25:36,993 INFO L133 SettingsManager]: * SV-COMP memtrack compatibility mode=true [2018-11-28 11:25:36,993 INFO L133 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=IGNORE [2018-11-28 11:25:36,993 INFO L133 SettingsManager]: * sizeof long double=12 [2018-11-28 11:25:36,993 INFO L133 SettingsManager]: * Use constant arrays=true [2018-11-28 11:25:36,994 INFO L131 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2018-11-28 11:25:36,994 INFO L133 SettingsManager]: * Size of a code block=SequenceOfStatements [2018-11-28 11:25:36,994 INFO L133 SettingsManager]: * To the following directory=./dump/ [2018-11-28 11:25:36,994 INFO L133 SettingsManager]: * SMT solver=External_DefaultMode [2018-11-28 11:25:36,994 INFO L133 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2018-11-28 11:25:36,994 INFO L131 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2018-11-28 11:25:36,995 INFO L133 SettingsManager]: * Compute Interpolants along a Counterexample=FPandBP [2018-11-28 11:25:36,995 INFO L133 SettingsManager]: * Trace refinement strategy=CAMEL [2018-11-28 11:25:36,995 INFO L133 SettingsManager]: * SMT solver=External_ModelsAndUnsatCoreMode [2018-11-28 11:25:36,995 INFO L133 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud-vcloud-master/worker/working_dir_2ca7a644-5b0a-4f3d-9179-f30a2c52dfce/bin-2019/uautomizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(G valid-free) ) CHECK( init(main()), LTL(G valid-deref) ) CHECK( init(main()), LTL(G valid-memtrack) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> 4867b1d8e60a05de2199d52aa990071fe8bd647c [2018-11-28 11:25:37,019 INFO L81 nceAwareModelManager]: Repository-Root is: /tmp [2018-11-28 11:25:37,028 INFO L258 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2018-11-28 11:25:37,030 INFO L214 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2018-11-28 11:25:37,030 INFO L271 PluginConnector]: Initializing CDTParser... [2018-11-28 11:25:37,031 INFO L276 PluginConnector]: CDTParser initialized [2018-11-28 11:25:37,031 INFO L418 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud-vcloud-master/worker/working_dir_2ca7a644-5b0a-4f3d-9179-f30a2c52dfce/bin-2019/uautomizer/../../sv-benchmarks/c/ldv-memsafety/memleaks_test22_1_false-valid-memtrack_true-termination.i [2018-11-28 11:25:37,067 INFO L221 CDTParser]: Created temporary CDT project at /tmp/vcloud-vcloud-master/worker/working_dir_2ca7a644-5b0a-4f3d-9179-f30a2c52dfce/bin-2019/uautomizer/data/3d02f4c34/e47e20c9648446a68719bf566341d09f/FLAG1d5f2988e [2018-11-28 11:25:37,460 INFO L307 CDTParser]: Found 1 translation units. [2018-11-28 11:25:37,461 INFO L161 CDTParser]: Scanning /tmp/vcloud-vcloud-master/worker/working_dir_2ca7a644-5b0a-4f3d-9179-f30a2c52dfce/sv-benchmarks/c/ldv-memsafety/memleaks_test22_1_false-valid-memtrack_true-termination.i [2018-11-28 11:25:37,476 INFO L355 CDTParser]: About to delete temporary CDT project at /tmp/vcloud-vcloud-master/worker/working_dir_2ca7a644-5b0a-4f3d-9179-f30a2c52dfce/bin-2019/uautomizer/data/3d02f4c34/e47e20c9648446a68719bf566341d09f/FLAG1d5f2988e [2018-11-28 11:25:37,831 INFO L363 CDTParser]: Successfully deleted /tmp/vcloud-vcloud-master/worker/working_dir_2ca7a644-5b0a-4f3d-9179-f30a2c52dfce/bin-2019/uautomizer/data/3d02f4c34/e47e20c9648446a68719bf566341d09f [2018-11-28 11:25:37,834 INFO L296 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2018-11-28 11:25:37,835 INFO L131 ToolchainWalker]: Walking toolchain with 5 elements. [2018-11-28 11:25:37,836 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2018-11-28 11:25:37,836 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2018-11-28 11:25:37,838 INFO L276 PluginConnector]: CACSL2BoogieTranslator initialized [2018-11-28 11:25:37,839 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 28.11 11:25:37" (1/1) ... [2018-11-28 11:25:37,840 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@4aaba035 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 11:25:37, skipping insertion in model container [2018-11-28 11:25:37,840 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 28.11 11:25:37" (1/1) ... [2018-11-28 11:25:37,845 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2018-11-28 11:25:37,874 INFO L176 MainTranslator]: Built tables and reachable declarations [2018-11-28 11:25:38,145 INFO L203 PostProcessor]: Analyzing one entry point: main [2018-11-28 11:25:38,160 INFO L191 MainTranslator]: Completed pre-run [2018-11-28 11:25:38,206 INFO L203 PostProcessor]: Analyzing one entry point: main [2018-11-28 11:25:38,242 INFO L195 MainTranslator]: Completed translation [2018-11-28 11:25:38,242 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 11:25:38 WrapperNode [2018-11-28 11:25:38,242 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2018-11-28 11:25:38,243 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2018-11-28 11:25:38,243 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2018-11-28 11:25:38,243 INFO L276 PluginConnector]: Boogie Preprocessor initialized [2018-11-28 11:25:38,254 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 11:25:38" (1/1) ... [2018-11-28 11:25:38,254 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 11:25:38" (1/1) ... [2018-11-28 11:25:38,270 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 11:25:38" (1/1) ... [2018-11-28 11:25:38,270 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 11:25:38" (1/1) ... [2018-11-28 11:25:38,293 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 11:25:38" (1/1) ... [2018-11-28 11:25:38,298 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 11:25:38" (1/1) ... [2018-11-28 11:25:38,302 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 11:25:38" (1/1) ... [2018-11-28 11:25:38,308 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2018-11-28 11:25:38,309 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2018-11-28 11:25:38,309 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2018-11-28 11:25:38,309 INFO L276 PluginConnector]: RCFGBuilder initialized [2018-11-28 11:25:38,310 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 11:25:38" (1/1) ... No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_2ca7a644-5b0a-4f3d-9179-f30a2c52dfce/bin-2019/uautomizer/z3 Starting monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2018-11-28 11:25:38,344 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.init [2018-11-28 11:25:38,344 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2018-11-28 11:25:38,344 INFO L138 BoogieDeclarations]: Found implementation of procedure ##fun~$Pointer$~TO~VOID [2018-11-28 11:25:38,344 INFO L138 BoogieDeclarations]: Found implementation of procedure __bswap_32 [2018-11-28 11:25:38,344 INFO L138 BoogieDeclarations]: Found implementation of procedure __bswap_64 [2018-11-28 11:25:38,344 INFO L138 BoogieDeclarations]: Found implementation of procedure ldv_nonpositive [2018-11-28 11:25:38,344 INFO L138 BoogieDeclarations]: Found implementation of procedure ldv_positive [2018-11-28 11:25:38,345 INFO L138 BoogieDeclarations]: Found implementation of procedure ldv_malloc [2018-11-28 11:25:38,345 INFO L138 BoogieDeclarations]: Found implementation of procedure ldv_zalloc [2018-11-28 11:25:38,345 INFO L138 BoogieDeclarations]: Found implementation of procedure LDV_INIT_LIST_HEAD [2018-11-28 11:25:38,345 INFO L138 BoogieDeclarations]: Found implementation of procedure __ldv_list_add [2018-11-28 11:25:38,345 INFO L138 BoogieDeclarations]: Found implementation of procedure __ldv_list_del [2018-11-28 11:25:38,345 INFO L138 BoogieDeclarations]: Found implementation of procedure ldv_list_add [2018-11-28 11:25:38,345 INFO L138 BoogieDeclarations]: Found implementation of procedure ldv_list_add_tail [2018-11-28 11:25:38,345 INFO L138 BoogieDeclarations]: Found implementation of procedure ldv_list_del [2018-11-28 11:25:38,346 INFO L138 BoogieDeclarations]: Found implementation of procedure ldv_msg_alloc [2018-11-28 11:25:38,346 INFO L138 BoogieDeclarations]: Found implementation of procedure ldv_msg_fill [2018-11-28 11:25:38,346 INFO L138 BoogieDeclarations]: Found implementation of procedure ldv_msg_free [2018-11-28 11:25:38,346 INFO L138 BoogieDeclarations]: Found implementation of procedure ldv_submit_msg [2018-11-28 11:25:38,346 INFO L138 BoogieDeclarations]: Found implementation of procedure ldv_destroy_msgs [2018-11-28 11:25:38,346 INFO L138 BoogieDeclarations]: Found implementation of procedure ldv_dev_get_drvdata [2018-11-28 11:25:38,346 INFO L138 BoogieDeclarations]: Found implementation of procedure ldv_dev_set_drvdata [2018-11-28 11:25:38,346 INFO L138 BoogieDeclarations]: Found implementation of procedure ldv_atomic_add_return [2018-11-28 11:25:38,346 INFO L138 BoogieDeclarations]: Found implementation of procedure ldv_atomic_sub_return [2018-11-28 11:25:38,346 INFO L138 BoogieDeclarations]: Found implementation of procedure ldv_kref_sub [2018-11-28 11:25:38,347 INFO L138 BoogieDeclarations]: Found implementation of procedure ldv_kref_init [2018-11-28 11:25:38,347 INFO L138 BoogieDeclarations]: Found implementation of procedure ldv_kref_get [2018-11-28 11:25:38,347 INFO L138 BoogieDeclarations]: Found implementation of procedure ldv_kref_put [2018-11-28 11:25:38,347 INFO L138 BoogieDeclarations]: Found implementation of procedure ldv_kobject_del [2018-11-28 11:25:38,347 INFO L138 BoogieDeclarations]: Found implementation of procedure ldv_kobject_cleanup [2018-11-28 11:25:38,347 INFO L138 BoogieDeclarations]: Found implementation of procedure ldv_kobject_release [2018-11-28 11:25:38,347 INFO L138 BoogieDeclarations]: Found implementation of procedure ldv_kobject_put [2018-11-28 11:25:38,347 INFO L138 BoogieDeclarations]: Found implementation of procedure ldv_kobject_get [2018-11-28 11:25:38,347 INFO L138 BoogieDeclarations]: Found implementation of procedure ldv_kobject_init_internal [2018-11-28 11:25:38,347 INFO L138 BoogieDeclarations]: Found implementation of procedure ldv_kobject_init [2018-11-28 11:25:38,348 INFO L138 BoogieDeclarations]: Found implementation of procedure ldv_kobject_create [2018-11-28 11:25:38,348 INFO L138 BoogieDeclarations]: Found implementation of procedure f [2018-11-28 11:25:38,348 INFO L138 BoogieDeclarations]: Found implementation of procedure g [2018-11-28 11:25:38,348 INFO L138 BoogieDeclarations]: Found implementation of procedure entry_point [2018-11-28 11:25:38,348 INFO L138 BoogieDeclarations]: Found implementation of procedure main [2018-11-28 11:25:38,348 INFO L138 BoogieDeclarations]: Found implementation of procedure #Ultimate.C_memset [2018-11-28 11:25:38,348 INFO L138 BoogieDeclarations]: Found implementation of procedure #Ultimate.meminit [2018-11-28 11:25:38,348 INFO L138 BoogieDeclarations]: Found implementation of procedure #Ultimate.C_memcpy [2018-11-28 11:25:38,348 INFO L130 BoogieDeclarations]: Found specification of procedure __bswap_32 [2018-11-28 11:25:38,348 INFO L130 BoogieDeclarations]: Found specification of procedure __bswap_64 [2018-11-28 11:25:38,349 INFO L130 BoogieDeclarations]: Found specification of procedure __ctype_get_mb_cur_max [2018-11-28 11:25:38,349 INFO L130 BoogieDeclarations]: Found specification of procedure atof [2018-11-28 11:25:38,349 INFO L130 BoogieDeclarations]: Found specification of procedure atoi [2018-11-28 11:25:38,349 INFO L130 BoogieDeclarations]: Found specification of procedure atol [2018-11-28 11:25:38,349 INFO L130 BoogieDeclarations]: Found specification of procedure atoll [2018-11-28 11:25:38,349 INFO L130 BoogieDeclarations]: Found specification of procedure strtod [2018-11-28 11:25:38,349 INFO L130 BoogieDeclarations]: Found specification of procedure strtof [2018-11-28 11:25:38,349 INFO L130 BoogieDeclarations]: Found specification of procedure strtold [2018-11-28 11:25:38,349 INFO L130 BoogieDeclarations]: Found specification of procedure strtol [2018-11-28 11:25:38,349 INFO L130 BoogieDeclarations]: Found specification of procedure strtoul [2018-11-28 11:25:38,349 INFO L130 BoogieDeclarations]: Found specification of procedure strtoq [2018-11-28 11:25:38,350 INFO L130 BoogieDeclarations]: Found specification of procedure strtouq [2018-11-28 11:25:38,350 INFO L130 BoogieDeclarations]: Found specification of procedure strtoll [2018-11-28 11:25:38,350 INFO L130 BoogieDeclarations]: Found specification of procedure strtoull [2018-11-28 11:25:38,350 INFO L130 BoogieDeclarations]: Found specification of procedure l64a [2018-11-28 11:25:38,350 INFO L130 BoogieDeclarations]: Found specification of procedure a64l [2018-11-28 11:25:38,350 INFO L130 BoogieDeclarations]: Found specification of procedure select [2018-11-28 11:25:38,350 INFO L130 BoogieDeclarations]: Found specification of procedure pselect [2018-11-28 11:25:38,350 INFO L130 BoogieDeclarations]: Found specification of procedure gnu_dev_major [2018-11-28 11:25:38,350 INFO L130 BoogieDeclarations]: Found specification of procedure gnu_dev_minor [2018-11-28 11:25:38,350 INFO L130 BoogieDeclarations]: Found specification of procedure gnu_dev_makedev [2018-11-28 11:25:38,350 INFO L130 BoogieDeclarations]: Found specification of procedure random [2018-11-28 11:25:38,350 INFO L130 BoogieDeclarations]: Found specification of procedure srandom [2018-11-28 11:25:38,350 INFO L130 BoogieDeclarations]: Found specification of procedure initstate [2018-11-28 11:25:38,350 INFO L130 BoogieDeclarations]: Found specification of procedure setstate [2018-11-28 11:25:38,350 INFO L130 BoogieDeclarations]: Found specification of procedure random_r [2018-11-28 11:25:38,350 INFO L130 BoogieDeclarations]: Found specification of procedure srandom_r [2018-11-28 11:25:38,350 INFO L130 BoogieDeclarations]: Found specification of procedure initstate_r [2018-11-28 11:25:38,351 INFO L130 BoogieDeclarations]: Found specification of procedure setstate_r [2018-11-28 11:25:38,351 INFO L130 BoogieDeclarations]: Found specification of procedure rand [2018-11-28 11:25:38,351 INFO L130 BoogieDeclarations]: Found specification of procedure srand [2018-11-28 11:25:38,351 INFO L130 BoogieDeclarations]: Found specification of procedure rand_r [2018-11-28 11:25:38,351 INFO L130 BoogieDeclarations]: Found specification of procedure drand48 [2018-11-28 11:25:38,351 INFO L130 BoogieDeclarations]: Found specification of procedure erand48 [2018-11-28 11:25:38,351 INFO L130 BoogieDeclarations]: Found specification of procedure lrand48 [2018-11-28 11:25:38,351 INFO L130 BoogieDeclarations]: Found specification of procedure nrand48 [2018-11-28 11:25:38,351 INFO L130 BoogieDeclarations]: Found specification of procedure mrand48 [2018-11-28 11:25:38,351 INFO L130 BoogieDeclarations]: Found specification of procedure jrand48 [2018-11-28 11:25:38,351 INFO L130 BoogieDeclarations]: Found specification of procedure srand48 [2018-11-28 11:25:38,351 INFO L130 BoogieDeclarations]: Found specification of procedure seed48 [2018-11-28 11:25:38,351 INFO L130 BoogieDeclarations]: Found specification of procedure lcong48 [2018-11-28 11:25:38,351 INFO L130 BoogieDeclarations]: Found specification of procedure drand48_r [2018-11-28 11:25:38,352 INFO L130 BoogieDeclarations]: Found specification of procedure erand48_r [2018-11-28 11:25:38,352 INFO L130 BoogieDeclarations]: Found specification of procedure lrand48_r [2018-11-28 11:25:38,352 INFO L130 BoogieDeclarations]: Found specification of procedure nrand48_r [2018-11-28 11:25:38,352 INFO L130 BoogieDeclarations]: Found specification of procedure mrand48_r [2018-11-28 11:25:38,352 INFO L130 BoogieDeclarations]: Found specification of procedure jrand48_r [2018-11-28 11:25:38,352 INFO L130 BoogieDeclarations]: Found specification of procedure srand48_r [2018-11-28 11:25:38,352 INFO L130 BoogieDeclarations]: Found specification of procedure seed48_r [2018-11-28 11:25:38,352 INFO L130 BoogieDeclarations]: Found specification of procedure lcong48_r [2018-11-28 11:25:38,352 INFO L130 BoogieDeclarations]: Found specification of procedure malloc [2018-11-28 11:25:38,352 INFO L130 BoogieDeclarations]: Found specification of procedure calloc [2018-11-28 11:25:38,352 INFO L130 BoogieDeclarations]: Found specification of procedure realloc [2018-11-28 11:25:38,353 INFO L130 BoogieDeclarations]: Found specification of procedure free [2018-11-28 11:25:38,353 INFO L130 BoogieDeclarations]: Found specification of procedure cfree [2018-11-28 11:25:38,353 INFO L130 BoogieDeclarations]: Found specification of procedure alloca [2018-11-28 11:25:38,353 INFO L130 BoogieDeclarations]: Found specification of procedure valloc [2018-11-28 11:25:38,353 INFO L130 BoogieDeclarations]: Found specification of procedure posix_memalign [2018-11-28 11:25:38,353 INFO L130 BoogieDeclarations]: Found specification of procedure abort [2018-11-28 11:25:38,353 INFO L130 BoogieDeclarations]: Found specification of procedure atexit [2018-11-28 11:25:38,353 INFO L130 BoogieDeclarations]: Found specification of procedure on_exit [2018-11-28 11:25:38,353 INFO L130 BoogieDeclarations]: Found specification of procedure exit [2018-11-28 11:25:38,353 INFO L130 BoogieDeclarations]: Found specification of procedure _Exit [2018-11-28 11:25:38,354 INFO L130 BoogieDeclarations]: Found specification of procedure getenv [2018-11-28 11:25:38,354 INFO L130 BoogieDeclarations]: Found specification of procedure putenv [2018-11-28 11:25:38,354 INFO L130 BoogieDeclarations]: Found specification of procedure setenv [2018-11-28 11:25:38,354 INFO L130 BoogieDeclarations]: Found specification of procedure unsetenv [2018-11-28 11:25:38,354 INFO L130 BoogieDeclarations]: Found specification of procedure clearenv [2018-11-28 11:25:38,354 INFO L130 BoogieDeclarations]: Found specification of procedure mktemp [2018-11-28 11:25:38,354 INFO L130 BoogieDeclarations]: Found specification of procedure mkstemp [2018-11-28 11:25:38,354 INFO L130 BoogieDeclarations]: Found specification of procedure mkstemps [2018-11-28 11:25:38,354 INFO L130 BoogieDeclarations]: Found specification of procedure mkdtemp [2018-11-28 11:25:38,354 INFO L130 BoogieDeclarations]: Found specification of procedure system [2018-11-28 11:25:38,354 INFO L130 BoogieDeclarations]: Found specification of procedure realpath [2018-11-28 11:25:38,355 INFO L130 BoogieDeclarations]: Found specification of procedure bsearch [2018-11-28 11:25:38,355 INFO L130 BoogieDeclarations]: Found specification of procedure qsort [2018-11-28 11:25:38,355 INFO L130 BoogieDeclarations]: Found specification of procedure abs [2018-11-28 11:25:38,355 INFO L130 BoogieDeclarations]: Found specification of procedure labs [2018-11-28 11:25:38,355 INFO L130 BoogieDeclarations]: Found specification of procedure llabs [2018-11-28 11:25:38,355 INFO L130 BoogieDeclarations]: Found specification of procedure div [2018-11-28 11:25:38,355 INFO L130 BoogieDeclarations]: Found specification of procedure ldiv [2018-11-28 11:25:38,355 INFO L130 BoogieDeclarations]: Found specification of procedure lldiv [2018-11-28 11:25:38,355 INFO L130 BoogieDeclarations]: Found specification of procedure ecvt [2018-11-28 11:25:38,355 INFO L130 BoogieDeclarations]: Found specification of procedure fcvt [2018-11-28 11:25:38,356 INFO L130 BoogieDeclarations]: Found specification of procedure gcvt [2018-11-28 11:25:38,356 INFO L130 BoogieDeclarations]: Found specification of procedure qecvt [2018-11-28 11:25:38,356 INFO L130 BoogieDeclarations]: Found specification of procedure qfcvt [2018-11-28 11:25:38,356 INFO L130 BoogieDeclarations]: Found specification of procedure qgcvt [2018-11-28 11:25:38,356 INFO L130 BoogieDeclarations]: Found specification of procedure ecvt_r [2018-11-28 11:25:38,356 INFO L130 BoogieDeclarations]: Found specification of procedure fcvt_r [2018-11-28 11:25:38,356 INFO L130 BoogieDeclarations]: Found specification of procedure qecvt_r [2018-11-28 11:25:38,356 INFO L130 BoogieDeclarations]: Found specification of procedure qfcvt_r [2018-11-28 11:25:38,356 INFO L130 BoogieDeclarations]: Found specification of procedure mblen [2018-11-28 11:25:38,356 INFO L130 BoogieDeclarations]: Found specification of procedure mbtowc [2018-11-28 11:25:38,357 INFO L130 BoogieDeclarations]: Found specification of procedure wctomb [2018-11-28 11:25:38,357 INFO L130 BoogieDeclarations]: Found specification of procedure mbstowcs [2018-11-28 11:25:38,357 INFO L130 BoogieDeclarations]: Found specification of procedure wcstombs [2018-11-28 11:25:38,357 INFO L130 BoogieDeclarations]: Found specification of procedure rpmatch [2018-11-28 11:25:38,357 INFO L130 BoogieDeclarations]: Found specification of procedure getsubopt [2018-11-28 11:25:38,357 INFO L130 BoogieDeclarations]: Found specification of procedure getloadavg [2018-11-28 11:25:38,357 INFO L130 BoogieDeclarations]: Found specification of procedure kfree [2018-11-28 11:25:38,357 INFO L130 BoogieDeclarations]: Found specification of procedure __VERIFIER_nondet_int [2018-11-28 11:25:38,357 INFO L130 BoogieDeclarations]: Found specification of procedure __VERIFIER_nondet_pointer [2018-11-28 11:25:38,357 INFO L130 BoogieDeclarations]: Found specification of procedure ldv_nonpositive [2018-11-28 11:25:38,358 INFO L130 BoogieDeclarations]: Found specification of procedure ldv_positive [2018-11-28 11:25:38,358 INFO L130 BoogieDeclarations]: Found specification of procedure memcpy [2018-11-28 11:25:38,358 INFO L130 BoogieDeclarations]: Found specification of procedure memset [2018-11-28 11:25:38,358 INFO L130 BoogieDeclarations]: Found specification of procedure ldv_malloc [2018-11-28 11:25:38,358 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.alloc [2018-11-28 11:25:38,358 INFO L130 BoogieDeclarations]: Found specification of procedure ldv_zalloc [2018-11-28 11:25:38,358 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.meminit [2018-11-28 11:25:38,358 INFO L130 BoogieDeclarations]: Found specification of procedure LDV_INIT_LIST_HEAD [2018-11-28 11:25:38,358 INFO L130 BoogieDeclarations]: Found specification of procedure write~$Pointer$ [2018-11-28 11:25:38,358 INFO L130 BoogieDeclarations]: Found specification of procedure __ldv_list_add [2018-11-28 11:25:38,358 INFO L130 BoogieDeclarations]: Found specification of procedure __ldv_list_del [2018-11-28 11:25:38,359 INFO L130 BoogieDeclarations]: Found specification of procedure ldv_list_add [2018-11-28 11:25:38,359 INFO L130 BoogieDeclarations]: Found specification of procedure read~$Pointer$ [2018-11-28 11:25:38,359 INFO L130 BoogieDeclarations]: Found specification of procedure ldv_list_add_tail [2018-11-28 11:25:38,359 INFO L130 BoogieDeclarations]: Found specification of procedure ldv_list_del [2018-11-28 11:25:38,359 INFO L130 BoogieDeclarations]: Found specification of procedure ldv_msg_alloc [2018-11-28 11:25:38,359 INFO L130 BoogieDeclarations]: Found specification of procedure ldv_msg_fill [2018-11-28 11:25:38,359 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.C_memcpy [2018-11-28 11:25:38,359 INFO L130 BoogieDeclarations]: Found specification of procedure ldv_msg_free [2018-11-28 11:25:38,359 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.dealloc [2018-11-28 11:25:38,359 INFO L130 BoogieDeclarations]: Found specification of procedure ldv_submit_msg [2018-11-28 11:25:38,359 INFO L130 BoogieDeclarations]: Found specification of procedure ldv_destroy_msgs [2018-11-28 11:25:38,360 INFO L130 BoogieDeclarations]: Found specification of procedure ldv_dev_get_drvdata [2018-11-28 11:25:38,360 INFO L130 BoogieDeclarations]: Found specification of procedure ldv_dev_set_drvdata [2018-11-28 11:25:38,360 INFO L130 BoogieDeclarations]: Found specification of procedure ldv_atomic_add_return [2018-11-28 11:25:38,360 INFO L130 BoogieDeclarations]: Found specification of procedure read~int [2018-11-28 11:25:38,360 INFO L130 BoogieDeclarations]: Found specification of procedure write~int [2018-11-28 11:25:38,360 INFO L130 BoogieDeclarations]: Found specification of procedure ldv_atomic_sub_return [2018-11-28 11:25:38,360 INFO L130 BoogieDeclarations]: Found specification of procedure ldv_kref_sub [2018-11-28 11:25:38,360 INFO L130 BoogieDeclarations]: Found specification of procedure ##fun~$Pointer$~TO~VOID [2018-11-28 11:25:38,360 INFO L130 BoogieDeclarations]: Found specification of procedure ldv_kref_init [2018-11-28 11:25:38,360 INFO L130 BoogieDeclarations]: Found specification of procedure ldv_kref_get [2018-11-28 11:25:38,361 INFO L130 BoogieDeclarations]: Found specification of procedure ldv_kref_put [2018-11-28 11:25:38,361 INFO L130 BoogieDeclarations]: Found specification of procedure ldv_kobject_del [2018-11-28 11:25:38,361 INFO L130 BoogieDeclarations]: Found specification of procedure ldv_kobject_cleanup [2018-11-28 11:25:38,361 INFO L130 BoogieDeclarations]: Found specification of procedure ldv_kobject_release [2018-11-28 11:25:38,361 INFO L130 BoogieDeclarations]: Found specification of procedure ldv_kobject_put [2018-11-28 11:25:38,361 INFO L130 BoogieDeclarations]: Found specification of procedure ldv_kobject_get [2018-11-28 11:25:38,361 INFO L130 BoogieDeclarations]: Found specification of procedure ldv_kobject_init_internal [2018-11-28 11:25:38,361 INFO L130 BoogieDeclarations]: Found specification of procedure ldv_kobject_init [2018-11-28 11:25:38,361 INFO L130 BoogieDeclarations]: Found specification of procedure ldv_kobject_create [2018-11-28 11:25:38,361 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.C_memset [2018-11-28 11:25:38,361 INFO L130 BoogieDeclarations]: Found specification of procedure f [2018-11-28 11:25:38,362 INFO L130 BoogieDeclarations]: Found specification of procedure g [2018-11-28 11:25:38,362 INFO L130 BoogieDeclarations]: Found specification of procedure entry_point [2018-11-28 11:25:38,362 INFO L130 BoogieDeclarations]: Found specification of procedure main [2018-11-28 11:25:38,362 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.init [2018-11-28 11:25:38,362 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~$Pointer$ [2018-11-28 11:25:38,362 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2018-11-28 11:25:38,362 INFO L130 BoogieDeclarations]: Found specification of procedure write~unchecked~$Pointer$ [2018-11-28 11:25:38,362 INFO L130 BoogieDeclarations]: Found specification of procedure read~unchecked~$Pointer$ [2018-11-28 11:25:38,362 INFO L130 BoogieDeclarations]: Found specification of procedure write~unchecked~int [2018-11-28 11:25:38,362 INFO L130 BoogieDeclarations]: Found specification of procedure read~unchecked~int [2018-11-28 11:25:38,662 WARN L615 $ProcedureCfgBuilder]: Label in the middle of a codeblock. [2018-11-28 11:25:38,828 WARN L615 $ProcedureCfgBuilder]: Label in the middle of a codeblock. [2018-11-28 11:25:38,991 INFO L275 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2018-11-28 11:25:38,991 INFO L280 CfgBuilder]: Removed 1 assue(true) statements. [2018-11-28 11:25:38,992 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 28.11 11:25:38 BoogieIcfgContainer [2018-11-28 11:25:38,992 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2018-11-28 11:25:38,992 INFO L113 PluginConnector]: ------------------------TraceAbstraction---------------------------- [2018-11-28 11:25:38,992 INFO L271 PluginConnector]: Initializing TraceAbstraction... [2018-11-28 11:25:38,994 INFO L276 PluginConnector]: TraceAbstraction initialized [2018-11-28 11:25:38,994 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "CDTParser AST 28.11 11:25:37" (1/3) ... [2018-11-28 11:25:38,995 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@154bdc2f and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 28.11 11:25:38, skipping insertion in model container [2018-11-28 11:25:38,995 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 11:25:38" (2/3) ... [2018-11-28 11:25:38,995 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@154bdc2f and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 28.11 11:25:38, skipping insertion in model container [2018-11-28 11:25:38,995 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 28.11 11:25:38" (3/3) ... [2018-11-28 11:25:38,996 INFO L112 eAbstractionObserver]: Analyzing ICFG memleaks_test22_1_false-valid-memtrack_true-termination.i [2018-11-28 11:25:39,003 INFO L156 ceAbstractionStarter]: Automizer settings: Hoare:false NWA Interpolation:FPandBP Determinization: PREDICATE_ABSTRACTION [2018-11-28 11:25:39,009 INFO L168 ceAbstractionStarter]: Appying trace abstraction to program that has 67 error locations. [2018-11-28 11:25:39,019 INFO L257 AbstractCegarLoop]: Starting to check reachability of 67 error locations. [2018-11-28 11:25:39,036 INFO L133 ementStrategyFactory]: Using default assertion order modulation [2018-11-28 11:25:39,036 INFO L382 AbstractCegarLoop]: Interprodecural is true [2018-11-28 11:25:39,037 INFO L383 AbstractCegarLoop]: Hoare is false [2018-11-28 11:25:39,037 INFO L384 AbstractCegarLoop]: Compute interpolants for FPandBP [2018-11-28 11:25:39,037 INFO L385 AbstractCegarLoop]: Backedges is STRAIGHT_LINE [2018-11-28 11:25:39,037 INFO L386 AbstractCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2018-11-28 11:25:39,037 INFO L387 AbstractCegarLoop]: Difference is false [2018-11-28 11:25:39,037 INFO L388 AbstractCegarLoop]: Minimize is MINIMIZE_SEVPA [2018-11-28 11:25:39,037 INFO L393 AbstractCegarLoop]: ======== Iteration 0==of CEGAR loop == AllErrorsAtOnce======== [2018-11-28 11:25:39,051 INFO L276 IsEmpty]: Start isEmpty. Operand 171 states. [2018-11-28 11:25:39,058 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 18 [2018-11-28 11:25:39,058 INFO L394 BasicCegarLoop]: Found error trace [2018-11-28 11:25:39,058 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-28 11:25:39,060 INFO L423 AbstractCegarLoop]: === Iteration 1 === [ldv_kref_initErr1REQUIRES_VIOLATION, ldv_kref_initErr0REQUIRES_VIOLATION, ldv_list_addErr0REQUIRES_VIOLATION, ldv_list_addErr1REQUIRES_VIOLATION, ldv_kobject_createErr0REQUIRES_VIOLATION, ldv_kobject_createErr1REQUIRES_VIOLATION, ldv_destroy_msgsErr3REQUIRES_VIOLATION, ldv_destroy_msgsErr4REQUIRES_VIOLATION, ldv_destroy_msgsErr0REQUIRES_VIOLATION, ldv_destroy_msgsErr5REQUIRES_VIOLATION, ldv_destroy_msgsErr2REQUIRES_VIOLATION, ldv_destroy_msgsErr1REQUIRES_VIOLATION, ldv_msg_fillErr0REQUIRES_VIOLATION, ldv_msg_fillErr5REQUIRES_VIOLATION, ldv_msg_fillErr1REQUIRES_VIOLATION, ldv_msg_fillErr2REQUIRES_VIOLATION, ldv_msg_fillErr3REQUIRES_VIOLATION, ldv_msg_fillErr4REQUIRES_VIOLATION, ldv_atomic_add_returnErr0REQUIRES_VIOLATION, ldv_atomic_add_returnErr2REQUIRES_VIOLATION, ldv_atomic_add_returnErr1REQUIRES_VIOLATION, ldv_atomic_add_returnErr3REQUIRES_VIOLATION, __ldv_list_delErr3REQUIRES_VIOLATION, __ldv_list_delErr1REQUIRES_VIOLATION, __ldv_list_delErr2REQUIRES_VIOLATION, __ldv_list_delErr0REQUIRES_VIOLATION, ldv_kobject_cleanupErr3ASSERT_VIOLATIONMEMORY_FREE, ldv_kobject_cleanupErr2ASSERT_VIOLATIONMEMORY_FREE, ldv_kobject_cleanupErr4ASSERT_VIOLATIONMEMORY_FREE, ldv_kobject_cleanupErr0REQUIRES_VIOLATION, ldv_kobject_cleanupErr5ASSERT_VIOLATIONMEMORY_FREE, ldv_kobject_cleanupErr1REQUIRES_VIOLATION, ldv_msg_freeErr3ASSERT_VIOLATIONMEMORY_FREE, ldv_msg_freeErr5ASSERT_VIOLATIONMEMORY_FREE, ldv_msg_freeErr2ASSERT_VIOLATIONMEMORY_FREE, ldv_msg_freeErr4ASSERT_VIOLATIONMEMORY_FREE, ldv_msg_freeErr0REQUIRES_VIOLATION, ldv_msg_freeErr1REQUIRES_VIOLATION, mainErr0ENSURES_VIOLATIONMEMORY_LEAK, LDV_INIT_LIST_HEADErr1REQUIRES_VIOLATION, LDV_INIT_LIST_HEADErr2REQUIRES_VIOLATION, LDV_INIT_LIST_HEADErr0REQUIRES_VIOLATION, LDV_INIT_LIST_HEADErr3REQUIRES_VIOLATION, ldv_list_delErr0REQUIRES_VIOLATION, ldv_list_delErr2REQUIRES_VIOLATION, ldv_list_delErr1REQUIRES_VIOLATION, ldv_list_delErr3REQUIRES_VIOLATION, __ldv_list_addErr4REQUIRES_VIOLATION, __ldv_list_addErr3REQUIRES_VIOLATION, __ldv_list_addErr1REQUIRES_VIOLATION, __ldv_list_addErr2REQUIRES_VIOLATION, __ldv_list_addErr7REQUIRES_VIOLATION, __ldv_list_addErr0REQUIRES_VIOLATION, __ldv_list_addErr5REQUIRES_VIOLATION, __ldv_list_addErr6REQUIRES_VIOLATION, ldv_dev_set_drvdataErr1REQUIRES_VIOLATION, ldv_dev_set_drvdataErr0REQUIRES_VIOLATION, ldv_atomic_sub_returnErr0REQUIRES_VIOLATION, ldv_atomic_sub_returnErr2REQUIRES_VIOLATION, ldv_atomic_sub_returnErr1REQUIRES_VIOLATION, ldv_atomic_sub_returnErr3REQUIRES_VIOLATION, ldv_list_add_tailErr1REQUIRES_VIOLATION, ldv_list_add_tailErr0REQUIRES_VIOLATION, ldv_dev_get_drvdataErr0REQUIRES_VIOLATION, ldv_dev_get_drvdataErr1REQUIRES_VIOLATION, ldv_msg_allocErr1REQUIRES_VIOLATION, ldv_msg_allocErr0REQUIRES_VIOLATION]=== [2018-11-28 11:25:39,064 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-28 11:25:39,064 INFO L82 PathProgramCache]: Analyzing trace with hash 280699124, now seen corresponding path program 1 times [2018-11-28 11:25:39,065 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-28 11:25:39,066 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-28 11:25:39,105 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 11:25:39,105 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-28 11:25:39,105 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 11:25:39,149 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-28 11:25:39,250 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-28 11:25:39,252 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-28 11:25:39,253 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2018-11-28 11:25:39,255 INFO L459 AbstractCegarLoop]: Interpolant automaton has 5 states [2018-11-28 11:25:39,264 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-11-28 11:25:39,265 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-11-28 11:25:39,266 INFO L87 Difference]: Start difference. First operand 171 states. Second operand 5 states. [2018-11-28 11:25:39,545 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-28 11:25:39,546 INFO L93 Difference]: Finished difference Result 153 states and 164 transitions. [2018-11-28 11:25:39,546 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2018-11-28 11:25:39,547 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 17 [2018-11-28 11:25:39,547 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-28 11:25:39,557 INFO L225 Difference]: With dead ends: 153 [2018-11-28 11:25:39,558 INFO L226 Difference]: Without dead ends: 150 [2018-11-28 11:25:39,559 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 4 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-11-28 11:25:39,570 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 150 states. [2018-11-28 11:25:39,591 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 150 to 144. [2018-11-28 11:25:39,592 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 144 states. [2018-11-28 11:25:39,595 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 144 states to 144 states and 155 transitions. [2018-11-28 11:25:39,596 INFO L78 Accepts]: Start accepts. Automaton has 144 states and 155 transitions. Word has length 17 [2018-11-28 11:25:39,596 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-28 11:25:39,596 INFO L480 AbstractCegarLoop]: Abstraction has 144 states and 155 transitions. [2018-11-28 11:25:39,596 INFO L481 AbstractCegarLoop]: Interpolant automaton has 5 states. [2018-11-28 11:25:39,597 INFO L276 IsEmpty]: Start isEmpty. Operand 144 states and 155 transitions. [2018-11-28 11:25:39,597 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 18 [2018-11-28 11:25:39,597 INFO L394 BasicCegarLoop]: Found error trace [2018-11-28 11:25:39,597 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-28 11:25:39,600 INFO L423 AbstractCegarLoop]: === Iteration 2 === [ldv_kref_initErr1REQUIRES_VIOLATION, ldv_kref_initErr0REQUIRES_VIOLATION, ldv_list_addErr0REQUIRES_VIOLATION, ldv_list_addErr1REQUIRES_VIOLATION, ldv_kobject_createErr0REQUIRES_VIOLATION, ldv_kobject_createErr1REQUIRES_VIOLATION, ldv_destroy_msgsErr3REQUIRES_VIOLATION, ldv_destroy_msgsErr4REQUIRES_VIOLATION, ldv_destroy_msgsErr0REQUIRES_VIOLATION, ldv_destroy_msgsErr5REQUIRES_VIOLATION, ldv_destroy_msgsErr2REQUIRES_VIOLATION, ldv_destroy_msgsErr1REQUIRES_VIOLATION, ldv_msg_fillErr0REQUIRES_VIOLATION, ldv_msg_fillErr5REQUIRES_VIOLATION, ldv_msg_fillErr1REQUIRES_VIOLATION, ldv_msg_fillErr2REQUIRES_VIOLATION, ldv_msg_fillErr3REQUIRES_VIOLATION, ldv_msg_fillErr4REQUIRES_VIOLATION, ldv_atomic_add_returnErr0REQUIRES_VIOLATION, ldv_atomic_add_returnErr2REQUIRES_VIOLATION, ldv_atomic_add_returnErr1REQUIRES_VIOLATION, ldv_atomic_add_returnErr3REQUIRES_VIOLATION, __ldv_list_delErr3REQUIRES_VIOLATION, __ldv_list_delErr1REQUIRES_VIOLATION, __ldv_list_delErr2REQUIRES_VIOLATION, __ldv_list_delErr0REQUIRES_VIOLATION, ldv_kobject_cleanupErr3ASSERT_VIOLATIONMEMORY_FREE, ldv_kobject_cleanupErr2ASSERT_VIOLATIONMEMORY_FREE, ldv_kobject_cleanupErr4ASSERT_VIOLATIONMEMORY_FREE, ldv_kobject_cleanupErr0REQUIRES_VIOLATION, ldv_kobject_cleanupErr5ASSERT_VIOLATIONMEMORY_FREE, ldv_kobject_cleanupErr1REQUIRES_VIOLATION, ldv_msg_freeErr3ASSERT_VIOLATIONMEMORY_FREE, ldv_msg_freeErr5ASSERT_VIOLATIONMEMORY_FREE, ldv_msg_freeErr2ASSERT_VIOLATIONMEMORY_FREE, ldv_msg_freeErr4ASSERT_VIOLATIONMEMORY_FREE, ldv_msg_freeErr0REQUIRES_VIOLATION, ldv_msg_freeErr1REQUIRES_VIOLATION, mainErr0ENSURES_VIOLATIONMEMORY_LEAK, LDV_INIT_LIST_HEADErr1REQUIRES_VIOLATION, LDV_INIT_LIST_HEADErr2REQUIRES_VIOLATION, LDV_INIT_LIST_HEADErr0REQUIRES_VIOLATION, LDV_INIT_LIST_HEADErr3REQUIRES_VIOLATION, ldv_list_delErr0REQUIRES_VIOLATION, ldv_list_delErr2REQUIRES_VIOLATION, ldv_list_delErr1REQUIRES_VIOLATION, ldv_list_delErr3REQUIRES_VIOLATION, __ldv_list_addErr4REQUIRES_VIOLATION, __ldv_list_addErr3REQUIRES_VIOLATION, __ldv_list_addErr1REQUIRES_VIOLATION, __ldv_list_addErr2REQUIRES_VIOLATION, __ldv_list_addErr7REQUIRES_VIOLATION, __ldv_list_addErr0REQUIRES_VIOLATION, __ldv_list_addErr5REQUIRES_VIOLATION, __ldv_list_addErr6REQUIRES_VIOLATION, ldv_dev_set_drvdataErr1REQUIRES_VIOLATION, ldv_dev_set_drvdataErr0REQUIRES_VIOLATION, ldv_atomic_sub_returnErr0REQUIRES_VIOLATION, ldv_atomic_sub_returnErr2REQUIRES_VIOLATION, ldv_atomic_sub_returnErr1REQUIRES_VIOLATION, ldv_atomic_sub_returnErr3REQUIRES_VIOLATION, ldv_list_add_tailErr1REQUIRES_VIOLATION, ldv_list_add_tailErr0REQUIRES_VIOLATION, ldv_dev_get_drvdataErr0REQUIRES_VIOLATION, ldv_dev_get_drvdataErr1REQUIRES_VIOLATION, ldv_msg_allocErr1REQUIRES_VIOLATION, ldv_msg_allocErr0REQUIRES_VIOLATION]=== [2018-11-28 11:25:39,600 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-28 11:25:39,600 INFO L82 PathProgramCache]: Analyzing trace with hash 280699125, now seen corresponding path program 1 times [2018-11-28 11:25:39,600 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-28 11:25:39,600 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-28 11:25:39,602 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 11:25:39,602 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-28 11:25:39,603 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 11:25:39,620 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-28 11:25:39,695 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-28 11:25:39,696 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-28 11:25:39,696 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-11-28 11:25:39,697 INFO L459 AbstractCegarLoop]: Interpolant automaton has 6 states [2018-11-28 11:25:39,697 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2018-11-28 11:25:39,698 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=21, Unknown=0, NotChecked=0, Total=30 [2018-11-28 11:25:39,698 INFO L87 Difference]: Start difference. First operand 144 states and 155 transitions. Second operand 6 states. [2018-11-28 11:25:39,818 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-28 11:25:39,818 INFO L93 Difference]: Finished difference Result 149 states and 160 transitions. [2018-11-28 11:25:39,819 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2018-11-28 11:25:39,819 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 17 [2018-11-28 11:25:39,820 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-28 11:25:39,821 INFO L225 Difference]: With dead ends: 149 [2018-11-28 11:25:39,821 INFO L226 Difference]: Without dead ends: 149 [2018-11-28 11:25:39,822 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 7 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=13, Invalid=29, Unknown=0, NotChecked=0, Total=42 [2018-11-28 11:25:39,822 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 149 states. [2018-11-28 11:25:39,829 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 149 to 144. [2018-11-28 11:25:39,830 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 144 states. [2018-11-28 11:25:39,831 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 144 states to 144 states and 154 transitions. [2018-11-28 11:25:39,831 INFO L78 Accepts]: Start accepts. Automaton has 144 states and 154 transitions. Word has length 17 [2018-11-28 11:25:39,831 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-28 11:25:39,832 INFO L480 AbstractCegarLoop]: Abstraction has 144 states and 154 transitions. [2018-11-28 11:25:39,832 INFO L481 AbstractCegarLoop]: Interpolant automaton has 6 states. [2018-11-28 11:25:39,832 INFO L276 IsEmpty]: Start isEmpty. Operand 144 states and 154 transitions. [2018-11-28 11:25:39,832 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 18 [2018-11-28 11:25:39,832 INFO L394 BasicCegarLoop]: Found error trace [2018-11-28 11:25:39,833 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-28 11:25:39,833 INFO L423 AbstractCegarLoop]: === Iteration 3 === [ldv_kref_initErr1REQUIRES_VIOLATION, ldv_kref_initErr0REQUIRES_VIOLATION, ldv_list_addErr0REQUIRES_VIOLATION, ldv_list_addErr1REQUIRES_VIOLATION, ldv_kobject_createErr0REQUIRES_VIOLATION, ldv_kobject_createErr1REQUIRES_VIOLATION, ldv_destroy_msgsErr3REQUIRES_VIOLATION, ldv_destroy_msgsErr4REQUIRES_VIOLATION, ldv_destroy_msgsErr0REQUIRES_VIOLATION, ldv_destroy_msgsErr5REQUIRES_VIOLATION, ldv_destroy_msgsErr2REQUIRES_VIOLATION, ldv_destroy_msgsErr1REQUIRES_VIOLATION, ldv_msg_fillErr0REQUIRES_VIOLATION, ldv_msg_fillErr5REQUIRES_VIOLATION, ldv_msg_fillErr1REQUIRES_VIOLATION, ldv_msg_fillErr2REQUIRES_VIOLATION, ldv_msg_fillErr3REQUIRES_VIOLATION, ldv_msg_fillErr4REQUIRES_VIOLATION, ldv_atomic_add_returnErr0REQUIRES_VIOLATION, ldv_atomic_add_returnErr2REQUIRES_VIOLATION, ldv_atomic_add_returnErr1REQUIRES_VIOLATION, ldv_atomic_add_returnErr3REQUIRES_VIOLATION, __ldv_list_delErr3REQUIRES_VIOLATION, __ldv_list_delErr1REQUIRES_VIOLATION, __ldv_list_delErr2REQUIRES_VIOLATION, __ldv_list_delErr0REQUIRES_VIOLATION, ldv_kobject_cleanupErr3ASSERT_VIOLATIONMEMORY_FREE, ldv_kobject_cleanupErr2ASSERT_VIOLATIONMEMORY_FREE, ldv_kobject_cleanupErr4ASSERT_VIOLATIONMEMORY_FREE, ldv_kobject_cleanupErr0REQUIRES_VIOLATION, ldv_kobject_cleanupErr5ASSERT_VIOLATIONMEMORY_FREE, ldv_kobject_cleanupErr1REQUIRES_VIOLATION, ldv_msg_freeErr3ASSERT_VIOLATIONMEMORY_FREE, ldv_msg_freeErr5ASSERT_VIOLATIONMEMORY_FREE, ldv_msg_freeErr2ASSERT_VIOLATIONMEMORY_FREE, ldv_msg_freeErr4ASSERT_VIOLATIONMEMORY_FREE, ldv_msg_freeErr0REQUIRES_VIOLATION, ldv_msg_freeErr1REQUIRES_VIOLATION, mainErr0ENSURES_VIOLATIONMEMORY_LEAK, LDV_INIT_LIST_HEADErr1REQUIRES_VIOLATION, LDV_INIT_LIST_HEADErr2REQUIRES_VIOLATION, LDV_INIT_LIST_HEADErr0REQUIRES_VIOLATION, LDV_INIT_LIST_HEADErr3REQUIRES_VIOLATION, ldv_list_delErr0REQUIRES_VIOLATION, ldv_list_delErr2REQUIRES_VIOLATION, ldv_list_delErr1REQUIRES_VIOLATION, ldv_list_delErr3REQUIRES_VIOLATION, __ldv_list_addErr4REQUIRES_VIOLATION, __ldv_list_addErr3REQUIRES_VIOLATION, __ldv_list_addErr1REQUIRES_VIOLATION, __ldv_list_addErr2REQUIRES_VIOLATION, __ldv_list_addErr7REQUIRES_VIOLATION, __ldv_list_addErr0REQUIRES_VIOLATION, __ldv_list_addErr5REQUIRES_VIOLATION, __ldv_list_addErr6REQUIRES_VIOLATION, ldv_dev_set_drvdataErr1REQUIRES_VIOLATION, ldv_dev_set_drvdataErr0REQUIRES_VIOLATION, ldv_atomic_sub_returnErr0REQUIRES_VIOLATION, ldv_atomic_sub_returnErr2REQUIRES_VIOLATION, ldv_atomic_sub_returnErr1REQUIRES_VIOLATION, ldv_atomic_sub_returnErr3REQUIRES_VIOLATION, ldv_list_add_tailErr1REQUIRES_VIOLATION, ldv_list_add_tailErr0REQUIRES_VIOLATION, ldv_dev_get_drvdataErr0REQUIRES_VIOLATION, ldv_dev_get_drvdataErr1REQUIRES_VIOLATION, ldv_msg_allocErr1REQUIRES_VIOLATION, ldv_msg_allocErr0REQUIRES_VIOLATION]=== [2018-11-28 11:25:39,833 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-28 11:25:39,833 INFO L82 PathProgramCache]: Analyzing trace with hash 309328275, now seen corresponding path program 1 times [2018-11-28 11:25:39,833 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-28 11:25:39,833 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-28 11:25:39,834 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 11:25:39,834 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-28 11:25:39,834 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 11:25:39,842 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-28 11:25:39,873 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-28 11:25:39,873 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-28 11:25:39,873 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-11-28 11:25:39,873 INFO L459 AbstractCegarLoop]: Interpolant automaton has 5 states [2018-11-28 11:25:39,873 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-11-28 11:25:39,873 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-11-28 11:25:39,874 INFO L87 Difference]: Start difference. First operand 144 states and 154 transitions. Second operand 5 states. [2018-11-28 11:25:39,887 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-28 11:25:39,887 INFO L93 Difference]: Finished difference Result 143 states and 151 transitions. [2018-11-28 11:25:39,887 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2018-11-28 11:25:39,888 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 17 [2018-11-28 11:25:39,888 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-28 11:25:39,889 INFO L225 Difference]: With dead ends: 143 [2018-11-28 11:25:39,889 INFO L226 Difference]: Without dead ends: 143 [2018-11-28 11:25:39,889 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 5 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-11-28 11:25:39,890 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 143 states. [2018-11-28 11:25:39,896 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 143 to 141. [2018-11-28 11:25:39,896 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 141 states. [2018-11-28 11:25:39,897 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 141 states to 141 states and 149 transitions. [2018-11-28 11:25:39,897 INFO L78 Accepts]: Start accepts. Automaton has 141 states and 149 transitions. Word has length 17 [2018-11-28 11:25:39,898 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-28 11:25:39,898 INFO L480 AbstractCegarLoop]: Abstraction has 141 states and 149 transitions. [2018-11-28 11:25:39,898 INFO L481 AbstractCegarLoop]: Interpolant automaton has 5 states. [2018-11-28 11:25:39,898 INFO L276 IsEmpty]: Start isEmpty. Operand 141 states and 149 transitions. [2018-11-28 11:25:39,898 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 28 [2018-11-28 11:25:39,899 INFO L394 BasicCegarLoop]: Found error trace [2018-11-28 11:25:39,899 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-28 11:25:39,899 INFO L423 AbstractCegarLoop]: === Iteration 4 === [ldv_kref_initErr1REQUIRES_VIOLATION, ldv_kref_initErr0REQUIRES_VIOLATION, ldv_list_addErr0REQUIRES_VIOLATION, ldv_list_addErr1REQUIRES_VIOLATION, ldv_kobject_createErr0REQUIRES_VIOLATION, ldv_kobject_createErr1REQUIRES_VIOLATION, ldv_destroy_msgsErr3REQUIRES_VIOLATION, ldv_destroy_msgsErr4REQUIRES_VIOLATION, ldv_destroy_msgsErr0REQUIRES_VIOLATION, ldv_destroy_msgsErr5REQUIRES_VIOLATION, ldv_destroy_msgsErr2REQUIRES_VIOLATION, ldv_destroy_msgsErr1REQUIRES_VIOLATION, ldv_msg_fillErr0REQUIRES_VIOLATION, ldv_msg_fillErr5REQUIRES_VIOLATION, ldv_msg_fillErr1REQUIRES_VIOLATION, ldv_msg_fillErr2REQUIRES_VIOLATION, ldv_msg_fillErr3REQUIRES_VIOLATION, ldv_msg_fillErr4REQUIRES_VIOLATION, ldv_atomic_add_returnErr0REQUIRES_VIOLATION, ldv_atomic_add_returnErr2REQUIRES_VIOLATION, ldv_atomic_add_returnErr1REQUIRES_VIOLATION, ldv_atomic_add_returnErr3REQUIRES_VIOLATION, __ldv_list_delErr3REQUIRES_VIOLATION, __ldv_list_delErr1REQUIRES_VIOLATION, __ldv_list_delErr2REQUIRES_VIOLATION, __ldv_list_delErr0REQUIRES_VIOLATION, ldv_kobject_cleanupErr3ASSERT_VIOLATIONMEMORY_FREE, ldv_kobject_cleanupErr2ASSERT_VIOLATIONMEMORY_FREE, ldv_kobject_cleanupErr4ASSERT_VIOLATIONMEMORY_FREE, ldv_kobject_cleanupErr0REQUIRES_VIOLATION, ldv_kobject_cleanupErr5ASSERT_VIOLATIONMEMORY_FREE, ldv_kobject_cleanupErr1REQUIRES_VIOLATION, ldv_msg_freeErr3ASSERT_VIOLATIONMEMORY_FREE, ldv_msg_freeErr5ASSERT_VIOLATIONMEMORY_FREE, ldv_msg_freeErr2ASSERT_VIOLATIONMEMORY_FREE, ldv_msg_freeErr4ASSERT_VIOLATIONMEMORY_FREE, ldv_msg_freeErr0REQUIRES_VIOLATION, ldv_msg_freeErr1REQUIRES_VIOLATION, mainErr0ENSURES_VIOLATIONMEMORY_LEAK, LDV_INIT_LIST_HEADErr1REQUIRES_VIOLATION, LDV_INIT_LIST_HEADErr2REQUIRES_VIOLATION, LDV_INIT_LIST_HEADErr0REQUIRES_VIOLATION, LDV_INIT_LIST_HEADErr3REQUIRES_VIOLATION, ldv_list_delErr0REQUIRES_VIOLATION, ldv_list_delErr2REQUIRES_VIOLATION, ldv_list_delErr1REQUIRES_VIOLATION, ldv_list_delErr3REQUIRES_VIOLATION, __ldv_list_addErr4REQUIRES_VIOLATION, __ldv_list_addErr3REQUIRES_VIOLATION, __ldv_list_addErr1REQUIRES_VIOLATION, __ldv_list_addErr2REQUIRES_VIOLATION, __ldv_list_addErr7REQUIRES_VIOLATION, __ldv_list_addErr0REQUIRES_VIOLATION, __ldv_list_addErr5REQUIRES_VIOLATION, __ldv_list_addErr6REQUIRES_VIOLATION, ldv_dev_set_drvdataErr1REQUIRES_VIOLATION, ldv_dev_set_drvdataErr0REQUIRES_VIOLATION, ldv_atomic_sub_returnErr0REQUIRES_VIOLATION, ldv_atomic_sub_returnErr2REQUIRES_VIOLATION, ldv_atomic_sub_returnErr1REQUIRES_VIOLATION, ldv_atomic_sub_returnErr3REQUIRES_VIOLATION, ldv_list_add_tailErr1REQUIRES_VIOLATION, ldv_list_add_tailErr0REQUIRES_VIOLATION, ldv_dev_get_drvdataErr0REQUIRES_VIOLATION, ldv_dev_get_drvdataErr1REQUIRES_VIOLATION, ldv_msg_allocErr1REQUIRES_VIOLATION, ldv_msg_allocErr0REQUIRES_VIOLATION]=== [2018-11-28 11:25:39,899 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-28 11:25:39,900 INFO L82 PathProgramCache]: Analyzing trace with hash -1990609809, now seen corresponding path program 1 times [2018-11-28 11:25:39,900 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-28 11:25:39,900 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-28 11:25:39,901 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 11:25:39,901 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-28 11:25:39,901 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 11:25:39,911 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-28 11:25:39,938 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-28 11:25:39,938 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-28 11:25:39,938 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-11-28 11:25:39,938 INFO L459 AbstractCegarLoop]: Interpolant automaton has 5 states [2018-11-28 11:25:39,939 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-11-28 11:25:39,939 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-11-28 11:25:39,939 INFO L87 Difference]: Start difference. First operand 141 states and 149 transitions. Second operand 5 states. [2018-11-28 11:25:39,958 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-28 11:25:39,959 INFO L93 Difference]: Finished difference Result 143 states and 150 transitions. [2018-11-28 11:25:39,959 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2018-11-28 11:25:39,959 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 27 [2018-11-28 11:25:39,959 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-28 11:25:39,960 INFO L225 Difference]: With dead ends: 143 [2018-11-28 11:25:39,960 INFO L226 Difference]: Without dead ends: 143 [2018-11-28 11:25:39,960 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 5 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-11-28 11:25:39,961 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 143 states. [2018-11-28 11:25:39,967 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 143 to 141. [2018-11-28 11:25:39,967 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 141 states. [2018-11-28 11:25:39,968 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 141 states to 141 states and 148 transitions. [2018-11-28 11:25:39,968 INFO L78 Accepts]: Start accepts. Automaton has 141 states and 148 transitions. Word has length 27 [2018-11-28 11:25:39,968 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-28 11:25:39,968 INFO L480 AbstractCegarLoop]: Abstraction has 141 states and 148 transitions. [2018-11-28 11:25:39,968 INFO L481 AbstractCegarLoop]: Interpolant automaton has 5 states. [2018-11-28 11:25:39,969 INFO L276 IsEmpty]: Start isEmpty. Operand 141 states and 148 transitions. [2018-11-28 11:25:39,969 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 28 [2018-11-28 11:25:39,969 INFO L394 BasicCegarLoop]: Found error trace [2018-11-28 11:25:39,969 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-28 11:25:39,970 INFO L423 AbstractCegarLoop]: === Iteration 5 === [ldv_kref_initErr1REQUIRES_VIOLATION, ldv_kref_initErr0REQUIRES_VIOLATION, ldv_list_addErr0REQUIRES_VIOLATION, ldv_list_addErr1REQUIRES_VIOLATION, ldv_kobject_createErr0REQUIRES_VIOLATION, ldv_kobject_createErr1REQUIRES_VIOLATION, ldv_destroy_msgsErr3REQUIRES_VIOLATION, ldv_destroy_msgsErr4REQUIRES_VIOLATION, ldv_destroy_msgsErr0REQUIRES_VIOLATION, ldv_destroy_msgsErr5REQUIRES_VIOLATION, ldv_destroy_msgsErr2REQUIRES_VIOLATION, ldv_destroy_msgsErr1REQUIRES_VIOLATION, ldv_msg_fillErr0REQUIRES_VIOLATION, ldv_msg_fillErr5REQUIRES_VIOLATION, ldv_msg_fillErr1REQUIRES_VIOLATION, ldv_msg_fillErr2REQUIRES_VIOLATION, ldv_msg_fillErr3REQUIRES_VIOLATION, ldv_msg_fillErr4REQUIRES_VIOLATION, ldv_atomic_add_returnErr0REQUIRES_VIOLATION, ldv_atomic_add_returnErr2REQUIRES_VIOLATION, ldv_atomic_add_returnErr1REQUIRES_VIOLATION, ldv_atomic_add_returnErr3REQUIRES_VIOLATION, __ldv_list_delErr3REQUIRES_VIOLATION, __ldv_list_delErr1REQUIRES_VIOLATION, __ldv_list_delErr2REQUIRES_VIOLATION, __ldv_list_delErr0REQUIRES_VIOLATION, ldv_kobject_cleanupErr3ASSERT_VIOLATIONMEMORY_FREE, ldv_kobject_cleanupErr2ASSERT_VIOLATIONMEMORY_FREE, ldv_kobject_cleanupErr4ASSERT_VIOLATIONMEMORY_FREE, ldv_kobject_cleanupErr0REQUIRES_VIOLATION, ldv_kobject_cleanupErr5ASSERT_VIOLATIONMEMORY_FREE, ldv_kobject_cleanupErr1REQUIRES_VIOLATION, ldv_msg_freeErr3ASSERT_VIOLATIONMEMORY_FREE, ldv_msg_freeErr5ASSERT_VIOLATIONMEMORY_FREE, ldv_msg_freeErr2ASSERT_VIOLATIONMEMORY_FREE, ldv_msg_freeErr4ASSERT_VIOLATIONMEMORY_FREE, ldv_msg_freeErr0REQUIRES_VIOLATION, ldv_msg_freeErr1REQUIRES_VIOLATION, mainErr0ENSURES_VIOLATIONMEMORY_LEAK, LDV_INIT_LIST_HEADErr1REQUIRES_VIOLATION, LDV_INIT_LIST_HEADErr2REQUIRES_VIOLATION, LDV_INIT_LIST_HEADErr0REQUIRES_VIOLATION, LDV_INIT_LIST_HEADErr3REQUIRES_VIOLATION, ldv_list_delErr0REQUIRES_VIOLATION, ldv_list_delErr2REQUIRES_VIOLATION, ldv_list_delErr1REQUIRES_VIOLATION, ldv_list_delErr3REQUIRES_VIOLATION, __ldv_list_addErr4REQUIRES_VIOLATION, __ldv_list_addErr3REQUIRES_VIOLATION, __ldv_list_addErr1REQUIRES_VIOLATION, __ldv_list_addErr2REQUIRES_VIOLATION, __ldv_list_addErr7REQUIRES_VIOLATION, __ldv_list_addErr0REQUIRES_VIOLATION, __ldv_list_addErr5REQUIRES_VIOLATION, __ldv_list_addErr6REQUIRES_VIOLATION, ldv_dev_set_drvdataErr1REQUIRES_VIOLATION, ldv_dev_set_drvdataErr0REQUIRES_VIOLATION, ldv_atomic_sub_returnErr0REQUIRES_VIOLATION, ldv_atomic_sub_returnErr2REQUIRES_VIOLATION, ldv_atomic_sub_returnErr1REQUIRES_VIOLATION, ldv_atomic_sub_returnErr3REQUIRES_VIOLATION, ldv_list_add_tailErr1REQUIRES_VIOLATION, ldv_list_add_tailErr0REQUIRES_VIOLATION, ldv_dev_get_drvdataErr0REQUIRES_VIOLATION, ldv_dev_get_drvdataErr1REQUIRES_VIOLATION, ldv_msg_allocErr1REQUIRES_VIOLATION, ldv_msg_allocErr0REQUIRES_VIOLATION]=== [2018-11-28 11:25:39,970 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-28 11:25:39,970 INFO L82 PathProgramCache]: Analyzing trace with hash 1793823310, now seen corresponding path program 1 times [2018-11-28 11:25:39,970 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-28 11:25:39,970 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-28 11:25:39,975 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 11:25:39,975 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-28 11:25:39,975 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 11:25:39,986 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-28 11:25:40,045 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-28 11:25:40,046 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-28 11:25:40,046 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [7] imperfect sequences [] total 7 [2018-11-28 11:25:40,046 INFO L459 AbstractCegarLoop]: Interpolant automaton has 7 states [2018-11-28 11:25:40,046 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2018-11-28 11:25:40,046 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=11, Invalid=31, Unknown=0, NotChecked=0, Total=42 [2018-11-28 11:25:40,046 INFO L87 Difference]: Start difference. First operand 141 states and 148 transitions. Second operand 7 states. [2018-11-28 11:25:40,078 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-28 11:25:40,078 INFO L93 Difference]: Finished difference Result 157 states and 165 transitions. [2018-11-28 11:25:40,079 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 8 states. [2018-11-28 11:25:40,079 INFO L78 Accepts]: Start accepts. Automaton has 7 states. Word has length 27 [2018-11-28 11:25:40,079 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-28 11:25:40,080 INFO L225 Difference]: With dead ends: 157 [2018-11-28 11:25:40,080 INFO L226 Difference]: Without dead ends: 157 [2018-11-28 11:25:40,081 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 8 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 6 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=15, Invalid=41, Unknown=0, NotChecked=0, Total=56 [2018-11-28 11:25:40,082 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 157 states. [2018-11-28 11:25:40,088 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 157 to 150. [2018-11-28 11:25:40,088 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 150 states. [2018-11-28 11:25:40,089 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 150 states to 150 states and 157 transitions. [2018-11-28 11:25:40,089 INFO L78 Accepts]: Start accepts. Automaton has 150 states and 157 transitions. Word has length 27 [2018-11-28 11:25:40,090 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-28 11:25:40,090 INFO L480 AbstractCegarLoop]: Abstraction has 150 states and 157 transitions. [2018-11-28 11:25:40,090 INFO L481 AbstractCegarLoop]: Interpolant automaton has 7 states. [2018-11-28 11:25:40,090 INFO L276 IsEmpty]: Start isEmpty. Operand 150 states and 157 transitions. [2018-11-28 11:25:40,092 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 33 [2018-11-28 11:25:40,093 INFO L394 BasicCegarLoop]: Found error trace [2018-11-28 11:25:40,093 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-28 11:25:40,093 INFO L423 AbstractCegarLoop]: === Iteration 6 === [ldv_kref_initErr1REQUIRES_VIOLATION, ldv_kref_initErr0REQUIRES_VIOLATION, ldv_list_addErr0REQUIRES_VIOLATION, ldv_list_addErr1REQUIRES_VIOLATION, ldv_kobject_createErr0REQUIRES_VIOLATION, ldv_kobject_createErr1REQUIRES_VIOLATION, ldv_destroy_msgsErr3REQUIRES_VIOLATION, ldv_destroy_msgsErr4REQUIRES_VIOLATION, ldv_destroy_msgsErr0REQUIRES_VIOLATION, ldv_destroy_msgsErr5REQUIRES_VIOLATION, ldv_destroy_msgsErr2REQUIRES_VIOLATION, ldv_destroy_msgsErr1REQUIRES_VIOLATION, ldv_msg_fillErr0REQUIRES_VIOLATION, ldv_msg_fillErr5REQUIRES_VIOLATION, ldv_msg_fillErr1REQUIRES_VIOLATION, ldv_msg_fillErr2REQUIRES_VIOLATION, ldv_msg_fillErr3REQUIRES_VIOLATION, ldv_msg_fillErr4REQUIRES_VIOLATION, ldv_atomic_add_returnErr0REQUIRES_VIOLATION, ldv_atomic_add_returnErr2REQUIRES_VIOLATION, ldv_atomic_add_returnErr1REQUIRES_VIOLATION, ldv_atomic_add_returnErr3REQUIRES_VIOLATION, __ldv_list_delErr3REQUIRES_VIOLATION, __ldv_list_delErr1REQUIRES_VIOLATION, __ldv_list_delErr2REQUIRES_VIOLATION, __ldv_list_delErr0REQUIRES_VIOLATION, ldv_kobject_cleanupErr3ASSERT_VIOLATIONMEMORY_FREE, ldv_kobject_cleanupErr2ASSERT_VIOLATIONMEMORY_FREE, ldv_kobject_cleanupErr4ASSERT_VIOLATIONMEMORY_FREE, ldv_kobject_cleanupErr0REQUIRES_VIOLATION, ldv_kobject_cleanupErr5ASSERT_VIOLATIONMEMORY_FREE, ldv_kobject_cleanupErr1REQUIRES_VIOLATION, ldv_msg_freeErr3ASSERT_VIOLATIONMEMORY_FREE, ldv_msg_freeErr5ASSERT_VIOLATIONMEMORY_FREE, ldv_msg_freeErr2ASSERT_VIOLATIONMEMORY_FREE, ldv_msg_freeErr4ASSERT_VIOLATIONMEMORY_FREE, ldv_msg_freeErr0REQUIRES_VIOLATION, ldv_msg_freeErr1REQUIRES_VIOLATION, mainErr0ENSURES_VIOLATIONMEMORY_LEAK, LDV_INIT_LIST_HEADErr1REQUIRES_VIOLATION, LDV_INIT_LIST_HEADErr2REQUIRES_VIOLATION, LDV_INIT_LIST_HEADErr0REQUIRES_VIOLATION, LDV_INIT_LIST_HEADErr3REQUIRES_VIOLATION, ldv_list_delErr0REQUIRES_VIOLATION, ldv_list_delErr2REQUIRES_VIOLATION, ldv_list_delErr1REQUIRES_VIOLATION, ldv_list_delErr3REQUIRES_VIOLATION, __ldv_list_addErr4REQUIRES_VIOLATION, __ldv_list_addErr3REQUIRES_VIOLATION, __ldv_list_addErr1REQUIRES_VIOLATION, __ldv_list_addErr2REQUIRES_VIOLATION, __ldv_list_addErr7REQUIRES_VIOLATION, __ldv_list_addErr0REQUIRES_VIOLATION, __ldv_list_addErr5REQUIRES_VIOLATION, __ldv_list_addErr6REQUIRES_VIOLATION, ldv_dev_set_drvdataErr1REQUIRES_VIOLATION, ldv_dev_set_drvdataErr0REQUIRES_VIOLATION, ldv_atomic_sub_returnErr0REQUIRES_VIOLATION, ldv_atomic_sub_returnErr2REQUIRES_VIOLATION, ldv_atomic_sub_returnErr1REQUIRES_VIOLATION, ldv_atomic_sub_returnErr3REQUIRES_VIOLATION, ldv_list_add_tailErr1REQUIRES_VIOLATION, ldv_list_add_tailErr0REQUIRES_VIOLATION, ldv_dev_get_drvdataErr0REQUIRES_VIOLATION, ldv_dev_get_drvdataErr1REQUIRES_VIOLATION, ldv_msg_allocErr1REQUIRES_VIOLATION, ldv_msg_allocErr0REQUIRES_VIOLATION]=== [2018-11-28 11:25:40,093 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-28 11:25:40,093 INFO L82 PathProgramCache]: Analyzing trace with hash 1482045916, now seen corresponding path program 1 times [2018-11-28 11:25:40,094 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-28 11:25:40,094 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-28 11:25:40,095 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 11:25:40,095 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-28 11:25:40,095 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 11:25:40,107 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-28 11:25:40,181 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-28 11:25:40,181 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-28 11:25:40,181 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [10] imperfect sequences [] total 10 [2018-11-28 11:25:40,182 INFO L459 AbstractCegarLoop]: Interpolant automaton has 11 states [2018-11-28 11:25:40,182 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 11 interpolants. [2018-11-28 11:25:40,182 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=19, Invalid=91, Unknown=0, NotChecked=0, Total=110 [2018-11-28 11:25:40,182 INFO L87 Difference]: Start difference. First operand 150 states and 157 transitions. Second operand 11 states. [2018-11-28 11:25:40,386 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-28 11:25:40,386 INFO L93 Difference]: Finished difference Result 149 states and 156 transitions. [2018-11-28 11:25:40,387 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 11 states. [2018-11-28 11:25:40,387 INFO L78 Accepts]: Start accepts. Automaton has 11 states. Word has length 32 [2018-11-28 11:25:40,387 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-28 11:25:40,388 INFO L225 Difference]: With dead ends: 149 [2018-11-28 11:25:40,388 INFO L226 Difference]: Without dead ends: 149 [2018-11-28 11:25:40,388 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 13 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 12 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 3 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=31, Invalid=151, Unknown=0, NotChecked=0, Total=182 [2018-11-28 11:25:40,388 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 149 states. [2018-11-28 11:25:40,391 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 149 to 149. [2018-11-28 11:25:40,391 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 149 states. [2018-11-28 11:25:40,395 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 149 states to 149 states and 156 transitions. [2018-11-28 11:25:40,395 INFO L78 Accepts]: Start accepts. Automaton has 149 states and 156 transitions. Word has length 32 [2018-11-28 11:25:40,396 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-28 11:25:40,396 INFO L480 AbstractCegarLoop]: Abstraction has 149 states and 156 transitions. [2018-11-28 11:25:40,396 INFO L481 AbstractCegarLoop]: Interpolant automaton has 11 states. [2018-11-28 11:25:40,396 INFO L276 IsEmpty]: Start isEmpty. Operand 149 states and 156 transitions. [2018-11-28 11:25:40,397 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 33 [2018-11-28 11:25:40,397 INFO L394 BasicCegarLoop]: Found error trace [2018-11-28 11:25:40,397 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-28 11:25:40,397 INFO L423 AbstractCegarLoop]: === Iteration 7 === [ldv_kref_initErr1REQUIRES_VIOLATION, ldv_kref_initErr0REQUIRES_VIOLATION, ldv_list_addErr0REQUIRES_VIOLATION, ldv_list_addErr1REQUIRES_VIOLATION, ldv_kobject_createErr0REQUIRES_VIOLATION, ldv_kobject_createErr1REQUIRES_VIOLATION, ldv_destroy_msgsErr3REQUIRES_VIOLATION, ldv_destroy_msgsErr4REQUIRES_VIOLATION, ldv_destroy_msgsErr0REQUIRES_VIOLATION, ldv_destroy_msgsErr5REQUIRES_VIOLATION, ldv_destroy_msgsErr2REQUIRES_VIOLATION, ldv_destroy_msgsErr1REQUIRES_VIOLATION, ldv_msg_fillErr0REQUIRES_VIOLATION, ldv_msg_fillErr5REQUIRES_VIOLATION, ldv_msg_fillErr1REQUIRES_VIOLATION, ldv_msg_fillErr2REQUIRES_VIOLATION, ldv_msg_fillErr3REQUIRES_VIOLATION, ldv_msg_fillErr4REQUIRES_VIOLATION, ldv_atomic_add_returnErr0REQUIRES_VIOLATION, ldv_atomic_add_returnErr2REQUIRES_VIOLATION, ldv_atomic_add_returnErr1REQUIRES_VIOLATION, ldv_atomic_add_returnErr3REQUIRES_VIOLATION, __ldv_list_delErr3REQUIRES_VIOLATION, __ldv_list_delErr1REQUIRES_VIOLATION, __ldv_list_delErr2REQUIRES_VIOLATION, __ldv_list_delErr0REQUIRES_VIOLATION, ldv_kobject_cleanupErr3ASSERT_VIOLATIONMEMORY_FREE, ldv_kobject_cleanupErr2ASSERT_VIOLATIONMEMORY_FREE, ldv_kobject_cleanupErr4ASSERT_VIOLATIONMEMORY_FREE, ldv_kobject_cleanupErr0REQUIRES_VIOLATION, ldv_kobject_cleanupErr5ASSERT_VIOLATIONMEMORY_FREE, ldv_kobject_cleanupErr1REQUIRES_VIOLATION, ldv_msg_freeErr3ASSERT_VIOLATIONMEMORY_FREE, ldv_msg_freeErr5ASSERT_VIOLATIONMEMORY_FREE, ldv_msg_freeErr2ASSERT_VIOLATIONMEMORY_FREE, ldv_msg_freeErr4ASSERT_VIOLATIONMEMORY_FREE, ldv_msg_freeErr0REQUIRES_VIOLATION, ldv_msg_freeErr1REQUIRES_VIOLATION, mainErr0ENSURES_VIOLATIONMEMORY_LEAK, LDV_INIT_LIST_HEADErr1REQUIRES_VIOLATION, LDV_INIT_LIST_HEADErr2REQUIRES_VIOLATION, LDV_INIT_LIST_HEADErr0REQUIRES_VIOLATION, LDV_INIT_LIST_HEADErr3REQUIRES_VIOLATION, ldv_list_delErr0REQUIRES_VIOLATION, ldv_list_delErr2REQUIRES_VIOLATION, ldv_list_delErr1REQUIRES_VIOLATION, ldv_list_delErr3REQUIRES_VIOLATION, __ldv_list_addErr4REQUIRES_VIOLATION, __ldv_list_addErr3REQUIRES_VIOLATION, __ldv_list_addErr1REQUIRES_VIOLATION, __ldv_list_addErr2REQUIRES_VIOLATION, __ldv_list_addErr7REQUIRES_VIOLATION, __ldv_list_addErr0REQUIRES_VIOLATION, __ldv_list_addErr5REQUIRES_VIOLATION, __ldv_list_addErr6REQUIRES_VIOLATION, ldv_dev_set_drvdataErr1REQUIRES_VIOLATION, ldv_dev_set_drvdataErr0REQUIRES_VIOLATION, ldv_atomic_sub_returnErr0REQUIRES_VIOLATION, ldv_atomic_sub_returnErr2REQUIRES_VIOLATION, ldv_atomic_sub_returnErr1REQUIRES_VIOLATION, ldv_atomic_sub_returnErr3REQUIRES_VIOLATION, ldv_list_add_tailErr1REQUIRES_VIOLATION, ldv_list_add_tailErr0REQUIRES_VIOLATION, ldv_dev_get_drvdataErr0REQUIRES_VIOLATION, ldv_dev_get_drvdataErr1REQUIRES_VIOLATION, ldv_msg_allocErr1REQUIRES_VIOLATION, ldv_msg_allocErr0REQUIRES_VIOLATION]=== [2018-11-28 11:25:40,397 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-28 11:25:40,398 INFO L82 PathProgramCache]: Analyzing trace with hash 1482045917, now seen corresponding path program 1 times [2018-11-28 11:25:40,398 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-28 11:25:40,398 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-28 11:25:40,399 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 11:25:40,399 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-28 11:25:40,399 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 11:25:40,408 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-28 11:25:40,429 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-28 11:25:40,429 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-28 11:25:40,429 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2018-11-28 11:25:40,430 INFO L459 AbstractCegarLoop]: Interpolant automaton has 4 states [2018-11-28 11:25:40,430 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2018-11-28 11:25:40,430 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2018-11-28 11:25:40,430 INFO L87 Difference]: Start difference. First operand 149 states and 156 transitions. Second operand 4 states. [2018-11-28 11:25:40,444 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-28 11:25:40,444 INFO L93 Difference]: Finished difference Result 152 states and 159 transitions. [2018-11-28 11:25:40,445 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2018-11-28 11:25:40,445 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 32 [2018-11-28 11:25:40,445 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-28 11:25:40,446 INFO L225 Difference]: With dead ends: 152 [2018-11-28 11:25:40,446 INFO L226 Difference]: Without dead ends: 150 [2018-11-28 11:25:40,446 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 5 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2018-11-28 11:25:40,447 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 150 states. [2018-11-28 11:25:40,451 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 150 to 150. [2018-11-28 11:25:40,451 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 150 states. [2018-11-28 11:25:40,452 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 150 states to 150 states and 157 transitions. [2018-11-28 11:25:40,452 INFO L78 Accepts]: Start accepts. Automaton has 150 states and 157 transitions. Word has length 32 [2018-11-28 11:25:40,452 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-28 11:25:40,453 INFO L480 AbstractCegarLoop]: Abstraction has 150 states and 157 transitions. [2018-11-28 11:25:40,453 INFO L481 AbstractCegarLoop]: Interpolant automaton has 4 states. [2018-11-28 11:25:40,453 INFO L276 IsEmpty]: Start isEmpty. Operand 150 states and 157 transitions. [2018-11-28 11:25:40,453 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 34 [2018-11-28 11:25:40,453 INFO L394 BasicCegarLoop]: Found error trace [2018-11-28 11:25:40,454 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-28 11:25:40,454 INFO L423 AbstractCegarLoop]: === Iteration 8 === [ldv_kref_initErr1REQUIRES_VIOLATION, ldv_kref_initErr0REQUIRES_VIOLATION, ldv_list_addErr0REQUIRES_VIOLATION, ldv_list_addErr1REQUIRES_VIOLATION, ldv_kobject_createErr0REQUIRES_VIOLATION, ldv_kobject_createErr1REQUIRES_VIOLATION, ldv_destroy_msgsErr3REQUIRES_VIOLATION, ldv_destroy_msgsErr4REQUIRES_VIOLATION, ldv_destroy_msgsErr0REQUIRES_VIOLATION, ldv_destroy_msgsErr5REQUIRES_VIOLATION, ldv_destroy_msgsErr2REQUIRES_VIOLATION, ldv_destroy_msgsErr1REQUIRES_VIOLATION, ldv_msg_fillErr0REQUIRES_VIOLATION, ldv_msg_fillErr5REQUIRES_VIOLATION, ldv_msg_fillErr1REQUIRES_VIOLATION, ldv_msg_fillErr2REQUIRES_VIOLATION, ldv_msg_fillErr3REQUIRES_VIOLATION, ldv_msg_fillErr4REQUIRES_VIOLATION, ldv_atomic_add_returnErr0REQUIRES_VIOLATION, ldv_atomic_add_returnErr2REQUIRES_VIOLATION, ldv_atomic_add_returnErr1REQUIRES_VIOLATION, ldv_atomic_add_returnErr3REQUIRES_VIOLATION, __ldv_list_delErr3REQUIRES_VIOLATION, __ldv_list_delErr1REQUIRES_VIOLATION, __ldv_list_delErr2REQUIRES_VIOLATION, __ldv_list_delErr0REQUIRES_VIOLATION, ldv_kobject_cleanupErr3ASSERT_VIOLATIONMEMORY_FREE, ldv_kobject_cleanupErr2ASSERT_VIOLATIONMEMORY_FREE, ldv_kobject_cleanupErr4ASSERT_VIOLATIONMEMORY_FREE, ldv_kobject_cleanupErr0REQUIRES_VIOLATION, ldv_kobject_cleanupErr5ASSERT_VIOLATIONMEMORY_FREE, ldv_kobject_cleanupErr1REQUIRES_VIOLATION, ldv_msg_freeErr3ASSERT_VIOLATIONMEMORY_FREE, ldv_msg_freeErr5ASSERT_VIOLATIONMEMORY_FREE, ldv_msg_freeErr2ASSERT_VIOLATIONMEMORY_FREE, ldv_msg_freeErr4ASSERT_VIOLATIONMEMORY_FREE, ldv_msg_freeErr0REQUIRES_VIOLATION, ldv_msg_freeErr1REQUIRES_VIOLATION, mainErr0ENSURES_VIOLATIONMEMORY_LEAK, LDV_INIT_LIST_HEADErr1REQUIRES_VIOLATION, LDV_INIT_LIST_HEADErr2REQUIRES_VIOLATION, LDV_INIT_LIST_HEADErr0REQUIRES_VIOLATION, LDV_INIT_LIST_HEADErr3REQUIRES_VIOLATION, ldv_list_delErr0REQUIRES_VIOLATION, ldv_list_delErr2REQUIRES_VIOLATION, ldv_list_delErr1REQUIRES_VIOLATION, ldv_list_delErr3REQUIRES_VIOLATION, __ldv_list_addErr4REQUIRES_VIOLATION, __ldv_list_addErr3REQUIRES_VIOLATION, __ldv_list_addErr1REQUIRES_VIOLATION, __ldv_list_addErr2REQUIRES_VIOLATION, __ldv_list_addErr7REQUIRES_VIOLATION, __ldv_list_addErr0REQUIRES_VIOLATION, __ldv_list_addErr5REQUIRES_VIOLATION, __ldv_list_addErr6REQUIRES_VIOLATION, ldv_dev_set_drvdataErr1REQUIRES_VIOLATION, ldv_dev_set_drvdataErr0REQUIRES_VIOLATION, ldv_atomic_sub_returnErr0REQUIRES_VIOLATION, ldv_atomic_sub_returnErr2REQUIRES_VIOLATION, ldv_atomic_sub_returnErr1REQUIRES_VIOLATION, ldv_atomic_sub_returnErr3REQUIRES_VIOLATION, ldv_list_add_tailErr1REQUIRES_VIOLATION, ldv_list_add_tailErr0REQUIRES_VIOLATION, ldv_dev_get_drvdataErr0REQUIRES_VIOLATION, ldv_dev_get_drvdataErr1REQUIRES_VIOLATION, ldv_msg_allocErr1REQUIRES_VIOLATION, ldv_msg_allocErr0REQUIRES_VIOLATION]=== [2018-11-28 11:25:40,454 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-28 11:25:40,454 INFO L82 PathProgramCache]: Analyzing trace with hash 426736712, now seen corresponding path program 1 times [2018-11-28 11:25:40,454 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-28 11:25:40,454 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-28 11:25:40,459 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 11:25:40,459 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-28 11:25:40,459 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 11:25:40,468 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-28 11:25:40,506 INFO L134 CoverageAnalysis]: Checked inductivity of 1 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-28 11:25:40,506 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-28 11:25:40,506 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_2ca7a644-5b0a-4f3d-9179-f30a2c52dfce/bin-2019/uautomizer/z3 Starting monitored process 2 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 2 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-28 11:25:40,530 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-28 11:25:40,561 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-28 11:25:40,567 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-28 11:25:40,604 INFO L134 CoverageAnalysis]: Checked inductivity of 1 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-28 11:25:40,620 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-11-28 11:25:40,620 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [5, 5] total 6 [2018-11-28 11:25:40,620 INFO L459 AbstractCegarLoop]: Interpolant automaton has 6 states [2018-11-28 11:25:40,620 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2018-11-28 11:25:40,621 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=12, Invalid=18, Unknown=0, NotChecked=0, Total=30 [2018-11-28 11:25:40,621 INFO L87 Difference]: Start difference. First operand 150 states and 157 transitions. Second operand 6 states. [2018-11-28 11:25:40,643 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-28 11:25:40,643 INFO L93 Difference]: Finished difference Result 153 states and 160 transitions. [2018-11-28 11:25:40,643 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2018-11-28 11:25:40,644 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 33 [2018-11-28 11:25:40,644 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-28 11:25:40,644 INFO L225 Difference]: With dead ends: 153 [2018-11-28 11:25:40,645 INFO L226 Difference]: Without dead ends: 151 [2018-11-28 11:25:40,645 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 38 GetRequests, 33 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=16, Invalid=26, Unknown=0, NotChecked=0, Total=42 [2018-11-28 11:25:40,645 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 151 states. [2018-11-28 11:25:40,649 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 151 to 151. [2018-11-28 11:25:40,649 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 151 states. [2018-11-28 11:25:40,649 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 151 states to 151 states and 158 transitions. [2018-11-28 11:25:40,650 INFO L78 Accepts]: Start accepts. Automaton has 151 states and 158 transitions. Word has length 33 [2018-11-28 11:25:40,650 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-28 11:25:40,650 INFO L480 AbstractCegarLoop]: Abstraction has 151 states and 158 transitions. [2018-11-28 11:25:40,650 INFO L481 AbstractCegarLoop]: Interpolant automaton has 6 states. [2018-11-28 11:25:40,650 INFO L276 IsEmpty]: Start isEmpty. Operand 151 states and 158 transitions. [2018-11-28 11:25:40,651 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 35 [2018-11-28 11:25:40,651 INFO L394 BasicCegarLoop]: Found error trace [2018-11-28 11:25:40,651 INFO L402 BasicCegarLoop]: trace histogram [2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-28 11:25:40,654 INFO L423 AbstractCegarLoop]: === Iteration 9 === [ldv_kref_initErr1REQUIRES_VIOLATION, ldv_kref_initErr0REQUIRES_VIOLATION, ldv_list_addErr0REQUIRES_VIOLATION, ldv_list_addErr1REQUIRES_VIOLATION, ldv_kobject_createErr0REQUIRES_VIOLATION, ldv_kobject_createErr1REQUIRES_VIOLATION, ldv_destroy_msgsErr3REQUIRES_VIOLATION, ldv_destroy_msgsErr4REQUIRES_VIOLATION, ldv_destroy_msgsErr0REQUIRES_VIOLATION, ldv_destroy_msgsErr5REQUIRES_VIOLATION, ldv_destroy_msgsErr2REQUIRES_VIOLATION, ldv_destroy_msgsErr1REQUIRES_VIOLATION, ldv_msg_fillErr0REQUIRES_VIOLATION, ldv_msg_fillErr5REQUIRES_VIOLATION, ldv_msg_fillErr1REQUIRES_VIOLATION, ldv_msg_fillErr2REQUIRES_VIOLATION, ldv_msg_fillErr3REQUIRES_VIOLATION, ldv_msg_fillErr4REQUIRES_VIOLATION, ldv_atomic_add_returnErr0REQUIRES_VIOLATION, ldv_atomic_add_returnErr2REQUIRES_VIOLATION, ldv_atomic_add_returnErr1REQUIRES_VIOLATION, ldv_atomic_add_returnErr3REQUIRES_VIOLATION, __ldv_list_delErr3REQUIRES_VIOLATION, __ldv_list_delErr1REQUIRES_VIOLATION, __ldv_list_delErr2REQUIRES_VIOLATION, __ldv_list_delErr0REQUIRES_VIOLATION, ldv_kobject_cleanupErr3ASSERT_VIOLATIONMEMORY_FREE, ldv_kobject_cleanupErr2ASSERT_VIOLATIONMEMORY_FREE, ldv_kobject_cleanupErr4ASSERT_VIOLATIONMEMORY_FREE, ldv_kobject_cleanupErr0REQUIRES_VIOLATION, ldv_kobject_cleanupErr5ASSERT_VIOLATIONMEMORY_FREE, ldv_kobject_cleanupErr1REQUIRES_VIOLATION, ldv_msg_freeErr3ASSERT_VIOLATIONMEMORY_FREE, ldv_msg_freeErr5ASSERT_VIOLATIONMEMORY_FREE, ldv_msg_freeErr2ASSERT_VIOLATIONMEMORY_FREE, ldv_msg_freeErr4ASSERT_VIOLATIONMEMORY_FREE, ldv_msg_freeErr0REQUIRES_VIOLATION, ldv_msg_freeErr1REQUIRES_VIOLATION, mainErr0ENSURES_VIOLATIONMEMORY_LEAK, LDV_INIT_LIST_HEADErr1REQUIRES_VIOLATION, LDV_INIT_LIST_HEADErr2REQUIRES_VIOLATION, LDV_INIT_LIST_HEADErr0REQUIRES_VIOLATION, LDV_INIT_LIST_HEADErr3REQUIRES_VIOLATION, ldv_list_delErr0REQUIRES_VIOLATION, ldv_list_delErr2REQUIRES_VIOLATION, ldv_list_delErr1REQUIRES_VIOLATION, ldv_list_delErr3REQUIRES_VIOLATION, __ldv_list_addErr4REQUIRES_VIOLATION, __ldv_list_addErr3REQUIRES_VIOLATION, __ldv_list_addErr1REQUIRES_VIOLATION, __ldv_list_addErr2REQUIRES_VIOLATION, __ldv_list_addErr7REQUIRES_VIOLATION, __ldv_list_addErr0REQUIRES_VIOLATION, __ldv_list_addErr5REQUIRES_VIOLATION, __ldv_list_addErr6REQUIRES_VIOLATION, ldv_dev_set_drvdataErr1REQUIRES_VIOLATION, ldv_dev_set_drvdataErr0REQUIRES_VIOLATION, ldv_atomic_sub_returnErr0REQUIRES_VIOLATION, ldv_atomic_sub_returnErr2REQUIRES_VIOLATION, ldv_atomic_sub_returnErr1REQUIRES_VIOLATION, ldv_atomic_sub_returnErr3REQUIRES_VIOLATION, ldv_list_add_tailErr1REQUIRES_VIOLATION, ldv_list_add_tailErr0REQUIRES_VIOLATION, ldv_dev_get_drvdataErr0REQUIRES_VIOLATION, ldv_dev_get_drvdataErr1REQUIRES_VIOLATION, ldv_msg_allocErr1REQUIRES_VIOLATION, ldv_msg_allocErr0REQUIRES_VIOLATION]=== [2018-11-28 11:25:40,654 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-28 11:25:40,654 INFO L82 PathProgramCache]: Analyzing trace with hash 2071889725, now seen corresponding path program 2 times [2018-11-28 11:25:40,654 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-28 11:25:40,654 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-28 11:25:40,655 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 11:25:40,658 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-28 11:25:40,658 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 11:25:40,669 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-28 11:25:40,698 INFO L134 CoverageAnalysis]: Checked inductivity of 3 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-28 11:25:40,698 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-28 11:25:40,698 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_2ca7a644-5b0a-4f3d-9179-f30a2c52dfce/bin-2019/uautomizer/z3 Starting monitored process 3 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 3 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-28 11:25:40,712 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-11-28 11:25:40,738 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) [2018-11-28 11:25:40,739 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-11-28 11:25:40,742 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-28 11:25:40,796 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 6 treesize of output 5 [2018-11-28 11:25:40,797 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-11-28 11:25:40,820 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-0 vars, 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-28 11:25:40,820 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 2 variables, input treesize:13, output treesize:9 [2018-11-28 11:25:40,953 INFO L134 CoverageAnalysis]: Checked inductivity of 3 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 3 trivial. 0 not checked. [2018-11-28 11:25:40,968 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 1 imperfect interpolant sequences. [2018-11-28 11:25:40,968 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [12] imperfect sequences [6] total 17 [2018-11-28 11:25:40,969 INFO L459 AbstractCegarLoop]: Interpolant automaton has 17 states [2018-11-28 11:25:40,969 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 17 interpolants. [2018-11-28 11:25:40,969 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=42, Invalid=230, Unknown=0, NotChecked=0, Total=272 [2018-11-28 11:25:40,969 INFO L87 Difference]: Start difference. First operand 151 states and 158 transitions. Second operand 17 states. [2018-11-28 11:25:41,492 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-28 11:25:41,493 INFO L93 Difference]: Finished difference Result 213 states and 222 transitions. [2018-11-28 11:25:41,493 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 17 states. [2018-11-28 11:25:41,493 INFO L78 Accepts]: Start accepts. Automaton has 17 states. Word has length 34 [2018-11-28 11:25:41,493 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-28 11:25:41,494 INFO L225 Difference]: With dead ends: 213 [2018-11-28 11:25:41,494 INFO L226 Difference]: Without dead ends: 211 [2018-11-28 11:25:41,494 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 47 GetRequests, 23 SyntacticMatches, 1 SemanticMatches, 23 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 67 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=85, Invalid=515, Unknown=0, NotChecked=0, Total=600 [2018-11-28 11:25:41,494 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 211 states. [2018-11-28 11:25:41,498 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 211 to 151. [2018-11-28 11:25:41,498 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 151 states. [2018-11-28 11:25:41,499 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 151 states to 151 states and 158 transitions. [2018-11-28 11:25:41,499 INFO L78 Accepts]: Start accepts. Automaton has 151 states and 158 transitions. Word has length 34 [2018-11-28 11:25:41,499 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-28 11:25:41,499 INFO L480 AbstractCegarLoop]: Abstraction has 151 states and 158 transitions. [2018-11-28 11:25:41,499 INFO L481 AbstractCegarLoop]: Interpolant automaton has 17 states. [2018-11-28 11:25:41,499 INFO L276 IsEmpty]: Start isEmpty. Operand 151 states and 158 transitions. [2018-11-28 11:25:41,500 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 37 [2018-11-28 11:25:41,500 INFO L394 BasicCegarLoop]: Found error trace [2018-11-28 11:25:41,500 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-28 11:25:41,500 INFO L423 AbstractCegarLoop]: === Iteration 10 === [ldv_kref_initErr1REQUIRES_VIOLATION, ldv_kref_initErr0REQUIRES_VIOLATION, ldv_list_addErr0REQUIRES_VIOLATION, ldv_list_addErr1REQUIRES_VIOLATION, ldv_kobject_createErr0REQUIRES_VIOLATION, ldv_kobject_createErr1REQUIRES_VIOLATION, ldv_destroy_msgsErr3REQUIRES_VIOLATION, ldv_destroy_msgsErr4REQUIRES_VIOLATION, ldv_destroy_msgsErr0REQUIRES_VIOLATION, ldv_destroy_msgsErr5REQUIRES_VIOLATION, ldv_destroy_msgsErr2REQUIRES_VIOLATION, ldv_destroy_msgsErr1REQUIRES_VIOLATION, ldv_msg_fillErr0REQUIRES_VIOLATION, ldv_msg_fillErr5REQUIRES_VIOLATION, ldv_msg_fillErr1REQUIRES_VIOLATION, ldv_msg_fillErr2REQUIRES_VIOLATION, ldv_msg_fillErr3REQUIRES_VIOLATION, ldv_msg_fillErr4REQUIRES_VIOLATION, ldv_atomic_add_returnErr0REQUIRES_VIOLATION, ldv_atomic_add_returnErr2REQUIRES_VIOLATION, ldv_atomic_add_returnErr1REQUIRES_VIOLATION, ldv_atomic_add_returnErr3REQUIRES_VIOLATION, __ldv_list_delErr3REQUIRES_VIOLATION, __ldv_list_delErr1REQUIRES_VIOLATION, __ldv_list_delErr2REQUIRES_VIOLATION, __ldv_list_delErr0REQUIRES_VIOLATION, ldv_kobject_cleanupErr3ASSERT_VIOLATIONMEMORY_FREE, ldv_kobject_cleanupErr2ASSERT_VIOLATIONMEMORY_FREE, ldv_kobject_cleanupErr4ASSERT_VIOLATIONMEMORY_FREE, ldv_kobject_cleanupErr0REQUIRES_VIOLATION, ldv_kobject_cleanupErr5ASSERT_VIOLATIONMEMORY_FREE, ldv_kobject_cleanupErr1REQUIRES_VIOLATION, ldv_msg_freeErr3ASSERT_VIOLATIONMEMORY_FREE, ldv_msg_freeErr5ASSERT_VIOLATIONMEMORY_FREE, ldv_msg_freeErr2ASSERT_VIOLATIONMEMORY_FREE, ldv_msg_freeErr4ASSERT_VIOLATIONMEMORY_FREE, ldv_msg_freeErr0REQUIRES_VIOLATION, ldv_msg_freeErr1REQUIRES_VIOLATION, mainErr0ENSURES_VIOLATIONMEMORY_LEAK, LDV_INIT_LIST_HEADErr1REQUIRES_VIOLATION, LDV_INIT_LIST_HEADErr2REQUIRES_VIOLATION, LDV_INIT_LIST_HEADErr0REQUIRES_VIOLATION, LDV_INIT_LIST_HEADErr3REQUIRES_VIOLATION, ldv_list_delErr0REQUIRES_VIOLATION, ldv_list_delErr2REQUIRES_VIOLATION, ldv_list_delErr1REQUIRES_VIOLATION, ldv_list_delErr3REQUIRES_VIOLATION, __ldv_list_addErr4REQUIRES_VIOLATION, __ldv_list_addErr3REQUIRES_VIOLATION, __ldv_list_addErr1REQUIRES_VIOLATION, __ldv_list_addErr2REQUIRES_VIOLATION, __ldv_list_addErr7REQUIRES_VIOLATION, __ldv_list_addErr0REQUIRES_VIOLATION, __ldv_list_addErr5REQUIRES_VIOLATION, __ldv_list_addErr6REQUIRES_VIOLATION, ldv_dev_set_drvdataErr1REQUIRES_VIOLATION, ldv_dev_set_drvdataErr0REQUIRES_VIOLATION, ldv_atomic_sub_returnErr0REQUIRES_VIOLATION, ldv_atomic_sub_returnErr2REQUIRES_VIOLATION, ldv_atomic_sub_returnErr1REQUIRES_VIOLATION, ldv_atomic_sub_returnErr3REQUIRES_VIOLATION, ldv_list_add_tailErr1REQUIRES_VIOLATION, ldv_list_add_tailErr0REQUIRES_VIOLATION, ldv_dev_get_drvdataErr0REQUIRES_VIOLATION, ldv_dev_get_drvdataErr1REQUIRES_VIOLATION, ldv_msg_allocErr1REQUIRES_VIOLATION, ldv_msg_allocErr0REQUIRES_VIOLATION]=== [2018-11-28 11:25:41,501 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-28 11:25:41,501 INFO L82 PathProgramCache]: Analyzing trace with hash -1823867884, now seen corresponding path program 1 times [2018-11-28 11:25:41,501 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-28 11:25:41,501 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-28 11:25:41,502 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 11:25:41,502 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-28 11:25:41,502 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 11:25:41,511 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-28 11:25:41,583 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-28 11:25:41,584 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-28 11:25:41,584 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [7] imperfect sequences [] total 7 [2018-11-28 11:25:41,584 INFO L459 AbstractCegarLoop]: Interpolant automaton has 7 states [2018-11-28 11:25:41,584 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2018-11-28 11:25:41,584 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=11, Invalid=31, Unknown=0, NotChecked=0, Total=42 [2018-11-28 11:25:41,585 INFO L87 Difference]: Start difference. First operand 151 states and 158 transitions. Second operand 7 states. [2018-11-28 11:25:41,627 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-28 11:25:41,627 INFO L93 Difference]: Finished difference Result 161 states and 168 transitions. [2018-11-28 11:25:41,629 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 8 states. [2018-11-28 11:25:41,629 INFO L78 Accepts]: Start accepts. Automaton has 7 states. Word has length 36 [2018-11-28 11:25:41,630 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-28 11:25:41,630 INFO L225 Difference]: With dead ends: 161 [2018-11-28 11:25:41,630 INFO L226 Difference]: Without dead ends: 161 [2018-11-28 11:25:41,631 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 8 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 6 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=15, Invalid=41, Unknown=0, NotChecked=0, Total=56 [2018-11-28 11:25:41,631 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 161 states. [2018-11-28 11:25:41,634 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 161 to 157. [2018-11-28 11:25:41,634 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 157 states. [2018-11-28 11:25:41,635 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 157 states to 157 states and 164 transitions. [2018-11-28 11:25:41,635 INFO L78 Accepts]: Start accepts. Automaton has 157 states and 164 transitions. Word has length 36 [2018-11-28 11:25:41,635 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-28 11:25:41,635 INFO L480 AbstractCegarLoop]: Abstraction has 157 states and 164 transitions. [2018-11-28 11:25:41,635 INFO L481 AbstractCegarLoop]: Interpolant automaton has 7 states. [2018-11-28 11:25:41,636 INFO L276 IsEmpty]: Start isEmpty. Operand 157 states and 164 transitions. [2018-11-28 11:25:41,636 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 35 [2018-11-28 11:25:41,636 INFO L394 BasicCegarLoop]: Found error trace [2018-11-28 11:25:41,636 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-28 11:25:41,637 INFO L423 AbstractCegarLoop]: === Iteration 11 === [ldv_kref_initErr1REQUIRES_VIOLATION, ldv_kref_initErr0REQUIRES_VIOLATION, ldv_list_addErr0REQUIRES_VIOLATION, ldv_list_addErr1REQUIRES_VIOLATION, ldv_kobject_createErr0REQUIRES_VIOLATION, ldv_kobject_createErr1REQUIRES_VIOLATION, ldv_destroy_msgsErr3REQUIRES_VIOLATION, ldv_destroy_msgsErr4REQUIRES_VIOLATION, ldv_destroy_msgsErr0REQUIRES_VIOLATION, ldv_destroy_msgsErr5REQUIRES_VIOLATION, ldv_destroy_msgsErr2REQUIRES_VIOLATION, ldv_destroy_msgsErr1REQUIRES_VIOLATION, ldv_msg_fillErr0REQUIRES_VIOLATION, ldv_msg_fillErr5REQUIRES_VIOLATION, ldv_msg_fillErr1REQUIRES_VIOLATION, ldv_msg_fillErr2REQUIRES_VIOLATION, ldv_msg_fillErr3REQUIRES_VIOLATION, ldv_msg_fillErr4REQUIRES_VIOLATION, ldv_atomic_add_returnErr0REQUIRES_VIOLATION, ldv_atomic_add_returnErr2REQUIRES_VIOLATION, ldv_atomic_add_returnErr1REQUIRES_VIOLATION, ldv_atomic_add_returnErr3REQUIRES_VIOLATION, __ldv_list_delErr3REQUIRES_VIOLATION, __ldv_list_delErr1REQUIRES_VIOLATION, __ldv_list_delErr2REQUIRES_VIOLATION, __ldv_list_delErr0REQUIRES_VIOLATION, ldv_kobject_cleanupErr3ASSERT_VIOLATIONMEMORY_FREE, ldv_kobject_cleanupErr2ASSERT_VIOLATIONMEMORY_FREE, ldv_kobject_cleanupErr4ASSERT_VIOLATIONMEMORY_FREE, ldv_kobject_cleanupErr0REQUIRES_VIOLATION, ldv_kobject_cleanupErr5ASSERT_VIOLATIONMEMORY_FREE, ldv_kobject_cleanupErr1REQUIRES_VIOLATION, ldv_msg_freeErr3ASSERT_VIOLATIONMEMORY_FREE, ldv_msg_freeErr5ASSERT_VIOLATIONMEMORY_FREE, ldv_msg_freeErr2ASSERT_VIOLATIONMEMORY_FREE, ldv_msg_freeErr4ASSERT_VIOLATIONMEMORY_FREE, ldv_msg_freeErr0REQUIRES_VIOLATION, ldv_msg_freeErr1REQUIRES_VIOLATION, mainErr0ENSURES_VIOLATIONMEMORY_LEAK, LDV_INIT_LIST_HEADErr1REQUIRES_VIOLATION, LDV_INIT_LIST_HEADErr2REQUIRES_VIOLATION, LDV_INIT_LIST_HEADErr0REQUIRES_VIOLATION, LDV_INIT_LIST_HEADErr3REQUIRES_VIOLATION, ldv_list_delErr0REQUIRES_VIOLATION, ldv_list_delErr2REQUIRES_VIOLATION, ldv_list_delErr1REQUIRES_VIOLATION, ldv_list_delErr3REQUIRES_VIOLATION, __ldv_list_addErr4REQUIRES_VIOLATION, __ldv_list_addErr3REQUIRES_VIOLATION, __ldv_list_addErr1REQUIRES_VIOLATION, __ldv_list_addErr2REQUIRES_VIOLATION, __ldv_list_addErr7REQUIRES_VIOLATION, __ldv_list_addErr0REQUIRES_VIOLATION, __ldv_list_addErr5REQUIRES_VIOLATION, __ldv_list_addErr6REQUIRES_VIOLATION, ldv_dev_set_drvdataErr1REQUIRES_VIOLATION, ldv_dev_set_drvdataErr0REQUIRES_VIOLATION, ldv_atomic_sub_returnErr0REQUIRES_VIOLATION, ldv_atomic_sub_returnErr2REQUIRES_VIOLATION, ldv_atomic_sub_returnErr1REQUIRES_VIOLATION, ldv_atomic_sub_returnErr3REQUIRES_VIOLATION, ldv_list_add_tailErr1REQUIRES_VIOLATION, ldv_list_add_tailErr0REQUIRES_VIOLATION, ldv_dev_get_drvdataErr0REQUIRES_VIOLATION, ldv_dev_get_drvdataErr1REQUIRES_VIOLATION, ldv_msg_allocErr1REQUIRES_VIOLATION, ldv_msg_allocErr0REQUIRES_VIOLATION]=== [2018-11-28 11:25:41,637 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-28 11:25:41,637 INFO L82 PathProgramCache]: Analyzing trace with hash -1550558175, now seen corresponding path program 1 times [2018-11-28 11:25:41,637 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-28 11:25:41,637 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-28 11:25:41,638 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 11:25:41,638 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-28 11:25:41,639 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 11:25:41,643 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-28 11:25:41,660 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-28 11:25:41,661 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-28 11:25:41,661 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2018-11-28 11:25:41,661 INFO L459 AbstractCegarLoop]: Interpolant automaton has 3 states [2018-11-28 11:25:41,671 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-28 11:25:41,671 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-28 11:25:41,672 INFO L87 Difference]: Start difference. First operand 157 states and 164 transitions. Second operand 3 states. [2018-11-28 11:25:41,746 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-28 11:25:41,747 INFO L93 Difference]: Finished difference Result 168 states and 174 transitions. [2018-11-28 11:25:41,748 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-28 11:25:41,748 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 34 [2018-11-28 11:25:41,748 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-28 11:25:41,749 INFO L225 Difference]: With dead ends: 168 [2018-11-28 11:25:41,749 INFO L226 Difference]: Without dead ends: 146 [2018-11-28 11:25:41,749 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 10 GetRequests, 9 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-28 11:25:41,749 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 146 states. [2018-11-28 11:25:41,753 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 146 to 138. [2018-11-28 11:25:41,753 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 138 states. [2018-11-28 11:25:41,754 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 138 states to 138 states and 144 transitions. [2018-11-28 11:25:41,754 INFO L78 Accepts]: Start accepts. Automaton has 138 states and 144 transitions. Word has length 34 [2018-11-28 11:25:41,754 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-28 11:25:41,754 INFO L480 AbstractCegarLoop]: Abstraction has 138 states and 144 transitions. [2018-11-28 11:25:41,754 INFO L481 AbstractCegarLoop]: Interpolant automaton has 3 states. [2018-11-28 11:25:41,754 INFO L276 IsEmpty]: Start isEmpty. Operand 138 states and 144 transitions. [2018-11-28 11:25:41,755 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 41 [2018-11-28 11:25:41,755 INFO L394 BasicCegarLoop]: Found error trace [2018-11-28 11:25:41,755 INFO L402 BasicCegarLoop]: trace histogram [3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-28 11:25:41,758 INFO L423 AbstractCegarLoop]: === Iteration 12 === [ldv_kref_initErr1REQUIRES_VIOLATION, ldv_kref_initErr0REQUIRES_VIOLATION, ldv_list_addErr0REQUIRES_VIOLATION, ldv_list_addErr1REQUIRES_VIOLATION, ldv_kobject_createErr0REQUIRES_VIOLATION, ldv_kobject_createErr1REQUIRES_VIOLATION, ldv_destroy_msgsErr3REQUIRES_VIOLATION, ldv_destroy_msgsErr4REQUIRES_VIOLATION, ldv_destroy_msgsErr0REQUIRES_VIOLATION, ldv_destroy_msgsErr5REQUIRES_VIOLATION, ldv_destroy_msgsErr2REQUIRES_VIOLATION, ldv_destroy_msgsErr1REQUIRES_VIOLATION, ldv_msg_fillErr0REQUIRES_VIOLATION, ldv_msg_fillErr5REQUIRES_VIOLATION, ldv_msg_fillErr1REQUIRES_VIOLATION, ldv_msg_fillErr2REQUIRES_VIOLATION, ldv_msg_fillErr3REQUIRES_VIOLATION, ldv_msg_fillErr4REQUIRES_VIOLATION, ldv_atomic_add_returnErr0REQUIRES_VIOLATION, ldv_atomic_add_returnErr2REQUIRES_VIOLATION, ldv_atomic_add_returnErr1REQUIRES_VIOLATION, ldv_atomic_add_returnErr3REQUIRES_VIOLATION, __ldv_list_delErr3REQUIRES_VIOLATION, __ldv_list_delErr1REQUIRES_VIOLATION, __ldv_list_delErr2REQUIRES_VIOLATION, __ldv_list_delErr0REQUIRES_VIOLATION, ldv_kobject_cleanupErr3ASSERT_VIOLATIONMEMORY_FREE, ldv_kobject_cleanupErr2ASSERT_VIOLATIONMEMORY_FREE, ldv_kobject_cleanupErr4ASSERT_VIOLATIONMEMORY_FREE, ldv_kobject_cleanupErr0REQUIRES_VIOLATION, ldv_kobject_cleanupErr5ASSERT_VIOLATIONMEMORY_FREE, ldv_kobject_cleanupErr1REQUIRES_VIOLATION, ldv_msg_freeErr3ASSERT_VIOLATIONMEMORY_FREE, ldv_msg_freeErr5ASSERT_VIOLATIONMEMORY_FREE, ldv_msg_freeErr2ASSERT_VIOLATIONMEMORY_FREE, ldv_msg_freeErr4ASSERT_VIOLATIONMEMORY_FREE, ldv_msg_freeErr0REQUIRES_VIOLATION, ldv_msg_freeErr1REQUIRES_VIOLATION, mainErr0ENSURES_VIOLATIONMEMORY_LEAK, LDV_INIT_LIST_HEADErr1REQUIRES_VIOLATION, LDV_INIT_LIST_HEADErr2REQUIRES_VIOLATION, LDV_INIT_LIST_HEADErr0REQUIRES_VIOLATION, LDV_INIT_LIST_HEADErr3REQUIRES_VIOLATION, ldv_list_delErr0REQUIRES_VIOLATION, ldv_list_delErr2REQUIRES_VIOLATION, ldv_list_delErr1REQUIRES_VIOLATION, ldv_list_delErr3REQUIRES_VIOLATION, __ldv_list_addErr4REQUIRES_VIOLATION, __ldv_list_addErr3REQUIRES_VIOLATION, __ldv_list_addErr1REQUIRES_VIOLATION, __ldv_list_addErr2REQUIRES_VIOLATION, __ldv_list_addErr7REQUIRES_VIOLATION, __ldv_list_addErr0REQUIRES_VIOLATION, __ldv_list_addErr5REQUIRES_VIOLATION, __ldv_list_addErr6REQUIRES_VIOLATION, ldv_dev_set_drvdataErr1REQUIRES_VIOLATION, ldv_dev_set_drvdataErr0REQUIRES_VIOLATION, ldv_atomic_sub_returnErr0REQUIRES_VIOLATION, ldv_atomic_sub_returnErr2REQUIRES_VIOLATION, ldv_atomic_sub_returnErr1REQUIRES_VIOLATION, ldv_atomic_sub_returnErr3REQUIRES_VIOLATION, ldv_list_add_tailErr1REQUIRES_VIOLATION, ldv_list_add_tailErr0REQUIRES_VIOLATION, ldv_dev_get_drvdataErr0REQUIRES_VIOLATION, ldv_dev_get_drvdataErr1REQUIRES_VIOLATION, ldv_msg_allocErr1REQUIRES_VIOLATION, ldv_msg_allocErr0REQUIRES_VIOLATION]=== [2018-11-28 11:25:41,758 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-28 11:25:41,758 INFO L82 PathProgramCache]: Analyzing trace with hash -1036104256, now seen corresponding path program 1 times [2018-11-28 11:25:41,758 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-28 11:25:41,759 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-28 11:25:41,759 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 11:25:41,759 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-28 11:25:41,760 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 11:25:41,768 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-28 11:25:41,846 INFO L134 CoverageAnalysis]: Checked inductivity of 6 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 6 trivial. 0 not checked. [2018-11-28 11:25:41,846 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-28 11:25:41,846 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [10] imperfect sequences [] total 10 [2018-11-28 11:25:41,846 INFO L459 AbstractCegarLoop]: Interpolant automaton has 11 states [2018-11-28 11:25:41,847 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 11 interpolants. [2018-11-28 11:25:41,847 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=19, Invalid=91, Unknown=0, NotChecked=0, Total=110 [2018-11-28 11:25:41,847 INFO L87 Difference]: Start difference. First operand 138 states and 144 transitions. Second operand 11 states. [2018-11-28 11:25:42,064 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-28 11:25:42,065 INFO L93 Difference]: Finished difference Result 136 states and 142 transitions. [2018-11-28 11:25:42,065 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 11 states. [2018-11-28 11:25:42,065 INFO L78 Accepts]: Start accepts. Automaton has 11 states. Word has length 40 [2018-11-28 11:25:42,065 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-28 11:25:42,066 INFO L225 Difference]: With dead ends: 136 [2018-11-28 11:25:42,066 INFO L226 Difference]: Without dead ends: 136 [2018-11-28 11:25:42,066 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 13 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 12 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 3 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=31, Invalid=151, Unknown=0, NotChecked=0, Total=182 [2018-11-28 11:25:42,067 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 136 states. [2018-11-28 11:25:42,068 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 136 to 136. [2018-11-28 11:25:42,068 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 136 states. [2018-11-28 11:25:42,069 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 136 states to 136 states and 142 transitions. [2018-11-28 11:25:42,069 INFO L78 Accepts]: Start accepts. Automaton has 136 states and 142 transitions. Word has length 40 [2018-11-28 11:25:42,070 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-28 11:25:42,070 INFO L480 AbstractCegarLoop]: Abstraction has 136 states and 142 transitions. [2018-11-28 11:25:42,070 INFO L481 AbstractCegarLoop]: Interpolant automaton has 11 states. [2018-11-28 11:25:42,070 INFO L276 IsEmpty]: Start isEmpty. Operand 136 states and 142 transitions. [2018-11-28 11:25:42,073 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 41 [2018-11-28 11:25:42,073 INFO L394 BasicCegarLoop]: Found error trace [2018-11-28 11:25:42,073 INFO L402 BasicCegarLoop]: trace histogram [3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-28 11:25:42,073 INFO L423 AbstractCegarLoop]: === Iteration 13 === [ldv_kref_initErr1REQUIRES_VIOLATION, ldv_kref_initErr0REQUIRES_VIOLATION, ldv_list_addErr0REQUIRES_VIOLATION, ldv_list_addErr1REQUIRES_VIOLATION, ldv_kobject_createErr0REQUIRES_VIOLATION, ldv_kobject_createErr1REQUIRES_VIOLATION, ldv_destroy_msgsErr3REQUIRES_VIOLATION, ldv_destroy_msgsErr4REQUIRES_VIOLATION, ldv_destroy_msgsErr0REQUIRES_VIOLATION, ldv_destroy_msgsErr5REQUIRES_VIOLATION, ldv_destroy_msgsErr2REQUIRES_VIOLATION, ldv_destroy_msgsErr1REQUIRES_VIOLATION, ldv_msg_fillErr0REQUIRES_VIOLATION, ldv_msg_fillErr5REQUIRES_VIOLATION, ldv_msg_fillErr1REQUIRES_VIOLATION, ldv_msg_fillErr2REQUIRES_VIOLATION, ldv_msg_fillErr3REQUIRES_VIOLATION, ldv_msg_fillErr4REQUIRES_VIOLATION, ldv_atomic_add_returnErr0REQUIRES_VIOLATION, ldv_atomic_add_returnErr2REQUIRES_VIOLATION, ldv_atomic_add_returnErr1REQUIRES_VIOLATION, ldv_atomic_add_returnErr3REQUIRES_VIOLATION, __ldv_list_delErr3REQUIRES_VIOLATION, __ldv_list_delErr1REQUIRES_VIOLATION, __ldv_list_delErr2REQUIRES_VIOLATION, __ldv_list_delErr0REQUIRES_VIOLATION, ldv_kobject_cleanupErr3ASSERT_VIOLATIONMEMORY_FREE, ldv_kobject_cleanupErr2ASSERT_VIOLATIONMEMORY_FREE, ldv_kobject_cleanupErr4ASSERT_VIOLATIONMEMORY_FREE, ldv_kobject_cleanupErr0REQUIRES_VIOLATION, ldv_kobject_cleanupErr5ASSERT_VIOLATIONMEMORY_FREE, ldv_kobject_cleanupErr1REQUIRES_VIOLATION, ldv_msg_freeErr3ASSERT_VIOLATIONMEMORY_FREE, ldv_msg_freeErr5ASSERT_VIOLATIONMEMORY_FREE, ldv_msg_freeErr2ASSERT_VIOLATIONMEMORY_FREE, ldv_msg_freeErr4ASSERT_VIOLATIONMEMORY_FREE, ldv_msg_freeErr0REQUIRES_VIOLATION, ldv_msg_freeErr1REQUIRES_VIOLATION, mainErr0ENSURES_VIOLATIONMEMORY_LEAK, LDV_INIT_LIST_HEADErr1REQUIRES_VIOLATION, LDV_INIT_LIST_HEADErr2REQUIRES_VIOLATION, LDV_INIT_LIST_HEADErr0REQUIRES_VIOLATION, LDV_INIT_LIST_HEADErr3REQUIRES_VIOLATION, ldv_list_delErr0REQUIRES_VIOLATION, ldv_list_delErr2REQUIRES_VIOLATION, ldv_list_delErr1REQUIRES_VIOLATION, ldv_list_delErr3REQUIRES_VIOLATION, __ldv_list_addErr4REQUIRES_VIOLATION, __ldv_list_addErr3REQUIRES_VIOLATION, __ldv_list_addErr1REQUIRES_VIOLATION, __ldv_list_addErr2REQUIRES_VIOLATION, __ldv_list_addErr7REQUIRES_VIOLATION, __ldv_list_addErr0REQUIRES_VIOLATION, __ldv_list_addErr5REQUIRES_VIOLATION, __ldv_list_addErr6REQUIRES_VIOLATION, ldv_dev_set_drvdataErr1REQUIRES_VIOLATION, ldv_dev_set_drvdataErr0REQUIRES_VIOLATION, ldv_atomic_sub_returnErr0REQUIRES_VIOLATION, ldv_atomic_sub_returnErr2REQUIRES_VIOLATION, ldv_atomic_sub_returnErr1REQUIRES_VIOLATION, ldv_atomic_sub_returnErr3REQUIRES_VIOLATION, ldv_list_add_tailErr1REQUIRES_VIOLATION, ldv_list_add_tailErr0REQUIRES_VIOLATION, ldv_dev_get_drvdataErr0REQUIRES_VIOLATION, ldv_dev_get_drvdataErr1REQUIRES_VIOLATION, ldv_msg_allocErr1REQUIRES_VIOLATION, ldv_msg_allocErr0REQUIRES_VIOLATION]=== [2018-11-28 11:25:42,074 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-28 11:25:42,074 INFO L82 PathProgramCache]: Analyzing trace with hash -1036104255, now seen corresponding path program 1 times [2018-11-28 11:25:42,074 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-28 11:25:42,074 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-28 11:25:42,075 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 11:25:42,075 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-28 11:25:42,075 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 11:25:42,085 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-28 11:25:42,128 INFO L134 CoverageAnalysis]: Checked inductivity of 6 backedges. 0 proven. 6 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-28 11:25:42,128 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-28 11:25:42,128 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_2ca7a644-5b0a-4f3d-9179-f30a2c52dfce/bin-2019/uautomizer/z3 Starting monitored process 4 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 4 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-28 11:25:42,142 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-28 11:25:42,170 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-28 11:25:42,172 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-28 11:25:42,197 INFO L134 CoverageAnalysis]: Checked inductivity of 6 backedges. 0 proven. 6 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-28 11:25:42,222 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-11-28 11:25:42,222 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [7, 7] total 8 [2018-11-28 11:25:42,223 INFO L459 AbstractCegarLoop]: Interpolant automaton has 8 states [2018-11-28 11:25:42,223 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 8 interpolants. [2018-11-28 11:25:42,223 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=23, Invalid=33, Unknown=0, NotChecked=0, Total=56 [2018-11-28 11:25:42,223 INFO L87 Difference]: Start difference. First operand 136 states and 142 transitions. Second operand 8 states. [2018-11-28 11:25:42,244 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-28 11:25:42,244 INFO L93 Difference]: Finished difference Result 139 states and 145 transitions. [2018-11-28 11:25:42,245 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2018-11-28 11:25:42,245 INFO L78 Accepts]: Start accepts. Automaton has 8 states. Word has length 40 [2018-11-28 11:25:42,245 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-28 11:25:42,246 INFO L225 Difference]: With dead ends: 139 [2018-11-28 11:25:42,246 INFO L226 Difference]: Without dead ends: 137 [2018-11-28 11:25:42,246 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 47 GetRequests, 40 SyntacticMatches, 0 SemanticMatches, 7 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 8 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=27, Invalid=45, Unknown=0, NotChecked=0, Total=72 [2018-11-28 11:25:42,246 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 137 states. [2018-11-28 11:25:42,251 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 137 to 137. [2018-11-28 11:25:42,251 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 137 states. [2018-11-28 11:25:42,252 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 137 states to 137 states and 143 transitions. [2018-11-28 11:25:42,252 INFO L78 Accepts]: Start accepts. Automaton has 137 states and 143 transitions. Word has length 40 [2018-11-28 11:25:42,252 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-28 11:25:42,252 INFO L480 AbstractCegarLoop]: Abstraction has 137 states and 143 transitions. [2018-11-28 11:25:42,252 INFO L481 AbstractCegarLoop]: Interpolant automaton has 8 states. [2018-11-28 11:25:42,252 INFO L276 IsEmpty]: Start isEmpty. Operand 137 states and 143 transitions. [2018-11-28 11:25:42,253 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 42 [2018-11-28 11:25:42,253 INFO L394 BasicCegarLoop]: Found error trace [2018-11-28 11:25:42,253 INFO L402 BasicCegarLoop]: trace histogram [4, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-28 11:25:42,253 INFO L423 AbstractCegarLoop]: === Iteration 14 === [ldv_kref_initErr1REQUIRES_VIOLATION, ldv_kref_initErr0REQUIRES_VIOLATION, ldv_list_addErr0REQUIRES_VIOLATION, ldv_list_addErr1REQUIRES_VIOLATION, ldv_kobject_createErr0REQUIRES_VIOLATION, ldv_kobject_createErr1REQUIRES_VIOLATION, ldv_destroy_msgsErr3REQUIRES_VIOLATION, ldv_destroy_msgsErr4REQUIRES_VIOLATION, ldv_destroy_msgsErr0REQUIRES_VIOLATION, ldv_destroy_msgsErr5REQUIRES_VIOLATION, ldv_destroy_msgsErr2REQUIRES_VIOLATION, ldv_destroy_msgsErr1REQUIRES_VIOLATION, ldv_msg_fillErr0REQUIRES_VIOLATION, ldv_msg_fillErr5REQUIRES_VIOLATION, ldv_msg_fillErr1REQUIRES_VIOLATION, ldv_msg_fillErr2REQUIRES_VIOLATION, ldv_msg_fillErr3REQUIRES_VIOLATION, ldv_msg_fillErr4REQUIRES_VIOLATION, ldv_atomic_add_returnErr0REQUIRES_VIOLATION, ldv_atomic_add_returnErr2REQUIRES_VIOLATION, ldv_atomic_add_returnErr1REQUIRES_VIOLATION, ldv_atomic_add_returnErr3REQUIRES_VIOLATION, __ldv_list_delErr3REQUIRES_VIOLATION, __ldv_list_delErr1REQUIRES_VIOLATION, __ldv_list_delErr2REQUIRES_VIOLATION, __ldv_list_delErr0REQUIRES_VIOLATION, ldv_kobject_cleanupErr3ASSERT_VIOLATIONMEMORY_FREE, ldv_kobject_cleanupErr2ASSERT_VIOLATIONMEMORY_FREE, ldv_kobject_cleanupErr4ASSERT_VIOLATIONMEMORY_FREE, ldv_kobject_cleanupErr0REQUIRES_VIOLATION, ldv_kobject_cleanupErr5ASSERT_VIOLATIONMEMORY_FREE, ldv_kobject_cleanupErr1REQUIRES_VIOLATION, ldv_msg_freeErr3ASSERT_VIOLATIONMEMORY_FREE, ldv_msg_freeErr5ASSERT_VIOLATIONMEMORY_FREE, ldv_msg_freeErr2ASSERT_VIOLATIONMEMORY_FREE, ldv_msg_freeErr4ASSERT_VIOLATIONMEMORY_FREE, ldv_msg_freeErr0REQUIRES_VIOLATION, ldv_msg_freeErr1REQUIRES_VIOLATION, mainErr0ENSURES_VIOLATIONMEMORY_LEAK, LDV_INIT_LIST_HEADErr1REQUIRES_VIOLATION, LDV_INIT_LIST_HEADErr2REQUIRES_VIOLATION, LDV_INIT_LIST_HEADErr0REQUIRES_VIOLATION, LDV_INIT_LIST_HEADErr3REQUIRES_VIOLATION, ldv_list_delErr0REQUIRES_VIOLATION, ldv_list_delErr2REQUIRES_VIOLATION, ldv_list_delErr1REQUIRES_VIOLATION, ldv_list_delErr3REQUIRES_VIOLATION, __ldv_list_addErr4REQUIRES_VIOLATION, __ldv_list_addErr3REQUIRES_VIOLATION, __ldv_list_addErr1REQUIRES_VIOLATION, __ldv_list_addErr2REQUIRES_VIOLATION, __ldv_list_addErr7REQUIRES_VIOLATION, __ldv_list_addErr0REQUIRES_VIOLATION, __ldv_list_addErr5REQUIRES_VIOLATION, __ldv_list_addErr6REQUIRES_VIOLATION, ldv_dev_set_drvdataErr1REQUIRES_VIOLATION, ldv_dev_set_drvdataErr0REQUIRES_VIOLATION, ldv_atomic_sub_returnErr0REQUIRES_VIOLATION, ldv_atomic_sub_returnErr2REQUIRES_VIOLATION, ldv_atomic_sub_returnErr1REQUIRES_VIOLATION, ldv_atomic_sub_returnErr3REQUIRES_VIOLATION, ldv_list_add_tailErr1REQUIRES_VIOLATION, ldv_list_add_tailErr0REQUIRES_VIOLATION, ldv_dev_get_drvdataErr0REQUIRES_VIOLATION, ldv_dev_get_drvdataErr1REQUIRES_VIOLATION, ldv_msg_allocErr1REQUIRES_VIOLATION, ldv_msg_allocErr0REQUIRES_VIOLATION]=== [2018-11-28 11:25:42,253 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-28 11:25:42,253 INFO L82 PathProgramCache]: Analyzing trace with hash -141560532, now seen corresponding path program 2 times [2018-11-28 11:25:42,253 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-28 11:25:42,254 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-28 11:25:42,254 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 11:25:42,254 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-28 11:25:42,255 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 11:25:42,263 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-28 11:25:42,313 INFO L134 CoverageAnalysis]: Checked inductivity of 10 backedges. 0 proven. 10 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-28 11:25:42,314 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-28 11:25:42,314 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_2ca7a644-5b0a-4f3d-9179-f30a2c52dfce/bin-2019/uautomizer/z3 Starting monitored process 5 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 5 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-28 11:25:42,325 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-11-28 11:25:42,344 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) [2018-11-28 11:25:42,344 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-11-28 11:25:42,347 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-28 11:25:42,358 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 6 treesize of output 5 [2018-11-28 11:25:42,358 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-11-28 11:25:42,365 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-0 vars, 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-28 11:25:42,366 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 2 variables, input treesize:13, output treesize:9 [2018-11-28 11:25:42,504 INFO L134 CoverageAnalysis]: Checked inductivity of 10 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 10 trivial. 0 not checked. [2018-11-28 11:25:42,519 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 1 imperfect interpolant sequences. [2018-11-28 11:25:42,519 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [12] imperfect sequences [8] total 19 [2018-11-28 11:25:42,519 INFO L459 AbstractCegarLoop]: Interpolant automaton has 19 states [2018-11-28 11:25:42,519 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 19 interpolants. [2018-11-28 11:25:42,520 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=53, Invalid=289, Unknown=0, NotChecked=0, Total=342 [2018-11-28 11:25:42,520 INFO L87 Difference]: Start difference. First operand 137 states and 143 transitions. Second operand 19 states. [2018-11-28 11:25:42,950 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-28 11:25:42,950 INFO L93 Difference]: Finished difference Result 138 states and 144 transitions. [2018-11-28 11:25:42,950 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 19 states. [2018-11-28 11:25:42,950 INFO L78 Accepts]: Start accepts. Automaton has 19 states. Word has length 41 [2018-11-28 11:25:42,951 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-28 11:25:42,952 INFO L225 Difference]: With dead ends: 138 [2018-11-28 11:25:42,952 INFO L226 Difference]: Without dead ends: 136 [2018-11-28 11:25:42,952 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 58 GetRequests, 28 SyntacticMatches, 3 SemanticMatches, 27 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 123 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=118, Invalid=694, Unknown=0, NotChecked=0, Total=812 [2018-11-28 11:25:42,953 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 136 states. [2018-11-28 11:25:42,955 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 136 to 136. [2018-11-28 11:25:42,955 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 136 states. [2018-11-28 11:25:42,956 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 136 states to 136 states and 142 transitions. [2018-11-28 11:25:42,956 INFO L78 Accepts]: Start accepts. Automaton has 136 states and 142 transitions. Word has length 41 [2018-11-28 11:25:42,956 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-28 11:25:42,956 INFO L480 AbstractCegarLoop]: Abstraction has 136 states and 142 transitions. [2018-11-28 11:25:42,956 INFO L481 AbstractCegarLoop]: Interpolant automaton has 19 states. [2018-11-28 11:25:42,957 INFO L276 IsEmpty]: Start isEmpty. Operand 136 states and 142 transitions. [2018-11-28 11:25:42,957 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 46 [2018-11-28 11:25:42,957 INFO L394 BasicCegarLoop]: Found error trace [2018-11-28 11:25:42,957 INFO L402 BasicCegarLoop]: trace histogram [5, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-28 11:25:42,958 INFO L423 AbstractCegarLoop]: === Iteration 15 === [ldv_kref_initErr1REQUIRES_VIOLATION, ldv_kref_initErr0REQUIRES_VIOLATION, ldv_list_addErr0REQUIRES_VIOLATION, ldv_list_addErr1REQUIRES_VIOLATION, ldv_kobject_createErr0REQUIRES_VIOLATION, ldv_kobject_createErr1REQUIRES_VIOLATION, ldv_destroy_msgsErr3REQUIRES_VIOLATION, ldv_destroy_msgsErr4REQUIRES_VIOLATION, ldv_destroy_msgsErr0REQUIRES_VIOLATION, ldv_destroy_msgsErr5REQUIRES_VIOLATION, ldv_destroy_msgsErr2REQUIRES_VIOLATION, ldv_destroy_msgsErr1REQUIRES_VIOLATION, ldv_msg_fillErr0REQUIRES_VIOLATION, ldv_msg_fillErr5REQUIRES_VIOLATION, ldv_msg_fillErr1REQUIRES_VIOLATION, ldv_msg_fillErr2REQUIRES_VIOLATION, ldv_msg_fillErr3REQUIRES_VIOLATION, ldv_msg_fillErr4REQUIRES_VIOLATION, ldv_atomic_add_returnErr0REQUIRES_VIOLATION, ldv_atomic_add_returnErr2REQUIRES_VIOLATION, ldv_atomic_add_returnErr1REQUIRES_VIOLATION, ldv_atomic_add_returnErr3REQUIRES_VIOLATION, __ldv_list_delErr3REQUIRES_VIOLATION, __ldv_list_delErr1REQUIRES_VIOLATION, __ldv_list_delErr2REQUIRES_VIOLATION, __ldv_list_delErr0REQUIRES_VIOLATION, ldv_kobject_cleanupErr3ASSERT_VIOLATIONMEMORY_FREE, ldv_kobject_cleanupErr2ASSERT_VIOLATIONMEMORY_FREE, ldv_kobject_cleanupErr4ASSERT_VIOLATIONMEMORY_FREE, ldv_kobject_cleanupErr0REQUIRES_VIOLATION, ldv_kobject_cleanupErr5ASSERT_VIOLATIONMEMORY_FREE, ldv_kobject_cleanupErr1REQUIRES_VIOLATION, ldv_msg_freeErr3ASSERT_VIOLATIONMEMORY_FREE, ldv_msg_freeErr5ASSERT_VIOLATIONMEMORY_FREE, ldv_msg_freeErr2ASSERT_VIOLATIONMEMORY_FREE, ldv_msg_freeErr4ASSERT_VIOLATIONMEMORY_FREE, ldv_msg_freeErr0REQUIRES_VIOLATION, ldv_msg_freeErr1REQUIRES_VIOLATION, mainErr0ENSURES_VIOLATIONMEMORY_LEAK, LDV_INIT_LIST_HEADErr1REQUIRES_VIOLATION, LDV_INIT_LIST_HEADErr2REQUIRES_VIOLATION, LDV_INIT_LIST_HEADErr0REQUIRES_VIOLATION, LDV_INIT_LIST_HEADErr3REQUIRES_VIOLATION, ldv_list_delErr0REQUIRES_VIOLATION, ldv_list_delErr2REQUIRES_VIOLATION, ldv_list_delErr1REQUIRES_VIOLATION, ldv_list_delErr3REQUIRES_VIOLATION, __ldv_list_addErr4REQUIRES_VIOLATION, __ldv_list_addErr3REQUIRES_VIOLATION, __ldv_list_addErr1REQUIRES_VIOLATION, __ldv_list_addErr2REQUIRES_VIOLATION, __ldv_list_addErr7REQUIRES_VIOLATION, __ldv_list_addErr0REQUIRES_VIOLATION, __ldv_list_addErr5REQUIRES_VIOLATION, __ldv_list_addErr6REQUIRES_VIOLATION, ldv_dev_set_drvdataErr1REQUIRES_VIOLATION, ldv_dev_set_drvdataErr0REQUIRES_VIOLATION, ldv_atomic_sub_returnErr0REQUIRES_VIOLATION, ldv_atomic_sub_returnErr2REQUIRES_VIOLATION, ldv_atomic_sub_returnErr1REQUIRES_VIOLATION, ldv_atomic_sub_returnErr3REQUIRES_VIOLATION, ldv_list_add_tailErr1REQUIRES_VIOLATION, ldv_list_add_tailErr0REQUIRES_VIOLATION, ldv_dev_get_drvdataErr0REQUIRES_VIOLATION, ldv_dev_get_drvdataErr1REQUIRES_VIOLATION, ldv_msg_allocErr1REQUIRES_VIOLATION, ldv_msg_allocErr0REQUIRES_VIOLATION]=== [2018-11-28 11:25:42,958 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-28 11:25:42,958 INFO L82 PathProgramCache]: Analyzing trace with hash -271503917, now seen corresponding path program 1 times [2018-11-28 11:25:42,958 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-28 11:25:42,958 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-28 11:25:42,963 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 11:25:42,963 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-28 11:25:42,964 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 11:25:42,972 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-28 11:25:43,010 INFO L134 CoverageAnalysis]: Checked inductivity of 15 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 15 trivial. 0 not checked. [2018-11-28 11:25:43,010 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-28 11:25:43,010 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [7] imperfect sequences [] total 7 [2018-11-28 11:25:43,010 INFO L459 AbstractCegarLoop]: Interpolant automaton has 7 states [2018-11-28 11:25:43,011 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2018-11-28 11:25:43,011 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=11, Invalid=31, Unknown=0, NotChecked=0, Total=42 [2018-11-28 11:25:43,011 INFO L87 Difference]: Start difference. First operand 136 states and 142 transitions. Second operand 7 states. [2018-11-28 11:25:43,037 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-28 11:25:43,037 INFO L93 Difference]: Finished difference Result 138 states and 143 transitions. [2018-11-28 11:25:43,039 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2018-11-28 11:25:43,039 INFO L78 Accepts]: Start accepts. Automaton has 7 states. Word has length 45 [2018-11-28 11:25:43,039 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-28 11:25:43,040 INFO L225 Difference]: With dead ends: 138 [2018-11-28 11:25:43,040 INFO L226 Difference]: Without dead ends: 136 [2018-11-28 11:25:43,040 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 8 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 6 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=15, Invalid=41, Unknown=0, NotChecked=0, Total=56 [2018-11-28 11:25:43,041 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 136 states. [2018-11-28 11:25:43,043 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 136 to 136. [2018-11-28 11:25:43,043 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 136 states. [2018-11-28 11:25:43,044 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 136 states to 136 states and 141 transitions. [2018-11-28 11:25:43,044 INFO L78 Accepts]: Start accepts. Automaton has 136 states and 141 transitions. Word has length 45 [2018-11-28 11:25:43,044 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-28 11:25:43,044 INFO L480 AbstractCegarLoop]: Abstraction has 136 states and 141 transitions. [2018-11-28 11:25:43,044 INFO L481 AbstractCegarLoop]: Interpolant automaton has 7 states. [2018-11-28 11:25:43,044 INFO L276 IsEmpty]: Start isEmpty. Operand 136 states and 141 transitions. [2018-11-28 11:25:43,045 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 51 [2018-11-28 11:25:43,045 INFO L394 BasicCegarLoop]: Found error trace [2018-11-28 11:25:43,045 INFO L402 BasicCegarLoop]: trace histogram [5, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-28 11:25:43,045 INFO L423 AbstractCegarLoop]: === Iteration 16 === [ldv_kref_initErr1REQUIRES_VIOLATION, ldv_kref_initErr0REQUIRES_VIOLATION, ldv_list_addErr0REQUIRES_VIOLATION, ldv_list_addErr1REQUIRES_VIOLATION, ldv_kobject_createErr0REQUIRES_VIOLATION, ldv_kobject_createErr1REQUIRES_VIOLATION, ldv_destroy_msgsErr3REQUIRES_VIOLATION, ldv_destroy_msgsErr4REQUIRES_VIOLATION, ldv_destroy_msgsErr0REQUIRES_VIOLATION, ldv_destroy_msgsErr5REQUIRES_VIOLATION, ldv_destroy_msgsErr2REQUIRES_VIOLATION, ldv_destroy_msgsErr1REQUIRES_VIOLATION, ldv_msg_fillErr0REQUIRES_VIOLATION, ldv_msg_fillErr5REQUIRES_VIOLATION, ldv_msg_fillErr1REQUIRES_VIOLATION, ldv_msg_fillErr2REQUIRES_VIOLATION, ldv_msg_fillErr3REQUIRES_VIOLATION, ldv_msg_fillErr4REQUIRES_VIOLATION, ldv_atomic_add_returnErr0REQUIRES_VIOLATION, ldv_atomic_add_returnErr2REQUIRES_VIOLATION, ldv_atomic_add_returnErr1REQUIRES_VIOLATION, ldv_atomic_add_returnErr3REQUIRES_VIOLATION, __ldv_list_delErr3REQUIRES_VIOLATION, __ldv_list_delErr1REQUIRES_VIOLATION, __ldv_list_delErr2REQUIRES_VIOLATION, __ldv_list_delErr0REQUIRES_VIOLATION, ldv_kobject_cleanupErr3ASSERT_VIOLATIONMEMORY_FREE, ldv_kobject_cleanupErr2ASSERT_VIOLATIONMEMORY_FREE, ldv_kobject_cleanupErr4ASSERT_VIOLATIONMEMORY_FREE, ldv_kobject_cleanupErr0REQUIRES_VIOLATION, ldv_kobject_cleanupErr5ASSERT_VIOLATIONMEMORY_FREE, ldv_kobject_cleanupErr1REQUIRES_VIOLATION, ldv_msg_freeErr3ASSERT_VIOLATIONMEMORY_FREE, ldv_msg_freeErr5ASSERT_VIOLATIONMEMORY_FREE, ldv_msg_freeErr2ASSERT_VIOLATIONMEMORY_FREE, ldv_msg_freeErr4ASSERT_VIOLATIONMEMORY_FREE, ldv_msg_freeErr0REQUIRES_VIOLATION, ldv_msg_freeErr1REQUIRES_VIOLATION, mainErr0ENSURES_VIOLATIONMEMORY_LEAK, LDV_INIT_LIST_HEADErr1REQUIRES_VIOLATION, LDV_INIT_LIST_HEADErr2REQUIRES_VIOLATION, LDV_INIT_LIST_HEADErr0REQUIRES_VIOLATION, LDV_INIT_LIST_HEADErr3REQUIRES_VIOLATION, ldv_list_delErr0REQUIRES_VIOLATION, ldv_list_delErr2REQUIRES_VIOLATION, ldv_list_delErr1REQUIRES_VIOLATION, ldv_list_delErr3REQUIRES_VIOLATION, __ldv_list_addErr4REQUIRES_VIOLATION, __ldv_list_addErr3REQUIRES_VIOLATION, __ldv_list_addErr1REQUIRES_VIOLATION, __ldv_list_addErr2REQUIRES_VIOLATION, __ldv_list_addErr7REQUIRES_VIOLATION, __ldv_list_addErr0REQUIRES_VIOLATION, __ldv_list_addErr5REQUIRES_VIOLATION, __ldv_list_addErr6REQUIRES_VIOLATION, ldv_dev_set_drvdataErr1REQUIRES_VIOLATION, ldv_dev_set_drvdataErr0REQUIRES_VIOLATION, ldv_atomic_sub_returnErr0REQUIRES_VIOLATION, ldv_atomic_sub_returnErr2REQUIRES_VIOLATION, ldv_atomic_sub_returnErr1REQUIRES_VIOLATION, ldv_atomic_sub_returnErr3REQUIRES_VIOLATION, ldv_list_add_tailErr1REQUIRES_VIOLATION, ldv_list_add_tailErr0REQUIRES_VIOLATION, ldv_dev_get_drvdataErr0REQUIRES_VIOLATION, ldv_dev_get_drvdataErr1REQUIRES_VIOLATION, ldv_msg_allocErr1REQUIRES_VIOLATION, ldv_msg_allocErr0REQUIRES_VIOLATION]=== [2018-11-28 11:25:43,046 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-28 11:25:43,046 INFO L82 PathProgramCache]: Analyzing trace with hash 865251330, now seen corresponding path program 1 times [2018-11-28 11:25:43,046 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-28 11:25:43,046 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-28 11:25:43,047 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 11:25:43,047 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-28 11:25:43,047 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 11:25:43,061 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-28 11:25:43,116 INFO L134 CoverageAnalysis]: Checked inductivity of 15 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 15 trivial. 0 not checked. [2018-11-28 11:25:43,116 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-28 11:25:43,116 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [9] imperfect sequences [] total 9 [2018-11-28 11:25:43,116 INFO L459 AbstractCegarLoop]: Interpolant automaton has 9 states [2018-11-28 11:25:43,117 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 9 interpolants. [2018-11-28 11:25:43,117 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=15, Invalid=57, Unknown=0, NotChecked=0, Total=72 [2018-11-28 11:25:43,117 INFO L87 Difference]: Start difference. First operand 136 states and 141 transitions. Second operand 9 states. [2018-11-28 11:25:43,152 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-28 11:25:43,153 INFO L93 Difference]: Finished difference Result 140 states and 144 transitions. [2018-11-28 11:25:43,153 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2018-11-28 11:25:43,154 INFO L78 Accepts]: Start accepts. Automaton has 9 states. Word has length 50 [2018-11-28 11:25:43,154 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-28 11:25:43,154 INFO L225 Difference]: With dead ends: 140 [2018-11-28 11:25:43,155 INFO L226 Difference]: Without dead ends: 136 [2018-11-28 11:25:43,155 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 11 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 9 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=23, Invalid=87, Unknown=0, NotChecked=0, Total=110 [2018-11-28 11:25:43,155 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 136 states. [2018-11-28 11:25:43,157 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 136 to 136. [2018-11-28 11:25:43,157 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 136 states. [2018-11-28 11:25:43,158 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 136 states to 136 states and 140 transitions. [2018-11-28 11:25:43,158 INFO L78 Accepts]: Start accepts. Automaton has 136 states and 140 transitions. Word has length 50 [2018-11-28 11:25:43,158 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-28 11:25:43,158 INFO L480 AbstractCegarLoop]: Abstraction has 136 states and 140 transitions. [2018-11-28 11:25:43,158 INFO L481 AbstractCegarLoop]: Interpolant automaton has 9 states. [2018-11-28 11:25:43,158 INFO L276 IsEmpty]: Start isEmpty. Operand 136 states and 140 transitions. [2018-11-28 11:25:43,159 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 62 [2018-11-28 11:25:43,159 INFO L394 BasicCegarLoop]: Found error trace [2018-11-28 11:25:43,159 INFO L402 BasicCegarLoop]: trace histogram [5, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-28 11:25:43,159 INFO L423 AbstractCegarLoop]: === Iteration 17 === [ldv_kref_initErr1REQUIRES_VIOLATION, ldv_kref_initErr0REQUIRES_VIOLATION, ldv_list_addErr0REQUIRES_VIOLATION, ldv_list_addErr1REQUIRES_VIOLATION, ldv_kobject_createErr0REQUIRES_VIOLATION, ldv_kobject_createErr1REQUIRES_VIOLATION, ldv_destroy_msgsErr3REQUIRES_VIOLATION, ldv_destroy_msgsErr4REQUIRES_VIOLATION, ldv_destroy_msgsErr0REQUIRES_VIOLATION, ldv_destroy_msgsErr5REQUIRES_VIOLATION, ldv_destroy_msgsErr2REQUIRES_VIOLATION, ldv_destroy_msgsErr1REQUIRES_VIOLATION, ldv_msg_fillErr0REQUIRES_VIOLATION, ldv_msg_fillErr5REQUIRES_VIOLATION, ldv_msg_fillErr1REQUIRES_VIOLATION, ldv_msg_fillErr2REQUIRES_VIOLATION, ldv_msg_fillErr3REQUIRES_VIOLATION, ldv_msg_fillErr4REQUIRES_VIOLATION, ldv_atomic_add_returnErr0REQUIRES_VIOLATION, ldv_atomic_add_returnErr2REQUIRES_VIOLATION, ldv_atomic_add_returnErr1REQUIRES_VIOLATION, ldv_atomic_add_returnErr3REQUIRES_VIOLATION, __ldv_list_delErr3REQUIRES_VIOLATION, __ldv_list_delErr1REQUIRES_VIOLATION, __ldv_list_delErr2REQUIRES_VIOLATION, __ldv_list_delErr0REQUIRES_VIOLATION, ldv_kobject_cleanupErr3ASSERT_VIOLATIONMEMORY_FREE, ldv_kobject_cleanupErr2ASSERT_VIOLATIONMEMORY_FREE, ldv_kobject_cleanupErr4ASSERT_VIOLATIONMEMORY_FREE, ldv_kobject_cleanupErr0REQUIRES_VIOLATION, ldv_kobject_cleanupErr5ASSERT_VIOLATIONMEMORY_FREE, ldv_kobject_cleanupErr1REQUIRES_VIOLATION, ldv_msg_freeErr3ASSERT_VIOLATIONMEMORY_FREE, ldv_msg_freeErr5ASSERT_VIOLATIONMEMORY_FREE, ldv_msg_freeErr2ASSERT_VIOLATIONMEMORY_FREE, ldv_msg_freeErr4ASSERT_VIOLATIONMEMORY_FREE, ldv_msg_freeErr0REQUIRES_VIOLATION, ldv_msg_freeErr1REQUIRES_VIOLATION, mainErr0ENSURES_VIOLATIONMEMORY_LEAK, LDV_INIT_LIST_HEADErr1REQUIRES_VIOLATION, LDV_INIT_LIST_HEADErr2REQUIRES_VIOLATION, LDV_INIT_LIST_HEADErr0REQUIRES_VIOLATION, LDV_INIT_LIST_HEADErr3REQUIRES_VIOLATION, ldv_list_delErr0REQUIRES_VIOLATION, ldv_list_delErr2REQUIRES_VIOLATION, ldv_list_delErr1REQUIRES_VIOLATION, ldv_list_delErr3REQUIRES_VIOLATION, __ldv_list_addErr4REQUIRES_VIOLATION, __ldv_list_addErr3REQUIRES_VIOLATION, __ldv_list_addErr1REQUIRES_VIOLATION, __ldv_list_addErr2REQUIRES_VIOLATION, __ldv_list_addErr7REQUIRES_VIOLATION, __ldv_list_addErr0REQUIRES_VIOLATION, __ldv_list_addErr5REQUIRES_VIOLATION, __ldv_list_addErr6REQUIRES_VIOLATION, ldv_dev_set_drvdataErr1REQUIRES_VIOLATION, ldv_dev_set_drvdataErr0REQUIRES_VIOLATION, ldv_atomic_sub_returnErr0REQUIRES_VIOLATION, ldv_atomic_sub_returnErr2REQUIRES_VIOLATION, ldv_atomic_sub_returnErr1REQUIRES_VIOLATION, ldv_atomic_sub_returnErr3REQUIRES_VIOLATION, ldv_list_add_tailErr1REQUIRES_VIOLATION, ldv_list_add_tailErr0REQUIRES_VIOLATION, ldv_dev_get_drvdataErr0REQUIRES_VIOLATION, ldv_dev_get_drvdataErr1REQUIRES_VIOLATION, ldv_msg_allocErr1REQUIRES_VIOLATION, ldv_msg_allocErr0REQUIRES_VIOLATION]=== [2018-11-28 11:25:43,160 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-28 11:25:43,160 INFO L82 PathProgramCache]: Analyzing trace with hash 1664444297, now seen corresponding path program 1 times [2018-11-28 11:25:43,160 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-28 11:25:43,160 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-28 11:25:43,164 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 11:25:43,164 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-28 11:25:43,164 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 11:25:43,173 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-28 11:25:43,256 INFO L134 CoverageAnalysis]: Checked inductivity of 15 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 15 trivial. 0 not checked. [2018-11-28 11:25:43,256 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-28 11:25:43,257 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [13] imperfect sequences [] total 13 [2018-11-28 11:25:43,257 INFO L459 AbstractCegarLoop]: Interpolant automaton has 14 states [2018-11-28 11:25:43,257 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 14 interpolants. [2018-11-28 11:25:43,257 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=25, Invalid=157, Unknown=0, NotChecked=0, Total=182 [2018-11-28 11:25:43,257 INFO L87 Difference]: Start difference. First operand 136 states and 140 transitions. Second operand 14 states. [2018-11-28 11:25:43,482 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-28 11:25:43,482 INFO L93 Difference]: Finished difference Result 134 states and 138 transitions. [2018-11-28 11:25:43,482 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 14 states. [2018-11-28 11:25:43,483 INFO L78 Accepts]: Start accepts. Automaton has 14 states. Word has length 61 [2018-11-28 11:25:43,483 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-28 11:25:43,483 INFO L225 Difference]: With dead ends: 134 [2018-11-28 11:25:43,483 INFO L226 Difference]: Without dead ends: 134 [2018-11-28 11:25:43,484 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 17 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 16 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 6 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=41, Invalid=265, Unknown=0, NotChecked=0, Total=306 [2018-11-28 11:25:43,484 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 134 states. [2018-11-28 11:25:43,486 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 134 to 134. [2018-11-28 11:25:43,486 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 134 states. [2018-11-28 11:25:43,486 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 134 states to 134 states and 138 transitions. [2018-11-28 11:25:43,487 INFO L78 Accepts]: Start accepts. Automaton has 134 states and 138 transitions. Word has length 61 [2018-11-28 11:25:43,487 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-28 11:25:43,487 INFO L480 AbstractCegarLoop]: Abstraction has 134 states and 138 transitions. [2018-11-28 11:25:43,487 INFO L481 AbstractCegarLoop]: Interpolant automaton has 14 states. [2018-11-28 11:25:43,487 INFO L276 IsEmpty]: Start isEmpty. Operand 134 states and 138 transitions. [2018-11-28 11:25:43,488 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 62 [2018-11-28 11:25:43,489 INFO L394 BasicCegarLoop]: Found error trace [2018-11-28 11:25:43,489 INFO L402 BasicCegarLoop]: trace histogram [5, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-28 11:25:43,489 INFO L423 AbstractCegarLoop]: === Iteration 18 === [ldv_kref_initErr1REQUIRES_VIOLATION, ldv_kref_initErr0REQUIRES_VIOLATION, ldv_list_addErr0REQUIRES_VIOLATION, ldv_list_addErr1REQUIRES_VIOLATION, ldv_kobject_createErr0REQUIRES_VIOLATION, ldv_kobject_createErr1REQUIRES_VIOLATION, ldv_destroy_msgsErr3REQUIRES_VIOLATION, ldv_destroy_msgsErr4REQUIRES_VIOLATION, ldv_destroy_msgsErr0REQUIRES_VIOLATION, ldv_destroy_msgsErr5REQUIRES_VIOLATION, ldv_destroy_msgsErr2REQUIRES_VIOLATION, ldv_destroy_msgsErr1REQUIRES_VIOLATION, ldv_msg_fillErr0REQUIRES_VIOLATION, ldv_msg_fillErr5REQUIRES_VIOLATION, ldv_msg_fillErr1REQUIRES_VIOLATION, ldv_msg_fillErr2REQUIRES_VIOLATION, ldv_msg_fillErr3REQUIRES_VIOLATION, ldv_msg_fillErr4REQUIRES_VIOLATION, ldv_atomic_add_returnErr0REQUIRES_VIOLATION, ldv_atomic_add_returnErr2REQUIRES_VIOLATION, ldv_atomic_add_returnErr1REQUIRES_VIOLATION, ldv_atomic_add_returnErr3REQUIRES_VIOLATION, __ldv_list_delErr3REQUIRES_VIOLATION, __ldv_list_delErr1REQUIRES_VIOLATION, __ldv_list_delErr2REQUIRES_VIOLATION, __ldv_list_delErr0REQUIRES_VIOLATION, ldv_kobject_cleanupErr3ASSERT_VIOLATIONMEMORY_FREE, ldv_kobject_cleanupErr2ASSERT_VIOLATIONMEMORY_FREE, ldv_kobject_cleanupErr4ASSERT_VIOLATIONMEMORY_FREE, ldv_kobject_cleanupErr0REQUIRES_VIOLATION, ldv_kobject_cleanupErr5ASSERT_VIOLATIONMEMORY_FREE, ldv_kobject_cleanupErr1REQUIRES_VIOLATION, ldv_msg_freeErr3ASSERT_VIOLATIONMEMORY_FREE, ldv_msg_freeErr5ASSERT_VIOLATIONMEMORY_FREE, ldv_msg_freeErr2ASSERT_VIOLATIONMEMORY_FREE, ldv_msg_freeErr4ASSERT_VIOLATIONMEMORY_FREE, ldv_msg_freeErr0REQUIRES_VIOLATION, ldv_msg_freeErr1REQUIRES_VIOLATION, mainErr0ENSURES_VIOLATIONMEMORY_LEAK, LDV_INIT_LIST_HEADErr1REQUIRES_VIOLATION, LDV_INIT_LIST_HEADErr2REQUIRES_VIOLATION, LDV_INIT_LIST_HEADErr0REQUIRES_VIOLATION, LDV_INIT_LIST_HEADErr3REQUIRES_VIOLATION, ldv_list_delErr0REQUIRES_VIOLATION, ldv_list_delErr2REQUIRES_VIOLATION, ldv_list_delErr1REQUIRES_VIOLATION, ldv_list_delErr3REQUIRES_VIOLATION, __ldv_list_addErr4REQUIRES_VIOLATION, __ldv_list_addErr3REQUIRES_VIOLATION, __ldv_list_addErr1REQUIRES_VIOLATION, __ldv_list_addErr2REQUIRES_VIOLATION, __ldv_list_addErr7REQUIRES_VIOLATION, __ldv_list_addErr0REQUIRES_VIOLATION, __ldv_list_addErr5REQUIRES_VIOLATION, __ldv_list_addErr6REQUIRES_VIOLATION, ldv_dev_set_drvdataErr1REQUIRES_VIOLATION, ldv_dev_set_drvdataErr0REQUIRES_VIOLATION, ldv_atomic_sub_returnErr0REQUIRES_VIOLATION, ldv_atomic_sub_returnErr2REQUIRES_VIOLATION, ldv_atomic_sub_returnErr1REQUIRES_VIOLATION, ldv_atomic_sub_returnErr3REQUIRES_VIOLATION, ldv_list_add_tailErr1REQUIRES_VIOLATION, ldv_list_add_tailErr0REQUIRES_VIOLATION, ldv_dev_get_drvdataErr0REQUIRES_VIOLATION, ldv_dev_get_drvdataErr1REQUIRES_VIOLATION, ldv_msg_allocErr1REQUIRES_VIOLATION, ldv_msg_allocErr0REQUIRES_VIOLATION]=== [2018-11-28 11:25:43,489 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-28 11:25:43,489 INFO L82 PathProgramCache]: Analyzing trace with hash 1664444298, now seen corresponding path program 1 times [2018-11-28 11:25:43,489 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-28 11:25:43,490 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-28 11:25:43,491 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 11:25:43,491 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-28 11:25:43,491 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 11:25:43,502 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-28 11:25:43,550 INFO L134 CoverageAnalysis]: Checked inductivity of 15 backedges. 0 proven. 15 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-28 11:25:43,550 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-28 11:25:43,550 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_2ca7a644-5b0a-4f3d-9179-f30a2c52dfce/bin-2019/uautomizer/z3 Starting monitored process 6 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 6 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-28 11:25:43,563 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-28 11:25:43,589 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-28 11:25:43,592 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-28 11:25:43,605 INFO L134 CoverageAnalysis]: Checked inductivity of 15 backedges. 0 proven. 15 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-28 11:25:43,620 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-11-28 11:25:43,620 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [9, 9] total 10 [2018-11-28 11:25:43,621 INFO L459 AbstractCegarLoop]: Interpolant automaton has 10 states [2018-11-28 11:25:43,621 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 10 interpolants. [2018-11-28 11:25:43,621 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=38, Invalid=52, Unknown=0, NotChecked=0, Total=90 [2018-11-28 11:25:43,621 INFO L87 Difference]: Start difference. First operand 134 states and 138 transitions. Second operand 10 states. [2018-11-28 11:25:43,650 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-28 11:25:43,651 INFO L93 Difference]: Finished difference Result 137 states and 141 transitions. [2018-11-28 11:25:43,651 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2018-11-28 11:25:43,651 INFO L78 Accepts]: Start accepts. Automaton has 10 states. Word has length 61 [2018-11-28 11:25:43,651 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-28 11:25:43,652 INFO L225 Difference]: With dead ends: 137 [2018-11-28 11:25:43,652 INFO L226 Difference]: Without dead ends: 135 [2018-11-28 11:25:43,652 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 70 GetRequests, 61 SyntacticMatches, 0 SemanticMatches, 9 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 14 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=42, Invalid=68, Unknown=0, NotChecked=0, Total=110 [2018-11-28 11:25:43,652 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 135 states. [2018-11-28 11:25:43,654 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 135 to 135. [2018-11-28 11:25:43,654 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 135 states. [2018-11-28 11:25:43,655 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 135 states to 135 states and 139 transitions. [2018-11-28 11:25:43,655 INFO L78 Accepts]: Start accepts. Automaton has 135 states and 139 transitions. Word has length 61 [2018-11-28 11:25:43,655 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-28 11:25:43,655 INFO L480 AbstractCegarLoop]: Abstraction has 135 states and 139 transitions. [2018-11-28 11:25:43,655 INFO L481 AbstractCegarLoop]: Interpolant automaton has 10 states. [2018-11-28 11:25:43,655 INFO L276 IsEmpty]: Start isEmpty. Operand 135 states and 139 transitions. [2018-11-28 11:25:43,656 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 63 [2018-11-28 11:25:43,656 INFO L394 BasicCegarLoop]: Found error trace [2018-11-28 11:25:43,656 INFO L402 BasicCegarLoop]: trace histogram [6, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-28 11:25:43,656 INFO L423 AbstractCegarLoop]: === Iteration 19 === [ldv_kref_initErr1REQUIRES_VIOLATION, ldv_kref_initErr0REQUIRES_VIOLATION, ldv_list_addErr0REQUIRES_VIOLATION, ldv_list_addErr1REQUIRES_VIOLATION, ldv_kobject_createErr0REQUIRES_VIOLATION, ldv_kobject_createErr1REQUIRES_VIOLATION, ldv_destroy_msgsErr3REQUIRES_VIOLATION, ldv_destroy_msgsErr4REQUIRES_VIOLATION, ldv_destroy_msgsErr0REQUIRES_VIOLATION, ldv_destroy_msgsErr5REQUIRES_VIOLATION, ldv_destroy_msgsErr2REQUIRES_VIOLATION, ldv_destroy_msgsErr1REQUIRES_VIOLATION, ldv_msg_fillErr0REQUIRES_VIOLATION, ldv_msg_fillErr5REQUIRES_VIOLATION, ldv_msg_fillErr1REQUIRES_VIOLATION, ldv_msg_fillErr2REQUIRES_VIOLATION, ldv_msg_fillErr3REQUIRES_VIOLATION, ldv_msg_fillErr4REQUIRES_VIOLATION, ldv_atomic_add_returnErr0REQUIRES_VIOLATION, ldv_atomic_add_returnErr2REQUIRES_VIOLATION, ldv_atomic_add_returnErr1REQUIRES_VIOLATION, ldv_atomic_add_returnErr3REQUIRES_VIOLATION, __ldv_list_delErr3REQUIRES_VIOLATION, __ldv_list_delErr1REQUIRES_VIOLATION, __ldv_list_delErr2REQUIRES_VIOLATION, __ldv_list_delErr0REQUIRES_VIOLATION, ldv_kobject_cleanupErr3ASSERT_VIOLATIONMEMORY_FREE, ldv_kobject_cleanupErr2ASSERT_VIOLATIONMEMORY_FREE, ldv_kobject_cleanupErr4ASSERT_VIOLATIONMEMORY_FREE, ldv_kobject_cleanupErr0REQUIRES_VIOLATION, ldv_kobject_cleanupErr5ASSERT_VIOLATIONMEMORY_FREE, ldv_kobject_cleanupErr1REQUIRES_VIOLATION, ldv_msg_freeErr3ASSERT_VIOLATIONMEMORY_FREE, ldv_msg_freeErr5ASSERT_VIOLATIONMEMORY_FREE, ldv_msg_freeErr2ASSERT_VIOLATIONMEMORY_FREE, ldv_msg_freeErr4ASSERT_VIOLATIONMEMORY_FREE, ldv_msg_freeErr0REQUIRES_VIOLATION, ldv_msg_freeErr1REQUIRES_VIOLATION, mainErr0ENSURES_VIOLATIONMEMORY_LEAK, LDV_INIT_LIST_HEADErr1REQUIRES_VIOLATION, LDV_INIT_LIST_HEADErr2REQUIRES_VIOLATION, LDV_INIT_LIST_HEADErr0REQUIRES_VIOLATION, LDV_INIT_LIST_HEADErr3REQUIRES_VIOLATION, ldv_list_delErr0REQUIRES_VIOLATION, ldv_list_delErr2REQUIRES_VIOLATION, ldv_list_delErr1REQUIRES_VIOLATION, ldv_list_delErr3REQUIRES_VIOLATION, __ldv_list_addErr4REQUIRES_VIOLATION, __ldv_list_addErr3REQUIRES_VIOLATION, __ldv_list_addErr1REQUIRES_VIOLATION, __ldv_list_addErr2REQUIRES_VIOLATION, __ldv_list_addErr7REQUIRES_VIOLATION, __ldv_list_addErr0REQUIRES_VIOLATION, __ldv_list_addErr5REQUIRES_VIOLATION, __ldv_list_addErr6REQUIRES_VIOLATION, ldv_dev_set_drvdataErr1REQUIRES_VIOLATION, ldv_dev_set_drvdataErr0REQUIRES_VIOLATION, ldv_atomic_sub_returnErr0REQUIRES_VIOLATION, ldv_atomic_sub_returnErr2REQUIRES_VIOLATION, ldv_atomic_sub_returnErr1REQUIRES_VIOLATION, ldv_atomic_sub_returnErr3REQUIRES_VIOLATION, ldv_list_add_tailErr1REQUIRES_VIOLATION, ldv_list_add_tailErr0REQUIRES_VIOLATION, ldv_dev_get_drvdataErr0REQUIRES_VIOLATION, ldv_dev_get_drvdataErr1REQUIRES_VIOLATION, ldv_msg_allocErr1REQUIRES_VIOLATION, ldv_msg_allocErr0REQUIRES_VIOLATION]=== [2018-11-28 11:25:43,656 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-28 11:25:43,657 INFO L82 PathProgramCache]: Analyzing trace with hash -785964801, now seen corresponding path program 2 times [2018-11-28 11:25:43,657 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-28 11:25:43,657 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-28 11:25:43,657 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 11:25:43,658 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-28 11:25:43,658 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 11:25:43,668 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-28 11:25:43,712 INFO L134 CoverageAnalysis]: Checked inductivity of 21 backedges. 0 proven. 21 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-28 11:25:43,712 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-28 11:25:43,712 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_2ca7a644-5b0a-4f3d-9179-f30a2c52dfce/bin-2019/uautomizer/z3 Starting monitored process 7 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 7 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-28 11:25:43,724 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-11-28 11:25:43,760 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) [2018-11-28 11:25:43,760 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-11-28 11:25:43,764 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-28 11:25:43,799 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 6 treesize of output 5 [2018-11-28 11:25:43,800 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-11-28 11:25:43,805 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-0 vars, 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-28 11:25:43,805 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 2 variables, input treesize:13, output treesize:9 [2018-11-28 11:25:44,058 INFO L134 CoverageAnalysis]: Checked inductivity of 21 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 21 trivial. 0 not checked. [2018-11-28 11:25:44,074 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 1 imperfect interpolant sequences. [2018-11-28 11:25:44,074 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [15] imperfect sequences [10] total 24 [2018-11-28 11:25:44,075 INFO L459 AbstractCegarLoop]: Interpolant automaton has 24 states [2018-11-28 11:25:44,075 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 24 interpolants. [2018-11-28 11:25:44,075 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=77, Invalid=475, Unknown=0, NotChecked=0, Total=552 [2018-11-28 11:25:44,075 INFO L87 Difference]: Start difference. First operand 135 states and 139 transitions. Second operand 24 states. [2018-11-28 11:25:44,641 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-28 11:25:44,641 INFO L93 Difference]: Finished difference Result 136 states and 140 transitions. [2018-11-28 11:25:44,642 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 24 states. [2018-11-28 11:25:44,642 INFO L78 Accepts]: Start accepts. Automaton has 24 states. Word has length 62 [2018-11-28 11:25:44,642 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-28 11:25:44,642 INFO L225 Difference]: With dead ends: 136 [2018-11-28 11:25:44,642 INFO L226 Difference]: Without dead ends: 134 [2018-11-28 11:25:44,643 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 84 GetRequests, 46 SyntacticMatches, 3 SemanticMatches, 35 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 207 ImplicationChecksByTransitivity, 0.4s TimeCoverageRelationStatistics Valid=177, Invalid=1155, Unknown=0, NotChecked=0, Total=1332 [2018-11-28 11:25:44,643 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 134 states. [2018-11-28 11:25:44,645 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 134 to 134. [2018-11-28 11:25:44,646 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 134 states. [2018-11-28 11:25:44,646 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 134 states to 134 states and 138 transitions. [2018-11-28 11:25:44,646 INFO L78 Accepts]: Start accepts. Automaton has 134 states and 138 transitions. Word has length 62 [2018-11-28 11:25:44,646 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-28 11:25:44,646 INFO L480 AbstractCegarLoop]: Abstraction has 134 states and 138 transitions. [2018-11-28 11:25:44,647 INFO L481 AbstractCegarLoop]: Interpolant automaton has 24 states. [2018-11-28 11:25:44,647 INFO L276 IsEmpty]: Start isEmpty. Operand 134 states and 138 transitions. [2018-11-28 11:25:44,647 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 73 [2018-11-28 11:25:44,647 INFO L394 BasicCegarLoop]: Found error trace [2018-11-28 11:25:44,647 INFO L402 BasicCegarLoop]: trace histogram [7, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-28 11:25:44,648 INFO L423 AbstractCegarLoop]: === Iteration 20 === [ldv_kref_initErr1REQUIRES_VIOLATION, ldv_kref_initErr0REQUIRES_VIOLATION, ldv_list_addErr0REQUIRES_VIOLATION, ldv_list_addErr1REQUIRES_VIOLATION, ldv_kobject_createErr0REQUIRES_VIOLATION, ldv_kobject_createErr1REQUIRES_VIOLATION, ldv_destroy_msgsErr3REQUIRES_VIOLATION, ldv_destroy_msgsErr4REQUIRES_VIOLATION, ldv_destroy_msgsErr0REQUIRES_VIOLATION, ldv_destroy_msgsErr5REQUIRES_VIOLATION, ldv_destroy_msgsErr2REQUIRES_VIOLATION, ldv_destroy_msgsErr1REQUIRES_VIOLATION, ldv_msg_fillErr0REQUIRES_VIOLATION, ldv_msg_fillErr5REQUIRES_VIOLATION, ldv_msg_fillErr1REQUIRES_VIOLATION, ldv_msg_fillErr2REQUIRES_VIOLATION, ldv_msg_fillErr3REQUIRES_VIOLATION, ldv_msg_fillErr4REQUIRES_VIOLATION, ldv_atomic_add_returnErr0REQUIRES_VIOLATION, ldv_atomic_add_returnErr2REQUIRES_VIOLATION, ldv_atomic_add_returnErr1REQUIRES_VIOLATION, ldv_atomic_add_returnErr3REQUIRES_VIOLATION, __ldv_list_delErr3REQUIRES_VIOLATION, __ldv_list_delErr1REQUIRES_VIOLATION, __ldv_list_delErr2REQUIRES_VIOLATION, __ldv_list_delErr0REQUIRES_VIOLATION, ldv_kobject_cleanupErr3ASSERT_VIOLATIONMEMORY_FREE, ldv_kobject_cleanupErr2ASSERT_VIOLATIONMEMORY_FREE, ldv_kobject_cleanupErr4ASSERT_VIOLATIONMEMORY_FREE, ldv_kobject_cleanupErr0REQUIRES_VIOLATION, ldv_kobject_cleanupErr5ASSERT_VIOLATIONMEMORY_FREE, ldv_kobject_cleanupErr1REQUIRES_VIOLATION, ldv_msg_freeErr3ASSERT_VIOLATIONMEMORY_FREE, ldv_msg_freeErr5ASSERT_VIOLATIONMEMORY_FREE, ldv_msg_freeErr2ASSERT_VIOLATIONMEMORY_FREE, ldv_msg_freeErr4ASSERT_VIOLATIONMEMORY_FREE, ldv_msg_freeErr0REQUIRES_VIOLATION, ldv_msg_freeErr1REQUIRES_VIOLATION, mainErr0ENSURES_VIOLATIONMEMORY_LEAK, LDV_INIT_LIST_HEADErr1REQUIRES_VIOLATION, LDV_INIT_LIST_HEADErr2REQUIRES_VIOLATION, LDV_INIT_LIST_HEADErr0REQUIRES_VIOLATION, LDV_INIT_LIST_HEADErr3REQUIRES_VIOLATION, ldv_list_delErr0REQUIRES_VIOLATION, ldv_list_delErr2REQUIRES_VIOLATION, ldv_list_delErr1REQUIRES_VIOLATION, ldv_list_delErr3REQUIRES_VIOLATION, __ldv_list_addErr4REQUIRES_VIOLATION, __ldv_list_addErr3REQUIRES_VIOLATION, __ldv_list_addErr1REQUIRES_VIOLATION, __ldv_list_addErr2REQUIRES_VIOLATION, __ldv_list_addErr7REQUIRES_VIOLATION, __ldv_list_addErr0REQUIRES_VIOLATION, __ldv_list_addErr5REQUIRES_VIOLATION, __ldv_list_addErr6REQUIRES_VIOLATION, ldv_dev_set_drvdataErr1REQUIRES_VIOLATION, ldv_dev_set_drvdataErr0REQUIRES_VIOLATION, ldv_atomic_sub_returnErr0REQUIRES_VIOLATION, ldv_atomic_sub_returnErr2REQUIRES_VIOLATION, ldv_atomic_sub_returnErr1REQUIRES_VIOLATION, ldv_atomic_sub_returnErr3REQUIRES_VIOLATION, ldv_list_add_tailErr1REQUIRES_VIOLATION, ldv_list_add_tailErr0REQUIRES_VIOLATION, ldv_dev_get_drvdataErr0REQUIRES_VIOLATION, ldv_dev_get_drvdataErr1REQUIRES_VIOLATION, ldv_msg_allocErr1REQUIRES_VIOLATION, ldv_msg_allocErr0REQUIRES_VIOLATION]=== [2018-11-28 11:25:44,648 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-28 11:25:44,648 INFO L82 PathProgramCache]: Analyzing trace with hash 1963990681, now seen corresponding path program 1 times [2018-11-28 11:25:44,648 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-28 11:25:44,648 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-28 11:25:44,649 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 11:25:44,649 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-28 11:25:44,649 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 11:25:44,668 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-28 11:25:44,737 INFO L134 CoverageAnalysis]: Checked inductivity of 28 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 28 trivial. 0 not checked. [2018-11-28 11:25:44,737 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-28 11:25:44,737 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [10] imperfect sequences [] total 10 [2018-11-28 11:25:44,737 INFO L459 AbstractCegarLoop]: Interpolant automaton has 10 states [2018-11-28 11:25:44,737 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 10 interpolants. [2018-11-28 11:25:44,738 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=17, Invalid=73, Unknown=0, NotChecked=0, Total=90 [2018-11-28 11:25:44,738 INFO L87 Difference]: Start difference. First operand 134 states and 138 transitions. Second operand 10 states. [2018-11-28 11:25:44,792 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-28 11:25:44,793 INFO L93 Difference]: Finished difference Result 137 states and 140 transitions. [2018-11-28 11:25:44,794 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 10 states. [2018-11-28 11:25:44,794 INFO L78 Accepts]: Start accepts. Automaton has 10 states. Word has length 72 [2018-11-28 11:25:44,794 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-28 11:25:44,794 INFO L225 Difference]: With dead ends: 137 [2018-11-28 11:25:44,795 INFO L226 Difference]: Without dead ends: 134 [2018-11-28 11:25:44,795 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 12 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 10 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=25, Invalid=107, Unknown=0, NotChecked=0, Total=132 [2018-11-28 11:25:44,795 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 134 states. [2018-11-28 11:25:44,797 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 134 to 134. [2018-11-28 11:25:44,797 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 134 states. [2018-11-28 11:25:44,797 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 134 states to 134 states and 137 transitions. [2018-11-28 11:25:44,798 INFO L78 Accepts]: Start accepts. Automaton has 134 states and 137 transitions. Word has length 72 [2018-11-28 11:25:44,798 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-28 11:25:44,798 INFO L480 AbstractCegarLoop]: Abstraction has 134 states and 137 transitions. [2018-11-28 11:25:44,798 INFO L481 AbstractCegarLoop]: Interpolant automaton has 10 states. [2018-11-28 11:25:44,798 INFO L276 IsEmpty]: Start isEmpty. Operand 134 states and 137 transitions. [2018-11-28 11:25:44,799 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 86 [2018-11-28 11:25:44,799 INFO L394 BasicCegarLoop]: Found error trace [2018-11-28 11:25:44,799 INFO L402 BasicCegarLoop]: trace histogram [7, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-28 11:25:44,799 INFO L423 AbstractCegarLoop]: === Iteration 21 === [ldv_kref_initErr1REQUIRES_VIOLATION, ldv_kref_initErr0REQUIRES_VIOLATION, ldv_list_addErr0REQUIRES_VIOLATION, ldv_list_addErr1REQUIRES_VIOLATION, ldv_kobject_createErr0REQUIRES_VIOLATION, ldv_kobject_createErr1REQUIRES_VIOLATION, ldv_destroy_msgsErr3REQUIRES_VIOLATION, ldv_destroy_msgsErr4REQUIRES_VIOLATION, ldv_destroy_msgsErr0REQUIRES_VIOLATION, ldv_destroy_msgsErr5REQUIRES_VIOLATION, ldv_destroy_msgsErr2REQUIRES_VIOLATION, ldv_destroy_msgsErr1REQUIRES_VIOLATION, ldv_msg_fillErr0REQUIRES_VIOLATION, ldv_msg_fillErr5REQUIRES_VIOLATION, ldv_msg_fillErr1REQUIRES_VIOLATION, ldv_msg_fillErr2REQUIRES_VIOLATION, ldv_msg_fillErr3REQUIRES_VIOLATION, ldv_msg_fillErr4REQUIRES_VIOLATION, ldv_atomic_add_returnErr0REQUIRES_VIOLATION, ldv_atomic_add_returnErr2REQUIRES_VIOLATION, ldv_atomic_add_returnErr1REQUIRES_VIOLATION, ldv_atomic_add_returnErr3REQUIRES_VIOLATION, __ldv_list_delErr3REQUIRES_VIOLATION, __ldv_list_delErr1REQUIRES_VIOLATION, __ldv_list_delErr2REQUIRES_VIOLATION, __ldv_list_delErr0REQUIRES_VIOLATION, ldv_kobject_cleanupErr3ASSERT_VIOLATIONMEMORY_FREE, ldv_kobject_cleanupErr2ASSERT_VIOLATIONMEMORY_FREE, ldv_kobject_cleanupErr4ASSERT_VIOLATIONMEMORY_FREE, ldv_kobject_cleanupErr0REQUIRES_VIOLATION, ldv_kobject_cleanupErr5ASSERT_VIOLATIONMEMORY_FREE, ldv_kobject_cleanupErr1REQUIRES_VIOLATION, ldv_msg_freeErr3ASSERT_VIOLATIONMEMORY_FREE, ldv_msg_freeErr5ASSERT_VIOLATIONMEMORY_FREE, ldv_msg_freeErr2ASSERT_VIOLATIONMEMORY_FREE, ldv_msg_freeErr4ASSERT_VIOLATIONMEMORY_FREE, ldv_msg_freeErr0REQUIRES_VIOLATION, ldv_msg_freeErr1REQUIRES_VIOLATION, mainErr0ENSURES_VIOLATIONMEMORY_LEAK, LDV_INIT_LIST_HEADErr1REQUIRES_VIOLATION, LDV_INIT_LIST_HEADErr2REQUIRES_VIOLATION, LDV_INIT_LIST_HEADErr0REQUIRES_VIOLATION, LDV_INIT_LIST_HEADErr3REQUIRES_VIOLATION, ldv_list_delErr0REQUIRES_VIOLATION, ldv_list_delErr2REQUIRES_VIOLATION, ldv_list_delErr1REQUIRES_VIOLATION, ldv_list_delErr3REQUIRES_VIOLATION, __ldv_list_addErr4REQUIRES_VIOLATION, __ldv_list_addErr3REQUIRES_VIOLATION, __ldv_list_addErr1REQUIRES_VIOLATION, __ldv_list_addErr2REQUIRES_VIOLATION, __ldv_list_addErr7REQUIRES_VIOLATION, __ldv_list_addErr0REQUIRES_VIOLATION, __ldv_list_addErr5REQUIRES_VIOLATION, __ldv_list_addErr6REQUIRES_VIOLATION, ldv_dev_set_drvdataErr1REQUIRES_VIOLATION, ldv_dev_set_drvdataErr0REQUIRES_VIOLATION, ldv_atomic_sub_returnErr0REQUIRES_VIOLATION, ldv_atomic_sub_returnErr2REQUIRES_VIOLATION, ldv_atomic_sub_returnErr1REQUIRES_VIOLATION, ldv_atomic_sub_returnErr3REQUIRES_VIOLATION, ldv_list_add_tailErr1REQUIRES_VIOLATION, ldv_list_add_tailErr0REQUIRES_VIOLATION, ldv_dev_get_drvdataErr0REQUIRES_VIOLATION, ldv_dev_get_drvdataErr1REQUIRES_VIOLATION, ldv_msg_allocErr1REQUIRES_VIOLATION, ldv_msg_allocErr0REQUIRES_VIOLATION]=== [2018-11-28 11:25:44,800 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-28 11:25:44,800 INFO L82 PathProgramCache]: Analyzing trace with hash -1499600980, now seen corresponding path program 1 times [2018-11-28 11:25:44,800 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-28 11:25:44,800 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-28 11:25:44,801 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 11:25:44,801 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-28 11:25:44,801 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 11:25:44,814 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-28 11:25:44,929 INFO L134 CoverageAnalysis]: Checked inductivity of 28 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 28 trivial. 0 not checked. [2018-11-28 11:25:44,929 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-28 11:25:44,929 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [15] imperfect sequences [] total 15 [2018-11-28 11:25:44,930 INFO L459 AbstractCegarLoop]: Interpolant automaton has 16 states [2018-11-28 11:25:44,930 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 16 interpolants. [2018-11-28 11:25:44,930 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=29, Invalid=211, Unknown=0, NotChecked=0, Total=240 [2018-11-28 11:25:44,930 INFO L87 Difference]: Start difference. First operand 134 states and 137 transitions. Second operand 16 states. [2018-11-28 11:25:45,222 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-28 11:25:45,222 INFO L93 Difference]: Finished difference Result 141 states and 144 transitions. [2018-11-28 11:25:45,223 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 17 states. [2018-11-28 11:25:45,223 INFO L78 Accepts]: Start accepts. Automaton has 16 states. Word has length 85 [2018-11-28 11:25:45,223 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-28 11:25:45,224 INFO L225 Difference]: With dead ends: 141 [2018-11-28 11:25:45,224 INFO L226 Difference]: Without dead ends: 141 [2018-11-28 11:25:45,224 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 20 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 19 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 10 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=49, Invalid=371, Unknown=0, NotChecked=0, Total=420 [2018-11-28 11:25:45,225 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 141 states. [2018-11-28 11:25:45,227 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 141 to 132. [2018-11-28 11:25:45,227 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 132 states. [2018-11-28 11:25:45,228 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 132 states to 132 states and 135 transitions. [2018-11-28 11:25:45,228 INFO L78 Accepts]: Start accepts. Automaton has 132 states and 135 transitions. Word has length 85 [2018-11-28 11:25:45,228 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-28 11:25:45,228 INFO L480 AbstractCegarLoop]: Abstraction has 132 states and 135 transitions. [2018-11-28 11:25:45,228 INFO L481 AbstractCegarLoop]: Interpolant automaton has 16 states. [2018-11-28 11:25:45,228 INFO L276 IsEmpty]: Start isEmpty. Operand 132 states and 135 transitions. [2018-11-28 11:25:45,229 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 86 [2018-11-28 11:25:45,229 INFO L394 BasicCegarLoop]: Found error trace [2018-11-28 11:25:45,229 INFO L402 BasicCegarLoop]: trace histogram [7, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-28 11:25:45,230 INFO L423 AbstractCegarLoop]: === Iteration 22 === [ldv_kref_initErr1REQUIRES_VIOLATION, ldv_kref_initErr0REQUIRES_VIOLATION, ldv_list_addErr0REQUIRES_VIOLATION, ldv_list_addErr1REQUIRES_VIOLATION, ldv_kobject_createErr0REQUIRES_VIOLATION, ldv_kobject_createErr1REQUIRES_VIOLATION, ldv_destroy_msgsErr3REQUIRES_VIOLATION, ldv_destroy_msgsErr4REQUIRES_VIOLATION, ldv_destroy_msgsErr0REQUIRES_VIOLATION, ldv_destroy_msgsErr5REQUIRES_VIOLATION, ldv_destroy_msgsErr2REQUIRES_VIOLATION, ldv_destroy_msgsErr1REQUIRES_VIOLATION, ldv_msg_fillErr0REQUIRES_VIOLATION, ldv_msg_fillErr5REQUIRES_VIOLATION, ldv_msg_fillErr1REQUIRES_VIOLATION, ldv_msg_fillErr2REQUIRES_VIOLATION, ldv_msg_fillErr3REQUIRES_VIOLATION, ldv_msg_fillErr4REQUIRES_VIOLATION, ldv_atomic_add_returnErr0REQUIRES_VIOLATION, ldv_atomic_add_returnErr2REQUIRES_VIOLATION, ldv_atomic_add_returnErr1REQUIRES_VIOLATION, ldv_atomic_add_returnErr3REQUIRES_VIOLATION, __ldv_list_delErr3REQUIRES_VIOLATION, __ldv_list_delErr1REQUIRES_VIOLATION, __ldv_list_delErr2REQUIRES_VIOLATION, __ldv_list_delErr0REQUIRES_VIOLATION, ldv_kobject_cleanupErr3ASSERT_VIOLATIONMEMORY_FREE, ldv_kobject_cleanupErr2ASSERT_VIOLATIONMEMORY_FREE, ldv_kobject_cleanupErr4ASSERT_VIOLATIONMEMORY_FREE, ldv_kobject_cleanupErr0REQUIRES_VIOLATION, ldv_kobject_cleanupErr5ASSERT_VIOLATIONMEMORY_FREE, ldv_kobject_cleanupErr1REQUIRES_VIOLATION, ldv_msg_freeErr3ASSERT_VIOLATIONMEMORY_FREE, ldv_msg_freeErr5ASSERT_VIOLATIONMEMORY_FREE, ldv_msg_freeErr2ASSERT_VIOLATIONMEMORY_FREE, ldv_msg_freeErr4ASSERT_VIOLATIONMEMORY_FREE, ldv_msg_freeErr0REQUIRES_VIOLATION, ldv_msg_freeErr1REQUIRES_VIOLATION, mainErr0ENSURES_VIOLATIONMEMORY_LEAK, LDV_INIT_LIST_HEADErr1REQUIRES_VIOLATION, LDV_INIT_LIST_HEADErr2REQUIRES_VIOLATION, LDV_INIT_LIST_HEADErr0REQUIRES_VIOLATION, LDV_INIT_LIST_HEADErr3REQUIRES_VIOLATION, ldv_list_delErr0REQUIRES_VIOLATION, ldv_list_delErr2REQUIRES_VIOLATION, ldv_list_delErr1REQUIRES_VIOLATION, ldv_list_delErr3REQUIRES_VIOLATION, __ldv_list_addErr4REQUIRES_VIOLATION, __ldv_list_addErr3REQUIRES_VIOLATION, __ldv_list_addErr1REQUIRES_VIOLATION, __ldv_list_addErr2REQUIRES_VIOLATION, __ldv_list_addErr7REQUIRES_VIOLATION, __ldv_list_addErr0REQUIRES_VIOLATION, __ldv_list_addErr5REQUIRES_VIOLATION, __ldv_list_addErr6REQUIRES_VIOLATION, ldv_dev_set_drvdataErr1REQUIRES_VIOLATION, ldv_dev_set_drvdataErr0REQUIRES_VIOLATION, ldv_atomic_sub_returnErr0REQUIRES_VIOLATION, ldv_atomic_sub_returnErr2REQUIRES_VIOLATION, ldv_atomic_sub_returnErr1REQUIRES_VIOLATION, ldv_atomic_sub_returnErr3REQUIRES_VIOLATION, ldv_list_add_tailErr1REQUIRES_VIOLATION, ldv_list_add_tailErr0REQUIRES_VIOLATION, ldv_dev_get_drvdataErr0REQUIRES_VIOLATION, ldv_dev_get_drvdataErr1REQUIRES_VIOLATION, ldv_msg_allocErr1REQUIRES_VIOLATION, ldv_msg_allocErr0REQUIRES_VIOLATION]=== [2018-11-28 11:25:45,230 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-28 11:25:45,230 INFO L82 PathProgramCache]: Analyzing trace with hash -1499600979, now seen corresponding path program 1 times [2018-11-28 11:25:45,230 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-28 11:25:45,230 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-28 11:25:45,231 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 11:25:45,231 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-28 11:25:45,231 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 11:25:45,243 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-28 11:25:45,308 INFO L134 CoverageAnalysis]: Checked inductivity of 28 backedges. 0 proven. 28 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-28 11:25:45,308 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-28 11:25:45,308 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_2ca7a644-5b0a-4f3d-9179-f30a2c52dfce/bin-2019/uautomizer/z3 Starting monitored process 8 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 8 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-28 11:25:45,324 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-28 11:25:45,362 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-28 11:25:45,365 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-28 11:25:45,403 INFO L134 CoverageAnalysis]: Checked inductivity of 28 backedges. 0 proven. 28 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-28 11:25:45,428 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-11-28 11:25:45,429 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [11, 11] total 12 [2018-11-28 11:25:45,429 INFO L459 AbstractCegarLoop]: Interpolant automaton has 12 states [2018-11-28 11:25:45,429 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 12 interpolants. [2018-11-28 11:25:45,429 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=57, Invalid=75, Unknown=0, NotChecked=0, Total=132 [2018-11-28 11:25:45,429 INFO L87 Difference]: Start difference. First operand 132 states and 135 transitions. Second operand 12 states. [2018-11-28 11:25:45,458 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-28 11:25:45,458 INFO L93 Difference]: Finished difference Result 135 states and 138 transitions. [2018-11-28 11:25:45,459 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 11 states. [2018-11-28 11:25:45,459 INFO L78 Accepts]: Start accepts. Automaton has 12 states. Word has length 85 [2018-11-28 11:25:45,460 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-28 11:25:45,460 INFO L225 Difference]: With dead ends: 135 [2018-11-28 11:25:45,460 INFO L226 Difference]: Without dead ends: 133 [2018-11-28 11:25:45,460 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 96 GetRequests, 85 SyntacticMatches, 0 SemanticMatches, 11 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 20 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=61, Invalid=95, Unknown=0, NotChecked=0, Total=156 [2018-11-28 11:25:45,461 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 133 states. [2018-11-28 11:25:45,462 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 133 to 133. [2018-11-28 11:25:45,463 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 133 states. [2018-11-28 11:25:45,463 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 133 states to 133 states and 136 transitions. [2018-11-28 11:25:45,463 INFO L78 Accepts]: Start accepts. Automaton has 133 states and 136 transitions. Word has length 85 [2018-11-28 11:25:45,463 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-28 11:25:45,464 INFO L480 AbstractCegarLoop]: Abstraction has 133 states and 136 transitions. [2018-11-28 11:25:45,464 INFO L481 AbstractCegarLoop]: Interpolant automaton has 12 states. [2018-11-28 11:25:45,464 INFO L276 IsEmpty]: Start isEmpty. Operand 133 states and 136 transitions. [2018-11-28 11:25:45,464 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 87 [2018-11-28 11:25:45,464 INFO L394 BasicCegarLoop]: Found error trace [2018-11-28 11:25:45,465 INFO L402 BasicCegarLoop]: trace histogram [8, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-28 11:25:45,465 INFO L423 AbstractCegarLoop]: === Iteration 23 === [ldv_kref_initErr1REQUIRES_VIOLATION, ldv_kref_initErr0REQUIRES_VIOLATION, ldv_list_addErr0REQUIRES_VIOLATION, ldv_list_addErr1REQUIRES_VIOLATION, ldv_kobject_createErr0REQUIRES_VIOLATION, ldv_kobject_createErr1REQUIRES_VIOLATION, ldv_destroy_msgsErr3REQUIRES_VIOLATION, ldv_destroy_msgsErr4REQUIRES_VIOLATION, ldv_destroy_msgsErr0REQUIRES_VIOLATION, ldv_destroy_msgsErr5REQUIRES_VIOLATION, ldv_destroy_msgsErr2REQUIRES_VIOLATION, ldv_destroy_msgsErr1REQUIRES_VIOLATION, ldv_msg_fillErr0REQUIRES_VIOLATION, ldv_msg_fillErr5REQUIRES_VIOLATION, ldv_msg_fillErr1REQUIRES_VIOLATION, ldv_msg_fillErr2REQUIRES_VIOLATION, ldv_msg_fillErr3REQUIRES_VIOLATION, ldv_msg_fillErr4REQUIRES_VIOLATION, ldv_atomic_add_returnErr0REQUIRES_VIOLATION, ldv_atomic_add_returnErr2REQUIRES_VIOLATION, ldv_atomic_add_returnErr1REQUIRES_VIOLATION, ldv_atomic_add_returnErr3REQUIRES_VIOLATION, __ldv_list_delErr3REQUIRES_VIOLATION, __ldv_list_delErr1REQUIRES_VIOLATION, __ldv_list_delErr2REQUIRES_VIOLATION, __ldv_list_delErr0REQUIRES_VIOLATION, ldv_kobject_cleanupErr3ASSERT_VIOLATIONMEMORY_FREE, ldv_kobject_cleanupErr2ASSERT_VIOLATIONMEMORY_FREE, ldv_kobject_cleanupErr4ASSERT_VIOLATIONMEMORY_FREE, ldv_kobject_cleanupErr0REQUIRES_VIOLATION, ldv_kobject_cleanupErr5ASSERT_VIOLATIONMEMORY_FREE, ldv_kobject_cleanupErr1REQUIRES_VIOLATION, ldv_msg_freeErr3ASSERT_VIOLATIONMEMORY_FREE, ldv_msg_freeErr5ASSERT_VIOLATIONMEMORY_FREE, ldv_msg_freeErr2ASSERT_VIOLATIONMEMORY_FREE, ldv_msg_freeErr4ASSERT_VIOLATIONMEMORY_FREE, ldv_msg_freeErr0REQUIRES_VIOLATION, ldv_msg_freeErr1REQUIRES_VIOLATION, mainErr0ENSURES_VIOLATIONMEMORY_LEAK, LDV_INIT_LIST_HEADErr1REQUIRES_VIOLATION, LDV_INIT_LIST_HEADErr2REQUIRES_VIOLATION, LDV_INIT_LIST_HEADErr0REQUIRES_VIOLATION, LDV_INIT_LIST_HEADErr3REQUIRES_VIOLATION, ldv_list_delErr0REQUIRES_VIOLATION, ldv_list_delErr2REQUIRES_VIOLATION, ldv_list_delErr1REQUIRES_VIOLATION, ldv_list_delErr3REQUIRES_VIOLATION, __ldv_list_addErr4REQUIRES_VIOLATION, __ldv_list_addErr3REQUIRES_VIOLATION, __ldv_list_addErr1REQUIRES_VIOLATION, __ldv_list_addErr2REQUIRES_VIOLATION, __ldv_list_addErr7REQUIRES_VIOLATION, __ldv_list_addErr0REQUIRES_VIOLATION, __ldv_list_addErr5REQUIRES_VIOLATION, __ldv_list_addErr6REQUIRES_VIOLATION, ldv_dev_set_drvdataErr1REQUIRES_VIOLATION, ldv_dev_set_drvdataErr0REQUIRES_VIOLATION, ldv_atomic_sub_returnErr0REQUIRES_VIOLATION, ldv_atomic_sub_returnErr2REQUIRES_VIOLATION, ldv_atomic_sub_returnErr1REQUIRES_VIOLATION, ldv_atomic_sub_returnErr3REQUIRES_VIOLATION, ldv_list_add_tailErr1REQUIRES_VIOLATION, ldv_list_add_tailErr0REQUIRES_VIOLATION, ldv_dev_get_drvdataErr0REQUIRES_VIOLATION, ldv_dev_get_drvdataErr1REQUIRES_VIOLATION, ldv_msg_allocErr1REQUIRES_VIOLATION, ldv_msg_allocErr0REQUIRES_VIOLATION]=== [2018-11-28 11:25:45,465 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-28 11:25:45,465 INFO L82 PathProgramCache]: Analyzing trace with hash -481832414, now seen corresponding path program 2 times [2018-11-28 11:25:45,465 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-28 11:25:45,465 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-28 11:25:45,466 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 11:25:45,466 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-28 11:25:45,466 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 11:25:45,481 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-28 11:25:45,563 INFO L134 CoverageAnalysis]: Checked inductivity of 36 backedges. 0 proven. 36 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-28 11:25:45,563 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-28 11:25:45,563 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_2ca7a644-5b0a-4f3d-9179-f30a2c52dfce/bin-2019/uautomizer/z3 Starting monitored process 9 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 9 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-28 11:25:45,579 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-11-28 11:25:45,627 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) [2018-11-28 11:25:45,627 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-11-28 11:25:45,632 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-28 11:25:45,643 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 6 treesize of output 5 [2018-11-28 11:25:45,643 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-11-28 11:25:45,656 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-0 vars, 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-28 11:25:45,656 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 2 variables, input treesize:13, output treesize:9 [2018-11-28 11:25:45,953 INFO L134 CoverageAnalysis]: Checked inductivity of 36 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 36 trivial. 0 not checked. [2018-11-28 11:25:45,968 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 1 imperfect interpolant sequences. [2018-11-28 11:25:45,968 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [18] imperfect sequences [12] total 29 [2018-11-28 11:25:45,968 INFO L459 AbstractCegarLoop]: Interpolant automaton has 29 states [2018-11-28 11:25:45,969 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 29 interpolants. [2018-11-28 11:25:45,969 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=105, Invalid=707, Unknown=0, NotChecked=0, Total=812 [2018-11-28 11:25:45,969 INFO L87 Difference]: Start difference. First operand 133 states and 136 transitions. Second operand 29 states. [2018-11-28 11:25:46,690 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-28 11:25:46,690 INFO L93 Difference]: Finished difference Result 134 states and 137 transitions. [2018-11-28 11:25:46,691 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 29 states. [2018-11-28 11:25:46,691 INFO L78 Accepts]: Start accepts. Automaton has 29 states. Word has length 86 [2018-11-28 11:25:46,691 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-28 11:25:46,692 INFO L225 Difference]: With dead ends: 134 [2018-11-28 11:25:46,692 INFO L226 Difference]: Without dead ends: 132 [2018-11-28 11:25:46,693 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 113 GetRequests, 65 SyntacticMatches, 5 SemanticMatches, 43 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 337 ImplicationChecksByTransitivity, 0.5s TimeCoverageRelationStatistics Valid=258, Invalid=1722, Unknown=0, NotChecked=0, Total=1980 [2018-11-28 11:25:46,693 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 132 states. [2018-11-28 11:25:46,695 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 132 to 132. [2018-11-28 11:25:46,695 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 132 states. [2018-11-28 11:25:46,695 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 132 states to 132 states and 135 transitions. [2018-11-28 11:25:46,695 INFO L78 Accepts]: Start accepts. Automaton has 132 states and 135 transitions. Word has length 86 [2018-11-28 11:25:46,696 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-28 11:25:46,696 INFO L480 AbstractCegarLoop]: Abstraction has 132 states and 135 transitions. [2018-11-28 11:25:46,696 INFO L481 AbstractCegarLoop]: Interpolant automaton has 29 states. [2018-11-28 11:25:46,696 INFO L276 IsEmpty]: Start isEmpty. Operand 132 states and 135 transitions. [2018-11-28 11:25:46,696 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 86 [2018-11-28 11:25:46,696 INFO L394 BasicCegarLoop]: Found error trace [2018-11-28 11:25:46,696 INFO L402 BasicCegarLoop]: trace histogram [9, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-28 11:25:46,697 INFO L423 AbstractCegarLoop]: === Iteration 24 === [ldv_kref_initErr1REQUIRES_VIOLATION, ldv_kref_initErr0REQUIRES_VIOLATION, ldv_list_addErr0REQUIRES_VIOLATION, ldv_list_addErr1REQUIRES_VIOLATION, ldv_kobject_createErr0REQUIRES_VIOLATION, ldv_kobject_createErr1REQUIRES_VIOLATION, ldv_destroy_msgsErr3REQUIRES_VIOLATION, ldv_destroy_msgsErr4REQUIRES_VIOLATION, ldv_destroy_msgsErr0REQUIRES_VIOLATION, ldv_destroy_msgsErr5REQUIRES_VIOLATION, ldv_destroy_msgsErr2REQUIRES_VIOLATION, ldv_destroy_msgsErr1REQUIRES_VIOLATION, ldv_msg_fillErr0REQUIRES_VIOLATION, ldv_msg_fillErr5REQUIRES_VIOLATION, ldv_msg_fillErr1REQUIRES_VIOLATION, ldv_msg_fillErr2REQUIRES_VIOLATION, ldv_msg_fillErr3REQUIRES_VIOLATION, ldv_msg_fillErr4REQUIRES_VIOLATION, ldv_atomic_add_returnErr0REQUIRES_VIOLATION, ldv_atomic_add_returnErr2REQUIRES_VIOLATION, ldv_atomic_add_returnErr1REQUIRES_VIOLATION, ldv_atomic_add_returnErr3REQUIRES_VIOLATION, __ldv_list_delErr3REQUIRES_VIOLATION, __ldv_list_delErr1REQUIRES_VIOLATION, __ldv_list_delErr2REQUIRES_VIOLATION, __ldv_list_delErr0REQUIRES_VIOLATION, ldv_kobject_cleanupErr3ASSERT_VIOLATIONMEMORY_FREE, ldv_kobject_cleanupErr2ASSERT_VIOLATIONMEMORY_FREE, ldv_kobject_cleanupErr4ASSERT_VIOLATIONMEMORY_FREE, ldv_kobject_cleanupErr0REQUIRES_VIOLATION, ldv_kobject_cleanupErr5ASSERT_VIOLATIONMEMORY_FREE, ldv_kobject_cleanupErr1REQUIRES_VIOLATION, ldv_msg_freeErr3ASSERT_VIOLATIONMEMORY_FREE, ldv_msg_freeErr5ASSERT_VIOLATIONMEMORY_FREE, ldv_msg_freeErr2ASSERT_VIOLATIONMEMORY_FREE, ldv_msg_freeErr4ASSERT_VIOLATIONMEMORY_FREE, ldv_msg_freeErr0REQUIRES_VIOLATION, ldv_msg_freeErr1REQUIRES_VIOLATION, mainErr0ENSURES_VIOLATIONMEMORY_LEAK, LDV_INIT_LIST_HEADErr1REQUIRES_VIOLATION, LDV_INIT_LIST_HEADErr2REQUIRES_VIOLATION, LDV_INIT_LIST_HEADErr0REQUIRES_VIOLATION, LDV_INIT_LIST_HEADErr3REQUIRES_VIOLATION, ldv_list_delErr0REQUIRES_VIOLATION, ldv_list_delErr2REQUIRES_VIOLATION, ldv_list_delErr1REQUIRES_VIOLATION, ldv_list_delErr3REQUIRES_VIOLATION, __ldv_list_addErr4REQUIRES_VIOLATION, __ldv_list_addErr3REQUIRES_VIOLATION, __ldv_list_addErr1REQUIRES_VIOLATION, __ldv_list_addErr2REQUIRES_VIOLATION, __ldv_list_addErr7REQUIRES_VIOLATION, __ldv_list_addErr0REQUIRES_VIOLATION, __ldv_list_addErr5REQUIRES_VIOLATION, __ldv_list_addErr6REQUIRES_VIOLATION, ldv_dev_set_drvdataErr1REQUIRES_VIOLATION, ldv_dev_set_drvdataErr0REQUIRES_VIOLATION, ldv_atomic_sub_returnErr0REQUIRES_VIOLATION, ldv_atomic_sub_returnErr2REQUIRES_VIOLATION, ldv_atomic_sub_returnErr1REQUIRES_VIOLATION, ldv_atomic_sub_returnErr3REQUIRES_VIOLATION, ldv_list_add_tailErr1REQUIRES_VIOLATION, ldv_list_add_tailErr0REQUIRES_VIOLATION, ldv_dev_get_drvdataErr0REQUIRES_VIOLATION, ldv_dev_get_drvdataErr1REQUIRES_VIOLATION, ldv_msg_allocErr1REQUIRES_VIOLATION, ldv_msg_allocErr0REQUIRES_VIOLATION]=== [2018-11-28 11:25:46,697 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-28 11:25:46,697 INFO L82 PathProgramCache]: Analyzing trace with hash -2061581223, now seen corresponding path program 1 times [2018-11-28 11:25:46,697 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-28 11:25:46,697 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-28 11:25:46,698 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 11:25:46,698 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-28 11:25:46,698 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 11:25:46,708 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-28 11:25:46,767 INFO L134 CoverageAnalysis]: Checked inductivity of 45 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 45 trivial. 0 not checked. [2018-11-28 11:25:46,767 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-28 11:25:46,767 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [10] imperfect sequences [] total 10 [2018-11-28 11:25:46,768 INFO L459 AbstractCegarLoop]: Interpolant automaton has 10 states [2018-11-28 11:25:46,768 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 10 interpolants. [2018-11-28 11:25:46,768 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=17, Invalid=73, Unknown=0, NotChecked=0, Total=90 [2018-11-28 11:25:46,768 INFO L87 Difference]: Start difference. First operand 132 states and 135 transitions. Second operand 10 states. [2018-11-28 11:25:46,814 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-28 11:25:46,814 INFO L93 Difference]: Finished difference Result 134 states and 136 transitions. [2018-11-28 11:25:46,814 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 10 states. [2018-11-28 11:25:46,815 INFO L78 Accepts]: Start accepts. Automaton has 10 states. Word has length 85 [2018-11-28 11:25:46,815 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-28 11:25:46,815 INFO L225 Difference]: With dead ends: 134 [2018-11-28 11:25:46,815 INFO L226 Difference]: Without dead ends: 132 [2018-11-28 11:25:46,816 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 12 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 10 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=25, Invalid=107, Unknown=0, NotChecked=0, Total=132 [2018-11-28 11:25:46,816 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 132 states. [2018-11-28 11:25:46,817 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 132 to 132. [2018-11-28 11:25:46,818 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 132 states. [2018-11-28 11:25:46,818 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 132 states to 132 states and 134 transitions. [2018-11-28 11:25:46,818 INFO L78 Accepts]: Start accepts. Automaton has 132 states and 134 transitions. Word has length 85 [2018-11-28 11:25:46,818 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-28 11:25:46,819 INFO L480 AbstractCegarLoop]: Abstraction has 132 states and 134 transitions. [2018-11-28 11:25:46,819 INFO L481 AbstractCegarLoop]: Interpolant automaton has 10 states. [2018-11-28 11:25:46,819 INFO L276 IsEmpty]: Start isEmpty. Operand 132 states and 134 transitions. [2018-11-28 11:25:46,819 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 102 [2018-11-28 11:25:46,819 INFO L394 BasicCegarLoop]: Found error trace [2018-11-28 11:25:46,819 INFO L402 BasicCegarLoop]: trace histogram [9, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-28 11:25:46,820 INFO L423 AbstractCegarLoop]: === Iteration 25 === [ldv_kref_initErr1REQUIRES_VIOLATION, ldv_kref_initErr0REQUIRES_VIOLATION, ldv_list_addErr0REQUIRES_VIOLATION, ldv_list_addErr1REQUIRES_VIOLATION, ldv_kobject_createErr0REQUIRES_VIOLATION, ldv_kobject_createErr1REQUIRES_VIOLATION, ldv_destroy_msgsErr3REQUIRES_VIOLATION, ldv_destroy_msgsErr4REQUIRES_VIOLATION, ldv_destroy_msgsErr0REQUIRES_VIOLATION, ldv_destroy_msgsErr5REQUIRES_VIOLATION, ldv_destroy_msgsErr2REQUIRES_VIOLATION, ldv_destroy_msgsErr1REQUIRES_VIOLATION, ldv_msg_fillErr0REQUIRES_VIOLATION, ldv_msg_fillErr5REQUIRES_VIOLATION, ldv_msg_fillErr1REQUIRES_VIOLATION, ldv_msg_fillErr2REQUIRES_VIOLATION, ldv_msg_fillErr3REQUIRES_VIOLATION, ldv_msg_fillErr4REQUIRES_VIOLATION, ldv_atomic_add_returnErr0REQUIRES_VIOLATION, ldv_atomic_add_returnErr2REQUIRES_VIOLATION, ldv_atomic_add_returnErr1REQUIRES_VIOLATION, ldv_atomic_add_returnErr3REQUIRES_VIOLATION, __ldv_list_delErr3REQUIRES_VIOLATION, __ldv_list_delErr1REQUIRES_VIOLATION, __ldv_list_delErr2REQUIRES_VIOLATION, __ldv_list_delErr0REQUIRES_VIOLATION, ldv_kobject_cleanupErr3ASSERT_VIOLATIONMEMORY_FREE, ldv_kobject_cleanupErr2ASSERT_VIOLATIONMEMORY_FREE, ldv_kobject_cleanupErr4ASSERT_VIOLATIONMEMORY_FREE, ldv_kobject_cleanupErr0REQUIRES_VIOLATION, ldv_kobject_cleanupErr5ASSERT_VIOLATIONMEMORY_FREE, ldv_kobject_cleanupErr1REQUIRES_VIOLATION, ldv_msg_freeErr3ASSERT_VIOLATIONMEMORY_FREE, ldv_msg_freeErr5ASSERT_VIOLATIONMEMORY_FREE, ldv_msg_freeErr2ASSERT_VIOLATIONMEMORY_FREE, ldv_msg_freeErr4ASSERT_VIOLATIONMEMORY_FREE, ldv_msg_freeErr0REQUIRES_VIOLATION, ldv_msg_freeErr1REQUIRES_VIOLATION, mainErr0ENSURES_VIOLATIONMEMORY_LEAK, LDV_INIT_LIST_HEADErr1REQUIRES_VIOLATION, LDV_INIT_LIST_HEADErr2REQUIRES_VIOLATION, LDV_INIT_LIST_HEADErr0REQUIRES_VIOLATION, LDV_INIT_LIST_HEADErr3REQUIRES_VIOLATION, ldv_list_delErr0REQUIRES_VIOLATION, ldv_list_delErr2REQUIRES_VIOLATION, ldv_list_delErr1REQUIRES_VIOLATION, ldv_list_delErr3REQUIRES_VIOLATION, __ldv_list_addErr4REQUIRES_VIOLATION, __ldv_list_addErr3REQUIRES_VIOLATION, __ldv_list_addErr1REQUIRES_VIOLATION, __ldv_list_addErr2REQUIRES_VIOLATION, __ldv_list_addErr7REQUIRES_VIOLATION, __ldv_list_addErr0REQUIRES_VIOLATION, __ldv_list_addErr5REQUIRES_VIOLATION, __ldv_list_addErr6REQUIRES_VIOLATION, ldv_dev_set_drvdataErr1REQUIRES_VIOLATION, ldv_dev_set_drvdataErr0REQUIRES_VIOLATION, ldv_atomic_sub_returnErr0REQUIRES_VIOLATION, ldv_atomic_sub_returnErr2REQUIRES_VIOLATION, ldv_atomic_sub_returnErr1REQUIRES_VIOLATION, ldv_atomic_sub_returnErr3REQUIRES_VIOLATION, ldv_list_add_tailErr1REQUIRES_VIOLATION, ldv_list_add_tailErr0REQUIRES_VIOLATION, ldv_dev_get_drvdataErr0REQUIRES_VIOLATION, ldv_dev_get_drvdataErr1REQUIRES_VIOLATION, ldv_msg_allocErr1REQUIRES_VIOLATION, ldv_msg_allocErr0REQUIRES_VIOLATION]=== [2018-11-28 11:25:46,820 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-28 11:25:46,820 INFO L82 PathProgramCache]: Analyzing trace with hash -1177100084, now seen corresponding path program 1 times [2018-11-28 11:25:46,820 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-28 11:25:46,820 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-28 11:25:46,821 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 11:25:46,821 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-28 11:25:46,821 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 11:25:46,832 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-28 11:25:46,998 INFO L134 CoverageAnalysis]: Checked inductivity of 45 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 45 trivial. 0 not checked. [2018-11-28 11:25:46,998 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-28 11:25:46,998 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [19] imperfect sequences [] total 19 [2018-11-28 11:25:46,998 INFO L459 AbstractCegarLoop]: Interpolant automaton has 20 states [2018-11-28 11:25:46,998 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 20 interpolants. [2018-11-28 11:25:46,998 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=37, Invalid=343, Unknown=0, NotChecked=0, Total=380 [2018-11-28 11:25:46,998 INFO L87 Difference]: Start difference. First operand 132 states and 134 transitions. Second operand 20 states. [2018-11-28 11:25:47,312 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-28 11:25:47,312 INFO L93 Difference]: Finished difference Result 135 states and 137 transitions. [2018-11-28 11:25:47,312 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 21 states. [2018-11-28 11:25:47,312 INFO L78 Accepts]: Start accepts. Automaton has 20 states. Word has length 101 [2018-11-28 11:25:47,313 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-28 11:25:47,313 INFO L225 Difference]: With dead ends: 135 [2018-11-28 11:25:47,313 INFO L226 Difference]: Without dead ends: 135 [2018-11-28 11:25:47,314 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 26 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 25 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 21 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=65, Invalid=637, Unknown=0, NotChecked=0, Total=702 [2018-11-28 11:25:47,314 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 135 states. [2018-11-28 11:25:47,315 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 135 to 130. [2018-11-28 11:25:47,316 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 130 states. [2018-11-28 11:25:47,316 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 130 states to 130 states and 132 transitions. [2018-11-28 11:25:47,316 INFO L78 Accepts]: Start accepts. Automaton has 130 states and 132 transitions. Word has length 101 [2018-11-28 11:25:47,316 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-28 11:25:47,317 INFO L480 AbstractCegarLoop]: Abstraction has 130 states and 132 transitions. [2018-11-28 11:25:47,317 INFO L481 AbstractCegarLoop]: Interpolant automaton has 20 states. [2018-11-28 11:25:47,317 INFO L276 IsEmpty]: Start isEmpty. Operand 130 states and 132 transitions. [2018-11-28 11:25:47,317 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 102 [2018-11-28 11:25:47,317 INFO L394 BasicCegarLoop]: Found error trace [2018-11-28 11:25:47,317 INFO L402 BasicCegarLoop]: trace histogram [9, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-28 11:25:47,318 INFO L423 AbstractCegarLoop]: === Iteration 26 === [ldv_kref_initErr1REQUIRES_VIOLATION, ldv_kref_initErr0REQUIRES_VIOLATION, ldv_list_addErr0REQUIRES_VIOLATION, ldv_list_addErr1REQUIRES_VIOLATION, ldv_kobject_createErr0REQUIRES_VIOLATION, ldv_kobject_createErr1REQUIRES_VIOLATION, ldv_destroy_msgsErr3REQUIRES_VIOLATION, ldv_destroy_msgsErr4REQUIRES_VIOLATION, ldv_destroy_msgsErr0REQUIRES_VIOLATION, ldv_destroy_msgsErr5REQUIRES_VIOLATION, ldv_destroy_msgsErr2REQUIRES_VIOLATION, ldv_destroy_msgsErr1REQUIRES_VIOLATION, ldv_msg_fillErr0REQUIRES_VIOLATION, ldv_msg_fillErr5REQUIRES_VIOLATION, ldv_msg_fillErr1REQUIRES_VIOLATION, ldv_msg_fillErr2REQUIRES_VIOLATION, ldv_msg_fillErr3REQUIRES_VIOLATION, ldv_msg_fillErr4REQUIRES_VIOLATION, ldv_atomic_add_returnErr0REQUIRES_VIOLATION, ldv_atomic_add_returnErr2REQUIRES_VIOLATION, ldv_atomic_add_returnErr1REQUIRES_VIOLATION, ldv_atomic_add_returnErr3REQUIRES_VIOLATION, __ldv_list_delErr3REQUIRES_VIOLATION, __ldv_list_delErr1REQUIRES_VIOLATION, __ldv_list_delErr2REQUIRES_VIOLATION, __ldv_list_delErr0REQUIRES_VIOLATION, ldv_kobject_cleanupErr3ASSERT_VIOLATIONMEMORY_FREE, ldv_kobject_cleanupErr2ASSERT_VIOLATIONMEMORY_FREE, ldv_kobject_cleanupErr4ASSERT_VIOLATIONMEMORY_FREE, ldv_kobject_cleanupErr0REQUIRES_VIOLATION, ldv_kobject_cleanupErr5ASSERT_VIOLATIONMEMORY_FREE, ldv_kobject_cleanupErr1REQUIRES_VIOLATION, ldv_msg_freeErr3ASSERT_VIOLATIONMEMORY_FREE, ldv_msg_freeErr5ASSERT_VIOLATIONMEMORY_FREE, ldv_msg_freeErr2ASSERT_VIOLATIONMEMORY_FREE, ldv_msg_freeErr4ASSERT_VIOLATIONMEMORY_FREE, ldv_msg_freeErr0REQUIRES_VIOLATION, ldv_msg_freeErr1REQUIRES_VIOLATION, mainErr0ENSURES_VIOLATIONMEMORY_LEAK, LDV_INIT_LIST_HEADErr1REQUIRES_VIOLATION, LDV_INIT_LIST_HEADErr2REQUIRES_VIOLATION, LDV_INIT_LIST_HEADErr0REQUIRES_VIOLATION, LDV_INIT_LIST_HEADErr3REQUIRES_VIOLATION, ldv_list_delErr0REQUIRES_VIOLATION, ldv_list_delErr2REQUIRES_VIOLATION, ldv_list_delErr1REQUIRES_VIOLATION, ldv_list_delErr3REQUIRES_VIOLATION, __ldv_list_addErr4REQUIRES_VIOLATION, __ldv_list_addErr3REQUIRES_VIOLATION, __ldv_list_addErr1REQUIRES_VIOLATION, __ldv_list_addErr2REQUIRES_VIOLATION, __ldv_list_addErr7REQUIRES_VIOLATION, __ldv_list_addErr0REQUIRES_VIOLATION, __ldv_list_addErr5REQUIRES_VIOLATION, __ldv_list_addErr6REQUIRES_VIOLATION, ldv_dev_set_drvdataErr1REQUIRES_VIOLATION, ldv_dev_set_drvdataErr0REQUIRES_VIOLATION, ldv_atomic_sub_returnErr0REQUIRES_VIOLATION, ldv_atomic_sub_returnErr2REQUIRES_VIOLATION, ldv_atomic_sub_returnErr1REQUIRES_VIOLATION, ldv_atomic_sub_returnErr3REQUIRES_VIOLATION, ldv_list_add_tailErr1REQUIRES_VIOLATION, ldv_list_add_tailErr0REQUIRES_VIOLATION, ldv_dev_get_drvdataErr0REQUIRES_VIOLATION, ldv_dev_get_drvdataErr1REQUIRES_VIOLATION, ldv_msg_allocErr1REQUIRES_VIOLATION, ldv_msg_allocErr0REQUIRES_VIOLATION]=== [2018-11-28 11:25:47,318 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-28 11:25:47,318 INFO L82 PathProgramCache]: Analyzing trace with hash -1177100083, now seen corresponding path program 1 times [2018-11-28 11:25:47,318 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-28 11:25:47,318 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-28 11:25:47,319 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 11:25:47,319 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-28 11:25:47,319 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 11:25:47,331 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-28 11:25:47,436 INFO L134 CoverageAnalysis]: Checked inductivity of 45 backedges. 0 proven. 45 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-28 11:25:47,436 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-28 11:25:47,436 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_2ca7a644-5b0a-4f3d-9179-f30a2c52dfce/bin-2019/uautomizer/z3 Starting monitored process 10 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 10 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-28 11:25:47,448 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-28 11:25:47,484 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-28 11:25:47,487 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-28 11:25:47,502 INFO L134 CoverageAnalysis]: Checked inductivity of 45 backedges. 0 proven. 45 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-28 11:25:47,528 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-11-28 11:25:47,529 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [13, 13] total 14 [2018-11-28 11:25:47,529 INFO L459 AbstractCegarLoop]: Interpolant automaton has 14 states [2018-11-28 11:25:47,529 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 14 interpolants. [2018-11-28 11:25:47,529 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=80, Invalid=102, Unknown=0, NotChecked=0, Total=182 [2018-11-28 11:25:47,530 INFO L87 Difference]: Start difference. First operand 130 states and 132 transitions. Second operand 14 states. [2018-11-28 11:25:47,563 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-28 11:25:47,563 INFO L93 Difference]: Finished difference Result 133 states and 135 transitions. [2018-11-28 11:25:47,563 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 13 states. [2018-11-28 11:25:47,563 INFO L78 Accepts]: Start accepts. Automaton has 14 states. Word has length 101 [2018-11-28 11:25:47,563 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-28 11:25:47,564 INFO L225 Difference]: With dead ends: 133 [2018-11-28 11:25:47,564 INFO L226 Difference]: Without dead ends: 131 [2018-11-28 11:25:47,564 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 114 GetRequests, 101 SyntacticMatches, 0 SemanticMatches, 13 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 26 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=84, Invalid=126, Unknown=0, NotChecked=0, Total=210 [2018-11-28 11:25:47,565 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 131 states. [2018-11-28 11:25:47,566 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 131 to 131. [2018-11-28 11:25:47,566 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 131 states. [2018-11-28 11:25:47,567 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 131 states to 131 states and 133 transitions. [2018-11-28 11:25:47,567 INFO L78 Accepts]: Start accepts. Automaton has 131 states and 133 transitions. Word has length 101 [2018-11-28 11:25:47,567 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-28 11:25:47,567 INFO L480 AbstractCegarLoop]: Abstraction has 131 states and 133 transitions. [2018-11-28 11:25:47,567 INFO L481 AbstractCegarLoop]: Interpolant automaton has 14 states. [2018-11-28 11:25:47,567 INFO L276 IsEmpty]: Start isEmpty. Operand 131 states and 133 transitions. [2018-11-28 11:25:47,567 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 103 [2018-11-28 11:25:47,567 INFO L394 BasicCegarLoop]: Found error trace [2018-11-28 11:25:47,568 INFO L402 BasicCegarLoop]: trace histogram [10, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-28 11:25:47,568 INFO L423 AbstractCegarLoop]: === Iteration 27 === [ldv_kref_initErr1REQUIRES_VIOLATION, ldv_kref_initErr0REQUIRES_VIOLATION, ldv_list_addErr0REQUIRES_VIOLATION, ldv_list_addErr1REQUIRES_VIOLATION, ldv_kobject_createErr0REQUIRES_VIOLATION, ldv_kobject_createErr1REQUIRES_VIOLATION, ldv_destroy_msgsErr3REQUIRES_VIOLATION, ldv_destroy_msgsErr4REQUIRES_VIOLATION, ldv_destroy_msgsErr0REQUIRES_VIOLATION, ldv_destroy_msgsErr5REQUIRES_VIOLATION, ldv_destroy_msgsErr2REQUIRES_VIOLATION, ldv_destroy_msgsErr1REQUIRES_VIOLATION, ldv_msg_fillErr0REQUIRES_VIOLATION, ldv_msg_fillErr5REQUIRES_VIOLATION, ldv_msg_fillErr1REQUIRES_VIOLATION, ldv_msg_fillErr2REQUIRES_VIOLATION, ldv_msg_fillErr3REQUIRES_VIOLATION, ldv_msg_fillErr4REQUIRES_VIOLATION, ldv_atomic_add_returnErr0REQUIRES_VIOLATION, ldv_atomic_add_returnErr2REQUIRES_VIOLATION, ldv_atomic_add_returnErr1REQUIRES_VIOLATION, ldv_atomic_add_returnErr3REQUIRES_VIOLATION, __ldv_list_delErr3REQUIRES_VIOLATION, __ldv_list_delErr1REQUIRES_VIOLATION, __ldv_list_delErr2REQUIRES_VIOLATION, __ldv_list_delErr0REQUIRES_VIOLATION, ldv_kobject_cleanupErr3ASSERT_VIOLATIONMEMORY_FREE, ldv_kobject_cleanupErr2ASSERT_VIOLATIONMEMORY_FREE, ldv_kobject_cleanupErr4ASSERT_VIOLATIONMEMORY_FREE, ldv_kobject_cleanupErr0REQUIRES_VIOLATION, ldv_kobject_cleanupErr5ASSERT_VIOLATIONMEMORY_FREE, ldv_kobject_cleanupErr1REQUIRES_VIOLATION, ldv_msg_freeErr3ASSERT_VIOLATIONMEMORY_FREE, ldv_msg_freeErr5ASSERT_VIOLATIONMEMORY_FREE, ldv_msg_freeErr2ASSERT_VIOLATIONMEMORY_FREE, ldv_msg_freeErr4ASSERT_VIOLATIONMEMORY_FREE, ldv_msg_freeErr0REQUIRES_VIOLATION, ldv_msg_freeErr1REQUIRES_VIOLATION, mainErr0ENSURES_VIOLATIONMEMORY_LEAK, LDV_INIT_LIST_HEADErr1REQUIRES_VIOLATION, LDV_INIT_LIST_HEADErr2REQUIRES_VIOLATION, LDV_INIT_LIST_HEADErr0REQUIRES_VIOLATION, LDV_INIT_LIST_HEADErr3REQUIRES_VIOLATION, ldv_list_delErr0REQUIRES_VIOLATION, ldv_list_delErr2REQUIRES_VIOLATION, ldv_list_delErr1REQUIRES_VIOLATION, ldv_list_delErr3REQUIRES_VIOLATION, __ldv_list_addErr4REQUIRES_VIOLATION, __ldv_list_addErr3REQUIRES_VIOLATION, __ldv_list_addErr1REQUIRES_VIOLATION, __ldv_list_addErr2REQUIRES_VIOLATION, __ldv_list_addErr7REQUIRES_VIOLATION, __ldv_list_addErr0REQUIRES_VIOLATION, __ldv_list_addErr5REQUIRES_VIOLATION, __ldv_list_addErr6REQUIRES_VIOLATION, ldv_dev_set_drvdataErr1REQUIRES_VIOLATION, ldv_dev_set_drvdataErr0REQUIRES_VIOLATION, ldv_atomic_sub_returnErr0REQUIRES_VIOLATION, ldv_atomic_sub_returnErr2REQUIRES_VIOLATION, ldv_atomic_sub_returnErr1REQUIRES_VIOLATION, ldv_atomic_sub_returnErr3REQUIRES_VIOLATION, ldv_list_add_tailErr1REQUIRES_VIOLATION, ldv_list_add_tailErr0REQUIRES_VIOLATION, ldv_dev_get_drvdataErr0REQUIRES_VIOLATION, ldv_dev_get_drvdataErr1REQUIRES_VIOLATION, ldv_msg_allocErr1REQUIRES_VIOLATION, ldv_msg_allocErr0REQUIRES_VIOLATION]=== [2018-11-28 11:25:47,568 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-28 11:25:47,568 INFO L82 PathProgramCache]: Analyzing trace with hash -1492172478, now seen corresponding path program 2 times [2018-11-28 11:25:47,568 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-28 11:25:47,568 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-28 11:25:47,569 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 11:25:47,569 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-28 11:25:47,569 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 11:25:47,585 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-28 11:25:47,669 INFO L134 CoverageAnalysis]: Checked inductivity of 55 backedges. 0 proven. 55 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-28 11:25:47,670 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-28 11:25:47,670 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_2ca7a644-5b0a-4f3d-9179-f30a2c52dfce/bin-2019/uautomizer/z3 Starting monitored process 11 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 11 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-28 11:25:47,681 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-11-28 11:25:47,723 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) [2018-11-28 11:25:47,723 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-11-28 11:25:47,727 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-28 11:25:47,745 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 6 treesize of output 5 [2018-11-28 11:25:47,746 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-11-28 11:25:47,761 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-0 vars, 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-28 11:25:47,761 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 2 variables, input treesize:13, output treesize:9 [2018-11-28 11:25:48,179 INFO L134 CoverageAnalysis]: Checked inductivity of 55 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 55 trivial. 0 not checked. [2018-11-28 11:25:48,194 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 1 imperfect interpolant sequences. [2018-11-28 11:25:48,194 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [22] imperfect sequences [14] total 35 [2018-11-28 11:25:48,194 INFO L459 AbstractCegarLoop]: Interpolant automaton has 35 states [2018-11-28 11:25:48,194 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 35 interpolants. [2018-11-28 11:25:48,195 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=140, Invalid=1050, Unknown=0, NotChecked=0, Total=1190 [2018-11-28 11:25:48,195 INFO L87 Difference]: Start difference. First operand 131 states and 133 transitions. Second operand 35 states. [2018-11-28 11:25:49,099 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-28 11:25:49,099 INFO L93 Difference]: Finished difference Result 132 states and 134 transitions. [2018-11-28 11:25:49,099 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 35 states. [2018-11-28 11:25:49,100 INFO L78 Accepts]: Start accepts. Automaton has 35 states. Word has length 102 [2018-11-28 11:25:49,100 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-28 11:25:49,100 INFO L225 Difference]: With dead ends: 132 [2018-11-28 11:25:49,100 INFO L226 Difference]: Without dead ends: 130 [2018-11-28 11:25:49,101 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 135 GetRequests, 75 SyntacticMatches, 7 SemanticMatches, 53 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 532 ImplicationChecksByTransitivity, 0.7s TimeCoverageRelationStatistics Valid=351, Invalid=2619, Unknown=0, NotChecked=0, Total=2970 [2018-11-28 11:25:49,101 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 130 states. [2018-11-28 11:25:49,102 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 130 to 130. [2018-11-28 11:25:49,102 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 130 states. [2018-11-28 11:25:49,102 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 130 states to 130 states and 132 transitions. [2018-11-28 11:25:49,102 INFO L78 Accepts]: Start accepts. Automaton has 130 states and 132 transitions. Word has length 102 [2018-11-28 11:25:49,102 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-28 11:25:49,102 INFO L480 AbstractCegarLoop]: Abstraction has 130 states and 132 transitions. [2018-11-28 11:25:49,103 INFO L481 AbstractCegarLoop]: Interpolant automaton has 35 states. [2018-11-28 11:25:49,103 INFO L276 IsEmpty]: Start isEmpty. Operand 130 states and 132 transitions. [2018-11-28 11:25:49,103 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 109 [2018-11-28 11:25:49,103 INFO L394 BasicCegarLoop]: Found error trace [2018-11-28 11:25:49,103 INFO L402 BasicCegarLoop]: trace histogram [11, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-28 11:25:49,110 INFO L423 AbstractCegarLoop]: === Iteration 28 === [ldv_kref_initErr1REQUIRES_VIOLATION, ldv_kref_initErr0REQUIRES_VIOLATION, ldv_list_addErr0REQUIRES_VIOLATION, ldv_list_addErr1REQUIRES_VIOLATION, ldv_kobject_createErr0REQUIRES_VIOLATION, ldv_kobject_createErr1REQUIRES_VIOLATION, ldv_destroy_msgsErr3REQUIRES_VIOLATION, ldv_destroy_msgsErr4REQUIRES_VIOLATION, ldv_destroy_msgsErr0REQUIRES_VIOLATION, ldv_destroy_msgsErr5REQUIRES_VIOLATION, ldv_destroy_msgsErr2REQUIRES_VIOLATION, ldv_destroy_msgsErr1REQUIRES_VIOLATION, ldv_msg_fillErr0REQUIRES_VIOLATION, ldv_msg_fillErr5REQUIRES_VIOLATION, ldv_msg_fillErr1REQUIRES_VIOLATION, ldv_msg_fillErr2REQUIRES_VIOLATION, ldv_msg_fillErr3REQUIRES_VIOLATION, ldv_msg_fillErr4REQUIRES_VIOLATION, ldv_atomic_add_returnErr0REQUIRES_VIOLATION, ldv_atomic_add_returnErr2REQUIRES_VIOLATION, ldv_atomic_add_returnErr1REQUIRES_VIOLATION, ldv_atomic_add_returnErr3REQUIRES_VIOLATION, __ldv_list_delErr3REQUIRES_VIOLATION, __ldv_list_delErr1REQUIRES_VIOLATION, __ldv_list_delErr2REQUIRES_VIOLATION, __ldv_list_delErr0REQUIRES_VIOLATION, ldv_kobject_cleanupErr3ASSERT_VIOLATIONMEMORY_FREE, ldv_kobject_cleanupErr2ASSERT_VIOLATIONMEMORY_FREE, ldv_kobject_cleanupErr4ASSERT_VIOLATIONMEMORY_FREE, ldv_kobject_cleanupErr0REQUIRES_VIOLATION, ldv_kobject_cleanupErr5ASSERT_VIOLATIONMEMORY_FREE, ldv_kobject_cleanupErr1REQUIRES_VIOLATION, ldv_msg_freeErr3ASSERT_VIOLATIONMEMORY_FREE, ldv_msg_freeErr5ASSERT_VIOLATIONMEMORY_FREE, ldv_msg_freeErr2ASSERT_VIOLATIONMEMORY_FREE, ldv_msg_freeErr4ASSERT_VIOLATIONMEMORY_FREE, ldv_msg_freeErr0REQUIRES_VIOLATION, ldv_msg_freeErr1REQUIRES_VIOLATION, mainErr0ENSURES_VIOLATIONMEMORY_LEAK, LDV_INIT_LIST_HEADErr1REQUIRES_VIOLATION, LDV_INIT_LIST_HEADErr2REQUIRES_VIOLATION, LDV_INIT_LIST_HEADErr0REQUIRES_VIOLATION, LDV_INIT_LIST_HEADErr3REQUIRES_VIOLATION, ldv_list_delErr0REQUIRES_VIOLATION, ldv_list_delErr2REQUIRES_VIOLATION, ldv_list_delErr1REQUIRES_VIOLATION, ldv_list_delErr3REQUIRES_VIOLATION, __ldv_list_addErr4REQUIRES_VIOLATION, __ldv_list_addErr3REQUIRES_VIOLATION, __ldv_list_addErr1REQUIRES_VIOLATION, __ldv_list_addErr2REQUIRES_VIOLATION, __ldv_list_addErr7REQUIRES_VIOLATION, __ldv_list_addErr0REQUIRES_VIOLATION, __ldv_list_addErr5REQUIRES_VIOLATION, __ldv_list_addErr6REQUIRES_VIOLATION, ldv_dev_set_drvdataErr1REQUIRES_VIOLATION, ldv_dev_set_drvdataErr0REQUIRES_VIOLATION, ldv_atomic_sub_returnErr0REQUIRES_VIOLATION, ldv_atomic_sub_returnErr2REQUIRES_VIOLATION, ldv_atomic_sub_returnErr1REQUIRES_VIOLATION, ldv_atomic_sub_returnErr3REQUIRES_VIOLATION, ldv_list_add_tailErr1REQUIRES_VIOLATION, ldv_list_add_tailErr0REQUIRES_VIOLATION, ldv_dev_get_drvdataErr0REQUIRES_VIOLATION, ldv_dev_get_drvdataErr1REQUIRES_VIOLATION, ldv_msg_allocErr1REQUIRES_VIOLATION, ldv_msg_allocErr0REQUIRES_VIOLATION]=== [2018-11-28 11:25:49,111 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-28 11:25:49,111 INFO L82 PathProgramCache]: Analyzing trace with hash 2022543782, now seen corresponding path program 1 times [2018-11-28 11:25:49,111 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-28 11:25:49,111 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-28 11:25:49,112 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 11:25:49,112 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-28 11:25:49,112 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 11:25:49,128 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-28 11:25:49,237 INFO L134 CoverageAnalysis]: Checked inductivity of 66 backedges. 0 proven. 66 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-28 11:25:49,237 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-28 11:25:49,238 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_2ca7a644-5b0a-4f3d-9179-f30a2c52dfce/bin-2019/uautomizer/z3 Starting monitored process 12 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 12 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-28 11:25:49,251 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-28 11:25:49,308 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-28 11:25:49,311 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-28 11:25:49,329 INFO L134 CoverageAnalysis]: Checked inductivity of 66 backedges. 0 proven. 66 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-28 11:25:49,344 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-11-28 11:25:49,344 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [15, 15] total 16 [2018-11-28 11:25:49,344 INFO L459 AbstractCegarLoop]: Interpolant automaton has 16 states [2018-11-28 11:25:49,345 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 16 interpolants. [2018-11-28 11:25:49,345 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=107, Invalid=133, Unknown=0, NotChecked=0, Total=240 [2018-11-28 11:25:49,345 INFO L87 Difference]: Start difference. First operand 130 states and 132 transitions. Second operand 16 states. [2018-11-28 11:25:49,375 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-28 11:25:49,375 INFO L93 Difference]: Finished difference Result 133 states and 135 transitions. [2018-11-28 11:25:49,377 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 15 states. [2018-11-28 11:25:49,377 INFO L78 Accepts]: Start accepts. Automaton has 16 states. Word has length 108 [2018-11-28 11:25:49,378 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-28 11:25:49,378 INFO L225 Difference]: With dead ends: 133 [2018-11-28 11:25:49,378 INFO L226 Difference]: Without dead ends: 131 [2018-11-28 11:25:49,379 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 123 GetRequests, 108 SyntacticMatches, 0 SemanticMatches, 15 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 32 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=111, Invalid=161, Unknown=0, NotChecked=0, Total=272 [2018-11-28 11:25:49,379 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 131 states. [2018-11-28 11:25:49,381 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 131 to 131. [2018-11-28 11:25:49,381 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 131 states. [2018-11-28 11:25:49,381 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 131 states to 131 states and 133 transitions. [2018-11-28 11:25:49,381 INFO L78 Accepts]: Start accepts. Automaton has 131 states and 133 transitions. Word has length 108 [2018-11-28 11:25:49,382 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-28 11:25:49,382 INFO L480 AbstractCegarLoop]: Abstraction has 131 states and 133 transitions. [2018-11-28 11:25:49,382 INFO L481 AbstractCegarLoop]: Interpolant automaton has 16 states. [2018-11-28 11:25:49,382 INFO L276 IsEmpty]: Start isEmpty. Operand 131 states and 133 transitions. [2018-11-28 11:25:49,382 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 110 [2018-11-28 11:25:49,382 INFO L394 BasicCegarLoop]: Found error trace [2018-11-28 11:25:49,383 INFO L402 BasicCegarLoop]: trace histogram [12, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-28 11:25:49,383 INFO L423 AbstractCegarLoop]: === Iteration 29 === [ldv_kref_initErr1REQUIRES_VIOLATION, ldv_kref_initErr0REQUIRES_VIOLATION, ldv_list_addErr0REQUIRES_VIOLATION, ldv_list_addErr1REQUIRES_VIOLATION, ldv_kobject_createErr0REQUIRES_VIOLATION, ldv_kobject_createErr1REQUIRES_VIOLATION, ldv_destroy_msgsErr3REQUIRES_VIOLATION, ldv_destroy_msgsErr4REQUIRES_VIOLATION, ldv_destroy_msgsErr0REQUIRES_VIOLATION, ldv_destroy_msgsErr5REQUIRES_VIOLATION, ldv_destroy_msgsErr2REQUIRES_VIOLATION, ldv_destroy_msgsErr1REQUIRES_VIOLATION, ldv_msg_fillErr0REQUIRES_VIOLATION, ldv_msg_fillErr5REQUIRES_VIOLATION, ldv_msg_fillErr1REQUIRES_VIOLATION, ldv_msg_fillErr2REQUIRES_VIOLATION, ldv_msg_fillErr3REQUIRES_VIOLATION, ldv_msg_fillErr4REQUIRES_VIOLATION, ldv_atomic_add_returnErr0REQUIRES_VIOLATION, ldv_atomic_add_returnErr2REQUIRES_VIOLATION, ldv_atomic_add_returnErr1REQUIRES_VIOLATION, ldv_atomic_add_returnErr3REQUIRES_VIOLATION, __ldv_list_delErr3REQUIRES_VIOLATION, __ldv_list_delErr1REQUIRES_VIOLATION, __ldv_list_delErr2REQUIRES_VIOLATION, __ldv_list_delErr0REQUIRES_VIOLATION, ldv_kobject_cleanupErr3ASSERT_VIOLATIONMEMORY_FREE, ldv_kobject_cleanupErr2ASSERT_VIOLATIONMEMORY_FREE, ldv_kobject_cleanupErr4ASSERT_VIOLATIONMEMORY_FREE, ldv_kobject_cleanupErr0REQUIRES_VIOLATION, ldv_kobject_cleanupErr5ASSERT_VIOLATIONMEMORY_FREE, ldv_kobject_cleanupErr1REQUIRES_VIOLATION, ldv_msg_freeErr3ASSERT_VIOLATIONMEMORY_FREE, ldv_msg_freeErr5ASSERT_VIOLATIONMEMORY_FREE, ldv_msg_freeErr2ASSERT_VIOLATIONMEMORY_FREE, ldv_msg_freeErr4ASSERT_VIOLATIONMEMORY_FREE, ldv_msg_freeErr0REQUIRES_VIOLATION, ldv_msg_freeErr1REQUIRES_VIOLATION, mainErr0ENSURES_VIOLATIONMEMORY_LEAK, LDV_INIT_LIST_HEADErr1REQUIRES_VIOLATION, LDV_INIT_LIST_HEADErr2REQUIRES_VIOLATION, LDV_INIT_LIST_HEADErr0REQUIRES_VIOLATION, LDV_INIT_LIST_HEADErr3REQUIRES_VIOLATION, ldv_list_delErr0REQUIRES_VIOLATION, ldv_list_delErr2REQUIRES_VIOLATION, ldv_list_delErr1REQUIRES_VIOLATION, ldv_list_delErr3REQUIRES_VIOLATION, __ldv_list_addErr4REQUIRES_VIOLATION, __ldv_list_addErr3REQUIRES_VIOLATION, __ldv_list_addErr1REQUIRES_VIOLATION, __ldv_list_addErr2REQUIRES_VIOLATION, __ldv_list_addErr7REQUIRES_VIOLATION, __ldv_list_addErr0REQUIRES_VIOLATION, __ldv_list_addErr5REQUIRES_VIOLATION, __ldv_list_addErr6REQUIRES_VIOLATION, ldv_dev_set_drvdataErr1REQUIRES_VIOLATION, ldv_dev_set_drvdataErr0REQUIRES_VIOLATION, ldv_atomic_sub_returnErr0REQUIRES_VIOLATION, ldv_atomic_sub_returnErr2REQUIRES_VIOLATION, ldv_atomic_sub_returnErr1REQUIRES_VIOLATION, ldv_atomic_sub_returnErr3REQUIRES_VIOLATION, ldv_list_add_tailErr1REQUIRES_VIOLATION, ldv_list_add_tailErr0REQUIRES_VIOLATION, ldv_dev_get_drvdataErr0REQUIRES_VIOLATION, ldv_dev_get_drvdataErr1REQUIRES_VIOLATION, ldv_msg_allocErr1REQUIRES_VIOLATION, ldv_msg_allocErr0REQUIRES_VIOLATION]=== [2018-11-28 11:25:49,383 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-28 11:25:49,383 INFO L82 PathProgramCache]: Analyzing trace with hash -1491946607, now seen corresponding path program 2 times [2018-11-28 11:25:49,383 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-28 11:25:49,383 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-28 11:25:49,384 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 11:25:49,384 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-28 11:25:49,384 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 11:25:49,399 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-28 11:25:49,539 INFO L134 CoverageAnalysis]: Checked inductivity of 78 backedges. 0 proven. 78 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-28 11:25:49,539 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-28 11:25:49,539 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_2ca7a644-5b0a-4f3d-9179-f30a2c52dfce/bin-2019/uautomizer/z3 Starting monitored process 13 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 13 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-28 11:25:49,557 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-11-28 11:25:49,601 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) [2018-11-28 11:25:49,601 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-11-28 11:25:49,606 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-28 11:25:49,684 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 11 treesize of output 8 [2018-11-28 11:25:49,686 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 8 treesize of output 7 [2018-11-28 11:25:49,686 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-11-28 11:25:49,688 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-28 11:25:49,689 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-2 vars, End of recursive call: and 1 xjuncts. [2018-11-28 11:25:49,689 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 1 variables, input treesize:11, output treesize:7 [2018-11-28 11:25:49,771 INFO L267 ElimStorePlain]: Start of recursive call 3: 1 dim-0 vars, End of recursive call: 1 dim-0 vars, and 1 xjuncts. [2018-11-28 11:25:49,773 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: 1 dim-0 vars, and 1 xjuncts. [2018-11-28 11:25:49,777 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-0 vars, 1 dim-2 vars, End of recursive call: 2 dim-0 vars, and 1 xjuncts. [2018-11-28 11:25:49,777 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 2 variables, input treesize:38, output treesize:26 [2018-11-28 11:25:50,381 WARN L854 $PredicateComparison]: unable to prove that (exists ((LDV_INIT_LIST_HEAD_~list.offset Int) (v_DerPreprocessor_2 Int)) (and (= |c_#memory_int| (store |c_old(#memory_int)| |c_LDV_INIT_LIST_HEAD_#in~list.base| (let ((.cse0 (+ LDV_INIT_LIST_HEAD_~list.offset 4))) (store (store (select |c_old(#memory_int)| |c_LDV_INIT_LIST_HEAD_#in~list.base|) LDV_INIT_LIST_HEAD_~list.offset v_DerPreprocessor_2) .cse0 (select (select |c_#memory_int| |c_LDV_INIT_LIST_HEAD_#in~list.base|) .cse0))))) (<= LDV_INIT_LIST_HEAD_~list.offset |c_LDV_INIT_LIST_HEAD_#in~list.offset|))) is different from true [2018-11-28 11:25:50,386 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 32 treesize of output 27 [2018-11-28 11:25:50,388 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:25:50,389 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 27 treesize of output 35 [2018-11-28 11:25:50,392 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:25:50,393 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:25:50,395 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 2 select indices, 2 select index equivalence classes, 3 disjoint index pairs (out of 1 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 29 treesize of output 37 [2018-11-28 11:25:50,396 INFO L267 ElimStorePlain]: Start of recursive call 4: End of recursive call: and 1 xjuncts. [2018-11-28 11:25:50,400 INFO L267 ElimStorePlain]: Start of recursive call 3: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-28 11:25:50,403 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-28 11:25:50,406 INFO L267 ElimStorePlain]: Start of recursive call 1: 2 dim-0 vars, 1 dim-2 vars, End of recursive call: and 1 xjuncts. [2018-11-28 11:25:50,406 INFO L202 ElimStorePlain]: Needed 4 recursive calls to eliminate 3 variables, input treesize:37, output treesize:9 [2018-11-28 11:25:50,686 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:25:50,687 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 29 treesize of output 36 [2018-11-28 11:25:50,698 INFO L683 Elim1Store]: detected equality via solver [2018-11-28 11:25:50,700 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:25:50,701 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 2 select indices, 2 select index equivalence classes, 1 disjoint index pairs (out of 1 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 36 treesize of output 15 [2018-11-28 11:25:50,701 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-11-28 11:25:50,703 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-28 11:25:50,705 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-2 vars, End of recursive call: and 1 xjuncts. [2018-11-28 11:25:50,705 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 1 variables, input treesize:32, output treesize:13 [2018-11-28 11:25:50,998 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 17 treesize of output 13 [2018-11-28 11:25:51,001 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 13 treesize of output 5 [2018-11-28 11:25:51,001 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-11-28 11:25:51,003 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-28 11:25:51,004 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-0 vars, 1 dim-2 vars, End of recursive call: and 1 xjuncts. [2018-11-28 11:25:51,004 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 2 variables, input treesize:17, output treesize:5 [2018-11-28 11:25:51,040 INFO L134 CoverageAnalysis]: Checked inductivity of 78 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 78 trivial. 0 not checked. [2018-11-28 11:25:51,055 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 1 imperfect interpolant sequences. [2018-11-28 11:25:51,056 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [41] imperfect sequences [16] total 55 [2018-11-28 11:25:51,056 INFO L459 AbstractCegarLoop]: Interpolant automaton has 55 states [2018-11-28 11:25:51,056 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 55 interpolants. [2018-11-28 11:25:51,057 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=197, Invalid=2668, Unknown=1, NotChecked=104, Total=2970 [2018-11-28 11:25:51,057 INFO L87 Difference]: Start difference. First operand 131 states and 133 transitions. Second operand 55 states. [2018-11-28 11:25:52,628 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-28 11:25:52,628 INFO L93 Difference]: Finished difference Result 112 states and 112 transitions. [2018-11-28 11:25:52,628 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 58 states. [2018-11-28 11:25:52,628 INFO L78 Accepts]: Start accepts. Automaton has 55 states. Word has length 109 [2018-11-28 11:25:52,629 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-28 11:25:52,629 INFO L225 Difference]: With dead ends: 112 [2018-11-28 11:25:52,629 INFO L226 Difference]: Without dead ends: 110 [2018-11-28 11:25:52,630 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 158 GetRequests, 70 SyntacticMatches, 1 SemanticMatches, 87 ConstructedPredicates, 1 IntricatePredicates, 0 DeprecatedPredicates, 1436 ImplicationChecksByTransitivity, 2.0s TimeCoverageRelationStatistics Valid=503, Invalid=7156, Unknown=1, NotChecked=172, Total=7832 [2018-11-28 11:25:52,630 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 110 states. [2018-11-28 11:25:52,632 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 110 to 110. [2018-11-28 11:25:52,632 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 110 states. [2018-11-28 11:25:52,632 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 110 states to 110 states and 110 transitions. [2018-11-28 11:25:52,632 INFO L78 Accepts]: Start accepts. Automaton has 110 states and 110 transitions. Word has length 109 [2018-11-28 11:25:52,633 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-28 11:25:52,633 INFO L480 AbstractCegarLoop]: Abstraction has 110 states and 110 transitions. [2018-11-28 11:25:52,633 INFO L481 AbstractCegarLoop]: Interpolant automaton has 55 states. [2018-11-28 11:25:52,633 INFO L276 IsEmpty]: Start isEmpty. Operand 110 states and 110 transitions. [2018-11-28 11:25:52,633 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 110 [2018-11-28 11:25:52,633 INFO L394 BasicCegarLoop]: Found error trace [2018-11-28 11:25:52,634 INFO L402 BasicCegarLoop]: trace histogram [13, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-28 11:25:52,634 INFO L423 AbstractCegarLoop]: === Iteration 30 === [ldv_kref_initErr1REQUIRES_VIOLATION, ldv_kref_initErr0REQUIRES_VIOLATION, ldv_list_addErr0REQUIRES_VIOLATION, ldv_list_addErr1REQUIRES_VIOLATION, ldv_kobject_createErr0REQUIRES_VIOLATION, ldv_kobject_createErr1REQUIRES_VIOLATION, ldv_destroy_msgsErr3REQUIRES_VIOLATION, ldv_destroy_msgsErr4REQUIRES_VIOLATION, ldv_destroy_msgsErr0REQUIRES_VIOLATION, ldv_destroy_msgsErr5REQUIRES_VIOLATION, ldv_destroy_msgsErr2REQUIRES_VIOLATION, ldv_destroy_msgsErr1REQUIRES_VIOLATION, ldv_msg_fillErr0REQUIRES_VIOLATION, ldv_msg_fillErr5REQUIRES_VIOLATION, ldv_msg_fillErr1REQUIRES_VIOLATION, ldv_msg_fillErr2REQUIRES_VIOLATION, ldv_msg_fillErr3REQUIRES_VIOLATION, ldv_msg_fillErr4REQUIRES_VIOLATION, ldv_atomic_add_returnErr0REQUIRES_VIOLATION, ldv_atomic_add_returnErr2REQUIRES_VIOLATION, ldv_atomic_add_returnErr1REQUIRES_VIOLATION, ldv_atomic_add_returnErr3REQUIRES_VIOLATION, __ldv_list_delErr3REQUIRES_VIOLATION, __ldv_list_delErr1REQUIRES_VIOLATION, __ldv_list_delErr2REQUIRES_VIOLATION, __ldv_list_delErr0REQUIRES_VIOLATION, ldv_kobject_cleanupErr3ASSERT_VIOLATIONMEMORY_FREE, ldv_kobject_cleanupErr2ASSERT_VIOLATIONMEMORY_FREE, ldv_kobject_cleanupErr4ASSERT_VIOLATIONMEMORY_FREE, ldv_kobject_cleanupErr0REQUIRES_VIOLATION, ldv_kobject_cleanupErr5ASSERT_VIOLATIONMEMORY_FREE, ldv_kobject_cleanupErr1REQUIRES_VIOLATION, ldv_msg_freeErr3ASSERT_VIOLATIONMEMORY_FREE, ldv_msg_freeErr5ASSERT_VIOLATIONMEMORY_FREE, ldv_msg_freeErr2ASSERT_VIOLATIONMEMORY_FREE, ldv_msg_freeErr4ASSERT_VIOLATIONMEMORY_FREE, ldv_msg_freeErr0REQUIRES_VIOLATION, ldv_msg_freeErr1REQUIRES_VIOLATION, mainErr0ENSURES_VIOLATIONMEMORY_LEAK, LDV_INIT_LIST_HEADErr1REQUIRES_VIOLATION, LDV_INIT_LIST_HEADErr2REQUIRES_VIOLATION, LDV_INIT_LIST_HEADErr0REQUIRES_VIOLATION, LDV_INIT_LIST_HEADErr3REQUIRES_VIOLATION, ldv_list_delErr0REQUIRES_VIOLATION, ldv_list_delErr2REQUIRES_VIOLATION, ldv_list_delErr1REQUIRES_VIOLATION, ldv_list_delErr3REQUIRES_VIOLATION, __ldv_list_addErr4REQUIRES_VIOLATION, __ldv_list_addErr3REQUIRES_VIOLATION, __ldv_list_addErr1REQUIRES_VIOLATION, __ldv_list_addErr2REQUIRES_VIOLATION, __ldv_list_addErr7REQUIRES_VIOLATION, __ldv_list_addErr0REQUIRES_VIOLATION, __ldv_list_addErr5REQUIRES_VIOLATION, __ldv_list_addErr6REQUIRES_VIOLATION, ldv_dev_set_drvdataErr1REQUIRES_VIOLATION, ldv_dev_set_drvdataErr0REQUIRES_VIOLATION, ldv_atomic_sub_returnErr0REQUIRES_VIOLATION, ldv_atomic_sub_returnErr2REQUIRES_VIOLATION, ldv_atomic_sub_returnErr1REQUIRES_VIOLATION, ldv_atomic_sub_returnErr3REQUIRES_VIOLATION, ldv_list_add_tailErr1REQUIRES_VIOLATION, ldv_list_add_tailErr0REQUIRES_VIOLATION, ldv_dev_get_drvdataErr0REQUIRES_VIOLATION, ldv_dev_get_drvdataErr1REQUIRES_VIOLATION, ldv_msg_allocErr1REQUIRES_VIOLATION, ldv_msg_allocErr0REQUIRES_VIOLATION]=== [2018-11-28 11:25:52,634 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-28 11:25:52,634 INFO L82 PathProgramCache]: Analyzing trace with hash 281292969, now seen corresponding path program 1 times [2018-11-28 11:25:52,634 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-28 11:25:52,635 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-28 11:25:52,636 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 11:25:52,636 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-28 11:25:52,636 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 11:25:52,651 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-28 11:25:52,794 INFO L134 CoverageAnalysis]: Checked inductivity of 91 backedges. 0 proven. 91 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-28 11:25:52,794 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-28 11:25:52,794 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_2ca7a644-5b0a-4f3d-9179-f30a2c52dfce/bin-2019/uautomizer/z3 Starting monitored process 14 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 14 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-28 11:25:52,800 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-28 11:25:52,855 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-28 11:25:52,859 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-28 11:25:52,875 INFO L134 CoverageAnalysis]: Checked inductivity of 91 backedges. 0 proven. 91 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-28 11:25:52,890 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-11-28 11:25:52,891 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [17, 17] total 18 [2018-11-28 11:25:52,891 INFO L459 AbstractCegarLoop]: Interpolant automaton has 18 states [2018-11-28 11:25:52,891 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 18 interpolants. [2018-11-28 11:25:52,891 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=138, Invalid=168, Unknown=0, NotChecked=0, Total=306 [2018-11-28 11:25:52,892 INFO L87 Difference]: Start difference. First operand 110 states and 110 transitions. Second operand 18 states. [2018-11-28 11:25:52,922 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-28 11:25:52,922 INFO L93 Difference]: Finished difference Result 113 states and 113 transitions. [2018-11-28 11:25:52,922 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 17 states. [2018-11-28 11:25:52,922 INFO L78 Accepts]: Start accepts. Automaton has 18 states. Word has length 109 [2018-11-28 11:25:52,922 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-28 11:25:52,923 INFO L225 Difference]: With dead ends: 113 [2018-11-28 11:25:52,923 INFO L226 Difference]: Without dead ends: 111 [2018-11-28 11:25:52,923 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 126 GetRequests, 109 SyntacticMatches, 0 SemanticMatches, 17 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 38 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=142, Invalid=200, Unknown=0, NotChecked=0, Total=342 [2018-11-28 11:25:52,923 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 111 states. [2018-11-28 11:25:52,925 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 111 to 111. [2018-11-28 11:25:52,925 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 111 states. [2018-11-28 11:25:52,925 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 111 states to 111 states and 111 transitions. [2018-11-28 11:25:52,925 INFO L78 Accepts]: Start accepts. Automaton has 111 states and 111 transitions. Word has length 109 [2018-11-28 11:25:52,925 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-28 11:25:52,925 INFO L480 AbstractCegarLoop]: Abstraction has 111 states and 111 transitions. [2018-11-28 11:25:52,925 INFO L481 AbstractCegarLoop]: Interpolant automaton has 18 states. [2018-11-28 11:25:52,925 INFO L276 IsEmpty]: Start isEmpty. Operand 111 states and 111 transitions. [2018-11-28 11:25:52,926 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 111 [2018-11-28 11:25:52,926 INFO L394 BasicCegarLoop]: Found error trace [2018-11-28 11:25:52,926 INFO L402 BasicCegarLoop]: trace histogram [14, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-28 11:25:52,926 INFO L423 AbstractCegarLoop]: === Iteration 31 === [ldv_kref_initErr1REQUIRES_VIOLATION, ldv_kref_initErr0REQUIRES_VIOLATION, ldv_list_addErr0REQUIRES_VIOLATION, ldv_list_addErr1REQUIRES_VIOLATION, ldv_kobject_createErr0REQUIRES_VIOLATION, ldv_kobject_createErr1REQUIRES_VIOLATION, ldv_destroy_msgsErr3REQUIRES_VIOLATION, ldv_destroy_msgsErr4REQUIRES_VIOLATION, ldv_destroy_msgsErr0REQUIRES_VIOLATION, ldv_destroy_msgsErr5REQUIRES_VIOLATION, ldv_destroy_msgsErr2REQUIRES_VIOLATION, ldv_destroy_msgsErr1REQUIRES_VIOLATION, ldv_msg_fillErr0REQUIRES_VIOLATION, ldv_msg_fillErr5REQUIRES_VIOLATION, ldv_msg_fillErr1REQUIRES_VIOLATION, ldv_msg_fillErr2REQUIRES_VIOLATION, ldv_msg_fillErr3REQUIRES_VIOLATION, ldv_msg_fillErr4REQUIRES_VIOLATION, ldv_atomic_add_returnErr0REQUIRES_VIOLATION, ldv_atomic_add_returnErr2REQUIRES_VIOLATION, ldv_atomic_add_returnErr1REQUIRES_VIOLATION, ldv_atomic_add_returnErr3REQUIRES_VIOLATION, __ldv_list_delErr3REQUIRES_VIOLATION, __ldv_list_delErr1REQUIRES_VIOLATION, __ldv_list_delErr2REQUIRES_VIOLATION, __ldv_list_delErr0REQUIRES_VIOLATION, ldv_kobject_cleanupErr3ASSERT_VIOLATIONMEMORY_FREE, ldv_kobject_cleanupErr2ASSERT_VIOLATIONMEMORY_FREE, ldv_kobject_cleanupErr4ASSERT_VIOLATIONMEMORY_FREE, ldv_kobject_cleanupErr0REQUIRES_VIOLATION, ldv_kobject_cleanupErr5ASSERT_VIOLATIONMEMORY_FREE, ldv_kobject_cleanupErr1REQUIRES_VIOLATION, ldv_msg_freeErr3ASSERT_VIOLATIONMEMORY_FREE, ldv_msg_freeErr5ASSERT_VIOLATIONMEMORY_FREE, ldv_msg_freeErr2ASSERT_VIOLATIONMEMORY_FREE, ldv_msg_freeErr4ASSERT_VIOLATIONMEMORY_FREE, ldv_msg_freeErr0REQUIRES_VIOLATION, ldv_msg_freeErr1REQUIRES_VIOLATION, mainErr0ENSURES_VIOLATIONMEMORY_LEAK, LDV_INIT_LIST_HEADErr1REQUIRES_VIOLATION, LDV_INIT_LIST_HEADErr2REQUIRES_VIOLATION, LDV_INIT_LIST_HEADErr0REQUIRES_VIOLATION, LDV_INIT_LIST_HEADErr3REQUIRES_VIOLATION, ldv_list_delErr0REQUIRES_VIOLATION, ldv_list_delErr2REQUIRES_VIOLATION, ldv_list_delErr1REQUIRES_VIOLATION, ldv_list_delErr3REQUIRES_VIOLATION, __ldv_list_addErr4REQUIRES_VIOLATION, __ldv_list_addErr3REQUIRES_VIOLATION, __ldv_list_addErr1REQUIRES_VIOLATION, __ldv_list_addErr2REQUIRES_VIOLATION, __ldv_list_addErr7REQUIRES_VIOLATION, __ldv_list_addErr0REQUIRES_VIOLATION, __ldv_list_addErr5REQUIRES_VIOLATION, __ldv_list_addErr6REQUIRES_VIOLATION, ldv_dev_set_drvdataErr1REQUIRES_VIOLATION, ldv_dev_set_drvdataErr0REQUIRES_VIOLATION, ldv_atomic_sub_returnErr0REQUIRES_VIOLATION, ldv_atomic_sub_returnErr2REQUIRES_VIOLATION, ldv_atomic_sub_returnErr1REQUIRES_VIOLATION, ldv_atomic_sub_returnErr3REQUIRES_VIOLATION, ldv_list_add_tailErr1REQUIRES_VIOLATION, ldv_list_add_tailErr0REQUIRES_VIOLATION, ldv_dev_get_drvdataErr0REQUIRES_VIOLATION, ldv_dev_get_drvdataErr1REQUIRES_VIOLATION, ldv_msg_allocErr1REQUIRES_VIOLATION, ldv_msg_allocErr0REQUIRES_VIOLATION]=== [2018-11-28 11:25:52,926 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-28 11:25:52,926 INFO L82 PathProgramCache]: Analyzing trace with hash -1293726690, now seen corresponding path program 2 times [2018-11-28 11:25:52,926 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-28 11:25:52,926 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-28 11:25:52,927 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 11:25:52,927 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-28 11:25:52,927 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 11:25:52,940 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-28 11:25:53,051 INFO L134 CoverageAnalysis]: Checked inductivity of 105 backedges. 0 proven. 105 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-28 11:25:53,051 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-28 11:25:53,051 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_2ca7a644-5b0a-4f3d-9179-f30a2c52dfce/bin-2019/uautomizer/z3 Starting monitored process 15 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 15 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-28 11:25:53,058 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-11-28 11:25:53,112 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2018-11-28 11:25:53,112 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-11-28 11:25:53,115 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-28 11:25:53,130 INFO L134 CoverageAnalysis]: Checked inductivity of 105 backedges. 0 proven. 105 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-28 11:25:53,146 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-11-28 11:25:53,146 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [18, 18] total 19 [2018-11-28 11:25:53,146 INFO L459 AbstractCegarLoop]: Interpolant automaton has 19 states [2018-11-28 11:25:53,146 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 19 interpolants. [2018-11-28 11:25:53,147 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=155, Invalid=187, Unknown=0, NotChecked=0, Total=342 [2018-11-28 11:25:53,147 INFO L87 Difference]: Start difference. First operand 111 states and 111 transitions. Second operand 19 states. [2018-11-28 11:25:53,184 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-28 11:25:53,184 INFO L93 Difference]: Finished difference Result 114 states and 114 transitions. [2018-11-28 11:25:53,185 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 18 states. [2018-11-28 11:25:53,186 INFO L78 Accepts]: Start accepts. Automaton has 19 states. Word has length 110 [2018-11-28 11:25:53,186 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-28 11:25:53,186 INFO L225 Difference]: With dead ends: 114 [2018-11-28 11:25:53,186 INFO L226 Difference]: Without dead ends: 112 [2018-11-28 11:25:53,187 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 128 GetRequests, 110 SyntacticMatches, 0 SemanticMatches, 18 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 41 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=159, Invalid=221, Unknown=0, NotChecked=0, Total=380 [2018-11-28 11:25:53,187 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 112 states. [2018-11-28 11:25:53,188 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 112 to 112. [2018-11-28 11:25:53,188 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 112 states. [2018-11-28 11:25:53,189 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 112 states to 112 states and 112 transitions. [2018-11-28 11:25:53,189 INFO L78 Accepts]: Start accepts. Automaton has 112 states and 112 transitions. Word has length 110 [2018-11-28 11:25:53,189 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-28 11:25:53,189 INFO L480 AbstractCegarLoop]: Abstraction has 112 states and 112 transitions. [2018-11-28 11:25:53,189 INFO L481 AbstractCegarLoop]: Interpolant automaton has 19 states. [2018-11-28 11:25:53,189 INFO L276 IsEmpty]: Start isEmpty. Operand 112 states and 112 transitions. [2018-11-28 11:25:53,190 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 112 [2018-11-28 11:25:53,190 INFO L394 BasicCegarLoop]: Found error trace [2018-11-28 11:25:53,190 INFO L402 BasicCegarLoop]: trace histogram [15, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-28 11:25:53,190 INFO L423 AbstractCegarLoop]: === Iteration 32 === [ldv_kref_initErr1REQUIRES_VIOLATION, ldv_kref_initErr0REQUIRES_VIOLATION, ldv_list_addErr0REQUIRES_VIOLATION, ldv_list_addErr1REQUIRES_VIOLATION, ldv_kobject_createErr0REQUIRES_VIOLATION, ldv_kobject_createErr1REQUIRES_VIOLATION, ldv_destroy_msgsErr3REQUIRES_VIOLATION, ldv_destroy_msgsErr4REQUIRES_VIOLATION, ldv_destroy_msgsErr0REQUIRES_VIOLATION, ldv_destroy_msgsErr5REQUIRES_VIOLATION, ldv_destroy_msgsErr2REQUIRES_VIOLATION, ldv_destroy_msgsErr1REQUIRES_VIOLATION, ldv_msg_fillErr0REQUIRES_VIOLATION, ldv_msg_fillErr5REQUIRES_VIOLATION, ldv_msg_fillErr1REQUIRES_VIOLATION, ldv_msg_fillErr2REQUIRES_VIOLATION, ldv_msg_fillErr3REQUIRES_VIOLATION, ldv_msg_fillErr4REQUIRES_VIOLATION, ldv_atomic_add_returnErr0REQUIRES_VIOLATION, ldv_atomic_add_returnErr2REQUIRES_VIOLATION, ldv_atomic_add_returnErr1REQUIRES_VIOLATION, ldv_atomic_add_returnErr3REQUIRES_VIOLATION, __ldv_list_delErr3REQUIRES_VIOLATION, __ldv_list_delErr1REQUIRES_VIOLATION, __ldv_list_delErr2REQUIRES_VIOLATION, __ldv_list_delErr0REQUIRES_VIOLATION, ldv_kobject_cleanupErr3ASSERT_VIOLATIONMEMORY_FREE, ldv_kobject_cleanupErr2ASSERT_VIOLATIONMEMORY_FREE, ldv_kobject_cleanupErr4ASSERT_VIOLATIONMEMORY_FREE, ldv_kobject_cleanupErr0REQUIRES_VIOLATION, ldv_kobject_cleanupErr5ASSERT_VIOLATIONMEMORY_FREE, ldv_kobject_cleanupErr1REQUIRES_VIOLATION, ldv_msg_freeErr3ASSERT_VIOLATIONMEMORY_FREE, ldv_msg_freeErr5ASSERT_VIOLATIONMEMORY_FREE, ldv_msg_freeErr2ASSERT_VIOLATIONMEMORY_FREE, ldv_msg_freeErr4ASSERT_VIOLATIONMEMORY_FREE, ldv_msg_freeErr0REQUIRES_VIOLATION, ldv_msg_freeErr1REQUIRES_VIOLATION, mainErr0ENSURES_VIOLATIONMEMORY_LEAK, LDV_INIT_LIST_HEADErr1REQUIRES_VIOLATION, LDV_INIT_LIST_HEADErr2REQUIRES_VIOLATION, LDV_INIT_LIST_HEADErr0REQUIRES_VIOLATION, LDV_INIT_LIST_HEADErr3REQUIRES_VIOLATION, ldv_list_delErr0REQUIRES_VIOLATION, ldv_list_delErr2REQUIRES_VIOLATION, ldv_list_delErr1REQUIRES_VIOLATION, ldv_list_delErr3REQUIRES_VIOLATION, __ldv_list_addErr4REQUIRES_VIOLATION, __ldv_list_addErr3REQUIRES_VIOLATION, __ldv_list_addErr1REQUIRES_VIOLATION, __ldv_list_addErr2REQUIRES_VIOLATION, __ldv_list_addErr7REQUIRES_VIOLATION, __ldv_list_addErr0REQUIRES_VIOLATION, __ldv_list_addErr5REQUIRES_VIOLATION, __ldv_list_addErr6REQUIRES_VIOLATION, ldv_dev_set_drvdataErr1REQUIRES_VIOLATION, ldv_dev_set_drvdataErr0REQUIRES_VIOLATION, ldv_atomic_sub_returnErr0REQUIRES_VIOLATION, ldv_atomic_sub_returnErr2REQUIRES_VIOLATION, ldv_atomic_sub_returnErr1REQUIRES_VIOLATION, ldv_atomic_sub_returnErr3REQUIRES_VIOLATION, ldv_list_add_tailErr1REQUIRES_VIOLATION, ldv_list_add_tailErr0REQUIRES_VIOLATION, ldv_dev_get_drvdataErr0REQUIRES_VIOLATION, ldv_dev_get_drvdataErr1REQUIRES_VIOLATION, ldv_msg_allocErr1REQUIRES_VIOLATION, ldv_msg_allocErr0REQUIRES_VIOLATION]=== [2018-11-28 11:25:53,190 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-28 11:25:53,191 INFO L82 PathProgramCache]: Analyzing trace with hash 1420271433, now seen corresponding path program 3 times [2018-11-28 11:25:53,191 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-28 11:25:53,191 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-28 11:25:53,194 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 11:25:53,194 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-28 11:25:53,194 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 11:25:53,206 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-28 11:25:53,322 INFO L134 CoverageAnalysis]: Checked inductivity of 120 backedges. 0 proven. 120 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-28 11:25:53,323 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-28 11:25:53,323 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_2ca7a644-5b0a-4f3d-9179-f30a2c52dfce/bin-2019/uautomizer/z3 Starting monitored process 16 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 16 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-28 11:25:53,333 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-11-28 11:26:11,225 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 9 check-sat command(s) [2018-11-28 11:26:11,226 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-11-28 11:26:11,234 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-28 11:26:11,419 INFO L134 CoverageAnalysis]: Checked inductivity of 120 backedges. 0 proven. 120 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-28 11:26:11,436 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-11-28 11:26:11,437 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [19, 23] total 40 [2018-11-28 11:26:11,437 INFO L459 AbstractCegarLoop]: Interpolant automaton has 40 states [2018-11-28 11:26:11,437 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 40 interpolants. [2018-11-28 11:26:11,437 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=470, Invalid=1090, Unknown=0, NotChecked=0, Total=1560 [2018-11-28 11:26:11,437 INFO L87 Difference]: Start difference. First operand 112 states and 112 transitions. Second operand 40 states. [2018-11-28 11:26:11,575 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-28 11:26:11,575 INFO L93 Difference]: Finished difference Result 115 states and 115 transitions. [2018-11-28 11:26:11,575 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 23 states. [2018-11-28 11:26:11,575 INFO L78 Accepts]: Start accepts. Automaton has 40 states. Word has length 111 [2018-11-28 11:26:11,575 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-28 11:26:11,576 INFO L225 Difference]: With dead ends: 115 [2018-11-28 11:26:11,576 INFO L226 Difference]: Without dead ends: 113 [2018-11-28 11:26:11,576 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 131 GetRequests, 91 SyntacticMatches, 0 SemanticMatches, 40 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 616 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=512, Invalid=1210, Unknown=0, NotChecked=0, Total=1722 [2018-11-28 11:26:11,577 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 113 states. [2018-11-28 11:26:11,578 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 113 to 113. [2018-11-28 11:26:11,578 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 113 states. [2018-11-28 11:26:11,579 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 113 states to 113 states and 113 transitions. [2018-11-28 11:26:11,579 INFO L78 Accepts]: Start accepts. Automaton has 113 states and 113 transitions. Word has length 111 [2018-11-28 11:26:11,579 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-28 11:26:11,580 INFO L480 AbstractCegarLoop]: Abstraction has 113 states and 113 transitions. [2018-11-28 11:26:11,580 INFO L481 AbstractCegarLoop]: Interpolant automaton has 40 states. [2018-11-28 11:26:11,580 INFO L276 IsEmpty]: Start isEmpty. Operand 113 states and 113 transitions. [2018-11-28 11:26:11,581 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 113 [2018-11-28 11:26:11,581 INFO L394 BasicCegarLoop]: Found error trace [2018-11-28 11:26:11,581 INFO L402 BasicCegarLoop]: trace histogram [16, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-28 11:26:11,581 INFO L423 AbstractCegarLoop]: === Iteration 33 === [ldv_kref_initErr1REQUIRES_VIOLATION, ldv_kref_initErr0REQUIRES_VIOLATION, ldv_list_addErr0REQUIRES_VIOLATION, ldv_list_addErr1REQUIRES_VIOLATION, ldv_kobject_createErr0REQUIRES_VIOLATION, ldv_kobject_createErr1REQUIRES_VIOLATION, ldv_destroy_msgsErr3REQUIRES_VIOLATION, ldv_destroy_msgsErr4REQUIRES_VIOLATION, ldv_destroy_msgsErr0REQUIRES_VIOLATION, ldv_destroy_msgsErr5REQUIRES_VIOLATION, ldv_destroy_msgsErr2REQUIRES_VIOLATION, ldv_destroy_msgsErr1REQUIRES_VIOLATION, ldv_msg_fillErr0REQUIRES_VIOLATION, ldv_msg_fillErr5REQUIRES_VIOLATION, ldv_msg_fillErr1REQUIRES_VIOLATION, ldv_msg_fillErr2REQUIRES_VIOLATION, ldv_msg_fillErr3REQUIRES_VIOLATION, ldv_msg_fillErr4REQUIRES_VIOLATION, ldv_atomic_add_returnErr0REQUIRES_VIOLATION, ldv_atomic_add_returnErr2REQUIRES_VIOLATION, ldv_atomic_add_returnErr1REQUIRES_VIOLATION, ldv_atomic_add_returnErr3REQUIRES_VIOLATION, __ldv_list_delErr3REQUIRES_VIOLATION, __ldv_list_delErr1REQUIRES_VIOLATION, __ldv_list_delErr2REQUIRES_VIOLATION, __ldv_list_delErr0REQUIRES_VIOLATION, ldv_kobject_cleanupErr3ASSERT_VIOLATIONMEMORY_FREE, ldv_kobject_cleanupErr2ASSERT_VIOLATIONMEMORY_FREE, ldv_kobject_cleanupErr4ASSERT_VIOLATIONMEMORY_FREE, ldv_kobject_cleanupErr0REQUIRES_VIOLATION, ldv_kobject_cleanupErr5ASSERT_VIOLATIONMEMORY_FREE, ldv_kobject_cleanupErr1REQUIRES_VIOLATION, ldv_msg_freeErr3ASSERT_VIOLATIONMEMORY_FREE, ldv_msg_freeErr5ASSERT_VIOLATIONMEMORY_FREE, ldv_msg_freeErr2ASSERT_VIOLATIONMEMORY_FREE, ldv_msg_freeErr4ASSERT_VIOLATIONMEMORY_FREE, ldv_msg_freeErr0REQUIRES_VIOLATION, ldv_msg_freeErr1REQUIRES_VIOLATION, mainErr0ENSURES_VIOLATIONMEMORY_LEAK, LDV_INIT_LIST_HEADErr1REQUIRES_VIOLATION, LDV_INIT_LIST_HEADErr2REQUIRES_VIOLATION, LDV_INIT_LIST_HEADErr0REQUIRES_VIOLATION, LDV_INIT_LIST_HEADErr3REQUIRES_VIOLATION, ldv_list_delErr0REQUIRES_VIOLATION, ldv_list_delErr2REQUIRES_VIOLATION, ldv_list_delErr1REQUIRES_VIOLATION, ldv_list_delErr3REQUIRES_VIOLATION, __ldv_list_addErr4REQUIRES_VIOLATION, __ldv_list_addErr3REQUIRES_VIOLATION, __ldv_list_addErr1REQUIRES_VIOLATION, __ldv_list_addErr2REQUIRES_VIOLATION, __ldv_list_addErr7REQUIRES_VIOLATION, __ldv_list_addErr0REQUIRES_VIOLATION, __ldv_list_addErr5REQUIRES_VIOLATION, __ldv_list_addErr6REQUIRES_VIOLATION, ldv_dev_set_drvdataErr1REQUIRES_VIOLATION, ldv_dev_set_drvdataErr0REQUIRES_VIOLATION, ldv_atomic_sub_returnErr0REQUIRES_VIOLATION, ldv_atomic_sub_returnErr2REQUIRES_VIOLATION, ldv_atomic_sub_returnErr1REQUIRES_VIOLATION, ldv_atomic_sub_returnErr3REQUIRES_VIOLATION, ldv_list_add_tailErr1REQUIRES_VIOLATION, ldv_list_add_tailErr0REQUIRES_VIOLATION, ldv_dev_get_drvdataErr0REQUIRES_VIOLATION, ldv_dev_get_drvdataErr1REQUIRES_VIOLATION, ldv_msg_allocErr1REQUIRES_VIOLATION, ldv_msg_allocErr0REQUIRES_VIOLATION]=== [2018-11-28 11:26:11,581 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-28 11:26:11,582 INFO L82 PathProgramCache]: Analyzing trace with hash -345132674, now seen corresponding path program 4 times [2018-11-28 11:26:11,582 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-28 11:26:11,582 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-28 11:26:11,582 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 11:26:11,583 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-28 11:26:11,583 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 11:26:11,630 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-28 11:26:11,665 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-28 11:26:11,688 INFO L469 BasicCegarLoop]: Counterexample might be feasible [2018-11-28 11:26:11,700 WARN L416 cessorBacktranslator]: Generated EnsuresSpecification free ensures #res.base == #ptr.base && #res.offset == #ptr.offset; is not ensure(true) [2018-11-28 11:26:11,705 WARN L416 cessorBacktranslator]: Generated EnsuresSpecification ensures #valid == old(#valid); is not ensure(true) [2018-11-28 11:26:11,711 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: IntegerLiteral 17 could not be translated for associated CType STRUCT~~ldv_list_head?next~*ldv_list_head?prev~*ldv_list_head# [2018-11-28 11:26:11,711 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: IntegerLiteral 18 could not be translated for associated CType STRUCT~~ldv_list_head?next~*ldv_list_head?prev~*ldv_list_head# [2018-11-28 11:26:11,725 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction CFG 28.11 11:26:11 BoogieIcfgContainer [2018-11-28 11:26:11,725 INFO L132 PluginConnector]: ------------------------ END TraceAbstraction---------------------------- [2018-11-28 11:26:11,725 INFO L113 PluginConnector]: ------------------------Witness Printer---------------------------- [2018-11-28 11:26:11,725 INFO L271 PluginConnector]: Initializing Witness Printer... [2018-11-28 11:26:11,725 INFO L276 PluginConnector]: Witness Printer initialized [2018-11-28 11:26:11,726 INFO L185 PluginConnector]: Executing the observer RCFGCatcher from plugin Witness Printer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 28.11 11:25:38" (3/4) ... [2018-11-28 11:26:11,730 INFO L147 WitnessPrinter]: No result that supports witness generation found [2018-11-28 11:26:11,730 INFO L132 PluginConnector]: ------------------------ END Witness Printer---------------------------- [2018-11-28 11:26:11,730 INFO L168 Benchmark]: Toolchain (without parser) took 33896.22 ms. Allocated memory was 1.0 GB in the beginning and 1.4 GB in the end (delta: 359.1 MB). Free memory was 949.5 MB in the beginning and 916.1 MB in the end (delta: 33.5 MB). Peak memory consumption was 392.6 MB. Max. memory is 11.5 GB. [2018-11-28 11:26:11,732 INFO L168 Benchmark]: CDTParser took 0.12 ms. Allocated memory is still 1.0 GB. Free memory is still 979.6 MB. There was no memory consumed. Max. memory is 11.5 GB. [2018-11-28 11:26:11,732 INFO L168 Benchmark]: CACSL2BoogieTranslator took 406.99 ms. Allocated memory was 1.0 GB in the beginning and 1.2 GB in the end (delta: 124.8 MB). Free memory was 949.5 MB in the beginning and 1.1 GB in the end (delta: -151.0 MB). Peak memory consumption was 27.8 MB. Max. memory is 11.5 GB. [2018-11-28 11:26:11,732 INFO L168 Benchmark]: Boogie Preprocessor took 65.83 ms. Allocated memory is still 1.2 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 2.7 MB). Peak memory consumption was 2.7 MB. Max. memory is 11.5 GB. [2018-11-28 11:26:11,732 INFO L168 Benchmark]: RCFGBuilder took 682.85 ms. Allocated memory is still 1.2 GB. Free memory was 1.1 GB in the beginning and 998.2 MB in the end (delta: 99.7 MB). Peak memory consumption was 99.7 MB. Max. memory is 11.5 GB. [2018-11-28 11:26:11,733 INFO L168 Benchmark]: TraceAbstraction took 32732.85 ms. Allocated memory was 1.2 GB in the beginning and 1.4 GB in the end (delta: 234.4 MB). Free memory was 998.2 MB in the beginning and 916.1 MB in the end (delta: 82.1 MB). Peak memory consumption was 316.5 MB. Max. memory is 11.5 GB. [2018-11-28 11:26:11,733 INFO L168 Benchmark]: Witness Printer took 4.43 ms. Allocated memory is still 1.4 GB. Free memory is still 916.1 MB. There was no memory consumed. Max. memory is 11.5 GB. [2018-11-28 11:26:11,735 INFO L336 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.12 ms. Allocated memory is still 1.0 GB. Free memory is still 979.6 MB. There was no memory consumed. Max. memory is 11.5 GB. * CACSL2BoogieTranslator took 406.99 ms. Allocated memory was 1.0 GB in the beginning and 1.2 GB in the end (delta: 124.8 MB). Free memory was 949.5 MB in the beginning and 1.1 GB in the end (delta: -151.0 MB). Peak memory consumption was 27.8 MB. Max. memory is 11.5 GB. * Boogie Preprocessor took 65.83 ms. Allocated memory is still 1.2 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 2.7 MB). Peak memory consumption was 2.7 MB. Max. memory is 11.5 GB. * RCFGBuilder took 682.85 ms. Allocated memory is still 1.2 GB. Free memory was 1.1 GB in the beginning and 998.2 MB in the end (delta: 99.7 MB). Peak memory consumption was 99.7 MB. Max. memory is 11.5 GB. * TraceAbstraction took 32732.85 ms. Allocated memory was 1.2 GB in the beginning and 1.4 GB in the end (delta: 234.4 MB). Free memory was 998.2 MB in the beginning and 916.1 MB in the end (delta: 82.1 MB). Peak memory consumption was 316.5 MB. Max. memory is 11.5 GB. * Witness Printer took 4.43 ms. Allocated memory is still 1.4 GB. Free memory is still 916.1 MB. There was no memory consumed. Max. memory is 11.5 GB. * Results from de.uni_freiburg.informatik.ultimate.boogie.preprocessor: - GenericResult: Unfinished Backtranslation Generated EnsuresSpecification free ensures #res.base == #ptr.base && #res.offset == #ptr.offset; is not ensure(true) - GenericResult: Unfinished Backtranslation Generated EnsuresSpecification ensures #valid == old(#valid); is not ensure(true) * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: IntegerLiteral 17 could not be translated for associated CType STRUCT~~ldv_list_head?next~*ldv_list_head?prev~*ldv_list_head# - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: IntegerLiteral 18 could not be translated for associated CType STRUCT~~ldv_list_head?next~*ldv_list_head?prev~*ldv_list_head# * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - UnprovableResult [Line: 1443]: Unable to prove that all allocated memory was freed Unable to prove that all allocated memory was freed Reason: overapproximation of memtrack at line 1443. Possible FailurePath: [L1135] struct ldv_list_head ldv_global_msg_list = { &(ldv_global_msg_list), &(ldv_global_msg_list) }; VAL [\old(ldv_global_msg_list)=null, \old(ldv_global_msg_list)=null, ldv_global_msg_list={30:0}] [L1444] CALL entry_point() VAL [ldv_global_msg_list={30:0}] [L1436] struct ldv_kobject *kobj; VAL [ldv_global_msg_list={30:0}] [L1437] CALL, EXPR ldv_kobject_create() VAL [ldv_global_msg_list={30:0}] [L1406] struct ldv_kobject *kobj; VAL [ldv_global_msg_list={30:0}] [L1408] CALL, EXPR ldv_malloc(sizeof(*kobj)) VAL [\old(size)=16, ldv_global_msg_list={30:0}] [L1073] COND TRUE __VERIFIER_nondet_int() [L1074] return malloc(size); VAL [\old(size)=16, \result={26:0}, ldv_global_msg_list={30:0}, malloc(size)={26:0}, size=16] [L1408] RET, EXPR ldv_malloc(sizeof(*kobj)) VAL [ldv_global_msg_list={30:0}, ldv_malloc(sizeof(*kobj))={26:0}] [L1408] kobj = ldv_malloc(sizeof(*kobj)) [L1409] COND FALSE !(!kobj) VAL [kobj={26:0}, ldv_global_msg_list={30:0}] [L1411] FCALL memset(kobj, 0, sizeof(*kobj)) VAL [kobj={26:0}, ldv_global_msg_list={30:0}, memset(kobj, 0, sizeof(*kobj))={26:0}] [L1413] CALL ldv_kobject_init(kobj) VAL [kobj={26:0}, ldv_global_msg_list={30:0}] [L1394] COND FALSE !(!kobj) VAL [kobj={26:0}, kobj={26:0}, ldv_global_msg_list={30:0}] [L1398] CALL ldv_kobject_init_internal(kobj) VAL [kobj={26:0}, ldv_global_msg_list={30:0}] [L1380] COND FALSE !(!kobj) VAL [kobj={26:0}, kobj={26:0}, ldv_global_msg_list={30:0}] [L1382] CALL ldv_kref_init(&kobj->kref) VAL [kref={26:12}, ldv_global_msg_list={30:0}] [L1294] ((&kref->refcount)->counter) = (1) VAL [kref={26:12}, kref={26:12}, ldv_global_msg_list={30:0}] [L1382] RET ldv_kref_init(&kobj->kref) VAL [kobj={26:0}, kobj={26:0}, ldv_global_msg_list={30:0}] [L1383] CALL LDV_INIT_LIST_HEAD(&kobj->entry) VAL [ldv_global_msg_list={30:0}, list={26:4}] [L1099] list->next = list VAL [ldv_global_msg_list={30:0}, list={26:4}, list={26:4}] [L1100] list->prev = list VAL [ldv_global_msg_list={30:0}, list={26:4}, list={26:4}] [L1383] RET LDV_INIT_LIST_HEAD(&kobj->entry) VAL [kobj={26:0}, kobj={26:0}, ldv_global_msg_list={30:0}] [L1398] RET ldv_kobject_init_internal(kobj) VAL [kobj={26:0}, kobj={26:0}, ldv_global_msg_list={30:0}] [L1413] RET ldv_kobject_init(kobj) VAL [kobj={26:0}, ldv_global_msg_list={30:0}] [L1414] return kobj; VAL [\result={26:0}, kobj={26:0}, ldv_global_msg_list={30:0}] [L1437] RET, EXPR ldv_kobject_create() VAL [ldv_global_msg_list={30:0}, ldv_kobject_create()={26:0}] [L1437] kobj = ldv_kobject_create() [L1438] CALL ldv_kobject_get(kobj) VAL [kobj={26:0}, ldv_global_msg_list={30:0}] [L1373] COND TRUE \read(*kobj) VAL [kobj={26:0}, kobj={26:0}, ldv_global_msg_list={30:0}] [L1374] CALL ldv_kref_get(&kobj->kref) VAL [kref={26:12}, ldv_global_msg_list={30:0}] [L1308] CALL ldv_atomic_add_return(1, (&kref->refcount)) VAL [\old(i)=1, ldv_global_msg_list={30:0}, v={26:12}] [L1255] int temp; VAL [\old(i)=1, i=1, ldv_global_msg_list={30:0}, v={26:12}, v={26:12}] [L1256] EXPR v->counter VAL [\old(i)=1, i=1, ldv_global_msg_list={30:0}, v={26:12}, v={26:12}, v->counter=1] [L1256] temp = v->counter [L1257] temp += i VAL [\old(i)=1, i=1, ldv_global_msg_list={30:0}, temp=2, v={26:12}, v={26:12}] [L1258] v->counter = temp VAL [\old(i)=1, i=1, ldv_global_msg_list={30:0}, temp=2, v={26:12}, v={26:12}] [L1259] return temp; VAL [\old(i)=1, \result=2, i=1, ldv_global_msg_list={30:0}, temp=2, v={26:12}, v={26:12}] [L1308] RET ldv_atomic_add_return(1, (&kref->refcount)) VAL [kref={26:12}, kref={26:12}, ldv_atomic_add_return(1, (&kref->refcount))=2, ldv_global_msg_list={30:0}] [L1374] RET ldv_kref_get(&kobj->kref) VAL [kobj={26:0}, kobj={26:0}, ldv_global_msg_list={30:0}] [L1375] return kobj; VAL [\result={26:0}, kobj={26:0}, kobj={26:0}, ldv_global_msg_list={30:0}] [L1438] RET ldv_kobject_get(kobj) VAL [kobj={26:0}, ldv_global_msg_list={30:0}, ldv_kobject_get(kobj)={26:0}] [L1440] CALL ldv_kobject_put(kobj) VAL [kobj={26:0}, ldv_global_msg_list={30:0}] [L1361] COND TRUE \read(*kobj) VAL [kobj={26:0}, kobj={26:0}, ldv_global_msg_list={30:0}] [L1363] CALL ldv_kref_put(&kobj->kref, ldv_kobject_release) VAL [kref={26:12}, ldv_global_msg_list={30:0}, release={-1:0}] [L1313] CALL, EXPR ldv_kref_sub(kref, 1, release) VAL [\old(count)=1, kref={26:12}, ldv_global_msg_list={30:0}, release={-1:0}] [L1281] CALL, EXPR ldv_atomic_sub_return(((int) count), (&kref->refcount)) VAL [\old(i)=1, ldv_global_msg_list={30:0}, v={26:12}] [L1264] int temp; VAL [\old(i)=1, i=1, ldv_global_msg_list={30:0}, v={26:12}, v={26:12}] [L1265] EXPR v->counter VAL [\old(i)=1, i=1, ldv_global_msg_list={30:0}, v={26:12}, v={26:12}, v->counter=2] [L1265] temp = v->counter [L1266] temp -= i VAL [\old(i)=1, i=1, ldv_global_msg_list={30:0}, temp=1, v={26:12}, v={26:12}] [L1267] v->counter = temp VAL [\old(i)=1, i=1, ldv_global_msg_list={30:0}, temp=1, v={26:12}, v={26:12}] [L1268] return temp; VAL [\old(i)=1, \result=1, i=1, ldv_global_msg_list={30:0}, temp=1, v={26:12}, v={26:12}] [L1281] RET, EXPR ldv_atomic_sub_return(((int) count), (&kref->refcount)) VAL [\old(count)=1, count=1, kref={26:12}, kref={26:12}, ldv_atomic_sub_return(((int) count), (&kref->refcount))=1, ldv_global_msg_list={30:0}, release={-1:0}, release={-1:0}] [L1281] COND FALSE !((ldv_atomic_sub_return(((int) count), (&kref->refcount)) == 0)) [L1285] return 0; VAL [\old(count)=1, \result=0, count=1, kref={26:12}, kref={26:12}, ldv_global_msg_list={30:0}, release={-1:0}, release={-1:0}] [L1313] RET, EXPR ldv_kref_sub(kref, 1, release) VAL [kref={26:12}, kref={26:12}, ldv_global_msg_list={30:0}, ldv_kref_sub(kref, 1, release)=0, release={-1:0}, release={-1:0}] [L1313] return ldv_kref_sub(kref, 1, release); [L1363] RET ldv_kref_put(&kobj->kref, ldv_kobject_release) VAL [kobj={26:0}, kobj={26:0}, ldv_global_msg_list={30:0}, ldv_kref_put(&kobj->kref, ldv_kobject_release)=0] [L1440] RET ldv_kobject_put(kobj) VAL [kobj={26:0}, ldv_global_msg_list={30:0}] [L1444] RET entry_point() VAL [ldv_global_msg_list={30:0}] - StatisticsResult: Ultimate Automizer benchmark data CFG has 43 procedures, 311 locations, 67 error locations. UNSAFE Result, 32.6s OverallTime, 33 OverallIterations, 16 TraceHistogramMax, 7.1s AutomataDifference, 0.0s DeadEndRemovalTime, 0.0s HoareAnnotationTime, HoareTripleCheckerStatistics: 3887 SDtfs, 878 SDslu, 33527 SDs, 0 SdLazy, 11483 SolverSat, 218 SolverUnsat, 0 SolverUnknown, 0 SolverNotchecked, 4.3s Time, PredicateUnifierStatistics: 0 DeclaredPredicates, 1652 GetRequests, 1080 SyntacticMatches, 20 SemanticMatches, 552 ConstructedPredicates, 1 IntricatePredicates, 0 DeprecatedPredicates, 3544 ImplicationChecksByTransitivity, 6.2s Time, 0.0s BasicInterpolantAutomatonTime, BiggestAbstraction: size=171occurred in iteration=0, traceCheckStatistics: No data available, InterpolantConsolidationStatistics: No data available, PathInvariantsStatistics: No data available, 0/0 InterpolantCoveringCapability, TotalInterpolationStatistics: No data available, 0.0s AbstIntTime, 0 AbstIntIterations, 0 AbstIntStrong, NaN AbsIntWeakeningRatio, NaN AbsIntAvgWeakeningVarsNumRemoved, NaN AbsIntAvgWeakenedConjuncts, 0.0s DumpTime, AutomataMinimizationStatistics: 0.1s AutomataMinimizationTime, 32 MinimizatonAttempts, 108 StatesRemovedByMinimization, 10 NontrivialMinimizations, HoareAnnotationStatistics: No data available, RefinementEngineStatistics: TraceCheckStatistics: 0.2s SsaConstructionTime, 18.6s SatisfiabilityAnalysisTime, 5.5s InterpolantComputationTime, 3274 NumberOfCodeBlocks, 3232 NumberOfCodeBlocksAsserted, 57 NumberOfCheckSat, 3115 ConstructedInterpolants, 164 QuantifiedInterpolants, 566107 SizeOfPredicates, 110 NumberOfNonLiveVariables, 5947 ConjunctsInSsa, 568 ConjunctsInUnsatCore, 47 InterpolantComputations, 23 PerfectInterpolantSequences, 400/1557 InterpolantCoveringCapability, InvariantSynthesisStatistics: No data available, InterpolantConsolidationStatistics: No data available, ReuseStatistics: No data available RESULT: Ultimate could not prove your program: unable to determine feasibility of some traces Received shutdown request... ### Bit-precise run ### This is Ultimate 0.1.23-0cd3be1 [2018-11-28 11:26:13,173 INFO L170 SettingsManager]: Resetting all preferences to default values... [2018-11-28 11:26:13,174 INFO L174 SettingsManager]: Resetting UltimateCore preferences to default values [2018-11-28 11:26:13,183 INFO L177 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2018-11-28 11:26:13,183 INFO L174 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2018-11-28 11:26:13,184 INFO L174 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2018-11-28 11:26:13,184 INFO L174 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2018-11-28 11:26:13,186 INFO L174 SettingsManager]: Resetting LassoRanker preferences to default values [2018-11-28 11:26:13,187 INFO L174 SettingsManager]: Resetting Reaching Definitions preferences to default values [2018-11-28 11:26:13,188 INFO L174 SettingsManager]: Resetting SyntaxChecker preferences to default values [2018-11-28 11:26:13,188 INFO L177 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2018-11-28 11:26:13,189 INFO L174 SettingsManager]: Resetting LTL2Aut preferences to default values [2018-11-28 11:26:13,189 INFO L174 SettingsManager]: Resetting PEA to Boogie preferences to default values [2018-11-28 11:26:13,190 INFO L174 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2018-11-28 11:26:13,191 INFO L174 SettingsManager]: Resetting ChcToBoogie preferences to default values [2018-11-28 11:26:13,192 INFO L174 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2018-11-28 11:26:13,193 INFO L174 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2018-11-28 11:26:13,194 INFO L174 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2018-11-28 11:26:13,195 INFO L174 SettingsManager]: Resetting CodeCheck preferences to default values [2018-11-28 11:26:13,197 INFO L174 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2018-11-28 11:26:13,197 INFO L174 SettingsManager]: Resetting RCFGBuilder preferences to default values [2018-11-28 11:26:13,198 INFO L174 SettingsManager]: Resetting TraceAbstraction preferences to default values [2018-11-28 11:26:13,200 INFO L177 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2018-11-28 11:26:13,200 INFO L177 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2018-11-28 11:26:13,200 INFO L174 SettingsManager]: Resetting TreeAutomizer preferences to default values [2018-11-28 11:26:13,201 INFO L174 SettingsManager]: Resetting IcfgTransformer preferences to default values [2018-11-28 11:26:13,202 INFO L174 SettingsManager]: Resetting Boogie Printer preferences to default values [2018-11-28 11:26:13,202 INFO L174 SettingsManager]: Resetting ReqPrinter preferences to default values [2018-11-28 11:26:13,203 INFO L174 SettingsManager]: Resetting Witness Printer preferences to default values [2018-11-28 11:26:13,204 INFO L177 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2018-11-28 11:26:13,204 INFO L174 SettingsManager]: Resetting CDTParser preferences to default values [2018-11-28 11:26:13,205 INFO L177 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2018-11-28 11:26:13,205 INFO L177 SettingsManager]: ReqParser provides no preferences, ignoring... [2018-11-28 11:26:13,205 INFO L174 SettingsManager]: Resetting SmtParser preferences to default values [2018-11-28 11:26:13,206 INFO L174 SettingsManager]: Resetting Witness Parser preferences to default values [2018-11-28 11:26:13,206 INFO L181 SettingsManager]: Finished resetting all preferences to default values... [2018-11-28 11:26:13,206 INFO L98 SettingsManager]: Beginning loading settings from /tmp/vcloud-vcloud-master/worker/working_dir_2ca7a644-5b0a-4f3d-9179-f30a2c52dfce/bin-2019/uautomizer/config/svcomp-DerefFreeMemtrack-32bit-Automizer_Bitvector.epf [2018-11-28 11:26:13,217 INFO L110 SettingsManager]: Loading preferences was successful [2018-11-28 11:26:13,217 INFO L112 SettingsManager]: Preferences different from defaults after loading the file: [2018-11-28 11:26:13,217 INFO L131 SettingsManager]: Preferences of Boogie Procedure Inliner differ from their defaults: [2018-11-28 11:26:13,218 INFO L133 SettingsManager]: * ... calls to implemented procedures=ONLY_FOR_CONCURRENT_PROGRAMS [2018-11-28 11:26:13,218 INFO L131 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2018-11-28 11:26:13,218 INFO L133 SettingsManager]: * Create parallel compositions if possible=false [2018-11-28 11:26:13,218 INFO L133 SettingsManager]: * Use SBE=true [2018-11-28 11:26:13,219 INFO L131 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2018-11-28 11:26:13,219 INFO L133 SettingsManager]: * sizeof long=4 [2018-11-28 11:26:13,219 INFO L133 SettingsManager]: * Check unreachability of error function in SV-COMP mode=false [2018-11-28 11:26:13,219 INFO L133 SettingsManager]: * Overapproximate operations on floating types=true [2018-11-28 11:26:13,219 INFO L133 SettingsManager]: * sizeof POINTER=4 [2018-11-28 11:26:13,220 INFO L133 SettingsManager]: * Check division by zero=IGNORE [2018-11-28 11:26:13,220 INFO L133 SettingsManager]: * Check for the main procedure if all allocated memory was freed=true [2018-11-28 11:26:13,220 INFO L133 SettingsManager]: * Bitprecise bitfields=true [2018-11-28 11:26:13,221 INFO L133 SettingsManager]: * SV-COMP memtrack compatibility mode=true [2018-11-28 11:26:13,221 INFO L133 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=IGNORE [2018-11-28 11:26:13,221 INFO L133 SettingsManager]: * Use bitvectors instead of ints=true [2018-11-28 11:26:13,221 INFO L133 SettingsManager]: * Memory model=HoenickeLindenmann_4ByteResolution [2018-11-28 11:26:13,221 INFO L133 SettingsManager]: * sizeof long double=12 [2018-11-28 11:26:13,221 INFO L133 SettingsManager]: * Use constant arrays=true [2018-11-28 11:26:13,221 INFO L131 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2018-11-28 11:26:13,222 INFO L133 SettingsManager]: * Size of a code block=SequenceOfStatements [2018-11-28 11:26:13,222 INFO L133 SettingsManager]: * To the following directory=./dump/ [2018-11-28 11:26:13,222 INFO L133 SettingsManager]: * SMT solver=External_DefaultMode [2018-11-28 11:26:13,222 INFO L133 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2018-11-28 11:26:13,222 INFO L131 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2018-11-28 11:26:13,222 INFO L133 SettingsManager]: * Compute Interpolants along a Counterexample=FPandBP [2018-11-28 11:26:13,222 INFO L133 SettingsManager]: * Trace refinement strategy=WOLF [2018-11-28 11:26:13,222 INFO L133 SettingsManager]: * SMT solver=External_ModelsAndUnsatCoreMode [2018-11-28 11:26:13,223 INFO L133 SettingsManager]: * Command for external solver=cvc4 --incremental --rewrite-divk --print-success --lang smt [2018-11-28 11:26:13,223 INFO L133 SettingsManager]: * Logic for external solver=AUFBV Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud-vcloud-master/worker/working_dir_2ca7a644-5b0a-4f3d-9179-f30a2c52dfce/bin-2019/uautomizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(G valid-free) ) CHECK( init(main()), LTL(G valid-deref) ) CHECK( init(main()), LTL(G valid-memtrack) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> 4867b1d8e60a05de2199d52aa990071fe8bd647c [2018-11-28 11:26:13,249 INFO L81 nceAwareModelManager]: Repository-Root is: /tmp [2018-11-28 11:26:13,258 INFO L258 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2018-11-28 11:26:13,261 INFO L214 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2018-11-28 11:26:13,262 INFO L271 PluginConnector]: Initializing CDTParser... [2018-11-28 11:26:13,263 INFO L276 PluginConnector]: CDTParser initialized [2018-11-28 11:26:13,263 INFO L418 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud-vcloud-master/worker/working_dir_2ca7a644-5b0a-4f3d-9179-f30a2c52dfce/bin-2019/uautomizer/../../sv-benchmarks/c/ldv-memsafety/memleaks_test22_1_false-valid-memtrack_true-termination.i [2018-11-28 11:26:13,309 INFO L221 CDTParser]: Created temporary CDT project at /tmp/vcloud-vcloud-master/worker/working_dir_2ca7a644-5b0a-4f3d-9179-f30a2c52dfce/bin-2019/uautomizer/data/20178b434/4744d0468b23467b914c4d61392cc6cd/FLAG1a0003a88 [2018-11-28 11:26:13,702 INFO L307 CDTParser]: Found 1 translation units. [2018-11-28 11:26:13,703 INFO L161 CDTParser]: Scanning /tmp/vcloud-vcloud-master/worker/working_dir_2ca7a644-5b0a-4f3d-9179-f30a2c52dfce/sv-benchmarks/c/ldv-memsafety/memleaks_test22_1_false-valid-memtrack_true-termination.i [2018-11-28 11:26:13,712 INFO L355 CDTParser]: About to delete temporary CDT project at /tmp/vcloud-vcloud-master/worker/working_dir_2ca7a644-5b0a-4f3d-9179-f30a2c52dfce/bin-2019/uautomizer/data/20178b434/4744d0468b23467b914c4d61392cc6cd/FLAG1a0003a88 [2018-11-28 11:26:13,722 INFO L363 CDTParser]: Successfully deleted /tmp/vcloud-vcloud-master/worker/working_dir_2ca7a644-5b0a-4f3d-9179-f30a2c52dfce/bin-2019/uautomizer/data/20178b434/4744d0468b23467b914c4d61392cc6cd [2018-11-28 11:26:13,724 INFO L296 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2018-11-28 11:26:13,725 INFO L131 ToolchainWalker]: Walking toolchain with 5 elements. [2018-11-28 11:26:13,726 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2018-11-28 11:26:13,726 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2018-11-28 11:26:13,728 INFO L276 PluginConnector]: CACSL2BoogieTranslator initialized [2018-11-28 11:26:13,729 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 28.11 11:26:13" (1/1) ... [2018-11-28 11:26:13,730 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@72e2e544 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 11:26:13, skipping insertion in model container [2018-11-28 11:26:13,730 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 28.11 11:26:13" (1/1) ... [2018-11-28 11:26:13,735 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2018-11-28 11:26:13,765 INFO L176 MainTranslator]: Built tables and reachable declarations [2018-11-28 11:26:14,018 INFO L203 PostProcessor]: Analyzing one entry point: main [2018-11-28 11:26:14,080 INFO L191 MainTranslator]: Completed pre-run [2018-11-28 11:26:14,124 INFO L203 PostProcessor]: Analyzing one entry point: main [2018-11-28 11:26:14,170 INFO L195 MainTranslator]: Completed translation [2018-11-28 11:26:14,171 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 11:26:14 WrapperNode [2018-11-28 11:26:14,171 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2018-11-28 11:26:14,171 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2018-11-28 11:26:14,171 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2018-11-28 11:26:14,171 INFO L276 PluginConnector]: Boogie Preprocessor initialized [2018-11-28 11:26:14,179 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 11:26:14" (1/1) ... [2018-11-28 11:26:14,180 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 11:26:14" (1/1) ... [2018-11-28 11:26:14,191 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 11:26:14" (1/1) ... [2018-11-28 11:26:14,191 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 11:26:14" (1/1) ... [2018-11-28 11:26:14,208 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 11:26:14" (1/1) ... [2018-11-28 11:26:14,211 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 11:26:14" (1/1) ... [2018-11-28 11:26:14,214 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 11:26:14" (1/1) ... [2018-11-28 11:26:14,219 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2018-11-28 11:26:14,219 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2018-11-28 11:26:14,219 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2018-11-28 11:26:14,219 INFO L276 PluginConnector]: RCFGBuilder initialized [2018-11-28 11:26:14,220 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 11:26:14" (1/1) ... No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_2ca7a644-5b0a-4f3d-9179-f30a2c52dfce/bin-2019/uautomizer/z3 Starting monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2018-11-28 11:26:14,259 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.init [2018-11-28 11:26:14,260 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2018-11-28 11:26:14,260 INFO L138 BoogieDeclarations]: Found implementation of procedure ##fun~$Pointer$~TO~VOID [2018-11-28 11:26:14,260 INFO L138 BoogieDeclarations]: Found implementation of procedure __bswap_32 [2018-11-28 11:26:14,260 INFO L138 BoogieDeclarations]: Found implementation of procedure __bswap_64 [2018-11-28 11:26:14,260 INFO L138 BoogieDeclarations]: Found implementation of procedure ldv_nonpositive [2018-11-28 11:26:14,260 INFO L138 BoogieDeclarations]: Found implementation of procedure ldv_positive [2018-11-28 11:26:14,260 INFO L138 BoogieDeclarations]: Found implementation of procedure ldv_malloc [2018-11-28 11:26:14,261 INFO L138 BoogieDeclarations]: Found implementation of procedure ldv_zalloc [2018-11-28 11:26:14,261 INFO L138 BoogieDeclarations]: Found implementation of procedure LDV_INIT_LIST_HEAD [2018-11-28 11:26:14,261 INFO L138 BoogieDeclarations]: Found implementation of procedure __ldv_list_add [2018-11-28 11:26:14,261 INFO L138 BoogieDeclarations]: Found implementation of procedure __ldv_list_del [2018-11-28 11:26:14,261 INFO L138 BoogieDeclarations]: Found implementation of procedure ldv_list_add [2018-11-28 11:26:14,261 INFO L138 BoogieDeclarations]: Found implementation of procedure ldv_list_add_tail [2018-11-28 11:26:14,261 INFO L138 BoogieDeclarations]: Found implementation of procedure ldv_list_del [2018-11-28 11:26:14,262 INFO L138 BoogieDeclarations]: Found implementation of procedure ldv_msg_alloc [2018-11-28 11:26:14,262 INFO L138 BoogieDeclarations]: Found implementation of procedure ldv_msg_fill [2018-11-28 11:26:14,262 INFO L138 BoogieDeclarations]: Found implementation of procedure ldv_msg_free [2018-11-28 11:26:14,262 INFO L138 BoogieDeclarations]: Found implementation of procedure ldv_submit_msg [2018-11-28 11:26:14,262 INFO L138 BoogieDeclarations]: Found implementation of procedure ldv_destroy_msgs [2018-11-28 11:26:14,262 INFO L138 BoogieDeclarations]: Found implementation of procedure ldv_dev_get_drvdata [2018-11-28 11:26:14,262 INFO L138 BoogieDeclarations]: Found implementation of procedure ldv_dev_set_drvdata [2018-11-28 11:26:14,262 INFO L138 BoogieDeclarations]: Found implementation of procedure ldv_atomic_add_return [2018-11-28 11:26:14,263 INFO L138 BoogieDeclarations]: Found implementation of procedure ldv_atomic_sub_return [2018-11-28 11:26:14,263 INFO L138 BoogieDeclarations]: Found implementation of procedure ldv_kref_sub [2018-11-28 11:26:14,263 INFO L138 BoogieDeclarations]: Found implementation of procedure ldv_kref_init [2018-11-28 11:26:14,263 INFO L138 BoogieDeclarations]: Found implementation of procedure ldv_kref_get [2018-11-28 11:26:14,263 INFO L138 BoogieDeclarations]: Found implementation of procedure ldv_kref_put [2018-11-28 11:26:14,263 INFO L138 BoogieDeclarations]: Found implementation of procedure ldv_kobject_del [2018-11-28 11:26:14,263 INFO L138 BoogieDeclarations]: Found implementation of procedure ldv_kobject_cleanup [2018-11-28 11:26:14,263 INFO L138 BoogieDeclarations]: Found implementation of procedure ldv_kobject_release [2018-11-28 11:26:14,263 INFO L138 BoogieDeclarations]: Found implementation of procedure ldv_kobject_put [2018-11-28 11:26:14,263 INFO L138 BoogieDeclarations]: Found implementation of procedure ldv_kobject_get [2018-11-28 11:26:14,263 INFO L138 BoogieDeclarations]: Found implementation of procedure ldv_kobject_init_internal [2018-11-28 11:26:14,264 INFO L138 BoogieDeclarations]: Found implementation of procedure ldv_kobject_init [2018-11-28 11:26:14,264 INFO L138 BoogieDeclarations]: Found implementation of procedure ldv_kobject_create [2018-11-28 11:26:14,264 INFO L138 BoogieDeclarations]: Found implementation of procedure f [2018-11-28 11:26:14,264 INFO L138 BoogieDeclarations]: Found implementation of procedure g [2018-11-28 11:26:14,264 INFO L138 BoogieDeclarations]: Found implementation of procedure entry_point [2018-11-28 11:26:14,264 INFO L138 BoogieDeclarations]: Found implementation of procedure main [2018-11-28 11:26:14,264 INFO L138 BoogieDeclarations]: Found implementation of procedure #Ultimate.C_memset [2018-11-28 11:26:14,264 INFO L138 BoogieDeclarations]: Found implementation of procedure #Ultimate.meminit [2018-11-28 11:26:14,264 INFO L138 BoogieDeclarations]: Found implementation of procedure #Ultimate.C_memcpy [2018-11-28 11:26:14,264 INFO L130 BoogieDeclarations]: Found specification of procedure __bswap_32 [2018-11-28 11:26:14,264 INFO L130 BoogieDeclarations]: Found specification of procedure __bswap_64 [2018-11-28 11:26:14,264 INFO L130 BoogieDeclarations]: Found specification of procedure __ctype_get_mb_cur_max [2018-11-28 11:26:14,265 INFO L130 BoogieDeclarations]: Found specification of procedure atof [2018-11-28 11:26:14,265 INFO L130 BoogieDeclarations]: Found specification of procedure atoi [2018-11-28 11:26:14,265 INFO L130 BoogieDeclarations]: Found specification of procedure atol [2018-11-28 11:26:14,265 INFO L130 BoogieDeclarations]: Found specification of procedure atoll [2018-11-28 11:26:14,265 INFO L130 BoogieDeclarations]: Found specification of procedure strtod [2018-11-28 11:26:14,265 INFO L130 BoogieDeclarations]: Found specification of procedure strtof [2018-11-28 11:26:14,265 INFO L130 BoogieDeclarations]: Found specification of procedure strtold [2018-11-28 11:26:14,265 INFO L130 BoogieDeclarations]: Found specification of procedure strtol [2018-11-28 11:26:14,265 INFO L130 BoogieDeclarations]: Found specification of procedure strtoul [2018-11-28 11:26:14,265 INFO L130 BoogieDeclarations]: Found specification of procedure strtoq [2018-11-28 11:26:14,265 INFO L130 BoogieDeclarations]: Found specification of procedure strtouq [2018-11-28 11:26:14,265 INFO L130 BoogieDeclarations]: Found specification of procedure strtoll [2018-11-28 11:26:14,265 INFO L130 BoogieDeclarations]: Found specification of procedure strtoull [2018-11-28 11:26:14,265 INFO L130 BoogieDeclarations]: Found specification of procedure l64a [2018-11-28 11:26:14,265 INFO L130 BoogieDeclarations]: Found specification of procedure a64l [2018-11-28 11:26:14,265 INFO L130 BoogieDeclarations]: Found specification of procedure select [2018-11-28 11:26:14,266 INFO L130 BoogieDeclarations]: Found specification of procedure pselect [2018-11-28 11:26:14,266 INFO L130 BoogieDeclarations]: Found specification of procedure gnu_dev_major [2018-11-28 11:26:14,266 INFO L130 BoogieDeclarations]: Found specification of procedure gnu_dev_minor [2018-11-28 11:26:14,266 INFO L130 BoogieDeclarations]: Found specification of procedure gnu_dev_makedev [2018-11-28 11:26:14,266 INFO L130 BoogieDeclarations]: Found specification of procedure random [2018-11-28 11:26:14,266 INFO L130 BoogieDeclarations]: Found specification of procedure srandom [2018-11-28 11:26:14,266 INFO L130 BoogieDeclarations]: Found specification of procedure initstate [2018-11-28 11:26:14,266 INFO L130 BoogieDeclarations]: Found specification of procedure setstate [2018-11-28 11:26:14,266 INFO L130 BoogieDeclarations]: Found specification of procedure random_r [2018-11-28 11:26:14,266 INFO L130 BoogieDeclarations]: Found specification of procedure srandom_r [2018-11-28 11:26:14,266 INFO L130 BoogieDeclarations]: Found specification of procedure initstate_r [2018-11-28 11:26:14,266 INFO L130 BoogieDeclarations]: Found specification of procedure setstate_r [2018-11-28 11:26:14,266 INFO L130 BoogieDeclarations]: Found specification of procedure rand [2018-11-28 11:26:14,267 INFO L130 BoogieDeclarations]: Found specification of procedure srand [2018-11-28 11:26:14,267 INFO L130 BoogieDeclarations]: Found specification of procedure rand_r [2018-11-28 11:26:14,267 INFO L130 BoogieDeclarations]: Found specification of procedure drand48 [2018-11-28 11:26:14,267 INFO L130 BoogieDeclarations]: Found specification of procedure erand48 [2018-11-28 11:26:14,267 INFO L130 BoogieDeclarations]: Found specification of procedure lrand48 [2018-11-28 11:26:14,267 INFO L130 BoogieDeclarations]: Found specification of procedure nrand48 [2018-11-28 11:26:14,267 INFO L130 BoogieDeclarations]: Found specification of procedure mrand48 [2018-11-28 11:26:14,267 INFO L130 BoogieDeclarations]: Found specification of procedure jrand48 [2018-11-28 11:26:14,267 INFO L130 BoogieDeclarations]: Found specification of procedure srand48 [2018-11-28 11:26:14,267 INFO L130 BoogieDeclarations]: Found specification of procedure seed48 [2018-11-28 11:26:14,268 INFO L130 BoogieDeclarations]: Found specification of procedure lcong48 [2018-11-28 11:26:14,268 INFO L130 BoogieDeclarations]: Found specification of procedure drand48_r [2018-11-28 11:26:14,268 INFO L130 BoogieDeclarations]: Found specification of procedure erand48_r [2018-11-28 11:26:14,268 INFO L130 BoogieDeclarations]: Found specification of procedure lrand48_r [2018-11-28 11:26:14,268 INFO L130 BoogieDeclarations]: Found specification of procedure nrand48_r [2018-11-28 11:26:14,268 INFO L130 BoogieDeclarations]: Found specification of procedure mrand48_r [2018-11-28 11:26:14,268 INFO L130 BoogieDeclarations]: Found specification of procedure jrand48_r [2018-11-28 11:26:14,268 INFO L130 BoogieDeclarations]: Found specification of procedure srand48_r [2018-11-28 11:26:14,268 INFO L130 BoogieDeclarations]: Found specification of procedure seed48_r [2018-11-28 11:26:14,269 INFO L130 BoogieDeclarations]: Found specification of procedure lcong48_r [2018-11-28 11:26:14,269 INFO L130 BoogieDeclarations]: Found specification of procedure malloc [2018-11-28 11:26:14,269 INFO L130 BoogieDeclarations]: Found specification of procedure calloc [2018-11-28 11:26:14,269 INFO L130 BoogieDeclarations]: Found specification of procedure realloc [2018-11-28 11:26:14,269 INFO L130 BoogieDeclarations]: Found specification of procedure free [2018-11-28 11:26:14,269 INFO L130 BoogieDeclarations]: Found specification of procedure cfree [2018-11-28 11:26:14,269 INFO L130 BoogieDeclarations]: Found specification of procedure alloca [2018-11-28 11:26:14,269 INFO L130 BoogieDeclarations]: Found specification of procedure valloc [2018-11-28 11:26:14,269 INFO L130 BoogieDeclarations]: Found specification of procedure posix_memalign [2018-11-28 11:26:14,269 INFO L130 BoogieDeclarations]: Found specification of procedure abort [2018-11-28 11:26:14,270 INFO L130 BoogieDeclarations]: Found specification of procedure atexit [2018-11-28 11:26:14,270 INFO L130 BoogieDeclarations]: Found specification of procedure on_exit [2018-11-28 11:26:14,270 INFO L130 BoogieDeclarations]: Found specification of procedure exit [2018-11-28 11:26:14,270 INFO L130 BoogieDeclarations]: Found specification of procedure _Exit [2018-11-28 11:26:14,270 INFO L130 BoogieDeclarations]: Found specification of procedure getenv [2018-11-28 11:26:14,270 INFO L130 BoogieDeclarations]: Found specification of procedure putenv [2018-11-28 11:26:14,270 INFO L130 BoogieDeclarations]: Found specification of procedure setenv [2018-11-28 11:26:14,270 INFO L130 BoogieDeclarations]: Found specification of procedure unsetenv [2018-11-28 11:26:14,270 INFO L130 BoogieDeclarations]: Found specification of procedure clearenv [2018-11-28 11:26:14,271 INFO L130 BoogieDeclarations]: Found specification of procedure mktemp [2018-11-28 11:26:14,271 INFO L130 BoogieDeclarations]: Found specification of procedure mkstemp [2018-11-28 11:26:14,271 INFO L130 BoogieDeclarations]: Found specification of procedure mkstemps [2018-11-28 11:26:14,271 INFO L130 BoogieDeclarations]: Found specification of procedure mkdtemp [2018-11-28 11:26:14,271 INFO L130 BoogieDeclarations]: Found specification of procedure system [2018-11-28 11:26:14,271 INFO L130 BoogieDeclarations]: Found specification of procedure realpath [2018-11-28 11:26:14,271 INFO L130 BoogieDeclarations]: Found specification of procedure bsearch [2018-11-28 11:26:14,271 INFO L130 BoogieDeclarations]: Found specification of procedure qsort [2018-11-28 11:26:14,271 INFO L130 BoogieDeclarations]: Found specification of procedure abs [2018-11-28 11:26:14,271 INFO L130 BoogieDeclarations]: Found specification of procedure labs [2018-11-28 11:26:14,272 INFO L130 BoogieDeclarations]: Found specification of procedure llabs [2018-11-28 11:26:14,272 INFO L130 BoogieDeclarations]: Found specification of procedure div [2018-11-28 11:26:14,272 INFO L130 BoogieDeclarations]: Found specification of procedure ldiv [2018-11-28 11:26:14,272 INFO L130 BoogieDeclarations]: Found specification of procedure lldiv [2018-11-28 11:26:14,272 INFO L130 BoogieDeclarations]: Found specification of procedure ecvt [2018-11-28 11:26:14,272 INFO L130 BoogieDeclarations]: Found specification of procedure fcvt [2018-11-28 11:26:14,272 INFO L130 BoogieDeclarations]: Found specification of procedure gcvt [2018-11-28 11:26:14,272 INFO L130 BoogieDeclarations]: Found specification of procedure qecvt [2018-11-28 11:26:14,272 INFO L130 BoogieDeclarations]: Found specification of procedure qfcvt [2018-11-28 11:26:14,272 INFO L130 BoogieDeclarations]: Found specification of procedure qgcvt [2018-11-28 11:26:14,273 INFO L130 BoogieDeclarations]: Found specification of procedure ecvt_r [2018-11-28 11:26:14,273 INFO L130 BoogieDeclarations]: Found specification of procedure fcvt_r [2018-11-28 11:26:14,273 INFO L130 BoogieDeclarations]: Found specification of procedure qecvt_r [2018-11-28 11:26:14,273 INFO L130 BoogieDeclarations]: Found specification of procedure qfcvt_r [2018-11-28 11:26:14,273 INFO L130 BoogieDeclarations]: Found specification of procedure mblen [2018-11-28 11:26:14,273 INFO L130 BoogieDeclarations]: Found specification of procedure mbtowc [2018-11-28 11:26:14,273 INFO L130 BoogieDeclarations]: Found specification of procedure wctomb [2018-11-28 11:26:14,273 INFO L130 BoogieDeclarations]: Found specification of procedure mbstowcs [2018-11-28 11:26:14,273 INFO L130 BoogieDeclarations]: Found specification of procedure wcstombs [2018-11-28 11:26:14,273 INFO L130 BoogieDeclarations]: Found specification of procedure rpmatch [2018-11-28 11:26:14,274 INFO L130 BoogieDeclarations]: Found specification of procedure getsubopt [2018-11-28 11:26:14,274 INFO L130 BoogieDeclarations]: Found specification of procedure getloadavg [2018-11-28 11:26:14,274 INFO L130 BoogieDeclarations]: Found specification of procedure kfree [2018-11-28 11:26:14,274 INFO L130 BoogieDeclarations]: Found specification of procedure __VERIFIER_nondet_int [2018-11-28 11:26:14,274 INFO L130 BoogieDeclarations]: Found specification of procedure __VERIFIER_nondet_pointer [2018-11-28 11:26:14,274 INFO L130 BoogieDeclarations]: Found specification of procedure ldv_nonpositive [2018-11-28 11:26:14,274 INFO L130 BoogieDeclarations]: Found specification of procedure ldv_positive [2018-11-28 11:26:14,274 INFO L130 BoogieDeclarations]: Found specification of procedure memcpy [2018-11-28 11:26:14,274 INFO L130 BoogieDeclarations]: Found specification of procedure memset [2018-11-28 11:26:14,275 INFO L130 BoogieDeclarations]: Found specification of procedure ldv_malloc [2018-11-28 11:26:14,275 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.alloc [2018-11-28 11:26:14,275 INFO L130 BoogieDeclarations]: Found specification of procedure ldv_zalloc [2018-11-28 11:26:14,275 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.meminit [2018-11-28 11:26:14,275 INFO L130 BoogieDeclarations]: Found specification of procedure LDV_INIT_LIST_HEAD [2018-11-28 11:26:14,275 INFO L130 BoogieDeclarations]: Found specification of procedure write~$Pointer$ [2018-11-28 11:26:14,275 INFO L130 BoogieDeclarations]: Found specification of procedure __ldv_list_add [2018-11-28 11:26:14,275 INFO L130 BoogieDeclarations]: Found specification of procedure __ldv_list_del [2018-11-28 11:26:14,275 INFO L130 BoogieDeclarations]: Found specification of procedure ldv_list_add [2018-11-28 11:26:14,275 INFO L130 BoogieDeclarations]: Found specification of procedure read~$Pointer$ [2018-11-28 11:26:14,276 INFO L130 BoogieDeclarations]: Found specification of procedure ldv_list_add_tail [2018-11-28 11:26:14,276 INFO L130 BoogieDeclarations]: Found specification of procedure ldv_list_del [2018-11-28 11:26:14,276 INFO L130 BoogieDeclarations]: Found specification of procedure ldv_msg_alloc [2018-11-28 11:26:14,276 INFO L130 BoogieDeclarations]: Found specification of procedure ldv_msg_fill [2018-11-28 11:26:14,276 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.C_memcpy [2018-11-28 11:26:14,276 INFO L130 BoogieDeclarations]: Found specification of procedure ldv_msg_free [2018-11-28 11:26:14,276 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.dealloc [2018-11-28 11:26:14,276 INFO L130 BoogieDeclarations]: Found specification of procedure ldv_submit_msg [2018-11-28 11:26:14,276 INFO L130 BoogieDeclarations]: Found specification of procedure ldv_destroy_msgs [2018-11-28 11:26:14,277 INFO L130 BoogieDeclarations]: Found specification of procedure ldv_dev_get_drvdata [2018-11-28 11:26:14,277 INFO L130 BoogieDeclarations]: Found specification of procedure ldv_dev_set_drvdata [2018-11-28 11:26:14,277 INFO L130 BoogieDeclarations]: Found specification of procedure ldv_atomic_add_return [2018-11-28 11:26:14,277 INFO L130 BoogieDeclarations]: Found specification of procedure read~intINTTYPE4 [2018-11-28 11:26:14,277 INFO L130 BoogieDeclarations]: Found specification of procedure write~intINTTYPE4 [2018-11-28 11:26:14,277 INFO L130 BoogieDeclarations]: Found specification of procedure ldv_atomic_sub_return [2018-11-28 11:26:14,277 INFO L130 BoogieDeclarations]: Found specification of procedure ldv_kref_sub [2018-11-28 11:26:14,277 INFO L130 BoogieDeclarations]: Found specification of procedure ##fun~$Pointer$~TO~VOID [2018-11-28 11:26:14,277 INFO L130 BoogieDeclarations]: Found specification of procedure ldv_kref_init [2018-11-28 11:26:14,277 INFO L130 BoogieDeclarations]: Found specification of procedure ldv_kref_get [2018-11-28 11:26:14,278 INFO L130 BoogieDeclarations]: Found specification of procedure ldv_kref_put [2018-11-28 11:26:14,278 INFO L130 BoogieDeclarations]: Found specification of procedure ldv_kobject_del [2018-11-28 11:26:14,278 INFO L130 BoogieDeclarations]: Found specification of procedure ldv_kobject_cleanup [2018-11-28 11:26:14,278 INFO L130 BoogieDeclarations]: Found specification of procedure ldv_kobject_release [2018-11-28 11:26:14,278 INFO L130 BoogieDeclarations]: Found specification of procedure ldv_kobject_put [2018-11-28 11:26:14,278 INFO L130 BoogieDeclarations]: Found specification of procedure ldv_kobject_get [2018-11-28 11:26:14,278 INFO L130 BoogieDeclarations]: Found specification of procedure ldv_kobject_init_internal [2018-11-28 11:26:14,278 INFO L130 BoogieDeclarations]: Found specification of procedure ldv_kobject_init [2018-11-28 11:26:14,278 INFO L130 BoogieDeclarations]: Found specification of procedure ldv_kobject_create [2018-11-28 11:26:14,279 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.C_memset [2018-11-28 11:26:14,279 INFO L130 BoogieDeclarations]: Found specification of procedure f [2018-11-28 11:26:14,279 INFO L130 BoogieDeclarations]: Found specification of procedure g [2018-11-28 11:26:14,279 INFO L130 BoogieDeclarations]: Found specification of procedure entry_point [2018-11-28 11:26:14,279 INFO L130 BoogieDeclarations]: Found specification of procedure main [2018-11-28 11:26:14,279 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.init [2018-11-28 11:26:14,279 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~$Pointer$ [2018-11-28 11:26:14,279 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2018-11-28 11:26:14,279 INFO L130 BoogieDeclarations]: Found specification of procedure write~unchecked~intINTTYPE4 [2018-11-28 11:26:14,279 INFO L130 BoogieDeclarations]: Found specification of procedure read~unchecked~intINTTYPE4 [2018-11-28 11:26:14,280 INFO L130 BoogieDeclarations]: Found specification of procedure write~unchecked~$Pointer$ [2018-11-28 11:26:14,280 INFO L130 BoogieDeclarations]: Found specification of procedure read~unchecked~$Pointer$ [2018-11-28 11:26:14,647 WARN L615 $ProcedureCfgBuilder]: Label in the middle of a codeblock. [2018-11-28 11:26:14,947 WARN L615 $ProcedureCfgBuilder]: Label in the middle of a codeblock. [2018-11-28 11:26:15,295 INFO L275 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2018-11-28 11:26:15,295 INFO L280 CfgBuilder]: Removed 1 assue(true) statements. [2018-11-28 11:26:15,295 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 28.11 11:26:15 BoogieIcfgContainer [2018-11-28 11:26:15,295 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2018-11-28 11:26:15,296 INFO L113 PluginConnector]: ------------------------TraceAbstraction---------------------------- [2018-11-28 11:26:15,296 INFO L271 PluginConnector]: Initializing TraceAbstraction... [2018-11-28 11:26:15,299 INFO L276 PluginConnector]: TraceAbstraction initialized [2018-11-28 11:26:15,299 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "CDTParser AST 28.11 11:26:13" (1/3) ... [2018-11-28 11:26:15,300 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@419a1af0 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 28.11 11:26:15, skipping insertion in model container [2018-11-28 11:26:15,300 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 11:26:14" (2/3) ... [2018-11-28 11:26:15,300 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@419a1af0 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 28.11 11:26:15, skipping insertion in model container [2018-11-28 11:26:15,301 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 28.11 11:26:15" (3/3) ... [2018-11-28 11:26:15,302 INFO L112 eAbstractionObserver]: Analyzing ICFG memleaks_test22_1_false-valid-memtrack_true-termination.i [2018-11-28 11:26:15,309 INFO L156 ceAbstractionStarter]: Automizer settings: Hoare:false NWA Interpolation:FPandBP Determinization: PREDICATE_ABSTRACTION [2018-11-28 11:26:15,316 INFO L168 ceAbstractionStarter]: Appying trace abstraction to program that has 67 error locations. [2018-11-28 11:26:15,329 INFO L257 AbstractCegarLoop]: Starting to check reachability of 67 error locations. [2018-11-28 11:26:15,349 INFO L133 ementStrategyFactory]: Using default assertion order modulation [2018-11-28 11:26:15,350 INFO L382 AbstractCegarLoop]: Interprodecural is true [2018-11-28 11:26:15,350 INFO L383 AbstractCegarLoop]: Hoare is false [2018-11-28 11:26:15,350 INFO L384 AbstractCegarLoop]: Compute interpolants for FPandBP [2018-11-28 11:26:15,350 INFO L385 AbstractCegarLoop]: Backedges is STRAIGHT_LINE [2018-11-28 11:26:15,350 INFO L386 AbstractCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2018-11-28 11:26:15,350 INFO L387 AbstractCegarLoop]: Difference is false [2018-11-28 11:26:15,351 INFO L388 AbstractCegarLoop]: Minimize is MINIMIZE_SEVPA [2018-11-28 11:26:15,351 INFO L393 AbstractCegarLoop]: ======== Iteration 0==of CEGAR loop == AllErrorsAtOnce======== [2018-11-28 11:26:15,365 INFO L276 IsEmpty]: Start isEmpty. Operand 170 states. [2018-11-28 11:26:15,372 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 18 [2018-11-28 11:26:15,372 INFO L394 BasicCegarLoop]: Found error trace [2018-11-28 11:26:15,372 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-28 11:26:15,374 INFO L423 AbstractCegarLoop]: === Iteration 1 === [ldv_kref_initErr0REQUIRES_VIOLATION, ldv_kref_initErr1REQUIRES_VIOLATION, ldv_list_addErr1REQUIRES_VIOLATION, ldv_list_addErr0REQUIRES_VIOLATION, ldv_kobject_createErr1REQUIRES_VIOLATION, ldv_kobject_createErr0REQUIRES_VIOLATION, ldv_destroy_msgsErr5REQUIRES_VIOLATION, ldv_destroy_msgsErr0REQUIRES_VIOLATION, ldv_destroy_msgsErr4REQUIRES_VIOLATION, ldv_destroy_msgsErr2REQUIRES_VIOLATION, ldv_destroy_msgsErr3REQUIRES_VIOLATION, ldv_destroy_msgsErr1REQUIRES_VIOLATION, ldv_msg_fillErr1REQUIRES_VIOLATION, ldv_msg_fillErr3REQUIRES_VIOLATION, ldv_msg_fillErr2REQUIRES_VIOLATION, ldv_msg_fillErr4REQUIRES_VIOLATION, ldv_msg_fillErr0REQUIRES_VIOLATION, ldv_msg_fillErr5REQUIRES_VIOLATION, ldv_atomic_add_returnErr2REQUIRES_VIOLATION, ldv_atomic_add_returnErr3REQUIRES_VIOLATION, ldv_atomic_add_returnErr1REQUIRES_VIOLATION, ldv_atomic_add_returnErr0REQUIRES_VIOLATION, __ldv_list_delErr0REQUIRES_VIOLATION, __ldv_list_delErr3REQUIRES_VIOLATION, __ldv_list_delErr2REQUIRES_VIOLATION, __ldv_list_delErr1REQUIRES_VIOLATION, ldv_kobject_cleanupErr2ASSERT_VIOLATIONMEMORY_FREE, ldv_kobject_cleanupErr0REQUIRES_VIOLATION, ldv_kobject_cleanupErr4ASSERT_VIOLATIONMEMORY_FREE, ldv_kobject_cleanupErr3ASSERT_VIOLATIONMEMORY_FREE, ldv_kobject_cleanupErr5ASSERT_VIOLATIONMEMORY_FREE, ldv_kobject_cleanupErr1REQUIRES_VIOLATION, ldv_msg_freeErr3ASSERT_VIOLATIONMEMORY_FREE, ldv_msg_freeErr5ASSERT_VIOLATIONMEMORY_FREE, ldv_msg_freeErr0REQUIRES_VIOLATION, ldv_msg_freeErr2ASSERT_VIOLATIONMEMORY_FREE, ldv_msg_freeErr1REQUIRES_VIOLATION, ldv_msg_freeErr4ASSERT_VIOLATIONMEMORY_FREE, mainErr0ENSURES_VIOLATIONMEMORY_LEAK, LDV_INIT_LIST_HEADErr3REQUIRES_VIOLATION, LDV_INIT_LIST_HEADErr2REQUIRES_VIOLATION, LDV_INIT_LIST_HEADErr1REQUIRES_VIOLATION, LDV_INIT_LIST_HEADErr0REQUIRES_VIOLATION, ldv_list_delErr2REQUIRES_VIOLATION, ldv_list_delErr3REQUIRES_VIOLATION, ldv_list_delErr1REQUIRES_VIOLATION, ldv_list_delErr0REQUIRES_VIOLATION, __ldv_list_addErr0REQUIRES_VIOLATION, __ldv_list_addErr5REQUIRES_VIOLATION, __ldv_list_addErr4REQUIRES_VIOLATION, __ldv_list_addErr3REQUIRES_VIOLATION, __ldv_list_addErr2REQUIRES_VIOLATION, __ldv_list_addErr7REQUIRES_VIOLATION, __ldv_list_addErr1REQUIRES_VIOLATION, __ldv_list_addErr6REQUIRES_VIOLATION, ldv_dev_set_drvdataErr1REQUIRES_VIOLATION, ldv_dev_set_drvdataErr0REQUIRES_VIOLATION, ldv_atomic_sub_returnErr2REQUIRES_VIOLATION, ldv_atomic_sub_returnErr3REQUIRES_VIOLATION, ldv_atomic_sub_returnErr1REQUIRES_VIOLATION, ldv_atomic_sub_returnErr0REQUIRES_VIOLATION, ldv_list_add_tailErr0REQUIRES_VIOLATION, ldv_list_add_tailErr1REQUIRES_VIOLATION, ldv_dev_get_drvdataErr1REQUIRES_VIOLATION, ldv_dev_get_drvdataErr0REQUIRES_VIOLATION, ldv_msg_allocErr0REQUIRES_VIOLATION, ldv_msg_allocErr1REQUIRES_VIOLATION]=== [2018-11-28 11:26:15,377 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-28 11:26:15,378 INFO L82 PathProgramCache]: Analyzing trace with hash 1655346548, now seen corresponding path program 1 times [2018-11-28 11:26:15,381 INFO L223 ckRefinementStrategy]: Switched to mode CVC4_FPBP [2018-11-28 11:26:15,381 INFO L69 tionRefinementEngine]: Using refinement strategy WolfRefinementStrategy No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_2ca7a644-5b0a-4f3d-9179-f30a2c52dfce/bin-2019/uautomizer/cvc4 Starting monitored process 2 with cvc4 --incremental --print-success --lang smt --rewrite-divk (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 2 with cvc4 --incremental --print-success --lang smt --rewrite-divk [2018-11-28 11:26:15,400 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-28 11:26:15,469 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-28 11:26:15,476 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-28 11:26:15,517 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 6 treesize of output 5 [2018-11-28 11:26:15,519 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-11-28 11:26:15,524 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-28 11:26:15,525 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 1 variables, input treesize:6, output treesize:5 [2018-11-28 11:26:15,562 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-28 11:26:15,562 INFO L312 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2018-11-28 11:26:15,565 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-28 11:26:15,565 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2018-11-28 11:26:15,568 INFO L459 AbstractCegarLoop]: Interpolant automaton has 5 states [2018-11-28 11:26:15,576 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-11-28 11:26:15,576 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-11-28 11:26:15,578 INFO L87 Difference]: Start difference. First operand 170 states. Second operand 5 states. [2018-11-28 11:26:15,815 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-28 11:26:15,815 INFO L93 Difference]: Finished difference Result 152 states and 163 transitions. [2018-11-28 11:26:15,817 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2018-11-28 11:26:15,818 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 17 [2018-11-28 11:26:15,818 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-28 11:26:15,828 INFO L225 Difference]: With dead ends: 152 [2018-11-28 11:26:15,828 INFO L226 Difference]: Without dead ends: 149 [2018-11-28 11:26:15,829 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 16 GetRequests, 13 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-11-28 11:26:15,841 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 149 states. [2018-11-28 11:26:15,861 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 149 to 143. [2018-11-28 11:26:15,862 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 143 states. [2018-11-28 11:26:15,863 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 143 states to 143 states and 154 transitions. [2018-11-28 11:26:15,864 INFO L78 Accepts]: Start accepts. Automaton has 143 states and 154 transitions. Word has length 17 [2018-11-28 11:26:15,864 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-28 11:26:15,864 INFO L480 AbstractCegarLoop]: Abstraction has 143 states and 154 transitions. [2018-11-28 11:26:15,864 INFO L481 AbstractCegarLoop]: Interpolant automaton has 5 states. [2018-11-28 11:26:15,865 INFO L276 IsEmpty]: Start isEmpty. Operand 143 states and 154 transitions. [2018-11-28 11:26:15,865 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 18 [2018-11-28 11:26:15,865 INFO L394 BasicCegarLoop]: Found error trace [2018-11-28 11:26:15,865 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-28 11:26:15,866 INFO L423 AbstractCegarLoop]: === Iteration 2 === [ldv_kref_initErr0REQUIRES_VIOLATION, ldv_kref_initErr1REQUIRES_VIOLATION, ldv_list_addErr1REQUIRES_VIOLATION, ldv_list_addErr0REQUIRES_VIOLATION, ldv_kobject_createErr1REQUIRES_VIOLATION, ldv_kobject_createErr0REQUIRES_VIOLATION, ldv_destroy_msgsErr5REQUIRES_VIOLATION, ldv_destroy_msgsErr0REQUIRES_VIOLATION, ldv_destroy_msgsErr4REQUIRES_VIOLATION, ldv_destroy_msgsErr2REQUIRES_VIOLATION, ldv_destroy_msgsErr3REQUIRES_VIOLATION, ldv_destroy_msgsErr1REQUIRES_VIOLATION, ldv_msg_fillErr1REQUIRES_VIOLATION, ldv_msg_fillErr3REQUIRES_VIOLATION, ldv_msg_fillErr2REQUIRES_VIOLATION, ldv_msg_fillErr4REQUIRES_VIOLATION, ldv_msg_fillErr0REQUIRES_VIOLATION, ldv_msg_fillErr5REQUIRES_VIOLATION, ldv_atomic_add_returnErr2REQUIRES_VIOLATION, ldv_atomic_add_returnErr3REQUIRES_VIOLATION, ldv_atomic_add_returnErr1REQUIRES_VIOLATION, ldv_atomic_add_returnErr0REQUIRES_VIOLATION, __ldv_list_delErr0REQUIRES_VIOLATION, __ldv_list_delErr3REQUIRES_VIOLATION, __ldv_list_delErr2REQUIRES_VIOLATION, __ldv_list_delErr1REQUIRES_VIOLATION, ldv_kobject_cleanupErr2ASSERT_VIOLATIONMEMORY_FREE, ldv_kobject_cleanupErr0REQUIRES_VIOLATION, ldv_kobject_cleanupErr4ASSERT_VIOLATIONMEMORY_FREE, ldv_kobject_cleanupErr3ASSERT_VIOLATIONMEMORY_FREE, ldv_kobject_cleanupErr5ASSERT_VIOLATIONMEMORY_FREE, ldv_kobject_cleanupErr1REQUIRES_VIOLATION, ldv_msg_freeErr3ASSERT_VIOLATIONMEMORY_FREE, ldv_msg_freeErr5ASSERT_VIOLATIONMEMORY_FREE, ldv_msg_freeErr0REQUIRES_VIOLATION, ldv_msg_freeErr2ASSERT_VIOLATIONMEMORY_FREE, ldv_msg_freeErr1REQUIRES_VIOLATION, ldv_msg_freeErr4ASSERT_VIOLATIONMEMORY_FREE, mainErr0ENSURES_VIOLATIONMEMORY_LEAK, LDV_INIT_LIST_HEADErr3REQUIRES_VIOLATION, LDV_INIT_LIST_HEADErr2REQUIRES_VIOLATION, LDV_INIT_LIST_HEADErr1REQUIRES_VIOLATION, LDV_INIT_LIST_HEADErr0REQUIRES_VIOLATION, ldv_list_delErr2REQUIRES_VIOLATION, ldv_list_delErr3REQUIRES_VIOLATION, ldv_list_delErr1REQUIRES_VIOLATION, ldv_list_delErr0REQUIRES_VIOLATION, __ldv_list_addErr0REQUIRES_VIOLATION, __ldv_list_addErr5REQUIRES_VIOLATION, __ldv_list_addErr4REQUIRES_VIOLATION, __ldv_list_addErr3REQUIRES_VIOLATION, __ldv_list_addErr2REQUIRES_VIOLATION, __ldv_list_addErr7REQUIRES_VIOLATION, __ldv_list_addErr1REQUIRES_VIOLATION, __ldv_list_addErr6REQUIRES_VIOLATION, ldv_dev_set_drvdataErr1REQUIRES_VIOLATION, ldv_dev_set_drvdataErr0REQUIRES_VIOLATION, ldv_atomic_sub_returnErr2REQUIRES_VIOLATION, ldv_atomic_sub_returnErr3REQUIRES_VIOLATION, ldv_atomic_sub_returnErr1REQUIRES_VIOLATION, ldv_atomic_sub_returnErr0REQUIRES_VIOLATION, ldv_list_add_tailErr0REQUIRES_VIOLATION, ldv_list_add_tailErr1REQUIRES_VIOLATION, ldv_dev_get_drvdataErr1REQUIRES_VIOLATION, ldv_dev_get_drvdataErr0REQUIRES_VIOLATION, ldv_msg_allocErr0REQUIRES_VIOLATION, ldv_msg_allocErr1REQUIRES_VIOLATION]=== [2018-11-28 11:26:15,866 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-28 11:26:15,866 INFO L82 PathProgramCache]: Analyzing trace with hash 1655346549, now seen corresponding path program 1 times [2018-11-28 11:26:15,866 INFO L223 ckRefinementStrategy]: Switched to mode CVC4_FPBP [2018-11-28 11:26:15,866 INFO L69 tionRefinementEngine]: Using refinement strategy WolfRefinementStrategy No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_2ca7a644-5b0a-4f3d-9179-f30a2c52dfce/bin-2019/uautomizer/cvc4 Starting monitored process 3 with cvc4 --incremental --print-success --lang smt --rewrite-divk (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 3 with cvc4 --incremental --print-success --lang smt --rewrite-divk [2018-11-28 11:26:15,881 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-28 11:26:15,922 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-28 11:26:15,924 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-28 11:26:15,936 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 6 treesize of output 5 [2018-11-28 11:26:15,936 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-11-28 11:26:15,944 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-28 11:26:15,944 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 1 variables, input treesize:10, output treesize:9 [2018-11-28 11:26:15,993 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-28 11:26:15,993 INFO L312 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2018-11-28 11:26:15,996 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-28 11:26:15,996 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-11-28 11:26:15,997 INFO L459 AbstractCegarLoop]: Interpolant automaton has 6 states [2018-11-28 11:26:15,998 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2018-11-28 11:26:15,998 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=21, Unknown=0, NotChecked=0, Total=30 [2018-11-28 11:26:15,998 INFO L87 Difference]: Start difference. First operand 143 states and 154 transitions. Second operand 6 states. [2018-11-28 11:26:16,225 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-28 11:26:16,225 INFO L93 Difference]: Finished difference Result 148 states and 159 transitions. [2018-11-28 11:26:16,226 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2018-11-28 11:26:16,226 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 17 [2018-11-28 11:26:16,226 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-28 11:26:16,228 INFO L225 Difference]: With dead ends: 148 [2018-11-28 11:26:16,228 INFO L226 Difference]: Without dead ends: 148 [2018-11-28 11:26:16,229 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 17 GetRequests, 12 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=13, Invalid=29, Unknown=0, NotChecked=0, Total=42 [2018-11-28 11:26:16,229 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 148 states. [2018-11-28 11:26:16,235 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 148 to 143. [2018-11-28 11:26:16,235 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 143 states. [2018-11-28 11:26:16,236 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 143 states to 143 states and 153 transitions. [2018-11-28 11:26:16,236 INFO L78 Accepts]: Start accepts. Automaton has 143 states and 153 transitions. Word has length 17 [2018-11-28 11:26:16,237 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-28 11:26:16,237 INFO L480 AbstractCegarLoop]: Abstraction has 143 states and 153 transitions. [2018-11-28 11:26:16,237 INFO L481 AbstractCegarLoop]: Interpolant automaton has 6 states. [2018-11-28 11:26:16,237 INFO L276 IsEmpty]: Start isEmpty. Operand 143 states and 153 transitions. [2018-11-28 11:26:16,237 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 18 [2018-11-28 11:26:16,237 INFO L394 BasicCegarLoop]: Found error trace [2018-11-28 11:26:16,237 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-28 11:26:16,238 INFO L423 AbstractCegarLoop]: === Iteration 3 === [ldv_kref_initErr0REQUIRES_VIOLATION, ldv_kref_initErr1REQUIRES_VIOLATION, ldv_list_addErr1REQUIRES_VIOLATION, ldv_list_addErr0REQUIRES_VIOLATION, ldv_kobject_createErr1REQUIRES_VIOLATION, ldv_kobject_createErr0REQUIRES_VIOLATION, ldv_destroy_msgsErr5REQUIRES_VIOLATION, ldv_destroy_msgsErr0REQUIRES_VIOLATION, ldv_destroy_msgsErr4REQUIRES_VIOLATION, ldv_destroy_msgsErr2REQUIRES_VIOLATION, ldv_destroy_msgsErr3REQUIRES_VIOLATION, ldv_destroy_msgsErr1REQUIRES_VIOLATION, ldv_msg_fillErr1REQUIRES_VIOLATION, ldv_msg_fillErr3REQUIRES_VIOLATION, ldv_msg_fillErr2REQUIRES_VIOLATION, ldv_msg_fillErr4REQUIRES_VIOLATION, ldv_msg_fillErr0REQUIRES_VIOLATION, ldv_msg_fillErr5REQUIRES_VIOLATION, ldv_atomic_add_returnErr2REQUIRES_VIOLATION, ldv_atomic_add_returnErr3REQUIRES_VIOLATION, ldv_atomic_add_returnErr1REQUIRES_VIOLATION, ldv_atomic_add_returnErr0REQUIRES_VIOLATION, __ldv_list_delErr0REQUIRES_VIOLATION, __ldv_list_delErr3REQUIRES_VIOLATION, __ldv_list_delErr2REQUIRES_VIOLATION, __ldv_list_delErr1REQUIRES_VIOLATION, ldv_kobject_cleanupErr2ASSERT_VIOLATIONMEMORY_FREE, ldv_kobject_cleanupErr0REQUIRES_VIOLATION, ldv_kobject_cleanupErr4ASSERT_VIOLATIONMEMORY_FREE, ldv_kobject_cleanupErr3ASSERT_VIOLATIONMEMORY_FREE, ldv_kobject_cleanupErr5ASSERT_VIOLATIONMEMORY_FREE, ldv_kobject_cleanupErr1REQUIRES_VIOLATION, ldv_msg_freeErr3ASSERT_VIOLATIONMEMORY_FREE, ldv_msg_freeErr5ASSERT_VIOLATIONMEMORY_FREE, ldv_msg_freeErr0REQUIRES_VIOLATION, ldv_msg_freeErr2ASSERT_VIOLATIONMEMORY_FREE, ldv_msg_freeErr1REQUIRES_VIOLATION, ldv_msg_freeErr4ASSERT_VIOLATIONMEMORY_FREE, mainErr0ENSURES_VIOLATIONMEMORY_LEAK, LDV_INIT_LIST_HEADErr3REQUIRES_VIOLATION, LDV_INIT_LIST_HEADErr2REQUIRES_VIOLATION, LDV_INIT_LIST_HEADErr1REQUIRES_VIOLATION, LDV_INIT_LIST_HEADErr0REQUIRES_VIOLATION, ldv_list_delErr2REQUIRES_VIOLATION, ldv_list_delErr3REQUIRES_VIOLATION, ldv_list_delErr1REQUIRES_VIOLATION, ldv_list_delErr0REQUIRES_VIOLATION, __ldv_list_addErr0REQUIRES_VIOLATION, __ldv_list_addErr5REQUIRES_VIOLATION, __ldv_list_addErr4REQUIRES_VIOLATION, __ldv_list_addErr3REQUIRES_VIOLATION, __ldv_list_addErr2REQUIRES_VIOLATION, __ldv_list_addErr7REQUIRES_VIOLATION, __ldv_list_addErr1REQUIRES_VIOLATION, __ldv_list_addErr6REQUIRES_VIOLATION, ldv_dev_set_drvdataErr1REQUIRES_VIOLATION, ldv_dev_set_drvdataErr0REQUIRES_VIOLATION, ldv_atomic_sub_returnErr2REQUIRES_VIOLATION, ldv_atomic_sub_returnErr3REQUIRES_VIOLATION, ldv_atomic_sub_returnErr1REQUIRES_VIOLATION, ldv_atomic_sub_returnErr0REQUIRES_VIOLATION, ldv_list_add_tailErr0REQUIRES_VIOLATION, ldv_list_add_tailErr1REQUIRES_VIOLATION, ldv_dev_get_drvdataErr1REQUIRES_VIOLATION, ldv_dev_get_drvdataErr0REQUIRES_VIOLATION, ldv_msg_allocErr0REQUIRES_VIOLATION, ldv_msg_allocErr1REQUIRES_VIOLATION]=== [2018-11-28 11:26:16,238 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-28 11:26:16,238 INFO L82 PathProgramCache]: Analyzing trace with hash 1683975699, now seen corresponding path program 1 times [2018-11-28 11:26:16,238 INFO L223 ckRefinementStrategy]: Switched to mode CVC4_FPBP [2018-11-28 11:26:16,238 INFO L69 tionRefinementEngine]: Using refinement strategy WolfRefinementStrategy No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_2ca7a644-5b0a-4f3d-9179-f30a2c52dfce/bin-2019/uautomizer/cvc4 Starting monitored process 4 with cvc4 --incremental --print-success --lang smt --rewrite-divk (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 4 with cvc4 --incremental --print-success --lang smt --rewrite-divk [2018-11-28 11:26:16,253 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-28 11:26:16,280 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-28 11:26:16,282 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-28 11:26:16,306 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-28 11:26:16,307 INFO L312 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2018-11-28 11:26:16,308 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-28 11:26:16,308 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-11-28 11:26:16,309 INFO L459 AbstractCegarLoop]: Interpolant automaton has 5 states [2018-11-28 11:26:16,309 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-11-28 11:26:16,309 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-11-28 11:26:16,309 INFO L87 Difference]: Start difference. First operand 143 states and 153 transitions. Second operand 5 states. [2018-11-28 11:26:16,346 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-28 11:26:16,347 INFO L93 Difference]: Finished difference Result 142 states and 150 transitions. [2018-11-28 11:26:16,349 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2018-11-28 11:26:16,349 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 17 [2018-11-28 11:26:16,350 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-28 11:26:16,351 INFO L225 Difference]: With dead ends: 142 [2018-11-28 11:26:16,351 INFO L226 Difference]: Without dead ends: 142 [2018-11-28 11:26:16,351 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 16 GetRequests, 13 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-11-28 11:26:16,352 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 142 states. [2018-11-28 11:26:16,357 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 142 to 140. [2018-11-28 11:26:16,358 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 140 states. [2018-11-28 11:26:16,359 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 140 states to 140 states and 148 transitions. [2018-11-28 11:26:16,359 INFO L78 Accepts]: Start accepts. Automaton has 140 states and 148 transitions. Word has length 17 [2018-11-28 11:26:16,360 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-28 11:26:16,360 INFO L480 AbstractCegarLoop]: Abstraction has 140 states and 148 transitions. [2018-11-28 11:26:16,360 INFO L481 AbstractCegarLoop]: Interpolant automaton has 5 states. [2018-11-28 11:26:16,360 INFO L276 IsEmpty]: Start isEmpty. Operand 140 states and 148 transitions. [2018-11-28 11:26:16,361 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 28 [2018-11-28 11:26:16,361 INFO L394 BasicCegarLoop]: Found error trace [2018-11-28 11:26:16,361 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-28 11:26:16,361 INFO L423 AbstractCegarLoop]: === Iteration 4 === [ldv_kref_initErr0REQUIRES_VIOLATION, ldv_kref_initErr1REQUIRES_VIOLATION, ldv_list_addErr1REQUIRES_VIOLATION, ldv_list_addErr0REQUIRES_VIOLATION, ldv_kobject_createErr1REQUIRES_VIOLATION, ldv_kobject_createErr0REQUIRES_VIOLATION, ldv_destroy_msgsErr5REQUIRES_VIOLATION, ldv_destroy_msgsErr0REQUIRES_VIOLATION, ldv_destroy_msgsErr4REQUIRES_VIOLATION, ldv_destroy_msgsErr2REQUIRES_VIOLATION, ldv_destroy_msgsErr3REQUIRES_VIOLATION, ldv_destroy_msgsErr1REQUIRES_VIOLATION, ldv_msg_fillErr1REQUIRES_VIOLATION, ldv_msg_fillErr3REQUIRES_VIOLATION, ldv_msg_fillErr2REQUIRES_VIOLATION, ldv_msg_fillErr4REQUIRES_VIOLATION, ldv_msg_fillErr0REQUIRES_VIOLATION, ldv_msg_fillErr5REQUIRES_VIOLATION, ldv_atomic_add_returnErr2REQUIRES_VIOLATION, ldv_atomic_add_returnErr3REQUIRES_VIOLATION, ldv_atomic_add_returnErr1REQUIRES_VIOLATION, ldv_atomic_add_returnErr0REQUIRES_VIOLATION, __ldv_list_delErr0REQUIRES_VIOLATION, __ldv_list_delErr3REQUIRES_VIOLATION, __ldv_list_delErr2REQUIRES_VIOLATION, __ldv_list_delErr1REQUIRES_VIOLATION, ldv_kobject_cleanupErr2ASSERT_VIOLATIONMEMORY_FREE, ldv_kobject_cleanupErr0REQUIRES_VIOLATION, ldv_kobject_cleanupErr4ASSERT_VIOLATIONMEMORY_FREE, ldv_kobject_cleanupErr3ASSERT_VIOLATIONMEMORY_FREE, ldv_kobject_cleanupErr5ASSERT_VIOLATIONMEMORY_FREE, ldv_kobject_cleanupErr1REQUIRES_VIOLATION, ldv_msg_freeErr3ASSERT_VIOLATIONMEMORY_FREE, ldv_msg_freeErr5ASSERT_VIOLATIONMEMORY_FREE, ldv_msg_freeErr0REQUIRES_VIOLATION, ldv_msg_freeErr2ASSERT_VIOLATIONMEMORY_FREE, ldv_msg_freeErr1REQUIRES_VIOLATION, ldv_msg_freeErr4ASSERT_VIOLATIONMEMORY_FREE, mainErr0ENSURES_VIOLATIONMEMORY_LEAK, LDV_INIT_LIST_HEADErr3REQUIRES_VIOLATION, LDV_INIT_LIST_HEADErr2REQUIRES_VIOLATION, LDV_INIT_LIST_HEADErr1REQUIRES_VIOLATION, LDV_INIT_LIST_HEADErr0REQUIRES_VIOLATION, ldv_list_delErr2REQUIRES_VIOLATION, ldv_list_delErr3REQUIRES_VIOLATION, ldv_list_delErr1REQUIRES_VIOLATION, ldv_list_delErr0REQUIRES_VIOLATION, __ldv_list_addErr0REQUIRES_VIOLATION, __ldv_list_addErr5REQUIRES_VIOLATION, __ldv_list_addErr4REQUIRES_VIOLATION, __ldv_list_addErr3REQUIRES_VIOLATION, __ldv_list_addErr2REQUIRES_VIOLATION, __ldv_list_addErr7REQUIRES_VIOLATION, __ldv_list_addErr1REQUIRES_VIOLATION, __ldv_list_addErr6REQUIRES_VIOLATION, ldv_dev_set_drvdataErr1REQUIRES_VIOLATION, ldv_dev_set_drvdataErr0REQUIRES_VIOLATION, ldv_atomic_sub_returnErr2REQUIRES_VIOLATION, ldv_atomic_sub_returnErr3REQUIRES_VIOLATION, ldv_atomic_sub_returnErr1REQUIRES_VIOLATION, ldv_atomic_sub_returnErr0REQUIRES_VIOLATION, ldv_list_add_tailErr0REQUIRES_VIOLATION, ldv_list_add_tailErr1REQUIRES_VIOLATION, ldv_dev_get_drvdataErr1REQUIRES_VIOLATION, ldv_dev_get_drvdataErr0REQUIRES_VIOLATION, ldv_msg_allocErr0REQUIRES_VIOLATION, ldv_msg_allocErr1REQUIRES_VIOLATION]=== [2018-11-28 11:26:16,361 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-28 11:26:16,361 INFO L82 PathProgramCache]: Analyzing trace with hash 1758022862, now seen corresponding path program 1 times [2018-11-28 11:26:16,364 INFO L223 ckRefinementStrategy]: Switched to mode CVC4_FPBP [2018-11-28 11:26:16,364 INFO L69 tionRefinementEngine]: Using refinement strategy WolfRefinementStrategy No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_2ca7a644-5b0a-4f3d-9179-f30a2c52dfce/bin-2019/uautomizer/cvc4 Starting monitored process 5 with cvc4 --incremental --print-success --lang smt --rewrite-divk (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 5 with cvc4 --incremental --print-success --lang smt --rewrite-divk [2018-11-28 11:26:16,392 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-28 11:26:16,432 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-28 11:26:16,435 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-28 11:26:16,469 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-28 11:26:16,469 INFO L312 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2018-11-28 11:26:16,471 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-28 11:26:16,471 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-11-28 11:26:16,471 INFO L459 AbstractCegarLoop]: Interpolant automaton has 5 states [2018-11-28 11:26:16,472 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-11-28 11:26:16,472 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-11-28 11:26:16,472 INFO L87 Difference]: Start difference. First operand 140 states and 148 transitions. Second operand 5 states. [2018-11-28 11:26:16,496 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-28 11:26:16,496 INFO L93 Difference]: Finished difference Result 142 states and 149 transitions. [2018-11-28 11:26:16,498 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2018-11-28 11:26:16,498 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 27 [2018-11-28 11:26:16,499 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-28 11:26:16,500 INFO L225 Difference]: With dead ends: 142 [2018-11-28 11:26:16,500 INFO L226 Difference]: Without dead ends: 142 [2018-11-28 11:26:16,500 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 26 GetRequests, 23 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-11-28 11:26:16,500 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 142 states. [2018-11-28 11:26:16,505 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 142 to 140. [2018-11-28 11:26:16,506 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 140 states. [2018-11-28 11:26:16,507 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 140 states to 140 states and 147 transitions. [2018-11-28 11:26:16,507 INFO L78 Accepts]: Start accepts. Automaton has 140 states and 147 transitions. Word has length 27 [2018-11-28 11:26:16,507 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-28 11:26:16,508 INFO L480 AbstractCegarLoop]: Abstraction has 140 states and 147 transitions. [2018-11-28 11:26:16,508 INFO L481 AbstractCegarLoop]: Interpolant automaton has 5 states. [2018-11-28 11:26:16,508 INFO L276 IsEmpty]: Start isEmpty. Operand 140 states and 147 transitions. [2018-11-28 11:26:16,508 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 28 [2018-11-28 11:26:16,508 INFO L394 BasicCegarLoop]: Found error trace [2018-11-28 11:26:16,508 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-28 11:26:16,509 INFO L423 AbstractCegarLoop]: === Iteration 5 === [ldv_kref_initErr0REQUIRES_VIOLATION, ldv_kref_initErr1REQUIRES_VIOLATION, ldv_list_addErr1REQUIRES_VIOLATION, ldv_list_addErr0REQUIRES_VIOLATION, ldv_kobject_createErr1REQUIRES_VIOLATION, ldv_kobject_createErr0REQUIRES_VIOLATION, ldv_destroy_msgsErr5REQUIRES_VIOLATION, ldv_destroy_msgsErr0REQUIRES_VIOLATION, ldv_destroy_msgsErr4REQUIRES_VIOLATION, ldv_destroy_msgsErr2REQUIRES_VIOLATION, ldv_destroy_msgsErr3REQUIRES_VIOLATION, ldv_destroy_msgsErr1REQUIRES_VIOLATION, ldv_msg_fillErr1REQUIRES_VIOLATION, ldv_msg_fillErr3REQUIRES_VIOLATION, ldv_msg_fillErr2REQUIRES_VIOLATION, ldv_msg_fillErr4REQUIRES_VIOLATION, ldv_msg_fillErr0REQUIRES_VIOLATION, ldv_msg_fillErr5REQUIRES_VIOLATION, ldv_atomic_add_returnErr2REQUIRES_VIOLATION, ldv_atomic_add_returnErr3REQUIRES_VIOLATION, ldv_atomic_add_returnErr1REQUIRES_VIOLATION, ldv_atomic_add_returnErr0REQUIRES_VIOLATION, __ldv_list_delErr0REQUIRES_VIOLATION, __ldv_list_delErr3REQUIRES_VIOLATION, __ldv_list_delErr2REQUIRES_VIOLATION, __ldv_list_delErr1REQUIRES_VIOLATION, ldv_kobject_cleanupErr2ASSERT_VIOLATIONMEMORY_FREE, ldv_kobject_cleanupErr0REQUIRES_VIOLATION, ldv_kobject_cleanupErr4ASSERT_VIOLATIONMEMORY_FREE, ldv_kobject_cleanupErr3ASSERT_VIOLATIONMEMORY_FREE, ldv_kobject_cleanupErr5ASSERT_VIOLATIONMEMORY_FREE, ldv_kobject_cleanupErr1REQUIRES_VIOLATION, ldv_msg_freeErr3ASSERT_VIOLATIONMEMORY_FREE, ldv_msg_freeErr5ASSERT_VIOLATIONMEMORY_FREE, ldv_msg_freeErr0REQUIRES_VIOLATION, ldv_msg_freeErr2ASSERT_VIOLATIONMEMORY_FREE, ldv_msg_freeErr1REQUIRES_VIOLATION, ldv_msg_freeErr4ASSERT_VIOLATIONMEMORY_FREE, mainErr0ENSURES_VIOLATIONMEMORY_LEAK, LDV_INIT_LIST_HEADErr3REQUIRES_VIOLATION, LDV_INIT_LIST_HEADErr2REQUIRES_VIOLATION, LDV_INIT_LIST_HEADErr1REQUIRES_VIOLATION, LDV_INIT_LIST_HEADErr0REQUIRES_VIOLATION, ldv_list_delErr2REQUIRES_VIOLATION, ldv_list_delErr3REQUIRES_VIOLATION, ldv_list_delErr1REQUIRES_VIOLATION, ldv_list_delErr0REQUIRES_VIOLATION, __ldv_list_addErr0REQUIRES_VIOLATION, __ldv_list_addErr5REQUIRES_VIOLATION, __ldv_list_addErr4REQUIRES_VIOLATION, __ldv_list_addErr3REQUIRES_VIOLATION, __ldv_list_addErr2REQUIRES_VIOLATION, __ldv_list_addErr7REQUIRES_VIOLATION, __ldv_list_addErr1REQUIRES_VIOLATION, __ldv_list_addErr6REQUIRES_VIOLATION, ldv_dev_set_drvdataErr1REQUIRES_VIOLATION, ldv_dev_set_drvdataErr0REQUIRES_VIOLATION, ldv_atomic_sub_returnErr2REQUIRES_VIOLATION, ldv_atomic_sub_returnErr3REQUIRES_VIOLATION, ldv_atomic_sub_returnErr1REQUIRES_VIOLATION, ldv_atomic_sub_returnErr0REQUIRES_VIOLATION, ldv_list_add_tailErr0REQUIRES_VIOLATION, ldv_list_add_tailErr1REQUIRES_VIOLATION, ldv_dev_get_drvdataErr1REQUIRES_VIOLATION, ldv_dev_get_drvdataErr0REQUIRES_VIOLATION, ldv_msg_allocErr0REQUIRES_VIOLATION, ldv_msg_allocErr1REQUIRES_VIOLATION]=== [2018-11-28 11:26:16,509 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-28 11:26:16,509 INFO L82 PathProgramCache]: Analyzing trace with hash 1247488685, now seen corresponding path program 1 times [2018-11-28 11:26:16,509 INFO L223 ckRefinementStrategy]: Switched to mode CVC4_FPBP [2018-11-28 11:26:16,509 INFO L69 tionRefinementEngine]: Using refinement strategy WolfRefinementStrategy No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_2ca7a644-5b0a-4f3d-9179-f30a2c52dfce/bin-2019/uautomizer/cvc4 Starting monitored process 6 with cvc4 --incremental --print-success --lang smt --rewrite-divk (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 6 with cvc4 --incremental --print-success --lang smt --rewrite-divk [2018-11-28 11:26:16,535 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-28 11:26:16,606 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-28 11:26:16,610 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-28 11:26:16,675 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-28 11:26:16,675 INFO L312 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2018-11-28 11:26:16,677 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-28 11:26:16,677 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [7] imperfect sequences [] total 7 [2018-11-28 11:26:16,677 INFO L459 AbstractCegarLoop]: Interpolant automaton has 7 states [2018-11-28 11:26:16,677 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2018-11-28 11:26:16,678 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=11, Invalid=31, Unknown=0, NotChecked=0, Total=42 [2018-11-28 11:26:16,678 INFO L87 Difference]: Start difference. First operand 140 states and 147 transitions. Second operand 7 states. [2018-11-28 11:26:16,759 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-28 11:26:16,759 INFO L93 Difference]: Finished difference Result 156 states and 164 transitions. [2018-11-28 11:26:16,762 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 8 states. [2018-11-28 11:26:16,762 INFO L78 Accepts]: Start accepts. Automaton has 7 states. Word has length 27 [2018-11-28 11:26:16,763 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-28 11:26:16,764 INFO L225 Difference]: With dead ends: 156 [2018-11-28 11:26:16,764 INFO L226 Difference]: Without dead ends: 156 [2018-11-28 11:26:16,764 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 27 GetRequests, 21 SyntacticMatches, 0 SemanticMatches, 6 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=15, Invalid=41, Unknown=0, NotChecked=0, Total=56 [2018-11-28 11:26:16,765 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 156 states. [2018-11-28 11:26:16,770 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 156 to 149. [2018-11-28 11:26:16,770 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 149 states. [2018-11-28 11:26:16,772 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 149 states to 149 states and 156 transitions. [2018-11-28 11:26:16,772 INFO L78 Accepts]: Start accepts. Automaton has 149 states and 156 transitions. Word has length 27 [2018-11-28 11:26:16,772 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-28 11:26:16,772 INFO L480 AbstractCegarLoop]: Abstraction has 149 states and 156 transitions. [2018-11-28 11:26:16,772 INFO L481 AbstractCegarLoop]: Interpolant automaton has 7 states. [2018-11-28 11:26:16,772 INFO L276 IsEmpty]: Start isEmpty. Operand 149 states and 156 transitions. [2018-11-28 11:26:16,773 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 33 [2018-11-28 11:26:16,773 INFO L394 BasicCegarLoop]: Found error trace [2018-11-28 11:26:16,773 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-28 11:26:16,774 INFO L423 AbstractCegarLoop]: === Iteration 6 === [ldv_kref_initErr0REQUIRES_VIOLATION, ldv_kref_initErr1REQUIRES_VIOLATION, ldv_list_addErr1REQUIRES_VIOLATION, ldv_list_addErr0REQUIRES_VIOLATION, ldv_kobject_createErr1REQUIRES_VIOLATION, ldv_kobject_createErr0REQUIRES_VIOLATION, ldv_destroy_msgsErr5REQUIRES_VIOLATION, ldv_destroy_msgsErr0REQUIRES_VIOLATION, ldv_destroy_msgsErr4REQUIRES_VIOLATION, ldv_destroy_msgsErr2REQUIRES_VIOLATION, ldv_destroy_msgsErr3REQUIRES_VIOLATION, ldv_destroy_msgsErr1REQUIRES_VIOLATION, ldv_msg_fillErr1REQUIRES_VIOLATION, ldv_msg_fillErr3REQUIRES_VIOLATION, ldv_msg_fillErr2REQUIRES_VIOLATION, ldv_msg_fillErr4REQUIRES_VIOLATION, ldv_msg_fillErr0REQUIRES_VIOLATION, ldv_msg_fillErr5REQUIRES_VIOLATION, ldv_atomic_add_returnErr2REQUIRES_VIOLATION, ldv_atomic_add_returnErr3REQUIRES_VIOLATION, ldv_atomic_add_returnErr1REQUIRES_VIOLATION, ldv_atomic_add_returnErr0REQUIRES_VIOLATION, __ldv_list_delErr0REQUIRES_VIOLATION, __ldv_list_delErr3REQUIRES_VIOLATION, __ldv_list_delErr2REQUIRES_VIOLATION, __ldv_list_delErr1REQUIRES_VIOLATION, ldv_kobject_cleanupErr2ASSERT_VIOLATIONMEMORY_FREE, ldv_kobject_cleanupErr0REQUIRES_VIOLATION, ldv_kobject_cleanupErr4ASSERT_VIOLATIONMEMORY_FREE, ldv_kobject_cleanupErr3ASSERT_VIOLATIONMEMORY_FREE, ldv_kobject_cleanupErr5ASSERT_VIOLATIONMEMORY_FREE, ldv_kobject_cleanupErr1REQUIRES_VIOLATION, ldv_msg_freeErr3ASSERT_VIOLATIONMEMORY_FREE, ldv_msg_freeErr5ASSERT_VIOLATIONMEMORY_FREE, ldv_msg_freeErr0REQUIRES_VIOLATION, ldv_msg_freeErr2ASSERT_VIOLATIONMEMORY_FREE, ldv_msg_freeErr1REQUIRES_VIOLATION, ldv_msg_freeErr4ASSERT_VIOLATIONMEMORY_FREE, mainErr0ENSURES_VIOLATIONMEMORY_LEAK, LDV_INIT_LIST_HEADErr3REQUIRES_VIOLATION, LDV_INIT_LIST_HEADErr2REQUIRES_VIOLATION, LDV_INIT_LIST_HEADErr1REQUIRES_VIOLATION, LDV_INIT_LIST_HEADErr0REQUIRES_VIOLATION, ldv_list_delErr2REQUIRES_VIOLATION, ldv_list_delErr3REQUIRES_VIOLATION, ldv_list_delErr1REQUIRES_VIOLATION, ldv_list_delErr0REQUIRES_VIOLATION, __ldv_list_addErr0REQUIRES_VIOLATION, __ldv_list_addErr5REQUIRES_VIOLATION, __ldv_list_addErr4REQUIRES_VIOLATION, __ldv_list_addErr3REQUIRES_VIOLATION, __ldv_list_addErr2REQUIRES_VIOLATION, __ldv_list_addErr7REQUIRES_VIOLATION, __ldv_list_addErr1REQUIRES_VIOLATION, __ldv_list_addErr6REQUIRES_VIOLATION, ldv_dev_set_drvdataErr1REQUIRES_VIOLATION, ldv_dev_set_drvdataErr0REQUIRES_VIOLATION, ldv_atomic_sub_returnErr2REQUIRES_VIOLATION, ldv_atomic_sub_returnErr3REQUIRES_VIOLATION, ldv_atomic_sub_returnErr1REQUIRES_VIOLATION, ldv_atomic_sub_returnErr0REQUIRES_VIOLATION, ldv_list_add_tailErr0REQUIRES_VIOLATION, ldv_list_add_tailErr1REQUIRES_VIOLATION, ldv_dev_get_drvdataErr1REQUIRES_VIOLATION, ldv_dev_get_drvdataErr0REQUIRES_VIOLATION, ldv_msg_allocErr0REQUIRES_VIOLATION, ldv_msg_allocErr1REQUIRES_VIOLATION]=== [2018-11-28 11:26:16,774 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-28 11:26:16,774 INFO L82 PathProgramCache]: Analyzing trace with hash -858274277, now seen corresponding path program 1 times [2018-11-28 11:26:16,774 INFO L223 ckRefinementStrategy]: Switched to mode CVC4_FPBP [2018-11-28 11:26:16,774 INFO L69 tionRefinementEngine]: Using refinement strategy WolfRefinementStrategy No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_2ca7a644-5b0a-4f3d-9179-f30a2c52dfce/bin-2019/uautomizer/cvc4 Starting monitored process 7 with cvc4 --incremental --print-success --lang smt --rewrite-divk (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 7 with cvc4 --incremental --print-success --lang smt --rewrite-divk [2018-11-28 11:26:16,806 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-28 11:26:16,892 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-28 11:26:16,895 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-28 11:26:16,922 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-28 11:26:16,923 INFO L312 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2018-11-28 11:26:16,928 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-28 11:26:16,928 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2018-11-28 11:26:16,928 INFO L459 AbstractCegarLoop]: Interpolant automaton has 4 states [2018-11-28 11:26:16,929 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2018-11-28 11:26:16,929 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2018-11-28 11:26:16,929 INFO L87 Difference]: Start difference. First operand 149 states and 156 transitions. Second operand 4 states. [2018-11-28 11:26:16,965 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-28 11:26:16,965 INFO L93 Difference]: Finished difference Result 152 states and 159 transitions. [2018-11-28 11:26:16,966 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2018-11-28 11:26:16,966 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 32 [2018-11-28 11:26:16,966 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-28 11:26:16,967 INFO L225 Difference]: With dead ends: 152 [2018-11-28 11:26:16,967 INFO L226 Difference]: Without dead ends: 150 [2018-11-28 11:26:16,967 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 32 GetRequests, 29 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2018-11-28 11:26:16,968 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 150 states. [2018-11-28 11:26:16,972 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 150 to 150. [2018-11-28 11:26:16,972 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 150 states. [2018-11-28 11:26:16,973 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 150 states to 150 states and 157 transitions. [2018-11-28 11:26:16,973 INFO L78 Accepts]: Start accepts. Automaton has 150 states and 157 transitions. Word has length 32 [2018-11-28 11:26:16,973 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-28 11:26:16,973 INFO L480 AbstractCegarLoop]: Abstraction has 150 states and 157 transitions. [2018-11-28 11:26:16,974 INFO L481 AbstractCegarLoop]: Interpolant automaton has 4 states. [2018-11-28 11:26:16,974 INFO L276 IsEmpty]: Start isEmpty. Operand 150 states and 157 transitions. [2018-11-28 11:26:16,974 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 34 [2018-11-28 11:26:16,974 INFO L394 BasicCegarLoop]: Found error trace [2018-11-28 11:26:16,975 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-28 11:26:16,975 INFO L423 AbstractCegarLoop]: === Iteration 7 === [ldv_kref_initErr0REQUIRES_VIOLATION, ldv_kref_initErr1REQUIRES_VIOLATION, ldv_list_addErr1REQUIRES_VIOLATION, ldv_list_addErr0REQUIRES_VIOLATION, ldv_kobject_createErr1REQUIRES_VIOLATION, ldv_kobject_createErr0REQUIRES_VIOLATION, ldv_destroy_msgsErr5REQUIRES_VIOLATION, ldv_destroy_msgsErr0REQUIRES_VIOLATION, ldv_destroy_msgsErr4REQUIRES_VIOLATION, ldv_destroy_msgsErr2REQUIRES_VIOLATION, ldv_destroy_msgsErr3REQUIRES_VIOLATION, ldv_destroy_msgsErr1REQUIRES_VIOLATION, ldv_msg_fillErr1REQUIRES_VIOLATION, ldv_msg_fillErr3REQUIRES_VIOLATION, ldv_msg_fillErr2REQUIRES_VIOLATION, ldv_msg_fillErr4REQUIRES_VIOLATION, ldv_msg_fillErr0REQUIRES_VIOLATION, ldv_msg_fillErr5REQUIRES_VIOLATION, ldv_atomic_add_returnErr2REQUIRES_VIOLATION, ldv_atomic_add_returnErr3REQUIRES_VIOLATION, ldv_atomic_add_returnErr1REQUIRES_VIOLATION, ldv_atomic_add_returnErr0REQUIRES_VIOLATION, __ldv_list_delErr0REQUIRES_VIOLATION, __ldv_list_delErr3REQUIRES_VIOLATION, __ldv_list_delErr2REQUIRES_VIOLATION, __ldv_list_delErr1REQUIRES_VIOLATION, ldv_kobject_cleanupErr2ASSERT_VIOLATIONMEMORY_FREE, ldv_kobject_cleanupErr0REQUIRES_VIOLATION, ldv_kobject_cleanupErr4ASSERT_VIOLATIONMEMORY_FREE, ldv_kobject_cleanupErr3ASSERT_VIOLATIONMEMORY_FREE, ldv_kobject_cleanupErr5ASSERT_VIOLATIONMEMORY_FREE, ldv_kobject_cleanupErr1REQUIRES_VIOLATION, ldv_msg_freeErr3ASSERT_VIOLATIONMEMORY_FREE, ldv_msg_freeErr5ASSERT_VIOLATIONMEMORY_FREE, ldv_msg_freeErr0REQUIRES_VIOLATION, ldv_msg_freeErr2ASSERT_VIOLATIONMEMORY_FREE, ldv_msg_freeErr1REQUIRES_VIOLATION, ldv_msg_freeErr4ASSERT_VIOLATIONMEMORY_FREE, mainErr0ENSURES_VIOLATIONMEMORY_LEAK, LDV_INIT_LIST_HEADErr3REQUIRES_VIOLATION, LDV_INIT_LIST_HEADErr2REQUIRES_VIOLATION, LDV_INIT_LIST_HEADErr1REQUIRES_VIOLATION, LDV_INIT_LIST_HEADErr0REQUIRES_VIOLATION, ldv_list_delErr2REQUIRES_VIOLATION, ldv_list_delErr3REQUIRES_VIOLATION, ldv_list_delErr1REQUIRES_VIOLATION, ldv_list_delErr0REQUIRES_VIOLATION, __ldv_list_addErr0REQUIRES_VIOLATION, __ldv_list_addErr5REQUIRES_VIOLATION, __ldv_list_addErr4REQUIRES_VIOLATION, __ldv_list_addErr3REQUIRES_VIOLATION, __ldv_list_addErr2REQUIRES_VIOLATION, __ldv_list_addErr7REQUIRES_VIOLATION, __ldv_list_addErr1REQUIRES_VIOLATION, __ldv_list_addErr6REQUIRES_VIOLATION, ldv_dev_set_drvdataErr1REQUIRES_VIOLATION, ldv_dev_set_drvdataErr0REQUIRES_VIOLATION, ldv_atomic_sub_returnErr2REQUIRES_VIOLATION, ldv_atomic_sub_returnErr3REQUIRES_VIOLATION, ldv_atomic_sub_returnErr1REQUIRES_VIOLATION, ldv_atomic_sub_returnErr0REQUIRES_VIOLATION, ldv_list_add_tailErr0REQUIRES_VIOLATION, ldv_list_add_tailErr1REQUIRES_VIOLATION, ldv_dev_get_drvdataErr1REQUIRES_VIOLATION, ldv_dev_get_drvdataErr0REQUIRES_VIOLATION, ldv_msg_allocErr0REQUIRES_VIOLATION, ldv_msg_allocErr1REQUIRES_VIOLATION]=== [2018-11-28 11:26:16,977 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-28 11:26:16,978 INFO L82 PathProgramCache]: Analyzing trace with hash -608271994, now seen corresponding path program 1 times [2018-11-28 11:26:16,978 INFO L223 ckRefinementStrategy]: Switched to mode CVC4_FPBP [2018-11-28 11:26:16,978 INFO L69 tionRefinementEngine]: Using refinement strategy WolfRefinementStrategy No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_2ca7a644-5b0a-4f3d-9179-f30a2c52dfce/bin-2019/uautomizer/cvc4 Starting monitored process 8 with cvc4 --incremental --print-success --lang smt --rewrite-divk (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 8 with cvc4 --incremental --print-success --lang smt --rewrite-divk [2018-11-28 11:26:16,992 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-28 11:26:17,066 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-28 11:26:17,069 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-28 11:26:17,129 INFO L134 CoverageAnalysis]: Checked inductivity of 1 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-28 11:26:17,129 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-11-28 11:26:17,197 INFO L134 CoverageAnalysis]: Checked inductivity of 1 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-28 11:26:17,199 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-11-28 11:26:17,200 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [5, 5] total 8 [2018-11-28 11:26:17,200 INFO L459 AbstractCegarLoop]: Interpolant automaton has 8 states [2018-11-28 11:26:17,200 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 8 interpolants. [2018-11-28 11:26:17,200 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=22, Invalid=34, Unknown=0, NotChecked=0, Total=56 [2018-11-28 11:26:17,200 INFO L87 Difference]: Start difference. First operand 150 states and 157 transitions. Second operand 8 states. [2018-11-28 11:26:17,294 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-28 11:26:17,294 INFO L93 Difference]: Finished difference Result 157 states and 165 transitions. [2018-11-28 11:26:17,294 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 8 states. [2018-11-28 11:26:17,295 INFO L78 Accepts]: Start accepts. Automaton has 8 states. Word has length 33 [2018-11-28 11:26:17,295 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-28 11:26:17,296 INFO L225 Difference]: With dead ends: 157 [2018-11-28 11:26:17,296 INFO L226 Difference]: Without dead ends: 153 [2018-11-28 11:26:17,296 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 67 GetRequests, 58 SyntacticMatches, 1 SemanticMatches, 8 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=38, Invalid=52, Unknown=0, NotChecked=0, Total=90 [2018-11-28 11:26:17,296 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 153 states. [2018-11-28 11:26:17,301 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 153 to 153. [2018-11-28 11:26:17,301 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 153 states. [2018-11-28 11:26:17,301 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 153 states to 153 states and 160 transitions. [2018-11-28 11:26:17,302 INFO L78 Accepts]: Start accepts. Automaton has 153 states and 160 transitions. Word has length 33 [2018-11-28 11:26:17,302 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-28 11:26:17,302 INFO L480 AbstractCegarLoop]: Abstraction has 153 states and 160 transitions. [2018-11-28 11:26:17,302 INFO L481 AbstractCegarLoop]: Interpolant automaton has 8 states. [2018-11-28 11:26:17,302 INFO L276 IsEmpty]: Start isEmpty. Operand 153 states and 160 transitions. [2018-11-28 11:26:17,303 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 37 [2018-11-28 11:26:17,303 INFO L394 BasicCegarLoop]: Found error trace [2018-11-28 11:26:17,303 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-28 11:26:17,304 INFO L423 AbstractCegarLoop]: === Iteration 8 === [ldv_kref_initErr0REQUIRES_VIOLATION, ldv_kref_initErr1REQUIRES_VIOLATION, ldv_list_addErr1REQUIRES_VIOLATION, ldv_list_addErr0REQUIRES_VIOLATION, ldv_kobject_createErr1REQUIRES_VIOLATION, ldv_kobject_createErr0REQUIRES_VIOLATION, ldv_destroy_msgsErr5REQUIRES_VIOLATION, ldv_destroy_msgsErr0REQUIRES_VIOLATION, ldv_destroy_msgsErr4REQUIRES_VIOLATION, ldv_destroy_msgsErr2REQUIRES_VIOLATION, ldv_destroy_msgsErr3REQUIRES_VIOLATION, ldv_destroy_msgsErr1REQUIRES_VIOLATION, ldv_msg_fillErr1REQUIRES_VIOLATION, ldv_msg_fillErr3REQUIRES_VIOLATION, ldv_msg_fillErr2REQUIRES_VIOLATION, ldv_msg_fillErr4REQUIRES_VIOLATION, ldv_msg_fillErr0REQUIRES_VIOLATION, ldv_msg_fillErr5REQUIRES_VIOLATION, ldv_atomic_add_returnErr2REQUIRES_VIOLATION, ldv_atomic_add_returnErr3REQUIRES_VIOLATION, ldv_atomic_add_returnErr1REQUIRES_VIOLATION, ldv_atomic_add_returnErr0REQUIRES_VIOLATION, __ldv_list_delErr0REQUIRES_VIOLATION, __ldv_list_delErr3REQUIRES_VIOLATION, __ldv_list_delErr2REQUIRES_VIOLATION, __ldv_list_delErr1REQUIRES_VIOLATION, ldv_kobject_cleanupErr2ASSERT_VIOLATIONMEMORY_FREE, ldv_kobject_cleanupErr0REQUIRES_VIOLATION, ldv_kobject_cleanupErr4ASSERT_VIOLATIONMEMORY_FREE, ldv_kobject_cleanupErr3ASSERT_VIOLATIONMEMORY_FREE, ldv_kobject_cleanupErr5ASSERT_VIOLATIONMEMORY_FREE, ldv_kobject_cleanupErr1REQUIRES_VIOLATION, ldv_msg_freeErr3ASSERT_VIOLATIONMEMORY_FREE, ldv_msg_freeErr5ASSERT_VIOLATIONMEMORY_FREE, ldv_msg_freeErr0REQUIRES_VIOLATION, ldv_msg_freeErr2ASSERT_VIOLATIONMEMORY_FREE, ldv_msg_freeErr1REQUIRES_VIOLATION, ldv_msg_freeErr4ASSERT_VIOLATIONMEMORY_FREE, mainErr0ENSURES_VIOLATIONMEMORY_LEAK, LDV_INIT_LIST_HEADErr3REQUIRES_VIOLATION, LDV_INIT_LIST_HEADErr2REQUIRES_VIOLATION, LDV_INIT_LIST_HEADErr1REQUIRES_VIOLATION, LDV_INIT_LIST_HEADErr0REQUIRES_VIOLATION, ldv_list_delErr2REQUIRES_VIOLATION, ldv_list_delErr3REQUIRES_VIOLATION, ldv_list_delErr1REQUIRES_VIOLATION, ldv_list_delErr0REQUIRES_VIOLATION, __ldv_list_addErr0REQUIRES_VIOLATION, __ldv_list_addErr5REQUIRES_VIOLATION, __ldv_list_addErr4REQUIRES_VIOLATION, __ldv_list_addErr3REQUIRES_VIOLATION, __ldv_list_addErr2REQUIRES_VIOLATION, __ldv_list_addErr7REQUIRES_VIOLATION, __ldv_list_addErr1REQUIRES_VIOLATION, __ldv_list_addErr6REQUIRES_VIOLATION, ldv_dev_set_drvdataErr1REQUIRES_VIOLATION, ldv_dev_set_drvdataErr0REQUIRES_VIOLATION, ldv_atomic_sub_returnErr2REQUIRES_VIOLATION, ldv_atomic_sub_returnErr3REQUIRES_VIOLATION, ldv_atomic_sub_returnErr1REQUIRES_VIOLATION, ldv_atomic_sub_returnErr0REQUIRES_VIOLATION, ldv_list_add_tailErr0REQUIRES_VIOLATION, ldv_list_add_tailErr1REQUIRES_VIOLATION, ldv_dev_get_drvdataErr1REQUIRES_VIOLATION, ldv_dev_get_drvdataErr0REQUIRES_VIOLATION, ldv_msg_allocErr0REQUIRES_VIOLATION, ldv_msg_allocErr1REQUIRES_VIOLATION]=== [2018-11-28 11:26:17,304 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-28 11:26:17,304 INFO L82 PathProgramCache]: Analyzing trace with hash 885785874, now seen corresponding path program 1 times [2018-11-28 11:26:17,304 INFO L223 ckRefinementStrategy]: Switched to mode CVC4_FPBP [2018-11-28 11:26:17,304 INFO L69 tionRefinementEngine]: Using refinement strategy WolfRefinementStrategy No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_2ca7a644-5b0a-4f3d-9179-f30a2c52dfce/bin-2019/uautomizer/cvc4 Starting monitored process 9 with cvc4 --incremental --print-success --lang smt --rewrite-divk (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 9 with cvc4 --incremental --print-success --lang smt --rewrite-divk [2018-11-28 11:26:17,324 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-28 11:26:17,393 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-28 11:26:17,396 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-28 11:26:17,445 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-28 11:26:17,445 INFO L312 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2018-11-28 11:26:17,447 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-28 11:26:17,447 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [7] imperfect sequences [] total 7 [2018-11-28 11:26:17,447 INFO L459 AbstractCegarLoop]: Interpolant automaton has 7 states [2018-11-28 11:26:17,448 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2018-11-28 11:26:17,448 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=11, Invalid=31, Unknown=0, NotChecked=0, Total=42 [2018-11-28 11:26:17,448 INFO L87 Difference]: Start difference. First operand 153 states and 160 transitions. Second operand 7 states. [2018-11-28 11:26:17,482 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-28 11:26:17,482 INFO L93 Difference]: Finished difference Result 163 states and 170 transitions. [2018-11-28 11:26:17,487 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 8 states. [2018-11-28 11:26:17,487 INFO L78 Accepts]: Start accepts. Automaton has 7 states. Word has length 36 [2018-11-28 11:26:17,488 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-28 11:26:17,488 INFO L225 Difference]: With dead ends: 163 [2018-11-28 11:26:17,489 INFO L226 Difference]: Without dead ends: 163 [2018-11-28 11:26:17,489 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 36 GetRequests, 30 SyntacticMatches, 0 SemanticMatches, 6 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=15, Invalid=41, Unknown=0, NotChecked=0, Total=56 [2018-11-28 11:26:17,489 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 163 states. [2018-11-28 11:26:17,493 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 163 to 159. [2018-11-28 11:26:17,493 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 159 states. [2018-11-28 11:26:17,494 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 159 states to 159 states and 166 transitions. [2018-11-28 11:26:17,494 INFO L78 Accepts]: Start accepts. Automaton has 159 states and 166 transitions. Word has length 36 [2018-11-28 11:26:17,494 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-28 11:26:17,494 INFO L480 AbstractCegarLoop]: Abstraction has 159 states and 166 transitions. [2018-11-28 11:26:17,494 INFO L481 AbstractCegarLoop]: Interpolant automaton has 7 states. [2018-11-28 11:26:17,494 INFO L276 IsEmpty]: Start isEmpty. Operand 159 states and 166 transitions. [2018-11-28 11:26:17,495 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 37 [2018-11-28 11:26:17,495 INFO L394 BasicCegarLoop]: Found error trace [2018-11-28 11:26:17,495 INFO L402 BasicCegarLoop]: trace histogram [4, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-28 11:26:17,497 INFO L423 AbstractCegarLoop]: === Iteration 9 === [ldv_kref_initErr0REQUIRES_VIOLATION, ldv_kref_initErr1REQUIRES_VIOLATION, ldv_list_addErr1REQUIRES_VIOLATION, ldv_list_addErr0REQUIRES_VIOLATION, ldv_kobject_createErr1REQUIRES_VIOLATION, ldv_kobject_createErr0REQUIRES_VIOLATION, ldv_destroy_msgsErr5REQUIRES_VIOLATION, ldv_destroy_msgsErr0REQUIRES_VIOLATION, ldv_destroy_msgsErr4REQUIRES_VIOLATION, ldv_destroy_msgsErr2REQUIRES_VIOLATION, ldv_destroy_msgsErr3REQUIRES_VIOLATION, ldv_destroy_msgsErr1REQUIRES_VIOLATION, ldv_msg_fillErr1REQUIRES_VIOLATION, ldv_msg_fillErr3REQUIRES_VIOLATION, ldv_msg_fillErr2REQUIRES_VIOLATION, ldv_msg_fillErr4REQUIRES_VIOLATION, ldv_msg_fillErr0REQUIRES_VIOLATION, ldv_msg_fillErr5REQUIRES_VIOLATION, ldv_atomic_add_returnErr2REQUIRES_VIOLATION, ldv_atomic_add_returnErr3REQUIRES_VIOLATION, ldv_atomic_add_returnErr1REQUIRES_VIOLATION, ldv_atomic_add_returnErr0REQUIRES_VIOLATION, __ldv_list_delErr0REQUIRES_VIOLATION, __ldv_list_delErr3REQUIRES_VIOLATION, __ldv_list_delErr2REQUIRES_VIOLATION, __ldv_list_delErr1REQUIRES_VIOLATION, ldv_kobject_cleanupErr2ASSERT_VIOLATIONMEMORY_FREE, ldv_kobject_cleanupErr0REQUIRES_VIOLATION, ldv_kobject_cleanupErr4ASSERT_VIOLATIONMEMORY_FREE, ldv_kobject_cleanupErr3ASSERT_VIOLATIONMEMORY_FREE, ldv_kobject_cleanupErr5ASSERT_VIOLATIONMEMORY_FREE, ldv_kobject_cleanupErr1REQUIRES_VIOLATION, ldv_msg_freeErr3ASSERT_VIOLATIONMEMORY_FREE, ldv_msg_freeErr5ASSERT_VIOLATIONMEMORY_FREE, ldv_msg_freeErr0REQUIRES_VIOLATION, ldv_msg_freeErr2ASSERT_VIOLATIONMEMORY_FREE, ldv_msg_freeErr1REQUIRES_VIOLATION, ldv_msg_freeErr4ASSERT_VIOLATIONMEMORY_FREE, mainErr0ENSURES_VIOLATIONMEMORY_LEAK, LDV_INIT_LIST_HEADErr3REQUIRES_VIOLATION, LDV_INIT_LIST_HEADErr2REQUIRES_VIOLATION, LDV_INIT_LIST_HEADErr1REQUIRES_VIOLATION, LDV_INIT_LIST_HEADErr0REQUIRES_VIOLATION, ldv_list_delErr2REQUIRES_VIOLATION, ldv_list_delErr3REQUIRES_VIOLATION, ldv_list_delErr1REQUIRES_VIOLATION, ldv_list_delErr0REQUIRES_VIOLATION, __ldv_list_addErr0REQUIRES_VIOLATION, __ldv_list_addErr5REQUIRES_VIOLATION, __ldv_list_addErr4REQUIRES_VIOLATION, __ldv_list_addErr3REQUIRES_VIOLATION, __ldv_list_addErr2REQUIRES_VIOLATION, __ldv_list_addErr7REQUIRES_VIOLATION, __ldv_list_addErr1REQUIRES_VIOLATION, __ldv_list_addErr6REQUIRES_VIOLATION, ldv_dev_set_drvdataErr1REQUIRES_VIOLATION, ldv_dev_set_drvdataErr0REQUIRES_VIOLATION, ldv_atomic_sub_returnErr2REQUIRES_VIOLATION, ldv_atomic_sub_returnErr3REQUIRES_VIOLATION, ldv_atomic_sub_returnErr1REQUIRES_VIOLATION, ldv_atomic_sub_returnErr0REQUIRES_VIOLATION, ldv_list_add_tailErr0REQUIRES_VIOLATION, ldv_list_add_tailErr1REQUIRES_VIOLATION, ldv_dev_get_drvdataErr1REQUIRES_VIOLATION, ldv_dev_get_drvdataErr0REQUIRES_VIOLATION, ldv_msg_allocErr0REQUIRES_VIOLATION, ldv_msg_allocErr1REQUIRES_VIOLATION]=== [2018-11-28 11:26:17,497 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-28 11:26:17,497 INFO L82 PathProgramCache]: Analyzing trace with hash -1369388837, now seen corresponding path program 2 times [2018-11-28 11:26:17,497 INFO L223 ckRefinementStrategy]: Switched to mode CVC4_FPBP [2018-11-28 11:26:17,497 INFO L69 tionRefinementEngine]: Using refinement strategy WolfRefinementStrategy No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_2ca7a644-5b0a-4f3d-9179-f30a2c52dfce/bin-2019/uautomizer/cvc4 Starting monitored process 10 with cvc4 --incremental --print-success --lang smt --rewrite-divk (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 10 with cvc4 --incremental --print-success --lang smt --rewrite-divk [2018-11-28 11:26:17,527 INFO L101 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2018-11-28 11:26:17,580 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) [2018-11-28 11:26:17,580 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-11-28 11:26:17,583 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-28 11:26:17,585 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 6 treesize of output 5 [2018-11-28 11:26:17,585 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-11-28 11:26:17,586 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-28 11:26:17,587 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 1 variables, input treesize:6, output treesize:5 [2018-11-28 11:26:17,690 INFO L134 CoverageAnalysis]: Checked inductivity of 10 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 10 trivial. 0 not checked. [2018-11-28 11:26:17,690 INFO L312 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2018-11-28 11:26:17,695 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-28 11:26:17,696 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [12] imperfect sequences [] total 12 [2018-11-28 11:26:17,696 INFO L459 AbstractCegarLoop]: Interpolant automaton has 13 states [2018-11-28 11:26:17,696 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 13 interpolants. [2018-11-28 11:26:17,696 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=33, Invalid=123, Unknown=0, NotChecked=0, Total=156 [2018-11-28 11:26:17,696 INFO L87 Difference]: Start difference. First operand 159 states and 166 transitions. Second operand 13 states. [2018-11-28 11:26:18,549 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-28 11:26:18,549 INFO L93 Difference]: Finished difference Result 170 states and 176 transitions. [2018-11-28 11:26:18,550 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 13 states. [2018-11-28 11:26:18,550 INFO L78 Accepts]: Start accepts. Automaton has 13 states. Word has length 36 [2018-11-28 11:26:18,550 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-28 11:26:18,550 INFO L225 Difference]: With dead ends: 170 [2018-11-28 11:26:18,550 INFO L226 Difference]: Without dead ends: 170 [2018-11-28 11:26:18,551 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 38 GetRequests, 23 SyntacticMatches, 1 SemanticMatches, 14 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 12 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=48, Invalid=192, Unknown=0, NotChecked=0, Total=240 [2018-11-28 11:26:18,551 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 170 states. [2018-11-28 11:26:18,554 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 170 to 158. [2018-11-28 11:26:18,554 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 158 states. [2018-11-28 11:26:18,555 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 158 states to 158 states and 165 transitions. [2018-11-28 11:26:18,555 INFO L78 Accepts]: Start accepts. Automaton has 158 states and 165 transitions. Word has length 36 [2018-11-28 11:26:18,555 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-28 11:26:18,556 INFO L480 AbstractCegarLoop]: Abstraction has 158 states and 165 transitions. [2018-11-28 11:26:18,556 INFO L481 AbstractCegarLoop]: Interpolant automaton has 13 states. [2018-11-28 11:26:18,556 INFO L276 IsEmpty]: Start isEmpty. Operand 158 states and 165 transitions. [2018-11-28 11:26:18,556 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 37 [2018-11-28 11:26:18,556 INFO L394 BasicCegarLoop]: Found error trace [2018-11-28 11:26:18,556 INFO L402 BasicCegarLoop]: trace histogram [4, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-28 11:26:18,557 INFO L423 AbstractCegarLoop]: === Iteration 10 === [ldv_kref_initErr0REQUIRES_VIOLATION, ldv_kref_initErr1REQUIRES_VIOLATION, ldv_list_addErr1REQUIRES_VIOLATION, ldv_list_addErr0REQUIRES_VIOLATION, ldv_kobject_createErr1REQUIRES_VIOLATION, ldv_kobject_createErr0REQUIRES_VIOLATION, ldv_destroy_msgsErr5REQUIRES_VIOLATION, ldv_destroy_msgsErr0REQUIRES_VIOLATION, ldv_destroy_msgsErr4REQUIRES_VIOLATION, ldv_destroy_msgsErr2REQUIRES_VIOLATION, ldv_destroy_msgsErr3REQUIRES_VIOLATION, ldv_destroy_msgsErr1REQUIRES_VIOLATION, ldv_msg_fillErr1REQUIRES_VIOLATION, ldv_msg_fillErr3REQUIRES_VIOLATION, ldv_msg_fillErr2REQUIRES_VIOLATION, ldv_msg_fillErr4REQUIRES_VIOLATION, ldv_msg_fillErr0REQUIRES_VIOLATION, ldv_msg_fillErr5REQUIRES_VIOLATION, ldv_atomic_add_returnErr2REQUIRES_VIOLATION, ldv_atomic_add_returnErr3REQUIRES_VIOLATION, ldv_atomic_add_returnErr1REQUIRES_VIOLATION, ldv_atomic_add_returnErr0REQUIRES_VIOLATION, __ldv_list_delErr0REQUIRES_VIOLATION, __ldv_list_delErr3REQUIRES_VIOLATION, __ldv_list_delErr2REQUIRES_VIOLATION, __ldv_list_delErr1REQUIRES_VIOLATION, ldv_kobject_cleanupErr2ASSERT_VIOLATIONMEMORY_FREE, ldv_kobject_cleanupErr0REQUIRES_VIOLATION, ldv_kobject_cleanupErr4ASSERT_VIOLATIONMEMORY_FREE, ldv_kobject_cleanupErr3ASSERT_VIOLATIONMEMORY_FREE, ldv_kobject_cleanupErr5ASSERT_VIOLATIONMEMORY_FREE, ldv_kobject_cleanupErr1REQUIRES_VIOLATION, ldv_msg_freeErr3ASSERT_VIOLATIONMEMORY_FREE, ldv_msg_freeErr5ASSERT_VIOLATIONMEMORY_FREE, ldv_msg_freeErr0REQUIRES_VIOLATION, ldv_msg_freeErr2ASSERT_VIOLATIONMEMORY_FREE, ldv_msg_freeErr1REQUIRES_VIOLATION, ldv_msg_freeErr4ASSERT_VIOLATIONMEMORY_FREE, mainErr0ENSURES_VIOLATIONMEMORY_LEAK, LDV_INIT_LIST_HEADErr3REQUIRES_VIOLATION, LDV_INIT_LIST_HEADErr2REQUIRES_VIOLATION, LDV_INIT_LIST_HEADErr1REQUIRES_VIOLATION, LDV_INIT_LIST_HEADErr0REQUIRES_VIOLATION, ldv_list_delErr2REQUIRES_VIOLATION, ldv_list_delErr3REQUIRES_VIOLATION, ldv_list_delErr1REQUIRES_VIOLATION, ldv_list_delErr0REQUIRES_VIOLATION, __ldv_list_addErr0REQUIRES_VIOLATION, __ldv_list_addErr5REQUIRES_VIOLATION, __ldv_list_addErr4REQUIRES_VIOLATION, __ldv_list_addErr3REQUIRES_VIOLATION, __ldv_list_addErr2REQUIRES_VIOLATION, __ldv_list_addErr7REQUIRES_VIOLATION, __ldv_list_addErr1REQUIRES_VIOLATION, __ldv_list_addErr6REQUIRES_VIOLATION, ldv_dev_set_drvdataErr1REQUIRES_VIOLATION, ldv_dev_set_drvdataErr0REQUIRES_VIOLATION, ldv_atomic_sub_returnErr2REQUIRES_VIOLATION, ldv_atomic_sub_returnErr3REQUIRES_VIOLATION, ldv_atomic_sub_returnErr1REQUIRES_VIOLATION, ldv_atomic_sub_returnErr0REQUIRES_VIOLATION, ldv_list_add_tailErr0REQUIRES_VIOLATION, ldv_list_add_tailErr1REQUIRES_VIOLATION, ldv_dev_get_drvdataErr1REQUIRES_VIOLATION, ldv_dev_get_drvdataErr0REQUIRES_VIOLATION, ldv_msg_allocErr0REQUIRES_VIOLATION, ldv_msg_allocErr1REQUIRES_VIOLATION]=== [2018-11-28 11:26:18,557 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-28 11:26:18,557 INFO L82 PathProgramCache]: Analyzing trace with hash -1369388836, now seen corresponding path program 1 times [2018-11-28 11:26:18,557 INFO L223 ckRefinementStrategy]: Switched to mode CVC4_FPBP [2018-11-28 11:26:18,557 INFO L69 tionRefinementEngine]: Using refinement strategy WolfRefinementStrategy No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_2ca7a644-5b0a-4f3d-9179-f30a2c52dfce/bin-2019/uautomizer/cvc4 Starting monitored process 11 with cvc4 --incremental --print-success --lang smt --rewrite-divk (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 11 with cvc4 --incremental --print-success --lang smt --rewrite-divk [2018-11-28 11:26:18,573 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-28 11:26:18,641 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-28 11:26:18,643 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-28 11:26:18,672 INFO L134 CoverageAnalysis]: Checked inductivity of 10 backedges. 0 proven. 10 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-28 11:26:18,672 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-11-28 11:26:18,798 INFO L134 CoverageAnalysis]: Checked inductivity of 10 backedges. 0 proven. 10 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-28 11:26:18,801 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-11-28 11:26:18,802 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [8, 8] total 14 [2018-11-28 11:26:18,802 INFO L459 AbstractCegarLoop]: Interpolant automaton has 14 states [2018-11-28 11:26:18,802 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 14 interpolants. [2018-11-28 11:26:18,802 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=61, Invalid=121, Unknown=0, NotChecked=0, Total=182 [2018-11-28 11:26:18,802 INFO L87 Difference]: Start difference. First operand 158 states and 165 transitions. Second operand 14 states. [2018-11-28 11:26:19,234 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-28 11:26:19,234 INFO L93 Difference]: Finished difference Result 168 states and 179 transitions. [2018-11-28 11:26:19,235 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 14 states. [2018-11-28 11:26:19,235 INFO L78 Accepts]: Start accepts. Automaton has 14 states. Word has length 36 [2018-11-28 11:26:19,235 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-28 11:26:19,236 INFO L225 Difference]: With dead ends: 168 [2018-11-28 11:26:19,236 INFO L226 Difference]: Without dead ends: 164 [2018-11-28 11:26:19,236 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 76 GetRequests, 58 SyntacticMatches, 1 SemanticMatches, 17 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 12 ImplicationChecksByTransitivity, 0.3s TimeCoverageRelationStatistics Valid=131, Invalid=211, Unknown=0, NotChecked=0, Total=342 [2018-11-28 11:26:19,237 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 164 states. [2018-11-28 11:26:19,240 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 164 to 164. [2018-11-28 11:26:19,240 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 164 states. [2018-11-28 11:26:19,241 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 164 states to 164 states and 171 transitions. [2018-11-28 11:26:19,241 INFO L78 Accepts]: Start accepts. Automaton has 164 states and 171 transitions. Word has length 36 [2018-11-28 11:26:19,242 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-28 11:26:19,242 INFO L480 AbstractCegarLoop]: Abstraction has 164 states and 171 transitions. [2018-11-28 11:26:19,242 INFO L481 AbstractCegarLoop]: Interpolant automaton has 14 states. [2018-11-28 11:26:19,242 INFO L276 IsEmpty]: Start isEmpty. Operand 164 states and 171 transitions. [2018-11-28 11:26:19,242 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 35 [2018-11-28 11:26:19,242 INFO L394 BasicCegarLoop]: Found error trace [2018-11-28 11:26:19,243 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-28 11:26:19,243 INFO L423 AbstractCegarLoop]: === Iteration 11 === [ldv_kref_initErr0REQUIRES_VIOLATION, ldv_kref_initErr1REQUIRES_VIOLATION, ldv_list_addErr1REQUIRES_VIOLATION, ldv_list_addErr0REQUIRES_VIOLATION, ldv_kobject_createErr1REQUIRES_VIOLATION, ldv_kobject_createErr0REQUIRES_VIOLATION, ldv_destroy_msgsErr5REQUIRES_VIOLATION, ldv_destroy_msgsErr0REQUIRES_VIOLATION, ldv_destroy_msgsErr4REQUIRES_VIOLATION, ldv_destroy_msgsErr2REQUIRES_VIOLATION, ldv_destroy_msgsErr3REQUIRES_VIOLATION, ldv_destroy_msgsErr1REQUIRES_VIOLATION, ldv_msg_fillErr1REQUIRES_VIOLATION, ldv_msg_fillErr3REQUIRES_VIOLATION, ldv_msg_fillErr2REQUIRES_VIOLATION, ldv_msg_fillErr4REQUIRES_VIOLATION, ldv_msg_fillErr0REQUIRES_VIOLATION, ldv_msg_fillErr5REQUIRES_VIOLATION, ldv_atomic_add_returnErr2REQUIRES_VIOLATION, ldv_atomic_add_returnErr3REQUIRES_VIOLATION, ldv_atomic_add_returnErr1REQUIRES_VIOLATION, ldv_atomic_add_returnErr0REQUIRES_VIOLATION, __ldv_list_delErr0REQUIRES_VIOLATION, __ldv_list_delErr3REQUIRES_VIOLATION, __ldv_list_delErr2REQUIRES_VIOLATION, __ldv_list_delErr1REQUIRES_VIOLATION, ldv_kobject_cleanupErr2ASSERT_VIOLATIONMEMORY_FREE, ldv_kobject_cleanupErr0REQUIRES_VIOLATION, ldv_kobject_cleanupErr4ASSERT_VIOLATIONMEMORY_FREE, ldv_kobject_cleanupErr3ASSERT_VIOLATIONMEMORY_FREE, ldv_kobject_cleanupErr5ASSERT_VIOLATIONMEMORY_FREE, ldv_kobject_cleanupErr1REQUIRES_VIOLATION, ldv_msg_freeErr3ASSERT_VIOLATIONMEMORY_FREE, ldv_msg_freeErr5ASSERT_VIOLATIONMEMORY_FREE, ldv_msg_freeErr0REQUIRES_VIOLATION, ldv_msg_freeErr2ASSERT_VIOLATIONMEMORY_FREE, ldv_msg_freeErr1REQUIRES_VIOLATION, ldv_msg_freeErr4ASSERT_VIOLATIONMEMORY_FREE, mainErr0ENSURES_VIOLATIONMEMORY_LEAK, LDV_INIT_LIST_HEADErr3REQUIRES_VIOLATION, LDV_INIT_LIST_HEADErr2REQUIRES_VIOLATION, LDV_INIT_LIST_HEADErr1REQUIRES_VIOLATION, LDV_INIT_LIST_HEADErr0REQUIRES_VIOLATION, ldv_list_delErr2REQUIRES_VIOLATION, ldv_list_delErr3REQUIRES_VIOLATION, ldv_list_delErr1REQUIRES_VIOLATION, ldv_list_delErr0REQUIRES_VIOLATION, __ldv_list_addErr0REQUIRES_VIOLATION, __ldv_list_addErr5REQUIRES_VIOLATION, __ldv_list_addErr4REQUIRES_VIOLATION, __ldv_list_addErr3REQUIRES_VIOLATION, __ldv_list_addErr2REQUIRES_VIOLATION, __ldv_list_addErr7REQUIRES_VIOLATION, __ldv_list_addErr1REQUIRES_VIOLATION, __ldv_list_addErr6REQUIRES_VIOLATION, ldv_dev_set_drvdataErr1REQUIRES_VIOLATION, ldv_dev_set_drvdataErr0REQUIRES_VIOLATION, ldv_atomic_sub_returnErr2REQUIRES_VIOLATION, ldv_atomic_sub_returnErr3REQUIRES_VIOLATION, ldv_atomic_sub_returnErr1REQUIRES_VIOLATION, ldv_atomic_sub_returnErr0REQUIRES_VIOLATION, ldv_list_add_tailErr0REQUIRES_VIOLATION, ldv_list_add_tailErr1REQUIRES_VIOLATION, ldv_dev_get_drvdataErr1REQUIRES_VIOLATION, ldv_dev_get_drvdataErr0REQUIRES_VIOLATION, ldv_msg_allocErr0REQUIRES_VIOLATION, ldv_msg_allocErr1REQUIRES_VIOLATION]=== [2018-11-28 11:26:19,243 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-28 11:26:19,243 INFO L82 PathProgramCache]: Analyzing trace with hash 124691458, now seen corresponding path program 1 times [2018-11-28 11:26:19,243 INFO L223 ckRefinementStrategy]: Switched to mode CVC4_FPBP [2018-11-28 11:26:19,244 INFO L69 tionRefinementEngine]: Using refinement strategy WolfRefinementStrategy No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_2ca7a644-5b0a-4f3d-9179-f30a2c52dfce/bin-2019/uautomizer/cvc4 Starting monitored process 12 with cvc4 --incremental --print-success --lang smt --rewrite-divk (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 12 with cvc4 --incremental --print-success --lang smt --rewrite-divk [2018-11-28 11:26:19,260 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-28 11:26:19,280 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-28 11:26:19,282 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-28 11:26:19,291 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-28 11:26:19,291 INFO L312 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2018-11-28 11:26:19,293 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-28 11:26:19,293 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2018-11-28 11:26:19,293 INFO L459 AbstractCegarLoop]: Interpolant automaton has 3 states [2018-11-28 11:26:19,294 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-28 11:26:19,294 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-28 11:26:19,294 INFO L87 Difference]: Start difference. First operand 164 states and 171 transitions. Second operand 3 states. [2018-11-28 11:26:19,409 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-28 11:26:19,409 INFO L93 Difference]: Finished difference Result 175 states and 181 transitions. [2018-11-28 11:26:19,410 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-28 11:26:19,410 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 34 [2018-11-28 11:26:19,410 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-28 11:26:19,411 INFO L225 Difference]: With dead ends: 175 [2018-11-28 11:26:19,411 INFO L226 Difference]: Without dead ends: 153 [2018-11-28 11:26:19,411 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 33 GetRequests, 32 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-28 11:26:19,412 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 153 states. [2018-11-28 11:26:19,413 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 153 to 145. [2018-11-28 11:26:19,413 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 145 states. [2018-11-28 11:26:19,414 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 145 states to 145 states and 151 transitions. [2018-11-28 11:26:19,414 INFO L78 Accepts]: Start accepts. Automaton has 145 states and 151 transitions. Word has length 34 [2018-11-28 11:26:19,414 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-28 11:26:19,414 INFO L480 AbstractCegarLoop]: Abstraction has 145 states and 151 transitions. [2018-11-28 11:26:19,414 INFO L481 AbstractCegarLoop]: Interpolant automaton has 3 states. [2018-11-28 11:26:19,414 INFO L276 IsEmpty]: Start isEmpty. Operand 145 states and 151 transitions. [2018-11-28 11:26:19,415 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 43 [2018-11-28 11:26:19,415 INFO L394 BasicCegarLoop]: Found error trace [2018-11-28 11:26:19,415 INFO L402 BasicCegarLoop]: trace histogram [10, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-28 11:26:19,415 INFO L423 AbstractCegarLoop]: === Iteration 12 === [ldv_kref_initErr0REQUIRES_VIOLATION, ldv_kref_initErr1REQUIRES_VIOLATION, ldv_list_addErr1REQUIRES_VIOLATION, ldv_list_addErr0REQUIRES_VIOLATION, ldv_kobject_createErr1REQUIRES_VIOLATION, ldv_kobject_createErr0REQUIRES_VIOLATION, ldv_destroy_msgsErr5REQUIRES_VIOLATION, ldv_destroy_msgsErr0REQUIRES_VIOLATION, ldv_destroy_msgsErr4REQUIRES_VIOLATION, ldv_destroy_msgsErr2REQUIRES_VIOLATION, ldv_destroy_msgsErr3REQUIRES_VIOLATION, ldv_destroy_msgsErr1REQUIRES_VIOLATION, ldv_msg_fillErr1REQUIRES_VIOLATION, ldv_msg_fillErr3REQUIRES_VIOLATION, ldv_msg_fillErr2REQUIRES_VIOLATION, ldv_msg_fillErr4REQUIRES_VIOLATION, ldv_msg_fillErr0REQUIRES_VIOLATION, ldv_msg_fillErr5REQUIRES_VIOLATION, ldv_atomic_add_returnErr2REQUIRES_VIOLATION, ldv_atomic_add_returnErr3REQUIRES_VIOLATION, ldv_atomic_add_returnErr1REQUIRES_VIOLATION, ldv_atomic_add_returnErr0REQUIRES_VIOLATION, __ldv_list_delErr0REQUIRES_VIOLATION, __ldv_list_delErr3REQUIRES_VIOLATION, __ldv_list_delErr2REQUIRES_VIOLATION, __ldv_list_delErr1REQUIRES_VIOLATION, ldv_kobject_cleanupErr2ASSERT_VIOLATIONMEMORY_FREE, ldv_kobject_cleanupErr0REQUIRES_VIOLATION, ldv_kobject_cleanupErr4ASSERT_VIOLATIONMEMORY_FREE, ldv_kobject_cleanupErr3ASSERT_VIOLATIONMEMORY_FREE, ldv_kobject_cleanupErr5ASSERT_VIOLATIONMEMORY_FREE, ldv_kobject_cleanupErr1REQUIRES_VIOLATION, ldv_msg_freeErr3ASSERT_VIOLATIONMEMORY_FREE, ldv_msg_freeErr5ASSERT_VIOLATIONMEMORY_FREE, ldv_msg_freeErr0REQUIRES_VIOLATION, ldv_msg_freeErr2ASSERT_VIOLATIONMEMORY_FREE, ldv_msg_freeErr1REQUIRES_VIOLATION, ldv_msg_freeErr4ASSERT_VIOLATIONMEMORY_FREE, mainErr0ENSURES_VIOLATIONMEMORY_LEAK, LDV_INIT_LIST_HEADErr3REQUIRES_VIOLATION, LDV_INIT_LIST_HEADErr2REQUIRES_VIOLATION, LDV_INIT_LIST_HEADErr1REQUIRES_VIOLATION, LDV_INIT_LIST_HEADErr0REQUIRES_VIOLATION, ldv_list_delErr2REQUIRES_VIOLATION, ldv_list_delErr3REQUIRES_VIOLATION, ldv_list_delErr1REQUIRES_VIOLATION, ldv_list_delErr0REQUIRES_VIOLATION, __ldv_list_addErr0REQUIRES_VIOLATION, __ldv_list_addErr5REQUIRES_VIOLATION, __ldv_list_addErr4REQUIRES_VIOLATION, __ldv_list_addErr3REQUIRES_VIOLATION, __ldv_list_addErr2REQUIRES_VIOLATION, __ldv_list_addErr7REQUIRES_VIOLATION, __ldv_list_addErr1REQUIRES_VIOLATION, __ldv_list_addErr6REQUIRES_VIOLATION, ldv_dev_set_drvdataErr1REQUIRES_VIOLATION, ldv_dev_set_drvdataErr0REQUIRES_VIOLATION, ldv_atomic_sub_returnErr2REQUIRES_VIOLATION, ldv_atomic_sub_returnErr3REQUIRES_VIOLATION, ldv_atomic_sub_returnErr1REQUIRES_VIOLATION, ldv_atomic_sub_returnErr0REQUIRES_VIOLATION, ldv_list_add_tailErr0REQUIRES_VIOLATION, ldv_list_add_tailErr1REQUIRES_VIOLATION, ldv_dev_get_drvdataErr1REQUIRES_VIOLATION, ldv_dev_get_drvdataErr0REQUIRES_VIOLATION, ldv_msg_allocErr0REQUIRES_VIOLATION, ldv_msg_allocErr1REQUIRES_VIOLATION]=== [2018-11-28 11:26:19,415 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-28 11:26:19,416 INFO L82 PathProgramCache]: Analyzing trace with hash -1662093060, now seen corresponding path program 2 times [2018-11-28 11:26:19,416 INFO L223 ckRefinementStrategy]: Switched to mode CVC4_FPBP [2018-11-28 11:26:19,416 INFO L69 tionRefinementEngine]: Using refinement strategy WolfRefinementStrategy No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_2ca7a644-5b0a-4f3d-9179-f30a2c52dfce/bin-2019/uautomizer/cvc4 Starting monitored process 13 with cvc4 --incremental --print-success --lang smt --rewrite-divk (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 13 with cvc4 --incremental --print-success --lang smt --rewrite-divk [2018-11-28 11:26:19,435 INFO L101 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2018-11-28 11:26:19,488 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) [2018-11-28 11:26:19,488 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-11-28 11:26:19,491 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-28 11:26:19,496 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 6 treesize of output 5 [2018-11-28 11:26:19,497 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-11-28 11:26:19,501 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-28 11:26:19,501 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 1 variables, input treesize:10, output treesize:9 [2018-11-28 11:26:19,672 INFO L134 CoverageAnalysis]: Checked inductivity of 55 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 55 trivial. 0 not checked. [2018-11-28 11:26:19,672 INFO L312 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2018-11-28 11:26:19,674 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-28 11:26:19,674 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [12] imperfect sequences [] total 12 [2018-11-28 11:26:19,674 INFO L459 AbstractCegarLoop]: Interpolant automaton has 13 states [2018-11-28 11:26:19,675 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 13 interpolants. [2018-11-28 11:26:19,675 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=31, Invalid=125, Unknown=0, NotChecked=0, Total=156 [2018-11-28 11:26:19,675 INFO L87 Difference]: Start difference. First operand 145 states and 151 transitions. Second operand 13 states. [2018-11-28 11:26:20,502 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-28 11:26:20,503 INFO L93 Difference]: Finished difference Result 144 states and 150 transitions. [2018-11-28 11:26:20,503 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 13 states. [2018-11-28 11:26:20,503 INFO L78 Accepts]: Start accepts. Automaton has 13 states. Word has length 42 [2018-11-28 11:26:20,503 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-28 11:26:20,504 INFO L225 Difference]: With dead ends: 144 [2018-11-28 11:26:20,504 INFO L226 Difference]: Without dead ends: 144 [2018-11-28 11:26:20,504 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 45 GetRequests, 29 SyntacticMatches, 1 SemanticMatches, 15 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 20 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=50, Invalid=222, Unknown=0, NotChecked=0, Total=272 [2018-11-28 11:26:20,505 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 144 states. [2018-11-28 11:26:20,507 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 144 to 144. [2018-11-28 11:26:20,507 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 144 states. [2018-11-28 11:26:20,507 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 144 states to 144 states and 150 transitions. [2018-11-28 11:26:20,508 INFO L78 Accepts]: Start accepts. Automaton has 144 states and 150 transitions. Word has length 42 [2018-11-28 11:26:20,508 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-28 11:26:20,508 INFO L480 AbstractCegarLoop]: Abstraction has 144 states and 150 transitions. [2018-11-28 11:26:20,508 INFO L481 AbstractCegarLoop]: Interpolant automaton has 13 states. [2018-11-28 11:26:20,508 INFO L276 IsEmpty]: Start isEmpty. Operand 144 states and 150 transitions. [2018-11-28 11:26:20,509 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 48 [2018-11-28 11:26:20,509 INFO L394 BasicCegarLoop]: Found error trace [2018-11-28 11:26:20,509 INFO L402 BasicCegarLoop]: trace histogram [10, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-28 11:26:20,509 INFO L423 AbstractCegarLoop]: === Iteration 13 === [ldv_kref_initErr0REQUIRES_VIOLATION, ldv_kref_initErr1REQUIRES_VIOLATION, ldv_list_addErr1REQUIRES_VIOLATION, ldv_list_addErr0REQUIRES_VIOLATION, ldv_kobject_createErr1REQUIRES_VIOLATION, ldv_kobject_createErr0REQUIRES_VIOLATION, ldv_destroy_msgsErr5REQUIRES_VIOLATION, ldv_destroy_msgsErr0REQUIRES_VIOLATION, ldv_destroy_msgsErr4REQUIRES_VIOLATION, ldv_destroy_msgsErr2REQUIRES_VIOLATION, ldv_destroy_msgsErr3REQUIRES_VIOLATION, ldv_destroy_msgsErr1REQUIRES_VIOLATION, ldv_msg_fillErr1REQUIRES_VIOLATION, ldv_msg_fillErr3REQUIRES_VIOLATION, ldv_msg_fillErr2REQUIRES_VIOLATION, ldv_msg_fillErr4REQUIRES_VIOLATION, ldv_msg_fillErr0REQUIRES_VIOLATION, ldv_msg_fillErr5REQUIRES_VIOLATION, ldv_atomic_add_returnErr2REQUIRES_VIOLATION, ldv_atomic_add_returnErr3REQUIRES_VIOLATION, ldv_atomic_add_returnErr1REQUIRES_VIOLATION, ldv_atomic_add_returnErr0REQUIRES_VIOLATION, __ldv_list_delErr0REQUIRES_VIOLATION, __ldv_list_delErr3REQUIRES_VIOLATION, __ldv_list_delErr2REQUIRES_VIOLATION, __ldv_list_delErr1REQUIRES_VIOLATION, ldv_kobject_cleanupErr2ASSERT_VIOLATIONMEMORY_FREE, ldv_kobject_cleanupErr0REQUIRES_VIOLATION, ldv_kobject_cleanupErr4ASSERT_VIOLATIONMEMORY_FREE, ldv_kobject_cleanupErr3ASSERT_VIOLATIONMEMORY_FREE, ldv_kobject_cleanupErr5ASSERT_VIOLATIONMEMORY_FREE, ldv_kobject_cleanupErr1REQUIRES_VIOLATION, ldv_msg_freeErr3ASSERT_VIOLATIONMEMORY_FREE, ldv_msg_freeErr5ASSERT_VIOLATIONMEMORY_FREE, ldv_msg_freeErr0REQUIRES_VIOLATION, ldv_msg_freeErr2ASSERT_VIOLATIONMEMORY_FREE, ldv_msg_freeErr1REQUIRES_VIOLATION, ldv_msg_freeErr4ASSERT_VIOLATIONMEMORY_FREE, mainErr0ENSURES_VIOLATIONMEMORY_LEAK, LDV_INIT_LIST_HEADErr3REQUIRES_VIOLATION, LDV_INIT_LIST_HEADErr2REQUIRES_VIOLATION, LDV_INIT_LIST_HEADErr1REQUIRES_VIOLATION, LDV_INIT_LIST_HEADErr0REQUIRES_VIOLATION, ldv_list_delErr2REQUIRES_VIOLATION, ldv_list_delErr3REQUIRES_VIOLATION, ldv_list_delErr1REQUIRES_VIOLATION, ldv_list_delErr0REQUIRES_VIOLATION, __ldv_list_addErr0REQUIRES_VIOLATION, __ldv_list_addErr5REQUIRES_VIOLATION, __ldv_list_addErr4REQUIRES_VIOLATION, __ldv_list_addErr3REQUIRES_VIOLATION, __ldv_list_addErr2REQUIRES_VIOLATION, __ldv_list_addErr7REQUIRES_VIOLATION, __ldv_list_addErr1REQUIRES_VIOLATION, __ldv_list_addErr6REQUIRES_VIOLATION, ldv_dev_set_drvdataErr1REQUIRES_VIOLATION, ldv_dev_set_drvdataErr0REQUIRES_VIOLATION, ldv_atomic_sub_returnErr2REQUIRES_VIOLATION, ldv_atomic_sub_returnErr3REQUIRES_VIOLATION, ldv_atomic_sub_returnErr1REQUIRES_VIOLATION, ldv_atomic_sub_returnErr0REQUIRES_VIOLATION, ldv_list_add_tailErr0REQUIRES_VIOLATION, ldv_list_add_tailErr1REQUIRES_VIOLATION, ldv_dev_get_drvdataErr1REQUIRES_VIOLATION, ldv_dev_get_drvdataErr0REQUIRES_VIOLATION, ldv_msg_allocErr0REQUIRES_VIOLATION, ldv_msg_allocErr1REQUIRES_VIOLATION]=== [2018-11-28 11:26:20,509 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-28 11:26:20,510 INFO L82 PathProgramCache]: Analyzing trace with hash -1164712948, now seen corresponding path program 1 times [2018-11-28 11:26:20,510 INFO L223 ckRefinementStrategy]: Switched to mode CVC4_FPBP [2018-11-28 11:26:20,510 INFO L69 tionRefinementEngine]: Using refinement strategy WolfRefinementStrategy No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_2ca7a644-5b0a-4f3d-9179-f30a2c52dfce/bin-2019/uautomizer/cvc4 Starting monitored process 14 with cvc4 --incremental --print-success --lang smt --rewrite-divk (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 14 with cvc4 --incremental --print-success --lang smt --rewrite-divk [2018-11-28 11:26:20,526 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-28 11:26:20,626 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-28 11:26:20,630 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-28 11:26:20,702 INFO L134 CoverageAnalysis]: Checked inductivity of 55 backedges. 0 proven. 55 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-28 11:26:20,702 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-11-28 11:26:21,128 INFO L134 CoverageAnalysis]: Checked inductivity of 55 backedges. 0 proven. 55 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-28 11:26:21,130 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-11-28 11:26:21,130 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [14, 14] total 26 [2018-11-28 11:26:21,130 INFO L459 AbstractCegarLoop]: Interpolant automaton has 26 states [2018-11-28 11:26:21,130 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 26 interpolants. [2018-11-28 11:26:21,131 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=178, Invalid=472, Unknown=0, NotChecked=0, Total=650 [2018-11-28 11:26:21,131 INFO L87 Difference]: Start difference. First operand 144 states and 150 transitions. Second operand 26 states. [2018-11-28 11:26:22,133 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-28 11:26:22,134 INFO L93 Difference]: Finished difference Result 154 states and 164 transitions. [2018-11-28 11:26:22,134 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 20 states. [2018-11-28 11:26:22,134 INFO L78 Accepts]: Start accepts. Automaton has 26 states. Word has length 47 [2018-11-28 11:26:22,134 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-28 11:26:22,135 INFO L225 Difference]: With dead ends: 154 [2018-11-28 11:26:22,135 INFO L226 Difference]: Without dead ends: 150 [2018-11-28 11:26:22,135 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 98 GetRequests, 68 SyntacticMatches, 1 SemanticMatches, 29 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 52 ImplicationChecksByTransitivity, 0.6s TimeCoverageRelationStatistics Valid=278, Invalid=652, Unknown=0, NotChecked=0, Total=930 [2018-11-28 11:26:22,136 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 150 states. [2018-11-28 11:26:22,137 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 150 to 150. [2018-11-28 11:26:22,138 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 150 states. [2018-11-28 11:26:22,138 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 150 states to 150 states and 156 transitions. [2018-11-28 11:26:22,138 INFO L78 Accepts]: Start accepts. Automaton has 150 states and 156 transitions. Word has length 47 [2018-11-28 11:26:22,138 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-28 11:26:22,138 INFO L480 AbstractCegarLoop]: Abstraction has 150 states and 156 transitions. [2018-11-28 11:26:22,139 INFO L481 AbstractCegarLoop]: Interpolant automaton has 26 states. [2018-11-28 11:26:22,139 INFO L276 IsEmpty]: Start isEmpty. Operand 150 states and 156 transitions. [2018-11-28 11:26:22,139 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 54 [2018-11-28 11:26:22,139 INFO L394 BasicCegarLoop]: Found error trace [2018-11-28 11:26:22,139 INFO L402 BasicCegarLoop]: trace histogram [16, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-28 11:26:22,140 INFO L423 AbstractCegarLoop]: === Iteration 14 === [ldv_kref_initErr0REQUIRES_VIOLATION, ldv_kref_initErr1REQUIRES_VIOLATION, ldv_list_addErr1REQUIRES_VIOLATION, ldv_list_addErr0REQUIRES_VIOLATION, ldv_kobject_createErr1REQUIRES_VIOLATION, ldv_kobject_createErr0REQUIRES_VIOLATION, ldv_destroy_msgsErr5REQUIRES_VIOLATION, ldv_destroy_msgsErr0REQUIRES_VIOLATION, ldv_destroy_msgsErr4REQUIRES_VIOLATION, ldv_destroy_msgsErr2REQUIRES_VIOLATION, ldv_destroy_msgsErr3REQUIRES_VIOLATION, ldv_destroy_msgsErr1REQUIRES_VIOLATION, ldv_msg_fillErr1REQUIRES_VIOLATION, ldv_msg_fillErr3REQUIRES_VIOLATION, ldv_msg_fillErr2REQUIRES_VIOLATION, ldv_msg_fillErr4REQUIRES_VIOLATION, ldv_msg_fillErr0REQUIRES_VIOLATION, ldv_msg_fillErr5REQUIRES_VIOLATION, ldv_atomic_add_returnErr2REQUIRES_VIOLATION, ldv_atomic_add_returnErr3REQUIRES_VIOLATION, ldv_atomic_add_returnErr1REQUIRES_VIOLATION, ldv_atomic_add_returnErr0REQUIRES_VIOLATION, __ldv_list_delErr0REQUIRES_VIOLATION, __ldv_list_delErr3REQUIRES_VIOLATION, __ldv_list_delErr2REQUIRES_VIOLATION, __ldv_list_delErr1REQUIRES_VIOLATION, ldv_kobject_cleanupErr2ASSERT_VIOLATIONMEMORY_FREE, ldv_kobject_cleanupErr0REQUIRES_VIOLATION, ldv_kobject_cleanupErr4ASSERT_VIOLATIONMEMORY_FREE, ldv_kobject_cleanupErr3ASSERT_VIOLATIONMEMORY_FREE, ldv_kobject_cleanupErr5ASSERT_VIOLATIONMEMORY_FREE, ldv_kobject_cleanupErr1REQUIRES_VIOLATION, ldv_msg_freeErr3ASSERT_VIOLATIONMEMORY_FREE, ldv_msg_freeErr5ASSERT_VIOLATIONMEMORY_FREE, ldv_msg_freeErr0REQUIRES_VIOLATION, ldv_msg_freeErr2ASSERT_VIOLATIONMEMORY_FREE, ldv_msg_freeErr1REQUIRES_VIOLATION, ldv_msg_freeErr4ASSERT_VIOLATIONMEMORY_FREE, mainErr0ENSURES_VIOLATIONMEMORY_LEAK, LDV_INIT_LIST_HEADErr3REQUIRES_VIOLATION, LDV_INIT_LIST_HEADErr2REQUIRES_VIOLATION, LDV_INIT_LIST_HEADErr1REQUIRES_VIOLATION, LDV_INIT_LIST_HEADErr0REQUIRES_VIOLATION, ldv_list_delErr2REQUIRES_VIOLATION, ldv_list_delErr3REQUIRES_VIOLATION, ldv_list_delErr1REQUIRES_VIOLATION, ldv_list_delErr0REQUIRES_VIOLATION, __ldv_list_addErr0REQUIRES_VIOLATION, __ldv_list_addErr5REQUIRES_VIOLATION, __ldv_list_addErr4REQUIRES_VIOLATION, __ldv_list_addErr3REQUIRES_VIOLATION, __ldv_list_addErr2REQUIRES_VIOLATION, __ldv_list_addErr7REQUIRES_VIOLATION, __ldv_list_addErr1REQUIRES_VIOLATION, __ldv_list_addErr6REQUIRES_VIOLATION, ldv_dev_set_drvdataErr1REQUIRES_VIOLATION, ldv_dev_set_drvdataErr0REQUIRES_VIOLATION, ldv_atomic_sub_returnErr2REQUIRES_VIOLATION, ldv_atomic_sub_returnErr3REQUIRES_VIOLATION, ldv_atomic_sub_returnErr1REQUIRES_VIOLATION, ldv_atomic_sub_returnErr0REQUIRES_VIOLATION, ldv_list_add_tailErr0REQUIRES_VIOLATION, ldv_list_add_tailErr1REQUIRES_VIOLATION, ldv_dev_get_drvdataErr1REQUIRES_VIOLATION, ldv_dev_get_drvdataErr0REQUIRES_VIOLATION, ldv_msg_allocErr0REQUIRES_VIOLATION, ldv_msg_allocErr1REQUIRES_VIOLATION]=== [2018-11-28 11:26:22,140 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-28 11:26:22,140 INFO L82 PathProgramCache]: Analyzing trace with hash 969727980, now seen corresponding path program 2 times [2018-11-28 11:26:22,140 INFO L223 ckRefinementStrategy]: Switched to mode CVC4_FPBP [2018-11-28 11:26:22,140 INFO L69 tionRefinementEngine]: Using refinement strategy WolfRefinementStrategy No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_2ca7a644-5b0a-4f3d-9179-f30a2c52dfce/bin-2019/uautomizer/cvc4 Starting monitored process 15 with cvc4 --incremental --print-success --lang smt --rewrite-divk (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 15 with cvc4 --incremental --print-success --lang smt --rewrite-divk [2018-11-28 11:26:22,160 INFO L101 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2018-11-28 11:26:22,241 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) [2018-11-28 11:26:22,241 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-11-28 11:26:22,244 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-28 11:26:22,246 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 6 treesize of output 5 [2018-11-28 11:26:22,246 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-11-28 11:26:22,247 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-28 11:26:22,247 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 1 variables, input treesize:6, output treesize:5 [2018-11-28 11:26:22,378 INFO L134 CoverageAnalysis]: Checked inductivity of 136 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 136 trivial. 0 not checked. [2018-11-28 11:26:22,378 INFO L312 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2018-11-28 11:26:22,380 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-28 11:26:22,380 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [12] imperfect sequences [] total 12 [2018-11-28 11:26:22,380 INFO L459 AbstractCegarLoop]: Interpolant automaton has 13 states [2018-11-28 11:26:22,380 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 13 interpolants. [2018-11-28 11:26:22,381 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=33, Invalid=123, Unknown=0, NotChecked=0, Total=156 [2018-11-28 11:26:22,381 INFO L87 Difference]: Start difference. First operand 150 states and 156 transitions. Second operand 13 states. [2018-11-28 11:26:23,190 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-28 11:26:23,191 INFO L93 Difference]: Finished difference Result 160 states and 165 transitions. [2018-11-28 11:26:23,191 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 13 states. [2018-11-28 11:26:23,191 INFO L78 Accepts]: Start accepts. Automaton has 13 states. Word has length 53 [2018-11-28 11:26:23,191 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-28 11:26:23,192 INFO L225 Difference]: With dead ends: 160 [2018-11-28 11:26:23,192 INFO L226 Difference]: Without dead ends: 160 [2018-11-28 11:26:23,192 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 55 GetRequests, 38 SyntacticMatches, 3 SemanticMatches, 14 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 18 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=48, Invalid=192, Unknown=0, NotChecked=0, Total=240 [2018-11-28 11:26:23,192 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 160 states. [2018-11-28 11:26:23,194 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 160 to 148. [2018-11-28 11:26:23,194 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 148 states. [2018-11-28 11:26:23,195 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 148 states to 148 states and 154 transitions. [2018-11-28 11:26:23,195 INFO L78 Accepts]: Start accepts. Automaton has 148 states and 154 transitions. Word has length 53 [2018-11-28 11:26:23,195 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-28 11:26:23,195 INFO L480 AbstractCegarLoop]: Abstraction has 148 states and 154 transitions. [2018-11-28 11:26:23,195 INFO L481 AbstractCegarLoop]: Interpolant automaton has 13 states. [2018-11-28 11:26:23,195 INFO L276 IsEmpty]: Start isEmpty. Operand 148 states and 154 transitions. [2018-11-28 11:26:23,196 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 54 [2018-11-28 11:26:23,196 INFO L394 BasicCegarLoop]: Found error trace [2018-11-28 11:26:23,196 INFO L402 BasicCegarLoop]: trace histogram [16, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-28 11:26:23,196 INFO L423 AbstractCegarLoop]: === Iteration 15 === [ldv_kref_initErr0REQUIRES_VIOLATION, ldv_kref_initErr1REQUIRES_VIOLATION, ldv_list_addErr1REQUIRES_VIOLATION, ldv_list_addErr0REQUIRES_VIOLATION, ldv_kobject_createErr1REQUIRES_VIOLATION, ldv_kobject_createErr0REQUIRES_VIOLATION, ldv_destroy_msgsErr5REQUIRES_VIOLATION, ldv_destroy_msgsErr0REQUIRES_VIOLATION, ldv_destroy_msgsErr4REQUIRES_VIOLATION, ldv_destroy_msgsErr2REQUIRES_VIOLATION, ldv_destroy_msgsErr3REQUIRES_VIOLATION, ldv_destroy_msgsErr1REQUIRES_VIOLATION, ldv_msg_fillErr1REQUIRES_VIOLATION, ldv_msg_fillErr3REQUIRES_VIOLATION, ldv_msg_fillErr2REQUIRES_VIOLATION, ldv_msg_fillErr4REQUIRES_VIOLATION, ldv_msg_fillErr0REQUIRES_VIOLATION, ldv_msg_fillErr5REQUIRES_VIOLATION, ldv_atomic_add_returnErr2REQUIRES_VIOLATION, ldv_atomic_add_returnErr3REQUIRES_VIOLATION, ldv_atomic_add_returnErr1REQUIRES_VIOLATION, ldv_atomic_add_returnErr0REQUIRES_VIOLATION, __ldv_list_delErr0REQUIRES_VIOLATION, __ldv_list_delErr3REQUIRES_VIOLATION, __ldv_list_delErr2REQUIRES_VIOLATION, __ldv_list_delErr1REQUIRES_VIOLATION, ldv_kobject_cleanupErr2ASSERT_VIOLATIONMEMORY_FREE, ldv_kobject_cleanupErr0REQUIRES_VIOLATION, ldv_kobject_cleanupErr4ASSERT_VIOLATIONMEMORY_FREE, ldv_kobject_cleanupErr3ASSERT_VIOLATIONMEMORY_FREE, ldv_kobject_cleanupErr5ASSERT_VIOLATIONMEMORY_FREE, ldv_kobject_cleanupErr1REQUIRES_VIOLATION, ldv_msg_freeErr3ASSERT_VIOLATIONMEMORY_FREE, ldv_msg_freeErr5ASSERT_VIOLATIONMEMORY_FREE, ldv_msg_freeErr0REQUIRES_VIOLATION, ldv_msg_freeErr2ASSERT_VIOLATIONMEMORY_FREE, ldv_msg_freeErr1REQUIRES_VIOLATION, ldv_msg_freeErr4ASSERT_VIOLATIONMEMORY_FREE, mainErr0ENSURES_VIOLATIONMEMORY_LEAK, LDV_INIT_LIST_HEADErr3REQUIRES_VIOLATION, LDV_INIT_LIST_HEADErr2REQUIRES_VIOLATION, LDV_INIT_LIST_HEADErr1REQUIRES_VIOLATION, LDV_INIT_LIST_HEADErr0REQUIRES_VIOLATION, ldv_list_delErr2REQUIRES_VIOLATION, ldv_list_delErr3REQUIRES_VIOLATION, ldv_list_delErr1REQUIRES_VIOLATION, ldv_list_delErr0REQUIRES_VIOLATION, __ldv_list_addErr0REQUIRES_VIOLATION, __ldv_list_addErr5REQUIRES_VIOLATION, __ldv_list_addErr4REQUIRES_VIOLATION, __ldv_list_addErr3REQUIRES_VIOLATION, __ldv_list_addErr2REQUIRES_VIOLATION, __ldv_list_addErr7REQUIRES_VIOLATION, __ldv_list_addErr1REQUIRES_VIOLATION, __ldv_list_addErr6REQUIRES_VIOLATION, ldv_dev_set_drvdataErr1REQUIRES_VIOLATION, ldv_dev_set_drvdataErr0REQUIRES_VIOLATION, ldv_atomic_sub_returnErr2REQUIRES_VIOLATION, ldv_atomic_sub_returnErr3REQUIRES_VIOLATION, ldv_atomic_sub_returnErr1REQUIRES_VIOLATION, ldv_atomic_sub_returnErr0REQUIRES_VIOLATION, ldv_list_add_tailErr0REQUIRES_VIOLATION, ldv_list_add_tailErr1REQUIRES_VIOLATION, ldv_dev_get_drvdataErr1REQUIRES_VIOLATION, ldv_dev_get_drvdataErr0REQUIRES_VIOLATION, ldv_msg_allocErr0REQUIRES_VIOLATION, ldv_msg_allocErr1REQUIRES_VIOLATION]=== [2018-11-28 11:26:23,196 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-28 11:26:23,197 INFO L82 PathProgramCache]: Analyzing trace with hash 969727981, now seen corresponding path program 1 times [2018-11-28 11:26:23,197 INFO L223 ckRefinementStrategy]: Switched to mode CVC4_FPBP [2018-11-28 11:26:23,197 INFO L69 tionRefinementEngine]: Using refinement strategy WolfRefinementStrategy No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_2ca7a644-5b0a-4f3d-9179-f30a2c52dfce/bin-2019/uautomizer/cvc4 Starting monitored process 16 with cvc4 --incremental --print-success --lang smt --rewrite-divk (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 16 with cvc4 --incremental --print-success --lang smt --rewrite-divk [2018-11-28 11:26:23,216 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-28 11:26:23,384 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-28 11:26:23,387 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-28 11:26:23,393 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 6 treesize of output 5 [2018-11-28 11:26:23,393 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-11-28 11:26:23,398 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-28 11:26:23,398 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 1 variables, input treesize:10, output treesize:9 [2018-11-28 11:26:23,564 INFO L134 CoverageAnalysis]: Checked inductivity of 136 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 136 trivial. 0 not checked. [2018-11-28 11:26:23,564 INFO L312 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2018-11-28 11:26:23,566 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-28 11:26:23,566 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [12] imperfect sequences [] total 12 [2018-11-28 11:26:23,567 INFO L459 AbstractCegarLoop]: Interpolant automaton has 13 states [2018-11-28 11:26:23,567 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 13 interpolants. [2018-11-28 11:26:23,567 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=31, Invalid=125, Unknown=0, NotChecked=0, Total=156 [2018-11-28 11:26:23,567 INFO L87 Difference]: Start difference. First operand 148 states and 154 transitions. Second operand 13 states. [2018-11-28 11:26:24,288 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-28 11:26:24,288 INFO L93 Difference]: Finished difference Result 146 states and 152 transitions. [2018-11-28 11:26:24,289 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 13 states. [2018-11-28 11:26:24,289 INFO L78 Accepts]: Start accepts. Automaton has 13 states. Word has length 53 [2018-11-28 11:26:24,289 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-28 11:26:24,289 INFO L225 Difference]: With dead ends: 146 [2018-11-28 11:26:24,289 INFO L226 Difference]: Without dead ends: 146 [2018-11-28 11:26:24,290 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 56 GetRequests, 38 SyntacticMatches, 3 SemanticMatches, 15 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 25 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=50, Invalid=222, Unknown=0, NotChecked=0, Total=272 [2018-11-28 11:26:24,290 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 146 states. [2018-11-28 11:26:24,292 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 146 to 146. [2018-11-28 11:26:24,292 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 146 states. [2018-11-28 11:26:24,293 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 146 states to 146 states and 152 transitions. [2018-11-28 11:26:24,293 INFO L78 Accepts]: Start accepts. Automaton has 146 states and 152 transitions. Word has length 53 [2018-11-28 11:26:24,293 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-28 11:26:24,293 INFO L480 AbstractCegarLoop]: Abstraction has 146 states and 152 transitions. [2018-11-28 11:26:24,294 INFO L481 AbstractCegarLoop]: Interpolant automaton has 13 states. [2018-11-28 11:26:24,294 INFO L276 IsEmpty]: Start isEmpty. Operand 146 states and 152 transitions. [2018-11-28 11:26:24,294 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 57 [2018-11-28 11:26:24,294 INFO L394 BasicCegarLoop]: Found error trace [2018-11-28 11:26:24,294 INFO L402 BasicCegarLoop]: trace histogram [16, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-28 11:26:24,295 INFO L423 AbstractCegarLoop]: === Iteration 16 === [ldv_kref_initErr0REQUIRES_VIOLATION, ldv_kref_initErr1REQUIRES_VIOLATION, ldv_list_addErr1REQUIRES_VIOLATION, ldv_list_addErr0REQUIRES_VIOLATION, ldv_kobject_createErr1REQUIRES_VIOLATION, ldv_kobject_createErr0REQUIRES_VIOLATION, ldv_destroy_msgsErr5REQUIRES_VIOLATION, ldv_destroy_msgsErr0REQUIRES_VIOLATION, ldv_destroy_msgsErr4REQUIRES_VIOLATION, ldv_destroy_msgsErr2REQUIRES_VIOLATION, ldv_destroy_msgsErr3REQUIRES_VIOLATION, ldv_destroy_msgsErr1REQUIRES_VIOLATION, ldv_msg_fillErr1REQUIRES_VIOLATION, ldv_msg_fillErr3REQUIRES_VIOLATION, ldv_msg_fillErr2REQUIRES_VIOLATION, ldv_msg_fillErr4REQUIRES_VIOLATION, ldv_msg_fillErr0REQUIRES_VIOLATION, ldv_msg_fillErr5REQUIRES_VIOLATION, ldv_atomic_add_returnErr2REQUIRES_VIOLATION, ldv_atomic_add_returnErr3REQUIRES_VIOLATION, ldv_atomic_add_returnErr1REQUIRES_VIOLATION, ldv_atomic_add_returnErr0REQUIRES_VIOLATION, __ldv_list_delErr0REQUIRES_VIOLATION, __ldv_list_delErr3REQUIRES_VIOLATION, __ldv_list_delErr2REQUIRES_VIOLATION, __ldv_list_delErr1REQUIRES_VIOLATION, ldv_kobject_cleanupErr2ASSERT_VIOLATIONMEMORY_FREE, ldv_kobject_cleanupErr0REQUIRES_VIOLATION, ldv_kobject_cleanupErr4ASSERT_VIOLATIONMEMORY_FREE, ldv_kobject_cleanupErr3ASSERT_VIOLATIONMEMORY_FREE, ldv_kobject_cleanupErr5ASSERT_VIOLATIONMEMORY_FREE, ldv_kobject_cleanupErr1REQUIRES_VIOLATION, ldv_msg_freeErr3ASSERT_VIOLATIONMEMORY_FREE, ldv_msg_freeErr5ASSERT_VIOLATIONMEMORY_FREE, ldv_msg_freeErr0REQUIRES_VIOLATION, ldv_msg_freeErr2ASSERT_VIOLATIONMEMORY_FREE, ldv_msg_freeErr1REQUIRES_VIOLATION, ldv_msg_freeErr4ASSERT_VIOLATIONMEMORY_FREE, mainErr0ENSURES_VIOLATIONMEMORY_LEAK, LDV_INIT_LIST_HEADErr3REQUIRES_VIOLATION, LDV_INIT_LIST_HEADErr2REQUIRES_VIOLATION, LDV_INIT_LIST_HEADErr1REQUIRES_VIOLATION, LDV_INIT_LIST_HEADErr0REQUIRES_VIOLATION, ldv_list_delErr2REQUIRES_VIOLATION, ldv_list_delErr3REQUIRES_VIOLATION, ldv_list_delErr1REQUIRES_VIOLATION, ldv_list_delErr0REQUIRES_VIOLATION, __ldv_list_addErr0REQUIRES_VIOLATION, __ldv_list_addErr5REQUIRES_VIOLATION, __ldv_list_addErr4REQUIRES_VIOLATION, __ldv_list_addErr3REQUIRES_VIOLATION, __ldv_list_addErr2REQUIRES_VIOLATION, __ldv_list_addErr7REQUIRES_VIOLATION, __ldv_list_addErr1REQUIRES_VIOLATION, __ldv_list_addErr6REQUIRES_VIOLATION, ldv_dev_set_drvdataErr1REQUIRES_VIOLATION, ldv_dev_set_drvdataErr0REQUIRES_VIOLATION, ldv_atomic_sub_returnErr2REQUIRES_VIOLATION, ldv_atomic_sub_returnErr3REQUIRES_VIOLATION, ldv_atomic_sub_returnErr1REQUIRES_VIOLATION, ldv_atomic_sub_returnErr0REQUIRES_VIOLATION, ldv_list_add_tailErr0REQUIRES_VIOLATION, ldv_list_add_tailErr1REQUIRES_VIOLATION, ldv_dev_get_drvdataErr1REQUIRES_VIOLATION, ldv_dev_get_drvdataErr0REQUIRES_VIOLATION, ldv_msg_allocErr0REQUIRES_VIOLATION, ldv_msg_allocErr1REQUIRES_VIOLATION]=== [2018-11-28 11:26:24,295 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-28 11:26:24,295 INFO L82 PathProgramCache]: Analyzing trace with hash -1108493563, now seen corresponding path program 1 times [2018-11-28 11:26:24,295 INFO L223 ckRefinementStrategy]: Switched to mode CVC4_FPBP [2018-11-28 11:26:24,295 INFO L69 tionRefinementEngine]: Using refinement strategy WolfRefinementStrategy No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_2ca7a644-5b0a-4f3d-9179-f30a2c52dfce/bin-2019/uautomizer/cvc4 Starting monitored process 17 with cvc4 --incremental --print-success --lang smt --rewrite-divk (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 17 with cvc4 --incremental --print-success --lang smt --rewrite-divk [2018-11-28 11:26:24,325 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-28 11:26:24,370 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-28 11:26:24,373 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-28 11:26:24,397 INFO L134 CoverageAnalysis]: Checked inductivity of 136 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 136 trivial. 0 not checked. [2018-11-28 11:26:24,397 INFO L312 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2018-11-28 11:26:24,398 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-28 11:26:24,399 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [7] imperfect sequences [] total 7 [2018-11-28 11:26:24,399 INFO L459 AbstractCegarLoop]: Interpolant automaton has 7 states [2018-11-28 11:26:24,399 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2018-11-28 11:26:24,399 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=11, Invalid=31, Unknown=0, NotChecked=0, Total=42 [2018-11-28 11:26:24,399 INFO L87 Difference]: Start difference. First operand 146 states and 152 transitions. Second operand 7 states. [2018-11-28 11:26:24,428 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-28 11:26:24,429 INFO L93 Difference]: Finished difference Result 148 states and 153 transitions. [2018-11-28 11:26:24,429 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2018-11-28 11:26:24,429 INFO L78 Accepts]: Start accepts. Automaton has 7 states. Word has length 56 [2018-11-28 11:26:24,429 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-28 11:26:24,430 INFO L225 Difference]: With dead ends: 148 [2018-11-28 11:26:24,430 INFO L226 Difference]: Without dead ends: 146 [2018-11-28 11:26:24,430 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 56 GetRequests, 50 SyntacticMatches, 0 SemanticMatches, 6 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=15, Invalid=41, Unknown=0, NotChecked=0, Total=56 [2018-11-28 11:26:24,430 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 146 states. [2018-11-28 11:26:24,432 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 146 to 146. [2018-11-28 11:26:24,432 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 146 states. [2018-11-28 11:26:24,433 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 146 states to 146 states and 151 transitions. [2018-11-28 11:26:24,433 INFO L78 Accepts]: Start accepts. Automaton has 146 states and 151 transitions. Word has length 56 [2018-11-28 11:26:24,433 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-28 11:26:24,433 INFO L480 AbstractCegarLoop]: Abstraction has 146 states and 151 transitions. [2018-11-28 11:26:24,433 INFO L481 AbstractCegarLoop]: Interpolant automaton has 7 states. [2018-11-28 11:26:24,433 INFO L276 IsEmpty]: Start isEmpty. Operand 146 states and 151 transitions. [2018-11-28 11:26:24,434 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 62 [2018-11-28 11:26:24,434 INFO L394 BasicCegarLoop]: Found error trace [2018-11-28 11:26:24,434 INFO L402 BasicCegarLoop]: trace histogram [16, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-28 11:26:24,434 INFO L423 AbstractCegarLoop]: === Iteration 17 === [ldv_kref_initErr0REQUIRES_VIOLATION, ldv_kref_initErr1REQUIRES_VIOLATION, ldv_list_addErr1REQUIRES_VIOLATION, ldv_list_addErr0REQUIRES_VIOLATION, ldv_kobject_createErr1REQUIRES_VIOLATION, ldv_kobject_createErr0REQUIRES_VIOLATION, ldv_destroy_msgsErr5REQUIRES_VIOLATION, ldv_destroy_msgsErr0REQUIRES_VIOLATION, ldv_destroy_msgsErr4REQUIRES_VIOLATION, ldv_destroy_msgsErr2REQUIRES_VIOLATION, ldv_destroy_msgsErr3REQUIRES_VIOLATION, ldv_destroy_msgsErr1REQUIRES_VIOLATION, ldv_msg_fillErr1REQUIRES_VIOLATION, ldv_msg_fillErr3REQUIRES_VIOLATION, ldv_msg_fillErr2REQUIRES_VIOLATION, ldv_msg_fillErr4REQUIRES_VIOLATION, ldv_msg_fillErr0REQUIRES_VIOLATION, ldv_msg_fillErr5REQUIRES_VIOLATION, ldv_atomic_add_returnErr2REQUIRES_VIOLATION, ldv_atomic_add_returnErr3REQUIRES_VIOLATION, ldv_atomic_add_returnErr1REQUIRES_VIOLATION, ldv_atomic_add_returnErr0REQUIRES_VIOLATION, __ldv_list_delErr0REQUIRES_VIOLATION, __ldv_list_delErr3REQUIRES_VIOLATION, __ldv_list_delErr2REQUIRES_VIOLATION, __ldv_list_delErr1REQUIRES_VIOLATION, ldv_kobject_cleanupErr2ASSERT_VIOLATIONMEMORY_FREE, ldv_kobject_cleanupErr0REQUIRES_VIOLATION, ldv_kobject_cleanupErr4ASSERT_VIOLATIONMEMORY_FREE, ldv_kobject_cleanupErr3ASSERT_VIOLATIONMEMORY_FREE, ldv_kobject_cleanupErr5ASSERT_VIOLATIONMEMORY_FREE, ldv_kobject_cleanupErr1REQUIRES_VIOLATION, ldv_msg_freeErr3ASSERT_VIOLATIONMEMORY_FREE, ldv_msg_freeErr5ASSERT_VIOLATIONMEMORY_FREE, ldv_msg_freeErr0REQUIRES_VIOLATION, ldv_msg_freeErr2ASSERT_VIOLATIONMEMORY_FREE, ldv_msg_freeErr1REQUIRES_VIOLATION, ldv_msg_freeErr4ASSERT_VIOLATIONMEMORY_FREE, mainErr0ENSURES_VIOLATIONMEMORY_LEAK, LDV_INIT_LIST_HEADErr3REQUIRES_VIOLATION, LDV_INIT_LIST_HEADErr2REQUIRES_VIOLATION, LDV_INIT_LIST_HEADErr1REQUIRES_VIOLATION, LDV_INIT_LIST_HEADErr0REQUIRES_VIOLATION, ldv_list_delErr2REQUIRES_VIOLATION, ldv_list_delErr3REQUIRES_VIOLATION, ldv_list_delErr1REQUIRES_VIOLATION, ldv_list_delErr0REQUIRES_VIOLATION, __ldv_list_addErr0REQUIRES_VIOLATION, __ldv_list_addErr5REQUIRES_VIOLATION, __ldv_list_addErr4REQUIRES_VIOLATION, __ldv_list_addErr3REQUIRES_VIOLATION, __ldv_list_addErr2REQUIRES_VIOLATION, __ldv_list_addErr7REQUIRES_VIOLATION, __ldv_list_addErr1REQUIRES_VIOLATION, __ldv_list_addErr6REQUIRES_VIOLATION, ldv_dev_set_drvdataErr1REQUIRES_VIOLATION, ldv_dev_set_drvdataErr0REQUIRES_VIOLATION, ldv_atomic_sub_returnErr2REQUIRES_VIOLATION, ldv_atomic_sub_returnErr3REQUIRES_VIOLATION, ldv_atomic_sub_returnErr1REQUIRES_VIOLATION, ldv_atomic_sub_returnErr0REQUIRES_VIOLATION, ldv_list_add_tailErr0REQUIRES_VIOLATION, ldv_list_add_tailErr1REQUIRES_VIOLATION, ldv_dev_get_drvdataErr1REQUIRES_VIOLATION, ldv_dev_get_drvdataErr0REQUIRES_VIOLATION, ldv_msg_allocErr0REQUIRES_VIOLATION, ldv_msg_allocErr1REQUIRES_VIOLATION]=== [2018-11-28 11:26:24,435 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-28 11:26:24,435 INFO L82 PathProgramCache]: Analyzing trace with hash 128711114, now seen corresponding path program 1 times [2018-11-28 11:26:24,435 INFO L223 ckRefinementStrategy]: Switched to mode CVC4_FPBP [2018-11-28 11:26:24,435 INFO L69 tionRefinementEngine]: Using refinement strategy WolfRefinementStrategy No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_2ca7a644-5b0a-4f3d-9179-f30a2c52dfce/bin-2019/uautomizer/cvc4 Starting monitored process 18 with cvc4 --incremental --print-success --lang smt --rewrite-divk (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 18 with cvc4 --incremental --print-success --lang smt --rewrite-divk [2018-11-28 11:26:24,452 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-28 11:26:24,505 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-28 11:26:24,508 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-28 11:26:24,547 INFO L134 CoverageAnalysis]: Checked inductivity of 136 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 136 trivial. 0 not checked. [2018-11-28 11:26:24,547 INFO L312 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2018-11-28 11:26:24,548 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-28 11:26:24,549 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [9] imperfect sequences [] total 9 [2018-11-28 11:26:24,549 INFO L459 AbstractCegarLoop]: Interpolant automaton has 9 states [2018-11-28 11:26:24,549 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 9 interpolants. [2018-11-28 11:26:24,549 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=15, Invalid=57, Unknown=0, NotChecked=0, Total=72 [2018-11-28 11:26:24,549 INFO L87 Difference]: Start difference. First operand 146 states and 151 transitions. Second operand 9 states. [2018-11-28 11:26:24,608 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-28 11:26:24,608 INFO L93 Difference]: Finished difference Result 150 states and 154 transitions. [2018-11-28 11:26:24,609 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2018-11-28 11:26:24,609 INFO L78 Accepts]: Start accepts. Automaton has 9 states. Word has length 61 [2018-11-28 11:26:24,609 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-28 11:26:24,610 INFO L225 Difference]: With dead ends: 150 [2018-11-28 11:26:24,610 INFO L226 Difference]: Without dead ends: 146 [2018-11-28 11:26:24,610 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 62 GetRequests, 53 SyntacticMatches, 0 SemanticMatches, 9 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=23, Invalid=87, Unknown=0, NotChecked=0, Total=110 [2018-11-28 11:26:24,610 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 146 states. [2018-11-28 11:26:24,612 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 146 to 146. [2018-11-28 11:26:24,612 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 146 states. [2018-11-28 11:26:24,613 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 146 states to 146 states and 150 transitions. [2018-11-28 11:26:24,613 INFO L78 Accepts]: Start accepts. Automaton has 146 states and 150 transitions. Word has length 61 [2018-11-28 11:26:24,613 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-28 11:26:24,613 INFO L480 AbstractCegarLoop]: Abstraction has 146 states and 150 transitions. [2018-11-28 11:26:24,613 INFO L481 AbstractCegarLoop]: Interpolant automaton has 9 states. [2018-11-28 11:26:24,614 INFO L276 IsEmpty]: Start isEmpty. Operand 146 states and 150 transitions. [2018-11-28 11:26:24,614 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 73 [2018-11-28 11:26:24,614 INFO L394 BasicCegarLoop]: Found error trace [2018-11-28 11:26:24,614 INFO L402 BasicCegarLoop]: trace histogram [16, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-28 11:26:24,615 INFO L423 AbstractCegarLoop]: === Iteration 18 === [ldv_kref_initErr0REQUIRES_VIOLATION, ldv_kref_initErr1REQUIRES_VIOLATION, ldv_list_addErr1REQUIRES_VIOLATION, ldv_list_addErr0REQUIRES_VIOLATION, ldv_kobject_createErr1REQUIRES_VIOLATION, ldv_kobject_createErr0REQUIRES_VIOLATION, ldv_destroy_msgsErr5REQUIRES_VIOLATION, ldv_destroy_msgsErr0REQUIRES_VIOLATION, ldv_destroy_msgsErr4REQUIRES_VIOLATION, ldv_destroy_msgsErr2REQUIRES_VIOLATION, ldv_destroy_msgsErr3REQUIRES_VIOLATION, ldv_destroy_msgsErr1REQUIRES_VIOLATION, ldv_msg_fillErr1REQUIRES_VIOLATION, ldv_msg_fillErr3REQUIRES_VIOLATION, ldv_msg_fillErr2REQUIRES_VIOLATION, ldv_msg_fillErr4REQUIRES_VIOLATION, ldv_msg_fillErr0REQUIRES_VIOLATION, ldv_msg_fillErr5REQUIRES_VIOLATION, ldv_atomic_add_returnErr2REQUIRES_VIOLATION, ldv_atomic_add_returnErr3REQUIRES_VIOLATION, ldv_atomic_add_returnErr1REQUIRES_VIOLATION, ldv_atomic_add_returnErr0REQUIRES_VIOLATION, __ldv_list_delErr0REQUIRES_VIOLATION, __ldv_list_delErr3REQUIRES_VIOLATION, __ldv_list_delErr2REQUIRES_VIOLATION, __ldv_list_delErr1REQUIRES_VIOLATION, ldv_kobject_cleanupErr2ASSERT_VIOLATIONMEMORY_FREE, ldv_kobject_cleanupErr0REQUIRES_VIOLATION, ldv_kobject_cleanupErr4ASSERT_VIOLATIONMEMORY_FREE, ldv_kobject_cleanupErr3ASSERT_VIOLATIONMEMORY_FREE, ldv_kobject_cleanupErr5ASSERT_VIOLATIONMEMORY_FREE, ldv_kobject_cleanupErr1REQUIRES_VIOLATION, ldv_msg_freeErr3ASSERT_VIOLATIONMEMORY_FREE, ldv_msg_freeErr5ASSERT_VIOLATIONMEMORY_FREE, ldv_msg_freeErr0REQUIRES_VIOLATION, ldv_msg_freeErr2ASSERT_VIOLATIONMEMORY_FREE, ldv_msg_freeErr1REQUIRES_VIOLATION, ldv_msg_freeErr4ASSERT_VIOLATIONMEMORY_FREE, mainErr0ENSURES_VIOLATIONMEMORY_LEAK, LDV_INIT_LIST_HEADErr3REQUIRES_VIOLATION, LDV_INIT_LIST_HEADErr2REQUIRES_VIOLATION, LDV_INIT_LIST_HEADErr1REQUIRES_VIOLATION, LDV_INIT_LIST_HEADErr0REQUIRES_VIOLATION, ldv_list_delErr2REQUIRES_VIOLATION, ldv_list_delErr3REQUIRES_VIOLATION, ldv_list_delErr1REQUIRES_VIOLATION, ldv_list_delErr0REQUIRES_VIOLATION, __ldv_list_addErr0REQUIRES_VIOLATION, __ldv_list_addErr5REQUIRES_VIOLATION, __ldv_list_addErr4REQUIRES_VIOLATION, __ldv_list_addErr3REQUIRES_VIOLATION, __ldv_list_addErr2REQUIRES_VIOLATION, __ldv_list_addErr7REQUIRES_VIOLATION, __ldv_list_addErr1REQUIRES_VIOLATION, __ldv_list_addErr6REQUIRES_VIOLATION, ldv_dev_set_drvdataErr1REQUIRES_VIOLATION, ldv_dev_set_drvdataErr0REQUIRES_VIOLATION, ldv_atomic_sub_returnErr2REQUIRES_VIOLATION, ldv_atomic_sub_returnErr3REQUIRES_VIOLATION, ldv_atomic_sub_returnErr1REQUIRES_VIOLATION, ldv_atomic_sub_returnErr0REQUIRES_VIOLATION, ldv_list_add_tailErr0REQUIRES_VIOLATION, ldv_list_add_tailErr1REQUIRES_VIOLATION, ldv_dev_get_drvdataErr1REQUIRES_VIOLATION, ldv_dev_get_drvdataErr0REQUIRES_VIOLATION, ldv_msg_allocErr0REQUIRES_VIOLATION, ldv_msg_allocErr1REQUIRES_VIOLATION]=== [2018-11-28 11:26:24,615 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-28 11:26:24,615 INFO L82 PathProgramCache]: Analyzing trace with hash -489606087, now seen corresponding path program 1 times [2018-11-28 11:26:24,615 INFO L223 ckRefinementStrategy]: Switched to mode CVC4_FPBP [2018-11-28 11:26:24,615 INFO L69 tionRefinementEngine]: Using refinement strategy WolfRefinementStrategy No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_2ca7a644-5b0a-4f3d-9179-f30a2c52dfce/bin-2019/uautomizer/cvc4 Starting monitored process 19 with cvc4 --incremental --print-success --lang smt --rewrite-divk (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 19 with cvc4 --incremental --print-success --lang smt --rewrite-divk [2018-11-28 11:26:24,629 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-28 11:26:24,790 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-28 11:26:24,795 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-28 11:26:24,797 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 6 treesize of output 5 [2018-11-28 11:26:24,797 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-11-28 11:26:24,799 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-28 11:26:24,799 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 1 variables, input treesize:6, output treesize:5 [2018-11-28 11:26:25,007 INFO L134 CoverageAnalysis]: Checked inductivity of 136 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 136 trivial. 0 not checked. [2018-11-28 11:26:25,007 INFO L312 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2018-11-28 11:26:25,010 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-28 11:26:25,010 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [17] imperfect sequences [] total 17 [2018-11-28 11:26:25,010 INFO L459 AbstractCegarLoop]: Interpolant automaton has 18 states [2018-11-28 11:26:25,011 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 18 interpolants. [2018-11-28 11:26:25,011 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=48, Invalid=258, Unknown=0, NotChecked=0, Total=306 [2018-11-28 11:26:25,011 INFO L87 Difference]: Start difference. First operand 146 states and 150 transitions. Second operand 18 states. [2018-11-28 11:26:26,284 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-28 11:26:26,285 INFO L93 Difference]: Finished difference Result 156 states and 159 transitions. [2018-11-28 11:26:26,285 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 18 states. [2018-11-28 11:26:26,285 INFO L78 Accepts]: Start accepts. Automaton has 18 states. Word has length 72 [2018-11-28 11:26:26,285 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-28 11:26:26,286 INFO L225 Difference]: With dead ends: 156 [2018-11-28 11:26:26,286 INFO L226 Difference]: Without dead ends: 156 [2018-11-28 11:26:26,286 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 75 GetRequests, 52 SyntacticMatches, 3 SemanticMatches, 20 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 23 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=68, Invalid=394, Unknown=0, NotChecked=0, Total=462 [2018-11-28 11:26:26,286 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 156 states. [2018-11-28 11:26:26,288 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 156 to 144. [2018-11-28 11:26:26,288 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 144 states. [2018-11-28 11:26:26,289 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 144 states to 144 states and 148 transitions. [2018-11-28 11:26:26,289 INFO L78 Accepts]: Start accepts. Automaton has 144 states and 148 transitions. Word has length 72 [2018-11-28 11:26:26,289 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-28 11:26:26,289 INFO L480 AbstractCegarLoop]: Abstraction has 144 states and 148 transitions. [2018-11-28 11:26:26,289 INFO L481 AbstractCegarLoop]: Interpolant automaton has 18 states. [2018-11-28 11:26:26,289 INFO L276 IsEmpty]: Start isEmpty. Operand 144 states and 148 transitions. [2018-11-28 11:26:26,290 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 73 [2018-11-28 11:26:26,290 INFO L394 BasicCegarLoop]: Found error trace [2018-11-28 11:26:26,290 INFO L402 BasicCegarLoop]: trace histogram [16, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-28 11:26:26,290 INFO L423 AbstractCegarLoop]: === Iteration 19 === [ldv_kref_initErr0REQUIRES_VIOLATION, ldv_kref_initErr1REQUIRES_VIOLATION, ldv_list_addErr1REQUIRES_VIOLATION, ldv_list_addErr0REQUIRES_VIOLATION, ldv_kobject_createErr1REQUIRES_VIOLATION, ldv_kobject_createErr0REQUIRES_VIOLATION, ldv_destroy_msgsErr5REQUIRES_VIOLATION, ldv_destroy_msgsErr0REQUIRES_VIOLATION, ldv_destroy_msgsErr4REQUIRES_VIOLATION, ldv_destroy_msgsErr2REQUIRES_VIOLATION, ldv_destroy_msgsErr3REQUIRES_VIOLATION, ldv_destroy_msgsErr1REQUIRES_VIOLATION, ldv_msg_fillErr1REQUIRES_VIOLATION, ldv_msg_fillErr3REQUIRES_VIOLATION, ldv_msg_fillErr2REQUIRES_VIOLATION, ldv_msg_fillErr4REQUIRES_VIOLATION, ldv_msg_fillErr0REQUIRES_VIOLATION, ldv_msg_fillErr5REQUIRES_VIOLATION, ldv_atomic_add_returnErr2REQUIRES_VIOLATION, ldv_atomic_add_returnErr3REQUIRES_VIOLATION, ldv_atomic_add_returnErr1REQUIRES_VIOLATION, ldv_atomic_add_returnErr0REQUIRES_VIOLATION, __ldv_list_delErr0REQUIRES_VIOLATION, __ldv_list_delErr3REQUIRES_VIOLATION, __ldv_list_delErr2REQUIRES_VIOLATION, __ldv_list_delErr1REQUIRES_VIOLATION, ldv_kobject_cleanupErr2ASSERT_VIOLATIONMEMORY_FREE, ldv_kobject_cleanupErr0REQUIRES_VIOLATION, ldv_kobject_cleanupErr4ASSERT_VIOLATIONMEMORY_FREE, ldv_kobject_cleanupErr3ASSERT_VIOLATIONMEMORY_FREE, ldv_kobject_cleanupErr5ASSERT_VIOLATIONMEMORY_FREE, ldv_kobject_cleanupErr1REQUIRES_VIOLATION, ldv_msg_freeErr3ASSERT_VIOLATIONMEMORY_FREE, ldv_msg_freeErr5ASSERT_VIOLATIONMEMORY_FREE, ldv_msg_freeErr0REQUIRES_VIOLATION, ldv_msg_freeErr2ASSERT_VIOLATIONMEMORY_FREE, ldv_msg_freeErr1REQUIRES_VIOLATION, ldv_msg_freeErr4ASSERT_VIOLATIONMEMORY_FREE, mainErr0ENSURES_VIOLATIONMEMORY_LEAK, LDV_INIT_LIST_HEADErr3REQUIRES_VIOLATION, LDV_INIT_LIST_HEADErr2REQUIRES_VIOLATION, LDV_INIT_LIST_HEADErr1REQUIRES_VIOLATION, LDV_INIT_LIST_HEADErr0REQUIRES_VIOLATION, ldv_list_delErr2REQUIRES_VIOLATION, ldv_list_delErr3REQUIRES_VIOLATION, ldv_list_delErr1REQUIRES_VIOLATION, ldv_list_delErr0REQUIRES_VIOLATION, __ldv_list_addErr0REQUIRES_VIOLATION, __ldv_list_addErr5REQUIRES_VIOLATION, __ldv_list_addErr4REQUIRES_VIOLATION, __ldv_list_addErr3REQUIRES_VIOLATION, __ldv_list_addErr2REQUIRES_VIOLATION, __ldv_list_addErr7REQUIRES_VIOLATION, __ldv_list_addErr1REQUIRES_VIOLATION, __ldv_list_addErr6REQUIRES_VIOLATION, ldv_dev_set_drvdataErr1REQUIRES_VIOLATION, ldv_dev_set_drvdataErr0REQUIRES_VIOLATION, ldv_atomic_sub_returnErr2REQUIRES_VIOLATION, ldv_atomic_sub_returnErr3REQUIRES_VIOLATION, ldv_atomic_sub_returnErr1REQUIRES_VIOLATION, ldv_atomic_sub_returnErr0REQUIRES_VIOLATION, ldv_list_add_tailErr0REQUIRES_VIOLATION, ldv_list_add_tailErr1REQUIRES_VIOLATION, ldv_dev_get_drvdataErr1REQUIRES_VIOLATION, ldv_dev_get_drvdataErr0REQUIRES_VIOLATION, ldv_msg_allocErr0REQUIRES_VIOLATION, ldv_msg_allocErr1REQUIRES_VIOLATION]=== [2018-11-28 11:26:26,290 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-28 11:26:26,291 INFO L82 PathProgramCache]: Analyzing trace with hash -489606086, now seen corresponding path program 1 times [2018-11-28 11:26:26,291 INFO L223 ckRefinementStrategy]: Switched to mode CVC4_FPBP [2018-11-28 11:26:26,291 INFO L69 tionRefinementEngine]: Using refinement strategy WolfRefinementStrategy No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_2ca7a644-5b0a-4f3d-9179-f30a2c52dfce/bin-2019/uautomizer/cvc4 Starting monitored process 20 with cvc4 --incremental --print-success --lang smt --rewrite-divk (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 20 with cvc4 --incremental --print-success --lang smt --rewrite-divk [2018-11-28 11:26:26,315 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-28 11:26:26,541 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-28 11:26:26,559 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-28 11:26:26,576 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 6 treesize of output 5 [2018-11-28 11:26:26,576 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-11-28 11:26:26,586 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-28 11:26:26,586 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 1 variables, input treesize:10, output treesize:9 [2018-11-28 11:26:26,899 INFO L134 CoverageAnalysis]: Checked inductivity of 136 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 136 trivial. 0 not checked. [2018-11-28 11:26:26,899 INFO L312 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2018-11-28 11:26:26,903 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-28 11:26:26,903 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [17] imperfect sequences [] total 17 [2018-11-28 11:26:26,903 INFO L459 AbstractCegarLoop]: Interpolant automaton has 18 states [2018-11-28 11:26:26,903 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 18 interpolants. [2018-11-28 11:26:26,903 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=46, Invalid=260, Unknown=0, NotChecked=0, Total=306 [2018-11-28 11:26:26,903 INFO L87 Difference]: Start difference. First operand 144 states and 148 transitions. Second operand 18 states. [2018-11-28 11:26:28,472 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-28 11:26:28,472 INFO L93 Difference]: Finished difference Result 142 states and 146 transitions. [2018-11-28 11:26:28,472 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 18 states. [2018-11-28 11:26:28,472 INFO L78 Accepts]: Start accepts. Automaton has 18 states. Word has length 72 [2018-11-28 11:26:28,473 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-28 11:26:28,473 INFO L225 Difference]: With dead ends: 142 [2018-11-28 11:26:28,473 INFO L226 Difference]: Without dead ends: 142 [2018-11-28 11:26:28,473 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 76 GetRequests, 52 SyntacticMatches, 3 SemanticMatches, 21 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 36 ImplicationChecksByTransitivity, 0.4s TimeCoverageRelationStatistics Valid=70, Invalid=436, Unknown=0, NotChecked=0, Total=506 [2018-11-28 11:26:28,474 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 142 states. [2018-11-28 11:26:28,475 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 142 to 142. [2018-11-28 11:26:28,475 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 142 states. [2018-11-28 11:26:28,476 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 142 states to 142 states and 146 transitions. [2018-11-28 11:26:28,476 INFO L78 Accepts]: Start accepts. Automaton has 142 states and 146 transitions. Word has length 72 [2018-11-28 11:26:28,476 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-28 11:26:28,476 INFO L480 AbstractCegarLoop]: Abstraction has 142 states and 146 transitions. [2018-11-28 11:26:28,476 INFO L481 AbstractCegarLoop]: Interpolant automaton has 18 states. [2018-11-28 11:26:28,476 INFO L276 IsEmpty]: Start isEmpty. Operand 142 states and 146 transitions. [2018-11-28 11:26:28,477 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 82 [2018-11-28 11:26:28,477 INFO L394 BasicCegarLoop]: Found error trace [2018-11-28 11:26:28,477 INFO L402 BasicCegarLoop]: trace histogram [16, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-28 11:26:28,477 INFO L423 AbstractCegarLoop]: === Iteration 20 === [ldv_kref_initErr0REQUIRES_VIOLATION, ldv_kref_initErr1REQUIRES_VIOLATION, ldv_list_addErr1REQUIRES_VIOLATION, ldv_list_addErr0REQUIRES_VIOLATION, ldv_kobject_createErr1REQUIRES_VIOLATION, ldv_kobject_createErr0REQUIRES_VIOLATION, ldv_destroy_msgsErr5REQUIRES_VIOLATION, ldv_destroy_msgsErr0REQUIRES_VIOLATION, ldv_destroy_msgsErr4REQUIRES_VIOLATION, ldv_destroy_msgsErr2REQUIRES_VIOLATION, ldv_destroy_msgsErr3REQUIRES_VIOLATION, ldv_destroy_msgsErr1REQUIRES_VIOLATION, ldv_msg_fillErr1REQUIRES_VIOLATION, ldv_msg_fillErr3REQUIRES_VIOLATION, ldv_msg_fillErr2REQUIRES_VIOLATION, ldv_msg_fillErr4REQUIRES_VIOLATION, ldv_msg_fillErr0REQUIRES_VIOLATION, ldv_msg_fillErr5REQUIRES_VIOLATION, ldv_atomic_add_returnErr2REQUIRES_VIOLATION, ldv_atomic_add_returnErr3REQUIRES_VIOLATION, ldv_atomic_add_returnErr1REQUIRES_VIOLATION, ldv_atomic_add_returnErr0REQUIRES_VIOLATION, __ldv_list_delErr0REQUIRES_VIOLATION, __ldv_list_delErr3REQUIRES_VIOLATION, __ldv_list_delErr2REQUIRES_VIOLATION, __ldv_list_delErr1REQUIRES_VIOLATION, ldv_kobject_cleanupErr2ASSERT_VIOLATIONMEMORY_FREE, ldv_kobject_cleanupErr0REQUIRES_VIOLATION, ldv_kobject_cleanupErr4ASSERT_VIOLATIONMEMORY_FREE, ldv_kobject_cleanupErr3ASSERT_VIOLATIONMEMORY_FREE, ldv_kobject_cleanupErr5ASSERT_VIOLATIONMEMORY_FREE, ldv_kobject_cleanupErr1REQUIRES_VIOLATION, ldv_msg_freeErr3ASSERT_VIOLATIONMEMORY_FREE, ldv_msg_freeErr5ASSERT_VIOLATIONMEMORY_FREE, ldv_msg_freeErr0REQUIRES_VIOLATION, ldv_msg_freeErr2ASSERT_VIOLATIONMEMORY_FREE, ldv_msg_freeErr1REQUIRES_VIOLATION, ldv_msg_freeErr4ASSERT_VIOLATIONMEMORY_FREE, mainErr0ENSURES_VIOLATIONMEMORY_LEAK, LDV_INIT_LIST_HEADErr3REQUIRES_VIOLATION, LDV_INIT_LIST_HEADErr2REQUIRES_VIOLATION, LDV_INIT_LIST_HEADErr1REQUIRES_VIOLATION, LDV_INIT_LIST_HEADErr0REQUIRES_VIOLATION, ldv_list_delErr2REQUIRES_VIOLATION, ldv_list_delErr3REQUIRES_VIOLATION, ldv_list_delErr1REQUIRES_VIOLATION, ldv_list_delErr0REQUIRES_VIOLATION, __ldv_list_addErr0REQUIRES_VIOLATION, __ldv_list_addErr5REQUIRES_VIOLATION, __ldv_list_addErr4REQUIRES_VIOLATION, __ldv_list_addErr3REQUIRES_VIOLATION, __ldv_list_addErr2REQUIRES_VIOLATION, __ldv_list_addErr7REQUIRES_VIOLATION, __ldv_list_addErr1REQUIRES_VIOLATION, __ldv_list_addErr6REQUIRES_VIOLATION, ldv_dev_set_drvdataErr1REQUIRES_VIOLATION, ldv_dev_set_drvdataErr0REQUIRES_VIOLATION, ldv_atomic_sub_returnErr2REQUIRES_VIOLATION, ldv_atomic_sub_returnErr3REQUIRES_VIOLATION, ldv_atomic_sub_returnErr1REQUIRES_VIOLATION, ldv_atomic_sub_returnErr0REQUIRES_VIOLATION, ldv_list_add_tailErr0REQUIRES_VIOLATION, ldv_list_add_tailErr1REQUIRES_VIOLATION, ldv_dev_get_drvdataErr1REQUIRES_VIOLATION, ldv_dev_get_drvdataErr0REQUIRES_VIOLATION, ldv_msg_allocErr0REQUIRES_VIOLATION, ldv_msg_allocErr1REQUIRES_VIOLATION]=== [2018-11-28 11:26:28,477 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-28 11:26:28,478 INFO L82 PathProgramCache]: Analyzing trace with hash -298190586, now seen corresponding path program 1 times [2018-11-28 11:26:28,478 INFO L223 ckRefinementStrategy]: Switched to mode CVC4_FPBP [2018-11-28 11:26:28,478 INFO L69 tionRefinementEngine]: Using refinement strategy WolfRefinementStrategy No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_2ca7a644-5b0a-4f3d-9179-f30a2c52dfce/bin-2019/uautomizer/cvc4 Starting monitored process 21 with cvc4 --incremental --print-success --lang smt --rewrite-divk (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 21 with cvc4 --incremental --print-success --lang smt --rewrite-divk [2018-11-28 11:26:28,493 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-28 11:26:28,563 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-28 11:26:28,567 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-28 11:26:28,642 INFO L134 CoverageAnalysis]: Checked inductivity of 136 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 136 trivial. 0 not checked. [2018-11-28 11:26:28,642 INFO L312 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2018-11-28 11:26:28,644 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-28 11:26:28,644 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [10] imperfect sequences [] total 10 [2018-11-28 11:26:28,644 INFO L459 AbstractCegarLoop]: Interpolant automaton has 10 states [2018-11-28 11:26:28,645 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 10 interpolants. [2018-11-28 11:26:28,645 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=17, Invalid=73, Unknown=0, NotChecked=0, Total=90 [2018-11-28 11:26:28,645 INFO L87 Difference]: Start difference. First operand 142 states and 146 transitions. Second operand 10 states. [2018-11-28 11:26:28,708 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-28 11:26:28,708 INFO L93 Difference]: Finished difference Result 145 states and 148 transitions. [2018-11-28 11:26:28,708 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 10 states. [2018-11-28 11:26:28,709 INFO L78 Accepts]: Start accepts. Automaton has 10 states. Word has length 81 [2018-11-28 11:26:28,709 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-28 11:26:28,709 INFO L225 Difference]: With dead ends: 145 [2018-11-28 11:26:28,709 INFO L226 Difference]: Without dead ends: 142 [2018-11-28 11:26:28,709 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 82 GetRequests, 72 SyntacticMatches, 0 SemanticMatches, 10 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=25, Invalid=107, Unknown=0, NotChecked=0, Total=132 [2018-11-28 11:26:28,710 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 142 states. [2018-11-28 11:26:28,711 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 142 to 142. [2018-11-28 11:26:28,711 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 142 states. [2018-11-28 11:26:28,711 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 142 states to 142 states and 145 transitions. [2018-11-28 11:26:28,712 INFO L78 Accepts]: Start accepts. Automaton has 142 states and 145 transitions. Word has length 81 [2018-11-28 11:26:28,712 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-28 11:26:28,712 INFO L480 AbstractCegarLoop]: Abstraction has 142 states and 145 transitions. [2018-11-28 11:26:28,712 INFO L481 AbstractCegarLoop]: Interpolant automaton has 10 states. [2018-11-28 11:26:28,712 INFO L276 IsEmpty]: Start isEmpty. Operand 142 states and 145 transitions. [2018-11-28 11:26:28,713 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 95 [2018-11-28 11:26:28,713 INFO L394 BasicCegarLoop]: Found error trace [2018-11-28 11:26:28,713 INFO L402 BasicCegarLoop]: trace histogram [16, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-28 11:26:28,713 INFO L423 AbstractCegarLoop]: === Iteration 21 === [ldv_kref_initErr0REQUIRES_VIOLATION, ldv_kref_initErr1REQUIRES_VIOLATION, ldv_list_addErr1REQUIRES_VIOLATION, ldv_list_addErr0REQUIRES_VIOLATION, ldv_kobject_createErr1REQUIRES_VIOLATION, ldv_kobject_createErr0REQUIRES_VIOLATION, ldv_destroy_msgsErr5REQUIRES_VIOLATION, ldv_destroy_msgsErr0REQUIRES_VIOLATION, ldv_destroy_msgsErr4REQUIRES_VIOLATION, ldv_destroy_msgsErr2REQUIRES_VIOLATION, ldv_destroy_msgsErr3REQUIRES_VIOLATION, ldv_destroy_msgsErr1REQUIRES_VIOLATION, ldv_msg_fillErr1REQUIRES_VIOLATION, ldv_msg_fillErr3REQUIRES_VIOLATION, ldv_msg_fillErr2REQUIRES_VIOLATION, ldv_msg_fillErr4REQUIRES_VIOLATION, ldv_msg_fillErr0REQUIRES_VIOLATION, ldv_msg_fillErr5REQUIRES_VIOLATION, ldv_atomic_add_returnErr2REQUIRES_VIOLATION, ldv_atomic_add_returnErr3REQUIRES_VIOLATION, ldv_atomic_add_returnErr1REQUIRES_VIOLATION, ldv_atomic_add_returnErr0REQUIRES_VIOLATION, __ldv_list_delErr0REQUIRES_VIOLATION, __ldv_list_delErr3REQUIRES_VIOLATION, __ldv_list_delErr2REQUIRES_VIOLATION, __ldv_list_delErr1REQUIRES_VIOLATION, ldv_kobject_cleanupErr2ASSERT_VIOLATIONMEMORY_FREE, ldv_kobject_cleanupErr0REQUIRES_VIOLATION, ldv_kobject_cleanupErr4ASSERT_VIOLATIONMEMORY_FREE, ldv_kobject_cleanupErr3ASSERT_VIOLATIONMEMORY_FREE, ldv_kobject_cleanupErr5ASSERT_VIOLATIONMEMORY_FREE, ldv_kobject_cleanupErr1REQUIRES_VIOLATION, ldv_msg_freeErr3ASSERT_VIOLATIONMEMORY_FREE, ldv_msg_freeErr5ASSERT_VIOLATIONMEMORY_FREE, ldv_msg_freeErr0REQUIRES_VIOLATION, ldv_msg_freeErr2ASSERT_VIOLATIONMEMORY_FREE, ldv_msg_freeErr1REQUIRES_VIOLATION, ldv_msg_freeErr4ASSERT_VIOLATIONMEMORY_FREE, mainErr0ENSURES_VIOLATIONMEMORY_LEAK, LDV_INIT_LIST_HEADErr3REQUIRES_VIOLATION, LDV_INIT_LIST_HEADErr2REQUIRES_VIOLATION, LDV_INIT_LIST_HEADErr1REQUIRES_VIOLATION, LDV_INIT_LIST_HEADErr0REQUIRES_VIOLATION, ldv_list_delErr2REQUIRES_VIOLATION, ldv_list_delErr3REQUIRES_VIOLATION, ldv_list_delErr1REQUIRES_VIOLATION, ldv_list_delErr0REQUIRES_VIOLATION, __ldv_list_addErr0REQUIRES_VIOLATION, __ldv_list_addErr5REQUIRES_VIOLATION, __ldv_list_addErr4REQUIRES_VIOLATION, __ldv_list_addErr3REQUIRES_VIOLATION, __ldv_list_addErr2REQUIRES_VIOLATION, __ldv_list_addErr7REQUIRES_VIOLATION, __ldv_list_addErr1REQUIRES_VIOLATION, __ldv_list_addErr6REQUIRES_VIOLATION, ldv_dev_set_drvdataErr1REQUIRES_VIOLATION, ldv_dev_set_drvdataErr0REQUIRES_VIOLATION, ldv_atomic_sub_returnErr2REQUIRES_VIOLATION, ldv_atomic_sub_returnErr3REQUIRES_VIOLATION, ldv_atomic_sub_returnErr1REQUIRES_VIOLATION, ldv_atomic_sub_returnErr0REQUIRES_VIOLATION, ldv_list_add_tailErr0REQUIRES_VIOLATION, ldv_list_add_tailErr1REQUIRES_VIOLATION, ldv_dev_get_drvdataErr1REQUIRES_VIOLATION, ldv_dev_get_drvdataErr0REQUIRES_VIOLATION, ldv_msg_allocErr0REQUIRES_VIOLATION, ldv_msg_allocErr1REQUIRES_VIOLATION]=== [2018-11-28 11:26:28,713 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-28 11:26:28,713 INFO L82 PathProgramCache]: Analyzing trace with hash 240813275, now seen corresponding path program 1 times [2018-11-28 11:26:28,714 INFO L223 ckRefinementStrategy]: Switched to mode CVC4_FPBP [2018-11-28 11:26:28,714 INFO L69 tionRefinementEngine]: Using refinement strategy WolfRefinementStrategy No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_2ca7a644-5b0a-4f3d-9179-f30a2c52dfce/bin-2019/uautomizer/cvc4 Starting monitored process 22 with cvc4 --incremental --print-success --lang smt --rewrite-divk (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 22 with cvc4 --incremental --print-success --lang smt --rewrite-divk [2018-11-28 11:26:28,733 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-28 11:26:28,935 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-28 11:26:28,941 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-28 11:26:28,943 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 6 treesize of output 5 [2018-11-28 11:26:28,943 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-11-28 11:26:28,945 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-28 11:26:28,945 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 1 variables, input treesize:6, output treesize:5 [2018-11-28 11:26:29,307 INFO L134 CoverageAnalysis]: Checked inductivity of 136 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 136 trivial. 0 not checked. [2018-11-28 11:26:29,307 INFO L312 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2018-11-28 11:26:29,310 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-28 11:26:29,310 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [19] imperfect sequences [] total 19 [2018-11-28 11:26:29,310 INFO L459 AbstractCegarLoop]: Interpolant automaton has 20 states [2018-11-28 11:26:29,311 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 20 interpolants. [2018-11-28 11:26:29,311 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=54, Invalid=326, Unknown=0, NotChecked=0, Total=380 [2018-11-28 11:26:29,311 INFO L87 Difference]: Start difference. First operand 142 states and 145 transitions. Second operand 20 states. [2018-11-28 11:26:30,790 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-28 11:26:30,790 INFO L93 Difference]: Finished difference Result 156 states and 158 transitions. [2018-11-28 11:26:30,791 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 21 states. [2018-11-28 11:26:30,791 INFO L78 Accepts]: Start accepts. Automaton has 20 states. Word has length 94 [2018-11-28 11:26:30,791 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-28 11:26:30,791 INFO L225 Difference]: With dead ends: 156 [2018-11-28 11:26:30,791 INFO L226 Difference]: Without dead ends: 156 [2018-11-28 11:26:30,792 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 98 GetRequests, 70 SyntacticMatches, 5 SemanticMatches, 23 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 36 ImplicationChecksByTransitivity, 0.3s TimeCoverageRelationStatistics Valid=79, Invalid=521, Unknown=0, NotChecked=0, Total=600 [2018-11-28 11:26:30,792 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 156 states. [2018-11-28 11:26:30,793 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 156 to 140. [2018-11-28 11:26:30,793 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 140 states. [2018-11-28 11:26:30,794 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 140 states to 140 states and 143 transitions. [2018-11-28 11:26:30,794 INFO L78 Accepts]: Start accepts. Automaton has 140 states and 143 transitions. Word has length 94 [2018-11-28 11:26:30,794 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-28 11:26:30,794 INFO L480 AbstractCegarLoop]: Abstraction has 140 states and 143 transitions. [2018-11-28 11:26:30,794 INFO L481 AbstractCegarLoop]: Interpolant automaton has 20 states. [2018-11-28 11:26:30,795 INFO L276 IsEmpty]: Start isEmpty. Operand 140 states and 143 transitions. [2018-11-28 11:26:30,795 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 95 [2018-11-28 11:26:30,795 INFO L394 BasicCegarLoop]: Found error trace [2018-11-28 11:26:30,795 INFO L402 BasicCegarLoop]: trace histogram [16, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-28 11:26:30,796 INFO L423 AbstractCegarLoop]: === Iteration 22 === [ldv_kref_initErr0REQUIRES_VIOLATION, ldv_kref_initErr1REQUIRES_VIOLATION, ldv_list_addErr1REQUIRES_VIOLATION, ldv_list_addErr0REQUIRES_VIOLATION, ldv_kobject_createErr1REQUIRES_VIOLATION, ldv_kobject_createErr0REQUIRES_VIOLATION, ldv_destroy_msgsErr5REQUIRES_VIOLATION, ldv_destroy_msgsErr0REQUIRES_VIOLATION, ldv_destroy_msgsErr4REQUIRES_VIOLATION, ldv_destroy_msgsErr2REQUIRES_VIOLATION, ldv_destroy_msgsErr3REQUIRES_VIOLATION, ldv_destroy_msgsErr1REQUIRES_VIOLATION, ldv_msg_fillErr1REQUIRES_VIOLATION, ldv_msg_fillErr3REQUIRES_VIOLATION, ldv_msg_fillErr2REQUIRES_VIOLATION, ldv_msg_fillErr4REQUIRES_VIOLATION, ldv_msg_fillErr0REQUIRES_VIOLATION, ldv_msg_fillErr5REQUIRES_VIOLATION, ldv_atomic_add_returnErr2REQUIRES_VIOLATION, ldv_atomic_add_returnErr3REQUIRES_VIOLATION, ldv_atomic_add_returnErr1REQUIRES_VIOLATION, ldv_atomic_add_returnErr0REQUIRES_VIOLATION, __ldv_list_delErr0REQUIRES_VIOLATION, __ldv_list_delErr3REQUIRES_VIOLATION, __ldv_list_delErr2REQUIRES_VIOLATION, __ldv_list_delErr1REQUIRES_VIOLATION, ldv_kobject_cleanupErr2ASSERT_VIOLATIONMEMORY_FREE, ldv_kobject_cleanupErr0REQUIRES_VIOLATION, ldv_kobject_cleanupErr4ASSERT_VIOLATIONMEMORY_FREE, ldv_kobject_cleanupErr3ASSERT_VIOLATIONMEMORY_FREE, ldv_kobject_cleanupErr5ASSERT_VIOLATIONMEMORY_FREE, ldv_kobject_cleanupErr1REQUIRES_VIOLATION, ldv_msg_freeErr3ASSERT_VIOLATIONMEMORY_FREE, ldv_msg_freeErr5ASSERT_VIOLATIONMEMORY_FREE, ldv_msg_freeErr0REQUIRES_VIOLATION, ldv_msg_freeErr2ASSERT_VIOLATIONMEMORY_FREE, ldv_msg_freeErr1REQUIRES_VIOLATION, ldv_msg_freeErr4ASSERT_VIOLATIONMEMORY_FREE, mainErr0ENSURES_VIOLATIONMEMORY_LEAK, LDV_INIT_LIST_HEADErr3REQUIRES_VIOLATION, LDV_INIT_LIST_HEADErr2REQUIRES_VIOLATION, LDV_INIT_LIST_HEADErr1REQUIRES_VIOLATION, LDV_INIT_LIST_HEADErr0REQUIRES_VIOLATION, ldv_list_delErr2REQUIRES_VIOLATION, ldv_list_delErr3REQUIRES_VIOLATION, ldv_list_delErr1REQUIRES_VIOLATION, ldv_list_delErr0REQUIRES_VIOLATION, __ldv_list_addErr0REQUIRES_VIOLATION, __ldv_list_addErr5REQUIRES_VIOLATION, __ldv_list_addErr4REQUIRES_VIOLATION, __ldv_list_addErr3REQUIRES_VIOLATION, __ldv_list_addErr2REQUIRES_VIOLATION, __ldv_list_addErr7REQUIRES_VIOLATION, __ldv_list_addErr1REQUIRES_VIOLATION, __ldv_list_addErr6REQUIRES_VIOLATION, ldv_dev_set_drvdataErr1REQUIRES_VIOLATION, ldv_dev_set_drvdataErr0REQUIRES_VIOLATION, ldv_atomic_sub_returnErr2REQUIRES_VIOLATION, ldv_atomic_sub_returnErr3REQUIRES_VIOLATION, ldv_atomic_sub_returnErr1REQUIRES_VIOLATION, ldv_atomic_sub_returnErr0REQUIRES_VIOLATION, ldv_list_add_tailErr0REQUIRES_VIOLATION, ldv_list_add_tailErr1REQUIRES_VIOLATION, ldv_dev_get_drvdataErr1REQUIRES_VIOLATION, ldv_dev_get_drvdataErr0REQUIRES_VIOLATION, ldv_msg_allocErr0REQUIRES_VIOLATION, ldv_msg_allocErr1REQUIRES_VIOLATION]=== [2018-11-28 11:26:30,796 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-28 11:26:30,796 INFO L82 PathProgramCache]: Analyzing trace with hash 240813276, now seen corresponding path program 1 times [2018-11-28 11:26:30,796 INFO L223 ckRefinementStrategy]: Switched to mode CVC4_FPBP [2018-11-28 11:26:30,797 INFO L69 tionRefinementEngine]: Using refinement strategy WolfRefinementStrategy No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_2ca7a644-5b0a-4f3d-9179-f30a2c52dfce/bin-2019/uautomizer/cvc4 Starting monitored process 23 with cvc4 --incremental --print-success --lang smt --rewrite-divk (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 23 with cvc4 --incremental --print-success --lang smt --rewrite-divk [2018-11-28 11:26:30,826 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-28 11:26:31,078 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-28 11:26:31,083 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-28 11:26:31,089 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 6 treesize of output 5 [2018-11-28 11:26:31,090 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-11-28 11:26:31,095 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-28 11:26:31,096 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 1 variables, input treesize:10, output treesize:9 [2018-11-28 11:26:31,437 INFO L134 CoverageAnalysis]: Checked inductivity of 136 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 136 trivial. 0 not checked. [2018-11-28 11:26:31,437 INFO L312 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2018-11-28 11:26:31,441 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-28 11:26:31,441 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [19] imperfect sequences [] total 19 [2018-11-28 11:26:31,441 INFO L459 AbstractCegarLoop]: Interpolant automaton has 20 states [2018-11-28 11:26:31,441 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 20 interpolants. [2018-11-28 11:26:31,442 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=52, Invalid=328, Unknown=0, NotChecked=0, Total=380 [2018-11-28 11:26:31,442 INFO L87 Difference]: Start difference. First operand 140 states and 143 transitions. Second operand 20 states. [2018-11-28 11:26:32,735 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-28 11:26:32,735 INFO L93 Difference]: Finished difference Result 138 states and 141 transitions. [2018-11-28 11:26:32,736 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 20 states. [2018-11-28 11:26:32,736 INFO L78 Accepts]: Start accepts. Automaton has 20 states. Word has length 94 [2018-11-28 11:26:32,736 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-28 11:26:32,737 INFO L225 Difference]: With dead ends: 138 [2018-11-28 11:26:32,737 INFO L226 Difference]: Without dead ends: 138 [2018-11-28 11:26:32,737 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 99 GetRequests, 70 SyntacticMatches, 5 SemanticMatches, 24 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 51 ImplicationChecksByTransitivity, 0.4s TimeCoverageRelationStatistics Valid=81, Invalid=569, Unknown=0, NotChecked=0, Total=650 [2018-11-28 11:26:32,737 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 138 states. [2018-11-28 11:26:32,738 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 138 to 138. [2018-11-28 11:26:32,738 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 138 states. [2018-11-28 11:26:32,738 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 138 states to 138 states and 141 transitions. [2018-11-28 11:26:32,739 INFO L78 Accepts]: Start accepts. Automaton has 138 states and 141 transitions. Word has length 94 [2018-11-28 11:26:32,739 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-28 11:26:32,739 INFO L480 AbstractCegarLoop]: Abstraction has 138 states and 141 transitions. [2018-11-28 11:26:32,739 INFO L481 AbstractCegarLoop]: Interpolant automaton has 20 states. [2018-11-28 11:26:32,739 INFO L276 IsEmpty]: Start isEmpty. Operand 138 states and 141 transitions. [2018-11-28 11:26:32,739 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 93 [2018-11-28 11:26:32,739 INFO L394 BasicCegarLoop]: Found error trace [2018-11-28 11:26:32,739 INFO L402 BasicCegarLoop]: trace histogram [16, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-28 11:26:32,740 INFO L423 AbstractCegarLoop]: === Iteration 23 === [ldv_kref_initErr0REQUIRES_VIOLATION, ldv_kref_initErr1REQUIRES_VIOLATION, ldv_list_addErr1REQUIRES_VIOLATION, ldv_list_addErr0REQUIRES_VIOLATION, ldv_kobject_createErr1REQUIRES_VIOLATION, ldv_kobject_createErr0REQUIRES_VIOLATION, ldv_destroy_msgsErr5REQUIRES_VIOLATION, ldv_destroy_msgsErr0REQUIRES_VIOLATION, ldv_destroy_msgsErr4REQUIRES_VIOLATION, ldv_destroy_msgsErr2REQUIRES_VIOLATION, ldv_destroy_msgsErr3REQUIRES_VIOLATION, ldv_destroy_msgsErr1REQUIRES_VIOLATION, ldv_msg_fillErr1REQUIRES_VIOLATION, ldv_msg_fillErr3REQUIRES_VIOLATION, ldv_msg_fillErr2REQUIRES_VIOLATION, ldv_msg_fillErr4REQUIRES_VIOLATION, ldv_msg_fillErr0REQUIRES_VIOLATION, ldv_msg_fillErr5REQUIRES_VIOLATION, ldv_atomic_add_returnErr2REQUIRES_VIOLATION, ldv_atomic_add_returnErr3REQUIRES_VIOLATION, ldv_atomic_add_returnErr1REQUIRES_VIOLATION, ldv_atomic_add_returnErr0REQUIRES_VIOLATION, __ldv_list_delErr0REQUIRES_VIOLATION, __ldv_list_delErr3REQUIRES_VIOLATION, __ldv_list_delErr2REQUIRES_VIOLATION, __ldv_list_delErr1REQUIRES_VIOLATION, ldv_kobject_cleanupErr2ASSERT_VIOLATIONMEMORY_FREE, ldv_kobject_cleanupErr0REQUIRES_VIOLATION, ldv_kobject_cleanupErr4ASSERT_VIOLATIONMEMORY_FREE, ldv_kobject_cleanupErr3ASSERT_VIOLATIONMEMORY_FREE, ldv_kobject_cleanupErr5ASSERT_VIOLATIONMEMORY_FREE, ldv_kobject_cleanupErr1REQUIRES_VIOLATION, ldv_msg_freeErr3ASSERT_VIOLATIONMEMORY_FREE, ldv_msg_freeErr5ASSERT_VIOLATIONMEMORY_FREE, ldv_msg_freeErr0REQUIRES_VIOLATION, ldv_msg_freeErr2ASSERT_VIOLATIONMEMORY_FREE, ldv_msg_freeErr1REQUIRES_VIOLATION, ldv_msg_freeErr4ASSERT_VIOLATIONMEMORY_FREE, mainErr0ENSURES_VIOLATIONMEMORY_LEAK, LDV_INIT_LIST_HEADErr3REQUIRES_VIOLATION, LDV_INIT_LIST_HEADErr2REQUIRES_VIOLATION, LDV_INIT_LIST_HEADErr1REQUIRES_VIOLATION, LDV_INIT_LIST_HEADErr0REQUIRES_VIOLATION, ldv_list_delErr2REQUIRES_VIOLATION, ldv_list_delErr3REQUIRES_VIOLATION, ldv_list_delErr1REQUIRES_VIOLATION, ldv_list_delErr0REQUIRES_VIOLATION, __ldv_list_addErr0REQUIRES_VIOLATION, __ldv_list_addErr5REQUIRES_VIOLATION, __ldv_list_addErr4REQUIRES_VIOLATION, __ldv_list_addErr3REQUIRES_VIOLATION, __ldv_list_addErr2REQUIRES_VIOLATION, __ldv_list_addErr7REQUIRES_VIOLATION, __ldv_list_addErr1REQUIRES_VIOLATION, __ldv_list_addErr6REQUIRES_VIOLATION, ldv_dev_set_drvdataErr1REQUIRES_VIOLATION, ldv_dev_set_drvdataErr0REQUIRES_VIOLATION, ldv_atomic_sub_returnErr2REQUIRES_VIOLATION, ldv_atomic_sub_returnErr3REQUIRES_VIOLATION, ldv_atomic_sub_returnErr1REQUIRES_VIOLATION, ldv_atomic_sub_returnErr0REQUIRES_VIOLATION, ldv_list_add_tailErr0REQUIRES_VIOLATION, ldv_list_add_tailErr1REQUIRES_VIOLATION, ldv_dev_get_drvdataErr1REQUIRES_VIOLATION, ldv_dev_get_drvdataErr0REQUIRES_VIOLATION, ldv_msg_allocErr0REQUIRES_VIOLATION, ldv_msg_allocErr1REQUIRES_VIOLATION]=== [2018-11-28 11:26:32,740 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-28 11:26:32,740 INFO L82 PathProgramCache]: Analyzing trace with hash 217874955, now seen corresponding path program 1 times [2018-11-28 11:26:32,740 INFO L223 ckRefinementStrategy]: Switched to mode CVC4_FPBP [2018-11-28 11:26:32,740 INFO L69 tionRefinementEngine]: Using refinement strategy WolfRefinementStrategy No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_2ca7a644-5b0a-4f3d-9179-f30a2c52dfce/bin-2019/uautomizer/cvc4 Starting monitored process 24 with cvc4 --incremental --print-success --lang smt --rewrite-divk (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 24 with cvc4 --incremental --print-success --lang smt --rewrite-divk [2018-11-28 11:26:32,754 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-28 11:26:32,821 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-28 11:26:32,825 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-28 11:26:32,884 INFO L134 CoverageAnalysis]: Checked inductivity of 136 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 136 trivial. 0 not checked. [2018-11-28 11:26:32,884 INFO L312 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2018-11-28 11:26:32,885 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-28 11:26:32,885 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [10] imperfect sequences [] total 10 [2018-11-28 11:26:32,885 INFO L459 AbstractCegarLoop]: Interpolant automaton has 10 states [2018-11-28 11:26:32,885 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 10 interpolants. [2018-11-28 11:26:32,885 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=17, Invalid=73, Unknown=0, NotChecked=0, Total=90 [2018-11-28 11:26:32,885 INFO L87 Difference]: Start difference. First operand 138 states and 141 transitions. Second operand 10 states. [2018-11-28 11:26:32,933 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-28 11:26:32,933 INFO L93 Difference]: Finished difference Result 140 states and 142 transitions. [2018-11-28 11:26:32,933 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 10 states. [2018-11-28 11:26:32,933 INFO L78 Accepts]: Start accepts. Automaton has 10 states. Word has length 92 [2018-11-28 11:26:32,933 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-28 11:26:32,934 INFO L225 Difference]: With dead ends: 140 [2018-11-28 11:26:32,934 INFO L226 Difference]: Without dead ends: 138 [2018-11-28 11:26:32,934 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 93 GetRequests, 83 SyntacticMatches, 0 SemanticMatches, 10 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=25, Invalid=107, Unknown=0, NotChecked=0, Total=132 [2018-11-28 11:26:32,934 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 138 states. [2018-11-28 11:26:32,935 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 138 to 138. [2018-11-28 11:26:32,935 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 138 states. [2018-11-28 11:26:32,936 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 138 states to 138 states and 140 transitions. [2018-11-28 11:26:32,936 INFO L78 Accepts]: Start accepts. Automaton has 138 states and 140 transitions. Word has length 92 [2018-11-28 11:26:32,936 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-28 11:26:32,936 INFO L480 AbstractCegarLoop]: Abstraction has 138 states and 140 transitions. [2018-11-28 11:26:32,936 INFO L481 AbstractCegarLoop]: Interpolant automaton has 10 states. [2018-11-28 11:26:32,936 INFO L276 IsEmpty]: Start isEmpty. Operand 138 states and 140 transitions. [2018-11-28 11:26:32,936 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 108 [2018-11-28 11:26:32,936 INFO L394 BasicCegarLoop]: Found error trace [2018-11-28 11:26:32,936 INFO L402 BasicCegarLoop]: trace histogram [16, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-28 11:26:32,937 INFO L423 AbstractCegarLoop]: === Iteration 24 === [ldv_kref_initErr0REQUIRES_VIOLATION, ldv_kref_initErr1REQUIRES_VIOLATION, ldv_list_addErr1REQUIRES_VIOLATION, ldv_list_addErr0REQUIRES_VIOLATION, ldv_kobject_createErr1REQUIRES_VIOLATION, ldv_kobject_createErr0REQUIRES_VIOLATION, ldv_destroy_msgsErr5REQUIRES_VIOLATION, ldv_destroy_msgsErr0REQUIRES_VIOLATION, ldv_destroy_msgsErr4REQUIRES_VIOLATION, ldv_destroy_msgsErr2REQUIRES_VIOLATION, ldv_destroy_msgsErr3REQUIRES_VIOLATION, ldv_destroy_msgsErr1REQUIRES_VIOLATION, ldv_msg_fillErr1REQUIRES_VIOLATION, ldv_msg_fillErr3REQUIRES_VIOLATION, ldv_msg_fillErr2REQUIRES_VIOLATION, ldv_msg_fillErr4REQUIRES_VIOLATION, ldv_msg_fillErr0REQUIRES_VIOLATION, ldv_msg_fillErr5REQUIRES_VIOLATION, ldv_atomic_add_returnErr2REQUIRES_VIOLATION, ldv_atomic_add_returnErr3REQUIRES_VIOLATION, ldv_atomic_add_returnErr1REQUIRES_VIOLATION, ldv_atomic_add_returnErr0REQUIRES_VIOLATION, __ldv_list_delErr0REQUIRES_VIOLATION, __ldv_list_delErr3REQUIRES_VIOLATION, __ldv_list_delErr2REQUIRES_VIOLATION, __ldv_list_delErr1REQUIRES_VIOLATION, ldv_kobject_cleanupErr2ASSERT_VIOLATIONMEMORY_FREE, ldv_kobject_cleanupErr0REQUIRES_VIOLATION, ldv_kobject_cleanupErr4ASSERT_VIOLATIONMEMORY_FREE, ldv_kobject_cleanupErr3ASSERT_VIOLATIONMEMORY_FREE, ldv_kobject_cleanupErr5ASSERT_VIOLATIONMEMORY_FREE, ldv_kobject_cleanupErr1REQUIRES_VIOLATION, ldv_msg_freeErr3ASSERT_VIOLATIONMEMORY_FREE, ldv_msg_freeErr5ASSERT_VIOLATIONMEMORY_FREE, ldv_msg_freeErr0REQUIRES_VIOLATION, ldv_msg_freeErr2ASSERT_VIOLATIONMEMORY_FREE, ldv_msg_freeErr1REQUIRES_VIOLATION, ldv_msg_freeErr4ASSERT_VIOLATIONMEMORY_FREE, mainErr0ENSURES_VIOLATIONMEMORY_LEAK, LDV_INIT_LIST_HEADErr3REQUIRES_VIOLATION, LDV_INIT_LIST_HEADErr2REQUIRES_VIOLATION, LDV_INIT_LIST_HEADErr1REQUIRES_VIOLATION, LDV_INIT_LIST_HEADErr0REQUIRES_VIOLATION, ldv_list_delErr2REQUIRES_VIOLATION, ldv_list_delErr3REQUIRES_VIOLATION, ldv_list_delErr1REQUIRES_VIOLATION, ldv_list_delErr0REQUIRES_VIOLATION, __ldv_list_addErr0REQUIRES_VIOLATION, __ldv_list_addErr5REQUIRES_VIOLATION, __ldv_list_addErr4REQUIRES_VIOLATION, __ldv_list_addErr3REQUIRES_VIOLATION, __ldv_list_addErr2REQUIRES_VIOLATION, __ldv_list_addErr7REQUIRES_VIOLATION, __ldv_list_addErr1REQUIRES_VIOLATION, __ldv_list_addErr6REQUIRES_VIOLATION, ldv_dev_set_drvdataErr1REQUIRES_VIOLATION, ldv_dev_set_drvdataErr0REQUIRES_VIOLATION, ldv_atomic_sub_returnErr2REQUIRES_VIOLATION, ldv_atomic_sub_returnErr3REQUIRES_VIOLATION, ldv_atomic_sub_returnErr1REQUIRES_VIOLATION, ldv_atomic_sub_returnErr0REQUIRES_VIOLATION, ldv_list_add_tailErr0REQUIRES_VIOLATION, ldv_list_add_tailErr1REQUIRES_VIOLATION, ldv_dev_get_drvdataErr1REQUIRES_VIOLATION, ldv_dev_get_drvdataErr0REQUIRES_VIOLATION, ldv_msg_allocErr0REQUIRES_VIOLATION, ldv_msg_allocErr1REQUIRES_VIOLATION]=== [2018-11-28 11:26:32,937 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-28 11:26:32,937 INFO L82 PathProgramCache]: Analyzing trace with hash -220146983, now seen corresponding path program 1 times [2018-11-28 11:26:32,937 INFO L223 ckRefinementStrategy]: Switched to mode CVC4_FPBP [2018-11-28 11:26:32,937 INFO L69 tionRefinementEngine]: Using refinement strategy WolfRefinementStrategy No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_2ca7a644-5b0a-4f3d-9179-f30a2c52dfce/bin-2019/uautomizer/cvc4 Starting monitored process 25 with cvc4 --incremental --print-success --lang smt --rewrite-divk (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 25 with cvc4 --incremental --print-success --lang smt --rewrite-divk [2018-11-28 11:26:32,951 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-28 11:26:33,167 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-28 11:26:33,185 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-28 11:26:33,187 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 6 treesize of output 5 [2018-11-28 11:26:33,188 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-11-28 11:26:33,189 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-28 11:26:33,189 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 1 variables, input treesize:6, output treesize:5 [2018-11-28 11:26:33,635 INFO L134 CoverageAnalysis]: Checked inductivity of 136 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 136 trivial. 0 not checked. [2018-11-28 11:26:33,635 INFO L312 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2018-11-28 11:26:33,638 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-28 11:26:33,638 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [23] imperfect sequences [] total 23 [2018-11-28 11:26:33,639 INFO L459 AbstractCegarLoop]: Interpolant automaton has 24 states [2018-11-28 11:26:33,639 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 24 interpolants. [2018-11-28 11:26:33,639 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=66, Invalid=486, Unknown=0, NotChecked=0, Total=552 [2018-11-28 11:26:33,639 INFO L87 Difference]: Start difference. First operand 138 states and 140 transitions. Second operand 24 states. [2018-11-28 11:26:35,360 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-28 11:26:35,360 INFO L93 Difference]: Finished difference Result 148 states and 149 transitions. [2018-11-28 11:26:35,360 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 25 states. [2018-11-28 11:26:35,360 INFO L78 Accepts]: Start accepts. Automaton has 24 states. Word has length 107 [2018-11-28 11:26:35,361 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-28 11:26:35,361 INFO L225 Difference]: With dead ends: 148 [2018-11-28 11:26:35,361 INFO L226 Difference]: Without dead ends: 148 [2018-11-28 11:26:35,361 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 113 GetRequests, 77 SyntacticMatches, 7 SemanticMatches, 29 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 64 ImplicationChecksByTransitivity, 0.5s TimeCoverageRelationStatistics Valid=101, Invalid=829, Unknown=0, NotChecked=0, Total=930 [2018-11-28 11:26:35,362 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 148 states. [2018-11-28 11:26:35,363 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 148 to 136. [2018-11-28 11:26:35,363 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 136 states. [2018-11-28 11:26:35,364 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 136 states to 136 states and 138 transitions. [2018-11-28 11:26:35,364 INFO L78 Accepts]: Start accepts. Automaton has 136 states and 138 transitions. Word has length 107 [2018-11-28 11:26:35,364 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-28 11:26:35,364 INFO L480 AbstractCegarLoop]: Abstraction has 136 states and 138 transitions. [2018-11-28 11:26:35,364 INFO L481 AbstractCegarLoop]: Interpolant automaton has 24 states. [2018-11-28 11:26:35,364 INFO L276 IsEmpty]: Start isEmpty. Operand 136 states and 138 transitions. [2018-11-28 11:26:35,365 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 108 [2018-11-28 11:26:35,365 INFO L394 BasicCegarLoop]: Found error trace [2018-11-28 11:26:35,365 INFO L402 BasicCegarLoop]: trace histogram [16, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-28 11:26:35,365 INFO L423 AbstractCegarLoop]: === Iteration 25 === [ldv_kref_initErr0REQUIRES_VIOLATION, ldv_kref_initErr1REQUIRES_VIOLATION, ldv_list_addErr1REQUIRES_VIOLATION, ldv_list_addErr0REQUIRES_VIOLATION, ldv_kobject_createErr1REQUIRES_VIOLATION, ldv_kobject_createErr0REQUIRES_VIOLATION, ldv_destroy_msgsErr5REQUIRES_VIOLATION, ldv_destroy_msgsErr0REQUIRES_VIOLATION, ldv_destroy_msgsErr4REQUIRES_VIOLATION, ldv_destroy_msgsErr2REQUIRES_VIOLATION, ldv_destroy_msgsErr3REQUIRES_VIOLATION, ldv_destroy_msgsErr1REQUIRES_VIOLATION, ldv_msg_fillErr1REQUIRES_VIOLATION, ldv_msg_fillErr3REQUIRES_VIOLATION, ldv_msg_fillErr2REQUIRES_VIOLATION, ldv_msg_fillErr4REQUIRES_VIOLATION, ldv_msg_fillErr0REQUIRES_VIOLATION, ldv_msg_fillErr5REQUIRES_VIOLATION, ldv_atomic_add_returnErr2REQUIRES_VIOLATION, ldv_atomic_add_returnErr3REQUIRES_VIOLATION, ldv_atomic_add_returnErr1REQUIRES_VIOLATION, ldv_atomic_add_returnErr0REQUIRES_VIOLATION, __ldv_list_delErr0REQUIRES_VIOLATION, __ldv_list_delErr3REQUIRES_VIOLATION, __ldv_list_delErr2REQUIRES_VIOLATION, __ldv_list_delErr1REQUIRES_VIOLATION, ldv_kobject_cleanupErr2ASSERT_VIOLATIONMEMORY_FREE, ldv_kobject_cleanupErr0REQUIRES_VIOLATION, ldv_kobject_cleanupErr4ASSERT_VIOLATIONMEMORY_FREE, ldv_kobject_cleanupErr3ASSERT_VIOLATIONMEMORY_FREE, ldv_kobject_cleanupErr5ASSERT_VIOLATIONMEMORY_FREE, ldv_kobject_cleanupErr1REQUIRES_VIOLATION, ldv_msg_freeErr3ASSERT_VIOLATIONMEMORY_FREE, ldv_msg_freeErr5ASSERT_VIOLATIONMEMORY_FREE, ldv_msg_freeErr0REQUIRES_VIOLATION, ldv_msg_freeErr2ASSERT_VIOLATIONMEMORY_FREE, ldv_msg_freeErr1REQUIRES_VIOLATION, ldv_msg_freeErr4ASSERT_VIOLATIONMEMORY_FREE, mainErr0ENSURES_VIOLATIONMEMORY_LEAK, LDV_INIT_LIST_HEADErr3REQUIRES_VIOLATION, LDV_INIT_LIST_HEADErr2REQUIRES_VIOLATION, LDV_INIT_LIST_HEADErr1REQUIRES_VIOLATION, LDV_INIT_LIST_HEADErr0REQUIRES_VIOLATION, ldv_list_delErr2REQUIRES_VIOLATION, ldv_list_delErr3REQUIRES_VIOLATION, ldv_list_delErr1REQUIRES_VIOLATION, ldv_list_delErr0REQUIRES_VIOLATION, __ldv_list_addErr0REQUIRES_VIOLATION, __ldv_list_addErr5REQUIRES_VIOLATION, __ldv_list_addErr4REQUIRES_VIOLATION, __ldv_list_addErr3REQUIRES_VIOLATION, __ldv_list_addErr2REQUIRES_VIOLATION, __ldv_list_addErr7REQUIRES_VIOLATION, __ldv_list_addErr1REQUIRES_VIOLATION, __ldv_list_addErr6REQUIRES_VIOLATION, ldv_dev_set_drvdataErr1REQUIRES_VIOLATION, ldv_dev_set_drvdataErr0REQUIRES_VIOLATION, ldv_atomic_sub_returnErr2REQUIRES_VIOLATION, ldv_atomic_sub_returnErr3REQUIRES_VIOLATION, ldv_atomic_sub_returnErr1REQUIRES_VIOLATION, ldv_atomic_sub_returnErr0REQUIRES_VIOLATION, ldv_list_add_tailErr0REQUIRES_VIOLATION, ldv_list_add_tailErr1REQUIRES_VIOLATION, ldv_dev_get_drvdataErr1REQUIRES_VIOLATION, ldv_dev_get_drvdataErr0REQUIRES_VIOLATION, ldv_msg_allocErr0REQUIRES_VIOLATION, ldv_msg_allocErr1REQUIRES_VIOLATION]=== [2018-11-28 11:26:35,366 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-28 11:26:35,366 INFO L82 PathProgramCache]: Analyzing trace with hash -220146982, now seen corresponding path program 1 times [2018-11-28 11:26:35,366 INFO L223 ckRefinementStrategy]: Switched to mode CVC4_FPBP [2018-11-28 11:26:35,366 INFO L69 tionRefinementEngine]: Using refinement strategy WolfRefinementStrategy No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_2ca7a644-5b0a-4f3d-9179-f30a2c52dfce/bin-2019/uautomizer/cvc4 Starting monitored process 26 with cvc4 --incremental --print-success --lang smt --rewrite-divk (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 26 with cvc4 --incremental --print-success --lang smt --rewrite-divk [2018-11-28 11:26:35,381 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-28 11:26:35,709 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-28 11:26:35,716 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-28 11:26:35,723 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 6 treesize of output 5 [2018-11-28 11:26:35,723 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-11-28 11:26:35,730 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-28 11:26:35,730 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 1 variables, input treesize:10, output treesize:9 [2018-11-28 11:26:36,378 INFO L134 CoverageAnalysis]: Checked inductivity of 136 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 136 trivial. 0 not checked. [2018-11-28 11:26:36,378 INFO L312 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2018-11-28 11:26:36,381 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-28 11:26:36,381 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [23] imperfect sequences [] total 23 [2018-11-28 11:26:36,381 INFO L459 AbstractCegarLoop]: Interpolant automaton has 24 states [2018-11-28 11:26:36,382 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 24 interpolants. [2018-11-28 11:26:36,382 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=64, Invalid=488, Unknown=0, NotChecked=0, Total=552 [2018-11-28 11:26:36,382 INFO L87 Difference]: Start difference. First operand 136 states and 138 transitions. Second operand 24 states. [2018-11-28 11:26:37,957 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-28 11:26:37,957 INFO L93 Difference]: Finished difference Result 134 states and 136 transitions. [2018-11-28 11:26:37,957 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 24 states. [2018-11-28 11:26:37,957 INFO L78 Accepts]: Start accepts. Automaton has 24 states. Word has length 107 [2018-11-28 11:26:37,957 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-28 11:26:37,958 INFO L225 Difference]: With dead ends: 134 [2018-11-28 11:26:37,958 INFO L226 Difference]: Without dead ends: 134 [2018-11-28 11:26:37,958 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 114 GetRequests, 77 SyntacticMatches, 7 SemanticMatches, 30 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 84 ImplicationChecksByTransitivity, 0.7s TimeCoverageRelationStatistics Valid=103, Invalid=889, Unknown=0, NotChecked=0, Total=992 [2018-11-28 11:26:37,958 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 134 states. [2018-11-28 11:26:37,959 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 134 to 134. [2018-11-28 11:26:37,960 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 134 states. [2018-11-28 11:26:37,960 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 134 states to 134 states and 136 transitions. [2018-11-28 11:26:37,960 INFO L78 Accepts]: Start accepts. Automaton has 134 states and 136 transitions. Word has length 107 [2018-11-28 11:26:37,960 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-28 11:26:37,961 INFO L480 AbstractCegarLoop]: Abstraction has 134 states and 136 transitions. [2018-11-28 11:26:37,961 INFO L481 AbstractCegarLoop]: Interpolant automaton has 24 states. [2018-11-28 11:26:37,961 INFO L276 IsEmpty]: Start isEmpty. Operand 134 states and 136 transitions. [2018-11-28 11:26:37,961 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 113 [2018-11-28 11:26:37,961 INFO L394 BasicCegarLoop]: Found error trace [2018-11-28 11:26:37,961 INFO L402 BasicCegarLoop]: trace histogram [16, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-28 11:26:37,962 INFO L423 AbstractCegarLoop]: === Iteration 26 === [ldv_kref_initErr0REQUIRES_VIOLATION, ldv_kref_initErr1REQUIRES_VIOLATION, ldv_list_addErr1REQUIRES_VIOLATION, ldv_list_addErr0REQUIRES_VIOLATION, ldv_kobject_createErr1REQUIRES_VIOLATION, ldv_kobject_createErr0REQUIRES_VIOLATION, ldv_destroy_msgsErr5REQUIRES_VIOLATION, ldv_destroy_msgsErr0REQUIRES_VIOLATION, ldv_destroy_msgsErr4REQUIRES_VIOLATION, ldv_destroy_msgsErr2REQUIRES_VIOLATION, ldv_destroy_msgsErr3REQUIRES_VIOLATION, ldv_destroy_msgsErr1REQUIRES_VIOLATION, ldv_msg_fillErr1REQUIRES_VIOLATION, ldv_msg_fillErr3REQUIRES_VIOLATION, ldv_msg_fillErr2REQUIRES_VIOLATION, ldv_msg_fillErr4REQUIRES_VIOLATION, ldv_msg_fillErr0REQUIRES_VIOLATION, ldv_msg_fillErr5REQUIRES_VIOLATION, ldv_atomic_add_returnErr2REQUIRES_VIOLATION, ldv_atomic_add_returnErr3REQUIRES_VIOLATION, ldv_atomic_add_returnErr1REQUIRES_VIOLATION, ldv_atomic_add_returnErr0REQUIRES_VIOLATION, __ldv_list_delErr0REQUIRES_VIOLATION, __ldv_list_delErr3REQUIRES_VIOLATION, __ldv_list_delErr2REQUIRES_VIOLATION, __ldv_list_delErr1REQUIRES_VIOLATION, ldv_kobject_cleanupErr2ASSERT_VIOLATIONMEMORY_FREE, ldv_kobject_cleanupErr0REQUIRES_VIOLATION, ldv_kobject_cleanupErr4ASSERT_VIOLATIONMEMORY_FREE, ldv_kobject_cleanupErr3ASSERT_VIOLATIONMEMORY_FREE, ldv_kobject_cleanupErr5ASSERT_VIOLATIONMEMORY_FREE, ldv_kobject_cleanupErr1REQUIRES_VIOLATION, ldv_msg_freeErr3ASSERT_VIOLATIONMEMORY_FREE, ldv_msg_freeErr5ASSERT_VIOLATIONMEMORY_FREE, ldv_msg_freeErr0REQUIRES_VIOLATION, ldv_msg_freeErr2ASSERT_VIOLATIONMEMORY_FREE, ldv_msg_freeErr1REQUIRES_VIOLATION, ldv_msg_freeErr4ASSERT_VIOLATIONMEMORY_FREE, mainErr0ENSURES_VIOLATIONMEMORY_LEAK, LDV_INIT_LIST_HEADErr3REQUIRES_VIOLATION, LDV_INIT_LIST_HEADErr2REQUIRES_VIOLATION, LDV_INIT_LIST_HEADErr1REQUIRES_VIOLATION, LDV_INIT_LIST_HEADErr0REQUIRES_VIOLATION, ldv_list_delErr2REQUIRES_VIOLATION, ldv_list_delErr3REQUIRES_VIOLATION, ldv_list_delErr1REQUIRES_VIOLATION, ldv_list_delErr0REQUIRES_VIOLATION, __ldv_list_addErr0REQUIRES_VIOLATION, __ldv_list_addErr5REQUIRES_VIOLATION, __ldv_list_addErr4REQUIRES_VIOLATION, __ldv_list_addErr3REQUIRES_VIOLATION, __ldv_list_addErr2REQUIRES_VIOLATION, __ldv_list_addErr7REQUIRES_VIOLATION, __ldv_list_addErr1REQUIRES_VIOLATION, __ldv_list_addErr6REQUIRES_VIOLATION, ldv_dev_set_drvdataErr1REQUIRES_VIOLATION, ldv_dev_set_drvdataErr0REQUIRES_VIOLATION, ldv_atomic_sub_returnErr2REQUIRES_VIOLATION, ldv_atomic_sub_returnErr3REQUIRES_VIOLATION, ldv_atomic_sub_returnErr1REQUIRES_VIOLATION, ldv_atomic_sub_returnErr0REQUIRES_VIOLATION, ldv_list_add_tailErr0REQUIRES_VIOLATION, ldv_list_add_tailErr1REQUIRES_VIOLATION, ldv_dev_get_drvdataErr1REQUIRES_VIOLATION, ldv_dev_get_drvdataErr0REQUIRES_VIOLATION, ldv_msg_allocErr0REQUIRES_VIOLATION, ldv_msg_allocErr1REQUIRES_VIOLATION]=== [2018-11-28 11:26:37,962 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-28 11:26:37,962 INFO L82 PathProgramCache]: Analyzing trace with hash -1296614760, now seen corresponding path program 1 times [2018-11-28 11:26:37,962 INFO L223 ckRefinementStrategy]: Switched to mode CVC4_FPBP [2018-11-28 11:26:37,962 INFO L69 tionRefinementEngine]: Using refinement strategy WolfRefinementStrategy No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_2ca7a644-5b0a-4f3d-9179-f30a2c52dfce/bin-2019/uautomizer/cvc4 Starting monitored process 27 with cvc4 --incremental --print-success --lang smt --rewrite-divk (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 27 with cvc4 --incremental --print-success --lang smt --rewrite-divk [2018-11-28 11:26:37,976 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-28 11:26:38,340 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-28 11:26:38,370 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-28 11:26:38,393 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 13 treesize of output 10 [2018-11-28 11:26:38,395 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 10 treesize of output 9 [2018-11-28 11:26:38,395 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-11-28 11:26:38,398 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-28 11:26:38,404 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-2 vars, End of recursive call: and 1 xjuncts. [2018-11-28 11:26:38,404 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 1 variables, input treesize:17, output treesize:13 [2018-11-28 11:26:38,424 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 25 treesize of output 20 [2018-11-28 11:26:38,427 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:38,428 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 20 treesize of output 27 [2018-11-28 11:26:38,429 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-11-28 11:26:38,437 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-28 11:26:38,446 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-2 vars, End of recursive call: and 1 xjuncts. [2018-11-28 11:26:38,446 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 1 variables, input treesize:28, output treesize:24 [2018-11-28 11:26:38,474 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 36 treesize of output 29 [2018-11-28 11:26:38,478 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:38,479 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:38,481 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:38,482 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 2 select indices, 2 select index equivalence classes, 3 disjoint index pairs (out of 1 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 29 treesize of output 52 [2018-11-28 11:26:38,482 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-11-28 11:26:38,498 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-28 11:26:38,512 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-2 vars, End of recursive call: and 1 xjuncts. [2018-11-28 11:26:38,512 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 1 variables, input treesize:39, output treesize:35 [2018-11-28 11:26:38,553 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 47 treesize of output 38 [2018-11-28 11:26:38,558 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:38,560 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:38,562 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:38,564 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:38,565 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:38,568 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:38,569 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 3 select indices, 3 select index equivalence classes, 6 disjoint index pairs (out of 3 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 38 treesize of output 85 [2018-11-28 11:26:38,569 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-11-28 11:26:38,608 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-28 11:26:38,632 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-2 vars, End of recursive call: and 1 xjuncts. [2018-11-28 11:26:38,633 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 1 variables, input treesize:50, output treesize:46 [2018-11-28 11:26:38,688 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 58 treesize of output 47 [2018-11-28 11:26:38,693 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:38,695 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:38,696 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:38,698 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:38,700 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:38,702 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:38,703 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:38,705 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:38,706 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:38,708 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:38,709 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 4 select indices, 4 select index equivalence classes, 10 disjoint index pairs (out of 6 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 47 treesize of output 126 [2018-11-28 11:26:38,710 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-11-28 11:26:38,757 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-28 11:26:38,783 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-2 vars, End of recursive call: and 1 xjuncts. [2018-11-28 11:26:38,784 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 1 variables, input treesize:61, output treesize:57 [2018-11-28 11:26:38,859 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 69 treesize of output 56 [2018-11-28 11:26:38,866 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:38,868 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:38,870 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:38,872 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:38,874 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:38,876 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:38,878 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:38,880 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:38,881 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:38,883 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:38,885 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:38,886 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:38,888 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:38,890 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:38,892 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:38,893 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 5 select indices, 5 select index equivalence classes, 15 disjoint index pairs (out of 10 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 56 treesize of output 175 [2018-11-28 11:26:38,893 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-11-28 11:26:38,964 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-28 11:26:38,999 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-2 vars, End of recursive call: and 1 xjuncts. [2018-11-28 11:26:38,999 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 1 variables, input treesize:72, output treesize:68 [2018-11-28 11:26:39,089 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 80 treesize of output 65 [2018-11-28 11:26:39,095 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:39,097 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:39,099 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:39,101 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:39,103 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:39,105 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:39,107 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:39,109 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:39,111 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:39,113 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:39,115 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:39,117 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:39,119 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:39,121 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:39,123 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:39,125 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:39,127 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:39,129 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:39,131 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:39,133 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:39,135 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:39,136 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 6 select indices, 6 select index equivalence classes, 21 disjoint index pairs (out of 15 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 65 treesize of output 232 [2018-11-28 11:26:39,137 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-11-28 11:26:39,244 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-28 11:26:39,287 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-2 vars, End of recursive call: and 1 xjuncts. [2018-11-28 11:26:39,288 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 1 variables, input treesize:83, output treesize:79 [2018-11-28 11:26:39,426 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 91 treesize of output 74 [2018-11-28 11:26:39,433 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:39,436 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:39,438 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:39,440 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:39,444 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:39,446 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:39,448 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:39,450 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:39,453 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:39,455 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:39,457 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:39,459 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:39,461 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:39,463 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:39,466 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:39,468 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:39,470 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:39,472 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:39,474 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:39,476 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:39,478 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:39,481 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:39,483 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:39,485 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:39,487 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:39,489 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:39,492 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:39,494 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:39,495 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 7 select indices, 7 select index equivalence classes, 28 disjoint index pairs (out of 21 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 74 treesize of output 297 [2018-11-28 11:26:39,496 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-11-28 11:26:39,640 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-28 11:26:39,694 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-2 vars, End of recursive call: and 1 xjuncts. [2018-11-28 11:26:39,694 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 1 variables, input treesize:94, output treesize:90 [2018-11-28 11:26:39,829 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 102 treesize of output 83 [2018-11-28 11:26:39,837 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:39,839 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:39,841 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:39,843 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:39,846 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:39,848 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:39,850 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:39,853 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:39,855 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:39,858 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:39,860 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:39,862 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:39,864 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:39,866 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:39,868 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:39,869 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:39,871 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:39,874 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:39,875 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:39,877 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:39,880 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:39,882 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:39,885 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:39,887 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:39,890 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:39,892 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:39,894 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:39,897 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:39,899 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:39,901 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:39,904 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:39,906 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:39,909 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:39,911 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:39,913 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:39,916 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:39,917 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 8 select indices, 8 select index equivalence classes, 36 disjoint index pairs (out of 28 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 83 treesize of output 370 [2018-11-28 11:26:39,918 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-11-28 11:26:40,118 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-28 11:26:40,182 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-2 vars, End of recursive call: and 1 xjuncts. [2018-11-28 11:26:40,182 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 1 variables, input treesize:105, output treesize:101 [2018-11-28 11:26:40,346 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 113 treesize of output 92 [2018-11-28 11:26:40,354 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:40,357 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:40,360 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:40,363 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:40,367 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:40,369 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:40,374 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:40,378 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:40,382 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:40,387 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:40,391 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:40,395 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:40,399 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:40,403 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:40,407 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:40,411 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:40,415 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:40,418 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:40,421 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:40,424 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:40,426 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:40,429 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:40,432 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:40,435 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:40,437 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:40,440 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:40,443 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:40,445 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:40,448 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:40,451 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:40,454 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:40,456 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:40,459 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:40,462 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:40,464 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:40,467 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:40,470 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:40,472 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:40,475 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:40,478 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:40,480 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:40,483 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:40,486 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:40,488 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:40,491 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:40,492 INFO L303 Elim1Store]: Index analysis took 144 ms [2018-11-28 11:26:40,493 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 9 select indices, 9 select index equivalence classes, 45 disjoint index pairs (out of 36 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 92 treesize of output 451 [2018-11-28 11:26:40,494 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-11-28 11:26:40,762 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-28 11:26:40,838 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-2 vars, End of recursive call: and 1 xjuncts. [2018-11-28 11:26:40,838 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 1 variables, input treesize:116, output treesize:112 [2018-11-28 11:26:41,030 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 124 treesize of output 101 [2018-11-28 11:26:41,051 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:41,055 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:41,058 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:41,063 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:41,067 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:41,072 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:41,076 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:41,079 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:41,082 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:41,085 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:41,088 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:41,091 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:41,093 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:41,096 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:41,099 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:41,102 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:41,105 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:41,107 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:41,110 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:41,113 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:41,116 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:41,119 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:41,122 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:41,125 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:41,128 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:41,131 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:41,134 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:41,136 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:41,139 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:41,142 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:41,145 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:41,148 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:41,151 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:41,153 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:41,156 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:41,159 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:41,162 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:41,165 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:41,167 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:41,170 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:41,173 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:41,176 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:41,179 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:41,182 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:41,185 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:41,188 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:41,191 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:41,194 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:41,196 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:41,200 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:41,203 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:41,206 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:41,208 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:41,211 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:41,214 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:41,215 INFO L303 Elim1Store]: Index analysis took 183 ms [2018-11-28 11:26:41,216 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 10 select indices, 10 select index equivalence classes, 55 disjoint index pairs (out of 45 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 101 treesize of output 540 [2018-11-28 11:26:41,217 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-11-28 11:26:41,574 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-28 11:26:41,665 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-2 vars, End of recursive call: and 1 xjuncts. [2018-11-28 11:26:41,665 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 1 variables, input treesize:127, output treesize:123 [2018-11-28 11:26:41,906 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 135 treesize of output 110 [2018-11-28 11:26:41,917 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:41,920 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:41,923 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:41,926 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:41,931 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:41,934 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:41,938 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:41,942 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:41,946 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:41,949 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:41,952 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:41,955 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:41,958 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:41,961 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:41,964 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:41,967 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:41,969 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:41,972 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:41,975 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:41,978 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:41,981 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:41,984 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:41,987 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:41,990 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:41,993 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:41,996 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:41,999 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:42,002 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:42,006 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:42,009 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:42,012 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:42,015 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:42,018 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:42,021 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:42,024 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:42,027 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:42,030 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:42,033 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:42,036 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:42,039 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:42,042 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:42,045 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:42,048 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:42,051 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:42,054 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:42,057 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:42,060 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:42,063 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:42,066 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:42,069 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:42,073 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:42,076 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:42,079 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:42,082 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:42,085 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:42,088 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:42,091 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:42,094 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:42,097 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:42,100 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:42,103 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:42,106 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:42,109 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:42,112 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:42,115 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:42,118 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:42,119 INFO L303 Elim1Store]: Index analysis took 211 ms [2018-11-28 11:26:42,120 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 11 select indices, 11 select index equivalence classes, 66 disjoint index pairs (out of 55 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 110 treesize of output 637 [2018-11-28 11:26:42,121 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-11-28 11:26:42,574 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-28 11:26:42,678 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-2 vars, End of recursive call: and 1 xjuncts. [2018-11-28 11:26:42,678 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 1 variables, input treesize:138, output treesize:134 [2018-11-28 11:26:42,918 WARN L180 SmtUtils]: Spent 105.00 ms on a formula simplification that was a NOOP. DAG size: 57 [2018-11-28 11:26:42,937 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 146 treesize of output 119 [2018-11-28 11:26:42,948 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:42,951 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:42,954 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:42,957 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:42,961 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:42,964 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:42,967 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:42,970 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:42,973 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:42,977 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:42,980 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:42,983 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:42,986 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:42,989 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:42,992 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:42,996 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:42,999 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:43,002 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:43,005 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:43,008 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:43,011 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:43,014 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:43,017 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:43,021 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:43,024 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:43,027 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:43,030 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:43,033 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:43,037 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:43,040 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:43,043 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:43,046 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:43,049 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:43,052 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:43,055 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:43,058 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:43,061 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:43,065 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:43,068 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:43,071 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:43,074 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:43,077 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:43,080 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:43,083 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:43,086 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:43,090 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:43,093 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:43,096 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:43,099 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:43,102 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:43,105 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:43,109 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:43,112 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:43,115 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:43,118 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:43,121 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:43,124 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:43,127 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:43,131 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:43,134 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:43,137 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:43,140 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:43,143 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:43,146 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:43,149 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:43,152 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:43,155 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:43,158 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:43,161 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:43,164 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:43,168 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:43,171 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:43,174 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:43,177 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:43,180 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:43,183 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:43,186 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:43,189 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:43,191 INFO L303 Elim1Store]: Index analysis took 251 ms [2018-11-28 11:26:43,192 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 12 select indices, 12 select index equivalence classes, 78 disjoint index pairs (out of 66 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 119 treesize of output 742 [2018-11-28 11:26:43,193 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-11-28 11:26:43,785 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-28 11:26:43,943 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-2 vars, End of recursive call: and 1 xjuncts. [2018-11-28 11:26:43,943 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 1 variables, input treesize:149, output treesize:145 [2018-11-28 11:26:44,216 WARN L180 SmtUtils]: Spent 119.00 ms on a formula simplification that was a NOOP. DAG size: 61 [2018-11-28 11:26:44,256 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 157 treesize of output 128 [2018-11-28 11:26:44,278 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:44,289 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:44,303 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:44,307 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:44,320 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:44,334 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:44,341 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:44,355 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:44,366 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:44,375 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:44,382 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:44,393 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:44,404 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:44,413 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:44,422 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:44,434 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:44,448 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:44,463 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:44,467 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:44,479 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:44,493 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:44,505 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:44,518 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:44,523 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:44,538 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:44,548 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:44,554 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:44,558 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:44,567 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:44,575 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:44,589 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:44,601 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:44,614 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:44,625 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:44,638 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:44,652 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:44,663 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:44,672 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:44,685 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:44,695 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:44,707 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:44,720 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:44,731 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:44,745 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:44,755 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:44,765 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:44,776 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:44,787 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:44,800 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:44,814 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:44,827 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:44,839 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:44,843 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:44,858 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:44,872 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:44,884 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:44,898 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:44,912 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:44,926 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:44,939 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:44,951 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:44,964 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:44,973 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:44,986 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:44,993 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:45,001 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:45,014 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:45,027 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:45,041 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:45,045 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:45,059 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:45,067 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:45,076 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:45,086 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:45,095 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:45,107 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:45,119 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:45,125 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:45,138 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:45,145 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:45,154 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:45,166 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:45,174 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:45,188 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:45,199 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:45,208 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:45,219 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:45,232 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:45,246 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:45,259 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:45,270 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:45,271 INFO L303 Elim1Store]: Index analysis took 1013 ms [2018-11-28 11:26:45,273 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 13 select indices, 13 select index equivalence classes, 91 disjoint index pairs (out of 78 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 128 treesize of output 855 [2018-11-28 11:26:45,274 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-11-28 11:26:46,004 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-28 11:26:46,141 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-2 vars, End of recursive call: and 1 xjuncts. [2018-11-28 11:26:46,141 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 1 variables, input treesize:160, output treesize:156 [2018-11-28 11:26:46,455 WARN L180 SmtUtils]: Spent 137.00 ms on a formula simplification that was a NOOP. DAG size: 65 [2018-11-28 11:26:46,486 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 168 treesize of output 137 [2018-11-28 11:26:46,498 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:46,502 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:46,506 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:46,509 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:46,513 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:46,517 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:46,520 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:46,525 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:46,527 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:46,530 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:46,533 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:46,537 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:46,539 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:46,542 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:46,545 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:46,548 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:46,551 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:46,554 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:46,557 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:46,561 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:46,563 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:46,567 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:46,569 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:46,573 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:46,576 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:46,579 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:46,582 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:46,585 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:46,588 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:46,592 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:46,594 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:46,598 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:46,600 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:46,604 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:46,607 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:46,610 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:46,614 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:46,618 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:46,622 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:46,625 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:46,629 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:46,633 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:46,636 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:46,640 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:46,644 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:46,647 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:46,651 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:46,655 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:46,658 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:46,662 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:46,666 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:46,669 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:46,673 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:46,677 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:46,680 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:46,684 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:46,688 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:46,692 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:46,696 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:46,700 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:46,703 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:46,707 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:46,711 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:46,714 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:46,718 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:46,721 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:46,725 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:46,729 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:46,733 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:46,736 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:46,740 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:46,744 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:46,747 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:46,751 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:46,755 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:46,759 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:46,762 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:46,766 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:46,770 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:46,774 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:46,778 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:46,782 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:46,786 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:46,790 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:46,793 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:46,797 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:46,801 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:46,805 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:46,809 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:46,813 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:46,817 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:46,821 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:46,824 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:46,828 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:46,832 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:46,836 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:46,840 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:46,844 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:46,848 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:46,852 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:46,855 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:46,859 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:46,863 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:46,866 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:46,870 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:46,872 INFO L303 Elim1Store]: Index analysis took 383 ms [2018-11-28 11:26:46,873 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 14 select indices, 14 select index equivalence classes, 105 disjoint index pairs (out of 91 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 137 treesize of output 976 [2018-11-28 11:26:46,875 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-11-28 11:26:47,747 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-28 11:26:47,910 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-2 vars, End of recursive call: and 1 xjuncts. [2018-11-28 11:26:47,910 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 1 variables, input treesize:171, output treesize:167 [2018-11-28 11:26:48,268 WARN L180 SmtUtils]: Spent 159.00 ms on a formula simplification that was a NOOP. DAG size: 69 [2018-11-28 11:26:48,313 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 179 treesize of output 146 [2018-11-28 11:26:48,336 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:48,351 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:48,362 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:48,377 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:48,394 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:48,407 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:48,417 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:48,434 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:48,447 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:48,462 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:48,480 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:48,491 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:48,506 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:48,521 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:48,536 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:48,552 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:48,569 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:48,580 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:48,597 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:48,611 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:48,626 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:48,641 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:48,659 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:48,676 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:48,685 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:48,700 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:48,716 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:48,731 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:48,742 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:48,759 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:48,774 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:48,792 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:48,808 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:48,825 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:48,840 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:48,858 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:48,873 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:48,888 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:48,904 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:48,910 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:48,925 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:48,939 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:48,946 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:48,961 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:48,969 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:48,986 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:49,001 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:49,013 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:49,024 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:49,037 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:49,052 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:49,061 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:49,076 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:49,093 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:49,109 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:49,122 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:49,130 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:49,139 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:49,146 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:49,163 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:49,177 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:49,190 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:49,208 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:49,220 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:49,232 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:49,245 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:49,255 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:49,266 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:49,278 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:49,293 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:49,304 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:49,319 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:49,337 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:49,353 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:49,381 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:49,397 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:49,414 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:49,432 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:49,446 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:49,462 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:49,479 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:49,494 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:49,505 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:49,523 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:49,536 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:49,554 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:49,568 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:49,586 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:49,603 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:49,620 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:49,636 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:49,653 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:49,667 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:49,682 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:49,699 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:49,717 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:49,732 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:49,748 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:49,763 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:49,780 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:49,793 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:49,809 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:49,824 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:49,835 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:49,840 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:49,855 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:49,869 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:49,878 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:49,894 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:49,906 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:49,917 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:49,933 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:49,946 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:49,959 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:49,971 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:49,988 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:50,003 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:50,019 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:50,028 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:50,042 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:50,044 INFO L303 Elim1Store]: Index analysis took 1729 ms [2018-11-28 11:26:50,046 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 15 select indices, 15 select index equivalence classes, 120 disjoint index pairs (out of 105 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 146 treesize of output 1105 [2018-11-28 11:26:50,048 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-11-28 11:26:51,074 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-28 11:26:51,238 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-2 vars, End of recursive call: and 1 xjuncts. [2018-11-28 11:26:51,238 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 1 variables, input treesize:179, output treesize:175 [2018-11-28 11:26:51,665 WARN L180 SmtUtils]: Spent 164.00 ms on a formula simplification that was a NOOP. DAG size: 70 [2018-11-28 11:26:53,570 INFO L267 ElimStorePlain]: Start of recursive call 3: 1 dim-0 vars, End of recursive call: 1 dim-0 vars, and 1 xjuncts. [2018-11-28 11:26:53,579 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: 1 dim-0 vars, and 1 xjuncts. [2018-11-28 11:26:53,586 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-2 vars, End of recursive call: 1 dim-0 vars, and 1 xjuncts. [2018-11-28 11:26:53,586 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 1 variables, input treesize:42, output treesize:27 [2018-11-28 11:26:55,596 WARN L854 $PredicateComparison]: unable to prove that (exists ((v_DerPreprocessor_2 (_ BitVec 32))) (= |c_#memory_$Pointer$.offset| (store |c_old(#memory_$Pointer$.offset)| |c_ldv_kobject_init_internal_#in~kobj.base| (let ((.cse0 (bvadd |c_ldv_kobject_init_internal_#in~kobj.offset| (_ bv4 32)))) (store (store (store (select |c_old(#memory_$Pointer$.offset)| |c_ldv_kobject_init_internal_#in~kobj.base|) (bvadd |c_ldv_kobject_init_internal_#in~kobj.offset| (_ bv12 32)) v_DerPreprocessor_2) .cse0 .cse0) (bvadd |c_ldv_kobject_init_internal_#in~kobj.offset| (_ bv8 32)) .cse0))))) is different from true [2018-11-28 11:26:57,603 WARN L854 $PredicateComparison]: unable to prove that (exists ((v_DerPreprocessor_2 (_ BitVec 32))) (= (store |c_old(#memory_$Pointer$.offset)| |c_ldv_kobject_init_#in~kobj.base| (let ((.cse0 (bvadd |c_ldv_kobject_init_#in~kobj.offset| (_ bv4 32)))) (store (store (store (select |c_old(#memory_$Pointer$.offset)| |c_ldv_kobject_init_#in~kobj.base|) (bvadd |c_ldv_kobject_init_#in~kobj.offset| (_ bv12 32)) v_DerPreprocessor_2) .cse0 .cse0) (bvadd |c_ldv_kobject_init_#in~kobj.offset| (_ bv8 32)) .cse0))) |c_#memory_$Pointer$.offset|)) is different from true [2018-11-28 11:26:57,759 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:57,759 INFO L303 Elim1Store]: Index analysis took 153 ms [2018-11-28 11:26:57,760 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 170 treesize of output 158 [2018-11-28 11:26:57,881 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:57,938 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:57,985 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:58,035 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:58,093 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:58,141 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:58,193 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:58,252 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:58,303 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:58,355 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:58,407 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:58,457 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:58,506 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:58,559 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:58,616 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:58,670 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:58,727 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:58,776 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:58,825 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:58,878 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:58,931 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:58,983 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:59,030 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:59,081 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:59,137 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:59,187 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:59,226 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:59,282 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:59,338 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:59,401 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:59,460 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:59,517 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:59,575 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:59,629 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:59,671 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:59,724 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:59,776 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:59,831 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:59,884 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:59,938 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:26:59,989 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:00,042 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:00,096 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:00,151 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:00,187 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:00,239 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:00,287 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:00,337 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:00,387 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:00,438 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:00,483 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:00,533 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:00,588 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:00,639 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:00,693 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:00,743 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:00,792 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:00,845 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:00,899 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:00,955 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:01,004 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:01,056 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:01,218 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:01,268 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:01,323 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:01,380 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:01,437 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:01,494 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:01,547 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:01,601 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:01,652 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:01,701 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:01,752 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:01,817 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:01,879 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:01,939 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:01,994 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:02,042 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:02,100 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:02,156 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:02,217 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:02,269 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:02,322 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:02,368 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:02,420 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:02,470 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:02,522 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:02,577 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:02,627 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:02,679 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:02,723 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:02,767 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:02,817 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:02,874 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:02,925 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:02,972 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:03,031 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:03,087 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:03,144 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:03,194 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:03,247 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:03,298 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:03,346 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:03,400 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:03,447 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:03,499 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:03,551 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:03,600 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:03,757 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:03,911 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:03,957 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:04,006 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:04,156 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:04,209 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:04,261 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:04,307 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:04,357 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:04,409 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:04,463 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:04,508 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:04,557 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:04,610 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:04,663 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:04,715 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:04,769 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:04,821 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:04,873 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:04,924 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:04,976 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:05,029 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:05,083 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:05,133 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:05,181 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:05,182 INFO L683 Elim1Store]: detected equality via solver [2018-11-28 11:27:06,906 INFO L303 Elim1Store]: Index analysis took 9142 ms [2018-11-28 11:27:07,134 INFO L478 Elim1Store]: Elim1 applied some preprocessing eliminated variable of array dimension 1, 1 stores, 17 select indices, 17 select index equivalence classes, 134 disjoint index pairs (out of 136 index pairs), introduced 2 new quantified variables, introduced 2 case distinctions, treesize of input 158 treesize of output 1177 [2018-11-28 11:27:07,276 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:07,305 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:07,329 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:07,360 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:07,386 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:07,411 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:07,438 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:07,467 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:07,493 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:07,523 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:07,544 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:07,565 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:07,588 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:07,611 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:07,635 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:07,660 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:07,685 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:07,710 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:07,736 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:07,761 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:07,788 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:07,814 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:07,838 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:07,861 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:07,887 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:07,912 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:07,937 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:07,959 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:07,981 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:08,008 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:08,032 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:08,055 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:08,081 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:08,104 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:08,128 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:08,150 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:08,176 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:08,200 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:08,224 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:08,248 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:08,274 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:08,297 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:08,317 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:08,338 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:08,358 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:08,382 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:08,406 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:08,431 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:08,454 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:08,479 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:08,506 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:08,534 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:08,556 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:08,580 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:08,605 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:08,628 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:08,653 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:08,681 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:08,718 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:08,740 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:08,776 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:08,799 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:08,824 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:08,848 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:08,870 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:08,890 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:08,915 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:08,937 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:08,961 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:08,985 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:09,009 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:09,032 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:09,053 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:09,075 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:09,100 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:09,125 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:09,145 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:09,164 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:09,189 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:09,211 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:09,235 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:09,259 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:09,284 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:09,308 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:09,333 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:09,361 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:09,381 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:09,403 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:09,427 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:09,452 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:09,476 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:09,499 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:09,523 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:09,549 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:09,569 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:09,594 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:09,611 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:09,635 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:09,658 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:09,680 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:09,706 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:09,730 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:09,754 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:09,778 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:09,804 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:09,828 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:09,852 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:09,869 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:09,889 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:09,913 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:09,933 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:09,956 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:09,978 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:10,001 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:10,024 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:10,048 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:10,069 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:10,093 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:10,117 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:10,137 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:10,161 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:10,206 INFO L303 Elim1Store]: Index analysis took 3020 ms [2018-11-28 11:27:10,208 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 16 select indices, 16 select index equivalence classes, 121 disjoint index pairs (out of 120 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 1092 treesize of output 1092 [2018-11-28 11:27:10,975 WARN L180 SmtUtils]: Spent 761.00 ms on a formula simplification. DAG size of input: 80 DAG size of output: 77 [2018-11-28 11:27:11,000 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:11,009 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:11,019 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:11,026 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:11,036 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:11,045 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:11,054 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:11,057 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:11,063 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:11,071 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:11,080 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:11,090 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:11,099 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:11,107 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:11,116 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:11,125 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:11,133 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:11,141 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:11,149 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:11,157 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:11,165 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:11,174 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:11,182 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:11,190 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:11,197 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:11,204 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:11,213 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:11,221 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:11,227 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:11,234 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:11,242 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:11,250 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:11,258 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:11,266 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:11,274 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:11,281 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:11,289 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:11,296 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:11,303 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:11,309 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:11,317 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:11,324 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:11,332 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:11,340 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:11,348 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:11,356 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:11,364 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:11,370 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:11,379 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:11,387 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:11,395 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:11,404 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:11,412 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:11,420 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:11,426 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:11,435 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:11,443 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:11,450 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:11,457 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:11,465 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:11,473 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:11,481 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:11,489 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:11,497 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:11,505 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:11,513 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:11,521 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:11,529 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:11,537 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:11,544 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:11,552 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:11,559 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:11,567 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:11,575 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:11,582 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:11,591 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:11,598 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:11,606 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:11,614 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:11,621 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:11,629 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:11,636 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:11,642 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:11,649 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:11,655 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:11,664 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:11,670 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:11,679 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:11,687 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:11,693 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:11,701 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:11,710 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:11,718 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:11,726 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:11,734 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:11,743 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:11,750 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:11,758 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:11,765 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:11,771 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:11,776 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:11,780 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:11,788 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:11,796 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:11,804 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:11,812 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:11,841 INFO L303 Elim1Store]: Index analysis took 864 ms [2018-11-28 11:27:11,843 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 16 select indices, 16 select index equivalence classes, 121 disjoint index pairs (out of 120 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 137 treesize of output 1096 [2018-11-28 11:27:11,844 INFO L267 ElimStorePlain]: Start of recursive call 5: End of recursive call: and 1 xjuncts. [2018-11-28 11:27:12,238 INFO L267 ElimStorePlain]: Start of recursive call 4: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-28 11:27:13,623 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:13,654 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:13,681 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:13,712 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:13,739 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:13,767 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:13,792 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:13,822 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:13,851 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:13,878 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:13,906 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:13,936 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:13,962 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:13,989 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:14,018 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:14,046 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:14,076 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:14,104 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:14,131 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:14,154 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:14,183 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:14,207 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:14,230 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:14,257 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:14,286 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:14,313 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:14,343 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:14,367 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:14,378 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:14,406 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:14,435 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:14,463 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:14,492 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:14,521 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:14,546 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:14,576 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:14,603 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:14,627 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:14,649 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:14,675 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:14,705 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:14,730 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:14,758 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:14,787 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:14,814 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:14,838 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:14,866 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:14,894 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:14,921 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:14,949 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:14,976 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:15,001 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:15,027 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:15,054 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:15,075 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:15,094 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:15,117 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:15,143 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:15,172 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:15,201 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:15,224 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:15,253 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:15,334 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:15,363 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:15,389 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:15,413 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:15,442 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:15,468 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:15,496 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:15,522 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:15,547 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:15,571 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:15,595 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:15,622 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:15,650 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:15,676 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:15,703 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:15,731 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:15,760 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:15,786 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:15,815 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:15,845 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:15,873 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:15,900 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:15,928 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:15,956 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:15,983 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:16,010 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:16,037 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:16,064 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:16,089 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:16,113 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:16,139 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:16,158 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:16,185 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:16,212 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:16,237 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:16,264 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:16,289 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:16,309 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:16,336 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:16,360 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:16,391 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:16,422 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:16,450 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:16,478 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:16,518 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:16,547 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:16,570 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:16,653 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:16,679 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:16,700 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:16,725 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:16,802 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:16,831 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:16,858 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:16,885 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:16,912 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:16,940 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:16,968 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:16,995 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:17,021 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:17,050 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:17,076 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:17,100 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:17,127 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:17,151 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:17,175 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:17,203 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:17,231 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:17,258 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:17,285 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:17,312 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:17,341 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:18,170 INFO L303 Elim1Store]: Index analysis took 4604 ms [2018-11-28 11:27:18,255 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 17 select indices, 17 select index equivalence classes, 134 disjoint index pairs (out of 136 index pairs), introduced 1 new quantified variables, introduced 2 case distinctions, treesize of input 155 treesize of output 1164 [2018-11-28 11:27:20,082 WARN L180 SmtUtils]: Spent 1.82 s on a formula simplification. DAG size of input: 166 DAG size of output: 119 [2018-11-28 11:27:20,101 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:20,110 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:20,119 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:20,126 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:20,134 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:20,143 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:20,153 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:20,162 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:20,171 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:20,180 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:20,189 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:20,198 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:20,207 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:20,217 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:20,224 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:20,234 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:20,242 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:20,251 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:20,261 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:20,270 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:20,279 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:20,288 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:20,297 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:20,306 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:20,314 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:20,322 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:20,329 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:20,338 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:20,346 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:20,355 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:20,365 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:20,375 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:20,382 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:20,391 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:20,401 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:20,411 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:20,421 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:20,430 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:20,439 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:20,449 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:20,457 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:20,466 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:20,475 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:20,483 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:20,492 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:20,501 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:20,510 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:20,518 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:20,527 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:20,535 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:20,544 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:20,552 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:20,559 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:20,566 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:20,575 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:20,584 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:20,592 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:20,602 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:20,609 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:20,619 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:20,628 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:20,635 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:20,643 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:20,653 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:20,659 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:20,669 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:20,677 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:20,686 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:20,696 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:20,704 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:20,712 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:20,721 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:20,731 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:20,739 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:20,747 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:20,755 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:20,763 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:20,772 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:20,780 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:20,789 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:20,798 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:20,808 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:20,817 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:20,825 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:20,834 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:20,843 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:20,851 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:20,857 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:20,865 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:20,874 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:20,882 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:20,890 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:20,900 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:20,908 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:20,917 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:20,926 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:20,934 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:20,944 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:20,951 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:20,959 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:20,969 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:20,978 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:20,986 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:20,994 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:21,002 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:21,011 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:21,019 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:21,027 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:21,036 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:21,044 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:21,052 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:21,061 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:21,070 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:21,080 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:21,090 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:21,099 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:21,105 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:21,113 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:21,122 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:21,130 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:21,345 INFO L303 Elim1Store]: Index analysis took 1261 ms [2018-11-28 11:27:21,347 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 16 select indices, 16 select index equivalence classes, 120 disjoint index pairs (out of 120 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 133 treesize of output 1092 [2018-11-28 11:27:21,348 INFO L267 ElimStorePlain]: Start of recursive call 7: End of recursive call: and 1 xjuncts. [2018-11-28 11:27:21,925 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:21,927 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:21,935 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:21,944 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:21,953 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:21,962 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:21,971 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:21,979 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:21,986 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:21,995 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:22,003 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:22,010 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:22,018 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:22,026 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:22,033 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:22,040 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:22,049 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:22,058 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:22,066 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:22,076 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:22,085 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:22,093 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:22,102 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:22,112 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:22,121 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:22,131 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:22,140 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:22,148 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:22,157 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:22,165 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:22,173 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:22,182 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:22,191 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:22,201 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:22,210 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:22,215 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:22,224 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:22,233 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:22,242 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:22,251 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:22,261 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:22,269 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:22,275 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:22,281 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:22,288 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:22,297 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:22,303 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:22,311 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:22,320 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:22,329 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:22,339 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:22,348 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:22,357 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:22,366 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:22,374 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:22,381 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:22,390 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:22,399 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:22,406 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:22,415 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:22,422 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:22,429 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:22,437 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:22,447 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:22,457 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:22,465 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:22,474 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:22,484 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:22,493 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:22,503 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:22,512 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:22,522 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:22,531 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:22,539 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:22,548 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:22,557 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:22,566 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:22,576 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:22,583 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:22,590 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:22,599 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:22,609 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:22,617 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:22,626 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:22,635 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:22,644 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:22,654 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:22,662 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:22,671 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:22,680 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:22,689 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:22,698 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:22,706 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:22,715 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:22,724 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:22,730 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:22,740 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:22,747 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:22,755 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:22,762 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:22,771 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:22,780 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:22,790 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:22,799 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:22,805 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:22,814 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:22,823 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:22,832 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:22,842 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:22,851 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:22,859 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:22,869 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:22,877 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:22,886 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:22,895 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:22,903 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:22,911 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:22,919 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:22,928 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:22,936 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:23,161 INFO L303 Elim1Store]: Index analysis took 1254 ms [2018-11-28 11:27:23,163 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 16 select indices, 16 select index equivalence classes, 120 disjoint index pairs (out of 120 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 128 treesize of output 1062 [2018-11-28 11:27:23,165 INFO L267 ElimStorePlain]: Start of recursive call 8: End of recursive call: and 1 xjuncts. [2018-11-28 11:27:23,634 INFO L267 ElimStorePlain]: Start of recursive call 6: 2 dim-1 vars, End of recursive call: and 2 xjuncts. [2018-11-28 11:27:23,770 INFO L267 ElimStorePlain]: Start of recursive call 3: 1 dim-0 vars, 2 dim-1 vars, End of recursive call: and 3 xjuncts. [2018-11-28 11:27:23,836 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-28 11:27:23,886 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-0 vars, 1 dim-2 vars, End of recursive call: and 1 xjuncts. [2018-11-28 11:27:23,886 INFO L202 ElimStorePlain]: Needed 8 recursive calls to eliminate 2 variables, input treesize:173, output treesize:141 [2018-11-28 11:27:27,128 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 157 treesize of output 124 [2018-11-28 11:27:27,133 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:27,134 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:27,135 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:27,137 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:27,138 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:27,139 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:27,140 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:27,141 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:27,142 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:27,143 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:27,144 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:27,145 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:27,146 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:27,147 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:27,148 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:27,148 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:27,149 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:27,150 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:27,151 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:27,152 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:27,153 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:27,154 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:27,154 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:27,155 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:27,156 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:27,157 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:27,157 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:27,158 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:27,159 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:27,160 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:27,161 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:27,162 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:27,163 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:27,164 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:27,165 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:27,166 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:27,167 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:27,168 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:27,169 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:27,169 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:27,170 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:27,171 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:27,172 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:27,173 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:27,174 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:27,175 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:27,176 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:27,177 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:27,178 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:27,178 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:27,179 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:27,180 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:27,181 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:27,182 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:27,183 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:27,184 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:27,185 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:27,186 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:27,186 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:27,187 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:27,188 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:27,189 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:27,190 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:27,191 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:27,192 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:27,193 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:27,194 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:27,194 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:27,195 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:27,196 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:27,197 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:27,198 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:27,198 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:27,199 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:27,200 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:27,201 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:27,202 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:27,203 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:27,204 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:27,204 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:27,205 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:27,206 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:27,207 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:27,208 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:27,209 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:27,210 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:27,211 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:27,212 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:27,213 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:27,213 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:27,214 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:27,215 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:27,217 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:27,217 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:27,218 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:27,219 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:27,220 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:27,221 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:27,222 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:27,223 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:27,224 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:27,224 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:27,225 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:27,226 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:27,227 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:27,228 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:27,229 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:27,230 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:27,231 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:27,232 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:27,233 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:27,234 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:27,235 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:27,235 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:27,236 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:27,237 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:27,238 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:27,239 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:27,240 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:27,241 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:27,255 INFO L303 Elim1Store]: Index analysis took 125 ms [2018-11-28 11:27:27,258 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 15 select indices, 15 select index equivalence classes, 120 disjoint index pairs (out of 105 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 124 treesize of output 1068 [2018-11-28 11:27:27,260 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-11-28 11:27:27,602 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-28 11:27:27,650 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-2 vars, End of recursive call: and 1 xjuncts. [2018-11-28 11:27:27,650 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 1 variables, input treesize:160, output treesize:141 [2018-11-28 11:27:30,282 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 125 treesize of output 92 [2018-11-28 11:27:30,502 INFO L303 Elim1Store]: Index analysis took 217 ms [2018-11-28 11:27:30,503 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 15 select indices, 15 select index equivalence classes, 120 disjoint index pairs (out of 105 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 92 treesize of output 110 [2018-11-28 11:27:30,504 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-11-28 11:27:30,533 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-28 11:27:30,559 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-2 vars, End of recursive call: and 1 xjuncts. [2018-11-28 11:27:30,559 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 1 variables, input treesize:125, output treesize:110 [2018-11-28 11:27:32,609 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 113 treesize of output 81 [2018-11-28 11:27:32,685 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 16 select indices, 16 select index equivalence classes, 105 disjoint index pairs (out of 120 index pairs), introduced 0 new quantified variables, introduced 15 case distinctions, treesize of input 81 treesize of output 121 [2018-11-28 11:27:32,686 WARN L138 XnfTransformerHelper]: expecting exponential blowup for input size 15 [2018-11-28 11:27:32,687 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 4 xjuncts. [2018-11-28 11:27:32,740 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 3 xjuncts. [2018-11-28 11:27:32,790 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-0 vars, 1 dim-2 vars, End of recursive call: and 3 xjuncts. [2018-11-28 11:27:32,790 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 2 variables, input treesize:113, output treesize:130 [2018-11-28 11:27:33,688 INFO L134 CoverageAnalysis]: Checked inductivity of 136 backedges. 0 proven. 136 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-28 11:27:33,688 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-11-28 11:27:35,718 INFO L267 ElimStorePlain]: Start of recursive call 3: 1 dim-0 vars, End of recursive call: 1 dim-0 vars, and 1 xjuncts. [2018-11-28 11:27:35,720 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: 1 dim-0 vars, and 1 xjuncts. [2018-11-28 11:27:35,721 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-2 vars, End of recursive call: 1 dim-0 vars, and 1 xjuncts. [2018-11-28 11:27:35,721 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 1 variables, input treesize:24, output treesize:10 [2018-11-28 11:27:36,007 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-28 11:27:36,007 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FPBP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_2ca7a644-5b0a-4f3d-9179-f30a2c52dfce/bin-2019/uautomizer/z3 Starting monitored process 28 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 28 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-28 11:27:36,014 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-28 11:27:36,073 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-28 11:27:36,081 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-28 11:27:36,806 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 11 treesize of output 8 [2018-11-28 11:27:36,807 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 8 treesize of output 7 [2018-11-28 11:27:36,807 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-11-28 11:27:36,809 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-28 11:27:36,812 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-2 vars, End of recursive call: and 1 xjuncts. [2018-11-28 11:27:36,812 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 1 variables, input treesize:15, output treesize:11 [2018-11-28 11:27:38,151 INFO L267 ElimStorePlain]: Start of recursive call 3: 1 dim-0 vars, End of recursive call: 1 dim-0 vars, and 1 xjuncts. [2018-11-28 11:27:38,160 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: 1 dim-0 vars, and 1 xjuncts. [2018-11-28 11:27:38,178 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-2 vars, End of recursive call: 1 dim-0 vars, and 1 xjuncts. [2018-11-28 11:27:38,178 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 1 variables, input treesize:50, output treesize:38 [2018-11-28 11:27:40,765 WARN L180 SmtUtils]: Spent 2.03 s on a formula simplification that was a NOOP. DAG size: 22 [2018-11-28 11:27:40,775 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 36 treesize of output 31 [2018-11-28 11:27:40,779 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:40,781 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 31 treesize of output 41 [2018-11-28 11:27:40,785 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:40,787 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:40,788 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:40,793 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 2 select indices, 2 select index equivalence classes, 3 disjoint index pairs (out of 1 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 33 treesize of output 45 [2018-11-28 11:27:40,793 INFO L267 ElimStorePlain]: Start of recursive call 4: End of recursive call: and 1 xjuncts. [2018-11-28 11:27:40,803 INFO L267 ElimStorePlain]: Start of recursive call 3: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-28 11:27:40,809 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-28 11:27:40,828 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-0 vars, 1 dim-2 vars, End of recursive call: and 1 xjuncts. [2018-11-28 11:27:40,828 INFO L202 ElimStorePlain]: Needed 4 recursive calls to eliminate 2 variables, input treesize:58, output treesize:22 [2018-11-28 11:27:47,455 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:47,456 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 31 treesize of output 38 [2018-11-28 11:27:47,459 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 11:27:47,460 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 38 treesize of output 9 [2018-11-28 11:27:47,460 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-11-28 11:27:47,465 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-28 11:27:47,470 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-2 vars, End of recursive call: and 1 xjuncts. [2018-11-28 11:27:47,470 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 1 variables, input treesize:39, output treesize:13 [2018-11-28 11:27:51,113 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 19 treesize of output 15 [2018-11-28 11:27:51,115 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 5 [2018-11-28 11:27:51,115 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-11-28 11:27:51,116 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-28 11:27:51,117 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-0 vars, 1 dim-2 vars, End of recursive call: and 1 xjuncts. [2018-11-28 11:27:51,117 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 2 variables, input treesize:19, output treesize:5 [2018-11-28 11:27:51,397 INFO L134 CoverageAnalysis]: Checked inductivity of 136 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 136 trivial. 0 not checked. [2018-11-28 11:27:51,397 INFO L312 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2018-11-28 11:27:51,414 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 1 imperfect interpolant sequences. [2018-11-28 11:27:51,414 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [40] imperfect sequences [61] total 97 [2018-11-28 11:27:51,414 INFO L459 AbstractCegarLoop]: Interpolant automaton has 97 states [2018-11-28 11:27:51,414 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 97 interpolants. [2018-11-28 11:27:51,416 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=295, Invalid=10630, Unknown=3, NotChecked=414, Total=11342 [2018-11-28 11:27:51,416 INFO L87 Difference]: Start difference. First operand 134 states and 136 transitions. Second operand 97 states. [2018-11-28 11:28:49,487 WARN L180 SmtUtils]: Spent 2.04 s on a formula simplification that was a NOOP. DAG size: 29 [2018-11-28 11:28:55,541 WARN L180 SmtUtils]: Spent 4.10 s on a formula simplification. DAG size of input: 38 DAG size of output: 31 [2018-11-28 11:28:59,357 WARN L180 SmtUtils]: Spent 2.04 s on a formula simplification that was a NOOP. DAG size: 32 [2018-11-28 11:29:06,218 WARN L180 SmtUtils]: Spent 122.00 ms on a formula simplification that was a NOOP. DAG size: 128 [2018-11-28 11:29:32,561 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-28 11:29:32,561 INFO L93 Difference]: Finished difference Result 112 states and 112 transitions. [2018-11-28 11:29:32,562 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 61 states. [2018-11-28 11:29:32,562 INFO L78 Accepts]: Start accepts. Automaton has 97 states. Word has length 112 [2018-11-28 11:29:32,562 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-28 11:29:32,562 INFO L225 Difference]: With dead ends: 112 [2018-11-28 11:29:32,563 INFO L226 Difference]: Without dead ends: 112 [2018-11-28 11:29:32,565 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 278 GetRequests, 131 SyntacticMatches, 1 SemanticMatches, 146 ConstructedPredicates, 2 IntricatePredicates, 0 DeprecatedPredicates, 3132 ImplicationChecksByTransitivity, 56.2s TimeCoverageRelationStatistics Valid=677, Invalid=20498, Unknown=3, NotChecked=578, Total=21756 [2018-11-28 11:29:32,565 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 112 states. [2018-11-28 11:29:32,567 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 112 to 112. [2018-11-28 11:29:32,567 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 112 states. [2018-11-28 11:29:32,567 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 112 states to 112 states and 112 transitions. [2018-11-28 11:29:32,567 INFO L78 Accepts]: Start accepts. Automaton has 112 states and 112 transitions. Word has length 112 [2018-11-28 11:29:32,568 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-28 11:29:32,568 INFO L480 AbstractCegarLoop]: Abstraction has 112 states and 112 transitions. [2018-11-28 11:29:32,568 INFO L481 AbstractCegarLoop]: Interpolant automaton has 97 states. [2018-11-28 11:29:32,568 INFO L276 IsEmpty]: Start isEmpty. Operand 112 states and 112 transitions. [2018-11-28 11:29:32,569 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 112 [2018-11-28 11:29:32,569 INFO L394 BasicCegarLoop]: Found error trace [2018-11-28 11:29:32,569 INFO L402 BasicCegarLoop]: trace histogram [16, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-28 11:29:32,569 INFO L423 AbstractCegarLoop]: === Iteration 27 === [ldv_kref_initErr0REQUIRES_VIOLATION, ldv_kref_initErr1REQUIRES_VIOLATION, ldv_list_addErr1REQUIRES_VIOLATION, ldv_list_addErr0REQUIRES_VIOLATION, ldv_kobject_createErr1REQUIRES_VIOLATION, ldv_kobject_createErr0REQUIRES_VIOLATION, ldv_destroy_msgsErr5REQUIRES_VIOLATION, ldv_destroy_msgsErr0REQUIRES_VIOLATION, ldv_destroy_msgsErr4REQUIRES_VIOLATION, ldv_destroy_msgsErr2REQUIRES_VIOLATION, ldv_destroy_msgsErr3REQUIRES_VIOLATION, ldv_destroy_msgsErr1REQUIRES_VIOLATION, ldv_msg_fillErr1REQUIRES_VIOLATION, ldv_msg_fillErr3REQUIRES_VIOLATION, ldv_msg_fillErr2REQUIRES_VIOLATION, ldv_msg_fillErr4REQUIRES_VIOLATION, ldv_msg_fillErr0REQUIRES_VIOLATION, ldv_msg_fillErr5REQUIRES_VIOLATION, ldv_atomic_add_returnErr2REQUIRES_VIOLATION, ldv_atomic_add_returnErr3REQUIRES_VIOLATION, ldv_atomic_add_returnErr1REQUIRES_VIOLATION, ldv_atomic_add_returnErr0REQUIRES_VIOLATION, __ldv_list_delErr0REQUIRES_VIOLATION, __ldv_list_delErr3REQUIRES_VIOLATION, __ldv_list_delErr2REQUIRES_VIOLATION, __ldv_list_delErr1REQUIRES_VIOLATION, ldv_kobject_cleanupErr2ASSERT_VIOLATIONMEMORY_FREE, ldv_kobject_cleanupErr0REQUIRES_VIOLATION, ldv_kobject_cleanupErr4ASSERT_VIOLATIONMEMORY_FREE, ldv_kobject_cleanupErr3ASSERT_VIOLATIONMEMORY_FREE, ldv_kobject_cleanupErr5ASSERT_VIOLATIONMEMORY_FREE, ldv_kobject_cleanupErr1REQUIRES_VIOLATION, ldv_msg_freeErr3ASSERT_VIOLATIONMEMORY_FREE, ldv_msg_freeErr5ASSERT_VIOLATIONMEMORY_FREE, ldv_msg_freeErr0REQUIRES_VIOLATION, ldv_msg_freeErr2ASSERT_VIOLATIONMEMORY_FREE, ldv_msg_freeErr1REQUIRES_VIOLATION, ldv_msg_freeErr4ASSERT_VIOLATIONMEMORY_FREE, mainErr0ENSURES_VIOLATIONMEMORY_LEAK, LDV_INIT_LIST_HEADErr3REQUIRES_VIOLATION, LDV_INIT_LIST_HEADErr2REQUIRES_VIOLATION, LDV_INIT_LIST_HEADErr1REQUIRES_VIOLATION, LDV_INIT_LIST_HEADErr0REQUIRES_VIOLATION, ldv_list_delErr2REQUIRES_VIOLATION, ldv_list_delErr3REQUIRES_VIOLATION, ldv_list_delErr1REQUIRES_VIOLATION, ldv_list_delErr0REQUIRES_VIOLATION, __ldv_list_addErr0REQUIRES_VIOLATION, __ldv_list_addErr5REQUIRES_VIOLATION, __ldv_list_addErr4REQUIRES_VIOLATION, __ldv_list_addErr3REQUIRES_VIOLATION, __ldv_list_addErr2REQUIRES_VIOLATION, __ldv_list_addErr7REQUIRES_VIOLATION, __ldv_list_addErr1REQUIRES_VIOLATION, __ldv_list_addErr6REQUIRES_VIOLATION, ldv_dev_set_drvdataErr1REQUIRES_VIOLATION, ldv_dev_set_drvdataErr0REQUIRES_VIOLATION, ldv_atomic_sub_returnErr2REQUIRES_VIOLATION, ldv_atomic_sub_returnErr3REQUIRES_VIOLATION, ldv_atomic_sub_returnErr1REQUIRES_VIOLATION, ldv_atomic_sub_returnErr0REQUIRES_VIOLATION, ldv_list_add_tailErr0REQUIRES_VIOLATION, ldv_list_add_tailErr1REQUIRES_VIOLATION, ldv_dev_get_drvdataErr1REQUIRES_VIOLATION, ldv_dev_get_drvdataErr0REQUIRES_VIOLATION, ldv_msg_allocErr0REQUIRES_VIOLATION, ldv_msg_allocErr1REQUIRES_VIOLATION]=== [2018-11-28 11:29:32,569 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-28 11:29:32,569 INFO L82 PathProgramCache]: Analyzing trace with hash 425919928, now seen corresponding path program 1 times [2018-11-28 11:29:32,570 INFO L223 ckRefinementStrategy]: Switched to mode CVC4_FPBP [2018-11-28 11:29:32,570 INFO L69 tionRefinementEngine]: Using refinement strategy WolfRefinementStrategy No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_2ca7a644-5b0a-4f3d-9179-f30a2c52dfce/bin-2019/uautomizer/cvc4 Starting monitored process 29 with cvc4 --incremental --print-success --lang smt --rewrite-divk (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 29 with cvc4 --incremental --print-success --lang smt --rewrite-divk [2018-11-28 11:29:32,590 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-28 11:29:37,535 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-28 11:29:42,627 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-28 11:29:42,730 INFO L469 BasicCegarLoop]: Counterexample might be feasible [2018-11-28 11:29:42,745 WARN L416 cessorBacktranslator]: Generated EnsuresSpecification free ensures #res.base == #ptr.base && #res.offset == #ptr.offset; is not ensure(true) [2018-11-28 11:29:42,754 WARN L416 cessorBacktranslator]: Generated EnsuresSpecification ensures #valid == old(#valid); is not ensure(true) [2018-11-28 11:29:42,761 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType STRUCT~~ldv_list_head?next~*ldv_list_head?prev~*ldv_list_head# [2018-11-28 11:29:42,762 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType STRUCT~~ldv_list_head?next~*ldv_list_head?prev~*ldv_list_head# [2018-11-28 11:29:42,778 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction CFG 28.11 11:29:42 BoogieIcfgContainer [2018-11-28 11:29:42,778 INFO L132 PluginConnector]: ------------------------ END TraceAbstraction---------------------------- [2018-11-28 11:29:42,778 INFO L113 PluginConnector]: ------------------------Witness Printer---------------------------- [2018-11-28 11:29:42,778 INFO L271 PluginConnector]: Initializing Witness Printer... [2018-11-28 11:29:42,778 INFO L276 PluginConnector]: Witness Printer initialized [2018-11-28 11:29:42,779 INFO L185 PluginConnector]: Executing the observer RCFGCatcher from plugin Witness Printer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 28.11 11:26:15" (3/4) ... [2018-11-28 11:29:42,782 INFO L147 WitnessPrinter]: No result that supports witness generation found [2018-11-28 11:29:42,782 INFO L132 PluginConnector]: ------------------------ END Witness Printer---------------------------- [2018-11-28 11:29:42,783 INFO L168 Benchmark]: Toolchain (without parser) took 209058.43 ms. Allocated memory was 1.0 GB in the beginning and 1.4 GB in the end (delta: 354.9 MB). Free memory was 939.3 MB in the beginning and 1.0 GB in the end (delta: -106.6 MB). Peak memory consumption was 248.3 MB. Max. memory is 11.5 GB. [2018-11-28 11:29:42,783 INFO L168 Benchmark]: CDTParser took 0.17 ms. Allocated memory is still 1.0 GB. Free memory is still 972.9 MB. There was no memory consumed. Max. memory is 11.5 GB. [2018-11-28 11:29:42,783 INFO L168 Benchmark]: CACSL2BoogieTranslator took 445.42 ms. Allocated memory was 1.0 GB in the beginning and 1.2 GB in the end (delta: 159.9 MB). Free memory was 939.3 MB in the beginning and 1.1 GB in the end (delta: -187.6 MB). Peak memory consumption was 31.5 MB. Max. memory is 11.5 GB. [2018-11-28 11:29:42,784 INFO L168 Benchmark]: Boogie Preprocessor took 47.66 ms. Allocated memory is still 1.2 GB. Free memory is still 1.1 GB. There was no memory consumed. Max. memory is 11.5 GB. [2018-11-28 11:29:42,784 INFO L168 Benchmark]: RCFGBuilder took 1076.46 ms. Allocated memory is still 1.2 GB. Free memory was 1.1 GB in the beginning and 1.0 GB in the end (delta: 106.2 MB). Peak memory consumption was 106.2 MB. Max. memory is 11.5 GB. [2018-11-28 11:29:42,784 INFO L168 Benchmark]: TraceAbstraction took 207481.69 ms. Allocated memory was 1.2 GB in the beginning and 1.4 GB in the end (delta: 195.0 MB). Free memory was 1.0 GB in the beginning and 1.0 GB in the end (delta: -25.2 MB). Peak memory consumption was 169.8 MB. Max. memory is 11.5 GB. [2018-11-28 11:29:42,784 INFO L168 Benchmark]: Witness Printer took 4.01 ms. Allocated memory is still 1.4 GB. Free memory is still 1.0 GB. There was no memory consumed. Max. memory is 11.5 GB. [2018-11-28 11:29:42,785 INFO L336 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.17 ms. Allocated memory is still 1.0 GB. Free memory is still 972.9 MB. There was no memory consumed. Max. memory is 11.5 GB. * CACSL2BoogieTranslator took 445.42 ms. Allocated memory was 1.0 GB in the beginning and 1.2 GB in the end (delta: 159.9 MB). Free memory was 939.3 MB in the beginning and 1.1 GB in the end (delta: -187.6 MB). Peak memory consumption was 31.5 MB. Max. memory is 11.5 GB. * Boogie Preprocessor took 47.66 ms. Allocated memory is still 1.2 GB. Free memory is still 1.1 GB. There was no memory consumed. Max. memory is 11.5 GB. * RCFGBuilder took 1076.46 ms. Allocated memory is still 1.2 GB. Free memory was 1.1 GB in the beginning and 1.0 GB in the end (delta: 106.2 MB). Peak memory consumption was 106.2 MB. Max. memory is 11.5 GB. * TraceAbstraction took 207481.69 ms. Allocated memory was 1.2 GB in the beginning and 1.4 GB in the end (delta: 195.0 MB). Free memory was 1.0 GB in the beginning and 1.0 GB in the end (delta: -25.2 MB). Peak memory consumption was 169.8 MB. Max. memory is 11.5 GB. * Witness Printer took 4.01 ms. Allocated memory is still 1.4 GB. Free memory is still 1.0 GB. There was no memory consumed. Max. memory is 11.5 GB. * Results from de.uni_freiburg.informatik.ultimate.boogie.preprocessor: - GenericResult: Unfinished Backtranslation Generated EnsuresSpecification free ensures #res.base == #ptr.base && #res.offset == #ptr.offset; is not ensure(true) - GenericResult: Unfinished Backtranslation Generated EnsuresSpecification ensures #valid == old(#valid); is not ensure(true) * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType STRUCT~~ldv_list_head?next~*ldv_list_head?prev~*ldv_list_head# - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType STRUCT~~ldv_list_head?next~*ldv_list_head?prev~*ldv_list_head# * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - UnprovableResult [Line: 1443]: Unable to prove that all allocated memory was freed Unable to prove that all allocated memory was freed Reason: overapproximation of memtrack at line 1443. Possible FailurePath: [L1135] struct ldv_list_head ldv_global_msg_list = { &(ldv_global_msg_list), &(ldv_global_msg_list) }; VAL [\old(ldv_global_msg_list)=null, \old(ldv_global_msg_list)=null, ldv_global_msg_list={-1:0}] [L1444] CALL entry_point() VAL [ldv_global_msg_list={-1:0}] [L1436] struct ldv_kobject *kobj; VAL [ldv_global_msg_list={-1:0}] [L1437] CALL, EXPR ldv_kobject_create() VAL [ldv_global_msg_list={-1:0}] [L1406] struct ldv_kobject *kobj; VAL [ldv_global_msg_list={-1:0}] [L1408] CALL, EXPR ldv_malloc(sizeof(*kobj)) VAL [\old(size)=16, ldv_global_msg_list={-1:0}] [L1073] COND TRUE __VERIFIER_nondet_int() [L1074] return malloc(size); VAL [\old(size)=16, \result={1082401:0}, ldv_global_msg_list={-1:0}, malloc(size)={1082401:0}, size=16] [L1408] RET, EXPR ldv_malloc(sizeof(*kobj)) VAL [ldv_global_msg_list={-1:0}, ldv_malloc(sizeof(*kobj))={1082401:0}] [L1408] kobj = ldv_malloc(sizeof(*kobj)) [L1409] COND FALSE !(!kobj) VAL [kobj={1082401:0}, ldv_global_msg_list={-1:0}] [L1411] FCALL memset(kobj, 0, sizeof(*kobj)) VAL [kobj={1082401:0}, ldv_global_msg_list={-1:0}, memset(kobj, 0, sizeof(*kobj))={1082401:0}] [L1413] CALL ldv_kobject_init(kobj) VAL [kobj={1082401:0}, ldv_global_msg_list={-1:0}] [L1394] COND FALSE !(!kobj) VAL [kobj={1082401:0}, kobj={1082401:0}, ldv_global_msg_list={-1:0}] [L1398] CALL ldv_kobject_init_internal(kobj) VAL [kobj={1082401:0}, ldv_global_msg_list={-1:0}] [L1380] COND FALSE !(!kobj) VAL [kobj={1082401:0}, kobj={1082401:0}, ldv_global_msg_list={-1:0}] [L1382] CALL ldv_kref_init(&kobj->kref) VAL [kref={1082401:12}, ldv_global_msg_list={-1:0}] [L1294] ((&kref->refcount)->counter) = (1) VAL [kref={1082401:12}, kref={1082401:12}, ldv_global_msg_list={-1:0}] [L1382] RET ldv_kref_init(&kobj->kref) VAL [kobj={1082401:0}, kobj={1082401:0}, ldv_global_msg_list={-1:0}] [L1383] CALL LDV_INIT_LIST_HEAD(&kobj->entry) VAL [ldv_global_msg_list={-1:0}, list={1082401:4}] [L1099] list->next = list VAL [ldv_global_msg_list={-1:0}, list={1082401:4}, list={1082401:4}] [L1100] list->prev = list VAL [ldv_global_msg_list={-1:0}, list={1082401:4}, list={1082401:4}] [L1383] RET LDV_INIT_LIST_HEAD(&kobj->entry) VAL [kobj={1082401:0}, kobj={1082401:0}, ldv_global_msg_list={-1:0}] [L1398] RET ldv_kobject_init_internal(kobj) VAL [kobj={1082401:0}, kobj={1082401:0}, ldv_global_msg_list={-1:0}] [L1413] RET ldv_kobject_init(kobj) VAL [kobj={1082401:0}, ldv_global_msg_list={-1:0}] [L1414] return kobj; VAL [\result={1082401:0}, kobj={1082401:0}, ldv_global_msg_list={-1:0}] [L1437] RET, EXPR ldv_kobject_create() VAL [ldv_global_msg_list={-1:0}, ldv_kobject_create()={1082401:0}] [L1437] kobj = ldv_kobject_create() [L1438] CALL ldv_kobject_get(kobj) VAL [kobj={1082401:0}, ldv_global_msg_list={-1:0}] [L1373] COND TRUE \read(*kobj) VAL [kobj={1082401:0}, kobj={1082401:0}, ldv_global_msg_list={-1:0}] [L1374] CALL ldv_kref_get(&kobj->kref) VAL [kref={1082401:12}, ldv_global_msg_list={-1:0}] [L1308] CALL ldv_atomic_add_return(1, (&kref->refcount)) VAL [\old(i)=1, ldv_global_msg_list={-1:0}, v={1082401:12}] [L1255] int temp; VAL [\old(i)=1, i=1, ldv_global_msg_list={-1:0}, v={1082401:12}, v={1082401:12}] [L1256] EXPR v->counter VAL [\old(i)=1, i=1, ldv_global_msg_list={-1:0}, v={1082401:12}, v={1082401:12}, v->counter=1] [L1256] temp = v->counter [L1257] temp += i VAL [\old(i)=1, i=1, ldv_global_msg_list={-1:0}, temp=2, v={1082401:12}, v={1082401:12}] [L1258] v->counter = temp VAL [\old(i)=1, i=1, ldv_global_msg_list={-1:0}, temp=2, v={1082401:12}, v={1082401:12}] [L1259] return temp; VAL [\old(i)=1, \result=2, i=1, ldv_global_msg_list={-1:0}, temp=2, v={1082401:12}, v={1082401:12}] [L1308] RET ldv_atomic_add_return(1, (&kref->refcount)) VAL [kref={1082401:12}, kref={1082401:12}, ldv_atomic_add_return(1, (&kref->refcount))=2, ldv_global_msg_list={-1:0}] [L1374] RET ldv_kref_get(&kobj->kref) VAL [kobj={1082401:0}, kobj={1082401:0}, ldv_global_msg_list={-1:0}] [L1375] return kobj; VAL [\result={1082401:0}, kobj={1082401:0}, kobj={1082401:0}, ldv_global_msg_list={-1:0}] [L1438] RET ldv_kobject_get(kobj) VAL [kobj={1082401:0}, ldv_global_msg_list={-1:0}, ldv_kobject_get(kobj)={1082401:0}] [L1440] CALL ldv_kobject_put(kobj) VAL [kobj={1082401:0}, ldv_global_msg_list={-1:0}] [L1361] COND TRUE \read(*kobj) VAL [kobj={1082401:0}, kobj={1082401:0}, ldv_global_msg_list={-1:0}] [L1363] CALL ldv_kref_put(&kobj->kref, ldv_kobject_release) VAL [kref={1082401:12}, ldv_global_msg_list={-1:0}, release={-1:0}] [L1313] CALL, EXPR ldv_kref_sub(kref, 1, release) VAL [\old(count)=1, kref={1082401:12}, ldv_global_msg_list={-1:0}, release={-1:0}] [L1281] CALL, EXPR ldv_atomic_sub_return(((int) count), (&kref->refcount)) VAL [\old(i)=1, ldv_global_msg_list={-1:0}, v={1082401:12}] [L1264] int temp; VAL [\old(i)=1, i=1, ldv_global_msg_list={-1:0}, v={1082401:12}, v={1082401:12}] [L1265] EXPR v->counter VAL [\old(i)=1, i=1, ldv_global_msg_list={-1:0}, v={1082401:12}, v={1082401:12}, v->counter=2] [L1265] temp = v->counter [L1266] temp -= i VAL [\old(i)=1, i=1, ldv_global_msg_list={-1:0}, temp=1, v={1082401:12}, v={1082401:12}] [L1267] v->counter = temp VAL [\old(i)=1, i=1, ldv_global_msg_list={-1:0}, temp=1, v={1082401:12}, v={1082401:12}] [L1268] return temp; VAL [\old(i)=1, \result=1, i=1, ldv_global_msg_list={-1:0}, temp=1, v={1082401:12}, v={1082401:12}] [L1281] RET, EXPR ldv_atomic_sub_return(((int) count), (&kref->refcount)) VAL [\old(count)=1, count=1, kref={1082401:12}, kref={1082401:12}, ldv_atomic_sub_return(((int) count), (&kref->refcount))=1, ldv_global_msg_list={-1:0}, release={-1:0}, release={-1:0}] [L1281] COND FALSE !((ldv_atomic_sub_return(((int) count), (&kref->refcount)) == 0)) [L1285] return 0; VAL [\old(count)=1, \result=0, count=1, kref={1082401:12}, kref={1082401:12}, ldv_global_msg_list={-1:0}, release={-1:0}, release={-1:0}] [L1313] RET, EXPR ldv_kref_sub(kref, 1, release) VAL [kref={1082401:12}, kref={1082401:12}, ldv_global_msg_list={-1:0}, ldv_kref_sub(kref, 1, release)=0, release={-1:0}, release={-1:0}] [L1313] return ldv_kref_sub(kref, 1, release); [L1363] RET ldv_kref_put(&kobj->kref, ldv_kobject_release) VAL [kobj={1082401:0}, kobj={1082401:0}, ldv_global_msg_list={-1:0}, ldv_kref_put(&kobj->kref, ldv_kobject_release)=0] [L1440] RET ldv_kobject_put(kobj) VAL [kobj={1082401:0}, ldv_global_msg_list={-1:0}] [L1444] RET entry_point() VAL [ldv_global_msg_list={-1:0}] - StatisticsResult: Ultimate Automizer benchmark data CFG has 43 procedures, 310 locations, 67 error locations. UNSAFE Result, 207.4s OverallTime, 27 OverallIterations, 16 TraceHistogramMax, 115.8s AutomataDifference, 0.0s DeadEndRemovalTime, 0.0s HoareAnnotationTime, HoareTripleCheckerStatistics: 3053 SDtfs, 1375 SDslu, 22161 SDs, 0 SdLazy, 15666 SolverSat, 405 SolverUnsat, 8 SolverUnknown, 0 SolverNotchecked, 86.5s Time, PredicateUnifierStatistics: 0 DeclaredPredicates, 1784 GetRequests, 1272 SyntacticMatches, 42 SemanticMatches, 470 ConstructedPredicates, 2 IntricatePredicates, 0 DeprecatedPredicates, 3568 ImplicationChecksByTransitivity, 61.4s Time, 0.0s BasicInterpolantAutomatonTime, BiggestAbstraction: size=170occurred in iteration=0, traceCheckStatistics: No data available, InterpolantConsolidationStatistics: No data available, PathInvariantsStatistics: No data available, 0/0 InterpolantCoveringCapability, TotalInterpolationStatistics: No data available, 0.0s AbstIntTime, 0 AbstIntIterations, 0 AbstIntStrong, NaN AbsIntWeakeningRatio, NaN AbsIntAvgWeakeningVarsNumRemoved, NaN AbsIntAvgWeakenedConjuncts, 0.0s DumpTime, AutomataMinimizationStatistics: 0.1s AutomataMinimizationTime, 26 MinimizatonAttempts, 98 StatesRemovedByMinimization, 12 NontrivialMinimizations, HoareAnnotationStatistics: No data available, RefinementEngineStatistics: TraceCheckStatistics: 0.4s SsaConstructionTime, 7.5s SatisfiabilityAnalysisTime, 77.4s InterpolantComputationTime, 1678 NumberOfCodeBlocks, 1648 NumberOfCodeBlocksAsserted, 28 NumberOfCheckSat, 1653 ConstructedInterpolants, 324 QuantifiedInterpolants, 1218241 SizeOfPredicates, 226 NumberOfNonLiveVariables, 6317 ConjunctsInSsa, 645 ConjunctsInUnsatCore, 30 InterpolantComputations, 23 PerfectInterpolantSequences, 1833/2101 InterpolantCoveringCapability, InvariantSynthesisStatistics: No data available, InterpolantConsolidationStatistics: No data available, ReuseStatistics: No data available RESULT: Ultimate could not prove your program: unable to determine feasibility of some traces Received shutdown request...