./Ultimate.py --spec ../../sv-benchmarks/c/properties/valid-memsafety.prp --file ../../sv-benchmarks/c/ldv-memsafety/memleaks_test22_4_false-valid-memtrack_true-termination.i --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for memory safety (deref-memtrack) Using default analysis Version 0cd3be1d Calling Ultimate with: java -Dosgi.configuration.area=/tmp/vcloud-vcloud-master/worker/working_dir_a5616418-4a25-482a-a0cb-6eefe8bc17e5/bin-2019/uautomizer/data/config -Xmx12G -Xms1G -jar /tmp/vcloud-vcloud-master/worker/working_dir_a5616418-4a25-482a-a0cb-6eefe8bc17e5/bin-2019/uautomizer/plugins/org.eclipse.equinox.launcher_1.3.100.v20150511-1540.jar -data @noDefault -ultimatedata /tmp/vcloud-vcloud-master/worker/working_dir_a5616418-4a25-482a-a0cb-6eefe8bc17e5/bin-2019/uautomizer/data -tc /tmp/vcloud-vcloud-master/worker/working_dir_a5616418-4a25-482a-a0cb-6eefe8bc17e5/bin-2019/uautomizer/config/AutomizerMemDerefMemtrack.xml -i ../../sv-benchmarks/c/ldv-memsafety/memleaks_test22_4_false-valid-memtrack_true-termination.i -s /tmp/vcloud-vcloud-master/worker/working_dir_a5616418-4a25-482a-a0cb-6eefe8bc17e5/bin-2019/uautomizer/config/svcomp-DerefFreeMemtrack-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud-vcloud-master/worker/working_dir_a5616418-4a25-482a-a0cb-6eefe8bc17e5/bin-2019/uautomizer --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(G valid-free) ) CHECK( init(main()), LTL(G valid-deref) ) CHECK( init(main()), LTL(G valid-memtrack) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash bc6894f63179c5a0c3641b97a75e8f614c456bea .................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................... Execution finished normally Using bit-precise analysis Retrying with bit-precise analysis Calling Ultimate with: java -Dosgi.configuration.area=/tmp/vcloud-vcloud-master/worker/working_dir_a5616418-4a25-482a-a0cb-6eefe8bc17e5/bin-2019/uautomizer/data/config -Xmx12G -Xms1G -jar /tmp/vcloud-vcloud-master/worker/working_dir_a5616418-4a25-482a-a0cb-6eefe8bc17e5/bin-2019/uautomizer/plugins/org.eclipse.equinox.launcher_1.3.100.v20150511-1540.jar -data @noDefault -ultimatedata /tmp/vcloud-vcloud-master/worker/working_dir_a5616418-4a25-482a-a0cb-6eefe8bc17e5/bin-2019/uautomizer/data -tc /tmp/vcloud-vcloud-master/worker/working_dir_a5616418-4a25-482a-a0cb-6eefe8bc17e5/bin-2019/uautomizer/config/AutomizerMemDerefMemtrack.xml -i ../../sv-benchmarks/c/ldv-memsafety/memleaks_test22_4_false-valid-memtrack_true-termination.i -s /tmp/vcloud-vcloud-master/worker/working_dir_a5616418-4a25-482a-a0cb-6eefe8bc17e5/bin-2019/uautomizer/config/svcomp-DerefFreeMemtrack-32bit-Automizer_Bitvector.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud-vcloud-master/worker/working_dir_a5616418-4a25-482a-a0cb-6eefe8bc17e5/bin-2019/uautomizer --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(G valid-free) ) CHECK( init(main()), LTL(G valid-deref) ) CHECK( init(main()), LTL(G valid-memtrack) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash bc6894f63179c5a0c3641b97a75e8f614c456bea ................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................ Execution finished normally Writing output log to file Ultimate.log Result: UNKNOWN: Overapproximated counterexample --- Real Ultimate output --- This is Ultimate 0.1.23-0cd3be1 [2018-11-28 13:02:53,897 INFO L170 SettingsManager]: Resetting all preferences to default values... [2018-11-28 13:02:53,899 INFO L174 SettingsManager]: Resetting UltimateCore preferences to default values [2018-11-28 13:02:53,907 INFO L177 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2018-11-28 13:02:53,907 INFO L174 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2018-11-28 13:02:53,908 INFO L174 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2018-11-28 13:02:53,909 INFO L174 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2018-11-28 13:02:53,910 INFO L174 SettingsManager]: Resetting LassoRanker preferences to default values [2018-11-28 13:02:53,911 INFO L174 SettingsManager]: Resetting Reaching Definitions preferences to default values [2018-11-28 13:02:53,911 INFO L174 SettingsManager]: Resetting SyntaxChecker preferences to default values [2018-11-28 13:02:53,912 INFO L177 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2018-11-28 13:02:53,912 INFO L174 SettingsManager]: Resetting LTL2Aut preferences to default values [2018-11-28 13:02:53,913 INFO L174 SettingsManager]: Resetting PEA to Boogie preferences to default values [2018-11-28 13:02:53,914 INFO L174 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2018-11-28 13:02:53,914 INFO L174 SettingsManager]: Resetting ChcToBoogie preferences to default values [2018-11-28 13:02:53,915 INFO L174 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2018-11-28 13:02:53,915 INFO L174 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2018-11-28 13:02:53,917 INFO L174 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2018-11-28 13:02:53,918 INFO L174 SettingsManager]: Resetting CodeCheck preferences to default values [2018-11-28 13:02:53,919 INFO L174 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2018-11-28 13:02:53,920 INFO L174 SettingsManager]: Resetting RCFGBuilder preferences to default values [2018-11-28 13:02:53,921 INFO L174 SettingsManager]: Resetting TraceAbstraction preferences to default values [2018-11-28 13:02:53,922 INFO L177 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2018-11-28 13:02:53,922 INFO L177 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2018-11-28 13:02:53,922 INFO L174 SettingsManager]: Resetting TreeAutomizer preferences to default values [2018-11-28 13:02:53,923 INFO L174 SettingsManager]: Resetting IcfgTransformer preferences to default values [2018-11-28 13:02:53,924 INFO L174 SettingsManager]: Resetting Boogie Printer preferences to default values [2018-11-28 13:02:53,924 INFO L174 SettingsManager]: Resetting ReqPrinter preferences to default values [2018-11-28 13:02:53,925 INFO L174 SettingsManager]: Resetting Witness Printer preferences to default values [2018-11-28 13:02:53,926 INFO L177 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2018-11-28 13:02:53,926 INFO L174 SettingsManager]: Resetting CDTParser preferences to default values [2018-11-28 13:02:53,926 INFO L177 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2018-11-28 13:02:53,926 INFO L177 SettingsManager]: ReqParser provides no preferences, ignoring... [2018-11-28 13:02:53,926 INFO L174 SettingsManager]: Resetting SmtParser preferences to default values [2018-11-28 13:02:53,927 INFO L174 SettingsManager]: Resetting Witness Parser preferences to default values [2018-11-28 13:02:53,928 INFO L181 SettingsManager]: Finished resetting all preferences to default values... [2018-11-28 13:02:53,928 INFO L98 SettingsManager]: Beginning loading settings from /tmp/vcloud-vcloud-master/worker/working_dir_a5616418-4a25-482a-a0cb-6eefe8bc17e5/bin-2019/uautomizer/config/svcomp-DerefFreeMemtrack-32bit-Automizer_Default.epf [2018-11-28 13:02:53,937 INFO L110 SettingsManager]: Loading preferences was successful [2018-11-28 13:02:53,937 INFO L112 SettingsManager]: Preferences different from defaults after loading the file: [2018-11-28 13:02:53,938 INFO L131 SettingsManager]: Preferences of Boogie Procedure Inliner differ from their defaults: [2018-11-28 13:02:53,938 INFO L133 SettingsManager]: * ... calls to implemented procedures=ONLY_FOR_CONCURRENT_PROGRAMS [2018-11-28 13:02:53,938 INFO L131 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2018-11-28 13:02:53,938 INFO L133 SettingsManager]: * Create parallel compositions if possible=false [2018-11-28 13:02:53,939 INFO L133 SettingsManager]: * Use SBE=true [2018-11-28 13:02:53,939 INFO L131 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2018-11-28 13:02:53,939 INFO L133 SettingsManager]: * sizeof long=4 [2018-11-28 13:02:53,939 INFO L133 SettingsManager]: * Check unreachability of error function in SV-COMP mode=false [2018-11-28 13:02:53,939 INFO L133 SettingsManager]: * Overapproximate operations on floating types=true [2018-11-28 13:02:53,939 INFO L133 SettingsManager]: * sizeof POINTER=4 [2018-11-28 13:02:53,939 INFO L133 SettingsManager]: * Check division by zero=IGNORE [2018-11-28 13:02:53,940 INFO L133 SettingsManager]: * Check for the main procedure if all allocated memory was freed=true [2018-11-28 13:02:53,940 INFO L133 SettingsManager]: * Bitprecise bitfields=true [2018-11-28 13:02:53,940 INFO L133 SettingsManager]: * SV-COMP memtrack compatibility mode=true [2018-11-28 13:02:53,940 INFO L133 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=IGNORE [2018-11-28 13:02:53,940 INFO L133 SettingsManager]: * sizeof long double=12 [2018-11-28 13:02:53,940 INFO L133 SettingsManager]: * Use constant arrays=true [2018-11-28 13:02:53,940 INFO L131 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2018-11-28 13:02:53,940 INFO L133 SettingsManager]: * Size of a code block=SequenceOfStatements [2018-11-28 13:02:53,941 INFO L133 SettingsManager]: * To the following directory=./dump/ [2018-11-28 13:02:53,941 INFO L133 SettingsManager]: * SMT solver=External_DefaultMode [2018-11-28 13:02:53,941 INFO L133 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2018-11-28 13:02:53,941 INFO L131 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2018-11-28 13:02:53,942 INFO L133 SettingsManager]: * Compute Interpolants along a Counterexample=FPandBP [2018-11-28 13:02:53,942 INFO L133 SettingsManager]: * Trace refinement strategy=CAMEL [2018-11-28 13:02:53,942 INFO L133 SettingsManager]: * SMT solver=External_ModelsAndUnsatCoreMode [2018-11-28 13:02:53,942 INFO L133 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud-vcloud-master/worker/working_dir_a5616418-4a25-482a-a0cb-6eefe8bc17e5/bin-2019/uautomizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(G valid-free) ) CHECK( init(main()), LTL(G valid-deref) ) CHECK( init(main()), LTL(G valid-memtrack) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> bc6894f63179c5a0c3641b97a75e8f614c456bea [2018-11-28 13:02:53,965 INFO L81 nceAwareModelManager]: Repository-Root is: /tmp [2018-11-28 13:02:53,974 INFO L258 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2018-11-28 13:02:53,976 INFO L214 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2018-11-28 13:02:53,977 INFO L271 PluginConnector]: Initializing CDTParser... [2018-11-28 13:02:53,978 INFO L276 PluginConnector]: CDTParser initialized [2018-11-28 13:02:53,978 INFO L418 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud-vcloud-master/worker/working_dir_a5616418-4a25-482a-a0cb-6eefe8bc17e5/bin-2019/uautomizer/../../sv-benchmarks/c/ldv-memsafety/memleaks_test22_4_false-valid-memtrack_true-termination.i [2018-11-28 13:02:54,022 INFO L221 CDTParser]: Created temporary CDT project at /tmp/vcloud-vcloud-master/worker/working_dir_a5616418-4a25-482a-a0cb-6eefe8bc17e5/bin-2019/uautomizer/data/d3f1d76f5/eea60afdc0274e98a700c1851b32d8dc/FLAG00efd5fe4 [2018-11-28 13:02:54,481 INFO L307 CDTParser]: Found 1 translation units. [2018-11-28 13:02:54,482 INFO L161 CDTParser]: Scanning /tmp/vcloud-vcloud-master/worker/working_dir_a5616418-4a25-482a-a0cb-6eefe8bc17e5/sv-benchmarks/c/ldv-memsafety/memleaks_test22_4_false-valid-memtrack_true-termination.i [2018-11-28 13:02:54,492 INFO L355 CDTParser]: About to delete temporary CDT project at /tmp/vcloud-vcloud-master/worker/working_dir_a5616418-4a25-482a-a0cb-6eefe8bc17e5/bin-2019/uautomizer/data/d3f1d76f5/eea60afdc0274e98a700c1851b32d8dc/FLAG00efd5fe4 [2018-11-28 13:02:54,997 INFO L363 CDTParser]: Successfully deleted /tmp/vcloud-vcloud-master/worker/working_dir_a5616418-4a25-482a-a0cb-6eefe8bc17e5/bin-2019/uautomizer/data/d3f1d76f5/eea60afdc0274e98a700c1851b32d8dc [2018-11-28 13:02:54,999 INFO L296 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2018-11-28 13:02:55,000 INFO L131 ToolchainWalker]: Walking toolchain with 5 elements. [2018-11-28 13:02:55,001 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2018-11-28 13:02:55,001 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2018-11-28 13:02:55,004 INFO L276 PluginConnector]: CACSL2BoogieTranslator initialized [2018-11-28 13:02:55,005 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 28.11 01:02:54" (1/1) ... [2018-11-28 13:02:55,007 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@3711ebb6 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 01:02:55, skipping insertion in model container [2018-11-28 13:02:55,007 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 28.11 01:02:54" (1/1) ... [2018-11-28 13:02:55,013 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2018-11-28 13:02:55,043 INFO L176 MainTranslator]: Built tables and reachable declarations [2018-11-28 13:02:55,307 INFO L203 PostProcessor]: Analyzing one entry point: main [2018-11-28 13:02:55,322 INFO L191 MainTranslator]: Completed pre-run [2018-11-28 13:02:55,364 INFO L203 PostProcessor]: Analyzing one entry point: main [2018-11-28 13:02:55,409 INFO L195 MainTranslator]: Completed translation [2018-11-28 13:02:55,409 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 01:02:55 WrapperNode [2018-11-28 13:02:55,409 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2018-11-28 13:02:55,410 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2018-11-28 13:02:55,410 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2018-11-28 13:02:55,410 INFO L276 PluginConnector]: Boogie Preprocessor initialized [2018-11-28 13:02:55,421 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 01:02:55" (1/1) ... [2018-11-28 13:02:55,421 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 01:02:55" (1/1) ... [2018-11-28 13:02:55,433 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 01:02:55" (1/1) ... [2018-11-28 13:02:55,434 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 01:02:55" (1/1) ... [2018-11-28 13:02:55,454 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 01:02:55" (1/1) ... [2018-11-28 13:02:55,458 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 01:02:55" (1/1) ... [2018-11-28 13:02:55,461 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 01:02:55" (1/1) ... [2018-11-28 13:02:55,468 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2018-11-28 13:02:55,469 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2018-11-28 13:02:55,469 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2018-11-28 13:02:55,469 INFO L276 PluginConnector]: RCFGBuilder initialized [2018-11-28 13:02:55,469 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 01:02:55" (1/1) ... No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_a5616418-4a25-482a-a0cb-6eefe8bc17e5/bin-2019/uautomizer/z3 Starting monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2018-11-28 13:02:55,512 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.init [2018-11-28 13:02:55,512 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2018-11-28 13:02:55,513 INFO L138 BoogieDeclarations]: Found implementation of procedure ##fun~$Pointer$~TO~VOID [2018-11-28 13:02:55,513 INFO L138 BoogieDeclarations]: Found implementation of procedure __bswap_32 [2018-11-28 13:02:55,513 INFO L138 BoogieDeclarations]: Found implementation of procedure __bswap_64 [2018-11-28 13:02:55,513 INFO L138 BoogieDeclarations]: Found implementation of procedure ldv_nonpositive [2018-11-28 13:02:55,513 INFO L138 BoogieDeclarations]: Found implementation of procedure ldv_positive [2018-11-28 13:02:55,513 INFO L138 BoogieDeclarations]: Found implementation of procedure ldv_malloc [2018-11-28 13:02:55,513 INFO L138 BoogieDeclarations]: Found implementation of procedure ldv_zalloc [2018-11-28 13:02:55,513 INFO L138 BoogieDeclarations]: Found implementation of procedure LDV_INIT_LIST_HEAD [2018-11-28 13:02:55,513 INFO L138 BoogieDeclarations]: Found implementation of procedure __ldv_list_add [2018-11-28 13:02:55,514 INFO L138 BoogieDeclarations]: Found implementation of procedure __ldv_list_del [2018-11-28 13:02:55,514 INFO L138 BoogieDeclarations]: Found implementation of procedure ldv_list_add [2018-11-28 13:02:55,514 INFO L138 BoogieDeclarations]: Found implementation of procedure ldv_list_add_tail [2018-11-28 13:02:55,514 INFO L138 BoogieDeclarations]: Found implementation of procedure ldv_list_del [2018-11-28 13:02:55,514 INFO L138 BoogieDeclarations]: Found implementation of procedure ldv_msg_alloc [2018-11-28 13:02:55,514 INFO L138 BoogieDeclarations]: Found implementation of procedure ldv_msg_fill [2018-11-28 13:02:55,514 INFO L138 BoogieDeclarations]: Found implementation of procedure ldv_msg_free [2018-11-28 13:02:55,515 INFO L138 BoogieDeclarations]: Found implementation of procedure ldv_submit_msg [2018-11-28 13:02:55,515 INFO L138 BoogieDeclarations]: Found implementation of procedure ldv_destroy_msgs [2018-11-28 13:02:55,515 INFO L138 BoogieDeclarations]: Found implementation of procedure ldv_dev_get_drvdata [2018-11-28 13:02:55,515 INFO L138 BoogieDeclarations]: Found implementation of procedure ldv_dev_set_drvdata [2018-11-28 13:02:55,515 INFO L138 BoogieDeclarations]: Found implementation of procedure ldv_atomic_add_return [2018-11-28 13:02:55,515 INFO L138 BoogieDeclarations]: Found implementation of procedure ldv_atomic_sub_return [2018-11-28 13:02:55,515 INFO L138 BoogieDeclarations]: Found implementation of procedure ldv_kref_sub [2018-11-28 13:02:55,515 INFO L138 BoogieDeclarations]: Found implementation of procedure ldv_kref_init [2018-11-28 13:02:55,515 INFO L138 BoogieDeclarations]: Found implementation of procedure ldv_kref_get [2018-11-28 13:02:55,516 INFO L138 BoogieDeclarations]: Found implementation of procedure ldv_kref_put [2018-11-28 13:02:55,516 INFO L138 BoogieDeclarations]: Found implementation of procedure ldv_kobject_del [2018-11-28 13:02:55,516 INFO L138 BoogieDeclarations]: Found implementation of procedure ldv_kobject_cleanup [2018-11-28 13:02:55,516 INFO L138 BoogieDeclarations]: Found implementation of procedure ldv_kobject_release [2018-11-28 13:02:55,516 INFO L138 BoogieDeclarations]: Found implementation of procedure ldv_kobject_put [2018-11-28 13:02:55,516 INFO L138 BoogieDeclarations]: Found implementation of procedure ldv_kobject_get [2018-11-28 13:02:55,516 INFO L138 BoogieDeclarations]: Found implementation of procedure ldv_kobject_init_internal [2018-11-28 13:02:55,516 INFO L138 BoogieDeclarations]: Found implementation of procedure ldv_kobject_init [2018-11-28 13:02:55,516 INFO L138 BoogieDeclarations]: Found implementation of procedure ldv_kobject_create [2018-11-28 13:02:55,516 INFO L138 BoogieDeclarations]: Found implementation of procedure f [2018-11-28 13:02:55,517 INFO L138 BoogieDeclarations]: Found implementation of procedure g [2018-11-28 13:02:55,517 INFO L138 BoogieDeclarations]: Found implementation of procedure f_22_get [2018-11-28 13:02:55,517 INFO L138 BoogieDeclarations]: Found implementation of procedure f_22_put [2018-11-28 13:02:55,517 INFO L138 BoogieDeclarations]: Found implementation of procedure entry_point [2018-11-28 13:02:55,517 INFO L138 BoogieDeclarations]: Found implementation of procedure main [2018-11-28 13:02:55,517 INFO L138 BoogieDeclarations]: Found implementation of procedure #Ultimate.C_memset [2018-11-28 13:02:55,517 INFO L138 BoogieDeclarations]: Found implementation of procedure #Ultimate.meminit [2018-11-28 13:02:55,517 INFO L138 BoogieDeclarations]: Found implementation of procedure #Ultimate.C_memcpy [2018-11-28 13:02:55,517 INFO L130 BoogieDeclarations]: Found specification of procedure __bswap_32 [2018-11-28 13:02:55,517 INFO L130 BoogieDeclarations]: Found specification of procedure __bswap_64 [2018-11-28 13:02:55,518 INFO L130 BoogieDeclarations]: Found specification of procedure __ctype_get_mb_cur_max [2018-11-28 13:02:55,518 INFO L130 BoogieDeclarations]: Found specification of procedure atof [2018-11-28 13:02:55,518 INFO L130 BoogieDeclarations]: Found specification of procedure atoi [2018-11-28 13:02:55,518 INFO L130 BoogieDeclarations]: Found specification of procedure atol [2018-11-28 13:02:55,518 INFO L130 BoogieDeclarations]: Found specification of procedure atoll [2018-11-28 13:02:55,518 INFO L130 BoogieDeclarations]: Found specification of procedure strtod [2018-11-28 13:02:55,518 INFO L130 BoogieDeclarations]: Found specification of procedure strtof [2018-11-28 13:02:55,518 INFO L130 BoogieDeclarations]: Found specification of procedure strtold [2018-11-28 13:02:55,518 INFO L130 BoogieDeclarations]: Found specification of procedure strtol [2018-11-28 13:02:55,519 INFO L130 BoogieDeclarations]: Found specification of procedure strtoul [2018-11-28 13:02:55,519 INFO L130 BoogieDeclarations]: Found specification of procedure strtoq [2018-11-28 13:02:55,519 INFO L130 BoogieDeclarations]: Found specification of procedure strtouq [2018-11-28 13:02:55,519 INFO L130 BoogieDeclarations]: Found specification of procedure strtoll [2018-11-28 13:02:55,519 INFO L130 BoogieDeclarations]: Found specification of procedure strtoull [2018-11-28 13:02:55,519 INFO L130 BoogieDeclarations]: Found specification of procedure l64a [2018-11-28 13:02:55,519 INFO L130 BoogieDeclarations]: Found specification of procedure a64l [2018-11-28 13:02:55,519 INFO L130 BoogieDeclarations]: Found specification of procedure select [2018-11-28 13:02:55,519 INFO L130 BoogieDeclarations]: Found specification of procedure pselect [2018-11-28 13:02:55,519 INFO L130 BoogieDeclarations]: Found specification of procedure gnu_dev_major [2018-11-28 13:02:55,519 INFO L130 BoogieDeclarations]: Found specification of procedure gnu_dev_minor [2018-11-28 13:02:55,520 INFO L130 BoogieDeclarations]: Found specification of procedure gnu_dev_makedev [2018-11-28 13:02:55,520 INFO L130 BoogieDeclarations]: Found specification of procedure random [2018-11-28 13:02:55,520 INFO L130 BoogieDeclarations]: Found specification of procedure srandom [2018-11-28 13:02:55,520 INFO L130 BoogieDeclarations]: Found specification of procedure initstate [2018-11-28 13:02:55,520 INFO L130 BoogieDeclarations]: Found specification of procedure setstate [2018-11-28 13:02:55,520 INFO L130 BoogieDeclarations]: Found specification of procedure random_r [2018-11-28 13:02:55,520 INFO L130 BoogieDeclarations]: Found specification of procedure srandom_r [2018-11-28 13:02:55,520 INFO L130 BoogieDeclarations]: Found specification of procedure initstate_r [2018-11-28 13:02:55,520 INFO L130 BoogieDeclarations]: Found specification of procedure setstate_r [2018-11-28 13:02:55,520 INFO L130 BoogieDeclarations]: Found specification of procedure rand [2018-11-28 13:02:55,520 INFO L130 BoogieDeclarations]: Found specification of procedure srand [2018-11-28 13:02:55,521 INFO L130 BoogieDeclarations]: Found specification of procedure rand_r [2018-11-28 13:02:55,521 INFO L130 BoogieDeclarations]: Found specification of procedure drand48 [2018-11-28 13:02:55,521 INFO L130 BoogieDeclarations]: Found specification of procedure erand48 [2018-11-28 13:02:55,521 INFO L130 BoogieDeclarations]: Found specification of procedure lrand48 [2018-11-28 13:02:55,521 INFO L130 BoogieDeclarations]: Found specification of procedure nrand48 [2018-11-28 13:02:55,521 INFO L130 BoogieDeclarations]: Found specification of procedure mrand48 [2018-11-28 13:02:55,521 INFO L130 BoogieDeclarations]: Found specification of procedure jrand48 [2018-11-28 13:02:55,521 INFO L130 BoogieDeclarations]: Found specification of procedure srand48 [2018-11-28 13:02:55,521 INFO L130 BoogieDeclarations]: Found specification of procedure seed48 [2018-11-28 13:02:55,521 INFO L130 BoogieDeclarations]: Found specification of procedure lcong48 [2018-11-28 13:02:55,522 INFO L130 BoogieDeclarations]: Found specification of procedure drand48_r [2018-11-28 13:02:55,522 INFO L130 BoogieDeclarations]: Found specification of procedure erand48_r [2018-11-28 13:02:55,522 INFO L130 BoogieDeclarations]: Found specification of procedure lrand48_r [2018-11-28 13:02:55,522 INFO L130 BoogieDeclarations]: Found specification of procedure nrand48_r [2018-11-28 13:02:55,522 INFO L130 BoogieDeclarations]: Found specification of procedure mrand48_r [2018-11-28 13:02:55,522 INFO L130 BoogieDeclarations]: Found specification of procedure jrand48_r [2018-11-28 13:02:55,522 INFO L130 BoogieDeclarations]: Found specification of procedure srand48_r [2018-11-28 13:02:55,522 INFO L130 BoogieDeclarations]: Found specification of procedure seed48_r [2018-11-28 13:02:55,522 INFO L130 BoogieDeclarations]: Found specification of procedure lcong48_r [2018-11-28 13:02:55,522 INFO L130 BoogieDeclarations]: Found specification of procedure malloc [2018-11-28 13:02:55,523 INFO L130 BoogieDeclarations]: Found specification of procedure calloc [2018-11-28 13:02:55,523 INFO L130 BoogieDeclarations]: Found specification of procedure realloc [2018-11-28 13:02:55,523 INFO L130 BoogieDeclarations]: Found specification of procedure free [2018-11-28 13:02:55,523 INFO L130 BoogieDeclarations]: Found specification of procedure cfree [2018-11-28 13:02:55,523 INFO L130 BoogieDeclarations]: Found specification of procedure alloca [2018-11-28 13:02:55,523 INFO L130 BoogieDeclarations]: Found specification of procedure valloc [2018-11-28 13:02:55,523 INFO L130 BoogieDeclarations]: Found specification of procedure posix_memalign [2018-11-28 13:02:55,523 INFO L130 BoogieDeclarations]: Found specification of procedure abort [2018-11-28 13:02:55,523 INFO L130 BoogieDeclarations]: Found specification of procedure atexit [2018-11-28 13:02:55,523 INFO L130 BoogieDeclarations]: Found specification of procedure on_exit [2018-11-28 13:02:55,523 INFO L130 BoogieDeclarations]: Found specification of procedure exit [2018-11-28 13:02:55,524 INFO L130 BoogieDeclarations]: Found specification of procedure _Exit [2018-11-28 13:02:55,524 INFO L130 BoogieDeclarations]: Found specification of procedure getenv [2018-11-28 13:02:55,524 INFO L130 BoogieDeclarations]: Found specification of procedure putenv [2018-11-28 13:02:55,524 INFO L130 BoogieDeclarations]: Found specification of procedure setenv [2018-11-28 13:02:55,524 INFO L130 BoogieDeclarations]: Found specification of procedure unsetenv [2018-11-28 13:02:55,524 INFO L130 BoogieDeclarations]: Found specification of procedure clearenv [2018-11-28 13:02:55,524 INFO L130 BoogieDeclarations]: Found specification of procedure mktemp [2018-11-28 13:02:55,524 INFO L130 BoogieDeclarations]: Found specification of procedure mkstemp [2018-11-28 13:02:55,524 INFO L130 BoogieDeclarations]: Found specification of procedure mkstemps [2018-11-28 13:02:55,524 INFO L130 BoogieDeclarations]: Found specification of procedure mkdtemp [2018-11-28 13:02:55,524 INFO L130 BoogieDeclarations]: Found specification of procedure system [2018-11-28 13:02:55,525 INFO L130 BoogieDeclarations]: Found specification of procedure realpath [2018-11-28 13:02:55,525 INFO L130 BoogieDeclarations]: Found specification of procedure bsearch [2018-11-28 13:02:55,525 INFO L130 BoogieDeclarations]: Found specification of procedure qsort [2018-11-28 13:02:55,525 INFO L130 BoogieDeclarations]: Found specification of procedure abs [2018-11-28 13:02:55,525 INFO L130 BoogieDeclarations]: Found specification of procedure labs [2018-11-28 13:02:55,525 INFO L130 BoogieDeclarations]: Found specification of procedure llabs [2018-11-28 13:02:55,525 INFO L130 BoogieDeclarations]: Found specification of procedure div [2018-11-28 13:02:55,525 INFO L130 BoogieDeclarations]: Found specification of procedure ldiv [2018-11-28 13:02:55,525 INFO L130 BoogieDeclarations]: Found specification of procedure lldiv [2018-11-28 13:02:55,525 INFO L130 BoogieDeclarations]: Found specification of procedure ecvt [2018-11-28 13:02:55,525 INFO L130 BoogieDeclarations]: Found specification of procedure fcvt [2018-11-28 13:02:55,526 INFO L130 BoogieDeclarations]: Found specification of procedure gcvt [2018-11-28 13:02:55,526 INFO L130 BoogieDeclarations]: Found specification of procedure qecvt [2018-11-28 13:02:55,526 INFO L130 BoogieDeclarations]: Found specification of procedure qfcvt [2018-11-28 13:02:55,526 INFO L130 BoogieDeclarations]: Found specification of procedure qgcvt [2018-11-28 13:02:55,526 INFO L130 BoogieDeclarations]: Found specification of procedure ecvt_r [2018-11-28 13:02:55,526 INFO L130 BoogieDeclarations]: Found specification of procedure fcvt_r [2018-11-28 13:02:55,526 INFO L130 BoogieDeclarations]: Found specification of procedure qecvt_r [2018-11-28 13:02:55,526 INFO L130 BoogieDeclarations]: Found specification of procedure qfcvt_r [2018-11-28 13:02:55,526 INFO L130 BoogieDeclarations]: Found specification of procedure mblen [2018-11-28 13:02:55,526 INFO L130 BoogieDeclarations]: Found specification of procedure mbtowc [2018-11-28 13:02:55,527 INFO L130 BoogieDeclarations]: Found specification of procedure wctomb [2018-11-28 13:02:55,527 INFO L130 BoogieDeclarations]: Found specification of procedure mbstowcs [2018-11-28 13:02:55,527 INFO L130 BoogieDeclarations]: Found specification of procedure wcstombs [2018-11-28 13:02:55,527 INFO L130 BoogieDeclarations]: Found specification of procedure rpmatch [2018-11-28 13:02:55,527 INFO L130 BoogieDeclarations]: Found specification of procedure getsubopt [2018-11-28 13:02:55,527 INFO L130 BoogieDeclarations]: Found specification of procedure getloadavg [2018-11-28 13:02:55,527 INFO L130 BoogieDeclarations]: Found specification of procedure kfree [2018-11-28 13:02:55,527 INFO L130 BoogieDeclarations]: Found specification of procedure __VERIFIER_nondet_int [2018-11-28 13:02:55,527 INFO L130 BoogieDeclarations]: Found specification of procedure __VERIFIER_nondet_pointer [2018-11-28 13:02:55,527 INFO L130 BoogieDeclarations]: Found specification of procedure ldv_nonpositive [2018-11-28 13:02:55,527 INFO L130 BoogieDeclarations]: Found specification of procedure ldv_positive [2018-11-28 13:02:55,528 INFO L130 BoogieDeclarations]: Found specification of procedure memcpy [2018-11-28 13:02:55,528 INFO L130 BoogieDeclarations]: Found specification of procedure memset [2018-11-28 13:02:55,528 INFO L130 BoogieDeclarations]: Found specification of procedure ldv_malloc [2018-11-28 13:02:55,528 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.alloc [2018-11-28 13:02:55,528 INFO L130 BoogieDeclarations]: Found specification of procedure ldv_zalloc [2018-11-28 13:02:55,528 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.meminit [2018-11-28 13:02:55,528 INFO L130 BoogieDeclarations]: Found specification of procedure LDV_INIT_LIST_HEAD [2018-11-28 13:02:55,528 INFO L130 BoogieDeclarations]: Found specification of procedure write~$Pointer$ [2018-11-28 13:02:55,528 INFO L130 BoogieDeclarations]: Found specification of procedure __ldv_list_add [2018-11-28 13:02:55,528 INFO L130 BoogieDeclarations]: Found specification of procedure __ldv_list_del [2018-11-28 13:02:55,528 INFO L130 BoogieDeclarations]: Found specification of procedure ldv_list_add [2018-11-28 13:02:55,529 INFO L130 BoogieDeclarations]: Found specification of procedure read~$Pointer$ [2018-11-28 13:02:55,529 INFO L130 BoogieDeclarations]: Found specification of procedure ldv_list_add_tail [2018-11-28 13:02:55,529 INFO L130 BoogieDeclarations]: Found specification of procedure ldv_list_del [2018-11-28 13:02:55,529 INFO L130 BoogieDeclarations]: Found specification of procedure ldv_msg_alloc [2018-11-28 13:02:55,529 INFO L130 BoogieDeclarations]: Found specification of procedure ldv_msg_fill [2018-11-28 13:02:55,529 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.C_memcpy [2018-11-28 13:02:55,529 INFO L130 BoogieDeclarations]: Found specification of procedure ldv_msg_free [2018-11-28 13:02:55,529 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.dealloc [2018-11-28 13:02:55,529 INFO L130 BoogieDeclarations]: Found specification of procedure ldv_submit_msg [2018-11-28 13:02:55,529 INFO L130 BoogieDeclarations]: Found specification of procedure ldv_destroy_msgs [2018-11-28 13:02:55,530 INFO L130 BoogieDeclarations]: Found specification of procedure ldv_dev_get_drvdata [2018-11-28 13:02:55,530 INFO L130 BoogieDeclarations]: Found specification of procedure ldv_dev_set_drvdata [2018-11-28 13:02:55,530 INFO L130 BoogieDeclarations]: Found specification of procedure ldv_atomic_add_return [2018-11-28 13:02:55,530 INFO L130 BoogieDeclarations]: Found specification of procedure read~int [2018-11-28 13:02:55,530 INFO L130 BoogieDeclarations]: Found specification of procedure write~int [2018-11-28 13:02:55,530 INFO L130 BoogieDeclarations]: Found specification of procedure ldv_atomic_sub_return [2018-11-28 13:02:55,530 INFO L130 BoogieDeclarations]: Found specification of procedure ldv_kref_sub [2018-11-28 13:02:55,530 INFO L130 BoogieDeclarations]: Found specification of procedure ##fun~$Pointer$~TO~VOID [2018-11-28 13:02:55,530 INFO L130 BoogieDeclarations]: Found specification of procedure ldv_kref_init [2018-11-28 13:02:55,530 INFO L130 BoogieDeclarations]: Found specification of procedure ldv_kref_get [2018-11-28 13:02:55,530 INFO L130 BoogieDeclarations]: Found specification of procedure ldv_kref_put [2018-11-28 13:02:55,531 INFO L130 BoogieDeclarations]: Found specification of procedure ldv_kobject_del [2018-11-28 13:02:55,531 INFO L130 BoogieDeclarations]: Found specification of procedure ldv_kobject_cleanup [2018-11-28 13:02:55,531 INFO L130 BoogieDeclarations]: Found specification of procedure ldv_kobject_release [2018-11-28 13:02:55,531 INFO L130 BoogieDeclarations]: Found specification of procedure ldv_kobject_put [2018-11-28 13:02:55,531 INFO L130 BoogieDeclarations]: Found specification of procedure ldv_kobject_get [2018-11-28 13:02:55,531 INFO L130 BoogieDeclarations]: Found specification of procedure ldv_kobject_init_internal [2018-11-28 13:02:55,531 INFO L130 BoogieDeclarations]: Found specification of procedure ldv_kobject_init [2018-11-28 13:02:55,531 INFO L130 BoogieDeclarations]: Found specification of procedure ldv_kobject_create [2018-11-28 13:02:55,531 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.C_memset [2018-11-28 13:02:55,531 INFO L130 BoogieDeclarations]: Found specification of procedure f [2018-11-28 13:02:55,531 INFO L130 BoogieDeclarations]: Found specification of procedure g [2018-11-28 13:02:55,532 INFO L130 BoogieDeclarations]: Found specification of procedure f_22_get [2018-11-28 13:02:55,532 INFO L130 BoogieDeclarations]: Found specification of procedure f_22_put [2018-11-28 13:02:55,532 INFO L130 BoogieDeclarations]: Found specification of procedure entry_point [2018-11-28 13:02:55,532 INFO L130 BoogieDeclarations]: Found specification of procedure main [2018-11-28 13:02:55,532 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.init [2018-11-28 13:02:55,532 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~$Pointer$ [2018-11-28 13:02:55,532 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2018-11-28 13:02:55,532 INFO L130 BoogieDeclarations]: Found specification of procedure write~unchecked~int [2018-11-28 13:02:55,532 INFO L130 BoogieDeclarations]: Found specification of procedure read~unchecked~int [2018-11-28 13:02:55,532 INFO L130 BoogieDeclarations]: Found specification of procedure write~unchecked~$Pointer$ [2018-11-28 13:02:55,532 INFO L130 BoogieDeclarations]: Found specification of procedure read~unchecked~$Pointer$ [2018-11-28 13:02:55,866 WARN L615 $ProcedureCfgBuilder]: Label in the middle of a codeblock. [2018-11-28 13:02:56,030 WARN L615 $ProcedureCfgBuilder]: Label in the middle of a codeblock. [2018-11-28 13:02:56,192 INFO L275 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2018-11-28 13:02:56,192 INFO L280 CfgBuilder]: Removed 1 assue(true) statements. [2018-11-28 13:02:56,192 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 28.11 01:02:56 BoogieIcfgContainer [2018-11-28 13:02:56,192 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2018-11-28 13:02:56,193 INFO L113 PluginConnector]: ------------------------TraceAbstraction---------------------------- [2018-11-28 13:02:56,193 INFO L271 PluginConnector]: Initializing TraceAbstraction... [2018-11-28 13:02:56,196 INFO L276 PluginConnector]: TraceAbstraction initialized [2018-11-28 13:02:56,196 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "CDTParser AST 28.11 01:02:54" (1/3) ... [2018-11-28 13:02:56,197 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@7473b854 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 28.11 01:02:56, skipping insertion in model container [2018-11-28 13:02:56,197 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 01:02:55" (2/3) ... [2018-11-28 13:02:56,198 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@7473b854 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 28.11 01:02:56, skipping insertion in model container [2018-11-28 13:02:56,198 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 28.11 01:02:56" (3/3) ... [2018-11-28 13:02:56,199 INFO L112 eAbstractionObserver]: Analyzing ICFG memleaks_test22_4_false-valid-memtrack_true-termination.i [2018-11-28 13:02:56,205 INFO L156 ceAbstractionStarter]: Automizer settings: Hoare:false NWA Interpolation:FPandBP Determinization: PREDICATE_ABSTRACTION [2018-11-28 13:02:56,211 INFO L168 ceAbstractionStarter]: Appying trace abstraction to program that has 67 error locations. [2018-11-28 13:02:56,225 INFO L257 AbstractCegarLoop]: Starting to check reachability of 67 error locations. [2018-11-28 13:02:56,248 INFO L133 ementStrategyFactory]: Using default assertion order modulation [2018-11-28 13:02:56,249 INFO L382 AbstractCegarLoop]: Interprodecural is true [2018-11-28 13:02:56,249 INFO L383 AbstractCegarLoop]: Hoare is false [2018-11-28 13:02:56,249 INFO L384 AbstractCegarLoop]: Compute interpolants for FPandBP [2018-11-28 13:02:56,249 INFO L385 AbstractCegarLoop]: Backedges is STRAIGHT_LINE [2018-11-28 13:02:56,249 INFO L386 AbstractCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2018-11-28 13:02:56,249 INFO L387 AbstractCegarLoop]: Difference is false [2018-11-28 13:02:56,249 INFO L388 AbstractCegarLoop]: Minimize is MINIMIZE_SEVPA [2018-11-28 13:02:56,249 INFO L393 AbstractCegarLoop]: ======== Iteration 0==of CEGAR loop == AllErrorsAtOnce======== [2018-11-28 13:02:56,264 INFO L276 IsEmpty]: Start isEmpty. Operand 177 states. [2018-11-28 13:02:56,272 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 18 [2018-11-28 13:02:56,272 INFO L394 BasicCegarLoop]: Found error trace [2018-11-28 13:02:56,273 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-28 13:02:56,275 INFO L423 AbstractCegarLoop]: === Iteration 1 === [ldv_kref_initErr1REQUIRES_VIOLATION, ldv_kref_initErr0REQUIRES_VIOLATION, ldv_list_addErr1REQUIRES_VIOLATION, ldv_list_addErr0REQUIRES_VIOLATION, ldv_kobject_createErr0REQUIRES_VIOLATION, ldv_kobject_createErr1REQUIRES_VIOLATION, ldv_destroy_msgsErr3REQUIRES_VIOLATION, ldv_destroy_msgsErr2REQUIRES_VIOLATION, ldv_destroy_msgsErr1REQUIRES_VIOLATION, ldv_destroy_msgsErr0REQUIRES_VIOLATION, ldv_destroy_msgsErr5REQUIRES_VIOLATION, ldv_destroy_msgsErr4REQUIRES_VIOLATION, ldv_msg_fillErr1REQUIRES_VIOLATION, ldv_msg_fillErr4REQUIRES_VIOLATION, ldv_msg_fillErr0REQUIRES_VIOLATION, ldv_msg_fillErr5REQUIRES_VIOLATION, ldv_msg_fillErr3REQUIRES_VIOLATION, ldv_msg_fillErr2REQUIRES_VIOLATION, ldv_atomic_add_returnErr1REQUIRES_VIOLATION, ldv_atomic_add_returnErr0REQUIRES_VIOLATION, ldv_atomic_add_returnErr3REQUIRES_VIOLATION, ldv_atomic_add_returnErr2REQUIRES_VIOLATION, __ldv_list_delErr0REQUIRES_VIOLATION, __ldv_list_delErr1REQUIRES_VIOLATION, __ldv_list_delErr2REQUIRES_VIOLATION, __ldv_list_delErr3REQUIRES_VIOLATION, ldv_kobject_cleanupErr2ASSERT_VIOLATIONMEMORY_FREE, ldv_kobject_cleanupErr4ASSERT_VIOLATIONMEMORY_FREE, ldv_kobject_cleanupErr0REQUIRES_VIOLATION, ldv_kobject_cleanupErr5ASSERT_VIOLATIONMEMORY_FREE, ldv_kobject_cleanupErr1REQUIRES_VIOLATION, ldv_kobject_cleanupErr3ASSERT_VIOLATIONMEMORY_FREE, ldv_msg_freeErr2ASSERT_VIOLATIONMEMORY_FREE, ldv_msg_freeErr4ASSERT_VIOLATIONMEMORY_FREE, ldv_msg_freeErr5ASSERT_VIOLATIONMEMORY_FREE, ldv_msg_freeErr0REQUIRES_VIOLATION, ldv_msg_freeErr1REQUIRES_VIOLATION, ldv_msg_freeErr3ASSERT_VIOLATIONMEMORY_FREE, mainErr0ENSURES_VIOLATIONMEMORY_LEAK, LDV_INIT_LIST_HEADErr1REQUIRES_VIOLATION, LDV_INIT_LIST_HEADErr0REQUIRES_VIOLATION, LDV_INIT_LIST_HEADErr3REQUIRES_VIOLATION, LDV_INIT_LIST_HEADErr2REQUIRES_VIOLATION, ldv_list_delErr1REQUIRES_VIOLATION, ldv_list_delErr0REQUIRES_VIOLATION, ldv_list_delErr3REQUIRES_VIOLATION, ldv_list_delErr2REQUIRES_VIOLATION, __ldv_list_addErr4REQUIRES_VIOLATION, __ldv_list_addErr5REQUIRES_VIOLATION, __ldv_list_addErr0REQUIRES_VIOLATION, __ldv_list_addErr6REQUIRES_VIOLATION, __ldv_list_addErr1REQUIRES_VIOLATION, __ldv_list_addErr7REQUIRES_VIOLATION, __ldv_list_addErr2REQUIRES_VIOLATION, __ldv_list_addErr3REQUIRES_VIOLATION, ldv_dev_set_drvdataErr1REQUIRES_VIOLATION, ldv_dev_set_drvdataErr0REQUIRES_VIOLATION, ldv_atomic_sub_returnErr1REQUIRES_VIOLATION, ldv_atomic_sub_returnErr0REQUIRES_VIOLATION, ldv_atomic_sub_returnErr3REQUIRES_VIOLATION, ldv_atomic_sub_returnErr2REQUIRES_VIOLATION, ldv_list_add_tailErr0REQUIRES_VIOLATION, ldv_list_add_tailErr1REQUIRES_VIOLATION, ldv_dev_get_drvdataErr0REQUIRES_VIOLATION, ldv_dev_get_drvdataErr1REQUIRES_VIOLATION, ldv_msg_allocErr0REQUIRES_VIOLATION, ldv_msg_allocErr1REQUIRES_VIOLATION]=== [2018-11-28 13:02:56,279 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-28 13:02:56,280 INFO L82 PathProgramCache]: Analyzing trace with hash 256702444, now seen corresponding path program 1 times [2018-11-28 13:02:56,281 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-28 13:02:56,282 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-28 13:02:56,325 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 13:02:56,326 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-28 13:02:56,326 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 13:02:56,365 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-28 13:02:56,468 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-28 13:02:56,470 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-28 13:02:56,470 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2018-11-28 13:02:56,474 INFO L459 AbstractCegarLoop]: Interpolant automaton has 5 states [2018-11-28 13:02:56,486 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-11-28 13:02:56,486 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-11-28 13:02:56,489 INFO L87 Difference]: Start difference. First operand 177 states. Second operand 5 states. [2018-11-28 13:02:56,667 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-28 13:02:56,667 INFO L93 Difference]: Finished difference Result 157 states and 168 transitions. [2018-11-28 13:02:56,667 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2018-11-28 13:02:56,668 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 17 [2018-11-28 13:02:56,669 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-28 13:02:56,679 INFO L225 Difference]: With dead ends: 157 [2018-11-28 13:02:56,679 INFO L226 Difference]: Without dead ends: 154 [2018-11-28 13:02:56,680 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 4 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-11-28 13:02:56,692 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 154 states. [2018-11-28 13:02:56,716 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 154 to 148. [2018-11-28 13:02:56,717 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 148 states. [2018-11-28 13:02:56,720 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 148 states to 148 states and 159 transitions. [2018-11-28 13:02:56,721 INFO L78 Accepts]: Start accepts. Automaton has 148 states and 159 transitions. Word has length 17 [2018-11-28 13:02:56,722 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-28 13:02:56,722 INFO L480 AbstractCegarLoop]: Abstraction has 148 states and 159 transitions. [2018-11-28 13:02:56,722 INFO L481 AbstractCegarLoop]: Interpolant automaton has 5 states. [2018-11-28 13:02:56,722 INFO L276 IsEmpty]: Start isEmpty. Operand 148 states and 159 transitions. [2018-11-28 13:02:56,723 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 18 [2018-11-28 13:02:56,723 INFO L394 BasicCegarLoop]: Found error trace [2018-11-28 13:02:56,723 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-28 13:02:56,723 INFO L423 AbstractCegarLoop]: === Iteration 2 === [ldv_kref_initErr1REQUIRES_VIOLATION, ldv_kref_initErr0REQUIRES_VIOLATION, ldv_list_addErr1REQUIRES_VIOLATION, ldv_list_addErr0REQUIRES_VIOLATION, ldv_kobject_createErr0REQUIRES_VIOLATION, ldv_kobject_createErr1REQUIRES_VIOLATION, ldv_destroy_msgsErr3REQUIRES_VIOLATION, ldv_destroy_msgsErr2REQUIRES_VIOLATION, ldv_destroy_msgsErr1REQUIRES_VIOLATION, ldv_destroy_msgsErr0REQUIRES_VIOLATION, ldv_destroy_msgsErr5REQUIRES_VIOLATION, ldv_destroy_msgsErr4REQUIRES_VIOLATION, ldv_msg_fillErr1REQUIRES_VIOLATION, ldv_msg_fillErr4REQUIRES_VIOLATION, ldv_msg_fillErr0REQUIRES_VIOLATION, ldv_msg_fillErr5REQUIRES_VIOLATION, ldv_msg_fillErr3REQUIRES_VIOLATION, ldv_msg_fillErr2REQUIRES_VIOLATION, ldv_atomic_add_returnErr1REQUIRES_VIOLATION, ldv_atomic_add_returnErr0REQUIRES_VIOLATION, ldv_atomic_add_returnErr3REQUIRES_VIOLATION, ldv_atomic_add_returnErr2REQUIRES_VIOLATION, __ldv_list_delErr0REQUIRES_VIOLATION, __ldv_list_delErr1REQUIRES_VIOLATION, __ldv_list_delErr2REQUIRES_VIOLATION, __ldv_list_delErr3REQUIRES_VIOLATION, ldv_kobject_cleanupErr2ASSERT_VIOLATIONMEMORY_FREE, ldv_kobject_cleanupErr4ASSERT_VIOLATIONMEMORY_FREE, ldv_kobject_cleanupErr0REQUIRES_VIOLATION, ldv_kobject_cleanupErr5ASSERT_VIOLATIONMEMORY_FREE, ldv_kobject_cleanupErr1REQUIRES_VIOLATION, ldv_kobject_cleanupErr3ASSERT_VIOLATIONMEMORY_FREE, ldv_msg_freeErr2ASSERT_VIOLATIONMEMORY_FREE, ldv_msg_freeErr4ASSERT_VIOLATIONMEMORY_FREE, ldv_msg_freeErr5ASSERT_VIOLATIONMEMORY_FREE, ldv_msg_freeErr0REQUIRES_VIOLATION, ldv_msg_freeErr1REQUIRES_VIOLATION, ldv_msg_freeErr3ASSERT_VIOLATIONMEMORY_FREE, mainErr0ENSURES_VIOLATIONMEMORY_LEAK, LDV_INIT_LIST_HEADErr1REQUIRES_VIOLATION, LDV_INIT_LIST_HEADErr0REQUIRES_VIOLATION, LDV_INIT_LIST_HEADErr3REQUIRES_VIOLATION, LDV_INIT_LIST_HEADErr2REQUIRES_VIOLATION, ldv_list_delErr1REQUIRES_VIOLATION, ldv_list_delErr0REQUIRES_VIOLATION, ldv_list_delErr3REQUIRES_VIOLATION, ldv_list_delErr2REQUIRES_VIOLATION, __ldv_list_addErr4REQUIRES_VIOLATION, __ldv_list_addErr5REQUIRES_VIOLATION, __ldv_list_addErr0REQUIRES_VIOLATION, __ldv_list_addErr6REQUIRES_VIOLATION, __ldv_list_addErr1REQUIRES_VIOLATION, __ldv_list_addErr7REQUIRES_VIOLATION, __ldv_list_addErr2REQUIRES_VIOLATION, __ldv_list_addErr3REQUIRES_VIOLATION, ldv_dev_set_drvdataErr1REQUIRES_VIOLATION, ldv_dev_set_drvdataErr0REQUIRES_VIOLATION, ldv_atomic_sub_returnErr1REQUIRES_VIOLATION, ldv_atomic_sub_returnErr0REQUIRES_VIOLATION, ldv_atomic_sub_returnErr3REQUIRES_VIOLATION, ldv_atomic_sub_returnErr2REQUIRES_VIOLATION, ldv_list_add_tailErr0REQUIRES_VIOLATION, ldv_list_add_tailErr1REQUIRES_VIOLATION, ldv_dev_get_drvdataErr0REQUIRES_VIOLATION, ldv_dev_get_drvdataErr1REQUIRES_VIOLATION, ldv_msg_allocErr0REQUIRES_VIOLATION, ldv_msg_allocErr1REQUIRES_VIOLATION]=== [2018-11-28 13:02:56,724 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-28 13:02:56,724 INFO L82 PathProgramCache]: Analyzing trace with hash 256702445, now seen corresponding path program 1 times [2018-11-28 13:02:56,724 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-28 13:02:56,724 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-28 13:02:56,726 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 13:02:56,726 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-28 13:02:56,726 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 13:02:56,742 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-28 13:02:56,820 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-28 13:02:56,820 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-28 13:02:56,820 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-11-28 13:02:56,821 INFO L459 AbstractCegarLoop]: Interpolant automaton has 6 states [2018-11-28 13:02:56,821 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2018-11-28 13:02:56,821 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=21, Unknown=0, NotChecked=0, Total=30 [2018-11-28 13:02:56,822 INFO L87 Difference]: Start difference. First operand 148 states and 159 transitions. Second operand 6 states. [2018-11-28 13:02:56,938 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-28 13:02:56,938 INFO L93 Difference]: Finished difference Result 153 states and 164 transitions. [2018-11-28 13:02:56,938 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2018-11-28 13:02:56,938 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 17 [2018-11-28 13:02:56,939 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-28 13:02:56,940 INFO L225 Difference]: With dead ends: 153 [2018-11-28 13:02:56,940 INFO L226 Difference]: Without dead ends: 153 [2018-11-28 13:02:56,941 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 7 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=13, Invalid=29, Unknown=0, NotChecked=0, Total=42 [2018-11-28 13:02:56,941 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 153 states. [2018-11-28 13:02:56,949 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 153 to 148. [2018-11-28 13:02:56,949 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 148 states. [2018-11-28 13:02:56,951 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 148 states to 148 states and 158 transitions. [2018-11-28 13:02:56,951 INFO L78 Accepts]: Start accepts. Automaton has 148 states and 158 transitions. Word has length 17 [2018-11-28 13:02:56,951 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-28 13:02:56,951 INFO L480 AbstractCegarLoop]: Abstraction has 148 states and 158 transitions. [2018-11-28 13:02:56,951 INFO L481 AbstractCegarLoop]: Interpolant automaton has 6 states. [2018-11-28 13:02:56,951 INFO L276 IsEmpty]: Start isEmpty. Operand 148 states and 158 transitions. [2018-11-28 13:02:56,952 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 18 [2018-11-28 13:02:56,952 INFO L394 BasicCegarLoop]: Found error trace [2018-11-28 13:02:56,952 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-28 13:02:56,952 INFO L423 AbstractCegarLoop]: === Iteration 3 === [ldv_kref_initErr1REQUIRES_VIOLATION, ldv_kref_initErr0REQUIRES_VIOLATION, ldv_list_addErr1REQUIRES_VIOLATION, ldv_list_addErr0REQUIRES_VIOLATION, ldv_kobject_createErr0REQUIRES_VIOLATION, ldv_kobject_createErr1REQUIRES_VIOLATION, ldv_destroy_msgsErr3REQUIRES_VIOLATION, ldv_destroy_msgsErr2REQUIRES_VIOLATION, ldv_destroy_msgsErr1REQUIRES_VIOLATION, ldv_destroy_msgsErr0REQUIRES_VIOLATION, ldv_destroy_msgsErr5REQUIRES_VIOLATION, ldv_destroy_msgsErr4REQUIRES_VIOLATION, ldv_msg_fillErr1REQUIRES_VIOLATION, ldv_msg_fillErr4REQUIRES_VIOLATION, ldv_msg_fillErr0REQUIRES_VIOLATION, ldv_msg_fillErr5REQUIRES_VIOLATION, ldv_msg_fillErr3REQUIRES_VIOLATION, ldv_msg_fillErr2REQUIRES_VIOLATION, ldv_atomic_add_returnErr1REQUIRES_VIOLATION, ldv_atomic_add_returnErr0REQUIRES_VIOLATION, ldv_atomic_add_returnErr3REQUIRES_VIOLATION, ldv_atomic_add_returnErr2REQUIRES_VIOLATION, __ldv_list_delErr0REQUIRES_VIOLATION, __ldv_list_delErr1REQUIRES_VIOLATION, __ldv_list_delErr2REQUIRES_VIOLATION, __ldv_list_delErr3REQUIRES_VIOLATION, ldv_kobject_cleanupErr2ASSERT_VIOLATIONMEMORY_FREE, ldv_kobject_cleanupErr4ASSERT_VIOLATIONMEMORY_FREE, ldv_kobject_cleanupErr0REQUIRES_VIOLATION, ldv_kobject_cleanupErr5ASSERT_VIOLATIONMEMORY_FREE, ldv_kobject_cleanupErr1REQUIRES_VIOLATION, ldv_kobject_cleanupErr3ASSERT_VIOLATIONMEMORY_FREE, ldv_msg_freeErr2ASSERT_VIOLATIONMEMORY_FREE, ldv_msg_freeErr4ASSERT_VIOLATIONMEMORY_FREE, ldv_msg_freeErr5ASSERT_VIOLATIONMEMORY_FREE, ldv_msg_freeErr0REQUIRES_VIOLATION, ldv_msg_freeErr1REQUIRES_VIOLATION, ldv_msg_freeErr3ASSERT_VIOLATIONMEMORY_FREE, mainErr0ENSURES_VIOLATIONMEMORY_LEAK, LDV_INIT_LIST_HEADErr1REQUIRES_VIOLATION, LDV_INIT_LIST_HEADErr0REQUIRES_VIOLATION, LDV_INIT_LIST_HEADErr3REQUIRES_VIOLATION, LDV_INIT_LIST_HEADErr2REQUIRES_VIOLATION, ldv_list_delErr1REQUIRES_VIOLATION, ldv_list_delErr0REQUIRES_VIOLATION, ldv_list_delErr3REQUIRES_VIOLATION, ldv_list_delErr2REQUIRES_VIOLATION, __ldv_list_addErr4REQUIRES_VIOLATION, __ldv_list_addErr5REQUIRES_VIOLATION, __ldv_list_addErr0REQUIRES_VIOLATION, __ldv_list_addErr6REQUIRES_VIOLATION, __ldv_list_addErr1REQUIRES_VIOLATION, __ldv_list_addErr7REQUIRES_VIOLATION, __ldv_list_addErr2REQUIRES_VIOLATION, __ldv_list_addErr3REQUIRES_VIOLATION, ldv_dev_set_drvdataErr1REQUIRES_VIOLATION, ldv_dev_set_drvdataErr0REQUIRES_VIOLATION, ldv_atomic_sub_returnErr1REQUIRES_VIOLATION, ldv_atomic_sub_returnErr0REQUIRES_VIOLATION, ldv_atomic_sub_returnErr3REQUIRES_VIOLATION, ldv_atomic_sub_returnErr2REQUIRES_VIOLATION, ldv_list_add_tailErr0REQUIRES_VIOLATION, ldv_list_add_tailErr1REQUIRES_VIOLATION, ldv_dev_get_drvdataErr0REQUIRES_VIOLATION, ldv_dev_get_drvdataErr1REQUIRES_VIOLATION, ldv_msg_allocErr0REQUIRES_VIOLATION, ldv_msg_allocErr1REQUIRES_VIOLATION]=== [2018-11-28 13:02:56,952 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-28 13:02:56,953 INFO L82 PathProgramCache]: Analyzing trace with hash 285331595, now seen corresponding path program 1 times [2018-11-28 13:02:56,953 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-28 13:02:56,953 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-28 13:02:56,954 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 13:02:56,954 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-28 13:02:56,954 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 13:02:56,963 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-28 13:02:57,000 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-28 13:02:57,001 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-28 13:02:57,001 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-11-28 13:02:57,001 INFO L459 AbstractCegarLoop]: Interpolant automaton has 5 states [2018-11-28 13:02:57,001 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-11-28 13:02:57,001 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-11-28 13:02:57,001 INFO L87 Difference]: Start difference. First operand 148 states and 158 transitions. Second operand 5 states. [2018-11-28 13:02:57,013 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-28 13:02:57,014 INFO L93 Difference]: Finished difference Result 147 states and 155 transitions. [2018-11-28 13:02:57,014 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2018-11-28 13:02:57,014 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 17 [2018-11-28 13:02:57,014 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-28 13:02:57,015 INFO L225 Difference]: With dead ends: 147 [2018-11-28 13:02:57,015 INFO L226 Difference]: Without dead ends: 147 [2018-11-28 13:02:57,015 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 5 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-11-28 13:02:57,016 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 147 states. [2018-11-28 13:02:57,021 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 147 to 145. [2018-11-28 13:02:57,021 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 145 states. [2018-11-28 13:02:57,022 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 145 states to 145 states and 153 transitions. [2018-11-28 13:02:57,022 INFO L78 Accepts]: Start accepts. Automaton has 145 states and 153 transitions. Word has length 17 [2018-11-28 13:02:57,023 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-28 13:02:57,023 INFO L480 AbstractCegarLoop]: Abstraction has 145 states and 153 transitions. [2018-11-28 13:02:57,023 INFO L481 AbstractCegarLoop]: Interpolant automaton has 5 states. [2018-11-28 13:02:57,023 INFO L276 IsEmpty]: Start isEmpty. Operand 145 states and 153 transitions. [2018-11-28 13:02:57,023 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 30 [2018-11-28 13:02:57,023 INFO L394 BasicCegarLoop]: Found error trace [2018-11-28 13:02:57,024 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-28 13:02:57,024 INFO L423 AbstractCegarLoop]: === Iteration 4 === [ldv_kref_initErr1REQUIRES_VIOLATION, ldv_kref_initErr0REQUIRES_VIOLATION, ldv_list_addErr1REQUIRES_VIOLATION, ldv_list_addErr0REQUIRES_VIOLATION, ldv_kobject_createErr0REQUIRES_VIOLATION, ldv_kobject_createErr1REQUIRES_VIOLATION, ldv_destroy_msgsErr3REQUIRES_VIOLATION, ldv_destroy_msgsErr2REQUIRES_VIOLATION, ldv_destroy_msgsErr1REQUIRES_VIOLATION, ldv_destroy_msgsErr0REQUIRES_VIOLATION, ldv_destroy_msgsErr5REQUIRES_VIOLATION, ldv_destroy_msgsErr4REQUIRES_VIOLATION, ldv_msg_fillErr1REQUIRES_VIOLATION, ldv_msg_fillErr4REQUIRES_VIOLATION, ldv_msg_fillErr0REQUIRES_VIOLATION, ldv_msg_fillErr5REQUIRES_VIOLATION, ldv_msg_fillErr3REQUIRES_VIOLATION, ldv_msg_fillErr2REQUIRES_VIOLATION, ldv_atomic_add_returnErr1REQUIRES_VIOLATION, ldv_atomic_add_returnErr0REQUIRES_VIOLATION, ldv_atomic_add_returnErr3REQUIRES_VIOLATION, ldv_atomic_add_returnErr2REQUIRES_VIOLATION, __ldv_list_delErr0REQUIRES_VIOLATION, __ldv_list_delErr1REQUIRES_VIOLATION, __ldv_list_delErr2REQUIRES_VIOLATION, __ldv_list_delErr3REQUIRES_VIOLATION, ldv_kobject_cleanupErr2ASSERT_VIOLATIONMEMORY_FREE, ldv_kobject_cleanupErr4ASSERT_VIOLATIONMEMORY_FREE, ldv_kobject_cleanupErr0REQUIRES_VIOLATION, ldv_kobject_cleanupErr5ASSERT_VIOLATIONMEMORY_FREE, ldv_kobject_cleanupErr1REQUIRES_VIOLATION, ldv_kobject_cleanupErr3ASSERT_VIOLATIONMEMORY_FREE, ldv_msg_freeErr2ASSERT_VIOLATIONMEMORY_FREE, ldv_msg_freeErr4ASSERT_VIOLATIONMEMORY_FREE, ldv_msg_freeErr5ASSERT_VIOLATIONMEMORY_FREE, ldv_msg_freeErr0REQUIRES_VIOLATION, ldv_msg_freeErr1REQUIRES_VIOLATION, ldv_msg_freeErr3ASSERT_VIOLATIONMEMORY_FREE, mainErr0ENSURES_VIOLATIONMEMORY_LEAK, LDV_INIT_LIST_HEADErr1REQUIRES_VIOLATION, LDV_INIT_LIST_HEADErr0REQUIRES_VIOLATION, LDV_INIT_LIST_HEADErr3REQUIRES_VIOLATION, LDV_INIT_LIST_HEADErr2REQUIRES_VIOLATION, ldv_list_delErr1REQUIRES_VIOLATION, ldv_list_delErr0REQUIRES_VIOLATION, ldv_list_delErr3REQUIRES_VIOLATION, ldv_list_delErr2REQUIRES_VIOLATION, __ldv_list_addErr4REQUIRES_VIOLATION, __ldv_list_addErr5REQUIRES_VIOLATION, __ldv_list_addErr0REQUIRES_VIOLATION, __ldv_list_addErr6REQUIRES_VIOLATION, __ldv_list_addErr1REQUIRES_VIOLATION, __ldv_list_addErr7REQUIRES_VIOLATION, __ldv_list_addErr2REQUIRES_VIOLATION, __ldv_list_addErr3REQUIRES_VIOLATION, ldv_dev_set_drvdataErr1REQUIRES_VIOLATION, ldv_dev_set_drvdataErr0REQUIRES_VIOLATION, ldv_atomic_sub_returnErr1REQUIRES_VIOLATION, ldv_atomic_sub_returnErr0REQUIRES_VIOLATION, ldv_atomic_sub_returnErr3REQUIRES_VIOLATION, ldv_atomic_sub_returnErr2REQUIRES_VIOLATION, ldv_list_add_tailErr0REQUIRES_VIOLATION, ldv_list_add_tailErr1REQUIRES_VIOLATION, ldv_dev_get_drvdataErr0REQUIRES_VIOLATION, ldv_dev_get_drvdataErr1REQUIRES_VIOLATION, ldv_msg_allocErr0REQUIRES_VIOLATION, ldv_msg_allocErr1REQUIRES_VIOLATION]=== [2018-11-28 13:02:57,024 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-28 13:02:57,024 INFO L82 PathProgramCache]: Analyzing trace with hash 1651811587, now seen corresponding path program 1 times [2018-11-28 13:02:57,024 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-28 13:02:57,025 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-28 13:02:57,026 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 13:02:57,026 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-28 13:02:57,026 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 13:02:57,037 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-28 13:02:57,071 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-28 13:02:57,071 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-28 13:02:57,071 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-11-28 13:02:57,072 INFO L459 AbstractCegarLoop]: Interpolant automaton has 5 states [2018-11-28 13:02:57,072 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-11-28 13:02:57,072 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-11-28 13:02:57,072 INFO L87 Difference]: Start difference. First operand 145 states and 153 transitions. Second operand 5 states. [2018-11-28 13:02:57,087 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-28 13:02:57,088 INFO L93 Difference]: Finished difference Result 147 states and 154 transitions. [2018-11-28 13:02:57,093 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2018-11-28 13:02:57,093 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 29 [2018-11-28 13:02:57,093 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-28 13:02:57,094 INFO L225 Difference]: With dead ends: 147 [2018-11-28 13:02:57,094 INFO L226 Difference]: Without dead ends: 147 [2018-11-28 13:02:57,095 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 5 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-11-28 13:02:57,095 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 147 states. [2018-11-28 13:02:57,101 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 147 to 145. [2018-11-28 13:02:57,101 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 145 states. [2018-11-28 13:02:57,102 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 145 states to 145 states and 152 transitions. [2018-11-28 13:02:57,102 INFO L78 Accepts]: Start accepts. Automaton has 145 states and 152 transitions. Word has length 29 [2018-11-28 13:02:57,102 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-28 13:02:57,102 INFO L480 AbstractCegarLoop]: Abstraction has 145 states and 152 transitions. [2018-11-28 13:02:57,103 INFO L481 AbstractCegarLoop]: Interpolant automaton has 5 states. [2018-11-28 13:02:57,103 INFO L276 IsEmpty]: Start isEmpty. Operand 145 states and 152 transitions. [2018-11-28 13:02:57,103 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 30 [2018-11-28 13:02:57,103 INFO L394 BasicCegarLoop]: Found error trace [2018-11-28 13:02:57,104 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-28 13:02:57,104 INFO L423 AbstractCegarLoop]: === Iteration 5 === [ldv_kref_initErr1REQUIRES_VIOLATION, ldv_kref_initErr0REQUIRES_VIOLATION, ldv_list_addErr1REQUIRES_VIOLATION, ldv_list_addErr0REQUIRES_VIOLATION, ldv_kobject_createErr0REQUIRES_VIOLATION, ldv_kobject_createErr1REQUIRES_VIOLATION, ldv_destroy_msgsErr3REQUIRES_VIOLATION, ldv_destroy_msgsErr2REQUIRES_VIOLATION, ldv_destroy_msgsErr1REQUIRES_VIOLATION, ldv_destroy_msgsErr0REQUIRES_VIOLATION, ldv_destroy_msgsErr5REQUIRES_VIOLATION, ldv_destroy_msgsErr4REQUIRES_VIOLATION, ldv_msg_fillErr1REQUIRES_VIOLATION, ldv_msg_fillErr4REQUIRES_VIOLATION, ldv_msg_fillErr0REQUIRES_VIOLATION, ldv_msg_fillErr5REQUIRES_VIOLATION, ldv_msg_fillErr3REQUIRES_VIOLATION, ldv_msg_fillErr2REQUIRES_VIOLATION, ldv_atomic_add_returnErr1REQUIRES_VIOLATION, ldv_atomic_add_returnErr0REQUIRES_VIOLATION, ldv_atomic_add_returnErr3REQUIRES_VIOLATION, ldv_atomic_add_returnErr2REQUIRES_VIOLATION, __ldv_list_delErr0REQUIRES_VIOLATION, __ldv_list_delErr1REQUIRES_VIOLATION, __ldv_list_delErr2REQUIRES_VIOLATION, __ldv_list_delErr3REQUIRES_VIOLATION, ldv_kobject_cleanupErr2ASSERT_VIOLATIONMEMORY_FREE, ldv_kobject_cleanupErr4ASSERT_VIOLATIONMEMORY_FREE, ldv_kobject_cleanupErr0REQUIRES_VIOLATION, ldv_kobject_cleanupErr5ASSERT_VIOLATIONMEMORY_FREE, ldv_kobject_cleanupErr1REQUIRES_VIOLATION, ldv_kobject_cleanupErr3ASSERT_VIOLATIONMEMORY_FREE, ldv_msg_freeErr2ASSERT_VIOLATIONMEMORY_FREE, ldv_msg_freeErr4ASSERT_VIOLATIONMEMORY_FREE, ldv_msg_freeErr5ASSERT_VIOLATIONMEMORY_FREE, ldv_msg_freeErr0REQUIRES_VIOLATION, ldv_msg_freeErr1REQUIRES_VIOLATION, ldv_msg_freeErr3ASSERT_VIOLATIONMEMORY_FREE, mainErr0ENSURES_VIOLATIONMEMORY_LEAK, LDV_INIT_LIST_HEADErr1REQUIRES_VIOLATION, LDV_INIT_LIST_HEADErr0REQUIRES_VIOLATION, LDV_INIT_LIST_HEADErr3REQUIRES_VIOLATION, LDV_INIT_LIST_HEADErr2REQUIRES_VIOLATION, ldv_list_delErr1REQUIRES_VIOLATION, ldv_list_delErr0REQUIRES_VIOLATION, ldv_list_delErr3REQUIRES_VIOLATION, ldv_list_delErr2REQUIRES_VIOLATION, __ldv_list_addErr4REQUIRES_VIOLATION, __ldv_list_addErr5REQUIRES_VIOLATION, __ldv_list_addErr0REQUIRES_VIOLATION, __ldv_list_addErr6REQUIRES_VIOLATION, __ldv_list_addErr1REQUIRES_VIOLATION, __ldv_list_addErr7REQUIRES_VIOLATION, __ldv_list_addErr2REQUIRES_VIOLATION, __ldv_list_addErr3REQUIRES_VIOLATION, ldv_dev_set_drvdataErr1REQUIRES_VIOLATION, ldv_dev_set_drvdataErr0REQUIRES_VIOLATION, ldv_atomic_sub_returnErr1REQUIRES_VIOLATION, ldv_atomic_sub_returnErr0REQUIRES_VIOLATION, ldv_atomic_sub_returnErr3REQUIRES_VIOLATION, ldv_atomic_sub_returnErr2REQUIRES_VIOLATION, ldv_list_add_tailErr0REQUIRES_VIOLATION, ldv_list_add_tailErr1REQUIRES_VIOLATION, ldv_dev_get_drvdataErr0REQUIRES_VIOLATION, ldv_dev_get_drvdataErr1REQUIRES_VIOLATION, ldv_msg_allocErr0REQUIRES_VIOLATION, ldv_msg_allocErr1REQUIRES_VIOLATION]=== [2018-11-28 13:02:57,104 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-28 13:02:57,104 INFO L82 PathProgramCache]: Analyzing trace with hash 654739234, now seen corresponding path program 1 times [2018-11-28 13:02:57,104 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-28 13:02:57,104 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-28 13:02:57,106 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 13:02:57,106 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-28 13:02:57,106 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 13:02:57,116 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-28 13:02:57,208 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-28 13:02:57,208 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-28 13:02:57,208 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [9] imperfect sequences [] total 9 [2018-11-28 13:02:57,209 INFO L459 AbstractCegarLoop]: Interpolant automaton has 9 states [2018-11-28 13:02:57,209 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 9 interpolants. [2018-11-28 13:02:57,209 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=15, Invalid=57, Unknown=0, NotChecked=0, Total=72 [2018-11-28 13:02:57,210 INFO L87 Difference]: Start difference. First operand 145 states and 152 transitions. Second operand 9 states. [2018-11-28 13:02:57,274 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-28 13:02:57,274 INFO L93 Difference]: Finished difference Result 165 states and 173 transitions. [2018-11-28 13:02:57,274 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 10 states. [2018-11-28 13:02:57,274 INFO L78 Accepts]: Start accepts. Automaton has 9 states. Word has length 29 [2018-11-28 13:02:57,275 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-28 13:02:57,276 INFO L225 Difference]: With dead ends: 165 [2018-11-28 13:02:57,276 INFO L226 Difference]: Without dead ends: 165 [2018-11-28 13:02:57,276 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 11 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 9 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=23, Invalid=87, Unknown=0, NotChecked=0, Total=110 [2018-11-28 13:02:57,276 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 165 states. [2018-11-28 13:02:57,282 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 165 to 159. [2018-11-28 13:02:57,282 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 159 states. [2018-11-28 13:02:57,283 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 159 states to 159 states and 166 transitions. [2018-11-28 13:02:57,284 INFO L78 Accepts]: Start accepts. Automaton has 159 states and 166 transitions. Word has length 29 [2018-11-28 13:02:57,284 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-28 13:02:57,284 INFO L480 AbstractCegarLoop]: Abstraction has 159 states and 166 transitions. [2018-11-28 13:02:57,284 INFO L481 AbstractCegarLoop]: Interpolant automaton has 9 states. [2018-11-28 13:02:57,284 INFO L276 IsEmpty]: Start isEmpty. Operand 159 states and 166 transitions. [2018-11-28 13:02:57,285 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 33 [2018-11-28 13:02:57,285 INFO L394 BasicCegarLoop]: Found error trace [2018-11-28 13:02:57,285 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-28 13:02:57,285 INFO L423 AbstractCegarLoop]: === Iteration 6 === [ldv_kref_initErr1REQUIRES_VIOLATION, ldv_kref_initErr0REQUIRES_VIOLATION, ldv_list_addErr1REQUIRES_VIOLATION, ldv_list_addErr0REQUIRES_VIOLATION, ldv_kobject_createErr0REQUIRES_VIOLATION, ldv_kobject_createErr1REQUIRES_VIOLATION, ldv_destroy_msgsErr3REQUIRES_VIOLATION, ldv_destroy_msgsErr2REQUIRES_VIOLATION, ldv_destroy_msgsErr1REQUIRES_VIOLATION, ldv_destroy_msgsErr0REQUIRES_VIOLATION, ldv_destroy_msgsErr5REQUIRES_VIOLATION, ldv_destroy_msgsErr4REQUIRES_VIOLATION, ldv_msg_fillErr1REQUIRES_VIOLATION, ldv_msg_fillErr4REQUIRES_VIOLATION, ldv_msg_fillErr0REQUIRES_VIOLATION, ldv_msg_fillErr5REQUIRES_VIOLATION, ldv_msg_fillErr3REQUIRES_VIOLATION, ldv_msg_fillErr2REQUIRES_VIOLATION, ldv_atomic_add_returnErr1REQUIRES_VIOLATION, ldv_atomic_add_returnErr0REQUIRES_VIOLATION, ldv_atomic_add_returnErr3REQUIRES_VIOLATION, ldv_atomic_add_returnErr2REQUIRES_VIOLATION, __ldv_list_delErr0REQUIRES_VIOLATION, __ldv_list_delErr1REQUIRES_VIOLATION, __ldv_list_delErr2REQUIRES_VIOLATION, __ldv_list_delErr3REQUIRES_VIOLATION, ldv_kobject_cleanupErr2ASSERT_VIOLATIONMEMORY_FREE, ldv_kobject_cleanupErr4ASSERT_VIOLATIONMEMORY_FREE, ldv_kobject_cleanupErr0REQUIRES_VIOLATION, ldv_kobject_cleanupErr5ASSERT_VIOLATIONMEMORY_FREE, ldv_kobject_cleanupErr1REQUIRES_VIOLATION, ldv_kobject_cleanupErr3ASSERT_VIOLATIONMEMORY_FREE, ldv_msg_freeErr2ASSERT_VIOLATIONMEMORY_FREE, ldv_msg_freeErr4ASSERT_VIOLATIONMEMORY_FREE, ldv_msg_freeErr5ASSERT_VIOLATIONMEMORY_FREE, ldv_msg_freeErr0REQUIRES_VIOLATION, ldv_msg_freeErr1REQUIRES_VIOLATION, ldv_msg_freeErr3ASSERT_VIOLATIONMEMORY_FREE, mainErr0ENSURES_VIOLATIONMEMORY_LEAK, LDV_INIT_LIST_HEADErr1REQUIRES_VIOLATION, LDV_INIT_LIST_HEADErr0REQUIRES_VIOLATION, LDV_INIT_LIST_HEADErr3REQUIRES_VIOLATION, LDV_INIT_LIST_HEADErr2REQUIRES_VIOLATION, ldv_list_delErr1REQUIRES_VIOLATION, ldv_list_delErr0REQUIRES_VIOLATION, ldv_list_delErr3REQUIRES_VIOLATION, ldv_list_delErr2REQUIRES_VIOLATION, __ldv_list_addErr4REQUIRES_VIOLATION, __ldv_list_addErr5REQUIRES_VIOLATION, __ldv_list_addErr0REQUIRES_VIOLATION, __ldv_list_addErr6REQUIRES_VIOLATION, __ldv_list_addErr1REQUIRES_VIOLATION, __ldv_list_addErr7REQUIRES_VIOLATION, __ldv_list_addErr2REQUIRES_VIOLATION, __ldv_list_addErr3REQUIRES_VIOLATION, ldv_dev_set_drvdataErr1REQUIRES_VIOLATION, ldv_dev_set_drvdataErr0REQUIRES_VIOLATION, ldv_atomic_sub_returnErr1REQUIRES_VIOLATION, ldv_atomic_sub_returnErr0REQUIRES_VIOLATION, ldv_atomic_sub_returnErr3REQUIRES_VIOLATION, ldv_atomic_sub_returnErr2REQUIRES_VIOLATION, ldv_list_add_tailErr0REQUIRES_VIOLATION, ldv_list_add_tailErr1REQUIRES_VIOLATION, ldv_dev_get_drvdataErr0REQUIRES_VIOLATION, ldv_dev_get_drvdataErr1REQUIRES_VIOLATION, ldv_msg_allocErr0REQUIRES_VIOLATION, ldv_msg_allocErr1REQUIRES_VIOLATION]=== [2018-11-28 13:02:57,286 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-28 13:02:57,286 INFO L82 PathProgramCache]: Analyzing trace with hash 1700792364, now seen corresponding path program 1 times [2018-11-28 13:02:57,286 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-28 13:02:57,286 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-28 13:02:57,287 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 13:02:57,287 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-28 13:02:57,287 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 13:02:57,295 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-28 13:02:57,361 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-28 13:02:57,361 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-28 13:02:57,362 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [10] imperfect sequences [] total 10 [2018-11-28 13:02:57,362 INFO L459 AbstractCegarLoop]: Interpolant automaton has 11 states [2018-11-28 13:02:57,362 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 11 interpolants. [2018-11-28 13:02:57,362 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=19, Invalid=91, Unknown=0, NotChecked=0, Total=110 [2018-11-28 13:02:57,362 INFO L87 Difference]: Start difference. First operand 159 states and 166 transitions. Second operand 11 states. [2018-11-28 13:02:57,575 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-28 13:02:57,575 INFO L93 Difference]: Finished difference Result 158 states and 165 transitions. [2018-11-28 13:02:57,575 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 11 states. [2018-11-28 13:02:57,575 INFO L78 Accepts]: Start accepts. Automaton has 11 states. Word has length 32 [2018-11-28 13:02:57,575 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-28 13:02:57,576 INFO L225 Difference]: With dead ends: 158 [2018-11-28 13:02:57,576 INFO L226 Difference]: Without dead ends: 158 [2018-11-28 13:02:57,576 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 13 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 12 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 3 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=31, Invalid=151, Unknown=0, NotChecked=0, Total=182 [2018-11-28 13:02:57,577 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 158 states. [2018-11-28 13:02:57,582 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 158 to 158. [2018-11-28 13:02:57,582 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 158 states. [2018-11-28 13:02:57,583 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 158 states to 158 states and 165 transitions. [2018-11-28 13:02:57,583 INFO L78 Accepts]: Start accepts. Automaton has 158 states and 165 transitions. Word has length 32 [2018-11-28 13:02:57,583 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-28 13:02:57,583 INFO L480 AbstractCegarLoop]: Abstraction has 158 states and 165 transitions. [2018-11-28 13:02:57,583 INFO L481 AbstractCegarLoop]: Interpolant automaton has 11 states. [2018-11-28 13:02:57,583 INFO L276 IsEmpty]: Start isEmpty. Operand 158 states and 165 transitions. [2018-11-28 13:02:57,584 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 33 [2018-11-28 13:02:57,584 INFO L394 BasicCegarLoop]: Found error trace [2018-11-28 13:02:57,584 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-28 13:02:57,584 INFO L423 AbstractCegarLoop]: === Iteration 7 === [ldv_kref_initErr1REQUIRES_VIOLATION, ldv_kref_initErr0REQUIRES_VIOLATION, ldv_list_addErr1REQUIRES_VIOLATION, ldv_list_addErr0REQUIRES_VIOLATION, ldv_kobject_createErr0REQUIRES_VIOLATION, ldv_kobject_createErr1REQUIRES_VIOLATION, ldv_destroy_msgsErr3REQUIRES_VIOLATION, ldv_destroy_msgsErr2REQUIRES_VIOLATION, ldv_destroy_msgsErr1REQUIRES_VIOLATION, ldv_destroy_msgsErr0REQUIRES_VIOLATION, ldv_destroy_msgsErr5REQUIRES_VIOLATION, ldv_destroy_msgsErr4REQUIRES_VIOLATION, ldv_msg_fillErr1REQUIRES_VIOLATION, ldv_msg_fillErr4REQUIRES_VIOLATION, ldv_msg_fillErr0REQUIRES_VIOLATION, ldv_msg_fillErr5REQUIRES_VIOLATION, ldv_msg_fillErr3REQUIRES_VIOLATION, ldv_msg_fillErr2REQUIRES_VIOLATION, ldv_atomic_add_returnErr1REQUIRES_VIOLATION, ldv_atomic_add_returnErr0REQUIRES_VIOLATION, ldv_atomic_add_returnErr3REQUIRES_VIOLATION, ldv_atomic_add_returnErr2REQUIRES_VIOLATION, __ldv_list_delErr0REQUIRES_VIOLATION, __ldv_list_delErr1REQUIRES_VIOLATION, __ldv_list_delErr2REQUIRES_VIOLATION, __ldv_list_delErr3REQUIRES_VIOLATION, ldv_kobject_cleanupErr2ASSERT_VIOLATIONMEMORY_FREE, ldv_kobject_cleanupErr4ASSERT_VIOLATIONMEMORY_FREE, ldv_kobject_cleanupErr0REQUIRES_VIOLATION, ldv_kobject_cleanupErr5ASSERT_VIOLATIONMEMORY_FREE, ldv_kobject_cleanupErr1REQUIRES_VIOLATION, ldv_kobject_cleanupErr3ASSERT_VIOLATIONMEMORY_FREE, ldv_msg_freeErr2ASSERT_VIOLATIONMEMORY_FREE, ldv_msg_freeErr4ASSERT_VIOLATIONMEMORY_FREE, ldv_msg_freeErr5ASSERT_VIOLATIONMEMORY_FREE, ldv_msg_freeErr0REQUIRES_VIOLATION, ldv_msg_freeErr1REQUIRES_VIOLATION, ldv_msg_freeErr3ASSERT_VIOLATIONMEMORY_FREE, mainErr0ENSURES_VIOLATIONMEMORY_LEAK, LDV_INIT_LIST_HEADErr1REQUIRES_VIOLATION, LDV_INIT_LIST_HEADErr0REQUIRES_VIOLATION, LDV_INIT_LIST_HEADErr3REQUIRES_VIOLATION, LDV_INIT_LIST_HEADErr2REQUIRES_VIOLATION, ldv_list_delErr1REQUIRES_VIOLATION, ldv_list_delErr0REQUIRES_VIOLATION, ldv_list_delErr3REQUIRES_VIOLATION, ldv_list_delErr2REQUIRES_VIOLATION, __ldv_list_addErr4REQUIRES_VIOLATION, __ldv_list_addErr5REQUIRES_VIOLATION, __ldv_list_addErr0REQUIRES_VIOLATION, __ldv_list_addErr6REQUIRES_VIOLATION, __ldv_list_addErr1REQUIRES_VIOLATION, __ldv_list_addErr7REQUIRES_VIOLATION, __ldv_list_addErr2REQUIRES_VIOLATION, __ldv_list_addErr3REQUIRES_VIOLATION, ldv_dev_set_drvdataErr1REQUIRES_VIOLATION, ldv_dev_set_drvdataErr0REQUIRES_VIOLATION, ldv_atomic_sub_returnErr1REQUIRES_VIOLATION, ldv_atomic_sub_returnErr0REQUIRES_VIOLATION, ldv_atomic_sub_returnErr3REQUIRES_VIOLATION, ldv_atomic_sub_returnErr2REQUIRES_VIOLATION, ldv_list_add_tailErr0REQUIRES_VIOLATION, ldv_list_add_tailErr1REQUIRES_VIOLATION, ldv_dev_get_drvdataErr0REQUIRES_VIOLATION, ldv_dev_get_drvdataErr1REQUIRES_VIOLATION, ldv_msg_allocErr0REQUIRES_VIOLATION, ldv_msg_allocErr1REQUIRES_VIOLATION]=== [2018-11-28 13:02:57,585 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-28 13:02:57,585 INFO L82 PathProgramCache]: Analyzing trace with hash 1700792365, now seen corresponding path program 1 times [2018-11-28 13:02:57,585 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-28 13:02:57,585 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-28 13:02:57,586 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 13:02:57,586 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-28 13:02:57,586 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 13:02:57,595 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-28 13:02:57,612 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-28 13:02:57,612 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-28 13:02:57,613 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2018-11-28 13:02:57,613 INFO L459 AbstractCegarLoop]: Interpolant automaton has 4 states [2018-11-28 13:02:57,613 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2018-11-28 13:02:57,613 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2018-11-28 13:02:57,613 INFO L87 Difference]: Start difference. First operand 158 states and 165 transitions. Second operand 4 states. [2018-11-28 13:02:57,637 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-28 13:02:57,638 INFO L93 Difference]: Finished difference Result 161 states and 168 transitions. [2018-11-28 13:02:57,639 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2018-11-28 13:02:57,639 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 32 [2018-11-28 13:02:57,639 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-28 13:02:57,640 INFO L225 Difference]: With dead ends: 161 [2018-11-28 13:02:57,640 INFO L226 Difference]: Without dead ends: 159 [2018-11-28 13:02:57,641 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 5 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2018-11-28 13:02:57,641 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 159 states. [2018-11-28 13:02:57,645 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 159 to 159. [2018-11-28 13:02:57,645 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 159 states. [2018-11-28 13:02:57,646 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 159 states to 159 states and 166 transitions. [2018-11-28 13:02:57,646 INFO L78 Accepts]: Start accepts. Automaton has 159 states and 166 transitions. Word has length 32 [2018-11-28 13:02:57,646 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-28 13:02:57,647 INFO L480 AbstractCegarLoop]: Abstraction has 159 states and 166 transitions. [2018-11-28 13:02:57,647 INFO L481 AbstractCegarLoop]: Interpolant automaton has 4 states. [2018-11-28 13:02:57,647 INFO L276 IsEmpty]: Start isEmpty. Operand 159 states and 166 transitions. [2018-11-28 13:02:57,648 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 34 [2018-11-28 13:02:57,648 INFO L394 BasicCegarLoop]: Found error trace [2018-11-28 13:02:57,648 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-28 13:02:57,648 INFO L423 AbstractCegarLoop]: === Iteration 8 === [ldv_kref_initErr1REQUIRES_VIOLATION, ldv_kref_initErr0REQUIRES_VIOLATION, ldv_list_addErr1REQUIRES_VIOLATION, ldv_list_addErr0REQUIRES_VIOLATION, ldv_kobject_createErr0REQUIRES_VIOLATION, ldv_kobject_createErr1REQUIRES_VIOLATION, ldv_destroy_msgsErr3REQUIRES_VIOLATION, ldv_destroy_msgsErr2REQUIRES_VIOLATION, ldv_destroy_msgsErr1REQUIRES_VIOLATION, ldv_destroy_msgsErr0REQUIRES_VIOLATION, ldv_destroy_msgsErr5REQUIRES_VIOLATION, ldv_destroy_msgsErr4REQUIRES_VIOLATION, ldv_msg_fillErr1REQUIRES_VIOLATION, ldv_msg_fillErr4REQUIRES_VIOLATION, ldv_msg_fillErr0REQUIRES_VIOLATION, ldv_msg_fillErr5REQUIRES_VIOLATION, ldv_msg_fillErr3REQUIRES_VIOLATION, ldv_msg_fillErr2REQUIRES_VIOLATION, ldv_atomic_add_returnErr1REQUIRES_VIOLATION, ldv_atomic_add_returnErr0REQUIRES_VIOLATION, ldv_atomic_add_returnErr3REQUIRES_VIOLATION, ldv_atomic_add_returnErr2REQUIRES_VIOLATION, __ldv_list_delErr0REQUIRES_VIOLATION, __ldv_list_delErr1REQUIRES_VIOLATION, __ldv_list_delErr2REQUIRES_VIOLATION, __ldv_list_delErr3REQUIRES_VIOLATION, ldv_kobject_cleanupErr2ASSERT_VIOLATIONMEMORY_FREE, ldv_kobject_cleanupErr4ASSERT_VIOLATIONMEMORY_FREE, ldv_kobject_cleanupErr0REQUIRES_VIOLATION, ldv_kobject_cleanupErr5ASSERT_VIOLATIONMEMORY_FREE, ldv_kobject_cleanupErr1REQUIRES_VIOLATION, ldv_kobject_cleanupErr3ASSERT_VIOLATIONMEMORY_FREE, ldv_msg_freeErr2ASSERT_VIOLATIONMEMORY_FREE, ldv_msg_freeErr4ASSERT_VIOLATIONMEMORY_FREE, ldv_msg_freeErr5ASSERT_VIOLATIONMEMORY_FREE, ldv_msg_freeErr0REQUIRES_VIOLATION, ldv_msg_freeErr1REQUIRES_VIOLATION, ldv_msg_freeErr3ASSERT_VIOLATIONMEMORY_FREE, mainErr0ENSURES_VIOLATIONMEMORY_LEAK, LDV_INIT_LIST_HEADErr1REQUIRES_VIOLATION, LDV_INIT_LIST_HEADErr0REQUIRES_VIOLATION, LDV_INIT_LIST_HEADErr3REQUIRES_VIOLATION, LDV_INIT_LIST_HEADErr2REQUIRES_VIOLATION, ldv_list_delErr1REQUIRES_VIOLATION, ldv_list_delErr0REQUIRES_VIOLATION, ldv_list_delErr3REQUIRES_VIOLATION, ldv_list_delErr2REQUIRES_VIOLATION, __ldv_list_addErr4REQUIRES_VIOLATION, __ldv_list_addErr5REQUIRES_VIOLATION, __ldv_list_addErr0REQUIRES_VIOLATION, __ldv_list_addErr6REQUIRES_VIOLATION, __ldv_list_addErr1REQUIRES_VIOLATION, __ldv_list_addErr7REQUIRES_VIOLATION, __ldv_list_addErr2REQUIRES_VIOLATION, __ldv_list_addErr3REQUIRES_VIOLATION, ldv_dev_set_drvdataErr1REQUIRES_VIOLATION, ldv_dev_set_drvdataErr0REQUIRES_VIOLATION, ldv_atomic_sub_returnErr1REQUIRES_VIOLATION, ldv_atomic_sub_returnErr0REQUIRES_VIOLATION, ldv_atomic_sub_returnErr3REQUIRES_VIOLATION, ldv_atomic_sub_returnErr2REQUIRES_VIOLATION, ldv_list_add_tailErr0REQUIRES_VIOLATION, ldv_list_add_tailErr1REQUIRES_VIOLATION, ldv_dev_get_drvdataErr0REQUIRES_VIOLATION, ldv_dev_get_drvdataErr1REQUIRES_VIOLATION, ldv_msg_allocErr0REQUIRES_VIOLATION, ldv_msg_allocErr1REQUIRES_VIOLATION]=== [2018-11-28 13:02:57,648 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-28 13:02:57,649 INFO L82 PathProgramCache]: Analyzing trace with hash 1635244048, now seen corresponding path program 1 times [2018-11-28 13:02:57,649 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-28 13:02:57,649 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-28 13:02:57,650 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 13:02:57,650 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-28 13:02:57,650 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 13:02:57,660 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-28 13:02:57,697 INFO L134 CoverageAnalysis]: Checked inductivity of 1 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-28 13:02:57,697 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-28 13:02:57,697 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_a5616418-4a25-482a-a0cb-6eefe8bc17e5/bin-2019/uautomizer/z3 Starting monitored process 2 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 2 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-28 13:02:57,723 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-28 13:02:57,765 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-28 13:02:57,772 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-28 13:02:57,818 INFO L134 CoverageAnalysis]: Checked inductivity of 1 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-28 13:02:57,844 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-11-28 13:02:57,844 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [5, 5] total 6 [2018-11-28 13:02:57,844 INFO L459 AbstractCegarLoop]: Interpolant automaton has 6 states [2018-11-28 13:02:57,844 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2018-11-28 13:02:57,845 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=12, Invalid=18, Unknown=0, NotChecked=0, Total=30 [2018-11-28 13:02:57,845 INFO L87 Difference]: Start difference. First operand 159 states and 166 transitions. Second operand 6 states. [2018-11-28 13:02:57,870 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-28 13:02:57,870 INFO L93 Difference]: Finished difference Result 162 states and 169 transitions. [2018-11-28 13:02:57,870 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2018-11-28 13:02:57,870 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 33 [2018-11-28 13:02:57,870 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-28 13:02:57,871 INFO L225 Difference]: With dead ends: 162 [2018-11-28 13:02:57,871 INFO L226 Difference]: Without dead ends: 160 [2018-11-28 13:02:57,871 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 38 GetRequests, 33 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=16, Invalid=26, Unknown=0, NotChecked=0, Total=42 [2018-11-28 13:02:57,871 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 160 states. [2018-11-28 13:02:57,875 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 160 to 160. [2018-11-28 13:02:57,875 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 160 states. [2018-11-28 13:02:57,876 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 160 states to 160 states and 167 transitions. [2018-11-28 13:02:57,876 INFO L78 Accepts]: Start accepts. Automaton has 160 states and 167 transitions. Word has length 33 [2018-11-28 13:02:57,876 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-28 13:02:57,876 INFO L480 AbstractCegarLoop]: Abstraction has 160 states and 167 transitions. [2018-11-28 13:02:57,876 INFO L481 AbstractCegarLoop]: Interpolant automaton has 6 states. [2018-11-28 13:02:57,877 INFO L276 IsEmpty]: Start isEmpty. Operand 160 states and 167 transitions. [2018-11-28 13:02:57,877 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 35 [2018-11-28 13:02:57,877 INFO L394 BasicCegarLoop]: Found error trace [2018-11-28 13:02:57,877 INFO L402 BasicCegarLoop]: trace histogram [2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-28 13:02:57,878 INFO L423 AbstractCegarLoop]: === Iteration 9 === [ldv_kref_initErr1REQUIRES_VIOLATION, ldv_kref_initErr0REQUIRES_VIOLATION, ldv_list_addErr1REQUIRES_VIOLATION, ldv_list_addErr0REQUIRES_VIOLATION, ldv_kobject_createErr0REQUIRES_VIOLATION, ldv_kobject_createErr1REQUIRES_VIOLATION, ldv_destroy_msgsErr3REQUIRES_VIOLATION, ldv_destroy_msgsErr2REQUIRES_VIOLATION, ldv_destroy_msgsErr1REQUIRES_VIOLATION, ldv_destroy_msgsErr0REQUIRES_VIOLATION, ldv_destroy_msgsErr5REQUIRES_VIOLATION, ldv_destroy_msgsErr4REQUIRES_VIOLATION, ldv_msg_fillErr1REQUIRES_VIOLATION, ldv_msg_fillErr4REQUIRES_VIOLATION, ldv_msg_fillErr0REQUIRES_VIOLATION, ldv_msg_fillErr5REQUIRES_VIOLATION, ldv_msg_fillErr3REQUIRES_VIOLATION, ldv_msg_fillErr2REQUIRES_VIOLATION, ldv_atomic_add_returnErr1REQUIRES_VIOLATION, ldv_atomic_add_returnErr0REQUIRES_VIOLATION, ldv_atomic_add_returnErr3REQUIRES_VIOLATION, ldv_atomic_add_returnErr2REQUIRES_VIOLATION, __ldv_list_delErr0REQUIRES_VIOLATION, __ldv_list_delErr1REQUIRES_VIOLATION, __ldv_list_delErr2REQUIRES_VIOLATION, __ldv_list_delErr3REQUIRES_VIOLATION, ldv_kobject_cleanupErr2ASSERT_VIOLATIONMEMORY_FREE, ldv_kobject_cleanupErr4ASSERT_VIOLATIONMEMORY_FREE, ldv_kobject_cleanupErr0REQUIRES_VIOLATION, ldv_kobject_cleanupErr5ASSERT_VIOLATIONMEMORY_FREE, ldv_kobject_cleanupErr1REQUIRES_VIOLATION, ldv_kobject_cleanupErr3ASSERT_VIOLATIONMEMORY_FREE, ldv_msg_freeErr2ASSERT_VIOLATIONMEMORY_FREE, ldv_msg_freeErr4ASSERT_VIOLATIONMEMORY_FREE, ldv_msg_freeErr5ASSERT_VIOLATIONMEMORY_FREE, ldv_msg_freeErr0REQUIRES_VIOLATION, ldv_msg_freeErr1REQUIRES_VIOLATION, ldv_msg_freeErr3ASSERT_VIOLATIONMEMORY_FREE, mainErr0ENSURES_VIOLATIONMEMORY_LEAK, LDV_INIT_LIST_HEADErr1REQUIRES_VIOLATION, LDV_INIT_LIST_HEADErr0REQUIRES_VIOLATION, LDV_INIT_LIST_HEADErr3REQUIRES_VIOLATION, LDV_INIT_LIST_HEADErr2REQUIRES_VIOLATION, ldv_list_delErr1REQUIRES_VIOLATION, ldv_list_delErr0REQUIRES_VIOLATION, ldv_list_delErr3REQUIRES_VIOLATION, ldv_list_delErr2REQUIRES_VIOLATION, __ldv_list_addErr4REQUIRES_VIOLATION, __ldv_list_addErr5REQUIRES_VIOLATION, __ldv_list_addErr0REQUIRES_VIOLATION, __ldv_list_addErr6REQUIRES_VIOLATION, __ldv_list_addErr1REQUIRES_VIOLATION, __ldv_list_addErr7REQUIRES_VIOLATION, __ldv_list_addErr2REQUIRES_VIOLATION, __ldv_list_addErr3REQUIRES_VIOLATION, ldv_dev_set_drvdataErr1REQUIRES_VIOLATION, ldv_dev_set_drvdataErr0REQUIRES_VIOLATION, ldv_atomic_sub_returnErr1REQUIRES_VIOLATION, ldv_atomic_sub_returnErr0REQUIRES_VIOLATION, ldv_atomic_sub_returnErr3REQUIRES_VIOLATION, ldv_atomic_sub_returnErr2REQUIRES_VIOLATION, ldv_list_add_tailErr0REQUIRES_VIOLATION, ldv_list_add_tailErr1REQUIRES_VIOLATION, ldv_dev_get_drvdataErr0REQUIRES_VIOLATION, ldv_dev_get_drvdataErr1REQUIRES_VIOLATION, ldv_msg_allocErr0REQUIRES_VIOLATION, ldv_msg_allocErr1REQUIRES_VIOLATION]=== [2018-11-28 13:02:57,878 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-28 13:02:57,878 INFO L82 PathProgramCache]: Analyzing trace with hash -396753779, now seen corresponding path program 2 times [2018-11-28 13:02:57,878 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-28 13:02:57,878 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-28 13:02:57,880 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 13:02:57,880 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-28 13:02:57,880 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 13:02:57,890 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-28 13:02:57,929 INFO L134 CoverageAnalysis]: Checked inductivity of 3 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-28 13:02:57,929 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-28 13:02:57,929 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_a5616418-4a25-482a-a0cb-6eefe8bc17e5/bin-2019/uautomizer/z3 Starting monitored process 3 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 3 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-28 13:02:57,940 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-11-28 13:02:57,971 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) [2018-11-28 13:02:57,971 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-11-28 13:02:57,975 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-28 13:02:58,012 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 6 treesize of output 5 [2018-11-28 13:02:58,013 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-11-28 13:02:58,020 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-0 vars, 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-28 13:02:58,020 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 2 variables, input treesize:13, output treesize:9 [2018-11-28 13:02:58,211 INFO L134 CoverageAnalysis]: Checked inductivity of 3 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 3 trivial. 0 not checked. [2018-11-28 13:02:58,236 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 1 imperfect interpolant sequences. [2018-11-28 13:02:58,237 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [12] imperfect sequences [6] total 17 [2018-11-28 13:02:58,237 INFO L459 AbstractCegarLoop]: Interpolant automaton has 17 states [2018-11-28 13:02:58,237 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 17 interpolants. [2018-11-28 13:02:58,237 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=42, Invalid=230, Unknown=0, NotChecked=0, Total=272 [2018-11-28 13:02:58,237 INFO L87 Difference]: Start difference. First operand 160 states and 167 transitions. Second operand 17 states. [2018-11-28 13:02:58,758 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-28 13:02:58,758 INFO L93 Difference]: Finished difference Result 221 states and 230 transitions. [2018-11-28 13:02:58,758 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 17 states. [2018-11-28 13:02:58,759 INFO L78 Accepts]: Start accepts. Automaton has 17 states. Word has length 34 [2018-11-28 13:02:58,759 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-28 13:02:58,760 INFO L225 Difference]: With dead ends: 221 [2018-11-28 13:02:58,760 INFO L226 Difference]: Without dead ends: 219 [2018-11-28 13:02:58,760 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 47 GetRequests, 23 SyntacticMatches, 1 SemanticMatches, 23 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 67 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=85, Invalid=515, Unknown=0, NotChecked=0, Total=600 [2018-11-28 13:02:58,760 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 219 states. [2018-11-28 13:02:58,763 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 219 to 160. [2018-11-28 13:02:58,763 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 160 states. [2018-11-28 13:02:58,764 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 160 states to 160 states and 167 transitions. [2018-11-28 13:02:58,764 INFO L78 Accepts]: Start accepts. Automaton has 160 states and 167 transitions. Word has length 34 [2018-11-28 13:02:58,764 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-28 13:02:58,764 INFO L480 AbstractCegarLoop]: Abstraction has 160 states and 167 transitions. [2018-11-28 13:02:58,764 INFO L481 AbstractCegarLoop]: Interpolant automaton has 17 states. [2018-11-28 13:02:58,764 INFO L276 IsEmpty]: Start isEmpty. Operand 160 states and 167 transitions. [2018-11-28 13:02:58,765 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 41 [2018-11-28 13:02:58,765 INFO L394 BasicCegarLoop]: Found error trace [2018-11-28 13:02:58,765 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-28 13:02:58,765 INFO L423 AbstractCegarLoop]: === Iteration 10 === [ldv_kref_initErr1REQUIRES_VIOLATION, ldv_kref_initErr0REQUIRES_VIOLATION, ldv_list_addErr1REQUIRES_VIOLATION, ldv_list_addErr0REQUIRES_VIOLATION, ldv_kobject_createErr0REQUIRES_VIOLATION, ldv_kobject_createErr1REQUIRES_VIOLATION, ldv_destroy_msgsErr3REQUIRES_VIOLATION, ldv_destroy_msgsErr2REQUIRES_VIOLATION, ldv_destroy_msgsErr1REQUIRES_VIOLATION, ldv_destroy_msgsErr0REQUIRES_VIOLATION, ldv_destroy_msgsErr5REQUIRES_VIOLATION, ldv_destroy_msgsErr4REQUIRES_VIOLATION, ldv_msg_fillErr1REQUIRES_VIOLATION, ldv_msg_fillErr4REQUIRES_VIOLATION, ldv_msg_fillErr0REQUIRES_VIOLATION, ldv_msg_fillErr5REQUIRES_VIOLATION, ldv_msg_fillErr3REQUIRES_VIOLATION, ldv_msg_fillErr2REQUIRES_VIOLATION, ldv_atomic_add_returnErr1REQUIRES_VIOLATION, ldv_atomic_add_returnErr0REQUIRES_VIOLATION, ldv_atomic_add_returnErr3REQUIRES_VIOLATION, ldv_atomic_add_returnErr2REQUIRES_VIOLATION, __ldv_list_delErr0REQUIRES_VIOLATION, __ldv_list_delErr1REQUIRES_VIOLATION, __ldv_list_delErr2REQUIRES_VIOLATION, __ldv_list_delErr3REQUIRES_VIOLATION, ldv_kobject_cleanupErr2ASSERT_VIOLATIONMEMORY_FREE, ldv_kobject_cleanupErr4ASSERT_VIOLATIONMEMORY_FREE, ldv_kobject_cleanupErr0REQUIRES_VIOLATION, ldv_kobject_cleanupErr5ASSERT_VIOLATIONMEMORY_FREE, ldv_kobject_cleanupErr1REQUIRES_VIOLATION, ldv_kobject_cleanupErr3ASSERT_VIOLATIONMEMORY_FREE, ldv_msg_freeErr2ASSERT_VIOLATIONMEMORY_FREE, ldv_msg_freeErr4ASSERT_VIOLATIONMEMORY_FREE, ldv_msg_freeErr5ASSERT_VIOLATIONMEMORY_FREE, ldv_msg_freeErr0REQUIRES_VIOLATION, ldv_msg_freeErr1REQUIRES_VIOLATION, ldv_msg_freeErr3ASSERT_VIOLATIONMEMORY_FREE, mainErr0ENSURES_VIOLATIONMEMORY_LEAK, LDV_INIT_LIST_HEADErr1REQUIRES_VIOLATION, LDV_INIT_LIST_HEADErr0REQUIRES_VIOLATION, LDV_INIT_LIST_HEADErr3REQUIRES_VIOLATION, LDV_INIT_LIST_HEADErr2REQUIRES_VIOLATION, ldv_list_delErr1REQUIRES_VIOLATION, ldv_list_delErr0REQUIRES_VIOLATION, ldv_list_delErr3REQUIRES_VIOLATION, ldv_list_delErr2REQUIRES_VIOLATION, __ldv_list_addErr4REQUIRES_VIOLATION, __ldv_list_addErr5REQUIRES_VIOLATION, __ldv_list_addErr0REQUIRES_VIOLATION, __ldv_list_addErr6REQUIRES_VIOLATION, __ldv_list_addErr1REQUIRES_VIOLATION, __ldv_list_addErr7REQUIRES_VIOLATION, __ldv_list_addErr2REQUIRES_VIOLATION, __ldv_list_addErr3REQUIRES_VIOLATION, ldv_dev_set_drvdataErr1REQUIRES_VIOLATION, ldv_dev_set_drvdataErr0REQUIRES_VIOLATION, ldv_atomic_sub_returnErr1REQUIRES_VIOLATION, ldv_atomic_sub_returnErr0REQUIRES_VIOLATION, ldv_atomic_sub_returnErr3REQUIRES_VIOLATION, ldv_atomic_sub_returnErr2REQUIRES_VIOLATION, ldv_list_add_tailErr0REQUIRES_VIOLATION, ldv_list_add_tailErr1REQUIRES_VIOLATION, ldv_dev_get_drvdataErr0REQUIRES_VIOLATION, ldv_dev_get_drvdataErr1REQUIRES_VIOLATION, ldv_msg_allocErr0REQUIRES_VIOLATION, ldv_msg_allocErr1REQUIRES_VIOLATION]=== [2018-11-28 13:02:58,765 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-28 13:02:58,766 INFO L82 PathProgramCache]: Analyzing trace with hash -1603043185, now seen corresponding path program 1 times [2018-11-28 13:02:58,766 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-28 13:02:58,766 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-28 13:02:58,769 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 13:02:58,769 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-28 13:02:58,769 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 13:02:58,779 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-28 13:02:58,831 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-28 13:02:58,831 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-28 13:02:58,832 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [7] imperfect sequences [] total 7 [2018-11-28 13:02:58,832 INFO L459 AbstractCegarLoop]: Interpolant automaton has 7 states [2018-11-28 13:02:58,832 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2018-11-28 13:02:58,832 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=11, Invalid=31, Unknown=0, NotChecked=0, Total=42 [2018-11-28 13:02:58,832 INFO L87 Difference]: Start difference. First operand 160 states and 167 transitions. Second operand 7 states. [2018-11-28 13:02:58,853 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-28 13:02:58,853 INFO L93 Difference]: Finished difference Result 169 states and 176 transitions. [2018-11-28 13:02:58,853 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 8 states. [2018-11-28 13:02:58,853 INFO L78 Accepts]: Start accepts. Automaton has 7 states. Word has length 40 [2018-11-28 13:02:58,853 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-28 13:02:58,854 INFO L225 Difference]: With dead ends: 169 [2018-11-28 13:02:58,854 INFO L226 Difference]: Without dead ends: 169 [2018-11-28 13:02:58,855 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 8 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 6 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=15, Invalid=41, Unknown=0, NotChecked=0, Total=56 [2018-11-28 13:02:58,855 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 169 states. [2018-11-28 13:02:58,858 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 169 to 165. [2018-11-28 13:02:58,859 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 165 states. [2018-11-28 13:02:58,859 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 165 states to 165 states and 172 transitions. [2018-11-28 13:02:58,860 INFO L78 Accepts]: Start accepts. Automaton has 165 states and 172 transitions. Word has length 40 [2018-11-28 13:02:58,860 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-28 13:02:58,860 INFO L480 AbstractCegarLoop]: Abstraction has 165 states and 172 transitions. [2018-11-28 13:02:58,860 INFO L481 AbstractCegarLoop]: Interpolant automaton has 7 states. [2018-11-28 13:02:58,860 INFO L276 IsEmpty]: Start isEmpty. Operand 165 states and 172 transitions. [2018-11-28 13:02:58,861 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 41 [2018-11-28 13:02:58,861 INFO L394 BasicCegarLoop]: Found error trace [2018-11-28 13:02:58,861 INFO L402 BasicCegarLoop]: trace histogram [3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-28 13:02:58,861 INFO L423 AbstractCegarLoop]: === Iteration 11 === [ldv_kref_initErr1REQUIRES_VIOLATION, ldv_kref_initErr0REQUIRES_VIOLATION, ldv_list_addErr1REQUIRES_VIOLATION, ldv_list_addErr0REQUIRES_VIOLATION, ldv_kobject_createErr0REQUIRES_VIOLATION, ldv_kobject_createErr1REQUIRES_VIOLATION, ldv_destroy_msgsErr3REQUIRES_VIOLATION, ldv_destroy_msgsErr2REQUIRES_VIOLATION, ldv_destroy_msgsErr1REQUIRES_VIOLATION, ldv_destroy_msgsErr0REQUIRES_VIOLATION, ldv_destroy_msgsErr5REQUIRES_VIOLATION, ldv_destroy_msgsErr4REQUIRES_VIOLATION, ldv_msg_fillErr1REQUIRES_VIOLATION, ldv_msg_fillErr4REQUIRES_VIOLATION, ldv_msg_fillErr0REQUIRES_VIOLATION, ldv_msg_fillErr5REQUIRES_VIOLATION, ldv_msg_fillErr3REQUIRES_VIOLATION, ldv_msg_fillErr2REQUIRES_VIOLATION, ldv_atomic_add_returnErr1REQUIRES_VIOLATION, ldv_atomic_add_returnErr0REQUIRES_VIOLATION, ldv_atomic_add_returnErr3REQUIRES_VIOLATION, ldv_atomic_add_returnErr2REQUIRES_VIOLATION, __ldv_list_delErr0REQUIRES_VIOLATION, __ldv_list_delErr1REQUIRES_VIOLATION, __ldv_list_delErr2REQUIRES_VIOLATION, __ldv_list_delErr3REQUIRES_VIOLATION, ldv_kobject_cleanupErr2ASSERT_VIOLATIONMEMORY_FREE, ldv_kobject_cleanupErr4ASSERT_VIOLATIONMEMORY_FREE, ldv_kobject_cleanupErr0REQUIRES_VIOLATION, ldv_kobject_cleanupErr5ASSERT_VIOLATIONMEMORY_FREE, ldv_kobject_cleanupErr1REQUIRES_VIOLATION, ldv_kobject_cleanupErr3ASSERT_VIOLATIONMEMORY_FREE, ldv_msg_freeErr2ASSERT_VIOLATIONMEMORY_FREE, ldv_msg_freeErr4ASSERT_VIOLATIONMEMORY_FREE, ldv_msg_freeErr5ASSERT_VIOLATIONMEMORY_FREE, ldv_msg_freeErr0REQUIRES_VIOLATION, ldv_msg_freeErr1REQUIRES_VIOLATION, ldv_msg_freeErr3ASSERT_VIOLATIONMEMORY_FREE, mainErr0ENSURES_VIOLATIONMEMORY_LEAK, LDV_INIT_LIST_HEADErr1REQUIRES_VIOLATION, LDV_INIT_LIST_HEADErr0REQUIRES_VIOLATION, LDV_INIT_LIST_HEADErr3REQUIRES_VIOLATION, LDV_INIT_LIST_HEADErr2REQUIRES_VIOLATION, ldv_list_delErr1REQUIRES_VIOLATION, ldv_list_delErr0REQUIRES_VIOLATION, ldv_list_delErr3REQUIRES_VIOLATION, ldv_list_delErr2REQUIRES_VIOLATION, __ldv_list_addErr4REQUIRES_VIOLATION, __ldv_list_addErr5REQUIRES_VIOLATION, __ldv_list_addErr0REQUIRES_VIOLATION, __ldv_list_addErr6REQUIRES_VIOLATION, __ldv_list_addErr1REQUIRES_VIOLATION, __ldv_list_addErr7REQUIRES_VIOLATION, __ldv_list_addErr2REQUIRES_VIOLATION, __ldv_list_addErr3REQUIRES_VIOLATION, ldv_dev_set_drvdataErr1REQUIRES_VIOLATION, ldv_dev_set_drvdataErr0REQUIRES_VIOLATION, ldv_atomic_sub_returnErr1REQUIRES_VIOLATION, ldv_atomic_sub_returnErr0REQUIRES_VIOLATION, ldv_atomic_sub_returnErr3REQUIRES_VIOLATION, ldv_atomic_sub_returnErr2REQUIRES_VIOLATION, ldv_list_add_tailErr0REQUIRES_VIOLATION, ldv_list_add_tailErr1REQUIRES_VIOLATION, ldv_dev_get_drvdataErr0REQUIRES_VIOLATION, ldv_dev_get_drvdataErr1REQUIRES_VIOLATION, ldv_msg_allocErr0REQUIRES_VIOLATION, ldv_msg_allocErr1REQUIRES_VIOLATION]=== [2018-11-28 13:02:58,861 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-28 13:02:58,861 INFO L82 PathProgramCache]: Analyzing trace with hash -1089122632, now seen corresponding path program 1 times [2018-11-28 13:02:58,862 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-28 13:02:58,862 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-28 13:02:58,863 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 13:02:58,863 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-28 13:02:58,863 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 13:02:58,872 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-28 13:02:58,944 INFO L134 CoverageAnalysis]: Checked inductivity of 6 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 6 trivial. 0 not checked. [2018-11-28 13:02:58,944 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-28 13:02:58,944 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [10] imperfect sequences [] total 10 [2018-11-28 13:02:58,944 INFO L459 AbstractCegarLoop]: Interpolant automaton has 11 states [2018-11-28 13:02:58,944 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 11 interpolants. [2018-11-28 13:02:58,945 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=19, Invalid=91, Unknown=0, NotChecked=0, Total=110 [2018-11-28 13:02:58,945 INFO L87 Difference]: Start difference. First operand 165 states and 172 transitions. Second operand 11 states. [2018-11-28 13:02:59,114 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-28 13:02:59,115 INFO L93 Difference]: Finished difference Result 163 states and 170 transitions. [2018-11-28 13:02:59,115 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 11 states. [2018-11-28 13:02:59,115 INFO L78 Accepts]: Start accepts. Automaton has 11 states. Word has length 40 [2018-11-28 13:02:59,115 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-28 13:02:59,116 INFO L225 Difference]: With dead ends: 163 [2018-11-28 13:02:59,116 INFO L226 Difference]: Without dead ends: 163 [2018-11-28 13:02:59,116 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 13 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 12 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 3 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=31, Invalid=151, Unknown=0, NotChecked=0, Total=182 [2018-11-28 13:02:59,117 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 163 states. [2018-11-28 13:02:59,118 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 163 to 163. [2018-11-28 13:02:59,119 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 163 states. [2018-11-28 13:02:59,119 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 163 states to 163 states and 170 transitions. [2018-11-28 13:02:59,119 INFO L78 Accepts]: Start accepts. Automaton has 163 states and 170 transitions. Word has length 40 [2018-11-28 13:02:59,120 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-28 13:02:59,120 INFO L480 AbstractCegarLoop]: Abstraction has 163 states and 170 transitions. [2018-11-28 13:02:59,120 INFO L481 AbstractCegarLoop]: Interpolant automaton has 11 states. [2018-11-28 13:02:59,120 INFO L276 IsEmpty]: Start isEmpty. Operand 163 states and 170 transitions. [2018-11-28 13:02:59,120 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 41 [2018-11-28 13:02:59,121 INFO L394 BasicCegarLoop]: Found error trace [2018-11-28 13:02:59,121 INFO L402 BasicCegarLoop]: trace histogram [3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-28 13:02:59,121 INFO L423 AbstractCegarLoop]: === Iteration 12 === [ldv_kref_initErr1REQUIRES_VIOLATION, ldv_kref_initErr0REQUIRES_VIOLATION, ldv_list_addErr1REQUIRES_VIOLATION, ldv_list_addErr0REQUIRES_VIOLATION, ldv_kobject_createErr0REQUIRES_VIOLATION, ldv_kobject_createErr1REQUIRES_VIOLATION, ldv_destroy_msgsErr3REQUIRES_VIOLATION, ldv_destroy_msgsErr2REQUIRES_VIOLATION, ldv_destroy_msgsErr1REQUIRES_VIOLATION, ldv_destroy_msgsErr0REQUIRES_VIOLATION, ldv_destroy_msgsErr5REQUIRES_VIOLATION, ldv_destroy_msgsErr4REQUIRES_VIOLATION, ldv_msg_fillErr1REQUIRES_VIOLATION, ldv_msg_fillErr4REQUIRES_VIOLATION, ldv_msg_fillErr0REQUIRES_VIOLATION, ldv_msg_fillErr5REQUIRES_VIOLATION, ldv_msg_fillErr3REQUIRES_VIOLATION, ldv_msg_fillErr2REQUIRES_VIOLATION, ldv_atomic_add_returnErr1REQUIRES_VIOLATION, ldv_atomic_add_returnErr0REQUIRES_VIOLATION, ldv_atomic_add_returnErr3REQUIRES_VIOLATION, ldv_atomic_add_returnErr2REQUIRES_VIOLATION, __ldv_list_delErr0REQUIRES_VIOLATION, __ldv_list_delErr1REQUIRES_VIOLATION, __ldv_list_delErr2REQUIRES_VIOLATION, __ldv_list_delErr3REQUIRES_VIOLATION, ldv_kobject_cleanupErr2ASSERT_VIOLATIONMEMORY_FREE, ldv_kobject_cleanupErr4ASSERT_VIOLATIONMEMORY_FREE, ldv_kobject_cleanupErr0REQUIRES_VIOLATION, ldv_kobject_cleanupErr5ASSERT_VIOLATIONMEMORY_FREE, ldv_kobject_cleanupErr1REQUIRES_VIOLATION, ldv_kobject_cleanupErr3ASSERT_VIOLATIONMEMORY_FREE, ldv_msg_freeErr2ASSERT_VIOLATIONMEMORY_FREE, ldv_msg_freeErr4ASSERT_VIOLATIONMEMORY_FREE, ldv_msg_freeErr5ASSERT_VIOLATIONMEMORY_FREE, ldv_msg_freeErr0REQUIRES_VIOLATION, ldv_msg_freeErr1REQUIRES_VIOLATION, ldv_msg_freeErr3ASSERT_VIOLATIONMEMORY_FREE, mainErr0ENSURES_VIOLATIONMEMORY_LEAK, LDV_INIT_LIST_HEADErr1REQUIRES_VIOLATION, LDV_INIT_LIST_HEADErr0REQUIRES_VIOLATION, LDV_INIT_LIST_HEADErr3REQUIRES_VIOLATION, LDV_INIT_LIST_HEADErr2REQUIRES_VIOLATION, ldv_list_delErr1REQUIRES_VIOLATION, ldv_list_delErr0REQUIRES_VIOLATION, ldv_list_delErr3REQUIRES_VIOLATION, ldv_list_delErr2REQUIRES_VIOLATION, __ldv_list_addErr4REQUIRES_VIOLATION, __ldv_list_addErr5REQUIRES_VIOLATION, __ldv_list_addErr0REQUIRES_VIOLATION, __ldv_list_addErr6REQUIRES_VIOLATION, __ldv_list_addErr1REQUIRES_VIOLATION, __ldv_list_addErr7REQUIRES_VIOLATION, __ldv_list_addErr2REQUIRES_VIOLATION, __ldv_list_addErr3REQUIRES_VIOLATION, ldv_dev_set_drvdataErr1REQUIRES_VIOLATION, ldv_dev_set_drvdataErr0REQUIRES_VIOLATION, ldv_atomic_sub_returnErr1REQUIRES_VIOLATION, ldv_atomic_sub_returnErr0REQUIRES_VIOLATION, ldv_atomic_sub_returnErr3REQUIRES_VIOLATION, ldv_atomic_sub_returnErr2REQUIRES_VIOLATION, ldv_list_add_tailErr0REQUIRES_VIOLATION, ldv_list_add_tailErr1REQUIRES_VIOLATION, ldv_dev_get_drvdataErr0REQUIRES_VIOLATION, ldv_dev_get_drvdataErr1REQUIRES_VIOLATION, ldv_msg_allocErr0REQUIRES_VIOLATION, ldv_msg_allocErr1REQUIRES_VIOLATION]=== [2018-11-28 13:02:59,121 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-28 13:02:59,121 INFO L82 PathProgramCache]: Analyzing trace with hash -1089122631, now seen corresponding path program 1 times [2018-11-28 13:02:59,121 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-28 13:02:59,121 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-28 13:02:59,122 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 13:02:59,122 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-28 13:02:59,122 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 13:02:59,131 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-28 13:02:59,162 INFO L134 CoverageAnalysis]: Checked inductivity of 6 backedges. 0 proven. 6 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-28 13:02:59,163 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-28 13:02:59,163 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_a5616418-4a25-482a-a0cb-6eefe8bc17e5/bin-2019/uautomizer/z3 Starting monitored process 4 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 4 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-28 13:02:59,170 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-28 13:02:59,189 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-28 13:02:59,191 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-28 13:02:59,207 INFO L134 CoverageAnalysis]: Checked inductivity of 6 backedges. 0 proven. 6 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-28 13:02:59,222 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-11-28 13:02:59,222 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [7, 7] total 8 [2018-11-28 13:02:59,222 INFO L459 AbstractCegarLoop]: Interpolant automaton has 8 states [2018-11-28 13:02:59,222 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 8 interpolants. [2018-11-28 13:02:59,222 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=23, Invalid=33, Unknown=0, NotChecked=0, Total=56 [2018-11-28 13:02:59,222 INFO L87 Difference]: Start difference. First operand 163 states and 170 transitions. Second operand 8 states. [2018-11-28 13:02:59,237 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-28 13:02:59,237 INFO L93 Difference]: Finished difference Result 166 states and 173 transitions. [2018-11-28 13:02:59,238 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2018-11-28 13:02:59,238 INFO L78 Accepts]: Start accepts. Automaton has 8 states. Word has length 40 [2018-11-28 13:02:59,238 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-28 13:02:59,238 INFO L225 Difference]: With dead ends: 166 [2018-11-28 13:02:59,238 INFO L226 Difference]: Without dead ends: 164 [2018-11-28 13:02:59,238 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 47 GetRequests, 40 SyntacticMatches, 0 SemanticMatches, 7 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 8 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=27, Invalid=45, Unknown=0, NotChecked=0, Total=72 [2018-11-28 13:02:59,239 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 164 states. [2018-11-28 13:02:59,240 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 164 to 164. [2018-11-28 13:02:59,240 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 164 states. [2018-11-28 13:02:59,241 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 164 states to 164 states and 171 transitions. [2018-11-28 13:02:59,241 INFO L78 Accepts]: Start accepts. Automaton has 164 states and 171 transitions. Word has length 40 [2018-11-28 13:02:59,241 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-28 13:02:59,241 INFO L480 AbstractCegarLoop]: Abstraction has 164 states and 171 transitions. [2018-11-28 13:02:59,241 INFO L481 AbstractCegarLoop]: Interpolant automaton has 8 states. [2018-11-28 13:02:59,241 INFO L276 IsEmpty]: Start isEmpty. Operand 164 states and 171 transitions. [2018-11-28 13:02:59,242 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 39 [2018-11-28 13:02:59,242 INFO L394 BasicCegarLoop]: Found error trace [2018-11-28 13:02:59,242 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-28 13:02:59,242 INFO L423 AbstractCegarLoop]: === Iteration 13 === [ldv_kref_initErr1REQUIRES_VIOLATION, ldv_kref_initErr0REQUIRES_VIOLATION, ldv_list_addErr1REQUIRES_VIOLATION, ldv_list_addErr0REQUIRES_VIOLATION, ldv_kobject_createErr0REQUIRES_VIOLATION, ldv_kobject_createErr1REQUIRES_VIOLATION, ldv_destroy_msgsErr3REQUIRES_VIOLATION, ldv_destroy_msgsErr2REQUIRES_VIOLATION, ldv_destroy_msgsErr1REQUIRES_VIOLATION, ldv_destroy_msgsErr0REQUIRES_VIOLATION, ldv_destroy_msgsErr5REQUIRES_VIOLATION, ldv_destroy_msgsErr4REQUIRES_VIOLATION, ldv_msg_fillErr1REQUIRES_VIOLATION, ldv_msg_fillErr4REQUIRES_VIOLATION, ldv_msg_fillErr0REQUIRES_VIOLATION, ldv_msg_fillErr5REQUIRES_VIOLATION, ldv_msg_fillErr3REQUIRES_VIOLATION, ldv_msg_fillErr2REQUIRES_VIOLATION, ldv_atomic_add_returnErr1REQUIRES_VIOLATION, ldv_atomic_add_returnErr0REQUIRES_VIOLATION, ldv_atomic_add_returnErr3REQUIRES_VIOLATION, ldv_atomic_add_returnErr2REQUIRES_VIOLATION, __ldv_list_delErr0REQUIRES_VIOLATION, __ldv_list_delErr1REQUIRES_VIOLATION, __ldv_list_delErr2REQUIRES_VIOLATION, __ldv_list_delErr3REQUIRES_VIOLATION, ldv_kobject_cleanupErr2ASSERT_VIOLATIONMEMORY_FREE, ldv_kobject_cleanupErr4ASSERT_VIOLATIONMEMORY_FREE, ldv_kobject_cleanupErr0REQUIRES_VIOLATION, ldv_kobject_cleanupErr5ASSERT_VIOLATIONMEMORY_FREE, ldv_kobject_cleanupErr1REQUIRES_VIOLATION, ldv_kobject_cleanupErr3ASSERT_VIOLATIONMEMORY_FREE, ldv_msg_freeErr2ASSERT_VIOLATIONMEMORY_FREE, ldv_msg_freeErr4ASSERT_VIOLATIONMEMORY_FREE, ldv_msg_freeErr5ASSERT_VIOLATIONMEMORY_FREE, ldv_msg_freeErr0REQUIRES_VIOLATION, ldv_msg_freeErr1REQUIRES_VIOLATION, ldv_msg_freeErr3ASSERT_VIOLATIONMEMORY_FREE, mainErr0ENSURES_VIOLATIONMEMORY_LEAK, LDV_INIT_LIST_HEADErr1REQUIRES_VIOLATION, LDV_INIT_LIST_HEADErr0REQUIRES_VIOLATION, LDV_INIT_LIST_HEADErr3REQUIRES_VIOLATION, LDV_INIT_LIST_HEADErr2REQUIRES_VIOLATION, ldv_list_delErr1REQUIRES_VIOLATION, ldv_list_delErr0REQUIRES_VIOLATION, ldv_list_delErr3REQUIRES_VIOLATION, ldv_list_delErr2REQUIRES_VIOLATION, __ldv_list_addErr4REQUIRES_VIOLATION, __ldv_list_addErr5REQUIRES_VIOLATION, __ldv_list_addErr0REQUIRES_VIOLATION, __ldv_list_addErr6REQUIRES_VIOLATION, __ldv_list_addErr1REQUIRES_VIOLATION, __ldv_list_addErr7REQUIRES_VIOLATION, __ldv_list_addErr2REQUIRES_VIOLATION, __ldv_list_addErr3REQUIRES_VIOLATION, ldv_dev_set_drvdataErr1REQUIRES_VIOLATION, ldv_dev_set_drvdataErr0REQUIRES_VIOLATION, ldv_atomic_sub_returnErr1REQUIRES_VIOLATION, ldv_atomic_sub_returnErr0REQUIRES_VIOLATION, ldv_atomic_sub_returnErr3REQUIRES_VIOLATION, ldv_atomic_sub_returnErr2REQUIRES_VIOLATION, ldv_list_add_tailErr0REQUIRES_VIOLATION, ldv_list_add_tailErr1REQUIRES_VIOLATION, ldv_dev_get_drvdataErr0REQUIRES_VIOLATION, ldv_dev_get_drvdataErr1REQUIRES_VIOLATION, ldv_msg_allocErr0REQUIRES_VIOLATION, ldv_msg_allocErr1REQUIRES_VIOLATION]=== [2018-11-28 13:02:59,242 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-28 13:02:59,242 INFO L82 PathProgramCache]: Analyzing trace with hash 1617364353, now seen corresponding path program 1 times [2018-11-28 13:02:59,242 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-28 13:02:59,242 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-28 13:02:59,243 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 13:02:59,243 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-28 13:02:59,243 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 13:02:59,251 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-28 13:02:59,283 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-28 13:02:59,283 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-28 13:02:59,283 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2018-11-28 13:02:59,283 INFO L459 AbstractCegarLoop]: Interpolant automaton has 3 states [2018-11-28 13:02:59,284 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-28 13:02:59,284 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-28 13:02:59,284 INFO L87 Difference]: Start difference. First operand 164 states and 171 transitions. Second operand 3 states. [2018-11-28 13:02:59,367 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-28 13:02:59,367 INFO L93 Difference]: Finished difference Result 175 states and 181 transitions. [2018-11-28 13:02:59,367 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-28 13:02:59,368 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 38 [2018-11-28 13:02:59,368 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-28 13:02:59,368 INFO L225 Difference]: With dead ends: 175 [2018-11-28 13:02:59,368 INFO L226 Difference]: Without dead ends: 149 [2018-11-28 13:02:59,368 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 10 GetRequests, 9 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-28 13:02:59,369 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 149 states. [2018-11-28 13:02:59,370 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 149 to 141. [2018-11-28 13:02:59,370 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 141 states. [2018-11-28 13:02:59,371 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 141 states to 141 states and 147 transitions. [2018-11-28 13:02:59,371 INFO L78 Accepts]: Start accepts. Automaton has 141 states and 147 transitions. Word has length 38 [2018-11-28 13:02:59,371 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-28 13:02:59,371 INFO L480 AbstractCegarLoop]: Abstraction has 141 states and 147 transitions. [2018-11-28 13:02:59,371 INFO L481 AbstractCegarLoop]: Interpolant automaton has 3 states. [2018-11-28 13:02:59,371 INFO L276 IsEmpty]: Start isEmpty. Operand 141 states and 147 transitions. [2018-11-28 13:02:59,371 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 42 [2018-11-28 13:02:59,371 INFO L394 BasicCegarLoop]: Found error trace [2018-11-28 13:02:59,372 INFO L402 BasicCegarLoop]: trace histogram [4, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-28 13:02:59,372 INFO L423 AbstractCegarLoop]: === Iteration 14 === [ldv_kref_initErr1REQUIRES_VIOLATION, ldv_kref_initErr0REQUIRES_VIOLATION, ldv_list_addErr1REQUIRES_VIOLATION, ldv_list_addErr0REQUIRES_VIOLATION, ldv_kobject_createErr0REQUIRES_VIOLATION, ldv_kobject_createErr1REQUIRES_VIOLATION, ldv_destroy_msgsErr3REQUIRES_VIOLATION, ldv_destroy_msgsErr2REQUIRES_VIOLATION, ldv_destroy_msgsErr1REQUIRES_VIOLATION, ldv_destroy_msgsErr0REQUIRES_VIOLATION, ldv_destroy_msgsErr5REQUIRES_VIOLATION, ldv_destroy_msgsErr4REQUIRES_VIOLATION, ldv_msg_fillErr1REQUIRES_VIOLATION, ldv_msg_fillErr4REQUIRES_VIOLATION, ldv_msg_fillErr0REQUIRES_VIOLATION, ldv_msg_fillErr5REQUIRES_VIOLATION, ldv_msg_fillErr3REQUIRES_VIOLATION, ldv_msg_fillErr2REQUIRES_VIOLATION, ldv_atomic_add_returnErr1REQUIRES_VIOLATION, ldv_atomic_add_returnErr0REQUIRES_VIOLATION, ldv_atomic_add_returnErr3REQUIRES_VIOLATION, ldv_atomic_add_returnErr2REQUIRES_VIOLATION, __ldv_list_delErr0REQUIRES_VIOLATION, __ldv_list_delErr1REQUIRES_VIOLATION, __ldv_list_delErr2REQUIRES_VIOLATION, __ldv_list_delErr3REQUIRES_VIOLATION, ldv_kobject_cleanupErr2ASSERT_VIOLATIONMEMORY_FREE, ldv_kobject_cleanupErr4ASSERT_VIOLATIONMEMORY_FREE, ldv_kobject_cleanupErr0REQUIRES_VIOLATION, ldv_kobject_cleanupErr5ASSERT_VIOLATIONMEMORY_FREE, ldv_kobject_cleanupErr1REQUIRES_VIOLATION, ldv_kobject_cleanupErr3ASSERT_VIOLATIONMEMORY_FREE, ldv_msg_freeErr2ASSERT_VIOLATIONMEMORY_FREE, ldv_msg_freeErr4ASSERT_VIOLATIONMEMORY_FREE, ldv_msg_freeErr5ASSERT_VIOLATIONMEMORY_FREE, ldv_msg_freeErr0REQUIRES_VIOLATION, ldv_msg_freeErr1REQUIRES_VIOLATION, ldv_msg_freeErr3ASSERT_VIOLATIONMEMORY_FREE, mainErr0ENSURES_VIOLATIONMEMORY_LEAK, LDV_INIT_LIST_HEADErr1REQUIRES_VIOLATION, LDV_INIT_LIST_HEADErr0REQUIRES_VIOLATION, LDV_INIT_LIST_HEADErr3REQUIRES_VIOLATION, LDV_INIT_LIST_HEADErr2REQUIRES_VIOLATION, ldv_list_delErr1REQUIRES_VIOLATION, ldv_list_delErr0REQUIRES_VIOLATION, ldv_list_delErr3REQUIRES_VIOLATION, ldv_list_delErr2REQUIRES_VIOLATION, __ldv_list_addErr4REQUIRES_VIOLATION, __ldv_list_addErr5REQUIRES_VIOLATION, __ldv_list_addErr0REQUIRES_VIOLATION, __ldv_list_addErr6REQUIRES_VIOLATION, __ldv_list_addErr1REQUIRES_VIOLATION, __ldv_list_addErr7REQUIRES_VIOLATION, __ldv_list_addErr2REQUIRES_VIOLATION, __ldv_list_addErr3REQUIRES_VIOLATION, ldv_dev_set_drvdataErr1REQUIRES_VIOLATION, ldv_dev_set_drvdataErr0REQUIRES_VIOLATION, ldv_atomic_sub_returnErr1REQUIRES_VIOLATION, ldv_atomic_sub_returnErr0REQUIRES_VIOLATION, ldv_atomic_sub_returnErr3REQUIRES_VIOLATION, ldv_atomic_sub_returnErr2REQUIRES_VIOLATION, ldv_list_add_tailErr0REQUIRES_VIOLATION, ldv_list_add_tailErr1REQUIRES_VIOLATION, ldv_dev_get_drvdataErr0REQUIRES_VIOLATION, ldv_dev_get_drvdataErr1REQUIRES_VIOLATION, ldv_msg_allocErr0REQUIRES_VIOLATION, ldv_msg_allocErr1REQUIRES_VIOLATION]=== [2018-11-28 13:02:59,372 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-28 13:02:59,372 INFO L82 PathProgramCache]: Analyzing trace with hash -2103669860, now seen corresponding path program 2 times [2018-11-28 13:02:59,372 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-28 13:02:59,372 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-28 13:02:59,373 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 13:02:59,373 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-28 13:02:59,373 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 13:02:59,382 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-28 13:02:59,419 INFO L134 CoverageAnalysis]: Checked inductivity of 10 backedges. 0 proven. 10 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-28 13:02:59,419 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-28 13:02:59,419 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_a5616418-4a25-482a-a0cb-6eefe8bc17e5/bin-2019/uautomizer/z3 Starting monitored process 5 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 5 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-28 13:02:59,435 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-11-28 13:02:59,464 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) [2018-11-28 13:02:59,464 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-11-28 13:02:59,467 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-28 13:02:59,492 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 6 treesize of output 5 [2018-11-28 13:02:59,493 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-11-28 13:02:59,497 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-0 vars, 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-28 13:02:59,498 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 2 variables, input treesize:13, output treesize:9 [2018-11-28 13:02:59,660 INFO L134 CoverageAnalysis]: Checked inductivity of 10 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 10 trivial. 0 not checked. [2018-11-28 13:02:59,675 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 1 imperfect interpolant sequences. [2018-11-28 13:02:59,675 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [12] imperfect sequences [8] total 19 [2018-11-28 13:02:59,675 INFO L459 AbstractCegarLoop]: Interpolant automaton has 19 states [2018-11-28 13:02:59,675 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 19 interpolants. [2018-11-28 13:02:59,675 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=53, Invalid=289, Unknown=0, NotChecked=0, Total=342 [2018-11-28 13:02:59,676 INFO L87 Difference]: Start difference. First operand 141 states and 147 transitions. Second operand 19 states. [2018-11-28 13:03:00,149 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-28 13:03:00,149 INFO L93 Difference]: Finished difference Result 142 states and 148 transitions. [2018-11-28 13:03:00,150 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 19 states. [2018-11-28 13:03:00,150 INFO L78 Accepts]: Start accepts. Automaton has 19 states. Word has length 41 [2018-11-28 13:03:00,150 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-28 13:03:00,150 INFO L225 Difference]: With dead ends: 142 [2018-11-28 13:03:00,150 INFO L226 Difference]: Without dead ends: 140 [2018-11-28 13:03:00,151 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 58 GetRequests, 28 SyntacticMatches, 3 SemanticMatches, 27 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 123 ImplicationChecksByTransitivity, 0.3s TimeCoverageRelationStatistics Valid=118, Invalid=694, Unknown=0, NotChecked=0, Total=812 [2018-11-28 13:03:00,151 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 140 states. [2018-11-28 13:03:00,153 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 140 to 140. [2018-11-28 13:03:00,153 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 140 states. [2018-11-28 13:03:00,154 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 140 states to 140 states and 146 transitions. [2018-11-28 13:03:00,154 INFO L78 Accepts]: Start accepts. Automaton has 140 states and 146 transitions. Word has length 41 [2018-11-28 13:03:00,154 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-28 13:03:00,154 INFO L480 AbstractCegarLoop]: Abstraction has 140 states and 146 transitions. [2018-11-28 13:03:00,154 INFO L481 AbstractCegarLoop]: Interpolant automaton has 19 states. [2018-11-28 13:03:00,155 INFO L276 IsEmpty]: Start isEmpty. Operand 140 states and 146 transitions. [2018-11-28 13:03:00,155 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 48 [2018-11-28 13:03:00,155 INFO L394 BasicCegarLoop]: Found error trace [2018-11-28 13:03:00,155 INFO L402 BasicCegarLoop]: trace histogram [5, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-28 13:03:00,156 INFO L423 AbstractCegarLoop]: === Iteration 15 === [ldv_kref_initErr1REQUIRES_VIOLATION, ldv_kref_initErr0REQUIRES_VIOLATION, ldv_list_addErr1REQUIRES_VIOLATION, ldv_list_addErr0REQUIRES_VIOLATION, ldv_kobject_createErr0REQUIRES_VIOLATION, ldv_kobject_createErr1REQUIRES_VIOLATION, ldv_destroy_msgsErr3REQUIRES_VIOLATION, ldv_destroy_msgsErr2REQUIRES_VIOLATION, ldv_destroy_msgsErr1REQUIRES_VIOLATION, ldv_destroy_msgsErr0REQUIRES_VIOLATION, ldv_destroy_msgsErr5REQUIRES_VIOLATION, ldv_destroy_msgsErr4REQUIRES_VIOLATION, ldv_msg_fillErr1REQUIRES_VIOLATION, ldv_msg_fillErr4REQUIRES_VIOLATION, ldv_msg_fillErr0REQUIRES_VIOLATION, ldv_msg_fillErr5REQUIRES_VIOLATION, ldv_msg_fillErr3REQUIRES_VIOLATION, ldv_msg_fillErr2REQUIRES_VIOLATION, ldv_atomic_add_returnErr1REQUIRES_VIOLATION, ldv_atomic_add_returnErr0REQUIRES_VIOLATION, ldv_atomic_add_returnErr3REQUIRES_VIOLATION, ldv_atomic_add_returnErr2REQUIRES_VIOLATION, __ldv_list_delErr0REQUIRES_VIOLATION, __ldv_list_delErr1REQUIRES_VIOLATION, __ldv_list_delErr2REQUIRES_VIOLATION, __ldv_list_delErr3REQUIRES_VIOLATION, ldv_kobject_cleanupErr2ASSERT_VIOLATIONMEMORY_FREE, ldv_kobject_cleanupErr4ASSERT_VIOLATIONMEMORY_FREE, ldv_kobject_cleanupErr0REQUIRES_VIOLATION, ldv_kobject_cleanupErr5ASSERT_VIOLATIONMEMORY_FREE, ldv_kobject_cleanupErr1REQUIRES_VIOLATION, ldv_kobject_cleanupErr3ASSERT_VIOLATIONMEMORY_FREE, ldv_msg_freeErr2ASSERT_VIOLATIONMEMORY_FREE, ldv_msg_freeErr4ASSERT_VIOLATIONMEMORY_FREE, ldv_msg_freeErr5ASSERT_VIOLATIONMEMORY_FREE, ldv_msg_freeErr0REQUIRES_VIOLATION, ldv_msg_freeErr1REQUIRES_VIOLATION, ldv_msg_freeErr3ASSERT_VIOLATIONMEMORY_FREE, mainErr0ENSURES_VIOLATIONMEMORY_LEAK, LDV_INIT_LIST_HEADErr1REQUIRES_VIOLATION, LDV_INIT_LIST_HEADErr0REQUIRES_VIOLATION, LDV_INIT_LIST_HEADErr3REQUIRES_VIOLATION, LDV_INIT_LIST_HEADErr2REQUIRES_VIOLATION, ldv_list_delErr1REQUIRES_VIOLATION, ldv_list_delErr0REQUIRES_VIOLATION, ldv_list_delErr3REQUIRES_VIOLATION, ldv_list_delErr2REQUIRES_VIOLATION, __ldv_list_addErr4REQUIRES_VIOLATION, __ldv_list_addErr5REQUIRES_VIOLATION, __ldv_list_addErr0REQUIRES_VIOLATION, __ldv_list_addErr6REQUIRES_VIOLATION, __ldv_list_addErr1REQUIRES_VIOLATION, __ldv_list_addErr7REQUIRES_VIOLATION, __ldv_list_addErr2REQUIRES_VIOLATION, __ldv_list_addErr3REQUIRES_VIOLATION, ldv_dev_set_drvdataErr1REQUIRES_VIOLATION, ldv_dev_set_drvdataErr0REQUIRES_VIOLATION, ldv_atomic_sub_returnErr1REQUIRES_VIOLATION, ldv_atomic_sub_returnErr0REQUIRES_VIOLATION, ldv_atomic_sub_returnErr3REQUIRES_VIOLATION, ldv_atomic_sub_returnErr2REQUIRES_VIOLATION, ldv_list_add_tailErr0REQUIRES_VIOLATION, ldv_list_add_tailErr1REQUIRES_VIOLATION, ldv_dev_get_drvdataErr0REQUIRES_VIOLATION, ldv_dev_get_drvdataErr1REQUIRES_VIOLATION, ldv_msg_allocErr0REQUIRES_VIOLATION, ldv_msg_allocErr1REQUIRES_VIOLATION]=== [2018-11-28 13:03:00,156 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-28 13:03:00,156 INFO L82 PathProgramCache]: Analyzing trace with hash 1575046783, now seen corresponding path program 1 times [2018-11-28 13:03:00,156 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-28 13:03:00,156 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-28 13:03:00,157 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 13:03:00,157 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-28 13:03:00,157 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 13:03:00,164 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-28 13:03:00,197 INFO L134 CoverageAnalysis]: Checked inductivity of 15 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 15 trivial. 0 not checked. [2018-11-28 13:03:00,197 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-28 13:03:00,198 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [7] imperfect sequences [] total 7 [2018-11-28 13:03:00,198 INFO L459 AbstractCegarLoop]: Interpolant automaton has 7 states [2018-11-28 13:03:00,198 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2018-11-28 13:03:00,198 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=11, Invalid=31, Unknown=0, NotChecked=0, Total=42 [2018-11-28 13:03:00,198 INFO L87 Difference]: Start difference. First operand 140 states and 146 transitions. Second operand 7 states. [2018-11-28 13:03:00,235 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-28 13:03:00,235 INFO L93 Difference]: Finished difference Result 142 states and 147 transitions. [2018-11-28 13:03:00,236 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2018-11-28 13:03:00,236 INFO L78 Accepts]: Start accepts. Automaton has 7 states. Word has length 47 [2018-11-28 13:03:00,236 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-28 13:03:00,236 INFO L225 Difference]: With dead ends: 142 [2018-11-28 13:03:00,237 INFO L226 Difference]: Without dead ends: 140 [2018-11-28 13:03:00,237 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 8 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 6 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=15, Invalid=41, Unknown=0, NotChecked=0, Total=56 [2018-11-28 13:03:00,237 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 140 states. [2018-11-28 13:03:00,239 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 140 to 140. [2018-11-28 13:03:00,239 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 140 states. [2018-11-28 13:03:00,240 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 140 states to 140 states and 145 transitions. [2018-11-28 13:03:00,240 INFO L78 Accepts]: Start accepts. Automaton has 140 states and 145 transitions. Word has length 47 [2018-11-28 13:03:00,243 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-28 13:03:00,244 INFO L480 AbstractCegarLoop]: Abstraction has 140 states and 145 transitions. [2018-11-28 13:03:00,244 INFO L481 AbstractCegarLoop]: Interpolant automaton has 7 states. [2018-11-28 13:03:00,244 INFO L276 IsEmpty]: Start isEmpty. Operand 140 states and 145 transitions. [2018-11-28 13:03:00,244 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 53 [2018-11-28 13:03:00,244 INFO L394 BasicCegarLoop]: Found error trace [2018-11-28 13:03:00,244 INFO L402 BasicCegarLoop]: trace histogram [5, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-28 13:03:00,245 INFO L423 AbstractCegarLoop]: === Iteration 16 === [ldv_kref_initErr1REQUIRES_VIOLATION, ldv_kref_initErr0REQUIRES_VIOLATION, ldv_list_addErr1REQUIRES_VIOLATION, ldv_list_addErr0REQUIRES_VIOLATION, ldv_kobject_createErr0REQUIRES_VIOLATION, ldv_kobject_createErr1REQUIRES_VIOLATION, ldv_destroy_msgsErr3REQUIRES_VIOLATION, ldv_destroy_msgsErr2REQUIRES_VIOLATION, ldv_destroy_msgsErr1REQUIRES_VIOLATION, ldv_destroy_msgsErr0REQUIRES_VIOLATION, ldv_destroy_msgsErr5REQUIRES_VIOLATION, ldv_destroy_msgsErr4REQUIRES_VIOLATION, ldv_msg_fillErr1REQUIRES_VIOLATION, ldv_msg_fillErr4REQUIRES_VIOLATION, ldv_msg_fillErr0REQUIRES_VIOLATION, ldv_msg_fillErr5REQUIRES_VIOLATION, ldv_msg_fillErr3REQUIRES_VIOLATION, ldv_msg_fillErr2REQUIRES_VIOLATION, ldv_atomic_add_returnErr1REQUIRES_VIOLATION, ldv_atomic_add_returnErr0REQUIRES_VIOLATION, ldv_atomic_add_returnErr3REQUIRES_VIOLATION, ldv_atomic_add_returnErr2REQUIRES_VIOLATION, __ldv_list_delErr0REQUIRES_VIOLATION, __ldv_list_delErr1REQUIRES_VIOLATION, __ldv_list_delErr2REQUIRES_VIOLATION, __ldv_list_delErr3REQUIRES_VIOLATION, ldv_kobject_cleanupErr2ASSERT_VIOLATIONMEMORY_FREE, ldv_kobject_cleanupErr4ASSERT_VIOLATIONMEMORY_FREE, ldv_kobject_cleanupErr0REQUIRES_VIOLATION, ldv_kobject_cleanupErr5ASSERT_VIOLATIONMEMORY_FREE, ldv_kobject_cleanupErr1REQUIRES_VIOLATION, ldv_kobject_cleanupErr3ASSERT_VIOLATIONMEMORY_FREE, ldv_msg_freeErr2ASSERT_VIOLATIONMEMORY_FREE, ldv_msg_freeErr4ASSERT_VIOLATIONMEMORY_FREE, ldv_msg_freeErr5ASSERT_VIOLATIONMEMORY_FREE, ldv_msg_freeErr0REQUIRES_VIOLATION, ldv_msg_freeErr1REQUIRES_VIOLATION, ldv_msg_freeErr3ASSERT_VIOLATIONMEMORY_FREE, mainErr0ENSURES_VIOLATIONMEMORY_LEAK, LDV_INIT_LIST_HEADErr1REQUIRES_VIOLATION, LDV_INIT_LIST_HEADErr0REQUIRES_VIOLATION, LDV_INIT_LIST_HEADErr3REQUIRES_VIOLATION, LDV_INIT_LIST_HEADErr2REQUIRES_VIOLATION, ldv_list_delErr1REQUIRES_VIOLATION, ldv_list_delErr0REQUIRES_VIOLATION, ldv_list_delErr3REQUIRES_VIOLATION, ldv_list_delErr2REQUIRES_VIOLATION, __ldv_list_addErr4REQUIRES_VIOLATION, __ldv_list_addErr5REQUIRES_VIOLATION, __ldv_list_addErr0REQUIRES_VIOLATION, __ldv_list_addErr6REQUIRES_VIOLATION, __ldv_list_addErr1REQUIRES_VIOLATION, __ldv_list_addErr7REQUIRES_VIOLATION, __ldv_list_addErr2REQUIRES_VIOLATION, __ldv_list_addErr3REQUIRES_VIOLATION, ldv_dev_set_drvdataErr1REQUIRES_VIOLATION, ldv_dev_set_drvdataErr0REQUIRES_VIOLATION, ldv_atomic_sub_returnErr1REQUIRES_VIOLATION, ldv_atomic_sub_returnErr0REQUIRES_VIOLATION, ldv_atomic_sub_returnErr3REQUIRES_VIOLATION, ldv_atomic_sub_returnErr2REQUIRES_VIOLATION, ldv_list_add_tailErr0REQUIRES_VIOLATION, ldv_list_add_tailErr1REQUIRES_VIOLATION, ldv_dev_get_drvdataErr0REQUIRES_VIOLATION, ldv_dev_get_drvdataErr1REQUIRES_VIOLATION, ldv_msg_allocErr0REQUIRES_VIOLATION, ldv_msg_allocErr1REQUIRES_VIOLATION]=== [2018-11-28 13:03:00,245 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-28 13:03:00,245 INFO L82 PathProgramCache]: Analyzing trace with hash -710961174, now seen corresponding path program 1 times [2018-11-28 13:03:00,245 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-28 13:03:00,245 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-28 13:03:00,246 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 13:03:00,246 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-28 13:03:00,246 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 13:03:00,257 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-28 13:03:00,314 INFO L134 CoverageAnalysis]: Checked inductivity of 15 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 15 trivial. 0 not checked. [2018-11-28 13:03:00,314 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-28 13:03:00,314 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [9] imperfect sequences [] total 9 [2018-11-28 13:03:00,314 INFO L459 AbstractCegarLoop]: Interpolant automaton has 9 states [2018-11-28 13:03:00,315 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 9 interpolants. [2018-11-28 13:03:00,315 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=15, Invalid=57, Unknown=0, NotChecked=0, Total=72 [2018-11-28 13:03:00,315 INFO L87 Difference]: Start difference. First operand 140 states and 145 transitions. Second operand 9 states. [2018-11-28 13:03:00,358 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-28 13:03:00,358 INFO L93 Difference]: Finished difference Result 144 states and 148 transitions. [2018-11-28 13:03:00,359 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2018-11-28 13:03:00,359 INFO L78 Accepts]: Start accepts. Automaton has 9 states. Word has length 52 [2018-11-28 13:03:00,359 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-28 13:03:00,360 INFO L225 Difference]: With dead ends: 144 [2018-11-28 13:03:00,360 INFO L226 Difference]: Without dead ends: 140 [2018-11-28 13:03:00,360 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 11 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 9 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=23, Invalid=87, Unknown=0, NotChecked=0, Total=110 [2018-11-28 13:03:00,360 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 140 states. [2018-11-28 13:03:00,362 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 140 to 140. [2018-11-28 13:03:00,362 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 140 states. [2018-11-28 13:03:00,363 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 140 states to 140 states and 144 transitions. [2018-11-28 13:03:00,363 INFO L78 Accepts]: Start accepts. Automaton has 140 states and 144 transitions. Word has length 52 [2018-11-28 13:03:00,363 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-28 13:03:00,363 INFO L480 AbstractCegarLoop]: Abstraction has 140 states and 144 transitions. [2018-11-28 13:03:00,363 INFO L481 AbstractCegarLoop]: Interpolant automaton has 9 states. [2018-11-28 13:03:00,363 INFO L276 IsEmpty]: Start isEmpty. Operand 140 states and 144 transitions. [2018-11-28 13:03:00,364 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 64 [2018-11-28 13:03:00,364 INFO L394 BasicCegarLoop]: Found error trace [2018-11-28 13:03:00,364 INFO L402 BasicCegarLoop]: trace histogram [5, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-28 13:03:00,365 INFO L423 AbstractCegarLoop]: === Iteration 17 === [ldv_kref_initErr1REQUIRES_VIOLATION, ldv_kref_initErr0REQUIRES_VIOLATION, ldv_list_addErr1REQUIRES_VIOLATION, ldv_list_addErr0REQUIRES_VIOLATION, ldv_kobject_createErr0REQUIRES_VIOLATION, ldv_kobject_createErr1REQUIRES_VIOLATION, ldv_destroy_msgsErr3REQUIRES_VIOLATION, ldv_destroy_msgsErr2REQUIRES_VIOLATION, ldv_destroy_msgsErr1REQUIRES_VIOLATION, ldv_destroy_msgsErr0REQUIRES_VIOLATION, ldv_destroy_msgsErr5REQUIRES_VIOLATION, ldv_destroy_msgsErr4REQUIRES_VIOLATION, ldv_msg_fillErr1REQUIRES_VIOLATION, ldv_msg_fillErr4REQUIRES_VIOLATION, ldv_msg_fillErr0REQUIRES_VIOLATION, ldv_msg_fillErr5REQUIRES_VIOLATION, ldv_msg_fillErr3REQUIRES_VIOLATION, ldv_msg_fillErr2REQUIRES_VIOLATION, ldv_atomic_add_returnErr1REQUIRES_VIOLATION, ldv_atomic_add_returnErr0REQUIRES_VIOLATION, ldv_atomic_add_returnErr3REQUIRES_VIOLATION, ldv_atomic_add_returnErr2REQUIRES_VIOLATION, __ldv_list_delErr0REQUIRES_VIOLATION, __ldv_list_delErr1REQUIRES_VIOLATION, __ldv_list_delErr2REQUIRES_VIOLATION, __ldv_list_delErr3REQUIRES_VIOLATION, ldv_kobject_cleanupErr2ASSERT_VIOLATIONMEMORY_FREE, ldv_kobject_cleanupErr4ASSERT_VIOLATIONMEMORY_FREE, ldv_kobject_cleanupErr0REQUIRES_VIOLATION, ldv_kobject_cleanupErr5ASSERT_VIOLATIONMEMORY_FREE, ldv_kobject_cleanupErr1REQUIRES_VIOLATION, ldv_kobject_cleanupErr3ASSERT_VIOLATIONMEMORY_FREE, ldv_msg_freeErr2ASSERT_VIOLATIONMEMORY_FREE, ldv_msg_freeErr4ASSERT_VIOLATIONMEMORY_FREE, ldv_msg_freeErr5ASSERT_VIOLATIONMEMORY_FREE, ldv_msg_freeErr0REQUIRES_VIOLATION, ldv_msg_freeErr1REQUIRES_VIOLATION, ldv_msg_freeErr3ASSERT_VIOLATIONMEMORY_FREE, mainErr0ENSURES_VIOLATIONMEMORY_LEAK, LDV_INIT_LIST_HEADErr1REQUIRES_VIOLATION, LDV_INIT_LIST_HEADErr0REQUIRES_VIOLATION, LDV_INIT_LIST_HEADErr3REQUIRES_VIOLATION, LDV_INIT_LIST_HEADErr2REQUIRES_VIOLATION, ldv_list_delErr1REQUIRES_VIOLATION, ldv_list_delErr0REQUIRES_VIOLATION, ldv_list_delErr3REQUIRES_VIOLATION, ldv_list_delErr2REQUIRES_VIOLATION, __ldv_list_addErr4REQUIRES_VIOLATION, __ldv_list_addErr5REQUIRES_VIOLATION, __ldv_list_addErr0REQUIRES_VIOLATION, __ldv_list_addErr6REQUIRES_VIOLATION, __ldv_list_addErr1REQUIRES_VIOLATION, __ldv_list_addErr7REQUIRES_VIOLATION, __ldv_list_addErr2REQUIRES_VIOLATION, __ldv_list_addErr3REQUIRES_VIOLATION, ldv_dev_set_drvdataErr1REQUIRES_VIOLATION, ldv_dev_set_drvdataErr0REQUIRES_VIOLATION, ldv_atomic_sub_returnErr1REQUIRES_VIOLATION, ldv_atomic_sub_returnErr0REQUIRES_VIOLATION, ldv_atomic_sub_returnErr3REQUIRES_VIOLATION, ldv_atomic_sub_returnErr2REQUIRES_VIOLATION, ldv_list_add_tailErr0REQUIRES_VIOLATION, ldv_list_add_tailErr1REQUIRES_VIOLATION, ldv_dev_get_drvdataErr0REQUIRES_VIOLATION, ldv_dev_get_drvdataErr1REQUIRES_VIOLATION, ldv_msg_allocErr0REQUIRES_VIOLATION, ldv_msg_allocErr1REQUIRES_VIOLATION]=== [2018-11-28 13:03:00,365 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-28 13:03:00,365 INFO L82 PathProgramCache]: Analyzing trace with hash 1867473601, now seen corresponding path program 1 times [2018-11-28 13:03:00,365 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-28 13:03:00,366 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-28 13:03:00,366 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 13:03:00,366 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-28 13:03:00,367 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 13:03:00,375 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-28 13:03:00,472 INFO L134 CoverageAnalysis]: Checked inductivity of 15 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 15 trivial. 0 not checked. [2018-11-28 13:03:00,472 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-28 13:03:00,472 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [15] imperfect sequences [] total 15 [2018-11-28 13:03:00,472 INFO L459 AbstractCegarLoop]: Interpolant automaton has 16 states [2018-11-28 13:03:00,472 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 16 interpolants. [2018-11-28 13:03:00,473 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=29, Invalid=211, Unknown=0, NotChecked=0, Total=240 [2018-11-28 13:03:00,473 INFO L87 Difference]: Start difference. First operand 140 states and 144 transitions. Second operand 16 states. [2018-11-28 13:03:00,731 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-28 13:03:00,732 INFO L93 Difference]: Finished difference Result 138 states and 142 transitions. [2018-11-28 13:03:00,732 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 16 states. [2018-11-28 13:03:00,732 INFO L78 Accepts]: Start accepts. Automaton has 16 states. Word has length 63 [2018-11-28 13:03:00,732 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-28 13:03:00,733 INFO L225 Difference]: With dead ends: 138 [2018-11-28 13:03:00,733 INFO L226 Difference]: Without dead ends: 138 [2018-11-28 13:03:00,733 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 20 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 19 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 10 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=49, Invalid=371, Unknown=0, NotChecked=0, Total=420 [2018-11-28 13:03:00,733 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 138 states. [2018-11-28 13:03:00,735 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 138 to 138. [2018-11-28 13:03:00,735 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 138 states. [2018-11-28 13:03:00,736 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 138 states to 138 states and 142 transitions. [2018-11-28 13:03:00,736 INFO L78 Accepts]: Start accepts. Automaton has 138 states and 142 transitions. Word has length 63 [2018-11-28 13:03:00,736 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-28 13:03:00,736 INFO L480 AbstractCegarLoop]: Abstraction has 138 states and 142 transitions. [2018-11-28 13:03:00,736 INFO L481 AbstractCegarLoop]: Interpolant automaton has 16 states. [2018-11-28 13:03:00,736 INFO L276 IsEmpty]: Start isEmpty. Operand 138 states and 142 transitions. [2018-11-28 13:03:00,737 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 64 [2018-11-28 13:03:00,737 INFO L394 BasicCegarLoop]: Found error trace [2018-11-28 13:03:00,737 INFO L402 BasicCegarLoop]: trace histogram [5, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-28 13:03:00,737 INFO L423 AbstractCegarLoop]: === Iteration 18 === [ldv_kref_initErr1REQUIRES_VIOLATION, ldv_kref_initErr0REQUIRES_VIOLATION, ldv_list_addErr1REQUIRES_VIOLATION, ldv_list_addErr0REQUIRES_VIOLATION, ldv_kobject_createErr0REQUIRES_VIOLATION, ldv_kobject_createErr1REQUIRES_VIOLATION, ldv_destroy_msgsErr3REQUIRES_VIOLATION, ldv_destroy_msgsErr2REQUIRES_VIOLATION, ldv_destroy_msgsErr1REQUIRES_VIOLATION, ldv_destroy_msgsErr0REQUIRES_VIOLATION, ldv_destroy_msgsErr5REQUIRES_VIOLATION, ldv_destroy_msgsErr4REQUIRES_VIOLATION, ldv_msg_fillErr1REQUIRES_VIOLATION, ldv_msg_fillErr4REQUIRES_VIOLATION, ldv_msg_fillErr0REQUIRES_VIOLATION, ldv_msg_fillErr5REQUIRES_VIOLATION, ldv_msg_fillErr3REQUIRES_VIOLATION, ldv_msg_fillErr2REQUIRES_VIOLATION, ldv_atomic_add_returnErr1REQUIRES_VIOLATION, ldv_atomic_add_returnErr0REQUIRES_VIOLATION, ldv_atomic_add_returnErr3REQUIRES_VIOLATION, ldv_atomic_add_returnErr2REQUIRES_VIOLATION, __ldv_list_delErr0REQUIRES_VIOLATION, __ldv_list_delErr1REQUIRES_VIOLATION, __ldv_list_delErr2REQUIRES_VIOLATION, __ldv_list_delErr3REQUIRES_VIOLATION, ldv_kobject_cleanupErr2ASSERT_VIOLATIONMEMORY_FREE, ldv_kobject_cleanupErr4ASSERT_VIOLATIONMEMORY_FREE, ldv_kobject_cleanupErr0REQUIRES_VIOLATION, ldv_kobject_cleanupErr5ASSERT_VIOLATIONMEMORY_FREE, ldv_kobject_cleanupErr1REQUIRES_VIOLATION, ldv_kobject_cleanupErr3ASSERT_VIOLATIONMEMORY_FREE, ldv_msg_freeErr2ASSERT_VIOLATIONMEMORY_FREE, ldv_msg_freeErr4ASSERT_VIOLATIONMEMORY_FREE, ldv_msg_freeErr5ASSERT_VIOLATIONMEMORY_FREE, ldv_msg_freeErr0REQUIRES_VIOLATION, ldv_msg_freeErr1REQUIRES_VIOLATION, ldv_msg_freeErr3ASSERT_VIOLATIONMEMORY_FREE, mainErr0ENSURES_VIOLATIONMEMORY_LEAK, LDV_INIT_LIST_HEADErr1REQUIRES_VIOLATION, LDV_INIT_LIST_HEADErr0REQUIRES_VIOLATION, LDV_INIT_LIST_HEADErr3REQUIRES_VIOLATION, LDV_INIT_LIST_HEADErr2REQUIRES_VIOLATION, ldv_list_delErr1REQUIRES_VIOLATION, ldv_list_delErr0REQUIRES_VIOLATION, ldv_list_delErr3REQUIRES_VIOLATION, ldv_list_delErr2REQUIRES_VIOLATION, __ldv_list_addErr4REQUIRES_VIOLATION, __ldv_list_addErr5REQUIRES_VIOLATION, __ldv_list_addErr0REQUIRES_VIOLATION, __ldv_list_addErr6REQUIRES_VIOLATION, __ldv_list_addErr1REQUIRES_VIOLATION, __ldv_list_addErr7REQUIRES_VIOLATION, __ldv_list_addErr2REQUIRES_VIOLATION, __ldv_list_addErr3REQUIRES_VIOLATION, ldv_dev_set_drvdataErr1REQUIRES_VIOLATION, ldv_dev_set_drvdataErr0REQUIRES_VIOLATION, ldv_atomic_sub_returnErr1REQUIRES_VIOLATION, ldv_atomic_sub_returnErr0REQUIRES_VIOLATION, ldv_atomic_sub_returnErr3REQUIRES_VIOLATION, ldv_atomic_sub_returnErr2REQUIRES_VIOLATION, ldv_list_add_tailErr0REQUIRES_VIOLATION, ldv_list_add_tailErr1REQUIRES_VIOLATION, ldv_dev_get_drvdataErr0REQUIRES_VIOLATION, ldv_dev_get_drvdataErr1REQUIRES_VIOLATION, ldv_msg_allocErr0REQUIRES_VIOLATION, ldv_msg_allocErr1REQUIRES_VIOLATION]=== [2018-11-28 13:03:00,737 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-28 13:03:00,738 INFO L82 PathProgramCache]: Analyzing trace with hash 1867473602, now seen corresponding path program 1 times [2018-11-28 13:03:00,738 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-28 13:03:00,738 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-28 13:03:00,739 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 13:03:00,739 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-28 13:03:00,739 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 13:03:00,747 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-28 13:03:00,788 INFO L134 CoverageAnalysis]: Checked inductivity of 15 backedges. 0 proven. 15 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-28 13:03:00,788 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-28 13:03:00,788 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_a5616418-4a25-482a-a0cb-6eefe8bc17e5/bin-2019/uautomizer/z3 Starting monitored process 6 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 6 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-28 13:03:00,806 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-28 13:03:00,836 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-28 13:03:00,839 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-28 13:03:00,856 INFO L134 CoverageAnalysis]: Checked inductivity of 15 backedges. 0 proven. 15 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-28 13:03:00,871 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-11-28 13:03:00,871 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [9, 9] total 10 [2018-11-28 13:03:00,872 INFO L459 AbstractCegarLoop]: Interpolant automaton has 10 states [2018-11-28 13:03:00,872 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 10 interpolants. [2018-11-28 13:03:00,872 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=38, Invalid=52, Unknown=0, NotChecked=0, Total=90 [2018-11-28 13:03:00,872 INFO L87 Difference]: Start difference. First operand 138 states and 142 transitions. Second operand 10 states. [2018-11-28 13:03:00,897 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-28 13:03:00,897 INFO L93 Difference]: Finished difference Result 141 states and 145 transitions. [2018-11-28 13:03:00,898 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2018-11-28 13:03:00,898 INFO L78 Accepts]: Start accepts. Automaton has 10 states. Word has length 63 [2018-11-28 13:03:00,898 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-28 13:03:00,899 INFO L225 Difference]: With dead ends: 141 [2018-11-28 13:03:00,899 INFO L226 Difference]: Without dead ends: 139 [2018-11-28 13:03:00,899 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 72 GetRequests, 63 SyntacticMatches, 0 SemanticMatches, 9 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 14 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=42, Invalid=68, Unknown=0, NotChecked=0, Total=110 [2018-11-28 13:03:00,900 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 139 states. [2018-11-28 13:03:00,901 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 139 to 139. [2018-11-28 13:03:00,902 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 139 states. [2018-11-28 13:03:00,902 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 139 states to 139 states and 143 transitions. [2018-11-28 13:03:00,902 INFO L78 Accepts]: Start accepts. Automaton has 139 states and 143 transitions. Word has length 63 [2018-11-28 13:03:00,902 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-28 13:03:00,903 INFO L480 AbstractCegarLoop]: Abstraction has 139 states and 143 transitions. [2018-11-28 13:03:00,903 INFO L481 AbstractCegarLoop]: Interpolant automaton has 10 states. [2018-11-28 13:03:00,903 INFO L276 IsEmpty]: Start isEmpty. Operand 139 states and 143 transitions. [2018-11-28 13:03:00,903 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 65 [2018-11-28 13:03:00,903 INFO L394 BasicCegarLoop]: Found error trace [2018-11-28 13:03:00,903 INFO L402 BasicCegarLoop]: trace histogram [6, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-28 13:03:00,904 INFO L423 AbstractCegarLoop]: === Iteration 19 === [ldv_kref_initErr1REQUIRES_VIOLATION, ldv_kref_initErr0REQUIRES_VIOLATION, ldv_list_addErr1REQUIRES_VIOLATION, ldv_list_addErr0REQUIRES_VIOLATION, ldv_kobject_createErr0REQUIRES_VIOLATION, ldv_kobject_createErr1REQUIRES_VIOLATION, ldv_destroy_msgsErr3REQUIRES_VIOLATION, ldv_destroy_msgsErr2REQUIRES_VIOLATION, ldv_destroy_msgsErr1REQUIRES_VIOLATION, ldv_destroy_msgsErr0REQUIRES_VIOLATION, ldv_destroy_msgsErr5REQUIRES_VIOLATION, ldv_destroy_msgsErr4REQUIRES_VIOLATION, ldv_msg_fillErr1REQUIRES_VIOLATION, ldv_msg_fillErr4REQUIRES_VIOLATION, ldv_msg_fillErr0REQUIRES_VIOLATION, ldv_msg_fillErr5REQUIRES_VIOLATION, ldv_msg_fillErr3REQUIRES_VIOLATION, ldv_msg_fillErr2REQUIRES_VIOLATION, ldv_atomic_add_returnErr1REQUIRES_VIOLATION, ldv_atomic_add_returnErr0REQUIRES_VIOLATION, ldv_atomic_add_returnErr3REQUIRES_VIOLATION, ldv_atomic_add_returnErr2REQUIRES_VIOLATION, __ldv_list_delErr0REQUIRES_VIOLATION, __ldv_list_delErr1REQUIRES_VIOLATION, __ldv_list_delErr2REQUIRES_VIOLATION, __ldv_list_delErr3REQUIRES_VIOLATION, ldv_kobject_cleanupErr2ASSERT_VIOLATIONMEMORY_FREE, ldv_kobject_cleanupErr4ASSERT_VIOLATIONMEMORY_FREE, ldv_kobject_cleanupErr0REQUIRES_VIOLATION, ldv_kobject_cleanupErr5ASSERT_VIOLATIONMEMORY_FREE, ldv_kobject_cleanupErr1REQUIRES_VIOLATION, ldv_kobject_cleanupErr3ASSERT_VIOLATIONMEMORY_FREE, ldv_msg_freeErr2ASSERT_VIOLATIONMEMORY_FREE, ldv_msg_freeErr4ASSERT_VIOLATIONMEMORY_FREE, ldv_msg_freeErr5ASSERT_VIOLATIONMEMORY_FREE, ldv_msg_freeErr0REQUIRES_VIOLATION, ldv_msg_freeErr1REQUIRES_VIOLATION, ldv_msg_freeErr3ASSERT_VIOLATIONMEMORY_FREE, mainErr0ENSURES_VIOLATIONMEMORY_LEAK, LDV_INIT_LIST_HEADErr1REQUIRES_VIOLATION, LDV_INIT_LIST_HEADErr0REQUIRES_VIOLATION, LDV_INIT_LIST_HEADErr3REQUIRES_VIOLATION, LDV_INIT_LIST_HEADErr2REQUIRES_VIOLATION, ldv_list_delErr1REQUIRES_VIOLATION, ldv_list_delErr0REQUIRES_VIOLATION, ldv_list_delErr3REQUIRES_VIOLATION, ldv_list_delErr2REQUIRES_VIOLATION, __ldv_list_addErr4REQUIRES_VIOLATION, __ldv_list_addErr5REQUIRES_VIOLATION, __ldv_list_addErr0REQUIRES_VIOLATION, __ldv_list_addErr6REQUIRES_VIOLATION, __ldv_list_addErr1REQUIRES_VIOLATION, __ldv_list_addErr7REQUIRES_VIOLATION, __ldv_list_addErr2REQUIRES_VIOLATION, __ldv_list_addErr3REQUIRES_VIOLATION, ldv_dev_set_drvdataErr1REQUIRES_VIOLATION, ldv_dev_set_drvdataErr0REQUIRES_VIOLATION, ldv_atomic_sub_returnErr1REQUIRES_VIOLATION, ldv_atomic_sub_returnErr0REQUIRES_VIOLATION, ldv_atomic_sub_returnErr3REQUIRES_VIOLATION, ldv_atomic_sub_returnErr2REQUIRES_VIOLATION, ldv_list_add_tailErr0REQUIRES_VIOLATION, ldv_list_add_tailErr1REQUIRES_VIOLATION, ldv_dev_get_drvdataErr0REQUIRES_VIOLATION, ldv_dev_get_drvdataErr1REQUIRES_VIOLATION, ldv_msg_allocErr0REQUIRES_VIOLATION, ldv_msg_allocErr1REQUIRES_VIOLATION]=== [2018-11-28 13:03:00,904 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-28 13:03:00,904 INFO L82 PathProgramCache]: Analyzing trace with hash 1992709759, now seen corresponding path program 2 times [2018-11-28 13:03:00,904 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-28 13:03:00,904 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-28 13:03:00,905 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 13:03:00,905 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-28 13:03:00,905 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 13:03:00,915 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-28 13:03:00,963 INFO L134 CoverageAnalysis]: Checked inductivity of 21 backedges. 0 proven. 21 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-28 13:03:00,963 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-28 13:03:00,964 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_a5616418-4a25-482a-a0cb-6eefe8bc17e5/bin-2019/uautomizer/z3 Starting monitored process 7 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 7 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-28 13:03:00,976 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-11-28 13:03:01,007 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) [2018-11-28 13:03:01,007 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-11-28 13:03:01,010 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-28 13:03:01,024 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 6 treesize of output 5 [2018-11-28 13:03:01,025 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-11-28 13:03:01,033 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-0 vars, 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-28 13:03:01,033 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 2 variables, input treesize:13, output treesize:9 [2018-11-28 13:03:01,255 INFO L134 CoverageAnalysis]: Checked inductivity of 21 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 21 trivial. 0 not checked. [2018-11-28 13:03:01,270 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 1 imperfect interpolant sequences. [2018-11-28 13:03:01,270 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [17] imperfect sequences [10] total 26 [2018-11-28 13:03:01,270 INFO L459 AbstractCegarLoop]: Interpolant automaton has 26 states [2018-11-28 13:03:01,270 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 26 interpolants. [2018-11-28 13:03:01,271 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=83, Invalid=567, Unknown=0, NotChecked=0, Total=650 [2018-11-28 13:03:01,271 INFO L87 Difference]: Start difference. First operand 139 states and 143 transitions. Second operand 26 states. [2018-11-28 13:03:01,893 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-28 13:03:01,893 INFO L93 Difference]: Finished difference Result 140 states and 144 transitions. [2018-11-28 13:03:01,893 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 26 states. [2018-11-28 13:03:01,893 INFO L78 Accepts]: Start accepts. Automaton has 26 states. Word has length 64 [2018-11-28 13:03:01,894 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-28 13:03:01,894 INFO L225 Difference]: With dead ends: 140 [2018-11-28 13:03:01,894 INFO L226 Difference]: Without dead ends: 138 [2018-11-28 13:03:01,895 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 87 GetRequests, 46 SyntacticMatches, 3 SemanticMatches, 38 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 236 ImplicationChecksByTransitivity, 0.4s TimeCoverageRelationStatistics Valid=188, Invalid=1372, Unknown=0, NotChecked=0, Total=1560 [2018-11-28 13:03:01,895 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 138 states. [2018-11-28 13:03:01,897 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 138 to 138. [2018-11-28 13:03:01,897 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 138 states. [2018-11-28 13:03:01,898 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 138 states to 138 states and 142 transitions. [2018-11-28 13:03:01,898 INFO L78 Accepts]: Start accepts. Automaton has 138 states and 142 transitions. Word has length 64 [2018-11-28 13:03:01,898 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-28 13:03:01,898 INFO L480 AbstractCegarLoop]: Abstraction has 138 states and 142 transitions. [2018-11-28 13:03:01,898 INFO L481 AbstractCegarLoop]: Interpolant automaton has 26 states. [2018-11-28 13:03:01,898 INFO L276 IsEmpty]: Start isEmpty. Operand 138 states and 142 transitions. [2018-11-28 13:03:01,899 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 77 [2018-11-28 13:03:01,899 INFO L394 BasicCegarLoop]: Found error trace [2018-11-28 13:03:01,899 INFO L402 BasicCegarLoop]: trace histogram [7, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-28 13:03:01,899 INFO L423 AbstractCegarLoop]: === Iteration 20 === [ldv_kref_initErr1REQUIRES_VIOLATION, ldv_kref_initErr0REQUIRES_VIOLATION, ldv_list_addErr1REQUIRES_VIOLATION, ldv_list_addErr0REQUIRES_VIOLATION, ldv_kobject_createErr0REQUIRES_VIOLATION, ldv_kobject_createErr1REQUIRES_VIOLATION, ldv_destroy_msgsErr3REQUIRES_VIOLATION, ldv_destroy_msgsErr2REQUIRES_VIOLATION, ldv_destroy_msgsErr1REQUIRES_VIOLATION, ldv_destroy_msgsErr0REQUIRES_VIOLATION, ldv_destroy_msgsErr5REQUIRES_VIOLATION, ldv_destroy_msgsErr4REQUIRES_VIOLATION, ldv_msg_fillErr1REQUIRES_VIOLATION, ldv_msg_fillErr4REQUIRES_VIOLATION, ldv_msg_fillErr0REQUIRES_VIOLATION, ldv_msg_fillErr5REQUIRES_VIOLATION, ldv_msg_fillErr3REQUIRES_VIOLATION, ldv_msg_fillErr2REQUIRES_VIOLATION, ldv_atomic_add_returnErr1REQUIRES_VIOLATION, ldv_atomic_add_returnErr0REQUIRES_VIOLATION, ldv_atomic_add_returnErr3REQUIRES_VIOLATION, ldv_atomic_add_returnErr2REQUIRES_VIOLATION, __ldv_list_delErr0REQUIRES_VIOLATION, __ldv_list_delErr1REQUIRES_VIOLATION, __ldv_list_delErr2REQUIRES_VIOLATION, __ldv_list_delErr3REQUIRES_VIOLATION, ldv_kobject_cleanupErr2ASSERT_VIOLATIONMEMORY_FREE, ldv_kobject_cleanupErr4ASSERT_VIOLATIONMEMORY_FREE, ldv_kobject_cleanupErr0REQUIRES_VIOLATION, ldv_kobject_cleanupErr5ASSERT_VIOLATIONMEMORY_FREE, ldv_kobject_cleanupErr1REQUIRES_VIOLATION, ldv_kobject_cleanupErr3ASSERT_VIOLATIONMEMORY_FREE, ldv_msg_freeErr2ASSERT_VIOLATIONMEMORY_FREE, ldv_msg_freeErr4ASSERT_VIOLATIONMEMORY_FREE, ldv_msg_freeErr5ASSERT_VIOLATIONMEMORY_FREE, ldv_msg_freeErr0REQUIRES_VIOLATION, ldv_msg_freeErr1REQUIRES_VIOLATION, ldv_msg_freeErr3ASSERT_VIOLATIONMEMORY_FREE, mainErr0ENSURES_VIOLATIONMEMORY_LEAK, LDV_INIT_LIST_HEADErr1REQUIRES_VIOLATION, LDV_INIT_LIST_HEADErr0REQUIRES_VIOLATION, LDV_INIT_LIST_HEADErr3REQUIRES_VIOLATION, LDV_INIT_LIST_HEADErr2REQUIRES_VIOLATION, ldv_list_delErr1REQUIRES_VIOLATION, ldv_list_delErr0REQUIRES_VIOLATION, ldv_list_delErr3REQUIRES_VIOLATION, ldv_list_delErr2REQUIRES_VIOLATION, __ldv_list_addErr4REQUIRES_VIOLATION, __ldv_list_addErr5REQUIRES_VIOLATION, __ldv_list_addErr0REQUIRES_VIOLATION, __ldv_list_addErr6REQUIRES_VIOLATION, __ldv_list_addErr1REQUIRES_VIOLATION, __ldv_list_addErr7REQUIRES_VIOLATION, __ldv_list_addErr2REQUIRES_VIOLATION, __ldv_list_addErr3REQUIRES_VIOLATION, ldv_dev_set_drvdataErr1REQUIRES_VIOLATION, ldv_dev_set_drvdataErr0REQUIRES_VIOLATION, ldv_atomic_sub_returnErr1REQUIRES_VIOLATION, ldv_atomic_sub_returnErr0REQUIRES_VIOLATION, ldv_atomic_sub_returnErr3REQUIRES_VIOLATION, ldv_atomic_sub_returnErr2REQUIRES_VIOLATION, ldv_list_add_tailErr0REQUIRES_VIOLATION, ldv_list_add_tailErr1REQUIRES_VIOLATION, ldv_dev_get_drvdataErr0REQUIRES_VIOLATION, ldv_dev_get_drvdataErr1REQUIRES_VIOLATION, ldv_msg_allocErr0REQUIRES_VIOLATION, ldv_msg_allocErr1REQUIRES_VIOLATION]=== [2018-11-28 13:03:01,900 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-28 13:03:01,900 INFO L82 PathProgramCache]: Analyzing trace with hash -1203634192, now seen corresponding path program 1 times [2018-11-28 13:03:01,900 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-28 13:03:01,900 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-28 13:03:01,901 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 13:03:01,901 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-28 13:03:01,901 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 13:03:01,912 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-28 13:03:01,988 INFO L134 CoverageAnalysis]: Checked inductivity of 28 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 28 trivial. 0 not checked. [2018-11-28 13:03:01,988 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-28 13:03:01,988 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [12] imperfect sequences [] total 12 [2018-11-28 13:03:01,988 INFO L459 AbstractCegarLoop]: Interpolant automaton has 12 states [2018-11-28 13:03:01,989 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 12 interpolants. [2018-11-28 13:03:01,989 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=21, Invalid=111, Unknown=0, NotChecked=0, Total=132 [2018-11-28 13:03:01,989 INFO L87 Difference]: Start difference. First operand 138 states and 142 transitions. Second operand 12 states. [2018-11-28 13:03:02,035 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-28 13:03:02,036 INFO L93 Difference]: Finished difference Result 144 states and 147 transitions. [2018-11-28 13:03:02,037 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 12 states. [2018-11-28 13:03:02,037 INFO L78 Accepts]: Start accepts. Automaton has 12 states. Word has length 76 [2018-11-28 13:03:02,037 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-28 13:03:02,038 INFO L225 Difference]: With dead ends: 144 [2018-11-28 13:03:02,038 INFO L226 Difference]: Without dead ends: 138 [2018-11-28 13:03:02,038 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 15 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 13 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 3 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=33, Invalid=177, Unknown=0, NotChecked=0, Total=210 [2018-11-28 13:03:02,038 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 138 states. [2018-11-28 13:03:02,040 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 138 to 138. [2018-11-28 13:03:02,040 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 138 states. [2018-11-28 13:03:02,041 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 138 states to 138 states and 141 transitions. [2018-11-28 13:03:02,041 INFO L78 Accepts]: Start accepts. Automaton has 138 states and 141 transitions. Word has length 76 [2018-11-28 13:03:02,041 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-28 13:03:02,042 INFO L480 AbstractCegarLoop]: Abstraction has 138 states and 141 transitions. [2018-11-28 13:03:02,042 INFO L481 AbstractCegarLoop]: Interpolant automaton has 12 states. [2018-11-28 13:03:02,042 INFO L276 IsEmpty]: Start isEmpty. Operand 138 states and 141 transitions. [2018-11-28 13:03:02,042 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 90 [2018-11-28 13:03:02,043 INFO L394 BasicCegarLoop]: Found error trace [2018-11-28 13:03:02,043 INFO L402 BasicCegarLoop]: trace histogram [7, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-28 13:03:02,043 INFO L423 AbstractCegarLoop]: === Iteration 21 === [ldv_kref_initErr1REQUIRES_VIOLATION, ldv_kref_initErr0REQUIRES_VIOLATION, ldv_list_addErr1REQUIRES_VIOLATION, ldv_list_addErr0REQUIRES_VIOLATION, ldv_kobject_createErr0REQUIRES_VIOLATION, ldv_kobject_createErr1REQUIRES_VIOLATION, ldv_destroy_msgsErr3REQUIRES_VIOLATION, ldv_destroy_msgsErr2REQUIRES_VIOLATION, ldv_destroy_msgsErr1REQUIRES_VIOLATION, ldv_destroy_msgsErr0REQUIRES_VIOLATION, ldv_destroy_msgsErr5REQUIRES_VIOLATION, ldv_destroy_msgsErr4REQUIRES_VIOLATION, ldv_msg_fillErr1REQUIRES_VIOLATION, ldv_msg_fillErr4REQUIRES_VIOLATION, ldv_msg_fillErr0REQUIRES_VIOLATION, ldv_msg_fillErr5REQUIRES_VIOLATION, ldv_msg_fillErr3REQUIRES_VIOLATION, ldv_msg_fillErr2REQUIRES_VIOLATION, ldv_atomic_add_returnErr1REQUIRES_VIOLATION, ldv_atomic_add_returnErr0REQUIRES_VIOLATION, ldv_atomic_add_returnErr3REQUIRES_VIOLATION, ldv_atomic_add_returnErr2REQUIRES_VIOLATION, __ldv_list_delErr0REQUIRES_VIOLATION, __ldv_list_delErr1REQUIRES_VIOLATION, __ldv_list_delErr2REQUIRES_VIOLATION, __ldv_list_delErr3REQUIRES_VIOLATION, ldv_kobject_cleanupErr2ASSERT_VIOLATIONMEMORY_FREE, ldv_kobject_cleanupErr4ASSERT_VIOLATIONMEMORY_FREE, ldv_kobject_cleanupErr0REQUIRES_VIOLATION, ldv_kobject_cleanupErr5ASSERT_VIOLATIONMEMORY_FREE, ldv_kobject_cleanupErr1REQUIRES_VIOLATION, ldv_kobject_cleanupErr3ASSERT_VIOLATIONMEMORY_FREE, ldv_msg_freeErr2ASSERT_VIOLATIONMEMORY_FREE, ldv_msg_freeErr4ASSERT_VIOLATIONMEMORY_FREE, ldv_msg_freeErr5ASSERT_VIOLATIONMEMORY_FREE, ldv_msg_freeErr0REQUIRES_VIOLATION, ldv_msg_freeErr1REQUIRES_VIOLATION, ldv_msg_freeErr3ASSERT_VIOLATIONMEMORY_FREE, mainErr0ENSURES_VIOLATIONMEMORY_LEAK, LDV_INIT_LIST_HEADErr1REQUIRES_VIOLATION, LDV_INIT_LIST_HEADErr0REQUIRES_VIOLATION, LDV_INIT_LIST_HEADErr3REQUIRES_VIOLATION, LDV_INIT_LIST_HEADErr2REQUIRES_VIOLATION, ldv_list_delErr1REQUIRES_VIOLATION, ldv_list_delErr0REQUIRES_VIOLATION, ldv_list_delErr3REQUIRES_VIOLATION, ldv_list_delErr2REQUIRES_VIOLATION, __ldv_list_addErr4REQUIRES_VIOLATION, __ldv_list_addErr5REQUIRES_VIOLATION, __ldv_list_addErr0REQUIRES_VIOLATION, __ldv_list_addErr6REQUIRES_VIOLATION, __ldv_list_addErr1REQUIRES_VIOLATION, __ldv_list_addErr7REQUIRES_VIOLATION, __ldv_list_addErr2REQUIRES_VIOLATION, __ldv_list_addErr3REQUIRES_VIOLATION, ldv_dev_set_drvdataErr1REQUIRES_VIOLATION, ldv_dev_set_drvdataErr0REQUIRES_VIOLATION, ldv_atomic_sub_returnErr1REQUIRES_VIOLATION, ldv_atomic_sub_returnErr0REQUIRES_VIOLATION, ldv_atomic_sub_returnErr3REQUIRES_VIOLATION, ldv_atomic_sub_returnErr2REQUIRES_VIOLATION, ldv_list_add_tailErr0REQUIRES_VIOLATION, ldv_list_add_tailErr1REQUIRES_VIOLATION, ldv_dev_get_drvdataErr0REQUIRES_VIOLATION, ldv_dev_get_drvdataErr1REQUIRES_VIOLATION, ldv_msg_allocErr0REQUIRES_VIOLATION, ldv_msg_allocErr1REQUIRES_VIOLATION]=== [2018-11-28 13:03:02,043 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-28 13:03:02,043 INFO L82 PathProgramCache]: Analyzing trace with hash -1506633113, now seen corresponding path program 1 times [2018-11-28 13:03:02,043 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-28 13:03:02,043 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-28 13:03:02,044 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 13:03:02,044 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-28 13:03:02,045 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 13:03:02,056 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-28 13:03:02,176 INFO L134 CoverageAnalysis]: Checked inductivity of 28 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 28 trivial. 0 not checked. [2018-11-28 13:03:02,176 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-28 13:03:02,176 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [15] imperfect sequences [] total 15 [2018-11-28 13:03:02,177 INFO L459 AbstractCegarLoop]: Interpolant automaton has 16 states [2018-11-28 13:03:02,177 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 16 interpolants. [2018-11-28 13:03:02,177 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=29, Invalid=211, Unknown=0, NotChecked=0, Total=240 [2018-11-28 13:03:02,177 INFO L87 Difference]: Start difference. First operand 138 states and 141 transitions. Second operand 16 states. [2018-11-28 13:03:02,466 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-28 13:03:02,466 INFO L93 Difference]: Finished difference Result 145 states and 148 transitions. [2018-11-28 13:03:02,466 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 17 states. [2018-11-28 13:03:02,466 INFO L78 Accepts]: Start accepts. Automaton has 16 states. Word has length 89 [2018-11-28 13:03:02,467 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-28 13:03:02,467 INFO L225 Difference]: With dead ends: 145 [2018-11-28 13:03:02,467 INFO L226 Difference]: Without dead ends: 145 [2018-11-28 13:03:02,468 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 20 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 19 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 10 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=49, Invalid=371, Unknown=0, NotChecked=0, Total=420 [2018-11-28 13:03:02,468 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 145 states. [2018-11-28 13:03:02,470 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 145 to 136. [2018-11-28 13:03:02,470 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 136 states. [2018-11-28 13:03:02,470 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 136 states to 136 states and 139 transitions. [2018-11-28 13:03:02,471 INFO L78 Accepts]: Start accepts. Automaton has 136 states and 139 transitions. Word has length 89 [2018-11-28 13:03:02,471 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-28 13:03:02,471 INFO L480 AbstractCegarLoop]: Abstraction has 136 states and 139 transitions. [2018-11-28 13:03:02,471 INFO L481 AbstractCegarLoop]: Interpolant automaton has 16 states. [2018-11-28 13:03:02,471 INFO L276 IsEmpty]: Start isEmpty. Operand 136 states and 139 transitions. [2018-11-28 13:03:02,472 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 90 [2018-11-28 13:03:02,472 INFO L394 BasicCegarLoop]: Found error trace [2018-11-28 13:03:02,472 INFO L402 BasicCegarLoop]: trace histogram [7, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-28 13:03:02,472 INFO L423 AbstractCegarLoop]: === Iteration 22 === [ldv_kref_initErr1REQUIRES_VIOLATION, ldv_kref_initErr0REQUIRES_VIOLATION, ldv_list_addErr1REQUIRES_VIOLATION, ldv_list_addErr0REQUIRES_VIOLATION, ldv_kobject_createErr0REQUIRES_VIOLATION, ldv_kobject_createErr1REQUIRES_VIOLATION, ldv_destroy_msgsErr3REQUIRES_VIOLATION, ldv_destroy_msgsErr2REQUIRES_VIOLATION, ldv_destroy_msgsErr1REQUIRES_VIOLATION, ldv_destroy_msgsErr0REQUIRES_VIOLATION, ldv_destroy_msgsErr5REQUIRES_VIOLATION, ldv_destroy_msgsErr4REQUIRES_VIOLATION, ldv_msg_fillErr1REQUIRES_VIOLATION, ldv_msg_fillErr4REQUIRES_VIOLATION, ldv_msg_fillErr0REQUIRES_VIOLATION, ldv_msg_fillErr5REQUIRES_VIOLATION, ldv_msg_fillErr3REQUIRES_VIOLATION, ldv_msg_fillErr2REQUIRES_VIOLATION, ldv_atomic_add_returnErr1REQUIRES_VIOLATION, ldv_atomic_add_returnErr0REQUIRES_VIOLATION, ldv_atomic_add_returnErr3REQUIRES_VIOLATION, ldv_atomic_add_returnErr2REQUIRES_VIOLATION, __ldv_list_delErr0REQUIRES_VIOLATION, __ldv_list_delErr1REQUIRES_VIOLATION, __ldv_list_delErr2REQUIRES_VIOLATION, __ldv_list_delErr3REQUIRES_VIOLATION, ldv_kobject_cleanupErr2ASSERT_VIOLATIONMEMORY_FREE, ldv_kobject_cleanupErr4ASSERT_VIOLATIONMEMORY_FREE, ldv_kobject_cleanupErr0REQUIRES_VIOLATION, ldv_kobject_cleanupErr5ASSERT_VIOLATIONMEMORY_FREE, ldv_kobject_cleanupErr1REQUIRES_VIOLATION, ldv_kobject_cleanupErr3ASSERT_VIOLATIONMEMORY_FREE, ldv_msg_freeErr2ASSERT_VIOLATIONMEMORY_FREE, ldv_msg_freeErr4ASSERT_VIOLATIONMEMORY_FREE, ldv_msg_freeErr5ASSERT_VIOLATIONMEMORY_FREE, ldv_msg_freeErr0REQUIRES_VIOLATION, ldv_msg_freeErr1REQUIRES_VIOLATION, ldv_msg_freeErr3ASSERT_VIOLATIONMEMORY_FREE, mainErr0ENSURES_VIOLATIONMEMORY_LEAK, LDV_INIT_LIST_HEADErr1REQUIRES_VIOLATION, LDV_INIT_LIST_HEADErr0REQUIRES_VIOLATION, LDV_INIT_LIST_HEADErr3REQUIRES_VIOLATION, LDV_INIT_LIST_HEADErr2REQUIRES_VIOLATION, ldv_list_delErr1REQUIRES_VIOLATION, ldv_list_delErr0REQUIRES_VIOLATION, ldv_list_delErr3REQUIRES_VIOLATION, ldv_list_delErr2REQUIRES_VIOLATION, __ldv_list_addErr4REQUIRES_VIOLATION, __ldv_list_addErr5REQUIRES_VIOLATION, __ldv_list_addErr0REQUIRES_VIOLATION, __ldv_list_addErr6REQUIRES_VIOLATION, __ldv_list_addErr1REQUIRES_VIOLATION, __ldv_list_addErr7REQUIRES_VIOLATION, __ldv_list_addErr2REQUIRES_VIOLATION, __ldv_list_addErr3REQUIRES_VIOLATION, ldv_dev_set_drvdataErr1REQUIRES_VIOLATION, ldv_dev_set_drvdataErr0REQUIRES_VIOLATION, ldv_atomic_sub_returnErr1REQUIRES_VIOLATION, ldv_atomic_sub_returnErr0REQUIRES_VIOLATION, ldv_atomic_sub_returnErr3REQUIRES_VIOLATION, ldv_atomic_sub_returnErr2REQUIRES_VIOLATION, ldv_list_add_tailErr0REQUIRES_VIOLATION, ldv_list_add_tailErr1REQUIRES_VIOLATION, ldv_dev_get_drvdataErr0REQUIRES_VIOLATION, ldv_dev_get_drvdataErr1REQUIRES_VIOLATION, ldv_msg_allocErr0REQUIRES_VIOLATION, ldv_msg_allocErr1REQUIRES_VIOLATION]=== [2018-11-28 13:03:02,472 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-28 13:03:02,472 INFO L82 PathProgramCache]: Analyzing trace with hash -1506633112, now seen corresponding path program 1 times [2018-11-28 13:03:02,472 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-28 13:03:02,473 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-28 13:03:02,473 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 13:03:02,473 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-28 13:03:02,473 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 13:03:02,485 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-28 13:03:02,545 INFO L134 CoverageAnalysis]: Checked inductivity of 28 backedges. 0 proven. 28 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-28 13:03:02,545 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-28 13:03:02,545 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_a5616418-4a25-482a-a0cb-6eefe8bc17e5/bin-2019/uautomizer/z3 Starting monitored process 8 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 8 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-28 13:03:02,566 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-28 13:03:02,606 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-28 13:03:02,609 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-28 13:03:02,620 INFO L134 CoverageAnalysis]: Checked inductivity of 28 backedges. 0 proven. 28 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-28 13:03:02,636 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-11-28 13:03:02,636 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [11, 11] total 12 [2018-11-28 13:03:02,636 INFO L459 AbstractCegarLoop]: Interpolant automaton has 12 states [2018-11-28 13:03:02,637 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 12 interpolants. [2018-11-28 13:03:02,637 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=57, Invalid=75, Unknown=0, NotChecked=0, Total=132 [2018-11-28 13:03:02,637 INFO L87 Difference]: Start difference. First operand 136 states and 139 transitions. Second operand 12 states. [2018-11-28 13:03:02,673 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-28 13:03:02,673 INFO L93 Difference]: Finished difference Result 139 states and 142 transitions. [2018-11-28 13:03:02,676 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 11 states. [2018-11-28 13:03:02,676 INFO L78 Accepts]: Start accepts. Automaton has 12 states. Word has length 89 [2018-11-28 13:03:02,677 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-28 13:03:02,677 INFO L225 Difference]: With dead ends: 139 [2018-11-28 13:03:02,677 INFO L226 Difference]: Without dead ends: 137 [2018-11-28 13:03:02,677 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 100 GetRequests, 89 SyntacticMatches, 0 SemanticMatches, 11 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 20 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=61, Invalid=95, Unknown=0, NotChecked=0, Total=156 [2018-11-28 13:03:02,678 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 137 states. [2018-11-28 13:03:02,679 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 137 to 137. [2018-11-28 13:03:02,680 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 137 states. [2018-11-28 13:03:02,684 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 137 states to 137 states and 140 transitions. [2018-11-28 13:03:02,684 INFO L78 Accepts]: Start accepts. Automaton has 137 states and 140 transitions. Word has length 89 [2018-11-28 13:03:02,684 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-28 13:03:02,684 INFO L480 AbstractCegarLoop]: Abstraction has 137 states and 140 transitions. [2018-11-28 13:03:02,684 INFO L481 AbstractCegarLoop]: Interpolant automaton has 12 states. [2018-11-28 13:03:02,684 INFO L276 IsEmpty]: Start isEmpty. Operand 137 states and 140 transitions. [2018-11-28 13:03:02,685 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 91 [2018-11-28 13:03:02,685 INFO L394 BasicCegarLoop]: Found error trace [2018-11-28 13:03:02,685 INFO L402 BasicCegarLoop]: trace histogram [8, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-28 13:03:02,685 INFO L423 AbstractCegarLoop]: === Iteration 23 === [ldv_kref_initErr1REQUIRES_VIOLATION, ldv_kref_initErr0REQUIRES_VIOLATION, ldv_list_addErr1REQUIRES_VIOLATION, ldv_list_addErr0REQUIRES_VIOLATION, ldv_kobject_createErr0REQUIRES_VIOLATION, ldv_kobject_createErr1REQUIRES_VIOLATION, ldv_destroy_msgsErr3REQUIRES_VIOLATION, ldv_destroy_msgsErr2REQUIRES_VIOLATION, ldv_destroy_msgsErr1REQUIRES_VIOLATION, ldv_destroy_msgsErr0REQUIRES_VIOLATION, ldv_destroy_msgsErr5REQUIRES_VIOLATION, ldv_destroy_msgsErr4REQUIRES_VIOLATION, ldv_msg_fillErr1REQUIRES_VIOLATION, ldv_msg_fillErr4REQUIRES_VIOLATION, ldv_msg_fillErr0REQUIRES_VIOLATION, ldv_msg_fillErr5REQUIRES_VIOLATION, ldv_msg_fillErr3REQUIRES_VIOLATION, ldv_msg_fillErr2REQUIRES_VIOLATION, ldv_atomic_add_returnErr1REQUIRES_VIOLATION, ldv_atomic_add_returnErr0REQUIRES_VIOLATION, ldv_atomic_add_returnErr3REQUIRES_VIOLATION, ldv_atomic_add_returnErr2REQUIRES_VIOLATION, __ldv_list_delErr0REQUIRES_VIOLATION, __ldv_list_delErr1REQUIRES_VIOLATION, __ldv_list_delErr2REQUIRES_VIOLATION, __ldv_list_delErr3REQUIRES_VIOLATION, ldv_kobject_cleanupErr2ASSERT_VIOLATIONMEMORY_FREE, ldv_kobject_cleanupErr4ASSERT_VIOLATIONMEMORY_FREE, ldv_kobject_cleanupErr0REQUIRES_VIOLATION, ldv_kobject_cleanupErr5ASSERT_VIOLATIONMEMORY_FREE, ldv_kobject_cleanupErr1REQUIRES_VIOLATION, ldv_kobject_cleanupErr3ASSERT_VIOLATIONMEMORY_FREE, ldv_msg_freeErr2ASSERT_VIOLATIONMEMORY_FREE, ldv_msg_freeErr4ASSERT_VIOLATIONMEMORY_FREE, ldv_msg_freeErr5ASSERT_VIOLATIONMEMORY_FREE, ldv_msg_freeErr0REQUIRES_VIOLATION, ldv_msg_freeErr1REQUIRES_VIOLATION, ldv_msg_freeErr3ASSERT_VIOLATIONMEMORY_FREE, mainErr0ENSURES_VIOLATIONMEMORY_LEAK, LDV_INIT_LIST_HEADErr1REQUIRES_VIOLATION, LDV_INIT_LIST_HEADErr0REQUIRES_VIOLATION, LDV_INIT_LIST_HEADErr3REQUIRES_VIOLATION, LDV_INIT_LIST_HEADErr2REQUIRES_VIOLATION, ldv_list_delErr1REQUIRES_VIOLATION, ldv_list_delErr0REQUIRES_VIOLATION, ldv_list_delErr3REQUIRES_VIOLATION, ldv_list_delErr2REQUIRES_VIOLATION, __ldv_list_addErr4REQUIRES_VIOLATION, __ldv_list_addErr5REQUIRES_VIOLATION, __ldv_list_addErr0REQUIRES_VIOLATION, __ldv_list_addErr6REQUIRES_VIOLATION, __ldv_list_addErr1REQUIRES_VIOLATION, __ldv_list_addErr7REQUIRES_VIOLATION, __ldv_list_addErr2REQUIRES_VIOLATION, __ldv_list_addErr3REQUIRES_VIOLATION, ldv_dev_set_drvdataErr1REQUIRES_VIOLATION, ldv_dev_set_drvdataErr0REQUIRES_VIOLATION, ldv_atomic_sub_returnErr1REQUIRES_VIOLATION, ldv_atomic_sub_returnErr0REQUIRES_VIOLATION, ldv_atomic_sub_returnErr3REQUIRES_VIOLATION, ldv_atomic_sub_returnErr2REQUIRES_VIOLATION, ldv_list_add_tailErr0REQUIRES_VIOLATION, ldv_list_add_tailErr1REQUIRES_VIOLATION, ldv_dev_get_drvdataErr0REQUIRES_VIOLATION, ldv_dev_get_drvdataErr1REQUIRES_VIOLATION, ldv_msg_allocErr0REQUIRES_VIOLATION, ldv_msg_allocErr1REQUIRES_VIOLATION]=== [2018-11-28 13:03:02,686 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-28 13:03:02,686 INFO L82 PathProgramCache]: Analyzing trace with hash -370594843, now seen corresponding path program 2 times [2018-11-28 13:03:02,686 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-28 13:03:02,686 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-28 13:03:02,687 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 13:03:02,687 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-28 13:03:02,687 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 13:03:02,709 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-28 13:03:02,789 INFO L134 CoverageAnalysis]: Checked inductivity of 36 backedges. 0 proven. 36 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-28 13:03:02,789 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-28 13:03:02,789 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_a5616418-4a25-482a-a0cb-6eefe8bc17e5/bin-2019/uautomizer/z3 Starting monitored process 9 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 9 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-28 13:03:02,804 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-11-28 13:03:02,857 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) [2018-11-28 13:03:02,857 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-11-28 13:03:02,862 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-28 13:03:02,904 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 6 treesize of output 5 [2018-11-28 13:03:02,904 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-11-28 13:03:02,910 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-0 vars, 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-28 13:03:02,910 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 2 variables, input treesize:13, output treesize:9 [2018-11-28 13:03:03,242 INFO L134 CoverageAnalysis]: Checked inductivity of 36 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 36 trivial. 0 not checked. [2018-11-28 13:03:03,267 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 1 imperfect interpolant sequences. [2018-11-28 13:03:03,267 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [18] imperfect sequences [12] total 29 [2018-11-28 13:03:03,267 INFO L459 AbstractCegarLoop]: Interpolant automaton has 29 states [2018-11-28 13:03:03,267 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 29 interpolants. [2018-11-28 13:03:03,268 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=105, Invalid=707, Unknown=0, NotChecked=0, Total=812 [2018-11-28 13:03:03,268 INFO L87 Difference]: Start difference. First operand 137 states and 140 transitions. Second operand 29 states. [2018-11-28 13:03:03,986 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-28 13:03:03,986 INFO L93 Difference]: Finished difference Result 138 states and 141 transitions. [2018-11-28 13:03:03,986 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 29 states. [2018-11-28 13:03:03,986 INFO L78 Accepts]: Start accepts. Automaton has 29 states. Word has length 90 [2018-11-28 13:03:03,986 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-28 13:03:03,987 INFO L225 Difference]: With dead ends: 138 [2018-11-28 13:03:03,987 INFO L226 Difference]: Without dead ends: 136 [2018-11-28 13:03:03,987 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 117 GetRequests, 69 SyntacticMatches, 5 SemanticMatches, 43 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 337 ImplicationChecksByTransitivity, 0.5s TimeCoverageRelationStatistics Valid=258, Invalid=1722, Unknown=0, NotChecked=0, Total=1980 [2018-11-28 13:03:03,987 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 136 states. [2018-11-28 13:03:03,990 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 136 to 136. [2018-11-28 13:03:03,990 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 136 states. [2018-11-28 13:03:03,990 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 136 states to 136 states and 139 transitions. [2018-11-28 13:03:03,991 INFO L78 Accepts]: Start accepts. Automaton has 136 states and 139 transitions. Word has length 90 [2018-11-28 13:03:03,991 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-28 13:03:03,991 INFO L480 AbstractCegarLoop]: Abstraction has 136 states and 139 transitions. [2018-11-28 13:03:03,991 INFO L481 AbstractCegarLoop]: Interpolant automaton has 29 states. [2018-11-28 13:03:03,991 INFO L276 IsEmpty]: Start isEmpty. Operand 136 states and 139 transitions. [2018-11-28 13:03:03,991 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 90 [2018-11-28 13:03:03,992 INFO L394 BasicCegarLoop]: Found error trace [2018-11-28 13:03:03,992 INFO L402 BasicCegarLoop]: trace histogram [9, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-28 13:03:03,992 INFO L423 AbstractCegarLoop]: === Iteration 24 === [ldv_kref_initErr1REQUIRES_VIOLATION, ldv_kref_initErr0REQUIRES_VIOLATION, ldv_list_addErr1REQUIRES_VIOLATION, ldv_list_addErr0REQUIRES_VIOLATION, ldv_kobject_createErr0REQUIRES_VIOLATION, ldv_kobject_createErr1REQUIRES_VIOLATION, ldv_destroy_msgsErr3REQUIRES_VIOLATION, ldv_destroy_msgsErr2REQUIRES_VIOLATION, ldv_destroy_msgsErr1REQUIRES_VIOLATION, ldv_destroy_msgsErr0REQUIRES_VIOLATION, ldv_destroy_msgsErr5REQUIRES_VIOLATION, ldv_destroy_msgsErr4REQUIRES_VIOLATION, ldv_msg_fillErr1REQUIRES_VIOLATION, ldv_msg_fillErr4REQUIRES_VIOLATION, ldv_msg_fillErr0REQUIRES_VIOLATION, ldv_msg_fillErr5REQUIRES_VIOLATION, ldv_msg_fillErr3REQUIRES_VIOLATION, ldv_msg_fillErr2REQUIRES_VIOLATION, ldv_atomic_add_returnErr1REQUIRES_VIOLATION, ldv_atomic_add_returnErr0REQUIRES_VIOLATION, ldv_atomic_add_returnErr3REQUIRES_VIOLATION, ldv_atomic_add_returnErr2REQUIRES_VIOLATION, __ldv_list_delErr0REQUIRES_VIOLATION, __ldv_list_delErr1REQUIRES_VIOLATION, __ldv_list_delErr2REQUIRES_VIOLATION, __ldv_list_delErr3REQUIRES_VIOLATION, ldv_kobject_cleanupErr2ASSERT_VIOLATIONMEMORY_FREE, ldv_kobject_cleanupErr4ASSERT_VIOLATIONMEMORY_FREE, ldv_kobject_cleanupErr0REQUIRES_VIOLATION, ldv_kobject_cleanupErr5ASSERT_VIOLATIONMEMORY_FREE, ldv_kobject_cleanupErr1REQUIRES_VIOLATION, ldv_kobject_cleanupErr3ASSERT_VIOLATIONMEMORY_FREE, ldv_msg_freeErr2ASSERT_VIOLATIONMEMORY_FREE, ldv_msg_freeErr4ASSERT_VIOLATIONMEMORY_FREE, ldv_msg_freeErr5ASSERT_VIOLATIONMEMORY_FREE, ldv_msg_freeErr0REQUIRES_VIOLATION, ldv_msg_freeErr1REQUIRES_VIOLATION, ldv_msg_freeErr3ASSERT_VIOLATIONMEMORY_FREE, mainErr0ENSURES_VIOLATIONMEMORY_LEAK, LDV_INIT_LIST_HEADErr1REQUIRES_VIOLATION, LDV_INIT_LIST_HEADErr0REQUIRES_VIOLATION, LDV_INIT_LIST_HEADErr3REQUIRES_VIOLATION, LDV_INIT_LIST_HEADErr2REQUIRES_VIOLATION, ldv_list_delErr1REQUIRES_VIOLATION, ldv_list_delErr0REQUIRES_VIOLATION, ldv_list_delErr3REQUIRES_VIOLATION, ldv_list_delErr2REQUIRES_VIOLATION, __ldv_list_addErr4REQUIRES_VIOLATION, __ldv_list_addErr5REQUIRES_VIOLATION, __ldv_list_addErr0REQUIRES_VIOLATION, __ldv_list_addErr6REQUIRES_VIOLATION, __ldv_list_addErr1REQUIRES_VIOLATION, __ldv_list_addErr7REQUIRES_VIOLATION, __ldv_list_addErr2REQUIRES_VIOLATION, __ldv_list_addErr3REQUIRES_VIOLATION, ldv_dev_set_drvdataErr1REQUIRES_VIOLATION, ldv_dev_set_drvdataErr0REQUIRES_VIOLATION, ldv_atomic_sub_returnErr1REQUIRES_VIOLATION, ldv_atomic_sub_returnErr0REQUIRES_VIOLATION, ldv_atomic_sub_returnErr3REQUIRES_VIOLATION, ldv_atomic_sub_returnErr2REQUIRES_VIOLATION, ldv_list_add_tailErr0REQUIRES_VIOLATION, ldv_list_add_tailErr1REQUIRES_VIOLATION, ldv_dev_get_drvdataErr0REQUIRES_VIOLATION, ldv_dev_get_drvdataErr1REQUIRES_VIOLATION, ldv_msg_allocErr0REQUIRES_VIOLATION, ldv_msg_allocErr1REQUIRES_VIOLATION]=== [2018-11-28 13:03:03,992 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-28 13:03:03,992 INFO L82 PathProgramCache]: Analyzing trace with hash -114537223, now seen corresponding path program 1 times [2018-11-28 13:03:03,992 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-28 13:03:03,992 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-28 13:03:03,993 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 13:03:03,994 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-28 13:03:03,994 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 13:03:04,003 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-28 13:03:04,063 INFO L134 CoverageAnalysis]: Checked inductivity of 45 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 45 trivial. 0 not checked. [2018-11-28 13:03:04,064 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-28 13:03:04,064 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [10] imperfect sequences [] total 10 [2018-11-28 13:03:04,065 INFO L459 AbstractCegarLoop]: Interpolant automaton has 10 states [2018-11-28 13:03:04,066 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 10 interpolants. [2018-11-28 13:03:04,066 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=17, Invalid=73, Unknown=0, NotChecked=0, Total=90 [2018-11-28 13:03:04,066 INFO L87 Difference]: Start difference. First operand 136 states and 139 transitions. Second operand 10 states. [2018-11-28 13:03:04,099 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-28 13:03:04,100 INFO L93 Difference]: Finished difference Result 138 states and 140 transitions. [2018-11-28 13:03:04,100 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 10 states. [2018-11-28 13:03:04,100 INFO L78 Accepts]: Start accepts. Automaton has 10 states. Word has length 89 [2018-11-28 13:03:04,101 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-28 13:03:04,101 INFO L225 Difference]: With dead ends: 138 [2018-11-28 13:03:04,101 INFO L226 Difference]: Without dead ends: 136 [2018-11-28 13:03:04,102 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 12 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 10 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=25, Invalid=107, Unknown=0, NotChecked=0, Total=132 [2018-11-28 13:03:04,102 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 136 states. [2018-11-28 13:03:04,103 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 136 to 136. [2018-11-28 13:03:04,104 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 136 states. [2018-11-28 13:03:04,106 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 136 states to 136 states and 138 transitions. [2018-11-28 13:03:04,106 INFO L78 Accepts]: Start accepts. Automaton has 136 states and 138 transitions. Word has length 89 [2018-11-28 13:03:04,106 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-28 13:03:04,106 INFO L480 AbstractCegarLoop]: Abstraction has 136 states and 138 transitions. [2018-11-28 13:03:04,106 INFO L481 AbstractCegarLoop]: Interpolant automaton has 10 states. [2018-11-28 13:03:04,106 INFO L276 IsEmpty]: Start isEmpty. Operand 136 states and 138 transitions. [2018-11-28 13:03:04,107 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 106 [2018-11-28 13:03:04,107 INFO L394 BasicCegarLoop]: Found error trace [2018-11-28 13:03:04,107 INFO L402 BasicCegarLoop]: trace histogram [9, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-28 13:03:04,108 INFO L423 AbstractCegarLoop]: === Iteration 25 === [ldv_kref_initErr1REQUIRES_VIOLATION, ldv_kref_initErr0REQUIRES_VIOLATION, ldv_list_addErr1REQUIRES_VIOLATION, ldv_list_addErr0REQUIRES_VIOLATION, ldv_kobject_createErr0REQUIRES_VIOLATION, ldv_kobject_createErr1REQUIRES_VIOLATION, ldv_destroy_msgsErr3REQUIRES_VIOLATION, ldv_destroy_msgsErr2REQUIRES_VIOLATION, ldv_destroy_msgsErr1REQUIRES_VIOLATION, ldv_destroy_msgsErr0REQUIRES_VIOLATION, ldv_destroy_msgsErr5REQUIRES_VIOLATION, ldv_destroy_msgsErr4REQUIRES_VIOLATION, ldv_msg_fillErr1REQUIRES_VIOLATION, ldv_msg_fillErr4REQUIRES_VIOLATION, ldv_msg_fillErr0REQUIRES_VIOLATION, ldv_msg_fillErr5REQUIRES_VIOLATION, ldv_msg_fillErr3REQUIRES_VIOLATION, ldv_msg_fillErr2REQUIRES_VIOLATION, ldv_atomic_add_returnErr1REQUIRES_VIOLATION, ldv_atomic_add_returnErr0REQUIRES_VIOLATION, ldv_atomic_add_returnErr3REQUIRES_VIOLATION, ldv_atomic_add_returnErr2REQUIRES_VIOLATION, __ldv_list_delErr0REQUIRES_VIOLATION, __ldv_list_delErr1REQUIRES_VIOLATION, __ldv_list_delErr2REQUIRES_VIOLATION, __ldv_list_delErr3REQUIRES_VIOLATION, ldv_kobject_cleanupErr2ASSERT_VIOLATIONMEMORY_FREE, ldv_kobject_cleanupErr4ASSERT_VIOLATIONMEMORY_FREE, ldv_kobject_cleanupErr0REQUIRES_VIOLATION, ldv_kobject_cleanupErr5ASSERT_VIOLATIONMEMORY_FREE, ldv_kobject_cleanupErr1REQUIRES_VIOLATION, ldv_kobject_cleanupErr3ASSERT_VIOLATIONMEMORY_FREE, ldv_msg_freeErr2ASSERT_VIOLATIONMEMORY_FREE, ldv_msg_freeErr4ASSERT_VIOLATIONMEMORY_FREE, ldv_msg_freeErr5ASSERT_VIOLATIONMEMORY_FREE, ldv_msg_freeErr0REQUIRES_VIOLATION, ldv_msg_freeErr1REQUIRES_VIOLATION, ldv_msg_freeErr3ASSERT_VIOLATIONMEMORY_FREE, mainErr0ENSURES_VIOLATIONMEMORY_LEAK, LDV_INIT_LIST_HEADErr1REQUIRES_VIOLATION, LDV_INIT_LIST_HEADErr0REQUIRES_VIOLATION, LDV_INIT_LIST_HEADErr3REQUIRES_VIOLATION, LDV_INIT_LIST_HEADErr2REQUIRES_VIOLATION, ldv_list_delErr1REQUIRES_VIOLATION, ldv_list_delErr0REQUIRES_VIOLATION, ldv_list_delErr3REQUIRES_VIOLATION, ldv_list_delErr2REQUIRES_VIOLATION, __ldv_list_addErr4REQUIRES_VIOLATION, __ldv_list_addErr5REQUIRES_VIOLATION, __ldv_list_addErr0REQUIRES_VIOLATION, __ldv_list_addErr6REQUIRES_VIOLATION, __ldv_list_addErr1REQUIRES_VIOLATION, __ldv_list_addErr7REQUIRES_VIOLATION, __ldv_list_addErr2REQUIRES_VIOLATION, __ldv_list_addErr3REQUIRES_VIOLATION, ldv_dev_set_drvdataErr1REQUIRES_VIOLATION, ldv_dev_set_drvdataErr0REQUIRES_VIOLATION, ldv_atomic_sub_returnErr1REQUIRES_VIOLATION, ldv_atomic_sub_returnErr0REQUIRES_VIOLATION, ldv_atomic_sub_returnErr3REQUIRES_VIOLATION, ldv_atomic_sub_returnErr2REQUIRES_VIOLATION, ldv_list_add_tailErr0REQUIRES_VIOLATION, ldv_list_add_tailErr1REQUIRES_VIOLATION, ldv_dev_get_drvdataErr0REQUIRES_VIOLATION, ldv_dev_get_drvdataErr1REQUIRES_VIOLATION, ldv_msg_allocErr0REQUIRES_VIOLATION, ldv_msg_allocErr1REQUIRES_VIOLATION]=== [2018-11-28 13:03:04,108 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-28 13:03:04,108 INFO L82 PathProgramCache]: Analyzing trace with hash 2013127602, now seen corresponding path program 1 times [2018-11-28 13:03:04,108 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-28 13:03:04,108 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-28 13:03:04,109 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 13:03:04,109 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-28 13:03:04,109 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 13:03:04,120 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-28 13:03:04,275 INFO L134 CoverageAnalysis]: Checked inductivity of 45 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 45 trivial. 0 not checked. [2018-11-28 13:03:04,275 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-28 13:03:04,275 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [19] imperfect sequences [] total 19 [2018-11-28 13:03:04,275 INFO L459 AbstractCegarLoop]: Interpolant automaton has 20 states [2018-11-28 13:03:04,275 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 20 interpolants. [2018-11-28 13:03:04,276 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=37, Invalid=343, Unknown=0, NotChecked=0, Total=380 [2018-11-28 13:03:04,276 INFO L87 Difference]: Start difference. First operand 136 states and 138 transitions. Second operand 20 states. [2018-11-28 13:03:04,602 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-28 13:03:04,602 INFO L93 Difference]: Finished difference Result 139 states and 141 transitions. [2018-11-28 13:03:04,602 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 21 states. [2018-11-28 13:03:04,602 INFO L78 Accepts]: Start accepts. Automaton has 20 states. Word has length 105 [2018-11-28 13:03:04,603 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-28 13:03:04,603 INFO L225 Difference]: With dead ends: 139 [2018-11-28 13:03:04,603 INFO L226 Difference]: Without dead ends: 139 [2018-11-28 13:03:04,604 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 26 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 25 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 21 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=65, Invalid=637, Unknown=0, NotChecked=0, Total=702 [2018-11-28 13:03:04,604 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 139 states. [2018-11-28 13:03:04,606 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 139 to 134. [2018-11-28 13:03:04,606 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 134 states. [2018-11-28 13:03:04,606 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 134 states to 134 states and 136 transitions. [2018-11-28 13:03:04,607 INFO L78 Accepts]: Start accepts. Automaton has 134 states and 136 transitions. Word has length 105 [2018-11-28 13:03:04,607 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-28 13:03:04,607 INFO L480 AbstractCegarLoop]: Abstraction has 134 states and 136 transitions. [2018-11-28 13:03:04,607 INFO L481 AbstractCegarLoop]: Interpolant automaton has 20 states. [2018-11-28 13:03:04,607 INFO L276 IsEmpty]: Start isEmpty. Operand 134 states and 136 transitions. [2018-11-28 13:03:04,608 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 106 [2018-11-28 13:03:04,608 INFO L394 BasicCegarLoop]: Found error trace [2018-11-28 13:03:04,608 INFO L402 BasicCegarLoop]: trace histogram [9, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-28 13:03:04,612 INFO L423 AbstractCegarLoop]: === Iteration 26 === [ldv_kref_initErr1REQUIRES_VIOLATION, ldv_kref_initErr0REQUIRES_VIOLATION, ldv_list_addErr1REQUIRES_VIOLATION, ldv_list_addErr0REQUIRES_VIOLATION, ldv_kobject_createErr0REQUIRES_VIOLATION, ldv_kobject_createErr1REQUIRES_VIOLATION, ldv_destroy_msgsErr3REQUIRES_VIOLATION, ldv_destroy_msgsErr2REQUIRES_VIOLATION, ldv_destroy_msgsErr1REQUIRES_VIOLATION, ldv_destroy_msgsErr0REQUIRES_VIOLATION, ldv_destroy_msgsErr5REQUIRES_VIOLATION, ldv_destroy_msgsErr4REQUIRES_VIOLATION, ldv_msg_fillErr1REQUIRES_VIOLATION, ldv_msg_fillErr4REQUIRES_VIOLATION, ldv_msg_fillErr0REQUIRES_VIOLATION, ldv_msg_fillErr5REQUIRES_VIOLATION, ldv_msg_fillErr3REQUIRES_VIOLATION, ldv_msg_fillErr2REQUIRES_VIOLATION, ldv_atomic_add_returnErr1REQUIRES_VIOLATION, ldv_atomic_add_returnErr0REQUIRES_VIOLATION, ldv_atomic_add_returnErr3REQUIRES_VIOLATION, ldv_atomic_add_returnErr2REQUIRES_VIOLATION, __ldv_list_delErr0REQUIRES_VIOLATION, __ldv_list_delErr1REQUIRES_VIOLATION, __ldv_list_delErr2REQUIRES_VIOLATION, __ldv_list_delErr3REQUIRES_VIOLATION, ldv_kobject_cleanupErr2ASSERT_VIOLATIONMEMORY_FREE, ldv_kobject_cleanupErr4ASSERT_VIOLATIONMEMORY_FREE, ldv_kobject_cleanupErr0REQUIRES_VIOLATION, ldv_kobject_cleanupErr5ASSERT_VIOLATIONMEMORY_FREE, ldv_kobject_cleanupErr1REQUIRES_VIOLATION, ldv_kobject_cleanupErr3ASSERT_VIOLATIONMEMORY_FREE, ldv_msg_freeErr2ASSERT_VIOLATIONMEMORY_FREE, ldv_msg_freeErr4ASSERT_VIOLATIONMEMORY_FREE, ldv_msg_freeErr5ASSERT_VIOLATIONMEMORY_FREE, ldv_msg_freeErr0REQUIRES_VIOLATION, ldv_msg_freeErr1REQUIRES_VIOLATION, ldv_msg_freeErr3ASSERT_VIOLATIONMEMORY_FREE, mainErr0ENSURES_VIOLATIONMEMORY_LEAK, LDV_INIT_LIST_HEADErr1REQUIRES_VIOLATION, LDV_INIT_LIST_HEADErr0REQUIRES_VIOLATION, LDV_INIT_LIST_HEADErr3REQUIRES_VIOLATION, LDV_INIT_LIST_HEADErr2REQUIRES_VIOLATION, ldv_list_delErr1REQUIRES_VIOLATION, ldv_list_delErr0REQUIRES_VIOLATION, ldv_list_delErr3REQUIRES_VIOLATION, ldv_list_delErr2REQUIRES_VIOLATION, __ldv_list_addErr4REQUIRES_VIOLATION, __ldv_list_addErr5REQUIRES_VIOLATION, __ldv_list_addErr0REQUIRES_VIOLATION, __ldv_list_addErr6REQUIRES_VIOLATION, __ldv_list_addErr1REQUIRES_VIOLATION, __ldv_list_addErr7REQUIRES_VIOLATION, __ldv_list_addErr2REQUIRES_VIOLATION, __ldv_list_addErr3REQUIRES_VIOLATION, ldv_dev_set_drvdataErr1REQUIRES_VIOLATION, ldv_dev_set_drvdataErr0REQUIRES_VIOLATION, ldv_atomic_sub_returnErr1REQUIRES_VIOLATION, ldv_atomic_sub_returnErr0REQUIRES_VIOLATION, ldv_atomic_sub_returnErr3REQUIRES_VIOLATION, ldv_atomic_sub_returnErr2REQUIRES_VIOLATION, ldv_list_add_tailErr0REQUIRES_VIOLATION, ldv_list_add_tailErr1REQUIRES_VIOLATION, ldv_dev_get_drvdataErr0REQUIRES_VIOLATION, ldv_dev_get_drvdataErr1REQUIRES_VIOLATION, ldv_msg_allocErr0REQUIRES_VIOLATION, ldv_msg_allocErr1REQUIRES_VIOLATION]=== [2018-11-28 13:03:04,613 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-28 13:03:04,613 INFO L82 PathProgramCache]: Analyzing trace with hash 2013127603, now seen corresponding path program 1 times [2018-11-28 13:03:04,613 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-28 13:03:04,613 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-28 13:03:04,614 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 13:03:04,614 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-28 13:03:04,614 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 13:03:04,628 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-28 13:03:04,729 INFO L134 CoverageAnalysis]: Checked inductivity of 45 backedges. 0 proven. 45 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-28 13:03:04,729 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-28 13:03:04,729 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_a5616418-4a25-482a-a0cb-6eefe8bc17e5/bin-2019/uautomizer/z3 Starting monitored process 10 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 10 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-28 13:03:04,737 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-28 13:03:04,780 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-28 13:03:04,783 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-28 13:03:04,806 INFO L134 CoverageAnalysis]: Checked inductivity of 45 backedges. 0 proven. 45 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-28 13:03:04,830 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-11-28 13:03:04,830 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [13, 13] total 14 [2018-11-28 13:03:04,830 INFO L459 AbstractCegarLoop]: Interpolant automaton has 14 states [2018-11-28 13:03:04,830 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 14 interpolants. [2018-11-28 13:03:04,831 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=80, Invalid=102, Unknown=0, NotChecked=0, Total=182 [2018-11-28 13:03:04,831 INFO L87 Difference]: Start difference. First operand 134 states and 136 transitions. Second operand 14 states. [2018-11-28 13:03:04,852 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-28 13:03:04,852 INFO L93 Difference]: Finished difference Result 137 states and 139 transitions. [2018-11-28 13:03:04,854 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 13 states. [2018-11-28 13:03:04,854 INFO L78 Accepts]: Start accepts. Automaton has 14 states. Word has length 105 [2018-11-28 13:03:04,854 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-28 13:03:04,855 INFO L225 Difference]: With dead ends: 137 [2018-11-28 13:03:04,855 INFO L226 Difference]: Without dead ends: 135 [2018-11-28 13:03:04,855 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 118 GetRequests, 105 SyntacticMatches, 0 SemanticMatches, 13 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 26 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=84, Invalid=126, Unknown=0, NotChecked=0, Total=210 [2018-11-28 13:03:04,855 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 135 states. [2018-11-28 13:03:04,857 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 135 to 135. [2018-11-28 13:03:04,857 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 135 states. [2018-11-28 13:03:04,858 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 135 states to 135 states and 137 transitions. [2018-11-28 13:03:04,858 INFO L78 Accepts]: Start accepts. Automaton has 135 states and 137 transitions. Word has length 105 [2018-11-28 13:03:04,858 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-28 13:03:04,858 INFO L480 AbstractCegarLoop]: Abstraction has 135 states and 137 transitions. [2018-11-28 13:03:04,858 INFO L481 AbstractCegarLoop]: Interpolant automaton has 14 states. [2018-11-28 13:03:04,858 INFO L276 IsEmpty]: Start isEmpty. Operand 135 states and 137 transitions. [2018-11-28 13:03:04,858 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 107 [2018-11-28 13:03:04,859 INFO L394 BasicCegarLoop]: Found error trace [2018-11-28 13:03:04,859 INFO L402 BasicCegarLoop]: trace histogram [10, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-28 13:03:04,859 INFO L423 AbstractCegarLoop]: === Iteration 27 === [ldv_kref_initErr1REQUIRES_VIOLATION, ldv_kref_initErr0REQUIRES_VIOLATION, ldv_list_addErr1REQUIRES_VIOLATION, ldv_list_addErr0REQUIRES_VIOLATION, ldv_kobject_createErr0REQUIRES_VIOLATION, ldv_kobject_createErr1REQUIRES_VIOLATION, ldv_destroy_msgsErr3REQUIRES_VIOLATION, ldv_destroy_msgsErr2REQUIRES_VIOLATION, ldv_destroy_msgsErr1REQUIRES_VIOLATION, ldv_destroy_msgsErr0REQUIRES_VIOLATION, ldv_destroy_msgsErr5REQUIRES_VIOLATION, ldv_destroy_msgsErr4REQUIRES_VIOLATION, ldv_msg_fillErr1REQUIRES_VIOLATION, ldv_msg_fillErr4REQUIRES_VIOLATION, ldv_msg_fillErr0REQUIRES_VIOLATION, ldv_msg_fillErr5REQUIRES_VIOLATION, ldv_msg_fillErr3REQUIRES_VIOLATION, ldv_msg_fillErr2REQUIRES_VIOLATION, ldv_atomic_add_returnErr1REQUIRES_VIOLATION, ldv_atomic_add_returnErr0REQUIRES_VIOLATION, ldv_atomic_add_returnErr3REQUIRES_VIOLATION, ldv_atomic_add_returnErr2REQUIRES_VIOLATION, __ldv_list_delErr0REQUIRES_VIOLATION, __ldv_list_delErr1REQUIRES_VIOLATION, __ldv_list_delErr2REQUIRES_VIOLATION, __ldv_list_delErr3REQUIRES_VIOLATION, ldv_kobject_cleanupErr2ASSERT_VIOLATIONMEMORY_FREE, ldv_kobject_cleanupErr4ASSERT_VIOLATIONMEMORY_FREE, ldv_kobject_cleanupErr0REQUIRES_VIOLATION, ldv_kobject_cleanupErr5ASSERT_VIOLATIONMEMORY_FREE, ldv_kobject_cleanupErr1REQUIRES_VIOLATION, ldv_kobject_cleanupErr3ASSERT_VIOLATIONMEMORY_FREE, ldv_msg_freeErr2ASSERT_VIOLATIONMEMORY_FREE, ldv_msg_freeErr4ASSERT_VIOLATIONMEMORY_FREE, ldv_msg_freeErr5ASSERT_VIOLATIONMEMORY_FREE, ldv_msg_freeErr0REQUIRES_VIOLATION, ldv_msg_freeErr1REQUIRES_VIOLATION, ldv_msg_freeErr3ASSERT_VIOLATIONMEMORY_FREE, mainErr0ENSURES_VIOLATIONMEMORY_LEAK, LDV_INIT_LIST_HEADErr1REQUIRES_VIOLATION, LDV_INIT_LIST_HEADErr0REQUIRES_VIOLATION, LDV_INIT_LIST_HEADErr3REQUIRES_VIOLATION, LDV_INIT_LIST_HEADErr2REQUIRES_VIOLATION, ldv_list_delErr1REQUIRES_VIOLATION, ldv_list_delErr0REQUIRES_VIOLATION, ldv_list_delErr3REQUIRES_VIOLATION, ldv_list_delErr2REQUIRES_VIOLATION, __ldv_list_addErr4REQUIRES_VIOLATION, __ldv_list_addErr5REQUIRES_VIOLATION, __ldv_list_addErr0REQUIRES_VIOLATION, __ldv_list_addErr6REQUIRES_VIOLATION, __ldv_list_addErr1REQUIRES_VIOLATION, __ldv_list_addErr7REQUIRES_VIOLATION, __ldv_list_addErr2REQUIRES_VIOLATION, __ldv_list_addErr3REQUIRES_VIOLATION, ldv_dev_set_drvdataErr1REQUIRES_VIOLATION, ldv_dev_set_drvdataErr0REQUIRES_VIOLATION, ldv_atomic_sub_returnErr1REQUIRES_VIOLATION, ldv_atomic_sub_returnErr0REQUIRES_VIOLATION, ldv_atomic_sub_returnErr3REQUIRES_VIOLATION, ldv_atomic_sub_returnErr2REQUIRES_VIOLATION, ldv_list_add_tailErr0REQUIRES_VIOLATION, ldv_list_add_tailErr1REQUIRES_VIOLATION, ldv_dev_get_drvdataErr0REQUIRES_VIOLATION, ldv_dev_get_drvdataErr1REQUIRES_VIOLATION, ldv_msg_allocErr0REQUIRES_VIOLATION, ldv_msg_allocErr1REQUIRES_VIOLATION]=== [2018-11-28 13:03:04,859 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-28 13:03:04,859 INFO L82 PathProgramCache]: Analyzing trace with hash 694410032, now seen corresponding path program 2 times [2018-11-28 13:03:04,859 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-28 13:03:04,859 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-28 13:03:04,868 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 13:03:04,868 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-28 13:03:04,868 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 13:03:04,884 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-28 13:03:05,068 INFO L134 CoverageAnalysis]: Checked inductivity of 55 backedges. 0 proven. 55 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-28 13:03:05,069 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-28 13:03:05,069 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_a5616418-4a25-482a-a0cb-6eefe8bc17e5/bin-2019/uautomizer/z3 Starting monitored process 11 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 11 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-28 13:03:05,080 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-11-28 13:03:05,144 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) [2018-11-28 13:03:05,145 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-11-28 13:03:05,151 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-28 13:03:05,169 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 6 treesize of output 5 [2018-11-28 13:03:05,169 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-11-28 13:03:05,174 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-0 vars, 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-28 13:03:05,175 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 2 variables, input treesize:13, output treesize:9 [2018-11-28 13:03:05,710 INFO L134 CoverageAnalysis]: Checked inductivity of 55 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 55 trivial. 0 not checked. [2018-11-28 13:03:05,726 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 1 imperfect interpolant sequences. [2018-11-28 13:03:05,726 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [22] imperfect sequences [14] total 35 [2018-11-28 13:03:05,726 INFO L459 AbstractCegarLoop]: Interpolant automaton has 35 states [2018-11-28 13:03:05,726 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 35 interpolants. [2018-11-28 13:03:05,726 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=140, Invalid=1050, Unknown=0, NotChecked=0, Total=1190 [2018-11-28 13:03:05,727 INFO L87 Difference]: Start difference. First operand 135 states and 137 transitions. Second operand 35 states. [2018-11-28 13:03:06,599 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-28 13:03:06,599 INFO L93 Difference]: Finished difference Result 136 states and 138 transitions. [2018-11-28 13:03:06,599 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 35 states. [2018-11-28 13:03:06,599 INFO L78 Accepts]: Start accepts. Automaton has 35 states. Word has length 106 [2018-11-28 13:03:06,600 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-28 13:03:06,600 INFO L225 Difference]: With dead ends: 136 [2018-11-28 13:03:06,600 INFO L226 Difference]: Without dead ends: 134 [2018-11-28 13:03:06,601 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 139 GetRequests, 79 SyntacticMatches, 7 SemanticMatches, 53 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 532 ImplicationChecksByTransitivity, 0.9s TimeCoverageRelationStatistics Valid=351, Invalid=2619, Unknown=0, NotChecked=0, Total=2970 [2018-11-28 13:03:06,601 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 134 states. [2018-11-28 13:03:06,603 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 134 to 134. [2018-11-28 13:03:06,603 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 134 states. [2018-11-28 13:03:06,603 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 134 states to 134 states and 136 transitions. [2018-11-28 13:03:06,604 INFO L78 Accepts]: Start accepts. Automaton has 134 states and 136 transitions. Word has length 106 [2018-11-28 13:03:06,604 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-28 13:03:06,604 INFO L480 AbstractCegarLoop]: Abstraction has 134 states and 136 transitions. [2018-11-28 13:03:06,604 INFO L481 AbstractCegarLoop]: Interpolant automaton has 35 states. [2018-11-28 13:03:06,604 INFO L276 IsEmpty]: Start isEmpty. Operand 134 states and 136 transitions. [2018-11-28 13:03:06,604 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 113 [2018-11-28 13:03:06,604 INFO L394 BasicCegarLoop]: Found error trace [2018-11-28 13:03:06,605 INFO L402 BasicCegarLoop]: trace histogram [11, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-28 13:03:06,605 INFO L423 AbstractCegarLoop]: === Iteration 28 === [ldv_kref_initErr1REQUIRES_VIOLATION, ldv_kref_initErr0REQUIRES_VIOLATION, ldv_list_addErr1REQUIRES_VIOLATION, ldv_list_addErr0REQUIRES_VIOLATION, ldv_kobject_createErr0REQUIRES_VIOLATION, ldv_kobject_createErr1REQUIRES_VIOLATION, ldv_destroy_msgsErr3REQUIRES_VIOLATION, ldv_destroy_msgsErr2REQUIRES_VIOLATION, ldv_destroy_msgsErr1REQUIRES_VIOLATION, ldv_destroy_msgsErr0REQUIRES_VIOLATION, ldv_destroy_msgsErr5REQUIRES_VIOLATION, ldv_destroy_msgsErr4REQUIRES_VIOLATION, ldv_msg_fillErr1REQUIRES_VIOLATION, ldv_msg_fillErr4REQUIRES_VIOLATION, ldv_msg_fillErr0REQUIRES_VIOLATION, ldv_msg_fillErr5REQUIRES_VIOLATION, ldv_msg_fillErr3REQUIRES_VIOLATION, ldv_msg_fillErr2REQUIRES_VIOLATION, ldv_atomic_add_returnErr1REQUIRES_VIOLATION, ldv_atomic_add_returnErr0REQUIRES_VIOLATION, ldv_atomic_add_returnErr3REQUIRES_VIOLATION, ldv_atomic_add_returnErr2REQUIRES_VIOLATION, __ldv_list_delErr0REQUIRES_VIOLATION, __ldv_list_delErr1REQUIRES_VIOLATION, __ldv_list_delErr2REQUIRES_VIOLATION, __ldv_list_delErr3REQUIRES_VIOLATION, ldv_kobject_cleanupErr2ASSERT_VIOLATIONMEMORY_FREE, ldv_kobject_cleanupErr4ASSERT_VIOLATIONMEMORY_FREE, ldv_kobject_cleanupErr0REQUIRES_VIOLATION, ldv_kobject_cleanupErr5ASSERT_VIOLATIONMEMORY_FREE, ldv_kobject_cleanupErr1REQUIRES_VIOLATION, ldv_kobject_cleanupErr3ASSERT_VIOLATIONMEMORY_FREE, ldv_msg_freeErr2ASSERT_VIOLATIONMEMORY_FREE, ldv_msg_freeErr4ASSERT_VIOLATIONMEMORY_FREE, ldv_msg_freeErr5ASSERT_VIOLATIONMEMORY_FREE, ldv_msg_freeErr0REQUIRES_VIOLATION, ldv_msg_freeErr1REQUIRES_VIOLATION, ldv_msg_freeErr3ASSERT_VIOLATIONMEMORY_FREE, mainErr0ENSURES_VIOLATIONMEMORY_LEAK, LDV_INIT_LIST_HEADErr1REQUIRES_VIOLATION, LDV_INIT_LIST_HEADErr0REQUIRES_VIOLATION, LDV_INIT_LIST_HEADErr3REQUIRES_VIOLATION, LDV_INIT_LIST_HEADErr2REQUIRES_VIOLATION, ldv_list_delErr1REQUIRES_VIOLATION, ldv_list_delErr0REQUIRES_VIOLATION, ldv_list_delErr3REQUIRES_VIOLATION, ldv_list_delErr2REQUIRES_VIOLATION, __ldv_list_addErr4REQUIRES_VIOLATION, __ldv_list_addErr5REQUIRES_VIOLATION, __ldv_list_addErr0REQUIRES_VIOLATION, __ldv_list_addErr6REQUIRES_VIOLATION, __ldv_list_addErr1REQUIRES_VIOLATION, __ldv_list_addErr7REQUIRES_VIOLATION, __ldv_list_addErr2REQUIRES_VIOLATION, __ldv_list_addErr3REQUIRES_VIOLATION, ldv_dev_set_drvdataErr1REQUIRES_VIOLATION, ldv_dev_set_drvdataErr0REQUIRES_VIOLATION, ldv_atomic_sub_returnErr1REQUIRES_VIOLATION, ldv_atomic_sub_returnErr0REQUIRES_VIOLATION, ldv_atomic_sub_returnErr3REQUIRES_VIOLATION, ldv_atomic_sub_returnErr2REQUIRES_VIOLATION, ldv_list_add_tailErr0REQUIRES_VIOLATION, ldv_list_add_tailErr1REQUIRES_VIOLATION, ldv_dev_get_drvdataErr0REQUIRES_VIOLATION, ldv_dev_get_drvdataErr1REQUIRES_VIOLATION, ldv_msg_allocErr0REQUIRES_VIOLATION, ldv_msg_allocErr1REQUIRES_VIOLATION]=== [2018-11-28 13:03:06,605 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-28 13:03:06,605 INFO L82 PathProgramCache]: Analyzing trace with hash -1729876608, now seen corresponding path program 1 times [2018-11-28 13:03:06,605 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-28 13:03:06,605 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-28 13:03:06,606 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 13:03:06,606 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-28 13:03:06,606 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 13:03:06,619 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-28 13:03:06,705 INFO L134 CoverageAnalysis]: Checked inductivity of 66 backedges. 0 proven. 66 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-28 13:03:06,706 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-28 13:03:06,706 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_a5616418-4a25-482a-a0cb-6eefe8bc17e5/bin-2019/uautomizer/z3 Starting monitored process 12 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 12 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-28 13:03:06,715 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-28 13:03:06,762 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-28 13:03:06,765 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-28 13:03:06,777 INFO L134 CoverageAnalysis]: Checked inductivity of 66 backedges. 0 proven. 66 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-28 13:03:06,793 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-11-28 13:03:06,793 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [15, 15] total 16 [2018-11-28 13:03:06,794 INFO L459 AbstractCegarLoop]: Interpolant automaton has 16 states [2018-11-28 13:03:06,794 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 16 interpolants. [2018-11-28 13:03:06,794 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=107, Invalid=133, Unknown=0, NotChecked=0, Total=240 [2018-11-28 13:03:06,794 INFO L87 Difference]: Start difference. First operand 134 states and 136 transitions. Second operand 16 states. [2018-11-28 13:03:06,823 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-28 13:03:06,823 INFO L93 Difference]: Finished difference Result 137 states and 139 transitions. [2018-11-28 13:03:06,824 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 15 states. [2018-11-28 13:03:06,824 INFO L78 Accepts]: Start accepts. Automaton has 16 states. Word has length 112 [2018-11-28 13:03:06,825 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-28 13:03:06,825 INFO L225 Difference]: With dead ends: 137 [2018-11-28 13:03:06,825 INFO L226 Difference]: Without dead ends: 135 [2018-11-28 13:03:06,825 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 127 GetRequests, 112 SyntacticMatches, 0 SemanticMatches, 15 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 32 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=111, Invalid=161, Unknown=0, NotChecked=0, Total=272 [2018-11-28 13:03:06,826 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 135 states. [2018-11-28 13:03:06,827 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 135 to 135. [2018-11-28 13:03:06,827 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 135 states. [2018-11-28 13:03:06,828 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 135 states to 135 states and 137 transitions. [2018-11-28 13:03:06,828 INFO L78 Accepts]: Start accepts. Automaton has 135 states and 137 transitions. Word has length 112 [2018-11-28 13:03:06,828 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-28 13:03:06,828 INFO L480 AbstractCegarLoop]: Abstraction has 135 states and 137 transitions. [2018-11-28 13:03:06,828 INFO L481 AbstractCegarLoop]: Interpolant automaton has 16 states. [2018-11-28 13:03:06,829 INFO L276 IsEmpty]: Start isEmpty. Operand 135 states and 137 transitions. [2018-11-28 13:03:06,829 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 114 [2018-11-28 13:03:06,829 INFO L394 BasicCegarLoop]: Found error trace [2018-11-28 13:03:06,829 INFO L402 BasicCegarLoop]: trace histogram [12, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-28 13:03:06,830 INFO L423 AbstractCegarLoop]: === Iteration 29 === [ldv_kref_initErr1REQUIRES_VIOLATION, ldv_kref_initErr0REQUIRES_VIOLATION, ldv_list_addErr1REQUIRES_VIOLATION, ldv_list_addErr0REQUIRES_VIOLATION, ldv_kobject_createErr0REQUIRES_VIOLATION, ldv_kobject_createErr1REQUIRES_VIOLATION, ldv_destroy_msgsErr3REQUIRES_VIOLATION, ldv_destroy_msgsErr2REQUIRES_VIOLATION, ldv_destroy_msgsErr1REQUIRES_VIOLATION, ldv_destroy_msgsErr0REQUIRES_VIOLATION, ldv_destroy_msgsErr5REQUIRES_VIOLATION, ldv_destroy_msgsErr4REQUIRES_VIOLATION, ldv_msg_fillErr1REQUIRES_VIOLATION, ldv_msg_fillErr4REQUIRES_VIOLATION, ldv_msg_fillErr0REQUIRES_VIOLATION, ldv_msg_fillErr5REQUIRES_VIOLATION, ldv_msg_fillErr3REQUIRES_VIOLATION, ldv_msg_fillErr2REQUIRES_VIOLATION, ldv_atomic_add_returnErr1REQUIRES_VIOLATION, ldv_atomic_add_returnErr0REQUIRES_VIOLATION, ldv_atomic_add_returnErr3REQUIRES_VIOLATION, ldv_atomic_add_returnErr2REQUIRES_VIOLATION, __ldv_list_delErr0REQUIRES_VIOLATION, __ldv_list_delErr1REQUIRES_VIOLATION, __ldv_list_delErr2REQUIRES_VIOLATION, __ldv_list_delErr3REQUIRES_VIOLATION, ldv_kobject_cleanupErr2ASSERT_VIOLATIONMEMORY_FREE, ldv_kobject_cleanupErr4ASSERT_VIOLATIONMEMORY_FREE, ldv_kobject_cleanupErr0REQUIRES_VIOLATION, ldv_kobject_cleanupErr5ASSERT_VIOLATIONMEMORY_FREE, ldv_kobject_cleanupErr1REQUIRES_VIOLATION, ldv_kobject_cleanupErr3ASSERT_VIOLATIONMEMORY_FREE, ldv_msg_freeErr2ASSERT_VIOLATIONMEMORY_FREE, ldv_msg_freeErr4ASSERT_VIOLATIONMEMORY_FREE, ldv_msg_freeErr5ASSERT_VIOLATIONMEMORY_FREE, ldv_msg_freeErr0REQUIRES_VIOLATION, ldv_msg_freeErr1REQUIRES_VIOLATION, ldv_msg_freeErr3ASSERT_VIOLATIONMEMORY_FREE, mainErr0ENSURES_VIOLATIONMEMORY_LEAK, LDV_INIT_LIST_HEADErr1REQUIRES_VIOLATION, LDV_INIT_LIST_HEADErr0REQUIRES_VIOLATION, LDV_INIT_LIST_HEADErr3REQUIRES_VIOLATION, LDV_INIT_LIST_HEADErr2REQUIRES_VIOLATION, ldv_list_delErr1REQUIRES_VIOLATION, ldv_list_delErr0REQUIRES_VIOLATION, ldv_list_delErr3REQUIRES_VIOLATION, ldv_list_delErr2REQUIRES_VIOLATION, __ldv_list_addErr4REQUIRES_VIOLATION, __ldv_list_addErr5REQUIRES_VIOLATION, __ldv_list_addErr0REQUIRES_VIOLATION, __ldv_list_addErr6REQUIRES_VIOLATION, __ldv_list_addErr1REQUIRES_VIOLATION, __ldv_list_addErr7REQUIRES_VIOLATION, __ldv_list_addErr2REQUIRES_VIOLATION, __ldv_list_addErr3REQUIRES_VIOLATION, ldv_dev_set_drvdataErr1REQUIRES_VIOLATION, ldv_dev_set_drvdataErr0REQUIRES_VIOLATION, ldv_atomic_sub_returnErr1REQUIRES_VIOLATION, ldv_atomic_sub_returnErr0REQUIRES_VIOLATION, ldv_atomic_sub_returnErr3REQUIRES_VIOLATION, ldv_atomic_sub_returnErr2REQUIRES_VIOLATION, ldv_list_add_tailErr0REQUIRES_VIOLATION, ldv_list_add_tailErr1REQUIRES_VIOLATION, ldv_dev_get_drvdataErr0REQUIRES_VIOLATION, ldv_dev_get_drvdataErr1REQUIRES_VIOLATION, ldv_msg_allocErr0REQUIRES_VIOLATION, ldv_msg_allocErr1REQUIRES_VIOLATION]=== [2018-11-28 13:03:06,830 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-28 13:03:06,830 INFO L82 PathProgramCache]: Analyzing trace with hash 1998405475, now seen corresponding path program 2 times [2018-11-28 13:03:06,830 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-28 13:03:06,830 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-28 13:03:06,831 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 13:03:06,831 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-28 13:03:06,831 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 13:03:06,845 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-28 13:03:06,936 INFO L134 CoverageAnalysis]: Checked inductivity of 78 backedges. 0 proven. 78 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-28 13:03:06,936 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-28 13:03:06,936 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_a5616418-4a25-482a-a0cb-6eefe8bc17e5/bin-2019/uautomizer/z3 Starting monitored process 13 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 13 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-28 13:03:06,946 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-11-28 13:03:07,000 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) [2018-11-28 13:03:07,000 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-11-28 13:03:07,006 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-28 13:03:07,079 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 11 treesize of output 8 [2018-11-28 13:03:07,081 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 8 treesize of output 7 [2018-11-28 13:03:07,081 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-11-28 13:03:07,083 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-28 13:03:07,084 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-2 vars, End of recursive call: and 1 xjuncts. [2018-11-28 13:03:07,084 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 1 variables, input treesize:11, output treesize:7 [2018-11-28 13:03:07,166 INFO L267 ElimStorePlain]: Start of recursive call 3: 1 dim-0 vars, End of recursive call: 1 dim-0 vars, and 1 xjuncts. [2018-11-28 13:03:07,167 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: 1 dim-0 vars, and 1 xjuncts. [2018-11-28 13:03:07,171 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-0 vars, 1 dim-2 vars, End of recursive call: 2 dim-0 vars, and 1 xjuncts. [2018-11-28 13:03:07,171 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 2 variables, input treesize:38, output treesize:26 [2018-11-28 13:03:07,793 WARN L854 $PredicateComparison]: unable to prove that (exists ((LDV_INIT_LIST_HEAD_~list.offset Int) (v_DerPreprocessor_2 Int)) (and (= |c_#memory_int| (store |c_old(#memory_int)| |c_LDV_INIT_LIST_HEAD_#in~list.base| (let ((.cse0 (+ LDV_INIT_LIST_HEAD_~list.offset 4))) (store (store (select |c_old(#memory_int)| |c_LDV_INIT_LIST_HEAD_#in~list.base|) LDV_INIT_LIST_HEAD_~list.offset v_DerPreprocessor_2) .cse0 (select (select |c_#memory_int| |c_LDV_INIT_LIST_HEAD_#in~list.base|) .cse0))))) (<= LDV_INIT_LIST_HEAD_~list.offset |c_LDV_INIT_LIST_HEAD_#in~list.offset|))) is different from true [2018-11-28 13:03:07,799 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 32 treesize of output 27 [2018-11-28 13:03:07,802 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:03:07,803 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 27 treesize of output 35 [2018-11-28 13:03:07,805 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:03:07,806 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:03:07,809 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 2 select indices, 2 select index equivalence classes, 3 disjoint index pairs (out of 1 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 29 treesize of output 37 [2018-11-28 13:03:07,809 INFO L267 ElimStorePlain]: Start of recursive call 4: End of recursive call: and 1 xjuncts. [2018-11-28 13:03:07,814 INFO L267 ElimStorePlain]: Start of recursive call 3: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-28 13:03:07,816 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-28 13:03:07,820 INFO L267 ElimStorePlain]: Start of recursive call 1: 2 dim-0 vars, 1 dim-2 vars, End of recursive call: and 1 xjuncts. [2018-11-28 13:03:07,820 INFO L202 ElimStorePlain]: Needed 4 recursive calls to eliminate 3 variables, input treesize:37, output treesize:9 [2018-11-28 13:03:08,163 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:03:08,163 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 29 treesize of output 36 [2018-11-28 13:03:08,167 INFO L683 Elim1Store]: detected equality via solver [2018-11-28 13:03:08,168 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:03:08,169 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 2 select indices, 2 select index equivalence classes, 1 disjoint index pairs (out of 1 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 36 treesize of output 15 [2018-11-28 13:03:08,169 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-11-28 13:03:08,171 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-28 13:03:08,173 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-2 vars, End of recursive call: and 1 xjuncts. [2018-11-28 13:03:08,174 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 1 variables, input treesize:32, output treesize:13 [2018-11-28 13:03:08,505 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 17 treesize of output 13 [2018-11-28 13:03:08,506 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 13 treesize of output 5 [2018-11-28 13:03:08,506 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-11-28 13:03:08,509 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-28 13:03:08,510 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-0 vars, 1 dim-2 vars, End of recursive call: and 1 xjuncts. [2018-11-28 13:03:08,510 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 2 variables, input treesize:17, output treesize:5 [2018-11-28 13:03:08,551 INFO L134 CoverageAnalysis]: Checked inductivity of 78 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 78 trivial. 0 not checked. [2018-11-28 13:03:08,576 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 1 imperfect interpolant sequences. [2018-11-28 13:03:08,576 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [43] imperfect sequences [16] total 57 [2018-11-28 13:03:08,576 INFO L459 AbstractCegarLoop]: Interpolant automaton has 57 states [2018-11-28 13:03:08,577 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 57 interpolants. [2018-11-28 13:03:08,577 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=202, Invalid=2881, Unknown=1, NotChecked=108, Total=3192 [2018-11-28 13:03:08,577 INFO L87 Difference]: Start difference. First operand 135 states and 137 transitions. Second operand 57 states. [2018-11-28 13:03:10,298 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-28 13:03:10,298 INFO L93 Difference]: Finished difference Result 116 states and 116 transitions. [2018-11-28 13:03:10,298 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 60 states. [2018-11-28 13:03:10,298 INFO L78 Accepts]: Start accepts. Automaton has 57 states. Word has length 113 [2018-11-28 13:03:10,299 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-28 13:03:10,299 INFO L225 Difference]: With dead ends: 116 [2018-11-28 13:03:10,299 INFO L226 Difference]: Without dead ends: 114 [2018-11-28 13:03:10,301 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 162 GetRequests, 72 SyntacticMatches, 1 SemanticMatches, 89 ConstructedPredicates, 1 IntricatePredicates, 0 DeprecatedPredicates, 1506 ImplicationChecksByTransitivity, 2.1s TimeCoverageRelationStatistics Valid=508, Invalid=7505, Unknown=1, NotChecked=176, Total=8190 [2018-11-28 13:03:10,301 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 114 states. [2018-11-28 13:03:10,302 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 114 to 114. [2018-11-28 13:03:10,302 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 114 states. [2018-11-28 13:03:10,302 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 114 states to 114 states and 114 transitions. [2018-11-28 13:03:10,303 INFO L78 Accepts]: Start accepts. Automaton has 114 states and 114 transitions. Word has length 113 [2018-11-28 13:03:10,303 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-28 13:03:10,303 INFO L480 AbstractCegarLoop]: Abstraction has 114 states and 114 transitions. [2018-11-28 13:03:10,303 INFO L481 AbstractCegarLoop]: Interpolant automaton has 57 states. [2018-11-28 13:03:10,303 INFO L276 IsEmpty]: Start isEmpty. Operand 114 states and 114 transitions. [2018-11-28 13:03:10,303 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 114 [2018-11-28 13:03:10,304 INFO L394 BasicCegarLoop]: Found error trace [2018-11-28 13:03:10,304 INFO L402 BasicCegarLoop]: trace histogram [13, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-28 13:03:10,304 INFO L423 AbstractCegarLoop]: === Iteration 30 === [ldv_kref_initErr1REQUIRES_VIOLATION, ldv_kref_initErr0REQUIRES_VIOLATION, ldv_list_addErr1REQUIRES_VIOLATION, ldv_list_addErr0REQUIRES_VIOLATION, ldv_kobject_createErr0REQUIRES_VIOLATION, ldv_kobject_createErr1REQUIRES_VIOLATION, ldv_destroy_msgsErr3REQUIRES_VIOLATION, ldv_destroy_msgsErr2REQUIRES_VIOLATION, ldv_destroy_msgsErr1REQUIRES_VIOLATION, ldv_destroy_msgsErr0REQUIRES_VIOLATION, ldv_destroy_msgsErr5REQUIRES_VIOLATION, ldv_destroy_msgsErr4REQUIRES_VIOLATION, ldv_msg_fillErr1REQUIRES_VIOLATION, ldv_msg_fillErr4REQUIRES_VIOLATION, ldv_msg_fillErr0REQUIRES_VIOLATION, ldv_msg_fillErr5REQUIRES_VIOLATION, ldv_msg_fillErr3REQUIRES_VIOLATION, ldv_msg_fillErr2REQUIRES_VIOLATION, ldv_atomic_add_returnErr1REQUIRES_VIOLATION, ldv_atomic_add_returnErr0REQUIRES_VIOLATION, ldv_atomic_add_returnErr3REQUIRES_VIOLATION, ldv_atomic_add_returnErr2REQUIRES_VIOLATION, __ldv_list_delErr0REQUIRES_VIOLATION, __ldv_list_delErr1REQUIRES_VIOLATION, __ldv_list_delErr2REQUIRES_VIOLATION, __ldv_list_delErr3REQUIRES_VIOLATION, ldv_kobject_cleanupErr2ASSERT_VIOLATIONMEMORY_FREE, ldv_kobject_cleanupErr4ASSERT_VIOLATIONMEMORY_FREE, ldv_kobject_cleanupErr0REQUIRES_VIOLATION, ldv_kobject_cleanupErr5ASSERT_VIOLATIONMEMORY_FREE, ldv_kobject_cleanupErr1REQUIRES_VIOLATION, ldv_kobject_cleanupErr3ASSERT_VIOLATIONMEMORY_FREE, ldv_msg_freeErr2ASSERT_VIOLATIONMEMORY_FREE, ldv_msg_freeErr4ASSERT_VIOLATIONMEMORY_FREE, ldv_msg_freeErr5ASSERT_VIOLATIONMEMORY_FREE, ldv_msg_freeErr0REQUIRES_VIOLATION, ldv_msg_freeErr1REQUIRES_VIOLATION, ldv_msg_freeErr3ASSERT_VIOLATIONMEMORY_FREE, mainErr0ENSURES_VIOLATIONMEMORY_LEAK, LDV_INIT_LIST_HEADErr1REQUIRES_VIOLATION, LDV_INIT_LIST_HEADErr0REQUIRES_VIOLATION, LDV_INIT_LIST_HEADErr3REQUIRES_VIOLATION, LDV_INIT_LIST_HEADErr2REQUIRES_VIOLATION, ldv_list_delErr1REQUIRES_VIOLATION, ldv_list_delErr0REQUIRES_VIOLATION, ldv_list_delErr3REQUIRES_VIOLATION, ldv_list_delErr2REQUIRES_VIOLATION, __ldv_list_addErr4REQUIRES_VIOLATION, __ldv_list_addErr5REQUIRES_VIOLATION, __ldv_list_addErr0REQUIRES_VIOLATION, __ldv_list_addErr6REQUIRES_VIOLATION, __ldv_list_addErr1REQUIRES_VIOLATION, __ldv_list_addErr7REQUIRES_VIOLATION, __ldv_list_addErr2REQUIRES_VIOLATION, __ldv_list_addErr3REQUIRES_VIOLATION, ldv_dev_set_drvdataErr1REQUIRES_VIOLATION, ldv_dev_set_drvdataErr0REQUIRES_VIOLATION, ldv_atomic_sub_returnErr1REQUIRES_VIOLATION, ldv_atomic_sub_returnErr0REQUIRES_VIOLATION, ldv_atomic_sub_returnErr3REQUIRES_VIOLATION, ldv_atomic_sub_returnErr2REQUIRES_VIOLATION, ldv_list_add_tailErr0REQUIRES_VIOLATION, ldv_list_add_tailErr1REQUIRES_VIOLATION, ldv_dev_get_drvdataErr0REQUIRES_VIOLATION, ldv_dev_get_drvdataErr1REQUIRES_VIOLATION, ldv_msg_allocErr0REQUIRES_VIOLATION, ldv_msg_allocErr1REQUIRES_VIOLATION]=== [2018-11-28 13:03:10,304 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-28 13:03:10,304 INFO L82 PathProgramCache]: Analyzing trace with hash 2034289743, now seen corresponding path program 1 times [2018-11-28 13:03:10,304 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-28 13:03:10,304 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-28 13:03:10,305 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 13:03:10,305 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-28 13:03:10,305 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 13:03:10,322 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-28 13:03:10,467 INFO L134 CoverageAnalysis]: Checked inductivity of 91 backedges. 0 proven. 91 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-28 13:03:10,468 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-28 13:03:10,468 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_a5616418-4a25-482a-a0cb-6eefe8bc17e5/bin-2019/uautomizer/z3 Starting monitored process 14 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 14 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-28 13:03:10,481 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-28 13:03:10,551 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-28 13:03:10,553 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-28 13:03:10,585 INFO L134 CoverageAnalysis]: Checked inductivity of 91 backedges. 0 proven. 91 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-28 13:03:10,601 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-11-28 13:03:10,601 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [17, 17] total 18 [2018-11-28 13:03:10,602 INFO L459 AbstractCegarLoop]: Interpolant automaton has 18 states [2018-11-28 13:03:10,602 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 18 interpolants. [2018-11-28 13:03:10,602 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=138, Invalid=168, Unknown=0, NotChecked=0, Total=306 [2018-11-28 13:03:10,602 INFO L87 Difference]: Start difference. First operand 114 states and 114 transitions. Second operand 18 states. [2018-11-28 13:03:10,634 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-28 13:03:10,634 INFO L93 Difference]: Finished difference Result 117 states and 117 transitions. [2018-11-28 13:03:10,635 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 17 states. [2018-11-28 13:03:10,635 INFO L78 Accepts]: Start accepts. Automaton has 18 states. Word has length 113 [2018-11-28 13:03:10,635 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-28 13:03:10,636 INFO L225 Difference]: With dead ends: 117 [2018-11-28 13:03:10,636 INFO L226 Difference]: Without dead ends: 115 [2018-11-28 13:03:10,636 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 130 GetRequests, 113 SyntacticMatches, 0 SemanticMatches, 17 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 38 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=142, Invalid=200, Unknown=0, NotChecked=0, Total=342 [2018-11-28 13:03:10,637 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 115 states. [2018-11-28 13:03:10,638 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 115 to 115. [2018-11-28 13:03:10,640 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 115 states. [2018-11-28 13:03:10,641 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 115 states to 115 states and 115 transitions. [2018-11-28 13:03:10,641 INFO L78 Accepts]: Start accepts. Automaton has 115 states and 115 transitions. Word has length 113 [2018-11-28 13:03:10,641 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-28 13:03:10,641 INFO L480 AbstractCegarLoop]: Abstraction has 115 states and 115 transitions. [2018-11-28 13:03:10,641 INFO L481 AbstractCegarLoop]: Interpolant automaton has 18 states. [2018-11-28 13:03:10,641 INFO L276 IsEmpty]: Start isEmpty. Operand 115 states and 115 transitions. [2018-11-28 13:03:10,642 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 115 [2018-11-28 13:03:10,642 INFO L394 BasicCegarLoop]: Found error trace [2018-11-28 13:03:10,642 INFO L402 BasicCegarLoop]: trace histogram [14, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-28 13:03:10,642 INFO L423 AbstractCegarLoop]: === Iteration 31 === [ldv_kref_initErr1REQUIRES_VIOLATION, ldv_kref_initErr0REQUIRES_VIOLATION, ldv_list_addErr1REQUIRES_VIOLATION, ldv_list_addErr0REQUIRES_VIOLATION, ldv_kobject_createErr0REQUIRES_VIOLATION, ldv_kobject_createErr1REQUIRES_VIOLATION, ldv_destroy_msgsErr3REQUIRES_VIOLATION, ldv_destroy_msgsErr2REQUIRES_VIOLATION, ldv_destroy_msgsErr1REQUIRES_VIOLATION, ldv_destroy_msgsErr0REQUIRES_VIOLATION, ldv_destroy_msgsErr5REQUIRES_VIOLATION, ldv_destroy_msgsErr4REQUIRES_VIOLATION, ldv_msg_fillErr1REQUIRES_VIOLATION, ldv_msg_fillErr4REQUIRES_VIOLATION, ldv_msg_fillErr0REQUIRES_VIOLATION, ldv_msg_fillErr5REQUIRES_VIOLATION, ldv_msg_fillErr3REQUIRES_VIOLATION, ldv_msg_fillErr2REQUIRES_VIOLATION, ldv_atomic_add_returnErr1REQUIRES_VIOLATION, ldv_atomic_add_returnErr0REQUIRES_VIOLATION, ldv_atomic_add_returnErr3REQUIRES_VIOLATION, ldv_atomic_add_returnErr2REQUIRES_VIOLATION, __ldv_list_delErr0REQUIRES_VIOLATION, __ldv_list_delErr1REQUIRES_VIOLATION, __ldv_list_delErr2REQUIRES_VIOLATION, __ldv_list_delErr3REQUIRES_VIOLATION, ldv_kobject_cleanupErr2ASSERT_VIOLATIONMEMORY_FREE, ldv_kobject_cleanupErr4ASSERT_VIOLATIONMEMORY_FREE, ldv_kobject_cleanupErr0REQUIRES_VIOLATION, ldv_kobject_cleanupErr5ASSERT_VIOLATIONMEMORY_FREE, ldv_kobject_cleanupErr1REQUIRES_VIOLATION, ldv_kobject_cleanupErr3ASSERT_VIOLATIONMEMORY_FREE, ldv_msg_freeErr2ASSERT_VIOLATIONMEMORY_FREE, ldv_msg_freeErr4ASSERT_VIOLATIONMEMORY_FREE, ldv_msg_freeErr5ASSERT_VIOLATIONMEMORY_FREE, ldv_msg_freeErr0REQUIRES_VIOLATION, ldv_msg_freeErr1REQUIRES_VIOLATION, ldv_msg_freeErr3ASSERT_VIOLATIONMEMORY_FREE, mainErr0ENSURES_VIOLATIONMEMORY_LEAK, LDV_INIT_LIST_HEADErr1REQUIRES_VIOLATION, LDV_INIT_LIST_HEADErr0REQUIRES_VIOLATION, LDV_INIT_LIST_HEADErr3REQUIRES_VIOLATION, LDV_INIT_LIST_HEADErr2REQUIRES_VIOLATION, ldv_list_delErr1REQUIRES_VIOLATION, ldv_list_delErr0REQUIRES_VIOLATION, ldv_list_delErr3REQUIRES_VIOLATION, ldv_list_delErr2REQUIRES_VIOLATION, __ldv_list_addErr4REQUIRES_VIOLATION, __ldv_list_addErr5REQUIRES_VIOLATION, __ldv_list_addErr0REQUIRES_VIOLATION, __ldv_list_addErr6REQUIRES_VIOLATION, __ldv_list_addErr1REQUIRES_VIOLATION, __ldv_list_addErr7REQUIRES_VIOLATION, __ldv_list_addErr2REQUIRES_VIOLATION, __ldv_list_addErr3REQUIRES_VIOLATION, ldv_dev_set_drvdataErr1REQUIRES_VIOLATION, ldv_dev_set_drvdataErr0REQUIRES_VIOLATION, ldv_atomic_sub_returnErr1REQUIRES_VIOLATION, ldv_atomic_sub_returnErr0REQUIRES_VIOLATION, ldv_atomic_sub_returnErr3REQUIRES_VIOLATION, ldv_atomic_sub_returnErr2REQUIRES_VIOLATION, ldv_list_add_tailErr0REQUIRES_VIOLATION, ldv_list_add_tailErr1REQUIRES_VIOLATION, ldv_dev_get_drvdataErr0REQUIRES_VIOLATION, ldv_dev_get_drvdataErr1REQUIRES_VIOLATION, ldv_msg_allocErr0REQUIRES_VIOLATION, ldv_msg_allocErr1REQUIRES_VIOLATION]=== [2018-11-28 13:03:10,642 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-28 13:03:10,643 INFO L82 PathProgramCache]: Analyzing trace with hash 1646917324, now seen corresponding path program 2 times [2018-11-28 13:03:10,643 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-28 13:03:10,643 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-28 13:03:10,644 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 13:03:10,644 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-28 13:03:10,644 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 13:03:10,659 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-28 13:03:10,873 INFO L134 CoverageAnalysis]: Checked inductivity of 105 backedges. 0 proven. 105 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-28 13:03:10,873 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-28 13:03:10,873 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_a5616418-4a25-482a-a0cb-6eefe8bc17e5/bin-2019/uautomizer/z3 Starting monitored process 15 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 15 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-28 13:03:10,888 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-11-28 13:03:10,962 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2018-11-28 13:03:10,963 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-11-28 13:03:10,965 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-28 13:03:10,981 INFO L134 CoverageAnalysis]: Checked inductivity of 105 backedges. 0 proven. 105 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-28 13:03:10,996 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-11-28 13:03:10,996 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [18, 18] total 19 [2018-11-28 13:03:10,997 INFO L459 AbstractCegarLoop]: Interpolant automaton has 19 states [2018-11-28 13:03:10,997 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 19 interpolants. [2018-11-28 13:03:10,997 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=155, Invalid=187, Unknown=0, NotChecked=0, Total=342 [2018-11-28 13:03:10,997 INFO L87 Difference]: Start difference. First operand 115 states and 115 transitions. Second operand 19 states. [2018-11-28 13:03:11,030 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-28 13:03:11,030 INFO L93 Difference]: Finished difference Result 118 states and 118 transitions. [2018-11-28 13:03:11,031 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 18 states. [2018-11-28 13:03:11,031 INFO L78 Accepts]: Start accepts. Automaton has 19 states. Word has length 114 [2018-11-28 13:03:11,031 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-28 13:03:11,031 INFO L225 Difference]: With dead ends: 118 [2018-11-28 13:03:11,031 INFO L226 Difference]: Without dead ends: 116 [2018-11-28 13:03:11,031 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 132 GetRequests, 114 SyntacticMatches, 0 SemanticMatches, 18 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 41 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=159, Invalid=221, Unknown=0, NotChecked=0, Total=380 [2018-11-28 13:03:11,032 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 116 states. [2018-11-28 13:03:11,033 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 116 to 116. [2018-11-28 13:03:11,033 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 116 states. [2018-11-28 13:03:11,033 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 116 states to 116 states and 116 transitions. [2018-11-28 13:03:11,033 INFO L78 Accepts]: Start accepts. Automaton has 116 states and 116 transitions. Word has length 114 [2018-11-28 13:03:11,033 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-28 13:03:11,033 INFO L480 AbstractCegarLoop]: Abstraction has 116 states and 116 transitions. [2018-11-28 13:03:11,033 INFO L481 AbstractCegarLoop]: Interpolant automaton has 19 states. [2018-11-28 13:03:11,033 INFO L276 IsEmpty]: Start isEmpty. Operand 116 states and 116 transitions. [2018-11-28 13:03:11,034 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 116 [2018-11-28 13:03:11,034 INFO L394 BasicCegarLoop]: Found error trace [2018-11-28 13:03:11,034 INFO L402 BasicCegarLoop]: trace histogram [15, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-28 13:03:11,034 INFO L423 AbstractCegarLoop]: === Iteration 32 === [ldv_kref_initErr1REQUIRES_VIOLATION, ldv_kref_initErr0REQUIRES_VIOLATION, ldv_list_addErr1REQUIRES_VIOLATION, ldv_list_addErr0REQUIRES_VIOLATION, ldv_kobject_createErr0REQUIRES_VIOLATION, ldv_kobject_createErr1REQUIRES_VIOLATION, ldv_destroy_msgsErr3REQUIRES_VIOLATION, ldv_destroy_msgsErr2REQUIRES_VIOLATION, ldv_destroy_msgsErr1REQUIRES_VIOLATION, ldv_destroy_msgsErr0REQUIRES_VIOLATION, ldv_destroy_msgsErr5REQUIRES_VIOLATION, ldv_destroy_msgsErr4REQUIRES_VIOLATION, ldv_msg_fillErr1REQUIRES_VIOLATION, ldv_msg_fillErr4REQUIRES_VIOLATION, ldv_msg_fillErr0REQUIRES_VIOLATION, ldv_msg_fillErr5REQUIRES_VIOLATION, ldv_msg_fillErr3REQUIRES_VIOLATION, ldv_msg_fillErr2REQUIRES_VIOLATION, ldv_atomic_add_returnErr1REQUIRES_VIOLATION, ldv_atomic_add_returnErr0REQUIRES_VIOLATION, ldv_atomic_add_returnErr3REQUIRES_VIOLATION, ldv_atomic_add_returnErr2REQUIRES_VIOLATION, __ldv_list_delErr0REQUIRES_VIOLATION, __ldv_list_delErr1REQUIRES_VIOLATION, __ldv_list_delErr2REQUIRES_VIOLATION, __ldv_list_delErr3REQUIRES_VIOLATION, ldv_kobject_cleanupErr2ASSERT_VIOLATIONMEMORY_FREE, ldv_kobject_cleanupErr4ASSERT_VIOLATIONMEMORY_FREE, ldv_kobject_cleanupErr0REQUIRES_VIOLATION, ldv_kobject_cleanupErr5ASSERT_VIOLATIONMEMORY_FREE, ldv_kobject_cleanupErr1REQUIRES_VIOLATION, ldv_kobject_cleanupErr3ASSERT_VIOLATIONMEMORY_FREE, ldv_msg_freeErr2ASSERT_VIOLATIONMEMORY_FREE, ldv_msg_freeErr4ASSERT_VIOLATIONMEMORY_FREE, ldv_msg_freeErr5ASSERT_VIOLATIONMEMORY_FREE, ldv_msg_freeErr0REQUIRES_VIOLATION, ldv_msg_freeErr1REQUIRES_VIOLATION, ldv_msg_freeErr3ASSERT_VIOLATIONMEMORY_FREE, mainErr0ENSURES_VIOLATIONMEMORY_LEAK, LDV_INIT_LIST_HEADErr1REQUIRES_VIOLATION, LDV_INIT_LIST_HEADErr0REQUIRES_VIOLATION, LDV_INIT_LIST_HEADErr3REQUIRES_VIOLATION, LDV_INIT_LIST_HEADErr2REQUIRES_VIOLATION, ldv_list_delErr1REQUIRES_VIOLATION, ldv_list_delErr0REQUIRES_VIOLATION, ldv_list_delErr3REQUIRES_VIOLATION, ldv_list_delErr2REQUIRES_VIOLATION, __ldv_list_addErr4REQUIRES_VIOLATION, __ldv_list_addErr5REQUIRES_VIOLATION, __ldv_list_addErr0REQUIRES_VIOLATION, __ldv_list_addErr6REQUIRES_VIOLATION, __ldv_list_addErr1REQUIRES_VIOLATION, __ldv_list_addErr7REQUIRES_VIOLATION, __ldv_list_addErr2REQUIRES_VIOLATION, __ldv_list_addErr3REQUIRES_VIOLATION, ldv_dev_set_drvdataErr1REQUIRES_VIOLATION, ldv_dev_set_drvdataErr0REQUIRES_VIOLATION, ldv_atomic_sub_returnErr1REQUIRES_VIOLATION, ldv_atomic_sub_returnErr0REQUIRES_VIOLATION, ldv_atomic_sub_returnErr3REQUIRES_VIOLATION, ldv_atomic_sub_returnErr2REQUIRES_VIOLATION, ldv_list_add_tailErr0REQUIRES_VIOLATION, ldv_list_add_tailErr1REQUIRES_VIOLATION, ldv_dev_get_drvdataErr0REQUIRES_VIOLATION, ldv_dev_get_drvdataErr1REQUIRES_VIOLATION, ldv_msg_allocErr0REQUIRES_VIOLATION, ldv_msg_allocErr1REQUIRES_VIOLATION]=== [2018-11-28 13:03:11,034 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-28 13:03:11,034 INFO L82 PathProgramCache]: Analyzing trace with hash -1771693073, now seen corresponding path program 3 times [2018-11-28 13:03:11,034 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-28 13:03:11,034 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-28 13:03:11,035 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 13:03:11,035 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-28 13:03:11,035 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 13:03:11,049 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-28 13:03:11,217 INFO L134 CoverageAnalysis]: Checked inductivity of 120 backedges. 0 proven. 120 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-28 13:03:11,218 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-28 13:03:11,218 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_a5616418-4a25-482a-a0cb-6eefe8bc17e5/bin-2019/uautomizer/z3 Starting monitored process 16 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 16 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-28 13:03:11,229 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-11-28 13:03:37,161 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 9 check-sat command(s) [2018-11-28 13:03:37,161 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-11-28 13:03:37,174 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-28 13:03:37,374 INFO L134 CoverageAnalysis]: Checked inductivity of 120 backedges. 0 proven. 120 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-28 13:03:37,394 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-11-28 13:03:37,394 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [19, 23] total 40 [2018-11-28 13:03:37,395 INFO L459 AbstractCegarLoop]: Interpolant automaton has 40 states [2018-11-28 13:03:37,395 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 40 interpolants. [2018-11-28 13:03:37,395 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=470, Invalid=1090, Unknown=0, NotChecked=0, Total=1560 [2018-11-28 13:03:37,395 INFO L87 Difference]: Start difference. First operand 116 states and 116 transitions. Second operand 40 states. [2018-11-28 13:03:37,468 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-28 13:03:37,468 INFO L93 Difference]: Finished difference Result 119 states and 119 transitions. [2018-11-28 13:03:37,468 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 23 states. [2018-11-28 13:03:37,468 INFO L78 Accepts]: Start accepts. Automaton has 40 states. Word has length 115 [2018-11-28 13:03:37,468 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-28 13:03:37,469 INFO L225 Difference]: With dead ends: 119 [2018-11-28 13:03:37,469 INFO L226 Difference]: Without dead ends: 117 [2018-11-28 13:03:37,469 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 135 GetRequests, 95 SyntacticMatches, 0 SemanticMatches, 40 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 616 ImplicationChecksByTransitivity, 0.3s TimeCoverageRelationStatistics Valid=512, Invalid=1210, Unknown=0, NotChecked=0, Total=1722 [2018-11-28 13:03:37,470 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 117 states. [2018-11-28 13:03:37,471 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 117 to 117. [2018-11-28 13:03:37,471 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 117 states. [2018-11-28 13:03:37,472 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 117 states to 117 states and 117 transitions. [2018-11-28 13:03:37,472 INFO L78 Accepts]: Start accepts. Automaton has 117 states and 117 transitions. Word has length 115 [2018-11-28 13:03:37,472 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-28 13:03:37,472 INFO L480 AbstractCegarLoop]: Abstraction has 117 states and 117 transitions. [2018-11-28 13:03:37,476 INFO L481 AbstractCegarLoop]: Interpolant automaton has 40 states. [2018-11-28 13:03:37,476 INFO L276 IsEmpty]: Start isEmpty. Operand 117 states and 117 transitions. [2018-11-28 13:03:37,477 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 117 [2018-11-28 13:03:37,477 INFO L394 BasicCegarLoop]: Found error trace [2018-11-28 13:03:37,477 INFO L402 BasicCegarLoop]: trace histogram [16, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-28 13:03:37,477 INFO L423 AbstractCegarLoop]: === Iteration 33 === [ldv_kref_initErr1REQUIRES_VIOLATION, ldv_kref_initErr0REQUIRES_VIOLATION, ldv_list_addErr1REQUIRES_VIOLATION, ldv_list_addErr0REQUIRES_VIOLATION, ldv_kobject_createErr0REQUIRES_VIOLATION, ldv_kobject_createErr1REQUIRES_VIOLATION, ldv_destroy_msgsErr3REQUIRES_VIOLATION, ldv_destroy_msgsErr2REQUIRES_VIOLATION, ldv_destroy_msgsErr1REQUIRES_VIOLATION, ldv_destroy_msgsErr0REQUIRES_VIOLATION, ldv_destroy_msgsErr5REQUIRES_VIOLATION, ldv_destroy_msgsErr4REQUIRES_VIOLATION, ldv_msg_fillErr1REQUIRES_VIOLATION, ldv_msg_fillErr4REQUIRES_VIOLATION, ldv_msg_fillErr0REQUIRES_VIOLATION, ldv_msg_fillErr5REQUIRES_VIOLATION, ldv_msg_fillErr3REQUIRES_VIOLATION, ldv_msg_fillErr2REQUIRES_VIOLATION, ldv_atomic_add_returnErr1REQUIRES_VIOLATION, ldv_atomic_add_returnErr0REQUIRES_VIOLATION, ldv_atomic_add_returnErr3REQUIRES_VIOLATION, ldv_atomic_add_returnErr2REQUIRES_VIOLATION, __ldv_list_delErr0REQUIRES_VIOLATION, __ldv_list_delErr1REQUIRES_VIOLATION, __ldv_list_delErr2REQUIRES_VIOLATION, __ldv_list_delErr3REQUIRES_VIOLATION, ldv_kobject_cleanupErr2ASSERT_VIOLATIONMEMORY_FREE, ldv_kobject_cleanupErr4ASSERT_VIOLATIONMEMORY_FREE, ldv_kobject_cleanupErr0REQUIRES_VIOLATION, ldv_kobject_cleanupErr5ASSERT_VIOLATIONMEMORY_FREE, ldv_kobject_cleanupErr1REQUIRES_VIOLATION, ldv_kobject_cleanupErr3ASSERT_VIOLATIONMEMORY_FREE, ldv_msg_freeErr2ASSERT_VIOLATIONMEMORY_FREE, ldv_msg_freeErr4ASSERT_VIOLATIONMEMORY_FREE, ldv_msg_freeErr5ASSERT_VIOLATIONMEMORY_FREE, ldv_msg_freeErr0REQUIRES_VIOLATION, ldv_msg_freeErr1REQUIRES_VIOLATION, ldv_msg_freeErr3ASSERT_VIOLATIONMEMORY_FREE, mainErr0ENSURES_VIOLATIONMEMORY_LEAK, LDV_INIT_LIST_HEADErr1REQUIRES_VIOLATION, LDV_INIT_LIST_HEADErr0REQUIRES_VIOLATION, LDV_INIT_LIST_HEADErr3REQUIRES_VIOLATION, LDV_INIT_LIST_HEADErr2REQUIRES_VIOLATION, ldv_list_delErr1REQUIRES_VIOLATION, ldv_list_delErr0REQUIRES_VIOLATION, ldv_list_delErr3REQUIRES_VIOLATION, ldv_list_delErr2REQUIRES_VIOLATION, __ldv_list_addErr4REQUIRES_VIOLATION, __ldv_list_addErr5REQUIRES_VIOLATION, __ldv_list_addErr0REQUIRES_VIOLATION, __ldv_list_addErr6REQUIRES_VIOLATION, __ldv_list_addErr1REQUIRES_VIOLATION, __ldv_list_addErr7REQUIRES_VIOLATION, __ldv_list_addErr2REQUIRES_VIOLATION, __ldv_list_addErr3REQUIRES_VIOLATION, ldv_dev_set_drvdataErr1REQUIRES_VIOLATION, ldv_dev_set_drvdataErr0REQUIRES_VIOLATION, ldv_atomic_sub_returnErr1REQUIRES_VIOLATION, ldv_atomic_sub_returnErr0REQUIRES_VIOLATION, ldv_atomic_sub_returnErr3REQUIRES_VIOLATION, ldv_atomic_sub_returnErr2REQUIRES_VIOLATION, ldv_list_add_tailErr0REQUIRES_VIOLATION, ldv_list_add_tailErr1REQUIRES_VIOLATION, ldv_dev_get_drvdataErr0REQUIRES_VIOLATION, ldv_dev_get_drvdataErr1REQUIRES_VIOLATION, ldv_msg_allocErr0REQUIRES_VIOLATION, ldv_msg_allocErr1REQUIRES_VIOLATION]=== [2018-11-28 13:03:37,477 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-28 13:03:37,478 INFO L82 PathProgramCache]: Analyzing trace with hash -374432980, now seen corresponding path program 4 times [2018-11-28 13:03:37,478 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-28 13:03:37,478 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-28 13:03:37,478 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 13:03:37,478 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-28 13:03:37,479 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 13:03:37,523 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-28 13:03:37,554 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-28 13:03:37,577 INFO L469 BasicCegarLoop]: Counterexample might be feasible [2018-11-28 13:03:37,588 WARN L416 cessorBacktranslator]: Generated EnsuresSpecification free ensures #res.base == #ptr.base && #res.offset == #ptr.offset; is not ensure(true) [2018-11-28 13:03:37,595 WARN L416 cessorBacktranslator]: Generated EnsuresSpecification ensures #valid == old(#valid); is not ensure(true) [2018-11-28 13:03:37,600 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: IntegerLiteral 17 could not be translated for associated CType STRUCT~~ldv_list_head?next~*ldv_list_head?prev~*ldv_list_head# [2018-11-28 13:03:37,600 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: IntegerLiteral 18 could not be translated for associated CType STRUCT~~ldv_list_head?next~*ldv_list_head?prev~*ldv_list_head# [2018-11-28 13:03:37,613 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction CFG 28.11 01:03:37 BoogieIcfgContainer [2018-11-28 13:03:37,613 INFO L132 PluginConnector]: ------------------------ END TraceAbstraction---------------------------- [2018-11-28 13:03:37,614 INFO L113 PluginConnector]: ------------------------Witness Printer---------------------------- [2018-11-28 13:03:37,614 INFO L271 PluginConnector]: Initializing Witness Printer... [2018-11-28 13:03:37,614 INFO L276 PluginConnector]: Witness Printer initialized [2018-11-28 13:03:37,614 INFO L185 PluginConnector]: Executing the observer RCFGCatcher from plugin Witness Printer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 28.11 01:02:56" (3/4) ... [2018-11-28 13:03:37,621 INFO L147 WitnessPrinter]: No result that supports witness generation found [2018-11-28 13:03:37,621 INFO L132 PluginConnector]: ------------------------ END Witness Printer---------------------------- [2018-11-28 13:03:37,623 INFO L168 Benchmark]: Toolchain (without parser) took 42622.38 ms. Allocated memory was 1.0 GB in the beginning and 1.5 GB in the end (delta: 511.2 MB). Free memory was 950.6 MB in the beginning and 1.1 GB in the end (delta: -176.7 MB). Peak memory consumption was 334.5 MB. Max. memory is 11.5 GB. [2018-11-28 13:03:37,624 INFO L168 Benchmark]: CDTParser took 0.15 ms. Allocated memory is still 1.0 GB. Free memory is still 979.6 MB. There was no memory consumed. Max. memory is 11.5 GB. [2018-11-28 13:03:37,624 INFO L168 Benchmark]: CACSL2BoogieTranslator took 408.72 ms. Allocated memory was 1.0 GB in the beginning and 1.2 GB in the end (delta: 123.7 MB). Free memory was 950.6 MB in the beginning and 1.1 GB in the end (delta: -145.9 MB). Peak memory consumption was 33.0 MB. Max. memory is 11.5 GB. [2018-11-28 13:03:37,625 INFO L168 Benchmark]: Boogie Preprocessor took 58.41 ms. Allocated memory is still 1.2 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 6.8 MB). Peak memory consumption was 6.8 MB. Max. memory is 11.5 GB. [2018-11-28 13:03:37,625 INFO L168 Benchmark]: RCFGBuilder took 723.86 ms. Allocated memory is still 1.2 GB. Free memory was 1.1 GB in the beginning and 993.2 MB in the end (delta: 96.6 MB). Peak memory consumption was 96.6 MB. Max. memory is 11.5 GB. [2018-11-28 13:03:37,625 INFO L168 Benchmark]: TraceAbstraction took 41420.49 ms. Allocated memory was 1.2 GB in the beginning and 1.5 GB in the end (delta: 387.4 MB). Free memory was 993.2 MB in the beginning and 1.1 GB in the end (delta: -134.1 MB). Peak memory consumption was 253.3 MB. Max. memory is 11.5 GB. [2018-11-28 13:03:37,625 INFO L168 Benchmark]: Witness Printer took 7.38 ms. Allocated memory is still 1.5 GB. Free memory is still 1.1 GB. There was no memory consumed. Max. memory is 11.5 GB. [2018-11-28 13:03:37,627 INFO L336 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.15 ms. Allocated memory is still 1.0 GB. Free memory is still 979.6 MB. There was no memory consumed. Max. memory is 11.5 GB. * CACSL2BoogieTranslator took 408.72 ms. Allocated memory was 1.0 GB in the beginning and 1.2 GB in the end (delta: 123.7 MB). Free memory was 950.6 MB in the beginning and 1.1 GB in the end (delta: -145.9 MB). Peak memory consumption was 33.0 MB. Max. memory is 11.5 GB. * Boogie Preprocessor took 58.41 ms. Allocated memory is still 1.2 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 6.8 MB). Peak memory consumption was 6.8 MB. Max. memory is 11.5 GB. * RCFGBuilder took 723.86 ms. Allocated memory is still 1.2 GB. Free memory was 1.1 GB in the beginning and 993.2 MB in the end (delta: 96.6 MB). Peak memory consumption was 96.6 MB. Max. memory is 11.5 GB. * TraceAbstraction took 41420.49 ms. Allocated memory was 1.2 GB in the beginning and 1.5 GB in the end (delta: 387.4 MB). Free memory was 993.2 MB in the beginning and 1.1 GB in the end (delta: -134.1 MB). Peak memory consumption was 253.3 MB. Max. memory is 11.5 GB. * Witness Printer took 7.38 ms. Allocated memory is still 1.5 GB. Free memory is still 1.1 GB. There was no memory consumed. Max. memory is 11.5 GB. * Results from de.uni_freiburg.informatik.ultimate.boogie.preprocessor: - GenericResult: Unfinished Backtranslation Generated EnsuresSpecification free ensures #res.base == #ptr.base && #res.offset == #ptr.offset; is not ensure(true) - GenericResult: Unfinished Backtranslation Generated EnsuresSpecification ensures #valid == old(#valid); is not ensure(true) * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: IntegerLiteral 17 could not be translated for associated CType STRUCT~~ldv_list_head?next~*ldv_list_head?prev~*ldv_list_head# - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: IntegerLiteral 18 could not be translated for associated CType STRUCT~~ldv_list_head?next~*ldv_list_head?prev~*ldv_list_head# * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - UnprovableResult [Line: 1452]: Unable to prove that all allocated memory was freed Unable to prove that all allocated memory was freed Reason: overapproximation of memtrack at line 1452. Possible FailurePath: [L1135] struct ldv_list_head ldv_global_msg_list = { &(ldv_global_msg_list), &(ldv_global_msg_list) }; VAL [\old(ldv_global_msg_list)=null, \old(ldv_global_msg_list)=null, ldv_global_msg_list={30:0}] [L1453] CALL entry_point() VAL [ldv_global_msg_list={30:0}] [L1445] struct ldv_kobject *kobj; VAL [ldv_global_msg_list={30:0}] [L1446] CALL, EXPR ldv_kobject_create() VAL [ldv_global_msg_list={30:0}] [L1406] struct ldv_kobject *kobj; VAL [ldv_global_msg_list={30:0}] [L1408] CALL, EXPR ldv_malloc(sizeof(*kobj)) VAL [\old(size)=16, ldv_global_msg_list={30:0}] [L1073] COND TRUE __VERIFIER_nondet_int() [L1074] return malloc(size); VAL [\old(size)=16, \result={25:0}, ldv_global_msg_list={30:0}, malloc(size)={25:0}, size=16] [L1408] RET, EXPR ldv_malloc(sizeof(*kobj)) VAL [ldv_global_msg_list={30:0}, ldv_malloc(sizeof(*kobj))={25:0}] [L1408] kobj = ldv_malloc(sizeof(*kobj)) [L1409] COND FALSE !(!kobj) VAL [kobj={25:0}, ldv_global_msg_list={30:0}] [L1411] FCALL memset(kobj, 0, sizeof(*kobj)) VAL [kobj={25:0}, ldv_global_msg_list={30:0}, memset(kobj, 0, sizeof(*kobj))={25:0}] [L1413] CALL ldv_kobject_init(kobj) VAL [kobj={25:0}, ldv_global_msg_list={30:0}] [L1394] COND FALSE !(!kobj) VAL [kobj={25:0}, kobj={25:0}, ldv_global_msg_list={30:0}] [L1398] CALL ldv_kobject_init_internal(kobj) VAL [kobj={25:0}, ldv_global_msg_list={30:0}] [L1380] COND FALSE !(!kobj) VAL [kobj={25:0}, kobj={25:0}, ldv_global_msg_list={30:0}] [L1382] CALL ldv_kref_init(&kobj->kref) VAL [kref={25:12}, ldv_global_msg_list={30:0}] [L1294] ((&kref->refcount)->counter) = (1) VAL [kref={25:12}, kref={25:12}, ldv_global_msg_list={30:0}] [L1382] RET ldv_kref_init(&kobj->kref) VAL [kobj={25:0}, kobj={25:0}, ldv_global_msg_list={30:0}] [L1383] CALL LDV_INIT_LIST_HEAD(&kobj->entry) VAL [ldv_global_msg_list={30:0}, list={25:4}] [L1099] list->next = list VAL [ldv_global_msg_list={30:0}, list={25:4}, list={25:4}] [L1100] list->prev = list VAL [ldv_global_msg_list={30:0}, list={25:4}, list={25:4}] [L1383] RET LDV_INIT_LIST_HEAD(&kobj->entry) VAL [kobj={25:0}, kobj={25:0}, ldv_global_msg_list={30:0}] [L1398] RET ldv_kobject_init_internal(kobj) VAL [kobj={25:0}, kobj={25:0}, ldv_global_msg_list={30:0}] [L1413] RET ldv_kobject_init(kobj) VAL [kobj={25:0}, ldv_global_msg_list={30:0}] [L1414] return kobj; VAL [\result={25:0}, kobj={25:0}, ldv_global_msg_list={30:0}] [L1446] RET, EXPR ldv_kobject_create() VAL [ldv_global_msg_list={30:0}, ldv_kobject_create()={25:0}] [L1446] kobj = ldv_kobject_create() [L1447] CALL f_22_get(kobj) VAL [kobj={25:0}, ldv_global_msg_list={30:0}] [L1437] CALL ldv_kobject_get(kobj) VAL [kobj={25:0}, ldv_global_msg_list={30:0}] [L1373] COND TRUE \read(*kobj) VAL [kobj={25:0}, kobj={25:0}, ldv_global_msg_list={30:0}] [L1374] CALL ldv_kref_get(&kobj->kref) VAL [kref={25:12}, ldv_global_msg_list={30:0}] [L1308] CALL ldv_atomic_add_return(1, (&kref->refcount)) VAL [\old(i)=1, ldv_global_msg_list={30:0}, v={25:12}] [L1255] int temp; VAL [\old(i)=1, i=1, ldv_global_msg_list={30:0}, v={25:12}, v={25:12}] [L1256] EXPR v->counter VAL [\old(i)=1, i=1, ldv_global_msg_list={30:0}, v={25:12}, v={25:12}, v->counter=1] [L1256] temp = v->counter [L1257] temp += i VAL [\old(i)=1, i=1, ldv_global_msg_list={30:0}, temp=2, v={25:12}, v={25:12}] [L1258] v->counter = temp VAL [\old(i)=1, i=1, ldv_global_msg_list={30:0}, temp=2, v={25:12}, v={25:12}] [L1259] return temp; VAL [\old(i)=1, \result=2, i=1, ldv_global_msg_list={30:0}, temp=2, v={25:12}, v={25:12}] [L1308] RET ldv_atomic_add_return(1, (&kref->refcount)) VAL [kref={25:12}, kref={25:12}, ldv_atomic_add_return(1, (&kref->refcount))=2, ldv_global_msg_list={30:0}] [L1374] RET ldv_kref_get(&kobj->kref) VAL [kobj={25:0}, kobj={25:0}, ldv_global_msg_list={30:0}] [L1375] return kobj; VAL [\result={25:0}, kobj={25:0}, kobj={25:0}, ldv_global_msg_list={30:0}] [L1437] RET ldv_kobject_get(kobj) VAL [kobj={25:0}, kobj={25:0}, ldv_global_msg_list={30:0}, ldv_kobject_get(kobj)={25:0}] [L1447] RET f_22_get(kobj) VAL [kobj={25:0}, ldv_global_msg_list={30:0}] [L1449] CALL ldv_kobject_put(kobj) VAL [kobj={25:0}, ldv_global_msg_list={30:0}] [L1361] COND TRUE \read(*kobj) VAL [kobj={25:0}, kobj={25:0}, ldv_global_msg_list={30:0}] [L1363] CALL ldv_kref_put(&kobj->kref, ldv_kobject_release) VAL [kref={25:12}, ldv_global_msg_list={30:0}, release={-1:0}] [L1313] CALL, EXPR ldv_kref_sub(kref, 1, release) VAL [\old(count)=1, kref={25:12}, ldv_global_msg_list={30:0}, release={-1:0}] [L1281] CALL, EXPR ldv_atomic_sub_return(((int) count), (&kref->refcount)) VAL [\old(i)=1, ldv_global_msg_list={30:0}, v={25:12}] [L1264] int temp; VAL [\old(i)=1, i=1, ldv_global_msg_list={30:0}, v={25:12}, v={25:12}] [L1265] EXPR v->counter VAL [\old(i)=1, i=1, ldv_global_msg_list={30:0}, v={25:12}, v={25:12}, v->counter=2] [L1265] temp = v->counter [L1266] temp -= i VAL [\old(i)=1, i=1, ldv_global_msg_list={30:0}, temp=1, v={25:12}, v={25:12}] [L1267] v->counter = temp VAL [\old(i)=1, i=1, ldv_global_msg_list={30:0}, temp=1, v={25:12}, v={25:12}] [L1268] return temp; VAL [\old(i)=1, \result=1, i=1, ldv_global_msg_list={30:0}, temp=1, v={25:12}, v={25:12}] [L1281] RET, EXPR ldv_atomic_sub_return(((int) count), (&kref->refcount)) VAL [\old(count)=1, count=1, kref={25:12}, kref={25:12}, ldv_atomic_sub_return(((int) count), (&kref->refcount))=1, ldv_global_msg_list={30:0}, release={-1:0}, release={-1:0}] [L1281] COND FALSE !((ldv_atomic_sub_return(((int) count), (&kref->refcount)) == 0)) [L1285] return 0; VAL [\old(count)=1, \result=0, count=1, kref={25:12}, kref={25:12}, ldv_global_msg_list={30:0}, release={-1:0}, release={-1:0}] [L1313] RET, EXPR ldv_kref_sub(kref, 1, release) VAL [kref={25:12}, kref={25:12}, ldv_global_msg_list={30:0}, ldv_kref_sub(kref, 1, release)=0, release={-1:0}, release={-1:0}] [L1313] return ldv_kref_sub(kref, 1, release); [L1363] RET ldv_kref_put(&kobj->kref, ldv_kobject_release) VAL [kobj={25:0}, kobj={25:0}, ldv_global_msg_list={30:0}, ldv_kref_put(&kobj->kref, ldv_kobject_release)=0] [L1449] RET ldv_kobject_put(kobj) VAL [kobj={25:0}, ldv_global_msg_list={30:0}] [L1453] RET entry_point() VAL [ldv_global_msg_list={30:0}] - StatisticsResult: Ultimate Automizer benchmark data CFG has 45 procedures, 319 locations, 67 error locations. UNSAFE Result, 41.3s OverallTime, 33 OverallIterations, 16 TraceHistogramMax, 7.2s AutomataDifference, 0.0s DeadEndRemovalTime, 0.0s HoareAnnotationTime, HoareTripleCheckerStatistics: 4019 SDtfs, 911 SDslu, 32532 SDs, 0 SdLazy, 11999 SolverSat, 228 SolverUnsat, 0 SolverUnknown, 0 SolverNotchecked, 4.3s Time, PredicateUnifierStatistics: 0 DeclaredPredicates, 1702 GetRequests, 1116 SyntacticMatches, 20 SemanticMatches, 566 ConstructedPredicates, 1 IntricatePredicates, 0 DeprecatedPredicates, 3650 ImplicationChecksByTransitivity, 6.7s Time, 0.0s BasicInterpolantAutomatonTime, BiggestAbstraction: size=177occurred in iteration=0, traceCheckStatistics: No data available, InterpolantConsolidationStatistics: No data available, PathInvariantsStatistics: No data available, 0/0 InterpolantCoveringCapability, TotalInterpolationStatistics: No data available, 0.0s AbstIntTime, 0 AbstIntIterations, 0 AbstIntStrong, NaN AbsIntWeakeningRatio, NaN AbsIntAvgWeakeningVarsNumRemoved, NaN AbsIntAvgWeakenedConjuncts, 0.0s DumpTime, AutomataMinimizationStatistics: 0.1s AutomataMinimizationTime, 32 MinimizatonAttempts, 106 StatesRemovedByMinimization, 10 NontrivialMinimizations, HoareAnnotationStatistics: No data available, RefinementEngineStatistics: TraceCheckStatistics: 0.2s SsaConstructionTime, 26.6s SatisfiabilityAnalysisTime, 6.0s InterpolantComputationTime, 3392 NumberOfCodeBlocks, 3350 NumberOfCodeBlocksAsserted, 57 NumberOfCheckSat, 3229 ConstructedInterpolants, 174 QuantifiedInterpolants, 608923 SizeOfPredicates, 114 NumberOfNonLiveVariables, 6119 ConjunctsInSsa, 586 ConjunctsInUnsatCore, 47 InterpolantComputations, 23 PerfectInterpolantSequences, 400/1557 InterpolantCoveringCapability, InvariantSynthesisStatistics: No data available, InterpolantConsolidationStatistics: No data available, ReuseStatistics: No data available RESULT: Ultimate could not prove your program: unable to determine feasibility of some traces Received shutdown request... ### Bit-precise run ### This is Ultimate 0.1.23-0cd3be1 [2018-11-28 13:03:39,100 INFO L170 SettingsManager]: Resetting all preferences to default values... [2018-11-28 13:03:39,101 INFO L174 SettingsManager]: Resetting UltimateCore preferences to default values [2018-11-28 13:03:39,109 INFO L177 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2018-11-28 13:03:39,109 INFO L174 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2018-11-28 13:03:39,110 INFO L174 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2018-11-28 13:03:39,111 INFO L174 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2018-11-28 13:03:39,112 INFO L174 SettingsManager]: Resetting LassoRanker preferences to default values [2018-11-28 13:03:39,113 INFO L174 SettingsManager]: Resetting Reaching Definitions preferences to default values [2018-11-28 13:03:39,114 INFO L174 SettingsManager]: Resetting SyntaxChecker preferences to default values [2018-11-28 13:03:39,114 INFO L177 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2018-11-28 13:03:39,115 INFO L174 SettingsManager]: Resetting LTL2Aut preferences to default values [2018-11-28 13:03:39,115 INFO L174 SettingsManager]: Resetting PEA to Boogie preferences to default values [2018-11-28 13:03:39,116 INFO L174 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2018-11-28 13:03:39,117 INFO L174 SettingsManager]: Resetting ChcToBoogie preferences to default values [2018-11-28 13:03:39,118 INFO L174 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2018-11-28 13:03:39,118 INFO L174 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2018-11-28 13:03:39,119 INFO L174 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2018-11-28 13:03:39,121 INFO L174 SettingsManager]: Resetting CodeCheck preferences to default values [2018-11-28 13:03:39,123 INFO L174 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2018-11-28 13:03:39,123 INFO L174 SettingsManager]: Resetting RCFGBuilder preferences to default values [2018-11-28 13:03:39,124 INFO L174 SettingsManager]: Resetting TraceAbstraction preferences to default values [2018-11-28 13:03:39,126 INFO L177 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2018-11-28 13:03:39,126 INFO L177 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2018-11-28 13:03:39,127 INFO L174 SettingsManager]: Resetting TreeAutomizer preferences to default values [2018-11-28 13:03:39,127 INFO L174 SettingsManager]: Resetting IcfgTransformer preferences to default values [2018-11-28 13:03:39,128 INFO L174 SettingsManager]: Resetting Boogie Printer preferences to default values [2018-11-28 13:03:39,129 INFO L174 SettingsManager]: Resetting ReqPrinter preferences to default values [2018-11-28 13:03:39,130 INFO L174 SettingsManager]: Resetting Witness Printer preferences to default values [2018-11-28 13:03:39,130 INFO L177 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2018-11-28 13:03:39,131 INFO L174 SettingsManager]: Resetting CDTParser preferences to default values [2018-11-28 13:03:39,131 INFO L177 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2018-11-28 13:03:39,131 INFO L177 SettingsManager]: ReqParser provides no preferences, ignoring... [2018-11-28 13:03:39,131 INFO L174 SettingsManager]: Resetting SmtParser preferences to default values [2018-11-28 13:03:39,133 INFO L174 SettingsManager]: Resetting Witness Parser preferences to default values [2018-11-28 13:03:39,133 INFO L181 SettingsManager]: Finished resetting all preferences to default values... [2018-11-28 13:03:39,133 INFO L98 SettingsManager]: Beginning loading settings from /tmp/vcloud-vcloud-master/worker/working_dir_a5616418-4a25-482a-a0cb-6eefe8bc17e5/bin-2019/uautomizer/config/svcomp-DerefFreeMemtrack-32bit-Automizer_Bitvector.epf [2018-11-28 13:03:39,144 INFO L110 SettingsManager]: Loading preferences was successful [2018-11-28 13:03:39,144 INFO L112 SettingsManager]: Preferences different from defaults after loading the file: [2018-11-28 13:03:39,145 INFO L131 SettingsManager]: Preferences of Boogie Procedure Inliner differ from their defaults: [2018-11-28 13:03:39,145 INFO L133 SettingsManager]: * ... calls to implemented procedures=ONLY_FOR_CONCURRENT_PROGRAMS [2018-11-28 13:03:39,146 INFO L131 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2018-11-28 13:03:39,146 INFO L133 SettingsManager]: * Create parallel compositions if possible=false [2018-11-28 13:03:39,146 INFO L133 SettingsManager]: * Use SBE=true [2018-11-28 13:03:39,146 INFO L131 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2018-11-28 13:03:39,146 INFO L133 SettingsManager]: * sizeof long=4 [2018-11-28 13:03:39,146 INFO L133 SettingsManager]: * Check unreachability of error function in SV-COMP mode=false [2018-11-28 13:03:39,146 INFO L133 SettingsManager]: * Overapproximate operations on floating types=true [2018-11-28 13:03:39,147 INFO L133 SettingsManager]: * sizeof POINTER=4 [2018-11-28 13:03:39,147 INFO L133 SettingsManager]: * Check division by zero=IGNORE [2018-11-28 13:03:39,147 INFO L133 SettingsManager]: * Check for the main procedure if all allocated memory was freed=true [2018-11-28 13:03:39,147 INFO L133 SettingsManager]: * Bitprecise bitfields=true [2018-11-28 13:03:39,147 INFO L133 SettingsManager]: * SV-COMP memtrack compatibility mode=true [2018-11-28 13:03:39,147 INFO L133 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=IGNORE [2018-11-28 13:03:39,147 INFO L133 SettingsManager]: * Use bitvectors instead of ints=true [2018-11-28 13:03:39,147 INFO L133 SettingsManager]: * Memory model=HoenickeLindenmann_4ByteResolution [2018-11-28 13:03:39,147 INFO L133 SettingsManager]: * sizeof long double=12 [2018-11-28 13:03:39,148 INFO L133 SettingsManager]: * Use constant arrays=true [2018-11-28 13:03:39,148 INFO L131 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2018-11-28 13:03:39,148 INFO L133 SettingsManager]: * Size of a code block=SequenceOfStatements [2018-11-28 13:03:39,148 INFO L133 SettingsManager]: * To the following directory=./dump/ [2018-11-28 13:03:39,149 INFO L133 SettingsManager]: * SMT solver=External_DefaultMode [2018-11-28 13:03:39,149 INFO L133 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2018-11-28 13:03:39,150 INFO L131 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2018-11-28 13:03:39,150 INFO L133 SettingsManager]: * Compute Interpolants along a Counterexample=FPandBP [2018-11-28 13:03:39,150 INFO L133 SettingsManager]: * Trace refinement strategy=WOLF [2018-11-28 13:03:39,150 INFO L133 SettingsManager]: * SMT solver=External_ModelsAndUnsatCoreMode [2018-11-28 13:03:39,150 INFO L133 SettingsManager]: * Command for external solver=cvc4 --incremental --rewrite-divk --print-success --lang smt [2018-11-28 13:03:39,150 INFO L133 SettingsManager]: * Logic for external solver=AUFBV Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud-vcloud-master/worker/working_dir_a5616418-4a25-482a-a0cb-6eefe8bc17e5/bin-2019/uautomizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(G valid-free) ) CHECK( init(main()), LTL(G valid-deref) ) CHECK( init(main()), LTL(G valid-memtrack) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> bc6894f63179c5a0c3641b97a75e8f614c456bea [2018-11-28 13:03:39,176 INFO L81 nceAwareModelManager]: Repository-Root is: /tmp [2018-11-28 13:03:39,185 INFO L258 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2018-11-28 13:03:39,188 INFO L214 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2018-11-28 13:03:39,189 INFO L271 PluginConnector]: Initializing CDTParser... [2018-11-28 13:03:39,189 INFO L276 PluginConnector]: CDTParser initialized [2018-11-28 13:03:39,190 INFO L418 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud-vcloud-master/worker/working_dir_a5616418-4a25-482a-a0cb-6eefe8bc17e5/bin-2019/uautomizer/../../sv-benchmarks/c/ldv-memsafety/memleaks_test22_4_false-valid-memtrack_true-termination.i [2018-11-28 13:03:39,235 INFO L221 CDTParser]: Created temporary CDT project at /tmp/vcloud-vcloud-master/worker/working_dir_a5616418-4a25-482a-a0cb-6eefe8bc17e5/bin-2019/uautomizer/data/b88c78c7a/250da99f46534fff8b159c8148694314/FLAG32e1916f9 [2018-11-28 13:03:39,618 INFO L307 CDTParser]: Found 1 translation units. [2018-11-28 13:03:39,618 INFO L161 CDTParser]: Scanning /tmp/vcloud-vcloud-master/worker/working_dir_a5616418-4a25-482a-a0cb-6eefe8bc17e5/sv-benchmarks/c/ldv-memsafety/memleaks_test22_4_false-valid-memtrack_true-termination.i [2018-11-28 13:03:39,628 INFO L355 CDTParser]: About to delete temporary CDT project at /tmp/vcloud-vcloud-master/worker/working_dir_a5616418-4a25-482a-a0cb-6eefe8bc17e5/bin-2019/uautomizer/data/b88c78c7a/250da99f46534fff8b159c8148694314/FLAG32e1916f9 [2018-11-28 13:03:39,640 INFO L363 CDTParser]: Successfully deleted /tmp/vcloud-vcloud-master/worker/working_dir_a5616418-4a25-482a-a0cb-6eefe8bc17e5/bin-2019/uautomizer/data/b88c78c7a/250da99f46534fff8b159c8148694314 [2018-11-28 13:03:39,643 INFO L296 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2018-11-28 13:03:39,644 INFO L131 ToolchainWalker]: Walking toolchain with 5 elements. [2018-11-28 13:03:39,645 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2018-11-28 13:03:39,645 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2018-11-28 13:03:39,648 INFO L276 PluginConnector]: CACSL2BoogieTranslator initialized [2018-11-28 13:03:39,649 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 28.11 01:03:39" (1/1) ... [2018-11-28 13:03:39,651 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@600c6be4 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 01:03:39, skipping insertion in model container [2018-11-28 13:03:39,651 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 28.11 01:03:39" (1/1) ... [2018-11-28 13:03:39,658 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2018-11-28 13:03:39,691 INFO L176 MainTranslator]: Built tables and reachable declarations [2018-11-28 13:03:39,951 INFO L203 PostProcessor]: Analyzing one entry point: main [2018-11-28 13:03:40,010 INFO L191 MainTranslator]: Completed pre-run [2018-11-28 13:03:40,058 INFO L203 PostProcessor]: Analyzing one entry point: main [2018-11-28 13:03:40,109 INFO L195 MainTranslator]: Completed translation [2018-11-28 13:03:40,110 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 01:03:40 WrapperNode [2018-11-28 13:03:40,110 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2018-11-28 13:03:40,111 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2018-11-28 13:03:40,111 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2018-11-28 13:03:40,111 INFO L276 PluginConnector]: Boogie Preprocessor initialized [2018-11-28 13:03:40,121 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 01:03:40" (1/1) ... [2018-11-28 13:03:40,121 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 01:03:40" (1/1) ... [2018-11-28 13:03:40,133 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 01:03:40" (1/1) ... [2018-11-28 13:03:40,133 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 01:03:40" (1/1) ... [2018-11-28 13:03:40,150 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 01:03:40" (1/1) ... [2018-11-28 13:03:40,153 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 01:03:40" (1/1) ... [2018-11-28 13:03:40,156 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 01:03:40" (1/1) ... [2018-11-28 13:03:40,161 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2018-11-28 13:03:40,161 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2018-11-28 13:03:40,162 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2018-11-28 13:03:40,162 INFO L276 PluginConnector]: RCFGBuilder initialized [2018-11-28 13:03:40,162 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 01:03:40" (1/1) ... No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_a5616418-4a25-482a-a0cb-6eefe8bc17e5/bin-2019/uautomizer/z3 Starting monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2018-11-28 13:03:40,196 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.init [2018-11-28 13:03:40,196 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2018-11-28 13:03:40,196 INFO L138 BoogieDeclarations]: Found implementation of procedure ##fun~$Pointer$~TO~VOID [2018-11-28 13:03:40,197 INFO L138 BoogieDeclarations]: Found implementation of procedure __bswap_32 [2018-11-28 13:03:40,197 INFO L138 BoogieDeclarations]: Found implementation of procedure __bswap_64 [2018-11-28 13:03:40,197 INFO L138 BoogieDeclarations]: Found implementation of procedure ldv_nonpositive [2018-11-28 13:03:40,197 INFO L138 BoogieDeclarations]: Found implementation of procedure ldv_positive [2018-11-28 13:03:40,197 INFO L138 BoogieDeclarations]: Found implementation of procedure ldv_malloc [2018-11-28 13:03:40,197 INFO L138 BoogieDeclarations]: Found implementation of procedure ldv_zalloc [2018-11-28 13:03:40,197 INFO L138 BoogieDeclarations]: Found implementation of procedure LDV_INIT_LIST_HEAD [2018-11-28 13:03:40,197 INFO L138 BoogieDeclarations]: Found implementation of procedure __ldv_list_add [2018-11-28 13:03:40,197 INFO L138 BoogieDeclarations]: Found implementation of procedure __ldv_list_del [2018-11-28 13:03:40,198 INFO L138 BoogieDeclarations]: Found implementation of procedure ldv_list_add [2018-11-28 13:03:40,198 INFO L138 BoogieDeclarations]: Found implementation of procedure ldv_list_add_tail [2018-11-28 13:03:40,198 INFO L138 BoogieDeclarations]: Found implementation of procedure ldv_list_del [2018-11-28 13:03:40,198 INFO L138 BoogieDeclarations]: Found implementation of procedure ldv_msg_alloc [2018-11-28 13:03:40,198 INFO L138 BoogieDeclarations]: Found implementation of procedure ldv_msg_fill [2018-11-28 13:03:40,198 INFO L138 BoogieDeclarations]: Found implementation of procedure ldv_msg_free [2018-11-28 13:03:40,198 INFO L138 BoogieDeclarations]: Found implementation of procedure ldv_submit_msg [2018-11-28 13:03:40,199 INFO L138 BoogieDeclarations]: Found implementation of procedure ldv_destroy_msgs [2018-11-28 13:03:40,199 INFO L138 BoogieDeclarations]: Found implementation of procedure ldv_dev_get_drvdata [2018-11-28 13:03:40,199 INFO L138 BoogieDeclarations]: Found implementation of procedure ldv_dev_set_drvdata [2018-11-28 13:03:40,199 INFO L138 BoogieDeclarations]: Found implementation of procedure ldv_atomic_add_return [2018-11-28 13:03:40,199 INFO L138 BoogieDeclarations]: Found implementation of procedure ldv_atomic_sub_return [2018-11-28 13:03:40,199 INFO L138 BoogieDeclarations]: Found implementation of procedure ldv_kref_sub [2018-11-28 13:03:40,199 INFO L138 BoogieDeclarations]: Found implementation of procedure ldv_kref_init [2018-11-28 13:03:40,199 INFO L138 BoogieDeclarations]: Found implementation of procedure ldv_kref_get [2018-11-28 13:03:40,199 INFO L138 BoogieDeclarations]: Found implementation of procedure ldv_kref_put [2018-11-28 13:03:40,199 INFO L138 BoogieDeclarations]: Found implementation of procedure ldv_kobject_del [2018-11-28 13:03:40,200 INFO L138 BoogieDeclarations]: Found implementation of procedure ldv_kobject_cleanup [2018-11-28 13:03:40,200 INFO L138 BoogieDeclarations]: Found implementation of procedure ldv_kobject_release [2018-11-28 13:03:40,200 INFO L138 BoogieDeclarations]: Found implementation of procedure ldv_kobject_put [2018-11-28 13:03:40,200 INFO L138 BoogieDeclarations]: Found implementation of procedure ldv_kobject_get [2018-11-28 13:03:40,200 INFO L138 BoogieDeclarations]: Found implementation of procedure ldv_kobject_init_internal [2018-11-28 13:03:40,200 INFO L138 BoogieDeclarations]: Found implementation of procedure ldv_kobject_init [2018-11-28 13:03:40,200 INFO L138 BoogieDeclarations]: Found implementation of procedure ldv_kobject_create [2018-11-28 13:03:40,200 INFO L138 BoogieDeclarations]: Found implementation of procedure f [2018-11-28 13:03:40,200 INFO L138 BoogieDeclarations]: Found implementation of procedure g [2018-11-28 13:03:40,201 INFO L138 BoogieDeclarations]: Found implementation of procedure f_22_get [2018-11-28 13:03:40,201 INFO L138 BoogieDeclarations]: Found implementation of procedure f_22_put [2018-11-28 13:03:40,201 INFO L138 BoogieDeclarations]: Found implementation of procedure entry_point [2018-11-28 13:03:40,201 INFO L138 BoogieDeclarations]: Found implementation of procedure main [2018-11-28 13:03:40,201 INFO L138 BoogieDeclarations]: Found implementation of procedure #Ultimate.C_memset [2018-11-28 13:03:40,201 INFO L138 BoogieDeclarations]: Found implementation of procedure #Ultimate.meminit [2018-11-28 13:03:40,201 INFO L138 BoogieDeclarations]: Found implementation of procedure #Ultimate.C_memcpy [2018-11-28 13:03:40,201 INFO L130 BoogieDeclarations]: Found specification of procedure __bswap_32 [2018-11-28 13:03:40,201 INFO L130 BoogieDeclarations]: Found specification of procedure __bswap_64 [2018-11-28 13:03:40,202 INFO L130 BoogieDeclarations]: Found specification of procedure __ctype_get_mb_cur_max [2018-11-28 13:03:40,202 INFO L130 BoogieDeclarations]: Found specification of procedure atof [2018-11-28 13:03:40,202 INFO L130 BoogieDeclarations]: Found specification of procedure atoi [2018-11-28 13:03:40,202 INFO L130 BoogieDeclarations]: Found specification of procedure atol [2018-11-28 13:03:40,202 INFO L130 BoogieDeclarations]: Found specification of procedure atoll [2018-11-28 13:03:40,202 INFO L130 BoogieDeclarations]: Found specification of procedure strtod [2018-11-28 13:03:40,202 INFO L130 BoogieDeclarations]: Found specification of procedure strtof [2018-11-28 13:03:40,202 INFO L130 BoogieDeclarations]: Found specification of procedure strtold [2018-11-28 13:03:40,202 INFO L130 BoogieDeclarations]: Found specification of procedure strtol [2018-11-28 13:03:40,202 INFO L130 BoogieDeclarations]: Found specification of procedure strtoul [2018-11-28 13:03:40,202 INFO L130 BoogieDeclarations]: Found specification of procedure strtoq [2018-11-28 13:03:40,202 INFO L130 BoogieDeclarations]: Found specification of procedure strtouq [2018-11-28 13:03:40,202 INFO L130 BoogieDeclarations]: Found specification of procedure strtoll [2018-11-28 13:03:40,202 INFO L130 BoogieDeclarations]: Found specification of procedure strtoull [2018-11-28 13:03:40,202 INFO L130 BoogieDeclarations]: Found specification of procedure l64a [2018-11-28 13:03:40,203 INFO L130 BoogieDeclarations]: Found specification of procedure a64l [2018-11-28 13:03:40,203 INFO L130 BoogieDeclarations]: Found specification of procedure select [2018-11-28 13:03:40,203 INFO L130 BoogieDeclarations]: Found specification of procedure pselect [2018-11-28 13:03:40,203 INFO L130 BoogieDeclarations]: Found specification of procedure gnu_dev_major [2018-11-28 13:03:40,203 INFO L130 BoogieDeclarations]: Found specification of procedure gnu_dev_minor [2018-11-28 13:03:40,203 INFO L130 BoogieDeclarations]: Found specification of procedure gnu_dev_makedev [2018-11-28 13:03:40,203 INFO L130 BoogieDeclarations]: Found specification of procedure random [2018-11-28 13:03:40,203 INFO L130 BoogieDeclarations]: Found specification of procedure srandom [2018-11-28 13:03:40,203 INFO L130 BoogieDeclarations]: Found specification of procedure initstate [2018-11-28 13:03:40,203 INFO L130 BoogieDeclarations]: Found specification of procedure setstate [2018-11-28 13:03:40,203 INFO L130 BoogieDeclarations]: Found specification of procedure random_r [2018-11-28 13:03:40,203 INFO L130 BoogieDeclarations]: Found specification of procedure srandom_r [2018-11-28 13:03:40,203 INFO L130 BoogieDeclarations]: Found specification of procedure initstate_r [2018-11-28 13:03:40,203 INFO L130 BoogieDeclarations]: Found specification of procedure setstate_r [2018-11-28 13:03:40,204 INFO L130 BoogieDeclarations]: Found specification of procedure rand [2018-11-28 13:03:40,204 INFO L130 BoogieDeclarations]: Found specification of procedure srand [2018-11-28 13:03:40,204 INFO L130 BoogieDeclarations]: Found specification of procedure rand_r [2018-11-28 13:03:40,204 INFO L130 BoogieDeclarations]: Found specification of procedure drand48 [2018-11-28 13:03:40,204 INFO L130 BoogieDeclarations]: Found specification of procedure erand48 [2018-11-28 13:03:40,204 INFO L130 BoogieDeclarations]: Found specification of procedure lrand48 [2018-11-28 13:03:40,204 INFO L130 BoogieDeclarations]: Found specification of procedure nrand48 [2018-11-28 13:03:40,204 INFO L130 BoogieDeclarations]: Found specification of procedure mrand48 [2018-11-28 13:03:40,204 INFO L130 BoogieDeclarations]: Found specification of procedure jrand48 [2018-11-28 13:03:40,204 INFO L130 BoogieDeclarations]: Found specification of procedure srand48 [2018-11-28 13:03:40,204 INFO L130 BoogieDeclarations]: Found specification of procedure seed48 [2018-11-28 13:03:40,204 INFO L130 BoogieDeclarations]: Found specification of procedure lcong48 [2018-11-28 13:03:40,204 INFO L130 BoogieDeclarations]: Found specification of procedure drand48_r [2018-11-28 13:03:40,204 INFO L130 BoogieDeclarations]: Found specification of procedure erand48_r [2018-11-28 13:03:40,205 INFO L130 BoogieDeclarations]: Found specification of procedure lrand48_r [2018-11-28 13:03:40,205 INFO L130 BoogieDeclarations]: Found specification of procedure nrand48_r [2018-11-28 13:03:40,205 INFO L130 BoogieDeclarations]: Found specification of procedure mrand48_r [2018-11-28 13:03:40,205 INFO L130 BoogieDeclarations]: Found specification of procedure jrand48_r [2018-11-28 13:03:40,205 INFO L130 BoogieDeclarations]: Found specification of procedure srand48_r [2018-11-28 13:03:40,205 INFO L130 BoogieDeclarations]: Found specification of procedure seed48_r [2018-11-28 13:03:40,205 INFO L130 BoogieDeclarations]: Found specification of procedure lcong48_r [2018-11-28 13:03:40,205 INFO L130 BoogieDeclarations]: Found specification of procedure malloc [2018-11-28 13:03:40,205 INFO L130 BoogieDeclarations]: Found specification of procedure calloc [2018-11-28 13:03:40,206 INFO L130 BoogieDeclarations]: Found specification of procedure realloc [2018-11-28 13:03:40,206 INFO L130 BoogieDeclarations]: Found specification of procedure free [2018-11-28 13:03:40,206 INFO L130 BoogieDeclarations]: Found specification of procedure cfree [2018-11-28 13:03:40,206 INFO L130 BoogieDeclarations]: Found specification of procedure alloca [2018-11-28 13:03:40,206 INFO L130 BoogieDeclarations]: Found specification of procedure valloc [2018-11-28 13:03:40,206 INFO L130 BoogieDeclarations]: Found specification of procedure posix_memalign [2018-11-28 13:03:40,206 INFO L130 BoogieDeclarations]: Found specification of procedure abort [2018-11-28 13:03:40,206 INFO L130 BoogieDeclarations]: Found specification of procedure atexit [2018-11-28 13:03:40,206 INFO L130 BoogieDeclarations]: Found specification of procedure on_exit [2018-11-28 13:03:40,206 INFO L130 BoogieDeclarations]: Found specification of procedure exit [2018-11-28 13:03:40,207 INFO L130 BoogieDeclarations]: Found specification of procedure _Exit [2018-11-28 13:03:40,207 INFO L130 BoogieDeclarations]: Found specification of procedure getenv [2018-11-28 13:03:40,207 INFO L130 BoogieDeclarations]: Found specification of procedure putenv [2018-11-28 13:03:40,207 INFO L130 BoogieDeclarations]: Found specification of procedure setenv [2018-11-28 13:03:40,207 INFO L130 BoogieDeclarations]: Found specification of procedure unsetenv [2018-11-28 13:03:40,207 INFO L130 BoogieDeclarations]: Found specification of procedure clearenv [2018-11-28 13:03:40,207 INFO L130 BoogieDeclarations]: Found specification of procedure mktemp [2018-11-28 13:03:40,207 INFO L130 BoogieDeclarations]: Found specification of procedure mkstemp [2018-11-28 13:03:40,208 INFO L130 BoogieDeclarations]: Found specification of procedure mkstemps [2018-11-28 13:03:40,208 INFO L130 BoogieDeclarations]: Found specification of procedure mkdtemp [2018-11-28 13:03:40,208 INFO L130 BoogieDeclarations]: Found specification of procedure system [2018-11-28 13:03:40,208 INFO L130 BoogieDeclarations]: Found specification of procedure realpath [2018-11-28 13:03:40,208 INFO L130 BoogieDeclarations]: Found specification of procedure bsearch [2018-11-28 13:03:40,208 INFO L130 BoogieDeclarations]: Found specification of procedure qsort [2018-11-28 13:03:40,208 INFO L130 BoogieDeclarations]: Found specification of procedure abs [2018-11-28 13:03:40,208 INFO L130 BoogieDeclarations]: Found specification of procedure labs [2018-11-28 13:03:40,209 INFO L130 BoogieDeclarations]: Found specification of procedure llabs [2018-11-28 13:03:40,209 INFO L130 BoogieDeclarations]: Found specification of procedure div [2018-11-28 13:03:40,209 INFO L130 BoogieDeclarations]: Found specification of procedure ldiv [2018-11-28 13:03:40,209 INFO L130 BoogieDeclarations]: Found specification of procedure lldiv [2018-11-28 13:03:40,209 INFO L130 BoogieDeclarations]: Found specification of procedure ecvt [2018-11-28 13:03:40,209 INFO L130 BoogieDeclarations]: Found specification of procedure fcvt [2018-11-28 13:03:40,209 INFO L130 BoogieDeclarations]: Found specification of procedure gcvt [2018-11-28 13:03:40,210 INFO L130 BoogieDeclarations]: Found specification of procedure qecvt [2018-11-28 13:03:40,210 INFO L130 BoogieDeclarations]: Found specification of procedure qfcvt [2018-11-28 13:03:40,210 INFO L130 BoogieDeclarations]: Found specification of procedure qgcvt [2018-11-28 13:03:40,210 INFO L130 BoogieDeclarations]: Found specification of procedure ecvt_r [2018-11-28 13:03:40,210 INFO L130 BoogieDeclarations]: Found specification of procedure fcvt_r [2018-11-28 13:03:40,210 INFO L130 BoogieDeclarations]: Found specification of procedure qecvt_r [2018-11-28 13:03:40,210 INFO L130 BoogieDeclarations]: Found specification of procedure qfcvt_r [2018-11-28 13:03:40,210 INFO L130 BoogieDeclarations]: Found specification of procedure mblen [2018-11-28 13:03:40,211 INFO L130 BoogieDeclarations]: Found specification of procedure mbtowc [2018-11-28 13:03:40,211 INFO L130 BoogieDeclarations]: Found specification of procedure wctomb [2018-11-28 13:03:40,211 INFO L130 BoogieDeclarations]: Found specification of procedure mbstowcs [2018-11-28 13:03:40,211 INFO L130 BoogieDeclarations]: Found specification of procedure wcstombs [2018-11-28 13:03:40,211 INFO L130 BoogieDeclarations]: Found specification of procedure rpmatch [2018-11-28 13:03:40,211 INFO L130 BoogieDeclarations]: Found specification of procedure getsubopt [2018-11-28 13:03:40,211 INFO L130 BoogieDeclarations]: Found specification of procedure getloadavg [2018-11-28 13:03:40,211 INFO L130 BoogieDeclarations]: Found specification of procedure kfree [2018-11-28 13:03:40,211 INFO L130 BoogieDeclarations]: Found specification of procedure __VERIFIER_nondet_int [2018-11-28 13:03:40,212 INFO L130 BoogieDeclarations]: Found specification of procedure __VERIFIER_nondet_pointer [2018-11-28 13:03:40,212 INFO L130 BoogieDeclarations]: Found specification of procedure ldv_nonpositive [2018-11-28 13:03:40,212 INFO L130 BoogieDeclarations]: Found specification of procedure ldv_positive [2018-11-28 13:03:40,212 INFO L130 BoogieDeclarations]: Found specification of procedure memcpy [2018-11-28 13:03:40,212 INFO L130 BoogieDeclarations]: Found specification of procedure memset [2018-11-28 13:03:40,212 INFO L130 BoogieDeclarations]: Found specification of procedure ldv_malloc [2018-11-28 13:03:40,212 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.alloc [2018-11-28 13:03:40,212 INFO L130 BoogieDeclarations]: Found specification of procedure ldv_zalloc [2018-11-28 13:03:40,212 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.meminit [2018-11-28 13:03:40,213 INFO L130 BoogieDeclarations]: Found specification of procedure LDV_INIT_LIST_HEAD [2018-11-28 13:03:40,213 INFO L130 BoogieDeclarations]: Found specification of procedure write~$Pointer$ [2018-11-28 13:03:40,213 INFO L130 BoogieDeclarations]: Found specification of procedure __ldv_list_add [2018-11-28 13:03:40,213 INFO L130 BoogieDeclarations]: Found specification of procedure __ldv_list_del [2018-11-28 13:03:40,213 INFO L130 BoogieDeclarations]: Found specification of procedure ldv_list_add [2018-11-28 13:03:40,213 INFO L130 BoogieDeclarations]: Found specification of procedure read~$Pointer$ [2018-11-28 13:03:40,213 INFO L130 BoogieDeclarations]: Found specification of procedure ldv_list_add_tail [2018-11-28 13:03:40,213 INFO L130 BoogieDeclarations]: Found specification of procedure ldv_list_del [2018-11-28 13:03:40,213 INFO L130 BoogieDeclarations]: Found specification of procedure ldv_msg_alloc [2018-11-28 13:03:40,213 INFO L130 BoogieDeclarations]: Found specification of procedure ldv_msg_fill [2018-11-28 13:03:40,214 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.C_memcpy [2018-11-28 13:03:40,214 INFO L130 BoogieDeclarations]: Found specification of procedure ldv_msg_free [2018-11-28 13:03:40,214 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.dealloc [2018-11-28 13:03:40,214 INFO L130 BoogieDeclarations]: Found specification of procedure ldv_submit_msg [2018-11-28 13:03:40,214 INFO L130 BoogieDeclarations]: Found specification of procedure ldv_destroy_msgs [2018-11-28 13:03:40,214 INFO L130 BoogieDeclarations]: Found specification of procedure ldv_dev_get_drvdata [2018-11-28 13:03:40,214 INFO L130 BoogieDeclarations]: Found specification of procedure ldv_dev_set_drvdata [2018-11-28 13:03:40,214 INFO L130 BoogieDeclarations]: Found specification of procedure ldv_atomic_add_return [2018-11-28 13:03:40,214 INFO L130 BoogieDeclarations]: Found specification of procedure read~intINTTYPE4 [2018-11-28 13:03:40,214 INFO L130 BoogieDeclarations]: Found specification of procedure write~intINTTYPE4 [2018-11-28 13:03:40,215 INFO L130 BoogieDeclarations]: Found specification of procedure ldv_atomic_sub_return [2018-11-28 13:03:40,215 INFO L130 BoogieDeclarations]: Found specification of procedure ldv_kref_sub [2018-11-28 13:03:40,215 INFO L130 BoogieDeclarations]: Found specification of procedure ##fun~$Pointer$~TO~VOID [2018-11-28 13:03:40,215 INFO L130 BoogieDeclarations]: Found specification of procedure ldv_kref_init [2018-11-28 13:03:40,215 INFO L130 BoogieDeclarations]: Found specification of procedure ldv_kref_get [2018-11-28 13:03:40,215 INFO L130 BoogieDeclarations]: Found specification of procedure ldv_kref_put [2018-11-28 13:03:40,215 INFO L130 BoogieDeclarations]: Found specification of procedure ldv_kobject_del [2018-11-28 13:03:40,215 INFO L130 BoogieDeclarations]: Found specification of procedure ldv_kobject_cleanup [2018-11-28 13:03:40,215 INFO L130 BoogieDeclarations]: Found specification of procedure ldv_kobject_release [2018-11-28 13:03:40,215 INFO L130 BoogieDeclarations]: Found specification of procedure ldv_kobject_put [2018-11-28 13:03:40,215 INFO L130 BoogieDeclarations]: Found specification of procedure ldv_kobject_get [2018-11-28 13:03:40,216 INFO L130 BoogieDeclarations]: Found specification of procedure ldv_kobject_init_internal [2018-11-28 13:03:40,216 INFO L130 BoogieDeclarations]: Found specification of procedure ldv_kobject_init [2018-11-28 13:03:40,216 INFO L130 BoogieDeclarations]: Found specification of procedure ldv_kobject_create [2018-11-28 13:03:40,216 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.C_memset [2018-11-28 13:03:40,216 INFO L130 BoogieDeclarations]: Found specification of procedure f [2018-11-28 13:03:40,216 INFO L130 BoogieDeclarations]: Found specification of procedure g [2018-11-28 13:03:40,216 INFO L130 BoogieDeclarations]: Found specification of procedure f_22_get [2018-11-28 13:03:40,216 INFO L130 BoogieDeclarations]: Found specification of procedure f_22_put [2018-11-28 13:03:40,216 INFO L130 BoogieDeclarations]: Found specification of procedure entry_point [2018-11-28 13:03:40,216 INFO L130 BoogieDeclarations]: Found specification of procedure main [2018-11-28 13:03:40,217 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.init [2018-11-28 13:03:40,217 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~$Pointer$ [2018-11-28 13:03:40,217 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2018-11-28 13:03:40,217 INFO L130 BoogieDeclarations]: Found specification of procedure write~unchecked~intINTTYPE4 [2018-11-28 13:03:40,217 INFO L130 BoogieDeclarations]: Found specification of procedure read~unchecked~intINTTYPE4 [2018-11-28 13:03:40,217 INFO L130 BoogieDeclarations]: Found specification of procedure write~unchecked~$Pointer$ [2018-11-28 13:03:40,217 INFO L130 BoogieDeclarations]: Found specification of procedure read~unchecked~$Pointer$ [2018-11-28 13:03:40,588 WARN L615 $ProcedureCfgBuilder]: Label in the middle of a codeblock. [2018-11-28 13:03:40,892 WARN L615 $ProcedureCfgBuilder]: Label in the middle of a codeblock. [2018-11-28 13:03:41,133 INFO L275 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2018-11-28 13:03:41,133 INFO L280 CfgBuilder]: Removed 1 assue(true) statements. [2018-11-28 13:03:41,134 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 28.11 01:03:41 BoogieIcfgContainer [2018-11-28 13:03:41,134 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2018-11-28 13:03:41,135 INFO L113 PluginConnector]: ------------------------TraceAbstraction---------------------------- [2018-11-28 13:03:41,135 INFO L271 PluginConnector]: Initializing TraceAbstraction... [2018-11-28 13:03:41,138 INFO L276 PluginConnector]: TraceAbstraction initialized [2018-11-28 13:03:41,138 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "CDTParser AST 28.11 01:03:39" (1/3) ... [2018-11-28 13:03:41,139 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@af26f16 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 28.11 01:03:41, skipping insertion in model container [2018-11-28 13:03:41,139 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 01:03:40" (2/3) ... [2018-11-28 13:03:41,139 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@af26f16 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 28.11 01:03:41, skipping insertion in model container [2018-11-28 13:03:41,139 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 28.11 01:03:41" (3/3) ... [2018-11-28 13:03:41,141 INFO L112 eAbstractionObserver]: Analyzing ICFG memleaks_test22_4_false-valid-memtrack_true-termination.i [2018-11-28 13:03:41,150 INFO L156 ceAbstractionStarter]: Automizer settings: Hoare:false NWA Interpolation:FPandBP Determinization: PREDICATE_ABSTRACTION [2018-11-28 13:03:41,158 INFO L168 ceAbstractionStarter]: Appying trace abstraction to program that has 67 error locations. [2018-11-28 13:03:41,172 INFO L257 AbstractCegarLoop]: Starting to check reachability of 67 error locations. [2018-11-28 13:03:41,195 INFO L133 ementStrategyFactory]: Using default assertion order modulation [2018-11-28 13:03:41,195 INFO L382 AbstractCegarLoop]: Interprodecural is true [2018-11-28 13:03:41,195 INFO L383 AbstractCegarLoop]: Hoare is false [2018-11-28 13:03:41,196 INFO L384 AbstractCegarLoop]: Compute interpolants for FPandBP [2018-11-28 13:03:41,196 INFO L385 AbstractCegarLoop]: Backedges is STRAIGHT_LINE [2018-11-28 13:03:41,196 INFO L386 AbstractCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2018-11-28 13:03:41,196 INFO L387 AbstractCegarLoop]: Difference is false [2018-11-28 13:03:41,196 INFO L388 AbstractCegarLoop]: Minimize is MINIMIZE_SEVPA [2018-11-28 13:03:41,196 INFO L393 AbstractCegarLoop]: ======== Iteration 0==of CEGAR loop == AllErrorsAtOnce======== [2018-11-28 13:03:41,214 INFO L276 IsEmpty]: Start isEmpty. Operand 176 states. [2018-11-28 13:03:41,222 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 18 [2018-11-28 13:03:41,222 INFO L394 BasicCegarLoop]: Found error trace [2018-11-28 13:03:41,223 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-28 13:03:41,226 INFO L423 AbstractCegarLoop]: === Iteration 1 === [ldv_kref_initErr0REQUIRES_VIOLATION, ldv_kref_initErr1REQUIRES_VIOLATION, ldv_list_addErr1REQUIRES_VIOLATION, ldv_list_addErr0REQUIRES_VIOLATION, ldv_kobject_createErr1REQUIRES_VIOLATION, ldv_kobject_createErr0REQUIRES_VIOLATION, ldv_destroy_msgsErr0REQUIRES_VIOLATION, ldv_destroy_msgsErr5REQUIRES_VIOLATION, ldv_destroy_msgsErr4REQUIRES_VIOLATION, ldv_destroy_msgsErr3REQUIRES_VIOLATION, ldv_destroy_msgsErr2REQUIRES_VIOLATION, ldv_destroy_msgsErr1REQUIRES_VIOLATION, ldv_msg_fillErr1REQUIRES_VIOLATION, ldv_msg_fillErr3REQUIRES_VIOLATION, ldv_msg_fillErr2REQUIRES_VIOLATION, ldv_msg_fillErr5REQUIRES_VIOLATION, ldv_msg_fillErr0REQUIRES_VIOLATION, ldv_msg_fillErr4REQUIRES_VIOLATION, ldv_atomic_add_returnErr3REQUIRES_VIOLATION, ldv_atomic_add_returnErr2REQUIRES_VIOLATION, ldv_atomic_add_returnErr1REQUIRES_VIOLATION, ldv_atomic_add_returnErr0REQUIRES_VIOLATION, __ldv_list_delErr1REQUIRES_VIOLATION, __ldv_list_delErr2REQUIRES_VIOLATION, __ldv_list_delErr3REQUIRES_VIOLATION, __ldv_list_delErr0REQUIRES_VIOLATION, ldv_kobject_cleanupErr0REQUIRES_VIOLATION, ldv_kobject_cleanupErr3ASSERT_VIOLATIONMEMORY_FREE, ldv_kobject_cleanupErr2ASSERT_VIOLATIONMEMORY_FREE, ldv_kobject_cleanupErr5ASSERT_VIOLATIONMEMORY_FREE, ldv_kobject_cleanupErr1REQUIRES_VIOLATION, ldv_kobject_cleanupErr4ASSERT_VIOLATIONMEMORY_FREE, ldv_msg_freeErr0REQUIRES_VIOLATION, ldv_msg_freeErr3ASSERT_VIOLATIONMEMORY_FREE, ldv_msg_freeErr2ASSERT_VIOLATIONMEMORY_FREE, ldv_msg_freeErr5ASSERT_VIOLATIONMEMORY_FREE, ldv_msg_freeErr4ASSERT_VIOLATIONMEMORY_FREE, ldv_msg_freeErr1REQUIRES_VIOLATION, mainErr0ENSURES_VIOLATIONMEMORY_LEAK, LDV_INIT_LIST_HEADErr3REQUIRES_VIOLATION, LDV_INIT_LIST_HEADErr2REQUIRES_VIOLATION, LDV_INIT_LIST_HEADErr1REQUIRES_VIOLATION, LDV_INIT_LIST_HEADErr0REQUIRES_VIOLATION, ldv_list_delErr3REQUIRES_VIOLATION, ldv_list_delErr2REQUIRES_VIOLATION, ldv_list_delErr1REQUIRES_VIOLATION, ldv_list_delErr0REQUIRES_VIOLATION, __ldv_list_addErr6REQUIRES_VIOLATION, __ldv_list_addErr1REQUIRES_VIOLATION, __ldv_list_addErr7REQUIRES_VIOLATION, __ldv_list_addErr2REQUIRES_VIOLATION, __ldv_list_addErr3REQUIRES_VIOLATION, __ldv_list_addErr4REQUIRES_VIOLATION, __ldv_list_addErr5REQUIRES_VIOLATION, __ldv_list_addErr0REQUIRES_VIOLATION, ldv_dev_set_drvdataErr1REQUIRES_VIOLATION, ldv_dev_set_drvdataErr0REQUIRES_VIOLATION, ldv_atomic_sub_returnErr3REQUIRES_VIOLATION, ldv_atomic_sub_returnErr2REQUIRES_VIOLATION, ldv_atomic_sub_returnErr1REQUIRES_VIOLATION, ldv_atomic_sub_returnErr0REQUIRES_VIOLATION, ldv_list_add_tailErr0REQUIRES_VIOLATION, ldv_list_add_tailErr1REQUIRES_VIOLATION, ldv_dev_get_drvdataErr1REQUIRES_VIOLATION, ldv_dev_get_drvdataErr0REQUIRES_VIOLATION, ldv_msg_allocErr0REQUIRES_VIOLATION, ldv_msg_allocErr1REQUIRES_VIOLATION]=== [2018-11-28 13:03:41,232 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-28 13:03:41,232 INFO L82 PathProgramCache]: Analyzing trace with hash 1631349868, now seen corresponding path program 1 times [2018-11-28 13:03:41,237 INFO L223 ckRefinementStrategy]: Switched to mode CVC4_FPBP [2018-11-28 13:03:41,237 INFO L69 tionRefinementEngine]: Using refinement strategy WolfRefinementStrategy No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_a5616418-4a25-482a-a0cb-6eefe8bc17e5/bin-2019/uautomizer/cvc4 Starting monitored process 2 with cvc4 --incremental --print-success --lang smt --rewrite-divk (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 2 with cvc4 --incremental --print-success --lang smt --rewrite-divk [2018-11-28 13:03:41,264 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-28 13:03:41,341 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-28 13:03:41,348 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-28 13:03:41,395 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 6 treesize of output 5 [2018-11-28 13:03:41,398 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-11-28 13:03:41,413 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-28 13:03:41,413 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 1 variables, input treesize:6, output treesize:5 [2018-11-28 13:03:41,450 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-28 13:03:41,450 INFO L312 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2018-11-28 13:03:41,458 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-28 13:03:41,458 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2018-11-28 13:03:41,461 INFO L459 AbstractCegarLoop]: Interpolant automaton has 5 states [2018-11-28 13:03:41,473 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-11-28 13:03:41,474 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-11-28 13:03:41,476 INFO L87 Difference]: Start difference. First operand 176 states. Second operand 5 states. [2018-11-28 13:03:41,732 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-28 13:03:41,732 INFO L93 Difference]: Finished difference Result 156 states and 167 transitions. [2018-11-28 13:03:41,735 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2018-11-28 13:03:41,736 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 17 [2018-11-28 13:03:41,736 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-28 13:03:41,746 INFO L225 Difference]: With dead ends: 156 [2018-11-28 13:03:41,746 INFO L226 Difference]: Without dead ends: 153 [2018-11-28 13:03:41,748 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 16 GetRequests, 13 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-11-28 13:03:41,759 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 153 states. [2018-11-28 13:03:41,779 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 153 to 147. [2018-11-28 13:03:41,780 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 147 states. [2018-11-28 13:03:41,783 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 147 states to 147 states and 158 transitions. [2018-11-28 13:03:41,784 INFO L78 Accepts]: Start accepts. Automaton has 147 states and 158 transitions. Word has length 17 [2018-11-28 13:03:41,784 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-28 13:03:41,784 INFO L480 AbstractCegarLoop]: Abstraction has 147 states and 158 transitions. [2018-11-28 13:03:41,784 INFO L481 AbstractCegarLoop]: Interpolant automaton has 5 states. [2018-11-28 13:03:41,784 INFO L276 IsEmpty]: Start isEmpty. Operand 147 states and 158 transitions. [2018-11-28 13:03:41,785 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 18 [2018-11-28 13:03:41,785 INFO L394 BasicCegarLoop]: Found error trace [2018-11-28 13:03:41,785 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-28 13:03:41,785 INFO L423 AbstractCegarLoop]: === Iteration 2 === [ldv_kref_initErr0REQUIRES_VIOLATION, ldv_kref_initErr1REQUIRES_VIOLATION, ldv_list_addErr1REQUIRES_VIOLATION, ldv_list_addErr0REQUIRES_VIOLATION, ldv_kobject_createErr1REQUIRES_VIOLATION, ldv_kobject_createErr0REQUIRES_VIOLATION, ldv_destroy_msgsErr0REQUIRES_VIOLATION, ldv_destroy_msgsErr5REQUIRES_VIOLATION, ldv_destroy_msgsErr4REQUIRES_VIOLATION, ldv_destroy_msgsErr3REQUIRES_VIOLATION, ldv_destroy_msgsErr2REQUIRES_VIOLATION, ldv_destroy_msgsErr1REQUIRES_VIOLATION, ldv_msg_fillErr1REQUIRES_VIOLATION, ldv_msg_fillErr3REQUIRES_VIOLATION, ldv_msg_fillErr2REQUIRES_VIOLATION, ldv_msg_fillErr5REQUIRES_VIOLATION, ldv_msg_fillErr0REQUIRES_VIOLATION, ldv_msg_fillErr4REQUIRES_VIOLATION, ldv_atomic_add_returnErr3REQUIRES_VIOLATION, ldv_atomic_add_returnErr2REQUIRES_VIOLATION, ldv_atomic_add_returnErr1REQUIRES_VIOLATION, ldv_atomic_add_returnErr0REQUIRES_VIOLATION, __ldv_list_delErr1REQUIRES_VIOLATION, __ldv_list_delErr2REQUIRES_VIOLATION, __ldv_list_delErr3REQUIRES_VIOLATION, __ldv_list_delErr0REQUIRES_VIOLATION, ldv_kobject_cleanupErr0REQUIRES_VIOLATION, ldv_kobject_cleanupErr3ASSERT_VIOLATIONMEMORY_FREE, ldv_kobject_cleanupErr2ASSERT_VIOLATIONMEMORY_FREE, ldv_kobject_cleanupErr5ASSERT_VIOLATIONMEMORY_FREE, ldv_kobject_cleanupErr1REQUIRES_VIOLATION, ldv_kobject_cleanupErr4ASSERT_VIOLATIONMEMORY_FREE, ldv_msg_freeErr0REQUIRES_VIOLATION, ldv_msg_freeErr3ASSERT_VIOLATIONMEMORY_FREE, ldv_msg_freeErr2ASSERT_VIOLATIONMEMORY_FREE, ldv_msg_freeErr5ASSERT_VIOLATIONMEMORY_FREE, ldv_msg_freeErr4ASSERT_VIOLATIONMEMORY_FREE, ldv_msg_freeErr1REQUIRES_VIOLATION, mainErr0ENSURES_VIOLATIONMEMORY_LEAK, LDV_INIT_LIST_HEADErr3REQUIRES_VIOLATION, LDV_INIT_LIST_HEADErr2REQUIRES_VIOLATION, LDV_INIT_LIST_HEADErr1REQUIRES_VIOLATION, LDV_INIT_LIST_HEADErr0REQUIRES_VIOLATION, ldv_list_delErr3REQUIRES_VIOLATION, ldv_list_delErr2REQUIRES_VIOLATION, ldv_list_delErr1REQUIRES_VIOLATION, ldv_list_delErr0REQUIRES_VIOLATION, __ldv_list_addErr6REQUIRES_VIOLATION, __ldv_list_addErr1REQUIRES_VIOLATION, __ldv_list_addErr7REQUIRES_VIOLATION, __ldv_list_addErr2REQUIRES_VIOLATION, __ldv_list_addErr3REQUIRES_VIOLATION, __ldv_list_addErr4REQUIRES_VIOLATION, __ldv_list_addErr5REQUIRES_VIOLATION, __ldv_list_addErr0REQUIRES_VIOLATION, ldv_dev_set_drvdataErr1REQUIRES_VIOLATION, ldv_dev_set_drvdataErr0REQUIRES_VIOLATION, ldv_atomic_sub_returnErr3REQUIRES_VIOLATION, ldv_atomic_sub_returnErr2REQUIRES_VIOLATION, ldv_atomic_sub_returnErr1REQUIRES_VIOLATION, ldv_atomic_sub_returnErr0REQUIRES_VIOLATION, ldv_list_add_tailErr0REQUIRES_VIOLATION, ldv_list_add_tailErr1REQUIRES_VIOLATION, ldv_dev_get_drvdataErr1REQUIRES_VIOLATION, ldv_dev_get_drvdataErr0REQUIRES_VIOLATION, ldv_msg_allocErr0REQUIRES_VIOLATION, ldv_msg_allocErr1REQUIRES_VIOLATION]=== [2018-11-28 13:03:41,785 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-28 13:03:41,785 INFO L82 PathProgramCache]: Analyzing trace with hash 1631349869, now seen corresponding path program 1 times [2018-11-28 13:03:41,786 INFO L223 ckRefinementStrategy]: Switched to mode CVC4_FPBP [2018-11-28 13:03:41,786 INFO L69 tionRefinementEngine]: Using refinement strategy WolfRefinementStrategy No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_a5616418-4a25-482a-a0cb-6eefe8bc17e5/bin-2019/uautomizer/cvc4 Starting monitored process 3 with cvc4 --incremental --print-success --lang smt --rewrite-divk (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 3 with cvc4 --incremental --print-success --lang smt --rewrite-divk [2018-11-28 13:03:41,804 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-28 13:03:41,847 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-28 13:03:41,849 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-28 13:03:41,866 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 6 treesize of output 5 [2018-11-28 13:03:41,867 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-11-28 13:03:41,872 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-28 13:03:41,872 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 1 variables, input treesize:10, output treesize:9 [2018-11-28 13:03:41,899 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-28 13:03:41,899 INFO L312 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2018-11-28 13:03:41,901 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-28 13:03:41,901 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-11-28 13:03:41,902 INFO L459 AbstractCegarLoop]: Interpolant automaton has 6 states [2018-11-28 13:03:41,902 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2018-11-28 13:03:41,903 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=21, Unknown=0, NotChecked=0, Total=30 [2018-11-28 13:03:41,903 INFO L87 Difference]: Start difference. First operand 147 states and 158 transitions. Second operand 6 states. [2018-11-28 13:03:42,141 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-28 13:03:42,142 INFO L93 Difference]: Finished difference Result 152 states and 163 transitions. [2018-11-28 13:03:42,142 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2018-11-28 13:03:42,143 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 17 [2018-11-28 13:03:42,143 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-28 13:03:42,145 INFO L225 Difference]: With dead ends: 152 [2018-11-28 13:03:42,145 INFO L226 Difference]: Without dead ends: 152 [2018-11-28 13:03:42,146 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 17 GetRequests, 12 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=13, Invalid=29, Unknown=0, NotChecked=0, Total=42 [2018-11-28 13:03:42,147 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 152 states. [2018-11-28 13:03:42,152 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 152 to 147. [2018-11-28 13:03:42,152 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 147 states. [2018-11-28 13:03:42,153 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 147 states to 147 states and 157 transitions. [2018-11-28 13:03:42,153 INFO L78 Accepts]: Start accepts. Automaton has 147 states and 157 transitions. Word has length 17 [2018-11-28 13:03:42,154 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-28 13:03:42,154 INFO L480 AbstractCegarLoop]: Abstraction has 147 states and 157 transitions. [2018-11-28 13:03:42,154 INFO L481 AbstractCegarLoop]: Interpolant automaton has 6 states. [2018-11-28 13:03:42,154 INFO L276 IsEmpty]: Start isEmpty. Operand 147 states and 157 transitions. [2018-11-28 13:03:42,154 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 18 [2018-11-28 13:03:42,154 INFO L394 BasicCegarLoop]: Found error trace [2018-11-28 13:03:42,154 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-28 13:03:42,155 INFO L423 AbstractCegarLoop]: === Iteration 3 === [ldv_kref_initErr0REQUIRES_VIOLATION, ldv_kref_initErr1REQUIRES_VIOLATION, ldv_list_addErr1REQUIRES_VIOLATION, ldv_list_addErr0REQUIRES_VIOLATION, ldv_kobject_createErr1REQUIRES_VIOLATION, ldv_kobject_createErr0REQUIRES_VIOLATION, ldv_destroy_msgsErr0REQUIRES_VIOLATION, ldv_destroy_msgsErr5REQUIRES_VIOLATION, ldv_destroy_msgsErr4REQUIRES_VIOLATION, ldv_destroy_msgsErr3REQUIRES_VIOLATION, ldv_destroy_msgsErr2REQUIRES_VIOLATION, ldv_destroy_msgsErr1REQUIRES_VIOLATION, ldv_msg_fillErr1REQUIRES_VIOLATION, ldv_msg_fillErr3REQUIRES_VIOLATION, ldv_msg_fillErr2REQUIRES_VIOLATION, ldv_msg_fillErr5REQUIRES_VIOLATION, ldv_msg_fillErr0REQUIRES_VIOLATION, ldv_msg_fillErr4REQUIRES_VIOLATION, ldv_atomic_add_returnErr3REQUIRES_VIOLATION, ldv_atomic_add_returnErr2REQUIRES_VIOLATION, ldv_atomic_add_returnErr1REQUIRES_VIOLATION, ldv_atomic_add_returnErr0REQUIRES_VIOLATION, __ldv_list_delErr1REQUIRES_VIOLATION, __ldv_list_delErr2REQUIRES_VIOLATION, __ldv_list_delErr3REQUIRES_VIOLATION, __ldv_list_delErr0REQUIRES_VIOLATION, ldv_kobject_cleanupErr0REQUIRES_VIOLATION, ldv_kobject_cleanupErr3ASSERT_VIOLATIONMEMORY_FREE, ldv_kobject_cleanupErr2ASSERT_VIOLATIONMEMORY_FREE, ldv_kobject_cleanupErr5ASSERT_VIOLATIONMEMORY_FREE, ldv_kobject_cleanupErr1REQUIRES_VIOLATION, ldv_kobject_cleanupErr4ASSERT_VIOLATIONMEMORY_FREE, ldv_msg_freeErr0REQUIRES_VIOLATION, ldv_msg_freeErr3ASSERT_VIOLATIONMEMORY_FREE, ldv_msg_freeErr2ASSERT_VIOLATIONMEMORY_FREE, ldv_msg_freeErr5ASSERT_VIOLATIONMEMORY_FREE, ldv_msg_freeErr4ASSERT_VIOLATIONMEMORY_FREE, ldv_msg_freeErr1REQUIRES_VIOLATION, mainErr0ENSURES_VIOLATIONMEMORY_LEAK, LDV_INIT_LIST_HEADErr3REQUIRES_VIOLATION, LDV_INIT_LIST_HEADErr2REQUIRES_VIOLATION, LDV_INIT_LIST_HEADErr1REQUIRES_VIOLATION, LDV_INIT_LIST_HEADErr0REQUIRES_VIOLATION, ldv_list_delErr3REQUIRES_VIOLATION, ldv_list_delErr2REQUIRES_VIOLATION, ldv_list_delErr1REQUIRES_VIOLATION, ldv_list_delErr0REQUIRES_VIOLATION, __ldv_list_addErr6REQUIRES_VIOLATION, __ldv_list_addErr1REQUIRES_VIOLATION, __ldv_list_addErr7REQUIRES_VIOLATION, __ldv_list_addErr2REQUIRES_VIOLATION, __ldv_list_addErr3REQUIRES_VIOLATION, __ldv_list_addErr4REQUIRES_VIOLATION, __ldv_list_addErr5REQUIRES_VIOLATION, __ldv_list_addErr0REQUIRES_VIOLATION, ldv_dev_set_drvdataErr1REQUIRES_VIOLATION, ldv_dev_set_drvdataErr0REQUIRES_VIOLATION, ldv_atomic_sub_returnErr3REQUIRES_VIOLATION, ldv_atomic_sub_returnErr2REQUIRES_VIOLATION, ldv_atomic_sub_returnErr1REQUIRES_VIOLATION, ldv_atomic_sub_returnErr0REQUIRES_VIOLATION, ldv_list_add_tailErr0REQUIRES_VIOLATION, ldv_list_add_tailErr1REQUIRES_VIOLATION, ldv_dev_get_drvdataErr1REQUIRES_VIOLATION, ldv_dev_get_drvdataErr0REQUIRES_VIOLATION, ldv_msg_allocErr0REQUIRES_VIOLATION, ldv_msg_allocErr1REQUIRES_VIOLATION]=== [2018-11-28 13:03:42,155 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-28 13:03:42,155 INFO L82 PathProgramCache]: Analyzing trace with hash 1659979019, now seen corresponding path program 1 times [2018-11-28 13:03:42,155 INFO L223 ckRefinementStrategy]: Switched to mode CVC4_FPBP [2018-11-28 13:03:42,155 INFO L69 tionRefinementEngine]: Using refinement strategy WolfRefinementStrategy No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_a5616418-4a25-482a-a0cb-6eefe8bc17e5/bin-2019/uautomizer/cvc4 Starting monitored process 4 with cvc4 --incremental --print-success --lang smt --rewrite-divk (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 4 with cvc4 --incremental --print-success --lang smt --rewrite-divk [2018-11-28 13:03:42,170 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-28 13:03:42,201 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-28 13:03:42,203 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-28 13:03:42,252 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-28 13:03:42,252 INFO L312 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2018-11-28 13:03:42,255 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-28 13:03:42,255 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-11-28 13:03:42,255 INFO L459 AbstractCegarLoop]: Interpolant automaton has 5 states [2018-11-28 13:03:42,255 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-11-28 13:03:42,256 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-11-28 13:03:42,256 INFO L87 Difference]: Start difference. First operand 147 states and 157 transitions. Second operand 5 states. [2018-11-28 13:03:42,281 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-28 13:03:42,281 INFO L93 Difference]: Finished difference Result 146 states and 154 transitions. [2018-11-28 13:03:42,281 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2018-11-28 13:03:42,282 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 17 [2018-11-28 13:03:42,282 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-28 13:03:42,283 INFO L225 Difference]: With dead ends: 146 [2018-11-28 13:03:42,283 INFO L226 Difference]: Without dead ends: 146 [2018-11-28 13:03:42,284 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 16 GetRequests, 13 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-11-28 13:03:42,284 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 146 states. [2018-11-28 13:03:42,294 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 146 to 144. [2018-11-28 13:03:42,296 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 144 states. [2018-11-28 13:03:42,297 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 144 states to 144 states and 152 transitions. [2018-11-28 13:03:42,297 INFO L78 Accepts]: Start accepts. Automaton has 144 states and 152 transitions. Word has length 17 [2018-11-28 13:03:42,297 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-28 13:03:42,297 INFO L480 AbstractCegarLoop]: Abstraction has 144 states and 152 transitions. [2018-11-28 13:03:42,297 INFO L481 AbstractCegarLoop]: Interpolant automaton has 5 states. [2018-11-28 13:03:42,298 INFO L276 IsEmpty]: Start isEmpty. Operand 144 states and 152 transitions. [2018-11-28 13:03:42,298 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 30 [2018-11-28 13:03:42,298 INFO L394 BasicCegarLoop]: Found error trace [2018-11-28 13:03:42,298 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-28 13:03:42,299 INFO L423 AbstractCegarLoop]: === Iteration 4 === [ldv_kref_initErr0REQUIRES_VIOLATION, ldv_kref_initErr1REQUIRES_VIOLATION, ldv_list_addErr1REQUIRES_VIOLATION, ldv_list_addErr0REQUIRES_VIOLATION, ldv_kobject_createErr1REQUIRES_VIOLATION, ldv_kobject_createErr0REQUIRES_VIOLATION, ldv_destroy_msgsErr0REQUIRES_VIOLATION, ldv_destroy_msgsErr5REQUIRES_VIOLATION, ldv_destroy_msgsErr4REQUIRES_VIOLATION, ldv_destroy_msgsErr3REQUIRES_VIOLATION, ldv_destroy_msgsErr2REQUIRES_VIOLATION, ldv_destroy_msgsErr1REQUIRES_VIOLATION, ldv_msg_fillErr1REQUIRES_VIOLATION, ldv_msg_fillErr3REQUIRES_VIOLATION, ldv_msg_fillErr2REQUIRES_VIOLATION, ldv_msg_fillErr5REQUIRES_VIOLATION, ldv_msg_fillErr0REQUIRES_VIOLATION, ldv_msg_fillErr4REQUIRES_VIOLATION, ldv_atomic_add_returnErr3REQUIRES_VIOLATION, ldv_atomic_add_returnErr2REQUIRES_VIOLATION, ldv_atomic_add_returnErr1REQUIRES_VIOLATION, ldv_atomic_add_returnErr0REQUIRES_VIOLATION, __ldv_list_delErr1REQUIRES_VIOLATION, __ldv_list_delErr2REQUIRES_VIOLATION, __ldv_list_delErr3REQUIRES_VIOLATION, __ldv_list_delErr0REQUIRES_VIOLATION, ldv_kobject_cleanupErr0REQUIRES_VIOLATION, ldv_kobject_cleanupErr3ASSERT_VIOLATIONMEMORY_FREE, ldv_kobject_cleanupErr2ASSERT_VIOLATIONMEMORY_FREE, ldv_kobject_cleanupErr5ASSERT_VIOLATIONMEMORY_FREE, ldv_kobject_cleanupErr1REQUIRES_VIOLATION, ldv_kobject_cleanupErr4ASSERT_VIOLATIONMEMORY_FREE, ldv_msg_freeErr0REQUIRES_VIOLATION, ldv_msg_freeErr3ASSERT_VIOLATIONMEMORY_FREE, ldv_msg_freeErr2ASSERT_VIOLATIONMEMORY_FREE, ldv_msg_freeErr5ASSERT_VIOLATIONMEMORY_FREE, ldv_msg_freeErr4ASSERT_VIOLATIONMEMORY_FREE, ldv_msg_freeErr1REQUIRES_VIOLATION, mainErr0ENSURES_VIOLATIONMEMORY_LEAK, LDV_INIT_LIST_HEADErr3REQUIRES_VIOLATION, LDV_INIT_LIST_HEADErr2REQUIRES_VIOLATION, LDV_INIT_LIST_HEADErr1REQUIRES_VIOLATION, LDV_INIT_LIST_HEADErr0REQUIRES_VIOLATION, ldv_list_delErr3REQUIRES_VIOLATION, ldv_list_delErr2REQUIRES_VIOLATION, ldv_list_delErr1REQUIRES_VIOLATION, ldv_list_delErr0REQUIRES_VIOLATION, __ldv_list_addErr6REQUIRES_VIOLATION, __ldv_list_addErr1REQUIRES_VIOLATION, __ldv_list_addErr7REQUIRES_VIOLATION, __ldv_list_addErr2REQUIRES_VIOLATION, __ldv_list_addErr3REQUIRES_VIOLATION, __ldv_list_addErr4REQUIRES_VIOLATION, __ldv_list_addErr5REQUIRES_VIOLATION, __ldv_list_addErr0REQUIRES_VIOLATION, ldv_dev_set_drvdataErr1REQUIRES_VIOLATION, ldv_dev_set_drvdataErr0REQUIRES_VIOLATION, ldv_atomic_sub_returnErr3REQUIRES_VIOLATION, ldv_atomic_sub_returnErr2REQUIRES_VIOLATION, ldv_atomic_sub_returnErr1REQUIRES_VIOLATION, ldv_atomic_sub_returnErr0REQUIRES_VIOLATION, ldv_list_add_tailErr0REQUIRES_VIOLATION, ldv_list_add_tailErr1REQUIRES_VIOLATION, ldv_dev_get_drvdataErr1REQUIRES_VIOLATION, ldv_dev_get_drvdataErr0REQUIRES_VIOLATION, ldv_msg_allocErr0REQUIRES_VIOLATION, ldv_msg_allocErr1REQUIRES_VIOLATION]=== [2018-11-28 13:03:42,299 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-28 13:03:42,299 INFO L82 PathProgramCache]: Analyzing trace with hash 581616962, now seen corresponding path program 1 times [2018-11-28 13:03:42,299 INFO L223 ckRefinementStrategy]: Switched to mode CVC4_FPBP [2018-11-28 13:03:42,300 INFO L69 tionRefinementEngine]: Using refinement strategy WolfRefinementStrategy No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_a5616418-4a25-482a-a0cb-6eefe8bc17e5/bin-2019/uautomizer/cvc4 Starting monitored process 5 with cvc4 --incremental --print-success --lang smt --rewrite-divk (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 5 with cvc4 --incremental --print-success --lang smt --rewrite-divk [2018-11-28 13:03:42,323 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-28 13:03:42,370 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-28 13:03:42,373 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-28 13:03:42,392 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-28 13:03:42,392 INFO L312 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [MP cvc4 --incremental --print-success --lang smt --rewrite-divk (5)] Exception during sending of exit command (exit): Broken pipe [2018-11-28 13:03:42,395 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-28 13:03:42,396 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-11-28 13:03:42,396 INFO L459 AbstractCegarLoop]: Interpolant automaton has 5 states [2018-11-28 13:03:42,396 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-11-28 13:03:42,396 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-11-28 13:03:42,396 INFO L87 Difference]: Start difference. First operand 144 states and 152 transitions. Second operand 5 states. [2018-11-28 13:03:42,449 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-28 13:03:42,449 INFO L93 Difference]: Finished difference Result 146 states and 153 transitions. [2018-11-28 13:03:42,450 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2018-11-28 13:03:42,450 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 29 [2018-11-28 13:03:42,450 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-28 13:03:42,451 INFO L225 Difference]: With dead ends: 146 [2018-11-28 13:03:42,451 INFO L226 Difference]: Without dead ends: 146 [2018-11-28 13:03:42,452 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 28 GetRequests, 25 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-11-28 13:03:42,452 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 146 states. [2018-11-28 13:03:42,458 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 146 to 144. [2018-11-28 13:03:42,458 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 144 states. [2018-11-28 13:03:42,459 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 144 states to 144 states and 151 transitions. [2018-11-28 13:03:42,459 INFO L78 Accepts]: Start accepts. Automaton has 144 states and 151 transitions. Word has length 29 [2018-11-28 13:03:42,460 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-28 13:03:42,460 INFO L480 AbstractCegarLoop]: Abstraction has 144 states and 151 transitions. [2018-11-28 13:03:42,460 INFO L481 AbstractCegarLoop]: Interpolant automaton has 5 states. [2018-11-28 13:03:42,460 INFO L276 IsEmpty]: Start isEmpty. Operand 144 states and 151 transitions. [2018-11-28 13:03:42,461 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 30 [2018-11-28 13:03:42,462 INFO L394 BasicCegarLoop]: Found error trace [2018-11-28 13:03:42,462 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-28 13:03:42,462 INFO L423 AbstractCegarLoop]: === Iteration 5 === [ldv_kref_initErr0REQUIRES_VIOLATION, ldv_kref_initErr1REQUIRES_VIOLATION, ldv_list_addErr1REQUIRES_VIOLATION, ldv_list_addErr0REQUIRES_VIOLATION, ldv_kobject_createErr1REQUIRES_VIOLATION, ldv_kobject_createErr0REQUIRES_VIOLATION, ldv_destroy_msgsErr0REQUIRES_VIOLATION, ldv_destroy_msgsErr5REQUIRES_VIOLATION, ldv_destroy_msgsErr4REQUIRES_VIOLATION, ldv_destroy_msgsErr3REQUIRES_VIOLATION, ldv_destroy_msgsErr2REQUIRES_VIOLATION, ldv_destroy_msgsErr1REQUIRES_VIOLATION, ldv_msg_fillErr1REQUIRES_VIOLATION, ldv_msg_fillErr3REQUIRES_VIOLATION, ldv_msg_fillErr2REQUIRES_VIOLATION, ldv_msg_fillErr5REQUIRES_VIOLATION, ldv_msg_fillErr0REQUIRES_VIOLATION, ldv_msg_fillErr4REQUIRES_VIOLATION, ldv_atomic_add_returnErr3REQUIRES_VIOLATION, ldv_atomic_add_returnErr2REQUIRES_VIOLATION, ldv_atomic_add_returnErr1REQUIRES_VIOLATION, ldv_atomic_add_returnErr0REQUIRES_VIOLATION, __ldv_list_delErr1REQUIRES_VIOLATION, __ldv_list_delErr2REQUIRES_VIOLATION, __ldv_list_delErr3REQUIRES_VIOLATION, __ldv_list_delErr0REQUIRES_VIOLATION, ldv_kobject_cleanupErr0REQUIRES_VIOLATION, ldv_kobject_cleanupErr3ASSERT_VIOLATIONMEMORY_FREE, ldv_kobject_cleanupErr2ASSERT_VIOLATIONMEMORY_FREE, ldv_kobject_cleanupErr5ASSERT_VIOLATIONMEMORY_FREE, ldv_kobject_cleanupErr1REQUIRES_VIOLATION, ldv_kobject_cleanupErr4ASSERT_VIOLATIONMEMORY_FREE, ldv_msg_freeErr0REQUIRES_VIOLATION, ldv_msg_freeErr3ASSERT_VIOLATIONMEMORY_FREE, ldv_msg_freeErr2ASSERT_VIOLATIONMEMORY_FREE, ldv_msg_freeErr5ASSERT_VIOLATIONMEMORY_FREE, ldv_msg_freeErr4ASSERT_VIOLATIONMEMORY_FREE, ldv_msg_freeErr1REQUIRES_VIOLATION, mainErr0ENSURES_VIOLATIONMEMORY_LEAK, LDV_INIT_LIST_HEADErr3REQUIRES_VIOLATION, LDV_INIT_LIST_HEADErr2REQUIRES_VIOLATION, LDV_INIT_LIST_HEADErr1REQUIRES_VIOLATION, LDV_INIT_LIST_HEADErr0REQUIRES_VIOLATION, ldv_list_delErr3REQUIRES_VIOLATION, ldv_list_delErr2REQUIRES_VIOLATION, ldv_list_delErr1REQUIRES_VIOLATION, ldv_list_delErr0REQUIRES_VIOLATION, __ldv_list_addErr6REQUIRES_VIOLATION, __ldv_list_addErr1REQUIRES_VIOLATION, __ldv_list_addErr7REQUIRES_VIOLATION, __ldv_list_addErr2REQUIRES_VIOLATION, __ldv_list_addErr3REQUIRES_VIOLATION, __ldv_list_addErr4REQUIRES_VIOLATION, __ldv_list_addErr5REQUIRES_VIOLATION, __ldv_list_addErr0REQUIRES_VIOLATION, ldv_dev_set_drvdataErr1REQUIRES_VIOLATION, ldv_dev_set_drvdataErr0REQUIRES_VIOLATION, ldv_atomic_sub_returnErr3REQUIRES_VIOLATION, ldv_atomic_sub_returnErr2REQUIRES_VIOLATION, ldv_atomic_sub_returnErr1REQUIRES_VIOLATION, ldv_atomic_sub_returnErr0REQUIRES_VIOLATION, ldv_list_add_tailErr0REQUIRES_VIOLATION, ldv_list_add_tailErr1REQUIRES_VIOLATION, ldv_dev_get_drvdataErr1REQUIRES_VIOLATION, ldv_dev_get_drvdataErr0REQUIRES_VIOLATION, ldv_msg_allocErr0REQUIRES_VIOLATION, ldv_msg_allocErr1REQUIRES_VIOLATION]=== [2018-11-28 13:03:42,462 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-28 13:03:42,462 INFO L82 PathProgramCache]: Analyzing trace with hash -415455391, now seen corresponding path program 1 times [2018-11-28 13:03:42,463 INFO L223 ckRefinementStrategy]: Switched to mode CVC4_FPBP [2018-11-28 13:03:42,463 INFO L69 tionRefinementEngine]: Using refinement strategy WolfRefinementStrategy No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_a5616418-4a25-482a-a0cb-6eefe8bc17e5/bin-2019/uautomizer/cvc4 Starting monitored process 6 with cvc4 --incremental --print-success --lang smt --rewrite-divk (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 6 with cvc4 --incremental --print-success --lang smt --rewrite-divk [2018-11-28 13:03:42,489 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-28 13:03:42,565 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-28 13:03:42,568 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-28 13:03:42,653 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-28 13:03:42,653 INFO L312 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2018-11-28 13:03:42,657 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-28 13:03:42,657 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [9] imperfect sequences [] total 9 [2018-11-28 13:03:42,657 INFO L459 AbstractCegarLoop]: Interpolant automaton has 9 states [2018-11-28 13:03:42,658 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 9 interpolants. [2018-11-28 13:03:42,658 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=15, Invalid=57, Unknown=0, NotChecked=0, Total=72 [2018-11-28 13:03:42,658 INFO L87 Difference]: Start difference. First operand 144 states and 151 transitions. Second operand 9 states. [2018-11-28 13:03:42,747 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-28 13:03:42,747 INFO L93 Difference]: Finished difference Result 164 states and 172 transitions. [2018-11-28 13:03:42,748 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 10 states. [2018-11-28 13:03:42,748 INFO L78 Accepts]: Start accepts. Automaton has 9 states. Word has length 29 [2018-11-28 13:03:42,748 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-28 13:03:42,749 INFO L225 Difference]: With dead ends: 164 [2018-11-28 13:03:42,750 INFO L226 Difference]: Without dead ends: 164 [2018-11-28 13:03:42,750 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 30 GetRequests, 21 SyntacticMatches, 0 SemanticMatches, 9 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=23, Invalid=87, Unknown=0, NotChecked=0, Total=110 [2018-11-28 13:03:42,750 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 164 states. [2018-11-28 13:03:42,757 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 164 to 158. [2018-11-28 13:03:42,758 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 158 states. [2018-11-28 13:03:42,758 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 158 states to 158 states and 165 transitions. [2018-11-28 13:03:42,759 INFO L78 Accepts]: Start accepts. Automaton has 158 states and 165 transitions. Word has length 29 [2018-11-28 13:03:42,759 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-28 13:03:42,759 INFO L480 AbstractCegarLoop]: Abstraction has 158 states and 165 transitions. [2018-11-28 13:03:42,759 INFO L481 AbstractCegarLoop]: Interpolant automaton has 9 states. [2018-11-28 13:03:42,759 INFO L276 IsEmpty]: Start isEmpty. Operand 158 states and 165 transitions. [2018-11-28 13:03:42,760 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 33 [2018-11-28 13:03:42,760 INFO L394 BasicCegarLoop]: Found error trace [2018-11-28 13:03:42,761 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-28 13:03:42,762 INFO L423 AbstractCegarLoop]: === Iteration 6 === [ldv_kref_initErr0REQUIRES_VIOLATION, ldv_kref_initErr1REQUIRES_VIOLATION, ldv_list_addErr1REQUIRES_VIOLATION, ldv_list_addErr0REQUIRES_VIOLATION, ldv_kobject_createErr1REQUIRES_VIOLATION, ldv_kobject_createErr0REQUIRES_VIOLATION, ldv_destroy_msgsErr0REQUIRES_VIOLATION, ldv_destroy_msgsErr5REQUIRES_VIOLATION, ldv_destroy_msgsErr4REQUIRES_VIOLATION, ldv_destroy_msgsErr3REQUIRES_VIOLATION, ldv_destroy_msgsErr2REQUIRES_VIOLATION, ldv_destroy_msgsErr1REQUIRES_VIOLATION, ldv_msg_fillErr1REQUIRES_VIOLATION, ldv_msg_fillErr3REQUIRES_VIOLATION, ldv_msg_fillErr2REQUIRES_VIOLATION, ldv_msg_fillErr5REQUIRES_VIOLATION, ldv_msg_fillErr0REQUIRES_VIOLATION, ldv_msg_fillErr4REQUIRES_VIOLATION, ldv_atomic_add_returnErr3REQUIRES_VIOLATION, ldv_atomic_add_returnErr2REQUIRES_VIOLATION, ldv_atomic_add_returnErr1REQUIRES_VIOLATION, ldv_atomic_add_returnErr0REQUIRES_VIOLATION, __ldv_list_delErr1REQUIRES_VIOLATION, __ldv_list_delErr2REQUIRES_VIOLATION, __ldv_list_delErr3REQUIRES_VIOLATION, __ldv_list_delErr0REQUIRES_VIOLATION, ldv_kobject_cleanupErr0REQUIRES_VIOLATION, ldv_kobject_cleanupErr3ASSERT_VIOLATIONMEMORY_FREE, ldv_kobject_cleanupErr2ASSERT_VIOLATIONMEMORY_FREE, ldv_kobject_cleanupErr5ASSERT_VIOLATIONMEMORY_FREE, ldv_kobject_cleanupErr1REQUIRES_VIOLATION, ldv_kobject_cleanupErr4ASSERT_VIOLATIONMEMORY_FREE, ldv_msg_freeErr0REQUIRES_VIOLATION, ldv_msg_freeErr3ASSERT_VIOLATIONMEMORY_FREE, ldv_msg_freeErr2ASSERT_VIOLATIONMEMORY_FREE, ldv_msg_freeErr5ASSERT_VIOLATIONMEMORY_FREE, ldv_msg_freeErr4ASSERT_VIOLATIONMEMORY_FREE, ldv_msg_freeErr1REQUIRES_VIOLATION, mainErr0ENSURES_VIOLATIONMEMORY_LEAK, LDV_INIT_LIST_HEADErr3REQUIRES_VIOLATION, LDV_INIT_LIST_HEADErr2REQUIRES_VIOLATION, LDV_INIT_LIST_HEADErr1REQUIRES_VIOLATION, LDV_INIT_LIST_HEADErr0REQUIRES_VIOLATION, ldv_list_delErr3REQUIRES_VIOLATION, ldv_list_delErr2REQUIRES_VIOLATION, ldv_list_delErr1REQUIRES_VIOLATION, ldv_list_delErr0REQUIRES_VIOLATION, __ldv_list_addErr6REQUIRES_VIOLATION, __ldv_list_addErr1REQUIRES_VIOLATION, __ldv_list_addErr7REQUIRES_VIOLATION, __ldv_list_addErr2REQUIRES_VIOLATION, __ldv_list_addErr3REQUIRES_VIOLATION, __ldv_list_addErr4REQUIRES_VIOLATION, __ldv_list_addErr5REQUIRES_VIOLATION, __ldv_list_addErr0REQUIRES_VIOLATION, ldv_dev_set_drvdataErr1REQUIRES_VIOLATION, ldv_dev_set_drvdataErr0REQUIRES_VIOLATION, ldv_atomic_sub_returnErr3REQUIRES_VIOLATION, ldv_atomic_sub_returnErr2REQUIRES_VIOLATION, ldv_atomic_sub_returnErr1REQUIRES_VIOLATION, ldv_atomic_sub_returnErr0REQUIRES_VIOLATION, ldv_list_add_tailErr0REQUIRES_VIOLATION, ldv_list_add_tailErr1REQUIRES_VIOLATION, ldv_dev_get_drvdataErr1REQUIRES_VIOLATION, ldv_dev_get_drvdataErr0REQUIRES_VIOLATION, ldv_msg_allocErr0REQUIRES_VIOLATION, ldv_msg_allocErr1REQUIRES_VIOLATION]=== [2018-11-28 13:03:42,762 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-28 13:03:42,762 INFO L82 PathProgramCache]: Analyzing trace with hash -639527829, now seen corresponding path program 1 times [2018-11-28 13:03:42,762 INFO L223 ckRefinementStrategy]: Switched to mode CVC4_FPBP [2018-11-28 13:03:42,762 INFO L69 tionRefinementEngine]: Using refinement strategy WolfRefinementStrategy No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_a5616418-4a25-482a-a0cb-6eefe8bc17e5/bin-2019/uautomizer/cvc4 Starting monitored process 7 with cvc4 --incremental --print-success --lang smt --rewrite-divk (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 7 with cvc4 --incremental --print-success --lang smt --rewrite-divk [2018-11-28 13:03:42,781 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-28 13:03:42,864 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-28 13:03:42,866 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-28 13:03:42,884 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-28 13:03:42,884 INFO L312 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2018-11-28 13:03:42,887 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-28 13:03:42,887 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2018-11-28 13:03:42,887 INFO L459 AbstractCegarLoop]: Interpolant automaton has 4 states [2018-11-28 13:03:42,887 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2018-11-28 13:03:42,887 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2018-11-28 13:03:42,888 INFO L87 Difference]: Start difference. First operand 158 states and 165 transitions. Second operand 4 states. [2018-11-28 13:03:42,915 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-28 13:03:42,915 INFO L93 Difference]: Finished difference Result 161 states and 168 transitions. [2018-11-28 13:03:42,915 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2018-11-28 13:03:42,915 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 32 [2018-11-28 13:03:42,916 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-28 13:03:42,916 INFO L225 Difference]: With dead ends: 161 [2018-11-28 13:03:42,916 INFO L226 Difference]: Without dead ends: 159 [2018-11-28 13:03:42,917 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 32 GetRequests, 29 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2018-11-28 13:03:42,917 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 159 states. [2018-11-28 13:03:42,921 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 159 to 159. [2018-11-28 13:03:42,921 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 159 states. [2018-11-28 13:03:42,922 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 159 states to 159 states and 166 transitions. [2018-11-28 13:03:42,922 INFO L78 Accepts]: Start accepts. Automaton has 159 states and 166 transitions. Word has length 32 [2018-11-28 13:03:42,922 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-28 13:03:42,923 INFO L480 AbstractCegarLoop]: Abstraction has 159 states and 166 transitions. [2018-11-28 13:03:42,923 INFO L481 AbstractCegarLoop]: Interpolant automaton has 4 states. [2018-11-28 13:03:42,923 INFO L276 IsEmpty]: Start isEmpty. Operand 159 states and 166 transitions. [2018-11-28 13:03:42,923 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 34 [2018-11-28 13:03:42,923 INFO L394 BasicCegarLoop]: Found error trace [2018-11-28 13:03:42,924 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-28 13:03:42,924 INFO L423 AbstractCegarLoop]: === Iteration 7 === [ldv_kref_initErr0REQUIRES_VIOLATION, ldv_kref_initErr1REQUIRES_VIOLATION, ldv_list_addErr1REQUIRES_VIOLATION, ldv_list_addErr0REQUIRES_VIOLATION, ldv_kobject_createErr1REQUIRES_VIOLATION, ldv_kobject_createErr0REQUIRES_VIOLATION, ldv_destroy_msgsErr0REQUIRES_VIOLATION, ldv_destroy_msgsErr5REQUIRES_VIOLATION, ldv_destroy_msgsErr4REQUIRES_VIOLATION, ldv_destroy_msgsErr3REQUIRES_VIOLATION, ldv_destroy_msgsErr2REQUIRES_VIOLATION, ldv_destroy_msgsErr1REQUIRES_VIOLATION, ldv_msg_fillErr1REQUIRES_VIOLATION, ldv_msg_fillErr3REQUIRES_VIOLATION, ldv_msg_fillErr2REQUIRES_VIOLATION, ldv_msg_fillErr5REQUIRES_VIOLATION, ldv_msg_fillErr0REQUIRES_VIOLATION, ldv_msg_fillErr4REQUIRES_VIOLATION, ldv_atomic_add_returnErr3REQUIRES_VIOLATION, ldv_atomic_add_returnErr2REQUIRES_VIOLATION, ldv_atomic_add_returnErr1REQUIRES_VIOLATION, ldv_atomic_add_returnErr0REQUIRES_VIOLATION, __ldv_list_delErr1REQUIRES_VIOLATION, __ldv_list_delErr2REQUIRES_VIOLATION, __ldv_list_delErr3REQUIRES_VIOLATION, __ldv_list_delErr0REQUIRES_VIOLATION, ldv_kobject_cleanupErr0REQUIRES_VIOLATION, ldv_kobject_cleanupErr3ASSERT_VIOLATIONMEMORY_FREE, ldv_kobject_cleanupErr2ASSERT_VIOLATIONMEMORY_FREE, ldv_kobject_cleanupErr5ASSERT_VIOLATIONMEMORY_FREE, ldv_kobject_cleanupErr1REQUIRES_VIOLATION, ldv_kobject_cleanupErr4ASSERT_VIOLATIONMEMORY_FREE, ldv_msg_freeErr0REQUIRES_VIOLATION, ldv_msg_freeErr3ASSERT_VIOLATIONMEMORY_FREE, ldv_msg_freeErr2ASSERT_VIOLATIONMEMORY_FREE, ldv_msg_freeErr5ASSERT_VIOLATIONMEMORY_FREE, ldv_msg_freeErr4ASSERT_VIOLATIONMEMORY_FREE, ldv_msg_freeErr1REQUIRES_VIOLATION, mainErr0ENSURES_VIOLATIONMEMORY_LEAK, LDV_INIT_LIST_HEADErr3REQUIRES_VIOLATION, LDV_INIT_LIST_HEADErr2REQUIRES_VIOLATION, LDV_INIT_LIST_HEADErr1REQUIRES_VIOLATION, LDV_INIT_LIST_HEADErr0REQUIRES_VIOLATION, ldv_list_delErr3REQUIRES_VIOLATION, ldv_list_delErr2REQUIRES_VIOLATION, ldv_list_delErr1REQUIRES_VIOLATION, ldv_list_delErr0REQUIRES_VIOLATION, __ldv_list_addErr6REQUIRES_VIOLATION, __ldv_list_addErr1REQUIRES_VIOLATION, __ldv_list_addErr7REQUIRES_VIOLATION, __ldv_list_addErr2REQUIRES_VIOLATION, __ldv_list_addErr3REQUIRES_VIOLATION, __ldv_list_addErr4REQUIRES_VIOLATION, __ldv_list_addErr5REQUIRES_VIOLATION, __ldv_list_addErr0REQUIRES_VIOLATION, ldv_dev_set_drvdataErr1REQUIRES_VIOLATION, ldv_dev_set_drvdataErr0REQUIRES_VIOLATION, ldv_atomic_sub_returnErr3REQUIRES_VIOLATION, ldv_atomic_sub_returnErr2REQUIRES_VIOLATION, ldv_atomic_sub_returnErr1REQUIRES_VIOLATION, ldv_atomic_sub_returnErr0REQUIRES_VIOLATION, ldv_list_add_tailErr0REQUIRES_VIOLATION, ldv_list_add_tailErr1REQUIRES_VIOLATION, ldv_dev_get_drvdataErr1REQUIRES_VIOLATION, ldv_dev_get_drvdataErr0REQUIRES_VIOLATION, ldv_msg_allocErr0REQUIRES_VIOLATION, ldv_msg_allocErr1REQUIRES_VIOLATION]=== [2018-11-28 13:03:42,924 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-28 13:03:42,924 INFO L82 PathProgramCache]: Analyzing trace with hash 600235342, now seen corresponding path program 1 times [2018-11-28 13:03:42,924 INFO L223 ckRefinementStrategy]: Switched to mode CVC4_FPBP [2018-11-28 13:03:42,924 INFO L69 tionRefinementEngine]: Using refinement strategy WolfRefinementStrategy No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_a5616418-4a25-482a-a0cb-6eefe8bc17e5/bin-2019/uautomizer/cvc4 Starting monitored process 8 with cvc4 --incremental --print-success --lang smt --rewrite-divk (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 8 with cvc4 --incremental --print-success --lang smt --rewrite-divk [2018-11-28 13:03:42,939 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-28 13:03:43,012 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-28 13:03:43,014 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-28 13:03:43,031 INFO L134 CoverageAnalysis]: Checked inductivity of 1 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-28 13:03:43,031 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-11-28 13:03:43,099 INFO L134 CoverageAnalysis]: Checked inductivity of 1 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-28 13:03:43,101 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-11-28 13:03:43,101 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [5, 5] total 8 [2018-11-28 13:03:43,102 INFO L459 AbstractCegarLoop]: Interpolant automaton has 8 states [2018-11-28 13:03:43,102 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 8 interpolants. [2018-11-28 13:03:43,102 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=22, Invalid=34, Unknown=0, NotChecked=0, Total=56 [2018-11-28 13:03:43,102 INFO L87 Difference]: Start difference. First operand 159 states and 166 transitions. Second operand 8 states. [2018-11-28 13:03:43,190 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-28 13:03:43,190 INFO L93 Difference]: Finished difference Result 166 states and 174 transitions. [2018-11-28 13:03:43,193 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 8 states. [2018-11-28 13:03:43,193 INFO L78 Accepts]: Start accepts. Automaton has 8 states. Word has length 33 [2018-11-28 13:03:43,193 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-28 13:03:43,194 INFO L225 Difference]: With dead ends: 166 [2018-11-28 13:03:43,194 INFO L226 Difference]: Without dead ends: 162 [2018-11-28 13:03:43,194 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 67 GetRequests, 58 SyntacticMatches, 1 SemanticMatches, 8 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=38, Invalid=52, Unknown=0, NotChecked=0, Total=90 [2018-11-28 13:03:43,195 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 162 states. [2018-11-28 13:03:43,199 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 162 to 162. [2018-11-28 13:03:43,199 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 162 states. [2018-11-28 13:03:43,200 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 162 states to 162 states and 169 transitions. [2018-11-28 13:03:43,200 INFO L78 Accepts]: Start accepts. Automaton has 162 states and 169 transitions. Word has length 33 [2018-11-28 13:03:43,201 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-28 13:03:43,201 INFO L480 AbstractCegarLoop]: Abstraction has 162 states and 169 transitions. [2018-11-28 13:03:43,201 INFO L481 AbstractCegarLoop]: Interpolant automaton has 8 states. [2018-11-28 13:03:43,201 INFO L276 IsEmpty]: Start isEmpty. Operand 162 states and 169 transitions. [2018-11-28 13:03:43,202 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 37 [2018-11-28 13:03:43,202 INFO L394 BasicCegarLoop]: Found error trace [2018-11-28 13:03:43,202 INFO L402 BasicCegarLoop]: trace histogram [4, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-28 13:03:43,202 INFO L423 AbstractCegarLoop]: === Iteration 8 === [ldv_kref_initErr0REQUIRES_VIOLATION, ldv_kref_initErr1REQUIRES_VIOLATION, ldv_list_addErr1REQUIRES_VIOLATION, ldv_list_addErr0REQUIRES_VIOLATION, ldv_kobject_createErr1REQUIRES_VIOLATION, ldv_kobject_createErr0REQUIRES_VIOLATION, ldv_destroy_msgsErr0REQUIRES_VIOLATION, ldv_destroy_msgsErr5REQUIRES_VIOLATION, ldv_destroy_msgsErr4REQUIRES_VIOLATION, ldv_destroy_msgsErr3REQUIRES_VIOLATION, ldv_destroy_msgsErr2REQUIRES_VIOLATION, ldv_destroy_msgsErr1REQUIRES_VIOLATION, ldv_msg_fillErr1REQUIRES_VIOLATION, ldv_msg_fillErr3REQUIRES_VIOLATION, ldv_msg_fillErr2REQUIRES_VIOLATION, ldv_msg_fillErr5REQUIRES_VIOLATION, ldv_msg_fillErr0REQUIRES_VIOLATION, ldv_msg_fillErr4REQUIRES_VIOLATION, ldv_atomic_add_returnErr3REQUIRES_VIOLATION, ldv_atomic_add_returnErr2REQUIRES_VIOLATION, ldv_atomic_add_returnErr1REQUIRES_VIOLATION, ldv_atomic_add_returnErr0REQUIRES_VIOLATION, __ldv_list_delErr1REQUIRES_VIOLATION, __ldv_list_delErr2REQUIRES_VIOLATION, __ldv_list_delErr3REQUIRES_VIOLATION, __ldv_list_delErr0REQUIRES_VIOLATION, ldv_kobject_cleanupErr0REQUIRES_VIOLATION, ldv_kobject_cleanupErr3ASSERT_VIOLATIONMEMORY_FREE, ldv_kobject_cleanupErr2ASSERT_VIOLATIONMEMORY_FREE, ldv_kobject_cleanupErr5ASSERT_VIOLATIONMEMORY_FREE, ldv_kobject_cleanupErr1REQUIRES_VIOLATION, ldv_kobject_cleanupErr4ASSERT_VIOLATIONMEMORY_FREE, ldv_msg_freeErr0REQUIRES_VIOLATION, ldv_msg_freeErr3ASSERT_VIOLATIONMEMORY_FREE, ldv_msg_freeErr2ASSERT_VIOLATIONMEMORY_FREE, ldv_msg_freeErr5ASSERT_VIOLATIONMEMORY_FREE, ldv_msg_freeErr4ASSERT_VIOLATIONMEMORY_FREE, ldv_msg_freeErr1REQUIRES_VIOLATION, mainErr0ENSURES_VIOLATIONMEMORY_LEAK, LDV_INIT_LIST_HEADErr3REQUIRES_VIOLATION, LDV_INIT_LIST_HEADErr2REQUIRES_VIOLATION, LDV_INIT_LIST_HEADErr1REQUIRES_VIOLATION, LDV_INIT_LIST_HEADErr0REQUIRES_VIOLATION, ldv_list_delErr3REQUIRES_VIOLATION, ldv_list_delErr2REQUIRES_VIOLATION, ldv_list_delErr1REQUIRES_VIOLATION, ldv_list_delErr0REQUIRES_VIOLATION, __ldv_list_addErr6REQUIRES_VIOLATION, __ldv_list_addErr1REQUIRES_VIOLATION, __ldv_list_addErr7REQUIRES_VIOLATION, __ldv_list_addErr2REQUIRES_VIOLATION, __ldv_list_addErr3REQUIRES_VIOLATION, __ldv_list_addErr4REQUIRES_VIOLATION, __ldv_list_addErr5REQUIRES_VIOLATION, __ldv_list_addErr0REQUIRES_VIOLATION, ldv_dev_set_drvdataErr1REQUIRES_VIOLATION, ldv_dev_set_drvdataErr0REQUIRES_VIOLATION, ldv_atomic_sub_returnErr3REQUIRES_VIOLATION, ldv_atomic_sub_returnErr2REQUIRES_VIOLATION, ldv_atomic_sub_returnErr1REQUIRES_VIOLATION, ldv_atomic_sub_returnErr0REQUIRES_VIOLATION, ldv_list_add_tailErr0REQUIRES_VIOLATION, ldv_list_add_tailErr1REQUIRES_VIOLATION, ldv_dev_get_drvdataErr1REQUIRES_VIOLATION, ldv_dev_get_drvdataErr0REQUIRES_VIOLATION, ldv_msg_allocErr0REQUIRES_VIOLATION, ldv_msg_allocErr1REQUIRES_VIOLATION]=== [2018-11-28 13:03:43,202 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-28 13:03:43,202 INFO L82 PathProgramCache]: Analyzing trace with hash -849464021, now seen corresponding path program 2 times [2018-11-28 13:03:43,203 INFO L223 ckRefinementStrategy]: Switched to mode CVC4_FPBP [2018-11-28 13:03:43,203 INFO L69 tionRefinementEngine]: Using refinement strategy WolfRefinementStrategy No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_a5616418-4a25-482a-a0cb-6eefe8bc17e5/bin-2019/uautomizer/cvc4 Starting monitored process 9 with cvc4 --incremental --print-success --lang smt --rewrite-divk (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 9 with cvc4 --incremental --print-success --lang smt --rewrite-divk [2018-11-28 13:03:43,221 INFO L101 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2018-11-28 13:03:43,281 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) [2018-11-28 13:03:43,282 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-11-28 13:03:43,284 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-28 13:03:43,287 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 6 treesize of output 5 [2018-11-28 13:03:43,287 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-11-28 13:03:43,288 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-28 13:03:43,289 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 1 variables, input treesize:6, output treesize:5 [2018-11-28 13:03:43,391 INFO L134 CoverageAnalysis]: Checked inductivity of 10 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 10 trivial. 0 not checked. [2018-11-28 13:03:43,391 INFO L312 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2018-11-28 13:03:43,401 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-28 13:03:43,401 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [12] imperfect sequences [] total 12 [2018-11-28 13:03:43,401 INFO L459 AbstractCegarLoop]: Interpolant automaton has 13 states [2018-11-28 13:03:43,402 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 13 interpolants. [2018-11-28 13:03:43,402 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=33, Invalid=123, Unknown=0, NotChecked=0, Total=156 [2018-11-28 13:03:43,402 INFO L87 Difference]: Start difference. First operand 162 states and 169 transitions. Second operand 13 states. [2018-11-28 13:03:44,279 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-28 13:03:44,279 INFO L93 Difference]: Finished difference Result 173 states and 179 transitions. [2018-11-28 13:03:44,279 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 13 states. [2018-11-28 13:03:44,280 INFO L78 Accepts]: Start accepts. Automaton has 13 states. Word has length 36 [2018-11-28 13:03:44,280 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-28 13:03:44,280 INFO L225 Difference]: With dead ends: 173 [2018-11-28 13:03:44,281 INFO L226 Difference]: Without dead ends: 173 [2018-11-28 13:03:44,281 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 38 GetRequests, 23 SyntacticMatches, 1 SemanticMatches, 14 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 12 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=48, Invalid=192, Unknown=0, NotChecked=0, Total=240 [2018-11-28 13:03:44,281 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 173 states. [2018-11-28 13:03:44,284 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 173 to 161. [2018-11-28 13:03:44,284 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 161 states. [2018-11-28 13:03:44,285 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 161 states to 161 states and 168 transitions. [2018-11-28 13:03:44,285 INFO L78 Accepts]: Start accepts. Automaton has 161 states and 168 transitions. Word has length 36 [2018-11-28 13:03:44,285 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-28 13:03:44,285 INFO L480 AbstractCegarLoop]: Abstraction has 161 states and 168 transitions. [2018-11-28 13:03:44,285 INFO L481 AbstractCegarLoop]: Interpolant automaton has 13 states. [2018-11-28 13:03:44,285 INFO L276 IsEmpty]: Start isEmpty. Operand 161 states and 168 transitions. [2018-11-28 13:03:44,286 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 37 [2018-11-28 13:03:44,286 INFO L394 BasicCegarLoop]: Found error trace [2018-11-28 13:03:44,286 INFO L402 BasicCegarLoop]: trace histogram [4, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-28 13:03:44,287 INFO L423 AbstractCegarLoop]: === Iteration 9 === [ldv_kref_initErr0REQUIRES_VIOLATION, ldv_kref_initErr1REQUIRES_VIOLATION, ldv_list_addErr1REQUIRES_VIOLATION, ldv_list_addErr0REQUIRES_VIOLATION, ldv_kobject_createErr1REQUIRES_VIOLATION, ldv_kobject_createErr0REQUIRES_VIOLATION, ldv_destroy_msgsErr0REQUIRES_VIOLATION, ldv_destroy_msgsErr5REQUIRES_VIOLATION, ldv_destroy_msgsErr4REQUIRES_VIOLATION, ldv_destroy_msgsErr3REQUIRES_VIOLATION, ldv_destroy_msgsErr2REQUIRES_VIOLATION, ldv_destroy_msgsErr1REQUIRES_VIOLATION, ldv_msg_fillErr1REQUIRES_VIOLATION, ldv_msg_fillErr3REQUIRES_VIOLATION, ldv_msg_fillErr2REQUIRES_VIOLATION, ldv_msg_fillErr5REQUIRES_VIOLATION, ldv_msg_fillErr0REQUIRES_VIOLATION, ldv_msg_fillErr4REQUIRES_VIOLATION, ldv_atomic_add_returnErr3REQUIRES_VIOLATION, ldv_atomic_add_returnErr2REQUIRES_VIOLATION, ldv_atomic_add_returnErr1REQUIRES_VIOLATION, ldv_atomic_add_returnErr0REQUIRES_VIOLATION, __ldv_list_delErr1REQUIRES_VIOLATION, __ldv_list_delErr2REQUIRES_VIOLATION, __ldv_list_delErr3REQUIRES_VIOLATION, __ldv_list_delErr0REQUIRES_VIOLATION, ldv_kobject_cleanupErr0REQUIRES_VIOLATION, ldv_kobject_cleanupErr3ASSERT_VIOLATIONMEMORY_FREE, ldv_kobject_cleanupErr2ASSERT_VIOLATIONMEMORY_FREE, ldv_kobject_cleanupErr5ASSERT_VIOLATIONMEMORY_FREE, ldv_kobject_cleanupErr1REQUIRES_VIOLATION, ldv_kobject_cleanupErr4ASSERT_VIOLATIONMEMORY_FREE, ldv_msg_freeErr0REQUIRES_VIOLATION, ldv_msg_freeErr3ASSERT_VIOLATIONMEMORY_FREE, ldv_msg_freeErr2ASSERT_VIOLATIONMEMORY_FREE, ldv_msg_freeErr5ASSERT_VIOLATIONMEMORY_FREE, ldv_msg_freeErr4ASSERT_VIOLATIONMEMORY_FREE, ldv_msg_freeErr1REQUIRES_VIOLATION, mainErr0ENSURES_VIOLATIONMEMORY_LEAK, LDV_INIT_LIST_HEADErr3REQUIRES_VIOLATION, LDV_INIT_LIST_HEADErr2REQUIRES_VIOLATION, LDV_INIT_LIST_HEADErr1REQUIRES_VIOLATION, LDV_INIT_LIST_HEADErr0REQUIRES_VIOLATION, ldv_list_delErr3REQUIRES_VIOLATION, ldv_list_delErr2REQUIRES_VIOLATION, ldv_list_delErr1REQUIRES_VIOLATION, ldv_list_delErr0REQUIRES_VIOLATION, __ldv_list_addErr6REQUIRES_VIOLATION, __ldv_list_addErr1REQUIRES_VIOLATION, __ldv_list_addErr7REQUIRES_VIOLATION, __ldv_list_addErr2REQUIRES_VIOLATION, __ldv_list_addErr3REQUIRES_VIOLATION, __ldv_list_addErr4REQUIRES_VIOLATION, __ldv_list_addErr5REQUIRES_VIOLATION, __ldv_list_addErr0REQUIRES_VIOLATION, ldv_dev_set_drvdataErr1REQUIRES_VIOLATION, ldv_dev_set_drvdataErr0REQUIRES_VIOLATION, ldv_atomic_sub_returnErr3REQUIRES_VIOLATION, ldv_atomic_sub_returnErr2REQUIRES_VIOLATION, ldv_atomic_sub_returnErr1REQUIRES_VIOLATION, ldv_atomic_sub_returnErr0REQUIRES_VIOLATION, ldv_list_add_tailErr0REQUIRES_VIOLATION, ldv_list_add_tailErr1REQUIRES_VIOLATION, ldv_dev_get_drvdataErr1REQUIRES_VIOLATION, ldv_dev_get_drvdataErr0REQUIRES_VIOLATION, ldv_msg_allocErr0REQUIRES_VIOLATION, ldv_msg_allocErr1REQUIRES_VIOLATION]=== [2018-11-28 13:03:44,287 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-28 13:03:44,287 INFO L82 PathProgramCache]: Analyzing trace with hash -849464020, now seen corresponding path program 1 times [2018-11-28 13:03:44,287 INFO L223 ckRefinementStrategy]: Switched to mode CVC4_FPBP [2018-11-28 13:03:44,288 INFO L69 tionRefinementEngine]: Using refinement strategy WolfRefinementStrategy No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_a5616418-4a25-482a-a0cb-6eefe8bc17e5/bin-2019/uautomizer/cvc4 Starting monitored process 10 with cvc4 --incremental --print-success --lang smt --rewrite-divk (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 10 with cvc4 --incremental --print-success --lang smt --rewrite-divk [2018-11-28 13:03:44,304 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-28 13:03:44,375 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-28 13:03:44,378 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-28 13:03:44,405 INFO L134 CoverageAnalysis]: Checked inductivity of 10 backedges. 0 proven. 10 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-28 13:03:44,405 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-11-28 13:03:44,526 INFO L134 CoverageAnalysis]: Checked inductivity of 10 backedges. 0 proven. 10 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-28 13:03:44,528 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-11-28 13:03:44,528 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [8, 8] total 14 [2018-11-28 13:03:44,529 INFO L459 AbstractCegarLoop]: Interpolant automaton has 14 states [2018-11-28 13:03:44,529 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 14 interpolants. [2018-11-28 13:03:44,529 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=61, Invalid=121, Unknown=0, NotChecked=0, Total=182 [2018-11-28 13:03:44,529 INFO L87 Difference]: Start difference. First operand 161 states and 168 transitions. Second operand 14 states. [2018-11-28 13:03:45,018 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-28 13:03:45,018 INFO L93 Difference]: Finished difference Result 171 states and 182 transitions. [2018-11-28 13:03:45,019 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 14 states. [2018-11-28 13:03:45,019 INFO L78 Accepts]: Start accepts. Automaton has 14 states. Word has length 36 [2018-11-28 13:03:45,019 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-28 13:03:45,020 INFO L225 Difference]: With dead ends: 171 [2018-11-28 13:03:45,020 INFO L226 Difference]: Without dead ends: 167 [2018-11-28 13:03:45,020 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 76 GetRequests, 58 SyntacticMatches, 1 SemanticMatches, 17 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 12 ImplicationChecksByTransitivity, 0.3s TimeCoverageRelationStatistics Valid=131, Invalid=211, Unknown=0, NotChecked=0, Total=342 [2018-11-28 13:03:45,021 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 167 states. [2018-11-28 13:03:45,024 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 167 to 167. [2018-11-28 13:03:45,025 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 167 states. [2018-11-28 13:03:45,026 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 167 states to 167 states and 174 transitions. [2018-11-28 13:03:45,026 INFO L78 Accepts]: Start accepts. Automaton has 167 states and 174 transitions. Word has length 36 [2018-11-28 13:03:45,027 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-28 13:03:45,027 INFO L480 AbstractCegarLoop]: Abstraction has 167 states and 174 transitions. [2018-11-28 13:03:45,027 INFO L481 AbstractCegarLoop]: Interpolant automaton has 14 states. [2018-11-28 13:03:45,027 INFO L276 IsEmpty]: Start isEmpty. Operand 167 states and 174 transitions. [2018-11-28 13:03:45,027 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 41 [2018-11-28 13:03:45,028 INFO L394 BasicCegarLoop]: Found error trace [2018-11-28 13:03:45,028 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-28 13:03:45,028 INFO L423 AbstractCegarLoop]: === Iteration 10 === [ldv_kref_initErr0REQUIRES_VIOLATION, ldv_kref_initErr1REQUIRES_VIOLATION, ldv_list_addErr1REQUIRES_VIOLATION, ldv_list_addErr0REQUIRES_VIOLATION, ldv_kobject_createErr1REQUIRES_VIOLATION, ldv_kobject_createErr0REQUIRES_VIOLATION, ldv_destroy_msgsErr0REQUIRES_VIOLATION, ldv_destroy_msgsErr5REQUIRES_VIOLATION, ldv_destroy_msgsErr4REQUIRES_VIOLATION, ldv_destroy_msgsErr3REQUIRES_VIOLATION, ldv_destroy_msgsErr2REQUIRES_VIOLATION, ldv_destroy_msgsErr1REQUIRES_VIOLATION, ldv_msg_fillErr1REQUIRES_VIOLATION, ldv_msg_fillErr3REQUIRES_VIOLATION, ldv_msg_fillErr2REQUIRES_VIOLATION, ldv_msg_fillErr5REQUIRES_VIOLATION, ldv_msg_fillErr0REQUIRES_VIOLATION, ldv_msg_fillErr4REQUIRES_VIOLATION, ldv_atomic_add_returnErr3REQUIRES_VIOLATION, ldv_atomic_add_returnErr2REQUIRES_VIOLATION, ldv_atomic_add_returnErr1REQUIRES_VIOLATION, ldv_atomic_add_returnErr0REQUIRES_VIOLATION, __ldv_list_delErr1REQUIRES_VIOLATION, __ldv_list_delErr2REQUIRES_VIOLATION, __ldv_list_delErr3REQUIRES_VIOLATION, __ldv_list_delErr0REQUIRES_VIOLATION, ldv_kobject_cleanupErr0REQUIRES_VIOLATION, ldv_kobject_cleanupErr3ASSERT_VIOLATIONMEMORY_FREE, ldv_kobject_cleanupErr2ASSERT_VIOLATIONMEMORY_FREE, ldv_kobject_cleanupErr5ASSERT_VIOLATIONMEMORY_FREE, ldv_kobject_cleanupErr1REQUIRES_VIOLATION, ldv_kobject_cleanupErr4ASSERT_VIOLATIONMEMORY_FREE, ldv_msg_freeErr0REQUIRES_VIOLATION, ldv_msg_freeErr3ASSERT_VIOLATIONMEMORY_FREE, ldv_msg_freeErr2ASSERT_VIOLATIONMEMORY_FREE, ldv_msg_freeErr5ASSERT_VIOLATIONMEMORY_FREE, ldv_msg_freeErr4ASSERT_VIOLATIONMEMORY_FREE, ldv_msg_freeErr1REQUIRES_VIOLATION, mainErr0ENSURES_VIOLATIONMEMORY_LEAK, LDV_INIT_LIST_HEADErr3REQUIRES_VIOLATION, LDV_INIT_LIST_HEADErr2REQUIRES_VIOLATION, LDV_INIT_LIST_HEADErr1REQUIRES_VIOLATION, LDV_INIT_LIST_HEADErr0REQUIRES_VIOLATION, ldv_list_delErr3REQUIRES_VIOLATION, ldv_list_delErr2REQUIRES_VIOLATION, ldv_list_delErr1REQUIRES_VIOLATION, ldv_list_delErr0REQUIRES_VIOLATION, __ldv_list_addErr6REQUIRES_VIOLATION, __ldv_list_addErr1REQUIRES_VIOLATION, __ldv_list_addErr7REQUIRES_VIOLATION, __ldv_list_addErr2REQUIRES_VIOLATION, __ldv_list_addErr3REQUIRES_VIOLATION, __ldv_list_addErr4REQUIRES_VIOLATION, __ldv_list_addErr5REQUIRES_VIOLATION, __ldv_list_addErr0REQUIRES_VIOLATION, ldv_dev_set_drvdataErr1REQUIRES_VIOLATION, ldv_dev_set_drvdataErr0REQUIRES_VIOLATION, ldv_atomic_sub_returnErr3REQUIRES_VIOLATION, ldv_atomic_sub_returnErr2REQUIRES_VIOLATION, ldv_atomic_sub_returnErr1REQUIRES_VIOLATION, ldv_atomic_sub_returnErr0REQUIRES_VIOLATION, ldv_list_add_tailErr0REQUIRES_VIOLATION, ldv_list_add_tailErr1REQUIRES_VIOLATION, ldv_dev_get_drvdataErr1REQUIRES_VIOLATION, ldv_dev_get_drvdataErr0REQUIRES_VIOLATION, ldv_msg_allocErr0REQUIRES_VIOLATION, ldv_msg_allocErr1REQUIRES_VIOLATION]=== [2018-11-28 13:03:45,028 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-28 13:03:45,028 INFO L82 PathProgramCache]: Analyzing trace with hash -872830515, now seen corresponding path program 1 times [2018-11-28 13:03:45,028 INFO L223 ckRefinementStrategy]: Switched to mode CVC4_FPBP [2018-11-28 13:03:45,029 INFO L69 tionRefinementEngine]: Using refinement strategy WolfRefinementStrategy No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_a5616418-4a25-482a-a0cb-6eefe8bc17e5/bin-2019/uautomizer/cvc4 Starting monitored process 11 with cvc4 --incremental --print-success --lang smt --rewrite-divk (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 11 with cvc4 --incremental --print-success --lang smt --rewrite-divk [2018-11-28 13:03:45,045 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-28 13:03:45,111 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-28 13:03:45,114 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-28 13:03:45,152 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-28 13:03:45,153 INFO L312 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2018-11-28 13:03:45,154 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-28 13:03:45,155 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [7] imperfect sequences [] total 7 [2018-11-28 13:03:45,155 INFO L459 AbstractCegarLoop]: Interpolant automaton has 7 states [2018-11-28 13:03:45,155 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2018-11-28 13:03:45,155 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=11, Invalid=31, Unknown=0, NotChecked=0, Total=42 [2018-11-28 13:03:45,155 INFO L87 Difference]: Start difference. First operand 167 states and 174 transitions. Second operand 7 states. [2018-11-28 13:03:45,188 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-28 13:03:45,188 INFO L93 Difference]: Finished difference Result 176 states and 183 transitions. [2018-11-28 13:03:45,188 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 8 states. [2018-11-28 13:03:45,188 INFO L78 Accepts]: Start accepts. Automaton has 7 states. Word has length 40 [2018-11-28 13:03:45,188 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-28 13:03:45,189 INFO L225 Difference]: With dead ends: 176 [2018-11-28 13:03:45,189 INFO L226 Difference]: Without dead ends: 176 [2018-11-28 13:03:45,189 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 40 GetRequests, 34 SyntacticMatches, 0 SemanticMatches, 6 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=15, Invalid=41, Unknown=0, NotChecked=0, Total=56 [2018-11-28 13:03:45,190 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 176 states. [2018-11-28 13:03:45,192 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 176 to 172. [2018-11-28 13:03:45,192 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 172 states. [2018-11-28 13:03:45,193 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 172 states to 172 states and 179 transitions. [2018-11-28 13:03:45,193 INFO L78 Accepts]: Start accepts. Automaton has 172 states and 179 transitions. Word has length 40 [2018-11-28 13:03:45,193 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-28 13:03:45,194 INFO L480 AbstractCegarLoop]: Abstraction has 172 states and 179 transitions. [2018-11-28 13:03:45,194 INFO L481 AbstractCegarLoop]: Interpolant automaton has 7 states. [2018-11-28 13:03:45,194 INFO L276 IsEmpty]: Start isEmpty. Operand 172 states and 179 transitions. [2018-11-28 13:03:45,194 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 39 [2018-11-28 13:03:45,194 INFO L394 BasicCegarLoop]: Found error trace [2018-11-28 13:03:45,194 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-28 13:03:45,195 INFO L423 AbstractCegarLoop]: === Iteration 11 === [ldv_kref_initErr0REQUIRES_VIOLATION, ldv_kref_initErr1REQUIRES_VIOLATION, ldv_list_addErr1REQUIRES_VIOLATION, ldv_list_addErr0REQUIRES_VIOLATION, ldv_kobject_createErr1REQUIRES_VIOLATION, ldv_kobject_createErr0REQUIRES_VIOLATION, ldv_destroy_msgsErr0REQUIRES_VIOLATION, ldv_destroy_msgsErr5REQUIRES_VIOLATION, ldv_destroy_msgsErr4REQUIRES_VIOLATION, ldv_destroy_msgsErr3REQUIRES_VIOLATION, ldv_destroy_msgsErr2REQUIRES_VIOLATION, ldv_destroy_msgsErr1REQUIRES_VIOLATION, ldv_msg_fillErr1REQUIRES_VIOLATION, ldv_msg_fillErr3REQUIRES_VIOLATION, ldv_msg_fillErr2REQUIRES_VIOLATION, ldv_msg_fillErr5REQUIRES_VIOLATION, ldv_msg_fillErr0REQUIRES_VIOLATION, ldv_msg_fillErr4REQUIRES_VIOLATION, ldv_atomic_add_returnErr3REQUIRES_VIOLATION, ldv_atomic_add_returnErr2REQUIRES_VIOLATION, ldv_atomic_add_returnErr1REQUIRES_VIOLATION, ldv_atomic_add_returnErr0REQUIRES_VIOLATION, __ldv_list_delErr1REQUIRES_VIOLATION, __ldv_list_delErr2REQUIRES_VIOLATION, __ldv_list_delErr3REQUIRES_VIOLATION, __ldv_list_delErr0REQUIRES_VIOLATION, ldv_kobject_cleanupErr0REQUIRES_VIOLATION, ldv_kobject_cleanupErr3ASSERT_VIOLATIONMEMORY_FREE, ldv_kobject_cleanupErr2ASSERT_VIOLATIONMEMORY_FREE, ldv_kobject_cleanupErr5ASSERT_VIOLATIONMEMORY_FREE, ldv_kobject_cleanupErr1REQUIRES_VIOLATION, ldv_kobject_cleanupErr4ASSERT_VIOLATIONMEMORY_FREE, ldv_msg_freeErr0REQUIRES_VIOLATION, ldv_msg_freeErr3ASSERT_VIOLATIONMEMORY_FREE, ldv_msg_freeErr2ASSERT_VIOLATIONMEMORY_FREE, ldv_msg_freeErr5ASSERT_VIOLATIONMEMORY_FREE, ldv_msg_freeErr4ASSERT_VIOLATIONMEMORY_FREE, ldv_msg_freeErr1REQUIRES_VIOLATION, mainErr0ENSURES_VIOLATIONMEMORY_LEAK, LDV_INIT_LIST_HEADErr3REQUIRES_VIOLATION, LDV_INIT_LIST_HEADErr2REQUIRES_VIOLATION, LDV_INIT_LIST_HEADErr1REQUIRES_VIOLATION, LDV_INIT_LIST_HEADErr0REQUIRES_VIOLATION, ldv_list_delErr3REQUIRES_VIOLATION, ldv_list_delErr2REQUIRES_VIOLATION, ldv_list_delErr1REQUIRES_VIOLATION, ldv_list_delErr0REQUIRES_VIOLATION, __ldv_list_addErr6REQUIRES_VIOLATION, __ldv_list_addErr1REQUIRES_VIOLATION, __ldv_list_addErr7REQUIRES_VIOLATION, __ldv_list_addErr2REQUIRES_VIOLATION, __ldv_list_addErr3REQUIRES_VIOLATION, __ldv_list_addErr4REQUIRES_VIOLATION, __ldv_list_addErr5REQUIRES_VIOLATION, __ldv_list_addErr0REQUIRES_VIOLATION, ldv_dev_set_drvdataErr1REQUIRES_VIOLATION, ldv_dev_set_drvdataErr0REQUIRES_VIOLATION, ldv_atomic_sub_returnErr3REQUIRES_VIOLATION, ldv_atomic_sub_returnErr2REQUIRES_VIOLATION, ldv_atomic_sub_returnErr1REQUIRES_VIOLATION, ldv_atomic_sub_returnErr0REQUIRES_VIOLATION, ldv_list_add_tailErr0REQUIRES_VIOLATION, ldv_list_add_tailErr1REQUIRES_VIOLATION, ldv_dev_get_drvdataErr1REQUIRES_VIOLATION, ldv_dev_get_drvdataErr0REQUIRES_VIOLATION, ldv_msg_allocErr0REQUIRES_VIOLATION, ldv_msg_allocErr1REQUIRES_VIOLATION]=== [2018-11-28 13:03:45,195 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-28 13:03:45,195 INFO L82 PathProgramCache]: Analyzing trace with hash 1431338402, now seen corresponding path program 1 times [2018-11-28 13:03:45,195 INFO L223 ckRefinementStrategy]: Switched to mode CVC4_FPBP [2018-11-28 13:03:45,195 INFO L69 tionRefinementEngine]: Using refinement strategy WolfRefinementStrategy No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_a5616418-4a25-482a-a0cb-6eefe8bc17e5/bin-2019/uautomizer/cvc4 Starting monitored process 12 with cvc4 --incremental --print-success --lang smt --rewrite-divk (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 12 with cvc4 --incremental --print-success --lang smt --rewrite-divk [2018-11-28 13:03:45,214 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-28 13:03:45,237 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-28 13:03:45,239 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-28 13:03:45,243 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-28 13:03:45,244 INFO L312 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2018-11-28 13:03:45,245 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-28 13:03:45,245 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2018-11-28 13:03:45,245 INFO L459 AbstractCegarLoop]: Interpolant automaton has 3 states [2018-11-28 13:03:45,245 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-28 13:03:45,246 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-28 13:03:45,246 INFO L87 Difference]: Start difference. First operand 172 states and 179 transitions. Second operand 3 states. [2018-11-28 13:03:45,356 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-28 13:03:45,356 INFO L93 Difference]: Finished difference Result 183 states and 189 transitions. [2018-11-28 13:03:45,357 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-28 13:03:45,357 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 38 [2018-11-28 13:03:45,357 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-28 13:03:45,358 INFO L225 Difference]: With dead ends: 183 [2018-11-28 13:03:45,358 INFO L226 Difference]: Without dead ends: 157 [2018-11-28 13:03:45,358 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 37 GetRequests, 36 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-28 13:03:45,359 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 157 states. [2018-11-28 13:03:45,361 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 157 to 149. [2018-11-28 13:03:45,361 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 149 states. [2018-11-28 13:03:45,362 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 149 states to 149 states and 155 transitions. [2018-11-28 13:03:45,362 INFO L78 Accepts]: Start accepts. Automaton has 149 states and 155 transitions. Word has length 38 [2018-11-28 13:03:45,362 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-28 13:03:45,362 INFO L480 AbstractCegarLoop]: Abstraction has 149 states and 155 transitions. [2018-11-28 13:03:45,362 INFO L481 AbstractCegarLoop]: Interpolant automaton has 3 states. [2018-11-28 13:03:45,362 INFO L276 IsEmpty]: Start isEmpty. Operand 149 states and 155 transitions. [2018-11-28 13:03:45,363 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 43 [2018-11-28 13:03:45,363 INFO L394 BasicCegarLoop]: Found error trace [2018-11-28 13:03:45,363 INFO L402 BasicCegarLoop]: trace histogram [10, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-28 13:03:45,364 INFO L423 AbstractCegarLoop]: === Iteration 12 === [ldv_kref_initErr0REQUIRES_VIOLATION, ldv_kref_initErr1REQUIRES_VIOLATION, ldv_list_addErr1REQUIRES_VIOLATION, ldv_list_addErr0REQUIRES_VIOLATION, ldv_kobject_createErr1REQUIRES_VIOLATION, ldv_kobject_createErr0REQUIRES_VIOLATION, ldv_destroy_msgsErr0REQUIRES_VIOLATION, ldv_destroy_msgsErr5REQUIRES_VIOLATION, ldv_destroy_msgsErr4REQUIRES_VIOLATION, ldv_destroy_msgsErr3REQUIRES_VIOLATION, ldv_destroy_msgsErr2REQUIRES_VIOLATION, ldv_destroy_msgsErr1REQUIRES_VIOLATION, ldv_msg_fillErr1REQUIRES_VIOLATION, ldv_msg_fillErr3REQUIRES_VIOLATION, ldv_msg_fillErr2REQUIRES_VIOLATION, ldv_msg_fillErr5REQUIRES_VIOLATION, ldv_msg_fillErr0REQUIRES_VIOLATION, ldv_msg_fillErr4REQUIRES_VIOLATION, ldv_atomic_add_returnErr3REQUIRES_VIOLATION, ldv_atomic_add_returnErr2REQUIRES_VIOLATION, ldv_atomic_add_returnErr1REQUIRES_VIOLATION, ldv_atomic_add_returnErr0REQUIRES_VIOLATION, __ldv_list_delErr1REQUIRES_VIOLATION, __ldv_list_delErr2REQUIRES_VIOLATION, __ldv_list_delErr3REQUIRES_VIOLATION, __ldv_list_delErr0REQUIRES_VIOLATION, ldv_kobject_cleanupErr0REQUIRES_VIOLATION, ldv_kobject_cleanupErr3ASSERT_VIOLATIONMEMORY_FREE, ldv_kobject_cleanupErr2ASSERT_VIOLATIONMEMORY_FREE, ldv_kobject_cleanupErr5ASSERT_VIOLATIONMEMORY_FREE, ldv_kobject_cleanupErr1REQUIRES_VIOLATION, ldv_kobject_cleanupErr4ASSERT_VIOLATIONMEMORY_FREE, ldv_msg_freeErr0REQUIRES_VIOLATION, ldv_msg_freeErr3ASSERT_VIOLATIONMEMORY_FREE, ldv_msg_freeErr2ASSERT_VIOLATIONMEMORY_FREE, ldv_msg_freeErr5ASSERT_VIOLATIONMEMORY_FREE, ldv_msg_freeErr4ASSERT_VIOLATIONMEMORY_FREE, ldv_msg_freeErr1REQUIRES_VIOLATION, mainErr0ENSURES_VIOLATIONMEMORY_LEAK, LDV_INIT_LIST_HEADErr3REQUIRES_VIOLATION, LDV_INIT_LIST_HEADErr2REQUIRES_VIOLATION, LDV_INIT_LIST_HEADErr1REQUIRES_VIOLATION, LDV_INIT_LIST_HEADErr0REQUIRES_VIOLATION, ldv_list_delErr3REQUIRES_VIOLATION, ldv_list_delErr2REQUIRES_VIOLATION, ldv_list_delErr1REQUIRES_VIOLATION, ldv_list_delErr0REQUIRES_VIOLATION, __ldv_list_addErr6REQUIRES_VIOLATION, __ldv_list_addErr1REQUIRES_VIOLATION, __ldv_list_addErr7REQUIRES_VIOLATION, __ldv_list_addErr2REQUIRES_VIOLATION, __ldv_list_addErr3REQUIRES_VIOLATION, __ldv_list_addErr4REQUIRES_VIOLATION, __ldv_list_addErr5REQUIRES_VIOLATION, __ldv_list_addErr0REQUIRES_VIOLATION, ldv_dev_set_drvdataErr1REQUIRES_VIOLATION, ldv_dev_set_drvdataErr0REQUIRES_VIOLATION, ldv_atomic_sub_returnErr3REQUIRES_VIOLATION, ldv_atomic_sub_returnErr2REQUIRES_VIOLATION, ldv_atomic_sub_returnErr1REQUIRES_VIOLATION, ldv_atomic_sub_returnErr0REQUIRES_VIOLATION, ldv_list_add_tailErr0REQUIRES_VIOLATION, ldv_list_add_tailErr1REQUIRES_VIOLATION, ldv_dev_get_drvdataErr1REQUIRES_VIOLATION, ldv_dev_get_drvdataErr0REQUIRES_VIOLATION, ldv_msg_allocErr0REQUIRES_VIOLATION, ldv_msg_allocErr1REQUIRES_VIOLATION]=== [2018-11-28 13:03:45,364 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-28 13:03:45,364 INFO L82 PathProgramCache]: Analyzing trace with hash 361968204, now seen corresponding path program 2 times [2018-11-28 13:03:45,368 INFO L223 ckRefinementStrategy]: Switched to mode CVC4_FPBP [2018-11-28 13:03:45,368 INFO L69 tionRefinementEngine]: Using refinement strategy WolfRefinementStrategy No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_a5616418-4a25-482a-a0cb-6eefe8bc17e5/bin-2019/uautomizer/cvc4 Starting monitored process 13 with cvc4 --incremental --print-success --lang smt --rewrite-divk (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 13 with cvc4 --incremental --print-success --lang smt --rewrite-divk [2018-11-28 13:03:45,387 INFO L101 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2018-11-28 13:03:45,445 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) [2018-11-28 13:03:45,445 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-11-28 13:03:45,448 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-28 13:03:45,459 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 6 treesize of output 5 [2018-11-28 13:03:45,460 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-11-28 13:03:45,464 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-28 13:03:45,464 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 1 variables, input treesize:10, output treesize:9 [2018-11-28 13:03:45,641 INFO L134 CoverageAnalysis]: Checked inductivity of 55 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 55 trivial. 0 not checked. [2018-11-28 13:03:45,641 INFO L312 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2018-11-28 13:03:45,644 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-28 13:03:45,644 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [12] imperfect sequences [] total 12 [2018-11-28 13:03:45,644 INFO L459 AbstractCegarLoop]: Interpolant automaton has 13 states [2018-11-28 13:03:45,644 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 13 interpolants. [2018-11-28 13:03:45,644 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=31, Invalid=125, Unknown=0, NotChecked=0, Total=156 [2018-11-28 13:03:45,645 INFO L87 Difference]: Start difference. First operand 149 states and 155 transitions. Second operand 13 states. [2018-11-28 13:03:46,522 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-28 13:03:46,523 INFO L93 Difference]: Finished difference Result 148 states and 154 transitions. [2018-11-28 13:03:46,523 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 13 states. [2018-11-28 13:03:46,523 INFO L78 Accepts]: Start accepts. Automaton has 13 states. Word has length 42 [2018-11-28 13:03:46,523 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-28 13:03:46,524 INFO L225 Difference]: With dead ends: 148 [2018-11-28 13:03:46,524 INFO L226 Difference]: Without dead ends: 148 [2018-11-28 13:03:46,524 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 45 GetRequests, 29 SyntacticMatches, 1 SemanticMatches, 15 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 20 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=50, Invalid=222, Unknown=0, NotChecked=0, Total=272 [2018-11-28 13:03:46,524 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 148 states. [2018-11-28 13:03:46,526 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 148 to 148. [2018-11-28 13:03:46,526 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 148 states. [2018-11-28 13:03:46,527 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 148 states to 148 states and 154 transitions. [2018-11-28 13:03:46,527 INFO L78 Accepts]: Start accepts. Automaton has 148 states and 154 transitions. Word has length 42 [2018-11-28 13:03:46,527 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-28 13:03:46,527 INFO L480 AbstractCegarLoop]: Abstraction has 148 states and 154 transitions. [2018-11-28 13:03:46,527 INFO L481 AbstractCegarLoop]: Interpolant automaton has 13 states. [2018-11-28 13:03:46,527 INFO L276 IsEmpty]: Start isEmpty. Operand 148 states and 154 transitions. [2018-11-28 13:03:46,528 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 48 [2018-11-28 13:03:46,528 INFO L394 BasicCegarLoop]: Found error trace [2018-11-28 13:03:46,529 INFO L402 BasicCegarLoop]: trace histogram [10, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-28 13:03:46,530 INFO L423 AbstractCegarLoop]: === Iteration 13 === [ldv_kref_initErr0REQUIRES_VIOLATION, ldv_kref_initErr1REQUIRES_VIOLATION, ldv_list_addErr1REQUIRES_VIOLATION, ldv_list_addErr0REQUIRES_VIOLATION, ldv_kobject_createErr1REQUIRES_VIOLATION, ldv_kobject_createErr0REQUIRES_VIOLATION, ldv_destroy_msgsErr0REQUIRES_VIOLATION, ldv_destroy_msgsErr5REQUIRES_VIOLATION, ldv_destroy_msgsErr4REQUIRES_VIOLATION, ldv_destroy_msgsErr3REQUIRES_VIOLATION, ldv_destroy_msgsErr2REQUIRES_VIOLATION, ldv_destroy_msgsErr1REQUIRES_VIOLATION, ldv_msg_fillErr1REQUIRES_VIOLATION, ldv_msg_fillErr3REQUIRES_VIOLATION, ldv_msg_fillErr2REQUIRES_VIOLATION, ldv_msg_fillErr5REQUIRES_VIOLATION, ldv_msg_fillErr0REQUIRES_VIOLATION, ldv_msg_fillErr4REQUIRES_VIOLATION, ldv_atomic_add_returnErr3REQUIRES_VIOLATION, ldv_atomic_add_returnErr2REQUIRES_VIOLATION, ldv_atomic_add_returnErr1REQUIRES_VIOLATION, ldv_atomic_add_returnErr0REQUIRES_VIOLATION, __ldv_list_delErr1REQUIRES_VIOLATION, __ldv_list_delErr2REQUIRES_VIOLATION, __ldv_list_delErr3REQUIRES_VIOLATION, __ldv_list_delErr0REQUIRES_VIOLATION, ldv_kobject_cleanupErr0REQUIRES_VIOLATION, ldv_kobject_cleanupErr3ASSERT_VIOLATIONMEMORY_FREE, ldv_kobject_cleanupErr2ASSERT_VIOLATIONMEMORY_FREE, ldv_kobject_cleanupErr5ASSERT_VIOLATIONMEMORY_FREE, ldv_kobject_cleanupErr1REQUIRES_VIOLATION, ldv_kobject_cleanupErr4ASSERT_VIOLATIONMEMORY_FREE, ldv_msg_freeErr0REQUIRES_VIOLATION, ldv_msg_freeErr3ASSERT_VIOLATIONMEMORY_FREE, ldv_msg_freeErr2ASSERT_VIOLATIONMEMORY_FREE, ldv_msg_freeErr5ASSERT_VIOLATIONMEMORY_FREE, ldv_msg_freeErr4ASSERT_VIOLATIONMEMORY_FREE, ldv_msg_freeErr1REQUIRES_VIOLATION, mainErr0ENSURES_VIOLATIONMEMORY_LEAK, LDV_INIT_LIST_HEADErr3REQUIRES_VIOLATION, LDV_INIT_LIST_HEADErr2REQUIRES_VIOLATION, LDV_INIT_LIST_HEADErr1REQUIRES_VIOLATION, LDV_INIT_LIST_HEADErr0REQUIRES_VIOLATION, ldv_list_delErr3REQUIRES_VIOLATION, ldv_list_delErr2REQUIRES_VIOLATION, ldv_list_delErr1REQUIRES_VIOLATION, ldv_list_delErr0REQUIRES_VIOLATION, __ldv_list_addErr6REQUIRES_VIOLATION, __ldv_list_addErr1REQUIRES_VIOLATION, __ldv_list_addErr7REQUIRES_VIOLATION, __ldv_list_addErr2REQUIRES_VIOLATION, __ldv_list_addErr3REQUIRES_VIOLATION, __ldv_list_addErr4REQUIRES_VIOLATION, __ldv_list_addErr5REQUIRES_VIOLATION, __ldv_list_addErr0REQUIRES_VIOLATION, ldv_dev_set_drvdataErr1REQUIRES_VIOLATION, ldv_dev_set_drvdataErr0REQUIRES_VIOLATION, ldv_atomic_sub_returnErr3REQUIRES_VIOLATION, ldv_atomic_sub_returnErr2REQUIRES_VIOLATION, ldv_atomic_sub_returnErr1REQUIRES_VIOLATION, ldv_atomic_sub_returnErr0REQUIRES_VIOLATION, ldv_list_add_tailErr0REQUIRES_VIOLATION, ldv_list_add_tailErr1REQUIRES_VIOLATION, ldv_dev_get_drvdataErr1REQUIRES_VIOLATION, ldv_dev_get_drvdataErr0REQUIRES_VIOLATION, ldv_msg_allocErr0REQUIRES_VIOLATION, ldv_msg_allocErr1REQUIRES_VIOLATION]=== [2018-11-28 13:03:46,530 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-28 13:03:46,530 INFO L82 PathProgramCache]: Analyzing trace with hash 1098993020, now seen corresponding path program 1 times [2018-11-28 13:03:46,530 INFO L223 ckRefinementStrategy]: Switched to mode CVC4_FPBP [2018-11-28 13:03:46,530 INFO L69 tionRefinementEngine]: Using refinement strategy WolfRefinementStrategy No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_a5616418-4a25-482a-a0cb-6eefe8bc17e5/bin-2019/uautomizer/cvc4 Starting monitored process 14 with cvc4 --incremental --print-success --lang smt --rewrite-divk (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 14 with cvc4 --incremental --print-success --lang smt --rewrite-divk [2018-11-28 13:03:46,546 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-28 13:03:46,652 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-28 13:03:46,655 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-28 13:03:46,737 INFO L134 CoverageAnalysis]: Checked inductivity of 55 backedges. 0 proven. 55 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-28 13:03:46,737 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-11-28 13:03:47,134 INFO L134 CoverageAnalysis]: Checked inductivity of 55 backedges. 0 proven. 55 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-28 13:03:47,136 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-11-28 13:03:47,137 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [14, 14] total 26 [2018-11-28 13:03:47,137 INFO L459 AbstractCegarLoop]: Interpolant automaton has 26 states [2018-11-28 13:03:47,137 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 26 interpolants. [2018-11-28 13:03:47,137 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=178, Invalid=472, Unknown=0, NotChecked=0, Total=650 [2018-11-28 13:03:47,138 INFO L87 Difference]: Start difference. First operand 148 states and 154 transitions. Second operand 26 states. [2018-11-28 13:03:48,136 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-28 13:03:48,136 INFO L93 Difference]: Finished difference Result 158 states and 168 transitions. [2018-11-28 13:03:48,137 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 20 states. [2018-11-28 13:03:48,137 INFO L78 Accepts]: Start accepts. Automaton has 26 states. Word has length 47 [2018-11-28 13:03:48,137 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-28 13:03:48,138 INFO L225 Difference]: With dead ends: 158 [2018-11-28 13:03:48,138 INFO L226 Difference]: Without dead ends: 154 [2018-11-28 13:03:48,138 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 98 GetRequests, 68 SyntacticMatches, 1 SemanticMatches, 29 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 52 ImplicationChecksByTransitivity, 0.7s TimeCoverageRelationStatistics Valid=278, Invalid=652, Unknown=0, NotChecked=0, Total=930 [2018-11-28 13:03:48,139 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 154 states. [2018-11-28 13:03:48,140 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 154 to 154. [2018-11-28 13:03:48,140 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 154 states. [2018-11-28 13:03:48,141 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 154 states to 154 states and 160 transitions. [2018-11-28 13:03:48,141 INFO L78 Accepts]: Start accepts. Automaton has 154 states and 160 transitions. Word has length 47 [2018-11-28 13:03:48,141 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-28 13:03:48,141 INFO L480 AbstractCegarLoop]: Abstraction has 154 states and 160 transitions. [2018-11-28 13:03:48,141 INFO L481 AbstractCegarLoop]: Interpolant automaton has 26 states. [2018-11-28 13:03:48,141 INFO L276 IsEmpty]: Start isEmpty. Operand 154 states and 160 transitions. [2018-11-28 13:03:48,142 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 54 [2018-11-28 13:03:48,142 INFO L394 BasicCegarLoop]: Found error trace [2018-11-28 13:03:48,142 INFO L402 BasicCegarLoop]: trace histogram [16, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-28 13:03:48,142 INFO L423 AbstractCegarLoop]: === Iteration 14 === [ldv_kref_initErr0REQUIRES_VIOLATION, ldv_kref_initErr1REQUIRES_VIOLATION, ldv_list_addErr1REQUIRES_VIOLATION, ldv_list_addErr0REQUIRES_VIOLATION, ldv_kobject_createErr1REQUIRES_VIOLATION, ldv_kobject_createErr0REQUIRES_VIOLATION, ldv_destroy_msgsErr0REQUIRES_VIOLATION, ldv_destroy_msgsErr5REQUIRES_VIOLATION, ldv_destroy_msgsErr4REQUIRES_VIOLATION, ldv_destroy_msgsErr3REQUIRES_VIOLATION, ldv_destroy_msgsErr2REQUIRES_VIOLATION, ldv_destroy_msgsErr1REQUIRES_VIOLATION, ldv_msg_fillErr1REQUIRES_VIOLATION, ldv_msg_fillErr3REQUIRES_VIOLATION, ldv_msg_fillErr2REQUIRES_VIOLATION, ldv_msg_fillErr5REQUIRES_VIOLATION, ldv_msg_fillErr0REQUIRES_VIOLATION, ldv_msg_fillErr4REQUIRES_VIOLATION, ldv_atomic_add_returnErr3REQUIRES_VIOLATION, ldv_atomic_add_returnErr2REQUIRES_VIOLATION, ldv_atomic_add_returnErr1REQUIRES_VIOLATION, ldv_atomic_add_returnErr0REQUIRES_VIOLATION, __ldv_list_delErr1REQUIRES_VIOLATION, __ldv_list_delErr2REQUIRES_VIOLATION, __ldv_list_delErr3REQUIRES_VIOLATION, __ldv_list_delErr0REQUIRES_VIOLATION, ldv_kobject_cleanupErr0REQUIRES_VIOLATION, ldv_kobject_cleanupErr3ASSERT_VIOLATIONMEMORY_FREE, ldv_kobject_cleanupErr2ASSERT_VIOLATIONMEMORY_FREE, ldv_kobject_cleanupErr5ASSERT_VIOLATIONMEMORY_FREE, ldv_kobject_cleanupErr1REQUIRES_VIOLATION, ldv_kobject_cleanupErr4ASSERT_VIOLATIONMEMORY_FREE, ldv_msg_freeErr0REQUIRES_VIOLATION, ldv_msg_freeErr3ASSERT_VIOLATIONMEMORY_FREE, ldv_msg_freeErr2ASSERT_VIOLATIONMEMORY_FREE, ldv_msg_freeErr5ASSERT_VIOLATIONMEMORY_FREE, ldv_msg_freeErr4ASSERT_VIOLATIONMEMORY_FREE, ldv_msg_freeErr1REQUIRES_VIOLATION, mainErr0ENSURES_VIOLATIONMEMORY_LEAK, LDV_INIT_LIST_HEADErr3REQUIRES_VIOLATION, LDV_INIT_LIST_HEADErr2REQUIRES_VIOLATION, LDV_INIT_LIST_HEADErr1REQUIRES_VIOLATION, LDV_INIT_LIST_HEADErr0REQUIRES_VIOLATION, ldv_list_delErr3REQUIRES_VIOLATION, ldv_list_delErr2REQUIRES_VIOLATION, ldv_list_delErr1REQUIRES_VIOLATION, ldv_list_delErr0REQUIRES_VIOLATION, __ldv_list_addErr6REQUIRES_VIOLATION, __ldv_list_addErr1REQUIRES_VIOLATION, __ldv_list_addErr7REQUIRES_VIOLATION, __ldv_list_addErr2REQUIRES_VIOLATION, __ldv_list_addErr3REQUIRES_VIOLATION, __ldv_list_addErr4REQUIRES_VIOLATION, __ldv_list_addErr5REQUIRES_VIOLATION, __ldv_list_addErr0REQUIRES_VIOLATION, ldv_dev_set_drvdataErr1REQUIRES_VIOLATION, ldv_dev_set_drvdataErr0REQUIRES_VIOLATION, ldv_atomic_sub_returnErr3REQUIRES_VIOLATION, ldv_atomic_sub_returnErr2REQUIRES_VIOLATION, ldv_atomic_sub_returnErr1REQUIRES_VIOLATION, ldv_atomic_sub_returnErr0REQUIRES_VIOLATION, ldv_list_add_tailErr0REQUIRES_VIOLATION, ldv_list_add_tailErr1REQUIRES_VIOLATION, ldv_dev_get_drvdataErr1REQUIRES_VIOLATION, ldv_dev_get_drvdataErr0REQUIRES_VIOLATION, ldv_msg_allocErr0REQUIRES_VIOLATION, ldv_msg_allocErr1REQUIRES_VIOLATION]=== [2018-11-28 13:03:48,142 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-28 13:03:48,143 INFO L82 PathProgramCache]: Analyzing trace with hash 393272412, now seen corresponding path program 2 times [2018-11-28 13:03:48,143 INFO L223 ckRefinementStrategy]: Switched to mode CVC4_FPBP [2018-11-28 13:03:48,143 INFO L69 tionRefinementEngine]: Using refinement strategy WolfRefinementStrategy No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_a5616418-4a25-482a-a0cb-6eefe8bc17e5/bin-2019/uautomizer/cvc4 Starting monitored process 15 with cvc4 --incremental --print-success --lang smt --rewrite-divk (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 15 with cvc4 --incremental --print-success --lang smt --rewrite-divk [2018-11-28 13:03:48,161 INFO L101 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2018-11-28 13:03:48,229 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) [2018-11-28 13:03:48,229 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-11-28 13:03:48,231 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-28 13:03:48,235 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 6 treesize of output 5 [2018-11-28 13:03:48,235 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-11-28 13:03:48,236 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-28 13:03:48,237 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 1 variables, input treesize:6, output treesize:5 [2018-11-28 13:03:48,349 INFO L134 CoverageAnalysis]: Checked inductivity of 136 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 136 trivial. 0 not checked. [2018-11-28 13:03:48,349 INFO L312 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2018-11-28 13:03:48,351 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-28 13:03:48,351 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [12] imperfect sequences [] total 12 [2018-11-28 13:03:48,351 INFO L459 AbstractCegarLoop]: Interpolant automaton has 13 states [2018-11-28 13:03:48,352 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 13 interpolants. [2018-11-28 13:03:48,352 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=33, Invalid=123, Unknown=0, NotChecked=0, Total=156 [2018-11-28 13:03:48,352 INFO L87 Difference]: Start difference. First operand 154 states and 160 transitions. Second operand 13 states. [2018-11-28 13:03:49,203 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-28 13:03:49,203 INFO L93 Difference]: Finished difference Result 164 states and 169 transitions. [2018-11-28 13:03:49,203 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 13 states. [2018-11-28 13:03:49,203 INFO L78 Accepts]: Start accepts. Automaton has 13 states. Word has length 53 [2018-11-28 13:03:49,204 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-28 13:03:49,204 INFO L225 Difference]: With dead ends: 164 [2018-11-28 13:03:49,204 INFO L226 Difference]: Without dead ends: 164 [2018-11-28 13:03:49,204 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 55 GetRequests, 38 SyntacticMatches, 3 SemanticMatches, 14 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 18 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=48, Invalid=192, Unknown=0, NotChecked=0, Total=240 [2018-11-28 13:03:49,205 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 164 states. [2018-11-28 13:03:49,207 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 164 to 152. [2018-11-28 13:03:49,207 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 152 states. [2018-11-28 13:03:49,208 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 152 states to 152 states and 158 transitions. [2018-11-28 13:03:49,208 INFO L78 Accepts]: Start accepts. Automaton has 152 states and 158 transitions. Word has length 53 [2018-11-28 13:03:49,208 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-28 13:03:49,208 INFO L480 AbstractCegarLoop]: Abstraction has 152 states and 158 transitions. [2018-11-28 13:03:49,208 INFO L481 AbstractCegarLoop]: Interpolant automaton has 13 states. [2018-11-28 13:03:49,208 INFO L276 IsEmpty]: Start isEmpty. Operand 152 states and 158 transitions. [2018-11-28 13:03:49,209 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 54 [2018-11-28 13:03:49,209 INFO L394 BasicCegarLoop]: Found error trace [2018-11-28 13:03:49,209 INFO L402 BasicCegarLoop]: trace histogram [16, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-28 13:03:49,209 INFO L423 AbstractCegarLoop]: === Iteration 15 === [ldv_kref_initErr0REQUIRES_VIOLATION, ldv_kref_initErr1REQUIRES_VIOLATION, ldv_list_addErr1REQUIRES_VIOLATION, ldv_list_addErr0REQUIRES_VIOLATION, ldv_kobject_createErr1REQUIRES_VIOLATION, ldv_kobject_createErr0REQUIRES_VIOLATION, ldv_destroy_msgsErr0REQUIRES_VIOLATION, ldv_destroy_msgsErr5REQUIRES_VIOLATION, ldv_destroy_msgsErr4REQUIRES_VIOLATION, ldv_destroy_msgsErr3REQUIRES_VIOLATION, ldv_destroy_msgsErr2REQUIRES_VIOLATION, ldv_destroy_msgsErr1REQUIRES_VIOLATION, ldv_msg_fillErr1REQUIRES_VIOLATION, ldv_msg_fillErr3REQUIRES_VIOLATION, ldv_msg_fillErr2REQUIRES_VIOLATION, ldv_msg_fillErr5REQUIRES_VIOLATION, ldv_msg_fillErr0REQUIRES_VIOLATION, ldv_msg_fillErr4REQUIRES_VIOLATION, ldv_atomic_add_returnErr3REQUIRES_VIOLATION, ldv_atomic_add_returnErr2REQUIRES_VIOLATION, ldv_atomic_add_returnErr1REQUIRES_VIOLATION, ldv_atomic_add_returnErr0REQUIRES_VIOLATION, __ldv_list_delErr1REQUIRES_VIOLATION, __ldv_list_delErr2REQUIRES_VIOLATION, __ldv_list_delErr3REQUIRES_VIOLATION, __ldv_list_delErr0REQUIRES_VIOLATION, ldv_kobject_cleanupErr0REQUIRES_VIOLATION, ldv_kobject_cleanupErr3ASSERT_VIOLATIONMEMORY_FREE, ldv_kobject_cleanupErr2ASSERT_VIOLATIONMEMORY_FREE, ldv_kobject_cleanupErr5ASSERT_VIOLATIONMEMORY_FREE, ldv_kobject_cleanupErr1REQUIRES_VIOLATION, ldv_kobject_cleanupErr4ASSERT_VIOLATIONMEMORY_FREE, ldv_msg_freeErr0REQUIRES_VIOLATION, ldv_msg_freeErr3ASSERT_VIOLATIONMEMORY_FREE, ldv_msg_freeErr2ASSERT_VIOLATIONMEMORY_FREE, ldv_msg_freeErr5ASSERT_VIOLATIONMEMORY_FREE, ldv_msg_freeErr4ASSERT_VIOLATIONMEMORY_FREE, ldv_msg_freeErr1REQUIRES_VIOLATION, mainErr0ENSURES_VIOLATIONMEMORY_LEAK, LDV_INIT_LIST_HEADErr3REQUIRES_VIOLATION, LDV_INIT_LIST_HEADErr2REQUIRES_VIOLATION, LDV_INIT_LIST_HEADErr1REQUIRES_VIOLATION, LDV_INIT_LIST_HEADErr0REQUIRES_VIOLATION, ldv_list_delErr3REQUIRES_VIOLATION, ldv_list_delErr2REQUIRES_VIOLATION, ldv_list_delErr1REQUIRES_VIOLATION, ldv_list_delErr0REQUIRES_VIOLATION, __ldv_list_addErr6REQUIRES_VIOLATION, __ldv_list_addErr1REQUIRES_VIOLATION, __ldv_list_addErr7REQUIRES_VIOLATION, __ldv_list_addErr2REQUIRES_VIOLATION, __ldv_list_addErr3REQUIRES_VIOLATION, __ldv_list_addErr4REQUIRES_VIOLATION, __ldv_list_addErr5REQUIRES_VIOLATION, __ldv_list_addErr0REQUIRES_VIOLATION, ldv_dev_set_drvdataErr1REQUIRES_VIOLATION, ldv_dev_set_drvdataErr0REQUIRES_VIOLATION, ldv_atomic_sub_returnErr3REQUIRES_VIOLATION, ldv_atomic_sub_returnErr2REQUIRES_VIOLATION, ldv_atomic_sub_returnErr1REQUIRES_VIOLATION, ldv_atomic_sub_returnErr0REQUIRES_VIOLATION, ldv_list_add_tailErr0REQUIRES_VIOLATION, ldv_list_add_tailErr1REQUIRES_VIOLATION, ldv_dev_get_drvdataErr1REQUIRES_VIOLATION, ldv_dev_get_drvdataErr0REQUIRES_VIOLATION, ldv_msg_allocErr0REQUIRES_VIOLATION, ldv_msg_allocErr1REQUIRES_VIOLATION]=== [2018-11-28 13:03:49,210 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-28 13:03:49,210 INFO L82 PathProgramCache]: Analyzing trace with hash 393272413, now seen corresponding path program 1 times [2018-11-28 13:03:49,210 INFO L223 ckRefinementStrategy]: Switched to mode CVC4_FPBP [2018-11-28 13:03:49,210 INFO L69 tionRefinementEngine]: Using refinement strategy WolfRefinementStrategy No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_a5616418-4a25-482a-a0cb-6eefe8bc17e5/bin-2019/uautomizer/cvc4 Starting monitored process 16 with cvc4 --incremental --print-success --lang smt --rewrite-divk (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 16 with cvc4 --incremental --print-success --lang smt --rewrite-divk [2018-11-28 13:03:49,226 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-28 13:03:49,410 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-28 13:03:49,414 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-28 13:03:49,422 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 6 treesize of output 5 [2018-11-28 13:03:49,423 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-11-28 13:03:49,433 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-28 13:03:49,433 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 1 variables, input treesize:10, output treesize:9 [2018-11-28 13:03:49,603 INFO L134 CoverageAnalysis]: Checked inductivity of 136 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 136 trivial. 0 not checked. [2018-11-28 13:03:49,603 INFO L312 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2018-11-28 13:03:49,606 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-28 13:03:49,606 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [12] imperfect sequences [] total 12 [2018-11-28 13:03:49,606 INFO L459 AbstractCegarLoop]: Interpolant automaton has 13 states [2018-11-28 13:03:49,606 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 13 interpolants. [2018-11-28 13:03:49,606 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=31, Invalid=125, Unknown=0, NotChecked=0, Total=156 [2018-11-28 13:03:49,607 INFO L87 Difference]: Start difference. First operand 152 states and 158 transitions. Second operand 13 states. [2018-11-28 13:03:50,399 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-28 13:03:50,399 INFO L93 Difference]: Finished difference Result 150 states and 156 transitions. [2018-11-28 13:03:50,400 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 13 states. [2018-11-28 13:03:50,400 INFO L78 Accepts]: Start accepts. Automaton has 13 states. Word has length 53 [2018-11-28 13:03:50,400 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-28 13:03:50,400 INFO L225 Difference]: With dead ends: 150 [2018-11-28 13:03:50,401 INFO L226 Difference]: Without dead ends: 150 [2018-11-28 13:03:50,401 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 56 GetRequests, 38 SyntacticMatches, 3 SemanticMatches, 15 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 25 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=50, Invalid=222, Unknown=0, NotChecked=0, Total=272 [2018-11-28 13:03:50,401 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 150 states. [2018-11-28 13:03:50,404 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 150 to 150. [2018-11-28 13:03:50,404 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 150 states. [2018-11-28 13:03:50,405 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 150 states to 150 states and 156 transitions. [2018-11-28 13:03:50,405 INFO L78 Accepts]: Start accepts. Automaton has 150 states and 156 transitions. Word has length 53 [2018-11-28 13:03:50,405 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-28 13:03:50,405 INFO L480 AbstractCegarLoop]: Abstraction has 150 states and 156 transitions. [2018-11-28 13:03:50,405 INFO L481 AbstractCegarLoop]: Interpolant automaton has 13 states. [2018-11-28 13:03:50,406 INFO L276 IsEmpty]: Start isEmpty. Operand 150 states and 156 transitions. [2018-11-28 13:03:50,406 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 59 [2018-11-28 13:03:50,406 INFO L394 BasicCegarLoop]: Found error trace [2018-11-28 13:03:50,406 INFO L402 BasicCegarLoop]: trace histogram [16, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-28 13:03:50,407 INFO L423 AbstractCegarLoop]: === Iteration 16 === [ldv_kref_initErr0REQUIRES_VIOLATION, ldv_kref_initErr1REQUIRES_VIOLATION, ldv_list_addErr1REQUIRES_VIOLATION, ldv_list_addErr0REQUIRES_VIOLATION, ldv_kobject_createErr1REQUIRES_VIOLATION, ldv_kobject_createErr0REQUIRES_VIOLATION, ldv_destroy_msgsErr0REQUIRES_VIOLATION, ldv_destroy_msgsErr5REQUIRES_VIOLATION, ldv_destroy_msgsErr4REQUIRES_VIOLATION, ldv_destroy_msgsErr3REQUIRES_VIOLATION, ldv_destroy_msgsErr2REQUIRES_VIOLATION, ldv_destroy_msgsErr1REQUIRES_VIOLATION, ldv_msg_fillErr1REQUIRES_VIOLATION, ldv_msg_fillErr3REQUIRES_VIOLATION, ldv_msg_fillErr2REQUIRES_VIOLATION, ldv_msg_fillErr5REQUIRES_VIOLATION, ldv_msg_fillErr0REQUIRES_VIOLATION, ldv_msg_fillErr4REQUIRES_VIOLATION, ldv_atomic_add_returnErr3REQUIRES_VIOLATION, ldv_atomic_add_returnErr2REQUIRES_VIOLATION, ldv_atomic_add_returnErr1REQUIRES_VIOLATION, ldv_atomic_add_returnErr0REQUIRES_VIOLATION, __ldv_list_delErr1REQUIRES_VIOLATION, __ldv_list_delErr2REQUIRES_VIOLATION, __ldv_list_delErr3REQUIRES_VIOLATION, __ldv_list_delErr0REQUIRES_VIOLATION, ldv_kobject_cleanupErr0REQUIRES_VIOLATION, ldv_kobject_cleanupErr3ASSERT_VIOLATIONMEMORY_FREE, ldv_kobject_cleanupErr2ASSERT_VIOLATIONMEMORY_FREE, ldv_kobject_cleanupErr5ASSERT_VIOLATIONMEMORY_FREE, ldv_kobject_cleanupErr1REQUIRES_VIOLATION, ldv_kobject_cleanupErr4ASSERT_VIOLATIONMEMORY_FREE, ldv_msg_freeErr0REQUIRES_VIOLATION, ldv_msg_freeErr3ASSERT_VIOLATIONMEMORY_FREE, ldv_msg_freeErr2ASSERT_VIOLATIONMEMORY_FREE, ldv_msg_freeErr5ASSERT_VIOLATIONMEMORY_FREE, ldv_msg_freeErr4ASSERT_VIOLATIONMEMORY_FREE, ldv_msg_freeErr1REQUIRES_VIOLATION, mainErr0ENSURES_VIOLATIONMEMORY_LEAK, LDV_INIT_LIST_HEADErr3REQUIRES_VIOLATION, LDV_INIT_LIST_HEADErr2REQUIRES_VIOLATION, LDV_INIT_LIST_HEADErr1REQUIRES_VIOLATION, LDV_INIT_LIST_HEADErr0REQUIRES_VIOLATION, ldv_list_delErr3REQUIRES_VIOLATION, ldv_list_delErr2REQUIRES_VIOLATION, ldv_list_delErr1REQUIRES_VIOLATION, ldv_list_delErr0REQUIRES_VIOLATION, __ldv_list_addErr6REQUIRES_VIOLATION, __ldv_list_addErr1REQUIRES_VIOLATION, __ldv_list_addErr7REQUIRES_VIOLATION, __ldv_list_addErr2REQUIRES_VIOLATION, __ldv_list_addErr3REQUIRES_VIOLATION, __ldv_list_addErr4REQUIRES_VIOLATION, __ldv_list_addErr5REQUIRES_VIOLATION, __ldv_list_addErr0REQUIRES_VIOLATION, ldv_dev_set_drvdataErr1REQUIRES_VIOLATION, ldv_dev_set_drvdataErr0REQUIRES_VIOLATION, ldv_atomic_sub_returnErr3REQUIRES_VIOLATION, ldv_atomic_sub_returnErr2REQUIRES_VIOLATION, ldv_atomic_sub_returnErr1REQUIRES_VIOLATION, ldv_atomic_sub_returnErr0REQUIRES_VIOLATION, ldv_list_add_tailErr0REQUIRES_VIOLATION, ldv_list_add_tailErr1REQUIRES_VIOLATION, ldv_dev_get_drvdataErr1REQUIRES_VIOLATION, ldv_dev_get_drvdataErr0REQUIRES_VIOLATION, ldv_msg_allocErr0REQUIRES_VIOLATION, ldv_msg_allocErr1REQUIRES_VIOLATION]=== [2018-11-28 13:03:50,407 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-28 13:03:50,407 INFO L82 PathProgramCache]: Analyzing trace with hash -1198180007, now seen corresponding path program 1 times [2018-11-28 13:03:50,407 INFO L223 ckRefinementStrategy]: Switched to mode CVC4_FPBP [2018-11-28 13:03:50,407 INFO L69 tionRefinementEngine]: Using refinement strategy WolfRefinementStrategy No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_a5616418-4a25-482a-a0cb-6eefe8bc17e5/bin-2019/uautomizer/cvc4 Starting monitored process 17 with cvc4 --incremental --print-success --lang smt --rewrite-divk (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 17 with cvc4 --incremental --print-success --lang smt --rewrite-divk [2018-11-28 13:03:50,424 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-28 13:03:50,476 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-28 13:03:50,480 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-28 13:03:50,508 INFO L134 CoverageAnalysis]: Checked inductivity of 136 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 136 trivial. 0 not checked. [2018-11-28 13:03:50,508 INFO L312 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2018-11-28 13:03:50,510 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-28 13:03:50,510 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [7] imperfect sequences [] total 7 [2018-11-28 13:03:50,510 INFO L459 AbstractCegarLoop]: Interpolant automaton has 7 states [2018-11-28 13:03:50,510 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2018-11-28 13:03:50,510 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=11, Invalid=31, Unknown=0, NotChecked=0, Total=42 [2018-11-28 13:03:50,510 INFO L87 Difference]: Start difference. First operand 150 states and 156 transitions. Second operand 7 states. [2018-11-28 13:03:50,540 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-28 13:03:50,540 INFO L93 Difference]: Finished difference Result 152 states and 157 transitions. [2018-11-28 13:03:50,544 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2018-11-28 13:03:50,545 INFO L78 Accepts]: Start accepts. Automaton has 7 states. Word has length 58 [2018-11-28 13:03:50,545 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-28 13:03:50,545 INFO L225 Difference]: With dead ends: 152 [2018-11-28 13:03:50,546 INFO L226 Difference]: Without dead ends: 150 [2018-11-28 13:03:50,546 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 58 GetRequests, 52 SyntacticMatches, 0 SemanticMatches, 6 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=15, Invalid=41, Unknown=0, NotChecked=0, Total=56 [2018-11-28 13:03:50,559 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 150 states. [2018-11-28 13:03:50,561 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 150 to 150. [2018-11-28 13:03:50,561 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 150 states. [2018-11-28 13:03:50,562 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 150 states to 150 states and 155 transitions. [2018-11-28 13:03:50,562 INFO L78 Accepts]: Start accepts. Automaton has 150 states and 155 transitions. Word has length 58 [2018-11-28 13:03:50,563 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-28 13:03:50,563 INFO L480 AbstractCegarLoop]: Abstraction has 150 states and 155 transitions. [2018-11-28 13:03:50,563 INFO L481 AbstractCegarLoop]: Interpolant automaton has 7 states. [2018-11-28 13:03:50,563 INFO L276 IsEmpty]: Start isEmpty. Operand 150 states and 155 transitions. [2018-11-28 13:03:50,564 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 64 [2018-11-28 13:03:50,564 INFO L394 BasicCegarLoop]: Found error trace [2018-11-28 13:03:50,564 INFO L402 BasicCegarLoop]: trace histogram [16, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-28 13:03:50,564 INFO L423 AbstractCegarLoop]: === Iteration 17 === [ldv_kref_initErr0REQUIRES_VIOLATION, ldv_kref_initErr1REQUIRES_VIOLATION, ldv_list_addErr1REQUIRES_VIOLATION, ldv_list_addErr0REQUIRES_VIOLATION, ldv_kobject_createErr1REQUIRES_VIOLATION, ldv_kobject_createErr0REQUIRES_VIOLATION, ldv_destroy_msgsErr0REQUIRES_VIOLATION, ldv_destroy_msgsErr5REQUIRES_VIOLATION, ldv_destroy_msgsErr4REQUIRES_VIOLATION, ldv_destroy_msgsErr3REQUIRES_VIOLATION, ldv_destroy_msgsErr2REQUIRES_VIOLATION, ldv_destroy_msgsErr1REQUIRES_VIOLATION, ldv_msg_fillErr1REQUIRES_VIOLATION, ldv_msg_fillErr3REQUIRES_VIOLATION, ldv_msg_fillErr2REQUIRES_VIOLATION, ldv_msg_fillErr5REQUIRES_VIOLATION, ldv_msg_fillErr0REQUIRES_VIOLATION, ldv_msg_fillErr4REQUIRES_VIOLATION, ldv_atomic_add_returnErr3REQUIRES_VIOLATION, ldv_atomic_add_returnErr2REQUIRES_VIOLATION, ldv_atomic_add_returnErr1REQUIRES_VIOLATION, ldv_atomic_add_returnErr0REQUIRES_VIOLATION, __ldv_list_delErr1REQUIRES_VIOLATION, __ldv_list_delErr2REQUIRES_VIOLATION, __ldv_list_delErr3REQUIRES_VIOLATION, __ldv_list_delErr0REQUIRES_VIOLATION, ldv_kobject_cleanupErr0REQUIRES_VIOLATION, ldv_kobject_cleanupErr3ASSERT_VIOLATIONMEMORY_FREE, ldv_kobject_cleanupErr2ASSERT_VIOLATIONMEMORY_FREE, ldv_kobject_cleanupErr5ASSERT_VIOLATIONMEMORY_FREE, ldv_kobject_cleanupErr1REQUIRES_VIOLATION, ldv_kobject_cleanupErr4ASSERT_VIOLATIONMEMORY_FREE, ldv_msg_freeErr0REQUIRES_VIOLATION, ldv_msg_freeErr3ASSERT_VIOLATIONMEMORY_FREE, ldv_msg_freeErr2ASSERT_VIOLATIONMEMORY_FREE, ldv_msg_freeErr5ASSERT_VIOLATIONMEMORY_FREE, ldv_msg_freeErr4ASSERT_VIOLATIONMEMORY_FREE, ldv_msg_freeErr1REQUIRES_VIOLATION, mainErr0ENSURES_VIOLATIONMEMORY_LEAK, LDV_INIT_LIST_HEADErr3REQUIRES_VIOLATION, LDV_INIT_LIST_HEADErr2REQUIRES_VIOLATION, LDV_INIT_LIST_HEADErr1REQUIRES_VIOLATION, LDV_INIT_LIST_HEADErr0REQUIRES_VIOLATION, ldv_list_delErr3REQUIRES_VIOLATION, ldv_list_delErr2REQUIRES_VIOLATION, ldv_list_delErr1REQUIRES_VIOLATION, ldv_list_delErr0REQUIRES_VIOLATION, __ldv_list_addErr6REQUIRES_VIOLATION, __ldv_list_addErr1REQUIRES_VIOLATION, __ldv_list_addErr7REQUIRES_VIOLATION, __ldv_list_addErr2REQUIRES_VIOLATION, __ldv_list_addErr3REQUIRES_VIOLATION, __ldv_list_addErr4REQUIRES_VIOLATION, __ldv_list_addErr5REQUIRES_VIOLATION, __ldv_list_addErr0REQUIRES_VIOLATION, ldv_dev_set_drvdataErr1REQUIRES_VIOLATION, ldv_dev_set_drvdataErr0REQUIRES_VIOLATION, ldv_atomic_sub_returnErr3REQUIRES_VIOLATION, ldv_atomic_sub_returnErr2REQUIRES_VIOLATION, ldv_atomic_sub_returnErr1REQUIRES_VIOLATION, ldv_atomic_sub_returnErr0REQUIRES_VIOLATION, ldv_list_add_tailErr0REQUIRES_VIOLATION, ldv_list_add_tailErr1REQUIRES_VIOLATION, ldv_dev_get_drvdataErr1REQUIRES_VIOLATION, ldv_dev_get_drvdataErr0REQUIRES_VIOLATION, ldv_msg_allocErr0REQUIRES_VIOLATION, ldv_msg_allocErr1REQUIRES_VIOLATION]=== [2018-11-28 13:03:50,564 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-28 13:03:50,564 INFO L82 PathProgramCache]: Analyzing trace with hash 2025310666, now seen corresponding path program 1 times [2018-11-28 13:03:50,565 INFO L223 ckRefinementStrategy]: Switched to mode CVC4_FPBP [2018-11-28 13:03:50,565 INFO L69 tionRefinementEngine]: Using refinement strategy WolfRefinementStrategy No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_a5616418-4a25-482a-a0cb-6eefe8bc17e5/bin-2019/uautomizer/cvc4 Starting monitored process 18 with cvc4 --incremental --print-success --lang smt --rewrite-divk (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 18 with cvc4 --incremental --print-success --lang smt --rewrite-divk [2018-11-28 13:03:50,583 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-28 13:03:50,632 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-28 13:03:50,635 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-28 13:03:50,673 INFO L134 CoverageAnalysis]: Checked inductivity of 136 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 136 trivial. 0 not checked. [2018-11-28 13:03:50,673 INFO L312 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2018-11-28 13:03:50,674 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-28 13:03:50,674 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [9] imperfect sequences [] total 9 [2018-11-28 13:03:50,675 INFO L459 AbstractCegarLoop]: Interpolant automaton has 9 states [2018-11-28 13:03:50,675 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 9 interpolants. [2018-11-28 13:03:50,675 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=15, Invalid=57, Unknown=0, NotChecked=0, Total=72 [2018-11-28 13:03:50,675 INFO L87 Difference]: Start difference. First operand 150 states and 155 transitions. Second operand 9 states. [2018-11-28 13:03:50,728 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-28 13:03:50,729 INFO L93 Difference]: Finished difference Result 154 states and 158 transitions. [2018-11-28 13:03:50,729 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2018-11-28 13:03:50,729 INFO L78 Accepts]: Start accepts. Automaton has 9 states. Word has length 63 [2018-11-28 13:03:50,729 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-28 13:03:50,730 INFO L225 Difference]: With dead ends: 154 [2018-11-28 13:03:50,730 INFO L226 Difference]: Without dead ends: 150 [2018-11-28 13:03:50,730 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 64 GetRequests, 55 SyntacticMatches, 0 SemanticMatches, 9 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=23, Invalid=87, Unknown=0, NotChecked=0, Total=110 [2018-11-28 13:03:50,730 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 150 states. [2018-11-28 13:03:50,733 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 150 to 150. [2018-11-28 13:03:50,733 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 150 states. [2018-11-28 13:03:50,733 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 150 states to 150 states and 154 transitions. [2018-11-28 13:03:50,734 INFO L78 Accepts]: Start accepts. Automaton has 150 states and 154 transitions. Word has length 63 [2018-11-28 13:03:50,734 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-28 13:03:50,734 INFO L480 AbstractCegarLoop]: Abstraction has 150 states and 154 transitions. [2018-11-28 13:03:50,734 INFO L481 AbstractCegarLoop]: Interpolant automaton has 9 states. [2018-11-28 13:03:50,734 INFO L276 IsEmpty]: Start isEmpty. Operand 150 states and 154 transitions. [2018-11-28 13:03:50,734 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 75 [2018-11-28 13:03:50,735 INFO L394 BasicCegarLoop]: Found error trace [2018-11-28 13:03:50,735 INFO L402 BasicCegarLoop]: trace histogram [16, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-28 13:03:50,735 INFO L423 AbstractCegarLoop]: === Iteration 18 === [ldv_kref_initErr0REQUIRES_VIOLATION, ldv_kref_initErr1REQUIRES_VIOLATION, ldv_list_addErr1REQUIRES_VIOLATION, ldv_list_addErr0REQUIRES_VIOLATION, ldv_kobject_createErr1REQUIRES_VIOLATION, ldv_kobject_createErr0REQUIRES_VIOLATION, ldv_destroy_msgsErr0REQUIRES_VIOLATION, ldv_destroy_msgsErr5REQUIRES_VIOLATION, ldv_destroy_msgsErr4REQUIRES_VIOLATION, ldv_destroy_msgsErr3REQUIRES_VIOLATION, ldv_destroy_msgsErr2REQUIRES_VIOLATION, ldv_destroy_msgsErr1REQUIRES_VIOLATION, ldv_msg_fillErr1REQUIRES_VIOLATION, ldv_msg_fillErr3REQUIRES_VIOLATION, ldv_msg_fillErr2REQUIRES_VIOLATION, ldv_msg_fillErr5REQUIRES_VIOLATION, ldv_msg_fillErr0REQUIRES_VIOLATION, ldv_msg_fillErr4REQUIRES_VIOLATION, ldv_atomic_add_returnErr3REQUIRES_VIOLATION, ldv_atomic_add_returnErr2REQUIRES_VIOLATION, ldv_atomic_add_returnErr1REQUIRES_VIOLATION, ldv_atomic_add_returnErr0REQUIRES_VIOLATION, __ldv_list_delErr1REQUIRES_VIOLATION, __ldv_list_delErr2REQUIRES_VIOLATION, __ldv_list_delErr3REQUIRES_VIOLATION, __ldv_list_delErr0REQUIRES_VIOLATION, ldv_kobject_cleanupErr0REQUIRES_VIOLATION, ldv_kobject_cleanupErr3ASSERT_VIOLATIONMEMORY_FREE, ldv_kobject_cleanupErr2ASSERT_VIOLATIONMEMORY_FREE, ldv_kobject_cleanupErr5ASSERT_VIOLATIONMEMORY_FREE, ldv_kobject_cleanupErr1REQUIRES_VIOLATION, ldv_kobject_cleanupErr4ASSERT_VIOLATIONMEMORY_FREE, ldv_msg_freeErr0REQUIRES_VIOLATION, ldv_msg_freeErr3ASSERT_VIOLATIONMEMORY_FREE, ldv_msg_freeErr2ASSERT_VIOLATIONMEMORY_FREE, ldv_msg_freeErr5ASSERT_VIOLATIONMEMORY_FREE, ldv_msg_freeErr4ASSERT_VIOLATIONMEMORY_FREE, ldv_msg_freeErr1REQUIRES_VIOLATION, mainErr0ENSURES_VIOLATIONMEMORY_LEAK, LDV_INIT_LIST_HEADErr3REQUIRES_VIOLATION, LDV_INIT_LIST_HEADErr2REQUIRES_VIOLATION, LDV_INIT_LIST_HEADErr1REQUIRES_VIOLATION, LDV_INIT_LIST_HEADErr0REQUIRES_VIOLATION, ldv_list_delErr3REQUIRES_VIOLATION, ldv_list_delErr2REQUIRES_VIOLATION, ldv_list_delErr1REQUIRES_VIOLATION, ldv_list_delErr0REQUIRES_VIOLATION, __ldv_list_addErr6REQUIRES_VIOLATION, __ldv_list_addErr1REQUIRES_VIOLATION, __ldv_list_addErr7REQUIRES_VIOLATION, __ldv_list_addErr2REQUIRES_VIOLATION, __ldv_list_addErr3REQUIRES_VIOLATION, __ldv_list_addErr4REQUIRES_VIOLATION, __ldv_list_addErr5REQUIRES_VIOLATION, __ldv_list_addErr0REQUIRES_VIOLATION, ldv_dev_set_drvdataErr1REQUIRES_VIOLATION, ldv_dev_set_drvdataErr0REQUIRES_VIOLATION, ldv_atomic_sub_returnErr3REQUIRES_VIOLATION, ldv_atomic_sub_returnErr2REQUIRES_VIOLATION, ldv_atomic_sub_returnErr1REQUIRES_VIOLATION, ldv_atomic_sub_returnErr0REQUIRES_VIOLATION, ldv_list_add_tailErr0REQUIRES_VIOLATION, ldv_list_add_tailErr1REQUIRES_VIOLATION, ldv_dev_get_drvdataErr1REQUIRES_VIOLATION, ldv_dev_get_drvdataErr0REQUIRES_VIOLATION, ldv_msg_allocErr0REQUIRES_VIOLATION, ldv_msg_allocErr1REQUIRES_VIOLATION]=== [2018-11-28 13:03:50,735 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-28 13:03:50,735 INFO L82 PathProgramCache]: Analyzing trace with hash 1370658201, now seen corresponding path program 1 times [2018-11-28 13:03:50,736 INFO L223 ckRefinementStrategy]: Switched to mode CVC4_FPBP [2018-11-28 13:03:50,736 INFO L69 tionRefinementEngine]: Using refinement strategy WolfRefinementStrategy No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_a5616418-4a25-482a-a0cb-6eefe8bc17e5/bin-2019/uautomizer/cvc4 Starting monitored process 19 with cvc4 --incremental --print-success --lang smt --rewrite-divk (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 19 with cvc4 --incremental --print-success --lang smt --rewrite-divk [2018-11-28 13:03:50,757 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-28 13:03:50,924 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-28 13:03:50,929 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-28 13:03:50,931 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 6 treesize of output 5 [2018-11-28 13:03:50,931 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-11-28 13:03:50,944 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-28 13:03:50,945 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 1 variables, input treesize:6, output treesize:5 [2018-11-28 13:03:51,185 INFO L134 CoverageAnalysis]: Checked inductivity of 136 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 136 trivial. 0 not checked. [2018-11-28 13:03:51,186 INFO L312 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2018-11-28 13:03:51,189 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-28 13:03:51,189 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [19] imperfect sequences [] total 19 [2018-11-28 13:03:51,189 INFO L459 AbstractCegarLoop]: Interpolant automaton has 20 states [2018-11-28 13:03:51,190 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 20 interpolants. [2018-11-28 13:03:51,190 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=54, Invalid=326, Unknown=0, NotChecked=0, Total=380 [2018-11-28 13:03:51,190 INFO L87 Difference]: Start difference. First operand 150 states and 154 transitions. Second operand 20 states. [2018-11-28 13:03:52,655 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-28 13:03:52,655 INFO L93 Difference]: Finished difference Result 160 states and 163 transitions. [2018-11-28 13:03:52,655 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 20 states. [2018-11-28 13:03:52,655 INFO L78 Accepts]: Start accepts. Automaton has 20 states. Word has length 74 [2018-11-28 13:03:52,655 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-28 13:03:52,656 INFO L225 Difference]: With dead ends: 160 [2018-11-28 13:03:52,656 INFO L226 Difference]: Without dead ends: 160 [2018-11-28 13:03:52,656 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 78 GetRequests, 52 SyntacticMatches, 3 SemanticMatches, 23 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 29 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=79, Invalid=521, Unknown=0, NotChecked=0, Total=600 [2018-11-28 13:03:52,657 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 160 states. [2018-11-28 13:03:52,658 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 160 to 148. [2018-11-28 13:03:52,659 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 148 states. [2018-11-28 13:03:52,660 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 148 states to 148 states and 152 transitions. [2018-11-28 13:03:52,660 INFO L78 Accepts]: Start accepts. Automaton has 148 states and 152 transitions. Word has length 74 [2018-11-28 13:03:52,660 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-28 13:03:52,660 INFO L480 AbstractCegarLoop]: Abstraction has 148 states and 152 transitions. [2018-11-28 13:03:52,660 INFO L481 AbstractCegarLoop]: Interpolant automaton has 20 states. [2018-11-28 13:03:52,661 INFO L276 IsEmpty]: Start isEmpty. Operand 148 states and 152 transitions. [2018-11-28 13:03:52,661 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 75 [2018-11-28 13:03:52,661 INFO L394 BasicCegarLoop]: Found error trace [2018-11-28 13:03:52,661 INFO L402 BasicCegarLoop]: trace histogram [16, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-28 13:03:52,662 INFO L423 AbstractCegarLoop]: === Iteration 19 === [ldv_kref_initErr0REQUIRES_VIOLATION, ldv_kref_initErr1REQUIRES_VIOLATION, ldv_list_addErr1REQUIRES_VIOLATION, ldv_list_addErr0REQUIRES_VIOLATION, ldv_kobject_createErr1REQUIRES_VIOLATION, ldv_kobject_createErr0REQUIRES_VIOLATION, ldv_destroy_msgsErr0REQUIRES_VIOLATION, ldv_destroy_msgsErr5REQUIRES_VIOLATION, ldv_destroy_msgsErr4REQUIRES_VIOLATION, ldv_destroy_msgsErr3REQUIRES_VIOLATION, ldv_destroy_msgsErr2REQUIRES_VIOLATION, ldv_destroy_msgsErr1REQUIRES_VIOLATION, ldv_msg_fillErr1REQUIRES_VIOLATION, ldv_msg_fillErr3REQUIRES_VIOLATION, ldv_msg_fillErr2REQUIRES_VIOLATION, ldv_msg_fillErr5REQUIRES_VIOLATION, ldv_msg_fillErr0REQUIRES_VIOLATION, ldv_msg_fillErr4REQUIRES_VIOLATION, ldv_atomic_add_returnErr3REQUIRES_VIOLATION, ldv_atomic_add_returnErr2REQUIRES_VIOLATION, ldv_atomic_add_returnErr1REQUIRES_VIOLATION, ldv_atomic_add_returnErr0REQUIRES_VIOLATION, __ldv_list_delErr1REQUIRES_VIOLATION, __ldv_list_delErr2REQUIRES_VIOLATION, __ldv_list_delErr3REQUIRES_VIOLATION, __ldv_list_delErr0REQUIRES_VIOLATION, ldv_kobject_cleanupErr0REQUIRES_VIOLATION, ldv_kobject_cleanupErr3ASSERT_VIOLATIONMEMORY_FREE, ldv_kobject_cleanupErr2ASSERT_VIOLATIONMEMORY_FREE, ldv_kobject_cleanupErr5ASSERT_VIOLATIONMEMORY_FREE, ldv_kobject_cleanupErr1REQUIRES_VIOLATION, ldv_kobject_cleanupErr4ASSERT_VIOLATIONMEMORY_FREE, ldv_msg_freeErr0REQUIRES_VIOLATION, ldv_msg_freeErr3ASSERT_VIOLATIONMEMORY_FREE, ldv_msg_freeErr2ASSERT_VIOLATIONMEMORY_FREE, ldv_msg_freeErr5ASSERT_VIOLATIONMEMORY_FREE, ldv_msg_freeErr4ASSERT_VIOLATIONMEMORY_FREE, ldv_msg_freeErr1REQUIRES_VIOLATION, mainErr0ENSURES_VIOLATIONMEMORY_LEAK, LDV_INIT_LIST_HEADErr3REQUIRES_VIOLATION, LDV_INIT_LIST_HEADErr2REQUIRES_VIOLATION, LDV_INIT_LIST_HEADErr1REQUIRES_VIOLATION, LDV_INIT_LIST_HEADErr0REQUIRES_VIOLATION, ldv_list_delErr3REQUIRES_VIOLATION, ldv_list_delErr2REQUIRES_VIOLATION, ldv_list_delErr1REQUIRES_VIOLATION, ldv_list_delErr0REQUIRES_VIOLATION, __ldv_list_addErr6REQUIRES_VIOLATION, __ldv_list_addErr1REQUIRES_VIOLATION, __ldv_list_addErr7REQUIRES_VIOLATION, __ldv_list_addErr2REQUIRES_VIOLATION, __ldv_list_addErr3REQUIRES_VIOLATION, __ldv_list_addErr4REQUIRES_VIOLATION, __ldv_list_addErr5REQUIRES_VIOLATION, __ldv_list_addErr0REQUIRES_VIOLATION, ldv_dev_set_drvdataErr1REQUIRES_VIOLATION, ldv_dev_set_drvdataErr0REQUIRES_VIOLATION, ldv_atomic_sub_returnErr3REQUIRES_VIOLATION, ldv_atomic_sub_returnErr2REQUIRES_VIOLATION, ldv_atomic_sub_returnErr1REQUIRES_VIOLATION, ldv_atomic_sub_returnErr0REQUIRES_VIOLATION, ldv_list_add_tailErr0REQUIRES_VIOLATION, ldv_list_add_tailErr1REQUIRES_VIOLATION, ldv_dev_get_drvdataErr1REQUIRES_VIOLATION, ldv_dev_get_drvdataErr0REQUIRES_VIOLATION, ldv_msg_allocErr0REQUIRES_VIOLATION, ldv_msg_allocErr1REQUIRES_VIOLATION]=== [2018-11-28 13:03:52,662 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-28 13:03:52,662 INFO L82 PathProgramCache]: Analyzing trace with hash 1370658202, now seen corresponding path program 1 times [2018-11-28 13:03:52,662 INFO L223 ckRefinementStrategy]: Switched to mode CVC4_FPBP [2018-11-28 13:03:52,662 INFO L69 tionRefinementEngine]: Using refinement strategy WolfRefinementStrategy No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_a5616418-4a25-482a-a0cb-6eefe8bc17e5/bin-2019/uautomizer/cvc4 Starting monitored process 20 with cvc4 --incremental --print-success --lang smt --rewrite-divk (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 20 with cvc4 --incremental --print-success --lang smt --rewrite-divk [2018-11-28 13:03:52,693 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-28 13:03:52,906 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-28 13:03:52,924 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-28 13:03:52,936 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 6 treesize of output 5 [2018-11-28 13:03:52,936 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-11-28 13:03:52,943 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-28 13:03:52,943 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 1 variables, input treesize:10, output treesize:9 [2018-11-28 13:03:53,345 INFO L134 CoverageAnalysis]: Checked inductivity of 136 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 136 trivial. 0 not checked. [2018-11-28 13:03:53,346 INFO L312 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2018-11-28 13:03:53,349 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-28 13:03:53,349 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [19] imperfect sequences [] total 19 [2018-11-28 13:03:53,349 INFO L459 AbstractCegarLoop]: Interpolant automaton has 20 states [2018-11-28 13:03:53,350 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 20 interpolants. [2018-11-28 13:03:53,350 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=52, Invalid=328, Unknown=0, NotChecked=0, Total=380 [2018-11-28 13:03:53,350 INFO L87 Difference]: Start difference. First operand 148 states and 152 transitions. Second operand 20 states. [2018-11-28 13:03:54,958 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-28 13:03:54,958 INFO L93 Difference]: Finished difference Result 146 states and 150 transitions. [2018-11-28 13:03:54,959 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 20 states. [2018-11-28 13:03:54,960 INFO L78 Accepts]: Start accepts. Automaton has 20 states. Word has length 74 [2018-11-28 13:03:54,960 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-28 13:03:54,960 INFO L225 Difference]: With dead ends: 146 [2018-11-28 13:03:54,961 INFO L226 Difference]: Without dead ends: 146 [2018-11-28 13:03:54,961 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 79 GetRequests, 52 SyntacticMatches, 3 SemanticMatches, 24 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 45 ImplicationChecksByTransitivity, 0.5s TimeCoverageRelationStatistics Valid=81, Invalid=569, Unknown=0, NotChecked=0, Total=650 [2018-11-28 13:03:54,961 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 146 states. [2018-11-28 13:03:54,963 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 146 to 146. [2018-11-28 13:03:54,964 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 146 states. [2018-11-28 13:03:54,965 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 146 states to 146 states and 150 transitions. [2018-11-28 13:03:54,965 INFO L78 Accepts]: Start accepts. Automaton has 146 states and 150 transitions. Word has length 74 [2018-11-28 13:03:54,965 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-28 13:03:54,965 INFO L480 AbstractCegarLoop]: Abstraction has 146 states and 150 transitions. [2018-11-28 13:03:54,965 INFO L481 AbstractCegarLoop]: Interpolant automaton has 20 states. [2018-11-28 13:03:54,965 INFO L276 IsEmpty]: Start isEmpty. Operand 146 states and 150 transitions. [2018-11-28 13:03:54,966 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 86 [2018-11-28 13:03:54,966 INFO L394 BasicCegarLoop]: Found error trace [2018-11-28 13:03:54,966 INFO L402 BasicCegarLoop]: trace histogram [16, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-28 13:03:54,966 INFO L423 AbstractCegarLoop]: === Iteration 20 === [ldv_kref_initErr0REQUIRES_VIOLATION, ldv_kref_initErr1REQUIRES_VIOLATION, ldv_list_addErr1REQUIRES_VIOLATION, ldv_list_addErr0REQUIRES_VIOLATION, ldv_kobject_createErr1REQUIRES_VIOLATION, ldv_kobject_createErr0REQUIRES_VIOLATION, ldv_destroy_msgsErr0REQUIRES_VIOLATION, ldv_destroy_msgsErr5REQUIRES_VIOLATION, ldv_destroy_msgsErr4REQUIRES_VIOLATION, ldv_destroy_msgsErr3REQUIRES_VIOLATION, ldv_destroy_msgsErr2REQUIRES_VIOLATION, ldv_destroy_msgsErr1REQUIRES_VIOLATION, ldv_msg_fillErr1REQUIRES_VIOLATION, ldv_msg_fillErr3REQUIRES_VIOLATION, ldv_msg_fillErr2REQUIRES_VIOLATION, ldv_msg_fillErr5REQUIRES_VIOLATION, ldv_msg_fillErr0REQUIRES_VIOLATION, ldv_msg_fillErr4REQUIRES_VIOLATION, ldv_atomic_add_returnErr3REQUIRES_VIOLATION, ldv_atomic_add_returnErr2REQUIRES_VIOLATION, ldv_atomic_add_returnErr1REQUIRES_VIOLATION, ldv_atomic_add_returnErr0REQUIRES_VIOLATION, __ldv_list_delErr1REQUIRES_VIOLATION, __ldv_list_delErr2REQUIRES_VIOLATION, __ldv_list_delErr3REQUIRES_VIOLATION, __ldv_list_delErr0REQUIRES_VIOLATION, ldv_kobject_cleanupErr0REQUIRES_VIOLATION, ldv_kobject_cleanupErr3ASSERT_VIOLATIONMEMORY_FREE, ldv_kobject_cleanupErr2ASSERT_VIOLATIONMEMORY_FREE, ldv_kobject_cleanupErr5ASSERT_VIOLATIONMEMORY_FREE, ldv_kobject_cleanupErr1REQUIRES_VIOLATION, ldv_kobject_cleanupErr4ASSERT_VIOLATIONMEMORY_FREE, ldv_msg_freeErr0REQUIRES_VIOLATION, ldv_msg_freeErr3ASSERT_VIOLATIONMEMORY_FREE, ldv_msg_freeErr2ASSERT_VIOLATIONMEMORY_FREE, ldv_msg_freeErr5ASSERT_VIOLATIONMEMORY_FREE, ldv_msg_freeErr4ASSERT_VIOLATIONMEMORY_FREE, ldv_msg_freeErr1REQUIRES_VIOLATION, mainErr0ENSURES_VIOLATIONMEMORY_LEAK, LDV_INIT_LIST_HEADErr3REQUIRES_VIOLATION, LDV_INIT_LIST_HEADErr2REQUIRES_VIOLATION, LDV_INIT_LIST_HEADErr1REQUIRES_VIOLATION, LDV_INIT_LIST_HEADErr0REQUIRES_VIOLATION, ldv_list_delErr3REQUIRES_VIOLATION, ldv_list_delErr2REQUIRES_VIOLATION, ldv_list_delErr1REQUIRES_VIOLATION, ldv_list_delErr0REQUIRES_VIOLATION, __ldv_list_addErr6REQUIRES_VIOLATION, __ldv_list_addErr1REQUIRES_VIOLATION, __ldv_list_addErr7REQUIRES_VIOLATION, __ldv_list_addErr2REQUIRES_VIOLATION, __ldv_list_addErr3REQUIRES_VIOLATION, __ldv_list_addErr4REQUIRES_VIOLATION, __ldv_list_addErr5REQUIRES_VIOLATION, __ldv_list_addErr0REQUIRES_VIOLATION, ldv_dev_set_drvdataErr1REQUIRES_VIOLATION, ldv_dev_set_drvdataErr0REQUIRES_VIOLATION, ldv_atomic_sub_returnErr3REQUIRES_VIOLATION, ldv_atomic_sub_returnErr2REQUIRES_VIOLATION, ldv_atomic_sub_returnErr1REQUIRES_VIOLATION, ldv_atomic_sub_returnErr0REQUIRES_VIOLATION, ldv_list_add_tailErr0REQUIRES_VIOLATION, ldv_list_add_tailErr1REQUIRES_VIOLATION, ldv_dev_get_drvdataErr1REQUIRES_VIOLATION, ldv_dev_get_drvdataErr0REQUIRES_VIOLATION, ldv_msg_allocErr0REQUIRES_VIOLATION, ldv_msg_allocErr1REQUIRES_VIOLATION]=== [2018-11-28 13:03:54,966 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-28 13:03:54,967 INFO L82 PathProgramCache]: Analyzing trace with hash -1929434987, now seen corresponding path program 1 times [2018-11-28 13:03:54,967 INFO L223 ckRefinementStrategy]: Switched to mode CVC4_FPBP [2018-11-28 13:03:54,967 INFO L69 tionRefinementEngine]: Using refinement strategy WolfRefinementStrategy No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_a5616418-4a25-482a-a0cb-6eefe8bc17e5/bin-2019/uautomizer/cvc4 Starting monitored process 21 with cvc4 --incremental --print-success --lang smt --rewrite-divk (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 21 with cvc4 --incremental --print-success --lang smt --rewrite-divk [2018-11-28 13:03:54,990 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-28 13:03:55,093 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-28 13:03:55,100 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-28 13:03:55,232 INFO L134 CoverageAnalysis]: Checked inductivity of 136 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 136 trivial. 0 not checked. [2018-11-28 13:03:55,232 INFO L312 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2018-11-28 13:03:55,234 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-28 13:03:55,234 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [12] imperfect sequences [] total 12 [2018-11-28 13:03:55,234 INFO L459 AbstractCegarLoop]: Interpolant automaton has 12 states [2018-11-28 13:03:55,234 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 12 interpolants. [2018-11-28 13:03:55,234 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=21, Invalid=111, Unknown=0, NotChecked=0, Total=132 [2018-11-28 13:03:55,234 INFO L87 Difference]: Start difference. First operand 146 states and 150 transitions. Second operand 12 states. [2018-11-28 13:03:55,346 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-28 13:03:55,346 INFO L93 Difference]: Finished difference Result 152 states and 155 transitions. [2018-11-28 13:03:55,347 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 12 states. [2018-11-28 13:03:55,347 INFO L78 Accepts]: Start accepts. Automaton has 12 states. Word has length 85 [2018-11-28 13:03:55,347 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-28 13:03:55,347 INFO L225 Difference]: With dead ends: 152 [2018-11-28 13:03:55,347 INFO L226 Difference]: Without dead ends: 146 [2018-11-28 13:03:55,348 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 87 GetRequests, 74 SyntacticMatches, 0 SemanticMatches, 13 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 3 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=33, Invalid=177, Unknown=0, NotChecked=0, Total=210 [2018-11-28 13:03:55,348 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 146 states. [2018-11-28 13:03:55,350 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 146 to 146. [2018-11-28 13:03:55,350 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 146 states. [2018-11-28 13:03:55,350 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 146 states to 146 states and 149 transitions. [2018-11-28 13:03:55,351 INFO L78 Accepts]: Start accepts. Automaton has 146 states and 149 transitions. Word has length 85 [2018-11-28 13:03:55,351 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-28 13:03:55,351 INFO L480 AbstractCegarLoop]: Abstraction has 146 states and 149 transitions. [2018-11-28 13:03:55,351 INFO L481 AbstractCegarLoop]: Interpolant automaton has 12 states. [2018-11-28 13:03:55,351 INFO L276 IsEmpty]: Start isEmpty. Operand 146 states and 149 transitions. [2018-11-28 13:03:55,352 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 99 [2018-11-28 13:03:55,352 INFO L394 BasicCegarLoop]: Found error trace [2018-11-28 13:03:55,352 INFO L402 BasicCegarLoop]: trace histogram [16, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-28 13:03:55,352 INFO L423 AbstractCegarLoop]: === Iteration 21 === [ldv_kref_initErr0REQUIRES_VIOLATION, ldv_kref_initErr1REQUIRES_VIOLATION, ldv_list_addErr1REQUIRES_VIOLATION, ldv_list_addErr0REQUIRES_VIOLATION, ldv_kobject_createErr1REQUIRES_VIOLATION, ldv_kobject_createErr0REQUIRES_VIOLATION, ldv_destroy_msgsErr0REQUIRES_VIOLATION, ldv_destroy_msgsErr5REQUIRES_VIOLATION, ldv_destroy_msgsErr4REQUIRES_VIOLATION, ldv_destroy_msgsErr3REQUIRES_VIOLATION, ldv_destroy_msgsErr2REQUIRES_VIOLATION, ldv_destroy_msgsErr1REQUIRES_VIOLATION, ldv_msg_fillErr1REQUIRES_VIOLATION, ldv_msg_fillErr3REQUIRES_VIOLATION, ldv_msg_fillErr2REQUIRES_VIOLATION, ldv_msg_fillErr5REQUIRES_VIOLATION, ldv_msg_fillErr0REQUIRES_VIOLATION, ldv_msg_fillErr4REQUIRES_VIOLATION, ldv_atomic_add_returnErr3REQUIRES_VIOLATION, ldv_atomic_add_returnErr2REQUIRES_VIOLATION, ldv_atomic_add_returnErr1REQUIRES_VIOLATION, ldv_atomic_add_returnErr0REQUIRES_VIOLATION, __ldv_list_delErr1REQUIRES_VIOLATION, __ldv_list_delErr2REQUIRES_VIOLATION, __ldv_list_delErr3REQUIRES_VIOLATION, __ldv_list_delErr0REQUIRES_VIOLATION, ldv_kobject_cleanupErr0REQUIRES_VIOLATION, ldv_kobject_cleanupErr3ASSERT_VIOLATIONMEMORY_FREE, ldv_kobject_cleanupErr2ASSERT_VIOLATIONMEMORY_FREE, ldv_kobject_cleanupErr5ASSERT_VIOLATIONMEMORY_FREE, ldv_kobject_cleanupErr1REQUIRES_VIOLATION, ldv_kobject_cleanupErr4ASSERT_VIOLATIONMEMORY_FREE, ldv_msg_freeErr0REQUIRES_VIOLATION, ldv_msg_freeErr3ASSERT_VIOLATIONMEMORY_FREE, ldv_msg_freeErr2ASSERT_VIOLATIONMEMORY_FREE, ldv_msg_freeErr5ASSERT_VIOLATIONMEMORY_FREE, ldv_msg_freeErr4ASSERT_VIOLATIONMEMORY_FREE, ldv_msg_freeErr1REQUIRES_VIOLATION, mainErr0ENSURES_VIOLATIONMEMORY_LEAK, LDV_INIT_LIST_HEADErr3REQUIRES_VIOLATION, LDV_INIT_LIST_HEADErr2REQUIRES_VIOLATION, LDV_INIT_LIST_HEADErr1REQUIRES_VIOLATION, LDV_INIT_LIST_HEADErr0REQUIRES_VIOLATION, ldv_list_delErr3REQUIRES_VIOLATION, ldv_list_delErr2REQUIRES_VIOLATION, ldv_list_delErr1REQUIRES_VIOLATION, ldv_list_delErr0REQUIRES_VIOLATION, __ldv_list_addErr6REQUIRES_VIOLATION, __ldv_list_addErr1REQUIRES_VIOLATION, __ldv_list_addErr7REQUIRES_VIOLATION, __ldv_list_addErr2REQUIRES_VIOLATION, __ldv_list_addErr3REQUIRES_VIOLATION, __ldv_list_addErr4REQUIRES_VIOLATION, __ldv_list_addErr5REQUIRES_VIOLATION, __ldv_list_addErr0REQUIRES_VIOLATION, ldv_dev_set_drvdataErr1REQUIRES_VIOLATION, ldv_dev_set_drvdataErr0REQUIRES_VIOLATION, ldv_atomic_sub_returnErr3REQUIRES_VIOLATION, ldv_atomic_sub_returnErr2REQUIRES_VIOLATION, ldv_atomic_sub_returnErr1REQUIRES_VIOLATION, ldv_atomic_sub_returnErr0REQUIRES_VIOLATION, ldv_list_add_tailErr0REQUIRES_VIOLATION, ldv_list_add_tailErr1REQUIRES_VIOLATION, ldv_dev_get_drvdataErr1REQUIRES_VIOLATION, ldv_dev_get_drvdataErr0REQUIRES_VIOLATION, ldv_msg_allocErr0REQUIRES_VIOLATION, ldv_msg_allocErr1REQUIRES_VIOLATION]=== [2018-11-28 13:03:55,353 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-28 13:03:55,353 INFO L82 PathProgramCache]: Analyzing trace with hash 1961126046, now seen corresponding path program 1 times [2018-11-28 13:03:55,353 INFO L223 ckRefinementStrategy]: Switched to mode CVC4_FPBP [2018-11-28 13:03:55,353 INFO L69 tionRefinementEngine]: Using refinement strategy WolfRefinementStrategy No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_a5616418-4a25-482a-a0cb-6eefe8bc17e5/bin-2019/uautomizer/cvc4 Starting monitored process 22 with cvc4 --incremental --print-success --lang smt --rewrite-divk (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 22 with cvc4 --incremental --print-success --lang smt --rewrite-divk [2018-11-28 13:03:55,388 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-28 13:03:55,607 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-28 13:03:55,613 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-28 13:03:55,616 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 6 treesize of output 5 [2018-11-28 13:03:55,616 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-11-28 13:03:55,617 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-28 13:03:55,618 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 1 variables, input treesize:6, output treesize:5 [2018-11-28 13:03:55,907 INFO L134 CoverageAnalysis]: Checked inductivity of 136 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 136 trivial. 0 not checked. [2018-11-28 13:03:55,907 INFO L312 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2018-11-28 13:03:55,910 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-28 13:03:55,910 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [19] imperfect sequences [] total 19 [2018-11-28 13:03:55,910 INFO L459 AbstractCegarLoop]: Interpolant automaton has 20 states [2018-11-28 13:03:55,911 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 20 interpolants. [2018-11-28 13:03:55,911 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=54, Invalid=326, Unknown=0, NotChecked=0, Total=380 [2018-11-28 13:03:55,911 INFO L87 Difference]: Start difference. First operand 146 states and 149 transitions. Second operand 20 states. [2018-11-28 13:03:57,366 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-28 13:03:57,366 INFO L93 Difference]: Finished difference Result 160 states and 162 transitions. [2018-11-28 13:03:57,367 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 21 states. [2018-11-28 13:03:57,367 INFO L78 Accepts]: Start accepts. Automaton has 20 states. Word has length 98 [2018-11-28 13:03:57,367 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-28 13:03:57,367 INFO L225 Difference]: With dead ends: 160 [2018-11-28 13:03:57,367 INFO L226 Difference]: Without dead ends: 160 [2018-11-28 13:03:57,368 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 102 GetRequests, 74 SyntacticMatches, 5 SemanticMatches, 23 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 36 ImplicationChecksByTransitivity, 0.3s TimeCoverageRelationStatistics Valid=79, Invalid=521, Unknown=0, NotChecked=0, Total=600 [2018-11-28 13:03:57,368 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 160 states. [2018-11-28 13:03:57,369 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 160 to 144. [2018-11-28 13:03:57,369 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 144 states. [2018-11-28 13:03:57,370 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 144 states to 144 states and 147 transitions. [2018-11-28 13:03:57,370 INFO L78 Accepts]: Start accepts. Automaton has 144 states and 147 transitions. Word has length 98 [2018-11-28 13:03:57,370 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-28 13:03:57,371 INFO L480 AbstractCegarLoop]: Abstraction has 144 states and 147 transitions. [2018-11-28 13:03:57,371 INFO L481 AbstractCegarLoop]: Interpolant automaton has 20 states. [2018-11-28 13:03:57,371 INFO L276 IsEmpty]: Start isEmpty. Operand 144 states and 147 transitions. [2018-11-28 13:03:57,371 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 99 [2018-11-28 13:03:57,371 INFO L394 BasicCegarLoop]: Found error trace [2018-11-28 13:03:57,372 INFO L402 BasicCegarLoop]: trace histogram [16, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-28 13:03:57,372 INFO L423 AbstractCegarLoop]: === Iteration 22 === [ldv_kref_initErr0REQUIRES_VIOLATION, ldv_kref_initErr1REQUIRES_VIOLATION, ldv_list_addErr1REQUIRES_VIOLATION, ldv_list_addErr0REQUIRES_VIOLATION, ldv_kobject_createErr1REQUIRES_VIOLATION, ldv_kobject_createErr0REQUIRES_VIOLATION, ldv_destroy_msgsErr0REQUIRES_VIOLATION, ldv_destroy_msgsErr5REQUIRES_VIOLATION, ldv_destroy_msgsErr4REQUIRES_VIOLATION, ldv_destroy_msgsErr3REQUIRES_VIOLATION, ldv_destroy_msgsErr2REQUIRES_VIOLATION, ldv_destroy_msgsErr1REQUIRES_VIOLATION, ldv_msg_fillErr1REQUIRES_VIOLATION, ldv_msg_fillErr3REQUIRES_VIOLATION, ldv_msg_fillErr2REQUIRES_VIOLATION, ldv_msg_fillErr5REQUIRES_VIOLATION, ldv_msg_fillErr0REQUIRES_VIOLATION, ldv_msg_fillErr4REQUIRES_VIOLATION, ldv_atomic_add_returnErr3REQUIRES_VIOLATION, ldv_atomic_add_returnErr2REQUIRES_VIOLATION, ldv_atomic_add_returnErr1REQUIRES_VIOLATION, ldv_atomic_add_returnErr0REQUIRES_VIOLATION, __ldv_list_delErr1REQUIRES_VIOLATION, __ldv_list_delErr2REQUIRES_VIOLATION, __ldv_list_delErr3REQUIRES_VIOLATION, __ldv_list_delErr0REQUIRES_VIOLATION, ldv_kobject_cleanupErr0REQUIRES_VIOLATION, ldv_kobject_cleanupErr3ASSERT_VIOLATIONMEMORY_FREE, ldv_kobject_cleanupErr2ASSERT_VIOLATIONMEMORY_FREE, ldv_kobject_cleanupErr5ASSERT_VIOLATIONMEMORY_FREE, ldv_kobject_cleanupErr1REQUIRES_VIOLATION, ldv_kobject_cleanupErr4ASSERT_VIOLATIONMEMORY_FREE, ldv_msg_freeErr0REQUIRES_VIOLATION, ldv_msg_freeErr3ASSERT_VIOLATIONMEMORY_FREE, ldv_msg_freeErr2ASSERT_VIOLATIONMEMORY_FREE, ldv_msg_freeErr5ASSERT_VIOLATIONMEMORY_FREE, ldv_msg_freeErr4ASSERT_VIOLATIONMEMORY_FREE, ldv_msg_freeErr1REQUIRES_VIOLATION, mainErr0ENSURES_VIOLATIONMEMORY_LEAK, LDV_INIT_LIST_HEADErr3REQUIRES_VIOLATION, LDV_INIT_LIST_HEADErr2REQUIRES_VIOLATION, LDV_INIT_LIST_HEADErr1REQUIRES_VIOLATION, LDV_INIT_LIST_HEADErr0REQUIRES_VIOLATION, ldv_list_delErr3REQUIRES_VIOLATION, ldv_list_delErr2REQUIRES_VIOLATION, ldv_list_delErr1REQUIRES_VIOLATION, ldv_list_delErr0REQUIRES_VIOLATION, __ldv_list_addErr6REQUIRES_VIOLATION, __ldv_list_addErr1REQUIRES_VIOLATION, __ldv_list_addErr7REQUIRES_VIOLATION, __ldv_list_addErr2REQUIRES_VIOLATION, __ldv_list_addErr3REQUIRES_VIOLATION, __ldv_list_addErr4REQUIRES_VIOLATION, __ldv_list_addErr5REQUIRES_VIOLATION, __ldv_list_addErr0REQUIRES_VIOLATION, ldv_dev_set_drvdataErr1REQUIRES_VIOLATION, ldv_dev_set_drvdataErr0REQUIRES_VIOLATION, ldv_atomic_sub_returnErr3REQUIRES_VIOLATION, ldv_atomic_sub_returnErr2REQUIRES_VIOLATION, ldv_atomic_sub_returnErr1REQUIRES_VIOLATION, ldv_atomic_sub_returnErr0REQUIRES_VIOLATION, ldv_list_add_tailErr0REQUIRES_VIOLATION, ldv_list_add_tailErr1REQUIRES_VIOLATION, ldv_dev_get_drvdataErr1REQUIRES_VIOLATION, ldv_dev_get_drvdataErr0REQUIRES_VIOLATION, ldv_msg_allocErr0REQUIRES_VIOLATION, ldv_msg_allocErr1REQUIRES_VIOLATION]=== [2018-11-28 13:03:57,375 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-28 13:03:57,376 INFO L82 PathProgramCache]: Analyzing trace with hash 1961126047, now seen corresponding path program 1 times [2018-11-28 13:03:57,376 INFO L223 ckRefinementStrategy]: Switched to mode CVC4_FPBP [2018-11-28 13:03:57,376 INFO L69 tionRefinementEngine]: Using refinement strategy WolfRefinementStrategy No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_a5616418-4a25-482a-a0cb-6eefe8bc17e5/bin-2019/uautomizer/cvc4 Starting monitored process 23 with cvc4 --incremental --print-success --lang smt --rewrite-divk (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 23 with cvc4 --incremental --print-success --lang smt --rewrite-divk [2018-11-28 13:03:57,404 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-28 13:03:57,686 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-28 13:03:57,693 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-28 13:03:57,702 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 6 treesize of output 5 [2018-11-28 13:03:57,702 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-11-28 13:03:57,711 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-28 13:03:57,712 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 1 variables, input treesize:10, output treesize:9 [2018-11-28 13:03:58,144 INFO L134 CoverageAnalysis]: Checked inductivity of 136 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 136 trivial. 0 not checked. [2018-11-28 13:03:58,144 INFO L312 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2018-11-28 13:03:58,147 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-28 13:03:58,147 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [19] imperfect sequences [] total 19 [2018-11-28 13:03:58,147 INFO L459 AbstractCegarLoop]: Interpolant automaton has 20 states [2018-11-28 13:03:58,148 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 20 interpolants. [2018-11-28 13:03:58,148 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=52, Invalid=328, Unknown=0, NotChecked=0, Total=380 [2018-11-28 13:03:58,148 INFO L87 Difference]: Start difference. First operand 144 states and 147 transitions. Second operand 20 states. [2018-11-28 13:03:59,579 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-28 13:03:59,579 INFO L93 Difference]: Finished difference Result 142 states and 145 transitions. [2018-11-28 13:03:59,580 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 20 states. [2018-11-28 13:03:59,580 INFO L78 Accepts]: Start accepts. Automaton has 20 states. Word has length 98 [2018-11-28 13:03:59,580 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-28 13:03:59,580 INFO L225 Difference]: With dead ends: 142 [2018-11-28 13:03:59,581 INFO L226 Difference]: Without dead ends: 142 [2018-11-28 13:03:59,581 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 103 GetRequests, 74 SyntacticMatches, 5 SemanticMatches, 24 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 51 ImplicationChecksByTransitivity, 0.5s TimeCoverageRelationStatistics Valid=81, Invalid=569, Unknown=0, NotChecked=0, Total=650 [2018-11-28 13:03:59,581 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 142 states. [2018-11-28 13:03:59,583 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 142 to 142. [2018-11-28 13:03:59,583 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 142 states. [2018-11-28 13:03:59,583 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 142 states to 142 states and 145 transitions. [2018-11-28 13:03:59,584 INFO L78 Accepts]: Start accepts. Automaton has 142 states and 145 transitions. Word has length 98 [2018-11-28 13:03:59,584 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-28 13:03:59,584 INFO L480 AbstractCegarLoop]: Abstraction has 142 states and 145 transitions. [2018-11-28 13:03:59,584 INFO L481 AbstractCegarLoop]: Interpolant automaton has 20 states. [2018-11-28 13:03:59,584 INFO L276 IsEmpty]: Start isEmpty. Operand 142 states and 145 transitions. [2018-11-28 13:03:59,584 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 97 [2018-11-28 13:03:59,585 INFO L394 BasicCegarLoop]: Found error trace [2018-11-28 13:03:59,585 INFO L402 BasicCegarLoop]: trace histogram [16, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-28 13:03:59,585 INFO L423 AbstractCegarLoop]: === Iteration 23 === [ldv_kref_initErr0REQUIRES_VIOLATION, ldv_kref_initErr1REQUIRES_VIOLATION, ldv_list_addErr1REQUIRES_VIOLATION, ldv_list_addErr0REQUIRES_VIOLATION, ldv_kobject_createErr1REQUIRES_VIOLATION, ldv_kobject_createErr0REQUIRES_VIOLATION, ldv_destroy_msgsErr0REQUIRES_VIOLATION, ldv_destroy_msgsErr5REQUIRES_VIOLATION, ldv_destroy_msgsErr4REQUIRES_VIOLATION, ldv_destroy_msgsErr3REQUIRES_VIOLATION, ldv_destroy_msgsErr2REQUIRES_VIOLATION, ldv_destroy_msgsErr1REQUIRES_VIOLATION, ldv_msg_fillErr1REQUIRES_VIOLATION, ldv_msg_fillErr3REQUIRES_VIOLATION, ldv_msg_fillErr2REQUIRES_VIOLATION, ldv_msg_fillErr5REQUIRES_VIOLATION, ldv_msg_fillErr0REQUIRES_VIOLATION, ldv_msg_fillErr4REQUIRES_VIOLATION, ldv_atomic_add_returnErr3REQUIRES_VIOLATION, ldv_atomic_add_returnErr2REQUIRES_VIOLATION, ldv_atomic_add_returnErr1REQUIRES_VIOLATION, ldv_atomic_add_returnErr0REQUIRES_VIOLATION, __ldv_list_delErr1REQUIRES_VIOLATION, __ldv_list_delErr2REQUIRES_VIOLATION, __ldv_list_delErr3REQUIRES_VIOLATION, __ldv_list_delErr0REQUIRES_VIOLATION, ldv_kobject_cleanupErr0REQUIRES_VIOLATION, ldv_kobject_cleanupErr3ASSERT_VIOLATIONMEMORY_FREE, ldv_kobject_cleanupErr2ASSERT_VIOLATIONMEMORY_FREE, ldv_kobject_cleanupErr5ASSERT_VIOLATIONMEMORY_FREE, ldv_kobject_cleanupErr1REQUIRES_VIOLATION, ldv_kobject_cleanupErr4ASSERT_VIOLATIONMEMORY_FREE, ldv_msg_freeErr0REQUIRES_VIOLATION, ldv_msg_freeErr3ASSERT_VIOLATIONMEMORY_FREE, ldv_msg_freeErr2ASSERT_VIOLATIONMEMORY_FREE, ldv_msg_freeErr5ASSERT_VIOLATIONMEMORY_FREE, ldv_msg_freeErr4ASSERT_VIOLATIONMEMORY_FREE, ldv_msg_freeErr1REQUIRES_VIOLATION, mainErr0ENSURES_VIOLATIONMEMORY_LEAK, LDV_INIT_LIST_HEADErr3REQUIRES_VIOLATION, LDV_INIT_LIST_HEADErr2REQUIRES_VIOLATION, LDV_INIT_LIST_HEADErr1REQUIRES_VIOLATION, LDV_INIT_LIST_HEADErr0REQUIRES_VIOLATION, ldv_list_delErr3REQUIRES_VIOLATION, ldv_list_delErr2REQUIRES_VIOLATION, ldv_list_delErr1REQUIRES_VIOLATION, ldv_list_delErr0REQUIRES_VIOLATION, __ldv_list_addErr6REQUIRES_VIOLATION, __ldv_list_addErr1REQUIRES_VIOLATION, __ldv_list_addErr7REQUIRES_VIOLATION, __ldv_list_addErr2REQUIRES_VIOLATION, __ldv_list_addErr3REQUIRES_VIOLATION, __ldv_list_addErr4REQUIRES_VIOLATION, __ldv_list_addErr5REQUIRES_VIOLATION, __ldv_list_addErr0REQUIRES_VIOLATION, ldv_dev_set_drvdataErr1REQUIRES_VIOLATION, ldv_dev_set_drvdataErr0REQUIRES_VIOLATION, ldv_atomic_sub_returnErr3REQUIRES_VIOLATION, ldv_atomic_sub_returnErr2REQUIRES_VIOLATION, ldv_atomic_sub_returnErr1REQUIRES_VIOLATION, ldv_atomic_sub_returnErr0REQUIRES_VIOLATION, ldv_list_add_tailErr0REQUIRES_VIOLATION, ldv_list_add_tailErr1REQUIRES_VIOLATION, ldv_dev_get_drvdataErr1REQUIRES_VIOLATION, ldv_dev_get_drvdataErr0REQUIRES_VIOLATION, ldv_msg_allocErr0REQUIRES_VIOLATION, ldv_msg_allocErr1REQUIRES_VIOLATION]=== [2018-11-28 13:03:59,585 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-28 13:03:59,585 INFO L82 PathProgramCache]: Analyzing trace with hash -456213325, now seen corresponding path program 1 times [2018-11-28 13:03:59,586 INFO L223 ckRefinementStrategy]: Switched to mode CVC4_FPBP [2018-11-28 13:03:59,586 INFO L69 tionRefinementEngine]: Using refinement strategy WolfRefinementStrategy No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_a5616418-4a25-482a-a0cb-6eefe8bc17e5/bin-2019/uautomizer/cvc4 Starting monitored process 24 with cvc4 --incremental --print-success --lang smt --rewrite-divk (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 24 with cvc4 --incremental --print-success --lang smt --rewrite-divk [2018-11-28 13:03:59,609 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-28 13:03:59,676 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-28 13:03:59,680 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-28 13:03:59,769 INFO L134 CoverageAnalysis]: Checked inductivity of 136 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 136 trivial. 0 not checked. [2018-11-28 13:03:59,769 INFO L312 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2018-11-28 13:03:59,771 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-28 13:03:59,771 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [10] imperfect sequences [] total 10 [2018-11-28 13:03:59,771 INFO L459 AbstractCegarLoop]: Interpolant automaton has 10 states [2018-11-28 13:03:59,771 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 10 interpolants. [2018-11-28 13:03:59,771 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=17, Invalid=73, Unknown=0, NotChecked=0, Total=90 [2018-11-28 13:03:59,771 INFO L87 Difference]: Start difference. First operand 142 states and 145 transitions. Second operand 10 states. [2018-11-28 13:03:59,831 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-28 13:03:59,831 INFO L93 Difference]: Finished difference Result 144 states and 146 transitions. [2018-11-28 13:03:59,831 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 10 states. [2018-11-28 13:03:59,831 INFO L78 Accepts]: Start accepts. Automaton has 10 states. Word has length 96 [2018-11-28 13:03:59,832 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-28 13:03:59,832 INFO L225 Difference]: With dead ends: 144 [2018-11-28 13:03:59,832 INFO L226 Difference]: Without dead ends: 142 [2018-11-28 13:03:59,832 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 97 GetRequests, 87 SyntacticMatches, 0 SemanticMatches, 10 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=25, Invalid=107, Unknown=0, NotChecked=0, Total=132 [2018-11-28 13:03:59,833 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 142 states. [2018-11-28 13:03:59,834 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 142 to 142. [2018-11-28 13:03:59,834 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 142 states. [2018-11-28 13:03:59,835 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 142 states to 142 states and 144 transitions. [2018-11-28 13:03:59,835 INFO L78 Accepts]: Start accepts. Automaton has 142 states and 144 transitions. Word has length 96 [2018-11-28 13:03:59,835 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-28 13:03:59,835 INFO L480 AbstractCegarLoop]: Abstraction has 142 states and 144 transitions. [2018-11-28 13:03:59,835 INFO L481 AbstractCegarLoop]: Interpolant automaton has 10 states. [2018-11-28 13:03:59,835 INFO L276 IsEmpty]: Start isEmpty. Operand 142 states and 144 transitions. [2018-11-28 13:03:59,836 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 112 [2018-11-28 13:03:59,837 INFO L394 BasicCegarLoop]: Found error trace [2018-11-28 13:03:59,838 INFO L402 BasicCegarLoop]: trace histogram [16, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-28 13:03:59,838 INFO L423 AbstractCegarLoop]: === Iteration 24 === [ldv_kref_initErr0REQUIRES_VIOLATION, ldv_kref_initErr1REQUIRES_VIOLATION, ldv_list_addErr1REQUIRES_VIOLATION, ldv_list_addErr0REQUIRES_VIOLATION, ldv_kobject_createErr1REQUIRES_VIOLATION, ldv_kobject_createErr0REQUIRES_VIOLATION, ldv_destroy_msgsErr0REQUIRES_VIOLATION, ldv_destroy_msgsErr5REQUIRES_VIOLATION, ldv_destroy_msgsErr4REQUIRES_VIOLATION, ldv_destroy_msgsErr3REQUIRES_VIOLATION, ldv_destroy_msgsErr2REQUIRES_VIOLATION, ldv_destroy_msgsErr1REQUIRES_VIOLATION, ldv_msg_fillErr1REQUIRES_VIOLATION, ldv_msg_fillErr3REQUIRES_VIOLATION, ldv_msg_fillErr2REQUIRES_VIOLATION, ldv_msg_fillErr5REQUIRES_VIOLATION, ldv_msg_fillErr0REQUIRES_VIOLATION, ldv_msg_fillErr4REQUIRES_VIOLATION, ldv_atomic_add_returnErr3REQUIRES_VIOLATION, ldv_atomic_add_returnErr2REQUIRES_VIOLATION, ldv_atomic_add_returnErr1REQUIRES_VIOLATION, ldv_atomic_add_returnErr0REQUIRES_VIOLATION, __ldv_list_delErr1REQUIRES_VIOLATION, __ldv_list_delErr2REQUIRES_VIOLATION, __ldv_list_delErr3REQUIRES_VIOLATION, __ldv_list_delErr0REQUIRES_VIOLATION, ldv_kobject_cleanupErr0REQUIRES_VIOLATION, ldv_kobject_cleanupErr3ASSERT_VIOLATIONMEMORY_FREE, ldv_kobject_cleanupErr2ASSERT_VIOLATIONMEMORY_FREE, ldv_kobject_cleanupErr5ASSERT_VIOLATIONMEMORY_FREE, ldv_kobject_cleanupErr1REQUIRES_VIOLATION, ldv_kobject_cleanupErr4ASSERT_VIOLATIONMEMORY_FREE, ldv_msg_freeErr0REQUIRES_VIOLATION, ldv_msg_freeErr3ASSERT_VIOLATIONMEMORY_FREE, ldv_msg_freeErr2ASSERT_VIOLATIONMEMORY_FREE, ldv_msg_freeErr5ASSERT_VIOLATIONMEMORY_FREE, ldv_msg_freeErr4ASSERT_VIOLATIONMEMORY_FREE, ldv_msg_freeErr1REQUIRES_VIOLATION, mainErr0ENSURES_VIOLATIONMEMORY_LEAK, LDV_INIT_LIST_HEADErr3REQUIRES_VIOLATION, LDV_INIT_LIST_HEADErr2REQUIRES_VIOLATION, LDV_INIT_LIST_HEADErr1REQUIRES_VIOLATION, LDV_INIT_LIST_HEADErr0REQUIRES_VIOLATION, ldv_list_delErr3REQUIRES_VIOLATION, ldv_list_delErr2REQUIRES_VIOLATION, ldv_list_delErr1REQUIRES_VIOLATION, ldv_list_delErr0REQUIRES_VIOLATION, __ldv_list_addErr6REQUIRES_VIOLATION, __ldv_list_addErr1REQUIRES_VIOLATION, __ldv_list_addErr7REQUIRES_VIOLATION, __ldv_list_addErr2REQUIRES_VIOLATION, __ldv_list_addErr3REQUIRES_VIOLATION, __ldv_list_addErr4REQUIRES_VIOLATION, __ldv_list_addErr5REQUIRES_VIOLATION, __ldv_list_addErr0REQUIRES_VIOLATION, ldv_dev_set_drvdataErr1REQUIRES_VIOLATION, ldv_dev_set_drvdataErr0REQUIRES_VIOLATION, ldv_atomic_sub_returnErr3REQUIRES_VIOLATION, ldv_atomic_sub_returnErr2REQUIRES_VIOLATION, ldv_atomic_sub_returnErr1REQUIRES_VIOLATION, ldv_atomic_sub_returnErr0REQUIRES_VIOLATION, ldv_list_add_tailErr0REQUIRES_VIOLATION, ldv_list_add_tailErr1REQUIRES_VIOLATION, ldv_dev_get_drvdataErr1REQUIRES_VIOLATION, ldv_dev_get_drvdataErr0REQUIRES_VIOLATION, ldv_msg_allocErr0REQUIRES_VIOLATION, ldv_msg_allocErr1REQUIRES_VIOLATION]=== [2018-11-28 13:03:59,838 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-28 13:03:59,838 INFO L82 PathProgramCache]: Analyzing trace with hash -1610192467, now seen corresponding path program 1 times [2018-11-28 13:03:59,839 INFO L223 ckRefinementStrategy]: Switched to mode CVC4_FPBP [2018-11-28 13:03:59,839 INFO L69 tionRefinementEngine]: Using refinement strategy WolfRefinementStrategy No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_a5616418-4a25-482a-a0cb-6eefe8bc17e5/bin-2019/uautomizer/cvc4 Starting monitored process 25 with cvc4 --incremental --print-success --lang smt --rewrite-divk (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 25 with cvc4 --incremental --print-success --lang smt --rewrite-divk [2018-11-28 13:03:59,861 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-28 13:04:00,093 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-28 13:04:00,114 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-28 13:04:00,117 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 6 treesize of output 5 [2018-11-28 13:04:00,117 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-11-28 13:04:00,118 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-28 13:04:00,119 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 1 variables, input treesize:6, output treesize:5 [2018-11-28 13:04:00,538 INFO L134 CoverageAnalysis]: Checked inductivity of 136 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 136 trivial. 0 not checked. [2018-11-28 13:04:00,538 INFO L312 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2018-11-28 13:04:00,541 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-28 13:04:00,541 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [23] imperfect sequences [] total 23 [2018-11-28 13:04:00,541 INFO L459 AbstractCegarLoop]: Interpolant automaton has 24 states [2018-11-28 13:04:00,541 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 24 interpolants. [2018-11-28 13:04:00,542 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=66, Invalid=486, Unknown=0, NotChecked=0, Total=552 [2018-11-28 13:04:00,542 INFO L87 Difference]: Start difference. First operand 142 states and 144 transitions. Second operand 24 states. [2018-11-28 13:04:02,276 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-28 13:04:02,276 INFO L93 Difference]: Finished difference Result 152 states and 153 transitions. [2018-11-28 13:04:02,276 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 25 states. [2018-11-28 13:04:02,276 INFO L78 Accepts]: Start accepts. Automaton has 24 states. Word has length 111 [2018-11-28 13:04:02,277 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-28 13:04:02,277 INFO L225 Difference]: With dead ends: 152 [2018-11-28 13:04:02,277 INFO L226 Difference]: Without dead ends: 152 [2018-11-28 13:04:02,278 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 117 GetRequests, 81 SyntacticMatches, 7 SemanticMatches, 29 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 64 ImplicationChecksByTransitivity, 0.5s TimeCoverageRelationStatistics Valid=101, Invalid=829, Unknown=0, NotChecked=0, Total=930 [2018-11-28 13:04:02,278 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 152 states. [2018-11-28 13:04:02,280 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 152 to 140. [2018-11-28 13:04:02,280 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 140 states. [2018-11-28 13:04:02,281 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 140 states to 140 states and 142 transitions. [2018-11-28 13:04:02,281 INFO L78 Accepts]: Start accepts. Automaton has 140 states and 142 transitions. Word has length 111 [2018-11-28 13:04:02,281 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-28 13:04:02,281 INFO L480 AbstractCegarLoop]: Abstraction has 140 states and 142 transitions. [2018-11-28 13:04:02,281 INFO L481 AbstractCegarLoop]: Interpolant automaton has 24 states. [2018-11-28 13:04:02,281 INFO L276 IsEmpty]: Start isEmpty. Operand 140 states and 142 transitions. [2018-11-28 13:04:02,282 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 112 [2018-11-28 13:04:02,282 INFO L394 BasicCegarLoop]: Found error trace [2018-11-28 13:04:02,282 INFO L402 BasicCegarLoop]: trace histogram [16, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-28 13:04:02,282 INFO L423 AbstractCegarLoop]: === Iteration 25 === [ldv_kref_initErr0REQUIRES_VIOLATION, ldv_kref_initErr1REQUIRES_VIOLATION, ldv_list_addErr1REQUIRES_VIOLATION, ldv_list_addErr0REQUIRES_VIOLATION, ldv_kobject_createErr1REQUIRES_VIOLATION, ldv_kobject_createErr0REQUIRES_VIOLATION, ldv_destroy_msgsErr0REQUIRES_VIOLATION, ldv_destroy_msgsErr5REQUIRES_VIOLATION, ldv_destroy_msgsErr4REQUIRES_VIOLATION, ldv_destroy_msgsErr3REQUIRES_VIOLATION, ldv_destroy_msgsErr2REQUIRES_VIOLATION, ldv_destroy_msgsErr1REQUIRES_VIOLATION, ldv_msg_fillErr1REQUIRES_VIOLATION, ldv_msg_fillErr3REQUIRES_VIOLATION, ldv_msg_fillErr2REQUIRES_VIOLATION, ldv_msg_fillErr5REQUIRES_VIOLATION, ldv_msg_fillErr0REQUIRES_VIOLATION, ldv_msg_fillErr4REQUIRES_VIOLATION, ldv_atomic_add_returnErr3REQUIRES_VIOLATION, ldv_atomic_add_returnErr2REQUIRES_VIOLATION, ldv_atomic_add_returnErr1REQUIRES_VIOLATION, ldv_atomic_add_returnErr0REQUIRES_VIOLATION, __ldv_list_delErr1REQUIRES_VIOLATION, __ldv_list_delErr2REQUIRES_VIOLATION, __ldv_list_delErr3REQUIRES_VIOLATION, __ldv_list_delErr0REQUIRES_VIOLATION, ldv_kobject_cleanupErr0REQUIRES_VIOLATION, ldv_kobject_cleanupErr3ASSERT_VIOLATIONMEMORY_FREE, ldv_kobject_cleanupErr2ASSERT_VIOLATIONMEMORY_FREE, ldv_kobject_cleanupErr5ASSERT_VIOLATIONMEMORY_FREE, ldv_kobject_cleanupErr1REQUIRES_VIOLATION, ldv_kobject_cleanupErr4ASSERT_VIOLATIONMEMORY_FREE, ldv_msg_freeErr0REQUIRES_VIOLATION, ldv_msg_freeErr3ASSERT_VIOLATIONMEMORY_FREE, ldv_msg_freeErr2ASSERT_VIOLATIONMEMORY_FREE, ldv_msg_freeErr5ASSERT_VIOLATIONMEMORY_FREE, ldv_msg_freeErr4ASSERT_VIOLATIONMEMORY_FREE, ldv_msg_freeErr1REQUIRES_VIOLATION, mainErr0ENSURES_VIOLATIONMEMORY_LEAK, LDV_INIT_LIST_HEADErr3REQUIRES_VIOLATION, LDV_INIT_LIST_HEADErr2REQUIRES_VIOLATION, LDV_INIT_LIST_HEADErr1REQUIRES_VIOLATION, LDV_INIT_LIST_HEADErr0REQUIRES_VIOLATION, ldv_list_delErr3REQUIRES_VIOLATION, ldv_list_delErr2REQUIRES_VIOLATION, ldv_list_delErr1REQUIRES_VIOLATION, ldv_list_delErr0REQUIRES_VIOLATION, __ldv_list_addErr6REQUIRES_VIOLATION, __ldv_list_addErr1REQUIRES_VIOLATION, __ldv_list_addErr7REQUIRES_VIOLATION, __ldv_list_addErr2REQUIRES_VIOLATION, __ldv_list_addErr3REQUIRES_VIOLATION, __ldv_list_addErr4REQUIRES_VIOLATION, __ldv_list_addErr5REQUIRES_VIOLATION, __ldv_list_addErr0REQUIRES_VIOLATION, ldv_dev_set_drvdataErr1REQUIRES_VIOLATION, ldv_dev_set_drvdataErr0REQUIRES_VIOLATION, ldv_atomic_sub_returnErr3REQUIRES_VIOLATION, ldv_atomic_sub_returnErr2REQUIRES_VIOLATION, ldv_atomic_sub_returnErr1REQUIRES_VIOLATION, ldv_atomic_sub_returnErr0REQUIRES_VIOLATION, ldv_list_add_tailErr0REQUIRES_VIOLATION, ldv_list_add_tailErr1REQUIRES_VIOLATION, ldv_dev_get_drvdataErr1REQUIRES_VIOLATION, ldv_dev_get_drvdataErr0REQUIRES_VIOLATION, ldv_msg_allocErr0REQUIRES_VIOLATION, ldv_msg_allocErr1REQUIRES_VIOLATION]=== [2018-11-28 13:04:02,282 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-28 13:04:02,283 INFO L82 PathProgramCache]: Analyzing trace with hash -1610192466, now seen corresponding path program 1 times [2018-11-28 13:04:02,283 INFO L223 ckRefinementStrategy]: Switched to mode CVC4_FPBP [2018-11-28 13:04:02,283 INFO L69 tionRefinementEngine]: Using refinement strategy WolfRefinementStrategy No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_a5616418-4a25-482a-a0cb-6eefe8bc17e5/bin-2019/uautomizer/cvc4 Starting monitored process 26 with cvc4 --incremental --print-success --lang smt --rewrite-divk (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 26 with cvc4 --incremental --print-success --lang smt --rewrite-divk [2018-11-28 13:04:02,312 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-28 13:04:02,651 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-28 13:04:02,660 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-28 13:04:02,685 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 6 treesize of output 5 [2018-11-28 13:04:02,686 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-11-28 13:04:02,700 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-28 13:04:02,701 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 1 variables, input treesize:10, output treesize:9 [2018-11-28 13:04:03,335 INFO L134 CoverageAnalysis]: Checked inductivity of 136 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 136 trivial. 0 not checked. [2018-11-28 13:04:03,335 INFO L312 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2018-11-28 13:04:03,339 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-28 13:04:03,339 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [23] imperfect sequences [] total 23 [2018-11-28 13:04:03,340 INFO L459 AbstractCegarLoop]: Interpolant automaton has 24 states [2018-11-28 13:04:03,340 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 24 interpolants. [2018-11-28 13:04:03,340 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=64, Invalid=488, Unknown=0, NotChecked=0, Total=552 [2018-11-28 13:04:03,340 INFO L87 Difference]: Start difference. First operand 140 states and 142 transitions. Second operand 24 states. [2018-11-28 13:04:05,059 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-28 13:04:05,059 INFO L93 Difference]: Finished difference Result 138 states and 140 transitions. [2018-11-28 13:04:05,059 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 24 states. [2018-11-28 13:04:05,059 INFO L78 Accepts]: Start accepts. Automaton has 24 states. Word has length 111 [2018-11-28 13:04:05,059 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-28 13:04:05,060 INFO L225 Difference]: With dead ends: 138 [2018-11-28 13:04:05,060 INFO L226 Difference]: Without dead ends: 138 [2018-11-28 13:04:05,060 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 118 GetRequests, 81 SyntacticMatches, 7 SemanticMatches, 30 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 84 ImplicationChecksByTransitivity, 0.7s TimeCoverageRelationStatistics Valid=103, Invalid=889, Unknown=0, NotChecked=0, Total=992 [2018-11-28 13:04:05,060 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 138 states. [2018-11-28 13:04:05,061 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 138 to 138. [2018-11-28 13:04:05,061 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 138 states. [2018-11-28 13:04:05,062 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 138 states to 138 states and 140 transitions. [2018-11-28 13:04:05,062 INFO L78 Accepts]: Start accepts. Automaton has 138 states and 140 transitions. Word has length 111 [2018-11-28 13:04:05,062 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-28 13:04:05,062 INFO L480 AbstractCegarLoop]: Abstraction has 138 states and 140 transitions. [2018-11-28 13:04:05,062 INFO L481 AbstractCegarLoop]: Interpolant automaton has 24 states. [2018-11-28 13:04:05,062 INFO L276 IsEmpty]: Start isEmpty. Operand 138 states and 140 transitions. [2018-11-28 13:04:05,063 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 117 [2018-11-28 13:04:05,063 INFO L394 BasicCegarLoop]: Found error trace [2018-11-28 13:04:05,063 INFO L402 BasicCegarLoop]: trace histogram [16, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-28 13:04:05,063 INFO L423 AbstractCegarLoop]: === Iteration 26 === [ldv_kref_initErr0REQUIRES_VIOLATION, ldv_kref_initErr1REQUIRES_VIOLATION, ldv_list_addErr1REQUIRES_VIOLATION, ldv_list_addErr0REQUIRES_VIOLATION, ldv_kobject_createErr1REQUIRES_VIOLATION, ldv_kobject_createErr0REQUIRES_VIOLATION, ldv_destroy_msgsErr0REQUIRES_VIOLATION, ldv_destroy_msgsErr5REQUIRES_VIOLATION, ldv_destroy_msgsErr4REQUIRES_VIOLATION, ldv_destroy_msgsErr3REQUIRES_VIOLATION, ldv_destroy_msgsErr2REQUIRES_VIOLATION, ldv_destroy_msgsErr1REQUIRES_VIOLATION, ldv_msg_fillErr1REQUIRES_VIOLATION, ldv_msg_fillErr3REQUIRES_VIOLATION, ldv_msg_fillErr2REQUIRES_VIOLATION, ldv_msg_fillErr5REQUIRES_VIOLATION, ldv_msg_fillErr0REQUIRES_VIOLATION, ldv_msg_fillErr4REQUIRES_VIOLATION, ldv_atomic_add_returnErr3REQUIRES_VIOLATION, ldv_atomic_add_returnErr2REQUIRES_VIOLATION, ldv_atomic_add_returnErr1REQUIRES_VIOLATION, ldv_atomic_add_returnErr0REQUIRES_VIOLATION, __ldv_list_delErr1REQUIRES_VIOLATION, __ldv_list_delErr2REQUIRES_VIOLATION, __ldv_list_delErr3REQUIRES_VIOLATION, __ldv_list_delErr0REQUIRES_VIOLATION, ldv_kobject_cleanupErr0REQUIRES_VIOLATION, ldv_kobject_cleanupErr3ASSERT_VIOLATIONMEMORY_FREE, ldv_kobject_cleanupErr2ASSERT_VIOLATIONMEMORY_FREE, ldv_kobject_cleanupErr5ASSERT_VIOLATIONMEMORY_FREE, ldv_kobject_cleanupErr1REQUIRES_VIOLATION, ldv_kobject_cleanupErr4ASSERT_VIOLATIONMEMORY_FREE, ldv_msg_freeErr0REQUIRES_VIOLATION, ldv_msg_freeErr3ASSERT_VIOLATIONMEMORY_FREE, ldv_msg_freeErr2ASSERT_VIOLATIONMEMORY_FREE, ldv_msg_freeErr5ASSERT_VIOLATIONMEMORY_FREE, ldv_msg_freeErr4ASSERT_VIOLATIONMEMORY_FREE, ldv_msg_freeErr1REQUIRES_VIOLATION, mainErr0ENSURES_VIOLATIONMEMORY_LEAK, LDV_INIT_LIST_HEADErr3REQUIRES_VIOLATION, LDV_INIT_LIST_HEADErr2REQUIRES_VIOLATION, LDV_INIT_LIST_HEADErr1REQUIRES_VIOLATION, LDV_INIT_LIST_HEADErr0REQUIRES_VIOLATION, ldv_list_delErr3REQUIRES_VIOLATION, ldv_list_delErr2REQUIRES_VIOLATION, ldv_list_delErr1REQUIRES_VIOLATION, ldv_list_delErr0REQUIRES_VIOLATION, __ldv_list_addErr6REQUIRES_VIOLATION, __ldv_list_addErr1REQUIRES_VIOLATION, __ldv_list_addErr7REQUIRES_VIOLATION, __ldv_list_addErr2REQUIRES_VIOLATION, __ldv_list_addErr3REQUIRES_VIOLATION, __ldv_list_addErr4REQUIRES_VIOLATION, __ldv_list_addErr5REQUIRES_VIOLATION, __ldv_list_addErr0REQUIRES_VIOLATION, ldv_dev_set_drvdataErr1REQUIRES_VIOLATION, ldv_dev_set_drvdataErr0REQUIRES_VIOLATION, ldv_atomic_sub_returnErr3REQUIRES_VIOLATION, ldv_atomic_sub_returnErr2REQUIRES_VIOLATION, ldv_atomic_sub_returnErr1REQUIRES_VIOLATION, ldv_atomic_sub_returnErr0REQUIRES_VIOLATION, ldv_list_add_tailErr0REQUIRES_VIOLATION, ldv_list_add_tailErr1REQUIRES_VIOLATION, ldv_dev_get_drvdataErr1REQUIRES_VIOLATION, ldv_dev_get_drvdataErr0REQUIRES_VIOLATION, ldv_msg_allocErr0REQUIRES_VIOLATION, ldv_msg_allocErr1REQUIRES_VIOLATION]=== [2018-11-28 13:04:05,063 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-28 13:04:05,064 INFO L82 PathProgramCache]: Analyzing trace with hash -714946492, now seen corresponding path program 1 times [2018-11-28 13:04:05,064 INFO L223 ckRefinementStrategy]: Switched to mode CVC4_FPBP [2018-11-28 13:04:05,064 INFO L69 tionRefinementEngine]: Using refinement strategy WolfRefinementStrategy No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_a5616418-4a25-482a-a0cb-6eefe8bc17e5/bin-2019/uautomizer/cvc4 Starting monitored process 27 with cvc4 --incremental --print-success --lang smt --rewrite-divk (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 27 with cvc4 --incremental --print-success --lang smt --rewrite-divk [2018-11-28 13:04:05,081 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-28 13:04:05,490 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-28 13:04:05,526 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-28 13:04:05,559 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 13 treesize of output 10 [2018-11-28 13:04:05,560 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 10 treesize of output 9 [2018-11-28 13:04:05,560 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-11-28 13:04:05,563 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-28 13:04:05,567 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-2 vars, End of recursive call: and 1 xjuncts. [2018-11-28 13:04:05,567 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 1 variables, input treesize:17, output treesize:13 [2018-11-28 13:04:05,584 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 25 treesize of output 20 [2018-11-28 13:04:05,588 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:05,589 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 20 treesize of output 27 [2018-11-28 13:04:05,589 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-11-28 13:04:05,598 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-28 13:04:05,608 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-2 vars, End of recursive call: and 1 xjuncts. [2018-11-28 13:04:05,608 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 1 variables, input treesize:28, output treesize:24 [2018-11-28 13:04:05,638 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 36 treesize of output 29 [2018-11-28 13:04:05,643 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:05,644 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:05,646 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:05,647 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 2 select indices, 2 select index equivalence classes, 3 disjoint index pairs (out of 1 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 29 treesize of output 52 [2018-11-28 13:04:05,648 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-11-28 13:04:05,663 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-28 13:04:05,677 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-2 vars, End of recursive call: and 1 xjuncts. [2018-11-28 13:04:05,677 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 1 variables, input treesize:39, output treesize:35 [2018-11-28 13:04:05,720 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 47 treesize of output 38 [2018-11-28 13:04:05,725 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:05,726 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:05,728 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:05,729 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:05,731 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:05,732 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:05,733 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 3 select indices, 3 select index equivalence classes, 6 disjoint index pairs (out of 3 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 38 treesize of output 85 [2018-11-28 13:04:05,733 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-11-28 13:04:05,762 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-28 13:04:05,784 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-2 vars, End of recursive call: and 1 xjuncts. [2018-11-28 13:04:05,784 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 1 variables, input treesize:50, output treesize:46 [2018-11-28 13:04:05,842 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 58 treesize of output 47 [2018-11-28 13:04:05,847 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:05,849 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:05,851 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:05,853 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:05,854 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:05,856 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:05,858 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:05,860 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:05,861 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:05,863 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:05,864 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 4 select indices, 4 select index equivalence classes, 10 disjoint index pairs (out of 6 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 47 treesize of output 126 [2018-11-28 13:04:05,865 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-11-28 13:04:05,914 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-28 13:04:05,943 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-2 vars, End of recursive call: and 1 xjuncts. [2018-11-28 13:04:05,943 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 1 variables, input treesize:61, output treesize:57 [2018-11-28 13:04:06,022 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 69 treesize of output 56 [2018-11-28 13:04:06,028 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:06,030 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:06,032 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:06,034 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:06,036 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:06,038 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:06,040 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:06,042 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:06,044 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:06,046 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:06,047 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:06,049 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:06,051 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:06,053 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:06,055 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:06,056 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 5 select indices, 5 select index equivalence classes, 15 disjoint index pairs (out of 10 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 56 treesize of output 175 [2018-11-28 13:04:06,057 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-11-28 13:04:06,131 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-28 13:04:06,168 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-2 vars, End of recursive call: and 1 xjuncts. [2018-11-28 13:04:06,169 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 1 variables, input treesize:72, output treesize:68 [2018-11-28 13:04:06,270 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 80 treesize of output 65 [2018-11-28 13:04:06,280 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:06,284 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:06,288 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:06,290 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:06,292 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:06,294 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:06,296 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:06,298 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:06,300 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:06,303 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:06,305 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:06,308 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:06,311 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:06,314 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:06,316 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:06,318 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:06,320 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:06,322 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:06,324 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:06,326 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:06,328 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:06,330 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 6 select indices, 6 select index equivalence classes, 21 disjoint index pairs (out of 15 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 65 treesize of output 232 [2018-11-28 13:04:06,330 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-11-28 13:04:06,433 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-28 13:04:06,480 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-2 vars, End of recursive call: and 1 xjuncts. [2018-11-28 13:04:06,480 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 1 variables, input treesize:83, output treesize:79 [2018-11-28 13:04:06,604 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 91 treesize of output 74 [2018-11-28 13:04:06,612 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:06,614 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:06,617 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:06,620 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:06,622 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:06,625 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:06,627 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:06,629 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:06,632 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:06,634 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:06,637 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:06,639 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:06,642 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:06,644 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:06,647 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:06,649 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:06,652 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:06,654 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:06,657 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:06,659 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:06,662 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:06,665 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:06,667 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:06,670 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:06,672 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:06,674 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:06,677 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:06,679 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:06,681 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 7 select indices, 7 select index equivalence classes, 28 disjoint index pairs (out of 21 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 74 treesize of output 297 [2018-11-28 13:04:06,682 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-11-28 13:04:06,839 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-28 13:04:06,897 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-2 vars, End of recursive call: and 1 xjuncts. [2018-11-28 13:04:06,897 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 1 variables, input treesize:94, output treesize:90 [2018-11-28 13:04:07,045 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 102 treesize of output 83 [2018-11-28 13:04:07,054 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:07,056 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:07,059 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:07,062 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:07,065 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:07,067 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:07,070 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:07,073 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:07,076 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:07,078 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:07,081 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:07,084 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:07,086 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:07,089 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:07,092 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:07,095 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:07,098 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:07,100 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:07,103 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:07,106 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:07,109 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:07,112 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:07,115 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:07,117 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:07,120 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:07,123 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:07,126 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:07,128 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:07,131 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:07,134 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:07,137 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:07,139 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:07,142 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:07,145 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:07,147 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:07,150 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:07,151 INFO L303 Elim1Store]: Index analysis took 104 ms [2018-11-28 13:04:07,152 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 8 select indices, 8 select index equivalence classes, 36 disjoint index pairs (out of 28 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 83 treesize of output 370 [2018-11-28 13:04:07,153 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-11-28 13:04:07,398 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-28 13:04:07,468 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-2 vars, End of recursive call: and 1 xjuncts. [2018-11-28 13:04:07,469 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 1 variables, input treesize:105, output treesize:101 [2018-11-28 13:04:07,651 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 113 treesize of output 92 [2018-11-28 13:04:07,659 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:07,662 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:07,665 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:07,668 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:07,671 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:07,674 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:07,675 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:07,678 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:07,681 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:07,684 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:07,687 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:07,690 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:07,693 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:07,696 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:07,699 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:07,702 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:07,706 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:07,708 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:07,712 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:07,715 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:07,718 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:07,721 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:07,724 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:07,727 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:07,730 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:07,733 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:07,736 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:07,739 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:07,742 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:07,745 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:07,748 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:07,751 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:07,754 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:07,757 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:07,760 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:07,763 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:07,766 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:07,769 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:07,772 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:07,775 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:07,778 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:07,781 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:07,783 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:07,786 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:07,789 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:07,790 INFO L303 Elim1Store]: Index analysis took 138 ms [2018-11-28 13:04:07,792 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 9 select indices, 9 select index equivalence classes, 45 disjoint index pairs (out of 36 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 92 treesize of output 451 [2018-11-28 13:04:07,793 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-11-28 13:04:08,096 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-28 13:04:08,188 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-2 vars, End of recursive call: and 1 xjuncts. [2018-11-28 13:04:08,188 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 1 variables, input treesize:116, output treesize:112 [2018-11-28 13:04:08,413 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 124 treesize of output 101 [2018-11-28 13:04:08,429 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:08,434 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:08,437 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:08,439 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:08,442 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:08,445 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:08,448 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:08,451 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:08,453 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:08,457 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:08,460 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:08,463 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:08,466 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:08,469 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:08,473 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:08,476 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:08,480 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:08,483 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:08,486 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:08,489 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:08,493 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:08,496 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:08,500 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:08,503 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:08,507 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:08,510 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:08,514 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:08,517 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:08,521 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:08,524 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:08,527 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:08,531 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:08,534 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:08,538 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:08,541 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:08,544 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:08,548 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:08,551 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:08,555 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:08,558 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:08,562 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:08,565 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:08,568 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:08,572 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:08,575 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:08,579 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:08,582 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:08,585 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:08,589 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:08,592 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:08,595 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:08,599 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:08,602 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:08,606 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:08,609 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:08,610 INFO L303 Elim1Store]: Index analysis took 195 ms [2018-11-28 13:04:08,612 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 10 select indices, 10 select index equivalence classes, 55 disjoint index pairs (out of 45 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 101 treesize of output 540 [2018-11-28 13:04:08,613 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-11-28 13:04:08,995 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-28 13:04:09,093 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-2 vars, End of recursive call: and 1 xjuncts. [2018-11-28 13:04:09,093 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 1 variables, input treesize:127, output treesize:123 [2018-11-28 13:04:09,323 WARN L180 SmtUtils]: Spent 100.00 ms on a formula simplification that was a NOOP. DAG size: 53 [2018-11-28 13:04:09,352 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 135 treesize of output 110 [2018-11-28 13:04:09,364 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:09,367 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:09,371 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:09,374 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:09,378 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:09,382 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:09,385 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:09,393 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:09,396 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:09,399 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:09,402 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:09,406 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:09,409 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:09,412 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:09,415 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:09,418 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:09,421 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:09,424 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:09,427 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:09,431 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:09,434 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:09,438 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:09,442 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:09,445 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:09,449 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:09,452 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:09,455 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:09,458 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:09,461 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:09,465 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:09,469 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:09,472 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:09,475 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:09,479 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:09,482 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:09,485 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:09,489 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:09,491 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:09,494 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:09,498 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:09,501 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:09,505 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:09,508 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:09,512 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:09,515 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:09,519 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:09,522 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:09,526 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:09,529 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:09,533 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:09,537 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:09,540 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:09,544 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:09,547 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:09,550 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:09,554 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:09,558 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:09,561 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:09,565 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:09,568 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:09,572 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:09,575 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:09,579 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:09,583 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:09,586 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:09,590 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:09,591 INFO L303 Elim1Store]: Index analysis took 237 ms [2018-11-28 13:04:09,592 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 11 select indices, 11 select index equivalence classes, 66 disjoint index pairs (out of 55 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 110 treesize of output 637 [2018-11-28 13:04:09,594 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-11-28 13:04:10,095 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-28 13:04:10,210 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-2 vars, End of recursive call: and 1 xjuncts. [2018-11-28 13:04:10,210 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 1 variables, input treesize:138, output treesize:134 [2018-11-28 13:04:10,472 WARN L180 SmtUtils]: Spent 115.00 ms on a formula simplification that was a NOOP. DAG size: 57 [2018-11-28 13:04:10,495 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 146 treesize of output 119 [2018-11-28 13:04:10,506 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:10,510 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:10,514 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:10,518 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:10,522 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:10,525 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:10,529 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:10,532 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:10,536 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:10,540 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:10,543 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:10,547 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:10,551 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:10,555 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:10,558 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:10,562 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:10,566 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:10,570 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:10,574 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:10,578 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:10,582 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:10,586 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:10,589 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:10,593 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:10,597 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:10,601 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:10,605 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:10,609 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:10,612 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:10,616 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:10,620 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:10,623 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:10,627 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:10,631 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:10,635 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:10,639 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:10,643 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:10,647 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:10,650 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:10,654 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:10,658 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:10,661 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:10,665 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:10,669 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:10,672 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:10,676 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:10,679 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:10,683 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:10,687 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:10,690 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:10,694 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:10,698 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:10,702 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:10,706 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:10,709 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:10,713 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:10,717 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:10,721 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:10,725 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:10,728 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:10,732 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:10,735 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:10,739 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:10,743 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:10,746 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:10,750 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:10,753 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:10,757 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:10,761 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:10,764 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:10,767 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:10,771 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:10,775 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:10,778 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:10,782 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:10,785 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:10,789 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:10,792 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:10,794 INFO L303 Elim1Store]: Index analysis took 296 ms [2018-11-28 13:04:10,795 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 12 select indices, 12 select index equivalence classes, 78 disjoint index pairs (out of 66 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 119 treesize of output 742 [2018-11-28 13:04:10,796 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-11-28 13:04:11,426 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-28 13:04:11,560 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-2 vars, End of recursive call: and 1 xjuncts. [2018-11-28 13:04:11,560 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 1 variables, input treesize:149, output treesize:145 [2018-11-28 13:04:11,859 WARN L180 SmtUtils]: Spent 132.00 ms on a formula simplification that was a NOOP. DAG size: 61 [2018-11-28 13:04:11,892 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 157 treesize of output 128 [2018-11-28 13:04:11,921 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:11,935 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:11,944 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:11,959 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:11,972 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:11,983 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:11,995 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:12,008 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:12,018 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:12,028 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:12,043 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:12,050 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:12,057 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:12,066 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:12,079 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:12,090 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:12,095 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:12,110 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:12,115 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:12,121 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:12,133 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:12,148 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:12,162 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:12,175 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:12,184 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:12,196 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:12,202 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:12,211 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:12,214 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:12,229 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:12,242 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:12,255 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:12,266 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:12,281 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:12,290 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:12,303 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:12,318 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:12,330 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:12,345 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:12,354 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:12,365 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:12,376 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:12,387 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:12,400 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:12,412 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:12,427 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:12,440 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:12,453 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:12,465 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:12,478 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:12,487 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:12,502 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:12,517 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:12,530 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:12,539 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:12,554 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:12,559 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:12,574 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:12,589 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:12,603 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:12,617 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:12,627 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:12,637 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:12,646 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:12,660 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:12,672 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:12,685 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:12,694 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:12,705 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:12,718 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:12,731 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:12,734 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:12,749 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:12,762 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:12,773 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:12,782 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:12,792 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:12,795 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:12,802 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:12,817 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:12,831 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:12,845 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:12,853 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:12,869 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:12,884 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:12,895 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:12,906 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:12,921 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:12,936 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:12,946 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:12,954 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:12,955 INFO L303 Elim1Store]: Index analysis took 1061 ms [2018-11-28 13:04:12,956 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 13 select indices, 13 select index equivalence classes, 91 disjoint index pairs (out of 78 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 128 treesize of output 855 [2018-11-28 13:04:12,957 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-11-28 13:04:13,695 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-28 13:04:13,846 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-2 vars, End of recursive call: and 1 xjuncts. [2018-11-28 13:04:13,846 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 1 variables, input treesize:160, output treesize:156 [2018-11-28 13:04:14,188 WARN L180 SmtUtils]: Spent 150.00 ms on a formula simplification that was a NOOP. DAG size: 65 [2018-11-28 13:04:14,212 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 168 treesize of output 137 [2018-11-28 13:04:14,225 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:14,229 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:14,233 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:14,237 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:14,241 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:14,245 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:14,249 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:14,253 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:14,257 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:14,261 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:14,265 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:14,269 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:14,273 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:14,277 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:14,281 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:14,285 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:14,289 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:14,293 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:14,297 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:14,301 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:14,305 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:14,309 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:14,313 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:14,317 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:14,321 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:14,326 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:14,330 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:14,334 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:14,338 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:14,342 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:14,346 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:14,351 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:14,355 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:14,359 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:14,363 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:14,368 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:14,372 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:14,376 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:14,380 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:14,384 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:14,388 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:14,392 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:14,396 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:14,400 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:14,404 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:14,408 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:14,412 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:14,416 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:14,420 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:14,424 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:14,428 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:14,432 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:14,436 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:14,440 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:14,444 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:14,448 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:14,452 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:14,456 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:14,460 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:14,464 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:14,468 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:14,472 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:14,476 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:14,479 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:14,484 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:14,488 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:14,492 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:14,496 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:14,500 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:14,504 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:14,508 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:14,512 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:14,517 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:14,521 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:14,525 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:14,529 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:14,533 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:14,537 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:14,542 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:14,546 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:14,550 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:14,555 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:14,559 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:14,563 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:14,568 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:14,572 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:14,576 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:14,580 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:14,585 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:14,589 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:14,594 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:14,598 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:14,602 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:14,606 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:14,611 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:14,615 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:14,619 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:14,623 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:14,628 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:14,632 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:14,636 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:14,640 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:14,645 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:14,649 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:14,654 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:14,655 INFO L303 Elim1Store]: Index analysis took 441 ms [2018-11-28 13:04:14,657 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 14 select indices, 14 select index equivalence classes, 105 disjoint index pairs (out of 91 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 137 treesize of output 976 [2018-11-28 13:04:14,659 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-11-28 13:04:15,593 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-28 13:04:15,773 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-2 vars, End of recursive call: and 1 xjuncts. [2018-11-28 13:04:15,773 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 1 variables, input treesize:171, output treesize:167 [2018-11-28 13:04:16,159 WARN L180 SmtUtils]: Spent 170.00 ms on a formula simplification that was a NOOP. DAG size: 69 [2018-11-28 13:04:16,200 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 179 treesize of output 146 [2018-11-28 13:04:16,234 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:16,251 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:16,270 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:16,282 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:16,302 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:16,321 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:16,337 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:16,349 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:16,355 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:16,371 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:16,389 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:16,408 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:16,424 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:16,440 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:16,450 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:16,466 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:16,485 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:16,504 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:16,516 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:16,532 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:16,551 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:16,567 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:16,582 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:16,596 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:16,610 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:16,627 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:16,645 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:16,664 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:16,680 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:16,694 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:16,711 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:16,723 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:16,741 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:16,753 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:16,772 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:16,788 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:16,805 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:16,824 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:16,842 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:16,861 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:16,877 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:16,896 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:16,912 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:16,928 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:16,946 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:16,965 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:16,982 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:16,994 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:17,010 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:17,025 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:17,032 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:17,042 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:17,059 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:17,077 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:17,083 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:17,101 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:17,120 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:17,139 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:17,158 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:17,175 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:17,187 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:17,201 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:17,209 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:17,226 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:17,242 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:17,261 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:17,279 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:17,298 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:17,314 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:17,333 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:17,341 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:17,355 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:17,370 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:17,389 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:17,407 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:17,424 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:17,436 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:17,454 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:17,471 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:17,487 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:17,501 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:17,516 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:17,530 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:17,549 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:17,556 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:17,575 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:17,591 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:17,607 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:17,623 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:17,640 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:17,659 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:17,676 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:17,691 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:17,704 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:17,719 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:17,731 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:17,745 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:17,749 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:17,767 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:17,780 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:17,795 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:17,814 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:17,833 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:17,852 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:17,867 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:17,883 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:17,899 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:17,916 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:17,924 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:17,942 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:17,961 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:17,977 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:17,991 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:18,003 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:18,016 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:18,032 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:18,042 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:18,054 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:18,072 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:18,084 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:18,086 INFO L303 Elim1Store]: Index analysis took 1883 ms [2018-11-28 13:04:18,088 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 15 select indices, 15 select index equivalence classes, 120 disjoint index pairs (out of 105 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 146 treesize of output 1105 [2018-11-28 13:04:18,090 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-11-28 13:04:19,146 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-28 13:04:19,330 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-2 vars, End of recursive call: and 1 xjuncts. [2018-11-28 13:04:19,330 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 1 variables, input treesize:179, output treesize:175 [2018-11-28 13:04:19,848 WARN L180 SmtUtils]: Spent 193.00 ms on a formula simplification that was a NOOP. DAG size: 70 [2018-11-28 13:04:21,955 INFO L267 ElimStorePlain]: Start of recursive call 3: 1 dim-0 vars, End of recursive call: 1 dim-0 vars, and 1 xjuncts. [2018-11-28 13:04:21,965 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: 1 dim-0 vars, and 1 xjuncts. [2018-11-28 13:04:21,974 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-2 vars, End of recursive call: 1 dim-0 vars, and 1 xjuncts. [2018-11-28 13:04:21,974 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 1 variables, input treesize:42, output treesize:27 [2018-11-28 13:04:23,979 WARN L854 $PredicateComparison]: unable to prove that (exists ((v_DerPreprocessor_2 (_ BitVec 32))) (= |c_#memory_$Pointer$.offset| (store |c_old(#memory_$Pointer$.offset)| |c_ldv_kobject_init_internal_#in~kobj.base| (let ((.cse0 (bvadd |c_ldv_kobject_init_internal_#in~kobj.offset| (_ bv4 32)))) (store (store (store (select |c_old(#memory_$Pointer$.offset)| |c_ldv_kobject_init_internal_#in~kobj.base|) (bvadd |c_ldv_kobject_init_internal_#in~kobj.offset| (_ bv12 32)) v_DerPreprocessor_2) .cse0 .cse0) (bvadd |c_ldv_kobject_init_internal_#in~kobj.offset| (_ bv8 32)) .cse0))))) is different from true [2018-11-28 13:04:25,986 WARN L854 $PredicateComparison]: unable to prove that (exists ((v_DerPreprocessor_2 (_ BitVec 32))) (= (store |c_old(#memory_$Pointer$.offset)| |c_ldv_kobject_init_#in~kobj.base| (let ((.cse0 (bvadd |c_ldv_kobject_init_#in~kobj.offset| (_ bv4 32)))) (store (store (store (select |c_old(#memory_$Pointer$.offset)| |c_ldv_kobject_init_#in~kobj.base|) (bvadd |c_ldv_kobject_init_#in~kobj.offset| (_ bv12 32)) v_DerPreprocessor_2) .cse0 .cse0) (bvadd |c_ldv_kobject_init_#in~kobj.offset| (_ bv8 32)) .cse0))) |c_#memory_$Pointer$.offset|)) is different from true [2018-11-28 13:04:26,114 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:26,115 INFO L303 Elim1Store]: Index analysis took 124 ms [2018-11-28 13:04:26,115 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 170 treesize of output 158 [2018-11-28 13:04:26,232 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:26,290 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:26,349 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:26,407 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:26,460 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:26,518 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:26,572 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:26,621 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:26,670 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:26,712 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:26,770 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:26,831 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:26,883 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:26,933 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:26,987 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:27,042 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:27,100 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:27,156 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:27,199 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:27,255 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:27,313 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:27,371 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:27,429 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:27,487 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:27,541 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:27,592 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:27,649 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:27,705 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:27,762 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:27,819 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:27,872 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:27,929 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:27,976 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:28,031 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:28,086 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:28,143 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:28,199 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:28,260 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:28,319 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:28,377 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:28,432 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:28,491 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:28,546 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:28,607 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:28,669 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:28,722 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:28,781 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:28,842 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:28,903 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:28,960 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:29,021 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:29,075 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:29,132 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:29,185 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:29,241 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:29,297 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:29,355 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:29,406 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:29,462 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:29,520 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:29,567 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:29,596 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:29,770 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:29,820 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:29,873 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:29,935 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:29,997 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:30,054 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:30,111 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:30,173 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:30,232 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:30,293 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:30,352 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:30,408 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:30,464 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:30,518 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:30,580 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:30,639 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:30,699 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:30,761 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:30,824 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:30,884 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:30,939 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:30,994 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:31,054 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:31,114 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:31,174 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:31,233 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:31,289 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:31,349 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:31,406 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:31,462 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:31,522 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:31,583 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:31,644 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:31,701 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:31,758 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:31,818 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:31,881 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:31,936 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:31,987 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:32,046 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:32,104 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:32,161 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:32,217 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:32,273 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:32,331 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:32,386 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:32,550 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:32,714 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:32,773 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:32,830 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:32,989 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:33,046 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:33,101 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:33,159 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:33,215 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:33,261 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:33,318 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:33,373 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:33,426 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:33,479 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:33,537 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:33,588 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:33,644 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:33,701 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:33,759 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:33,815 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:33,869 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:33,920 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:33,977 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:34,032 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:34,088 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:34,089 INFO L683 Elim1Store]: detected equality via solver [2018-11-28 13:04:36,003 INFO L303 Elim1Store]: Index analysis took 9884 ms [2018-11-28 13:04:36,257 INFO L478 Elim1Store]: Elim1 applied some preprocessing eliminated variable of array dimension 1, 1 stores, 17 select indices, 17 select index equivalence classes, 134 disjoint index pairs (out of 136 index pairs), introduced 2 new quantified variables, introduced 2 case distinctions, treesize of input 158 treesize of output 1177 [2018-11-28 13:04:36,405 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:36,431 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:36,456 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:36,476 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:36,503 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:36,524 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:36,548 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:36,572 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:36,598 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:36,622 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:36,645 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:36,669 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:36,696 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:36,722 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:36,747 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:36,772 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:36,797 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:36,823 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:36,849 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:36,875 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:36,902 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:36,928 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:36,948 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:36,973 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:36,999 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:37,026 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:37,047 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:37,072 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:37,097 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:37,122 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:37,148 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:37,171 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:37,196 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:37,220 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:37,247 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:37,272 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:37,295 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:37,319 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:37,345 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:37,370 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:37,391 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:37,418 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:37,443 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:37,467 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:37,493 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:37,538 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:37,564 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:37,587 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:37,620 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:37,647 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:37,673 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:37,700 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:37,724 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:37,748 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:37,773 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:37,797 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:37,822 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:37,849 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:37,875 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:37,900 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:37,926 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:37,952 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:37,975 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:38,001 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:38,027 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:38,052 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:38,076 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:38,100 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:38,122 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:38,148 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:38,173 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:38,200 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:38,226 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:38,249 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:38,274 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:38,298 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:38,324 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:38,350 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:38,375 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:38,402 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:38,425 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:38,450 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:38,477 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:38,502 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:38,522 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:38,544 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:38,571 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:38,592 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:38,618 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:38,643 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:38,671 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:38,692 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:38,718 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:38,744 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:38,768 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:38,795 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:38,819 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:38,842 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:38,866 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:38,888 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:38,914 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:38,940 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:38,965 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:38,991 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:39,016 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:39,039 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:39,065 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:39,089 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:39,114 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:39,137 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:39,163 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:39,186 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:39,210 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:39,237 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:39,260 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:39,285 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:39,310 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:39,329 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:39,355 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:39,380 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:39,404 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:39,454 INFO L303 Elim1Store]: Index analysis took 3116 ms [2018-11-28 13:04:39,455 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 16 select indices, 16 select index equivalence classes, 121 disjoint index pairs (out of 120 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 1092 treesize of output 1092 [2018-11-28 13:04:40,230 WARN L180 SmtUtils]: Spent 771.00 ms on a formula simplification. DAG size of input: 80 DAG size of output: 77 [2018-11-28 13:04:40,257 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:40,267 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:40,278 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:40,289 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:40,297 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:40,307 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:40,316 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:40,325 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:40,335 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:40,346 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:40,355 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:40,366 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:40,375 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:40,384 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:40,394 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:40,402 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:40,412 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:40,421 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:40,430 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:40,439 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:40,448 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:40,454 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:40,464 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:40,474 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:40,483 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:40,492 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:40,500 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:40,507 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:40,516 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:40,523 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:40,531 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:40,538 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:40,545 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:40,554 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:40,562 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:40,568 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:40,576 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:40,584 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:40,590 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:40,594 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:40,601 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:40,609 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:40,617 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:40,624 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:40,631 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:40,639 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:40,647 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:40,655 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:40,663 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:40,671 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:40,678 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:40,685 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:40,694 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:40,702 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:40,710 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:40,719 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:40,727 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:40,735 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:40,743 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:40,751 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:40,759 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:40,767 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:40,774 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:40,781 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:40,789 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:40,798 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:40,805 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:40,814 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:40,822 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:40,831 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:40,838 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:40,847 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:40,855 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:40,864 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:40,869 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:40,877 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:40,886 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:40,894 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:40,902 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:40,912 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:40,919 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:40,928 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:40,936 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:40,945 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:40,951 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:40,960 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:40,968 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:40,975 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:40,983 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:40,991 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:40,998 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:41,004 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:41,011 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:41,018 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:41,026 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:41,034 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:41,042 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:41,048 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:41,056 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:41,064 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:41,072 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:41,079 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:41,088 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:41,097 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:41,103 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:41,111 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:41,142 INFO L303 Elim1Store]: Index analysis took 909 ms [2018-11-28 13:04:41,144 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 16 select indices, 16 select index equivalence classes, 121 disjoint index pairs (out of 120 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 137 treesize of output 1096 [2018-11-28 13:04:41,146 INFO L267 ElimStorePlain]: Start of recursive call 5: End of recursive call: and 1 xjuncts. [2018-11-28 13:04:41,571 INFO L267 ElimStorePlain]: Start of recursive call 4: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-28 13:04:42,904 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:42,931 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:42,955 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:42,983 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:43,014 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:43,044 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:43,074 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:43,103 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:43,131 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:43,162 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:43,186 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:43,214 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:43,243 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:43,270 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:43,298 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:43,329 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:43,358 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:43,389 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:43,420 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:43,446 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:43,474 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:43,504 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:43,530 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:43,557 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:43,588 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:43,612 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:43,637 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:43,665 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:43,694 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:43,722 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:43,752 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:43,781 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:43,812 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:43,842 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:43,871 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:43,899 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:43,929 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:43,955 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:43,986 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:44,016 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:44,041 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:44,068 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:44,099 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:44,129 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:44,160 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:44,187 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:44,214 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:44,243 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:44,272 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:44,302 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:44,329 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:44,360 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:44,388 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:44,415 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:44,440 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:44,466 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:44,493 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:44,524 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:44,553 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:44,581 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:44,612 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:44,639 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:44,722 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:44,748 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:44,775 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:44,796 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:44,822 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:44,849 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:44,880 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:44,906 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:44,933 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:44,963 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:44,990 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:45,018 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:45,047 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:45,078 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:45,109 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:45,139 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:45,167 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:45,192 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:45,221 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:45,252 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:45,281 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:45,311 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:45,340 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:45,362 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:45,391 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:45,419 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:45,448 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:45,478 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:45,507 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:45,535 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:45,566 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:45,595 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:45,623 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:45,651 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:45,673 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:45,695 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:45,720 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:45,751 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:45,781 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:45,807 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:45,836 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:45,862 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:45,890 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:45,917 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:45,941 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:45,969 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:45,997 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:46,075 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:46,104 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:46,130 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:46,158 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:46,251 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:46,281 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:46,315 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:46,344 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:46,375 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:46,406 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:46,434 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:46,462 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:46,491 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:46,518 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:46,547 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:46,576 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:46,606 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:46,636 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:46,658 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:46,685 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:46,711 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:46,741 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:46,771 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:46,797 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:46,825 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:47,687 INFO L303 Elim1Store]: Index analysis took 4837 ms [2018-11-28 13:04:47,771 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 17 select indices, 17 select index equivalence classes, 134 disjoint index pairs (out of 136 index pairs), introduced 1 new quantified variables, introduced 2 case distinctions, treesize of input 155 treesize of output 1164 [2018-11-28 13:04:49,614 WARN L180 SmtUtils]: Spent 1.84 s on a formula simplification. DAG size of input: 166 DAG size of output: 119 [2018-11-28 13:04:49,635 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:49,644 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:49,654 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:49,664 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:49,671 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:49,681 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:49,690 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:49,699 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:49,708 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:49,718 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:49,727 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:49,736 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:49,746 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:49,755 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:49,765 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:49,771 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:49,779 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:49,789 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:49,797 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:49,805 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:49,821 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:49,831 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:49,841 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:49,849 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:49,858 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:49,866 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:49,874 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:49,880 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:49,891 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:49,897 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:49,906 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:49,916 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:49,926 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:49,936 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:49,946 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:49,955 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:49,962 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:49,971 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:49,981 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:49,990 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:49,999 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:50,008 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:50,018 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:50,027 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:50,035 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:50,044 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:50,054 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:50,061 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:50,069 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:50,076 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:50,086 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:50,096 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:50,104 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:50,111 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:50,120 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:50,130 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:50,140 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:50,146 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:50,156 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:50,166 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:50,175 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:50,183 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:50,191 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:50,201 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:50,211 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:50,217 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:50,226 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:50,234 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:50,244 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:50,253 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:50,263 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:50,271 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:50,280 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:50,289 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:50,299 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:50,308 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:50,318 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:50,326 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:50,335 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:50,345 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:50,354 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:50,360 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:50,370 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:50,380 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:50,388 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:50,395 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:50,403 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:50,412 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:50,422 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:50,431 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:50,441 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:50,451 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:50,459 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:50,466 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:50,474 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:50,484 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:50,490 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:50,498 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:50,507 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:50,517 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:50,526 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:50,535 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:50,541 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:50,550 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:50,559 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:50,569 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:50,579 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:50,587 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:50,596 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:50,604 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:50,613 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:50,621 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:50,630 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:50,640 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:50,647 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:50,654 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:50,663 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:50,671 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:50,682 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:50,690 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:50,921 INFO L303 Elim1Store]: Index analysis took 1305 ms [2018-11-28 13:04:50,923 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 16 select indices, 16 select index equivalence classes, 120 disjoint index pairs (out of 120 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 133 treesize of output 1092 [2018-11-28 13:04:50,924 INFO L267 ElimStorePlain]: Start of recursive call 7: End of recursive call: and 1 xjuncts. [2018-11-28 13:04:51,554 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:51,563 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:51,573 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:51,582 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:51,590 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:51,599 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:51,609 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:51,618 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:51,627 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:51,634 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:51,643 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:51,653 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:51,662 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:51,671 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:51,681 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:51,689 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:51,698 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:51,708 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:51,718 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:51,727 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:51,736 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:51,746 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:51,756 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:51,766 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:51,774 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:51,783 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:51,793 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:51,802 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:51,811 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:51,820 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:51,830 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:51,840 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:51,849 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:51,858 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:51,868 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:51,877 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:51,887 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:51,897 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:51,907 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:51,916 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:51,924 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:51,933 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:51,942 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:51,951 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:51,961 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:51,969 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:51,978 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:51,988 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:51,998 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:52,007 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:52,017 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:52,026 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:52,036 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:52,046 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:52,055 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:52,065 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:52,074 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:52,084 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:52,093 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:52,103 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:52,111 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:52,120 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:52,129 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:52,137 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:52,147 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:52,156 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:52,165 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:52,175 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:52,181 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:52,190 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:52,200 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:52,210 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:52,215 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:52,225 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:52,234 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:52,242 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:52,251 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:52,261 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:52,271 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:52,279 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:52,289 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:52,298 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:52,307 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:52,316 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:52,325 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:52,335 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:52,344 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:52,354 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:52,364 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:52,374 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:52,383 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:52,392 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:52,402 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:52,411 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:52,420 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:52,430 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:52,440 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:52,450 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:52,460 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:52,470 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:52,479 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:52,488 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:52,497 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:52,506 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:52,516 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:52,526 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:52,536 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:52,545 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:52,555 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:52,563 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:52,572 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:52,582 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:52,591 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:52,600 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:52,609 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:52,618 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:52,627 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:52,635 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:52,641 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:52,650 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:52,887 INFO L303 Elim1Store]: Index analysis took 1351 ms [2018-11-28 13:04:52,889 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 16 select indices, 16 select index equivalence classes, 120 disjoint index pairs (out of 120 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 128 treesize of output 1062 [2018-11-28 13:04:52,890 INFO L267 ElimStorePlain]: Start of recursive call 8: End of recursive call: and 1 xjuncts. [2018-11-28 13:04:53,363 INFO L267 ElimStorePlain]: Start of recursive call 6: 2 dim-1 vars, End of recursive call: and 2 xjuncts. [2018-11-28 13:04:53,507 INFO L267 ElimStorePlain]: Start of recursive call 3: 1 dim-0 vars, 2 dim-1 vars, End of recursive call: and 3 xjuncts. [2018-11-28 13:04:53,574 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-28 13:04:53,637 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-0 vars, 1 dim-2 vars, End of recursive call: and 1 xjuncts. [2018-11-28 13:04:53,637 INFO L202 ElimStorePlain]: Needed 8 recursive calls to eliminate 2 variables, input treesize:173, output treesize:141 [2018-11-28 13:04:57,478 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 129 treesize of output 96 [2018-11-28 13:04:57,483 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:57,485 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:57,485 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:57,486 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:57,487 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:57,488 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:57,489 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:57,490 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:57,491 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:57,492 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:57,493 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:57,494 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:57,494 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:57,495 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:57,496 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:04:57,512 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 15 select indices, 15 select index equivalence classes, 120 disjoint index pairs (out of 105 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 96 treesize of output 200 [2018-11-28 13:04:57,512 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-11-28 13:04:57,561 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-28 13:04:57,590 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-2 vars, End of recursive call: and 1 xjuncts. [2018-11-28 13:04:57,590 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 1 variables, input treesize:132, output treesize:113 [2018-11-28 13:04:59,989 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 121 treesize of output 88 [2018-11-28 13:05:00,223 INFO L303 Elim1Store]: Index analysis took 231 ms [2018-11-28 13:05:00,224 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 15 select indices, 15 select index equivalence classes, 120 disjoint index pairs (out of 105 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 88 treesize of output 106 [2018-11-28 13:05:00,224 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-11-28 13:05:00,250 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-28 13:05:00,276 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-2 vars, End of recursive call: and 1 xjuncts. [2018-11-28 13:05:00,276 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 1 variables, input treesize:121, output treesize:106 [2018-11-28 13:05:02,565 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 113 treesize of output 81 [2018-11-28 13:05:02,668 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 16 select indices, 16 select index equivalence classes, 105 disjoint index pairs (out of 120 index pairs), introduced 0 new quantified variables, introduced 15 case distinctions, treesize of input 81 treesize of output 121 [2018-11-28 13:05:02,669 WARN L138 XnfTransformerHelper]: expecting exponential blowup for input size 15 [2018-11-28 13:05:02,670 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 4 xjuncts. [2018-11-28 13:05:02,724 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 3 xjuncts. [2018-11-28 13:05:02,776 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-0 vars, 1 dim-2 vars, End of recursive call: and 3 xjuncts. [2018-11-28 13:05:02,776 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 2 variables, input treesize:113, output treesize:130 [2018-11-28 13:05:03,746 INFO L134 CoverageAnalysis]: Checked inductivity of 136 backedges. 0 proven. 136 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-28 13:05:03,746 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-11-28 13:05:05,921 INFO L267 ElimStorePlain]: Start of recursive call 3: 1 dim-0 vars, End of recursive call: 1 dim-0 vars, and 1 xjuncts. [2018-11-28 13:05:05,929 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: 1 dim-0 vars, and 1 xjuncts. [2018-11-28 13:05:05,931 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-2 vars, End of recursive call: 1 dim-0 vars, and 1 xjuncts. [2018-11-28 13:05:05,932 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 1 variables, input treesize:24, output treesize:10 [2018-11-28 13:05:06,246 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-28 13:05:06,246 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FPBP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_a5616418-4a25-482a-a0cb-6eefe8bc17e5/bin-2019/uautomizer/z3 Starting monitored process 28 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 28 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-28 13:05:06,255 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-28 13:05:06,324 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-28 13:05:06,332 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-28 13:05:07,163 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 11 treesize of output 8 [2018-11-28 13:05:07,164 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 8 treesize of output 7 [2018-11-28 13:05:07,165 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-11-28 13:05:07,167 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-28 13:05:07,170 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-2 vars, End of recursive call: and 1 xjuncts. [2018-11-28 13:05:07,170 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 1 variables, input treesize:15, output treesize:11 [2018-11-28 13:05:08,639 INFO L267 ElimStorePlain]: Start of recursive call 3: 1 dim-0 vars, End of recursive call: 1 dim-0 vars, and 1 xjuncts. [2018-11-28 13:05:08,649 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: 1 dim-0 vars, and 1 xjuncts. [2018-11-28 13:05:08,678 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-2 vars, End of recursive call: 1 dim-0 vars, and 1 xjuncts. [2018-11-28 13:05:08,678 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 1 variables, input treesize:50, output treesize:38 [2018-11-28 13:05:11,235 WARN L180 SmtUtils]: Spent 2.02 s on a formula simplification that was a NOOP. DAG size: 22 [2018-11-28 13:05:11,246 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 36 treesize of output 31 [2018-11-28 13:05:11,250 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:05:11,252 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 31 treesize of output 41 [2018-11-28 13:05:11,256 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:05:11,257 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:05:11,258 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:05:11,264 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 2 select indices, 2 select index equivalence classes, 3 disjoint index pairs (out of 1 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 33 treesize of output 45 [2018-11-28 13:05:11,265 INFO L267 ElimStorePlain]: Start of recursive call 4: End of recursive call: and 1 xjuncts. [2018-11-28 13:05:11,275 INFO L267 ElimStorePlain]: Start of recursive call 3: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-28 13:05:11,281 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-28 13:05:11,299 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-0 vars, 1 dim-2 vars, End of recursive call: and 1 xjuncts. [2018-11-28 13:05:11,300 INFO L202 ElimStorePlain]: Needed 4 recursive calls to eliminate 2 variables, input treesize:58, output treesize:22 [2018-11-28 13:05:16,986 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:05:16,987 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 31 treesize of output 38 [2018-11-28 13:05:16,991 INFO L683 Elim1Store]: detected equality via solver [2018-11-28 13:05:16,992 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:05:16,993 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 2 select indices, 2 select index equivalence classes, 1 disjoint index pairs (out of 1 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 38 treesize of output 15 [2018-11-28 13:05:16,993 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-11-28 13:05:16,996 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-28 13:05:17,002 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-2 vars, End of recursive call: and 1 xjuncts. [2018-11-28 13:05:17,002 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 1 variables, input treesize:39, output treesize:13 [2018-11-28 13:05:21,091 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 17 treesize of output 13 [2018-11-28 13:05:21,092 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 13 treesize of output 5 [2018-11-28 13:05:21,092 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-11-28 13:05:21,093 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-28 13:05:21,094 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-0 vars, 1 dim-2 vars, End of recursive call: and 1 xjuncts. [2018-11-28 13:05:21,095 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 2 variables, input treesize:17, output treesize:5 [2018-11-28 13:05:21,398 INFO L134 CoverageAnalysis]: Checked inductivity of 136 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 136 trivial. 0 not checked. [2018-11-28 13:05:21,399 INFO L312 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2018-11-28 13:05:21,415 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 1 imperfect interpolant sequences. [2018-11-28 13:05:21,415 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [42] imperfect sequences [63] total 101 [2018-11-28 13:05:21,416 INFO L459 AbstractCegarLoop]: Interpolant automaton has 101 states [2018-11-28 13:05:21,416 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 101 interpolants. [2018-11-28 13:05:21,417 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=320, Invalid=11458, Unknown=2, NotChecked=430, Total=12210 [2018-11-28 13:05:21,417 INFO L87 Difference]: Start difference. First operand 138 states and 140 transitions. Second operand 101 states. [2018-11-28 13:06:30,538 WARN L180 SmtUtils]: Spent 2.04 s on a formula simplification that was a NOOP. DAG size: 29 [2018-11-28 13:06:38,261 WARN L180 SmtUtils]: Spent 4.08 s on a formula simplification. DAG size of input: 38 DAG size of output: 31 [2018-11-28 13:06:43,910 WARN L180 SmtUtils]: Spent 2.04 s on a formula simplification that was a NOOP. DAG size: 32 [2018-11-28 13:06:53,729 WARN L180 SmtUtils]: Spent 135.00 ms on a formula simplification that was a NOOP. DAG size: 128 [2018-11-28 13:07:05,788 WARN L180 SmtUtils]: Spent 104.00 ms on a formula simplification that was a NOOP. DAG size: 102 [2018-11-28 13:07:07,373 WARN L180 SmtUtils]: Spent 100.00 ms on a formula simplification that was a NOOP. DAG size: 104 [2018-11-28 13:07:08,678 WARN L180 SmtUtils]: Spent 104.00 ms on a formula simplification that was a NOOP. DAG size: 108 [2018-11-28 13:07:19,714 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-28 13:07:19,714 INFO L93 Difference]: Finished difference Result 116 states and 116 transitions. [2018-11-28 13:07:19,714 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 63 states. [2018-11-28 13:07:19,714 INFO L78 Accepts]: Start accepts. Automaton has 101 states. Word has length 116 [2018-11-28 13:07:19,715 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-28 13:07:19,715 INFO L225 Difference]: With dead ends: 116 [2018-11-28 13:07:19,715 INFO L226 Difference]: Without dead ends: 116 [2018-11-28 13:07:19,717 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 288 GetRequests, 136 SyntacticMatches, 0 SemanticMatches, 152 ConstructedPredicates, 2 IntricatePredicates, 0 DeprecatedPredicates, 3510 ImplicationChecksByTransitivity, 61.6s TimeCoverageRelationStatistics Valid=742, Invalid=22215, Unknown=3, NotChecked=602, Total=23562 [2018-11-28 13:07:19,718 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 116 states. [2018-11-28 13:07:19,719 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 116 to 116. [2018-11-28 13:07:19,719 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 116 states. [2018-11-28 13:07:19,719 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 116 states to 116 states and 116 transitions. [2018-11-28 13:07:19,719 INFO L78 Accepts]: Start accepts. Automaton has 116 states and 116 transitions. Word has length 116 [2018-11-28 13:07:19,719 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-28 13:07:19,719 INFO L480 AbstractCegarLoop]: Abstraction has 116 states and 116 transitions. [2018-11-28 13:07:19,719 INFO L481 AbstractCegarLoop]: Interpolant automaton has 101 states. [2018-11-28 13:07:19,719 INFO L276 IsEmpty]: Start isEmpty. Operand 116 states and 116 transitions. [2018-11-28 13:07:19,720 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 116 [2018-11-28 13:07:19,720 INFO L394 BasicCegarLoop]: Found error trace [2018-11-28 13:07:19,720 INFO L402 BasicCegarLoop]: trace histogram [16, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-28 13:07:19,720 INFO L423 AbstractCegarLoop]: === Iteration 27 === [ldv_kref_initErr0REQUIRES_VIOLATION, ldv_kref_initErr1REQUIRES_VIOLATION, ldv_list_addErr1REQUIRES_VIOLATION, ldv_list_addErr0REQUIRES_VIOLATION, ldv_kobject_createErr1REQUIRES_VIOLATION, ldv_kobject_createErr0REQUIRES_VIOLATION, ldv_destroy_msgsErr0REQUIRES_VIOLATION, ldv_destroy_msgsErr5REQUIRES_VIOLATION, ldv_destroy_msgsErr4REQUIRES_VIOLATION, ldv_destroy_msgsErr3REQUIRES_VIOLATION, ldv_destroy_msgsErr2REQUIRES_VIOLATION, ldv_destroy_msgsErr1REQUIRES_VIOLATION, ldv_msg_fillErr1REQUIRES_VIOLATION, ldv_msg_fillErr3REQUIRES_VIOLATION, ldv_msg_fillErr2REQUIRES_VIOLATION, ldv_msg_fillErr5REQUIRES_VIOLATION, ldv_msg_fillErr0REQUIRES_VIOLATION, ldv_msg_fillErr4REQUIRES_VIOLATION, ldv_atomic_add_returnErr3REQUIRES_VIOLATION, ldv_atomic_add_returnErr2REQUIRES_VIOLATION, ldv_atomic_add_returnErr1REQUIRES_VIOLATION, ldv_atomic_add_returnErr0REQUIRES_VIOLATION, __ldv_list_delErr1REQUIRES_VIOLATION, __ldv_list_delErr2REQUIRES_VIOLATION, __ldv_list_delErr3REQUIRES_VIOLATION, __ldv_list_delErr0REQUIRES_VIOLATION, ldv_kobject_cleanupErr0REQUIRES_VIOLATION, ldv_kobject_cleanupErr3ASSERT_VIOLATIONMEMORY_FREE, ldv_kobject_cleanupErr2ASSERT_VIOLATIONMEMORY_FREE, ldv_kobject_cleanupErr5ASSERT_VIOLATIONMEMORY_FREE, ldv_kobject_cleanupErr1REQUIRES_VIOLATION, ldv_kobject_cleanupErr4ASSERT_VIOLATIONMEMORY_FREE, ldv_msg_freeErr0REQUIRES_VIOLATION, ldv_msg_freeErr3ASSERT_VIOLATIONMEMORY_FREE, ldv_msg_freeErr2ASSERT_VIOLATIONMEMORY_FREE, ldv_msg_freeErr5ASSERT_VIOLATIONMEMORY_FREE, ldv_msg_freeErr4ASSERT_VIOLATIONMEMORY_FREE, ldv_msg_freeErr1REQUIRES_VIOLATION, mainErr0ENSURES_VIOLATIONMEMORY_LEAK, LDV_INIT_LIST_HEADErr3REQUIRES_VIOLATION, LDV_INIT_LIST_HEADErr2REQUIRES_VIOLATION, LDV_INIT_LIST_HEADErr1REQUIRES_VIOLATION, LDV_INIT_LIST_HEADErr0REQUIRES_VIOLATION, ldv_list_delErr3REQUIRES_VIOLATION, ldv_list_delErr2REQUIRES_VIOLATION, ldv_list_delErr1REQUIRES_VIOLATION, ldv_list_delErr0REQUIRES_VIOLATION, __ldv_list_addErr6REQUIRES_VIOLATION, __ldv_list_addErr1REQUIRES_VIOLATION, __ldv_list_addErr7REQUIRES_VIOLATION, __ldv_list_addErr2REQUIRES_VIOLATION, __ldv_list_addErr3REQUIRES_VIOLATION, __ldv_list_addErr4REQUIRES_VIOLATION, __ldv_list_addErr5REQUIRES_VIOLATION, __ldv_list_addErr0REQUIRES_VIOLATION, ldv_dev_set_drvdataErr1REQUIRES_VIOLATION, ldv_dev_set_drvdataErr0REQUIRES_VIOLATION, ldv_atomic_sub_returnErr3REQUIRES_VIOLATION, ldv_atomic_sub_returnErr2REQUIRES_VIOLATION, ldv_atomic_sub_returnErr1REQUIRES_VIOLATION, ldv_atomic_sub_returnErr0REQUIRES_VIOLATION, ldv_list_add_tailErr0REQUIRES_VIOLATION, ldv_list_add_tailErr1REQUIRES_VIOLATION, ldv_dev_get_drvdataErr1REQUIRES_VIOLATION, ldv_dev_get_drvdataErr0REQUIRES_VIOLATION, ldv_msg_allocErr0REQUIRES_VIOLATION, ldv_msg_allocErr1REQUIRES_VIOLATION]=== [2018-11-28 13:07:19,721 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-28 13:07:19,721 INFO L82 PathProgramCache]: Analyzing trace with hash -724169652, now seen corresponding path program 1 times [2018-11-28 13:07:19,721 INFO L223 ckRefinementStrategy]: Switched to mode CVC4_FPBP [2018-11-28 13:07:19,721 INFO L69 tionRefinementEngine]: Using refinement strategy WolfRefinementStrategy No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_a5616418-4a25-482a-a0cb-6eefe8bc17e5/bin-2019/uautomizer/cvc4 Starting monitored process 29 with cvc4 --incremental --print-success --lang smt --rewrite-divk (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 29 with cvc4 --incremental --print-success --lang smt --rewrite-divk [2018-11-28 13:07:19,737 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-28 13:07:24,611 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-28 13:07:29,854 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-28 13:07:29,952 INFO L469 BasicCegarLoop]: Counterexample might be feasible [2018-11-28 13:07:29,969 WARN L416 cessorBacktranslator]: Generated EnsuresSpecification free ensures #res.base == #ptr.base && #res.offset == #ptr.offset; is not ensure(true) [2018-11-28 13:07:29,979 WARN L416 cessorBacktranslator]: Generated EnsuresSpecification ensures #valid == old(#valid); is not ensure(true) [2018-11-28 13:07:29,984 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType STRUCT~~ldv_list_head?next~*ldv_list_head?prev~*ldv_list_head# [2018-11-28 13:07:29,985 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType STRUCT~~ldv_list_head?next~*ldv_list_head?prev~*ldv_list_head# [2018-11-28 13:07:29,997 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction CFG 28.11 01:07:29 BoogieIcfgContainer [2018-11-28 13:07:29,997 INFO L132 PluginConnector]: ------------------------ END TraceAbstraction---------------------------- [2018-11-28 13:07:29,998 INFO L113 PluginConnector]: ------------------------Witness Printer---------------------------- [2018-11-28 13:07:29,998 INFO L271 PluginConnector]: Initializing Witness Printer... [2018-11-28 13:07:29,998 INFO L276 PluginConnector]: Witness Printer initialized [2018-11-28 13:07:29,998 INFO L185 PluginConnector]: Executing the observer RCFGCatcher from plugin Witness Printer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 28.11 01:03:41" (3/4) ... [2018-11-28 13:07:30,002 INFO L147 WitnessPrinter]: No result that supports witness generation found [2018-11-28 13:07:30,002 INFO L132 PluginConnector]: ------------------------ END Witness Printer---------------------------- [2018-11-28 13:07:30,003 INFO L168 Benchmark]: Toolchain (without parser) took 230359.29 ms. Allocated memory was 1.0 GB in the beginning and 1.3 GB in the end (delta: 303.6 MB). Free memory was 943.4 MB in the beginning and 1.0 GB in the end (delta: -81.6 MB). Peak memory consumption was 222.0 MB. Max. memory is 11.5 GB. [2018-11-28 13:07:30,003 INFO L168 Benchmark]: CDTParser took 0.15 ms. Allocated memory is still 1.0 GB. Free memory is still 978.3 MB. There was no memory consumed. Max. memory is 11.5 GB. [2018-11-28 13:07:30,003 INFO L168 Benchmark]: CACSL2BoogieTranslator took 465.12 ms. Allocated memory was 1.0 GB in the beginning and 1.2 GB in the end (delta: 135.3 MB). Free memory was 943.4 MB in the beginning and 1.1 GB in the end (delta: -159.8 MB). Peak memory consumption was 37.2 MB. Max. memory is 11.5 GB. [2018-11-28 13:07:30,003 INFO L168 Benchmark]: Boogie Preprocessor took 50.61 ms. Allocated memory is still 1.2 GB. Free memory is still 1.1 GB. There was no memory consumed. Max. memory is 11.5 GB. [2018-11-28 13:07:30,004 INFO L168 Benchmark]: RCFGBuilder took 972.64 ms. Allocated memory is still 1.2 GB. Free memory was 1.1 GB in the beginning and 986.6 MB in the end (delta: 116.6 MB). Peak memory consumption was 116.6 MB. Max. memory is 11.5 GB. [2018-11-28 13:07:30,004 INFO L168 Benchmark]: TraceAbstraction took 228862.65 ms. Allocated memory was 1.2 GB in the beginning and 1.3 GB in the end (delta: 168.3 MB). Free memory was 986.6 MB in the beginning and 1.0 GB in the end (delta: -38.4 MB). Peak memory consumption was 129.9 MB. Max. memory is 11.5 GB. [2018-11-28 13:07:30,004 INFO L168 Benchmark]: Witness Printer took 4.24 ms. Allocated memory is still 1.3 GB. Free memory is still 1.0 GB. There was no memory consumed. Max. memory is 11.5 GB. [2018-11-28 13:07:30,005 INFO L336 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.15 ms. Allocated memory is still 1.0 GB. Free memory is still 978.3 MB. There was no memory consumed. Max. memory is 11.5 GB. * CACSL2BoogieTranslator took 465.12 ms. Allocated memory was 1.0 GB in the beginning and 1.2 GB in the end (delta: 135.3 MB). Free memory was 943.4 MB in the beginning and 1.1 GB in the end (delta: -159.8 MB). Peak memory consumption was 37.2 MB. Max. memory is 11.5 GB. * Boogie Preprocessor took 50.61 ms. Allocated memory is still 1.2 GB. Free memory is still 1.1 GB. There was no memory consumed. Max. memory is 11.5 GB. * RCFGBuilder took 972.64 ms. Allocated memory is still 1.2 GB. Free memory was 1.1 GB in the beginning and 986.6 MB in the end (delta: 116.6 MB). Peak memory consumption was 116.6 MB. Max. memory is 11.5 GB. * TraceAbstraction took 228862.65 ms. Allocated memory was 1.2 GB in the beginning and 1.3 GB in the end (delta: 168.3 MB). Free memory was 986.6 MB in the beginning and 1.0 GB in the end (delta: -38.4 MB). Peak memory consumption was 129.9 MB. Max. memory is 11.5 GB. * Witness Printer took 4.24 ms. Allocated memory is still 1.3 GB. Free memory is still 1.0 GB. There was no memory consumed. Max. memory is 11.5 GB. * Results from de.uni_freiburg.informatik.ultimate.boogie.preprocessor: - GenericResult: Unfinished Backtranslation Generated EnsuresSpecification free ensures #res.base == #ptr.base && #res.offset == #ptr.offset; is not ensure(true) - GenericResult: Unfinished Backtranslation Generated EnsuresSpecification ensures #valid == old(#valid); is not ensure(true) * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType STRUCT~~ldv_list_head?next~*ldv_list_head?prev~*ldv_list_head# - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType STRUCT~~ldv_list_head?next~*ldv_list_head?prev~*ldv_list_head# * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - UnprovableResult [Line: 1452]: Unable to prove that all allocated memory was freed Unable to prove that all allocated memory was freed Reason: overapproximation of memtrack at line 1452. Possible FailurePath: [L1135] struct ldv_list_head ldv_global_msg_list = { &(ldv_global_msg_list), &(ldv_global_msg_list) }; VAL [\old(ldv_global_msg_list)=null, \old(ldv_global_msg_list)=null, ldv_global_msg_list={-1:0}] [L1453] CALL entry_point() VAL [ldv_global_msg_list={-1:0}] [L1445] struct ldv_kobject *kobj; VAL [ldv_global_msg_list={-1:0}] [L1446] CALL, EXPR ldv_kobject_create() VAL [ldv_global_msg_list={-1:0}] [L1406] struct ldv_kobject *kobj; VAL [ldv_global_msg_list={-1:0}] [L1408] CALL, EXPR ldv_malloc(sizeof(*kobj)) VAL [\old(size)=16, ldv_global_msg_list={-1:0}] [L1073] COND TRUE __VERIFIER_nondet_int() [L1074] return malloc(size); VAL [\old(size)=16, \result={1082401:0}, ldv_global_msg_list={-1:0}, malloc(size)={1082401:0}, size=16] [L1408] RET, EXPR ldv_malloc(sizeof(*kobj)) VAL [ldv_global_msg_list={-1:0}, ldv_malloc(sizeof(*kobj))={1082401:0}] [L1408] kobj = ldv_malloc(sizeof(*kobj)) [L1409] COND FALSE !(!kobj) VAL [kobj={1082401:0}, ldv_global_msg_list={-1:0}] [L1411] FCALL memset(kobj, 0, sizeof(*kobj)) VAL [kobj={1082401:0}, ldv_global_msg_list={-1:0}, memset(kobj, 0, sizeof(*kobj))={1082401:0}] [L1413] CALL ldv_kobject_init(kobj) VAL [kobj={1082401:0}, ldv_global_msg_list={-1:0}] [L1394] COND FALSE !(!kobj) VAL [kobj={1082401:0}, kobj={1082401:0}, ldv_global_msg_list={-1:0}] [L1398] CALL ldv_kobject_init_internal(kobj) VAL [kobj={1082401:0}, ldv_global_msg_list={-1:0}] [L1380] COND FALSE !(!kobj) VAL [kobj={1082401:0}, kobj={1082401:0}, ldv_global_msg_list={-1:0}] [L1382] CALL ldv_kref_init(&kobj->kref) VAL [kref={1082401:12}, ldv_global_msg_list={-1:0}] [L1294] ((&kref->refcount)->counter) = (1) VAL [kref={1082401:12}, kref={1082401:12}, ldv_global_msg_list={-1:0}] [L1382] RET ldv_kref_init(&kobj->kref) VAL [kobj={1082401:0}, kobj={1082401:0}, ldv_global_msg_list={-1:0}] [L1383] CALL LDV_INIT_LIST_HEAD(&kobj->entry) VAL [ldv_global_msg_list={-1:0}, list={1082401:4}] [L1099] list->next = list VAL [ldv_global_msg_list={-1:0}, list={1082401:4}, list={1082401:4}] [L1100] list->prev = list VAL [ldv_global_msg_list={-1:0}, list={1082401:4}, list={1082401:4}] [L1383] RET LDV_INIT_LIST_HEAD(&kobj->entry) VAL [kobj={1082401:0}, kobj={1082401:0}, ldv_global_msg_list={-1:0}] [L1398] RET ldv_kobject_init_internal(kobj) VAL [kobj={1082401:0}, kobj={1082401:0}, ldv_global_msg_list={-1:0}] [L1413] RET ldv_kobject_init(kobj) VAL [kobj={1082401:0}, ldv_global_msg_list={-1:0}] [L1414] return kobj; VAL [\result={1082401:0}, kobj={1082401:0}, ldv_global_msg_list={-1:0}] [L1446] RET, EXPR ldv_kobject_create() VAL [ldv_global_msg_list={-1:0}, ldv_kobject_create()={1082401:0}] [L1446] kobj = ldv_kobject_create() [L1447] CALL f_22_get(kobj) VAL [kobj={1082401:0}, ldv_global_msg_list={-1:0}] [L1437] CALL ldv_kobject_get(kobj) VAL [kobj={1082401:0}, ldv_global_msg_list={-1:0}] [L1373] COND TRUE \read(*kobj) VAL [kobj={1082401:0}, kobj={1082401:0}, ldv_global_msg_list={-1:0}] [L1374] CALL ldv_kref_get(&kobj->kref) VAL [kref={1082401:12}, ldv_global_msg_list={-1:0}] [L1308] CALL ldv_atomic_add_return(1, (&kref->refcount)) VAL [\old(i)=1, ldv_global_msg_list={-1:0}, v={1082401:12}] [L1255] int temp; VAL [\old(i)=1, i=1, ldv_global_msg_list={-1:0}, v={1082401:12}, v={1082401:12}] [L1256] EXPR v->counter VAL [\old(i)=1, i=1, ldv_global_msg_list={-1:0}, v={1082401:12}, v={1082401:12}, v->counter=1] [L1256] temp = v->counter [L1257] temp += i VAL [\old(i)=1, i=1, ldv_global_msg_list={-1:0}, temp=2, v={1082401:12}, v={1082401:12}] [L1258] v->counter = temp VAL [\old(i)=1, i=1, ldv_global_msg_list={-1:0}, temp=2, v={1082401:12}, v={1082401:12}] [L1259] return temp; VAL [\old(i)=1, \result=2, i=1, ldv_global_msg_list={-1:0}, temp=2, v={1082401:12}, v={1082401:12}] [L1308] RET ldv_atomic_add_return(1, (&kref->refcount)) VAL [kref={1082401:12}, kref={1082401:12}, ldv_atomic_add_return(1, (&kref->refcount))=2, ldv_global_msg_list={-1:0}] [L1374] RET ldv_kref_get(&kobj->kref) VAL [kobj={1082401:0}, kobj={1082401:0}, ldv_global_msg_list={-1:0}] [L1375] return kobj; VAL [\result={1082401:0}, kobj={1082401:0}, kobj={1082401:0}, ldv_global_msg_list={-1:0}] [L1437] RET ldv_kobject_get(kobj) VAL [kobj={1082401:0}, kobj={1082401:0}, ldv_global_msg_list={-1:0}, ldv_kobject_get(kobj)={1082401:0}] [L1447] RET f_22_get(kobj) VAL [kobj={1082401:0}, ldv_global_msg_list={-1:0}] [L1449] CALL ldv_kobject_put(kobj) VAL [kobj={1082401:0}, ldv_global_msg_list={-1:0}] [L1361] COND TRUE \read(*kobj) VAL [kobj={1082401:0}, kobj={1082401:0}, ldv_global_msg_list={-1:0}] [L1363] CALL ldv_kref_put(&kobj->kref, ldv_kobject_release) VAL [kref={1082401:12}, ldv_global_msg_list={-1:0}, release={-1:0}] [L1313] CALL, EXPR ldv_kref_sub(kref, 1, release) VAL [\old(count)=1, kref={1082401:12}, ldv_global_msg_list={-1:0}, release={-1:0}] [L1281] CALL, EXPR ldv_atomic_sub_return(((int) count), (&kref->refcount)) VAL [\old(i)=1, ldv_global_msg_list={-1:0}, v={1082401:12}] [L1264] int temp; VAL [\old(i)=1, i=1, ldv_global_msg_list={-1:0}, v={1082401:12}, v={1082401:12}] [L1265] EXPR v->counter VAL [\old(i)=1, i=1, ldv_global_msg_list={-1:0}, v={1082401:12}, v={1082401:12}, v->counter=2] [L1265] temp = v->counter [L1266] temp -= i VAL [\old(i)=1, i=1, ldv_global_msg_list={-1:0}, temp=1, v={1082401:12}, v={1082401:12}] [L1267] v->counter = temp VAL [\old(i)=1, i=1, ldv_global_msg_list={-1:0}, temp=1, v={1082401:12}, v={1082401:12}] [L1268] return temp; VAL [\old(i)=1, \result=1, i=1, ldv_global_msg_list={-1:0}, temp=1, v={1082401:12}, v={1082401:12}] [L1281] RET, EXPR ldv_atomic_sub_return(((int) count), (&kref->refcount)) VAL [\old(count)=1, count=1, kref={1082401:12}, kref={1082401:12}, ldv_atomic_sub_return(((int) count), (&kref->refcount))=1, ldv_global_msg_list={-1:0}, release={-1:0}, release={-1:0}] [L1281] COND FALSE !((ldv_atomic_sub_return(((int) count), (&kref->refcount)) == 0)) [L1285] return 0; VAL [\old(count)=1, \result=0, count=1, kref={1082401:12}, kref={1082401:12}, ldv_global_msg_list={-1:0}, release={-1:0}, release={-1:0}] [L1313] RET, EXPR ldv_kref_sub(kref, 1, release) VAL [kref={1082401:12}, kref={1082401:12}, ldv_global_msg_list={-1:0}, ldv_kref_sub(kref, 1, release)=0, release={-1:0}, release={-1:0}] [L1313] return ldv_kref_sub(kref, 1, release); [L1363] RET ldv_kref_put(&kobj->kref, ldv_kobject_release) VAL [kobj={1082401:0}, kobj={1082401:0}, ldv_global_msg_list={-1:0}, ldv_kref_put(&kobj->kref, ldv_kobject_release)=0] [L1449] RET ldv_kobject_put(kobj) VAL [kobj={1082401:0}, ldv_global_msg_list={-1:0}] [L1453] RET entry_point() VAL [ldv_global_msg_list={-1:0}] - StatisticsResult: Ultimate Automizer benchmark data CFG has 45 procedures, 318 locations, 67 error locations. UNSAFE Result, 228.8s OverallTime, 27 OverallIterations, 16 TraceHistogramMax, 133.8s AutomataDifference, 0.0s DeadEndRemovalTime, 0.0s HoareAnnotationTime, HoareTripleCheckerStatistics: 3142 SDtfs, 1387 SDslu, 22924 SDs, 0 SdLazy, 16434 SolverSat, 417 SolverUnsat, 9 SolverUnknown, 0 SolverNotchecked, 99.2s Time, PredicateUnifierStatistics: 0 DeclaredPredicates, 1842 GetRequests, 1313 SyntacticMatches, 41 SemanticMatches, 488 ConstructedPredicates, 2 IntricatePredicates, 0 DeprecatedPredicates, 3964 ImplicationChecksByTransitivity, 67.0s Time, 0.0s BasicInterpolantAutomatonTime, BiggestAbstraction: size=176occurred in iteration=0, traceCheckStatistics: No data available, InterpolantConsolidationStatistics: No data available, PathInvariantsStatistics: No data available, 0/0 InterpolantCoveringCapability, TotalInterpolationStatistics: No data available, 0.0s AbstIntTime, 0 AbstIntIterations, 0 AbstIntStrong, NaN AbsIntWeakeningRatio, NaN AbsIntAvgWeakeningVarsNumRemoved, NaN AbsIntAvgWeakenedConjuncts, 0.0s DumpTime, AutomataMinimizationStatistics: 0.1s AutomataMinimizationTime, 26 MinimizatonAttempts, 97 StatesRemovedByMinimization, 12 NontrivialMinimizations, HoareAnnotationStatistics: No data available, RefinementEngineStatistics: TraceCheckStatistics: 0.4s SsaConstructionTime, 7.6s SatisfiabilityAnalysisTime, 80.4s InterpolantComputationTime, 1734 NumberOfCodeBlocks, 1704 NumberOfCodeBlocksAsserted, 28 NumberOfCheckSat, 1705 ConstructedInterpolants, 344 QuantifiedInterpolants, 1272556 SizeOfPredicates, 236 NumberOfNonLiveVariables, 6497 ConjunctsInSsa, 669 ConjunctsInUnsatCore, 30 InterpolantComputations, 23 PerfectInterpolantSequences, 1833/2101 InterpolantCoveringCapability, InvariantSynthesisStatistics: No data available, InterpolantConsolidationStatistics: No data available, ReuseStatistics: No data available RESULT: Ultimate could not prove your program: unable to determine feasibility of some traces Received shutdown request...