./Ultimate.py --spec ../../sv-benchmarks/c/properties/no-overflow.prp --file ../../sv-benchmarks/c/busybox-1.22.0/basename_false-unreach-call_true-no-overflow_true-valid-memsafety.i --full-output --architecture 64bit -------------------------------------------------------------------------------- Checking for overflows Using default analysis Version 0cd3be1d Calling Ultimate with: java -Dosgi.configuration.area=/tmp/vcloud-vcloud-master/worker/working_dir_a2c4633f-02cb-4486-be39-ce67b7f0e7a6/bin-2019/uautomizer/data/config -Xmx12G -Xms1G -jar /tmp/vcloud-vcloud-master/worker/working_dir_a2c4633f-02cb-4486-be39-ce67b7f0e7a6/bin-2019/uautomizer/plugins/org.eclipse.equinox.launcher_1.3.100.v20150511-1540.jar -data @noDefault -ultimatedata /tmp/vcloud-vcloud-master/worker/working_dir_a2c4633f-02cb-4486-be39-ce67b7f0e7a6/bin-2019/uautomizer/data -tc /tmp/vcloud-vcloud-master/worker/working_dir_a2c4633f-02cb-4486-be39-ce67b7f0e7a6/bin-2019/uautomizer/config/AutomizerReach.xml -i ../../sv-benchmarks/c/busybox-1.22.0/basename_false-unreach-call_true-no-overflow_true-valid-memsafety.i -s /tmp/vcloud-vcloud-master/worker/working_dir_a2c4633f-02cb-4486-be39-ce67b7f0e7a6/bin-2019/uautomizer/config/svcomp-Overflow-64bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud-vcloud-master/worker/working_dir_a2c4633f-02cb-4486-be39-ce67b7f0e7a6/bin-2019/uautomizer --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(G ! overflow) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 64bit --witnessprinter.graph.data.programhash c57ebc44b313bf301635c00d4458ecfdd41286b1 .................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................. Execution finished normally Using bit-precise analysis No suitable file found in config dir /tmp/vcloud-vcloud-master/worker/working_dir_a2c4633f-02cb-4486-be39-ce67b7f0e7a6/bin-2019/uautomizer/config using search string *Overflow*64bit*_Bitvector*.epf No suitable settings file found using Overflow*64bit*_Bitvector ERROR: UNSUPPORTED PROPERTY Writing output log to file Ultimate.log Result: ERROR: ExceptionOrErrorResult: SMTLIBException: External (z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000)Received EOF on stdin. stderr output: (error "out of memory") --- Real Ultimate output --- This is Ultimate 0.1.23-0cd3be1 [2018-11-28 12:38:27,882 INFO L170 SettingsManager]: Resetting all preferences to default values... [2018-11-28 12:38:27,883 INFO L174 SettingsManager]: Resetting UltimateCore preferences to default values [2018-11-28 12:38:27,892 INFO L177 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2018-11-28 12:38:27,892 INFO L174 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2018-11-28 12:38:27,892 INFO L174 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2018-11-28 12:38:27,893 INFO L174 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2018-11-28 12:38:27,894 INFO L174 SettingsManager]: Resetting LassoRanker preferences to default values [2018-11-28 12:38:27,896 INFO L174 SettingsManager]: Resetting Reaching Definitions preferences to default values [2018-11-28 12:38:27,896 INFO L174 SettingsManager]: Resetting SyntaxChecker preferences to default values [2018-11-28 12:38:27,897 INFO L177 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2018-11-28 12:38:27,897 INFO L174 SettingsManager]: Resetting LTL2Aut preferences to default values [2018-11-28 12:38:27,897 INFO L174 SettingsManager]: Resetting PEA to Boogie preferences to default values [2018-11-28 12:38:27,898 INFO L174 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2018-11-28 12:38:27,899 INFO L174 SettingsManager]: Resetting ChcToBoogie preferences to default values [2018-11-28 12:38:27,899 INFO L174 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2018-11-28 12:38:27,900 INFO L174 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2018-11-28 12:38:27,901 INFO L174 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2018-11-28 12:38:27,902 INFO L174 SettingsManager]: Resetting CodeCheck preferences to default values [2018-11-28 12:38:27,904 INFO L174 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2018-11-28 12:38:27,905 INFO L174 SettingsManager]: Resetting RCFGBuilder preferences to default values [2018-11-28 12:38:27,905 INFO L174 SettingsManager]: Resetting TraceAbstraction preferences to default values [2018-11-28 12:38:27,907 INFO L177 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2018-11-28 12:38:27,907 INFO L177 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2018-11-28 12:38:27,907 INFO L174 SettingsManager]: Resetting TreeAutomizer preferences to default values [2018-11-28 12:38:27,908 INFO L174 SettingsManager]: Resetting IcfgTransformer preferences to default values [2018-11-28 12:38:27,909 INFO L174 SettingsManager]: Resetting Boogie Printer preferences to default values [2018-11-28 12:38:27,909 INFO L174 SettingsManager]: Resetting ReqPrinter preferences to default values [2018-11-28 12:38:27,910 INFO L174 SettingsManager]: Resetting Witness Printer preferences to default values [2018-11-28 12:38:27,911 INFO L177 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2018-11-28 12:38:27,911 INFO L174 SettingsManager]: Resetting CDTParser preferences to default values [2018-11-28 12:38:27,911 INFO L177 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2018-11-28 12:38:27,912 INFO L177 SettingsManager]: ReqParser provides no preferences, ignoring... [2018-11-28 12:38:27,912 INFO L174 SettingsManager]: Resetting SmtParser preferences to default values [2018-11-28 12:38:27,913 INFO L174 SettingsManager]: Resetting Witness Parser preferences to default values [2018-11-28 12:38:27,913 INFO L181 SettingsManager]: Finished resetting all preferences to default values... [2018-11-28 12:38:27,913 INFO L98 SettingsManager]: Beginning loading settings from /tmp/vcloud-vcloud-master/worker/working_dir_a2c4633f-02cb-4486-be39-ce67b7f0e7a6/bin-2019/uautomizer/config/svcomp-Overflow-64bit-Automizer_Default.epf [2018-11-28 12:38:27,922 INFO L110 SettingsManager]: Loading preferences was successful [2018-11-28 12:38:27,923 INFO L112 SettingsManager]: Preferences different from defaults after loading the file: [2018-11-28 12:38:27,923 INFO L131 SettingsManager]: Preferences of Boogie Procedure Inliner differ from their defaults: [2018-11-28 12:38:27,923 INFO L133 SettingsManager]: * ... calls to implemented procedures=ONLY_FOR_CONCURRENT_PROGRAMS [2018-11-28 12:38:27,924 INFO L131 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2018-11-28 12:38:27,924 INFO L133 SettingsManager]: * Create parallel compositions if possible=false [2018-11-28 12:38:27,924 INFO L133 SettingsManager]: * Use SBE=true [2018-11-28 12:38:27,924 INFO L131 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2018-11-28 12:38:27,924 INFO L133 SettingsManager]: * Check unreachability of error function in SV-COMP mode=false [2018-11-28 12:38:27,925 INFO L133 SettingsManager]: * Overapproximate operations on floating types=true [2018-11-28 12:38:27,925 INFO L133 SettingsManager]: * Check division by zero=IGNORE [2018-11-28 12:38:27,925 INFO L133 SettingsManager]: * Pointer to allocated memory at dereference=IGNORE [2018-11-28 12:38:27,925 INFO L133 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=IGNORE [2018-11-28 12:38:27,925 INFO L133 SettingsManager]: * Check array bounds for arrays that are off heap=IGNORE [2018-11-28 12:38:27,925 INFO L133 SettingsManager]: * Check absence of signed integer overflows=true [2018-11-28 12:38:27,925 INFO L133 SettingsManager]: * Check if freed pointer was valid=false [2018-11-28 12:38:27,925 INFO L133 SettingsManager]: * Use constant arrays=true [2018-11-28 12:38:27,926 INFO L133 SettingsManager]: * Pointer base address is valid at dereference=IGNORE [2018-11-28 12:38:27,926 INFO L131 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2018-11-28 12:38:27,926 INFO L133 SettingsManager]: * Size of a code block=SequenceOfStatements [2018-11-28 12:38:27,926 INFO L133 SettingsManager]: * To the following directory=./dump/ [2018-11-28 12:38:27,926 INFO L133 SettingsManager]: * SMT solver=External_DefaultMode [2018-11-28 12:38:27,926 INFO L133 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2018-11-28 12:38:27,926 INFO L131 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2018-11-28 12:38:27,926 INFO L133 SettingsManager]: * Compute Interpolants along a Counterexample=FPandBP [2018-11-28 12:38:27,927 INFO L133 SettingsManager]: * Positions where we compute the Hoare Annotation=LoopsAndPotentialCycles [2018-11-28 12:38:27,927 INFO L133 SettingsManager]: * Trace refinement strategy=CAMEL [2018-11-28 12:38:27,927 INFO L133 SettingsManager]: * SMT solver=External_ModelsAndUnsatCoreMode [2018-11-28 12:38:27,927 INFO L133 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in [2018-11-28 12:38:27,927 INFO L133 SettingsManager]: * Compute Hoare Annotation of negated interpolant automaton, abstraction and CFG=true Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud-vcloud-master/worker/working_dir_a2c4633f-02cb-4486-be39-ce67b7f0e7a6/bin-2019/uautomizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(G ! overflow) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 64bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> c57ebc44b313bf301635c00d4458ecfdd41286b1 [2018-11-28 12:38:27,952 INFO L81 nceAwareModelManager]: Repository-Root is: /tmp [2018-11-28 12:38:27,961 INFO L258 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2018-11-28 12:38:27,963 INFO L214 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2018-11-28 12:38:27,965 INFO L271 PluginConnector]: Initializing CDTParser... [2018-11-28 12:38:27,965 INFO L276 PluginConnector]: CDTParser initialized [2018-11-28 12:38:27,965 INFO L418 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud-vcloud-master/worker/working_dir_a2c4633f-02cb-4486-be39-ce67b7f0e7a6/bin-2019/uautomizer/../../sv-benchmarks/c/busybox-1.22.0/basename_false-unreach-call_true-no-overflow_true-valid-memsafety.i [2018-11-28 12:38:28,003 INFO L221 CDTParser]: Created temporary CDT project at /tmp/vcloud-vcloud-master/worker/working_dir_a2c4633f-02cb-4486-be39-ce67b7f0e7a6/bin-2019/uautomizer/data/f0bcaa0fe/cbb526a94a0d41b8b4e0f2f75e04a1a7/FLAG258a223b5 [2018-11-28 12:38:28,415 INFO L307 CDTParser]: Found 1 translation units. [2018-11-28 12:38:28,416 INFO L161 CDTParser]: Scanning /tmp/vcloud-vcloud-master/worker/working_dir_a2c4633f-02cb-4486-be39-ce67b7f0e7a6/sv-benchmarks/c/busybox-1.22.0/basename_false-unreach-call_true-no-overflow_true-valid-memsafety.i [2018-11-28 12:38:28,429 INFO L355 CDTParser]: About to delete temporary CDT project at /tmp/vcloud-vcloud-master/worker/working_dir_a2c4633f-02cb-4486-be39-ce67b7f0e7a6/bin-2019/uautomizer/data/f0bcaa0fe/cbb526a94a0d41b8b4e0f2f75e04a1a7/FLAG258a223b5 [2018-11-28 12:38:28,772 INFO L363 CDTParser]: Successfully deleted /tmp/vcloud-vcloud-master/worker/working_dir_a2c4633f-02cb-4486-be39-ce67b7f0e7a6/bin-2019/uautomizer/data/f0bcaa0fe/cbb526a94a0d41b8b4e0f2f75e04a1a7 [2018-11-28 12:38:28,776 INFO L296 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2018-11-28 12:38:28,777 INFO L131 ToolchainWalker]: Walking toolchain with 6 elements. [2018-11-28 12:38:28,778 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2018-11-28 12:38:28,778 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2018-11-28 12:38:28,782 INFO L276 PluginConnector]: CACSL2BoogieTranslator initialized [2018-11-28 12:38:28,783 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 28.11 12:38:28" (1/1) ... [2018-11-28 12:38:28,786 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@4664a3e4 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 12:38:28, skipping insertion in model container [2018-11-28 12:38:28,787 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 28.11 12:38:28" (1/1) ... [2018-11-28 12:38:28,793 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2018-11-28 12:38:28,828 INFO L176 MainTranslator]: Built tables and reachable declarations [2018-11-28 12:38:29,272 INFO L203 PostProcessor]: Analyzing one entry point: main [2018-11-28 12:38:29,292 INFO L191 MainTranslator]: Completed pre-run [2018-11-28 12:38:29,350 INFO L203 PostProcessor]: Analyzing one entry point: main [2018-11-28 12:38:29,491 INFO L195 MainTranslator]: Completed translation [2018-11-28 12:38:29,491 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 12:38:29 WrapperNode [2018-11-28 12:38:29,492 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2018-11-28 12:38:29,492 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2018-11-28 12:38:29,492 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2018-11-28 12:38:29,492 INFO L276 PluginConnector]: Boogie Procedure Inliner initialized [2018-11-28 12:38:29,499 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 12:38:29" (1/1) ... [2018-11-28 12:38:29,521 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 12:38:29" (1/1) ... [2018-11-28 12:38:29,531 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2018-11-28 12:38:29,532 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2018-11-28 12:38:29,532 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2018-11-28 12:38:29,532 INFO L276 PluginConnector]: Boogie Preprocessor initialized [2018-11-28 12:38:29,540 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 12:38:29" (1/1) ... [2018-11-28 12:38:29,540 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 12:38:29" (1/1) ... [2018-11-28 12:38:29,545 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 12:38:29" (1/1) ... [2018-11-28 12:38:29,546 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 12:38:29" (1/1) ... [2018-11-28 12:38:29,574 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 12:38:29" (1/1) ... [2018-11-28 12:38:29,580 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 12:38:29" (1/1) ... [2018-11-28 12:38:29,586 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 12:38:29" (1/1) ... [2018-11-28 12:38:29,593 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2018-11-28 12:38:29,593 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2018-11-28 12:38:29,593 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2018-11-28 12:38:29,593 INFO L276 PluginConnector]: RCFGBuilder initialized [2018-11-28 12:38:29,594 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 12:38:29" (1/1) ... No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_a2c4633f-02cb-4486-be39-ce67b7f0e7a6/bin-2019/uautomizer/z3 Starting monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2018-11-28 12:38:29,638 INFO L130 BoogieDeclarations]: Found specification of procedure __main [2018-11-28 12:38:29,639 INFO L138 BoogieDeclarations]: Found implementation of procedure __main [2018-11-28 12:38:29,639 INFO L130 BoogieDeclarations]: Found specification of procedure last_char_is [2018-11-28 12:38:29,639 INFO L138 BoogieDeclarations]: Found implementation of procedure last_char_is [2018-11-28 12:38:29,639 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.init [2018-11-28 12:38:29,639 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.init [2018-11-28 12:38:29,639 INFO L130 BoogieDeclarations]: Found specification of procedure read~$Pointer$ [2018-11-28 12:38:29,640 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.dealloc [2018-11-28 12:38:29,640 INFO L130 BoogieDeclarations]: Found specification of procedure safe_write [2018-11-28 12:38:29,640 INFO L138 BoogieDeclarations]: Found implementation of procedure safe_write [2018-11-28 12:38:29,640 INFO L130 BoogieDeclarations]: Found specification of procedure bb_get_last_path_component_nostrip [2018-11-28 12:38:29,640 INFO L138 BoogieDeclarations]: Found implementation of procedure bb_get_last_path_component_nostrip [2018-11-28 12:38:29,640 INFO L130 BoogieDeclarations]: Found specification of procedure bb_get_last_path_component_strip [2018-11-28 12:38:29,640 INFO L138 BoogieDeclarations]: Found implementation of procedure bb_get_last_path_component_strip [2018-11-28 12:38:29,641 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.alloc [2018-11-28 12:38:29,641 INFO L130 BoogieDeclarations]: Found specification of procedure read~int [2018-11-28 12:38:29,641 INFO L130 BoogieDeclarations]: Found specification of procedure write [2018-11-28 12:38:29,641 INFO L138 BoogieDeclarations]: Found implementation of procedure write [2018-11-28 12:38:29,641 INFO L130 BoogieDeclarations]: Found specification of procedure write~int [2018-11-28 12:38:29,642 INFO L130 BoogieDeclarations]: Found specification of procedure strrchr [2018-11-28 12:38:29,642 INFO L130 BoogieDeclarations]: Found specification of procedure main [2018-11-28 12:38:29,642 INFO L138 BoogieDeclarations]: Found implementation of procedure main [2018-11-28 12:38:29,642 INFO L130 BoogieDeclarations]: Found specification of procedure write~$Pointer$ [2018-11-28 12:38:29,642 INFO L130 BoogieDeclarations]: Found specification of procedure full_write [2018-11-28 12:38:29,642 INFO L138 BoogieDeclarations]: Found implementation of procedure full_write [2018-11-28 12:38:29,642 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int [2018-11-28 12:38:29,643 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2018-11-28 12:38:29,643 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2018-11-28 12:38:30,481 INFO L275 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2018-11-28 12:38:30,481 INFO L280 CfgBuilder]: Removed 8 assue(true) statements. [2018-11-28 12:38:30,482 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 28.11 12:38:30 BoogieIcfgContainer [2018-11-28 12:38:30,482 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2018-11-28 12:38:30,483 INFO L113 PluginConnector]: ------------------------TraceAbstraction---------------------------- [2018-11-28 12:38:30,483 INFO L271 PluginConnector]: Initializing TraceAbstraction... [2018-11-28 12:38:30,486 INFO L276 PluginConnector]: TraceAbstraction initialized [2018-11-28 12:38:30,486 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "CDTParser AST 28.11 12:38:28" (1/3) ... [2018-11-28 12:38:30,487 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@4716d349 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 28.11 12:38:30, skipping insertion in model container [2018-11-28 12:38:30,487 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 12:38:29" (2/3) ... [2018-11-28 12:38:30,487 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@4716d349 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 28.11 12:38:30, skipping insertion in model container [2018-11-28 12:38:30,487 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 28.11 12:38:30" (3/3) ... [2018-11-28 12:38:30,489 INFO L112 eAbstractionObserver]: Analyzing ICFG basename_false-unreach-call_true-no-overflow_true-valid-memsafety.i [2018-11-28 12:38:30,497 INFO L156 ceAbstractionStarter]: Automizer settings: Hoare:true NWA Interpolation:FPandBP Determinization: PREDICATE_ABSTRACTION [2018-11-28 12:38:30,503 INFO L168 ceAbstractionStarter]: Appying trace abstraction to program that has 28 error locations. [2018-11-28 12:38:30,517 INFO L257 AbstractCegarLoop]: Starting to check reachability of 28 error locations. [2018-11-28 12:38:30,541 INFO L133 ementStrategyFactory]: Using default assertion order modulation [2018-11-28 12:38:30,541 INFO L382 AbstractCegarLoop]: Interprodecural is true [2018-11-28 12:38:30,541 INFO L383 AbstractCegarLoop]: Hoare is true [2018-11-28 12:38:30,541 INFO L384 AbstractCegarLoop]: Compute interpolants for FPandBP [2018-11-28 12:38:30,542 INFO L385 AbstractCegarLoop]: Backedges is STRAIGHT_LINE [2018-11-28 12:38:30,542 INFO L386 AbstractCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2018-11-28 12:38:30,542 INFO L387 AbstractCegarLoop]: Difference is false [2018-11-28 12:38:30,542 INFO L388 AbstractCegarLoop]: Minimize is MINIMIZE_SEVPA [2018-11-28 12:38:30,542 INFO L393 AbstractCegarLoop]: ======== Iteration 0==of CEGAR loop == AllErrorsAtOnce======== [2018-11-28 12:38:30,559 INFO L276 IsEmpty]: Start isEmpty. Operand 154 states. [2018-11-28 12:38:30,563 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 9 [2018-11-28 12:38:30,563 INFO L394 BasicCegarLoop]: Found error trace [2018-11-28 12:38:30,563 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1] [2018-11-28 12:38:30,565 INFO L423 AbstractCegarLoop]: === Iteration 1 === [__mainErr0ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr7ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr6ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr4ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr2ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr5ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr8ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr1ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr3ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr9ASSERT_VIOLATIONINTEGER_OVERFLOW, full_writeErr0ASSERT_VIOLATIONINTEGER_OVERFLOW, full_writeErr1ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr9ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr10ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr14ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr7ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr6ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr15ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr0ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr3ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr8ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr12ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr13ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr1ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr4ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr5ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr2ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr11ASSERT_VIOLATIONINTEGER_OVERFLOW]=== [2018-11-28 12:38:30,570 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-28 12:38:30,570 INFO L82 PathProgramCache]: Analyzing trace with hash -51273939, now seen corresponding path program 1 times [2018-11-28 12:38:30,571 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-28 12:38:30,572 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-28 12:38:30,645 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 12:38:30,645 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-28 12:38:30,645 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 12:38:30,746 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-28 12:38:30,859 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-28 12:38:30,862 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-28 12:38:30,862 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2018-11-28 12:38:30,865 INFO L459 AbstractCegarLoop]: Interpolant automaton has 3 states [2018-11-28 12:38:30,876 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-28 12:38:30,876 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-28 12:38:30,878 INFO L87 Difference]: Start difference. First operand 154 states. Second operand 3 states. [2018-11-28 12:38:30,934 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-28 12:38:30,935 INFO L93 Difference]: Finished difference Result 298 states and 388 transitions. [2018-11-28 12:38:30,935 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-28 12:38:30,936 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 8 [2018-11-28 12:38:30,937 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-28 12:38:30,945 INFO L225 Difference]: With dead ends: 298 [2018-11-28 12:38:30,946 INFO L226 Difference]: Without dead ends: 149 [2018-11-28 12:38:30,949 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 2 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-28 12:38:30,962 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 149 states. [2018-11-28 12:38:30,980 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 149 to 149. [2018-11-28 12:38:30,981 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 149 states. [2018-11-28 12:38:30,982 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 149 states to 149 states and 183 transitions. [2018-11-28 12:38:30,984 INFO L78 Accepts]: Start accepts. Automaton has 149 states and 183 transitions. Word has length 8 [2018-11-28 12:38:30,984 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-28 12:38:30,984 INFO L480 AbstractCegarLoop]: Abstraction has 149 states and 183 transitions. [2018-11-28 12:38:30,984 INFO L481 AbstractCegarLoop]: Interpolant automaton has 3 states. [2018-11-28 12:38:30,984 INFO L276 IsEmpty]: Start isEmpty. Operand 149 states and 183 transitions. [2018-11-28 12:38:30,984 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 10 [2018-11-28 12:38:30,984 INFO L394 BasicCegarLoop]: Found error trace [2018-11-28 12:38:30,985 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-28 12:38:30,985 INFO L423 AbstractCegarLoop]: === Iteration 2 === [__mainErr0ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr7ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr6ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr4ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr2ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr5ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr8ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr1ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr3ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr9ASSERT_VIOLATIONINTEGER_OVERFLOW, full_writeErr0ASSERT_VIOLATIONINTEGER_OVERFLOW, full_writeErr1ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr9ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr10ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr14ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr7ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr6ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr15ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr0ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr3ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr8ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr12ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr13ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr1ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr4ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr5ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr2ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr11ASSERT_VIOLATIONINTEGER_OVERFLOW]=== [2018-11-28 12:38:30,985 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-28 12:38:30,985 INFO L82 PathProgramCache]: Analyzing trace with hash -1589491972, now seen corresponding path program 1 times [2018-11-28 12:38:30,986 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-28 12:38:30,986 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-28 12:38:30,995 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 12:38:30,995 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-28 12:38:30,995 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 12:38:31,021 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-28 12:38:31,084 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-28 12:38:31,084 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-28 12:38:31,085 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2018-11-28 12:38:31,086 INFO L459 AbstractCegarLoop]: Interpolant automaton has 3 states [2018-11-28 12:38:31,086 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-28 12:38:31,086 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-28 12:38:31,087 INFO L87 Difference]: Start difference. First operand 149 states and 183 transitions. Second operand 3 states. [2018-11-28 12:38:31,114 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-28 12:38:31,114 INFO L93 Difference]: Finished difference Result 152 states and 186 transitions. [2018-11-28 12:38:31,114 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-28 12:38:31,115 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 9 [2018-11-28 12:38:31,115 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-28 12:38:31,116 INFO L225 Difference]: With dead ends: 152 [2018-11-28 12:38:31,116 INFO L226 Difference]: Without dead ends: 151 [2018-11-28 12:38:31,117 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 2 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-28 12:38:31,118 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 151 states. [2018-11-28 12:38:31,125 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 151 to 151. [2018-11-28 12:38:31,126 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 151 states. [2018-11-28 12:38:31,127 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 151 states to 151 states and 185 transitions. [2018-11-28 12:38:31,127 INFO L78 Accepts]: Start accepts. Automaton has 151 states and 185 transitions. Word has length 9 [2018-11-28 12:38:31,128 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-28 12:38:31,128 INFO L480 AbstractCegarLoop]: Abstraction has 151 states and 185 transitions. [2018-11-28 12:38:31,128 INFO L481 AbstractCegarLoop]: Interpolant automaton has 3 states. [2018-11-28 12:38:31,128 INFO L276 IsEmpty]: Start isEmpty. Operand 151 states and 185 transitions. [2018-11-28 12:38:31,128 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 13 [2018-11-28 12:38:31,128 INFO L394 BasicCegarLoop]: Found error trace [2018-11-28 12:38:31,129 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-28 12:38:31,129 INFO L423 AbstractCegarLoop]: === Iteration 3 === [__mainErr0ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr7ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr6ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr4ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr2ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr5ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr8ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr1ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr3ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr9ASSERT_VIOLATIONINTEGER_OVERFLOW, full_writeErr0ASSERT_VIOLATIONINTEGER_OVERFLOW, full_writeErr1ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr9ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr10ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr14ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr7ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr6ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr15ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr0ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr3ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr8ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr12ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr13ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr1ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr4ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr5ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr2ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr11ASSERT_VIOLATIONINTEGER_OVERFLOW]=== [2018-11-28 12:38:31,129 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-28 12:38:31,129 INFO L82 PathProgramCache]: Analyzing trace with hash -540770008, now seen corresponding path program 1 times [2018-11-28 12:38:31,130 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-28 12:38:31,130 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-28 12:38:31,139 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 12:38:31,139 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-28 12:38:31,139 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 12:38:31,164 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-28 12:38:31,219 INFO L134 CoverageAnalysis]: Checked inductivity of 1 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2018-11-28 12:38:31,219 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-28 12:38:31,219 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2018-11-28 12:38:31,219 INFO L459 AbstractCegarLoop]: Interpolant automaton has 3 states [2018-11-28 12:38:31,219 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-28 12:38:31,220 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-28 12:38:31,220 INFO L87 Difference]: Start difference. First operand 151 states and 185 transitions. Second operand 3 states. [2018-11-28 12:38:31,282 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-28 12:38:31,282 INFO L93 Difference]: Finished difference Result 151 states and 185 transitions. [2018-11-28 12:38:31,282 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-28 12:38:31,283 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 12 [2018-11-28 12:38:31,283 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-28 12:38:31,284 INFO L225 Difference]: With dead ends: 151 [2018-11-28 12:38:31,284 INFO L226 Difference]: Without dead ends: 147 [2018-11-28 12:38:31,284 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 2 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-28 12:38:31,285 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 147 states. [2018-11-28 12:38:31,292 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 147 to 147. [2018-11-28 12:38:31,292 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 147 states. [2018-11-28 12:38:31,293 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 147 states to 147 states and 181 transitions. [2018-11-28 12:38:31,293 INFO L78 Accepts]: Start accepts. Automaton has 147 states and 181 transitions. Word has length 12 [2018-11-28 12:38:31,294 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-28 12:38:31,294 INFO L480 AbstractCegarLoop]: Abstraction has 147 states and 181 transitions. [2018-11-28 12:38:31,294 INFO L481 AbstractCegarLoop]: Interpolant automaton has 3 states. [2018-11-28 12:38:31,294 INFO L276 IsEmpty]: Start isEmpty. Operand 147 states and 181 transitions. [2018-11-28 12:38:31,294 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 13 [2018-11-28 12:38:31,294 INFO L394 BasicCegarLoop]: Found error trace [2018-11-28 12:38:31,295 INFO L402 BasicCegarLoop]: trace histogram [2, 2, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-28 12:38:31,295 INFO L423 AbstractCegarLoop]: === Iteration 4 === [__mainErr0ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr7ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr6ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr4ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr2ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr5ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr8ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr1ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr3ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr9ASSERT_VIOLATIONINTEGER_OVERFLOW, full_writeErr0ASSERT_VIOLATIONINTEGER_OVERFLOW, full_writeErr1ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr9ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr10ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr14ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr7ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr6ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr15ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr0ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr3ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr8ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr12ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr13ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr1ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr4ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr5ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr2ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr11ASSERT_VIOLATIONINTEGER_OVERFLOW]=== [2018-11-28 12:38:31,295 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-28 12:38:31,296 INFO L82 PathProgramCache]: Analyzing trace with hash -540768278, now seen corresponding path program 1 times [2018-11-28 12:38:31,296 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-28 12:38:31,296 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-28 12:38:31,305 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 12:38:31,305 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-28 12:38:31,305 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 12:38:31,329 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-28 12:38:31,379 INFO L134 CoverageAnalysis]: Checked inductivity of 3 backedges. 3 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-28 12:38:31,379 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-28 12:38:31,380 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2018-11-28 12:38:31,380 INFO L459 AbstractCegarLoop]: Interpolant automaton has 3 states [2018-11-28 12:38:31,380 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-28 12:38:31,380 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-28 12:38:31,380 INFO L87 Difference]: Start difference. First operand 147 states and 181 transitions. Second operand 3 states. [2018-11-28 12:38:31,402 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-28 12:38:31,402 INFO L93 Difference]: Finished difference Result 147 states and 181 transitions. [2018-11-28 12:38:31,403 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-28 12:38:31,403 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 12 [2018-11-28 12:38:31,403 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-28 12:38:31,404 INFO L225 Difference]: With dead ends: 147 [2018-11-28 12:38:31,404 INFO L226 Difference]: Without dead ends: 146 [2018-11-28 12:38:31,405 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 2 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-28 12:38:31,405 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 146 states. [2018-11-28 12:38:31,411 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 146 to 144. [2018-11-28 12:38:31,411 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 144 states. [2018-11-28 12:38:31,412 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 144 states to 144 states and 178 transitions. [2018-11-28 12:38:31,412 INFO L78 Accepts]: Start accepts. Automaton has 144 states and 178 transitions. Word has length 12 [2018-11-28 12:38:31,413 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-28 12:38:31,413 INFO L480 AbstractCegarLoop]: Abstraction has 144 states and 178 transitions. [2018-11-28 12:38:31,413 INFO L481 AbstractCegarLoop]: Interpolant automaton has 3 states. [2018-11-28 12:38:31,413 INFO L276 IsEmpty]: Start isEmpty. Operand 144 states and 178 transitions. [2018-11-28 12:38:31,413 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 14 [2018-11-28 12:38:31,413 INFO L394 BasicCegarLoop]: Found error trace [2018-11-28 12:38:31,413 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-28 12:38:31,414 INFO L423 AbstractCegarLoop]: === Iteration 5 === [__mainErr0ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr7ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr6ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr4ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr2ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr5ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr8ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr1ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr3ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr9ASSERT_VIOLATIONINTEGER_OVERFLOW, full_writeErr0ASSERT_VIOLATIONINTEGER_OVERFLOW, full_writeErr1ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr9ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr10ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr14ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr7ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr6ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr15ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr0ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr3ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr8ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr12ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr13ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr1ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr4ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr5ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr2ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr11ASSERT_VIOLATIONINTEGER_OVERFLOW]=== [2018-11-28 12:38:31,414 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-28 12:38:31,414 INFO L82 PathProgramCache]: Analyzing trace with hash 415999081, now seen corresponding path program 1 times [2018-11-28 12:38:31,415 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-28 12:38:31,415 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-28 12:38:31,423 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 12:38:31,423 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-28 12:38:31,423 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 12:38:31,445 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-28 12:38:31,537 INFO L134 CoverageAnalysis]: Checked inductivity of 1 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2018-11-28 12:38:31,538 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-28 12:38:31,538 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2018-11-28 12:38:31,538 INFO L459 AbstractCegarLoop]: Interpolant automaton has 3 states [2018-11-28 12:38:31,538 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-28 12:38:31,538 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-28 12:38:31,538 INFO L87 Difference]: Start difference. First operand 144 states and 178 transitions. Second operand 3 states. [2018-11-28 12:38:31,594 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-28 12:38:31,594 INFO L93 Difference]: Finished difference Result 144 states and 178 transitions. [2018-11-28 12:38:31,596 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-28 12:38:31,596 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 13 [2018-11-28 12:38:31,596 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-28 12:38:31,597 INFO L225 Difference]: With dead ends: 144 [2018-11-28 12:38:31,597 INFO L226 Difference]: Without dead ends: 142 [2018-11-28 12:38:31,597 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 2 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-28 12:38:31,598 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 142 states. [2018-11-28 12:38:31,609 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 142 to 142. [2018-11-28 12:38:31,609 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 142 states. [2018-11-28 12:38:31,610 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 142 states to 142 states and 176 transitions. [2018-11-28 12:38:31,610 INFO L78 Accepts]: Start accepts. Automaton has 142 states and 176 transitions. Word has length 13 [2018-11-28 12:38:31,610 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-28 12:38:31,610 INFO L480 AbstractCegarLoop]: Abstraction has 142 states and 176 transitions. [2018-11-28 12:38:31,610 INFO L481 AbstractCegarLoop]: Interpolant automaton has 3 states. [2018-11-28 12:38:31,610 INFO L276 IsEmpty]: Start isEmpty. Operand 142 states and 176 transitions. [2018-11-28 12:38:31,610 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 16 [2018-11-28 12:38:31,611 INFO L394 BasicCegarLoop]: Found error trace [2018-11-28 12:38:31,611 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-28 12:38:31,611 INFO L423 AbstractCegarLoop]: === Iteration 6 === [__mainErr0ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr7ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr6ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr4ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr2ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr5ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr8ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr1ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr3ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr9ASSERT_VIOLATIONINTEGER_OVERFLOW, full_writeErr0ASSERT_VIOLATIONINTEGER_OVERFLOW, full_writeErr1ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr9ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr10ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr14ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr7ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr6ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr15ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr0ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr3ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr8ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr12ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr13ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr1ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr4ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr5ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr2ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr11ASSERT_VIOLATIONINTEGER_OVERFLOW]=== [2018-11-28 12:38:31,611 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-28 12:38:31,612 INFO L82 PathProgramCache]: Analyzing trace with hash 343163019, now seen corresponding path program 1 times [2018-11-28 12:38:31,612 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-28 12:38:31,612 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-28 12:38:31,619 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 12:38:31,620 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-28 12:38:31,620 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 12:38:31,639 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-28 12:38:31,700 INFO L134 CoverageAnalysis]: Checked inductivity of 1 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2018-11-28 12:38:31,700 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-28 12:38:31,700 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2018-11-28 12:38:31,701 INFO L459 AbstractCegarLoop]: Interpolant automaton has 3 states [2018-11-28 12:38:31,701 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-28 12:38:31,701 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-28 12:38:31,701 INFO L87 Difference]: Start difference. First operand 142 states and 176 transitions. Second operand 3 states. [2018-11-28 12:38:31,739 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-28 12:38:31,739 INFO L93 Difference]: Finished difference Result 142 states and 176 transitions. [2018-11-28 12:38:31,740 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-28 12:38:31,740 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 15 [2018-11-28 12:38:31,740 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-28 12:38:31,741 INFO L225 Difference]: With dead ends: 142 [2018-11-28 12:38:31,741 INFO L226 Difference]: Without dead ends: 140 [2018-11-28 12:38:31,741 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 2 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-28 12:38:31,741 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 140 states. [2018-11-28 12:38:31,746 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 140 to 140. [2018-11-28 12:38:31,746 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 140 states. [2018-11-28 12:38:31,747 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 140 states to 140 states and 174 transitions. [2018-11-28 12:38:31,747 INFO L78 Accepts]: Start accepts. Automaton has 140 states and 174 transitions. Word has length 15 [2018-11-28 12:38:31,747 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-28 12:38:31,747 INFO L480 AbstractCegarLoop]: Abstraction has 140 states and 174 transitions. [2018-11-28 12:38:31,747 INFO L481 AbstractCegarLoop]: Interpolant automaton has 3 states. [2018-11-28 12:38:31,747 INFO L276 IsEmpty]: Start isEmpty. Operand 140 states and 174 transitions. [2018-11-28 12:38:31,748 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 23 [2018-11-28 12:38:31,748 INFO L394 BasicCegarLoop]: Found error trace [2018-11-28 12:38:31,748 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-28 12:38:31,748 INFO L423 AbstractCegarLoop]: === Iteration 7 === [__mainErr0ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr7ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr6ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr4ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr2ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr5ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr8ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr1ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr3ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr9ASSERT_VIOLATIONINTEGER_OVERFLOW, full_writeErr0ASSERT_VIOLATIONINTEGER_OVERFLOW, full_writeErr1ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr9ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr10ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr14ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr7ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr6ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr15ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr0ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr3ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr8ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr12ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr13ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr1ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr4ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr5ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr2ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr11ASSERT_VIOLATIONINTEGER_OVERFLOW]=== [2018-11-28 12:38:31,749 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-28 12:38:31,749 INFO L82 PathProgramCache]: Analyzing trace with hash -1254383198, now seen corresponding path program 1 times [2018-11-28 12:38:31,749 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-28 12:38:31,749 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-28 12:38:31,756 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 12:38:31,757 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-28 12:38:31,757 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 12:38:31,779 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-28 12:38:31,832 INFO L134 CoverageAnalysis]: Checked inductivity of 1 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2018-11-28 12:38:31,832 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-28 12:38:31,833 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-28 12:38:31,833 INFO L459 AbstractCegarLoop]: Interpolant automaton has 3 states [2018-11-28 12:38:31,833 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-28 12:38:31,833 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-28 12:38:31,833 INFO L87 Difference]: Start difference. First operand 140 states and 174 transitions. Second operand 3 states. [2018-11-28 12:38:31,860 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-28 12:38:31,861 INFO L93 Difference]: Finished difference Result 264 states and 334 transitions. [2018-11-28 12:38:31,861 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-28 12:38:31,861 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 22 [2018-11-28 12:38:31,861 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-28 12:38:31,862 INFO L225 Difference]: With dead ends: 264 [2018-11-28 12:38:31,862 INFO L226 Difference]: Without dead ends: 143 [2018-11-28 12:38:31,863 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-28 12:38:31,863 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 143 states. [2018-11-28 12:38:31,868 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 143 to 143. [2018-11-28 12:38:31,868 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 143 states. [2018-11-28 12:38:31,868 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 143 states to 143 states and 177 transitions. [2018-11-28 12:38:31,869 INFO L78 Accepts]: Start accepts. Automaton has 143 states and 177 transitions. Word has length 22 [2018-11-28 12:38:31,869 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-28 12:38:31,869 INFO L480 AbstractCegarLoop]: Abstraction has 143 states and 177 transitions. [2018-11-28 12:38:31,869 INFO L481 AbstractCegarLoop]: Interpolant automaton has 3 states. [2018-11-28 12:38:31,869 INFO L276 IsEmpty]: Start isEmpty. Operand 143 states and 177 transitions. [2018-11-28 12:38:31,870 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 26 [2018-11-28 12:38:31,870 INFO L394 BasicCegarLoop]: Found error trace [2018-11-28 12:38:31,870 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-28 12:38:31,870 INFO L423 AbstractCegarLoop]: === Iteration 8 === [__mainErr0ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr7ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr6ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr4ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr2ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr5ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr8ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr1ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr3ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr9ASSERT_VIOLATIONINTEGER_OVERFLOW, full_writeErr0ASSERT_VIOLATIONINTEGER_OVERFLOW, full_writeErr1ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr9ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr10ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr14ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr7ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr6ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr15ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr0ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr3ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr8ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr12ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr13ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr1ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr4ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr5ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr2ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr11ASSERT_VIOLATIONINTEGER_OVERFLOW]=== [2018-11-28 12:38:31,870 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-28 12:38:31,871 INFO L82 PathProgramCache]: Analyzing trace with hash 1182405925, now seen corresponding path program 1 times [2018-11-28 12:38:31,871 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-28 12:38:31,871 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-28 12:38:31,878 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 12:38:31,878 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-28 12:38:31,878 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 12:38:31,901 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-28 12:38:31,976 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 2 trivial. 0 not checked. [2018-11-28 12:38:31,976 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-28 12:38:31,977 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-28 12:38:31,977 INFO L459 AbstractCegarLoop]: Interpolant automaton has 4 states [2018-11-28 12:38:31,977 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2018-11-28 12:38:31,977 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2018-11-28 12:38:31,977 INFO L87 Difference]: Start difference. First operand 143 states and 177 transitions. Second operand 4 states. [2018-11-28 12:38:32,056 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-28 12:38:32,056 INFO L93 Difference]: Finished difference Result 151 states and 187 transitions. [2018-11-28 12:38:32,057 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2018-11-28 12:38:32,057 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 25 [2018-11-28 12:38:32,057 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-28 12:38:32,058 INFO L225 Difference]: With dead ends: 151 [2018-11-28 12:38:32,059 INFO L226 Difference]: Without dead ends: 150 [2018-11-28 12:38:32,059 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 4 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2018-11-28 12:38:32,059 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 150 states. [2018-11-28 12:38:32,067 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 150 to 142. [2018-11-28 12:38:32,067 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 142 states. [2018-11-28 12:38:32,068 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 142 states to 142 states and 176 transitions. [2018-11-28 12:38:32,068 INFO L78 Accepts]: Start accepts. Automaton has 142 states and 176 transitions. Word has length 25 [2018-11-28 12:38:32,068 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-28 12:38:32,068 INFO L480 AbstractCegarLoop]: Abstraction has 142 states and 176 transitions. [2018-11-28 12:38:32,069 INFO L481 AbstractCegarLoop]: Interpolant automaton has 4 states. [2018-11-28 12:38:32,069 INFO L276 IsEmpty]: Start isEmpty. Operand 142 states and 176 transitions. [2018-11-28 12:38:32,069 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 26 [2018-11-28 12:38:32,069 INFO L394 BasicCegarLoop]: Found error trace [2018-11-28 12:38:32,069 INFO L402 BasicCegarLoop]: trace histogram [2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-28 12:38:32,070 INFO L423 AbstractCegarLoop]: === Iteration 9 === [__mainErr0ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr7ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr6ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr4ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr2ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr5ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr8ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr1ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr3ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr9ASSERT_VIOLATIONINTEGER_OVERFLOW, full_writeErr0ASSERT_VIOLATIONINTEGER_OVERFLOW, full_writeErr1ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr9ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr10ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr14ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr7ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr6ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr15ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr0ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr3ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr8ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr12ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr13ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr1ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr4ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr5ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr2ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr11ASSERT_VIOLATIONINTEGER_OVERFLOW]=== [2018-11-28 12:38:32,070 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-28 12:38:32,070 INFO L82 PathProgramCache]: Analyzing trace with hash 1182405980, now seen corresponding path program 1 times [2018-11-28 12:38:32,070 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-28 12:38:32,070 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-28 12:38:32,078 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 12:38:32,078 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-28 12:38:32,078 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 12:38:32,099 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-28 12:38:32,152 INFO L134 CoverageAnalysis]: Checked inductivity of 3 backedges. 1 proven. 0 refuted. 0 times theorem prover too weak. 2 trivial. 0 not checked. [2018-11-28 12:38:32,152 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-28 12:38:32,153 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2018-11-28 12:38:32,153 INFO L459 AbstractCegarLoop]: Interpolant automaton has 3 states [2018-11-28 12:38:32,153 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-28 12:38:32,153 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-28 12:38:32,153 INFO L87 Difference]: Start difference. First operand 142 states and 176 transitions. Second operand 3 states. [2018-11-28 12:38:32,175 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-28 12:38:32,175 INFO L93 Difference]: Finished difference Result 142 states and 176 transitions. [2018-11-28 12:38:32,176 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-28 12:38:32,176 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 25 [2018-11-28 12:38:32,177 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-28 12:38:32,177 INFO L225 Difference]: With dead ends: 142 [2018-11-28 12:38:32,177 INFO L226 Difference]: Without dead ends: 141 [2018-11-28 12:38:32,177 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 2 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-28 12:38:32,178 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 141 states. [2018-11-28 12:38:32,183 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 141 to 141. [2018-11-28 12:38:32,183 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 141 states. [2018-11-28 12:38:32,183 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 141 states to 141 states and 175 transitions. [2018-11-28 12:38:32,184 INFO L78 Accepts]: Start accepts. Automaton has 141 states and 175 transitions. Word has length 25 [2018-11-28 12:38:32,184 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-28 12:38:32,184 INFO L480 AbstractCegarLoop]: Abstraction has 141 states and 175 transitions. [2018-11-28 12:38:32,184 INFO L481 AbstractCegarLoop]: Interpolant automaton has 3 states. [2018-11-28 12:38:32,184 INFO L276 IsEmpty]: Start isEmpty. Operand 141 states and 175 transitions. [2018-11-28 12:38:32,185 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 28 [2018-11-28 12:38:32,185 INFO L394 BasicCegarLoop]: Found error trace [2018-11-28 12:38:32,185 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-28 12:38:32,185 INFO L423 AbstractCegarLoop]: === Iteration 10 === [__mainErr0ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr7ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr6ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr4ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr2ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr5ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr8ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr1ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr3ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr9ASSERT_VIOLATIONINTEGER_OVERFLOW, full_writeErr0ASSERT_VIOLATIONINTEGER_OVERFLOW, full_writeErr1ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr9ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr10ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr14ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr7ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr6ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr15ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr0ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr3ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr8ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr12ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr13ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr1ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr4ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr5ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr2ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr11ASSERT_VIOLATIONINTEGER_OVERFLOW]=== [2018-11-28 12:38:32,186 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-28 12:38:32,186 INFO L82 PathProgramCache]: Analyzing trace with hash -1458323352, now seen corresponding path program 1 times [2018-11-28 12:38:32,186 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-28 12:38:32,186 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-28 12:38:32,193 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 12:38:32,193 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-28 12:38:32,193 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 12:38:32,217 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-28 12:38:32,288 INFO L134 CoverageAnalysis]: Checked inductivity of 1 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-28 12:38:32,289 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-28 12:38:32,289 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_a2c4633f-02cb-4486-be39-ce67b7f0e7a6/bin-2019/uautomizer/z3 Starting monitored process 2 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 2 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-28 12:38:32,318 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-28 12:38:32,439 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-28 12:38:32,449 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-28 12:38:32,485 INFO L134 CoverageAnalysis]: Checked inductivity of 1 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-28 12:38:32,512 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-11-28 12:38:32,512 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [4, 4] total 5 [2018-11-28 12:38:32,512 INFO L459 AbstractCegarLoop]: Interpolant automaton has 5 states [2018-11-28 12:38:32,512 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-11-28 12:38:32,512 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=10, Invalid=10, Unknown=0, NotChecked=0, Total=20 [2018-11-28 12:38:32,513 INFO L87 Difference]: Start difference. First operand 141 states and 175 transitions. Second operand 5 states. [2018-11-28 12:38:32,554 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-28 12:38:32,554 INFO L93 Difference]: Finished difference Result 277 states and 345 transitions. [2018-11-28 12:38:32,554 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2018-11-28 12:38:32,555 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 27 [2018-11-28 12:38:32,555 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-28 12:38:32,555 INFO L225 Difference]: With dead ends: 277 [2018-11-28 12:38:32,556 INFO L226 Difference]: Without dead ends: 146 [2018-11-28 12:38:32,556 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 30 GetRequests, 27 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=10, Invalid=10, Unknown=0, NotChecked=0, Total=20 [2018-11-28 12:38:32,557 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 146 states. [2018-11-28 12:38:32,560 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 146 to 144. [2018-11-28 12:38:32,560 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 144 states. [2018-11-28 12:38:32,561 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 144 states to 144 states and 178 transitions. [2018-11-28 12:38:32,561 INFO L78 Accepts]: Start accepts. Automaton has 144 states and 178 transitions. Word has length 27 [2018-11-28 12:38:32,561 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-28 12:38:32,561 INFO L480 AbstractCegarLoop]: Abstraction has 144 states and 178 transitions. [2018-11-28 12:38:32,561 INFO L481 AbstractCegarLoop]: Interpolant automaton has 5 states. [2018-11-28 12:38:32,562 INFO L276 IsEmpty]: Start isEmpty. Operand 144 states and 178 transitions. [2018-11-28 12:38:32,562 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 31 [2018-11-28 12:38:32,562 INFO L394 BasicCegarLoop]: Found error trace [2018-11-28 12:38:32,562 INFO L402 BasicCegarLoop]: trace histogram [2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-28 12:38:32,563 INFO L423 AbstractCegarLoop]: === Iteration 11 === [__mainErr0ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr7ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr6ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr4ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr2ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr5ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr8ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr1ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr3ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr9ASSERT_VIOLATIONINTEGER_OVERFLOW, full_writeErr0ASSERT_VIOLATIONINTEGER_OVERFLOW, full_writeErr1ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr9ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr10ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr14ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr7ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr6ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr15ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr0ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr3ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr8ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr12ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr13ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr1ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr4ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr5ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr2ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr11ASSERT_VIOLATIONINTEGER_OVERFLOW]=== [2018-11-28 12:38:32,563 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-28 12:38:32,563 INFO L82 PathProgramCache]: Analyzing trace with hash -672341546, now seen corresponding path program 2 times [2018-11-28 12:38:32,563 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-28 12:38:32,563 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-28 12:38:32,571 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 12:38:32,571 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-28 12:38:32,571 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 12:38:32,594 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-28 12:38:32,650 INFO L134 CoverageAnalysis]: Checked inductivity of 5 backedges. 0 proven. 5 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-28 12:38:32,650 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-28 12:38:32,651 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_a2c4633f-02cb-4486-be39-ce67b7f0e7a6/bin-2019/uautomizer/z3 Starting monitored process 3 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 3 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-28 12:38:32,680 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-11-28 12:38:32,796 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) [2018-11-28 12:38:32,796 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-11-28 12:38:32,801 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-28 12:38:32,848 INFO L134 CoverageAnalysis]: Checked inductivity of 5 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2018-11-28 12:38:32,866 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 1 imperfect interpolant sequences. [2018-11-28 12:38:32,866 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [4] imperfect sequences [5] total 7 [2018-11-28 12:38:32,866 INFO L459 AbstractCegarLoop]: Interpolant automaton has 7 states [2018-11-28 12:38:32,866 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2018-11-28 12:38:32,866 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=15, Invalid=27, Unknown=0, NotChecked=0, Total=42 [2018-11-28 12:38:32,866 INFO L87 Difference]: Start difference. First operand 144 states and 178 transitions. Second operand 7 states. [2018-11-28 12:38:32,988 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-28 12:38:32,989 INFO L93 Difference]: Finished difference Result 290 states and 361 transitions. [2018-11-28 12:38:32,989 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2018-11-28 12:38:32,989 INFO L78 Accepts]: Start accepts. Automaton has 7 states. Word has length 30 [2018-11-28 12:38:32,990 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-28 12:38:32,990 INFO L225 Difference]: With dead ends: 290 [2018-11-28 12:38:32,990 INFO L226 Difference]: Without dead ends: 159 [2018-11-28 12:38:32,991 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 34 GetRequests, 29 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 4 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=15, Invalid=27, Unknown=0, NotChecked=0, Total=42 [2018-11-28 12:38:32,991 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 159 states. [2018-11-28 12:38:32,995 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 159 to 148. [2018-11-28 12:38:32,995 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 148 states. [2018-11-28 12:38:32,996 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 148 states to 148 states and 182 transitions. [2018-11-28 12:38:32,996 INFO L78 Accepts]: Start accepts. Automaton has 148 states and 182 transitions. Word has length 30 [2018-11-28 12:38:32,996 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-28 12:38:32,996 INFO L480 AbstractCegarLoop]: Abstraction has 148 states and 182 transitions. [2018-11-28 12:38:32,996 INFO L481 AbstractCegarLoop]: Interpolant automaton has 7 states. [2018-11-28 12:38:32,996 INFO L276 IsEmpty]: Start isEmpty. Operand 148 states and 182 transitions. [2018-11-28 12:38:32,996 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 33 [2018-11-28 12:38:32,997 INFO L394 BasicCegarLoop]: Found error trace [2018-11-28 12:38:32,997 INFO L402 BasicCegarLoop]: trace histogram [3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-28 12:38:32,997 INFO L423 AbstractCegarLoop]: === Iteration 12 === [__mainErr0ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr7ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr6ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr4ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr2ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr5ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr8ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr1ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr3ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr9ASSERT_VIOLATIONINTEGER_OVERFLOW, full_writeErr0ASSERT_VIOLATIONINTEGER_OVERFLOW, full_writeErr1ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr9ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr10ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr14ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr7ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr6ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr15ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr0ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr3ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr8ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr12ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr13ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr1ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr4ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr5ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr2ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr11ASSERT_VIOLATIONINTEGER_OVERFLOW]=== [2018-11-28 12:38:32,997 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-28 12:38:32,997 INFO L82 PathProgramCache]: Analyzing trace with hash -205191436, now seen corresponding path program 1 times [2018-11-28 12:38:32,998 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-28 12:38:32,998 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-28 12:38:33,003 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 12:38:33,004 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-28 12:38:33,004 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 12:38:33,020 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-28 12:38:33,064 INFO L134 CoverageAnalysis]: Checked inductivity of 13 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 13 trivial. 0 not checked. [2018-11-28 12:38:33,064 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-28 12:38:33,065 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2018-11-28 12:38:33,065 INFO L459 AbstractCegarLoop]: Interpolant automaton has 3 states [2018-11-28 12:38:33,065 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-28 12:38:33,065 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-28 12:38:33,065 INFO L87 Difference]: Start difference. First operand 148 states and 182 transitions. Second operand 3 states. [2018-11-28 12:38:33,101 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-28 12:38:33,101 INFO L93 Difference]: Finished difference Result 158 states and 193 transitions. [2018-11-28 12:38:33,102 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-28 12:38:33,102 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 32 [2018-11-28 12:38:33,102 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-28 12:38:33,103 INFO L225 Difference]: With dead ends: 158 [2018-11-28 12:38:33,103 INFO L226 Difference]: Without dead ends: 157 [2018-11-28 12:38:33,103 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 2 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-28 12:38:33,104 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 157 states. [2018-11-28 12:38:33,107 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 157 to 156. [2018-11-28 12:38:33,107 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 156 states. [2018-11-28 12:38:33,108 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 156 states to 156 states and 192 transitions. [2018-11-28 12:38:33,108 INFO L78 Accepts]: Start accepts. Automaton has 156 states and 192 transitions. Word has length 32 [2018-11-28 12:38:33,108 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-28 12:38:33,108 INFO L480 AbstractCegarLoop]: Abstraction has 156 states and 192 transitions. [2018-11-28 12:38:33,108 INFO L481 AbstractCegarLoop]: Interpolant automaton has 3 states. [2018-11-28 12:38:33,109 INFO L276 IsEmpty]: Start isEmpty. Operand 156 states and 192 transitions. [2018-11-28 12:38:33,109 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 33 [2018-11-28 12:38:33,109 INFO L394 BasicCegarLoop]: Found error trace [2018-11-28 12:38:33,109 INFO L402 BasicCegarLoop]: trace histogram [3, 3, 3, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-28 12:38:33,110 INFO L423 AbstractCegarLoop]: === Iteration 13 === [__mainErr0ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr7ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr6ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr4ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr2ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr5ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr8ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr1ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr3ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr9ASSERT_VIOLATIONINTEGER_OVERFLOW, full_writeErr0ASSERT_VIOLATIONINTEGER_OVERFLOW, full_writeErr1ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr9ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr10ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr14ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr7ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr6ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr15ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr0ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr3ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr8ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr12ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr13ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr1ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr4ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr5ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr2ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr11ASSERT_VIOLATIONINTEGER_OVERFLOW]=== [2018-11-28 12:38:33,110 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-28 12:38:33,110 INFO L82 PathProgramCache]: Analyzing trace with hash -205189738, now seen corresponding path program 1 times [2018-11-28 12:38:33,110 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-28 12:38:33,110 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-28 12:38:33,116 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 12:38:33,116 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-28 12:38:33,117 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 12:38:33,134 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-28 12:38:33,180 INFO L134 CoverageAnalysis]: Checked inductivity of 15 backedges. 3 proven. 0 refuted. 0 times theorem prover too weak. 12 trivial. 0 not checked. [2018-11-28 12:38:33,181 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-28 12:38:33,181 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2018-11-28 12:38:33,181 INFO L459 AbstractCegarLoop]: Interpolant automaton has 3 states [2018-11-28 12:38:33,181 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-28 12:38:33,181 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-28 12:38:33,182 INFO L87 Difference]: Start difference. First operand 156 states and 192 transitions. Second operand 3 states. [2018-11-28 12:38:33,196 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-28 12:38:33,196 INFO L93 Difference]: Finished difference Result 156 states and 192 transitions. [2018-11-28 12:38:33,197 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-28 12:38:33,197 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 32 [2018-11-28 12:38:33,197 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-28 12:38:33,198 INFO L225 Difference]: With dead ends: 156 [2018-11-28 12:38:33,198 INFO L226 Difference]: Without dead ends: 155 [2018-11-28 12:38:33,198 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 2 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-28 12:38:33,198 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 155 states. [2018-11-28 12:38:33,202 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 155 to 151. [2018-11-28 12:38:33,202 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 151 states. [2018-11-28 12:38:33,203 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 151 states to 151 states and 186 transitions. [2018-11-28 12:38:33,203 INFO L78 Accepts]: Start accepts. Automaton has 151 states and 186 transitions. Word has length 32 [2018-11-28 12:38:33,203 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-28 12:38:33,204 INFO L480 AbstractCegarLoop]: Abstraction has 151 states and 186 transitions. [2018-11-28 12:38:33,204 INFO L481 AbstractCegarLoop]: Interpolant automaton has 3 states. [2018-11-28 12:38:33,204 INFO L276 IsEmpty]: Start isEmpty. Operand 151 states and 186 transitions. [2018-11-28 12:38:33,204 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 41 [2018-11-28 12:38:33,204 INFO L394 BasicCegarLoop]: Found error trace [2018-11-28 12:38:33,205 INFO L402 BasicCegarLoop]: trace histogram [3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-28 12:38:33,205 INFO L423 AbstractCegarLoop]: === Iteration 14 === [__mainErr0ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr7ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr6ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr4ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr2ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr5ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr8ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr1ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr3ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr9ASSERT_VIOLATIONINTEGER_OVERFLOW, full_writeErr0ASSERT_VIOLATIONINTEGER_OVERFLOW, full_writeErr1ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr9ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr10ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr14ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr7ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr6ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr15ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr0ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr3ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr8ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr12ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr13ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr1ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr4ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr5ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr2ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr11ASSERT_VIOLATIONINTEGER_OVERFLOW]=== [2018-11-28 12:38:33,205 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-28 12:38:33,205 INFO L82 PathProgramCache]: Analyzing trace with hash 1301076365, now seen corresponding path program 1 times [2018-11-28 12:38:33,206 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-28 12:38:33,206 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-28 12:38:33,212 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 12:38:33,212 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-28 12:38:33,212 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 12:38:33,230 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-28 12:38:33,273 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 1 proven. 1 refuted. 0 times theorem prover too weak. 12 trivial. 0 not checked. [2018-11-28 12:38:33,274 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-28 12:38:33,274 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_a2c4633f-02cb-4486-be39-ce67b7f0e7a6/bin-2019/uautomizer/z3 Starting monitored process 4 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 4 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-28 12:38:33,304 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-28 12:38:33,424 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-28 12:38:33,428 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-28 12:38:33,500 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 0 proven. 12 refuted. 0 times theorem prover too weak. 2 trivial. 0 not checked. [2018-11-28 12:38:33,521 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-11-28 12:38:33,521 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [4, 6] total 8 [2018-11-28 12:38:33,521 INFO L459 AbstractCegarLoop]: Interpolant automaton has 8 states [2018-11-28 12:38:33,521 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 8 interpolants. [2018-11-28 12:38:33,522 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=20, Invalid=36, Unknown=0, NotChecked=0, Total=56 [2018-11-28 12:38:33,522 INFO L87 Difference]: Start difference. First operand 151 states and 186 transitions. Second operand 8 states. [2018-11-28 12:38:33,603 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-28 12:38:33,604 INFO L93 Difference]: Finished difference Result 301 states and 373 transitions. [2018-11-28 12:38:33,604 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 8 states. [2018-11-28 12:38:33,604 INFO L78 Accepts]: Start accepts. Automaton has 8 states. Word has length 40 [2018-11-28 12:38:33,604 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-28 12:38:33,605 INFO L225 Difference]: With dead ends: 301 [2018-11-28 12:38:33,605 INFO L226 Difference]: Without dead ends: 166 [2018-11-28 12:38:33,605 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 43 GetRequests, 37 SyntacticMatches, 0 SemanticMatches, 6 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 4 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=20, Invalid=36, Unknown=0, NotChecked=0, Total=56 [2018-11-28 12:38:33,606 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 166 states. [2018-11-28 12:38:33,610 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 166 to 160. [2018-11-28 12:38:33,610 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 160 states. [2018-11-28 12:38:33,611 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 160 states to 160 states and 195 transitions. [2018-11-28 12:38:33,611 INFO L78 Accepts]: Start accepts. Automaton has 160 states and 195 transitions. Word has length 40 [2018-11-28 12:38:33,611 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-28 12:38:33,611 INFO L480 AbstractCegarLoop]: Abstraction has 160 states and 195 transitions. [2018-11-28 12:38:33,611 INFO L481 AbstractCegarLoop]: Interpolant automaton has 8 states. [2018-11-28 12:38:33,612 INFO L276 IsEmpty]: Start isEmpty. Operand 160 states and 195 transitions. [2018-11-28 12:38:33,612 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 47 [2018-11-28 12:38:33,612 INFO L394 BasicCegarLoop]: Found error trace [2018-11-28 12:38:33,612 INFO L402 BasicCegarLoop]: trace histogram [4, 4, 4, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-28 12:38:33,613 INFO L423 AbstractCegarLoop]: === Iteration 15 === [__mainErr0ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr7ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr6ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr4ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr2ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr5ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr8ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr1ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr3ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr9ASSERT_VIOLATIONINTEGER_OVERFLOW, full_writeErr0ASSERT_VIOLATIONINTEGER_OVERFLOW, full_writeErr1ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr9ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr10ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr14ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr7ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr6ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr15ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr0ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr3ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr8ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr12ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr13ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr1ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr4ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr5ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr2ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr11ASSERT_VIOLATIONINTEGER_OVERFLOW]=== [2018-11-28 12:38:33,613 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-28 12:38:33,613 INFO L82 PathProgramCache]: Analyzing trace with hash 532136062, now seen corresponding path program 2 times [2018-11-28 12:38:33,613 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-28 12:38:33,613 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-28 12:38:33,620 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 12:38:33,620 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-28 12:38:33,620 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 12:38:33,639 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-28 12:38:33,702 INFO L134 CoverageAnalysis]: Checked inductivity of 28 backedges. 1 proven. 5 refuted. 0 times theorem prover too weak. 22 trivial. 0 not checked. [2018-11-28 12:38:33,702 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-28 12:38:33,703 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_a2c4633f-02cb-4486-be39-ce67b7f0e7a6/bin-2019/uautomizer/z3 Starting monitored process 5 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 5 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-28 12:38:33,734 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-11-28 12:38:33,819 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) [2018-11-28 12:38:33,819 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-11-28 12:38:33,823 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-28 12:38:33,875 INFO L134 CoverageAnalysis]: Checked inductivity of 28 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 28 trivial. 0 not checked. [2018-11-28 12:38:33,901 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 1 imperfect interpolant sequences. [2018-11-28 12:38:33,901 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [5] total 6 [2018-11-28 12:38:33,901 INFO L459 AbstractCegarLoop]: Interpolant automaton has 6 states [2018-11-28 12:38:33,902 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2018-11-28 12:38:33,902 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=12, Invalid=18, Unknown=0, NotChecked=0, Total=30 [2018-11-28 12:38:33,902 INFO L87 Difference]: Start difference. First operand 160 states and 195 transitions. Second operand 6 states. [2018-11-28 12:38:33,964 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-28 12:38:33,965 INFO L93 Difference]: Finished difference Result 312 states and 391 transitions. [2018-11-28 12:38:33,967 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2018-11-28 12:38:33,968 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 46 [2018-11-28 12:38:33,968 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-28 12:38:33,970 INFO L225 Difference]: With dead ends: 312 [2018-11-28 12:38:33,970 INFO L226 Difference]: Without dead ends: 188 [2018-11-28 12:38:33,971 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 50 GetRequests, 46 SyntacticMatches, 0 SemanticMatches, 4 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=12, Invalid=18, Unknown=0, NotChecked=0, Total=30 [2018-11-28 12:38:33,971 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 188 states. [2018-11-28 12:38:33,978 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 188 to 167. [2018-11-28 12:38:33,978 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 167 states. [2018-11-28 12:38:33,979 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 167 states to 167 states and 202 transitions. [2018-11-28 12:38:33,979 INFO L78 Accepts]: Start accepts. Automaton has 167 states and 202 transitions. Word has length 46 [2018-11-28 12:38:33,979 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-28 12:38:33,979 INFO L480 AbstractCegarLoop]: Abstraction has 167 states and 202 transitions. [2018-11-28 12:38:33,979 INFO L481 AbstractCegarLoop]: Interpolant automaton has 6 states. [2018-11-28 12:38:33,979 INFO L276 IsEmpty]: Start isEmpty. Operand 167 states and 202 transitions. [2018-11-28 12:38:33,980 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 51 [2018-11-28 12:38:33,980 INFO L394 BasicCegarLoop]: Found error trace [2018-11-28 12:38:33,980 INFO L402 BasicCegarLoop]: trace histogram [4, 4, 4, 3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-28 12:38:33,980 INFO L423 AbstractCegarLoop]: === Iteration 16 === [__mainErr0ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr7ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr6ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr4ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr2ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr5ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr8ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr1ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr3ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr9ASSERT_VIOLATIONINTEGER_OVERFLOW, full_writeErr0ASSERT_VIOLATIONINTEGER_OVERFLOW, full_writeErr1ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr9ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr10ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr14ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr7ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr6ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr15ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr0ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr3ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr8ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr12ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr13ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr1ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr4ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr5ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr2ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr11ASSERT_VIOLATIONINTEGER_OVERFLOW]=== [2018-11-28 12:38:33,980 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-28 12:38:33,981 INFO L82 PathProgramCache]: Analyzing trace with hash -1211589613, now seen corresponding path program 1 times [2018-11-28 12:38:33,981 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-28 12:38:33,981 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-28 12:38:33,987 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 12:38:33,987 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-28 12:38:33,987 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 12:38:34,014 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-28 12:38:34,090 INFO L134 CoverageAnalysis]: Checked inductivity of 35 backedges. 1 proven. 12 refuted. 0 times theorem prover too weak. 22 trivial. 0 not checked. [2018-11-28 12:38:34,090 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-28 12:38:34,090 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_a2c4633f-02cb-4486-be39-ce67b7f0e7a6/bin-2019/uautomizer/z3 Starting monitored process 6 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 6 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-28 12:38:34,120 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-28 12:38:34,234 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-28 12:38:34,238 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-28 12:38:34,326 INFO L134 CoverageAnalysis]: Checked inductivity of 35 backedges. 0 proven. 22 refuted. 0 times theorem prover too weak. 13 trivial. 0 not checked. [2018-11-28 12:38:34,354 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-11-28 12:38:34,354 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [6, 7] total 11 [2018-11-28 12:38:34,354 INFO L459 AbstractCegarLoop]: Interpolant automaton has 11 states [2018-11-28 12:38:34,354 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 11 interpolants. [2018-11-28 12:38:34,354 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=35, Invalid=75, Unknown=0, NotChecked=0, Total=110 [2018-11-28 12:38:34,355 INFO L87 Difference]: Start difference. First operand 167 states and 202 transitions. Second operand 11 states. [2018-11-28 12:38:34,474 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-28 12:38:34,474 INFO L93 Difference]: Finished difference Result 330 states and 402 transitions. [2018-11-28 12:38:34,475 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 11 states. [2018-11-28 12:38:34,475 INFO L78 Accepts]: Start accepts. Automaton has 11 states. Word has length 50 [2018-11-28 12:38:34,475 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-28 12:38:34,476 INFO L225 Difference]: With dead ends: 330 [2018-11-28 12:38:34,476 INFO L226 Difference]: Without dead ends: 182 [2018-11-28 12:38:34,477 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 55 GetRequests, 46 SyntacticMatches, 0 SemanticMatches, 9 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 15 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=35, Invalid=75, Unknown=0, NotChecked=0, Total=110 [2018-11-28 12:38:34,477 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 182 states. [2018-11-28 12:38:34,483 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 182 to 176. [2018-11-28 12:38:34,483 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 176 states. [2018-11-28 12:38:34,484 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 176 states to 176 states and 211 transitions. [2018-11-28 12:38:34,485 INFO L78 Accepts]: Start accepts. Automaton has 176 states and 211 transitions. Word has length 50 [2018-11-28 12:38:34,485 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-28 12:38:34,485 INFO L480 AbstractCegarLoop]: Abstraction has 176 states and 211 transitions. [2018-11-28 12:38:34,485 INFO L481 AbstractCegarLoop]: Interpolant automaton has 11 states. [2018-11-28 12:38:34,485 INFO L276 IsEmpty]: Start isEmpty. Operand 176 states and 211 transitions. [2018-11-28 12:38:34,485 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 57 [2018-11-28 12:38:34,485 INFO L394 BasicCegarLoop]: Found error trace [2018-11-28 12:38:34,485 INFO L402 BasicCegarLoop]: trace histogram [5, 5, 5, 4, 4, 4, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-28 12:38:34,486 INFO L423 AbstractCegarLoop]: === Iteration 17 === [__mainErr0ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr7ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr6ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr4ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr2ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr5ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr8ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr1ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr3ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr9ASSERT_VIOLATIONINTEGER_OVERFLOW, full_writeErr0ASSERT_VIOLATIONINTEGER_OVERFLOW, full_writeErr1ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr9ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr10ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr14ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr7ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr6ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr15ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr0ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr3ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr8ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr12ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr13ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr1ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr4ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr5ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr2ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr11ASSERT_VIOLATIONINTEGER_OVERFLOW]=== [2018-11-28 12:38:34,486 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-28 12:38:34,486 INFO L82 PathProgramCache]: Analyzing trace with hash -1484183166, now seen corresponding path program 2 times [2018-11-28 12:38:34,486 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-28 12:38:34,486 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-28 12:38:34,493 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 12:38:34,493 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-28 12:38:34,493 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 12:38:34,517 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-28 12:38:34,597 INFO L134 CoverageAnalysis]: Checked inductivity of 58 backedges. 1 proven. 22 refuted. 0 times theorem prover too weak. 35 trivial. 0 not checked. [2018-11-28 12:38:34,597 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-28 12:38:34,597 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_a2c4633f-02cb-4486-be39-ce67b7f0e7a6/bin-2019/uautomizer/z3 Starting monitored process 7 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 7 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-28 12:38:34,628 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-11-28 12:38:34,780 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2018-11-28 12:38:34,780 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-11-28 12:38:34,784 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-28 12:38:34,863 INFO L134 CoverageAnalysis]: Checked inductivity of 58 backedges. 0 proven. 35 refuted. 0 times theorem prover too weak. 23 trivial. 0 not checked. [2018-11-28 12:38:34,879 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-11-28 12:38:34,880 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [7, 8] total 13 [2018-11-28 12:38:34,880 INFO L459 AbstractCegarLoop]: Interpolant automaton has 13 states [2018-11-28 12:38:34,880 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 13 interpolants. [2018-11-28 12:38:34,880 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=48, Invalid=108, Unknown=0, NotChecked=0, Total=156 [2018-11-28 12:38:34,880 INFO L87 Difference]: Start difference. First operand 176 states and 211 transitions. Second operand 13 states. [2018-11-28 12:38:34,971 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-28 12:38:34,971 INFO L93 Difference]: Finished difference Result 345 states and 417 transitions. [2018-11-28 12:38:34,972 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 13 states. [2018-11-28 12:38:34,972 INFO L78 Accepts]: Start accepts. Automaton has 13 states. Word has length 56 [2018-11-28 12:38:34,972 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-28 12:38:34,973 INFO L225 Difference]: With dead ends: 345 [2018-11-28 12:38:34,973 INFO L226 Difference]: Without dead ends: 191 [2018-11-28 12:38:34,974 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 62 GetRequests, 51 SyntacticMatches, 0 SemanticMatches, 11 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 24 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=48, Invalid=108, Unknown=0, NotChecked=0, Total=156 [2018-11-28 12:38:34,974 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 191 states. [2018-11-28 12:38:34,981 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 191 to 185. [2018-11-28 12:38:34,981 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 185 states. [2018-11-28 12:38:34,982 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 185 states to 185 states and 220 transitions. [2018-11-28 12:38:34,982 INFO L78 Accepts]: Start accepts. Automaton has 185 states and 220 transitions. Word has length 56 [2018-11-28 12:38:34,982 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-28 12:38:34,982 INFO L480 AbstractCegarLoop]: Abstraction has 185 states and 220 transitions. [2018-11-28 12:38:34,982 INFO L481 AbstractCegarLoop]: Interpolant automaton has 13 states. [2018-11-28 12:38:34,982 INFO L276 IsEmpty]: Start isEmpty. Operand 185 states and 220 transitions. [2018-11-28 12:38:34,983 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 63 [2018-11-28 12:38:34,983 INFO L394 BasicCegarLoop]: Found error trace [2018-11-28 12:38:34,983 INFO L402 BasicCegarLoop]: trace histogram [6, 6, 6, 5, 5, 5, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-28 12:38:34,983 INFO L423 AbstractCegarLoop]: === Iteration 18 === [__mainErr0ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr7ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr6ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr4ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr2ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr5ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr8ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr1ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr3ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr9ASSERT_VIOLATIONINTEGER_OVERFLOW, full_writeErr0ASSERT_VIOLATIONINTEGER_OVERFLOW, full_writeErr1ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr9ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr10ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr14ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr7ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr6ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr15ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr0ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr3ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr8ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr12ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr13ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr1ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr4ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr5ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr2ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr11ASSERT_VIOLATIONINTEGER_OVERFLOW]=== [2018-11-28 12:38:34,983 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-28 12:38:34,984 INFO L82 PathProgramCache]: Analyzing trace with hash 1464125235, now seen corresponding path program 3 times [2018-11-28 12:38:34,984 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-28 12:38:34,984 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-28 12:38:34,989 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 12:38:34,989 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-28 12:38:34,989 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 12:38:35,012 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-28 12:38:35,122 INFO L134 CoverageAnalysis]: Checked inductivity of 87 backedges. 1 proven. 35 refuted. 0 times theorem prover too weak. 51 trivial. 0 not checked. [2018-11-28 12:38:35,123 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-28 12:38:35,123 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_a2c4633f-02cb-4486-be39-ce67b7f0e7a6/bin-2019/uautomizer/z3 Starting monitored process 8 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 8 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-28 12:38:35,153 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-11-28 12:38:37,443 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 7 check-sat command(s) [2018-11-28 12:38:37,443 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-11-28 12:38:37,448 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-28 12:38:37,474 INFO L134 CoverageAnalysis]: Checked inductivity of 87 backedges. 1 proven. 35 refuted. 0 times theorem prover too weak. 51 trivial. 0 not checked. [2018-11-28 12:38:37,493 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-11-28 12:38:37,493 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [8, 8] total 9 [2018-11-28 12:38:37,493 INFO L459 AbstractCegarLoop]: Interpolant automaton has 9 states [2018-11-28 12:38:37,493 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 9 interpolants. [2018-11-28 12:38:37,494 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=36, Invalid=36, Unknown=0, NotChecked=0, Total=72 [2018-11-28 12:38:37,494 INFO L87 Difference]: Start difference. First operand 185 states and 220 transitions. Second operand 9 states. [2018-11-28 12:38:37,544 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-28 12:38:37,544 INFO L93 Difference]: Finished difference Result 329 states and 399 transitions. [2018-11-28 12:38:37,544 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 8 states. [2018-11-28 12:38:37,545 INFO L78 Accepts]: Start accepts. Automaton has 9 states. Word has length 62 [2018-11-28 12:38:37,545 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-28 12:38:37,546 INFO L225 Difference]: With dead ends: 329 [2018-11-28 12:38:37,546 INFO L226 Difference]: Without dead ends: 195 [2018-11-28 12:38:37,546 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 69 GetRequests, 62 SyntacticMatches, 0 SemanticMatches, 7 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 8 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=36, Invalid=36, Unknown=0, NotChecked=0, Total=72 [2018-11-28 12:38:37,547 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 195 states. [2018-11-28 12:38:37,554 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 195 to 191. [2018-11-28 12:38:37,554 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 191 states. [2018-11-28 12:38:37,555 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 191 states to 191 states and 226 transitions. [2018-11-28 12:38:37,555 INFO L78 Accepts]: Start accepts. Automaton has 191 states and 226 transitions. Word has length 62 [2018-11-28 12:38:37,556 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-28 12:38:37,556 INFO L480 AbstractCegarLoop]: Abstraction has 191 states and 226 transitions. [2018-11-28 12:38:37,556 INFO L481 AbstractCegarLoop]: Interpolant automaton has 9 states. [2018-11-28 12:38:37,556 INFO L276 IsEmpty]: Start isEmpty. Operand 191 states and 226 transitions. [2018-11-28 12:38:37,556 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 66 [2018-11-28 12:38:37,557 INFO L394 BasicCegarLoop]: Found error trace [2018-11-28 12:38:37,557 INFO L402 BasicCegarLoop]: trace histogram [6, 6, 6, 6, 6, 6, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-28 12:38:37,557 INFO L423 AbstractCegarLoop]: === Iteration 19 === [__mainErr0ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr7ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr6ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr4ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr2ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr5ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr8ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr1ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr3ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr9ASSERT_VIOLATIONINTEGER_OVERFLOW, full_writeErr0ASSERT_VIOLATIONINTEGER_OVERFLOW, full_writeErr1ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr9ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr10ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr14ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr7ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr6ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr15ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr0ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr3ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr8ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr12ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr13ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr1ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr4ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr5ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr2ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr11ASSERT_VIOLATIONINTEGER_OVERFLOW]=== [2018-11-28 12:38:37,558 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-28 12:38:37,558 INFO L82 PathProgramCache]: Analyzing trace with hash 613455476, now seen corresponding path program 4 times [2018-11-28 12:38:37,558 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-28 12:38:37,558 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-28 12:38:37,564 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 12:38:37,565 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-28 12:38:37,565 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 12:38:37,594 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-28 12:38:37,741 INFO L134 CoverageAnalysis]: Checked inductivity of 103 backedges. 0 proven. 51 refuted. 0 times theorem prover too weak. 52 trivial. 0 not checked. [2018-11-28 12:38:37,742 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-28 12:38:37,742 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_a2c4633f-02cb-4486-be39-ce67b7f0e7a6/bin-2019/uautomizer/z3 Starting monitored process 9 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 9 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-28 12:38:37,777 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-11-28 12:38:37,938 INFO L249 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-11-28 12:38:37,939 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-11-28 12:38:37,943 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-28 12:38:37,954 INFO L134 CoverageAnalysis]: Checked inductivity of 103 backedges. 0 proven. 51 refuted. 0 times theorem prover too weak. 52 trivial. 0 not checked. [2018-11-28 12:38:37,970 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-11-28 12:38:37,970 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [9, 9] total 10 [2018-11-28 12:38:37,971 INFO L459 AbstractCegarLoop]: Interpolant automaton has 10 states [2018-11-28 12:38:37,971 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 10 interpolants. [2018-11-28 12:38:37,971 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=45, Invalid=45, Unknown=0, NotChecked=0, Total=90 [2018-11-28 12:38:37,971 INFO L87 Difference]: Start difference. First operand 191 states and 226 transitions. Second operand 10 states. [2018-11-28 12:38:38,021 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-28 12:38:38,021 INFO L93 Difference]: Finished difference Result 362 states and 432 transitions. [2018-11-28 12:38:38,022 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2018-11-28 12:38:38,022 INFO L78 Accepts]: Start accepts. Automaton has 10 states. Word has length 65 [2018-11-28 12:38:38,022 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-28 12:38:38,023 INFO L225 Difference]: With dead ends: 362 [2018-11-28 12:38:38,023 INFO L226 Difference]: Without dead ends: 196 [2018-11-28 12:38:38,024 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 73 GetRequests, 65 SyntacticMatches, 0 SemanticMatches, 8 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 10 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=45, Invalid=45, Unknown=0, NotChecked=0, Total=90 [2018-11-28 12:38:38,024 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 196 states. [2018-11-28 12:38:38,030 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 196 to 194. [2018-11-28 12:38:38,030 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 194 states. [2018-11-28 12:38:38,031 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 194 states to 194 states and 229 transitions. [2018-11-28 12:38:38,031 INFO L78 Accepts]: Start accepts. Automaton has 194 states and 229 transitions. Word has length 65 [2018-11-28 12:38:38,032 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-28 12:38:38,032 INFO L480 AbstractCegarLoop]: Abstraction has 194 states and 229 transitions. [2018-11-28 12:38:38,032 INFO L481 AbstractCegarLoop]: Interpolant automaton has 10 states. [2018-11-28 12:38:38,032 INFO L276 IsEmpty]: Start isEmpty. Operand 194 states and 229 transitions. [2018-11-28 12:38:38,032 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 69 [2018-11-28 12:38:38,032 INFO L394 BasicCegarLoop]: Found error trace [2018-11-28 12:38:38,032 INFO L402 BasicCegarLoop]: trace histogram [7, 7, 7, 6, 6, 6, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-28 12:38:38,033 INFO L423 AbstractCegarLoop]: === Iteration 20 === [__mainErr0ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr7ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr6ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr4ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr2ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr5ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr8ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr1ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr3ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr9ASSERT_VIOLATIONINTEGER_OVERFLOW, full_writeErr0ASSERT_VIOLATIONINTEGER_OVERFLOW, full_writeErr1ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr9ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr10ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr14ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr7ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr6ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr15ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr0ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr3ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr8ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr12ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr13ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr1ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr4ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr5ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr2ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr11ASSERT_VIOLATIONINTEGER_OVERFLOW]=== [2018-11-28 12:38:38,033 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-28 12:38:38,033 INFO L82 PathProgramCache]: Analyzing trace with hash -420268702, now seen corresponding path program 5 times [2018-11-28 12:38:38,033 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-28 12:38:38,033 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-28 12:38:38,038 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 12:38:38,038 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-28 12:38:38,039 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 12:38:38,061 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-28 12:38:38,180 INFO L134 CoverageAnalysis]: Checked inductivity of 122 backedges. 0 proven. 70 refuted. 0 times theorem prover too weak. 52 trivial. 0 not checked. [2018-11-28 12:38:38,181 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-28 12:38:38,181 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_a2c4633f-02cb-4486-be39-ce67b7f0e7a6/bin-2019/uautomizer/z3 Starting monitored process 10 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 10 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-28 12:38:38,202 INFO L103 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-11-28 12:38:39,662 INFO L249 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 7 check-sat command(s) [2018-11-28 12:38:39,662 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-11-28 12:38:39,664 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-28 12:38:39,780 INFO L134 CoverageAnalysis]: Checked inductivity of 122 backedges. 1 proven. 51 refuted. 0 times theorem prover too weak. 70 trivial. 0 not checked. [2018-11-28 12:38:39,797 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-11-28 12:38:39,797 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [10, 9] total 17 [2018-11-28 12:38:39,798 INFO L459 AbstractCegarLoop]: Interpolant automaton has 17 states [2018-11-28 12:38:39,798 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 17 interpolants. [2018-11-28 12:38:39,798 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=80, Invalid=192, Unknown=0, NotChecked=0, Total=272 [2018-11-28 12:38:39,798 INFO L87 Difference]: Start difference. First operand 194 states and 229 transitions. Second operand 17 states. [2018-11-28 12:38:39,907 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-28 12:38:39,907 INFO L93 Difference]: Finished difference Result 375 states and 447 transitions. [2018-11-28 12:38:39,908 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 17 states. [2018-11-28 12:38:39,908 INFO L78 Accepts]: Start accepts. Automaton has 17 states. Word has length 68 [2018-11-28 12:38:39,908 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-28 12:38:39,909 INFO L225 Difference]: With dead ends: 375 [2018-11-28 12:38:39,909 INFO L226 Difference]: Without dead ends: 209 [2018-11-28 12:38:39,909 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 77 GetRequests, 62 SyntacticMatches, 0 SemanticMatches, 15 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 49 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=80, Invalid=192, Unknown=0, NotChecked=0, Total=272 [2018-11-28 12:38:39,910 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 209 states. [2018-11-28 12:38:39,916 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 209 to 203. [2018-11-28 12:38:39,916 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 203 states. [2018-11-28 12:38:39,917 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 203 states to 203 states and 238 transitions. [2018-11-28 12:38:39,917 INFO L78 Accepts]: Start accepts. Automaton has 203 states and 238 transitions. Word has length 68 [2018-11-28 12:38:39,917 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-28 12:38:39,917 INFO L480 AbstractCegarLoop]: Abstraction has 203 states and 238 transitions. [2018-11-28 12:38:39,917 INFO L481 AbstractCegarLoop]: Interpolant automaton has 17 states. [2018-11-28 12:38:39,918 INFO L276 IsEmpty]: Start isEmpty. Operand 203 states and 238 transitions. [2018-11-28 12:38:39,918 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 75 [2018-11-28 12:38:39,918 INFO L394 BasicCegarLoop]: Found error trace [2018-11-28 12:38:39,918 INFO L402 BasicCegarLoop]: trace histogram [8, 8, 8, 7, 7, 7, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-28 12:38:39,919 INFO L423 AbstractCegarLoop]: === Iteration 21 === [__mainErr0ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr7ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr6ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr4ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr2ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr5ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr8ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr1ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr3ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr9ASSERT_VIOLATIONINTEGER_OVERFLOW, full_writeErr0ASSERT_VIOLATIONINTEGER_OVERFLOW, full_writeErr1ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr9ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr10ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr14ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr7ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr6ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr15ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr0ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr3ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr8ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr12ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr13ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr1ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr4ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr5ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr2ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr11ASSERT_VIOLATIONINTEGER_OVERFLOW]=== [2018-11-28 12:38:39,919 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-28 12:38:39,919 INFO L82 PathProgramCache]: Analyzing trace with hash -1212679597, now seen corresponding path program 6 times [2018-11-28 12:38:39,919 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-28 12:38:39,919 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-28 12:38:39,924 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 12:38:39,924 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-28 12:38:39,924 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 12:38:39,948 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-28 12:38:40,088 INFO L134 CoverageAnalysis]: Checked inductivity of 163 backedges. 1 proven. 70 refuted. 0 times theorem prover too weak. 92 trivial. 0 not checked. [2018-11-28 12:38:40,088 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-28 12:38:40,089 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_a2c4633f-02cb-4486-be39-ce67b7f0e7a6/bin-2019/uautomizer/z3 Starting monitored process 11 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 11 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-28 12:38:40,115 INFO L103 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-11-28 12:38:59,563 INFO L249 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 9 check-sat command(s) [2018-11-28 12:38:59,563 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-11-28 12:38:59,570 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-28 12:38:59,696 INFO L134 CoverageAnalysis]: Checked inductivity of 163 backedges. 0 proven. 92 refuted. 0 times theorem prover too weak. 71 trivial. 0 not checked. [2018-11-28 12:38:59,715 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-11-28 12:38:59,715 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [10, 11] total 19 [2018-11-28 12:38:59,715 INFO L459 AbstractCegarLoop]: Interpolant automaton has 19 states [2018-11-28 12:38:59,716 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 19 interpolants. [2018-11-28 12:38:59,716 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=99, Invalid=243, Unknown=0, NotChecked=0, Total=342 [2018-11-28 12:38:59,716 INFO L87 Difference]: Start difference. First operand 203 states and 238 transitions. Second operand 19 states. [2018-11-28 12:38:59,822 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-28 12:38:59,822 INFO L93 Difference]: Finished difference Result 390 states and 462 transitions. [2018-11-28 12:38:59,823 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 19 states. [2018-11-28 12:38:59,823 INFO L78 Accepts]: Start accepts. Automaton has 19 states. Word has length 74 [2018-11-28 12:38:59,824 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-28 12:38:59,824 INFO L225 Difference]: With dead ends: 390 [2018-11-28 12:38:59,824 INFO L226 Difference]: Without dead ends: 218 [2018-11-28 12:38:59,825 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 83 GetRequests, 66 SyntacticMatches, 0 SemanticMatches, 17 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 63 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=99, Invalid=243, Unknown=0, NotChecked=0, Total=342 [2018-11-28 12:38:59,825 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 218 states. [2018-11-28 12:38:59,831 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 218 to 212. [2018-11-28 12:38:59,831 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 212 states. [2018-11-28 12:38:59,832 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 212 states to 212 states and 247 transitions. [2018-11-28 12:38:59,832 INFO L78 Accepts]: Start accepts. Automaton has 212 states and 247 transitions. Word has length 74 [2018-11-28 12:38:59,832 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-28 12:38:59,832 INFO L480 AbstractCegarLoop]: Abstraction has 212 states and 247 transitions. [2018-11-28 12:38:59,832 INFO L481 AbstractCegarLoop]: Interpolant automaton has 19 states. [2018-11-28 12:38:59,833 INFO L276 IsEmpty]: Start isEmpty. Operand 212 states and 247 transitions. [2018-11-28 12:38:59,833 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 81 [2018-11-28 12:38:59,833 INFO L394 BasicCegarLoop]: Found error trace [2018-11-28 12:38:59,833 INFO L402 BasicCegarLoop]: trace histogram [9, 9, 9, 8, 8, 8, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-28 12:38:59,834 INFO L423 AbstractCegarLoop]: === Iteration 22 === [__mainErr0ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr7ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr6ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr4ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr2ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr5ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr8ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr1ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr3ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr9ASSERT_VIOLATIONINTEGER_OVERFLOW, full_writeErr0ASSERT_VIOLATIONINTEGER_OVERFLOW, full_writeErr1ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr9ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr10ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr14ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr7ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr6ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr15ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr0ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr3ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr8ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr12ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr13ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr1ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr4ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr5ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr2ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr11ASSERT_VIOLATIONINTEGER_OVERFLOW]=== [2018-11-28 12:38:59,834 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-28 12:38:59,834 INFO L82 PathProgramCache]: Analyzing trace with hash -38749886, now seen corresponding path program 7 times [2018-11-28 12:38:59,834 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-28 12:38:59,834 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-28 12:38:59,839 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 12:38:59,839 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-28 12:38:59,839 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 12:38:59,861 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-28 12:39:00,002 INFO L134 CoverageAnalysis]: Checked inductivity of 210 backedges. 1 proven. 92 refuted. 0 times theorem prover too weak. 117 trivial. 0 not checked. [2018-11-28 12:39:00,002 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-28 12:39:00,002 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_a2c4633f-02cb-4486-be39-ce67b7f0e7a6/bin-2019/uautomizer/z3 Starting monitored process 12 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 12 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-28 12:39:00,029 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-28 12:39:00,142 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-28 12:39:00,146 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-28 12:39:00,300 INFO L134 CoverageAnalysis]: Checked inductivity of 210 backedges. 0 proven. 117 refuted. 0 times theorem prover too weak. 93 trivial. 0 not checked. [2018-11-28 12:39:00,315 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-11-28 12:39:00,315 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [11, 12] total 21 [2018-11-28 12:39:00,315 INFO L459 AbstractCegarLoop]: Interpolant automaton has 21 states [2018-11-28 12:39:00,316 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 21 interpolants. [2018-11-28 12:39:00,316 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=120, Invalid=300, Unknown=0, NotChecked=0, Total=420 [2018-11-28 12:39:00,316 INFO L87 Difference]: Start difference. First operand 212 states and 247 transitions. Second operand 21 states. [2018-11-28 12:39:00,437 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-28 12:39:00,437 INFO L93 Difference]: Finished difference Result 403 states and 475 transitions. [2018-11-28 12:39:00,438 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 21 states. [2018-11-28 12:39:00,438 INFO L78 Accepts]: Start accepts. Automaton has 21 states. Word has length 80 [2018-11-28 12:39:00,438 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-28 12:39:00,439 INFO L225 Difference]: With dead ends: 403 [2018-11-28 12:39:00,439 INFO L226 Difference]: Without dead ends: 225 [2018-11-28 12:39:00,439 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 90 GetRequests, 71 SyntacticMatches, 0 SemanticMatches, 19 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 80 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=120, Invalid=300, Unknown=0, NotChecked=0, Total=420 [2018-11-28 12:39:00,440 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 225 states. [2018-11-28 12:39:00,447 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 225 to 221. [2018-11-28 12:39:00,447 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 221 states. [2018-11-28 12:39:00,448 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 221 states to 221 states and 256 transitions. [2018-11-28 12:39:00,448 INFO L78 Accepts]: Start accepts. Automaton has 221 states and 256 transitions. Word has length 80 [2018-11-28 12:39:00,448 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-28 12:39:00,448 INFO L480 AbstractCegarLoop]: Abstraction has 221 states and 256 transitions. [2018-11-28 12:39:00,448 INFO L481 AbstractCegarLoop]: Interpolant automaton has 21 states. [2018-11-28 12:39:00,448 INFO L276 IsEmpty]: Start isEmpty. Operand 221 states and 256 transitions. [2018-11-28 12:39:00,449 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 87 [2018-11-28 12:39:00,449 INFO L394 BasicCegarLoop]: Found error trace [2018-11-28 12:39:00,449 INFO L402 BasicCegarLoop]: trace histogram [10, 10, 10, 9, 9, 9, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-28 12:39:00,449 INFO L423 AbstractCegarLoop]: === Iteration 23 === [__mainErr0ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr7ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr6ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr4ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr2ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr5ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr8ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr1ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr3ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr9ASSERT_VIOLATIONINTEGER_OVERFLOW, full_writeErr0ASSERT_VIOLATIONINTEGER_OVERFLOW, full_writeErr1ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr9ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr10ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr14ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr7ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr6ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr15ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr0ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr3ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr8ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr12ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr13ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr1ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr4ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr5ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr2ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr11ASSERT_VIOLATIONINTEGER_OVERFLOW]=== [2018-11-28 12:39:00,450 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-28 12:39:00,450 INFO L82 PathProgramCache]: Analyzing trace with hash -622054029, now seen corresponding path program 8 times [2018-11-28 12:39:00,450 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-28 12:39:00,450 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-28 12:39:00,454 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 12:39:00,454 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-28 12:39:00,454 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 12:39:00,477 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-28 12:39:00,636 INFO L134 CoverageAnalysis]: Checked inductivity of 263 backedges. 1 proven. 117 refuted. 0 times theorem prover too weak. 145 trivial. 0 not checked. [2018-11-28 12:39:00,636 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-28 12:39:00,636 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_a2c4633f-02cb-4486-be39-ce67b7f0e7a6/bin-2019/uautomizer/z3 Starting monitored process 13 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 13 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-28 12:39:00,656 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-11-28 12:39:00,759 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2018-11-28 12:39:00,759 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-11-28 12:39:00,763 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-28 12:39:00,782 INFO L134 CoverageAnalysis]: Checked inductivity of 263 backedges. 1 proven. 117 refuted. 0 times theorem prover too weak. 145 trivial. 0 not checked. [2018-11-28 12:39:00,797 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-11-28 12:39:00,797 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [12, 12] total 13 [2018-11-28 12:39:00,797 INFO L459 AbstractCegarLoop]: Interpolant automaton has 13 states [2018-11-28 12:39:00,798 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 13 interpolants. [2018-11-28 12:39:00,798 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=78, Invalid=78, Unknown=0, NotChecked=0, Total=156 [2018-11-28 12:39:00,798 INFO L87 Difference]: Start difference. First operand 221 states and 256 transitions. Second operand 13 states. [2018-11-28 12:39:00,853 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-28 12:39:00,853 INFO L93 Difference]: Finished difference Result 373 states and 443 transitions. [2018-11-28 12:39:00,853 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 12 states. [2018-11-28 12:39:00,853 INFO L78 Accepts]: Start accepts. Automaton has 13 states. Word has length 86 [2018-11-28 12:39:00,853 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-28 12:39:00,854 INFO L225 Difference]: With dead ends: 373 [2018-11-28 12:39:00,854 INFO L226 Difference]: Without dead ends: 227 [2018-11-28 12:39:00,855 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 97 GetRequests, 86 SyntacticMatches, 0 SemanticMatches, 11 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 16 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=78, Invalid=78, Unknown=0, NotChecked=0, Total=156 [2018-11-28 12:39:00,855 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 227 states. [2018-11-28 12:39:00,862 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 227 to 227. [2018-11-28 12:39:00,862 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 227 states. [2018-11-28 12:39:00,862 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 227 states to 227 states and 262 transitions. [2018-11-28 12:39:00,863 INFO L78 Accepts]: Start accepts. Automaton has 227 states and 262 transitions. Word has length 86 [2018-11-28 12:39:00,863 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-28 12:39:00,863 INFO L480 AbstractCegarLoop]: Abstraction has 227 states and 262 transitions. [2018-11-28 12:39:00,863 INFO L481 AbstractCegarLoop]: Interpolant automaton has 13 states. [2018-11-28 12:39:00,863 INFO L276 IsEmpty]: Start isEmpty. Operand 227 states and 262 transitions. [2018-11-28 12:39:00,863 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 90 [2018-11-28 12:39:00,863 INFO L394 BasicCegarLoop]: Found error trace [2018-11-28 12:39:00,864 INFO L402 BasicCegarLoop]: trace histogram [10, 10, 10, 10, 10, 10, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-28 12:39:00,864 INFO L423 AbstractCegarLoop]: === Iteration 24 === [__mainErr0ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr7ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr6ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr4ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr2ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr5ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr8ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr1ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr3ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr9ASSERT_VIOLATIONINTEGER_OVERFLOW, full_writeErr0ASSERT_VIOLATIONINTEGER_OVERFLOW, full_writeErr1ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr9ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr10ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr14ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr7ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr6ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr15ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr0ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr3ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr8ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr12ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr13ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr1ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr4ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr5ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr2ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr11ASSERT_VIOLATIONINTEGER_OVERFLOW]=== [2018-11-28 12:39:00,864 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-28 12:39:00,864 INFO L82 PathProgramCache]: Analyzing trace with hash -576225228, now seen corresponding path program 9 times [2018-11-28 12:39:00,864 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-28 12:39:00,864 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-28 12:39:00,869 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 12:39:00,869 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-28 12:39:00,869 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 12:39:01,165 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-28 12:39:01,525 WARN L180 SmtUtils]: Spent 106.00 ms on a formula simplification. DAG size of input: 61 DAG size of output: 35 [2018-11-28 12:39:01,872 INFO L134 CoverageAnalysis]: Checked inductivity of 291 backedges. 0 proven. 29 refuted. 0 times theorem prover too weak. 262 trivial. 0 not checked. [2018-11-28 12:39:01,872 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-28 12:39:01,872 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_a2c4633f-02cb-4486-be39-ce67b7f0e7a6/bin-2019/uautomizer/z3 Starting monitored process 14 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 14 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-28 12:39:01,889 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-11-28 12:39:48,887 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 12 check-sat command(s) [2018-11-28 12:39:48,888 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-11-28 12:39:48,900 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-28 12:39:48,957 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 6 treesize of output 5 [2018-11-28 12:39:48,958 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-11-28 12:39:48,966 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-28 12:39:48,967 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 1 variables, input treesize:16, output treesize:15 [2018-11-28 12:39:49,005 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 12:39:49,007 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 12:39:49,007 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 2 select indices, 2 select index equivalence classes, 2 disjoint index pairs (out of 1 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 17 treesize of output 21 [2018-11-28 12:39:49,008 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-11-28 12:39:49,048 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 12 [2018-11-28 12:39:49,052 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 12 treesize of output 11 [2018-11-28 12:39:49,053 INFO L267 ElimStorePlain]: Start of recursive call 4: End of recursive call: and 1 xjuncts. [2018-11-28 12:39:49,057 INFO L267 ElimStorePlain]: Start of recursive call 3: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-28 12:39:49,113 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 12 [2018-11-28 12:39:49,116 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 12 treesize of output 11 [2018-11-28 12:39:49,117 INFO L267 ElimStorePlain]: Start of recursive call 6: End of recursive call: and 1 xjuncts. [2018-11-28 12:39:49,124 INFO L267 ElimStorePlain]: Start of recursive call 5: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-28 12:39:49,152 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-1 vars, 2 dim-2 vars, End of recursive call: and 1 xjuncts. [2018-11-28 12:39:49,152 INFO L202 ElimStorePlain]: Needed 6 recursive calls to eliminate 3 variables, input treesize:59, output treesize:49 [2018-11-28 12:39:49,232 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 12:39:49,235 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 12:39:49,238 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 12:39:49,238 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 3 select indices, 3 select index equivalence classes, 4 disjoint index pairs (out of 3 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 16 treesize of output 13 [2018-11-28 12:39:49,239 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-11-28 12:39:49,326 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 2 disjoint index pairs (out of 0 index pairs), introduced 2 new quantified variables, introduced 0 case distinctions, treesize of input 634 treesize of output 452 [2018-11-28 12:39:49,410 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 12:39:49,413 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 3 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 22 treesize of output 35 [2018-11-28 12:39:49,414 INFO L267 ElimStorePlain]: Start of recursive call 4: End of recursive call: and 1 xjuncts. [2018-11-28 12:39:49,446 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 2 select indices, 2 select index equivalence classes, 3 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 0 case distinctions, treesize of input 154 treesize of output 146 [2018-11-28 12:39:49,451 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 2 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 12 treesize of output 11 [2018-11-28 12:39:49,451 INFO L267 ElimStorePlain]: Start of recursive call 6: End of recursive call: and 1 xjuncts. [2018-11-28 12:39:49,490 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 3 select indices, 3 select index equivalence classes, 3 disjoint index pairs (out of 3 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 141 treesize of output 150 [2018-11-28 12:39:49,495 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 104 treesize of output 1 [2018-11-28 12:39:49,495 INFO L267 ElimStorePlain]: Start of recursive call 8: End of recursive call: and 1 xjuncts. [2018-11-28 12:39:49,510 INFO L267 ElimStorePlain]: Start of recursive call 7: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-28 12:39:49,520 INFO L267 ElimStorePlain]: Start of recursive call 5: 1 dim-1 vars, 1 dim-2 vars, End of recursive call: and 1 xjuncts. [2018-11-28 12:39:49,534 INFO L267 ElimStorePlain]: Start of recursive call 3: 1 dim-1 vars, 1 dim-2 vars, End of recursive call: and 1 xjuncts. [2018-11-28 12:39:49,577 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 2 disjoint index pairs (out of 0 index pairs), introduced 2 new quantified variables, introduced 0 case distinctions, treesize of input 191 treesize of output 105 [2018-11-28 12:39:49,612 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 12:39:49,615 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 22 treesize of output 35 [2018-11-28 12:39:49,616 INFO L267 ElimStorePlain]: Start of recursive call 10: End of recursive call: and 1 xjuncts. [2018-11-28 12:39:49,635 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 2 select indices, 2 select index equivalence classes, 3 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 0 case distinctions, treesize of input 66 treesize of output 58 [2018-11-28 12:39:49,638 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 12 treesize of output 11 [2018-11-28 12:39:49,638 INFO L267 ElimStorePlain]: Start of recursive call 12: End of recursive call: and 1 xjuncts. [2018-11-28 12:39:49,662 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 3 select indices, 3 select index equivalence classes, 3 disjoint index pairs (out of 3 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 53 treesize of output 70 [2018-11-28 12:39:49,665 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 24 treesize of output 23 [2018-11-28 12:39:49,665 INFO L267 ElimStorePlain]: Start of recursive call 14: End of recursive call: and 1 xjuncts. [2018-11-28 12:39:49,677 INFO L267 ElimStorePlain]: Start of recursive call 13: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-28 12:39:49,685 INFO L267 ElimStorePlain]: Start of recursive call 11: 1 dim-1 vars, 1 dim-2 vars, End of recursive call: and 1 xjuncts. [2018-11-28 12:39:49,693 INFO L267 ElimStorePlain]: Start of recursive call 9: 1 dim-1 vars, 1 dim-2 vars, End of recursive call: and 1 xjuncts. [2018-11-28 12:39:49,723 INFO L267 ElimStorePlain]: Start of recursive call 1: 4 dim-0 vars, 1 dim-1 vars, 2 dim-2 vars, End of recursive call: 2 dim-0 vars, and 1 xjuncts. [2018-11-28 12:39:49,723 INFO L202 ElimStorePlain]: Needed 14 recursive calls to eliminate 7 variables, input treesize:676, output treesize:101 [2018-11-28 12:39:49,799 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 3 select indices, 3 select index equivalence classes, 3 disjoint index pairs (out of 3 index pairs), introduced 2 new quantified variables, introduced 0 case distinctions, treesize of input 173 treesize of output 169 [2018-11-28 12:39:49,802 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 48 treesize of output 47 [2018-11-28 12:39:49,802 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-11-28 12:39:49,818 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-28 12:39:49,864 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 3 select indices, 3 select index equivalence classes, 3 disjoint index pairs (out of 3 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 90 treesize of output 107 [2018-11-28 12:39:49,867 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 48 treesize of output 1 [2018-11-28 12:39:49,867 INFO L267 ElimStorePlain]: Start of recursive call 5: End of recursive call: and 1 xjuncts. [2018-11-28 12:39:49,877 INFO L267 ElimStorePlain]: Start of recursive call 4: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-28 12:39:49,903 INFO L267 ElimStorePlain]: Start of recursive call 1: 3 dim-0 vars, 2 dim-2 vars, End of recursive call: 2 dim-0 vars, and 1 xjuncts. [2018-11-28 12:39:49,903 INFO L202 ElimStorePlain]: Needed 5 recursive calls to eliminate 5 variables, input treesize:219, output treesize:101 [2018-11-28 12:39:49,936 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 3 select indices, 3 select index equivalence classes, 3 disjoint index pairs (out of 3 index pairs), introduced 2 new quantified variables, introduced 0 case distinctions, treesize of input 173 treesize of output 169 [2018-11-28 12:39:49,940 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 48 treesize of output 47 [2018-11-28 12:39:49,941 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-11-28 12:39:49,959 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-28 12:39:50,006 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 3 select indices, 3 select index equivalence classes, 3 disjoint index pairs (out of 3 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 90 treesize of output 107 [2018-11-28 12:39:50,010 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 48 treesize of output 1 [2018-11-28 12:39:50,010 INFO L267 ElimStorePlain]: Start of recursive call 5: End of recursive call: and 1 xjuncts. [2018-11-28 12:39:50,020 INFO L267 ElimStorePlain]: Start of recursive call 4: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-28 12:39:50,045 INFO L267 ElimStorePlain]: Start of recursive call 1: 3 dim-0 vars, 2 dim-2 vars, End of recursive call: 2 dim-0 vars, and 1 xjuncts. [2018-11-28 12:39:50,046 INFO L202 ElimStorePlain]: Needed 5 recursive calls to eliminate 5 variables, input treesize:219, output treesize:101 [2018-11-28 12:39:50,070 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 3 select indices, 3 select index equivalence classes, 3 disjoint index pairs (out of 3 index pairs), introduced 2 new quantified variables, introduced 0 case distinctions, treesize of input 173 treesize of output 169 [2018-11-28 12:39:50,074 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 48 treesize of output 47 [2018-11-28 12:39:50,074 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-11-28 12:39:50,091 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-28 12:39:50,156 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 3 select indices, 3 select index equivalence classes, 3 disjoint index pairs (out of 3 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 90 treesize of output 107 [2018-11-28 12:39:50,159 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 48 treesize of output 1 [2018-11-28 12:39:50,159 INFO L267 ElimStorePlain]: Start of recursive call 5: End of recursive call: and 1 xjuncts. [2018-11-28 12:39:50,180 INFO L267 ElimStorePlain]: Start of recursive call 4: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-28 12:39:50,212 INFO L267 ElimStorePlain]: Start of recursive call 1: 3 dim-0 vars, 2 dim-2 vars, End of recursive call: 2 dim-0 vars, and 1 xjuncts. [2018-11-28 12:39:50,212 INFO L202 ElimStorePlain]: Needed 5 recursive calls to eliminate 5 variables, input treesize:219, output treesize:101 [2018-11-28 12:39:50,246 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 3 select indices, 3 select index equivalence classes, 3 disjoint index pairs (out of 3 index pairs), introduced 2 new quantified variables, introduced 0 case distinctions, treesize of input 173 treesize of output 169 [2018-11-28 12:39:50,250 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 48 treesize of output 47 [2018-11-28 12:39:50,250 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-11-28 12:39:50,266 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-28 12:39:50,313 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 3 select indices, 3 select index equivalence classes, 3 disjoint index pairs (out of 3 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 90 treesize of output 107 [2018-11-28 12:39:50,317 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 48 treesize of output 1 [2018-11-28 12:39:50,317 INFO L267 ElimStorePlain]: Start of recursive call 5: End of recursive call: and 1 xjuncts. [2018-11-28 12:39:50,334 INFO L267 ElimStorePlain]: Start of recursive call 4: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-28 12:39:50,369 INFO L267 ElimStorePlain]: Start of recursive call 1: 3 dim-0 vars, 2 dim-2 vars, End of recursive call: 2 dim-0 vars, and 1 xjuncts. [2018-11-28 12:39:50,370 INFO L202 ElimStorePlain]: Needed 5 recursive calls to eliminate 5 variables, input treesize:219, output treesize:101 [2018-11-28 12:39:50,401 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 3 select indices, 3 select index equivalence classes, 3 disjoint index pairs (out of 3 index pairs), introduced 2 new quantified variables, introduced 0 case distinctions, treesize of input 173 treesize of output 169 [2018-11-28 12:39:50,406 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 48 treesize of output 47 [2018-11-28 12:39:50,406 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-11-28 12:39:50,435 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-28 12:39:50,494 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 3 select indices, 3 select index equivalence classes, 3 disjoint index pairs (out of 3 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 90 treesize of output 107 [2018-11-28 12:39:50,497 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 48 treesize of output 1 [2018-11-28 12:39:50,497 INFO L267 ElimStorePlain]: Start of recursive call 5: End of recursive call: and 1 xjuncts. [2018-11-28 12:39:50,509 INFO L267 ElimStorePlain]: Start of recursive call 4: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-28 12:39:50,540 INFO L267 ElimStorePlain]: Start of recursive call 1: 3 dim-0 vars, 2 dim-2 vars, End of recursive call: 2 dim-0 vars, and 1 xjuncts. [2018-11-28 12:39:50,540 INFO L202 ElimStorePlain]: Needed 5 recursive calls to eliminate 5 variables, input treesize:219, output treesize:101 [2018-11-28 12:39:50,565 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 3 select indices, 3 select index equivalence classes, 3 disjoint index pairs (out of 3 index pairs), introduced 2 new quantified variables, introduced 0 case distinctions, treesize of input 173 treesize of output 169 [2018-11-28 12:39:50,570 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 48 treesize of output 47 [2018-11-28 12:39:50,571 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-11-28 12:39:50,592 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-28 12:39:50,647 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 3 select indices, 3 select index equivalence classes, 3 disjoint index pairs (out of 3 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 90 treesize of output 107 [2018-11-28 12:39:50,651 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 48 treesize of output 1 [2018-11-28 12:39:50,651 INFO L267 ElimStorePlain]: Start of recursive call 5: End of recursive call: and 1 xjuncts. [2018-11-28 12:39:50,664 INFO L267 ElimStorePlain]: Start of recursive call 4: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-28 12:39:50,697 INFO L267 ElimStorePlain]: Start of recursive call 1: 3 dim-0 vars, 2 dim-2 vars, End of recursive call: 2 dim-0 vars, and 1 xjuncts. [2018-11-28 12:39:50,697 INFO L202 ElimStorePlain]: Needed 5 recursive calls to eliminate 5 variables, input treesize:219, output treesize:101 [2018-11-28 12:39:50,725 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 3 select indices, 3 select index equivalence classes, 3 disjoint index pairs (out of 3 index pairs), introduced 2 new quantified variables, introduced 0 case distinctions, treesize of input 173 treesize of output 169 [2018-11-28 12:39:50,729 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 48 treesize of output 47 [2018-11-28 12:39:50,729 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-11-28 12:39:50,747 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-28 12:39:50,795 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 3 select indices, 3 select index equivalence classes, 3 disjoint index pairs (out of 3 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 90 treesize of output 107 [2018-11-28 12:39:50,797 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 48 treesize of output 1 [2018-11-28 12:39:50,798 INFO L267 ElimStorePlain]: Start of recursive call 5: End of recursive call: and 1 xjuncts. [2018-11-28 12:39:50,808 INFO L267 ElimStorePlain]: Start of recursive call 4: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-28 12:39:50,833 INFO L267 ElimStorePlain]: Start of recursive call 1: 3 dim-0 vars, 2 dim-2 vars, End of recursive call: 2 dim-0 vars, and 1 xjuncts. [2018-11-28 12:39:50,833 INFO L202 ElimStorePlain]: Needed 5 recursive calls to eliminate 5 variables, input treesize:219, output treesize:101 [2018-11-28 12:39:50,851 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 3 select indices, 3 select index equivalence classes, 3 disjoint index pairs (out of 3 index pairs), introduced 2 new quantified variables, introduced 0 case distinctions, treesize of input 173 treesize of output 169 [2018-11-28 12:39:50,855 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 48 treesize of output 47 [2018-11-28 12:39:50,855 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-11-28 12:39:50,871 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-28 12:39:50,919 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 3 select indices, 3 select index equivalence classes, 3 disjoint index pairs (out of 3 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 90 treesize of output 107 [2018-11-28 12:39:50,923 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 48 treesize of output 1 [2018-11-28 12:39:50,923 INFO L267 ElimStorePlain]: Start of recursive call 5: End of recursive call: and 1 xjuncts. [2018-11-28 12:39:50,938 INFO L267 ElimStorePlain]: Start of recursive call 4: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-28 12:39:50,963 INFO L267 ElimStorePlain]: Start of recursive call 1: 3 dim-0 vars, 2 dim-2 vars, End of recursive call: 2 dim-0 vars, and 1 xjuncts. [2018-11-28 12:39:50,963 INFO L202 ElimStorePlain]: Needed 5 recursive calls to eliminate 5 variables, input treesize:219, output treesize:101 [2018-11-28 12:39:50,981 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 3 select indices, 3 select index equivalence classes, 3 disjoint index pairs (out of 3 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 149 treesize of output 166 [2018-11-28 12:39:50,984 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 48 treesize of output 47 [2018-11-28 12:39:50,984 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-11-28 12:39:50,998 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-28 12:39:51,042 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 3 select indices, 3 select index equivalence classes, 3 disjoint index pairs (out of 3 index pairs), introduced 2 new quantified variables, introduced 0 case distinctions, treesize of input 114 treesize of output 110 [2018-11-28 12:39:51,044 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 48 treesize of output 47 [2018-11-28 12:39:51,045 INFO L267 ElimStorePlain]: Start of recursive call 5: End of recursive call: and 1 xjuncts. [2018-11-28 12:39:51,057 INFO L267 ElimStorePlain]: Start of recursive call 4: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-28 12:39:51,082 INFO L267 ElimStorePlain]: Start of recursive call 1: 3 dim-0 vars, 2 dim-2 vars, End of recursive call: 2 dim-0 vars, and 1 xjuncts. [2018-11-28 12:39:51,082 INFO L202 ElimStorePlain]: Needed 5 recursive calls to eliminate 5 variables, input treesize:219, output treesize:101 [2018-11-28 12:39:51,108 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 3 select indices, 3 select index equivalence classes, 3 disjoint index pairs (out of 3 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 149 treesize of output 166 [2018-11-28 12:39:51,111 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 48 treesize of output 1 [2018-11-28 12:39:51,111 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-11-28 12:39:51,125 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-28 12:39:51,167 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 3 select indices, 3 select index equivalence classes, 3 disjoint index pairs (out of 3 index pairs), introduced 2 new quantified variables, introduced 0 case distinctions, treesize of input 114 treesize of output 110 [2018-11-28 12:39:51,170 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 48 treesize of output 47 [2018-11-28 12:39:51,170 INFO L267 ElimStorePlain]: Start of recursive call 5: End of recursive call: and 1 xjuncts. [2018-11-28 12:39:51,182 INFO L267 ElimStorePlain]: Start of recursive call 4: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-28 12:39:51,206 INFO L267 ElimStorePlain]: Start of recursive call 1: 3 dim-0 vars, 2 dim-2 vars, End of recursive call: 2 dim-0 vars, and 1 xjuncts. [2018-11-28 12:39:51,207 INFO L202 ElimStorePlain]: Needed 5 recursive calls to eliminate 5 variables, input treesize:219, output treesize:101 [2018-11-28 12:39:51,352 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 2 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 0 case distinctions, treesize of input 56 treesize of output 48 [2018-11-28 12:39:51,355 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 12:39:51,356 INFO L683 Elim1Store]: detected equality via solver [2018-11-28 12:39:51,360 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 3 select indices, 3 select index equivalence classes, 3 disjoint index pairs (out of 3 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 44 treesize of output 39 [2018-11-28 12:39:51,360 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-11-28 12:39:51,372 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 2 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 21 treesize of output 9 [2018-11-28 12:39:51,373 INFO L267 ElimStorePlain]: Start of recursive call 4: End of recursive call: and 1 xjuncts. [2018-11-28 12:39:51,375 INFO L267 ElimStorePlain]: Start of recursive call 2: 2 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-28 12:39:51,395 INFO L267 ElimStorePlain]: Start of recursive call 1: 4 dim-0 vars, 1 dim-2 vars, End of recursive call: 4 dim-0 vars, and 1 xjuncts. [2018-11-28 12:39:51,395 INFO L202 ElimStorePlain]: Needed 4 recursive calls to eliminate 5 variables, input treesize:112, output treesize:57 [2018-11-28 12:39:51,465 INFO L134 CoverageAnalysis]: Checked inductivity of 291 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 290 trivial. 0 not checked. [2018-11-28 12:39:51,488 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-11-28 12:39:51,488 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [11, 10] total 19 [2018-11-28 12:39:51,488 INFO L459 AbstractCegarLoop]: Interpolant automaton has 19 states [2018-11-28 12:39:51,489 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 19 interpolants. [2018-11-28 12:39:51,489 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=62, Invalid=280, Unknown=0, NotChecked=0, Total=342 [2018-11-28 12:39:51,489 INFO L87 Difference]: Start difference. First operand 227 states and 262 transitions. Second operand 19 states. [2018-11-28 12:39:52,618 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-28 12:39:52,618 INFO L93 Difference]: Finished difference Result 352 states and 422 transitions. [2018-11-28 12:39:52,618 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 12 states. [2018-11-28 12:39:52,619 INFO L78 Accepts]: Start accepts. Automaton has 19 states. Word has length 89 [2018-11-28 12:39:52,619 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-28 12:39:52,619 INFO L225 Difference]: With dead ends: 352 [2018-11-28 12:39:52,619 INFO L226 Difference]: Without dead ends: 243 [2018-11-28 12:39:52,620 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 117 GetRequests, 85 SyntacticMatches, 8 SemanticMatches, 24 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 135 ImplicationChecksByTransitivity, 1.3s TimeCoverageRelationStatistics Valid=133, Invalid=517, Unknown=0, NotChecked=0, Total=650 [2018-11-28 12:39:52,620 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 243 states. [2018-11-28 12:39:52,628 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 243 to 234. [2018-11-28 12:39:52,628 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 234 states. [2018-11-28 12:39:52,629 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 234 states to 234 states and 272 transitions. [2018-11-28 12:39:52,629 INFO L78 Accepts]: Start accepts. Automaton has 234 states and 272 transitions. Word has length 89 [2018-11-28 12:39:52,629 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-28 12:39:52,629 INFO L480 AbstractCegarLoop]: Abstraction has 234 states and 272 transitions. [2018-11-28 12:39:52,630 INFO L481 AbstractCegarLoop]: Interpolant automaton has 19 states. [2018-11-28 12:39:52,630 INFO L276 IsEmpty]: Start isEmpty. Operand 234 states and 272 transitions. [2018-11-28 12:39:52,630 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 91 [2018-11-28 12:39:52,630 INFO L394 BasicCegarLoop]: Found error trace [2018-11-28 12:39:52,630 INFO L402 BasicCegarLoop]: trace histogram [10, 10, 10, 10, 10, 10, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-28 12:39:52,630 INFO L423 AbstractCegarLoop]: === Iteration 25 === [__mainErr0ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr7ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr6ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr4ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr2ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr5ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr8ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr1ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr3ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr9ASSERT_VIOLATIONINTEGER_OVERFLOW, full_writeErr0ASSERT_VIOLATIONINTEGER_OVERFLOW, full_writeErr1ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr9ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr10ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr14ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr7ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr6ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr15ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr0ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr3ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr8ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr12ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr13ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr1ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr4ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr5ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr2ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr11ASSERT_VIOLATIONINTEGER_OVERFLOW]=== [2018-11-28 12:39:52,631 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-28 12:39:52,631 INFO L82 PathProgramCache]: Analyzing trace with hash 1101225913, now seen corresponding path program 1 times [2018-11-28 12:39:52,631 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-28 12:39:52,631 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-28 12:39:52,636 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 12:39:52,636 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-28 12:39:52,636 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 12:39:52,661 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-28 12:39:52,730 INFO L134 CoverageAnalysis]: Checked inductivity of 291 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 291 trivial. 0 not checked. [2018-11-28 12:39:52,730 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-28 12:39:52,731 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-28 12:39:52,731 INFO L459 AbstractCegarLoop]: Interpolant automaton has 4 states [2018-11-28 12:39:52,731 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2018-11-28 12:39:52,731 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2018-11-28 12:39:52,731 INFO L87 Difference]: Start difference. First operand 234 states and 272 transitions. Second operand 4 states. [2018-11-28 12:39:52,782 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-28 12:39:52,782 INFO L93 Difference]: Finished difference Result 235 states and 273 transitions. [2018-11-28 12:39:52,783 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2018-11-28 12:39:52,783 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 90 [2018-11-28 12:39:52,784 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-28 12:39:52,784 INFO L225 Difference]: With dead ends: 235 [2018-11-28 12:39:52,784 INFO L226 Difference]: Without dead ends: 234 [2018-11-28 12:39:52,785 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 4 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2018-11-28 12:39:52,785 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 234 states. [2018-11-28 12:39:52,792 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 234 to 233. [2018-11-28 12:39:52,792 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 233 states. [2018-11-28 12:39:52,793 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 233 states to 233 states and 271 transitions. [2018-11-28 12:39:52,793 INFO L78 Accepts]: Start accepts. Automaton has 233 states and 271 transitions. Word has length 90 [2018-11-28 12:39:52,793 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-28 12:39:52,793 INFO L480 AbstractCegarLoop]: Abstraction has 233 states and 271 transitions. [2018-11-28 12:39:52,793 INFO L481 AbstractCegarLoop]: Interpolant automaton has 4 states. [2018-11-28 12:39:52,793 INFO L276 IsEmpty]: Start isEmpty. Operand 233 states and 271 transitions. [2018-11-28 12:39:52,794 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 92 [2018-11-28 12:39:52,794 INFO L394 BasicCegarLoop]: Found error trace [2018-11-28 12:39:52,794 INFO L402 BasicCegarLoop]: trace histogram [10, 10, 10, 10, 10, 10, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-28 12:39:52,794 INFO L423 AbstractCegarLoop]: === Iteration 26 === [__mainErr0ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr7ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr6ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr4ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr2ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr5ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr8ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr1ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr3ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr9ASSERT_VIOLATIONINTEGER_OVERFLOW, full_writeErr0ASSERT_VIOLATIONINTEGER_OVERFLOW, full_writeErr1ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr9ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr10ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr14ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr7ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr6ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr15ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr0ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr3ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr8ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr12ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr13ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr1ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr4ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr5ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr2ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr11ASSERT_VIOLATIONINTEGER_OVERFLOW]=== [2018-11-28 12:39:52,794 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-28 12:39:52,794 INFO L82 PathProgramCache]: Analyzing trace with hash -221734862, now seen corresponding path program 1 times [2018-11-28 12:39:52,794 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-28 12:39:52,795 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-28 12:39:52,799 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 12:39:52,799 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-28 12:39:52,799 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 12:39:52,815 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-28 12:39:52,849 INFO L134 CoverageAnalysis]: Checked inductivity of 291 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 291 trivial. 0 not checked. [2018-11-28 12:39:52,850 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-28 12:39:52,850 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2018-11-28 12:39:52,850 INFO L459 AbstractCegarLoop]: Interpolant automaton has 3 states [2018-11-28 12:39:52,850 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-28 12:39:52,850 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-28 12:39:52,850 INFO L87 Difference]: Start difference. First operand 233 states and 271 transitions. Second operand 3 states. [2018-11-28 12:39:52,866 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-28 12:39:52,866 INFO L93 Difference]: Finished difference Result 237 states and 275 transitions. [2018-11-28 12:39:52,867 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-28 12:39:52,868 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 91 [2018-11-28 12:39:52,868 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-28 12:39:52,869 INFO L225 Difference]: With dead ends: 237 [2018-11-28 12:39:52,869 INFO L226 Difference]: Without dead ends: 236 [2018-11-28 12:39:52,869 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 2 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-28 12:39:52,869 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 236 states. [2018-11-28 12:39:52,876 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 236 to 236. [2018-11-28 12:39:52,876 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 236 states. [2018-11-28 12:39:52,877 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 236 states to 236 states and 274 transitions. [2018-11-28 12:39:52,877 INFO L78 Accepts]: Start accepts. Automaton has 236 states and 274 transitions. Word has length 91 [2018-11-28 12:39:52,877 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-28 12:39:52,877 INFO L480 AbstractCegarLoop]: Abstraction has 236 states and 274 transitions. [2018-11-28 12:39:52,878 INFO L481 AbstractCegarLoop]: Interpolant automaton has 3 states. [2018-11-28 12:39:52,878 INFO L276 IsEmpty]: Start isEmpty. Operand 236 states and 274 transitions. [2018-11-28 12:39:52,878 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 95 [2018-11-28 12:39:52,878 INFO L394 BasicCegarLoop]: Found error trace [2018-11-28 12:39:52,878 INFO L402 BasicCegarLoop]: trace histogram [10, 10, 10, 10, 10, 10, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-28 12:39:52,879 INFO L423 AbstractCegarLoop]: === Iteration 27 === [__mainErr0ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr7ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr6ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr4ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr2ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr5ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr8ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr1ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr3ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr9ASSERT_VIOLATIONINTEGER_OVERFLOW, full_writeErr0ASSERT_VIOLATIONINTEGER_OVERFLOW, full_writeErr1ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr9ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr10ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr14ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr7ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr6ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr15ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr0ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr3ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr8ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr12ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr13ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr1ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr4ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr5ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr2ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr11ASSERT_VIOLATIONINTEGER_OVERFLOW]=== [2018-11-28 12:39:52,879 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-28 12:39:52,879 INFO L82 PathProgramCache]: Analyzing trace with hash -43375882, now seen corresponding path program 1 times [2018-11-28 12:39:52,879 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-28 12:39:52,879 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-28 12:39:52,884 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 12:39:52,884 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-28 12:39:52,884 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 12:39:52,900 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-28 12:39:52,934 INFO L134 CoverageAnalysis]: Checked inductivity of 294 backedges. 3 proven. 0 refuted. 0 times theorem prover too weak. 291 trivial. 0 not checked. [2018-11-28 12:39:52,934 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-28 12:39:52,934 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2018-11-28 12:39:52,934 INFO L459 AbstractCegarLoop]: Interpolant automaton has 3 states [2018-11-28 12:39:52,934 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-28 12:39:52,934 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-28 12:39:52,934 INFO L87 Difference]: Start difference. First operand 236 states and 274 transitions. Second operand 3 states. [2018-11-28 12:39:52,946 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-28 12:39:52,946 INFO L93 Difference]: Finished difference Result 236 states and 274 transitions. [2018-11-28 12:39:52,948 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-28 12:39:52,948 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 94 [2018-11-28 12:39:52,948 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-28 12:39:52,949 INFO L225 Difference]: With dead ends: 236 [2018-11-28 12:39:52,949 INFO L226 Difference]: Without dead ends: 219 [2018-11-28 12:39:52,949 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 2 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-28 12:39:52,949 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 219 states. [2018-11-28 12:39:52,955 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 219 to 218. [2018-11-28 12:39:52,955 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 218 states. [2018-11-28 12:39:52,956 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 218 states to 218 states and 250 transitions. [2018-11-28 12:39:52,956 INFO L78 Accepts]: Start accepts. Automaton has 218 states and 250 transitions. Word has length 94 [2018-11-28 12:39:52,956 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-28 12:39:52,956 INFO L480 AbstractCegarLoop]: Abstraction has 218 states and 250 transitions. [2018-11-28 12:39:52,956 INFO L481 AbstractCegarLoop]: Interpolant automaton has 3 states. [2018-11-28 12:39:52,956 INFO L276 IsEmpty]: Start isEmpty. Operand 218 states and 250 transitions. [2018-11-28 12:39:52,957 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 115 [2018-11-28 12:39:52,957 INFO L394 BasicCegarLoop]: Found error trace [2018-11-28 12:39:52,957 INFO L402 BasicCegarLoop]: trace histogram [20, 20, 20, 10, 10, 10, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-28 12:39:52,957 INFO L423 AbstractCegarLoop]: === Iteration 28 === [__mainErr0ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr7ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr6ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr4ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr2ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr5ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr8ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr1ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr3ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr9ASSERT_VIOLATIONINTEGER_OVERFLOW, full_writeErr0ASSERT_VIOLATIONINTEGER_OVERFLOW, full_writeErr1ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr9ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr10ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr14ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr7ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr6ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr15ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr0ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr3ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr8ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr12ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr13ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr1ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr4ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr5ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr2ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr11ASSERT_VIOLATIONINTEGER_OVERFLOW]=== [2018-11-28 12:39:52,957 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-28 12:39:52,958 INFO L82 PathProgramCache]: Analyzing trace with hash 1510247437, now seen corresponding path program 1 times [2018-11-28 12:39:52,958 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-28 12:39:52,958 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-28 12:39:52,964 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 12:39:52,964 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-28 12:39:52,964 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 12:39:52,981 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-28 12:39:53,032 INFO L134 CoverageAnalysis]: Checked inductivity of 759 backedges. 324 proven. 0 refuted. 0 times theorem prover too weak. 435 trivial. 0 not checked. [2018-11-28 12:39:53,032 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-28 12:39:53,032 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2018-11-28 12:39:53,033 INFO L459 AbstractCegarLoop]: Interpolant automaton has 3 states [2018-11-28 12:39:53,033 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-28 12:39:53,033 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-28 12:39:53,033 INFO L87 Difference]: Start difference. First operand 218 states and 250 transitions. Second operand 3 states. [2018-11-28 12:39:53,051 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-28 12:39:53,051 INFO L93 Difference]: Finished difference Result 218 states and 250 transitions. [2018-11-28 12:39:53,052 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-28 12:39:53,052 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 114 [2018-11-28 12:39:53,052 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-28 12:39:53,053 INFO L225 Difference]: With dead ends: 218 [2018-11-28 12:39:53,053 INFO L226 Difference]: Without dead ends: 217 [2018-11-28 12:39:53,053 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 2 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-28 12:39:53,053 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 217 states. [2018-11-28 12:39:53,060 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 217 to 217. [2018-11-28 12:39:53,060 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 217 states. [2018-11-28 12:39:53,061 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 217 states to 217 states and 249 transitions. [2018-11-28 12:39:53,061 INFO L78 Accepts]: Start accepts. Automaton has 217 states and 249 transitions. Word has length 114 [2018-11-28 12:39:53,061 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-28 12:39:53,061 INFO L480 AbstractCegarLoop]: Abstraction has 217 states and 249 transitions. [2018-11-28 12:39:53,061 INFO L481 AbstractCegarLoop]: Interpolant automaton has 3 states. [2018-11-28 12:39:53,061 INFO L276 IsEmpty]: Start isEmpty. Operand 217 states and 249 transitions. [2018-11-28 12:39:53,062 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 127 [2018-11-28 12:39:53,062 INFO L394 BasicCegarLoop]: Found error trace [2018-11-28 12:39:53,062 INFO L402 BasicCegarLoop]: trace histogram [10, 10, 10, 10, 10, 10, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-28 12:39:53,063 INFO L423 AbstractCegarLoop]: === Iteration 29 === [__mainErr0ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr7ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr6ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr4ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr2ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr5ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr8ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr1ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr3ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr9ASSERT_VIOLATIONINTEGER_OVERFLOW, full_writeErr0ASSERT_VIOLATIONINTEGER_OVERFLOW, full_writeErr1ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr9ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr10ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr14ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr7ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr6ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr15ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr0ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr3ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr8ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr12ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr13ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr1ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr4ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr5ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr2ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr11ASSERT_VIOLATIONINTEGER_OVERFLOW]=== [2018-11-28 12:39:53,063 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-28 12:39:53,063 INFO L82 PathProgramCache]: Analyzing trace with hash 1035682170, now seen corresponding path program 1 times [2018-11-28 12:39:53,063 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-28 12:39:53,063 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-28 12:39:53,068 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 12:39:53,068 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-28 12:39:53,069 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 12:39:53,095 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-28 12:39:53,217 INFO L134 CoverageAnalysis]: Checked inductivity of 291 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 291 trivial. 0 not checked. [2018-11-28 12:39:53,217 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-28 12:39:53,217 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-28 12:39:53,217 INFO L459 AbstractCegarLoop]: Interpolant automaton has 4 states [2018-11-28 12:39:53,217 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2018-11-28 12:39:53,217 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=6, Invalid=6, Unknown=0, NotChecked=0, Total=12 [2018-11-28 12:39:53,218 INFO L87 Difference]: Start difference. First operand 217 states and 249 transitions. Second operand 4 states. [2018-11-28 12:39:53,257 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-28 12:39:53,257 INFO L93 Difference]: Finished difference Result 225 states and 258 transitions. [2018-11-28 12:39:53,258 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2018-11-28 12:39:53,258 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 126 [2018-11-28 12:39:53,258 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-28 12:39:53,259 INFO L225 Difference]: With dead ends: 225 [2018-11-28 12:39:53,259 INFO L226 Difference]: Without dead ends: 224 [2018-11-28 12:39:53,259 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 2 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=6, Invalid=6, Unknown=0, NotChecked=0, Total=12 [2018-11-28 12:39:53,259 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 224 states. [2018-11-28 12:39:53,268 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 224 to 222. [2018-11-28 12:39:53,268 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 222 states. [2018-11-28 12:39:53,269 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 222 states to 222 states and 255 transitions. [2018-11-28 12:39:53,269 INFO L78 Accepts]: Start accepts. Automaton has 222 states and 255 transitions. Word has length 126 [2018-11-28 12:39:53,269 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-28 12:39:53,269 INFO L480 AbstractCegarLoop]: Abstraction has 222 states and 255 transitions. [2018-11-28 12:39:53,269 INFO L481 AbstractCegarLoop]: Interpolant automaton has 4 states. [2018-11-28 12:39:53,269 INFO L276 IsEmpty]: Start isEmpty. Operand 222 states and 255 transitions. [2018-11-28 12:39:53,270 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 128 [2018-11-28 12:39:53,270 INFO L394 BasicCegarLoop]: Found error trace [2018-11-28 12:39:53,270 INFO L402 BasicCegarLoop]: trace histogram [10, 10, 10, 10, 10, 10, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-28 12:39:53,271 INFO L423 AbstractCegarLoop]: === Iteration 30 === [__mainErr0ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr7ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr6ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr4ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr2ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr5ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr8ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr1ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr3ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr9ASSERT_VIOLATIONINTEGER_OVERFLOW, full_writeErr0ASSERT_VIOLATIONINTEGER_OVERFLOW, full_writeErr1ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr9ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr10ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr14ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr7ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr6ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr15ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr0ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr3ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr8ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr12ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr13ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr1ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr4ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr5ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr2ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr11ASSERT_VIOLATIONINTEGER_OVERFLOW]=== [2018-11-28 12:39:53,271 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-28 12:39:53,271 INFO L82 PathProgramCache]: Analyzing trace with hash 2041376282, now seen corresponding path program 1 times [2018-11-28 12:39:53,271 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-28 12:39:53,271 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-28 12:39:53,276 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 12:39:53,276 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-28 12:39:53,276 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 12:39:53,303 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-28 12:39:53,377 INFO L134 CoverageAnalysis]: Checked inductivity of 291 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 291 trivial. 0 not checked. [2018-11-28 12:39:53,377 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-28 12:39:53,377 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-28 12:39:53,377 INFO L459 AbstractCegarLoop]: Interpolant automaton has 4 states [2018-11-28 12:39:53,377 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2018-11-28 12:39:53,377 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=6, Invalid=6, Unknown=0, NotChecked=0, Total=12 [2018-11-28 12:39:53,378 INFO L87 Difference]: Start difference. First operand 222 states and 255 transitions. Second operand 4 states. [2018-11-28 12:39:53,407 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-28 12:39:53,408 INFO L93 Difference]: Finished difference Result 224 states and 257 transitions. [2018-11-28 12:39:53,408 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2018-11-28 12:39:53,408 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 127 [2018-11-28 12:39:53,408 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-28 12:39:53,409 INFO L225 Difference]: With dead ends: 224 [2018-11-28 12:39:53,409 INFO L226 Difference]: Without dead ends: 223 [2018-11-28 12:39:53,410 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 2 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=6, Invalid=6, Unknown=0, NotChecked=0, Total=12 [2018-11-28 12:39:53,410 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 223 states. [2018-11-28 12:39:53,419 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 223 to 223. [2018-11-28 12:39:53,419 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 223 states. [2018-11-28 12:39:53,420 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 223 states to 223 states and 256 transitions. [2018-11-28 12:39:53,420 INFO L78 Accepts]: Start accepts. Automaton has 223 states and 256 transitions. Word has length 127 [2018-11-28 12:39:53,420 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-28 12:39:53,420 INFO L480 AbstractCegarLoop]: Abstraction has 223 states and 256 transitions. [2018-11-28 12:39:53,421 INFO L481 AbstractCegarLoop]: Interpolant automaton has 4 states. [2018-11-28 12:39:53,421 INFO L276 IsEmpty]: Start isEmpty. Operand 223 states and 256 transitions. [2018-11-28 12:39:53,422 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 124 [2018-11-28 12:39:53,422 INFO L394 BasicCegarLoop]: Found error trace [2018-11-28 12:39:53,422 INFO L402 BasicCegarLoop]: trace histogram [20, 20, 20, 10, 10, 10, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-28 12:39:53,423 INFO L423 AbstractCegarLoop]: === Iteration 31 === [__mainErr0ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr7ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr6ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr4ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr2ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr5ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr8ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr1ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr3ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr9ASSERT_VIOLATIONINTEGER_OVERFLOW, full_writeErr0ASSERT_VIOLATIONINTEGER_OVERFLOW, full_writeErr1ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr9ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr10ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr14ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr7ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr6ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr15ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr0ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr3ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr8ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr12ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr13ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr1ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr4ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr5ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr2ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr11ASSERT_VIOLATIONINTEGER_OVERFLOW]=== [2018-11-28 12:39:53,424 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-28 12:39:53,424 INFO L82 PathProgramCache]: Analyzing trace with hash -1749488180, now seen corresponding path program 10 times [2018-11-28 12:39:53,424 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-28 12:39:53,424 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-28 12:39:53,429 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 12:39:53,429 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-28 12:39:53,429 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 12:39:54,200 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-28 12:39:54,660 WARN L180 SmtUtils]: Spent 104.00 ms on a formula simplification. DAG size of input: 30 DAG size of output: 23 [2018-11-28 12:39:55,278 WARN L180 SmtUtils]: Spent 137.00 ms on a formula simplification. DAG size of input: 71 DAG size of output: 40 [2018-11-28 12:39:55,417 WARN L180 SmtUtils]: Spent 120.00 ms on a formula simplification. DAG size of input: 73 DAG size of output: 46 [2018-11-28 12:39:55,585 WARN L180 SmtUtils]: Spent 142.00 ms on a formula simplification. DAG size of input: 86 DAG size of output: 46 [2018-11-28 12:39:55,846 WARN L180 SmtUtils]: Spent 147.00 ms on a formula simplification. DAG size of input: 76 DAG size of output: 47 [2018-11-28 12:39:56,041 WARN L180 SmtUtils]: Spent 142.00 ms on a formula simplification. DAG size of input: 84 DAG size of output: 48 [2018-11-28 12:39:56,212 WARN L180 SmtUtils]: Spent 142.00 ms on a formula simplification. DAG size of input: 81 DAG size of output: 48 [2018-11-28 12:39:56,385 WARN L180 SmtUtils]: Spent 138.00 ms on a formula simplification. DAG size of input: 93 DAG size of output: 46 [2018-11-28 12:39:56,579 WARN L180 SmtUtils]: Spent 130.00 ms on a formula simplification. DAG size of input: 78 DAG size of output: 46 [2018-11-28 12:39:56,782 WARN L180 SmtUtils]: Spent 132.00 ms on a formula simplification. DAG size of input: 80 DAG size of output: 46 [2018-11-28 12:39:57,009 WARN L180 SmtUtils]: Spent 150.00 ms on a formula simplification. DAG size of input: 82 DAG size of output: 46 [2018-11-28 12:39:57,189 WARN L180 SmtUtils]: Spent 139.00 ms on a formula simplification. DAG size of input: 80 DAG size of output: 45 [2018-11-28 12:39:57,381 WARN L180 SmtUtils]: Spent 144.00 ms on a formula simplification. DAG size of input: 82 DAG size of output: 47 [2018-11-28 12:39:57,593 WARN L180 SmtUtils]: Spent 124.00 ms on a formula simplification. DAG size of input: 74 DAG size of output: 46 [2018-11-28 12:39:58,371 INFO L134 CoverageAnalysis]: Checked inductivity of 761 backedges. 0 proven. 499 refuted. 0 times theorem prover too weak. 262 trivial. 0 not checked. [2018-11-28 12:39:58,371 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-28 12:39:58,372 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_a2c4633f-02cb-4486-be39-ce67b7f0e7a6/bin-2019/uautomizer/z3 Starting monitored process 15 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 15 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-28 12:39:58,388 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-11-28 12:39:58,541 INFO L249 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-11-28 12:39:58,541 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-11-28 12:39:58,549 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-28 12:39:58,560 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 132 treesize of output 122 [2018-11-28 12:39:58,565 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 12:39:58,603 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 2 case distinctions, treesize of input 122 treesize of output 116 [2018-11-28 12:39:58,614 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 110 treesize of output 100 [2018-11-28 12:39:58,641 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 97 treesize of output 87 [2018-11-28 12:39:58,721 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 12:39:58,727 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 12:39:58,731 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 12:39:58,779 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 12:39:58,780 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 4 select indices, 4 select index equivalence classes, 5 disjoint index pairs (out of 6 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 84 treesize of output 99 [2018-11-28 12:39:58,913 WARN L180 SmtUtils]: Spent 131.00 ms on a formula simplification. DAG size of input: 48 DAG size of output: 38 [2018-11-28 12:39:58,936 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 12:39:58,940 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 12:39:58,943 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 12:39:58,946 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 12:39:58,961 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 12:39:58,970 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 12:39:58,973 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 12:39:58,977 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 12:39:58,978 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 6 select indices, 6 select index equivalence classes, 10 disjoint index pairs (out of 15 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 74 treesize of output 110 [2018-11-28 12:39:59,142 WARN L180 SmtUtils]: Spent 162.00 ms on a formula simplification. DAG size of input: 58 DAG size of output: 46 [2018-11-28 12:39:59,161 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 12:39:59,164 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 12:39:59,167 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 12:39:59,179 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 12:39:59,182 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 12:39:59,189 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 12:39:59,192 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 12:39:59,194 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 12:39:59,197 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 12:39:59,200 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 12:39:59,201 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 7 select indices, 7 select index equivalence classes, 16 disjoint index pairs (out of 21 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 62 treesize of output 127 [2018-11-28 12:39:59,379 WARN L180 SmtUtils]: Spent 176.00 ms on a formula simplification. DAG size of input: 69 DAG size of output: 55 [2018-11-28 12:39:59,393 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 12:39:59,395 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 12:39:59,397 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 12:39:59,399 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 12:39:59,407 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 12:39:59,408 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 12:39:59,417 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 12:39:59,418 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 12:39:59,421 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 12:39:59,422 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 12:39:59,424 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 12:39:59,426 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 12:39:59,427 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 8 select indices, 8 select index equivalence classes, 23 disjoint index pairs (out of 28 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 53 treesize of output 147 [2018-11-28 12:39:59,448 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 8 select indices, 8 select index equivalence classes, 23 disjoint index pairs (out of 28 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 56 treesize of output 144 [2018-11-28 12:39:59,486 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 8 select indices, 8 select index equivalence classes, 23 disjoint index pairs (out of 28 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 53 treesize of output 138 [2018-11-28 12:39:59,486 INFO L267 ElimStorePlain]: Start of recursive call 11: End of recursive call: and 1 xjuncts. [2018-11-28 12:39:59,543 INFO L267 ElimStorePlain]: Start of recursive call 10: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-28 12:39:59,602 INFO L267 ElimStorePlain]: Start of recursive call 9: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-28 12:39:59,664 INFO L267 ElimStorePlain]: Start of recursive call 8: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-28 12:39:59,729 INFO L267 ElimStorePlain]: Start of recursive call 7: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-28 12:39:59,795 INFO L267 ElimStorePlain]: Start of recursive call 6: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-28 12:39:59,884 INFO L267 ElimStorePlain]: Start of recursive call 5: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-28 12:39:59,969 INFO L267 ElimStorePlain]: Start of recursive call 4: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-28 12:40:00,090 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 12:40:00,107 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 12:40:00,150 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 2 select indices, 2 select index equivalence classes, 2 disjoint index pairs (out of 1 index pairs), introduced 1 new quantified variables, introduced 2 case distinctions, treesize of input 112 treesize of output 110 [2018-11-28 12:40:00,177 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 12:40:00,196 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 12:40:00,208 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 3 select indices, 3 select index equivalence classes, 3 disjoint index pairs (out of 3 index pairs), introduced 1 new quantified variables, introduced 2 case distinctions, treesize of input 106 treesize of output 104 [2018-11-28 12:40:00,464 WARN L180 SmtUtils]: Spent 255.00 ms on a formula simplification. DAG size of input: 68 DAG size of output: 68 [2018-11-28 12:40:00,473 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 12:40:00,477 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 12:40:00,480 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 12:40:00,510 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 12:40:00,510 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 4 select indices, 4 select index equivalence classes, 7 disjoint index pairs (out of 6 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 99 treesize of output 118 [2018-11-28 12:40:00,678 WARN L180 SmtUtils]: Spent 167.00 ms on a formula simplification. DAG size of input: 57 DAG size of output: 43 [2018-11-28 12:40:00,687 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 12:40:00,707 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 12:40:00,710 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 12:40:00,714 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 12:40:00,717 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 12:40:00,721 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 12:40:00,729 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 12:40:00,733 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 12:40:00,736 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 12:40:00,737 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 6 select indices, 6 select index equivalence classes, 12 disjoint index pairs (out of 15 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 74 treesize of output 118 [2018-11-28 12:40:00,938 WARN L180 SmtUtils]: Spent 199.00 ms on a formula simplification. DAG size of input: 62 DAG size of output: 50 [2018-11-28 12:40:00,962 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 12:40:00,965 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 12:40:00,968 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 12:40:00,971 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 12:40:00,974 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 12:40:00,981 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 12:40:00,984 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 12:40:00,987 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 12:40:00,990 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 12:40:00,993 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 12:40:00,993 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 7 select indices, 7 select index equivalence classes, 18 disjoint index pairs (out of 21 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 62 treesize of output 135 [2018-11-28 12:40:01,171 WARN L180 SmtUtils]: Spent 176.00 ms on a formula simplification. DAG size of input: 73 DAG size of output: 59 [2018-11-28 12:40:01,186 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 12:40:01,188 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 12:40:01,191 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 12:40:01,193 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 12:40:01,195 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 12:40:01,197 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 12:40:01,202 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 12:40:01,204 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 12:40:01,206 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 12:40:01,208 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 12:40:01,210 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 12:40:01,213 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 12:40:01,214 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 8 select indices, 8 select index equivalence classes, 25 disjoint index pairs (out of 28 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 53 treesize of output 155 [2018-11-28 12:40:01,225 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 8 select indices, 8 select index equivalence classes, 25 disjoint index pairs (out of 28 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 56 treesize of output 152 [2018-11-28 12:40:01,249 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 8 select indices, 8 select index equivalence classes, 25 disjoint index pairs (out of 28 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 53 treesize of output 146 [2018-11-28 12:40:01,250 INFO L267 ElimStorePlain]: Start of recursive call 19: End of recursive call: and 1 xjuncts. [2018-11-28 12:40:01,307 INFO L267 ElimStorePlain]: Start of recursive call 18: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-28 12:40:01,371 INFO L267 ElimStorePlain]: Start of recursive call 17: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-28 12:40:01,438 INFO L267 ElimStorePlain]: Start of recursive call 16: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-28 12:40:01,508 INFO L267 ElimStorePlain]: Start of recursive call 15: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-28 12:40:01,584 INFO L267 ElimStorePlain]: Start of recursive call 14: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-28 12:40:01,706 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 12:40:01,707 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 12:40:01,708 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 12:40:01,715 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 12:40:01,719 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 12:40:01,722 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 12:40:01,727 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 12:40:01,765 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 5 select indices, 5 select index equivalence classes, 8 disjoint index pairs (out of 10 index pairs), introduced 1 new quantified variables, introduced 2 case distinctions, treesize of input 93 treesize of output 120 [2018-11-28 12:40:02,262 WARN L180 SmtUtils]: Spent 495.00 ms on a formula simplification. DAG size of input: 84 DAG size of output: 72 [2018-11-28 12:40:02,270 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 12:40:02,292 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 12:40:02,296 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 12:40:02,299 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 12:40:02,304 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 12:40:02,307 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 12:40:02,331 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 12:40:02,334 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 12:40:02,344 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 12:40:02,348 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 12:40:02,352 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 12:40:02,356 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 12:40:02,372 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 12:40:02,373 INFO L303 Elim1Store]: Index analysis took 109 ms [2018-11-28 12:40:02,400 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 7 select indices, 7 select index equivalence classes, 14 disjoint index pairs (out of 21 index pairs), introduced 1 new quantified variables, introduced 2 case distinctions, treesize of input 83 treesize of output 132 [2018-11-28 12:40:02,912 WARN L180 SmtUtils]: Spent 509.00 ms on a formula simplification. DAG size of input: 94 DAG size of output: 78 [2018-11-28 12:40:02,932 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 12:40:02,935 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 12:40:02,938 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 12:40:02,941 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 12:40:02,943 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 12:40:02,946 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 12:40:02,959 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 12:40:02,962 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 12:40:02,964 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 12:40:02,972 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 12:40:02,975 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 12:40:02,978 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 12:40:02,981 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 12:40:02,984 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 12:40:02,988 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 12:40:03,007 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 12:40:03,026 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 8 select indices, 8 select index equivalence classes, 21 disjoint index pairs (out of 28 index pairs), introduced 1 new quantified variables, introduced 2 case distinctions, treesize of input 87 treesize of output 153 [2018-11-28 12:40:03,592 WARN L180 SmtUtils]: Spent 563.00 ms on a formula simplification. DAG size of input: 106 DAG size of output: 88 [2018-11-28 12:40:03,606 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 12:40:03,608 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 12:40:03,610 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 12:40:03,612 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 12:40:03,620 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 12:40:03,622 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 12:40:03,627 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 12:40:03,630 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 12:40:03,632 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 12:40:03,634 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 12:40:03,636 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 12:40:03,638 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 12:40:03,641 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 12:40:03,642 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 8 select indices, 8 select index equivalence classes, 23 disjoint index pairs (out of 28 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 96 treesize of output 165 [2018-11-28 12:40:03,669 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 8 select indices, 8 select index equivalence classes, 23 disjoint index pairs (out of 28 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 58 treesize of output 144 [2018-11-28 12:40:03,712 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 8 select indices, 8 select index equivalence classes, 23 disjoint index pairs (out of 28 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 53 treesize of output 138 [2018-11-28 12:40:03,712 INFO L267 ElimStorePlain]: Start of recursive call 25: End of recursive call: and 1 xjuncts. [2018-11-28 12:40:03,765 INFO L267 ElimStorePlain]: Start of recursive call 24: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-28 12:40:03,843 INFO L267 ElimStorePlain]: Start of recursive call 23: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-28 12:40:03,997 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 12:40:03,999 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 12:40:04,001 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 12:40:04,004 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 12:40:04,005 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 12:40:04,008 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 12:40:04,016 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 12:40:04,018 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 12:40:04,020 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 12:40:04,026 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 12:40:04,028 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 12:40:04,030 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 12:40:04,032 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 12:40:04,034 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 12:40:04,036 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 12:40:04,038 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 12:40:04,044 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 12:40:04,050 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 12:40:04,055 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 12:40:04,065 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 9 select indices, 9 select index equivalence classes, 29 disjoint index pairs (out of 36 index pairs), introduced 1 new quantified variables, introduced 2 case distinctions, treesize of input 98 treesize of output 177 [2018-11-28 12:40:04,079 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 8 select indices, 8 select index equivalence classes, 23 disjoint index pairs (out of 28 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 171 treesize of output 168 [2018-11-28 12:40:04,107 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 8 select indices, 8 select index equivalence classes, 23 disjoint index pairs (out of 28 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 53 treesize of output 134 [2018-11-28 12:40:04,108 INFO L267 ElimStorePlain]: Start of recursive call 28: End of recursive call: and 1 xjuncts. [2018-11-28 12:40:04,203 INFO L267 ElimStorePlain]: Start of recursive call 27: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-28 12:40:04,416 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 12:40:04,417 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 12:40:04,418 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 12:40:04,420 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 12:40:04,424 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 12:40:04,425 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 12:40:04,427 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 12:40:04,428 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 12:40:04,430 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 12:40:04,431 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 12:40:04,432 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 12:40:04,433 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 12:40:04,434 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 12:40:04,437 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 12:40:04,439 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 12:40:04,451 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 9 select indices, 9 select index equivalence classes, 30 disjoint index pairs (out of 36 index pairs), introduced 1 new quantified variables, introduced 2 case distinctions, treesize of input 115 treesize of output 178 [2018-11-28 12:40:04,480 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 8 select indices, 8 select index equivalence classes, 23 disjoint index pairs (out of 28 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 172 treesize of output 165 [2018-11-28 12:40:04,480 INFO L267 ElimStorePlain]: Start of recursive call 30: End of recursive call: and 1 xjuncts. [2018-11-28 12:40:04,769 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 12:40:04,774 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 12:40:04,781 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 12:40:04,786 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 12:40:04,790 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 12:40:04,793 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 12:40:04,797 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 12:40:04,802 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 12:40:04,807 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 12:40:04,817 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 9 select indices, 9 select index equivalence classes, 31 disjoint index pairs (out of 36 index pairs), introduced 0 new quantified variables, introduced 2 case distinctions, treesize of input 140 treesize of output 175 [2018-11-28 12:40:04,818 INFO L267 ElimStorePlain]: Start of recursive call 31: End of recursive call: and 2 xjuncts. [2018-11-28 12:40:05,155 INFO L267 ElimStorePlain]: Start of recursive call 29: 2 dim-1 vars, End of recursive call: and 3 xjuncts. [2018-11-28 12:40:05,542 INFO L267 ElimStorePlain]: Start of recursive call 26: 2 dim-1 vars, End of recursive call: and 4 xjuncts. [2018-11-28 12:40:05,995 INFO L267 ElimStorePlain]: Start of recursive call 22: 2 dim-1 vars, End of recursive call: and 5 xjuncts. [2018-11-28 12:40:06,524 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 12:40:06,528 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 12:40:06,531 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 12:40:06,534 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 12:40:06,546 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 12:40:06,549 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 12:40:06,557 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 12:40:06,560 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 12:40:06,563 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 12:40:06,566 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 12:40:06,569 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 12:40:06,570 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 7 select indices, 7 select index equivalence classes, 16 disjoint index pairs (out of 21 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 85 treesize of output 139 [2018-11-28 12:40:06,754 WARN L180 SmtUtils]: Spent 168.00 ms on a formula simplification. DAG size of input: 75 DAG size of output: 55 [2018-11-28 12:40:06,768 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 12:40:06,770 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 12:40:06,772 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 12:40:06,774 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 12:40:06,783 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 12:40:06,784 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 12:40:06,789 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 12:40:06,791 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 12:40:06,793 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 12:40:06,795 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 12:40:06,797 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 12:40:06,799 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 12:40:06,801 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 12:40:06,801 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 8 select indices, 8 select index equivalence classes, 23 disjoint index pairs (out of 28 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 53 treesize of output 149 [2018-11-28 12:40:06,819 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 8 select indices, 8 select index equivalence classes, 23 disjoint index pairs (out of 28 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 58 treesize of output 144 [2018-11-28 12:40:06,847 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 8 select indices, 8 select index equivalence classes, 23 disjoint index pairs (out of 28 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 53 treesize of output 138 [2018-11-28 12:40:06,848 INFO L267 ElimStorePlain]: Start of recursive call 35: End of recursive call: and 1 xjuncts. [2018-11-28 12:40:06,901 INFO L267 ElimStorePlain]: Start of recursive call 34: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-28 12:40:06,962 INFO L267 ElimStorePlain]: Start of recursive call 33: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-28 12:40:07,033 INFO L267 ElimStorePlain]: Start of recursive call 32: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-28 12:40:07,559 INFO L267 ElimStorePlain]: Start of recursive call 21: 2 dim-1 vars, End of recursive call: and 6 xjuncts. [2018-11-28 12:40:08,156 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 12:40:08,160 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 12:40:08,163 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 12:40:08,166 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 12:40:08,170 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 12:40:08,186 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 12:40:08,195 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 12:40:08,199 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 12:40:08,203 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 12:40:08,204 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 6 select indices, 6 select index equivalence classes, 13 disjoint index pairs (out of 15 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 93 treesize of output 134 [2018-11-28 12:40:08,411 WARN L180 SmtUtils]: Spent 206.00 ms on a formula simplification. DAG size of input: 70 DAG size of output: 52 [2018-11-28 12:40:08,417 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 12:40:08,421 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 12:40:08,423 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 12:40:08,426 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 12:40:08,438 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 12:40:08,441 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 12:40:08,448 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 12:40:08,451 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 12:40:08,454 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 12:40:08,456 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 12:40:08,459 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 12:40:08,459 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 7 select indices, 7 select index equivalence classes, 19 disjoint index pairs (out of 21 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 62 treesize of output 139 [2018-11-28 12:40:08,649 WARN L180 SmtUtils]: Spent 189.00 ms on a formula simplification. DAG size of input: 75 DAG size of output: 61 [2018-11-28 12:40:08,657 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 12:40:08,660 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 12:40:08,661 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 12:40:08,665 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 12:40:08,675 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 12:40:08,677 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 12:40:08,682 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 12:40:08,684 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 12:40:08,685 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 12:40:08,687 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 12:40:08,689 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 12:40:08,691 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 12:40:08,692 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 8 select indices, 8 select index equivalence classes, 26 disjoint index pairs (out of 28 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 53 treesize of output 161 [2018-11-28 12:40:08,703 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 8 select indices, 8 select index equivalence classes, 26 disjoint index pairs (out of 28 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 58 treesize of output 156 [2018-11-28 12:40:08,726 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 8 select indices, 8 select index equivalence classes, 26 disjoint index pairs (out of 28 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 53 treesize of output 150 [2018-11-28 12:40:08,727 INFO L267 ElimStorePlain]: Start of recursive call 40: End of recursive call: and 1 xjuncts. [2018-11-28 12:40:08,785 INFO L267 ElimStorePlain]: Start of recursive call 39: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-28 12:40:08,861 INFO L267 ElimStorePlain]: Start of recursive call 38: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-28 12:40:08,929 INFO L267 ElimStorePlain]: Start of recursive call 37: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-28 12:40:09,008 INFO L267 ElimStorePlain]: Start of recursive call 36: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-28 12:40:09,602 INFO L267 ElimStorePlain]: Start of recursive call 20: 2 dim-1 vars, End of recursive call: and 7 xjuncts. [2018-11-28 12:40:10,279 INFO L267 ElimStorePlain]: Start of recursive call 13: 2 dim-1 vars, End of recursive call: and 8 xjuncts. [2018-11-28 12:40:11,074 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 2 select indices, 2 select index equivalence classes, 1 disjoint index pairs (out of 1 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 104 treesize of output 98 [2018-11-28 12:40:11,212 WARN L180 SmtUtils]: Spent 137.00 ms on a formula simplification. DAG size of input: 42 DAG size of output: 40 [2018-11-28 12:40:11,220 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 12:40:11,223 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 12:40:11,227 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 12:40:11,260 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 12:40:11,261 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 4 select indices, 4 select index equivalence classes, 6 disjoint index pairs (out of 6 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 84 treesize of output 103 [2018-11-28 12:40:11,412 WARN L180 SmtUtils]: Spent 150.00 ms on a formula simplification. DAG size of input: 50 DAG size of output: 40 [2018-11-28 12:40:11,437 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 12:40:11,440 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 12:40:11,443 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 12:40:11,447 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 12:40:11,462 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 12:40:11,465 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 12:40:11,469 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 12:40:11,472 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 12:40:11,473 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 6 select indices, 6 select index equivalence classes, 11 disjoint index pairs (out of 15 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 74 treesize of output 114 [2018-11-28 12:40:11,645 WARN L180 SmtUtils]: Spent 171.00 ms on a formula simplification. DAG size of input: 60 DAG size of output: 48 [2018-11-28 12:40:11,665 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 12:40:11,668 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 12:40:11,671 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 12:40:11,683 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 12:40:11,686 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 12:40:11,689 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 12:40:11,692 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 12:40:11,694 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 12:40:11,697 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 12:40:11,700 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 12:40:11,701 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 7 select indices, 7 select index equivalence classes, 17 disjoint index pairs (out of 21 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 62 treesize of output 131 [2018-11-28 12:40:11,866 WARN L180 SmtUtils]: Spent 163.00 ms on a formula simplification. DAG size of input: 71 DAG size of output: 57 [2018-11-28 12:40:11,879 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 12:40:11,881 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 12:40:11,883 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 12:40:11,885 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 12:40:11,893 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 12:40:11,895 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 12:40:11,897 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 12:40:11,899 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 12:40:11,902 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 12:40:11,904 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 12:40:11,906 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 12:40:11,908 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 12:40:11,908 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 8 select indices, 8 select index equivalence classes, 24 disjoint index pairs (out of 28 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 53 treesize of output 153 [2018-11-28 12:40:11,924 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 8 select indices, 8 select index equivalence classes, 24 disjoint index pairs (out of 28 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 58 treesize of output 148 [2018-11-28 12:40:11,950 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 8 select indices, 8 select index equivalence classes, 24 disjoint index pairs (out of 28 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 53 treesize of output 142 [2018-11-28 12:40:11,951 INFO L267 ElimStorePlain]: Start of recursive call 47: End of recursive call: and 1 xjuncts. [2018-11-28 12:40:12,022 INFO L267 ElimStorePlain]: Start of recursive call 46: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-28 12:40:12,092 INFO L267 ElimStorePlain]: Start of recursive call 45: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-28 12:40:12,156 INFO L267 ElimStorePlain]: Start of recursive call 44: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-28 12:40:12,224 INFO L267 ElimStorePlain]: Start of recursive call 43: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-28 12:40:12,291 INFO L267 ElimStorePlain]: Start of recursive call 42: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-28 12:40:12,364 INFO L267 ElimStorePlain]: Start of recursive call 41: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-28 12:40:13,109 INFO L267 ElimStorePlain]: Start of recursive call 12: 2 dim-1 vars, End of recursive call: and 9 xjuncts. [2018-11-28 12:40:13,917 INFO L267 ElimStorePlain]: Start of recursive call 3: 2 dim-1 vars, End of recursive call: and 10 xjuncts. [2018-11-28 12:40:14,731 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 10 xjuncts. [2018-11-28 12:40:15,544 INFO L267 ElimStorePlain]: Start of recursive call 1: 7 dim-0 vars, 1 dim-1 vars, End of recursive call: 63 dim-0 vars, and 10 xjuncts. [2018-11-28 12:40:15,545 INFO L202 ElimStorePlain]: Needed 47 recursive calls to eliminate 8 variables, input treesize:142, output treesize:1452 [2018-11-28 12:40:22,954 WARN L180 SmtUtils]: Spent 7.17 s on a formula simplification. DAG size of input: 656 DAG size of output: 148 [2018-11-28 12:40:26,647 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 12:40:26,658 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 12:40:26,667 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 12:40:26,675 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 12:40:26,681 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 12:40:26,685 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 12:40:26,688 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 12:40:26,692 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 12:40:26,693 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 12:40:26,696 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 12:40:26,697 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 10 select indices, 10 select index equivalence classes, 32 disjoint index pairs (out of 45 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 168 treesize of output 212 [2018-11-28 12:40:26,698 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-11-28 12:40:26,995 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 12:40:26,996 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 12:40:27,002 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 12:40:27,004 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 12:40:27,009 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 12:40:27,010 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 12:40:27,013 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 12:40:27,014 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 12:40:27,015 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 12:40:27,017 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 12:40:27,018 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 12:40:27,019 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 12:40:27,020 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 12:40:27,021 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 12:40:27,023 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 12:40:27,024 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 12:40:27,029 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 12:40:27,040 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 10 select indices, 10 select index equivalence classes, 39 disjoint index pairs (out of 45 index pairs), introduced 0 new quantified variables, introduced 2 case distinctions, treesize of input 168 treesize of output 240 [2018-11-28 12:40:27,042 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 2 xjuncts. [2018-11-28 12:40:27,589 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 2 select indices, 2 select index equivalence classes, 16 disjoint index pairs (out of 1 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 198 treesize of output 195 [2018-11-28 12:40:27,592 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 10 treesize of output 9 [2018-11-28 12:40:27,592 INFO L267 ElimStorePlain]: Start of recursive call 5: End of recursive call: and 1 xjuncts. [2018-11-28 12:40:27,698 INFO L267 ElimStorePlain]: Start of recursive call 4: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-28 12:40:28,164 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 2 select indices, 2 select index equivalence classes, 13 disjoint index pairs (out of 1 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 192 treesize of output 193 [2018-11-28 12:40:28,166 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 10 treesize of output 9 [2018-11-28 12:40:28,167 INFO L267 ElimStorePlain]: Start of recursive call 7: End of recursive call: and 1 xjuncts. [2018-11-28 12:40:28,272 INFO L267 ElimStorePlain]: Start of recursive call 6: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-28 12:40:28,280 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 2 select indices, 2 select index equivalence classes, 15 disjoint index pairs (out of 1 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 194 treesize of output 191 [2018-11-28 12:40:28,283 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 10 treesize of output 9 [2018-11-28 12:40:28,283 INFO L267 ElimStorePlain]: Start of recursive call 9: End of recursive call: and 1 xjuncts. [2018-11-28 12:40:28,386 INFO L267 ElimStorePlain]: Start of recursive call 8: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-28 12:40:28,842 INFO L267 ElimStorePlain]: Start of recursive call 1: 12 dim-0 vars, 2 dim-1 vars, 2 dim-2 vars, End of recursive call: 18 dim-0 vars, and 3 xjuncts. [2018-11-28 12:40:28,843 INFO L202 ElimStorePlain]: Needed 9 recursive calls to eliminate 16 variables, input treesize:337, output treesize:573 [2018-11-28 12:40:32,669 WARN L180 SmtUtils]: Spent 1.46 s on a formula simplification. DAG size of input: 266 DAG size of output: 185 [2018-11-28 12:40:32,683 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 2 select indices, 2 select index equivalence classes, 15 disjoint index pairs (out of 1 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 203 treesize of output 198 [2018-11-28 12:40:32,698 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 2 case distinctions, treesize of input 18 treesize of output 27 [2018-11-28 12:40:32,698 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 2 xjuncts. [2018-11-28 12:40:32,820 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 2 xjuncts. [2018-11-28 12:40:33,292 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 2 select indices, 2 select index equivalence classes, 15 disjoint index pairs (out of 1 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 203 treesize of output 198 [2018-11-28 12:40:33,307 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 2 case distinctions, treesize of input 18 treesize of output 27 [2018-11-28 12:40:33,308 INFO L267 ElimStorePlain]: Start of recursive call 5: End of recursive call: and 2 xjuncts. [2018-11-28 12:40:33,427 INFO L267 ElimStorePlain]: Start of recursive call 4: 1 dim-1 vars, End of recursive call: and 2 xjuncts. [2018-11-28 12:40:34,067 INFO L267 ElimStorePlain]: Start of recursive call 1: 16 dim-0 vars, 2 dim-2 vars, End of recursive call: 24 dim-0 vars, and 4 xjuncts. [2018-11-28 12:40:34,068 INFO L202 ElimStorePlain]: Needed 5 recursive calls to eliminate 18 variables, input treesize:407, output treesize:743 [2018-11-28 12:40:44,062 WARN L180 SmtUtils]: Spent 3.00 s on a formula simplification. DAG size of input: 335 DAG size of output: 179 [2018-11-28 12:40:44,092 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 2 select indices, 2 select index equivalence classes, 15 disjoint index pairs (out of 1 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 194 treesize of output 191 [2018-11-28 12:40:44,095 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 10 treesize of output 9 [2018-11-28 12:40:44,096 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-11-28 12:40:44,223 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-28 12:40:44,503 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 2 select indices, 2 select index equivalence classes, 15 disjoint index pairs (out of 1 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 194 treesize of output 191 [2018-11-28 12:40:44,507 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 10 treesize of output 9 [2018-11-28 12:40:44,507 INFO L267 ElimStorePlain]: Start of recursive call 5: End of recursive call: and 1 xjuncts. [2018-11-28 12:40:44,620 INFO L267 ElimStorePlain]: Start of recursive call 4: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-28 12:40:44,891 INFO L267 ElimStorePlain]: Start of recursive call 1: 16 dim-0 vars, 2 dim-2 vars, End of recursive call: 12 dim-0 vars, and 2 xjuncts. [2018-11-28 12:40:44,891 INFO L202 ElimStorePlain]: Needed 5 recursive calls to eliminate 18 variables, input treesize:389, output treesize:363 [2018-11-28 12:40:44,924 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 2 select indices, 2 select index equivalence classes, 15 disjoint index pairs (out of 1 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 194 treesize of output 191 [2018-11-28 12:40:44,928 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 10 treesize of output 9 [2018-11-28 12:40:44,929 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-11-28 12:40:45,075 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-28 12:40:45,380 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 2 select indices, 2 select index equivalence classes, 15 disjoint index pairs (out of 1 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 194 treesize of output 191 [2018-11-28 12:40:45,384 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 10 treesize of output 9 [2018-11-28 12:40:45,384 INFO L267 ElimStorePlain]: Start of recursive call 5: End of recursive call: and 1 xjuncts. [2018-11-28 12:40:45,489 INFO L267 ElimStorePlain]: Start of recursive call 4: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-28 12:40:45,724 INFO L267 ElimStorePlain]: Start of recursive call 1: 16 dim-0 vars, 2 dim-2 vars, End of recursive call: 12 dim-0 vars, and 2 xjuncts. [2018-11-28 12:40:45,724 INFO L202 ElimStorePlain]: Needed 5 recursive calls to eliminate 18 variables, input treesize:389, output treesize:363 [2018-11-28 12:40:45,746 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 2 select indices, 2 select index equivalence classes, 15 disjoint index pairs (out of 1 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 194 treesize of output 191 [2018-11-28 12:40:45,749 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 10 treesize of output 9 [2018-11-28 12:40:45,749 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-11-28 12:40:45,854 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-28 12:40:46,106 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 2 select indices, 2 select index equivalence classes, 15 disjoint index pairs (out of 1 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 194 treesize of output 191 [2018-11-28 12:40:46,109 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 10 treesize of output 9 [2018-11-28 12:40:46,109 INFO L267 ElimStorePlain]: Start of recursive call 5: End of recursive call: and 1 xjuncts. [2018-11-28 12:40:46,214 INFO L267 ElimStorePlain]: Start of recursive call 4: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-28 12:40:46,450 INFO L267 ElimStorePlain]: Start of recursive call 1: 16 dim-0 vars, 2 dim-2 vars, End of recursive call: 12 dim-0 vars, and 2 xjuncts. [2018-11-28 12:40:46,450 INFO L202 ElimStorePlain]: Needed 5 recursive calls to eliminate 18 variables, input treesize:389, output treesize:363 [2018-11-28 12:40:46,469 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 2 select indices, 2 select index equivalence classes, 15 disjoint index pairs (out of 1 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 194 treesize of output 191 [2018-11-28 12:40:46,472 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 10 treesize of output 9 [2018-11-28 12:40:46,472 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-11-28 12:40:46,577 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-28 12:40:46,830 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 2 select indices, 2 select index equivalence classes, 15 disjoint index pairs (out of 1 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 194 treesize of output 191 [2018-11-28 12:40:46,833 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 10 treesize of output 9 [2018-11-28 12:40:46,833 INFO L267 ElimStorePlain]: Start of recursive call 5: End of recursive call: and 1 xjuncts. [2018-11-28 12:40:46,938 INFO L267 ElimStorePlain]: Start of recursive call 4: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-28 12:40:47,174 INFO L267 ElimStorePlain]: Start of recursive call 1: 16 dim-0 vars, 2 dim-2 vars, End of recursive call: 12 dim-0 vars, and 2 xjuncts. [2018-11-28 12:40:47,175 INFO L202 ElimStorePlain]: Needed 5 recursive calls to eliminate 18 variables, input treesize:389, output treesize:363 [2018-11-28 12:40:47,207 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 2 select indices, 2 select index equivalence classes, 15 disjoint index pairs (out of 1 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 194 treesize of output 191 [2018-11-28 12:40:47,212 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 10 treesize of output 9 [2018-11-28 12:40:47,212 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-11-28 12:40:47,322 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-28 12:40:47,576 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 2 select indices, 2 select index equivalence classes, 15 disjoint index pairs (out of 1 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 194 treesize of output 191 [2018-11-28 12:40:47,579 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 10 treesize of output 9 [2018-11-28 12:40:47,579 INFO L267 ElimStorePlain]: Start of recursive call 5: End of recursive call: and 1 xjuncts. [2018-11-28 12:40:47,685 INFO L267 ElimStorePlain]: Start of recursive call 4: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-28 12:40:47,920 INFO L267 ElimStorePlain]: Start of recursive call 1: 16 dim-0 vars, 2 dim-2 vars, End of recursive call: 12 dim-0 vars, and 2 xjuncts. [2018-11-28 12:40:47,920 INFO L202 ElimStorePlain]: Needed 5 recursive calls to eliminate 18 variables, input treesize:389, output treesize:363 [2018-11-28 12:40:47,943 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 2 select indices, 2 select index equivalence classes, 15 disjoint index pairs (out of 1 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 194 treesize of output 191 [2018-11-28 12:40:47,947 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 10 treesize of output 9 [2018-11-28 12:40:47,947 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-11-28 12:40:48,052 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-28 12:40:48,313 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 2 select indices, 2 select index equivalence classes, 15 disjoint index pairs (out of 1 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 194 treesize of output 191 [2018-11-28 12:40:48,316 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 10 treesize of output 9 [2018-11-28 12:40:48,316 INFO L267 ElimStorePlain]: Start of recursive call 5: End of recursive call: and 1 xjuncts. [2018-11-28 12:40:48,422 INFO L267 ElimStorePlain]: Start of recursive call 4: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-28 12:40:48,668 INFO L267 ElimStorePlain]: Start of recursive call 1: 16 dim-0 vars, 2 dim-2 vars, End of recursive call: 12 dim-0 vars, and 2 xjuncts. [2018-11-28 12:40:48,669 INFO L202 ElimStorePlain]: Needed 5 recursive calls to eliminate 18 variables, input treesize:389, output treesize:363 [2018-11-28 12:40:48,691 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 2 select indices, 2 select index equivalence classes, 15 disjoint index pairs (out of 1 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 194 treesize of output 191 [2018-11-28 12:40:48,694 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 10 treesize of output 9 [2018-11-28 12:40:48,694 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-11-28 12:40:48,800 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-28 12:40:49,050 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 2 select indices, 2 select index equivalence classes, 15 disjoint index pairs (out of 1 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 194 treesize of output 191 [2018-11-28 12:40:49,053 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 10 treesize of output 9 [2018-11-28 12:40:49,054 INFO L267 ElimStorePlain]: Start of recursive call 5: End of recursive call: and 1 xjuncts. [2018-11-28 12:40:49,158 INFO L267 ElimStorePlain]: Start of recursive call 4: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-28 12:40:49,393 INFO L267 ElimStorePlain]: Start of recursive call 1: 16 dim-0 vars, 2 dim-2 vars, End of recursive call: 12 dim-0 vars, and 2 xjuncts. [2018-11-28 12:40:49,393 INFO L202 ElimStorePlain]: Needed 5 recursive calls to eliminate 18 variables, input treesize:389, output treesize:363 [2018-11-28 12:40:49,414 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 2 select indices, 2 select index equivalence classes, 15 disjoint index pairs (out of 1 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 194 treesize of output 191 [2018-11-28 12:40:49,417 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 10 treesize of output 9 [2018-11-28 12:40:49,417 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-11-28 12:40:49,522 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-28 12:40:49,775 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 2 select indices, 2 select index equivalence classes, 15 disjoint index pairs (out of 1 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 194 treesize of output 191 [2018-11-28 12:40:49,778 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 10 treesize of output 9 [2018-11-28 12:40:49,778 INFO L267 ElimStorePlain]: Start of recursive call 5: End of recursive call: and 1 xjuncts. [2018-11-28 12:40:49,883 INFO L267 ElimStorePlain]: Start of recursive call 4: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-28 12:40:50,117 INFO L267 ElimStorePlain]: Start of recursive call 1: 16 dim-0 vars, 2 dim-2 vars, End of recursive call: 12 dim-0 vars, and 2 xjuncts. [2018-11-28 12:40:50,118 INFO L202 ElimStorePlain]: Needed 5 recursive calls to eliminate 18 variables, input treesize:389, output treesize:363 [2018-11-28 12:40:50,146 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 2 select indices, 2 select index equivalence classes, 15 disjoint index pairs (out of 1 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 194 treesize of output 191 [2018-11-28 12:40:50,151 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 10 treesize of output 9 [2018-11-28 12:40:50,151 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-11-28 12:40:50,268 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-28 12:40:50,517 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 2 select indices, 2 select index equivalence classes, 15 disjoint index pairs (out of 1 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 194 treesize of output 191 [2018-11-28 12:40:50,520 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 10 treesize of output 9 [2018-11-28 12:40:50,520 INFO L267 ElimStorePlain]: Start of recursive call 5: End of recursive call: and 1 xjuncts. [2018-11-28 12:40:50,626 INFO L267 ElimStorePlain]: Start of recursive call 4: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-28 12:40:50,859 INFO L267 ElimStorePlain]: Start of recursive call 1: 20 dim-0 vars, 2 dim-2 vars, End of recursive call: 14 dim-0 vars, and 2 xjuncts. [2018-11-28 12:40:50,859 INFO L202 ElimStorePlain]: Needed 5 recursive calls to eliminate 22 variables, input treesize:389, output treesize:363 [2018-11-28 12:41:01,927 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 2 select indices, 2 select index equivalence classes, 12 disjoint index pairs (out of 1 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 198 treesize of output 195 [2018-11-28 12:41:01,932 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 8 treesize of output 7 [2018-11-28 12:41:01,932 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-11-28 12:41:02,065 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-28 12:41:02,338 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 2 select indices, 2 select index equivalence classes, 12 disjoint index pairs (out of 1 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 198 treesize of output 195 [2018-11-28 12:41:02,341 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 8 treesize of output 7 [2018-11-28 12:41:02,341 INFO L267 ElimStorePlain]: Start of recursive call 5: End of recursive call: and 1 xjuncts. [2018-11-28 12:41:02,456 INFO L267 ElimStorePlain]: Start of recursive call 4: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-28 12:41:02,699 INFO L267 ElimStorePlain]: Start of recursive call 1: 20 dim-0 vars, 2 dim-2 vars, End of recursive call: 16 dim-0 vars, and 2 xjuncts. [2018-11-28 12:41:02,699 INFO L202 ElimStorePlain]: Needed 5 recursive calls to eliminate 22 variables, input treesize:397, output treesize:375 [2018-11-28 12:41:02,959 WARN L180 SmtUtils]: Spent 130.00 ms on a formula simplification that was a NOOP. DAG size: 195 [2018-11-28 12:41:02,979 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 12:41:02,982 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 12:41:02,989 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 12:41:02,994 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 12:41:02,999 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 12:41:03,004 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 12:41:03,009 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 12:41:03,010 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 12:41:03,011 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 12:41:03,013 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 12:41:03,020 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 12:41:03,021 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 11 select indices, 11 select index equivalence classes, 41 disjoint index pairs (out of 55 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 198 treesize of output 282 [2018-11-28 12:41:03,021 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-11-28 12:41:03,399 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 12:41:03,400 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 12:41:03,405 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 12:41:03,408 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 12:41:03,411 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 12:41:03,414 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 12:41:03,415 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 12:41:03,418 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 12:41:03,419 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 12:41:03,421 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 12:41:03,422 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 12:41:03,423 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 12:41:03,424 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 12:41:03,426 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 12:41:03,429 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 12:41:03,430 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 12:41:03,431 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 12:41:03,433 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 12:41:03,436 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 12:41:03,451 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 11 select indices, 11 select index equivalence classes, 49 disjoint index pairs (out of 55 index pairs), introduced 0 new quantified variables, introduced 2 case distinctions, treesize of input 198 treesize of output 294 [2018-11-28 12:41:03,452 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 2 xjuncts. [2018-11-28 12:41:04,145 INFO L267 ElimStorePlain]: Start of recursive call 1: 16 dim-0 vars, 2 dim-1 vars, End of recursive call: 24 dim-0 vars, and 3 xjuncts. [2018-11-28 12:41:04,146 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 18 variables, input treesize:397, output treesize:687 [2018-11-28 12:41:05,007 WARN L194 Executor]: External (z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000) stderr output: (error "out of memory") [2018-11-28 12:41:05,208 WARN L521 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 15 z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-28 12:41:05,209 FATAL L265 ToolchainWalker]: An unrecoverable error occured during an interaction with an SMT solver: de.uni_freiburg.informatik.ultimate.logic.SMTLIBException: External (z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000)Received EOF on stdin. stderr output: (error "out of memory") at de.uni_freiburg.informatik.ultimate.smtsolver.external.Executor.parse(Executor.java:208) at de.uni_freiburg.informatik.ultimate.smtsolver.external.Executor.parseCheckSatResult(Executor.java:225) at de.uni_freiburg.informatik.ultimate.smtsolver.external.Scriptor.checkSat(Scriptor.java:155) at de.uni_freiburg.informatik.ultimate.modelcheckerutils.smt.WrapperScript.checkSat(WrapperScript.java:116) at de.uni_freiburg.informatik.ultimate.modelcheckerutils.smt.managedscript.ManagedScript.checkSat(ManagedScript.java:141) at de.uni_freiburg.informatik.ultimate.modelcheckerutils.smt.MonolithicImplicationChecker.checkImplication(MonolithicImplicationChecker.java:84) at de.uni_freiburg.informatik.ultimate.modelcheckerutils.smt.predicates.PredicateUnifier$PredicateComparison.compare(PredicateUnifier.java:893) at de.uni_freiburg.informatik.ultimate.modelcheckerutils.smt.predicates.PredicateUnifier$PredicateComparison.(PredicateUnifier.java:767) at de.uni_freiburg.informatik.ultimate.modelcheckerutils.smt.predicates.PredicateUnifier.getOrConstructPredicate(PredicateUnifier.java:339) at de.uni_freiburg.informatik.ultimate.modelcheckerutils.smt.predicates.PredicateUnifier.getOrConstructPredicate(PredicateUnifier.java:299) at de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.singletracecheck.TraceCheckSpWp$UnifyPostprocessor.postprocess(TraceCheckSpWp.java:575) at de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.predicates.IterativePredicateTransformer.applyPostprocessors(IterativePredicateTransformer.java:439) at de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.predicates.IterativePredicateTransformer.computeStrongestPostconditionSequence(IterativePredicateTransformer.java:200) at de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.singletracecheck.TraceCheckSpWp.computeInterpolantsUsingUnsatCore(TraceCheckSpWp.java:286) at de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.singletracecheck.TraceCheckSpWp.computeInterpolants(TraceCheckSpWp.java:175) at de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.singletracecheck.TraceCheckSpWp.(TraceCheckSpWp.java:162) at de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.tracehandling.TraceCheckConstructor.constructForwardBackward(TraceCheckConstructor.java:224) at de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.tracehandling.TraceCheckConstructor.constructTraceCheck(TraceCheckConstructor.java:188) at de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.tracehandling.TraceCheckConstructor.get(TraceCheckConstructor.java:165) at de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.tracehandling.MultiTrackRefinementStrategy.getTraceCheck(MultiTrackRefinementStrategy.java:232) at de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.tracehandling.BaseRefinementStrategy.checkFeasibility(BaseRefinementStrategy.java:223) at de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.tracehandling.BaseRefinementStrategy.executeStrategy(BaseRefinementStrategy.java:197) at de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.tracehandling.TraceAbstractionRefinementEngine.(TraceAbstractionRefinementEngine.java:70) at de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.BasicCegarLoop.isCounterexampleFeasible(BasicCegarLoop.java:456) at de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.AbstractCegarLoop.iterateInternal(AbstractCegarLoop.java:434) at de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.AbstractCegarLoop.iterate(AbstractCegarLoop.java:376) at de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionStarter.iterate(TraceAbstractionStarter.java:334) at de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionStarter.runCegarLoops(TraceAbstractionStarter.java:174) at de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionStarter.(TraceAbstractionStarter.java:126) at de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver.finish(TraceAbstractionObserver.java:123) at de.uni_freiburg.informatik.ultimate.core.coreplugin.PluginConnector.runObserver(PluginConnector.java:168) at de.uni_freiburg.informatik.ultimate.core.coreplugin.PluginConnector.runTool(PluginConnector.java:151) at de.uni_freiburg.informatik.ultimate.core.coreplugin.PluginConnector.run(PluginConnector.java:128) at de.uni_freiburg.informatik.ultimate.core.coreplugin.ToolchainWalker.executePluginConnector(ToolchainWalker.java:232) at de.uni_freiburg.informatik.ultimate.core.coreplugin.ToolchainWalker.processPlugin(ToolchainWalker.java:226) at de.uni_freiburg.informatik.ultimate.core.coreplugin.ToolchainWalker.walkUnprotected(ToolchainWalker.java:142) at de.uni_freiburg.informatik.ultimate.core.coreplugin.ToolchainWalker.walk(ToolchainWalker.java:104) at de.uni_freiburg.informatik.ultimate.core.coreplugin.ToolchainManager$Toolchain.processToolchain(ToolchainManager.java:316) at de.uni_freiburg.informatik.ultimate.core.coreplugin.toolchain.DefaultToolchainJob.run(DefaultToolchainJob.java:145) at org.eclipse.core.internal.jobs.Worker.run(Worker.java:55) Caused by: de.uni_freiburg.informatik.ultimate.logic.SMTLIBException: EOF at de.uni_freiburg.informatik.ultimate.smtsolver.external.Parser$Action$.CUP$do_action(Parser.java:1427) at de.uni_freiburg.informatik.ultimate.smtsolver.external.Parser.do_action(Parser.java:630) at com.github.jhoenicke.javacup.runtime.LRParser.parse(LRParser.java:419) at de.uni_freiburg.informatik.ultimate.smtsolver.external.Executor.parse(Executor.java:205) ... 39 more [2018-11-28 12:41:05,211 INFO L168 Benchmark]: Toolchain (without parser) took 156435.23 ms. Allocated memory was 1.0 GB in the beginning and 1.5 GB in the end (delta: 508.0 MB). Free memory was 949.5 MB in the beginning and 847.1 MB in the end (delta: 102.5 MB). Peak memory consumption was 610.5 MB. Max. memory is 11.5 GB. [2018-11-28 12:41:05,212 INFO L168 Benchmark]: CDTParser took 0.16 ms. Allocated memory is still 1.0 GB. Free memory is still 979.6 MB. There was no memory consumed. Max. memory is 11.5 GB. [2018-11-28 12:41:05,212 INFO L168 Benchmark]: CACSL2BoogieTranslator took 713.76 ms. Allocated memory was 1.0 GB in the beginning and 1.2 GB in the end (delta: 121.6 MB). Free memory was 949.5 MB in the beginning and 1.0 GB in the end (delta: -81.6 MB). Peak memory consumption was 54.0 MB. Max. memory is 11.5 GB. [2018-11-28 12:41:05,212 INFO L168 Benchmark]: Boogie Procedure Inliner took 39.56 ms. Allocated memory is still 1.2 GB. Free memory was 1.0 GB in the beginning and 1.0 GB in the end (delta: 3.3 MB). Peak memory consumption was 3.3 MB. Max. memory is 11.5 GB. [2018-11-28 12:41:05,212 INFO L168 Benchmark]: Boogie Preprocessor took 61.05 ms. Allocated memory is still 1.2 GB. Free memory was 1.0 GB in the beginning and 1.0 GB in the end (delta: 6.7 MB). Peak memory consumption was 6.7 MB. Max. memory is 11.5 GB. [2018-11-28 12:41:05,212 INFO L168 Benchmark]: RCFGBuilder took 888.84 ms. Allocated memory is still 1.2 GB. Free memory was 1.0 GB in the beginning and 927.2 MB in the end (delta: 93.9 MB). Peak memory consumption was 93.9 MB. Max. memory is 11.5 GB. [2018-11-28 12:41:05,212 INFO L168 Benchmark]: TraceAbstraction took 154728.26 ms. Allocated memory was 1.2 GB in the beginning and 1.5 GB in the end (delta: 386.4 MB). Free memory was 927.2 MB in the beginning and 847.1 MB in the end (delta: 80.1 MB). Peak memory consumption was 466.5 MB. Max. memory is 11.5 GB. [2018-11-28 12:41:05,213 INFO L336 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.16 ms. Allocated memory is still 1.0 GB. Free memory is still 979.6 MB. There was no memory consumed. Max. memory is 11.5 GB. * CACSL2BoogieTranslator took 713.76 ms. Allocated memory was 1.0 GB in the beginning and 1.2 GB in the end (delta: 121.6 MB). Free memory was 949.5 MB in the beginning and 1.0 GB in the end (delta: -81.6 MB). Peak memory consumption was 54.0 MB. Max. memory is 11.5 GB. * Boogie Procedure Inliner took 39.56 ms. Allocated memory is still 1.2 GB. Free memory was 1.0 GB in the beginning and 1.0 GB in the end (delta: 3.3 MB). Peak memory consumption was 3.3 MB. Max. memory is 11.5 GB. * Boogie Preprocessor took 61.05 ms. Allocated memory is still 1.2 GB. Free memory was 1.0 GB in the beginning and 1.0 GB in the end (delta: 6.7 MB). Peak memory consumption was 6.7 MB. Max. memory is 11.5 GB. * RCFGBuilder took 888.84 ms. Allocated memory is still 1.2 GB. Free memory was 1.0 GB in the beginning and 927.2 MB in the end (delta: 93.9 MB). Peak memory consumption was 93.9 MB. Max. memory is 11.5 GB. * TraceAbstraction took 154728.26 ms. Allocated memory was 1.2 GB in the beginning and 1.5 GB in the end (delta: 386.4 MB). Free memory was 927.2 MB in the beginning and 847.1 MB in the end (delta: 80.1 MB). Peak memory consumption was 466.5 MB. Max. memory is 11.5 GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - ExceptionOrErrorResult: SMTLIBException: External (z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000)Received EOF on stdin. stderr output: (error "out of memory") de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: SMTLIBException: External (z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000)Received EOF on stdin. stderr output: (error "out of memory") : de.uni_freiburg.informatik.ultimate.smtsolver.external.Executor.parse(Executor.java:208) RESULT: Ultimate could not prove your program: Toolchain returned no result. Received shutdown request...