./Ultimate.py --spec ../../sv-benchmarks/c/properties/no-overflow.prp --file ../../sv-benchmarks/c/busybox-1.22.0/dirname_true-no-overflow_true-valid-memsafety.i --full-output --architecture 64bit -------------------------------------------------------------------------------- Checking for overflows Using default analysis Version 0cd3be1d Calling Ultimate with: java -Dosgi.configuration.area=/tmp/vcloud-vcloud-master/worker/working_dir_b218a3f8-accd-4719-941b-ce9fe174b24c/bin-2019/uautomizer/data/config -Xmx12G -Xms1G -jar /tmp/vcloud-vcloud-master/worker/working_dir_b218a3f8-accd-4719-941b-ce9fe174b24c/bin-2019/uautomizer/plugins/org.eclipse.equinox.launcher_1.3.100.v20150511-1540.jar -data @noDefault -ultimatedata /tmp/vcloud-vcloud-master/worker/working_dir_b218a3f8-accd-4719-941b-ce9fe174b24c/bin-2019/uautomizer/data -tc /tmp/vcloud-vcloud-master/worker/working_dir_b218a3f8-accd-4719-941b-ce9fe174b24c/bin-2019/uautomizer/config/AutomizerReach.xml -i ../../sv-benchmarks/c/busybox-1.22.0/dirname_true-no-overflow_true-valid-memsafety.i -s /tmp/vcloud-vcloud-master/worker/working_dir_b218a3f8-accd-4719-941b-ce9fe174b24c/bin-2019/uautomizer/config/svcomp-Overflow-64bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud-vcloud-master/worker/working_dir_b218a3f8-accd-4719-941b-ce9fe174b24c/bin-2019/uautomizer --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(G ! overflow) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 64bit --witnessprinter.graph.data.programhash eb1520ccd16a6dcbfeb7912e1d04b4742bbea576 ............................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................... Execution finished normally Using bit-precise analysis No suitable file found in config dir /tmp/vcloud-vcloud-master/worker/working_dir_b218a3f8-accd-4719-941b-ce9fe174b24c/bin-2019/uautomizer/config using search string *Overflow*64bit*_Bitvector*.epf No suitable settings file found using Overflow*64bit*_Bitvector ERROR: UNSUPPORTED PROPERTY Writing output log to file Ultimate.log Result: ERROR: ExceptionOrErrorResult: SMTLIBException: External (z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000)Received EOF on stdin. stderr output: (error "out of memory") --- Real Ultimate output --- This is Ultimate 0.1.23-0cd3be1 [2018-11-28 13:06:44,539 INFO L170 SettingsManager]: Resetting all preferences to default values... [2018-11-28 13:06:44,541 INFO L174 SettingsManager]: Resetting UltimateCore preferences to default values [2018-11-28 13:06:44,548 INFO L177 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2018-11-28 13:06:44,548 INFO L174 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2018-11-28 13:06:44,548 INFO L174 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2018-11-28 13:06:44,549 INFO L174 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2018-11-28 13:06:44,550 INFO L174 SettingsManager]: Resetting LassoRanker preferences to default values [2018-11-28 13:06:44,551 INFO L174 SettingsManager]: Resetting Reaching Definitions preferences to default values [2018-11-28 13:06:44,551 INFO L174 SettingsManager]: Resetting SyntaxChecker preferences to default values [2018-11-28 13:06:44,552 INFO L177 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2018-11-28 13:06:44,552 INFO L174 SettingsManager]: Resetting LTL2Aut preferences to default values [2018-11-28 13:06:44,553 INFO L174 SettingsManager]: Resetting PEA to Boogie preferences to default values [2018-11-28 13:06:44,554 INFO L174 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2018-11-28 13:06:44,554 INFO L174 SettingsManager]: Resetting ChcToBoogie preferences to default values [2018-11-28 13:06:44,555 INFO L174 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2018-11-28 13:06:44,555 INFO L174 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2018-11-28 13:06:44,556 INFO L174 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2018-11-28 13:06:44,558 INFO L174 SettingsManager]: Resetting CodeCheck preferences to default values [2018-11-28 13:06:44,559 INFO L174 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2018-11-28 13:06:44,560 INFO L174 SettingsManager]: Resetting RCFGBuilder preferences to default values [2018-11-28 13:06:44,560 INFO L174 SettingsManager]: Resetting TraceAbstraction preferences to default values [2018-11-28 13:06:44,562 INFO L177 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2018-11-28 13:06:44,562 INFO L177 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2018-11-28 13:06:44,562 INFO L174 SettingsManager]: Resetting TreeAutomizer preferences to default values [2018-11-28 13:06:44,563 INFO L174 SettingsManager]: Resetting IcfgTransformer preferences to default values [2018-11-28 13:06:44,564 INFO L174 SettingsManager]: Resetting Boogie Printer preferences to default values [2018-11-28 13:06:44,564 INFO L174 SettingsManager]: Resetting ReqPrinter preferences to default values [2018-11-28 13:06:44,565 INFO L174 SettingsManager]: Resetting Witness Printer preferences to default values [2018-11-28 13:06:44,566 INFO L177 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2018-11-28 13:06:44,566 INFO L174 SettingsManager]: Resetting CDTParser preferences to default values [2018-11-28 13:06:44,566 INFO L177 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2018-11-28 13:06:44,566 INFO L177 SettingsManager]: ReqParser provides no preferences, ignoring... [2018-11-28 13:06:44,567 INFO L174 SettingsManager]: Resetting SmtParser preferences to default values [2018-11-28 13:06:44,567 INFO L174 SettingsManager]: Resetting Witness Parser preferences to default values [2018-11-28 13:06:44,568 INFO L181 SettingsManager]: Finished resetting all preferences to default values... [2018-11-28 13:06:44,568 INFO L98 SettingsManager]: Beginning loading settings from /tmp/vcloud-vcloud-master/worker/working_dir_b218a3f8-accd-4719-941b-ce9fe174b24c/bin-2019/uautomizer/config/svcomp-Overflow-64bit-Automizer_Default.epf [2018-11-28 13:06:44,577 INFO L110 SettingsManager]: Loading preferences was successful [2018-11-28 13:06:44,578 INFO L112 SettingsManager]: Preferences different from defaults after loading the file: [2018-11-28 13:06:44,578 INFO L131 SettingsManager]: Preferences of Boogie Procedure Inliner differ from their defaults: [2018-11-28 13:06:44,578 INFO L133 SettingsManager]: * ... calls to implemented procedures=ONLY_FOR_CONCURRENT_PROGRAMS [2018-11-28 13:06:44,579 INFO L131 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2018-11-28 13:06:44,579 INFO L133 SettingsManager]: * Create parallel compositions if possible=false [2018-11-28 13:06:44,579 INFO L133 SettingsManager]: * Use SBE=true [2018-11-28 13:06:44,579 INFO L131 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2018-11-28 13:06:44,579 INFO L133 SettingsManager]: * Check unreachability of error function in SV-COMP mode=false [2018-11-28 13:06:44,579 INFO L133 SettingsManager]: * Overapproximate operations on floating types=true [2018-11-28 13:06:44,580 INFO L133 SettingsManager]: * Check division by zero=IGNORE [2018-11-28 13:06:44,580 INFO L133 SettingsManager]: * Pointer to allocated memory at dereference=IGNORE [2018-11-28 13:06:44,580 INFO L133 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=IGNORE [2018-11-28 13:06:44,580 INFO L133 SettingsManager]: * Check array bounds for arrays that are off heap=IGNORE [2018-11-28 13:06:44,580 INFO L133 SettingsManager]: * Check absence of signed integer overflows=true [2018-11-28 13:06:44,580 INFO L133 SettingsManager]: * Check if freed pointer was valid=false [2018-11-28 13:06:44,580 INFO L133 SettingsManager]: * Use constant arrays=true [2018-11-28 13:06:44,580 INFO L133 SettingsManager]: * Pointer base address is valid at dereference=IGNORE [2018-11-28 13:06:44,580 INFO L131 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2018-11-28 13:06:44,580 INFO L133 SettingsManager]: * Size of a code block=SequenceOfStatements [2018-11-28 13:06:44,580 INFO L133 SettingsManager]: * To the following directory=./dump/ [2018-11-28 13:06:44,580 INFO L133 SettingsManager]: * SMT solver=External_DefaultMode [2018-11-28 13:06:44,581 INFO L133 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2018-11-28 13:06:44,581 INFO L131 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2018-11-28 13:06:44,581 INFO L133 SettingsManager]: * Compute Interpolants along a Counterexample=FPandBP [2018-11-28 13:06:44,581 INFO L133 SettingsManager]: * Positions where we compute the Hoare Annotation=LoopsAndPotentialCycles [2018-11-28 13:06:44,581 INFO L133 SettingsManager]: * Trace refinement strategy=CAMEL [2018-11-28 13:06:44,581 INFO L133 SettingsManager]: * SMT solver=External_ModelsAndUnsatCoreMode [2018-11-28 13:06:44,581 INFO L133 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in [2018-11-28 13:06:44,581 INFO L133 SettingsManager]: * Compute Hoare Annotation of negated interpolant automaton, abstraction and CFG=true Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud-vcloud-master/worker/working_dir_b218a3f8-accd-4719-941b-ce9fe174b24c/bin-2019/uautomizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(G ! overflow) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 64bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> eb1520ccd16a6dcbfeb7912e1d04b4742bbea576 [2018-11-28 13:06:44,605 INFO L81 nceAwareModelManager]: Repository-Root is: /tmp [2018-11-28 13:06:44,613 INFO L258 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2018-11-28 13:06:44,615 INFO L214 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2018-11-28 13:06:44,616 INFO L271 PluginConnector]: Initializing CDTParser... [2018-11-28 13:06:44,616 INFO L276 PluginConnector]: CDTParser initialized [2018-11-28 13:06:44,617 INFO L418 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud-vcloud-master/worker/working_dir_b218a3f8-accd-4719-941b-ce9fe174b24c/bin-2019/uautomizer/../../sv-benchmarks/c/busybox-1.22.0/dirname_true-no-overflow_true-valid-memsafety.i [2018-11-28 13:06:44,654 INFO L221 CDTParser]: Created temporary CDT project at /tmp/vcloud-vcloud-master/worker/working_dir_b218a3f8-accd-4719-941b-ce9fe174b24c/bin-2019/uautomizer/data/62a4b3d1d/eff3bc15aa99447faa3c4856342c536a/FLAG9e8ca472f [2018-11-28 13:06:45,121 INFO L307 CDTParser]: Found 1 translation units. [2018-11-28 13:06:45,124 INFO L161 CDTParser]: Scanning /tmp/vcloud-vcloud-master/worker/working_dir_b218a3f8-accd-4719-941b-ce9fe174b24c/sv-benchmarks/c/busybox-1.22.0/dirname_true-no-overflow_true-valid-memsafety.i [2018-11-28 13:06:45,137 INFO L355 CDTParser]: About to delete temporary CDT project at /tmp/vcloud-vcloud-master/worker/working_dir_b218a3f8-accd-4719-941b-ce9fe174b24c/bin-2019/uautomizer/data/62a4b3d1d/eff3bc15aa99447faa3c4856342c536a/FLAG9e8ca472f [2018-11-28 13:06:45,632 INFO L363 CDTParser]: Successfully deleted /tmp/vcloud-vcloud-master/worker/working_dir_b218a3f8-accd-4719-941b-ce9fe174b24c/bin-2019/uautomizer/data/62a4b3d1d/eff3bc15aa99447faa3c4856342c536a [2018-11-28 13:06:45,634 INFO L296 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2018-11-28 13:06:45,635 INFO L131 ToolchainWalker]: Walking toolchain with 6 elements. [2018-11-28 13:06:45,636 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2018-11-28 13:06:45,636 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2018-11-28 13:06:45,639 INFO L276 PluginConnector]: CACSL2BoogieTranslator initialized [2018-11-28 13:06:45,639 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 28.11 01:06:45" (1/1) ... [2018-11-28 13:06:45,642 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@7cb69a7f and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 01:06:45, skipping insertion in model container [2018-11-28 13:06:45,642 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 28.11 01:06:45" (1/1) ... [2018-11-28 13:06:45,647 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2018-11-28 13:06:45,685 INFO L176 MainTranslator]: Built tables and reachable declarations [2018-11-28 13:06:46,151 INFO L203 PostProcessor]: Analyzing one entry point: main [2018-11-28 13:06:46,172 INFO L191 MainTranslator]: Completed pre-run [2018-11-28 13:06:46,230 INFO L203 PostProcessor]: Analyzing one entry point: main [2018-11-28 13:06:46,381 INFO L195 MainTranslator]: Completed translation [2018-11-28 13:06:46,381 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 01:06:46 WrapperNode [2018-11-28 13:06:46,381 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2018-11-28 13:06:46,383 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2018-11-28 13:06:46,383 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2018-11-28 13:06:46,383 INFO L276 PluginConnector]: Boogie Procedure Inliner initialized [2018-11-28 13:06:46,390 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 01:06:46" (1/1) ... [2018-11-28 13:06:46,413 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 01:06:46" (1/1) ... [2018-11-28 13:06:46,423 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2018-11-28 13:06:46,424 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2018-11-28 13:06:46,424 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2018-11-28 13:06:46,424 INFO L276 PluginConnector]: Boogie Preprocessor initialized [2018-11-28 13:06:46,432 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 01:06:46" (1/1) ... [2018-11-28 13:06:46,432 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 01:06:46" (1/1) ... [2018-11-28 13:06:46,438 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 01:06:46" (1/1) ... [2018-11-28 13:06:46,438 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 01:06:46" (1/1) ... [2018-11-28 13:06:46,464 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 01:06:46" (1/1) ... [2018-11-28 13:06:46,470 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 01:06:46" (1/1) ... [2018-11-28 13:06:46,473 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 01:06:46" (1/1) ... [2018-11-28 13:06:46,478 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2018-11-28 13:06:46,478 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2018-11-28 13:06:46,478 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2018-11-28 13:06:46,478 INFO L276 PluginConnector]: RCFGBuilder initialized [2018-11-28 13:06:46,479 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 01:06:46" (1/1) ... No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_b218a3f8-accd-4719-941b-ce9fe174b24c/bin-2019/uautomizer/z3 Starting monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2018-11-28 13:06:46,525 INFO L130 BoogieDeclarations]: Found specification of procedure __main [2018-11-28 13:06:46,526 INFO L138 BoogieDeclarations]: Found implementation of procedure __main [2018-11-28 13:06:46,526 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.init [2018-11-28 13:06:46,526 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.init [2018-11-28 13:06:46,526 INFO L130 BoogieDeclarations]: Found specification of procedure read~$Pointer$ [2018-11-28 13:06:46,526 INFO L130 BoogieDeclarations]: Found specification of procedure fflush_all [2018-11-28 13:06:46,526 INFO L138 BoogieDeclarations]: Found implementation of procedure fflush_all [2018-11-28 13:06:46,526 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.dealloc [2018-11-28 13:06:46,526 INFO L130 BoogieDeclarations]: Found specification of procedure single_argv [2018-11-28 13:06:46,526 INFO L138 BoogieDeclarations]: Found implementation of procedure single_argv [2018-11-28 13:06:46,527 INFO L130 BoogieDeclarations]: Found specification of procedure bb_show_usage [2018-11-28 13:06:46,527 INFO L138 BoogieDeclarations]: Found implementation of procedure bb_show_usage [2018-11-28 13:06:46,527 INFO L130 BoogieDeclarations]: Found specification of procedure dirname [2018-11-28 13:06:46,527 INFO L138 BoogieDeclarations]: Found implementation of procedure dirname [2018-11-28 13:06:46,527 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.alloc [2018-11-28 13:06:46,527 INFO L130 BoogieDeclarations]: Found specification of procedure read~int [2018-11-28 13:06:46,527 INFO L130 BoogieDeclarations]: Found specification of procedure write~int [2018-11-28 13:06:46,527 INFO L130 BoogieDeclarations]: Found specification of procedure puts [2018-11-28 13:06:46,527 INFO L130 BoogieDeclarations]: Found specification of procedure fflush [2018-11-28 13:06:46,527 INFO L130 BoogieDeclarations]: Found specification of procedure main [2018-11-28 13:06:46,528 INFO L138 BoogieDeclarations]: Found implementation of procedure main [2018-11-28 13:06:46,528 INFO L130 BoogieDeclarations]: Found specification of procedure write~$Pointer$ [2018-11-28 13:06:46,528 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int [2018-11-28 13:06:46,528 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2018-11-28 13:06:46,528 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2018-11-28 13:06:47,218 INFO L275 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2018-11-28 13:06:47,218 INFO L280 CfgBuilder]: Removed 6 assue(true) statements. [2018-11-28 13:06:47,218 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 28.11 01:06:47 BoogieIcfgContainer [2018-11-28 13:06:47,218 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2018-11-28 13:06:47,219 INFO L113 PluginConnector]: ------------------------TraceAbstraction---------------------------- [2018-11-28 13:06:47,219 INFO L271 PluginConnector]: Initializing TraceAbstraction... [2018-11-28 13:06:47,222 INFO L276 PluginConnector]: TraceAbstraction initialized [2018-11-28 13:06:47,222 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "CDTParser AST 28.11 01:06:45" (1/3) ... [2018-11-28 13:06:47,223 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@5fc0000d and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 28.11 01:06:47, skipping insertion in model container [2018-11-28 13:06:47,223 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 01:06:46" (2/3) ... [2018-11-28 13:06:47,223 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@5fc0000d and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 28.11 01:06:47, skipping insertion in model container [2018-11-28 13:06:47,224 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 28.11 01:06:47" (3/3) ... [2018-11-28 13:06:47,225 INFO L112 eAbstractionObserver]: Analyzing ICFG dirname_true-no-overflow_true-valid-memsafety.i [2018-11-28 13:06:47,234 INFO L156 ceAbstractionStarter]: Automizer settings: Hoare:true NWA Interpolation:FPandBP Determinization: PREDICATE_ABSTRACTION [2018-11-28 13:06:47,241 INFO L168 ceAbstractionStarter]: Appying trace abstraction to program that has 28 error locations. [2018-11-28 13:06:47,256 INFO L257 AbstractCegarLoop]: Starting to check reachability of 28 error locations. [2018-11-28 13:06:47,283 INFO L133 ementStrategyFactory]: Using default assertion order modulation [2018-11-28 13:06:47,283 INFO L382 AbstractCegarLoop]: Interprodecural is true [2018-11-28 13:06:47,283 INFO L383 AbstractCegarLoop]: Hoare is true [2018-11-28 13:06:47,284 INFO L384 AbstractCegarLoop]: Compute interpolants for FPandBP [2018-11-28 13:06:47,284 INFO L385 AbstractCegarLoop]: Backedges is STRAIGHT_LINE [2018-11-28 13:06:47,284 INFO L386 AbstractCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2018-11-28 13:06:47,284 INFO L387 AbstractCegarLoop]: Difference is false [2018-11-28 13:06:47,284 INFO L388 AbstractCegarLoop]: Minimize is MINIMIZE_SEVPA [2018-11-28 13:06:47,285 INFO L393 AbstractCegarLoop]: ======== Iteration 0==of CEGAR loop == AllErrorsAtOnce======== [2018-11-28 13:06:47,303 INFO L276 IsEmpty]: Start isEmpty. Operand 118 states. [2018-11-28 13:06:47,307 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 9 [2018-11-28 13:06:47,307 INFO L394 BasicCegarLoop]: Found error trace [2018-11-28 13:06:47,308 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1] [2018-11-28 13:06:47,310 INFO L423 AbstractCegarLoop]: === Iteration 1 === [single_argvErr6ASSERT_VIOLATIONINTEGER_OVERFLOW, single_argvErr0ASSERT_VIOLATIONINTEGER_OVERFLOW, single_argvErr2ASSERT_VIOLATIONINTEGER_OVERFLOW, single_argvErr4ASSERT_VIOLATIONINTEGER_OVERFLOW, single_argvErr5ASSERT_VIOLATIONINTEGER_OVERFLOW, single_argvErr1ASSERT_VIOLATIONINTEGER_OVERFLOW, single_argvErr3ASSERT_VIOLATIONINTEGER_OVERFLOW, single_argvErr7ASSERT_VIOLATIONINTEGER_OVERFLOW, single_argvErr8ASSERT_VIOLATIONINTEGER_OVERFLOW, single_argvErr9ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr6ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr10ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr5ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr11ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr7ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr0ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr15ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr8ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr14ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr1ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr4ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr3ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr2ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr9ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr12ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr13ASSERT_VIOLATIONINTEGER_OVERFLOW, dirnameErr0ASSERT_VIOLATIONINTEGER_OVERFLOW, dirnameErr1ASSERT_VIOLATIONINTEGER_OVERFLOW]=== [2018-11-28 13:06:47,315 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-28 13:06:47,315 INFO L82 PathProgramCache]: Analyzing trace with hash -484679774, now seen corresponding path program 1 times [2018-11-28 13:06:47,317 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-28 13:06:47,318 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-28 13:06:47,359 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 13:06:47,359 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-28 13:06:47,359 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 13:06:47,460 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-28 13:06:47,544 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-28 13:06:47,546 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-28 13:06:47,546 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2018-11-28 13:06:47,549 INFO L459 AbstractCegarLoop]: Interpolant automaton has 3 states [2018-11-28 13:06:47,556 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-28 13:06:47,557 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-28 13:06:47,559 INFO L87 Difference]: Start difference. First operand 118 states. Second operand 3 states. [2018-11-28 13:06:47,636 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-28 13:06:47,637 INFO L93 Difference]: Finished difference Result 226 states and 277 transitions. [2018-11-28 13:06:47,637 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-28 13:06:47,639 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 8 [2018-11-28 13:06:47,639 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-28 13:06:47,647 INFO L225 Difference]: With dead ends: 226 [2018-11-28 13:06:47,648 INFO L226 Difference]: Without dead ends: 113 [2018-11-28 13:06:47,651 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 2 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-28 13:06:47,666 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 113 states. [2018-11-28 13:06:47,685 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 113 to 113. [2018-11-28 13:06:47,686 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 113 states. [2018-11-28 13:06:47,687 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 113 states to 113 states and 131 transitions. [2018-11-28 13:06:47,689 INFO L78 Accepts]: Start accepts. Automaton has 113 states and 131 transitions. Word has length 8 [2018-11-28 13:06:47,689 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-28 13:06:47,689 INFO L480 AbstractCegarLoop]: Abstraction has 113 states and 131 transitions. [2018-11-28 13:06:47,689 INFO L481 AbstractCegarLoop]: Interpolant automaton has 3 states. [2018-11-28 13:06:47,689 INFO L276 IsEmpty]: Start isEmpty. Operand 113 states and 131 transitions. [2018-11-28 13:06:47,690 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 10 [2018-11-28 13:06:47,690 INFO L394 BasicCegarLoop]: Found error trace [2018-11-28 13:06:47,690 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-28 13:06:47,690 INFO L423 AbstractCegarLoop]: === Iteration 2 === [single_argvErr6ASSERT_VIOLATIONINTEGER_OVERFLOW, single_argvErr0ASSERT_VIOLATIONINTEGER_OVERFLOW, single_argvErr2ASSERT_VIOLATIONINTEGER_OVERFLOW, single_argvErr4ASSERT_VIOLATIONINTEGER_OVERFLOW, single_argvErr5ASSERT_VIOLATIONINTEGER_OVERFLOW, single_argvErr1ASSERT_VIOLATIONINTEGER_OVERFLOW, single_argvErr3ASSERT_VIOLATIONINTEGER_OVERFLOW, single_argvErr7ASSERT_VIOLATIONINTEGER_OVERFLOW, single_argvErr8ASSERT_VIOLATIONINTEGER_OVERFLOW, single_argvErr9ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr6ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr10ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr5ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr11ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr7ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr0ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr15ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr8ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr14ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr1ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr4ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr3ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr2ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr9ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr12ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr13ASSERT_VIOLATIONINTEGER_OVERFLOW, dirnameErr0ASSERT_VIOLATIONINTEGER_OVERFLOW, dirnameErr1ASSERT_VIOLATIONINTEGER_OVERFLOW]=== [2018-11-28 13:06:47,691 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-28 13:06:47,691 INFO L82 PathProgramCache]: Analyzing trace with hash -2140170941, now seen corresponding path program 1 times [2018-11-28 13:06:47,691 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-28 13:06:47,691 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-28 13:06:47,693 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 13:06:47,693 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-28 13:06:47,693 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 13:06:47,719 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-28 13:06:47,771 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-28 13:06:47,771 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-28 13:06:47,771 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2018-11-28 13:06:47,773 INFO L459 AbstractCegarLoop]: Interpolant automaton has 3 states [2018-11-28 13:06:47,773 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-28 13:06:47,773 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-28 13:06:47,773 INFO L87 Difference]: Start difference. First operand 113 states and 131 transitions. Second operand 3 states. [2018-11-28 13:06:47,799 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-28 13:06:47,799 INFO L93 Difference]: Finished difference Result 116 states and 134 transitions. [2018-11-28 13:06:47,800 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-28 13:06:47,800 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 9 [2018-11-28 13:06:47,800 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-28 13:06:47,801 INFO L225 Difference]: With dead ends: 116 [2018-11-28 13:06:47,801 INFO L226 Difference]: Without dead ends: 115 [2018-11-28 13:06:47,802 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 2 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-28 13:06:47,803 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 115 states. [2018-11-28 13:06:47,810 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 115 to 115. [2018-11-28 13:06:47,811 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 115 states. [2018-11-28 13:06:47,812 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 115 states to 115 states and 133 transitions. [2018-11-28 13:06:47,812 INFO L78 Accepts]: Start accepts. Automaton has 115 states and 133 transitions. Word has length 9 [2018-11-28 13:06:47,813 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-28 13:06:47,813 INFO L480 AbstractCegarLoop]: Abstraction has 115 states and 133 transitions. [2018-11-28 13:06:47,813 INFO L481 AbstractCegarLoop]: Interpolant automaton has 3 states. [2018-11-28 13:06:47,813 INFO L276 IsEmpty]: Start isEmpty. Operand 115 states and 133 transitions. [2018-11-28 13:06:47,813 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 13 [2018-11-28 13:06:47,813 INFO L394 BasicCegarLoop]: Found error trace [2018-11-28 13:06:47,813 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-28 13:06:47,814 INFO L423 AbstractCegarLoop]: === Iteration 3 === [single_argvErr6ASSERT_VIOLATIONINTEGER_OVERFLOW, single_argvErr0ASSERT_VIOLATIONINTEGER_OVERFLOW, single_argvErr2ASSERT_VIOLATIONINTEGER_OVERFLOW, single_argvErr4ASSERT_VIOLATIONINTEGER_OVERFLOW, single_argvErr5ASSERT_VIOLATIONINTEGER_OVERFLOW, single_argvErr1ASSERT_VIOLATIONINTEGER_OVERFLOW, single_argvErr3ASSERT_VIOLATIONINTEGER_OVERFLOW, single_argvErr7ASSERT_VIOLATIONINTEGER_OVERFLOW, single_argvErr8ASSERT_VIOLATIONINTEGER_OVERFLOW, single_argvErr9ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr6ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr10ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr5ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr11ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr7ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr0ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr15ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr8ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr14ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr1ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr4ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr3ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr2ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr9ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr12ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr13ASSERT_VIOLATIONINTEGER_OVERFLOW, dirnameErr0ASSERT_VIOLATIONINTEGER_OVERFLOW, dirnameErr1ASSERT_VIOLATIONINTEGER_OVERFLOW]=== [2018-11-28 13:06:47,814 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-28 13:06:47,814 INFO L82 PathProgramCache]: Analyzing trace with hash 957163037, now seen corresponding path program 1 times [2018-11-28 13:06:47,814 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-28 13:06:47,815 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-28 13:06:47,816 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 13:06:47,817 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-28 13:06:47,817 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 13:06:47,846 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-28 13:06:47,895 INFO L134 CoverageAnalysis]: Checked inductivity of 1 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2018-11-28 13:06:47,895 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-28 13:06:47,896 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2018-11-28 13:06:47,896 INFO L459 AbstractCegarLoop]: Interpolant automaton has 3 states [2018-11-28 13:06:47,896 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-28 13:06:47,896 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-28 13:06:47,896 INFO L87 Difference]: Start difference. First operand 115 states and 133 transitions. Second operand 3 states. [2018-11-28 13:06:47,941 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-28 13:06:47,941 INFO L93 Difference]: Finished difference Result 115 states and 133 transitions. [2018-11-28 13:06:47,942 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-28 13:06:47,942 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 12 [2018-11-28 13:06:47,942 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-28 13:06:47,943 INFO L225 Difference]: With dead ends: 115 [2018-11-28 13:06:47,943 INFO L226 Difference]: Without dead ends: 111 [2018-11-28 13:06:47,943 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 2 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-28 13:06:47,944 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 111 states. [2018-11-28 13:06:47,950 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 111 to 111. [2018-11-28 13:06:47,950 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 111 states. [2018-11-28 13:06:47,951 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 111 states to 111 states and 129 transitions. [2018-11-28 13:06:47,952 INFO L78 Accepts]: Start accepts. Automaton has 111 states and 129 transitions. Word has length 12 [2018-11-28 13:06:47,952 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-28 13:06:47,952 INFO L480 AbstractCegarLoop]: Abstraction has 111 states and 129 transitions. [2018-11-28 13:06:47,952 INFO L481 AbstractCegarLoop]: Interpolant automaton has 3 states. [2018-11-28 13:06:47,952 INFO L276 IsEmpty]: Start isEmpty. Operand 111 states and 129 transitions. [2018-11-28 13:06:47,952 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 13 [2018-11-28 13:06:47,953 INFO L394 BasicCegarLoop]: Found error trace [2018-11-28 13:06:47,953 INFO L402 BasicCegarLoop]: trace histogram [2, 2, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-28 13:06:47,953 INFO L423 AbstractCegarLoop]: === Iteration 4 === [single_argvErr6ASSERT_VIOLATIONINTEGER_OVERFLOW, single_argvErr0ASSERT_VIOLATIONINTEGER_OVERFLOW, single_argvErr2ASSERT_VIOLATIONINTEGER_OVERFLOW, single_argvErr4ASSERT_VIOLATIONINTEGER_OVERFLOW, single_argvErr5ASSERT_VIOLATIONINTEGER_OVERFLOW, single_argvErr1ASSERT_VIOLATIONINTEGER_OVERFLOW, single_argvErr3ASSERT_VIOLATIONINTEGER_OVERFLOW, single_argvErr7ASSERT_VIOLATIONINTEGER_OVERFLOW, single_argvErr8ASSERT_VIOLATIONINTEGER_OVERFLOW, single_argvErr9ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr6ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr10ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr5ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr11ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr7ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr0ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr15ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr8ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr14ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr1ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr4ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr3ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr2ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr9ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr12ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr13ASSERT_VIOLATIONINTEGER_OVERFLOW, dirnameErr0ASSERT_VIOLATIONINTEGER_OVERFLOW, dirnameErr1ASSERT_VIOLATIONINTEGER_OVERFLOW]=== [2018-11-28 13:06:47,953 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-28 13:06:47,954 INFO L82 PathProgramCache]: Analyzing trace with hash 957164767, now seen corresponding path program 1 times [2018-11-28 13:06:47,954 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-28 13:06:47,954 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-28 13:06:47,955 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 13:06:47,955 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-28 13:06:47,956 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 13:06:47,977 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-28 13:06:48,013 INFO L134 CoverageAnalysis]: Checked inductivity of 3 backedges. 3 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-28 13:06:48,013 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-28 13:06:48,013 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2018-11-28 13:06:48,014 INFO L459 AbstractCegarLoop]: Interpolant automaton has 3 states [2018-11-28 13:06:48,014 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-28 13:06:48,014 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-28 13:06:48,014 INFO L87 Difference]: Start difference. First operand 111 states and 129 transitions. Second operand 3 states. [2018-11-28 13:06:48,028 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-28 13:06:48,028 INFO L93 Difference]: Finished difference Result 111 states and 129 transitions. [2018-11-28 13:06:48,029 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-28 13:06:48,029 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 12 [2018-11-28 13:06:48,029 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-28 13:06:48,030 INFO L225 Difference]: With dead ends: 111 [2018-11-28 13:06:48,030 INFO L226 Difference]: Without dead ends: 110 [2018-11-28 13:06:48,030 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 2 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-28 13:06:48,031 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 110 states. [2018-11-28 13:06:48,037 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 110 to 108. [2018-11-28 13:06:48,037 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 108 states. [2018-11-28 13:06:48,038 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 108 states to 108 states and 126 transitions. [2018-11-28 13:06:48,038 INFO L78 Accepts]: Start accepts. Automaton has 108 states and 126 transitions. Word has length 12 [2018-11-28 13:06:48,038 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-28 13:06:48,039 INFO L480 AbstractCegarLoop]: Abstraction has 108 states and 126 transitions. [2018-11-28 13:06:48,039 INFO L481 AbstractCegarLoop]: Interpolant automaton has 3 states. [2018-11-28 13:06:48,039 INFO L276 IsEmpty]: Start isEmpty. Operand 108 states and 126 transitions. [2018-11-28 13:06:48,039 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 14 [2018-11-28 13:06:48,039 INFO L394 BasicCegarLoop]: Found error trace [2018-11-28 13:06:48,039 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-28 13:06:48,040 INFO L423 AbstractCegarLoop]: === Iteration 5 === [single_argvErr6ASSERT_VIOLATIONINTEGER_OVERFLOW, single_argvErr0ASSERT_VIOLATIONINTEGER_OVERFLOW, single_argvErr2ASSERT_VIOLATIONINTEGER_OVERFLOW, single_argvErr4ASSERT_VIOLATIONINTEGER_OVERFLOW, single_argvErr5ASSERT_VIOLATIONINTEGER_OVERFLOW, single_argvErr1ASSERT_VIOLATIONINTEGER_OVERFLOW, single_argvErr3ASSERT_VIOLATIONINTEGER_OVERFLOW, single_argvErr7ASSERT_VIOLATIONINTEGER_OVERFLOW, single_argvErr8ASSERT_VIOLATIONINTEGER_OVERFLOW, single_argvErr9ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr6ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr10ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr5ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr11ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr7ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr0ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr15ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr8ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr14ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr1ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr4ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr3ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr2ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr9ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr12ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr13ASSERT_VIOLATIONINTEGER_OVERFLOW, dirnameErr0ASSERT_VIOLATIONINTEGER_OVERFLOW, dirnameErr1ASSERT_VIOLATIONINTEGER_OVERFLOW]=== [2018-11-28 13:06:48,040 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-28 13:06:48,040 INFO L82 PathProgramCache]: Analyzing trace with hash -392716752, now seen corresponding path program 1 times [2018-11-28 13:06:48,041 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-28 13:06:48,041 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-28 13:06:48,042 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 13:06:48,043 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-28 13:06:48,043 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 13:06:48,081 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-28 13:06:48,131 INFO L134 CoverageAnalysis]: Checked inductivity of 1 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2018-11-28 13:06:48,131 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-28 13:06:48,131 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2018-11-28 13:06:48,131 INFO L459 AbstractCegarLoop]: Interpolant automaton has 3 states [2018-11-28 13:06:48,132 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-28 13:06:48,132 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-28 13:06:48,132 INFO L87 Difference]: Start difference. First operand 108 states and 126 transitions. Second operand 3 states. [2018-11-28 13:06:48,178 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-28 13:06:48,179 INFO L93 Difference]: Finished difference Result 108 states and 126 transitions. [2018-11-28 13:06:48,180 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-28 13:06:48,180 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 13 [2018-11-28 13:06:48,181 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-28 13:06:48,181 INFO L225 Difference]: With dead ends: 108 [2018-11-28 13:06:48,181 INFO L226 Difference]: Without dead ends: 106 [2018-11-28 13:06:48,182 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 2 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-28 13:06:48,182 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 106 states. [2018-11-28 13:06:48,192 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 106 to 106. [2018-11-28 13:06:48,192 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 106 states. [2018-11-28 13:06:48,192 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 106 states to 106 states and 124 transitions. [2018-11-28 13:06:48,193 INFO L78 Accepts]: Start accepts. Automaton has 106 states and 124 transitions. Word has length 13 [2018-11-28 13:06:48,193 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-28 13:06:48,193 INFO L480 AbstractCegarLoop]: Abstraction has 106 states and 124 transitions. [2018-11-28 13:06:48,193 INFO L481 AbstractCegarLoop]: Interpolant automaton has 3 states. [2018-11-28 13:06:48,193 INFO L276 IsEmpty]: Start isEmpty. Operand 106 states and 124 transitions. [2018-11-28 13:06:48,193 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 16 [2018-11-28 13:06:48,193 INFO L394 BasicCegarLoop]: Found error trace [2018-11-28 13:06:48,193 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-28 13:06:48,196 INFO L423 AbstractCegarLoop]: === Iteration 6 === [single_argvErr6ASSERT_VIOLATIONINTEGER_OVERFLOW, single_argvErr0ASSERT_VIOLATIONINTEGER_OVERFLOW, single_argvErr2ASSERT_VIOLATIONINTEGER_OVERFLOW, single_argvErr4ASSERT_VIOLATIONINTEGER_OVERFLOW, single_argvErr5ASSERT_VIOLATIONINTEGER_OVERFLOW, single_argvErr1ASSERT_VIOLATIONINTEGER_OVERFLOW, single_argvErr3ASSERT_VIOLATIONINTEGER_OVERFLOW, single_argvErr7ASSERT_VIOLATIONINTEGER_OVERFLOW, single_argvErr8ASSERT_VIOLATIONINTEGER_OVERFLOW, single_argvErr9ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr6ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr10ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr5ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr11ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr7ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr0ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr15ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr8ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr14ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr1ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr4ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr3ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr2ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr9ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr12ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr13ASSERT_VIOLATIONINTEGER_OVERFLOW, dirnameErr0ASSERT_VIOLATIONINTEGER_OVERFLOW, dirnameErr1ASSERT_VIOLATIONINTEGER_OVERFLOW]=== [2018-11-28 13:06:48,197 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-28 13:06:48,197 INFO L82 PathProgramCache]: Analyzing trace with hash 556328978, now seen corresponding path program 1 times [2018-11-28 13:06:48,197 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-28 13:06:48,197 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-28 13:06:48,198 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 13:06:48,199 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-28 13:06:48,199 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 13:06:48,220 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-28 13:06:48,252 INFO L134 CoverageAnalysis]: Checked inductivity of 1 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2018-11-28 13:06:48,252 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-28 13:06:48,252 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2018-11-28 13:06:48,252 INFO L459 AbstractCegarLoop]: Interpolant automaton has 3 states [2018-11-28 13:06:48,252 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-28 13:06:48,253 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-28 13:06:48,253 INFO L87 Difference]: Start difference. First operand 106 states and 124 transitions. Second operand 3 states. [2018-11-28 13:06:48,286 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-28 13:06:48,286 INFO L93 Difference]: Finished difference Result 106 states and 124 transitions. [2018-11-28 13:06:48,287 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-28 13:06:48,287 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 15 [2018-11-28 13:06:48,288 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-28 13:06:48,288 INFO L225 Difference]: With dead ends: 106 [2018-11-28 13:06:48,288 INFO L226 Difference]: Without dead ends: 104 [2018-11-28 13:06:48,289 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 2 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-28 13:06:48,289 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 104 states. [2018-11-28 13:06:48,293 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 104 to 104. [2018-11-28 13:06:48,294 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 104 states. [2018-11-28 13:06:48,294 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 104 states to 104 states and 122 transitions. [2018-11-28 13:06:48,294 INFO L78 Accepts]: Start accepts. Automaton has 104 states and 122 transitions. Word has length 15 [2018-11-28 13:06:48,295 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-28 13:06:48,295 INFO L480 AbstractCegarLoop]: Abstraction has 104 states and 122 transitions. [2018-11-28 13:06:48,295 INFO L481 AbstractCegarLoop]: Interpolant automaton has 3 states. [2018-11-28 13:06:48,295 INFO L276 IsEmpty]: Start isEmpty. Operand 104 states and 122 transitions. [2018-11-28 13:06:48,295 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 23 [2018-11-28 13:06:48,295 INFO L394 BasicCegarLoop]: Found error trace [2018-11-28 13:06:48,295 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-28 13:06:48,296 INFO L423 AbstractCegarLoop]: === Iteration 7 === [single_argvErr6ASSERT_VIOLATIONINTEGER_OVERFLOW, single_argvErr0ASSERT_VIOLATIONINTEGER_OVERFLOW, single_argvErr2ASSERT_VIOLATIONINTEGER_OVERFLOW, single_argvErr4ASSERT_VIOLATIONINTEGER_OVERFLOW, single_argvErr5ASSERT_VIOLATIONINTEGER_OVERFLOW, single_argvErr1ASSERT_VIOLATIONINTEGER_OVERFLOW, single_argvErr3ASSERT_VIOLATIONINTEGER_OVERFLOW, single_argvErr7ASSERT_VIOLATIONINTEGER_OVERFLOW, single_argvErr8ASSERT_VIOLATIONINTEGER_OVERFLOW, single_argvErr9ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr6ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr10ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr5ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr11ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr7ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr0ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr15ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr8ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr14ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr1ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr4ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr3ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr2ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr9ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr12ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr13ASSERT_VIOLATIONINTEGER_OVERFLOW, dirnameErr0ASSERT_VIOLATIONINTEGER_OVERFLOW, dirnameErr1ASSERT_VIOLATIONINTEGER_OVERFLOW]=== [2018-11-28 13:06:48,296 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-28 13:06:48,296 INFO L82 PathProgramCache]: Analyzing trace with hash 1553574359, now seen corresponding path program 1 times [2018-11-28 13:06:48,296 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-28 13:06:48,296 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-28 13:06:48,297 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 13:06:48,298 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-28 13:06:48,298 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 13:06:48,316 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-28 13:06:48,348 INFO L134 CoverageAnalysis]: Checked inductivity of 1 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2018-11-28 13:06:48,348 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-28 13:06:48,348 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-28 13:06:48,348 INFO L459 AbstractCegarLoop]: Interpolant automaton has 3 states [2018-11-28 13:06:48,349 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-28 13:06:48,349 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-28 13:06:48,349 INFO L87 Difference]: Start difference. First operand 104 states and 122 transitions. Second operand 3 states. [2018-11-28 13:06:48,375 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-28 13:06:48,376 INFO L93 Difference]: Finished difference Result 192 states and 230 transitions. [2018-11-28 13:06:48,376 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-28 13:06:48,376 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 22 [2018-11-28 13:06:48,376 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-28 13:06:48,377 INFO L225 Difference]: With dead ends: 192 [2018-11-28 13:06:48,377 INFO L226 Difference]: Without dead ends: 107 [2018-11-28 13:06:48,378 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-28 13:06:48,378 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 107 states. [2018-11-28 13:06:48,382 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 107 to 107. [2018-11-28 13:06:48,382 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 107 states. [2018-11-28 13:06:48,383 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 107 states to 107 states and 125 transitions. [2018-11-28 13:06:48,383 INFO L78 Accepts]: Start accepts. Automaton has 107 states and 125 transitions. Word has length 22 [2018-11-28 13:06:48,383 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-28 13:06:48,383 INFO L480 AbstractCegarLoop]: Abstraction has 107 states and 125 transitions. [2018-11-28 13:06:48,383 INFO L481 AbstractCegarLoop]: Interpolant automaton has 3 states. [2018-11-28 13:06:48,383 INFO L276 IsEmpty]: Start isEmpty. Operand 107 states and 125 transitions. [2018-11-28 13:06:48,384 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 26 [2018-11-28 13:06:48,384 INFO L394 BasicCegarLoop]: Found error trace [2018-11-28 13:06:48,384 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-28 13:06:48,385 INFO L423 AbstractCegarLoop]: === Iteration 8 === [single_argvErr6ASSERT_VIOLATIONINTEGER_OVERFLOW, single_argvErr0ASSERT_VIOLATIONINTEGER_OVERFLOW, single_argvErr2ASSERT_VIOLATIONINTEGER_OVERFLOW, single_argvErr4ASSERT_VIOLATIONINTEGER_OVERFLOW, single_argvErr5ASSERT_VIOLATIONINTEGER_OVERFLOW, single_argvErr1ASSERT_VIOLATIONINTEGER_OVERFLOW, single_argvErr3ASSERT_VIOLATIONINTEGER_OVERFLOW, single_argvErr7ASSERT_VIOLATIONINTEGER_OVERFLOW, single_argvErr8ASSERT_VIOLATIONINTEGER_OVERFLOW, single_argvErr9ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr6ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr10ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr5ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr11ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr7ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr0ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr15ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr8ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr14ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr1ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr4ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr3ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr2ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr9ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr12ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr13ASSERT_VIOLATIONINTEGER_OVERFLOW, dirnameErr0ASSERT_VIOLATIONINTEGER_OVERFLOW, dirnameErr1ASSERT_VIOLATIONINTEGER_OVERFLOW]=== [2018-11-28 13:06:48,385 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-28 13:06:48,385 INFO L82 PathProgramCache]: Analyzing trace with hash -32009876, now seen corresponding path program 1 times [2018-11-28 13:06:48,385 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-28 13:06:48,385 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-28 13:06:48,386 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 13:06:48,386 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-28 13:06:48,386 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 13:06:48,405 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-28 13:06:48,445 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 2 trivial. 0 not checked. [2018-11-28 13:06:48,445 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-28 13:06:48,445 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-28 13:06:48,445 INFO L459 AbstractCegarLoop]: Interpolant automaton has 4 states [2018-11-28 13:06:48,445 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2018-11-28 13:06:48,446 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2018-11-28 13:06:48,446 INFO L87 Difference]: Start difference. First operand 107 states and 125 transitions. Second operand 4 states. [2018-11-28 13:06:48,504 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-28 13:06:48,504 INFO L93 Difference]: Finished difference Result 115 states and 135 transitions. [2018-11-28 13:06:48,505 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2018-11-28 13:06:48,505 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 25 [2018-11-28 13:06:48,505 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-28 13:06:48,506 INFO L225 Difference]: With dead ends: 115 [2018-11-28 13:06:48,506 INFO L226 Difference]: Without dead ends: 114 [2018-11-28 13:06:48,507 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 4 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2018-11-28 13:06:48,507 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 114 states. [2018-11-28 13:06:48,515 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 114 to 106. [2018-11-28 13:06:48,515 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 106 states. [2018-11-28 13:06:48,516 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 106 states to 106 states and 124 transitions. [2018-11-28 13:06:48,516 INFO L78 Accepts]: Start accepts. Automaton has 106 states and 124 transitions. Word has length 25 [2018-11-28 13:06:48,516 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-28 13:06:48,516 INFO L480 AbstractCegarLoop]: Abstraction has 106 states and 124 transitions. [2018-11-28 13:06:48,516 INFO L481 AbstractCegarLoop]: Interpolant automaton has 4 states. [2018-11-28 13:06:48,516 INFO L276 IsEmpty]: Start isEmpty. Operand 106 states and 124 transitions. [2018-11-28 13:06:48,517 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 26 [2018-11-28 13:06:48,517 INFO L394 BasicCegarLoop]: Found error trace [2018-11-28 13:06:48,517 INFO L402 BasicCegarLoop]: trace histogram [2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-28 13:06:48,517 INFO L423 AbstractCegarLoop]: === Iteration 9 === [single_argvErr6ASSERT_VIOLATIONINTEGER_OVERFLOW, single_argvErr0ASSERT_VIOLATIONINTEGER_OVERFLOW, single_argvErr2ASSERT_VIOLATIONINTEGER_OVERFLOW, single_argvErr4ASSERT_VIOLATIONINTEGER_OVERFLOW, single_argvErr5ASSERT_VIOLATIONINTEGER_OVERFLOW, single_argvErr1ASSERT_VIOLATIONINTEGER_OVERFLOW, single_argvErr3ASSERT_VIOLATIONINTEGER_OVERFLOW, single_argvErr7ASSERT_VIOLATIONINTEGER_OVERFLOW, single_argvErr8ASSERT_VIOLATIONINTEGER_OVERFLOW, single_argvErr9ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr6ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr10ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr5ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr11ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr7ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr0ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr15ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr8ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr14ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr1ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr4ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr3ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr2ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr9ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr12ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr13ASSERT_VIOLATIONINTEGER_OVERFLOW, dirnameErr0ASSERT_VIOLATIONINTEGER_OVERFLOW, dirnameErr1ASSERT_VIOLATIONINTEGER_OVERFLOW]=== [2018-11-28 13:06:48,518 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-28 13:06:48,518 INFO L82 PathProgramCache]: Analyzing trace with hash -32009821, now seen corresponding path program 1 times [2018-11-28 13:06:48,518 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-28 13:06:48,518 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-28 13:06:48,519 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 13:06:48,519 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-28 13:06:48,519 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 13:06:48,538 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-28 13:06:48,575 INFO L134 CoverageAnalysis]: Checked inductivity of 3 backedges. 1 proven. 0 refuted. 0 times theorem prover too weak. 2 trivial. 0 not checked. [2018-11-28 13:06:48,575 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-28 13:06:48,575 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2018-11-28 13:06:48,576 INFO L459 AbstractCegarLoop]: Interpolant automaton has 3 states [2018-11-28 13:06:48,576 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-28 13:06:48,576 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-28 13:06:48,576 INFO L87 Difference]: Start difference. First operand 106 states and 124 transitions. Second operand 3 states. [2018-11-28 13:06:48,591 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-28 13:06:48,591 INFO L93 Difference]: Finished difference Result 106 states and 124 transitions. [2018-11-28 13:06:48,592 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-28 13:06:48,592 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 25 [2018-11-28 13:06:48,592 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-28 13:06:48,593 INFO L225 Difference]: With dead ends: 106 [2018-11-28 13:06:48,593 INFO L226 Difference]: Without dead ends: 105 [2018-11-28 13:06:48,593 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 2 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-28 13:06:48,594 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 105 states. [2018-11-28 13:06:48,597 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 105 to 105. [2018-11-28 13:06:48,598 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 105 states. [2018-11-28 13:06:48,603 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 105 states to 105 states and 123 transitions. [2018-11-28 13:06:48,604 INFO L78 Accepts]: Start accepts. Automaton has 105 states and 123 transitions. Word has length 25 [2018-11-28 13:06:48,604 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-28 13:06:48,604 INFO L480 AbstractCegarLoop]: Abstraction has 105 states and 123 transitions. [2018-11-28 13:06:48,605 INFO L481 AbstractCegarLoop]: Interpolant automaton has 3 states. [2018-11-28 13:06:48,605 INFO L276 IsEmpty]: Start isEmpty. Operand 105 states and 123 transitions. [2018-11-28 13:06:48,605 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 27 [2018-11-28 13:06:48,605 INFO L394 BasicCegarLoop]: Found error trace [2018-11-28 13:06:48,605 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-28 13:06:48,606 INFO L423 AbstractCegarLoop]: === Iteration 10 === [single_argvErr6ASSERT_VIOLATIONINTEGER_OVERFLOW, single_argvErr0ASSERT_VIOLATIONINTEGER_OVERFLOW, single_argvErr2ASSERT_VIOLATIONINTEGER_OVERFLOW, single_argvErr4ASSERT_VIOLATIONINTEGER_OVERFLOW, single_argvErr5ASSERT_VIOLATIONINTEGER_OVERFLOW, single_argvErr1ASSERT_VIOLATIONINTEGER_OVERFLOW, single_argvErr3ASSERT_VIOLATIONINTEGER_OVERFLOW, single_argvErr7ASSERT_VIOLATIONINTEGER_OVERFLOW, single_argvErr8ASSERT_VIOLATIONINTEGER_OVERFLOW, single_argvErr9ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr6ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr10ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr5ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr11ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr7ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr0ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr15ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr8ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr14ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr1ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr4ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr3ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr2ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr9ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr12ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr13ASSERT_VIOLATIONINTEGER_OVERFLOW, dirnameErr0ASSERT_VIOLATIONINTEGER_OVERFLOW, dirnameErr1ASSERT_VIOLATIONINTEGER_OVERFLOW]=== [2018-11-28 13:06:48,606 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-28 13:06:48,606 INFO L82 PathProgramCache]: Analyzing trace with hash -992305943, now seen corresponding path program 1 times [2018-11-28 13:06:48,606 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-28 13:06:48,606 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-28 13:06:48,611 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 13:06:48,611 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-28 13:06:48,611 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 13:06:48,630 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-28 13:06:48,672 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 2 trivial. 0 not checked. [2018-11-28 13:06:48,673 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-28 13:06:48,673 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2018-11-28 13:06:48,673 INFO L459 AbstractCegarLoop]: Interpolant automaton has 3 states [2018-11-28 13:06:48,673 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-28 13:06:48,673 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-28 13:06:48,673 INFO L87 Difference]: Start difference. First operand 105 states and 123 transitions. Second operand 3 states. [2018-11-28 13:06:48,711 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-28 13:06:48,711 INFO L93 Difference]: Finished difference Result 123 states and 144 transitions. [2018-11-28 13:06:48,711 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-28 13:06:48,711 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 26 [2018-11-28 13:06:48,711 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-28 13:06:48,712 INFO L225 Difference]: With dead ends: 123 [2018-11-28 13:06:48,712 INFO L226 Difference]: Without dead ends: 122 [2018-11-28 13:06:48,712 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 2 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-28 13:06:48,713 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 122 states. [2018-11-28 13:06:48,716 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 122 to 114. [2018-11-28 13:06:48,716 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 114 states. [2018-11-28 13:06:48,717 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 114 states to 114 states and 135 transitions. [2018-11-28 13:06:48,717 INFO L78 Accepts]: Start accepts. Automaton has 114 states and 135 transitions. Word has length 26 [2018-11-28 13:06:48,717 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-28 13:06:48,717 INFO L480 AbstractCegarLoop]: Abstraction has 114 states and 135 transitions. [2018-11-28 13:06:48,717 INFO L481 AbstractCegarLoop]: Interpolant automaton has 3 states. [2018-11-28 13:06:48,718 INFO L276 IsEmpty]: Start isEmpty. Operand 114 states and 135 transitions. [2018-11-28 13:06:48,718 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 27 [2018-11-28 13:06:48,718 INFO L394 BasicCegarLoop]: Found error trace [2018-11-28 13:06:48,718 INFO L402 BasicCegarLoop]: trace histogram [2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-28 13:06:48,719 INFO L423 AbstractCegarLoop]: === Iteration 11 === [single_argvErr6ASSERT_VIOLATIONINTEGER_OVERFLOW, single_argvErr0ASSERT_VIOLATIONINTEGER_OVERFLOW, single_argvErr2ASSERT_VIOLATIONINTEGER_OVERFLOW, single_argvErr4ASSERT_VIOLATIONINTEGER_OVERFLOW, single_argvErr5ASSERT_VIOLATIONINTEGER_OVERFLOW, single_argvErr1ASSERT_VIOLATIONINTEGER_OVERFLOW, single_argvErr3ASSERT_VIOLATIONINTEGER_OVERFLOW, single_argvErr7ASSERT_VIOLATIONINTEGER_OVERFLOW, single_argvErr8ASSERT_VIOLATIONINTEGER_OVERFLOW, single_argvErr9ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr6ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr10ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr5ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr11ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr7ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr0ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr15ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr8ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr14ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr1ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr4ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr3ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr2ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr9ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr12ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr13ASSERT_VIOLATIONINTEGER_OVERFLOW, dirnameErr0ASSERT_VIOLATIONINTEGER_OVERFLOW, dirnameErr1ASSERT_VIOLATIONINTEGER_OVERFLOW]=== [2018-11-28 13:06:48,719 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-28 13:06:48,719 INFO L82 PathProgramCache]: Analyzing trace with hash -992304245, now seen corresponding path program 1 times [2018-11-28 13:06:48,719 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-28 13:06:48,719 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-28 13:06:48,720 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 13:06:48,720 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-28 13:06:48,720 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 13:06:48,737 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-28 13:06:48,768 INFO L134 CoverageAnalysis]: Checked inductivity of 4 backedges. 3 proven. 0 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2018-11-28 13:06:48,768 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-28 13:06:48,768 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2018-11-28 13:06:48,768 INFO L459 AbstractCegarLoop]: Interpolant automaton has 3 states [2018-11-28 13:06:48,768 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-28 13:06:48,768 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-28 13:06:48,769 INFO L87 Difference]: Start difference. First operand 114 states and 135 transitions. Second operand 3 states. [2018-11-28 13:06:48,791 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-28 13:06:48,791 INFO L93 Difference]: Finished difference Result 121 states and 143 transitions. [2018-11-28 13:06:48,791 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-28 13:06:48,791 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 26 [2018-11-28 13:06:48,791 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-28 13:06:48,792 INFO L225 Difference]: With dead ends: 121 [2018-11-28 13:06:48,792 INFO L226 Difference]: Without dead ends: 120 [2018-11-28 13:06:48,792 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 2 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-28 13:06:48,793 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 120 states. [2018-11-28 13:06:48,796 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 120 to 109. [2018-11-28 13:06:48,796 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 109 states. [2018-11-28 13:06:48,797 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 109 states to 109 states and 129 transitions. [2018-11-28 13:06:48,797 INFO L78 Accepts]: Start accepts. Automaton has 109 states and 129 transitions. Word has length 26 [2018-11-28 13:06:48,797 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-28 13:06:48,797 INFO L480 AbstractCegarLoop]: Abstraction has 109 states and 129 transitions. [2018-11-28 13:06:48,797 INFO L481 AbstractCegarLoop]: Interpolant automaton has 3 states. [2018-11-28 13:06:48,798 INFO L276 IsEmpty]: Start isEmpty. Operand 109 states and 129 transitions. [2018-11-28 13:06:48,798 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 30 [2018-11-28 13:06:48,798 INFO L394 BasicCegarLoop]: Found error trace [2018-11-28 13:06:48,798 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-28 13:06:48,799 INFO L423 AbstractCegarLoop]: === Iteration 12 === [single_argvErr6ASSERT_VIOLATIONINTEGER_OVERFLOW, single_argvErr0ASSERT_VIOLATIONINTEGER_OVERFLOW, single_argvErr2ASSERT_VIOLATIONINTEGER_OVERFLOW, single_argvErr4ASSERT_VIOLATIONINTEGER_OVERFLOW, single_argvErr5ASSERT_VIOLATIONINTEGER_OVERFLOW, single_argvErr1ASSERT_VIOLATIONINTEGER_OVERFLOW, single_argvErr3ASSERT_VIOLATIONINTEGER_OVERFLOW, single_argvErr7ASSERT_VIOLATIONINTEGER_OVERFLOW, single_argvErr8ASSERT_VIOLATIONINTEGER_OVERFLOW, single_argvErr9ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr6ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr10ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr5ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr11ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr7ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr0ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr15ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr8ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr14ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr1ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr4ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr3ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr2ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr9ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr12ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr13ASSERT_VIOLATIONINTEGER_OVERFLOW, dirnameErr0ASSERT_VIOLATIONINTEGER_OVERFLOW, dirnameErr1ASSERT_VIOLATIONINTEGER_OVERFLOW]=== [2018-11-28 13:06:48,799 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-28 13:06:48,799 INFO L82 PathProgramCache]: Analyzing trace with hash 1525307751, now seen corresponding path program 1 times [2018-11-28 13:06:48,799 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-28 13:06:48,799 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-28 13:06:48,800 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 13:06:48,800 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-28 13:06:48,800 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 13:06:48,820 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-28 13:06:48,857 INFO L134 CoverageAnalysis]: Checked inductivity of 1 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-28 13:06:48,857 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-28 13:06:48,857 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_b218a3f8-accd-4719-941b-ce9fe174b24c/bin-2019/uautomizer/z3 Starting monitored process 2 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 2 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-28 13:06:48,876 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-28 13:06:49,011 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-28 13:06:49,024 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-28 13:06:49,081 INFO L134 CoverageAnalysis]: Checked inductivity of 1 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-28 13:06:49,101 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-11-28 13:06:49,101 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [4, 4] total 5 [2018-11-28 13:06:49,102 INFO L459 AbstractCegarLoop]: Interpolant automaton has 5 states [2018-11-28 13:06:49,102 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-11-28 13:06:49,102 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=10, Invalid=10, Unknown=0, NotChecked=0, Total=20 [2018-11-28 13:06:49,102 INFO L87 Difference]: Start difference. First operand 109 states and 129 transitions. Second operand 5 states. [2018-11-28 13:06:49,119 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-28 13:06:49,119 INFO L93 Difference]: Finished difference Result 213 states and 253 transitions. [2018-11-28 13:06:49,120 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2018-11-28 13:06:49,120 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 29 [2018-11-28 13:06:49,120 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-28 13:06:49,121 INFO L225 Difference]: With dead ends: 213 [2018-11-28 13:06:49,121 INFO L226 Difference]: Without dead ends: 114 [2018-11-28 13:06:49,121 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 32 GetRequests, 29 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=10, Invalid=10, Unknown=0, NotChecked=0, Total=20 [2018-11-28 13:06:49,122 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 114 states. [2018-11-28 13:06:49,125 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 114 to 112. [2018-11-28 13:06:49,126 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 112 states. [2018-11-28 13:06:49,126 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 112 states to 112 states and 132 transitions. [2018-11-28 13:06:49,126 INFO L78 Accepts]: Start accepts. Automaton has 112 states and 132 transitions. Word has length 29 [2018-11-28 13:06:49,126 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-28 13:06:49,127 INFO L480 AbstractCegarLoop]: Abstraction has 112 states and 132 transitions. [2018-11-28 13:06:49,127 INFO L481 AbstractCegarLoop]: Interpolant automaton has 5 states. [2018-11-28 13:06:49,127 INFO L276 IsEmpty]: Start isEmpty. Operand 112 states and 132 transitions. [2018-11-28 13:06:49,129 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 33 [2018-11-28 13:06:49,129 INFO L394 BasicCegarLoop]: Found error trace [2018-11-28 13:06:49,129 INFO L402 BasicCegarLoop]: trace histogram [2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-28 13:06:49,130 INFO L423 AbstractCegarLoop]: === Iteration 13 === [single_argvErr6ASSERT_VIOLATIONINTEGER_OVERFLOW, single_argvErr0ASSERT_VIOLATIONINTEGER_OVERFLOW, single_argvErr2ASSERT_VIOLATIONINTEGER_OVERFLOW, single_argvErr4ASSERT_VIOLATIONINTEGER_OVERFLOW, single_argvErr5ASSERT_VIOLATIONINTEGER_OVERFLOW, single_argvErr1ASSERT_VIOLATIONINTEGER_OVERFLOW, single_argvErr3ASSERT_VIOLATIONINTEGER_OVERFLOW, single_argvErr7ASSERT_VIOLATIONINTEGER_OVERFLOW, single_argvErr8ASSERT_VIOLATIONINTEGER_OVERFLOW, single_argvErr9ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr6ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr10ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr5ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr11ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr7ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr0ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr15ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr8ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr14ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr1ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr4ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr3ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr2ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr9ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr12ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr13ASSERT_VIOLATIONINTEGER_OVERFLOW, dirnameErr0ASSERT_VIOLATIONINTEGER_OVERFLOW, dirnameErr1ASSERT_VIOLATIONINTEGER_OVERFLOW]=== [2018-11-28 13:06:49,130 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-28 13:06:49,130 INFO L82 PathProgramCache]: Analyzing trace with hash -1995699453, now seen corresponding path program 2 times [2018-11-28 13:06:49,130 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-28 13:06:49,130 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-28 13:06:49,134 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 13:06:49,134 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-28 13:06:49,134 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 13:06:49,152 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-28 13:06:49,200 INFO L134 CoverageAnalysis]: Checked inductivity of 5 backedges. 0 proven. 5 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-28 13:06:49,200 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-28 13:06:49,200 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_b218a3f8-accd-4719-941b-ce9fe174b24c/bin-2019/uautomizer/z3 Starting monitored process 3 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 3 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-28 13:06:49,216 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-11-28 13:06:49,338 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) [2018-11-28 13:06:49,338 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-11-28 13:06:49,342 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-28 13:06:49,360 INFO L134 CoverageAnalysis]: Checked inductivity of 5 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2018-11-28 13:06:49,376 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 1 imperfect interpolant sequences. [2018-11-28 13:06:49,377 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [4] imperfect sequences [5] total 7 [2018-11-28 13:06:49,377 INFO L459 AbstractCegarLoop]: Interpolant automaton has 7 states [2018-11-28 13:06:49,377 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2018-11-28 13:06:49,377 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=15, Invalid=27, Unknown=0, NotChecked=0, Total=42 [2018-11-28 13:06:49,377 INFO L87 Difference]: Start difference. First operand 112 states and 132 transitions. Second operand 7 states. [2018-11-28 13:06:49,448 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-28 13:06:49,449 INFO L93 Difference]: Finished difference Result 216 states and 256 transitions. [2018-11-28 13:06:49,449 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2018-11-28 13:06:49,449 INFO L78 Accepts]: Start accepts. Automaton has 7 states. Word has length 32 [2018-11-28 13:06:49,449 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-28 13:06:49,450 INFO L225 Difference]: With dead ends: 216 [2018-11-28 13:06:49,450 INFO L226 Difference]: Without dead ends: 117 [2018-11-28 13:06:49,451 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 36 GetRequests, 31 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 4 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=15, Invalid=27, Unknown=0, NotChecked=0, Total=42 [2018-11-28 13:06:49,452 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 117 states. [2018-11-28 13:06:49,455 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 117 to 115. [2018-11-28 13:06:49,455 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 115 states. [2018-11-28 13:06:49,456 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 115 states to 115 states and 134 transitions. [2018-11-28 13:06:49,456 INFO L78 Accepts]: Start accepts. Automaton has 115 states and 134 transitions. Word has length 32 [2018-11-28 13:06:49,456 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-28 13:06:49,456 INFO L480 AbstractCegarLoop]: Abstraction has 115 states and 134 transitions. [2018-11-28 13:06:49,456 INFO L481 AbstractCegarLoop]: Interpolant automaton has 7 states. [2018-11-28 13:06:49,456 INFO L276 IsEmpty]: Start isEmpty. Operand 115 states and 134 transitions. [2018-11-28 13:06:49,457 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 40 [2018-11-28 13:06:49,457 INFO L394 BasicCegarLoop]: Found error trace [2018-11-28 13:06:49,457 INFO L402 BasicCegarLoop]: trace histogram [3, 3, 3, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-28 13:06:49,458 INFO L423 AbstractCegarLoop]: === Iteration 14 === [single_argvErr6ASSERT_VIOLATIONINTEGER_OVERFLOW, single_argvErr0ASSERT_VIOLATIONINTEGER_OVERFLOW, single_argvErr2ASSERT_VIOLATIONINTEGER_OVERFLOW, single_argvErr4ASSERT_VIOLATIONINTEGER_OVERFLOW, single_argvErr5ASSERT_VIOLATIONINTEGER_OVERFLOW, single_argvErr1ASSERT_VIOLATIONINTEGER_OVERFLOW, single_argvErr3ASSERT_VIOLATIONINTEGER_OVERFLOW, single_argvErr7ASSERT_VIOLATIONINTEGER_OVERFLOW, single_argvErr8ASSERT_VIOLATIONINTEGER_OVERFLOW, single_argvErr9ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr6ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr10ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr5ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr11ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr7ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr0ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr15ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr8ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr14ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr1ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr4ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr3ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr2ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr9ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr12ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr13ASSERT_VIOLATIONINTEGER_OVERFLOW, dirnameErr0ASSERT_VIOLATIONINTEGER_OVERFLOW, dirnameErr1ASSERT_VIOLATIONINTEGER_OVERFLOW]=== [2018-11-28 13:06:49,458 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-28 13:06:49,458 INFO L82 PathProgramCache]: Analyzing trace with hash -842011914, now seen corresponding path program 1 times [2018-11-28 13:06:49,461 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-28 13:06:49,461 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-28 13:06:49,462 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 13:06:49,462 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-28 13:06:49,462 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 13:06:49,478 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-28 13:06:49,507 INFO L134 CoverageAnalysis]: Checked inductivity of 23 backedges. 9 proven. 0 refuted. 0 times theorem prover too weak. 14 trivial. 0 not checked. [2018-11-28 13:06:49,507 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-28 13:06:49,507 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2018-11-28 13:06:49,508 INFO L459 AbstractCegarLoop]: Interpolant automaton has 3 states [2018-11-28 13:06:49,508 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-28 13:06:49,508 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-28 13:06:49,508 INFO L87 Difference]: Start difference. First operand 115 states and 134 transitions. Second operand 3 states. [2018-11-28 13:06:49,523 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-28 13:06:49,523 INFO L93 Difference]: Finished difference Result 115 states and 134 transitions. [2018-11-28 13:06:49,523 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-28 13:06:49,523 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 39 [2018-11-28 13:06:49,524 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-28 13:06:49,524 INFO L225 Difference]: With dead ends: 115 [2018-11-28 13:06:49,524 INFO L226 Difference]: Without dead ends: 114 [2018-11-28 13:06:49,525 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 2 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-28 13:06:49,525 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 114 states. [2018-11-28 13:06:49,528 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 114 to 108. [2018-11-28 13:06:49,528 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 108 states. [2018-11-28 13:06:49,528 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 108 states to 108 states and 126 transitions. [2018-11-28 13:06:49,528 INFO L78 Accepts]: Start accepts. Automaton has 108 states and 126 transitions. Word has length 39 [2018-11-28 13:06:49,528 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-28 13:06:49,529 INFO L480 AbstractCegarLoop]: Abstraction has 108 states and 126 transitions. [2018-11-28 13:06:49,529 INFO L481 AbstractCegarLoop]: Interpolant automaton has 3 states. [2018-11-28 13:06:49,529 INFO L276 IsEmpty]: Start isEmpty. Operand 108 states and 126 transitions. [2018-11-28 13:06:49,529 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 43 [2018-11-28 13:06:49,529 INFO L394 BasicCegarLoop]: Found error trace [2018-11-28 13:06:49,529 INFO L402 BasicCegarLoop]: trace histogram [3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-28 13:06:49,530 INFO L423 AbstractCegarLoop]: === Iteration 15 === [single_argvErr6ASSERT_VIOLATIONINTEGER_OVERFLOW, single_argvErr0ASSERT_VIOLATIONINTEGER_OVERFLOW, single_argvErr2ASSERT_VIOLATIONINTEGER_OVERFLOW, single_argvErr4ASSERT_VIOLATIONINTEGER_OVERFLOW, single_argvErr5ASSERT_VIOLATIONINTEGER_OVERFLOW, single_argvErr1ASSERT_VIOLATIONINTEGER_OVERFLOW, single_argvErr3ASSERT_VIOLATIONINTEGER_OVERFLOW, single_argvErr7ASSERT_VIOLATIONINTEGER_OVERFLOW, single_argvErr8ASSERT_VIOLATIONINTEGER_OVERFLOW, single_argvErr9ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr6ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr10ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr5ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr11ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr7ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr0ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr15ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr8ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr14ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr1ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr4ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr3ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr2ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr9ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr12ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr13ASSERT_VIOLATIONINTEGER_OVERFLOW, dirnameErr0ASSERT_VIOLATIONINTEGER_OVERFLOW, dirnameErr1ASSERT_VIOLATIONINTEGER_OVERFLOW]=== [2018-11-28 13:06:49,530 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-28 13:06:49,533 INFO L82 PathProgramCache]: Analyzing trace with hash -716164038, now seen corresponding path program 1 times [2018-11-28 13:06:49,533 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-28 13:06:49,533 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-28 13:06:49,534 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 13:06:49,534 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-28 13:06:49,535 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 13:06:49,550 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-28 13:06:49,591 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 1 proven. 1 refuted. 0 times theorem prover too weak. 12 trivial. 0 not checked. [2018-11-28 13:06:49,591 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-28 13:06:49,591 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_b218a3f8-accd-4719-941b-ce9fe174b24c/bin-2019/uautomizer/z3 Starting monitored process 4 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 4 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-28 13:06:49,602 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-28 13:06:49,701 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-28 13:06:49,706 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-28 13:06:49,724 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 0 proven. 12 refuted. 0 times theorem prover too weak. 2 trivial. 0 not checked. [2018-11-28 13:06:49,740 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-11-28 13:06:49,741 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [4, 6] total 8 [2018-11-28 13:06:49,741 INFO L459 AbstractCegarLoop]: Interpolant automaton has 8 states [2018-11-28 13:06:49,741 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 8 interpolants. [2018-11-28 13:06:49,741 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=20, Invalid=36, Unknown=0, NotChecked=0, Total=56 [2018-11-28 13:06:49,741 INFO L87 Difference]: Start difference. First operand 108 states and 126 transitions. Second operand 8 states. [2018-11-28 13:06:49,786 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-28 13:06:49,787 INFO L93 Difference]: Finished difference Result 210 states and 247 transitions. [2018-11-28 13:06:49,787 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 8 states. [2018-11-28 13:06:49,787 INFO L78 Accepts]: Start accepts. Automaton has 8 states. Word has length 42 [2018-11-28 13:06:49,788 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-28 13:06:49,788 INFO L225 Difference]: With dead ends: 210 [2018-11-28 13:06:49,788 INFO L226 Difference]: Without dead ends: 118 [2018-11-28 13:06:49,789 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 45 GetRequests, 39 SyntacticMatches, 0 SemanticMatches, 6 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 4 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=20, Invalid=36, Unknown=0, NotChecked=0, Total=56 [2018-11-28 13:06:49,790 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 118 states. [2018-11-28 13:06:49,793 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 118 to 114. [2018-11-28 13:06:49,793 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 114 states. [2018-11-28 13:06:49,793 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 114 states to 114 states and 132 transitions. [2018-11-28 13:06:49,793 INFO L78 Accepts]: Start accepts. Automaton has 114 states and 132 transitions. Word has length 42 [2018-11-28 13:06:49,793 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-28 13:06:49,794 INFO L480 AbstractCegarLoop]: Abstraction has 114 states and 132 transitions. [2018-11-28 13:06:49,794 INFO L481 AbstractCegarLoop]: Interpolant automaton has 8 states. [2018-11-28 13:06:49,794 INFO L276 IsEmpty]: Start isEmpty. Operand 114 states and 132 transitions. [2018-11-28 13:06:49,797 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 49 [2018-11-28 13:06:49,797 INFO L394 BasicCegarLoop]: Found error trace [2018-11-28 13:06:49,797 INFO L402 BasicCegarLoop]: trace histogram [4, 4, 4, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-28 13:06:49,798 INFO L423 AbstractCegarLoop]: === Iteration 16 === [single_argvErr6ASSERT_VIOLATIONINTEGER_OVERFLOW, single_argvErr0ASSERT_VIOLATIONINTEGER_OVERFLOW, single_argvErr2ASSERT_VIOLATIONINTEGER_OVERFLOW, single_argvErr4ASSERT_VIOLATIONINTEGER_OVERFLOW, single_argvErr5ASSERT_VIOLATIONINTEGER_OVERFLOW, single_argvErr1ASSERT_VIOLATIONINTEGER_OVERFLOW, single_argvErr3ASSERT_VIOLATIONINTEGER_OVERFLOW, single_argvErr7ASSERT_VIOLATIONINTEGER_OVERFLOW, single_argvErr8ASSERT_VIOLATIONINTEGER_OVERFLOW, single_argvErr9ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr6ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr10ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr5ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr11ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr7ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr0ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr15ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr8ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr14ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr1ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr4ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr3ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr2ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr9ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr12ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr13ASSERT_VIOLATIONINTEGER_OVERFLOW, dirnameErr0ASSERT_VIOLATIONINTEGER_OVERFLOW, dirnameErr1ASSERT_VIOLATIONINTEGER_OVERFLOW]=== [2018-11-28 13:06:49,798 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-28 13:06:49,798 INFO L82 PathProgramCache]: Analyzing trace with hash -86642261, now seen corresponding path program 2 times [2018-11-28 13:06:49,798 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-28 13:06:49,799 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-28 13:06:49,799 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 13:06:49,799 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-28 13:06:49,800 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 13:06:49,817 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-28 13:06:49,856 INFO L134 CoverageAnalysis]: Checked inductivity of 28 backedges. 1 proven. 5 refuted. 0 times theorem prover too weak. 22 trivial. 0 not checked. [2018-11-28 13:06:49,856 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-28 13:06:49,856 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_b218a3f8-accd-4719-941b-ce9fe174b24c/bin-2019/uautomizer/z3 Starting monitored process 5 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 5 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-28 13:06:49,868 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-11-28 13:06:49,957 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) [2018-11-28 13:06:49,957 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-11-28 13:06:49,962 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-28 13:06:49,976 INFO L134 CoverageAnalysis]: Checked inductivity of 28 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 28 trivial. 0 not checked. [2018-11-28 13:06:49,993 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 1 imperfect interpolant sequences. [2018-11-28 13:06:49,993 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [5] total 6 [2018-11-28 13:06:49,994 INFO L459 AbstractCegarLoop]: Interpolant automaton has 6 states [2018-11-28 13:06:49,994 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2018-11-28 13:06:49,994 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=12, Invalid=18, Unknown=0, NotChecked=0, Total=30 [2018-11-28 13:06:49,994 INFO L87 Difference]: Start difference. First operand 114 states and 132 transitions. Second operand 6 states. [2018-11-28 13:06:50,024 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-28 13:06:50,024 INFO L93 Difference]: Finished difference Result 216 states and 260 transitions. [2018-11-28 13:06:50,025 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2018-11-28 13:06:50,025 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 48 [2018-11-28 13:06:50,025 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-28 13:06:50,027 INFO L225 Difference]: With dead ends: 216 [2018-11-28 13:06:50,027 INFO L226 Difference]: Without dead ends: 131 [2018-11-28 13:06:50,027 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 52 GetRequests, 48 SyntacticMatches, 0 SemanticMatches, 4 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=12, Invalid=18, Unknown=0, NotChecked=0, Total=30 [2018-11-28 13:06:50,028 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 131 states. [2018-11-28 13:06:50,032 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 131 to 118. [2018-11-28 13:06:50,032 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 118 states. [2018-11-28 13:06:50,032 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 118 states to 118 states and 136 transitions. [2018-11-28 13:06:50,032 INFO L78 Accepts]: Start accepts. Automaton has 118 states and 136 transitions. Word has length 48 [2018-11-28 13:06:50,033 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-28 13:06:50,033 INFO L480 AbstractCegarLoop]: Abstraction has 118 states and 136 transitions. [2018-11-28 13:06:50,033 INFO L481 AbstractCegarLoop]: Interpolant automaton has 6 states. [2018-11-28 13:06:50,034 INFO L276 IsEmpty]: Start isEmpty. Operand 118 states and 136 transitions. [2018-11-28 13:06:50,034 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 53 [2018-11-28 13:06:50,034 INFO L394 BasicCegarLoop]: Found error trace [2018-11-28 13:06:50,035 INFO L402 BasicCegarLoop]: trace histogram [4, 4, 4, 3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-28 13:06:50,035 INFO L423 AbstractCegarLoop]: === Iteration 17 === [single_argvErr6ASSERT_VIOLATIONINTEGER_OVERFLOW, single_argvErr0ASSERT_VIOLATIONINTEGER_OVERFLOW, single_argvErr2ASSERT_VIOLATIONINTEGER_OVERFLOW, single_argvErr4ASSERT_VIOLATIONINTEGER_OVERFLOW, single_argvErr5ASSERT_VIOLATIONINTEGER_OVERFLOW, single_argvErr1ASSERT_VIOLATIONINTEGER_OVERFLOW, single_argvErr3ASSERT_VIOLATIONINTEGER_OVERFLOW, single_argvErr7ASSERT_VIOLATIONINTEGER_OVERFLOW, single_argvErr8ASSERT_VIOLATIONINTEGER_OVERFLOW, single_argvErr9ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr6ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr10ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr5ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr11ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr7ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr0ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr15ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr8ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr14ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr1ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr4ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr3ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr2ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr9ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr12ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr13ASSERT_VIOLATIONINTEGER_OVERFLOW, dirnameErr0ASSERT_VIOLATIONINTEGER_OVERFLOW, dirnameErr1ASSERT_VIOLATIONINTEGER_OVERFLOW]=== [2018-11-28 13:06:50,035 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-28 13:06:50,035 INFO L82 PathProgramCache]: Analyzing trace with hash 1247548610, now seen corresponding path program 1 times [2018-11-28 13:06:50,035 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-28 13:06:50,035 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-28 13:06:50,036 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 13:06:50,036 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-28 13:06:50,037 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 13:06:50,053 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-28 13:06:50,102 INFO L134 CoverageAnalysis]: Checked inductivity of 35 backedges. 1 proven. 12 refuted. 0 times theorem prover too weak. 22 trivial. 0 not checked. [2018-11-28 13:06:50,102 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-28 13:06:50,102 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_b218a3f8-accd-4719-941b-ce9fe174b24c/bin-2019/uautomizer/z3 Starting monitored process 6 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 6 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-28 13:06:50,110 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-28 13:06:50,201 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-28 13:06:50,206 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-28 13:06:50,245 INFO L134 CoverageAnalysis]: Checked inductivity of 35 backedges. 0 proven. 22 refuted. 0 times theorem prover too weak. 13 trivial. 0 not checked. [2018-11-28 13:06:50,262 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-11-28 13:06:50,262 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [6, 7] total 11 [2018-11-28 13:06:50,262 INFO L459 AbstractCegarLoop]: Interpolant automaton has 11 states [2018-11-28 13:06:50,262 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 11 interpolants. [2018-11-28 13:06:50,262 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=35, Invalid=75, Unknown=0, NotChecked=0, Total=110 [2018-11-28 13:06:50,263 INFO L87 Difference]: Start difference. First operand 118 states and 136 transitions. Second operand 11 states. [2018-11-28 13:06:50,311 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-28 13:06:50,312 INFO L93 Difference]: Finished difference Result 227 states and 264 transitions. [2018-11-28 13:06:50,313 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 11 states. [2018-11-28 13:06:50,313 INFO L78 Accepts]: Start accepts. Automaton has 11 states. Word has length 52 [2018-11-28 13:06:50,313 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-28 13:06:50,314 INFO L225 Difference]: With dead ends: 227 [2018-11-28 13:06:50,314 INFO L226 Difference]: Without dead ends: 128 [2018-11-28 13:06:50,314 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 57 GetRequests, 48 SyntacticMatches, 0 SemanticMatches, 9 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 15 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=35, Invalid=75, Unknown=0, NotChecked=0, Total=110 [2018-11-28 13:06:50,315 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 128 states. [2018-11-28 13:06:50,318 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 128 to 124. [2018-11-28 13:06:50,318 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 124 states. [2018-11-28 13:06:50,318 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 124 states to 124 states and 142 transitions. [2018-11-28 13:06:50,318 INFO L78 Accepts]: Start accepts. Automaton has 124 states and 142 transitions. Word has length 52 [2018-11-28 13:06:50,319 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-28 13:06:50,319 INFO L480 AbstractCegarLoop]: Abstraction has 124 states and 142 transitions. [2018-11-28 13:06:50,319 INFO L481 AbstractCegarLoop]: Interpolant automaton has 11 states. [2018-11-28 13:06:50,319 INFO L276 IsEmpty]: Start isEmpty. Operand 124 states and 142 transitions. [2018-11-28 13:06:50,319 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 59 [2018-11-28 13:06:50,319 INFO L394 BasicCegarLoop]: Found error trace [2018-11-28 13:06:50,320 INFO L402 BasicCegarLoop]: trace histogram [5, 5, 5, 4, 4, 4, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-28 13:06:50,320 INFO L423 AbstractCegarLoop]: === Iteration 18 === [single_argvErr6ASSERT_VIOLATIONINTEGER_OVERFLOW, single_argvErr0ASSERT_VIOLATIONINTEGER_OVERFLOW, single_argvErr2ASSERT_VIOLATIONINTEGER_OVERFLOW, single_argvErr4ASSERT_VIOLATIONINTEGER_OVERFLOW, single_argvErr5ASSERT_VIOLATIONINTEGER_OVERFLOW, single_argvErr1ASSERT_VIOLATIONINTEGER_OVERFLOW, single_argvErr3ASSERT_VIOLATIONINTEGER_OVERFLOW, single_argvErr7ASSERT_VIOLATIONINTEGER_OVERFLOW, single_argvErr8ASSERT_VIOLATIONINTEGER_OVERFLOW, single_argvErr9ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr6ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr10ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr5ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr11ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr7ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr0ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr15ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr8ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr14ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr1ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr4ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr3ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr2ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr9ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr12ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr13ASSERT_VIOLATIONINTEGER_OVERFLOW, dirnameErr0ASSERT_VIOLATIONINTEGER_OVERFLOW, dirnameErr1ASSERT_VIOLATIONINTEGER_OVERFLOW]=== [2018-11-28 13:06:50,320 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-28 13:06:50,320 INFO L82 PathProgramCache]: Analyzing trace with hash 2080661809, now seen corresponding path program 2 times [2018-11-28 13:06:50,320 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-28 13:06:50,321 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-28 13:06:50,322 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 13:06:50,322 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-28 13:06:50,322 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 13:06:50,341 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-28 13:06:50,396 INFO L134 CoverageAnalysis]: Checked inductivity of 58 backedges. 1 proven. 22 refuted. 0 times theorem prover too weak. 35 trivial. 0 not checked. [2018-11-28 13:06:50,396 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-28 13:06:50,396 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_b218a3f8-accd-4719-941b-ce9fe174b24c/bin-2019/uautomizer/z3 Starting monitored process 7 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 7 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-28 13:06:50,404 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-11-28 13:06:50,536 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2018-11-28 13:06:50,536 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-11-28 13:06:50,540 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-28 13:06:50,582 INFO L134 CoverageAnalysis]: Checked inductivity of 58 backedges. 0 proven. 35 refuted. 0 times theorem prover too weak. 23 trivial. 0 not checked. [2018-11-28 13:06:50,598 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-11-28 13:06:50,598 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [7, 8] total 13 [2018-11-28 13:06:50,598 INFO L459 AbstractCegarLoop]: Interpolant automaton has 13 states [2018-11-28 13:06:50,598 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 13 interpolants. [2018-11-28 13:06:50,598 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=48, Invalid=108, Unknown=0, NotChecked=0, Total=156 [2018-11-28 13:06:50,598 INFO L87 Difference]: Start difference. First operand 124 states and 142 transitions. Second operand 13 states. [2018-11-28 13:06:50,655 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-28 13:06:50,655 INFO L93 Difference]: Finished difference Result 236 states and 273 transitions. [2018-11-28 13:06:50,658 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 13 states. [2018-11-28 13:06:50,658 INFO L78 Accepts]: Start accepts. Automaton has 13 states. Word has length 58 [2018-11-28 13:06:50,659 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-28 13:06:50,659 INFO L225 Difference]: With dead ends: 236 [2018-11-28 13:06:50,659 INFO L226 Difference]: Without dead ends: 134 [2018-11-28 13:06:50,660 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 64 GetRequests, 53 SyntacticMatches, 0 SemanticMatches, 11 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 24 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=48, Invalid=108, Unknown=0, NotChecked=0, Total=156 [2018-11-28 13:06:50,660 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 134 states. [2018-11-28 13:06:50,664 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 134 to 130. [2018-11-28 13:06:50,665 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 130 states. [2018-11-28 13:06:50,665 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 130 states to 130 states and 148 transitions. [2018-11-28 13:06:50,665 INFO L78 Accepts]: Start accepts. Automaton has 130 states and 148 transitions. Word has length 58 [2018-11-28 13:06:50,666 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-28 13:06:50,666 INFO L480 AbstractCegarLoop]: Abstraction has 130 states and 148 transitions. [2018-11-28 13:06:50,666 INFO L481 AbstractCegarLoop]: Interpolant automaton has 13 states. [2018-11-28 13:06:50,666 INFO L276 IsEmpty]: Start isEmpty. Operand 130 states and 148 transitions. [2018-11-28 13:06:50,666 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 65 [2018-11-28 13:06:50,666 INFO L394 BasicCegarLoop]: Found error trace [2018-11-28 13:06:50,666 INFO L402 BasicCegarLoop]: trace histogram [6, 6, 6, 5, 5, 5, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-28 13:06:50,667 INFO L423 AbstractCegarLoop]: === Iteration 19 === [single_argvErr6ASSERT_VIOLATIONINTEGER_OVERFLOW, single_argvErr0ASSERT_VIOLATIONINTEGER_OVERFLOW, single_argvErr2ASSERT_VIOLATIONINTEGER_OVERFLOW, single_argvErr4ASSERT_VIOLATIONINTEGER_OVERFLOW, single_argvErr5ASSERT_VIOLATIONINTEGER_OVERFLOW, single_argvErr1ASSERT_VIOLATIONINTEGER_OVERFLOW, single_argvErr3ASSERT_VIOLATIONINTEGER_OVERFLOW, single_argvErr7ASSERT_VIOLATIONINTEGER_OVERFLOW, single_argvErr8ASSERT_VIOLATIONINTEGER_OVERFLOW, single_argvErr9ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr6ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr10ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr5ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr11ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr7ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr0ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr15ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr8ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr14ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr1ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr4ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr3ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr2ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr9ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr12ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr13ASSERT_VIOLATIONINTEGER_OVERFLOW, dirnameErr0ASSERT_VIOLATIONINTEGER_OVERFLOW, dirnameErr1ASSERT_VIOLATIONINTEGER_OVERFLOW]=== [2018-11-28 13:06:50,667 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-28 13:06:50,667 INFO L82 PathProgramCache]: Analyzing trace with hash -1647139486, now seen corresponding path program 3 times [2018-11-28 13:06:50,667 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-28 13:06:50,668 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-28 13:06:50,669 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 13:06:50,669 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-28 13:06:50,669 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 13:06:50,693 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-28 13:06:50,764 INFO L134 CoverageAnalysis]: Checked inductivity of 87 backedges. 1 proven. 35 refuted. 0 times theorem prover too weak. 51 trivial. 0 not checked. [2018-11-28 13:06:50,764 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-28 13:06:50,764 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_b218a3f8-accd-4719-941b-ce9fe174b24c/bin-2019/uautomizer/z3 Starting monitored process 8 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 8 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-28 13:06:50,782 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-11-28 13:06:52,738 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 7 check-sat command(s) [2018-11-28 13:06:52,739 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-11-28 13:06:52,743 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-28 13:06:52,751 INFO L134 CoverageAnalysis]: Checked inductivity of 87 backedges. 1 proven. 35 refuted. 0 times theorem prover too weak. 51 trivial. 0 not checked. [2018-11-28 13:06:52,769 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-11-28 13:06:52,769 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [8, 8] total 9 [2018-11-28 13:06:52,769 INFO L459 AbstractCegarLoop]: Interpolant automaton has 9 states [2018-11-28 13:06:52,770 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 9 interpolants. [2018-11-28 13:06:52,770 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=36, Invalid=36, Unknown=0, NotChecked=0, Total=72 [2018-11-28 13:06:52,770 INFO L87 Difference]: Start difference. First operand 130 states and 148 transitions. Second operand 9 states. [2018-11-28 13:06:52,794 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-28 13:06:52,794 INFO L93 Difference]: Finished difference Result 230 states and 266 transitions. [2018-11-28 13:06:52,802 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 8 states. [2018-11-28 13:06:52,802 INFO L78 Accepts]: Start accepts. Automaton has 9 states. Word has length 64 [2018-11-28 13:06:52,802 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-28 13:06:52,802 INFO L225 Difference]: With dead ends: 230 [2018-11-28 13:06:52,803 INFO L226 Difference]: Without dead ends: 135 [2018-11-28 13:06:52,803 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 71 GetRequests, 64 SyntacticMatches, 0 SemanticMatches, 7 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 8 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=36, Invalid=36, Unknown=0, NotChecked=0, Total=72 [2018-11-28 13:06:52,803 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 135 states. [2018-11-28 13:06:52,809 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 135 to 133. [2018-11-28 13:06:52,809 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 133 states. [2018-11-28 13:06:52,809 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 133 states to 133 states and 151 transitions. [2018-11-28 13:06:52,810 INFO L78 Accepts]: Start accepts. Automaton has 133 states and 151 transitions. Word has length 64 [2018-11-28 13:06:52,810 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-28 13:06:52,810 INFO L480 AbstractCegarLoop]: Abstraction has 133 states and 151 transitions. [2018-11-28 13:06:52,810 INFO L481 AbstractCegarLoop]: Interpolant automaton has 9 states. [2018-11-28 13:06:52,810 INFO L276 IsEmpty]: Start isEmpty. Operand 133 states and 151 transitions. [2018-11-28 13:06:52,810 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 68 [2018-11-28 13:06:52,811 INFO L394 BasicCegarLoop]: Found error trace [2018-11-28 13:06:52,811 INFO L402 BasicCegarLoop]: trace histogram [6, 6, 6, 6, 6, 6, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-28 13:06:52,811 INFO L423 AbstractCegarLoop]: === Iteration 20 === [single_argvErr6ASSERT_VIOLATIONINTEGER_OVERFLOW, single_argvErr0ASSERT_VIOLATIONINTEGER_OVERFLOW, single_argvErr2ASSERT_VIOLATIONINTEGER_OVERFLOW, single_argvErr4ASSERT_VIOLATIONINTEGER_OVERFLOW, single_argvErr5ASSERT_VIOLATIONINTEGER_OVERFLOW, single_argvErr1ASSERT_VIOLATIONINTEGER_OVERFLOW, single_argvErr3ASSERT_VIOLATIONINTEGER_OVERFLOW, single_argvErr7ASSERT_VIOLATIONINTEGER_OVERFLOW, single_argvErr8ASSERT_VIOLATIONINTEGER_OVERFLOW, single_argvErr9ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr6ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr10ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr5ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr11ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr7ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr0ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr15ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr8ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr14ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr1ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr4ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr3ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr2ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr9ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr12ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr13ASSERT_VIOLATIONINTEGER_OVERFLOW, dirnameErr0ASSERT_VIOLATIONINTEGER_OVERFLOW, dirnameErr1ASSERT_VIOLATIONINTEGER_OVERFLOW]=== [2018-11-28 13:06:52,811 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-28 13:06:52,811 INFO L82 PathProgramCache]: Analyzing trace with hash 1571808757, now seen corresponding path program 4 times [2018-11-28 13:06:52,811 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-28 13:06:52,811 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-28 13:06:52,812 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 13:06:52,812 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-28 13:06:52,813 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 13:06:52,836 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-28 13:06:52,907 INFO L134 CoverageAnalysis]: Checked inductivity of 103 backedges. 0 proven. 51 refuted. 0 times theorem prover too weak. 52 trivial. 0 not checked. [2018-11-28 13:06:52,907 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-28 13:06:52,907 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_b218a3f8-accd-4719-941b-ce9fe174b24c/bin-2019/uautomizer/z3 Starting monitored process 9 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 9 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-28 13:06:52,918 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-11-28 13:06:53,046 INFO L249 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-11-28 13:06:53,046 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-11-28 13:06:53,052 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-28 13:06:53,078 INFO L134 CoverageAnalysis]: Checked inductivity of 103 backedges. 0 proven. 51 refuted. 0 times theorem prover too weak. 52 trivial. 0 not checked. [2018-11-28 13:06:53,103 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-11-28 13:06:53,103 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [9, 9] total 10 [2018-11-28 13:06:53,104 INFO L459 AbstractCegarLoop]: Interpolant automaton has 10 states [2018-11-28 13:06:53,104 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 10 interpolants. [2018-11-28 13:06:53,104 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=45, Invalid=45, Unknown=0, NotChecked=0, Total=90 [2018-11-28 13:06:53,104 INFO L87 Difference]: Start difference. First operand 133 states and 151 transitions. Second operand 10 states. [2018-11-28 13:06:53,156 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-28 13:06:53,157 INFO L93 Difference]: Finished difference Result 246 states and 282 transitions. [2018-11-28 13:06:53,157 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2018-11-28 13:06:53,157 INFO L78 Accepts]: Start accepts. Automaton has 10 states. Word has length 67 [2018-11-28 13:06:53,158 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-28 13:06:53,158 INFO L225 Difference]: With dead ends: 246 [2018-11-28 13:06:53,158 INFO L226 Difference]: Without dead ends: 138 [2018-11-28 13:06:53,159 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 75 GetRequests, 67 SyntacticMatches, 0 SemanticMatches, 8 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 10 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=45, Invalid=45, Unknown=0, NotChecked=0, Total=90 [2018-11-28 13:06:53,159 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 138 states. [2018-11-28 13:06:53,163 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 138 to 136. [2018-11-28 13:06:53,163 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 136 states. [2018-11-28 13:06:53,164 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 136 states to 136 states and 154 transitions. [2018-11-28 13:06:53,164 INFO L78 Accepts]: Start accepts. Automaton has 136 states and 154 transitions. Word has length 67 [2018-11-28 13:06:53,164 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-28 13:06:53,164 INFO L480 AbstractCegarLoop]: Abstraction has 136 states and 154 transitions. [2018-11-28 13:06:53,164 INFO L481 AbstractCegarLoop]: Interpolant automaton has 10 states. [2018-11-28 13:06:53,165 INFO L276 IsEmpty]: Start isEmpty. Operand 136 states and 154 transitions. [2018-11-28 13:06:53,165 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 71 [2018-11-28 13:06:53,165 INFO L394 BasicCegarLoop]: Found error trace [2018-11-28 13:06:53,165 INFO L402 BasicCegarLoop]: trace histogram [7, 7, 7, 6, 6, 6, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-28 13:06:53,166 INFO L423 AbstractCegarLoop]: === Iteration 21 === [single_argvErr6ASSERT_VIOLATIONINTEGER_OVERFLOW, single_argvErr0ASSERT_VIOLATIONINTEGER_OVERFLOW, single_argvErr2ASSERT_VIOLATIONINTEGER_OVERFLOW, single_argvErr4ASSERT_VIOLATIONINTEGER_OVERFLOW, single_argvErr5ASSERT_VIOLATIONINTEGER_OVERFLOW, single_argvErr1ASSERT_VIOLATIONINTEGER_OVERFLOW, single_argvErr3ASSERT_VIOLATIONINTEGER_OVERFLOW, single_argvErr7ASSERT_VIOLATIONINTEGER_OVERFLOW, single_argvErr8ASSERT_VIOLATIONINTEGER_OVERFLOW, single_argvErr9ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr6ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr10ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr5ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr11ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr7ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr0ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr15ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr8ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr14ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr1ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr4ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr3ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr2ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr9ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr12ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr13ASSERT_VIOLATIONINTEGER_OVERFLOW, dirnameErr0ASSERT_VIOLATIONINTEGER_OVERFLOW, dirnameErr1ASSERT_VIOLATIONINTEGER_OVERFLOW]=== [2018-11-28 13:06:53,166 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-28 13:06:53,166 INFO L82 PathProgramCache]: Analyzing trace with hash 312181393, now seen corresponding path program 5 times [2018-11-28 13:06:53,166 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-28 13:06:53,166 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-28 13:06:53,167 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 13:06:53,167 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-28 13:06:53,167 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 13:06:53,190 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-28 13:06:53,273 INFO L134 CoverageAnalysis]: Checked inductivity of 122 backedges. 0 proven. 70 refuted. 0 times theorem prover too weak. 52 trivial. 0 not checked. [2018-11-28 13:06:53,273 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-28 13:06:53,273 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_b218a3f8-accd-4719-941b-ce9fe174b24c/bin-2019/uautomizer/z3 Starting monitored process 10 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 10 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-28 13:06:53,284 INFO L103 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-11-28 13:06:56,899 INFO L249 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 7 check-sat command(s) [2018-11-28 13:06:56,899 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-11-28 13:06:56,903 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-28 13:06:56,961 INFO L134 CoverageAnalysis]: Checked inductivity of 122 backedges. 1 proven. 51 refuted. 0 times theorem prover too weak. 70 trivial. 0 not checked. [2018-11-28 13:06:56,978 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-11-28 13:06:56,978 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [10, 9] total 17 [2018-11-28 13:06:56,978 INFO L459 AbstractCegarLoop]: Interpolant automaton has 17 states [2018-11-28 13:06:56,978 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 17 interpolants. [2018-11-28 13:06:56,979 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=80, Invalid=192, Unknown=0, NotChecked=0, Total=272 [2018-11-28 13:06:56,979 INFO L87 Difference]: Start difference. First operand 136 states and 154 transitions. Second operand 17 states. [2018-11-28 13:06:57,043 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-28 13:06:57,043 INFO L93 Difference]: Finished difference Result 254 states and 291 transitions. [2018-11-28 13:06:57,044 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 17 states. [2018-11-28 13:06:57,045 INFO L78 Accepts]: Start accepts. Automaton has 17 states. Word has length 70 [2018-11-28 13:06:57,045 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-28 13:06:57,045 INFO L225 Difference]: With dead ends: 254 [2018-11-28 13:06:57,045 INFO L226 Difference]: Without dead ends: 146 [2018-11-28 13:06:57,046 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 79 GetRequests, 64 SyntacticMatches, 0 SemanticMatches, 15 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 49 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=80, Invalid=192, Unknown=0, NotChecked=0, Total=272 [2018-11-28 13:06:57,046 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 146 states. [2018-11-28 13:06:57,057 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 146 to 142. [2018-11-28 13:06:57,057 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 142 states. [2018-11-28 13:06:57,058 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 142 states to 142 states and 160 transitions. [2018-11-28 13:06:57,058 INFO L78 Accepts]: Start accepts. Automaton has 142 states and 160 transitions. Word has length 70 [2018-11-28 13:06:57,058 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-28 13:06:57,058 INFO L480 AbstractCegarLoop]: Abstraction has 142 states and 160 transitions. [2018-11-28 13:06:57,059 INFO L481 AbstractCegarLoop]: Interpolant automaton has 17 states. [2018-11-28 13:06:57,059 INFO L276 IsEmpty]: Start isEmpty. Operand 142 states and 160 transitions. [2018-11-28 13:06:57,059 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 77 [2018-11-28 13:06:57,060 INFO L394 BasicCegarLoop]: Found error trace [2018-11-28 13:06:57,060 INFO L402 BasicCegarLoop]: trace histogram [8, 8, 8, 7, 7, 7, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-28 13:06:57,060 INFO L423 AbstractCegarLoop]: === Iteration 22 === [single_argvErr6ASSERT_VIOLATIONINTEGER_OVERFLOW, single_argvErr0ASSERT_VIOLATIONINTEGER_OVERFLOW, single_argvErr2ASSERT_VIOLATIONINTEGER_OVERFLOW, single_argvErr4ASSERT_VIOLATIONINTEGER_OVERFLOW, single_argvErr5ASSERT_VIOLATIONINTEGER_OVERFLOW, single_argvErr1ASSERT_VIOLATIONINTEGER_OVERFLOW, single_argvErr3ASSERT_VIOLATIONINTEGER_OVERFLOW, single_argvErr7ASSERT_VIOLATIONINTEGER_OVERFLOW, single_argvErr8ASSERT_VIOLATIONINTEGER_OVERFLOW, single_argvErr9ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr6ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr10ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr5ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr11ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr7ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr0ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr15ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr8ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr14ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr1ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr4ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr3ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr2ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr9ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr12ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr13ASSERT_VIOLATIONINTEGER_OVERFLOW, dirnameErr0ASSERT_VIOLATIONINTEGER_OVERFLOW, dirnameErr1ASSERT_VIOLATIONINTEGER_OVERFLOW]=== [2018-11-28 13:06:57,060 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-28 13:06:57,060 INFO L82 PathProgramCache]: Analyzing trace with hash 1501953538, now seen corresponding path program 6 times [2018-11-28 13:06:57,061 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-28 13:06:57,061 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-28 13:06:57,062 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 13:06:57,062 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-28 13:06:57,062 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 13:06:57,106 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-28 13:06:57,205 INFO L134 CoverageAnalysis]: Checked inductivity of 163 backedges. 1 proven. 70 refuted. 0 times theorem prover too weak. 92 trivial. 0 not checked. [2018-11-28 13:06:57,206 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-28 13:06:57,206 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_b218a3f8-accd-4719-941b-ce9fe174b24c/bin-2019/uautomizer/z3 Starting monitored process 11 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 11 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-28 13:06:57,215 INFO L103 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-11-28 13:07:02,359 INFO L249 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 9 check-sat command(s) [2018-11-28 13:07:02,359 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-11-28 13:07:02,366 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-28 13:07:02,434 INFO L134 CoverageAnalysis]: Checked inductivity of 163 backedges. 0 proven. 92 refuted. 0 times theorem prover too weak. 71 trivial. 0 not checked. [2018-11-28 13:07:02,453 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-11-28 13:07:02,453 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [10, 11] total 19 [2018-11-28 13:07:02,453 INFO L459 AbstractCegarLoop]: Interpolant automaton has 19 states [2018-11-28 13:07:02,453 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 19 interpolants. [2018-11-28 13:07:02,454 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=99, Invalid=243, Unknown=0, NotChecked=0, Total=342 [2018-11-28 13:07:02,454 INFO L87 Difference]: Start difference. First operand 142 states and 160 transitions. Second operand 19 states. [2018-11-28 13:07:02,525 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-28 13:07:02,526 INFO L93 Difference]: Finished difference Result 263 states and 300 transitions. [2018-11-28 13:07:02,526 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 19 states. [2018-11-28 13:07:02,526 INFO L78 Accepts]: Start accepts. Automaton has 19 states. Word has length 76 [2018-11-28 13:07:02,527 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-28 13:07:02,527 INFO L225 Difference]: With dead ends: 263 [2018-11-28 13:07:02,527 INFO L226 Difference]: Without dead ends: 152 [2018-11-28 13:07:02,528 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 85 GetRequests, 67 SyntacticMatches, 1 SemanticMatches, 17 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 70 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=99, Invalid=243, Unknown=0, NotChecked=0, Total=342 [2018-11-28 13:07:02,528 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 152 states. [2018-11-28 13:07:02,533 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 152 to 148. [2018-11-28 13:07:02,533 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 148 states. [2018-11-28 13:07:02,534 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 148 states to 148 states and 166 transitions. [2018-11-28 13:07:02,534 INFO L78 Accepts]: Start accepts. Automaton has 148 states and 166 transitions. Word has length 76 [2018-11-28 13:07:02,534 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-28 13:07:02,534 INFO L480 AbstractCegarLoop]: Abstraction has 148 states and 166 transitions. [2018-11-28 13:07:02,534 INFO L481 AbstractCegarLoop]: Interpolant automaton has 19 states. [2018-11-28 13:07:02,535 INFO L276 IsEmpty]: Start isEmpty. Operand 148 states and 166 transitions. [2018-11-28 13:07:02,535 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 83 [2018-11-28 13:07:02,535 INFO L394 BasicCegarLoop]: Found error trace [2018-11-28 13:07:02,535 INFO L402 BasicCegarLoop]: trace histogram [9, 9, 9, 8, 8, 8, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-28 13:07:02,536 INFO L423 AbstractCegarLoop]: === Iteration 23 === [single_argvErr6ASSERT_VIOLATIONINTEGER_OVERFLOW, single_argvErr0ASSERT_VIOLATIONINTEGER_OVERFLOW, single_argvErr2ASSERT_VIOLATIONINTEGER_OVERFLOW, single_argvErr4ASSERT_VIOLATIONINTEGER_OVERFLOW, single_argvErr5ASSERT_VIOLATIONINTEGER_OVERFLOW, single_argvErr1ASSERT_VIOLATIONINTEGER_OVERFLOW, single_argvErr3ASSERT_VIOLATIONINTEGER_OVERFLOW, single_argvErr7ASSERT_VIOLATIONINTEGER_OVERFLOW, single_argvErr8ASSERT_VIOLATIONINTEGER_OVERFLOW, single_argvErr9ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr6ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr10ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr5ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr11ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr7ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr0ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr15ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr8ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr14ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr1ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr4ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr3ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr2ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr9ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr12ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr13ASSERT_VIOLATIONINTEGER_OVERFLOW, dirnameErr0ASSERT_VIOLATIONINTEGER_OVERFLOW, dirnameErr1ASSERT_VIOLATIONINTEGER_OVERFLOW]=== [2018-11-28 13:07:02,536 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-28 13:07:02,536 INFO L82 PathProgramCache]: Analyzing trace with hash 631233521, now seen corresponding path program 7 times [2018-11-28 13:07:02,536 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-28 13:07:02,536 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-28 13:07:02,537 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 13:07:02,537 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-28 13:07:02,537 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 13:07:02,567 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-28 13:07:02,683 INFO L134 CoverageAnalysis]: Checked inductivity of 210 backedges. 1 proven. 92 refuted. 0 times theorem prover too weak. 117 trivial. 0 not checked. [2018-11-28 13:07:02,683 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-28 13:07:02,683 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_b218a3f8-accd-4719-941b-ce9fe174b24c/bin-2019/uautomizer/z3 Starting monitored process 12 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 12 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-28 13:07:02,693 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-28 13:07:02,813 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-28 13:07:02,818 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-28 13:07:02,906 INFO L134 CoverageAnalysis]: Checked inductivity of 210 backedges. 0 proven. 117 refuted. 0 times theorem prover too weak. 93 trivial. 0 not checked. [2018-11-28 13:07:02,923 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-11-28 13:07:02,923 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [11, 12] total 21 [2018-11-28 13:07:02,923 INFO L459 AbstractCegarLoop]: Interpolant automaton has 21 states [2018-11-28 13:07:02,923 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 21 interpolants. [2018-11-28 13:07:02,923 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=120, Invalid=300, Unknown=0, NotChecked=0, Total=420 [2018-11-28 13:07:02,924 INFO L87 Difference]: Start difference. First operand 148 states and 166 transitions. Second operand 21 states. [2018-11-28 13:07:02,995 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-28 13:07:02,995 INFO L93 Difference]: Finished difference Result 270 states and 307 transitions. [2018-11-28 13:07:02,996 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 21 states. [2018-11-28 13:07:02,996 INFO L78 Accepts]: Start accepts. Automaton has 21 states. Word has length 82 [2018-11-28 13:07:02,996 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-28 13:07:02,997 INFO L225 Difference]: With dead ends: 270 [2018-11-28 13:07:02,997 INFO L226 Difference]: Without dead ends: 156 [2018-11-28 13:07:02,997 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 92 GetRequests, 73 SyntacticMatches, 0 SemanticMatches, 19 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 80 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=120, Invalid=300, Unknown=0, NotChecked=0, Total=420 [2018-11-28 13:07:02,998 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 156 states. [2018-11-28 13:07:03,001 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 156 to 154. [2018-11-28 13:07:03,001 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 154 states. [2018-11-28 13:07:03,002 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 154 states to 154 states and 172 transitions. [2018-11-28 13:07:03,002 INFO L78 Accepts]: Start accepts. Automaton has 154 states and 172 transitions. Word has length 82 [2018-11-28 13:07:03,002 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-28 13:07:03,002 INFO L480 AbstractCegarLoop]: Abstraction has 154 states and 172 transitions. [2018-11-28 13:07:03,002 INFO L481 AbstractCegarLoop]: Interpolant automaton has 21 states. [2018-11-28 13:07:03,002 INFO L276 IsEmpty]: Start isEmpty. Operand 154 states and 172 transitions. [2018-11-28 13:07:03,003 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 89 [2018-11-28 13:07:03,003 INFO L394 BasicCegarLoop]: Found error trace [2018-11-28 13:07:03,003 INFO L402 BasicCegarLoop]: trace histogram [10, 10, 10, 9, 9, 9, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-28 13:07:03,003 INFO L423 AbstractCegarLoop]: === Iteration 24 === [single_argvErr6ASSERT_VIOLATIONINTEGER_OVERFLOW, single_argvErr0ASSERT_VIOLATIONINTEGER_OVERFLOW, single_argvErr2ASSERT_VIOLATIONINTEGER_OVERFLOW, single_argvErr4ASSERT_VIOLATIONINTEGER_OVERFLOW, single_argvErr5ASSERT_VIOLATIONINTEGER_OVERFLOW, single_argvErr1ASSERT_VIOLATIONINTEGER_OVERFLOW, single_argvErr3ASSERT_VIOLATIONINTEGER_OVERFLOW, single_argvErr7ASSERT_VIOLATIONINTEGER_OVERFLOW, single_argvErr8ASSERT_VIOLATIONINTEGER_OVERFLOW, single_argvErr9ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr6ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr10ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr5ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr11ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr7ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr0ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr15ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr8ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr14ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr1ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr4ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr3ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr2ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr9ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr12ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr13ASSERT_VIOLATIONINTEGER_OVERFLOW, dirnameErr0ASSERT_VIOLATIONINTEGER_OVERFLOW, dirnameErr1ASSERT_VIOLATIONINTEGER_OVERFLOW]=== [2018-11-28 13:07:03,003 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-28 13:07:03,003 INFO L82 PathProgramCache]: Analyzing trace with hash 1461722786, now seen corresponding path program 8 times [2018-11-28 13:07:03,003 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-28 13:07:03,003 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-28 13:07:03,004 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 13:07:03,004 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-28 13:07:03,004 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 13:07:03,024 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-28 13:07:03,093 INFO L134 CoverageAnalysis]: Checked inductivity of 263 backedges. 1 proven. 117 refuted. 0 times theorem prover too weak. 145 trivial. 0 not checked. [2018-11-28 13:07:03,093 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-28 13:07:03,093 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_b218a3f8-accd-4719-941b-ce9fe174b24c/bin-2019/uautomizer/z3 Starting monitored process 13 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 13 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-28 13:07:03,107 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-11-28 13:07:03,236 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2018-11-28 13:07:03,236 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-11-28 13:07:03,241 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-28 13:07:03,260 INFO L134 CoverageAnalysis]: Checked inductivity of 263 backedges. 1 proven. 117 refuted. 0 times theorem prover too weak. 145 trivial. 0 not checked. [2018-11-28 13:07:03,279 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-11-28 13:07:03,279 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [12, 12] total 13 [2018-11-28 13:07:03,279 INFO L459 AbstractCegarLoop]: Interpolant automaton has 13 states [2018-11-28 13:07:03,280 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 13 interpolants. [2018-11-28 13:07:03,280 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=78, Invalid=78, Unknown=0, NotChecked=0, Total=156 [2018-11-28 13:07:03,280 INFO L87 Difference]: Start difference. First operand 154 states and 172 transitions. Second operand 13 states. [2018-11-28 13:07:03,338 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-28 13:07:03,338 INFO L93 Difference]: Finished difference Result 264 states and 300 transitions. [2018-11-28 13:07:03,339 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 12 states. [2018-11-28 13:07:03,339 INFO L78 Accepts]: Start accepts. Automaton has 13 states. Word has length 88 [2018-11-28 13:07:03,339 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-28 13:07:03,340 INFO L225 Difference]: With dead ends: 264 [2018-11-28 13:07:03,340 INFO L226 Difference]: Without dead ends: 157 [2018-11-28 13:07:03,340 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 99 GetRequests, 88 SyntacticMatches, 0 SemanticMatches, 11 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 16 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=78, Invalid=78, Unknown=0, NotChecked=0, Total=156 [2018-11-28 13:07:03,340 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 157 states. [2018-11-28 13:07:03,346 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 157 to 157. [2018-11-28 13:07:03,346 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 157 states. [2018-11-28 13:07:03,347 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 157 states to 157 states and 175 transitions. [2018-11-28 13:07:03,347 INFO L78 Accepts]: Start accepts. Automaton has 157 states and 175 transitions. Word has length 88 [2018-11-28 13:07:03,347 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-28 13:07:03,347 INFO L480 AbstractCegarLoop]: Abstraction has 157 states and 175 transitions. [2018-11-28 13:07:03,347 INFO L481 AbstractCegarLoop]: Interpolant automaton has 13 states. [2018-11-28 13:07:03,347 INFO L276 IsEmpty]: Start isEmpty. Operand 157 states and 175 transitions. [2018-11-28 13:07:03,348 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 92 [2018-11-28 13:07:03,348 INFO L394 BasicCegarLoop]: Found error trace [2018-11-28 13:07:03,348 INFO L402 BasicCegarLoop]: trace histogram [10, 10, 10, 10, 10, 10, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-28 13:07:03,348 INFO L423 AbstractCegarLoop]: === Iteration 25 === [single_argvErr6ASSERT_VIOLATIONINTEGER_OVERFLOW, single_argvErr0ASSERT_VIOLATIONINTEGER_OVERFLOW, single_argvErr2ASSERT_VIOLATIONINTEGER_OVERFLOW, single_argvErr4ASSERT_VIOLATIONINTEGER_OVERFLOW, single_argvErr5ASSERT_VIOLATIONINTEGER_OVERFLOW, single_argvErr1ASSERT_VIOLATIONINTEGER_OVERFLOW, single_argvErr3ASSERT_VIOLATIONINTEGER_OVERFLOW, single_argvErr7ASSERT_VIOLATIONINTEGER_OVERFLOW, single_argvErr8ASSERT_VIOLATIONINTEGER_OVERFLOW, single_argvErr9ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr6ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr10ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr5ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr11ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr7ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr0ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr15ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr8ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr14ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr1ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr4ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr3ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr2ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr9ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr12ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr13ASSERT_VIOLATIONINTEGER_OVERFLOW, dirnameErr0ASSERT_VIOLATIONINTEGER_OVERFLOW, dirnameErr1ASSERT_VIOLATIONINTEGER_OVERFLOW]=== [2018-11-28 13:07:03,348 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-28 13:07:03,349 INFO L82 PathProgramCache]: Analyzing trace with hash 1012982965, now seen corresponding path program 9 times [2018-11-28 13:07:03,349 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-28 13:07:03,349 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-28 13:07:03,350 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 13:07:03,350 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-28 13:07:03,350 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 13:07:03,723 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-28 13:07:05,030 INFO L134 CoverageAnalysis]: Checked inductivity of 291 backedges. 0 proven. 146 refuted. 0 times theorem prover too weak. 145 trivial. 0 not checked. [2018-11-28 13:07:05,030 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-28 13:07:05,030 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_b218a3f8-accd-4719-941b-ce9fe174b24c/bin-2019/uautomizer/z3 Starting monitored process 14 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 14 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-28 13:07:05,037 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-11-28 13:07:36,615 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 12 check-sat command(s) [2018-11-28 13:07:36,615 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-11-28 13:07:36,627 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-28 13:07:36,717 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 6 treesize of output 5 [2018-11-28 13:07:36,718 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-11-28 13:07:36,723 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-28 13:07:36,723 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 1 variables, input treesize:16, output treesize:15 [2018-11-28 13:07:36,758 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:07:36,760 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:07:36,761 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 2 select indices, 2 select index equivalence classes, 2 disjoint index pairs (out of 1 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 17 treesize of output 21 [2018-11-28 13:07:36,762 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-11-28 13:07:36,803 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 12 [2018-11-28 13:07:36,806 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 12 treesize of output 11 [2018-11-28 13:07:36,806 INFO L267 ElimStorePlain]: Start of recursive call 4: End of recursive call: and 1 xjuncts. [2018-11-28 13:07:36,810 INFO L267 ElimStorePlain]: Start of recursive call 3: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-28 13:07:36,828 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 12 [2018-11-28 13:07:36,830 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 12 treesize of output 11 [2018-11-28 13:07:36,830 INFO L267 ElimStorePlain]: Start of recursive call 6: End of recursive call: and 1 xjuncts. [2018-11-28 13:07:36,833 INFO L267 ElimStorePlain]: Start of recursive call 5: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-28 13:07:36,844 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-1 vars, 2 dim-2 vars, End of recursive call: and 1 xjuncts. [2018-11-28 13:07:36,845 INFO L202 ElimStorePlain]: Needed 6 recursive calls to eliminate 3 variables, input treesize:62, output treesize:52 [2018-11-28 13:07:36,898 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:07:36,902 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:07:36,904 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:07:36,906 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 3 select indices, 3 select index equivalence classes, 4 disjoint index pairs (out of 3 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 16 treesize of output 13 [2018-11-28 13:07:36,907 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-11-28 13:07:37,014 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 2 disjoint index pairs (out of 0 index pairs), introduced 2 new quantified variables, introduced 0 case distinctions, treesize of input 606 treesize of output 424 [2018-11-28 13:07:37,106 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:07:37,111 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 3 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 22 treesize of output 35 [2018-11-28 13:07:37,112 INFO L267 ElimStorePlain]: Start of recursive call 4: End of recursive call: and 1 xjuncts. [2018-11-28 13:07:37,148 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 2 select indices, 2 select index equivalence classes, 3 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 0 case distinctions, treesize of input 341 treesize of output 335 [2018-11-28 13:07:37,153 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 2 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 10 treesize of output 9 [2018-11-28 13:07:37,153 INFO L267 ElimStorePlain]: Start of recursive call 6: End of recursive call: and 1 xjuncts. [2018-11-28 13:07:37,202 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 3 select indices, 3 select index equivalence classes, 3 disjoint index pairs (out of 3 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 330 treesize of output 339 [2018-11-28 13:07:37,206 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 100 treesize of output 1 [2018-11-28 13:07:37,206 INFO L267 ElimStorePlain]: Start of recursive call 8: End of recursive call: and 1 xjuncts. [2018-11-28 13:07:37,221 INFO L267 ElimStorePlain]: Start of recursive call 7: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-28 13:07:37,233 INFO L267 ElimStorePlain]: Start of recursive call 5: 1 dim-1 vars, 1 dim-2 vars, End of recursive call: and 1 xjuncts. [2018-11-28 13:07:37,245 INFO L267 ElimStorePlain]: Start of recursive call 3: 1 dim-1 vars, 1 dim-2 vars, End of recursive call: and 1 xjuncts. [2018-11-28 13:07:37,287 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 2 disjoint index pairs (out of 0 index pairs), introduced 2 new quantified variables, introduced 0 case distinctions, treesize of input 207 treesize of output 121 [2018-11-28 13:07:37,317 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:07:37,318 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 22 treesize of output 35 [2018-11-28 13:07:37,318 INFO L267 ElimStorePlain]: Start of recursive call 10: End of recursive call: and 1 xjuncts. [2018-11-28 13:07:37,332 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 2 select indices, 2 select index equivalence classes, 3 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 0 case distinctions, treesize of input 102 treesize of output 96 [2018-11-28 13:07:37,335 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 10 treesize of output 9 [2018-11-28 13:07:37,335 INFO L267 ElimStorePlain]: Start of recursive call 12: End of recursive call: and 1 xjuncts. [2018-11-28 13:07:37,351 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 3 select indices, 3 select index equivalence classes, 3 disjoint index pairs (out of 3 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 91 treesize of output 108 [2018-11-28 13:07:37,353 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 48 treesize of output 1 [2018-11-28 13:07:37,354 INFO L267 ElimStorePlain]: Start of recursive call 14: End of recursive call: and 1 xjuncts. [2018-11-28 13:07:37,362 INFO L267 ElimStorePlain]: Start of recursive call 13: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-28 13:07:37,366 INFO L267 ElimStorePlain]: Start of recursive call 11: 1 dim-1 vars, 1 dim-2 vars, End of recursive call: and 1 xjuncts. [2018-11-28 13:07:37,371 INFO L267 ElimStorePlain]: Start of recursive call 9: 1 dim-1 vars, 1 dim-2 vars, End of recursive call: and 1 xjuncts. [2018-11-28 13:07:37,390 INFO L267 ElimStorePlain]: Start of recursive call 1: 2 dim-0 vars, 1 dim-1 vars, 2 dim-2 vars, End of recursive call: 1 dim-0 vars, and 1 xjuncts. [2018-11-28 13:07:37,390 INFO L202 ElimStorePlain]: Needed 14 recursive calls to eliminate 5 variables, input treesize:654, output treesize:103 [2018-11-28 13:07:37,457 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 3 select indices, 3 select index equivalence classes, 3 disjoint index pairs (out of 3 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 142 treesize of output 159 [2018-11-28 13:07:37,460 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 44 treesize of output 1 [2018-11-28 13:07:37,460 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-11-28 13:07:37,475 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-28 13:07:37,515 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 3 select indices, 3 select index equivalence classes, 3 disjoint index pairs (out of 3 index pairs), introduced 2 new quantified variables, introduced 0 case distinctions, treesize of input 108 treesize of output 102 [2018-11-28 13:07:37,517 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 42 treesize of output 41 [2018-11-28 13:07:37,517 INFO L267 ElimStorePlain]: Start of recursive call 5: End of recursive call: and 1 xjuncts. [2018-11-28 13:07:37,523 INFO L267 ElimStorePlain]: Start of recursive call 4: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-28 13:07:37,537 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-0 vars, 2 dim-2 vars, End of recursive call: 1 dim-0 vars, and 1 xjuncts. [2018-11-28 13:07:37,537 INFO L202 ElimStorePlain]: Needed 5 recursive calls to eliminate 3 variables, input treesize:210, output treesize:100 [2018-11-28 13:07:37,588 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 3 select indices, 3 select index equivalence classes, 3 disjoint index pairs (out of 3 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 150 treesize of output 167 [2018-11-28 13:07:37,591 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 48 treesize of output 1 [2018-11-28 13:07:37,591 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-11-28 13:07:37,601 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-28 13:07:37,627 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 3 select indices, 3 select index equivalence classes, 3 disjoint index pairs (out of 3 index pairs), introduced 2 new quantified variables, introduced 0 case distinctions, treesize of input 112 treesize of output 106 [2018-11-28 13:07:37,629 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 46 treesize of output 45 [2018-11-28 13:07:37,629 INFO L267 ElimStorePlain]: Start of recursive call 5: End of recursive call: and 1 xjuncts. [2018-11-28 13:07:37,639 INFO L267 ElimStorePlain]: Start of recursive call 4: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-28 13:07:37,653 INFO L267 ElimStorePlain]: Start of recursive call 1: 2 dim-0 vars, 2 dim-2 vars, End of recursive call: 1 dim-0 vars, and 1 xjuncts. [2018-11-28 13:07:37,653 INFO L202 ElimStorePlain]: Needed 5 recursive calls to eliminate 4 variables, input treesize:218, output treesize:100 [2018-11-28 13:07:37,678 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 3 select indices, 3 select index equivalence classes, 3 disjoint index pairs (out of 3 index pairs), introduced 2 new quantified variables, introduced 0 case distinctions, treesize of input 171 treesize of output 165 [2018-11-28 13:07:37,680 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 46 treesize of output 45 [2018-11-28 13:07:37,681 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-11-28 13:07:37,690 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-28 13:07:37,717 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 3 select indices, 3 select index equivalence classes, 3 disjoint index pairs (out of 3 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 91 treesize of output 108 [2018-11-28 13:07:37,719 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 48 treesize of output 1 [2018-11-28 13:07:37,719 INFO L267 ElimStorePlain]: Start of recursive call 5: End of recursive call: and 1 xjuncts. [2018-11-28 13:07:37,726 INFO L267 ElimStorePlain]: Start of recursive call 4: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-28 13:07:37,742 INFO L267 ElimStorePlain]: Start of recursive call 1: 2 dim-0 vars, 2 dim-2 vars, End of recursive call: 1 dim-0 vars, and 1 xjuncts. [2018-11-28 13:07:37,742 INFO L202 ElimStorePlain]: Needed 5 recursive calls to eliminate 4 variables, input treesize:218, output treesize:100 [2018-11-28 13:07:37,757 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 3 select indices, 3 select index equivalence classes, 3 disjoint index pairs (out of 3 index pairs), introduced 2 new quantified variables, introduced 0 case distinctions, treesize of input 171 treesize of output 165 [2018-11-28 13:07:37,759 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 46 treesize of output 45 [2018-11-28 13:07:37,760 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-11-28 13:07:37,771 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-28 13:07:37,795 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 3 select indices, 3 select index equivalence classes, 3 disjoint index pairs (out of 3 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 91 treesize of output 108 [2018-11-28 13:07:37,797 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 48 treesize of output 1 [2018-11-28 13:07:37,797 INFO L267 ElimStorePlain]: Start of recursive call 5: End of recursive call: and 1 xjuncts. [2018-11-28 13:07:37,803 INFO L267 ElimStorePlain]: Start of recursive call 4: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-28 13:07:37,816 INFO L267 ElimStorePlain]: Start of recursive call 1: 2 dim-0 vars, 2 dim-2 vars, End of recursive call: 1 dim-0 vars, and 1 xjuncts. [2018-11-28 13:07:37,816 INFO L202 ElimStorePlain]: Needed 5 recursive calls to eliminate 4 variables, input treesize:218, output treesize:100 [2018-11-28 13:07:37,830 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 3 select indices, 3 select index equivalence classes, 3 disjoint index pairs (out of 3 index pairs), introduced 2 new quantified variables, introduced 0 case distinctions, treesize of input 171 treesize of output 165 [2018-11-28 13:07:37,832 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 46 treesize of output 45 [2018-11-28 13:07:37,833 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-11-28 13:07:37,841 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-28 13:07:37,864 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 3 select indices, 3 select index equivalence classes, 3 disjoint index pairs (out of 3 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 91 treesize of output 108 [2018-11-28 13:07:37,866 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 48 treesize of output 1 [2018-11-28 13:07:37,866 INFO L267 ElimStorePlain]: Start of recursive call 5: End of recursive call: and 1 xjuncts. [2018-11-28 13:07:37,872 INFO L267 ElimStorePlain]: Start of recursive call 4: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-28 13:07:37,885 INFO L267 ElimStorePlain]: Start of recursive call 1: 2 dim-0 vars, 2 dim-2 vars, End of recursive call: 1 dim-0 vars, and 1 xjuncts. [2018-11-28 13:07:37,885 INFO L202 ElimStorePlain]: Needed 5 recursive calls to eliminate 4 variables, input treesize:218, output treesize:100 [2018-11-28 13:07:37,898 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 3 select indices, 3 select index equivalence classes, 3 disjoint index pairs (out of 3 index pairs), introduced 2 new quantified variables, introduced 0 case distinctions, treesize of input 171 treesize of output 165 [2018-11-28 13:07:37,900 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 46 treesize of output 45 [2018-11-28 13:07:37,901 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-11-28 13:07:37,911 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-28 13:07:37,934 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 3 select indices, 3 select index equivalence classes, 3 disjoint index pairs (out of 3 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 91 treesize of output 108 [2018-11-28 13:07:37,936 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 48 treesize of output 1 [2018-11-28 13:07:37,936 INFO L267 ElimStorePlain]: Start of recursive call 5: End of recursive call: and 1 xjuncts. [2018-11-28 13:07:37,948 INFO L267 ElimStorePlain]: Start of recursive call 4: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-28 13:07:37,962 INFO L267 ElimStorePlain]: Start of recursive call 1: 2 dim-0 vars, 2 dim-2 vars, End of recursive call: 1 dim-0 vars, and 1 xjuncts. [2018-11-28 13:07:37,962 INFO L202 ElimStorePlain]: Needed 5 recursive calls to eliminate 4 variables, input treesize:218, output treesize:100 [2018-11-28 13:07:37,978 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 3 select indices, 3 select index equivalence classes, 3 disjoint index pairs (out of 3 index pairs), introduced 2 new quantified variables, introduced 0 case distinctions, treesize of input 171 treesize of output 165 [2018-11-28 13:07:37,980 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 46 treesize of output 45 [2018-11-28 13:07:37,981 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-11-28 13:07:37,990 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-28 13:07:38,014 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 3 select indices, 3 select index equivalence classes, 3 disjoint index pairs (out of 3 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 91 treesize of output 108 [2018-11-28 13:07:38,016 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 48 treesize of output 1 [2018-11-28 13:07:38,016 INFO L267 ElimStorePlain]: Start of recursive call 5: End of recursive call: and 1 xjuncts. [2018-11-28 13:07:38,022 INFO L267 ElimStorePlain]: Start of recursive call 4: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-28 13:07:38,036 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-0 vars, 2 dim-2 vars, End of recursive call: 1 dim-0 vars, and 1 xjuncts. [2018-11-28 13:07:38,036 INFO L202 ElimStorePlain]: Needed 5 recursive calls to eliminate 3 variables, input treesize:218, output treesize:100 [2018-11-28 13:07:38,048 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 3 select indices, 3 select index equivalence classes, 3 disjoint index pairs (out of 3 index pairs), introduced 2 new quantified variables, introduced 0 case distinctions, treesize of input 171 treesize of output 165 [2018-11-28 13:07:38,051 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 46 treesize of output 45 [2018-11-28 13:07:38,051 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-11-28 13:07:38,060 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-28 13:07:38,084 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 3 select indices, 3 select index equivalence classes, 3 disjoint index pairs (out of 3 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 91 treesize of output 108 [2018-11-28 13:07:38,088 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 48 treesize of output 1 [2018-11-28 13:07:38,088 INFO L267 ElimStorePlain]: Start of recursive call 5: End of recursive call: and 1 xjuncts. [2018-11-28 13:07:38,094 INFO L267 ElimStorePlain]: Start of recursive call 4: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-28 13:07:38,107 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-0 vars, 2 dim-2 vars, End of recursive call: 1 dim-0 vars, and 1 xjuncts. [2018-11-28 13:07:38,107 INFO L202 ElimStorePlain]: Needed 5 recursive calls to eliminate 3 variables, input treesize:218, output treesize:100 [2018-11-28 13:07:38,123 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 3 select indices, 3 select index equivalence classes, 3 disjoint index pairs (out of 3 index pairs), introduced 2 new quantified variables, introduced 0 case distinctions, treesize of input 171 treesize of output 165 [2018-11-28 13:07:38,125 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 46 treesize of output 45 [2018-11-28 13:07:38,126 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-11-28 13:07:38,134 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-28 13:07:38,158 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 3 select indices, 3 select index equivalence classes, 3 disjoint index pairs (out of 3 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 91 treesize of output 108 [2018-11-28 13:07:38,160 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 48 treesize of output 1 [2018-11-28 13:07:38,160 INFO L267 ElimStorePlain]: Start of recursive call 5: End of recursive call: and 1 xjuncts. [2018-11-28 13:07:38,167 INFO L267 ElimStorePlain]: Start of recursive call 4: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-28 13:07:38,182 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-0 vars, 2 dim-2 vars, End of recursive call: 1 dim-0 vars, and 1 xjuncts. [2018-11-28 13:07:38,182 INFO L202 ElimStorePlain]: Needed 5 recursive calls to eliminate 3 variables, input treesize:218, output treesize:100 [2018-11-28 13:07:38,196 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 3 select indices, 3 select index equivalence classes, 3 disjoint index pairs (out of 3 index pairs), introduced 2 new quantified variables, introduced 0 case distinctions, treesize of input 171 treesize of output 165 [2018-11-28 13:07:38,198 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 46 treesize of output 45 [2018-11-28 13:07:38,198 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-11-28 13:07:38,208 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-28 13:07:38,234 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 3 select indices, 3 select index equivalence classes, 3 disjoint index pairs (out of 3 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 91 treesize of output 108 [2018-11-28 13:07:38,237 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 48 treesize of output 1 [2018-11-28 13:07:38,237 INFO L267 ElimStorePlain]: Start of recursive call 5: End of recursive call: and 1 xjuncts. [2018-11-28 13:07:38,245 INFO L267 ElimStorePlain]: Start of recursive call 4: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-28 13:07:38,261 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-0 vars, 2 dim-2 vars, End of recursive call: 1 dim-0 vars, and 1 xjuncts. [2018-11-28 13:07:38,261 INFO L202 ElimStorePlain]: Needed 5 recursive calls to eliminate 3 variables, input treesize:221, output treesize:103 [2018-11-28 13:07:38,683 INFO L134 CoverageAnalysis]: Checked inductivity of 291 backedges. 55 proven. 11 refuted. 0 times theorem prover too weak. 225 trivial. 0 not checked. [2018-11-28 13:07:38,705 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-11-28 13:07:38,705 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [25, 17] total 40 [2018-11-28 13:07:38,705 INFO L459 AbstractCegarLoop]: Interpolant automaton has 40 states [2018-11-28 13:07:38,705 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 40 interpolants. [2018-11-28 13:07:38,706 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=271, Invalid=1289, Unknown=0, NotChecked=0, Total=1560 [2018-11-28 13:07:38,706 INFO L87 Difference]: Start difference. First operand 157 states and 175 transitions. Second operand 40 states. [2018-11-28 13:07:39,880 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-28 13:07:39,880 INFO L93 Difference]: Finished difference Result 279 states and 320 transitions. [2018-11-28 13:07:39,880 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 17 states. [2018-11-28 13:07:39,880 INFO L78 Accepts]: Start accepts. Automaton has 40 states. Word has length 91 [2018-11-28 13:07:39,880 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-28 13:07:39,881 INFO L225 Difference]: With dead ends: 279 [2018-11-28 13:07:39,881 INFO L226 Difference]: Without dead ends: 208 [2018-11-28 13:07:39,882 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 136 GetRequests, 81 SyntacticMatches, 6 SemanticMatches, 49 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 738 ImplicationChecksByTransitivity, 2.0s TimeCoverageRelationStatistics Valid=451, Invalid=2099, Unknown=0, NotChecked=0, Total=2550 [2018-11-28 13:07:39,882 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 208 states. [2018-11-28 13:07:39,892 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 208 to 205. [2018-11-28 13:07:39,892 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 205 states. [2018-11-28 13:07:39,893 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 205 states to 205 states and 230 transitions. [2018-11-28 13:07:39,893 INFO L78 Accepts]: Start accepts. Automaton has 205 states and 230 transitions. Word has length 91 [2018-11-28 13:07:39,893 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-28 13:07:39,893 INFO L480 AbstractCegarLoop]: Abstraction has 205 states and 230 transitions. [2018-11-28 13:07:39,893 INFO L481 AbstractCegarLoop]: Interpolant automaton has 40 states. [2018-11-28 13:07:39,893 INFO L276 IsEmpty]: Start isEmpty. Operand 205 states and 230 transitions. [2018-11-28 13:07:39,894 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 98 [2018-11-28 13:07:39,894 INFO L394 BasicCegarLoop]: Found error trace [2018-11-28 13:07:39,894 INFO L402 BasicCegarLoop]: trace histogram [10, 10, 10, 10, 10, 10, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-28 13:07:39,894 INFO L423 AbstractCegarLoop]: === Iteration 26 === [single_argvErr6ASSERT_VIOLATIONINTEGER_OVERFLOW, single_argvErr0ASSERT_VIOLATIONINTEGER_OVERFLOW, single_argvErr2ASSERT_VIOLATIONINTEGER_OVERFLOW, single_argvErr4ASSERT_VIOLATIONINTEGER_OVERFLOW, single_argvErr5ASSERT_VIOLATIONINTEGER_OVERFLOW, single_argvErr1ASSERT_VIOLATIONINTEGER_OVERFLOW, single_argvErr3ASSERT_VIOLATIONINTEGER_OVERFLOW, single_argvErr7ASSERT_VIOLATIONINTEGER_OVERFLOW, single_argvErr8ASSERT_VIOLATIONINTEGER_OVERFLOW, single_argvErr9ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr6ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr10ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr5ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr11ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr7ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr0ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr15ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr8ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr14ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr1ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr4ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr3ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr2ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr9ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr12ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr13ASSERT_VIOLATIONINTEGER_OVERFLOW, dirnameErr0ASSERT_VIOLATIONINTEGER_OVERFLOW, dirnameErr1ASSERT_VIOLATIONINTEGER_OVERFLOW]=== [2018-11-28 13:07:39,895 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-28 13:07:39,895 INFO L82 PathProgramCache]: Analyzing trace with hash -2132172502, now seen corresponding path program 1 times [2018-11-28 13:07:39,895 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-28 13:07:39,895 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-28 13:07:39,896 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 13:07:39,896 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-28 13:07:39,896 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 13:07:39,922 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-28 13:07:39,960 INFO L134 CoverageAnalysis]: Checked inductivity of 291 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 291 trivial. 0 not checked. [2018-11-28 13:07:39,960 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-28 13:07:39,960 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2018-11-28 13:07:39,961 INFO L459 AbstractCegarLoop]: Interpolant automaton has 3 states [2018-11-28 13:07:39,961 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-28 13:07:39,961 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-28 13:07:39,961 INFO L87 Difference]: Start difference. First operand 205 states and 230 transitions. Second operand 3 states. [2018-11-28 13:07:39,977 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-28 13:07:39,977 INFO L93 Difference]: Finished difference Result 223 states and 250 transitions. [2018-11-28 13:07:39,978 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-28 13:07:39,978 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 97 [2018-11-28 13:07:39,978 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-28 13:07:39,979 INFO L225 Difference]: With dead ends: 223 [2018-11-28 13:07:39,979 INFO L226 Difference]: Without dead ends: 205 [2018-11-28 13:07:39,979 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 2 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-28 13:07:39,980 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 205 states. [2018-11-28 13:07:39,986 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 205 to 205. [2018-11-28 13:07:39,986 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 205 states. [2018-11-28 13:07:39,987 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 205 states to 205 states and 230 transitions. [2018-11-28 13:07:39,987 INFO L78 Accepts]: Start accepts. Automaton has 205 states and 230 transitions. Word has length 97 [2018-11-28 13:07:39,988 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-28 13:07:39,988 INFO L480 AbstractCegarLoop]: Abstraction has 205 states and 230 transitions. [2018-11-28 13:07:39,988 INFO L481 AbstractCegarLoop]: Interpolant automaton has 3 states. [2018-11-28 13:07:39,988 INFO L276 IsEmpty]: Start isEmpty. Operand 205 states and 230 transitions. [2018-11-28 13:07:39,988 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 99 [2018-11-28 13:07:39,989 INFO L394 BasicCegarLoop]: Found error trace [2018-11-28 13:07:39,989 INFO L402 BasicCegarLoop]: trace histogram [10, 10, 10, 10, 10, 10, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-28 13:07:39,989 INFO L423 AbstractCegarLoop]: === Iteration 27 === [single_argvErr6ASSERT_VIOLATIONINTEGER_OVERFLOW, single_argvErr0ASSERT_VIOLATIONINTEGER_OVERFLOW, single_argvErr2ASSERT_VIOLATIONINTEGER_OVERFLOW, single_argvErr4ASSERT_VIOLATIONINTEGER_OVERFLOW, single_argvErr5ASSERT_VIOLATIONINTEGER_OVERFLOW, single_argvErr1ASSERT_VIOLATIONINTEGER_OVERFLOW, single_argvErr3ASSERT_VIOLATIONINTEGER_OVERFLOW, single_argvErr7ASSERT_VIOLATIONINTEGER_OVERFLOW, single_argvErr8ASSERT_VIOLATIONINTEGER_OVERFLOW, single_argvErr9ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr6ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr10ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr5ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr11ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr7ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr0ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr15ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr8ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr14ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr1ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr4ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr3ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr2ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr9ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr12ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr13ASSERT_VIOLATIONINTEGER_OVERFLOW, dirnameErr0ASSERT_VIOLATIONINTEGER_OVERFLOW, dirnameErr1ASSERT_VIOLATIONINTEGER_OVERFLOW]=== [2018-11-28 13:07:39,989 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-28 13:07:39,989 INFO L82 PathProgramCache]: Analyzing trace with hash -1672837872, now seen corresponding path program 1 times [2018-11-28 13:07:39,989 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-28 13:07:39,989 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-28 13:07:39,990 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 13:07:39,990 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-28 13:07:39,991 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 13:07:40,010 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-28 13:07:40,045 INFO L134 CoverageAnalysis]: Checked inductivity of 291 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 291 trivial. 0 not checked. [2018-11-28 13:07:40,045 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-28 13:07:40,045 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2018-11-28 13:07:40,045 INFO L459 AbstractCegarLoop]: Interpolant automaton has 3 states [2018-11-28 13:07:40,046 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-28 13:07:40,046 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-28 13:07:40,046 INFO L87 Difference]: Start difference. First operand 205 states and 230 transitions. Second operand 3 states. [2018-11-28 13:07:40,063 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-28 13:07:40,063 INFO L93 Difference]: Finished difference Result 208 states and 233 transitions. [2018-11-28 13:07:40,064 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-28 13:07:40,064 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 98 [2018-11-28 13:07:40,064 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-28 13:07:40,065 INFO L225 Difference]: With dead ends: 208 [2018-11-28 13:07:40,065 INFO L226 Difference]: Without dead ends: 207 [2018-11-28 13:07:40,066 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 2 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-28 13:07:40,066 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 207 states. [2018-11-28 13:07:40,073 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 207 to 207. [2018-11-28 13:07:40,073 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 207 states. [2018-11-28 13:07:40,074 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 207 states to 207 states and 232 transitions. [2018-11-28 13:07:40,074 INFO L78 Accepts]: Start accepts. Automaton has 207 states and 232 transitions. Word has length 98 [2018-11-28 13:07:40,074 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-28 13:07:40,074 INFO L480 AbstractCegarLoop]: Abstraction has 207 states and 232 transitions. [2018-11-28 13:07:40,074 INFO L481 AbstractCegarLoop]: Interpolant automaton has 3 states. [2018-11-28 13:07:40,074 INFO L276 IsEmpty]: Start isEmpty. Operand 207 states and 232 transitions. [2018-11-28 13:07:40,075 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 102 [2018-11-28 13:07:40,075 INFO L394 BasicCegarLoop]: Found error trace [2018-11-28 13:07:40,075 INFO L402 BasicCegarLoop]: trace histogram [10, 10, 10, 10, 10, 10, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-28 13:07:40,076 INFO L423 AbstractCegarLoop]: === Iteration 28 === [single_argvErr6ASSERT_VIOLATIONINTEGER_OVERFLOW, single_argvErr0ASSERT_VIOLATIONINTEGER_OVERFLOW, single_argvErr2ASSERT_VIOLATIONINTEGER_OVERFLOW, single_argvErr4ASSERT_VIOLATIONINTEGER_OVERFLOW, single_argvErr5ASSERT_VIOLATIONINTEGER_OVERFLOW, single_argvErr1ASSERT_VIOLATIONINTEGER_OVERFLOW, single_argvErr3ASSERT_VIOLATIONINTEGER_OVERFLOW, single_argvErr7ASSERT_VIOLATIONINTEGER_OVERFLOW, single_argvErr8ASSERT_VIOLATIONINTEGER_OVERFLOW, single_argvErr9ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr6ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr10ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr5ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr11ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr7ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr0ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr15ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr8ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr14ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr1ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr4ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr3ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr2ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr9ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr12ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr13ASSERT_VIOLATIONINTEGER_OVERFLOW, dirnameErr0ASSERT_VIOLATIONINTEGER_OVERFLOW, dirnameErr1ASSERT_VIOLATIONINTEGER_OVERFLOW]=== [2018-11-28 13:07:40,076 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-28 13:07:40,076 INFO L82 PathProgramCache]: Analyzing trace with hash -1007265881, now seen corresponding path program 1 times [2018-11-28 13:07:40,076 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-28 13:07:40,076 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-28 13:07:40,077 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 13:07:40,077 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-28 13:07:40,077 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 13:07:40,098 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-28 13:07:40,128 INFO L134 CoverageAnalysis]: Checked inductivity of 294 backedges. 3 proven. 0 refuted. 0 times theorem prover too weak. 291 trivial. 0 not checked. [2018-11-28 13:07:40,129 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-28 13:07:40,129 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2018-11-28 13:07:40,129 INFO L459 AbstractCegarLoop]: Interpolant automaton has 3 states [2018-11-28 13:07:40,129 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-28 13:07:40,129 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-28 13:07:40,129 INFO L87 Difference]: Start difference. First operand 207 states and 232 transitions. Second operand 3 states. [2018-11-28 13:07:40,144 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-28 13:07:40,144 INFO L93 Difference]: Finished difference Result 207 states and 232 transitions. [2018-11-28 13:07:40,145 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-28 13:07:40,145 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 101 [2018-11-28 13:07:40,145 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-28 13:07:40,146 INFO L225 Difference]: With dead ends: 207 [2018-11-28 13:07:40,146 INFO L226 Difference]: Without dead ends: 206 [2018-11-28 13:07:40,147 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 2 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-28 13:07:40,147 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 206 states. [2018-11-28 13:07:40,154 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 206 to 204. [2018-11-28 13:07:40,154 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 204 states. [2018-11-28 13:07:40,155 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 204 states to 204 states and 229 transitions. [2018-11-28 13:07:40,155 INFO L78 Accepts]: Start accepts. Automaton has 204 states and 229 transitions. Word has length 101 [2018-11-28 13:07:40,155 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-28 13:07:40,155 INFO L480 AbstractCegarLoop]: Abstraction has 204 states and 229 transitions. [2018-11-28 13:07:40,155 INFO L481 AbstractCegarLoop]: Interpolant automaton has 3 states. [2018-11-28 13:07:40,155 INFO L276 IsEmpty]: Start isEmpty. Operand 204 states and 229 transitions. [2018-11-28 13:07:40,156 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 114 [2018-11-28 13:07:40,156 INFO L394 BasicCegarLoop]: Found error trace [2018-11-28 13:07:40,156 INFO L402 BasicCegarLoop]: trace histogram [10, 10, 10, 10, 10, 10, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-28 13:07:40,156 INFO L423 AbstractCegarLoop]: === Iteration 29 === [single_argvErr6ASSERT_VIOLATIONINTEGER_OVERFLOW, single_argvErr0ASSERT_VIOLATIONINTEGER_OVERFLOW, single_argvErr2ASSERT_VIOLATIONINTEGER_OVERFLOW, single_argvErr4ASSERT_VIOLATIONINTEGER_OVERFLOW, single_argvErr5ASSERT_VIOLATIONINTEGER_OVERFLOW, single_argvErr1ASSERT_VIOLATIONINTEGER_OVERFLOW, single_argvErr3ASSERT_VIOLATIONINTEGER_OVERFLOW, single_argvErr7ASSERT_VIOLATIONINTEGER_OVERFLOW, single_argvErr8ASSERT_VIOLATIONINTEGER_OVERFLOW, single_argvErr9ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr6ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr10ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr5ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr11ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr7ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr0ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr15ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr8ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr14ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr1ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr4ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr3ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr2ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr9ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr12ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr13ASSERT_VIOLATIONINTEGER_OVERFLOW, dirnameErr0ASSERT_VIOLATIONINTEGER_OVERFLOW, dirnameErr1ASSERT_VIOLATIONINTEGER_OVERFLOW]=== [2018-11-28 13:07:40,156 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-28 13:07:40,156 INFO L82 PathProgramCache]: Analyzing trace with hash 446640932, now seen corresponding path program 1 times [2018-11-28 13:07:40,156 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-28 13:07:40,156 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-28 13:07:40,157 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 13:07:40,157 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-28 13:07:40,157 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 13:07:40,177 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-28 13:07:40,222 INFO L134 CoverageAnalysis]: Checked inductivity of 292 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 292 trivial. 0 not checked. [2018-11-28 13:07:40,222 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-28 13:07:40,222 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-28 13:07:40,222 INFO L459 AbstractCegarLoop]: Interpolant automaton has 4 states [2018-11-28 13:07:40,222 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2018-11-28 13:07:40,223 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2018-11-28 13:07:40,223 INFO L87 Difference]: Start difference. First operand 204 states and 229 transitions. Second operand 4 states. [2018-11-28 13:07:40,256 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-28 13:07:40,256 INFO L93 Difference]: Finished difference Result 205 states and 230 transitions. [2018-11-28 13:07:40,257 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2018-11-28 13:07:40,257 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 113 [2018-11-28 13:07:40,257 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-28 13:07:40,258 INFO L225 Difference]: With dead ends: 205 [2018-11-28 13:07:40,258 INFO L226 Difference]: Without dead ends: 204 [2018-11-28 13:07:40,258 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 4 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2018-11-28 13:07:40,258 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 204 states. [2018-11-28 13:07:40,265 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 204 to 203. [2018-11-28 13:07:40,265 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 203 states. [2018-11-28 13:07:40,266 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 203 states to 203 states and 228 transitions. [2018-11-28 13:07:40,266 INFO L78 Accepts]: Start accepts. Automaton has 203 states and 228 transitions. Word has length 113 [2018-11-28 13:07:40,266 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-28 13:07:40,266 INFO L480 AbstractCegarLoop]: Abstraction has 203 states and 228 transitions. [2018-11-28 13:07:40,267 INFO L481 AbstractCegarLoop]: Interpolant automaton has 4 states. [2018-11-28 13:07:40,267 INFO L276 IsEmpty]: Start isEmpty. Operand 203 states and 228 transitions. [2018-11-28 13:07:40,267 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 115 [2018-11-28 13:07:40,267 INFO L394 BasicCegarLoop]: Found error trace [2018-11-28 13:07:40,268 INFO L402 BasicCegarLoop]: trace histogram [10, 10, 10, 10, 10, 10, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-28 13:07:40,268 INFO L423 AbstractCegarLoop]: === Iteration 30 === [single_argvErr6ASSERT_VIOLATIONINTEGER_OVERFLOW, single_argvErr0ASSERT_VIOLATIONINTEGER_OVERFLOW, single_argvErr2ASSERT_VIOLATIONINTEGER_OVERFLOW, single_argvErr4ASSERT_VIOLATIONINTEGER_OVERFLOW, single_argvErr5ASSERT_VIOLATIONINTEGER_OVERFLOW, single_argvErr1ASSERT_VIOLATIONINTEGER_OVERFLOW, single_argvErr3ASSERT_VIOLATIONINTEGER_OVERFLOW, single_argvErr7ASSERT_VIOLATIONINTEGER_OVERFLOW, single_argvErr8ASSERT_VIOLATIONINTEGER_OVERFLOW, single_argvErr9ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr6ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr10ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr5ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr11ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr7ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr0ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr15ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr8ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr14ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr1ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr4ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr3ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr2ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr9ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr12ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr13ASSERT_VIOLATIONINTEGER_OVERFLOW, dirnameErr0ASSERT_VIOLATIONINTEGER_OVERFLOW, dirnameErr1ASSERT_VIOLATIONINTEGER_OVERFLOW]=== [2018-11-28 13:07:40,268 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-28 13:07:40,268 INFO L82 PathProgramCache]: Analyzing trace with hash 960967235, now seen corresponding path program 1 times [2018-11-28 13:07:40,268 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-28 13:07:40,268 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-28 13:07:40,269 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 13:07:40,269 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-28 13:07:40,269 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 13:07:40,289 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-28 13:07:40,349 INFO L134 CoverageAnalysis]: Checked inductivity of 292 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 292 trivial. 0 not checked. [2018-11-28 13:07:40,349 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-28 13:07:40,349 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2018-11-28 13:07:40,350 INFO L459 AbstractCegarLoop]: Interpolant automaton has 3 states [2018-11-28 13:07:40,350 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-28 13:07:40,350 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-28 13:07:40,350 INFO L87 Difference]: Start difference. First operand 203 states and 228 transitions. Second operand 3 states. [2018-11-28 13:07:40,362 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-28 13:07:40,362 INFO L93 Difference]: Finished difference Result 207 states and 232 transitions. [2018-11-28 13:07:40,363 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-28 13:07:40,363 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 114 [2018-11-28 13:07:40,363 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-28 13:07:40,364 INFO L225 Difference]: With dead ends: 207 [2018-11-28 13:07:40,364 INFO L226 Difference]: Without dead ends: 206 [2018-11-28 13:07:40,364 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 2 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-28 13:07:40,365 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 206 states. [2018-11-28 13:07:40,372 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 206 to 206. [2018-11-28 13:07:40,372 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 206 states. [2018-11-28 13:07:40,372 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 206 states to 206 states and 231 transitions. [2018-11-28 13:07:40,373 INFO L78 Accepts]: Start accepts. Automaton has 206 states and 231 transitions. Word has length 114 [2018-11-28 13:07:40,373 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-28 13:07:40,373 INFO L480 AbstractCegarLoop]: Abstraction has 206 states and 231 transitions. [2018-11-28 13:07:40,373 INFO L481 AbstractCegarLoop]: Interpolant automaton has 3 states. [2018-11-28 13:07:40,373 INFO L276 IsEmpty]: Start isEmpty. Operand 206 states and 231 transitions. [2018-11-28 13:07:40,374 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 118 [2018-11-28 13:07:40,374 INFO L394 BasicCegarLoop]: Found error trace [2018-11-28 13:07:40,374 INFO L402 BasicCegarLoop]: trace histogram [10, 10, 10, 10, 10, 10, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-28 13:07:40,374 INFO L423 AbstractCegarLoop]: === Iteration 31 === [single_argvErr6ASSERT_VIOLATIONINTEGER_OVERFLOW, single_argvErr0ASSERT_VIOLATIONINTEGER_OVERFLOW, single_argvErr2ASSERT_VIOLATIONINTEGER_OVERFLOW, single_argvErr4ASSERT_VIOLATIONINTEGER_OVERFLOW, single_argvErr5ASSERT_VIOLATIONINTEGER_OVERFLOW, single_argvErr1ASSERT_VIOLATIONINTEGER_OVERFLOW, single_argvErr3ASSERT_VIOLATIONINTEGER_OVERFLOW, single_argvErr7ASSERT_VIOLATIONINTEGER_OVERFLOW, single_argvErr8ASSERT_VIOLATIONINTEGER_OVERFLOW, single_argvErr9ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr6ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr10ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr5ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr11ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr7ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr0ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr15ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr8ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr14ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr1ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr4ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr3ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr2ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr9ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr12ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr13ASSERT_VIOLATIONINTEGER_OVERFLOW, dirnameErr0ASSERT_VIOLATIONINTEGER_OVERFLOW, dirnameErr1ASSERT_VIOLATIONINTEGER_OVERFLOW]=== [2018-11-28 13:07:40,374 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-28 13:07:40,375 INFO L82 PathProgramCache]: Analyzing trace with hash -2076872735, now seen corresponding path program 1 times [2018-11-28 13:07:40,375 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-28 13:07:40,375 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-28 13:07:40,376 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 13:07:40,376 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-28 13:07:40,376 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 13:07:40,395 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-28 13:07:40,425 INFO L134 CoverageAnalysis]: Checked inductivity of 295 backedges. 3 proven. 0 refuted. 0 times theorem prover too weak. 292 trivial. 0 not checked. [2018-11-28 13:07:40,425 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-28 13:07:40,425 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2018-11-28 13:07:40,426 INFO L459 AbstractCegarLoop]: Interpolant automaton has 3 states [2018-11-28 13:07:40,426 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-28 13:07:40,426 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-28 13:07:40,426 INFO L87 Difference]: Start difference. First operand 206 states and 231 transitions. Second operand 3 states. [2018-11-28 13:07:40,439 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-28 13:07:40,439 INFO L93 Difference]: Finished difference Result 206 states and 231 transitions. [2018-11-28 13:07:40,440 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-28 13:07:40,440 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 117 [2018-11-28 13:07:40,440 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-28 13:07:40,441 INFO L225 Difference]: With dead ends: 206 [2018-11-28 13:07:40,441 INFO L226 Difference]: Without dead ends: 151 [2018-11-28 13:07:40,441 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 2 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-28 13:07:40,441 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 151 states. [2018-11-28 13:07:40,447 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 151 to 151. [2018-11-28 13:07:40,447 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 151 states. [2018-11-28 13:07:40,447 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 151 states to 151 states and 161 transitions. [2018-11-28 13:07:40,448 INFO L78 Accepts]: Start accepts. Automaton has 151 states and 161 transitions. Word has length 117 [2018-11-28 13:07:40,448 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-28 13:07:40,448 INFO L480 AbstractCegarLoop]: Abstraction has 151 states and 161 transitions. [2018-11-28 13:07:40,448 INFO L481 AbstractCegarLoop]: Interpolant automaton has 3 states. [2018-11-28 13:07:40,448 INFO L276 IsEmpty]: Start isEmpty. Operand 151 states and 161 transitions. [2018-11-28 13:07:40,449 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 126 [2018-11-28 13:07:40,449 INFO L394 BasicCegarLoop]: Found error trace [2018-11-28 13:07:40,449 INFO L402 BasicCegarLoop]: trace histogram [20, 20, 20, 10, 10, 10, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-28 13:07:40,449 INFO L423 AbstractCegarLoop]: === Iteration 32 === [single_argvErr6ASSERT_VIOLATIONINTEGER_OVERFLOW, single_argvErr0ASSERT_VIOLATIONINTEGER_OVERFLOW, single_argvErr2ASSERT_VIOLATIONINTEGER_OVERFLOW, single_argvErr4ASSERT_VIOLATIONINTEGER_OVERFLOW, single_argvErr5ASSERT_VIOLATIONINTEGER_OVERFLOW, single_argvErr1ASSERT_VIOLATIONINTEGER_OVERFLOW, single_argvErr3ASSERT_VIOLATIONINTEGER_OVERFLOW, single_argvErr7ASSERT_VIOLATIONINTEGER_OVERFLOW, single_argvErr8ASSERT_VIOLATIONINTEGER_OVERFLOW, single_argvErr9ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr6ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr10ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr5ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr11ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr7ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr0ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr15ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr8ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr14ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr1ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr4ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr3ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr2ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr9ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr12ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr13ASSERT_VIOLATIONINTEGER_OVERFLOW, dirnameErr0ASSERT_VIOLATIONINTEGER_OVERFLOW, dirnameErr1ASSERT_VIOLATIONINTEGER_OVERFLOW]=== [2018-11-28 13:07:40,449 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-28 13:07:40,450 INFO L82 PathProgramCache]: Analyzing trace with hash 576931341, now seen corresponding path program 10 times [2018-11-28 13:07:40,450 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-28 13:07:40,450 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-28 13:07:40,451 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 13:07:40,451 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-28 13:07:40,451 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 13:07:41,451 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-28 13:07:42,600 WARN L180 SmtUtils]: Spent 172.00 ms on a formula simplification. DAG size of input: 100 DAG size of output: 41 [2018-11-28 13:07:42,749 WARN L180 SmtUtils]: Spent 121.00 ms on a formula simplification. DAG size of input: 99 DAG size of output: 52 [2018-11-28 13:07:42,902 WARN L180 SmtUtils]: Spent 131.00 ms on a formula simplification. DAG size of input: 101 DAG size of output: 50 [2018-11-28 13:07:43,104 WARN L180 SmtUtils]: Spent 155.00 ms on a formula simplification. DAG size of input: 116 DAG size of output: 50 [2018-11-28 13:07:43,282 WARN L180 SmtUtils]: Spent 148.00 ms on a formula simplification. DAG size of input: 100 DAG size of output: 54 [2018-11-28 13:07:43,466 WARN L180 SmtUtils]: Spent 154.00 ms on a formula simplification. DAG size of input: 107 DAG size of output: 54 [2018-11-28 13:07:43,703 WARN L180 SmtUtils]: Spent 172.00 ms on a formula simplification. DAG size of input: 109 DAG size of output: 55 [2018-11-28 13:07:43,860 WARN L180 SmtUtils]: Spent 127.00 ms on a formula simplification. DAG size of input: 96 DAG size of output: 50 [2018-11-28 13:07:44,031 WARN L180 SmtUtils]: Spent 139.00 ms on a formula simplification. DAG size of input: 104 DAG size of output: 50 [2018-11-28 13:07:44,237 WARN L180 SmtUtils]: Spent 137.00 ms on a formula simplification. DAG size of input: 102 DAG size of output: 49 [2018-11-28 13:07:44,453 WARN L180 SmtUtils]: Spent 148.00 ms on a formula simplification. DAG size of input: 108 DAG size of output: 51 [2018-11-28 13:07:44,697 WARN L180 SmtUtils]: Spent 161.00 ms on a formula simplification. DAG size of input: 105 DAG size of output: 50 [2018-11-28 13:07:44,941 WARN L180 SmtUtils]: Spent 160.00 ms on a formula simplification. DAG size of input: 95 DAG size of output: 48 [2018-11-28 13:07:45,589 INFO L134 CoverageAnalysis]: Checked inductivity of 761 backedges. 0 proven. 524 refuted. 0 times theorem prover too weak. 237 trivial. 0 not checked. [2018-11-28 13:07:45,589 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-28 13:07:45,589 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_b218a3f8-accd-4719-941b-ce9fe174b24c/bin-2019/uautomizer/z3 Starting monitored process 15 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 15 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-28 13:07:45,596 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-11-28 13:07:45,736 INFO L249 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-11-28 13:07:45,736 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-11-28 13:07:45,744 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-28 13:07:45,751 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 141 treesize of output 131 [2018-11-28 13:07:45,758 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:07:45,787 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 2 case distinctions, treesize of input 131 treesize of output 125 [2018-11-28 13:07:45,794 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:07:45,805 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:07:45,811 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 2 select indices, 2 select index equivalence classes, 2 disjoint index pairs (out of 1 index pairs), introduced 1 new quantified variables, introduced 2 case distinctions, treesize of input 121 treesize of output 119 [2018-11-28 13:07:45,817 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 2 select indices, 2 select index equivalence classes, 1 disjoint index pairs (out of 1 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 113 treesize of output 107 [2018-11-28 13:07:45,940 WARN L180 SmtUtils]: Spent 122.00 ms on a formula simplification. DAG size of input: 44 DAG size of output: 42 [2018-11-28 13:07:45,947 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:07:45,950 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:07:45,953 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:07:45,978 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:07:45,979 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 4 select indices, 4 select index equivalence classes, 6 disjoint index pairs (out of 6 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 93 treesize of output 112 [2018-11-28 13:07:46,089 WARN L180 SmtUtils]: Spent 108.00 ms on a formula simplification. DAG size of input: 52 DAG size of output: 42 [2018-11-28 13:07:46,094 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:07:46,097 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:07:46,100 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:07:46,103 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:07:46,114 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:07:46,125 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:07:46,128 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:07:46,135 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:07:46,136 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 6 select indices, 6 select index equivalence classes, 11 disjoint index pairs (out of 15 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 83 treesize of output 123 [2018-11-28 13:07:46,182 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:07:46,183 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:07:46,185 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:07:46,185 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:07:46,187 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:07:46,188 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:07:46,189 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:07:46,190 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:07:46,191 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:07:46,191 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:07:46,192 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 7 select indices, 7 select index equivalence classes, 17 disjoint index pairs (out of 21 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 71 treesize of output 138 [2018-11-28 13:07:46,214 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 7 select indices, 7 select index equivalence classes, 17 disjoint index pairs (out of 21 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 71 treesize of output 132 [2018-11-28 13:07:46,250 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 7 select indices, 7 select index equivalence classes, 17 disjoint index pairs (out of 21 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 65 treesize of output 126 [2018-11-28 13:07:46,299 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 9 select indices, 9 select index equivalence classes, 26 disjoint index pairs (out of 36 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 55 treesize of output 157 [2018-11-28 13:07:46,318 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 10 select indices, 10 select index equivalence classes, 26 disjoint index pairs (out of 45 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 57 treesize of output 154 [2018-11-28 13:07:46,318 INFO L267 ElimStorePlain]: Start of recursive call 12: End of recursive call: and 1 xjuncts. [2018-11-28 13:07:46,364 INFO L267 ElimStorePlain]: Start of recursive call 11: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-28 13:07:46,406 INFO L267 ElimStorePlain]: Start of recursive call 10: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-28 13:07:46,448 INFO L267 ElimStorePlain]: Start of recursive call 9: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-28 13:07:46,493 INFO L267 ElimStorePlain]: Start of recursive call 8: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-28 13:07:46,537 INFO L267 ElimStorePlain]: Start of recursive call 7: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-28 13:07:46,581 INFO L267 ElimStorePlain]: Start of recursive call 6: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-28 13:07:46,629 INFO L267 ElimStorePlain]: Start of recursive call 5: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-28 13:07:46,709 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:07:46,711 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:07:46,714 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:07:46,745 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 3 select indices, 3 select index equivalence classes, 3 disjoint index pairs (out of 3 index pairs), introduced 1 new quantified variables, introduced 2 case distinctions, treesize of input 111 treesize of output 113 [2018-11-28 13:07:47,076 WARN L180 SmtUtils]: Spent 329.00 ms on a formula simplification. DAG size of input: 71 DAG size of output: 71 [2018-11-28 13:07:47,083 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:07:47,086 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:07:47,090 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:07:47,108 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:07:47,121 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:07:47,129 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:07:47,144 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:07:47,172 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 5 select indices, 5 select index equivalence classes, 8 disjoint index pairs (out of 10 index pairs), introduced 1 new quantified variables, introduced 2 case distinctions, treesize of input 102 treesize of output 129 [2018-11-28 13:07:47,589 WARN L180 SmtUtils]: Spent 415.00 ms on a formula simplification. DAG size of input: 87 DAG size of output: 75 [2018-11-28 13:07:47,596 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:07:47,599 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:07:47,610 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:07:47,613 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:07:47,621 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:07:47,625 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:07:47,636 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:07:47,640 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:07:47,658 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:07:47,661 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:07:47,665 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:07:47,668 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:07:47,680 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:07:47,702 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 7 select indices, 7 select index equivalence classes, 14 disjoint index pairs (out of 21 index pairs), introduced 1 new quantified variables, introduced 2 case distinctions, treesize of input 92 treesize of output 141 [2018-11-28 13:07:48,173 WARN L180 SmtUtils]: Spent 469.00 ms on a formula simplification. DAG size of input: 97 DAG size of output: 81 [2018-11-28 13:07:48,179 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:07:48,181 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:07:48,183 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:07:48,190 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:07:48,193 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:07:48,204 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:07:48,206 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:07:48,208 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:07:48,219 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:07:48,222 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:07:48,223 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:07:48,231 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:07:48,233 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:07:48,245 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:07:48,248 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:07:48,255 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:07:48,277 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 8 select indices, 8 select index equivalence classes, 21 disjoint index pairs (out of 28 index pairs), introduced 1 new quantified variables, introduced 2 case distinctions, treesize of input 96 treesize of output 160 [2018-11-28 13:07:48,299 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 7 select indices, 7 select index equivalence classes, 16 disjoint index pairs (out of 21 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 154 treesize of output 148 [2018-11-28 13:07:48,336 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 7 select indices, 7 select index equivalence classes, 16 disjoint index pairs (out of 21 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 65 treesize of output 118 [2018-11-28 13:07:48,390 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:07:48,396 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:07:48,403 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:07:48,408 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:07:48,413 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:07:48,415 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:07:48,416 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:07:48,417 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:07:48,423 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:07:48,424 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 9 select indices, 9 select index equivalence classes, 25 disjoint index pairs (out of 36 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 55 treesize of output 159 [2018-11-28 13:07:48,447 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 10 select indices, 10 select index equivalence classes, 25 disjoint index pairs (out of 45 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 63 treesize of output 154 [2018-11-28 13:07:48,448 INFO L267 ElimStorePlain]: Start of recursive call 20: End of recursive call: and 1 xjuncts. [2018-11-28 13:07:48,505 INFO L267 ElimStorePlain]: Start of recursive call 19: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-28 13:07:48,544 INFO L267 ElimStorePlain]: Start of recursive call 18: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-28 13:07:48,596 INFO L267 ElimStorePlain]: Start of recursive call 17: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-28 13:07:48,715 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:07:48,717 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:07:48,722 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:07:48,727 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:07:48,732 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:07:48,737 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:07:48,744 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:07:48,746 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:07:48,749 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:07:48,754 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:07:48,759 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:07:48,764 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:07:48,767 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:07:48,783 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 8 select indices, 8 select index equivalence classes, 22 disjoint index pairs (out of 28 index pairs), introduced 1 new quantified variables, introduced 2 case distinctions, treesize of input 106 treesize of output 158 [2018-11-28 13:07:48,822 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 7 select indices, 7 select index equivalence classes, 16 disjoint index pairs (out of 21 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 152 treesize of output 145 [2018-11-28 13:07:48,937 WARN L180 SmtUtils]: Spent 113.00 ms on a formula simplification. DAG size of input: 81 DAG size of output: 69 [2018-11-28 13:07:48,942 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:07:48,948 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:07:48,955 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:07:48,960 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:07:48,965 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:07:48,967 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:07:48,968 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:07:48,969 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:07:48,975 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:07:48,976 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 9 select indices, 9 select index equivalence classes, 25 disjoint index pairs (out of 36 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 55 treesize of output 159 [2018-11-28 13:07:48,994 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 10 select indices, 10 select index equivalence classes, 25 disjoint index pairs (out of 45 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 63 treesize of output 154 [2018-11-28 13:07:48,994 INFO L267 ElimStorePlain]: Start of recursive call 24: End of recursive call: and 1 xjuncts. [2018-11-28 13:07:49,036 INFO L267 ElimStorePlain]: Start of recursive call 23: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-28 13:07:49,082 INFO L267 ElimStorePlain]: Start of recursive call 22: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-28 13:07:49,205 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:07:49,212 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:07:49,221 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:07:49,231 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:07:49,235 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:07:49,237 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:07:49,239 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:07:49,253 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:07:49,266 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 8 select indices, 8 select index equivalence classes, 23 disjoint index pairs (out of 28 index pairs), introduced 1 new quantified variables, introduced 2 case distinctions, treesize of input 124 treesize of output 155 [2018-11-28 13:07:49,587 WARN L180 SmtUtils]: Spent 319.00 ms on a formula simplification. DAG size of input: 109 DAG size of output: 109 [2018-11-28 13:07:49,590 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:07:49,591 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:07:49,593 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:07:49,596 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:07:49,598 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:07:49,599 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:07:49,600 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:07:49,601 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:07:49,604 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:07:49,605 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 9 select indices, 9 select index equivalence classes, 32 disjoint index pairs (out of 36 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 150 treesize of output 218 [2018-11-28 13:07:49,621 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 10 select indices, 10 select index equivalence classes, 32 disjoint index pairs (out of 45 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 63 treesize of output 182 [2018-11-28 13:07:49,622 INFO L267 ElimStorePlain]: Start of recursive call 27: End of recursive call: and 1 xjuncts. [2018-11-28 13:07:49,697 INFO L267 ElimStorePlain]: Start of recursive call 26: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-28 13:07:49,819 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:07:49,820 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:07:49,827 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:07:49,830 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:07:49,835 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:07:49,839 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:07:49,841 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:07:49,845 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:07:49,847 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:07:49,848 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:07:49,850 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:07:49,851 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:07:49,853 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:07:49,855 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:07:49,857 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:07:49,860 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:07:49,863 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:07:49,869 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 10 select indices, 10 select index equivalence classes, 33 disjoint index pairs (out of 45 index pairs), introduced 1 new quantified variables, introduced 2 case distinctions, treesize of input 124 treesize of output 200 [2018-11-28 13:07:49,895 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 11 select indices, 11 select index equivalence classes, 34 disjoint index pairs (out of 55 index pairs), introduced 0 new quantified variables, introduced 2 case distinctions, treesize of input 196 treesize of output 192 [2018-11-28 13:07:49,895 INFO L267 ElimStorePlain]: Start of recursive call 29: End of recursive call: and 2 xjuncts. [2018-11-28 13:07:50,149 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:07:50,150 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:07:50,153 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:07:50,157 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:07:50,159 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:07:50,162 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:07:50,162 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:07:50,163 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:07:50,164 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:07:50,165 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:07:50,166 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 10 select indices, 10 select index equivalence classes, 33 disjoint index pairs (out of 45 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 152 treesize of output 220 [2018-11-28 13:07:50,167 INFO L267 ElimStorePlain]: Start of recursive call 30: End of recursive call: and 1 xjuncts. [2018-11-28 13:07:50,393 INFO L267 ElimStorePlain]: Start of recursive call 28: 2 dim-1 vars, End of recursive call: and 3 xjuncts. [2018-11-28 13:07:50,689 INFO L267 ElimStorePlain]: Start of recursive call 25: 2 dim-1 vars, End of recursive call: and 4 xjuncts. [2018-11-28 13:07:50,994 INFO L267 ElimStorePlain]: Start of recursive call 21: 2 dim-1 vars, End of recursive call: and 5 xjuncts. [2018-11-28 13:07:51,340 INFO L267 ElimStorePlain]: Start of recursive call 16: 2 dim-1 vars, End of recursive call: and 6 xjuncts. [2018-11-28 13:07:51,745 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:07:51,748 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:07:51,755 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:07:51,766 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:07:51,769 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:07:51,781 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:07:51,783 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:07:51,786 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:07:51,792 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:07:51,794 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:07:51,797 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:07:51,798 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 7 select indices, 7 select index equivalence classes, 16 disjoint index pairs (out of 21 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 94 treesize of output 146 [2018-11-28 13:07:51,820 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 7 select indices, 7 select index equivalence classes, 16 disjoint index pairs (out of 21 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 71 treesize of output 128 [2018-11-28 13:07:51,848 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 7 select indices, 7 select index equivalence classes, 16 disjoint index pairs (out of 21 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 65 treesize of output 122 [2018-11-28 13:07:51,928 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 9 select indices, 9 select index equivalence classes, 25 disjoint index pairs (out of 36 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 55 treesize of output 153 [2018-11-28 13:07:51,945 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 10 select indices, 10 select index equivalence classes, 25 disjoint index pairs (out of 45 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 57 treesize of output 150 [2018-11-28 13:07:51,946 INFO L267 ElimStorePlain]: Start of recursive call 35: End of recursive call: and 1 xjuncts. [2018-11-28 13:07:51,986 INFO L267 ElimStorePlain]: Start of recursive call 34: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-28 13:07:52,026 INFO L267 ElimStorePlain]: Start of recursive call 33: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-28 13:07:52,066 INFO L267 ElimStorePlain]: Start of recursive call 32: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-28 13:07:52,115 INFO L267 ElimStorePlain]: Start of recursive call 31: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-28 13:07:52,508 INFO L267 ElimStorePlain]: Start of recursive call 15: 2 dim-1 vars, End of recursive call: and 7 xjuncts. [2018-11-28 13:07:52,986 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:07:52,989 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:07:52,992 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:07:52,994 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:07:53,001 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:07:53,008 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:07:53,014 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:07:53,017 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:07:53,019 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:07:53,020 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 6 select indices, 6 select index equivalence classes, 13 disjoint index pairs (out of 15 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 102 treesize of output 143 [2018-11-28 13:07:53,190 WARN L180 SmtUtils]: Spent 168.00 ms on a formula simplification. DAG size of input: 72 DAG size of output: 54 [2018-11-28 13:07:53,195 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:07:53,198 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:07:53,205 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:07:53,213 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:07:53,216 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:07:53,223 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:07:53,225 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:07:53,228 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:07:53,231 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:07:53,234 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:07:53,236 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:07:53,237 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 7 select indices, 7 select index equivalence classes, 19 disjoint index pairs (out of 21 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 71 treesize of output 146 [2018-11-28 13:07:53,253 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 7 select indices, 7 select index equivalence classes, 19 disjoint index pairs (out of 21 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 71 treesize of output 140 [2018-11-28 13:07:53,284 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 7 select indices, 7 select index equivalence classes, 19 disjoint index pairs (out of 21 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 65 treesize of output 134 [2018-11-28 13:07:53,367 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 9 select indices, 9 select index equivalence classes, 28 disjoint index pairs (out of 36 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 55 treesize of output 165 [2018-11-28 13:07:53,381 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 10 select indices, 10 select index equivalence classes, 28 disjoint index pairs (out of 45 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 57 treesize of output 162 [2018-11-28 13:07:53,382 INFO L267 ElimStorePlain]: Start of recursive call 41: End of recursive call: and 1 xjuncts. [2018-11-28 13:07:53,427 INFO L267 ElimStorePlain]: Start of recursive call 40: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-28 13:07:53,478 INFO L267 ElimStorePlain]: Start of recursive call 39: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-28 13:07:53,529 INFO L267 ElimStorePlain]: Start of recursive call 38: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-28 13:07:53,576 INFO L267 ElimStorePlain]: Start of recursive call 37: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-28 13:07:53,627 INFO L267 ElimStorePlain]: Start of recursive call 36: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-28 13:07:54,066 INFO L267 ElimStorePlain]: Start of recursive call 14: 2 dim-1 vars, End of recursive call: and 8 xjuncts. [2018-11-28 13:07:54,589 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:07:54,593 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:07:54,597 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:07:54,619 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:07:54,620 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 4 select indices, 4 select index equivalence classes, 7 disjoint index pairs (out of 6 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 108 treesize of output 127 [2018-11-28 13:07:54,759 WARN L180 SmtUtils]: Spent 138.00 ms on a formula simplification. DAG size of input: 59 DAG size of output: 45 [2018-11-28 13:07:54,765 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:07:54,768 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:07:54,770 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:07:54,772 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:07:54,779 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:07:54,786 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:07:54,793 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:07:54,796 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:07:54,803 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:07:54,803 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 6 select indices, 6 select index equivalence classes, 12 disjoint index pairs (out of 15 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 83 treesize of output 127 [2018-11-28 13:07:54,952 WARN L180 SmtUtils]: Spent 147.00 ms on a formula simplification. DAG size of input: 64 DAG size of output: 52 [2018-11-28 13:07:54,958 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:07:54,964 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:07:54,970 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:07:54,973 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:07:54,979 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:07:54,982 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:07:54,984 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:07:54,990 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:07:54,993 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:07:54,995 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:07:54,996 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 7 select indices, 7 select index equivalence classes, 18 disjoint index pairs (out of 21 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 71 treesize of output 142 [2018-11-28 13:07:55,013 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 7 select indices, 7 select index equivalence classes, 18 disjoint index pairs (out of 21 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 71 treesize of output 136 [2018-11-28 13:07:55,047 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 7 select indices, 7 select index equivalence classes, 18 disjoint index pairs (out of 21 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 65 treesize of output 130 [2018-11-28 13:07:55,128 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 9 select indices, 9 select index equivalence classes, 27 disjoint index pairs (out of 36 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 55 treesize of output 161 [2018-11-28 13:07:55,147 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 10 select indices, 10 select index equivalence classes, 27 disjoint index pairs (out of 45 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 57 treesize of output 158 [2018-11-28 13:07:55,147 INFO L267 ElimStorePlain]: Start of recursive call 48: End of recursive call: and 1 xjuncts. [2018-11-28 13:07:55,193 INFO L267 ElimStorePlain]: Start of recursive call 47: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-28 13:07:55,237 INFO L267 ElimStorePlain]: Start of recursive call 46: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-28 13:07:55,282 INFO L267 ElimStorePlain]: Start of recursive call 45: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-28 13:07:55,334 INFO L267 ElimStorePlain]: Start of recursive call 44: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-28 13:07:55,387 INFO L267 ElimStorePlain]: Start of recursive call 43: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-28 13:07:55,443 INFO L267 ElimStorePlain]: Start of recursive call 42: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-28 13:07:55,948 INFO L267 ElimStorePlain]: Start of recursive call 13: 2 dim-1 vars, End of recursive call: and 9 xjuncts. [2018-11-28 13:07:56,484 INFO L267 ElimStorePlain]: Start of recursive call 4: 2 dim-1 vars, End of recursive call: and 10 xjuncts. [2018-11-28 13:07:57,099 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 119 treesize of output 109 [2018-11-28 13:07:57,118 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 106 treesize of output 96 [2018-11-28 13:07:57,132 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:07:57,133 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:07:57,134 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:07:57,139 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:07:57,140 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 4 select indices, 4 select index equivalence classes, 5 disjoint index pairs (out of 6 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 93 treesize of output 108 [2018-11-28 13:07:57,242 WARN L180 SmtUtils]: Spent 101.00 ms on a formula simplification. DAG size of input: 50 DAG size of output: 40 [2018-11-28 13:07:57,248 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:07:57,252 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:07:57,255 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:07:57,262 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:07:57,274 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:07:57,285 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:07:57,288 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:07:57,294 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:07:57,295 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 6 select indices, 6 select index equivalence classes, 10 disjoint index pairs (out of 15 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 83 treesize of output 119 [2018-11-28 13:07:57,429 WARN L180 SmtUtils]: Spent 133.00 ms on a formula simplification. DAG size of input: 60 DAG size of output: 48 [2018-11-28 13:07:57,435 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:07:57,442 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:07:57,453 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:07:57,456 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:07:57,466 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:07:57,469 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:07:57,471 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:07:57,478 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:07:57,480 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:07:57,483 INFO L701 Elim1Store]: detected not equals via solver [2018-11-28 13:07:57,483 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 7 select indices, 7 select index equivalence classes, 16 disjoint index pairs (out of 21 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 71 treesize of output 134 [2018-11-28 13:07:57,506 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 7 select indices, 7 select index equivalence classes, 16 disjoint index pairs (out of 21 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 71 treesize of output 128 [2018-11-28 13:07:57,545 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 7 select indices, 7 select index equivalence classes, 16 disjoint index pairs (out of 21 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 65 treesize of output 122 [2018-11-28 13:07:57,625 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 9 select indices, 9 select index equivalence classes, 25 disjoint index pairs (out of 36 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 55 treesize of output 153 [2018-11-28 13:07:57,642 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 10 select indices, 10 select index equivalence classes, 25 disjoint index pairs (out of 45 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 57 treesize of output 150 [2018-11-28 13:07:57,643 INFO L267 ElimStorePlain]: Start of recursive call 57: End of recursive call: and 1 xjuncts. [2018-11-28 13:07:57,684 INFO L267 ElimStorePlain]: Start of recursive call 56: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-28 13:07:57,731 INFO L267 ElimStorePlain]: Start of recursive call 55: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-28 13:07:57,789 INFO L267 ElimStorePlain]: Start of recursive call 54: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-28 13:07:57,837 INFO L267 ElimStorePlain]: Start of recursive call 53: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-28 13:07:57,887 INFO L267 ElimStorePlain]: Start of recursive call 52: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-28 13:07:57,933 INFO L267 ElimStorePlain]: Start of recursive call 51: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-28 13:07:57,976 INFO L267 ElimStorePlain]: Start of recursive call 50: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-28 13:07:58,021 INFO L267 ElimStorePlain]: Start of recursive call 49: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-28 13:07:58,610 INFO L267 ElimStorePlain]: Start of recursive call 3: 2 dim-1 vars, End of recursive call: and 11 xjuncts. [2018-11-28 13:07:59,174 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 11 xjuncts. [2018-11-28 13:07:59,762 INFO L267 ElimStorePlain]: Start of recursive call 1: 9 dim-0 vars, 1 dim-1 vars, End of recursive call: 90 dim-0 vars, and 11 xjuncts. [2018-11-28 13:07:59,762 INFO L202 ElimStorePlain]: Needed 57 recursive calls to eliminate 10 variables, input treesize:151, output treesize:1736 [2018-11-28 13:08:21,236 WARN L194 Executor]: External (z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000) stderr output: (error "out of memory") [2018-11-28 13:08:21,436 WARN L521 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 15 z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-28 13:08:21,437 FATAL L265 ToolchainWalker]: An unrecoverable error occured during an interaction with an SMT solver: de.uni_freiburg.informatik.ultimate.logic.SMTLIBException: External (z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000)Received EOF on stdin. stderr output: (error "out of memory") at de.uni_freiburg.informatik.ultimate.smtsolver.external.Executor.parse(Executor.java:208) at de.uni_freiburg.informatik.ultimate.smtsolver.external.Executor.parseCheckSatResult(Executor.java:225) at de.uni_freiburg.informatik.ultimate.smtsolver.external.Scriptor.checkSat(Scriptor.java:155) at de.uni_freiburg.informatik.ultimate.modelcheckerutils.smt.WrapperScript.checkSat(WrapperScript.java:116) at de.uni_freiburg.informatik.ultimate.modelcheckerutils.smt.WrapperScript.checkSat(WrapperScript.java:116) at de.uni_freiburg.informatik.ultimate.logic.Util.checkSat(Util.java:61) at de.uni_freiburg.informatik.ultimate.logic.simplification.SimplifyDDA.getRedundancy(SimplifyDDA.java:626) at de.uni_freiburg.informatik.ultimate.modelcheckerutils.smt.SimplifyDDAWithTimeout.getRedundancy(SimplifyDDAWithTimeout.java:122) at de.uni_freiburg.informatik.ultimate.logic.simplification.SimplifyDDA$Simplifier.walk(SimplifyDDA.java:371) at de.uni_freiburg.informatik.ultimate.logic.NonRecursive.run(NonRecursive.java:122) at de.uni_freiburg.informatik.ultimate.logic.NonRecursive.run(NonRecursive.java:113) at de.uni_freiburg.informatik.ultimate.logic.simplification.SimplifyDDA.simplifyOnce(SimplifyDDA.java:650) at de.uni_freiburg.informatik.ultimate.modelcheckerutils.smt.SimplifyDDAWithTimeout.getSimplifiedTerm(SimplifyDDAWithTimeout.java:187) at de.uni_freiburg.informatik.ultimate.modelcheckerutils.smt.SmtUtils.simplify(SmtUtils.java:151) at de.uni_freiburg.informatik.ultimate.modelcheckerutils.smt.predicates.PredicateUnifier.getOrConstructPredicate(PredicateUnifier.java:354) at de.uni_freiburg.informatik.ultimate.modelcheckerutils.smt.predicates.PredicateUnifier.getOrConstructPredicate(PredicateUnifier.java:299) at de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.singletracecheck.TraceCheckSpWp$UnifyPostprocessor.postprocess(TraceCheckSpWp.java:575) at de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.predicates.IterativePredicateTransformer.applyPostprocessors(IterativePredicateTransformer.java:439) at de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.predicates.IterativePredicateTransformer.computeStrongestPostconditionSequence(IterativePredicateTransformer.java:200) at de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.singletracecheck.TraceCheckSpWp.computeInterpolantsUsingUnsatCore(TraceCheckSpWp.java:286) at de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.singletracecheck.TraceCheckSpWp.computeInterpolants(TraceCheckSpWp.java:175) at de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.singletracecheck.TraceCheckSpWp.(TraceCheckSpWp.java:162) at de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.tracehandling.TraceCheckConstructor.constructForwardBackward(TraceCheckConstructor.java:224) at de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.tracehandling.TraceCheckConstructor.constructTraceCheck(TraceCheckConstructor.java:188) at de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.tracehandling.TraceCheckConstructor.get(TraceCheckConstructor.java:165) at de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.tracehandling.MultiTrackRefinementStrategy.getTraceCheck(MultiTrackRefinementStrategy.java:232) at de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.tracehandling.BaseRefinementStrategy.checkFeasibility(BaseRefinementStrategy.java:223) at de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.tracehandling.BaseRefinementStrategy.executeStrategy(BaseRefinementStrategy.java:197) at de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.tracehandling.TraceAbstractionRefinementEngine.(TraceAbstractionRefinementEngine.java:70) at de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.BasicCegarLoop.isCounterexampleFeasible(BasicCegarLoop.java:456) at de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.AbstractCegarLoop.iterateInternal(AbstractCegarLoop.java:434) at de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.AbstractCegarLoop.iterate(AbstractCegarLoop.java:376) at de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionStarter.iterate(TraceAbstractionStarter.java:334) at de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionStarter.runCegarLoops(TraceAbstractionStarter.java:174) at de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionStarter.(TraceAbstractionStarter.java:126) at de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver.finish(TraceAbstractionObserver.java:123) at de.uni_freiburg.informatik.ultimate.core.coreplugin.PluginConnector.runObserver(PluginConnector.java:168) at de.uni_freiburg.informatik.ultimate.core.coreplugin.PluginConnector.runTool(PluginConnector.java:151) at de.uni_freiburg.informatik.ultimate.core.coreplugin.PluginConnector.run(PluginConnector.java:128) at de.uni_freiburg.informatik.ultimate.core.coreplugin.ToolchainWalker.executePluginConnector(ToolchainWalker.java:232) at de.uni_freiburg.informatik.ultimate.core.coreplugin.ToolchainWalker.processPlugin(ToolchainWalker.java:226) at de.uni_freiburg.informatik.ultimate.core.coreplugin.ToolchainWalker.walkUnprotected(ToolchainWalker.java:142) at de.uni_freiburg.informatik.ultimate.core.coreplugin.ToolchainWalker.walk(ToolchainWalker.java:104) at de.uni_freiburg.informatik.ultimate.core.coreplugin.ToolchainManager$Toolchain.processToolchain(ToolchainManager.java:316) at de.uni_freiburg.informatik.ultimate.core.coreplugin.toolchain.DefaultToolchainJob.run(DefaultToolchainJob.java:145) at org.eclipse.core.internal.jobs.Worker.run(Worker.java:55) Caused by: de.uni_freiburg.informatik.ultimate.logic.SMTLIBException: EOF at de.uni_freiburg.informatik.ultimate.smtsolver.external.Parser$Action$.CUP$do_action(Parser.java:1427) at de.uni_freiburg.informatik.ultimate.smtsolver.external.Parser.do_action(Parser.java:630) at com.github.jhoenicke.javacup.runtime.LRParser.parse(LRParser.java:419) at de.uni_freiburg.informatik.ultimate.smtsolver.external.Executor.parse(Executor.java:205) ... 45 more [2018-11-28 13:08:21,440 INFO L168 Benchmark]: Toolchain (without parser) took 95805.37 ms. Allocated memory was 1.0 GB in the beginning and 1.9 GB in the end (delta: 836.8 MB). Free memory was 950.6 MB in the beginning and 1.0 GB in the end (delta: -56.4 MB). Peak memory consumption was 780.4 MB. Max. memory is 11.5 GB. [2018-11-28 13:08:21,440 INFO L168 Benchmark]: CDTParser took 0.11 ms. Allocated memory is still 1.0 GB. Free memory is still 979.6 MB. There was no memory consumed. Max. memory is 11.5 GB. [2018-11-28 13:08:21,441 INFO L168 Benchmark]: CACSL2BoogieTranslator took 746.03 ms. Allocated memory was 1.0 GB in the beginning and 1.2 GB in the end (delta: 123.2 MB). Free memory was 950.6 MB in the beginning and 1.0 GB in the end (delta: -96.2 MB). Peak memory consumption was 40.3 MB. Max. memory is 11.5 GB. [2018-11-28 13:08:21,441 INFO L168 Benchmark]: Boogie Procedure Inliner took 40.98 ms. Allocated memory is still 1.2 GB. Free memory was 1.0 GB in the beginning and 1.0 GB in the end (delta: 2.7 MB). Peak memory consumption was 2.7 MB. Max. memory is 11.5 GB. [2018-11-28 13:08:21,441 INFO L168 Benchmark]: Boogie Preprocessor took 54.20 ms. Allocated memory is still 1.2 GB. Free memory was 1.0 GB in the beginning and 1.0 GB in the end (delta: 5.4 MB). Peak memory consumption was 5.4 MB. Max. memory is 11.5 GB. [2018-11-28 13:08:21,441 INFO L168 Benchmark]: RCFGBuilder took 740.32 ms. Allocated memory is still 1.2 GB. Free memory was 1.0 GB in the beginning and 962.7 MB in the end (delta: 76.1 MB). Peak memory consumption was 76.1 MB. Max. memory is 11.5 GB. [2018-11-28 13:08:21,441 INFO L168 Benchmark]: TraceAbstraction took 94220.19 ms. Allocated memory was 1.2 GB in the beginning and 1.9 GB in the end (delta: 713.6 MB). Free memory was 960.0 MB in the beginning and 1.0 GB in the end (delta: -47.0 MB). Peak memory consumption was 666.5 MB. Max. memory is 11.5 GB. [2018-11-28 13:08:21,443 INFO L336 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.11 ms. Allocated memory is still 1.0 GB. Free memory is still 979.6 MB. There was no memory consumed. Max. memory is 11.5 GB. * CACSL2BoogieTranslator took 746.03 ms. Allocated memory was 1.0 GB in the beginning and 1.2 GB in the end (delta: 123.2 MB). Free memory was 950.6 MB in the beginning and 1.0 GB in the end (delta: -96.2 MB). Peak memory consumption was 40.3 MB. Max. memory is 11.5 GB. * Boogie Procedure Inliner took 40.98 ms. Allocated memory is still 1.2 GB. Free memory was 1.0 GB in the beginning and 1.0 GB in the end (delta: 2.7 MB). Peak memory consumption was 2.7 MB. Max. memory is 11.5 GB. * Boogie Preprocessor took 54.20 ms. Allocated memory is still 1.2 GB. Free memory was 1.0 GB in the beginning and 1.0 GB in the end (delta: 5.4 MB). Peak memory consumption was 5.4 MB. Max. memory is 11.5 GB. * RCFGBuilder took 740.32 ms. Allocated memory is still 1.2 GB. Free memory was 1.0 GB in the beginning and 962.7 MB in the end (delta: 76.1 MB). Peak memory consumption was 76.1 MB. Max. memory is 11.5 GB. * TraceAbstraction took 94220.19 ms. Allocated memory was 1.2 GB in the beginning and 1.9 GB in the end (delta: 713.6 MB). Free memory was 960.0 MB in the beginning and 1.0 GB in the end (delta: -47.0 MB). Peak memory consumption was 666.5 MB. Max. memory is 11.5 GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - ExceptionOrErrorResult: SMTLIBException: External (z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000)Received EOF on stdin. stderr output: (error "out of memory") de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: SMTLIBException: External (z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000)Received EOF on stdin. stderr output: (error "out of memory") : de.uni_freiburg.informatik.ultimate.smtsolver.external.Executor.parse(Executor.java:208) RESULT: Ultimate could not prove your program: Toolchain returned no result. Received shutdown request...