./Ultimate.py --spec ../../sv-benchmarks/c/properties/unreach-call.prp --file ../../sv-benchmarks/c/systemc/kundu1_false-unreach-call_false-termination.cil.c --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for ERROR reachability Using default analysis Version 0cd3be1d Calling Ultimate with: java -Dosgi.configuration.area=/tmp/vcloud-vcloud-master/worker/working_dir_0205b283-43b4-4d39-9152-1c66ac810fde/bin-2019/uautomizer/data/config -Xmx12G -Xms1G -jar /tmp/vcloud-vcloud-master/worker/working_dir_0205b283-43b4-4d39-9152-1c66ac810fde/bin-2019/uautomizer/plugins/org.eclipse.equinox.launcher_1.3.100.v20150511-1540.jar -data @noDefault -ultimatedata /tmp/vcloud-vcloud-master/worker/working_dir_0205b283-43b4-4d39-9152-1c66ac810fde/bin-2019/uautomizer/data -tc /tmp/vcloud-vcloud-master/worker/working_dir_0205b283-43b4-4d39-9152-1c66ac810fde/bin-2019/uautomizer/config/AutomizerReach.xml -i ../../sv-benchmarks/c/systemc/kundu1_false-unreach-call_false-termination.cil.c -s /tmp/vcloud-vcloud-master/worker/working_dir_0205b283-43b4-4d39-9152-1c66ac810fde/bin-2019/uautomizer/config/svcomp-Reach-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud-vcloud-master/worker/working_dir_0205b283-43b4-4d39-9152-1c66ac810fde/bin-2019/uautomizer --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(G ! call(__VERIFIER_error())) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash 532163d21d7e473fbfa4a073427e9fd2a45c7337 ....................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................... Execution finished normally Writing output log to file Ultimate.log Writing human readable error path to file UltimateCounterExample.errorpath Result: FALSE --- Real Ultimate output --- This is Ultimate 0.1.23-0cd3be1 [2018-11-28 11:28:25,309 INFO L170 SettingsManager]: Resetting all preferences to default values... [2018-11-28 11:28:25,310 INFO L174 SettingsManager]: Resetting UltimateCore preferences to default values [2018-11-28 11:28:25,317 INFO L177 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2018-11-28 11:28:25,317 INFO L174 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2018-11-28 11:28:25,318 INFO L174 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2018-11-28 11:28:25,319 INFO L174 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2018-11-28 11:28:25,320 INFO L174 SettingsManager]: Resetting LassoRanker preferences to default values [2018-11-28 11:28:25,321 INFO L174 SettingsManager]: Resetting Reaching Definitions preferences to default values [2018-11-28 11:28:25,322 INFO L174 SettingsManager]: Resetting SyntaxChecker preferences to default values [2018-11-28 11:28:25,322 INFO L177 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2018-11-28 11:28:25,322 INFO L174 SettingsManager]: Resetting LTL2Aut preferences to default values [2018-11-28 11:28:25,323 INFO L174 SettingsManager]: Resetting PEA to Boogie preferences to default values [2018-11-28 11:28:25,323 INFO L174 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2018-11-28 11:28:25,324 INFO L174 SettingsManager]: Resetting ChcToBoogie preferences to default values [2018-11-28 11:28:25,324 INFO L174 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2018-11-28 11:28:25,325 INFO L174 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2018-11-28 11:28:25,326 INFO L174 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2018-11-28 11:28:25,327 INFO L174 SettingsManager]: Resetting CodeCheck preferences to default values [2018-11-28 11:28:25,328 INFO L174 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2018-11-28 11:28:25,329 INFO L174 SettingsManager]: Resetting RCFGBuilder preferences to default values [2018-11-28 11:28:25,330 INFO L174 SettingsManager]: Resetting TraceAbstraction preferences to default values [2018-11-28 11:28:25,332 INFO L177 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2018-11-28 11:28:25,332 INFO L177 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2018-11-28 11:28:25,332 INFO L174 SettingsManager]: Resetting TreeAutomizer preferences to default values [2018-11-28 11:28:25,333 INFO L174 SettingsManager]: Resetting IcfgTransformer preferences to default values [2018-11-28 11:28:25,333 INFO L174 SettingsManager]: Resetting Boogie Printer preferences to default values [2018-11-28 11:28:25,333 INFO L174 SettingsManager]: Resetting ReqPrinter preferences to default values [2018-11-28 11:28:25,334 INFO L174 SettingsManager]: Resetting Witness Printer preferences to default values [2018-11-28 11:28:25,334 INFO L177 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2018-11-28 11:28:25,334 INFO L174 SettingsManager]: Resetting CDTParser preferences to default values [2018-11-28 11:28:25,335 INFO L177 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2018-11-28 11:28:25,335 INFO L177 SettingsManager]: ReqParser provides no preferences, ignoring... [2018-11-28 11:28:25,335 INFO L174 SettingsManager]: Resetting SmtParser preferences to default values [2018-11-28 11:28:25,336 INFO L174 SettingsManager]: Resetting Witness Parser preferences to default values [2018-11-28 11:28:25,336 INFO L181 SettingsManager]: Finished resetting all preferences to default values... [2018-11-28 11:28:25,336 INFO L98 SettingsManager]: Beginning loading settings from /tmp/vcloud-vcloud-master/worker/working_dir_0205b283-43b4-4d39-9152-1c66ac810fde/bin-2019/uautomizer/config/svcomp-Reach-32bit-Automizer_Default.epf [2018-11-28 11:28:25,343 INFO L110 SettingsManager]: Loading preferences was successful [2018-11-28 11:28:25,344 INFO L112 SettingsManager]: Preferences different from defaults after loading the file: [2018-11-28 11:28:25,344 INFO L131 SettingsManager]: Preferences of Boogie Procedure Inliner differ from their defaults: [2018-11-28 11:28:25,344 INFO L133 SettingsManager]: * ... calls to implemented procedures=ONLY_FOR_CONCURRENT_PROGRAMS [2018-11-28 11:28:25,345 INFO L131 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2018-11-28 11:28:25,345 INFO L133 SettingsManager]: * Create parallel compositions if possible=false [2018-11-28 11:28:25,345 INFO L133 SettingsManager]: * Use SBE=true [2018-11-28 11:28:25,345 INFO L131 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2018-11-28 11:28:25,346 INFO L133 SettingsManager]: * sizeof long=4 [2018-11-28 11:28:25,346 INFO L133 SettingsManager]: * Overapproximate operations on floating types=true [2018-11-28 11:28:25,346 INFO L133 SettingsManager]: * sizeof POINTER=4 [2018-11-28 11:28:25,346 INFO L133 SettingsManager]: * Check division by zero=IGNORE [2018-11-28 11:28:25,346 INFO L133 SettingsManager]: * Pointer to allocated memory at dereference=IGNORE [2018-11-28 11:28:25,346 INFO L133 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=IGNORE [2018-11-28 11:28:25,346 INFO L133 SettingsManager]: * Check array bounds for arrays that are off heap=IGNORE [2018-11-28 11:28:25,346 INFO L133 SettingsManager]: * sizeof long double=12 [2018-11-28 11:28:25,347 INFO L133 SettingsManager]: * Check if freed pointer was valid=false [2018-11-28 11:28:25,347 INFO L133 SettingsManager]: * Use constant arrays=true [2018-11-28 11:28:25,347 INFO L133 SettingsManager]: * Pointer base address is valid at dereference=IGNORE [2018-11-28 11:28:25,347 INFO L131 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2018-11-28 11:28:25,347 INFO L133 SettingsManager]: * Size of a code block=SequenceOfStatements [2018-11-28 11:28:25,347 INFO L133 SettingsManager]: * To the following directory=./dump/ [2018-11-28 11:28:25,347 INFO L133 SettingsManager]: * SMT solver=External_DefaultMode [2018-11-28 11:28:25,348 INFO L133 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2018-11-28 11:28:25,348 INFO L131 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2018-11-28 11:28:25,348 INFO L133 SettingsManager]: * Compute Interpolants along a Counterexample=FPandBP [2018-11-28 11:28:25,348 INFO L133 SettingsManager]: * Positions where we compute the Hoare Annotation=LoopsAndPotentialCycles [2018-11-28 11:28:25,348 INFO L133 SettingsManager]: * Trace refinement strategy=CAMEL [2018-11-28 11:28:25,348 INFO L133 SettingsManager]: * SMT solver=External_ModelsAndUnsatCoreMode [2018-11-28 11:28:25,348 INFO L133 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in [2018-11-28 11:28:25,348 INFO L133 SettingsManager]: * Compute Hoare Annotation of negated interpolant automaton, abstraction and CFG=true Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud-vcloud-master/worker/working_dir_0205b283-43b4-4d39-9152-1c66ac810fde/bin-2019/uautomizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(G ! call(__VERIFIER_error())) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> 532163d21d7e473fbfa4a073427e9fd2a45c7337 [2018-11-28 11:28:25,377 INFO L81 nceAwareModelManager]: Repository-Root is: /tmp [2018-11-28 11:28:25,386 INFO L258 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2018-11-28 11:28:25,389 INFO L214 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2018-11-28 11:28:25,390 INFO L271 PluginConnector]: Initializing CDTParser... [2018-11-28 11:28:25,390 INFO L276 PluginConnector]: CDTParser initialized [2018-11-28 11:28:25,391 INFO L418 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud-vcloud-master/worker/working_dir_0205b283-43b4-4d39-9152-1c66ac810fde/bin-2019/uautomizer/../../sv-benchmarks/c/systemc/kundu1_false-unreach-call_false-termination.cil.c [2018-11-28 11:28:25,436 INFO L221 CDTParser]: Created temporary CDT project at /tmp/vcloud-vcloud-master/worker/working_dir_0205b283-43b4-4d39-9152-1c66ac810fde/bin-2019/uautomizer/data/940599ec9/f3c0a8f41af946bc8e616d0db677112f/FLAG70a5ef66f [2018-11-28 11:28:25,850 INFO L307 CDTParser]: Found 1 translation units. [2018-11-28 11:28:25,850 INFO L161 CDTParser]: Scanning /tmp/vcloud-vcloud-master/worker/working_dir_0205b283-43b4-4d39-9152-1c66ac810fde/sv-benchmarks/c/systemc/kundu1_false-unreach-call_false-termination.cil.c [2018-11-28 11:28:25,856 INFO L355 CDTParser]: About to delete temporary CDT project at /tmp/vcloud-vcloud-master/worker/working_dir_0205b283-43b4-4d39-9152-1c66ac810fde/bin-2019/uautomizer/data/940599ec9/f3c0a8f41af946bc8e616d0db677112f/FLAG70a5ef66f [2018-11-28 11:28:25,866 INFO L363 CDTParser]: Successfully deleted /tmp/vcloud-vcloud-master/worker/working_dir_0205b283-43b4-4d39-9152-1c66ac810fde/bin-2019/uautomizer/data/940599ec9/f3c0a8f41af946bc8e616d0db677112f [2018-11-28 11:28:25,868 INFO L296 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2018-11-28 11:28:25,869 INFO L131 ToolchainWalker]: Walking toolchain with 6 elements. [2018-11-28 11:28:25,870 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2018-11-28 11:28:25,870 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2018-11-28 11:28:25,873 INFO L276 PluginConnector]: CACSL2BoogieTranslator initialized [2018-11-28 11:28:25,874 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 28.11 11:28:25" (1/1) ... [2018-11-28 11:28:25,876 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@5abee42f and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 11:28:25, skipping insertion in model container [2018-11-28 11:28:25,876 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 28.11 11:28:25" (1/1) ... [2018-11-28 11:28:25,882 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2018-11-28 11:28:25,902 INFO L176 MainTranslator]: Built tables and reachable declarations [2018-11-28 11:28:26,029 INFO L203 PostProcessor]: Analyzing one entry point: main [2018-11-28 11:28:26,032 INFO L191 MainTranslator]: Completed pre-run [2018-11-28 11:28:26,053 INFO L203 PostProcessor]: Analyzing one entry point: main [2018-11-28 11:28:26,066 INFO L195 MainTranslator]: Completed translation [2018-11-28 11:28:26,066 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 11:28:26 WrapperNode [2018-11-28 11:28:26,066 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2018-11-28 11:28:26,067 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2018-11-28 11:28:26,067 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2018-11-28 11:28:26,067 INFO L276 PluginConnector]: Boogie Procedure Inliner initialized [2018-11-28 11:28:26,072 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 11:28:26" (1/1) ... [2018-11-28 11:28:26,076 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 11:28:26" (1/1) ... [2018-11-28 11:28:26,118 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2018-11-28 11:28:26,118 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2018-11-28 11:28:26,118 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2018-11-28 11:28:26,118 INFO L276 PluginConnector]: Boogie Preprocessor initialized [2018-11-28 11:28:26,125 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 11:28:26" (1/1) ... [2018-11-28 11:28:26,125 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 11:28:26" (1/1) ... [2018-11-28 11:28:26,126 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 11:28:26" (1/1) ... [2018-11-28 11:28:26,127 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 11:28:26" (1/1) ... [2018-11-28 11:28:26,131 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 11:28:26" (1/1) ... [2018-11-28 11:28:26,137 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 11:28:26" (1/1) ... [2018-11-28 11:28:26,138 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 11:28:26" (1/1) ... [2018-11-28 11:28:26,139 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2018-11-28 11:28:26,140 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2018-11-28 11:28:26,140 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2018-11-28 11:28:26,140 INFO L276 PluginConnector]: RCFGBuilder initialized [2018-11-28 11:28:26,140 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 11:28:26" (1/1) ... No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_0205b283-43b4-4d39-9152-1c66ac810fde/bin-2019/uautomizer/z3 Starting monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2018-11-28 11:28:26,173 INFO L130 BoogieDeclarations]: Found specification of procedure P_1 [2018-11-28 11:28:26,173 INFO L138 BoogieDeclarations]: Found implementation of procedure P_1 [2018-11-28 11:28:26,173 INFO L130 BoogieDeclarations]: Found specification of procedure write_data [2018-11-28 11:28:26,173 INFO L138 BoogieDeclarations]: Found implementation of procedure write_data [2018-11-28 11:28:26,173 INFO L130 BoogieDeclarations]: Found specification of procedure main [2018-11-28 11:28:26,173 INFO L138 BoogieDeclarations]: Found implementation of procedure main [2018-11-28 11:28:26,173 INFO L130 BoogieDeclarations]: Found specification of procedure error [2018-11-28 11:28:26,174 INFO L138 BoogieDeclarations]: Found implementation of procedure error [2018-11-28 11:28:26,174 INFO L130 BoogieDeclarations]: Found specification of procedure stop_simulation [2018-11-28 11:28:26,174 INFO L138 BoogieDeclarations]: Found implementation of procedure stop_simulation [2018-11-28 11:28:26,174 INFO L130 BoogieDeclarations]: Found specification of procedure fire_delta_events [2018-11-28 11:28:26,174 INFO L138 BoogieDeclarations]: Found implementation of procedure fire_delta_events [2018-11-28 11:28:26,174 INFO L130 BoogieDeclarations]: Found specification of procedure reset_time_events [2018-11-28 11:28:26,174 INFO L138 BoogieDeclarations]: Found implementation of procedure reset_time_events [2018-11-28 11:28:26,174 INFO L130 BoogieDeclarations]: Found specification of procedure activate_threads [2018-11-28 11:28:26,174 INFO L138 BoogieDeclarations]: Found implementation of procedure activate_threads [2018-11-28 11:28:26,175 INFO L130 BoogieDeclarations]: Found specification of procedure exists_runnable_thread [2018-11-28 11:28:26,175 INFO L138 BoogieDeclarations]: Found implementation of procedure exists_runnable_thread [2018-11-28 11:28:26,175 INFO L130 BoogieDeclarations]: Found specification of procedure reset_delta_events [2018-11-28 11:28:26,175 INFO L138 BoogieDeclarations]: Found implementation of procedure reset_delta_events [2018-11-28 11:28:26,175 INFO L130 BoogieDeclarations]: Found specification of procedure init_threads [2018-11-28 11:28:26,175 INFO L138 BoogieDeclarations]: Found implementation of procedure init_threads [2018-11-28 11:28:26,175 INFO L130 BoogieDeclarations]: Found specification of procedure is_P_1_triggered [2018-11-28 11:28:26,175 INFO L138 BoogieDeclarations]: Found implementation of procedure is_P_1_triggered [2018-11-28 11:28:26,175 INFO L130 BoogieDeclarations]: Found specification of procedure read_data [2018-11-28 11:28:26,176 INFO L138 BoogieDeclarations]: Found implementation of procedure read_data [2018-11-28 11:28:26,176 INFO L130 BoogieDeclarations]: Found specification of procedure fire_time_events [2018-11-28 11:28:26,176 INFO L138 BoogieDeclarations]: Found implementation of procedure fire_time_events [2018-11-28 11:28:26,176 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.init [2018-11-28 11:28:26,176 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.init [2018-11-28 11:28:26,176 INFO L130 BoogieDeclarations]: Found specification of procedure eval [2018-11-28 11:28:26,176 INFO L138 BoogieDeclarations]: Found implementation of procedure eval [2018-11-28 11:28:26,176 INFO L130 BoogieDeclarations]: Found specification of procedure C_1 [2018-11-28 11:28:26,176 INFO L138 BoogieDeclarations]: Found implementation of procedure C_1 [2018-11-28 11:28:26,176 INFO L130 BoogieDeclarations]: Found specification of procedure start_simulation [2018-11-28 11:28:26,176 INFO L138 BoogieDeclarations]: Found implementation of procedure start_simulation [2018-11-28 11:28:26,176 INFO L130 BoogieDeclarations]: Found specification of procedure update_channels [2018-11-28 11:28:26,176 INFO L138 BoogieDeclarations]: Found implementation of procedure update_channels [2018-11-28 11:28:26,176 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2018-11-28 11:28:26,177 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2018-11-28 11:28:26,177 INFO L130 BoogieDeclarations]: Found specification of procedure is_C_1_triggered [2018-11-28 11:28:26,177 INFO L138 BoogieDeclarations]: Found implementation of procedure is_C_1_triggered [2018-11-28 11:28:26,177 INFO L130 BoogieDeclarations]: Found specification of procedure init_model [2018-11-28 11:28:26,177 INFO L138 BoogieDeclarations]: Found implementation of procedure init_model [2018-11-28 11:28:26,502 INFO L275 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2018-11-28 11:28:26,503 INFO L280 CfgBuilder]: Removed 4 assue(true) statements. [2018-11-28 11:28:26,503 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 28.11 11:28:26 BoogieIcfgContainer [2018-11-28 11:28:26,503 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2018-11-28 11:28:26,504 INFO L113 PluginConnector]: ------------------------TraceAbstraction---------------------------- [2018-11-28 11:28:26,504 INFO L271 PluginConnector]: Initializing TraceAbstraction... [2018-11-28 11:28:26,505 INFO L276 PluginConnector]: TraceAbstraction initialized [2018-11-28 11:28:26,506 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "CDTParser AST 28.11 11:28:25" (1/3) ... [2018-11-28 11:28:26,506 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@3ec97b2f and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 28.11 11:28:26, skipping insertion in model container [2018-11-28 11:28:26,506 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 11:28:26" (2/3) ... [2018-11-28 11:28:26,506 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@3ec97b2f and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 28.11 11:28:26, skipping insertion in model container [2018-11-28 11:28:26,506 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 28.11 11:28:26" (3/3) ... [2018-11-28 11:28:26,508 INFO L112 eAbstractionObserver]: Analyzing ICFG kundu1_false-unreach-call_false-termination.cil.c [2018-11-28 11:28:26,514 INFO L156 ceAbstractionStarter]: Automizer settings: Hoare:true NWA Interpolation:FPandBP Determinization: PREDICATE_ABSTRACTION [2018-11-28 11:28:26,519 INFO L168 ceAbstractionStarter]: Appying trace abstraction to program that has 1 error locations. [2018-11-28 11:28:26,528 INFO L257 AbstractCegarLoop]: Starting to check reachability of 1 error locations. [2018-11-28 11:28:26,550 INFO L133 ementStrategyFactory]: Using default assertion order modulation [2018-11-28 11:28:26,551 INFO L382 AbstractCegarLoop]: Interprodecural is true [2018-11-28 11:28:26,551 INFO L383 AbstractCegarLoop]: Hoare is true [2018-11-28 11:28:26,551 INFO L384 AbstractCegarLoop]: Compute interpolants for FPandBP [2018-11-28 11:28:26,551 INFO L385 AbstractCegarLoop]: Backedges is STRAIGHT_LINE [2018-11-28 11:28:26,551 INFO L386 AbstractCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2018-11-28 11:28:26,551 INFO L387 AbstractCegarLoop]: Difference is false [2018-11-28 11:28:26,552 INFO L388 AbstractCegarLoop]: Minimize is MINIMIZE_SEVPA [2018-11-28 11:28:26,552 INFO L393 AbstractCegarLoop]: ======== Iteration 0==of CEGAR loop == AllErrorsAtOnce======== [2018-11-28 11:28:26,564 INFO L276 IsEmpty]: Start isEmpty. Operand 150 states. [2018-11-28 11:28:26,568 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 73 [2018-11-28 11:28:26,569 INFO L394 BasicCegarLoop]: Found error trace [2018-11-28 11:28:26,569 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-28 11:28:26,571 INFO L423 AbstractCegarLoop]: === Iteration 1 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-28 11:28:26,574 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-28 11:28:26,574 INFO L82 PathProgramCache]: Analyzing trace with hash -1385664965, now seen corresponding path program 1 times [2018-11-28 11:28:26,576 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-28 11:28:26,576 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-28 11:28:26,608 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 11:28:26,609 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-28 11:28:26,609 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 11:28:26,656 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-28 11:28:26,729 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-28 11:28:26,731 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-28 11:28:26,731 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2018-11-28 11:28:26,735 INFO L459 AbstractCegarLoop]: Interpolant automaton has 4 states [2018-11-28 11:28:26,743 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2018-11-28 11:28:26,744 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2018-11-28 11:28:26,746 INFO L87 Difference]: Start difference. First operand 150 states. Second operand 4 states. [2018-11-28 11:28:26,883 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-28 11:28:26,883 INFO L93 Difference]: Finished difference Result 282 states and 384 transitions. [2018-11-28 11:28:26,883 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2018-11-28 11:28:26,884 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 72 [2018-11-28 11:28:26,885 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-28 11:28:26,894 INFO L225 Difference]: With dead ends: 282 [2018-11-28 11:28:26,894 INFO L226 Difference]: Without dead ends: 140 [2018-11-28 11:28:26,896 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 4 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 2 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2018-11-28 11:28:26,907 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 140 states. [2018-11-28 11:28:26,931 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 140 to 140. [2018-11-28 11:28:26,932 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 140 states. [2018-11-28 11:28:26,934 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 140 states to 140 states and 179 transitions. [2018-11-28 11:28:26,935 INFO L78 Accepts]: Start accepts. Automaton has 140 states and 179 transitions. Word has length 72 [2018-11-28 11:28:26,937 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-28 11:28:26,937 INFO L480 AbstractCegarLoop]: Abstraction has 140 states and 179 transitions. [2018-11-28 11:28:26,937 INFO L481 AbstractCegarLoop]: Interpolant automaton has 4 states. [2018-11-28 11:28:26,937 INFO L276 IsEmpty]: Start isEmpty. Operand 140 states and 179 transitions. [2018-11-28 11:28:26,939 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 73 [2018-11-28 11:28:26,940 INFO L394 BasicCegarLoop]: Found error trace [2018-11-28 11:28:26,940 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-28 11:28:26,940 INFO L423 AbstractCegarLoop]: === Iteration 2 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-28 11:28:26,940 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-28 11:28:26,940 INFO L82 PathProgramCache]: Analyzing trace with hash -1426339715, now seen corresponding path program 1 times [2018-11-28 11:28:26,940 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-28 11:28:26,941 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-28 11:28:26,941 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 11:28:26,942 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-28 11:28:26,942 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 11:28:26,960 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-28 11:28:27,030 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-28 11:28:27,030 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-28 11:28:27,030 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2018-11-28 11:28:27,031 INFO L459 AbstractCegarLoop]: Interpolant automaton has 4 states [2018-11-28 11:28:27,032 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2018-11-28 11:28:27,032 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2018-11-28 11:28:27,032 INFO L87 Difference]: Start difference. First operand 140 states and 179 transitions. Second operand 4 states. [2018-11-28 11:28:27,253 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-28 11:28:27,254 INFO L93 Difference]: Finished difference Result 373 states and 490 transitions. [2018-11-28 11:28:27,254 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2018-11-28 11:28:27,254 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 72 [2018-11-28 11:28:27,254 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-28 11:28:27,257 INFO L225 Difference]: With dead ends: 373 [2018-11-28 11:28:27,257 INFO L226 Difference]: Without dead ends: 253 [2018-11-28 11:28:27,258 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 5 GetRequests, 2 SyntacticMatches, 1 SemanticMatches, 2 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2018-11-28 11:28:27,259 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 253 states. [2018-11-28 11:28:27,283 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 253 to 238. [2018-11-28 11:28:27,283 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 238 states. [2018-11-28 11:28:27,287 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 238 states to 238 states and 301 transitions. [2018-11-28 11:28:27,287 INFO L78 Accepts]: Start accepts. Automaton has 238 states and 301 transitions. Word has length 72 [2018-11-28 11:28:27,287 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-28 11:28:27,287 INFO L480 AbstractCegarLoop]: Abstraction has 238 states and 301 transitions. [2018-11-28 11:28:27,288 INFO L481 AbstractCegarLoop]: Interpolant automaton has 4 states. [2018-11-28 11:28:27,288 INFO L276 IsEmpty]: Start isEmpty. Operand 238 states and 301 transitions. [2018-11-28 11:28:27,289 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 74 [2018-11-28 11:28:27,289 INFO L394 BasicCegarLoop]: Found error trace [2018-11-28 11:28:27,289 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-28 11:28:27,289 INFO L423 AbstractCegarLoop]: === Iteration 3 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-28 11:28:27,289 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-28 11:28:27,289 INFO L82 PathProgramCache]: Analyzing trace with hash 1691683492, now seen corresponding path program 1 times [2018-11-28 11:28:27,290 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-28 11:28:27,290 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-28 11:28:27,290 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 11:28:27,290 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-28 11:28:27,291 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 11:28:27,306 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-28 11:28:27,345 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-28 11:28:27,346 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-28 11:28:27,346 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2018-11-28 11:28:27,346 INFO L459 AbstractCegarLoop]: Interpolant automaton has 4 states [2018-11-28 11:28:27,347 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2018-11-28 11:28:27,347 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2018-11-28 11:28:27,347 INFO L87 Difference]: Start difference. First operand 238 states and 301 transitions. Second operand 4 states. [2018-11-28 11:28:27,518 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-28 11:28:27,518 INFO L93 Difference]: Finished difference Result 573 states and 746 transitions. [2018-11-28 11:28:27,519 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2018-11-28 11:28:27,519 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 73 [2018-11-28 11:28:27,519 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-28 11:28:27,522 INFO L225 Difference]: With dead ends: 573 [2018-11-28 11:28:27,522 INFO L226 Difference]: Without dead ends: 355 [2018-11-28 11:28:27,523 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 5 GetRequests, 2 SyntacticMatches, 1 SemanticMatches, 2 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2018-11-28 11:28:27,524 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 355 states. [2018-11-28 11:28:27,551 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 355 to 339. [2018-11-28 11:28:27,551 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 339 states. [2018-11-28 11:28:27,553 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 339 states to 339 states and 428 transitions. [2018-11-28 11:28:27,553 INFO L78 Accepts]: Start accepts. Automaton has 339 states and 428 transitions. Word has length 73 [2018-11-28 11:28:27,553 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-28 11:28:27,553 INFO L480 AbstractCegarLoop]: Abstraction has 339 states and 428 transitions. [2018-11-28 11:28:27,553 INFO L481 AbstractCegarLoop]: Interpolant automaton has 4 states. [2018-11-28 11:28:27,553 INFO L276 IsEmpty]: Start isEmpty. Operand 339 states and 428 transitions. [2018-11-28 11:28:27,555 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 74 [2018-11-28 11:28:27,555 INFO L394 BasicCegarLoop]: Found error trace [2018-11-28 11:28:27,555 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-28 11:28:27,555 INFO L423 AbstractCegarLoop]: === Iteration 4 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-28 11:28:27,555 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-28 11:28:27,555 INFO L82 PathProgramCache]: Analyzing trace with hash -73133117, now seen corresponding path program 1 times [2018-11-28 11:28:27,556 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-28 11:28:27,556 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-28 11:28:27,556 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 11:28:27,557 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-28 11:28:27,557 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 11:28:27,575 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-28 11:28:27,637 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-28 11:28:27,637 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-28 11:28:27,637 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2018-11-28 11:28:27,637 INFO L459 AbstractCegarLoop]: Interpolant automaton has 6 states [2018-11-28 11:28:27,637 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2018-11-28 11:28:27,638 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=21, Unknown=0, NotChecked=0, Total=30 [2018-11-28 11:28:27,638 INFO L87 Difference]: Start difference. First operand 339 states and 428 transitions. Second operand 6 states. [2018-11-28 11:28:27,692 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-28 11:28:27,692 INFO L93 Difference]: Finished difference Result 688 states and 882 transitions. [2018-11-28 11:28:27,693 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2018-11-28 11:28:27,693 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 73 [2018-11-28 11:28:27,693 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-28 11:28:27,695 INFO L225 Difference]: With dead ends: 688 [2018-11-28 11:28:27,695 INFO L226 Difference]: Without dead ends: 369 [2018-11-28 11:28:27,697 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 7 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=13, Invalid=29, Unknown=0, NotChecked=0, Total=42 [2018-11-28 11:28:27,698 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 369 states. [2018-11-28 11:28:27,721 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 369 to 354. [2018-11-28 11:28:27,721 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 354 states. [2018-11-28 11:28:27,723 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 354 states to 354 states and 443 transitions. [2018-11-28 11:28:27,723 INFO L78 Accepts]: Start accepts. Automaton has 354 states and 443 transitions. Word has length 73 [2018-11-28 11:28:27,723 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-28 11:28:27,723 INFO L480 AbstractCegarLoop]: Abstraction has 354 states and 443 transitions. [2018-11-28 11:28:27,723 INFO L481 AbstractCegarLoop]: Interpolant automaton has 6 states. [2018-11-28 11:28:27,723 INFO L276 IsEmpty]: Start isEmpty. Operand 354 states and 443 transitions. [2018-11-28 11:28:27,724 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 74 [2018-11-28 11:28:27,725 INFO L394 BasicCegarLoop]: Found error trace [2018-11-28 11:28:27,725 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-28 11:28:27,725 INFO L423 AbstractCegarLoop]: === Iteration 5 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-28 11:28:27,725 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-28 11:28:27,725 INFO L82 PathProgramCache]: Analyzing trace with hash -1444940415, now seen corresponding path program 1 times [2018-11-28 11:28:27,725 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-28 11:28:27,726 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-28 11:28:27,726 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 11:28:27,726 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-28 11:28:27,727 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 11:28:27,740 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-28 11:28:27,808 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-28 11:28:27,808 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-28 11:28:27,808 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2018-11-28 11:28:27,809 INFO L459 AbstractCegarLoop]: Interpolant automaton has 6 states [2018-11-28 11:28:27,809 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2018-11-28 11:28:27,809 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=21, Unknown=0, NotChecked=0, Total=30 [2018-11-28 11:28:27,809 INFO L87 Difference]: Start difference. First operand 354 states and 443 transitions. Second operand 6 states. [2018-11-28 11:28:27,871 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-28 11:28:27,871 INFO L93 Difference]: Finished difference Result 702 states and 887 transitions. [2018-11-28 11:28:27,872 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2018-11-28 11:28:27,872 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 73 [2018-11-28 11:28:27,872 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-28 11:28:27,874 INFO L225 Difference]: With dead ends: 702 [2018-11-28 11:28:27,874 INFO L226 Difference]: Without dead ends: 368 [2018-11-28 11:28:27,875 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 7 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=13, Invalid=29, Unknown=0, NotChecked=0, Total=42 [2018-11-28 11:28:27,876 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 368 states. [2018-11-28 11:28:27,894 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 368 to 364. [2018-11-28 11:28:27,894 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 364 states. [2018-11-28 11:28:27,896 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 364 states to 364 states and 452 transitions. [2018-11-28 11:28:27,897 INFO L78 Accepts]: Start accepts. Automaton has 364 states and 452 transitions. Word has length 73 [2018-11-28 11:28:27,897 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-28 11:28:27,897 INFO L480 AbstractCegarLoop]: Abstraction has 364 states and 452 transitions. [2018-11-28 11:28:27,897 INFO L481 AbstractCegarLoop]: Interpolant automaton has 6 states. [2018-11-28 11:28:27,897 INFO L276 IsEmpty]: Start isEmpty. Operand 364 states and 452 transitions. [2018-11-28 11:28:27,898 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 74 [2018-11-28 11:28:27,898 INFO L394 BasicCegarLoop]: Found error trace [2018-11-28 11:28:27,898 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-28 11:28:27,898 INFO L423 AbstractCegarLoop]: === Iteration 6 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-28 11:28:27,899 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-28 11:28:27,899 INFO L82 PathProgramCache]: Analyzing trace with hash -1422308161, now seen corresponding path program 1 times [2018-11-28 11:28:27,899 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-28 11:28:27,899 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-28 11:28:27,900 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 11:28:27,900 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-28 11:28:27,900 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 11:28:27,913 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-28 11:28:27,970 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-28 11:28:27,970 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-28 11:28:27,970 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2018-11-28 11:28:27,970 INFO L459 AbstractCegarLoop]: Interpolant automaton has 6 states [2018-11-28 11:28:27,971 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2018-11-28 11:28:27,971 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=21, Unknown=0, NotChecked=0, Total=30 [2018-11-28 11:28:27,971 INFO L87 Difference]: Start difference. First operand 364 states and 452 transitions. Second operand 6 states. [2018-11-28 11:28:28,078 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-28 11:28:28,079 INFO L93 Difference]: Finished difference Result 926 states and 1173 transitions. [2018-11-28 11:28:28,081 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2018-11-28 11:28:28,081 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 73 [2018-11-28 11:28:28,081 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-28 11:28:28,084 INFO L225 Difference]: With dead ends: 926 [2018-11-28 11:28:28,084 INFO L226 Difference]: Without dead ends: 583 [2018-11-28 11:28:28,085 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 14 GetRequests, 7 SyntacticMatches, 0 SemanticMatches, 7 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=23, Invalid=49, Unknown=0, NotChecked=0, Total=72 [2018-11-28 11:28:28,086 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 583 states. [2018-11-28 11:28:28,113 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 583 to 570. [2018-11-28 11:28:28,113 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 570 states. [2018-11-28 11:28:28,116 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 570 states to 570 states and 714 transitions. [2018-11-28 11:28:28,117 INFO L78 Accepts]: Start accepts. Automaton has 570 states and 714 transitions. Word has length 73 [2018-11-28 11:28:28,117 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-28 11:28:28,117 INFO L480 AbstractCegarLoop]: Abstraction has 570 states and 714 transitions. [2018-11-28 11:28:28,117 INFO L481 AbstractCegarLoop]: Interpolant automaton has 6 states. [2018-11-28 11:28:28,118 INFO L276 IsEmpty]: Start isEmpty. Operand 570 states and 714 transitions. [2018-11-28 11:28:28,119 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 87 [2018-11-28 11:28:28,119 INFO L394 BasicCegarLoop]: Found error trace [2018-11-28 11:28:28,120 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-28 11:28:28,120 INFO L423 AbstractCegarLoop]: === Iteration 7 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-28 11:28:28,120 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-28 11:28:28,121 INFO L82 PathProgramCache]: Analyzing trace with hash -1577822909, now seen corresponding path program 1 times [2018-11-28 11:28:28,121 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-28 11:28:28,121 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-28 11:28:28,122 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 11:28:28,122 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-28 11:28:28,122 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 11:28:28,133 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-28 11:28:28,199 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-28 11:28:28,199 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-28 11:28:28,199 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2018-11-28 11:28:28,200 INFO L459 AbstractCegarLoop]: Interpolant automaton has 6 states [2018-11-28 11:28:28,200 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2018-11-28 11:28:28,200 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=10, Invalid=20, Unknown=0, NotChecked=0, Total=30 [2018-11-28 11:28:28,200 INFO L87 Difference]: Start difference. First operand 570 states and 714 transitions. Second operand 6 states. [2018-11-28 11:28:28,795 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-28 11:28:28,795 INFO L93 Difference]: Finished difference Result 1162 states and 1558 transitions. [2018-11-28 11:28:28,796 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 8 states. [2018-11-28 11:28:28,796 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 86 [2018-11-28 11:28:28,796 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-28 11:28:28,800 INFO L225 Difference]: With dead ends: 1162 [2018-11-28 11:28:28,800 INFO L226 Difference]: Without dead ends: 824 [2018-11-28 11:28:28,804 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 15 GetRequests, 8 SyntacticMatches, 0 SemanticMatches, 7 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=25, Invalid=47, Unknown=0, NotChecked=0, Total=72 [2018-11-28 11:28:28,805 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 824 states. [2018-11-28 11:28:28,848 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 824 to 771. [2018-11-28 11:28:28,849 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 771 states. [2018-11-28 11:28:28,852 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 771 states to 771 states and 1019 transitions. [2018-11-28 11:28:28,853 INFO L78 Accepts]: Start accepts. Automaton has 771 states and 1019 transitions. Word has length 86 [2018-11-28 11:28:28,853 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-28 11:28:28,853 INFO L480 AbstractCegarLoop]: Abstraction has 771 states and 1019 transitions. [2018-11-28 11:28:28,853 INFO L481 AbstractCegarLoop]: Interpolant automaton has 6 states. [2018-11-28 11:28:28,853 INFO L276 IsEmpty]: Start isEmpty. Operand 771 states and 1019 transitions. [2018-11-28 11:28:28,854 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 91 [2018-11-28 11:28:28,854 INFO L394 BasicCegarLoop]: Found error trace [2018-11-28 11:28:28,854 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-28 11:28:28,855 INFO L423 AbstractCegarLoop]: === Iteration 8 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-28 11:28:28,855 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-28 11:28:28,855 INFO L82 PathProgramCache]: Analyzing trace with hash -627422246, now seen corresponding path program 1 times [2018-11-28 11:28:28,855 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-28 11:28:28,855 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-28 11:28:28,856 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 11:28:28,856 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-28 11:28:28,856 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 11:28:28,866 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-28 11:28:28,956 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-28 11:28:28,956 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-28 11:28:28,956 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [8] imperfect sequences [] total 8 [2018-11-28 11:28:28,957 INFO L459 AbstractCegarLoop]: Interpolant automaton has 8 states [2018-11-28 11:28:28,957 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 8 interpolants. [2018-11-28 11:28:28,957 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=13, Invalid=43, Unknown=0, NotChecked=0, Total=56 [2018-11-28 11:28:28,957 INFO L87 Difference]: Start difference. First operand 771 states and 1019 transitions. Second operand 8 states. [2018-11-28 11:28:29,779 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-28 11:28:29,779 INFO L93 Difference]: Finished difference Result 1991 states and 2867 transitions. [2018-11-28 11:28:29,780 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 12 states. [2018-11-28 11:28:29,780 INFO L78 Accepts]: Start accepts. Automaton has 8 states. Word has length 90 [2018-11-28 11:28:29,780 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-28 11:28:29,785 INFO L225 Difference]: With dead ends: 1991 [2018-11-28 11:28:29,785 INFO L226 Difference]: Without dead ends: 1466 [2018-11-28 11:28:29,787 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 21 GetRequests, 8 SyntacticMatches, 1 SemanticMatches, 12 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 12 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=44, Invalid=138, Unknown=0, NotChecked=0, Total=182 [2018-11-28 11:28:29,789 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1466 states. [2018-11-28 11:28:29,832 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1466 to 1355. [2018-11-28 11:28:29,833 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1355 states. [2018-11-28 11:28:29,836 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1355 states to 1355 states and 1882 transitions. [2018-11-28 11:28:29,837 INFO L78 Accepts]: Start accepts. Automaton has 1355 states and 1882 transitions. Word has length 90 [2018-11-28 11:28:29,837 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-28 11:28:29,837 INFO L480 AbstractCegarLoop]: Abstraction has 1355 states and 1882 transitions. [2018-11-28 11:28:29,837 INFO L481 AbstractCegarLoop]: Interpolant automaton has 8 states. [2018-11-28 11:28:29,837 INFO L276 IsEmpty]: Start isEmpty. Operand 1355 states and 1882 transitions. [2018-11-28 11:28:29,838 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 93 [2018-11-28 11:28:29,838 INFO L394 BasicCegarLoop]: Found error trace [2018-11-28 11:28:29,838 INFO L402 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-28 11:28:29,839 INFO L423 AbstractCegarLoop]: === Iteration 9 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-28 11:28:29,839 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-28 11:28:29,839 INFO L82 PathProgramCache]: Analyzing trace with hash 1334723078, now seen corresponding path program 1 times [2018-11-28 11:28:29,839 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-28 11:28:29,839 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-28 11:28:29,839 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 11:28:29,839 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-28 11:28:29,840 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 11:28:29,847 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-28 11:28:29,868 INFO L134 CoverageAnalysis]: Checked inductivity of 15 backedges. 7 proven. 3 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2018-11-28 11:28:29,868 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-28 11:28:29,868 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_0205b283-43b4-4d39-9152-1c66ac810fde/bin-2019/uautomizer/z3 Starting monitored process 2 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 2 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-28 11:28:29,883 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-28 11:28:29,925 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-28 11:28:29,934 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-28 11:28:29,961 INFO L134 CoverageAnalysis]: Checked inductivity of 15 backedges. 10 proven. 0 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2018-11-28 11:28:29,978 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 1 imperfect interpolant sequences. [2018-11-28 11:28:29,978 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [3] total 3 [2018-11-28 11:28:29,979 INFO L459 AbstractCegarLoop]: Interpolant automaton has 3 states [2018-11-28 11:28:29,979 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-28 11:28:29,979 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-28 11:28:29,979 INFO L87 Difference]: Start difference. First operand 1355 states and 1882 transitions. Second operand 3 states. [2018-11-28 11:28:30,095 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-28 11:28:30,095 INFO L93 Difference]: Finished difference Result 3840 states and 5897 transitions. [2018-11-28 11:28:30,096 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-28 11:28:30,096 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 92 [2018-11-28 11:28:30,096 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-28 11:28:30,105 INFO L225 Difference]: With dead ends: 3840 [2018-11-28 11:28:30,105 INFO L226 Difference]: Without dead ends: 2506 [2018-11-28 11:28:30,110 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 94 GetRequests, 92 SyntacticMatches, 1 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-28 11:28:30,112 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2506 states. [2018-11-28 11:28:30,199 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2506 to 2502. [2018-11-28 11:28:30,199 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2502 states. [2018-11-28 11:28:30,208 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2502 states to 2502 states and 3704 transitions. [2018-11-28 11:28:30,209 INFO L78 Accepts]: Start accepts. Automaton has 2502 states and 3704 transitions. Word has length 92 [2018-11-28 11:28:30,209 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-28 11:28:30,209 INFO L480 AbstractCegarLoop]: Abstraction has 2502 states and 3704 transitions. [2018-11-28 11:28:30,209 INFO L481 AbstractCegarLoop]: Interpolant automaton has 3 states. [2018-11-28 11:28:30,209 INFO L276 IsEmpty]: Start isEmpty. Operand 2502 states and 3704 transitions. [2018-11-28 11:28:30,211 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 97 [2018-11-28 11:28:30,211 INFO L394 BasicCegarLoop]: Found error trace [2018-11-28 11:28:30,211 INFO L402 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-28 11:28:30,212 INFO L423 AbstractCegarLoop]: === Iteration 10 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-28 11:28:30,212 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-28 11:28:30,212 INFO L82 PathProgramCache]: Analyzing trace with hash -1839079452, now seen corresponding path program 1 times [2018-11-28 11:28:30,212 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-28 11:28:30,212 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-28 11:28:30,213 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 11:28:30,213 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-28 11:28:30,213 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 11:28:30,221 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-28 11:28:30,296 INFO L134 CoverageAnalysis]: Checked inductivity of 17 backedges. 13 proven. 2 refuted. 0 times theorem prover too weak. 2 trivial. 0 not checked. [2018-11-28 11:28:30,296 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-28 11:28:30,296 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_0205b283-43b4-4d39-9152-1c66ac810fde/bin-2019/uautomizer/z3 Starting monitored process 3 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 3 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-28 11:28:30,307 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-28 11:28:30,349 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-28 11:28:30,353 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-28 11:28:30,386 INFO L134 CoverageAnalysis]: Checked inductivity of 17 backedges. 17 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-28 11:28:30,401 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 1 imperfect interpolant sequences. [2018-11-28 11:28:30,401 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [8] total 9 [2018-11-28 11:28:30,401 INFO L459 AbstractCegarLoop]: Interpolant automaton has 9 states [2018-11-28 11:28:30,402 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 9 interpolants. [2018-11-28 11:28:30,402 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=19, Invalid=53, Unknown=0, NotChecked=0, Total=72 [2018-11-28 11:28:30,402 INFO L87 Difference]: Start difference. First operand 2502 states and 3704 transitions. Second operand 9 states. [2018-11-28 11:28:31,411 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-28 11:28:31,411 INFO L93 Difference]: Finished difference Result 6390 states and 10750 transitions. [2018-11-28 11:28:31,412 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 13 states. [2018-11-28 11:28:31,412 INFO L78 Accepts]: Start accepts. Automaton has 9 states. Word has length 96 [2018-11-28 11:28:31,412 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-28 11:28:31,425 INFO L225 Difference]: With dead ends: 6390 [2018-11-28 11:28:31,425 INFO L226 Difference]: Without dead ends: 3909 [2018-11-28 11:28:31,441 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 125 GetRequests, 105 SyntacticMatches, 3 SemanticMatches, 17 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 50 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=90, Invalid=252, Unknown=0, NotChecked=0, Total=342 [2018-11-28 11:28:31,444 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3909 states. [2018-11-28 11:28:31,580 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3909 to 3843. [2018-11-28 11:28:31,580 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3843 states. [2018-11-28 11:28:31,593 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3843 states to 3843 states and 5464 transitions. [2018-11-28 11:28:31,594 INFO L78 Accepts]: Start accepts. Automaton has 3843 states and 5464 transitions. Word has length 96 [2018-11-28 11:28:31,594 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-28 11:28:31,594 INFO L480 AbstractCegarLoop]: Abstraction has 3843 states and 5464 transitions. [2018-11-28 11:28:31,595 INFO L481 AbstractCegarLoop]: Interpolant automaton has 9 states. [2018-11-28 11:28:31,595 INFO L276 IsEmpty]: Start isEmpty. Operand 3843 states and 5464 transitions. [2018-11-28 11:28:31,596 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 95 [2018-11-28 11:28:31,596 INFO L394 BasicCegarLoop]: Found error trace [2018-11-28 11:28:31,596 INFO L402 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-28 11:28:31,596 INFO L423 AbstractCegarLoop]: === Iteration 11 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-28 11:28:31,596 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-28 11:28:31,597 INFO L82 PathProgramCache]: Analyzing trace with hash -758498226, now seen corresponding path program 1 times [2018-11-28 11:28:31,597 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-28 11:28:31,597 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-28 11:28:31,597 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 11:28:31,597 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-28 11:28:31,597 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 11:28:31,605 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-28 11:28:31,658 INFO L134 CoverageAnalysis]: Checked inductivity of 16 backedges. 4 proven. 7 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2018-11-28 11:28:31,659 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-28 11:28:31,659 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_0205b283-43b4-4d39-9152-1c66ac810fde/bin-2019/uautomizer/z3 Starting monitored process 4 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 4 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-28 11:28:31,666 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-28 11:28:31,706 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-28 11:28:31,710 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-28 11:28:31,729 INFO L134 CoverageAnalysis]: Checked inductivity of 16 backedges. 16 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-28 11:28:31,744 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 1 imperfect interpolant sequences. [2018-11-28 11:28:31,744 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [7] total 8 [2018-11-28 11:28:31,744 INFO L459 AbstractCegarLoop]: Interpolant automaton has 8 states [2018-11-28 11:28:31,745 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 8 interpolants. [2018-11-28 11:28:31,745 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=17, Invalid=39, Unknown=0, NotChecked=0, Total=56 [2018-11-28 11:28:31,745 INFO L87 Difference]: Start difference. First operand 3843 states and 5464 transitions. Second operand 8 states. [2018-11-28 11:28:33,634 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-28 11:28:33,634 INFO L93 Difference]: Finished difference Result 17414 states and 28965 transitions. [2018-11-28 11:28:33,634 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 23 states. [2018-11-28 11:28:33,635 INFO L78 Accepts]: Start accepts. Automaton has 8 states. Word has length 94 [2018-11-28 11:28:33,635 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-28 11:28:33,688 INFO L225 Difference]: With dead ends: 17414 [2018-11-28 11:28:33,688 INFO L226 Difference]: Without dead ends: 12986 [2018-11-28 11:28:33,723 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 131 GetRequests, 110 SyntacticMatches, 0 SemanticMatches, 21 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 119 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=146, Invalid=360, Unknown=0, NotChecked=0, Total=506 [2018-11-28 11:28:33,733 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 12986 states. [2018-11-28 11:28:34,375 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 12986 to 10564. [2018-11-28 11:28:34,376 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 10564 states. [2018-11-28 11:28:34,414 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 10564 states to 10564 states and 14050 transitions. [2018-11-28 11:28:34,418 INFO L78 Accepts]: Start accepts. Automaton has 10564 states and 14050 transitions. Word has length 94 [2018-11-28 11:28:34,418 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-28 11:28:34,418 INFO L480 AbstractCegarLoop]: Abstraction has 10564 states and 14050 transitions. [2018-11-28 11:28:34,418 INFO L481 AbstractCegarLoop]: Interpolant automaton has 8 states. [2018-11-28 11:28:34,418 INFO L276 IsEmpty]: Start isEmpty. Operand 10564 states and 14050 transitions. [2018-11-28 11:28:34,429 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 166 [2018-11-28 11:28:34,429 INFO L394 BasicCegarLoop]: Found error trace [2018-11-28 11:28:34,429 INFO L402 BasicCegarLoop]: trace histogram [5, 5, 5, 5, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-28 11:28:34,430 INFO L423 AbstractCegarLoop]: === Iteration 12 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-28 11:28:34,430 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-28 11:28:34,430 INFO L82 PathProgramCache]: Analyzing trace with hash -100635213, now seen corresponding path program 1 times [2018-11-28 11:28:34,430 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-28 11:28:34,430 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-28 11:28:34,431 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 11:28:34,431 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-28 11:28:34,431 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 11:28:34,439 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-28 11:28:34,531 INFO L134 CoverageAnalysis]: Checked inductivity of 99 backedges. 19 proven. 20 refuted. 0 times theorem prover too weak. 60 trivial. 0 not checked. [2018-11-28 11:28:34,531 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-28 11:28:34,531 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_0205b283-43b4-4d39-9152-1c66ac810fde/bin-2019/uautomizer/z3 Starting monitored process 5 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 5 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-28 11:28:34,540 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-28 11:28:34,605 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-28 11:28:34,609 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-28 11:28:34,647 INFO L134 CoverageAnalysis]: Checked inductivity of 99 backedges. 58 proven. 0 refuted. 0 times theorem prover too weak. 41 trivial. 0 not checked. [2018-11-28 11:28:34,673 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 1 imperfect interpolant sequences. [2018-11-28 11:28:34,674 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [8] total 9 [2018-11-28 11:28:34,674 INFO L459 AbstractCegarLoop]: Interpolant automaton has 9 states [2018-11-28 11:28:34,674 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 9 interpolants. [2018-11-28 11:28:34,674 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=17, Invalid=55, Unknown=0, NotChecked=0, Total=72 [2018-11-28 11:28:34,674 INFO L87 Difference]: Start difference. First operand 10564 states and 14050 transitions. Second operand 9 states. [2018-11-28 11:28:35,125 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-28 11:28:35,125 INFO L93 Difference]: Finished difference Result 17912 states and 23709 transitions. [2018-11-28 11:28:35,126 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2018-11-28 11:28:35,126 INFO L78 Accepts]: Start accepts. Automaton has 9 states. Word has length 165 [2018-11-28 11:28:35,126 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-28 11:28:35,158 INFO L225 Difference]: With dead ends: 17912 [2018-11-28 11:28:35,159 INFO L226 Difference]: Without dead ends: 6739 [2018-11-28 11:28:35,176 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 184 GetRequests, 168 SyntacticMatches, 3 SemanticMatches, 13 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 16 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=52, Invalid=158, Unknown=0, NotChecked=0, Total=210 [2018-11-28 11:28:35,183 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 6739 states. [2018-11-28 11:28:35,533 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 6739 to 6213. [2018-11-28 11:28:35,534 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 6213 states. [2018-11-28 11:28:35,550 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 6213 states to 6213 states and 7934 transitions. [2018-11-28 11:28:35,553 INFO L78 Accepts]: Start accepts. Automaton has 6213 states and 7934 transitions. Word has length 165 [2018-11-28 11:28:35,554 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-28 11:28:35,554 INFO L480 AbstractCegarLoop]: Abstraction has 6213 states and 7934 transitions. [2018-11-28 11:28:35,554 INFO L481 AbstractCegarLoop]: Interpolant automaton has 9 states. [2018-11-28 11:28:35,554 INFO L276 IsEmpty]: Start isEmpty. Operand 6213 states and 7934 transitions. [2018-11-28 11:28:35,561 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 171 [2018-11-28 11:28:35,561 INFO L394 BasicCegarLoop]: Found error trace [2018-11-28 11:28:35,561 INFO L402 BasicCegarLoop]: trace histogram [5, 5, 5, 4, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-28 11:28:35,561 INFO L423 AbstractCegarLoop]: === Iteration 13 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-28 11:28:35,561 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-28 11:28:35,562 INFO L82 PathProgramCache]: Analyzing trace with hash 1811941414, now seen corresponding path program 1 times [2018-11-28 11:28:35,562 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-28 11:28:35,562 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-28 11:28:35,562 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 11:28:35,562 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-28 11:28:35,562 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 11:28:35,571 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-28 11:28:35,630 INFO L134 CoverageAnalysis]: Checked inductivity of 101 backedges. 20 proven. 14 refuted. 0 times theorem prover too weak. 67 trivial. 0 not checked. [2018-11-28 11:28:35,630 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-28 11:28:35,631 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_0205b283-43b4-4d39-9152-1c66ac810fde/bin-2019/uautomizer/z3 Starting monitored process 6 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 6 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-28 11:28:35,642 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-28 11:28:35,714 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-28 11:28:35,719 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-28 11:28:35,772 INFO L134 CoverageAnalysis]: Checked inductivity of 101 backedges. 69 proven. 0 refuted. 0 times theorem prover too weak. 32 trivial. 0 not checked. [2018-11-28 11:28:35,797 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 1 imperfect interpolant sequences. [2018-11-28 11:28:35,798 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [5] total 6 [2018-11-28 11:28:35,798 INFO L459 AbstractCegarLoop]: Interpolant automaton has 6 states [2018-11-28 11:28:35,798 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2018-11-28 11:28:35,798 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=21, Unknown=0, NotChecked=0, Total=30 [2018-11-28 11:28:35,799 INFO L87 Difference]: Start difference. First operand 6213 states and 7934 transitions. Second operand 6 states. [2018-11-28 11:28:36,906 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-28 11:28:36,906 INFO L93 Difference]: Finished difference Result 18019 states and 23767 transitions. [2018-11-28 11:28:36,907 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 11 states. [2018-11-28 11:28:36,907 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 170 [2018-11-28 11:28:36,907 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-28 11:28:36,935 INFO L225 Difference]: With dead ends: 18019 [2018-11-28 11:28:36,935 INFO L226 Difference]: Without dead ends: 8848 [2018-11-28 11:28:36,947 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 188 GetRequests, 177 SyntacticMatches, 1 SemanticMatches, 10 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 13 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=40, Invalid=92, Unknown=0, NotChecked=0, Total=132 [2018-11-28 11:28:36,953 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 8848 states. [2018-11-28 11:28:37,237 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 8848 to 7075. [2018-11-28 11:28:37,237 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 7075 states. [2018-11-28 11:28:37,254 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 7075 states to 7075 states and 8944 transitions. [2018-11-28 11:28:37,257 INFO L78 Accepts]: Start accepts. Automaton has 7075 states and 8944 transitions. Word has length 170 [2018-11-28 11:28:37,257 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-28 11:28:37,257 INFO L480 AbstractCegarLoop]: Abstraction has 7075 states and 8944 transitions. [2018-11-28 11:28:37,257 INFO L481 AbstractCegarLoop]: Interpolant automaton has 6 states. [2018-11-28 11:28:37,257 INFO L276 IsEmpty]: Start isEmpty. Operand 7075 states and 8944 transitions. [2018-11-28 11:28:37,261 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 204 [2018-11-28 11:28:37,261 INFO L394 BasicCegarLoop]: Found error trace [2018-11-28 11:28:37,261 INFO L402 BasicCegarLoop]: trace histogram [5, 5, 5, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-28 11:28:37,261 INFO L423 AbstractCegarLoop]: === Iteration 14 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-28 11:28:37,262 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-28 11:28:37,262 INFO L82 PathProgramCache]: Analyzing trace with hash -1118584665, now seen corresponding path program 1 times [2018-11-28 11:28:37,262 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-28 11:28:37,262 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-28 11:28:37,262 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 11:28:37,263 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-28 11:28:37,263 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 11:28:37,273 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-28 11:28:37,329 INFO L134 CoverageAnalysis]: Checked inductivity of 146 backedges. 20 proven. 0 refuted. 0 times theorem prover too weak. 126 trivial. 0 not checked. [2018-11-28 11:28:37,330 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-28 11:28:37,330 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-11-28 11:28:37,330 INFO L459 AbstractCegarLoop]: Interpolant automaton has 5 states [2018-11-28 11:28:37,330 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-11-28 11:28:37,330 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-11-28 11:28:37,331 INFO L87 Difference]: Start difference. First operand 7075 states and 8944 transitions. Second operand 5 states. [2018-11-28 11:28:38,386 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-28 11:28:38,386 INFO L93 Difference]: Finished difference Result 19015 states and 26279 transitions. [2018-11-28 11:28:38,386 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 8 states. [2018-11-28 11:28:38,387 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 203 [2018-11-28 11:28:38,387 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-28 11:28:38,426 INFO L225 Difference]: With dead ends: 19015 [2018-11-28 11:28:38,427 INFO L226 Difference]: Without dead ends: 12533 [2018-11-28 11:28:38,438 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 11 GetRequests, 5 SyntacticMatches, 0 SemanticMatches, 6 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 3 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=19, Invalid=37, Unknown=0, NotChecked=0, Total=56 [2018-11-28 11:28:38,446 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 12533 states. [2018-11-28 11:28:39,051 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 12533 to 10400. [2018-11-28 11:28:39,051 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 10400 states. [2018-11-28 11:28:39,069 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 10400 states to 10400 states and 13123 transitions. [2018-11-28 11:28:39,072 INFO L78 Accepts]: Start accepts. Automaton has 10400 states and 13123 transitions. Word has length 203 [2018-11-28 11:28:39,072 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-28 11:28:39,072 INFO L480 AbstractCegarLoop]: Abstraction has 10400 states and 13123 transitions. [2018-11-28 11:28:39,072 INFO L481 AbstractCegarLoop]: Interpolant automaton has 5 states. [2018-11-28 11:28:39,072 INFO L276 IsEmpty]: Start isEmpty. Operand 10400 states and 13123 transitions. [2018-11-28 11:28:39,076 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 204 [2018-11-28 11:28:39,076 INFO L394 BasicCegarLoop]: Found error trace [2018-11-28 11:28:39,076 INFO L402 BasicCegarLoop]: trace histogram [5, 5, 5, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-28 11:28:39,077 INFO L423 AbstractCegarLoop]: === Iteration 15 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-28 11:28:39,077 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-28 11:28:39,077 INFO L82 PathProgramCache]: Analyzing trace with hash -1366731159, now seen corresponding path program 1 times [2018-11-28 11:28:39,077 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-28 11:28:39,077 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-28 11:28:39,078 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 11:28:39,078 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-28 11:28:39,078 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 11:28:39,090 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-28 11:28:39,166 INFO L134 CoverageAnalysis]: Checked inductivity of 146 backedges. 4 proven. 41 refuted. 0 times theorem prover too weak. 101 trivial. 0 not checked. [2018-11-28 11:28:39,166 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-28 11:28:39,166 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_0205b283-43b4-4d39-9152-1c66ac810fde/bin-2019/uautomizer/z3 Starting monitored process 7 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 7 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-28 11:28:39,173 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-28 11:28:39,227 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-28 11:28:39,231 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-28 11:28:39,262 INFO L134 CoverageAnalysis]: Checked inductivity of 146 backedges. 89 proven. 0 refuted. 0 times theorem prover too weak. 57 trivial. 0 not checked. [2018-11-28 11:28:39,277 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 1 imperfect interpolant sequences. [2018-11-28 11:28:39,277 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [7] total 8 [2018-11-28 11:28:39,278 INFO L459 AbstractCegarLoop]: Interpolant automaton has 8 states [2018-11-28 11:28:39,278 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 8 interpolants. [2018-11-28 11:28:39,278 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=17, Invalid=39, Unknown=0, NotChecked=0, Total=56 [2018-11-28 11:28:39,278 INFO L87 Difference]: Start difference. First operand 10400 states and 13123 transitions. Second operand 8 states. [2018-11-28 11:28:40,428 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-28 11:28:40,428 INFO L93 Difference]: Finished difference Result 19496 states and 25422 transitions. [2018-11-28 11:28:40,429 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 14 states. [2018-11-28 11:28:40,429 INFO L78 Accepts]: Start accepts. Automaton has 8 states. Word has length 203 [2018-11-28 11:28:40,429 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-28 11:28:40,464 INFO L225 Difference]: With dead ends: 19496 [2018-11-28 11:28:40,464 INFO L226 Difference]: Without dead ends: 10331 [2018-11-28 11:28:40,479 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 228 GetRequests, 214 SyntacticMatches, 0 SemanticMatches, 14 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 31 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=67, Invalid=173, Unknown=0, NotChecked=0, Total=240 [2018-11-28 11:28:40,487 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 10331 states. [2018-11-28 11:28:41,070 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 10331 to 9253. [2018-11-28 11:28:41,071 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 9253 states. [2018-11-28 11:28:41,093 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 9253 states to 9253 states and 11289 transitions. [2018-11-28 11:28:41,096 INFO L78 Accepts]: Start accepts. Automaton has 9253 states and 11289 transitions. Word has length 203 [2018-11-28 11:28:41,097 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-28 11:28:41,097 INFO L480 AbstractCegarLoop]: Abstraction has 9253 states and 11289 transitions. [2018-11-28 11:28:41,097 INFO L481 AbstractCegarLoop]: Interpolant automaton has 8 states. [2018-11-28 11:28:41,097 INFO L276 IsEmpty]: Start isEmpty. Operand 9253 states and 11289 transitions. [2018-11-28 11:28:41,103 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 205 [2018-11-28 11:28:41,103 INFO L394 BasicCegarLoop]: Found error trace [2018-11-28 11:28:41,103 INFO L402 BasicCegarLoop]: trace histogram [5, 5, 5, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-28 11:28:41,103 INFO L423 AbstractCegarLoop]: === Iteration 16 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-28 11:28:41,103 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-28 11:28:41,104 INFO L82 PathProgramCache]: Analyzing trace with hash -555580108, now seen corresponding path program 1 times [2018-11-28 11:28:41,104 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-28 11:28:41,104 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-28 11:28:41,104 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 11:28:41,104 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-28 11:28:41,105 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 11:28:41,121 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-28 11:28:41,293 INFO L134 CoverageAnalysis]: Checked inductivity of 146 backedges. 6 proven. 18 refuted. 0 times theorem prover too weak. 122 trivial. 0 not checked. [2018-11-28 11:28:41,293 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-28 11:28:41,293 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_0205b283-43b4-4d39-9152-1c66ac810fde/bin-2019/uautomizer/z3 Starting monitored process 8 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 8 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-28 11:28:41,303 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-28 11:28:41,371 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-28 11:28:41,376 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-28 11:28:41,474 INFO L134 CoverageAnalysis]: Checked inductivity of 146 backedges. 109 proven. 0 refuted. 0 times theorem prover too weak. 37 trivial. 0 not checked. [2018-11-28 11:28:41,499 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 1 imperfect interpolant sequences. [2018-11-28 11:28:41,499 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [6] imperfect sequences [8] total 12 [2018-11-28 11:28:41,500 INFO L459 AbstractCegarLoop]: Interpolant automaton has 12 states [2018-11-28 11:28:41,500 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 12 interpolants. [2018-11-28 11:28:41,500 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=24, Invalid=108, Unknown=0, NotChecked=0, Total=132 [2018-11-28 11:28:41,500 INFO L87 Difference]: Start difference. First operand 9253 states and 11289 transitions. Second operand 12 states. [2018-11-28 11:28:43,725 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-28 11:28:43,725 INFO L93 Difference]: Finished difference Result 16386 states and 20206 transitions. [2018-11-28 11:28:43,726 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 36 states. [2018-11-28 11:28:43,726 INFO L78 Accepts]: Start accepts. Automaton has 12 states. Word has length 204 [2018-11-28 11:28:43,726 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-28 11:28:43,750 INFO L225 Difference]: With dead ends: 16386 [2018-11-28 11:28:43,750 INFO L226 Difference]: Without dead ends: 7873 [2018-11-28 11:28:43,763 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 268 GetRequests, 224 SyntacticMatches, 3 SemanticMatches, 41 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 481 ImplicationChecksByTransitivity, 0.5s TimeCoverageRelationStatistics Valid=319, Invalid=1487, Unknown=0, NotChecked=0, Total=1806 [2018-11-28 11:28:43,769 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 7873 states. [2018-11-28 11:28:44,191 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 7873 to 7619. [2018-11-28 11:28:44,192 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 7619 states. [2018-11-28 11:28:44,201 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 7619 states to 7619 states and 9114 transitions. [2018-11-28 11:28:44,204 INFO L78 Accepts]: Start accepts. Automaton has 7619 states and 9114 transitions. Word has length 204 [2018-11-28 11:28:44,204 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-28 11:28:44,204 INFO L480 AbstractCegarLoop]: Abstraction has 7619 states and 9114 transitions. [2018-11-28 11:28:44,204 INFO L481 AbstractCegarLoop]: Interpolant automaton has 12 states. [2018-11-28 11:28:44,204 INFO L276 IsEmpty]: Start isEmpty. Operand 7619 states and 9114 transitions. [2018-11-28 11:28:44,209 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 223 [2018-11-28 11:28:44,209 INFO L394 BasicCegarLoop]: Found error trace [2018-11-28 11:28:44,210 INFO L402 BasicCegarLoop]: trace histogram [5, 5, 5, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-28 11:28:44,210 INFO L423 AbstractCegarLoop]: === Iteration 17 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-28 11:28:44,210 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-28 11:28:44,210 INFO L82 PathProgramCache]: Analyzing trace with hash -371471122, now seen corresponding path program 1 times [2018-11-28 11:28:44,210 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-28 11:28:44,210 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-28 11:28:44,211 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 11:28:44,211 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-28 11:28:44,211 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 11:28:44,224 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-28 11:28:44,282 INFO L134 CoverageAnalysis]: Checked inductivity of 145 backedges. 28 proven. 7 refuted. 0 times theorem prover too weak. 110 trivial. 0 not checked. [2018-11-28 11:28:44,282 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-28 11:28:44,282 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_0205b283-43b4-4d39-9152-1c66ac810fde/bin-2019/uautomizer/z3 Starting monitored process 9 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 9 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-28 11:28:44,297 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-28 11:28:44,378 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-28 11:28:44,382 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-28 11:28:44,414 INFO L134 CoverageAnalysis]: Checked inductivity of 145 backedges. 96 proven. 0 refuted. 0 times theorem prover too weak. 49 trivial. 0 not checked. [2018-11-28 11:28:44,439 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 1 imperfect interpolant sequences. [2018-11-28 11:28:44,439 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [4] total 5 [2018-11-28 11:28:44,440 INFO L459 AbstractCegarLoop]: Interpolant automaton has 5 states [2018-11-28 11:28:44,440 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-11-28 11:28:44,440 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=8, Invalid=12, Unknown=0, NotChecked=0, Total=20 [2018-11-28 11:28:44,440 INFO L87 Difference]: Start difference. First operand 7619 states and 9114 transitions. Second operand 5 states. [2018-11-28 11:28:44,772 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-28 11:28:44,773 INFO L93 Difference]: Finished difference Result 11247 states and 13466 transitions. [2018-11-28 11:28:44,773 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2018-11-28 11:28:44,773 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 222 [2018-11-28 11:28:44,773 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-28 11:28:44,787 INFO L225 Difference]: With dead ends: 11247 [2018-11-28 11:28:44,787 INFO L226 Difference]: Without dead ends: 4999 [2018-11-28 11:28:44,797 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 227 GetRequests, 223 SyntacticMatches, 1 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=8, Invalid=12, Unknown=0, NotChecked=0, Total=20 [2018-11-28 11:28:44,801 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 4999 states. [2018-11-28 11:28:45,206 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 4999 to 4960. [2018-11-28 11:28:45,206 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 4960 states. [2018-11-28 11:28:45,212 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 4960 states to 4960 states and 5843 transitions. [2018-11-28 11:28:45,213 INFO L78 Accepts]: Start accepts. Automaton has 4960 states and 5843 transitions. Word has length 222 [2018-11-28 11:28:45,214 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-28 11:28:45,214 INFO L480 AbstractCegarLoop]: Abstraction has 4960 states and 5843 transitions. [2018-11-28 11:28:45,214 INFO L481 AbstractCegarLoop]: Interpolant automaton has 5 states. [2018-11-28 11:28:45,214 INFO L276 IsEmpty]: Start isEmpty. Operand 4960 states and 5843 transitions. [2018-11-28 11:28:45,221 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 223 [2018-11-28 11:28:45,222 INFO L394 BasicCegarLoop]: Found error trace [2018-11-28 11:28:45,222 INFO L402 BasicCegarLoop]: trace histogram [5, 5, 5, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-28 11:28:45,222 INFO L423 AbstractCegarLoop]: === Iteration 18 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-28 11:28:45,222 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-28 11:28:45,222 INFO L82 PathProgramCache]: Analyzing trace with hash 1743806793, now seen corresponding path program 1 times [2018-11-28 11:28:45,222 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-28 11:28:45,223 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-28 11:28:45,223 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 11:28:45,223 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-28 11:28:45,223 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 11:28:45,239 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-28 11:28:45,373 INFO L134 CoverageAnalysis]: Checked inductivity of 145 backedges. 5 proven. 19 refuted. 0 times theorem prover too weak. 121 trivial. 0 not checked. [2018-11-28 11:28:45,373 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-28 11:28:45,373 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_0205b283-43b4-4d39-9152-1c66ac810fde/bin-2019/uautomizer/z3 Starting monitored process 10 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 10 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-28 11:28:45,378 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-28 11:28:45,428 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-28 11:28:45,432 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-28 11:28:45,496 INFO L134 CoverageAnalysis]: Checked inductivity of 145 backedges. 33 proven. 15 refuted. 0 times theorem prover too weak. 97 trivial. 0 not checked. [2018-11-28 11:28:45,512 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-11-28 11:28:45,512 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [12, 8] total 14 [2018-11-28 11:28:45,512 INFO L459 AbstractCegarLoop]: Interpolant automaton has 14 states [2018-11-28 11:28:45,513 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 14 interpolants. [2018-11-28 11:28:45,513 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=35, Invalid=147, Unknown=0, NotChecked=0, Total=182 [2018-11-28 11:28:45,513 INFO L87 Difference]: Start difference. First operand 4960 states and 5843 transitions. Second operand 14 states. [2018-11-28 11:28:47,156 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-28 11:28:47,156 INFO L93 Difference]: Finished difference Result 11863 states and 14844 transitions. [2018-11-28 11:28:47,156 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 23 states. [2018-11-28 11:28:47,156 INFO L78 Accepts]: Start accepts. Automaton has 14 states. Word has length 222 [2018-11-28 11:28:47,157 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-28 11:28:47,185 INFO L225 Difference]: With dead ends: 11863 [2018-11-28 11:28:47,185 INFO L226 Difference]: Without dead ends: 8320 [2018-11-28 11:28:47,194 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 257 GetRequests, 222 SyntacticMatches, 9 SemanticMatches, 26 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 190 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=158, Invalid=598, Unknown=0, NotChecked=0, Total=756 [2018-11-28 11:28:47,200 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 8320 states. [2018-11-28 11:28:47,713 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 8320 to 7250. [2018-11-28 11:28:47,713 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 7250 states. [2018-11-28 11:28:47,728 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 7250 states to 7250 states and 8808 transitions. [2018-11-28 11:28:47,730 INFO L78 Accepts]: Start accepts. Automaton has 7250 states and 8808 transitions. Word has length 222 [2018-11-28 11:28:47,730 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-28 11:28:47,731 INFO L480 AbstractCegarLoop]: Abstraction has 7250 states and 8808 transitions. [2018-11-28 11:28:47,731 INFO L481 AbstractCegarLoop]: Interpolant automaton has 14 states. [2018-11-28 11:28:47,731 INFO L276 IsEmpty]: Start isEmpty. Operand 7250 states and 8808 transitions. [2018-11-28 11:28:47,736 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 304 [2018-11-28 11:28:47,736 INFO L394 BasicCegarLoop]: Found error trace [2018-11-28 11:28:47,736 INFO L402 BasicCegarLoop]: trace histogram [9, 9, 9, 6, 5, 5, 5, 5, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-28 11:28:47,737 INFO L423 AbstractCegarLoop]: === Iteration 19 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-28 11:28:47,737 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-28 11:28:47,737 INFO L82 PathProgramCache]: Analyzing trace with hash -1143802509, now seen corresponding path program 1 times [2018-11-28 11:28:47,737 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-28 11:28:47,737 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-28 11:28:47,738 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 11:28:47,738 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-28 11:28:47,738 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 11:28:47,747 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-28 11:28:47,895 INFO L134 CoverageAnalysis]: Checked inductivity of 438 backedges. 37 proven. 0 refuted. 0 times theorem prover too weak. 401 trivial. 0 not checked. [2018-11-28 11:28:47,896 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-28 11:28:47,896 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2018-11-28 11:28:47,896 INFO L459 AbstractCegarLoop]: Interpolant automaton has 4 states [2018-11-28 11:28:47,896 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2018-11-28 11:28:47,897 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2018-11-28 11:28:47,897 INFO L87 Difference]: Start difference. First operand 7250 states and 8808 transitions. Second operand 4 states. [2018-11-28 11:28:48,504 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-28 11:28:48,504 INFO L93 Difference]: Finished difference Result 7966 states and 9627 transitions. [2018-11-28 11:28:48,504 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2018-11-28 11:28:48,504 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 303 [2018-11-28 11:28:48,504 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-28 11:28:48,516 INFO L225 Difference]: With dead ends: 7966 [2018-11-28 11:28:48,516 INFO L226 Difference]: Without dead ends: 7191 [2018-11-28 11:28:48,519 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 4 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 2 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2018-11-28 11:28:48,523 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 7191 states. [2018-11-28 11:28:48,889 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 7191 to 7053. [2018-11-28 11:28:48,889 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 7053 states. [2018-11-28 11:28:48,900 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 7053 states to 7053 states and 8580 transitions. [2018-11-28 11:28:48,902 INFO L78 Accepts]: Start accepts. Automaton has 7053 states and 8580 transitions. Word has length 303 [2018-11-28 11:28:48,903 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-28 11:28:48,903 INFO L480 AbstractCegarLoop]: Abstraction has 7053 states and 8580 transitions. [2018-11-28 11:28:48,903 INFO L481 AbstractCegarLoop]: Interpolant automaton has 4 states. [2018-11-28 11:28:48,903 INFO L276 IsEmpty]: Start isEmpty. Operand 7053 states and 8580 transitions. [2018-11-28 11:28:48,906 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 312 [2018-11-28 11:28:48,907 INFO L394 BasicCegarLoop]: Found error trace [2018-11-28 11:28:48,907 INFO L402 BasicCegarLoop]: trace histogram [9, 9, 9, 6, 5, 5, 5, 5, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-28 11:28:48,907 INFO L423 AbstractCegarLoop]: === Iteration 20 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-28 11:28:48,907 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-28 11:28:48,907 INFO L82 PathProgramCache]: Analyzing trace with hash 433667338, now seen corresponding path program 1 times [2018-11-28 11:28:48,907 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-28 11:28:48,908 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-28 11:28:48,908 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 11:28:48,908 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-28 11:28:48,908 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 11:28:48,920 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-28 11:28:48,985 INFO L134 CoverageAnalysis]: Checked inductivity of 438 backedges. 88 proven. 0 refuted. 0 times theorem prover too weak. 350 trivial. 0 not checked. [2018-11-28 11:28:48,985 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-28 11:28:48,985 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2018-11-28 11:28:48,986 INFO L459 AbstractCegarLoop]: Interpolant automaton has 4 states [2018-11-28 11:28:48,986 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2018-11-28 11:28:48,986 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2018-11-28 11:28:48,986 INFO L87 Difference]: Start difference. First operand 7053 states and 8580 transitions. Second operand 4 states. [2018-11-28 11:28:49,356 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-28 11:28:49,356 INFO L93 Difference]: Finished difference Result 11754 states and 14502 transitions. [2018-11-28 11:28:49,356 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2018-11-28 11:28:49,356 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 311 [2018-11-28 11:28:49,357 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-28 11:28:49,367 INFO L225 Difference]: With dead ends: 11754 [2018-11-28 11:28:49,367 INFO L226 Difference]: Without dead ends: 5207 [2018-11-28 11:28:49,374 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 4 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 2 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2018-11-28 11:28:49,377 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 5207 states. [2018-11-28 11:28:49,641 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 5207 to 4944. [2018-11-28 11:28:49,641 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 4944 states. [2018-11-28 11:28:49,647 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 4944 states to 4944 states and 5805 transitions. [2018-11-28 11:28:49,649 INFO L78 Accepts]: Start accepts. Automaton has 4944 states and 5805 transitions. Word has length 311 [2018-11-28 11:28:49,649 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-28 11:28:49,649 INFO L480 AbstractCegarLoop]: Abstraction has 4944 states and 5805 transitions. [2018-11-28 11:28:49,649 INFO L481 AbstractCegarLoop]: Interpolant automaton has 4 states. [2018-11-28 11:28:49,649 INFO L276 IsEmpty]: Start isEmpty. Operand 4944 states and 5805 transitions. [2018-11-28 11:28:49,652 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 345 [2018-11-28 11:28:49,652 INFO L394 BasicCegarLoop]: Found error trace [2018-11-28 11:28:49,652 INFO L402 BasicCegarLoop]: trace histogram [9, 9, 9, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 4, 4, 4, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-28 11:28:49,652 INFO L423 AbstractCegarLoop]: === Iteration 21 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-28 11:28:49,652 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-28 11:28:49,652 INFO L82 PathProgramCache]: Analyzing trace with hash -948129435, now seen corresponding path program 1 times [2018-11-28 11:28:49,652 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-28 11:28:49,652 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-28 11:28:49,653 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 11:28:49,653 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-28 11:28:49,653 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 11:28:49,668 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-28 11:28:49,775 INFO L134 CoverageAnalysis]: Checked inductivity of 538 backedges. 46 proven. 23 refuted. 0 times theorem prover too weak. 469 trivial. 0 not checked. [2018-11-28 11:28:49,775 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-28 11:28:49,775 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_0205b283-43b4-4d39-9152-1c66ac810fde/bin-2019/uautomizer/z3 Starting monitored process 11 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 11 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-28 11:28:49,792 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-28 11:28:49,920 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-28 11:28:49,925 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-28 11:28:50,031 INFO L134 CoverageAnalysis]: Checked inductivity of 538 backedges. 236 proven. 0 refuted. 0 times theorem prover too weak. 302 trivial. 0 not checked. [2018-11-28 11:28:50,047 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 1 imperfect interpolant sequences. [2018-11-28 11:28:50,047 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [7] imperfect sequences [5] total 10 [2018-11-28 11:28:50,047 INFO L459 AbstractCegarLoop]: Interpolant automaton has 10 states [2018-11-28 11:28:50,048 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 10 interpolants. [2018-11-28 11:28:50,048 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=25, Invalid=65, Unknown=0, NotChecked=0, Total=90 [2018-11-28 11:28:50,048 INFO L87 Difference]: Start difference. First operand 4944 states and 5805 transitions. Second operand 10 states. [2018-11-28 11:28:50,872 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-28 11:28:50,873 INFO L93 Difference]: Finished difference Result 12188 states and 14552 transitions. [2018-11-28 11:28:50,873 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2018-11-28 11:28:50,873 INFO L78 Accepts]: Start accepts. Automaton has 10 states. Word has length 344 [2018-11-28 11:28:50,873 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-28 11:28:50,883 INFO L225 Difference]: With dead ends: 12188 [2018-11-28 11:28:50,883 INFO L226 Difference]: Without dead ends: 3840 [2018-11-28 11:28:50,893 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 357 GetRequests, 345 SyntacticMatches, 1 SemanticMatches, 11 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 17 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=47, Invalid=109, Unknown=0, NotChecked=0, Total=156 [2018-11-28 11:28:50,896 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3840 states. [2018-11-28 11:28:51,107 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3840 to 3499. [2018-11-28 11:28:51,108 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3499 states. [2018-11-28 11:28:51,112 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3499 states to 3499 states and 4001 transitions. [2018-11-28 11:28:51,113 INFO L78 Accepts]: Start accepts. Automaton has 3499 states and 4001 transitions. Word has length 344 [2018-11-28 11:28:51,114 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-28 11:28:51,114 INFO L480 AbstractCegarLoop]: Abstraction has 3499 states and 4001 transitions. [2018-11-28 11:28:51,114 INFO L481 AbstractCegarLoop]: Interpolant automaton has 10 states. [2018-11-28 11:28:51,114 INFO L276 IsEmpty]: Start isEmpty. Operand 3499 states and 4001 transitions. [2018-11-28 11:28:51,116 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 361 [2018-11-28 11:28:51,116 INFO L394 BasicCegarLoop]: Found error trace [2018-11-28 11:28:51,117 INFO L402 BasicCegarLoop]: trace histogram [10, 10, 10, 6, 6, 6, 6, 6, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 4, 4, 4, 4, 4, 4, 4, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-28 11:28:51,117 INFO L423 AbstractCegarLoop]: === Iteration 22 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-28 11:28:51,117 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-28 11:28:51,117 INFO L82 PathProgramCache]: Analyzing trace with hash -1394352896, now seen corresponding path program 1 times [2018-11-28 11:28:51,117 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-28 11:28:51,117 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-28 11:28:51,118 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 11:28:51,118 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-28 11:28:51,118 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 11:28:51,134 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-28 11:28:51,149 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-28 11:28:51,213 INFO L469 BasicCegarLoop]: Counterexample might be feasible [2018-11-28 11:28:51,326 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction CFG 28.11 11:28:51 BoogieIcfgContainer [2018-11-28 11:28:51,326 INFO L132 PluginConnector]: ------------------------ END TraceAbstraction---------------------------- [2018-11-28 11:28:51,326 INFO L113 PluginConnector]: ------------------------Witness Printer---------------------------- [2018-11-28 11:28:51,326 INFO L271 PluginConnector]: Initializing Witness Printer... [2018-11-28 11:28:51,326 INFO L276 PluginConnector]: Witness Printer initialized [2018-11-28 11:28:51,326 INFO L185 PluginConnector]: Executing the observer RCFGCatcher from plugin Witness Printer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 28.11 11:28:26" (3/4) ... [2018-11-28 11:28:51,328 INFO L138 WitnessPrinter]: Generating witness for reachability counterexample [2018-11-28 11:28:51,454 INFO L145 WitnessManager]: Wrote witness to /tmp/vcloud-vcloud-master/worker/working_dir_0205b283-43b4-4d39-9152-1c66ac810fde/bin-2019/uautomizer/witness.graphml [2018-11-28 11:28:51,454 INFO L132 PluginConnector]: ------------------------ END Witness Printer---------------------------- [2018-11-28 11:28:51,455 INFO L168 Benchmark]: Toolchain (without parser) took 25586.23 ms. Allocated memory was 1.0 GB in the beginning and 2.9 GB in the end (delta: 1.9 GB). Free memory was 953.3 MB in the beginning and 1.6 GB in the end (delta: -626.6 MB). Peak memory consumption was 1.2 GB. Max. memory is 11.5 GB. [2018-11-28 11:28:51,456 INFO L168 Benchmark]: CDTParser took 0.15 ms. Allocated memory is still 1.0 GB. Free memory is still 979.6 MB. There was no memory consumed. Max. memory is 11.5 GB. [2018-11-28 11:28:51,456 INFO L168 Benchmark]: CACSL2BoogieTranslator took 196.54 ms. Allocated memory is still 1.0 GB. Free memory was 953.3 MB in the beginning and 939.9 MB in the end (delta: 13.4 MB). Peak memory consumption was 13.4 MB. Max. memory is 11.5 GB. [2018-11-28 11:28:51,456 INFO L168 Benchmark]: Boogie Procedure Inliner took 51.53 ms. Allocated memory was 1.0 GB in the beginning and 1.2 GB in the end (delta: 127.4 MB). Free memory was 939.9 MB in the beginning and 1.1 GB in the end (delta: -188.1 MB). Peak memory consumption was 15.9 MB. Max. memory is 11.5 GB. [2018-11-28 11:28:51,456 INFO L168 Benchmark]: Boogie Preprocessor took 21.24 ms. Allocated memory is still 1.2 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 2.7 MB). Peak memory consumption was 2.7 MB. Max. memory is 11.5 GB. [2018-11-28 11:28:51,456 INFO L168 Benchmark]: RCFGBuilder took 363.47 ms. Allocated memory is still 1.2 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 34.2 MB). Peak memory consumption was 34.2 MB. Max. memory is 11.5 GB. [2018-11-28 11:28:51,457 INFO L168 Benchmark]: TraceAbstraction took 24822.15 ms. Allocated memory was 1.2 GB in the beginning and 2.9 GB in the end (delta: 1.7 GB). Free memory was 1.1 GB in the beginning and 1.6 GB in the end (delta: -527.4 MB). Peak memory consumption was 1.2 GB. Max. memory is 11.5 GB. [2018-11-28 11:28:51,458 INFO L168 Benchmark]: Witness Printer took 127.91 ms. Allocated memory is still 2.9 GB. Free memory was 1.6 GB in the beginning and 1.6 GB in the end (delta: 38.6 MB). Peak memory consumption was 38.6 MB. Max. memory is 11.5 GB. [2018-11-28 11:28:51,460 INFO L336 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.15 ms. Allocated memory is still 1.0 GB. Free memory is still 979.6 MB. There was no memory consumed. Max. memory is 11.5 GB. * CACSL2BoogieTranslator took 196.54 ms. Allocated memory is still 1.0 GB. Free memory was 953.3 MB in the beginning and 939.9 MB in the end (delta: 13.4 MB). Peak memory consumption was 13.4 MB. Max. memory is 11.5 GB. * Boogie Procedure Inliner took 51.53 ms. Allocated memory was 1.0 GB in the beginning and 1.2 GB in the end (delta: 127.4 MB). Free memory was 939.9 MB in the beginning and 1.1 GB in the end (delta: -188.1 MB). Peak memory consumption was 15.9 MB. Max. memory is 11.5 GB. * Boogie Preprocessor took 21.24 ms. Allocated memory is still 1.2 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 2.7 MB). Peak memory consumption was 2.7 MB. Max. memory is 11.5 GB. * RCFGBuilder took 363.47 ms. Allocated memory is still 1.2 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 34.2 MB). Peak memory consumption was 34.2 MB. Max. memory is 11.5 GB. * TraceAbstraction took 24822.15 ms. Allocated memory was 1.2 GB in the beginning and 2.9 GB in the end (delta: 1.7 GB). Free memory was 1.1 GB in the beginning and 1.6 GB in the end (delta: -527.4 MB). Peak memory consumption was 1.2 GB. Max. memory is 11.5 GB. * Witness Printer took 127.91 ms. Allocated memory is still 2.9 GB. Free memory was 1.6 GB in the beginning and 1.6 GB in the end (delta: 38.6 MB). Peak memory consumption was 38.6 MB. Max. memory is 11.5 GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - CounterExampleResult [Line: 9]: a call of __VERIFIER_error() is reachable a call of __VERIFIER_error() is reachable We found a FailurePath: [L15] int max_loop ; [L16] int num ; [L17] int i ; [L18] int e ; [L19] int timer ; [L20] char data_0 ; [L21] char data_1 ; [L64] int P_1_pc; [L65] int P_1_st ; [L66] int P_1_i ; [L67] int P_1_ev ; [L122] int C_1_pc ; [L123] int C_1_st ; [L124] int C_1_i ; [L125] int C_1_ev ; [L126] int C_1_pr ; VAL [\old(C_1_ev)=76, \old(C_1_i)=68, \old(C_1_pc)=81, \old(C_1_pr)=78, \old(C_1_st)=80, \old(data_0)=74, \old(data_1)=67, \old(e)=66, \old(i)=70, \old(max_loop)=79, \old(num)=69, \old(P_1_ev)=71, \old(P_1_i)=77, \old(P_1_pc)=72, \old(P_1_st)=75, \old(timer)=73, C_1_ev=0, C_1_i=0, C_1_pc=0, C_1_pr=0, C_1_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=0, num=0, P_1_ev=0, P_1_i=0, P_1_pc=0, P_1_st=0, timer=0] [L490] int count ; [L491] int __retres2 ; [L495] num = 0 [L496] i = 0 [L497] max_loop = 2 [L499] timer = 0 [L500] P_1_pc = 0 [L501] C_1_pc = 0 [L503] count = 0 VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=0, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=0, \old(timer)=0, C_1_ev=0, C_1_i=0, C_1_pc=0, C_1_pr=0, C_1_st=0, count=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, P_1_ev=0, P_1_i=0, P_1_pc=0, P_1_st=0, timer=0] [L504] CALL init_model() VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=0, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=0, \old(timer)=0, C_1_ev=0, C_1_i=0, C_1_pc=0, C_1_pr=0, C_1_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, P_1_ev=0, P_1_i=0, P_1_pc=0, P_1_st=0, timer=0] [L483] P_1_i = 1 [L484] C_1_i = 1 VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=0, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=0, \old(timer)=0, C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, timer=0] [L504] RET init_model() VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=0, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=0, \old(timer)=0, C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, count=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, timer=0] [L505] CALL start_simulation() VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=0, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=0, \old(timer)=0, C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, timer=0] [L421] int kernel_st ; [L422] int tmp ; [L423] int tmp___0 ; [L427] kernel_st = 0 VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=0, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=0, \old(timer)=0, C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, data_0=0, data_1=0, e=0, i=0, kernel_st=0, max_loop=2, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, timer=0] [L428] FCALL update_channels() VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=0, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=0, \old(timer)=0, C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, data_0=0, data_1=0, e=0, i=0, kernel_st=0, max_loop=2, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, timer=0] [L429] CALL init_threads() VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=0, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=0, \old(timer)=0, C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, timer=0] [L226] COND TRUE (int )P_1_i == 1 [L227] P_1_st = 0 VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=0, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=0, \old(timer)=0, C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, timer=0] [L231] COND TRUE (int )C_1_i == 1 [L232] C_1_st = 0 VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=0, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=0, \old(timer)=0, C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, timer=0] [L429] RET init_threads() VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=0, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=0, \old(timer)=0, C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, data_0=0, data_1=0, e=0, i=0, kernel_st=0, max_loop=2, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, timer=0] [L430] FCALL fire_delta_events() VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=0, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=0, \old(timer)=0, C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, data_0=0, data_1=0, e=0, i=0, kernel_st=0, max_loop=2, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, timer=0] [L431] CALL activate_threads() VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=0, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=0, \old(timer)=0, C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, timer=0] [L365] int tmp ; [L366] int tmp___0 ; [L367] int tmp___1 ; VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=0, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=0, \old(timer)=0, C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, timer=0] [L371] CALL, EXPR is_P_1_triggered() VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=0, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=0, \old(timer)=0, C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, timer=0] [L104] int __retres1 ; VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=0, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=0, \old(timer)=0, C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, timer=0] [L107] COND FALSE !((int )P_1_pc == 1) VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=0, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=0, \old(timer)=0, C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, timer=0] [L117] __retres1 = 0 VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=0, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=0, \old(timer)=0, __retres1=0, C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, timer=0] [L119] return (__retres1); VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=0, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=0, \old(timer)=0, \result=0, __retres1=0, C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, timer=0] [L371] RET, EXPR is_P_1_triggered() VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=0, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=0, \old(timer)=0, C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, data_0=0, data_1=0, e=0, i=0, is_P_1_triggered()=0, max_loop=2, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, timer=0] [L371] tmp = is_P_1_triggered() [L373] COND FALSE !(\read(tmp)) VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=0, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=0, \old(timer)=0, C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, timer=0, tmp=0] [L379] CALL, EXPR is_C_1_triggered() VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=0, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=0, \old(timer)=0, C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, timer=0] [L186] int __retres1 ; VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=0, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=0, \old(timer)=0, C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, timer=0] [L189] COND FALSE !((int )C_1_pc == 1) VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=0, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=0, \old(timer)=0, C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, timer=0] [L199] COND FALSE !((int )C_1_pc == 2) VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=0, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=0, \old(timer)=0, C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, timer=0] [L209] __retres1 = 0 VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=0, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=0, \old(timer)=0, __retres1=0, C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, timer=0] [L211] return (__retres1); VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=0, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=0, \old(timer)=0, \result=0, __retres1=0, C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, timer=0] [L379] RET, EXPR is_C_1_triggered() VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=0, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=0, \old(timer)=0, C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, data_0=0, data_1=0, e=0, i=0, is_C_1_triggered()=0, max_loop=2, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, timer=0, tmp=0] [L379] tmp___1 = is_C_1_triggered() [L381] COND FALSE !(\read(tmp___1)) VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=0, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=0, \old(timer)=0, C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, timer=0, tmp=0, tmp___1=0] [L431] RET activate_threads() VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=0, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=0, \old(timer)=0, C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, data_0=0, data_1=0, e=0, i=0, kernel_st=0, max_loop=2, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, timer=0] [L432] FCALL reset_delta_events() VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=0, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=0, \old(timer)=0, C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, data_0=0, data_1=0, e=0, i=0, kernel_st=0, max_loop=2, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, timer=0] [L435] COND TRUE 1 VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=0, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=0, \old(timer)=0, C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, data_0=0, data_1=0, e=0, i=0, kernel_st=0, max_loop=2, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, timer=0] [L438] kernel_st = 1 VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=0, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=0, \old(timer)=0, C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, data_0=0, data_1=0, e=0, i=0, kernel_st=1, max_loop=2, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, timer=0] [L439] CALL eval() VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=0, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=0, \old(timer)=0, C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, timer=0] [L262] int tmp ; [L263] int tmp___0 ; [L264] int tmp___1 ; [L265] int tmp___2 ; VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=0, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=0, \old(timer)=0, C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, timer=0] [L269] COND TRUE 1 VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=0, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=0, \old(timer)=0, C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, timer=0] [L272] CALL, EXPR exists_runnable_thread() VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=0, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=0, \old(timer)=0, C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, timer=0] [L241] int __retres1 ; VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=0, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=0, \old(timer)=0, C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, timer=0] [L244] COND TRUE (int )P_1_st == 0 [L245] __retres1 = 1 VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=0, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=0, \old(timer)=0, __retres1=1, C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, timer=0] [L258] return (__retres1); VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=0, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=0, \old(timer)=0, \result=1, __retres1=1, C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, timer=0] [L272] RET, EXPR exists_runnable_thread() VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=0, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=0, \old(timer)=0, C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, data_0=0, data_1=0, e=0, exists_runnable_thread()=1, i=0, max_loop=2, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, timer=0] [L272] tmp___2 = exists_runnable_thread() [L274] COND TRUE \read(tmp___2) VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=0, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=0, \old(timer)=0, C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, timer=0, tmp___2=1] [L279] COND TRUE (int )P_1_st == 0 [L281] tmp = __VERIFIER_nondet_int() [L283] COND FALSE !(\read(tmp)) VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=0, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=0, \old(timer)=0, C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, timer=0, tmp=0, tmp___2=1] [L294] COND TRUE (int )C_1_st == 0 [L296] tmp___1 = __VERIFIER_nondet_int() [L298] COND TRUE \read(tmp___1) [L300] C_1_st = 1 VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=0, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=0, \old(timer)=0, C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=1, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, timer=0, tmp=0, tmp___1=1, tmp___2=1] [L301] CALL C_1() VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=1, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=0, \old(timer)=0, C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=1, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, timer=0] [L128] char c ; VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=1, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=0, \old(timer)=0, C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=1, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, timer=0] [L131] COND TRUE (int )C_1_pc == 0 VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=1, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=0, \old(timer)=0, C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=1, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, timer=0] [L146] COND TRUE i < max_loop VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=1, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=0, \old(timer)=0, C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=1, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, timer=0] [L148] COND TRUE num == 0 [L149] timer = 1 [L150] i += 1 [L151] C_1_pc = 1 [L152] C_1_st = 2 VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=1, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=0, \old(timer)=0, C_1_ev=0, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=0, data_1=0, e=0, i=1, max_loop=2, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, timer=1] [L301] RET C_1() VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=0, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=0, \old(timer)=0, C_1_ev=0, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=0, data_1=0, e=0, i=1, max_loop=2, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, timer=1, tmp=0, tmp___1=1, tmp___2=1] [L269] COND TRUE 1 VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=0, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=0, \old(timer)=0, C_1_ev=0, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=0, data_1=0, e=0, i=1, max_loop=2, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, timer=1, tmp=0, tmp___1=1, tmp___2=1] [L272] CALL, EXPR exists_runnable_thread() VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=0, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=0, \old(timer)=0, C_1_ev=0, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=0, data_1=0, e=0, i=1, max_loop=2, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, timer=1] [L241] int __retres1 ; VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=0, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=0, \old(timer)=0, C_1_ev=0, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=0, data_1=0, e=0, i=1, max_loop=2, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, timer=1] [L244] COND TRUE (int )P_1_st == 0 [L245] __retres1 = 1 VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=0, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=0, \old(timer)=0, __retres1=1, C_1_ev=0, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=0, data_1=0, e=0, i=1, max_loop=2, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, timer=1] [L258] return (__retres1); VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=0, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=0, \old(timer)=0, \result=1, __retres1=1, C_1_ev=0, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=0, data_1=0, e=0, i=1, max_loop=2, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, timer=1] [L272] RET, EXPR exists_runnable_thread() VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=0, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=0, \old(timer)=0, C_1_ev=0, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=0, data_1=0, e=0, exists_runnable_thread()=1, i=1, max_loop=2, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, timer=1, tmp=0, tmp___1=1, tmp___2=1] [L272] tmp___2 = exists_runnable_thread() [L274] COND TRUE \read(tmp___2) VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=0, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=0, \old(timer)=0, C_1_ev=0, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=0, data_1=0, e=0, i=1, max_loop=2, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, timer=1, tmp=0, tmp___1=1, tmp___2=1] [L279] COND TRUE (int )P_1_st == 0 [L281] tmp = __VERIFIER_nondet_int() [L283] COND TRUE \read(tmp) [L285] P_1_st = 1 VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=0, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=0, \old(timer)=0, C_1_ev=0, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=0, data_1=0, e=0, i=1, max_loop=2, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=1, timer=1, tmp=1, tmp___1=1, tmp___2=1] [L286] CALL P_1() VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=0, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=1, \old(timer)=0, C_1_ev=0, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=0, data_1=0, e=0, i=1, max_loop=2, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=1, timer=1] [L72] COND TRUE (int )P_1_pc == 0 VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=0, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=1, \old(timer)=0, C_1_ev=0, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=0, data_1=0, e=0, i=1, max_loop=2, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=1, timer=1] [L83] COND TRUE i < max_loop VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=0, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=1, \old(timer)=0, C_1_ev=0, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=0, data_1=0, e=0, i=1, max_loop=2, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=1, timer=1] [L86] CALL write_data(num, 'A') VAL [\old(c)=65, \old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=0, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(i___0)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=1, \old(timer)=0, C_1_ev=0, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=0, data_1=0, e=0, i=1, max_loop=2, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=1, timer=1] [L49] COND TRUE i___0 == 0 [L50] data_0 = c VAL [\old(c)=65, \old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=0, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(i___0)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=1, \old(timer)=0, c=65, C_1_ev=0, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, i___0=0, max_loop=2, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=1, timer=1] [L86] RET write_data(num, 'A') VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=0, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=1, \old(timer)=0, C_1_ev=0, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, max_loop=2, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=1, timer=1] [L87] num += 1 [L88] P_1_pc = 1 [L89] P_1_st = 2 VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=0, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=1, \old(timer)=0, C_1_ev=0, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, max_loop=2, num=1, P_1_ev=0, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1] [L286] RET P_1() VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=0, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=0, \old(timer)=0, C_1_ev=0, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, max_loop=2, num=1, P_1_ev=0, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1, tmp=1, tmp___1=1, tmp___2=1] [L294] COND FALSE !((int )C_1_st == 0) VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=0, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=0, \old(timer)=0, C_1_ev=0, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, max_loop=2, num=1, P_1_ev=0, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1, tmp=1, tmp___1=1, tmp___2=1] [L269] COND TRUE 1 VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=0, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=0, \old(timer)=0, C_1_ev=0, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, max_loop=2, num=1, P_1_ev=0, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1, tmp=1, tmp___1=1, tmp___2=1] [L272] CALL, EXPR exists_runnable_thread() VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=0, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=0, \old(timer)=0, C_1_ev=0, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, max_loop=2, num=1, P_1_ev=0, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1] [L241] int __retres1 ; VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=0, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=0, \old(timer)=0, C_1_ev=0, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, max_loop=2, num=1, P_1_ev=0, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1] [L244] COND FALSE !((int )P_1_st == 0) VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=0, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=0, \old(timer)=0, C_1_ev=0, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, max_loop=2, num=1, P_1_ev=0, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1] [L248] COND FALSE !((int )C_1_st == 0) [L256] __retres1 = 0 VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=0, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=0, \old(timer)=0, __retres1=0, C_1_ev=0, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, max_loop=2, num=1, P_1_ev=0, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1] [L258] return (__retres1); VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=0, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=0, \old(timer)=0, \result=0, __retres1=0, C_1_ev=0, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, max_loop=2, num=1, P_1_ev=0, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1] [L272] RET, EXPR exists_runnable_thread() VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=0, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=0, \old(timer)=0, C_1_ev=0, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, exists_runnable_thread()=0, i=1, max_loop=2, num=1, P_1_ev=0, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1, tmp=1, tmp___1=1, tmp___2=1] [L272] tmp___2 = exists_runnable_thread() [L274] COND FALSE !(\read(tmp___2)) VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=0, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=0, \old(timer)=0, C_1_ev=0, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, max_loop=2, num=1, P_1_ev=0, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1, tmp=1, tmp___1=1, tmp___2=0] [L439] RET eval() VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=0, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=0, \old(timer)=0, C_1_ev=0, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, kernel_st=1, max_loop=2, num=1, P_1_ev=0, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1] [L442] kernel_st = 2 VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=0, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=0, \old(timer)=0, C_1_ev=0, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, kernel_st=2, max_loop=2, num=1, P_1_ev=0, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1] [L443] FCALL update_channels() VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=0, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=0, \old(timer)=0, C_1_ev=0, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, kernel_st=2, max_loop=2, num=1, P_1_ev=0, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1] [L446] kernel_st = 3 VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=0, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=0, \old(timer)=0, C_1_ev=0, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, kernel_st=3, max_loop=2, num=1, P_1_ev=0, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1] [L447] FCALL fire_delta_events() VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=0, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=0, \old(timer)=0, C_1_ev=0, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, kernel_st=3, max_loop=2, num=1, P_1_ev=0, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1] [L448] CALL activate_threads() VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=2, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=2, \old(timer)=0, C_1_ev=0, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, max_loop=2, num=1, P_1_ev=0, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1] [L365] int tmp ; [L366] int tmp___0 ; [L367] int tmp___1 ; VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=2, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=2, \old(timer)=0, C_1_ev=0, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, max_loop=2, num=1, P_1_ev=0, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1] [L371] CALL, EXPR is_P_1_triggered() VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=2, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=2, \old(timer)=0, C_1_ev=0, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, max_loop=2, num=1, P_1_ev=0, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1] [L104] int __retres1 ; VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=2, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=2, \old(timer)=0, C_1_ev=0, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, max_loop=2, num=1, P_1_ev=0, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1] [L107] COND TRUE (int )P_1_pc == 1 VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=2, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=2, \old(timer)=0, C_1_ev=0, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, max_loop=2, num=1, P_1_ev=0, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1] [L108] COND FALSE !((int )P_1_ev == 1) VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=2, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=2, \old(timer)=0, C_1_ev=0, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, max_loop=2, num=1, P_1_ev=0, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1] [L117] __retres1 = 0 VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=2, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=2, \old(timer)=0, __retres1=0, C_1_ev=0, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, max_loop=2, num=1, P_1_ev=0, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1] [L119] return (__retres1); VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=2, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=2, \old(timer)=0, \result=0, __retres1=0, C_1_ev=0, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, max_loop=2, num=1, P_1_ev=0, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1] [L371] RET, EXPR is_P_1_triggered() VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=2, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=2, \old(timer)=0, C_1_ev=0, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, is_P_1_triggered()=0, max_loop=2, num=1, P_1_ev=0, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1] [L371] tmp = is_P_1_triggered() [L373] COND FALSE !(\read(tmp)) VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=2, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=2, \old(timer)=0, C_1_ev=0, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, max_loop=2, num=1, P_1_ev=0, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1, tmp=0] [L379] CALL, EXPR is_C_1_triggered() VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=2, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=2, \old(timer)=0, C_1_ev=0, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, max_loop=2, num=1, P_1_ev=0, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1] [L186] int __retres1 ; VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=2, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=2, \old(timer)=0, C_1_ev=0, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, max_loop=2, num=1, P_1_ev=0, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1] [L189] COND TRUE (int )C_1_pc == 1 VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=2, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=2, \old(timer)=0, C_1_ev=0, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, max_loop=2, num=1, P_1_ev=0, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1] [L190] COND FALSE !((int )e == 1) VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=2, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=2, \old(timer)=0, C_1_ev=0, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, max_loop=2, num=1, P_1_ev=0, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1] [L199] COND FALSE !((int )C_1_pc == 2) VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=2, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=2, \old(timer)=0, C_1_ev=0, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, max_loop=2, num=1, P_1_ev=0, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1] [L209] __retres1 = 0 VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=2, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=2, \old(timer)=0, __retres1=0, C_1_ev=0, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, max_loop=2, num=1, P_1_ev=0, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1] [L211] return (__retres1); VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=2, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=2, \old(timer)=0, \result=0, __retres1=0, C_1_ev=0, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, max_loop=2, num=1, P_1_ev=0, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1] [L379] RET, EXPR is_C_1_triggered() VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=2, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=2, \old(timer)=0, C_1_ev=0, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, is_C_1_triggered()=0, max_loop=2, num=1, P_1_ev=0, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1, tmp=0] [L379] tmp___1 = is_C_1_triggered() [L381] COND FALSE !(\read(tmp___1)) VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=2, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=2, \old(timer)=0, C_1_ev=0, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, max_loop=2, num=1, P_1_ev=0, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1, tmp=0, tmp___1=0] [L448] RET activate_threads() VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=0, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=0, \old(timer)=0, C_1_ev=0, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, kernel_st=3, max_loop=2, num=1, P_1_ev=0, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1] [L449] FCALL reset_delta_events() VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=0, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=0, \old(timer)=0, C_1_ev=0, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, kernel_st=3, max_loop=2, num=1, P_1_ev=0, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1] [L452] CALL, EXPR exists_runnable_thread() VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=0, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=0, \old(timer)=0, C_1_ev=0, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, max_loop=2, num=1, P_1_ev=0, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1] [L241] int __retres1 ; VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=0, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=0, \old(timer)=0, C_1_ev=0, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, max_loop=2, num=1, P_1_ev=0, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1] [L244] COND FALSE !((int )P_1_st == 0) VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=0, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=0, \old(timer)=0, C_1_ev=0, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, max_loop=2, num=1, P_1_ev=0, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1] [L248] COND FALSE !((int )C_1_st == 0) [L256] __retres1 = 0 VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=0, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=0, \old(timer)=0, __retres1=0, C_1_ev=0, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, max_loop=2, num=1, P_1_ev=0, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1] [L258] return (__retres1); VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=0, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=0, \old(timer)=0, \result=0, __retres1=0, C_1_ev=0, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, max_loop=2, num=1, P_1_ev=0, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1] [L452] RET, EXPR exists_runnable_thread() VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=0, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=0, \old(timer)=0, C_1_ev=0, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, exists_runnable_thread()=0, i=1, kernel_st=3, max_loop=2, num=1, P_1_ev=0, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1] [L452] tmp = exists_runnable_thread() [L454] COND TRUE tmp == 0 [L456] kernel_st = 4 VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=0, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=0, \old(timer)=0, C_1_ev=0, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, kernel_st=4, max_loop=2, num=1, P_1_ev=0, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1, tmp=0] [L457] CALL fire_time_events() VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=0, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=0, \old(timer)=0, C_1_ev=0, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, max_loop=2, num=1, P_1_ev=0, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1] [L336] C_1_ev = 1 [L338] P_1_ev = 1 VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=0, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=0, \old(timer)=0, C_1_ev=1, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, max_loop=2, num=1, P_1_ev=1, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1] [L457] RET fire_time_events() VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=0, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=0, \old(timer)=0, C_1_ev=1, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, kernel_st=4, max_loop=2, num=1, P_1_ev=1, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1, tmp=0] [L458] CALL activate_threads() VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=2, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=2, \old(timer)=0, C_1_ev=1, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, max_loop=2, num=1, P_1_ev=1, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1] [L365] int tmp ; [L366] int tmp___0 ; [L367] int tmp___1 ; VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=2, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=2, \old(timer)=0, C_1_ev=1, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, max_loop=2, num=1, P_1_ev=1, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1] [L371] CALL, EXPR is_P_1_triggered() VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=2, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=2, \old(timer)=0, C_1_ev=1, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, max_loop=2, num=1, P_1_ev=1, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1] [L104] int __retres1 ; VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=2, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=2, \old(timer)=0, C_1_ev=1, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, max_loop=2, num=1, P_1_ev=1, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1] [L107] COND TRUE (int )P_1_pc == 1 VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=2, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=2, \old(timer)=0, C_1_ev=1, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, max_loop=2, num=1, P_1_ev=1, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1] [L108] COND TRUE (int )P_1_ev == 1 [L109] __retres1 = 1 VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=2, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=2, \old(timer)=0, __retres1=1, C_1_ev=1, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, max_loop=2, num=1, P_1_ev=1, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1] [L119] return (__retres1); VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=2, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=2, \old(timer)=0, \result=1, __retres1=1, C_1_ev=1, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, max_loop=2, num=1, P_1_ev=1, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1] [L371] RET, EXPR is_P_1_triggered() VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=2, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=2, \old(timer)=0, C_1_ev=1, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, is_P_1_triggered()=1, max_loop=2, num=1, P_1_ev=1, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1] [L371] tmp = is_P_1_triggered() [L373] COND TRUE \read(tmp) [L374] P_1_st = 0 VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=2, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=2, \old(timer)=0, C_1_ev=1, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, max_loop=2, num=1, P_1_ev=1, P_1_i=1, P_1_pc=1, P_1_st=0, timer=1, tmp=1] [L379] CALL, EXPR is_C_1_triggered() VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=2, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=2, \old(timer)=0, C_1_ev=1, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, max_loop=2, num=1, P_1_ev=1, P_1_i=1, P_1_pc=1, P_1_st=0, timer=1] [L186] int __retres1 ; VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=2, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=2, \old(timer)=0, C_1_ev=1, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, max_loop=2, num=1, P_1_ev=1, P_1_i=1, P_1_pc=1, P_1_st=0, timer=1] [L189] COND TRUE (int )C_1_pc == 1 VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=2, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=2, \old(timer)=0, C_1_ev=1, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, max_loop=2, num=1, P_1_ev=1, P_1_i=1, P_1_pc=1, P_1_st=0, timer=1] [L190] COND FALSE !((int )e == 1) VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=2, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=2, \old(timer)=0, C_1_ev=1, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, max_loop=2, num=1, P_1_ev=1, P_1_i=1, P_1_pc=1, P_1_st=0, timer=1] [L199] COND FALSE !((int )C_1_pc == 2) VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=2, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=2, \old(timer)=0, C_1_ev=1, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, max_loop=2, num=1, P_1_ev=1, P_1_i=1, P_1_pc=1, P_1_st=0, timer=1] [L209] __retres1 = 0 VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=2, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=2, \old(timer)=0, __retres1=0, C_1_ev=1, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, max_loop=2, num=1, P_1_ev=1, P_1_i=1, P_1_pc=1, P_1_st=0, timer=1] [L211] return (__retres1); VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=2, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=2, \old(timer)=0, \result=0, __retres1=0, C_1_ev=1, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, max_loop=2, num=1, P_1_ev=1, P_1_i=1, P_1_pc=1, P_1_st=0, timer=1] [L379] RET, EXPR is_C_1_triggered() VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=2, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=2, \old(timer)=0, C_1_ev=1, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, is_C_1_triggered()=0, max_loop=2, num=1, P_1_ev=1, P_1_i=1, P_1_pc=1, P_1_st=0, timer=1, tmp=1] [L379] tmp___1 = is_C_1_triggered() [L381] COND FALSE !(\read(tmp___1)) VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=2, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=2, \old(timer)=0, C_1_ev=1, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, max_loop=2, num=1, P_1_ev=1, P_1_i=1, P_1_pc=1, P_1_st=0, timer=1, tmp=1, tmp___1=0] [L458] RET activate_threads() VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=0, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=0, \old(timer)=0, C_1_ev=1, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, kernel_st=4, max_loop=2, num=1, P_1_ev=1, P_1_i=1, P_1_pc=1, P_1_st=0, timer=1, tmp=0] [L459] CALL reset_time_events() VAL [\old(C_1_ev)=1, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=0, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=1, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=0, \old(timer)=0, C_1_ev=1, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, max_loop=2, num=1, P_1_ev=1, P_1_i=1, P_1_pc=1, P_1_st=0, timer=1] [L350] COND TRUE (int )P_1_ev == 1 [L351] P_1_ev = 2 VAL [\old(C_1_ev)=1, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=0, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=1, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=0, \old(timer)=0, C_1_ev=1, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, max_loop=2, num=1, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=0, timer=1] [L355] COND TRUE (int )C_1_ev == 1 [L356] C_1_ev = 2 VAL [\old(C_1_ev)=1, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=0, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=1, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=0, \old(timer)=0, C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, max_loop=2, num=1, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=0, timer=1] [L459] RET reset_time_events() VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=0, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=0, \old(timer)=0, C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, kernel_st=4, max_loop=2, num=1, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=0, timer=1, tmp=0] [L465] CALL, EXPR stop_simulation() VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=0, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=0, \old(timer)=0, C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, max_loop=2, num=1, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=0, timer=1] [L402] int tmp ; [L403] int __retres2 ; VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=0, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=0, \old(timer)=0, C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, max_loop=2, num=1, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=0, timer=1] [L407] CALL, EXPR exists_runnable_thread() VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=0, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=0, \old(timer)=0, C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, max_loop=2, num=1, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=0, timer=1] [L241] int __retres1 ; VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=0, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=0, \old(timer)=0, C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, max_loop=2, num=1, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=0, timer=1] [L244] COND TRUE (int )P_1_st == 0 [L245] __retres1 = 1 VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=0, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=0, \old(timer)=0, __retres1=1, C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, max_loop=2, num=1, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=0, timer=1] [L258] return (__retres1); VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=0, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=0, \old(timer)=0, \result=1, __retres1=1, C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, max_loop=2, num=1, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=0, timer=1] [L407] RET, EXPR exists_runnable_thread() VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=0, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=0, \old(timer)=0, C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, exists_runnable_thread()=1, i=1, max_loop=2, num=1, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=0, timer=1] [L407] tmp = exists_runnable_thread() [L409] COND TRUE \read(tmp) [L410] __retres2 = 0 VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=0, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=0, \old(timer)=0, __retres2=0, C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, max_loop=2, num=1, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=0, timer=1, tmp=1] [L417] return (__retres2); VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=0, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=0, \old(timer)=0, \result=0, __retres2=0, C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, max_loop=2, num=1, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=0, timer=1, tmp=1] [L465] RET, EXPR stop_simulation() VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=0, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=0, \old(timer)=0, C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, kernel_st=4, max_loop=2, num=1, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=0, stop_simulation()=0, timer=1, tmp=0] [L465] tmp___0 = stop_simulation() [L467] COND FALSE !(\read(tmp___0)) VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=0, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=0, \old(timer)=0, C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, kernel_st=4, max_loop=2, num=1, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=0, timer=1, tmp=0, tmp___0=0] [L435] COND TRUE 1 VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=0, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=0, \old(timer)=0, C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, kernel_st=4, max_loop=2, num=1, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=0, timer=1, tmp=0, tmp___0=0] [L438] kernel_st = 1 VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=0, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=0, \old(timer)=0, C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, kernel_st=1, max_loop=2, num=1, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=0, timer=1, tmp=0, tmp___0=0] [L439] CALL eval() VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=1, \old(C_1_st)=2, \old(data_0)=65, \old(data_1)=0, \old(i)=1, \old(max_loop)=0, \old(num)=1, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=1, \old(P_1_st)=0, \old(timer)=1, C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, max_loop=2, num=1, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=0, timer=1] [L262] int tmp ; [L263] int tmp___0 ; [L264] int tmp___1 ; [L265] int tmp___2 ; VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=1, \old(C_1_st)=2, \old(data_0)=65, \old(data_1)=0, \old(i)=1, \old(max_loop)=0, \old(num)=1, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=1, \old(P_1_st)=0, \old(timer)=1, C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, max_loop=2, num=1, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=0, timer=1] [L269] COND TRUE 1 VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=1, \old(C_1_st)=2, \old(data_0)=65, \old(data_1)=0, \old(i)=1, \old(max_loop)=0, \old(num)=1, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=1, \old(P_1_st)=0, \old(timer)=1, C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, max_loop=2, num=1, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=0, timer=1] [L272] CALL, EXPR exists_runnable_thread() VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=1, \old(C_1_st)=2, \old(data_0)=65, \old(data_1)=0, \old(i)=1, \old(max_loop)=0, \old(num)=1, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=1, \old(P_1_st)=0, \old(timer)=1, C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, max_loop=2, num=1, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=0, timer=1] [L241] int __retres1 ; VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=1, \old(C_1_st)=2, \old(data_0)=65, \old(data_1)=0, \old(i)=1, \old(max_loop)=0, \old(num)=1, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=1, \old(P_1_st)=0, \old(timer)=1, C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, max_loop=2, num=1, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=0, timer=1] [L244] COND TRUE (int )P_1_st == 0 [L245] __retres1 = 1 VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=1, \old(C_1_st)=2, \old(data_0)=65, \old(data_1)=0, \old(i)=1, \old(max_loop)=0, \old(num)=1, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=1, \old(P_1_st)=0, \old(timer)=1, __retres1=1, C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, max_loop=2, num=1, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=0, timer=1] [L258] return (__retres1); VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=1, \old(C_1_st)=2, \old(data_0)=65, \old(data_1)=0, \old(i)=1, \old(max_loop)=0, \old(num)=1, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=1, \old(P_1_st)=0, \old(timer)=1, \result=1, __retres1=1, C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, max_loop=2, num=1, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=0, timer=1] [L272] RET, EXPR exists_runnable_thread() VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=1, \old(C_1_st)=2, \old(data_0)=65, \old(data_1)=0, \old(i)=1, \old(max_loop)=0, \old(num)=1, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=1, \old(P_1_st)=0, \old(timer)=1, C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, exists_runnable_thread()=1, i=1, max_loop=2, num=1, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=0, timer=1] [L272] tmp___2 = exists_runnable_thread() [L274] COND TRUE \read(tmp___2) VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=1, \old(C_1_st)=2, \old(data_0)=65, \old(data_1)=0, \old(i)=1, \old(max_loop)=0, \old(num)=1, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=1, \old(P_1_st)=0, \old(timer)=1, C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, max_loop=2, num=1, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=0, timer=1, tmp___2=1] [L279] COND TRUE (int )P_1_st == 0 [L281] tmp = __VERIFIER_nondet_int() [L283] COND TRUE \read(tmp) [L285] P_1_st = 1 VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=1, \old(C_1_st)=2, \old(data_0)=65, \old(data_1)=0, \old(i)=1, \old(max_loop)=0, \old(num)=1, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=1, \old(P_1_st)=0, \old(timer)=1, C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, max_loop=2, num=1, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=1, timer=1, tmp=1, tmp___2=1] [L286] CALL P_1() VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=1, \old(C_1_st)=2, \old(data_0)=65, \old(data_1)=0, \old(i)=1, \old(max_loop)=0, \old(num)=1, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=1, \old(P_1_st)=1, \old(timer)=1, C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, max_loop=2, num=1, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=1, timer=1] [L72] COND FALSE !((int )P_1_pc == 0) VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=1, \old(C_1_st)=2, \old(data_0)=65, \old(data_1)=0, \old(i)=1, \old(max_loop)=0, \old(num)=1, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=1, \old(P_1_st)=1, \old(timer)=1, C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, max_loop=2, num=1, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=1, timer=1] [L75] COND TRUE (int )P_1_pc == 1 VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=1, \old(C_1_st)=2, \old(data_0)=65, \old(data_1)=0, \old(i)=1, \old(max_loop)=0, \old(num)=1, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=1, \old(P_1_st)=1, \old(timer)=1, C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, max_loop=2, num=1, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=1, timer=1] [L83] COND TRUE i < max_loop VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=1, \old(C_1_st)=2, \old(data_0)=65, \old(data_1)=0, \old(i)=1, \old(max_loop)=0, \old(num)=1, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=1, \old(P_1_st)=1, \old(timer)=1, C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, max_loop=2, num=1, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=1, timer=1] [L86] CALL write_data(num, 'A') VAL [\old(c)=65, \old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=1, \old(C_1_st)=2, \old(data_0)=65, \old(data_1)=0, \old(i)=1, \old(i___0)=1, \old(max_loop)=0, \old(num)=1, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=1, \old(P_1_st)=1, \old(timer)=1, C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, max_loop=2, num=1, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=1, timer=1] [L49] COND FALSE !(i___0 == 0) VAL [\old(c)=65, \old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=1, \old(C_1_st)=2, \old(data_0)=65, \old(data_1)=0, \old(i)=1, \old(i___0)=1, \old(max_loop)=0, \old(num)=1, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=1, \old(P_1_st)=1, \old(timer)=1, c=65, C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, i___0=1, max_loop=2, num=1, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=1, timer=1] [L52] COND TRUE i___0 == 1 [L53] data_1 = c VAL [\old(c)=65, \old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=1, \old(C_1_st)=2, \old(data_0)=65, \old(data_1)=0, \old(i)=1, \old(i___0)=1, \old(max_loop)=0, \old(num)=1, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=1, \old(P_1_st)=1, \old(timer)=1, c=65, C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, i___0=1, max_loop=2, num=1, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=1, timer=1] [L86] RET write_data(num, 'A') VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=1, \old(C_1_st)=2, \old(data_0)=65, \old(data_1)=0, \old(i)=1, \old(max_loop)=0, \old(num)=1, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=1, \old(P_1_st)=1, \old(timer)=1, C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, max_loop=2, num=1, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=1, timer=1] [L87] num += 1 [L88] P_1_pc = 1 [L89] P_1_st = 2 VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=1, \old(C_1_st)=2, \old(data_0)=65, \old(data_1)=0, \old(i)=1, \old(max_loop)=0, \old(num)=1, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=1, \old(P_1_st)=1, \old(timer)=1, C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, max_loop=2, num=2, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1] [L286] RET P_1() VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=1, \old(C_1_st)=2, \old(data_0)=65, \old(data_1)=0, \old(i)=1, \old(max_loop)=0, \old(num)=1, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=1, \old(P_1_st)=0, \old(timer)=1, C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, max_loop=2, num=2, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1, tmp=1, tmp___2=1] [L294] COND FALSE !((int )C_1_st == 0) VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=1, \old(C_1_st)=2, \old(data_0)=65, \old(data_1)=0, \old(i)=1, \old(max_loop)=0, \old(num)=1, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=1, \old(P_1_st)=0, \old(timer)=1, C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, max_loop=2, num=2, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1, tmp=1, tmp___2=1] [L269] COND TRUE 1 VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=1, \old(C_1_st)=2, \old(data_0)=65, \old(data_1)=0, \old(i)=1, \old(max_loop)=0, \old(num)=1, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=1, \old(P_1_st)=0, \old(timer)=1, C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, max_loop=2, num=2, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1, tmp=1, tmp___2=1] [L272] CALL, EXPR exists_runnable_thread() VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=1, \old(C_1_st)=2, \old(data_0)=65, \old(data_1)=0, \old(i)=1, \old(max_loop)=0, \old(num)=1, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=1, \old(P_1_st)=0, \old(timer)=1, C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, max_loop=2, num=2, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1] [L241] int __retres1 ; VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=1, \old(C_1_st)=2, \old(data_0)=65, \old(data_1)=0, \old(i)=1, \old(max_loop)=0, \old(num)=1, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=1, \old(P_1_st)=0, \old(timer)=1, C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, max_loop=2, num=2, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1] [L244] COND FALSE !((int )P_1_st == 0) VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=1, \old(C_1_st)=2, \old(data_0)=65, \old(data_1)=0, \old(i)=1, \old(max_loop)=0, \old(num)=1, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=1, \old(P_1_st)=0, \old(timer)=1, C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, max_loop=2, num=2, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1] [L248] COND FALSE !((int )C_1_st == 0) [L256] __retres1 = 0 VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=1, \old(C_1_st)=2, \old(data_0)=65, \old(data_1)=0, \old(i)=1, \old(max_loop)=0, \old(num)=1, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=1, \old(P_1_st)=0, \old(timer)=1, __retres1=0, C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, max_loop=2, num=2, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1] [L258] return (__retres1); VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=1, \old(C_1_st)=2, \old(data_0)=65, \old(data_1)=0, \old(i)=1, \old(max_loop)=0, \old(num)=1, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=1, \old(P_1_st)=0, \old(timer)=1, \result=0, __retres1=0, C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, max_loop=2, num=2, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1] [L272] RET, EXPR exists_runnable_thread() VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=1, \old(C_1_st)=2, \old(data_0)=65, \old(data_1)=0, \old(i)=1, \old(max_loop)=0, \old(num)=1, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=1, \old(P_1_st)=0, \old(timer)=1, C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, exists_runnable_thread()=0, i=1, max_loop=2, num=2, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1, tmp=1, tmp___2=1] [L272] tmp___2 = exists_runnable_thread() [L274] COND FALSE !(\read(tmp___2)) VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=1, \old(C_1_st)=2, \old(data_0)=65, \old(data_1)=0, \old(i)=1, \old(max_loop)=0, \old(num)=1, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=1, \old(P_1_st)=0, \old(timer)=1, C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, max_loop=2, num=2, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1, tmp=1, tmp___2=0] [L439] RET eval() VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=0, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=0, \old(timer)=0, C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, kernel_st=1, max_loop=2, num=2, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1, tmp=0, tmp___0=0] [L442] kernel_st = 2 VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=0, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=0, \old(timer)=0, C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, kernel_st=2, max_loop=2, num=2, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1, tmp=0, tmp___0=0] [L443] FCALL update_channels() VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=0, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=0, \old(timer)=0, C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, kernel_st=2, max_loop=2, num=2, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1, tmp=0, tmp___0=0] [L446] kernel_st = 3 VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=0, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=0, \old(timer)=0, C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, kernel_st=3, max_loop=2, num=2, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1, tmp=0, tmp___0=0] [L447] FCALL fire_delta_events() VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=0, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=0, \old(timer)=0, C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, kernel_st=3, max_loop=2, num=2, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1, tmp=0, tmp___0=0] [L448] CALL activate_threads() VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=2, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=2, \old(timer)=0, C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, max_loop=2, num=2, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1] [L365] int tmp ; [L366] int tmp___0 ; [L367] int tmp___1 ; VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=2, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=2, \old(timer)=0, C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, max_loop=2, num=2, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1] [L371] CALL, EXPR is_P_1_triggered() VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=2, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=2, \old(timer)=0, C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, max_loop=2, num=2, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1] [L104] int __retres1 ; VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=2, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=2, \old(timer)=0, C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, max_loop=2, num=2, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1] [L107] COND TRUE (int )P_1_pc == 1 VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=2, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=2, \old(timer)=0, C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, max_loop=2, num=2, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1] [L108] COND FALSE !((int )P_1_ev == 1) VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=2, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=2, \old(timer)=0, C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, max_loop=2, num=2, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1] [L117] __retres1 = 0 VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=2, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=2, \old(timer)=0, __retres1=0, C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, max_loop=2, num=2, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1] [L119] return (__retres1); VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=2, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=2, \old(timer)=0, \result=0, __retres1=0, C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, max_loop=2, num=2, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1] [L371] RET, EXPR is_P_1_triggered() VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=2, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=2, \old(timer)=0, C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, is_P_1_triggered()=0, max_loop=2, num=2, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1] [L371] tmp = is_P_1_triggered() [L373] COND FALSE !(\read(tmp)) VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=2, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=2, \old(timer)=0, C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, max_loop=2, num=2, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1, tmp=0] [L379] CALL, EXPR is_C_1_triggered() VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=2, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=2, \old(timer)=0, C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, max_loop=2, num=2, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1] [L186] int __retres1 ; VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=2, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=2, \old(timer)=0, C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, max_loop=2, num=2, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1] [L189] COND TRUE (int )C_1_pc == 1 VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=2, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=2, \old(timer)=0, C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, max_loop=2, num=2, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1] [L190] COND FALSE !((int )e == 1) VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=2, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=2, \old(timer)=0, C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, max_loop=2, num=2, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1] [L199] COND FALSE !((int )C_1_pc == 2) VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=2, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=2, \old(timer)=0, C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, max_loop=2, num=2, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1] [L209] __retres1 = 0 VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=2, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=2, \old(timer)=0, __retres1=0, C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, max_loop=2, num=2, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1] [L211] return (__retres1); VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=2, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=2, \old(timer)=0, \result=0, __retres1=0, C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, max_loop=2, num=2, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1] [L379] RET, EXPR is_C_1_triggered() VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=2, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=2, \old(timer)=0, C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, is_C_1_triggered()=0, max_loop=2, num=2, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1, tmp=0] [L379] tmp___1 = is_C_1_triggered() [L381] COND FALSE !(\read(tmp___1)) VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=2, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=2, \old(timer)=0, C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, max_loop=2, num=2, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1, tmp=0, tmp___1=0] [L448] RET activate_threads() VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=0, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=0, \old(timer)=0, C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, kernel_st=3, max_loop=2, num=2, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1, tmp=0, tmp___0=0] [L449] FCALL reset_delta_events() VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=0, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=0, \old(timer)=0, C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, kernel_st=3, max_loop=2, num=2, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1, tmp=0, tmp___0=0] [L452] CALL, EXPR exists_runnable_thread() VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=0, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=0, \old(timer)=0, C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, max_loop=2, num=2, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1] [L241] int __retres1 ; VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=0, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=0, \old(timer)=0, C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, max_loop=2, num=2, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1] [L244] COND FALSE !((int )P_1_st == 0) VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=0, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=0, \old(timer)=0, C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, max_loop=2, num=2, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1] [L248] COND FALSE !((int )C_1_st == 0) [L256] __retres1 = 0 VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=0, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=0, \old(timer)=0, __retres1=0, C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, max_loop=2, num=2, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1] [L258] return (__retres1); VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=0, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=0, \old(timer)=0, \result=0, __retres1=0, C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, max_loop=2, num=2, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1] [L452] RET, EXPR exists_runnable_thread() VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=0, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=0, \old(timer)=0, C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, exists_runnable_thread()=0, i=1, kernel_st=3, max_loop=2, num=2, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1, tmp=0, tmp___0=0] [L452] tmp = exists_runnable_thread() [L454] COND TRUE tmp == 0 [L456] kernel_st = 4 VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=0, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=0, \old(timer)=0, C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, kernel_st=4, max_loop=2, num=2, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1, tmp=0, tmp___0=0] [L457] CALL fire_time_events() VAL [\old(C_1_ev)=2, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=0, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=2, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=0, \old(timer)=0, C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, max_loop=2, num=2, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1] [L336] C_1_ev = 1 [L338] P_1_ev = 1 VAL [\old(C_1_ev)=2, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=0, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=2, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=0, \old(timer)=0, C_1_ev=1, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, max_loop=2, num=2, P_1_ev=1, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1] [L457] RET fire_time_events() VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=0, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=0, \old(timer)=0, C_1_ev=1, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, kernel_st=4, max_loop=2, num=2, P_1_ev=1, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1, tmp=0, tmp___0=0] [L458] CALL activate_threads() VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=2, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=2, \old(timer)=0, C_1_ev=1, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, max_loop=2, num=2, P_1_ev=1, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1] [L365] int tmp ; [L366] int tmp___0 ; [L367] int tmp___1 ; VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=2, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=2, \old(timer)=0, C_1_ev=1, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, max_loop=2, num=2, P_1_ev=1, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1] [L371] CALL, EXPR is_P_1_triggered() VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=2, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=2, \old(timer)=0, C_1_ev=1, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, max_loop=2, num=2, P_1_ev=1, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1] [L104] int __retres1 ; VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=2, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=2, \old(timer)=0, C_1_ev=1, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, max_loop=2, num=2, P_1_ev=1, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1] [L107] COND TRUE (int )P_1_pc == 1 VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=2, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=2, \old(timer)=0, C_1_ev=1, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, max_loop=2, num=2, P_1_ev=1, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1] [L108] COND TRUE (int )P_1_ev == 1 [L109] __retres1 = 1 VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=2, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=2, \old(timer)=0, __retres1=1, C_1_ev=1, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, max_loop=2, num=2, P_1_ev=1, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1] [L119] return (__retres1); VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=2, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=2, \old(timer)=0, \result=1, __retres1=1, C_1_ev=1, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, max_loop=2, num=2, P_1_ev=1, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1] [L371] RET, EXPR is_P_1_triggered() VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=2, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=2, \old(timer)=0, C_1_ev=1, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, is_P_1_triggered()=1, max_loop=2, num=2, P_1_ev=1, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1] [L371] tmp = is_P_1_triggered() [L373] COND TRUE \read(tmp) [L374] P_1_st = 0 VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=2, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=2, \old(timer)=0, C_1_ev=1, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, max_loop=2, num=2, P_1_ev=1, P_1_i=1, P_1_pc=1, P_1_st=0, timer=1, tmp=1] [L379] CALL, EXPR is_C_1_triggered() VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=2, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=2, \old(timer)=0, C_1_ev=1, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, max_loop=2, num=2, P_1_ev=1, P_1_i=1, P_1_pc=1, P_1_st=0, timer=1] [L186] int __retres1 ; VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=2, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=2, \old(timer)=0, C_1_ev=1, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, max_loop=2, num=2, P_1_ev=1, P_1_i=1, P_1_pc=1, P_1_st=0, timer=1] [L189] COND TRUE (int )C_1_pc == 1 VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=2, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=2, \old(timer)=0, C_1_ev=1, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, max_loop=2, num=2, P_1_ev=1, P_1_i=1, P_1_pc=1, P_1_st=0, timer=1] [L190] COND FALSE !((int )e == 1) VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=2, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=2, \old(timer)=0, C_1_ev=1, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, max_loop=2, num=2, P_1_ev=1, P_1_i=1, P_1_pc=1, P_1_st=0, timer=1] [L199] COND FALSE !((int )C_1_pc == 2) VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=2, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=2, \old(timer)=0, C_1_ev=1, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, max_loop=2, num=2, P_1_ev=1, P_1_i=1, P_1_pc=1, P_1_st=0, timer=1] [L209] __retres1 = 0 VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=2, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=2, \old(timer)=0, __retres1=0, C_1_ev=1, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, max_loop=2, num=2, P_1_ev=1, P_1_i=1, P_1_pc=1, P_1_st=0, timer=1] [L211] return (__retres1); VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=2, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=2, \old(timer)=0, \result=0, __retres1=0, C_1_ev=1, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, max_loop=2, num=2, P_1_ev=1, P_1_i=1, P_1_pc=1, P_1_st=0, timer=1] [L379] RET, EXPR is_C_1_triggered() VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=2, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=2, \old(timer)=0, C_1_ev=1, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, is_C_1_triggered()=0, max_loop=2, num=2, P_1_ev=1, P_1_i=1, P_1_pc=1, P_1_st=0, timer=1, tmp=1] [L379] tmp___1 = is_C_1_triggered() [L381] COND FALSE !(\read(tmp___1)) VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=2, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=2, \old(timer)=0, C_1_ev=1, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, max_loop=2, num=2, P_1_ev=1, P_1_i=1, P_1_pc=1, P_1_st=0, timer=1, tmp=1, tmp___1=0] [L458] RET activate_threads() VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=0, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=0, \old(timer)=0, C_1_ev=1, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, kernel_st=4, max_loop=2, num=2, P_1_ev=1, P_1_i=1, P_1_pc=1, P_1_st=0, timer=1, tmp=0, tmp___0=0] [L459] CALL reset_time_events() VAL [\old(C_1_ev)=1, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=0, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=1, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=0, \old(timer)=0, C_1_ev=1, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, max_loop=2, num=2, P_1_ev=1, P_1_i=1, P_1_pc=1, P_1_st=0, timer=1] [L350] COND TRUE (int )P_1_ev == 1 [L351] P_1_ev = 2 VAL [\old(C_1_ev)=1, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=0, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=1, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=0, \old(timer)=0, C_1_ev=1, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, max_loop=2, num=2, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=0, timer=1] [L355] COND TRUE (int )C_1_ev == 1 [L356] C_1_ev = 2 VAL [\old(C_1_ev)=1, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=0, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=1, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=0, \old(timer)=0, C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, max_loop=2, num=2, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=0, timer=1] [L459] RET reset_time_events() VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=0, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=0, \old(timer)=0, C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, kernel_st=4, max_loop=2, num=2, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=0, timer=1, tmp=0, tmp___0=0] [L465] CALL, EXPR stop_simulation() VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=0, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=0, \old(timer)=0, C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, max_loop=2, num=2, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=0, timer=1] [L402] int tmp ; [L403] int __retres2 ; VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=0, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=0, \old(timer)=0, C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, max_loop=2, num=2, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=0, timer=1] [L407] CALL, EXPR exists_runnable_thread() VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=0, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=0, \old(timer)=0, C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, max_loop=2, num=2, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=0, timer=1] [L241] int __retres1 ; VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=0, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=0, \old(timer)=0, C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, max_loop=2, num=2, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=0, timer=1] [L244] COND TRUE (int )P_1_st == 0 [L245] __retres1 = 1 VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=0, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=0, \old(timer)=0, __retres1=1, C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, max_loop=2, num=2, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=0, timer=1] [L258] return (__retres1); VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=0, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=0, \old(timer)=0, \result=1, __retres1=1, C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, max_loop=2, num=2, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=0, timer=1] [L407] RET, EXPR exists_runnable_thread() VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=0, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=0, \old(timer)=0, C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, exists_runnable_thread()=1, i=1, max_loop=2, num=2, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=0, timer=1] [L407] tmp = exists_runnable_thread() [L409] COND TRUE \read(tmp) [L410] __retres2 = 0 VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=0, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=0, \old(timer)=0, __retres2=0, C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, max_loop=2, num=2, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=0, timer=1, tmp=1] [L417] return (__retres2); VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=0, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=0, \old(timer)=0, \result=0, __retres2=0, C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, max_loop=2, num=2, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=0, timer=1, tmp=1] [L465] RET, EXPR stop_simulation() VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=0, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=0, \old(timer)=0, C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, kernel_st=4, max_loop=2, num=2, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=0, stop_simulation()=0, timer=1, tmp=0, tmp___0=0] [L465] tmp___0 = stop_simulation() [L467] COND FALSE !(\read(tmp___0)) VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=0, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=0, \old(timer)=0, C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, kernel_st=4, max_loop=2, num=2, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=0, timer=1, tmp=0, tmp___0=0] [L435] COND TRUE 1 VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=0, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=0, \old(timer)=0, C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, kernel_st=4, max_loop=2, num=2, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=0, timer=1, tmp=0, tmp___0=0] [L438] kernel_st = 1 VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=0, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=0, \old(timer)=0, C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, kernel_st=1, max_loop=2, num=2, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=0, timer=1, tmp=0, tmp___0=0] [L439] CALL eval() VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=1, \old(C_1_st)=2, \old(data_0)=65, \old(data_1)=65, \old(i)=1, \old(max_loop)=0, \old(num)=2, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=1, \old(P_1_st)=0, \old(timer)=1, C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, max_loop=2, num=2, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=0, timer=1] [L262] int tmp ; [L263] int tmp___0 ; [L264] int tmp___1 ; [L265] int tmp___2 ; VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=1, \old(C_1_st)=2, \old(data_0)=65, \old(data_1)=65, \old(i)=1, \old(max_loop)=0, \old(num)=2, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=1, \old(P_1_st)=0, \old(timer)=1, C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, max_loop=2, num=2, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=0, timer=1] [L269] COND TRUE 1 VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=1, \old(C_1_st)=2, \old(data_0)=65, \old(data_1)=65, \old(i)=1, \old(max_loop)=0, \old(num)=2, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=1, \old(P_1_st)=0, \old(timer)=1, C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, max_loop=2, num=2, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=0, timer=1] [L272] CALL, EXPR exists_runnable_thread() VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=1, \old(C_1_st)=2, \old(data_0)=65, \old(data_1)=65, \old(i)=1, \old(max_loop)=0, \old(num)=2, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=1, \old(P_1_st)=0, \old(timer)=1, C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, max_loop=2, num=2, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=0, timer=1] [L241] int __retres1 ; VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=1, \old(C_1_st)=2, \old(data_0)=65, \old(data_1)=65, \old(i)=1, \old(max_loop)=0, \old(num)=2, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=1, \old(P_1_st)=0, \old(timer)=1, C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, max_loop=2, num=2, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=0, timer=1] [L244] COND TRUE (int )P_1_st == 0 [L245] __retres1 = 1 VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=1, \old(C_1_st)=2, \old(data_0)=65, \old(data_1)=65, \old(i)=1, \old(max_loop)=0, \old(num)=2, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=1, \old(P_1_st)=0, \old(timer)=1, __retres1=1, C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, max_loop=2, num=2, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=0, timer=1] [L258] return (__retres1); VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=1, \old(C_1_st)=2, \old(data_0)=65, \old(data_1)=65, \old(i)=1, \old(max_loop)=0, \old(num)=2, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=1, \old(P_1_st)=0, \old(timer)=1, \result=1, __retres1=1, C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, max_loop=2, num=2, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=0, timer=1] [L272] RET, EXPR exists_runnable_thread() VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=1, \old(C_1_st)=2, \old(data_0)=65, \old(data_1)=65, \old(i)=1, \old(max_loop)=0, \old(num)=2, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=1, \old(P_1_st)=0, \old(timer)=1, C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, exists_runnable_thread()=1, i=1, max_loop=2, num=2, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=0, timer=1] [L272] tmp___2 = exists_runnable_thread() [L274] COND TRUE \read(tmp___2) VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=1, \old(C_1_st)=2, \old(data_0)=65, \old(data_1)=65, \old(i)=1, \old(max_loop)=0, \old(num)=2, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=1, \old(P_1_st)=0, \old(timer)=1, C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, max_loop=2, num=2, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=0, timer=1, tmp___2=1] [L279] COND TRUE (int )P_1_st == 0 [L281] tmp = __VERIFIER_nondet_int() [L283] COND TRUE \read(tmp) [L285] P_1_st = 1 VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=1, \old(C_1_st)=2, \old(data_0)=65, \old(data_1)=65, \old(i)=1, \old(max_loop)=0, \old(num)=2, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=1, \old(P_1_st)=0, \old(timer)=1, C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, max_loop=2, num=2, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=1, timer=1, tmp=1, tmp___2=1] [L286] CALL P_1() VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=1, \old(C_1_st)=2, \old(data_0)=65, \old(data_1)=65, \old(i)=1, \old(max_loop)=0, \old(num)=2, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=1, \old(P_1_st)=1, \old(timer)=1, C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, max_loop=2, num=2, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=1, timer=1] [L72] COND FALSE !((int )P_1_pc == 0) VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=1, \old(C_1_st)=2, \old(data_0)=65, \old(data_1)=65, \old(i)=1, \old(max_loop)=0, \old(num)=2, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=1, \old(P_1_st)=1, \old(timer)=1, C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, max_loop=2, num=2, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=1, timer=1] [L75] COND TRUE (int )P_1_pc == 1 VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=1, \old(C_1_st)=2, \old(data_0)=65, \old(data_1)=65, \old(i)=1, \old(max_loop)=0, \old(num)=2, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=1, \old(P_1_st)=1, \old(timer)=1, C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, max_loop=2, num=2, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=1, timer=1] [L83] COND TRUE i < max_loop VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=1, \old(C_1_st)=2, \old(data_0)=65, \old(data_1)=65, \old(i)=1, \old(max_loop)=0, \old(num)=2, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=1, \old(P_1_st)=1, \old(timer)=1, C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, max_loop=2, num=2, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=1, timer=1] [L86] CALL write_data(num, 'A') VAL [\old(c)=65, \old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=1, \old(C_1_st)=2, \old(data_0)=65, \old(data_1)=65, \old(i)=1, \old(i___0)=2, \old(max_loop)=0, \old(num)=2, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=1, \old(P_1_st)=1, \old(timer)=1, C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, max_loop=2, num=2, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=1, timer=1] [L49] COND FALSE !(i___0 == 0) VAL [\old(c)=65, \old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=1, \old(C_1_st)=2, \old(data_0)=65, \old(data_1)=65, \old(i)=1, \old(i___0)=2, \old(max_loop)=0, \old(num)=2, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=1, \old(P_1_st)=1, \old(timer)=1, c=65, C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, i___0=2, max_loop=2, num=2, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=1, timer=1] [L52] COND FALSE !(i___0 == 1) VAL [\old(c)=65, \old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=1, \old(C_1_st)=2, \old(data_0)=65, \old(data_1)=65, \old(i)=1, \old(i___0)=2, \old(max_loop)=0, \old(num)=2, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=1, \old(P_1_st)=1, \old(timer)=1, c=65, C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, i___0=2, max_loop=2, num=2, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=1, timer=1] [L56] CALL error() VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=1, \old(C_1_st)=2, \old(data_0)=65, \old(data_1)=65, \old(i)=1, \old(max_loop)=0, \old(num)=2, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=1, \old(P_1_st)=1, \old(timer)=1, C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, max_loop=2, num=2, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=1, timer=1] [L9] __VERIFIER_error() VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=1, \old(C_1_st)=2, \old(data_0)=65, \old(data_1)=65, \old(i)=1, \old(max_loop)=0, \old(num)=2, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=1, \old(P_1_st)=1, \old(timer)=1, C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, max_loop=2, num=2, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=1, timer=1] - StatisticsResult: Ultimate Automizer benchmark data CFG has 22 procedures, 150 locations, 1 error locations. UNSAFE Result, 24.7s OverallTime, 22 OverallIterations, 10 TraceHistogramMax, 15.5s AutomataDifference, 0.0s DeadEndRemovalTime, 0.0s HoareAnnotationTime, HoareTripleCheckerStatistics: 5707 SDtfs, 9928 SDslu, 8561 SDs, 0 SdLazy, 13178 SolverSat, 4694 SolverUnsat, 0 SolverUnknown, 0 SolverNotchecked, 6.8s Time, PredicateUnifierStatistics: 0 DeclaredPredicates, 2156 GetRequests, 1922 SyntacticMatches, 25 SemanticMatches, 209 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 936 ImplicationChecksByTransitivity, 1.9s Time, 0.0s BasicInterpolantAutomatonTime, BiggestAbstraction: size=10564occurred in iteration=11, traceCheckStatistics: No data available, InterpolantConsolidationStatistics: No data available, PathInvariantsStatistics: No data available, 0/0 InterpolantCoveringCapability, TotalInterpolationStatistics: No data available, 0.0s AbstIntTime, 0 AbstIntIterations, 0 AbstIntStrong, NaN AbsIntWeakeningRatio, NaN AbsIntAvgWeakeningVarsNumRemoved, NaN AbsIntAvgWeakenedConjuncts, 0.0s DumpTime, AutomataMinimizationStatistics: 5.3s AutomataMinimizationTime, 21 MinimizatonAttempts, 10334 StatesRemovedByMinimization, 20 NontrivialMinimizations, HoareAnnotationStatistics: No data available, RefinementEngineStatistics: TraceCheckStatistics: 0.2s SsaConstructionTime, 0.6s SatisfiabilityAnalysisTime, 1.8s InterpolantComputationTime, 5413 NumberOfCodeBlocks, 5413 NumberOfCodeBlocksAsserted, 32 NumberOfCheckSat, 5022 ConstructedInterpolants, 0 QuantifiedInterpolants, 1855027 SizeOfPredicates, 18 NumberOfNonLiveVariables, 7389 ConjunctsInSsa, 82 ConjunctsInUnsatCore, 31 InterpolantComputations, 20 PerfectInterpolantSequences, 3589/3758 InterpolantCoveringCapability, InvariantSynthesisStatistics: No data available, InterpolantConsolidationStatistics: No data available, ReuseStatistics: No data available RESULT: Ultimate proved your program to be incorrect! Received shutdown request...