./Ultimate.py --spec ../../sv-benchmarks/c/properties/unreach-call.prp --file ../../sv-benchmarks/c/psyco/psyco_abp_1_false-unreach-call_false-termination_true-no-overflow.c --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for ERROR reachability Using default analysis Version 0cd3be1d Calling Ultimate with: java -Dosgi.configuration.area=/tmp/vcloud-vcloud-master/worker/working_dir_907111b8-e5c3-4c9a-8b01-db5944a86240/bin-2019/uautomizer/data/config -Xmx12G -Xms1G -jar /tmp/vcloud-vcloud-master/worker/working_dir_907111b8-e5c3-4c9a-8b01-db5944a86240/bin-2019/uautomizer/plugins/org.eclipse.equinox.launcher_1.3.100.v20150511-1540.jar -data @noDefault -ultimatedata /tmp/vcloud-vcloud-master/worker/working_dir_907111b8-e5c3-4c9a-8b01-db5944a86240/bin-2019/uautomizer/data -tc /tmp/vcloud-vcloud-master/worker/working_dir_907111b8-e5c3-4c9a-8b01-db5944a86240/bin-2019/uautomizer/config/AutomizerReach.xml -i ../../sv-benchmarks/c/psyco/psyco_abp_1_false-unreach-call_false-termination_true-no-overflow.c -s /tmp/vcloud-vcloud-master/worker/working_dir_907111b8-e5c3-4c9a-8b01-db5944a86240/bin-2019/uautomizer/config/svcomp-Reach-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud-vcloud-master/worker/working_dir_907111b8-e5c3-4c9a-8b01-db5944a86240/bin-2019/uautomizer --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(G ! call(__VERIFIER_error())) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash 747981090a474d9d2269aea1ffd03eef2ddc8848 ......................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................... Execution finished normally Writing output log to file Ultimate.log Writing human readable error path to file UltimateCounterExample.errorpath Result: FALSE --- Real Ultimate output --- This is Ultimate 0.1.23-0cd3be1 [2018-11-28 12:12:29,955 INFO L170 SettingsManager]: Resetting all preferences to default values... [2018-11-28 12:12:29,956 INFO L174 SettingsManager]: Resetting UltimateCore preferences to default values [2018-11-28 12:12:29,963 INFO L177 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2018-11-28 12:12:29,963 INFO L174 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2018-11-28 12:12:29,963 INFO L174 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2018-11-28 12:12:29,964 INFO L174 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2018-11-28 12:12:29,965 INFO L174 SettingsManager]: Resetting LassoRanker preferences to default values [2018-11-28 12:12:29,966 INFO L174 SettingsManager]: Resetting Reaching Definitions preferences to default values [2018-11-28 12:12:29,967 INFO L174 SettingsManager]: Resetting SyntaxChecker preferences to default values [2018-11-28 12:12:29,967 INFO L177 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2018-11-28 12:12:29,968 INFO L174 SettingsManager]: Resetting LTL2Aut preferences to default values [2018-11-28 12:12:29,968 INFO L174 SettingsManager]: Resetting PEA to Boogie preferences to default values [2018-11-28 12:12:29,969 INFO L174 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2018-11-28 12:12:29,970 INFO L174 SettingsManager]: Resetting ChcToBoogie preferences to default values [2018-11-28 12:12:29,970 INFO L174 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2018-11-28 12:12:29,971 INFO L174 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2018-11-28 12:12:29,972 INFO L174 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2018-11-28 12:12:29,973 INFO L174 SettingsManager]: Resetting CodeCheck preferences to default values [2018-11-28 12:12:29,974 INFO L174 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2018-11-28 12:12:29,975 INFO L174 SettingsManager]: Resetting RCFGBuilder preferences to default values [2018-11-28 12:12:29,976 INFO L174 SettingsManager]: Resetting TraceAbstraction preferences to default values [2018-11-28 12:12:29,977 INFO L177 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2018-11-28 12:12:29,977 INFO L177 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2018-11-28 12:12:29,978 INFO L174 SettingsManager]: Resetting TreeAutomizer preferences to default values [2018-11-28 12:12:29,978 INFO L174 SettingsManager]: Resetting IcfgTransformer preferences to default values [2018-11-28 12:12:29,979 INFO L174 SettingsManager]: Resetting Boogie Printer preferences to default values [2018-11-28 12:12:29,979 INFO L174 SettingsManager]: Resetting ReqPrinter preferences to default values [2018-11-28 12:12:29,980 INFO L174 SettingsManager]: Resetting Witness Printer preferences to default values [2018-11-28 12:12:29,981 INFO L177 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2018-11-28 12:12:29,981 INFO L174 SettingsManager]: Resetting CDTParser preferences to default values [2018-11-28 12:12:29,981 INFO L177 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2018-11-28 12:12:29,981 INFO L177 SettingsManager]: ReqParser provides no preferences, ignoring... [2018-11-28 12:12:29,982 INFO L174 SettingsManager]: Resetting SmtParser preferences to default values [2018-11-28 12:12:29,982 INFO L174 SettingsManager]: Resetting Witness Parser preferences to default values [2018-11-28 12:12:29,983 INFO L181 SettingsManager]: Finished resetting all preferences to default values... [2018-11-28 12:12:29,983 INFO L98 SettingsManager]: Beginning loading settings from /tmp/vcloud-vcloud-master/worker/working_dir_907111b8-e5c3-4c9a-8b01-db5944a86240/bin-2019/uautomizer/config/svcomp-Reach-32bit-Automizer_Default.epf [2018-11-28 12:12:29,992 INFO L110 SettingsManager]: Loading preferences was successful [2018-11-28 12:12:29,993 INFO L112 SettingsManager]: Preferences different from defaults after loading the file: [2018-11-28 12:12:29,993 INFO L131 SettingsManager]: Preferences of Boogie Procedure Inliner differ from their defaults: [2018-11-28 12:12:29,993 INFO L133 SettingsManager]: * ... calls to implemented procedures=ONLY_FOR_CONCURRENT_PROGRAMS [2018-11-28 12:12:29,994 INFO L131 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2018-11-28 12:12:29,994 INFO L133 SettingsManager]: * Create parallel compositions if possible=false [2018-11-28 12:12:29,994 INFO L133 SettingsManager]: * Use SBE=true [2018-11-28 12:12:29,994 INFO L131 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2018-11-28 12:12:29,994 INFO L133 SettingsManager]: * sizeof long=4 [2018-11-28 12:12:29,994 INFO L133 SettingsManager]: * Overapproximate operations on floating types=true [2018-11-28 12:12:29,994 INFO L133 SettingsManager]: * sizeof POINTER=4 [2018-11-28 12:12:29,995 INFO L133 SettingsManager]: * Check division by zero=IGNORE [2018-11-28 12:12:29,995 INFO L133 SettingsManager]: * Pointer to allocated memory at dereference=IGNORE [2018-11-28 12:12:29,995 INFO L133 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=IGNORE [2018-11-28 12:12:29,995 INFO L133 SettingsManager]: * Check array bounds for arrays that are off heap=IGNORE [2018-11-28 12:12:29,995 INFO L133 SettingsManager]: * sizeof long double=12 [2018-11-28 12:12:29,995 INFO L133 SettingsManager]: * Check if freed pointer was valid=false [2018-11-28 12:12:29,995 INFO L133 SettingsManager]: * Use constant arrays=true [2018-11-28 12:12:29,995 INFO L133 SettingsManager]: * Pointer base address is valid at dereference=IGNORE [2018-11-28 12:12:29,996 INFO L131 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2018-11-28 12:12:29,996 INFO L133 SettingsManager]: * Size of a code block=SequenceOfStatements [2018-11-28 12:12:29,996 INFO L133 SettingsManager]: * To the following directory=./dump/ [2018-11-28 12:12:29,996 INFO L133 SettingsManager]: * SMT solver=External_DefaultMode [2018-11-28 12:12:29,996 INFO L133 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2018-11-28 12:12:29,996 INFO L131 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2018-11-28 12:12:29,996 INFO L133 SettingsManager]: * Compute Interpolants along a Counterexample=FPandBP [2018-11-28 12:12:29,996 INFO L133 SettingsManager]: * Positions where we compute the Hoare Annotation=LoopsAndPotentialCycles [2018-11-28 12:12:29,997 INFO L133 SettingsManager]: * Trace refinement strategy=CAMEL [2018-11-28 12:12:29,997 INFO L133 SettingsManager]: * SMT solver=External_ModelsAndUnsatCoreMode [2018-11-28 12:12:29,997 INFO L133 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in [2018-11-28 12:12:29,997 INFO L133 SettingsManager]: * Compute Hoare Annotation of negated interpolant automaton, abstraction and CFG=true Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud-vcloud-master/worker/working_dir_907111b8-e5c3-4c9a-8b01-db5944a86240/bin-2019/uautomizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(G ! call(__VERIFIER_error())) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> 747981090a474d9d2269aea1ffd03eef2ddc8848 [2018-11-28 12:12:30,018 INFO L81 nceAwareModelManager]: Repository-Root is: /tmp [2018-11-28 12:12:30,025 INFO L258 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2018-11-28 12:12:30,027 INFO L214 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2018-11-28 12:12:30,028 INFO L271 PluginConnector]: Initializing CDTParser... [2018-11-28 12:12:30,028 INFO L276 PluginConnector]: CDTParser initialized [2018-11-28 12:12:30,028 INFO L418 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud-vcloud-master/worker/working_dir_907111b8-e5c3-4c9a-8b01-db5944a86240/bin-2019/uautomizer/../../sv-benchmarks/c/psyco/psyco_abp_1_false-unreach-call_false-termination_true-no-overflow.c [2018-11-28 12:12:30,063 INFO L221 CDTParser]: Created temporary CDT project at /tmp/vcloud-vcloud-master/worker/working_dir_907111b8-e5c3-4c9a-8b01-db5944a86240/bin-2019/uautomizer/data/866a2bab9/4c87f86c694448bb8987bf25e9053021/FLAG679bd39b3 [2018-11-28 12:12:30,513 INFO L307 CDTParser]: Found 1 translation units. [2018-11-28 12:12:30,513 INFO L161 CDTParser]: Scanning /tmp/vcloud-vcloud-master/worker/working_dir_907111b8-e5c3-4c9a-8b01-db5944a86240/sv-benchmarks/c/psyco/psyco_abp_1_false-unreach-call_false-termination_true-no-overflow.c [2018-11-28 12:12:30,522 INFO L355 CDTParser]: About to delete temporary CDT project at /tmp/vcloud-vcloud-master/worker/working_dir_907111b8-e5c3-4c9a-8b01-db5944a86240/bin-2019/uautomizer/data/866a2bab9/4c87f86c694448bb8987bf25e9053021/FLAG679bd39b3 [2018-11-28 12:12:30,531 INFO L363 CDTParser]: Successfully deleted /tmp/vcloud-vcloud-master/worker/working_dir_907111b8-e5c3-4c9a-8b01-db5944a86240/bin-2019/uautomizer/data/866a2bab9/4c87f86c694448bb8987bf25e9053021 [2018-11-28 12:12:30,533 INFO L296 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2018-11-28 12:12:30,534 INFO L131 ToolchainWalker]: Walking toolchain with 6 elements. [2018-11-28 12:12:30,535 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2018-11-28 12:12:30,535 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2018-11-28 12:12:30,537 INFO L276 PluginConnector]: CACSL2BoogieTranslator initialized [2018-11-28 12:12:30,538 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 28.11 12:12:30" (1/1) ... [2018-11-28 12:12:30,539 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@14ec1fe4 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 12:12:30, skipping insertion in model container [2018-11-28 12:12:30,539 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 28.11 12:12:30" (1/1) ... [2018-11-28 12:12:30,544 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2018-11-28 12:12:30,569 INFO L176 MainTranslator]: Built tables and reachable declarations [2018-11-28 12:12:30,737 INFO L203 PostProcessor]: Analyzing one entry point: main [2018-11-28 12:12:30,741 INFO L191 MainTranslator]: Completed pre-run [2018-11-28 12:12:30,792 INFO L203 PostProcessor]: Analyzing one entry point: main [2018-11-28 12:12:30,842 INFO L195 MainTranslator]: Completed translation [2018-11-28 12:12:30,842 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 12:12:30 WrapperNode [2018-11-28 12:12:30,842 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2018-11-28 12:12:30,843 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2018-11-28 12:12:30,843 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2018-11-28 12:12:30,843 INFO L276 PluginConnector]: Boogie Procedure Inliner initialized [2018-11-28 12:12:30,848 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 12:12:30" (1/1) ... [2018-11-28 12:12:30,854 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 12:12:30" (1/1) ... [2018-11-28 12:12:30,858 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2018-11-28 12:12:30,859 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2018-11-28 12:12:30,859 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2018-11-28 12:12:30,859 INFO L276 PluginConnector]: Boogie Preprocessor initialized [2018-11-28 12:12:30,867 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 12:12:30" (1/1) ... [2018-11-28 12:12:30,867 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 12:12:30" (1/1) ... [2018-11-28 12:12:30,869 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 12:12:30" (1/1) ... [2018-11-28 12:12:30,869 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 12:12:30" (1/1) ... [2018-11-28 12:12:30,882 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 12:12:30" (1/1) ... [2018-11-28 12:12:30,888 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 12:12:30" (1/1) ... [2018-11-28 12:12:30,890 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 12:12:30" (1/1) ... [2018-11-28 12:12:30,893 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2018-11-28 12:12:30,894 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2018-11-28 12:12:30,894 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2018-11-28 12:12:30,894 INFO L276 PluginConnector]: RCFGBuilder initialized [2018-11-28 12:12:30,895 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 12:12:30" (1/1) ... No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_907111b8-e5c3-4c9a-8b01-db5944a86240/bin-2019/uautomizer/z3 Starting monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2018-11-28 12:12:30,935 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.init [2018-11-28 12:12:30,935 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.init [2018-11-28 12:12:30,935 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2018-11-28 12:12:30,935 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2018-11-28 12:12:30,935 INFO L130 BoogieDeclarations]: Found specification of procedure main [2018-11-28 12:12:30,936 INFO L138 BoogieDeclarations]: Found implementation of procedure main [2018-11-28 12:12:31,483 INFO L275 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2018-11-28 12:12:31,483 INFO L280 CfgBuilder]: Removed 2 assue(true) statements. [2018-11-28 12:12:31,484 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 28.11 12:12:31 BoogieIcfgContainer [2018-11-28 12:12:31,484 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2018-11-28 12:12:31,485 INFO L113 PluginConnector]: ------------------------TraceAbstraction---------------------------- [2018-11-28 12:12:31,485 INFO L271 PluginConnector]: Initializing TraceAbstraction... [2018-11-28 12:12:31,487 INFO L276 PluginConnector]: TraceAbstraction initialized [2018-11-28 12:12:31,487 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "CDTParser AST 28.11 12:12:30" (1/3) ... [2018-11-28 12:12:31,487 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@13170332 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 28.11 12:12:31, skipping insertion in model container [2018-11-28 12:12:31,488 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 12:12:30" (2/3) ... [2018-11-28 12:12:31,488 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@13170332 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 28.11 12:12:31, skipping insertion in model container [2018-11-28 12:12:31,488 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 28.11 12:12:31" (3/3) ... [2018-11-28 12:12:31,489 INFO L112 eAbstractionObserver]: Analyzing ICFG psyco_abp_1_false-unreach-call_false-termination_true-no-overflow.c [2018-11-28 12:12:31,495 INFO L156 ceAbstractionStarter]: Automizer settings: Hoare:true NWA Interpolation:FPandBP Determinization: PREDICATE_ABSTRACTION [2018-11-28 12:12:31,502 INFO L168 ceAbstractionStarter]: Appying trace abstraction to program that has 1 error locations. [2018-11-28 12:12:31,512 INFO L257 AbstractCegarLoop]: Starting to check reachability of 1 error locations. [2018-11-28 12:12:31,532 INFO L133 ementStrategyFactory]: Using default assertion order modulation [2018-11-28 12:12:31,533 INFO L382 AbstractCegarLoop]: Interprodecural is true [2018-11-28 12:12:31,533 INFO L383 AbstractCegarLoop]: Hoare is true [2018-11-28 12:12:31,533 INFO L384 AbstractCegarLoop]: Compute interpolants for FPandBP [2018-11-28 12:12:31,533 INFO L385 AbstractCegarLoop]: Backedges is STRAIGHT_LINE [2018-11-28 12:12:31,533 INFO L386 AbstractCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2018-11-28 12:12:31,533 INFO L387 AbstractCegarLoop]: Difference is false [2018-11-28 12:12:31,533 INFO L388 AbstractCegarLoop]: Minimize is MINIMIZE_SEVPA [2018-11-28 12:12:31,534 INFO L393 AbstractCegarLoop]: ======== Iteration 0==of CEGAR loop == AllErrorsAtOnce======== [2018-11-28 12:12:31,548 INFO L276 IsEmpty]: Start isEmpty. Operand 115 states. [2018-11-28 12:12:31,551 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 15 [2018-11-28 12:12:31,552 INFO L394 BasicCegarLoop]: Found error trace [2018-11-28 12:12:31,552 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-28 12:12:31,554 INFO L423 AbstractCegarLoop]: === Iteration 1 === [mainErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-28 12:12:31,557 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-28 12:12:31,558 INFO L82 PathProgramCache]: Analyzing trace with hash 919157391, now seen corresponding path program 1 times [2018-11-28 12:12:31,559 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-28 12:12:31,559 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-28 12:12:31,591 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 12:12:31,591 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-28 12:12:31,591 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 12:12:31,621 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-28 12:12:31,667 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-28 12:12:31,669 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-28 12:12:31,669 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-28 12:12:31,672 INFO L459 AbstractCegarLoop]: Interpolant automaton has 3 states [2018-11-28 12:12:31,679 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-28 12:12:31,679 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-28 12:12:31,681 INFO L87 Difference]: Start difference. First operand 115 states. Second operand 3 states. [2018-11-28 12:12:31,900 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-28 12:12:31,900 INFO L93 Difference]: Finished difference Result 331 states and 635 transitions. [2018-11-28 12:12:31,901 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-28 12:12:31,901 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 14 [2018-11-28 12:12:31,902 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-28 12:12:31,909 INFO L225 Difference]: With dead ends: 331 [2018-11-28 12:12:31,909 INFO L226 Difference]: Without dead ends: 206 [2018-11-28 12:12:31,912 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-28 12:12:31,924 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 206 states. [2018-11-28 12:12:31,941 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 206 to 182. [2018-11-28 12:12:31,942 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 182 states. [2018-11-28 12:12:31,944 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 182 states to 182 states and 314 transitions. [2018-11-28 12:12:31,945 INFO L78 Accepts]: Start accepts. Automaton has 182 states and 314 transitions. Word has length 14 [2018-11-28 12:12:31,945 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-28 12:12:31,945 INFO L480 AbstractCegarLoop]: Abstraction has 182 states and 314 transitions. [2018-11-28 12:12:31,945 INFO L481 AbstractCegarLoop]: Interpolant automaton has 3 states. [2018-11-28 12:12:31,945 INFO L276 IsEmpty]: Start isEmpty. Operand 182 states and 314 transitions. [2018-11-28 12:12:31,946 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 16 [2018-11-28 12:12:31,946 INFO L394 BasicCegarLoop]: Found error trace [2018-11-28 12:12:31,946 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-28 12:12:31,946 INFO L423 AbstractCegarLoop]: === Iteration 2 === [mainErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-28 12:12:31,946 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-28 12:12:31,946 INFO L82 PathProgramCache]: Analyzing trace with hash 736602936, now seen corresponding path program 1 times [2018-11-28 12:12:31,946 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-28 12:12:31,947 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-28 12:12:31,947 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 12:12:31,947 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-28 12:12:31,948 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 12:12:31,958 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-28 12:12:31,979 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-28 12:12:31,979 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-28 12:12:31,979 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-28 12:12:31,981 INFO L459 AbstractCegarLoop]: Interpolant automaton has 3 states [2018-11-28 12:12:31,981 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-28 12:12:31,981 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-28 12:12:31,981 INFO L87 Difference]: Start difference. First operand 182 states and 314 transitions. Second operand 3 states. [2018-11-28 12:12:32,016 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-28 12:12:32,016 INFO L93 Difference]: Finished difference Result 365 states and 632 transitions. [2018-11-28 12:12:32,016 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-28 12:12:32,016 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 15 [2018-11-28 12:12:32,017 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-28 12:12:32,017 INFO L225 Difference]: With dead ends: 365 [2018-11-28 12:12:32,017 INFO L226 Difference]: Without dead ends: 189 [2018-11-28 12:12:32,018 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-28 12:12:32,019 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 189 states. [2018-11-28 12:12:32,024 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 189 to 189. [2018-11-28 12:12:32,024 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 189 states. [2018-11-28 12:12:32,026 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 189 states to 189 states and 322 transitions. [2018-11-28 12:12:32,026 INFO L78 Accepts]: Start accepts. Automaton has 189 states and 322 transitions. Word has length 15 [2018-11-28 12:12:32,026 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-28 12:12:32,026 INFO L480 AbstractCegarLoop]: Abstraction has 189 states and 322 transitions. [2018-11-28 12:12:32,026 INFO L481 AbstractCegarLoop]: Interpolant automaton has 3 states. [2018-11-28 12:12:32,027 INFO L276 IsEmpty]: Start isEmpty. Operand 189 states and 322 transitions. [2018-11-28 12:12:32,027 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 22 [2018-11-28 12:12:32,027 INFO L394 BasicCegarLoop]: Found error trace [2018-11-28 12:12:32,027 INFO L402 BasicCegarLoop]: trace histogram [2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-28 12:12:32,027 INFO L423 AbstractCegarLoop]: === Iteration 3 === [mainErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-28 12:12:32,028 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-28 12:12:32,028 INFO L82 PathProgramCache]: Analyzing trace with hash 816788357, now seen corresponding path program 1 times [2018-11-28 12:12:32,028 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-28 12:12:32,028 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-28 12:12:32,029 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 12:12:32,029 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-28 12:12:32,029 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 12:12:32,063 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-28 12:12:32,206 INFO L134 CoverageAnalysis]: Checked inductivity of 3 backedges. 3 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-28 12:12:32,207 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-28 12:12:32,207 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2018-11-28 12:12:32,207 INFO L459 AbstractCegarLoop]: Interpolant automaton has 4 states [2018-11-28 12:12:32,207 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2018-11-28 12:12:32,208 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=6, Invalid=6, Unknown=0, NotChecked=0, Total=12 [2018-11-28 12:12:32,208 INFO L87 Difference]: Start difference. First operand 189 states and 322 transitions. Second operand 4 states. [2018-11-28 12:12:32,371 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-28 12:12:32,371 INFO L93 Difference]: Finished difference Result 290 states and 484 transitions. [2018-11-28 12:12:32,371 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-28 12:12:32,372 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 21 [2018-11-28 12:12:32,372 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-28 12:12:32,373 INFO L225 Difference]: With dead ends: 290 [2018-11-28 12:12:32,373 INFO L226 Difference]: Without dead ends: 274 [2018-11-28 12:12:32,374 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 5 GetRequests, 2 SyntacticMatches, 1 SemanticMatches, 2 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=6, Invalid=6, Unknown=0, NotChecked=0, Total=12 [2018-11-28 12:12:32,375 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 274 states. [2018-11-28 12:12:32,385 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 274 to 259. [2018-11-28 12:12:32,385 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 259 states. [2018-11-28 12:12:32,386 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 259 states to 259 states and 436 transitions. [2018-11-28 12:12:32,387 INFO L78 Accepts]: Start accepts. Automaton has 259 states and 436 transitions. Word has length 21 [2018-11-28 12:12:32,387 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-28 12:12:32,387 INFO L480 AbstractCegarLoop]: Abstraction has 259 states and 436 transitions. [2018-11-28 12:12:32,387 INFO L481 AbstractCegarLoop]: Interpolant automaton has 4 states. [2018-11-28 12:12:32,387 INFO L276 IsEmpty]: Start isEmpty. Operand 259 states and 436 transitions. [2018-11-28 12:12:32,388 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 23 [2018-11-28 12:12:32,388 INFO L394 BasicCegarLoop]: Found error trace [2018-11-28 12:12:32,388 INFO L402 BasicCegarLoop]: trace histogram [2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-28 12:12:32,388 INFO L423 AbstractCegarLoop]: === Iteration 4 === [mainErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-28 12:12:32,388 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-28 12:12:32,389 INFO L82 PathProgramCache]: Analyzing trace with hash -1993084704, now seen corresponding path program 1 times [2018-11-28 12:12:32,389 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-28 12:12:32,389 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-28 12:12:32,390 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 12:12:32,390 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-28 12:12:32,390 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 12:12:32,402 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-28 12:12:32,423 INFO L134 CoverageAnalysis]: Checked inductivity of 3 backedges. 3 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-28 12:12:32,423 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-28 12:12:32,423 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-28 12:12:32,424 INFO L459 AbstractCegarLoop]: Interpolant automaton has 3 states [2018-11-28 12:12:32,424 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-28 12:12:32,424 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-28 12:12:32,424 INFO L87 Difference]: Start difference. First operand 259 states and 436 transitions. Second operand 3 states. [2018-11-28 12:12:32,454 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-28 12:12:32,454 INFO L93 Difference]: Finished difference Result 468 states and 791 transitions. [2018-11-28 12:12:32,454 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-28 12:12:32,454 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 22 [2018-11-28 12:12:32,455 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-28 12:12:32,456 INFO L225 Difference]: With dead ends: 468 [2018-11-28 12:12:32,456 INFO L226 Difference]: Without dead ends: 216 [2018-11-28 12:12:32,457 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-28 12:12:32,457 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 216 states. [2018-11-28 12:12:32,464 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 216 to 214. [2018-11-28 12:12:32,464 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 214 states. [2018-11-28 12:12:32,465 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 214 states to 214 states and 355 transitions. [2018-11-28 12:12:32,465 INFO L78 Accepts]: Start accepts. Automaton has 214 states and 355 transitions. Word has length 22 [2018-11-28 12:12:32,466 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-28 12:12:32,466 INFO L480 AbstractCegarLoop]: Abstraction has 214 states and 355 transitions. [2018-11-28 12:12:32,466 INFO L481 AbstractCegarLoop]: Interpolant automaton has 3 states. [2018-11-28 12:12:32,466 INFO L276 IsEmpty]: Start isEmpty. Operand 214 states and 355 transitions. [2018-11-28 12:12:32,467 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 29 [2018-11-28 12:12:32,467 INFO L394 BasicCegarLoop]: Found error trace [2018-11-28 12:12:32,467 INFO L402 BasicCegarLoop]: trace histogram [3, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-28 12:12:32,467 INFO L423 AbstractCegarLoop]: === Iteration 5 === [mainErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-28 12:12:32,467 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-28 12:12:32,468 INFO L82 PathProgramCache]: Analyzing trace with hash -365898165, now seen corresponding path program 1 times [2018-11-28 12:12:32,468 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-28 12:12:32,468 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-28 12:12:32,468 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 12:12:32,469 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-28 12:12:32,469 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 12:12:32,480 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-28 12:12:32,515 INFO L134 CoverageAnalysis]: Checked inductivity of 13 backedges. 11 proven. 2 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-28 12:12:32,516 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-28 12:12:32,516 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_907111b8-e5c3-4c9a-8b01-db5944a86240/bin-2019/uautomizer/z3 Starting monitored process 2 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 2 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-28 12:12:32,528 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-28 12:12:32,552 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-28 12:12:32,557 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-28 12:12:32,575 INFO L134 CoverageAnalysis]: Checked inductivity of 13 backedges. 10 proven. 0 refuted. 0 times theorem prover too weak. 3 trivial. 0 not checked. [2018-11-28 12:12:32,589 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 1 imperfect interpolant sequences. [2018-11-28 12:12:32,589 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [4] total 5 [2018-11-28 12:12:32,589 INFO L459 AbstractCegarLoop]: Interpolant automaton has 5 states [2018-11-28 12:12:32,590 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-11-28 12:12:32,590 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=8, Invalid=12, Unknown=0, NotChecked=0, Total=20 [2018-11-28 12:12:32,590 INFO L87 Difference]: Start difference. First operand 214 states and 355 transitions. Second operand 5 states. [2018-11-28 12:12:32,784 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-28 12:12:32,784 INFO L93 Difference]: Finished difference Result 498 states and 813 transitions. [2018-11-28 12:12:32,785 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2018-11-28 12:12:32,785 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 28 [2018-11-28 12:12:32,785 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-28 12:12:32,786 INFO L225 Difference]: With dead ends: 498 [2018-11-28 12:12:32,786 INFO L226 Difference]: Without dead ends: 288 [2018-11-28 12:12:32,787 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 35 GetRequests, 30 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=18, Invalid=24, Unknown=0, NotChecked=0, Total=42 [2018-11-28 12:12:32,787 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 288 states. [2018-11-28 12:12:32,794 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 288 to 245. [2018-11-28 12:12:32,794 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 245 states. [2018-11-28 12:12:32,795 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 245 states to 245 states and 408 transitions. [2018-11-28 12:12:32,795 INFO L78 Accepts]: Start accepts. Automaton has 245 states and 408 transitions. Word has length 28 [2018-11-28 12:12:32,795 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-28 12:12:32,796 INFO L480 AbstractCegarLoop]: Abstraction has 245 states and 408 transitions. [2018-11-28 12:12:32,796 INFO L481 AbstractCegarLoop]: Interpolant automaton has 5 states. [2018-11-28 12:12:32,796 INFO L276 IsEmpty]: Start isEmpty. Operand 245 states and 408 transitions. [2018-11-28 12:12:32,796 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 31 [2018-11-28 12:12:32,796 INFO L394 BasicCegarLoop]: Found error trace [2018-11-28 12:12:32,796 INFO L402 BasicCegarLoop]: trace histogram [3, 3, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-28 12:12:32,797 INFO L423 AbstractCegarLoop]: === Iteration 6 === [mainErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-28 12:12:32,797 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-28 12:12:32,797 INFO L82 PathProgramCache]: Analyzing trace with hash -944739986, now seen corresponding path program 1 times [2018-11-28 12:12:32,797 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-28 12:12:32,797 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-28 12:12:32,798 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 12:12:32,798 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-28 12:12:32,798 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 12:12:32,810 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-28 12:12:32,837 INFO L134 CoverageAnalysis]: Checked inductivity of 10 backedges. 6 proven. 4 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-28 12:12:32,838 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-28 12:12:32,838 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_907111b8-e5c3-4c9a-8b01-db5944a86240/bin-2019/uautomizer/z3 Starting monitored process 3 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 3 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-28 12:12:32,867 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-28 12:12:32,892 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-28 12:12:32,894 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-28 12:12:32,900 INFO L134 CoverageAnalysis]: Checked inductivity of 10 backedges. 6 proven. 4 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-28 12:12:32,919 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-11-28 12:12:32,919 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [4, 4] total 5 [2018-11-28 12:12:32,919 INFO L459 AbstractCegarLoop]: Interpolant automaton has 5 states [2018-11-28 12:12:32,920 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-11-28 12:12:32,920 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=8, Invalid=12, Unknown=0, NotChecked=0, Total=20 [2018-11-28 12:12:32,920 INFO L87 Difference]: Start difference. First operand 245 states and 408 transitions. Second operand 5 states. [2018-11-28 12:12:33,017 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-28 12:12:33,017 INFO L93 Difference]: Finished difference Result 464 states and 780 transitions. [2018-11-28 12:12:33,017 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2018-11-28 12:12:33,018 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 30 [2018-11-28 12:12:33,018 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-28 12:12:33,019 INFO L225 Difference]: With dead ends: 464 [2018-11-28 12:12:33,019 INFO L226 Difference]: Without dead ends: 452 [2018-11-28 12:12:33,019 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 33 GetRequests, 30 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=8, Invalid=12, Unknown=0, NotChecked=0, Total=20 [2018-11-28 12:12:33,020 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 452 states. [2018-11-28 12:12:33,028 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 452 to 438. [2018-11-28 12:12:33,028 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 438 states. [2018-11-28 12:12:33,029 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 438 states to 438 states and 730 transitions. [2018-11-28 12:12:33,029 INFO L78 Accepts]: Start accepts. Automaton has 438 states and 730 transitions. Word has length 30 [2018-11-28 12:12:33,030 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-28 12:12:33,030 INFO L480 AbstractCegarLoop]: Abstraction has 438 states and 730 transitions. [2018-11-28 12:12:33,030 INFO L481 AbstractCegarLoop]: Interpolant automaton has 5 states. [2018-11-28 12:12:33,030 INFO L276 IsEmpty]: Start isEmpty. Operand 438 states and 730 transitions. [2018-11-28 12:12:33,030 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 32 [2018-11-28 12:12:33,031 INFO L394 BasicCegarLoop]: Found error trace [2018-11-28 12:12:33,031 INFO L402 BasicCegarLoop]: trace histogram [3, 3, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-28 12:12:33,031 INFO L423 AbstractCegarLoop]: === Iteration 7 === [mainErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-28 12:12:33,031 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-28 12:12:33,031 INFO L82 PathProgramCache]: Analyzing trace with hash 789275061, now seen corresponding path program 1 times [2018-11-28 12:12:33,031 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-28 12:12:33,031 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-28 12:12:33,032 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 12:12:33,032 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-28 12:12:33,032 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 12:12:33,044 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-28 12:12:33,121 INFO L134 CoverageAnalysis]: Checked inductivity of 10 backedges. 6 proven. 4 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-28 12:12:33,121 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-28 12:12:33,121 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_907111b8-e5c3-4c9a-8b01-db5944a86240/bin-2019/uautomizer/z3 Starting monitored process 4 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 4 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-28 12:12:33,127 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-28 12:12:33,151 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-28 12:12:33,153 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-28 12:12:33,179 INFO L134 CoverageAnalysis]: Checked inductivity of 10 backedges. 6 proven. 4 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-28 12:12:33,205 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-11-28 12:12:33,205 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [5, 4] total 6 [2018-11-28 12:12:33,205 INFO L459 AbstractCegarLoop]: Interpolant automaton has 6 states [2018-11-28 12:12:33,205 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2018-11-28 12:12:33,205 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=11, Invalid=19, Unknown=0, NotChecked=0, Total=30 [2018-11-28 12:12:33,206 INFO L87 Difference]: Start difference. First operand 438 states and 730 transitions. Second operand 6 states. [2018-11-28 12:12:33,294 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-28 12:12:33,294 INFO L93 Difference]: Finished difference Result 495 states and 817 transitions. [2018-11-28 12:12:33,294 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2018-11-28 12:12:33,294 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 31 [2018-11-28 12:12:33,294 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-28 12:12:33,295 INFO L225 Difference]: With dead ends: 495 [2018-11-28 12:12:33,296 INFO L226 Difference]: Without dead ends: 490 [2018-11-28 12:12:33,296 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 35 GetRequests, 30 SyntacticMatches, 1 SemanticMatches, 4 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 3 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=11, Invalid=19, Unknown=0, NotChecked=0, Total=30 [2018-11-28 12:12:33,296 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 490 states. [2018-11-28 12:12:33,302 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 490 to 484. [2018-11-28 12:12:33,302 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 484 states. [2018-11-28 12:12:33,303 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 484 states to 484 states and 802 transitions. [2018-11-28 12:12:33,304 INFO L78 Accepts]: Start accepts. Automaton has 484 states and 802 transitions. Word has length 31 [2018-11-28 12:12:33,304 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-28 12:12:33,304 INFO L480 AbstractCegarLoop]: Abstraction has 484 states and 802 transitions. [2018-11-28 12:12:33,304 INFO L481 AbstractCegarLoop]: Interpolant automaton has 6 states. [2018-11-28 12:12:33,304 INFO L276 IsEmpty]: Start isEmpty. Operand 484 states and 802 transitions. [2018-11-28 12:12:33,305 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 33 [2018-11-28 12:12:33,305 INFO L394 BasicCegarLoop]: Found error trace [2018-11-28 12:12:33,305 INFO L402 BasicCegarLoop]: trace histogram [3, 3, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-28 12:12:33,305 INFO L423 AbstractCegarLoop]: === Iteration 8 === [mainErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-28 12:12:33,305 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-28 12:12:33,305 INFO L82 PathProgramCache]: Analyzing trace with hash 2038890699, now seen corresponding path program 1 times [2018-11-28 12:12:33,305 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-28 12:12:33,306 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-28 12:12:33,306 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 12:12:33,306 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-28 12:12:33,306 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 12:12:33,313 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-28 12:12:33,327 INFO L134 CoverageAnalysis]: Checked inductivity of 10 backedges. 7 proven. 0 refuted. 0 times theorem prover too weak. 3 trivial. 0 not checked. [2018-11-28 12:12:33,327 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-28 12:12:33,327 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-28 12:12:33,327 INFO L459 AbstractCegarLoop]: Interpolant automaton has 3 states [2018-11-28 12:12:33,327 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-28 12:12:33,327 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-28 12:12:33,328 INFO L87 Difference]: Start difference. First operand 484 states and 802 transitions. Second operand 3 states. [2018-11-28 12:12:33,346 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-28 12:12:33,346 INFO L93 Difference]: Finished difference Result 949 states and 1566 transitions. [2018-11-28 12:12:33,347 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-28 12:12:33,347 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 32 [2018-11-28 12:12:33,347 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-28 12:12:33,348 INFO L225 Difference]: With dead ends: 949 [2018-11-28 12:12:33,348 INFO L226 Difference]: Without dead ends: 495 [2018-11-28 12:12:33,349 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-28 12:12:33,349 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 495 states. [2018-11-28 12:12:33,354 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 495 to 493. [2018-11-28 12:12:33,355 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 493 states. [2018-11-28 12:12:33,356 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 493 states to 493 states and 794 transitions. [2018-11-28 12:12:33,356 INFO L78 Accepts]: Start accepts. Automaton has 493 states and 794 transitions. Word has length 32 [2018-11-28 12:12:33,356 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-28 12:12:33,356 INFO L480 AbstractCegarLoop]: Abstraction has 493 states and 794 transitions. [2018-11-28 12:12:33,356 INFO L481 AbstractCegarLoop]: Interpolant automaton has 3 states. [2018-11-28 12:12:33,357 INFO L276 IsEmpty]: Start isEmpty. Operand 493 states and 794 transitions. [2018-11-28 12:12:33,357 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 41 [2018-11-28 12:12:33,357 INFO L394 BasicCegarLoop]: Found error trace [2018-11-28 12:12:33,357 INFO L402 BasicCegarLoop]: trace histogram [4, 4, 3, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-28 12:12:33,358 INFO L423 AbstractCegarLoop]: === Iteration 9 === [mainErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-28 12:12:33,358 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-28 12:12:33,358 INFO L82 PathProgramCache]: Analyzing trace with hash 820851006, now seen corresponding path program 1 times [2018-11-28 12:12:33,358 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-28 12:12:33,358 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-28 12:12:33,359 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 12:12:33,359 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-28 12:12:33,359 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 12:12:33,367 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-28 12:12:33,380 INFO L134 CoverageAnalysis]: Checked inductivity of 24 backedges. 14 proven. 0 refuted. 0 times theorem prover too weak. 10 trivial. 0 not checked. [2018-11-28 12:12:33,380 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-28 12:12:33,380 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-28 12:12:33,381 INFO L459 AbstractCegarLoop]: Interpolant automaton has 3 states [2018-11-28 12:12:33,381 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-28 12:12:33,381 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-28 12:12:33,381 INFO L87 Difference]: Start difference. First operand 493 states and 794 transitions. Second operand 3 states. [2018-11-28 12:12:33,399 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-28 12:12:33,399 INFO L93 Difference]: Finished difference Result 939 states and 1525 transitions. [2018-11-28 12:12:33,400 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-28 12:12:33,400 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 40 [2018-11-28 12:12:33,400 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-28 12:12:33,401 INFO L225 Difference]: With dead ends: 939 [2018-11-28 12:12:33,401 INFO L226 Difference]: Without dead ends: 495 [2018-11-28 12:12:33,402 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-28 12:12:33,402 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 495 states. [2018-11-28 12:12:33,408 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 495 to 493. [2018-11-28 12:12:33,408 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 493 states. [2018-11-28 12:12:33,410 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 493 states to 493 states and 788 transitions. [2018-11-28 12:12:33,410 INFO L78 Accepts]: Start accepts. Automaton has 493 states and 788 transitions. Word has length 40 [2018-11-28 12:12:33,410 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-28 12:12:33,410 INFO L480 AbstractCegarLoop]: Abstraction has 493 states and 788 transitions. [2018-11-28 12:12:33,410 INFO L481 AbstractCegarLoop]: Interpolant automaton has 3 states. [2018-11-28 12:12:33,410 INFO L276 IsEmpty]: Start isEmpty. Operand 493 states and 788 transitions. [2018-11-28 12:12:33,411 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 42 [2018-11-28 12:12:33,411 INFO L394 BasicCegarLoop]: Found error trace [2018-11-28 12:12:33,411 INFO L402 BasicCegarLoop]: trace histogram [4, 4, 3, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-28 12:12:33,411 INFO L423 AbstractCegarLoop]: === Iteration 10 === [mainErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-28 12:12:33,411 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-28 12:12:33,411 INFO L82 PathProgramCache]: Analyzing trace with hash -1867136664, now seen corresponding path program 1 times [2018-11-28 12:12:33,412 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-28 12:12:33,412 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-28 12:12:33,412 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 12:12:33,412 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-28 12:12:33,412 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 12:12:33,421 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-28 12:12:33,517 INFO L134 CoverageAnalysis]: Checked inductivity of 23 backedges. 9 proven. 14 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-28 12:12:33,518 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-28 12:12:33,518 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_907111b8-e5c3-4c9a-8b01-db5944a86240/bin-2019/uautomizer/z3 Starting monitored process 5 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 5 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-28 12:12:33,530 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-28 12:12:33,565 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-28 12:12:33,567 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-28 12:12:33,603 INFO L134 CoverageAnalysis]: Checked inductivity of 23 backedges. 9 proven. 8 refuted. 0 times theorem prover too weak. 6 trivial. 0 not checked. [2018-11-28 12:12:33,617 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-11-28 12:12:33,617 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [7, 5] total 8 [2018-11-28 12:12:33,618 INFO L459 AbstractCegarLoop]: Interpolant automaton has 8 states [2018-11-28 12:12:33,618 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 8 interpolants. [2018-11-28 12:12:33,618 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=19, Invalid=37, Unknown=0, NotChecked=0, Total=56 [2018-11-28 12:12:33,618 INFO L87 Difference]: Start difference. First operand 493 states and 788 transitions. Second operand 8 states. [2018-11-28 12:12:33,991 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-28 12:12:33,991 INFO L93 Difference]: Finished difference Result 1031 states and 1639 transitions. [2018-11-28 12:12:33,992 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2018-11-28 12:12:33,992 INFO L78 Accepts]: Start accepts. Automaton has 8 states. Word has length 41 [2018-11-28 12:12:33,992 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-28 12:12:33,994 INFO L225 Difference]: With dead ends: 1031 [2018-11-28 12:12:33,994 INFO L226 Difference]: Without dead ends: 580 [2018-11-28 12:12:33,994 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 51 GetRequests, 41 SyntacticMatches, 1 SemanticMatches, 9 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 13 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=37, Invalid=73, Unknown=0, NotChecked=0, Total=110 [2018-11-28 12:12:33,995 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 580 states. [2018-11-28 12:12:34,008 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 580 to 544. [2018-11-28 12:12:34,008 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 544 states. [2018-11-28 12:12:34,010 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 544 states to 544 states and 867 transitions. [2018-11-28 12:12:34,010 INFO L78 Accepts]: Start accepts. Automaton has 544 states and 867 transitions. Word has length 41 [2018-11-28 12:12:34,010 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-28 12:12:34,011 INFO L480 AbstractCegarLoop]: Abstraction has 544 states and 867 transitions. [2018-11-28 12:12:34,011 INFO L481 AbstractCegarLoop]: Interpolant automaton has 8 states. [2018-11-28 12:12:34,011 INFO L276 IsEmpty]: Start isEmpty. Operand 544 states and 867 transitions. [2018-11-28 12:12:34,011 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 43 [2018-11-28 12:12:34,011 INFO L394 BasicCegarLoop]: Found error trace [2018-11-28 12:12:34,011 INFO L402 BasicCegarLoop]: trace histogram [4, 4, 3, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-28 12:12:34,011 INFO L423 AbstractCegarLoop]: === Iteration 11 === [mainErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-28 12:12:34,012 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-28 12:12:34,012 INFO L82 PathProgramCache]: Analyzing trace with hash -2035215205, now seen corresponding path program 1 times [2018-11-28 12:12:34,012 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-28 12:12:34,012 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-28 12:12:34,012 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 12:12:34,013 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-28 12:12:34,013 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 12:12:34,022 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-28 12:12:34,048 INFO L134 CoverageAnalysis]: Checked inductivity of 23 backedges. 9 proven. 10 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2018-11-28 12:12:34,049 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-28 12:12:34,049 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_907111b8-e5c3-4c9a-8b01-db5944a86240/bin-2019/uautomizer/z3 Starting monitored process 6 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 6 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-28 12:12:34,057 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-28 12:12:34,104 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-28 12:12:34,106 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-28 12:12:34,120 INFO L134 CoverageAnalysis]: Checked inductivity of 23 backedges. 9 proven. 10 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2018-11-28 12:12:34,144 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-11-28 12:12:34,144 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [4, 4] total 4 [2018-11-28 12:12:34,145 INFO L459 AbstractCegarLoop]: Interpolant automaton has 4 states [2018-11-28 12:12:34,145 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2018-11-28 12:12:34,145 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2018-11-28 12:12:34,145 INFO L87 Difference]: Start difference. First operand 544 states and 867 transitions. Second operand 4 states. [2018-11-28 12:12:34,227 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-28 12:12:34,227 INFO L93 Difference]: Finished difference Result 558 states and 879 transitions. [2018-11-28 12:12:34,227 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2018-11-28 12:12:34,227 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 42 [2018-11-28 12:12:34,228 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-28 12:12:34,229 INFO L225 Difference]: With dead ends: 558 [2018-11-28 12:12:34,229 INFO L226 Difference]: Without dead ends: 546 [2018-11-28 12:12:34,230 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 46 GetRequests, 41 SyntacticMatches, 3 SemanticMatches, 2 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2018-11-28 12:12:34,230 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 546 states. [2018-11-28 12:12:34,242 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 546 to 544. [2018-11-28 12:12:34,242 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 544 states. [2018-11-28 12:12:34,244 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 544 states to 544 states and 841 transitions. [2018-11-28 12:12:34,244 INFO L78 Accepts]: Start accepts. Automaton has 544 states and 841 transitions. Word has length 42 [2018-11-28 12:12:34,244 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-28 12:12:34,244 INFO L480 AbstractCegarLoop]: Abstraction has 544 states and 841 transitions. [2018-11-28 12:12:34,244 INFO L481 AbstractCegarLoop]: Interpolant automaton has 4 states. [2018-11-28 12:12:34,244 INFO L276 IsEmpty]: Start isEmpty. Operand 544 states and 841 transitions. [2018-11-28 12:12:34,244 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 45 [2018-11-28 12:12:34,245 INFO L394 BasicCegarLoop]: Found error trace [2018-11-28 12:12:34,245 INFO L402 BasicCegarLoop]: trace histogram [4, 4, 3, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-28 12:12:34,245 INFO L423 AbstractCegarLoop]: === Iteration 12 === [mainErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-28 12:12:34,245 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-28 12:12:34,247 INFO L82 PathProgramCache]: Analyzing trace with hash -1265387988, now seen corresponding path program 1 times [2018-11-28 12:12:34,247 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-28 12:12:34,247 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-28 12:12:34,248 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 12:12:34,248 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-28 12:12:34,248 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 12:12:34,269 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-28 12:12:34,466 INFO L134 CoverageAnalysis]: Checked inductivity of 23 backedges. 9 proven. 14 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-28 12:12:34,466 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-28 12:12:34,466 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_907111b8-e5c3-4c9a-8b01-db5944a86240/bin-2019/uautomizer/z3 Starting monitored process 7 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 7 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-28 12:12:34,475 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-28 12:12:34,505 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-28 12:12:34,507 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-28 12:12:34,526 INFO L134 CoverageAnalysis]: Checked inductivity of 23 backedges. 9 proven. 14 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-28 12:12:34,551 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-11-28 12:12:34,551 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [7, 5] total 7 [2018-11-28 12:12:34,552 INFO L459 AbstractCegarLoop]: Interpolant automaton has 7 states [2018-11-28 12:12:34,552 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2018-11-28 12:12:34,552 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=14, Invalid=28, Unknown=0, NotChecked=0, Total=42 [2018-11-28 12:12:34,552 INFO L87 Difference]: Start difference. First operand 544 states and 841 transitions. Second operand 7 states. [2018-11-28 12:12:34,767 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-28 12:12:34,767 INFO L93 Difference]: Finished difference Result 555 states and 849 transitions. [2018-11-28 12:12:34,768 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2018-11-28 12:12:34,768 INFO L78 Accepts]: Start accepts. Automaton has 7 states. Word has length 44 [2018-11-28 12:12:34,768 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-28 12:12:34,769 INFO L225 Difference]: With dead ends: 555 [2018-11-28 12:12:34,770 INFO L226 Difference]: Without dead ends: 553 [2018-11-28 12:12:34,770 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 50 GetRequests, 43 SyntacticMatches, 2 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=14, Invalid=28, Unknown=0, NotChecked=0, Total=42 [2018-11-28 12:12:34,770 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 553 states. [2018-11-28 12:12:34,783 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 553 to 545. [2018-11-28 12:12:34,784 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 545 states. [2018-11-28 12:12:34,786 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 545 states to 545 states and 842 transitions. [2018-11-28 12:12:34,787 INFO L78 Accepts]: Start accepts. Automaton has 545 states and 842 transitions. Word has length 44 [2018-11-28 12:12:34,788 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-28 12:12:34,789 INFO L480 AbstractCegarLoop]: Abstraction has 545 states and 842 transitions. [2018-11-28 12:12:34,789 INFO L481 AbstractCegarLoop]: Interpolant automaton has 7 states. [2018-11-28 12:12:34,789 INFO L276 IsEmpty]: Start isEmpty. Operand 545 states and 842 transitions. [2018-11-28 12:12:34,790 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 46 [2018-11-28 12:12:34,790 INFO L394 BasicCegarLoop]: Found error trace [2018-11-28 12:12:34,790 INFO L402 BasicCegarLoop]: trace histogram [4, 4, 3, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-28 12:12:34,790 INFO L423 AbstractCegarLoop]: === Iteration 13 === [mainErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-28 12:12:34,790 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-28 12:12:34,790 INFO L82 PathProgramCache]: Analyzing trace with hash -447084202, now seen corresponding path program 1 times [2018-11-28 12:12:34,790 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-28 12:12:34,790 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-28 12:12:34,791 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 12:12:34,791 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-28 12:12:34,791 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 12:12:34,801 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-28 12:12:34,815 INFO L134 CoverageAnalysis]: Checked inductivity of 23 backedges. 13 proven. 0 refuted. 0 times theorem prover too weak. 10 trivial. 0 not checked. [2018-11-28 12:12:34,815 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-28 12:12:34,815 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-28 12:12:34,815 INFO L459 AbstractCegarLoop]: Interpolant automaton has 3 states [2018-11-28 12:12:34,816 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-28 12:12:34,816 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-28 12:12:34,817 INFO L87 Difference]: Start difference. First operand 545 states and 842 transitions. Second operand 3 states. [2018-11-28 12:12:34,846 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-28 12:12:34,846 INFO L93 Difference]: Finished difference Result 1053 states and 1621 transitions. [2018-11-28 12:12:34,847 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-28 12:12:34,847 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 45 [2018-11-28 12:12:34,848 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-28 12:12:34,849 INFO L225 Difference]: With dead ends: 1053 [2018-11-28 12:12:34,849 INFO L226 Difference]: Without dead ends: 557 [2018-11-28 12:12:34,850 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-28 12:12:34,851 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 557 states. [2018-11-28 12:12:34,863 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 557 to 555. [2018-11-28 12:12:34,863 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 555 states. [2018-11-28 12:12:34,865 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 555 states to 555 states and 835 transitions. [2018-11-28 12:12:34,865 INFO L78 Accepts]: Start accepts. Automaton has 555 states and 835 transitions. Word has length 45 [2018-11-28 12:12:34,866 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-28 12:12:34,866 INFO L480 AbstractCegarLoop]: Abstraction has 555 states and 835 transitions. [2018-11-28 12:12:34,866 INFO L481 AbstractCegarLoop]: Interpolant automaton has 3 states. [2018-11-28 12:12:34,867 INFO L276 IsEmpty]: Start isEmpty. Operand 555 states and 835 transitions. [2018-11-28 12:12:34,867 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 56 [2018-11-28 12:12:34,867 INFO L394 BasicCegarLoop]: Found error trace [2018-11-28 12:12:34,867 INFO L402 BasicCegarLoop]: trace histogram [5, 4, 4, 3, 3, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-28 12:12:34,867 INFO L423 AbstractCegarLoop]: === Iteration 14 === [mainErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-28 12:12:34,868 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-28 12:12:34,868 INFO L82 PathProgramCache]: Analyzing trace with hash 1882634818, now seen corresponding path program 1 times [2018-11-28 12:12:34,868 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-28 12:12:34,868 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-28 12:12:34,868 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 12:12:34,869 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-28 12:12:34,869 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 12:12:34,878 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-28 12:12:34,893 INFO L134 CoverageAnalysis]: Checked inductivity of 45 backedges. 22 proven. 0 refuted. 0 times theorem prover too weak. 23 trivial. 0 not checked. [2018-11-28 12:12:34,894 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-28 12:12:34,894 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-28 12:12:34,894 INFO L459 AbstractCegarLoop]: Interpolant automaton has 3 states [2018-11-28 12:12:34,894 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-28 12:12:34,894 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-28 12:12:34,894 INFO L87 Difference]: Start difference. First operand 555 states and 835 transitions. Second operand 3 states. [2018-11-28 12:12:34,918 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-28 12:12:34,919 INFO L93 Difference]: Finished difference Result 799 states and 1202 transitions. [2018-11-28 12:12:34,919 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-28 12:12:34,919 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 55 [2018-11-28 12:12:34,920 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-28 12:12:34,920 INFO L225 Difference]: With dead ends: 799 [2018-11-28 12:12:34,920 INFO L226 Difference]: Without dead ends: 313 [2018-11-28 12:12:34,921 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-28 12:12:34,922 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 313 states. [2018-11-28 12:12:34,929 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 313 to 311. [2018-11-28 12:12:34,929 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 311 states. [2018-11-28 12:12:34,930 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 311 states to 311 states and 454 transitions. [2018-11-28 12:12:34,930 INFO L78 Accepts]: Start accepts. Automaton has 311 states and 454 transitions. Word has length 55 [2018-11-28 12:12:34,931 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-28 12:12:34,931 INFO L480 AbstractCegarLoop]: Abstraction has 311 states and 454 transitions. [2018-11-28 12:12:34,931 INFO L481 AbstractCegarLoop]: Interpolant automaton has 3 states. [2018-11-28 12:12:34,931 INFO L276 IsEmpty]: Start isEmpty. Operand 311 states and 454 transitions. [2018-11-28 12:12:34,931 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 57 [2018-11-28 12:12:34,931 INFO L394 BasicCegarLoop]: Found error trace [2018-11-28 12:12:34,931 INFO L402 BasicCegarLoop]: trace histogram [5, 4, 4, 3, 3, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-28 12:12:34,932 INFO L423 AbstractCegarLoop]: === Iteration 15 === [mainErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-28 12:12:34,932 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-28 12:12:34,932 INFO L82 PathProgramCache]: Analyzing trace with hash 1573307774, now seen corresponding path program 1 times [2018-11-28 12:12:34,932 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-28 12:12:34,932 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-28 12:12:34,933 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 12:12:34,933 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-28 12:12:34,933 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 12:12:34,941 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-28 12:12:34,966 INFO L134 CoverageAnalysis]: Checked inductivity of 43 backedges. 23 proven. 14 refuted. 0 times theorem prover too weak. 6 trivial. 0 not checked. [2018-11-28 12:12:34,966 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-28 12:12:34,966 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_907111b8-e5c3-4c9a-8b01-db5944a86240/bin-2019/uautomizer/z3 Starting monitored process 8 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 8 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-28 12:12:34,975 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-28 12:12:35,009 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-28 12:12:35,012 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-28 12:12:35,018 INFO L134 CoverageAnalysis]: Checked inductivity of 43 backedges. 23 proven. 14 refuted. 0 times theorem prover too weak. 6 trivial. 0 not checked. [2018-11-28 12:12:35,042 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-11-28 12:12:35,042 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [5, 5] total 5 [2018-11-28 12:12:35,042 INFO L459 AbstractCegarLoop]: Interpolant automaton has 5 states [2018-11-28 12:12:35,042 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-11-28 12:12:35,042 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=10, Invalid=10, Unknown=0, NotChecked=0, Total=20 [2018-11-28 12:12:35,043 INFO L87 Difference]: Start difference. First operand 311 states and 454 transitions. Second operand 5 states. [2018-11-28 12:12:35,149 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-28 12:12:35,149 INFO L93 Difference]: Finished difference Result 660 states and 968 transitions. [2018-11-28 12:12:35,150 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2018-11-28 12:12:35,150 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 56 [2018-11-28 12:12:35,150 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-28 12:12:35,151 INFO L225 Difference]: With dead ends: 660 [2018-11-28 12:12:35,151 INFO L226 Difference]: Without dead ends: 418 [2018-11-28 12:12:35,152 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 61 GetRequests, 58 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=10, Invalid=10, Unknown=0, NotChecked=0, Total=20 [2018-11-28 12:12:35,152 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 418 states. [2018-11-28 12:12:35,164 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 418 to 389. [2018-11-28 12:12:35,165 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 389 states. [2018-11-28 12:12:35,166 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 389 states to 389 states and 573 transitions. [2018-11-28 12:12:35,166 INFO L78 Accepts]: Start accepts. Automaton has 389 states and 573 transitions. Word has length 56 [2018-11-28 12:12:35,166 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-28 12:12:35,166 INFO L480 AbstractCegarLoop]: Abstraction has 389 states and 573 transitions. [2018-11-28 12:12:35,166 INFO L481 AbstractCegarLoop]: Interpolant automaton has 5 states. [2018-11-28 12:12:35,166 INFO L276 IsEmpty]: Start isEmpty. Operand 389 states and 573 transitions. [2018-11-28 12:12:35,167 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 57 [2018-11-28 12:12:35,167 INFO L394 BasicCegarLoop]: Found error trace [2018-11-28 12:12:35,167 INFO L402 BasicCegarLoop]: trace histogram [5, 5, 4, 3, 3, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-28 12:12:35,167 INFO L423 AbstractCegarLoop]: === Iteration 16 === [mainErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-28 12:12:35,167 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-28 12:12:35,167 INFO L82 PathProgramCache]: Analyzing trace with hash 1831473212, now seen corresponding path program 1 times [2018-11-28 12:12:35,167 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-28 12:12:35,167 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-28 12:12:35,168 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 12:12:35,168 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-28 12:12:35,168 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 12:12:35,177 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-28 12:12:35,224 INFO L134 CoverageAnalysis]: Checked inductivity of 43 backedges. 12 proven. 25 refuted. 0 times theorem prover too weak. 6 trivial. 0 not checked. [2018-11-28 12:12:35,224 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-28 12:12:35,224 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_907111b8-e5c3-4c9a-8b01-db5944a86240/bin-2019/uautomizer/z3 Starting monitored process 9 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 9 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-28 12:12:35,233 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-28 12:12:35,270 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-28 12:12:35,273 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-28 12:12:35,288 INFO L134 CoverageAnalysis]: Checked inductivity of 43 backedges. 12 proven. 25 refuted. 0 times theorem prover too weak. 6 trivial. 0 not checked. [2018-11-28 12:12:35,312 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-11-28 12:12:35,312 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [5, 5] total 5 [2018-11-28 12:12:35,312 INFO L459 AbstractCegarLoop]: Interpolant automaton has 5 states [2018-11-28 12:12:35,312 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-11-28 12:12:35,312 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-11-28 12:12:35,313 INFO L87 Difference]: Start difference. First operand 389 states and 573 transitions. Second operand 5 states. [2018-11-28 12:12:35,383 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-28 12:12:35,384 INFO L93 Difference]: Finished difference Result 436 states and 639 transitions. [2018-11-28 12:12:35,384 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2018-11-28 12:12:35,384 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 56 [2018-11-28 12:12:35,385 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-28 12:12:35,386 INFO L225 Difference]: With dead ends: 436 [2018-11-28 12:12:35,386 INFO L226 Difference]: Without dead ends: 430 [2018-11-28 12:12:35,386 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 61 GetRequests, 57 SyntacticMatches, 1 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-11-28 12:12:35,387 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 430 states. [2018-11-28 12:12:35,399 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 430 to 427. [2018-11-28 12:12:35,399 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 427 states. [2018-11-28 12:12:35,400 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 427 states to 427 states and 627 transitions. [2018-11-28 12:12:35,400 INFO L78 Accepts]: Start accepts. Automaton has 427 states and 627 transitions. Word has length 56 [2018-11-28 12:12:35,401 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-28 12:12:35,401 INFO L480 AbstractCegarLoop]: Abstraction has 427 states and 627 transitions. [2018-11-28 12:12:35,401 INFO L481 AbstractCegarLoop]: Interpolant automaton has 5 states. [2018-11-28 12:12:35,401 INFO L276 IsEmpty]: Start isEmpty. Operand 427 states and 627 transitions. [2018-11-28 12:12:35,401 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 61 [2018-11-28 12:12:35,401 INFO L394 BasicCegarLoop]: Found error trace [2018-11-28 12:12:35,402 INFO L402 BasicCegarLoop]: trace histogram [5, 5, 4, 3, 3, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-28 12:12:35,402 INFO L423 AbstractCegarLoop]: === Iteration 17 === [mainErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-28 12:12:35,402 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-28 12:12:35,402 INFO L82 PathProgramCache]: Analyzing trace with hash -1104488738, now seen corresponding path program 1 times [2018-11-28 12:12:35,402 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-28 12:12:35,402 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-28 12:12:35,403 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 12:12:35,403 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-28 12:12:35,403 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 12:12:35,422 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-28 12:12:35,599 INFO L134 CoverageAnalysis]: Checked inductivity of 43 backedges. 12 proven. 31 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-28 12:12:35,599 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-28 12:12:35,599 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_907111b8-e5c3-4c9a-8b01-db5944a86240/bin-2019/uautomizer/z3 Starting monitored process 10 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 10 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-28 12:12:35,612 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-28 12:12:35,645 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-28 12:12:35,648 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-28 12:12:35,722 INFO L134 CoverageAnalysis]: Checked inductivity of 43 backedges. 12 proven. 31 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-28 12:12:35,746 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-11-28 12:12:35,746 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [7, 6] total 10 [2018-11-28 12:12:35,747 INFO L459 AbstractCegarLoop]: Interpolant automaton has 10 states [2018-11-28 12:12:35,747 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 10 interpolants. [2018-11-28 12:12:35,747 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=22, Invalid=68, Unknown=0, NotChecked=0, Total=90 [2018-11-28 12:12:35,747 INFO L87 Difference]: Start difference. First operand 427 states and 627 transitions. Second operand 10 states. [2018-11-28 12:12:35,933 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-28 12:12:35,933 INFO L93 Difference]: Finished difference Result 430 states and 629 transitions. [2018-11-28 12:12:35,933 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2018-11-28 12:12:35,934 INFO L78 Accepts]: Start accepts. Automaton has 10 states. Word has length 60 [2018-11-28 12:12:35,934 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-28 12:12:35,935 INFO L225 Difference]: With dead ends: 430 [2018-11-28 12:12:35,935 INFO L226 Difference]: Without dead ends: 428 [2018-11-28 12:12:35,935 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 70 GetRequests, 58 SyntacticMatches, 3 SemanticMatches, 9 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 10 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=27, Invalid=83, Unknown=0, NotChecked=0, Total=110 [2018-11-28 12:12:35,936 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 428 states. [2018-11-28 12:12:35,947 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 428 to 427. [2018-11-28 12:12:35,947 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 427 states. [2018-11-28 12:12:35,948 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 427 states to 427 states and 626 transitions. [2018-11-28 12:12:35,949 INFO L78 Accepts]: Start accepts. Automaton has 427 states and 626 transitions. Word has length 60 [2018-11-28 12:12:35,950 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-28 12:12:35,950 INFO L480 AbstractCegarLoop]: Abstraction has 427 states and 626 transitions. [2018-11-28 12:12:35,950 INFO L481 AbstractCegarLoop]: Interpolant automaton has 10 states. [2018-11-28 12:12:35,950 INFO L276 IsEmpty]: Start isEmpty. Operand 427 states and 626 transitions. [2018-11-28 12:12:35,951 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 68 [2018-11-28 12:12:35,951 INFO L394 BasicCegarLoop]: Found error trace [2018-11-28 12:12:35,951 INFO L402 BasicCegarLoop]: trace histogram [6, 6, 5, 3, 3, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-28 12:12:35,951 INFO L423 AbstractCegarLoop]: === Iteration 18 === [mainErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-28 12:12:35,951 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-28 12:12:35,951 INFO L82 PathProgramCache]: Analyzing trace with hash 855434068, now seen corresponding path program 1 times [2018-11-28 12:12:35,951 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-28 12:12:35,952 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-28 12:12:35,952 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 12:12:35,952 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-28 12:12:35,952 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 12:12:35,996 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-28 12:12:36,155 INFO L134 CoverageAnalysis]: Checked inductivity of 65 backedges. 15 proven. 50 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-28 12:12:36,155 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-28 12:12:36,155 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_907111b8-e5c3-4c9a-8b01-db5944a86240/bin-2019/uautomizer/z3 Starting monitored process 11 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 11 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-28 12:12:36,168 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-28 12:12:36,211 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-28 12:12:36,214 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-28 12:12:36,279 INFO L134 CoverageAnalysis]: Checked inductivity of 65 backedges. 15 proven. 50 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-28 12:12:36,303 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-11-28 12:12:36,303 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [8, 8] total 10 [2018-11-28 12:12:36,303 INFO L459 AbstractCegarLoop]: Interpolant automaton has 10 states [2018-11-28 12:12:36,303 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 10 interpolants. [2018-11-28 12:12:36,303 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=21, Invalid=69, Unknown=0, NotChecked=0, Total=90 [2018-11-28 12:12:36,304 INFO L87 Difference]: Start difference. First operand 427 states and 626 transitions. Second operand 10 states. [2018-11-28 12:12:36,486 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-28 12:12:36,486 INFO L93 Difference]: Finished difference Result 431 states and 630 transitions. [2018-11-28 12:12:36,487 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2018-11-28 12:12:36,487 INFO L78 Accepts]: Start accepts. Automaton has 10 states. Word has length 67 [2018-11-28 12:12:36,488 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-28 12:12:36,489 INFO L225 Difference]: With dead ends: 431 [2018-11-28 12:12:36,489 INFO L226 Difference]: Without dead ends: 429 [2018-11-28 12:12:36,489 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 76 GetRequests, 64 SyntacticMatches, 3 SemanticMatches, 9 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 9 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=25, Invalid=85, Unknown=0, NotChecked=0, Total=110 [2018-11-28 12:12:36,490 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 429 states. [2018-11-28 12:12:36,500 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 429 to 428. [2018-11-28 12:12:36,501 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 428 states. [2018-11-28 12:12:36,502 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 428 states to 428 states and 627 transitions. [2018-11-28 12:12:36,502 INFO L78 Accepts]: Start accepts. Automaton has 428 states and 627 transitions. Word has length 67 [2018-11-28 12:12:36,503 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-28 12:12:36,503 INFO L480 AbstractCegarLoop]: Abstraction has 428 states and 627 transitions. [2018-11-28 12:12:36,503 INFO L481 AbstractCegarLoop]: Interpolant automaton has 10 states. [2018-11-28 12:12:36,503 INFO L276 IsEmpty]: Start isEmpty. Operand 428 states and 627 transitions. [2018-11-28 12:12:36,503 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 78 [2018-11-28 12:12:36,503 INFO L394 BasicCegarLoop]: Found error trace [2018-11-28 12:12:36,504 INFO L402 BasicCegarLoop]: trace histogram [7, 6, 6, 4, 4, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-28 12:12:36,504 INFO L423 AbstractCegarLoop]: === Iteration 19 === [mainErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-28 12:12:36,504 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-28 12:12:36,504 INFO L82 PathProgramCache]: Analyzing trace with hash 1201928326, now seen corresponding path program 1 times [2018-11-28 12:12:36,504 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-28 12:12:36,504 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-28 12:12:36,505 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 12:12:36,505 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-28 12:12:36,505 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 12:12:36,520 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-28 12:12:36,555 INFO L134 CoverageAnalysis]: Checked inductivity of 98 backedges. 38 proven. 50 refuted. 0 times theorem prover too weak. 10 trivial. 0 not checked. [2018-11-28 12:12:36,555 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-28 12:12:36,555 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_907111b8-e5c3-4c9a-8b01-db5944a86240/bin-2019/uautomizer/z3 Starting monitored process 12 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 12 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-28 12:12:36,563 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-28 12:12:36,610 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-28 12:12:36,612 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-28 12:12:36,620 INFO L134 CoverageAnalysis]: Checked inductivity of 98 backedges. 38 proven. 50 refuted. 0 times theorem prover too weak. 10 trivial. 0 not checked. [2018-11-28 12:12:36,644 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-11-28 12:12:36,644 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [6, 6] total 6 [2018-11-28 12:12:36,644 INFO L459 AbstractCegarLoop]: Interpolant automaton has 6 states [2018-11-28 12:12:36,644 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2018-11-28 12:12:36,644 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=15, Invalid=15, Unknown=0, NotChecked=0, Total=30 [2018-11-28 12:12:36,645 INFO L87 Difference]: Start difference. First operand 428 states and 627 transitions. Second operand 6 states. [2018-11-28 12:12:36,771 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-28 12:12:36,771 INFO L93 Difference]: Finished difference Result 865 states and 1269 transitions. [2018-11-28 12:12:36,772 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2018-11-28 12:12:36,772 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 77 [2018-11-28 12:12:36,772 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-28 12:12:36,774 INFO L225 Difference]: With dead ends: 865 [2018-11-28 12:12:36,774 INFO L226 Difference]: Without dead ends: 545 [2018-11-28 12:12:36,774 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 84 GetRequests, 80 SyntacticMatches, 0 SemanticMatches, 4 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=15, Invalid=15, Unknown=0, NotChecked=0, Total=30 [2018-11-28 12:12:36,775 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 545 states. [2018-11-28 12:12:36,786 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 545 to 506. [2018-11-28 12:12:36,787 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 506 states. [2018-11-28 12:12:36,788 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 506 states to 506 states and 746 transitions. [2018-11-28 12:12:36,788 INFO L78 Accepts]: Start accepts. Automaton has 506 states and 746 transitions. Word has length 77 [2018-11-28 12:12:36,788 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-28 12:12:36,788 INFO L480 AbstractCegarLoop]: Abstraction has 506 states and 746 transitions. [2018-11-28 12:12:36,788 INFO L481 AbstractCegarLoop]: Interpolant automaton has 6 states. [2018-11-28 12:12:36,789 INFO L276 IsEmpty]: Start isEmpty. Operand 506 states and 746 transitions. [2018-11-28 12:12:36,789 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 78 [2018-11-28 12:12:36,789 INFO L394 BasicCegarLoop]: Found error trace [2018-11-28 12:12:36,789 INFO L402 BasicCegarLoop]: trace histogram [7, 7, 6, 4, 4, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-28 12:12:36,789 INFO L423 AbstractCegarLoop]: === Iteration 20 === [mainErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-28 12:12:36,790 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-28 12:12:36,790 INFO L82 PathProgramCache]: Analyzing trace with hash 808901316, now seen corresponding path program 1 times [2018-11-28 12:12:36,790 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-28 12:12:36,790 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-28 12:12:36,790 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 12:12:36,790 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-28 12:12:36,791 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 12:12:36,805 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-28 12:12:36,980 INFO L134 CoverageAnalysis]: Checked inductivity of 98 backedges. 18 proven. 80 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-28 12:12:36,980 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-28 12:12:36,980 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_907111b8-e5c3-4c9a-8b01-db5944a86240/bin-2019/uautomizer/z3 Starting monitored process 13 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 13 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-28 12:12:36,992 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-28 12:12:37,036 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-28 12:12:37,038 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-28 12:12:37,116 INFO L134 CoverageAnalysis]: Checked inductivity of 98 backedges. 18 proven. 70 refuted. 0 times theorem prover too weak. 10 trivial. 0 not checked. [2018-11-28 12:12:37,141 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-11-28 12:12:37,141 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [9, 7] total 13 [2018-11-28 12:12:37,142 INFO L459 AbstractCegarLoop]: Interpolant automaton has 13 states [2018-11-28 12:12:37,142 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 13 interpolants. [2018-11-28 12:12:37,143 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=30, Invalid=126, Unknown=0, NotChecked=0, Total=156 [2018-11-28 12:12:37,143 INFO L87 Difference]: Start difference. First operand 506 states and 746 transitions. Second operand 13 states. [2018-11-28 12:12:37,330 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-28 12:12:37,330 INFO L93 Difference]: Finished difference Result 529 states and 778 transitions. [2018-11-28 12:12:37,331 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 10 states. [2018-11-28 12:12:37,331 INFO L78 Accepts]: Start accepts. Automaton has 13 states. Word has length 77 [2018-11-28 12:12:37,331 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-28 12:12:37,333 INFO L225 Difference]: With dead ends: 529 [2018-11-28 12:12:37,333 INFO L226 Difference]: Without dead ends: 525 [2018-11-28 12:12:37,333 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 86 GetRequests, 73 SyntacticMatches, 1 SemanticMatches, 12 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 14 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=35, Invalid=147, Unknown=0, NotChecked=0, Total=182 [2018-11-28 12:12:37,334 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 525 states. [2018-11-28 12:12:37,345 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 525 to 525. [2018-11-28 12:12:37,345 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 525 states. [2018-11-28 12:12:37,347 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 525 states to 525 states and 772 transitions. [2018-11-28 12:12:37,347 INFO L78 Accepts]: Start accepts. Automaton has 525 states and 772 transitions. Word has length 77 [2018-11-28 12:12:37,347 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-28 12:12:37,347 INFO L480 AbstractCegarLoop]: Abstraction has 525 states and 772 transitions. [2018-11-28 12:12:37,347 INFO L481 AbstractCegarLoop]: Interpolant automaton has 13 states. [2018-11-28 12:12:37,347 INFO L276 IsEmpty]: Start isEmpty. Operand 525 states and 772 transitions. [2018-11-28 12:12:37,348 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 88 [2018-11-28 12:12:37,348 INFO L394 BasicCegarLoop]: Found error trace [2018-11-28 12:12:37,348 INFO L402 BasicCegarLoop]: trace histogram [8, 8, 7, 5, 5, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-28 12:12:37,348 INFO L423 AbstractCegarLoop]: === Iteration 21 === [mainErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-28 12:12:37,348 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-28 12:12:37,348 INFO L82 PathProgramCache]: Analyzing trace with hash 704934839, now seen corresponding path program 1 times [2018-11-28 12:12:37,348 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-28 12:12:37,349 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-28 12:12:37,349 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 12:12:37,349 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-28 12:12:37,349 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 12:12:37,363 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-28 12:12:37,481 INFO L134 CoverageAnalysis]: Checked inductivity of 136 backedges. 26 proven. 99 refuted. 0 times theorem prover too weak. 11 trivial. 0 not checked. [2018-11-28 12:12:37,481 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-28 12:12:37,481 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_907111b8-e5c3-4c9a-8b01-db5944a86240/bin-2019/uautomizer/z3 Starting monitored process 14 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 14 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-28 12:12:37,490 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-28 12:12:37,546 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-28 12:12:37,548 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-28 12:12:37,587 INFO L134 CoverageAnalysis]: Checked inductivity of 136 backedges. 21 proven. 99 refuted. 0 times theorem prover too weak. 16 trivial. 0 not checked. [2018-11-28 12:12:37,613 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-11-28 12:12:37,613 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [8, 7] total 9 [2018-11-28 12:12:37,614 INFO L459 AbstractCegarLoop]: Interpolant automaton has 9 states [2018-11-28 12:12:37,614 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 9 interpolants. [2018-11-28 12:12:37,614 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=19, Invalid=53, Unknown=0, NotChecked=0, Total=72 [2018-11-28 12:12:37,614 INFO L87 Difference]: Start difference. First operand 525 states and 772 transitions. Second operand 9 states. [2018-11-28 12:12:37,780 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-28 12:12:37,780 INFO L93 Difference]: Finished difference Result 555 states and 810 transitions. [2018-11-28 12:12:37,781 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2018-11-28 12:12:37,781 INFO L78 Accepts]: Start accepts. Automaton has 9 states. Word has length 87 [2018-11-28 12:12:37,782 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-28 12:12:37,783 INFO L225 Difference]: With dead ends: 555 [2018-11-28 12:12:37,783 INFO L226 Difference]: Without dead ends: 551 [2018-11-28 12:12:37,784 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 99 GetRequests, 89 SyntacticMatches, 2 SemanticMatches, 8 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 7 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=23, Invalid=67, Unknown=0, NotChecked=0, Total=90 [2018-11-28 12:12:37,784 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 551 states. [2018-11-28 12:12:37,794 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 551 to 544. [2018-11-28 12:12:37,795 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 544 states. [2018-11-28 12:12:37,796 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 544 states to 544 states and 798 transitions. [2018-11-28 12:12:37,796 INFO L78 Accepts]: Start accepts. Automaton has 544 states and 798 transitions. Word has length 87 [2018-11-28 12:12:37,796 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-28 12:12:37,796 INFO L480 AbstractCegarLoop]: Abstraction has 544 states and 798 transitions. [2018-11-28 12:12:37,796 INFO L481 AbstractCegarLoop]: Interpolant automaton has 9 states. [2018-11-28 12:12:37,796 INFO L276 IsEmpty]: Start isEmpty. Operand 544 states and 798 transitions. [2018-11-28 12:12:37,797 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 91 [2018-11-28 12:12:37,797 INFO L394 BasicCegarLoop]: Found error trace [2018-11-28 12:12:37,797 INFO L402 BasicCegarLoop]: trace histogram [8, 8, 7, 5, 5, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-28 12:12:37,797 INFO L423 AbstractCegarLoop]: === Iteration 22 === [mainErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-28 12:12:37,798 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-28 12:12:37,798 INFO L82 PathProgramCache]: Analyzing trace with hash 1100197245, now seen corresponding path program 1 times [2018-11-28 12:12:37,798 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-28 12:12:37,798 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-28 12:12:37,798 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 12:12:37,798 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-28 12:12:37,799 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 12:12:37,829 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-28 12:12:38,041 INFO L134 CoverageAnalysis]: Checked inductivity of 141 backedges. 21 proven. 120 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-28 12:12:38,041 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-28 12:12:38,041 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_907111b8-e5c3-4c9a-8b01-db5944a86240/bin-2019/uautomizer/z3 Starting monitored process 15 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 15 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-28 12:12:38,050 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-28 12:12:38,107 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-28 12:12:38,110 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-28 12:12:38,214 INFO L134 CoverageAnalysis]: Checked inductivity of 141 backedges. 21 proven. 110 refuted. 0 times theorem prover too weak. 10 trivial. 0 not checked. [2018-11-28 12:12:38,228 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-11-28 12:12:38,229 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [10, 8] total 15 [2018-11-28 12:12:38,229 INFO L459 AbstractCegarLoop]: Interpolant automaton has 15 states [2018-11-28 12:12:38,229 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 15 interpolants. [2018-11-28 12:12:38,229 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=36, Invalid=174, Unknown=0, NotChecked=0, Total=210 [2018-11-28 12:12:38,230 INFO L87 Difference]: Start difference. First operand 544 states and 798 transitions. Second operand 15 states. [2018-11-28 12:12:38,582 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-28 12:12:38,582 INFO L93 Difference]: Finished difference Result 575 states and 828 transitions. [2018-11-28 12:12:38,584 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 18 states. [2018-11-28 12:12:38,585 INFO L78 Accepts]: Start accepts. Automaton has 15 states. Word has length 90 [2018-11-28 12:12:38,585 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-28 12:12:38,586 INFO L225 Difference]: With dead ends: 575 [2018-11-28 12:12:38,587 INFO L226 Difference]: Without dead ends: 573 [2018-11-28 12:12:38,587 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 108 GetRequests, 85 SyntacticMatches, 3 SemanticMatches, 20 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 55 ImplicationChecksByTransitivity, 0.3s TimeCoverageRelationStatistics Valid=72, Invalid=390, Unknown=0, NotChecked=0, Total=462 [2018-11-28 12:12:38,588 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 573 states. [2018-11-28 12:12:38,600 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 573 to 545. [2018-11-28 12:12:38,601 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 545 states. [2018-11-28 12:12:38,602 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 545 states to 545 states and 799 transitions. [2018-11-28 12:12:38,602 INFO L78 Accepts]: Start accepts. Automaton has 545 states and 799 transitions. Word has length 90 [2018-11-28 12:12:38,602 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-28 12:12:38,603 INFO L480 AbstractCegarLoop]: Abstraction has 545 states and 799 transitions. [2018-11-28 12:12:38,603 INFO L481 AbstractCegarLoop]: Interpolant automaton has 15 states. [2018-11-28 12:12:38,603 INFO L276 IsEmpty]: Start isEmpty. Operand 545 states and 799 transitions. [2018-11-28 12:12:38,603 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 103 [2018-11-28 12:12:38,604 INFO L394 BasicCegarLoop]: Found error trace [2018-11-28 12:12:38,604 INFO L402 BasicCegarLoop]: trace histogram [9, 8, 8, 6, 6, 4, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-28 12:12:38,604 INFO L423 AbstractCegarLoop]: === Iteration 23 === [mainErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-28 12:12:38,604 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-28 12:12:38,604 INFO L82 PathProgramCache]: Analyzing trace with hash 1191267151, now seen corresponding path program 1 times [2018-11-28 12:12:38,604 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-28 12:12:38,604 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-28 12:12:38,605 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 12:12:38,605 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-28 12:12:38,605 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 12:12:38,620 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-28 12:12:38,677 INFO L134 CoverageAnalysis]: Checked inductivity of 188 backedges. 54 proven. 118 refuted. 0 times theorem prover too weak. 16 trivial. 0 not checked. [2018-11-28 12:12:38,677 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-28 12:12:38,677 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_907111b8-e5c3-4c9a-8b01-db5944a86240/bin-2019/uautomizer/z3 Starting monitored process 16 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 16 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-28 12:12:38,691 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-28 12:12:38,750 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-28 12:12:38,753 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-28 12:12:38,764 INFO L134 CoverageAnalysis]: Checked inductivity of 188 backedges. 54 proven. 118 refuted. 0 times theorem prover too weak. 16 trivial. 0 not checked. [2018-11-28 12:12:38,781 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-11-28 12:12:38,781 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [7, 7] total 7 [2018-11-28 12:12:38,781 INFO L459 AbstractCegarLoop]: Interpolant automaton has 7 states [2018-11-28 12:12:38,782 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2018-11-28 12:12:38,782 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=21, Invalid=21, Unknown=0, NotChecked=0, Total=42 [2018-11-28 12:12:38,782 INFO L87 Difference]: Start difference. First operand 545 states and 799 transitions. Second operand 7 states. [2018-11-28 12:12:38,907 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-28 12:12:38,908 INFO L93 Difference]: Finished difference Result 1070 states and 1569 transitions. [2018-11-28 12:12:38,908 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2018-11-28 12:12:38,908 INFO L78 Accepts]: Start accepts. Automaton has 7 states. Word has length 102 [2018-11-28 12:12:38,908 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-28 12:12:38,910 INFO L225 Difference]: With dead ends: 1070 [2018-11-28 12:12:38,910 INFO L226 Difference]: Without dead ends: 672 [2018-11-28 12:12:38,911 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 111 GetRequests, 106 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=21, Invalid=21, Unknown=0, NotChecked=0, Total=42 [2018-11-28 12:12:38,912 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 672 states. [2018-11-28 12:12:38,926 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 672 to 623. [2018-11-28 12:12:38,926 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 623 states. [2018-11-28 12:12:38,928 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 623 states to 623 states and 918 transitions. [2018-11-28 12:12:38,928 INFO L78 Accepts]: Start accepts. Automaton has 623 states and 918 transitions. Word has length 102 [2018-11-28 12:12:38,928 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-28 12:12:38,928 INFO L480 AbstractCegarLoop]: Abstraction has 623 states and 918 transitions. [2018-11-28 12:12:38,928 INFO L481 AbstractCegarLoop]: Interpolant automaton has 7 states. [2018-11-28 12:12:38,928 INFO L276 IsEmpty]: Start isEmpty. Operand 623 states and 918 transitions. [2018-11-28 12:12:38,929 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 103 [2018-11-28 12:12:38,929 INFO L394 BasicCegarLoop]: Found error trace [2018-11-28 12:12:38,929 INFO L402 BasicCegarLoop]: trace histogram [9, 9, 8, 6, 6, 4, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-28 12:12:38,929 INFO L423 AbstractCegarLoop]: === Iteration 24 === [mainErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-28 12:12:38,929 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-28 12:12:38,930 INFO L82 PathProgramCache]: Analyzing trace with hash 1449432589, now seen corresponding path program 1 times [2018-11-28 12:12:38,930 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-28 12:12:38,930 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-28 12:12:38,930 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 12:12:38,930 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-28 12:12:38,931 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 12:12:38,946 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-28 12:12:39,045 INFO L134 CoverageAnalysis]: Checked inductivity of 188 backedges. 24 proven. 148 refuted. 0 times theorem prover too weak. 16 trivial. 0 not checked. [2018-11-28 12:12:39,045 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-28 12:12:39,045 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_907111b8-e5c3-4c9a-8b01-db5944a86240/bin-2019/uautomizer/z3 Starting monitored process 17 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 17 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-28 12:12:39,055 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-28 12:12:39,112 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-28 12:12:39,115 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-28 12:12:39,160 INFO L134 CoverageAnalysis]: Checked inductivity of 188 backedges. 24 proven. 148 refuted. 0 times theorem prover too weak. 16 trivial. 0 not checked. [2018-11-28 12:12:39,175 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-11-28 12:12:39,175 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [7, 7] total 7 [2018-11-28 12:12:39,176 INFO L459 AbstractCegarLoop]: Interpolant automaton has 7 states [2018-11-28 12:12:39,176 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2018-11-28 12:12:39,176 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=11, Invalid=31, Unknown=0, NotChecked=0, Total=42 [2018-11-28 12:12:39,176 INFO L87 Difference]: Start difference. First operand 623 states and 918 transitions. Second operand 7 states. [2018-11-28 12:12:39,271 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-28 12:12:39,271 INFO L93 Difference]: Finished difference Result 670 states and 984 transitions. [2018-11-28 12:12:39,271 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2018-11-28 12:12:39,272 INFO L78 Accepts]: Start accepts. Automaton has 7 states. Word has length 102 [2018-11-28 12:12:39,272 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-28 12:12:39,273 INFO L225 Difference]: With dead ends: 670 [2018-11-28 12:12:39,273 INFO L226 Difference]: Without dead ends: 664 [2018-11-28 12:12:39,274 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 111 GetRequests, 104 SyntacticMatches, 2 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=11, Invalid=31, Unknown=0, NotChecked=0, Total=42 [2018-11-28 12:12:39,274 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 664 states. [2018-11-28 12:12:39,290 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 664 to 661. [2018-11-28 12:12:39,290 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 661 states. [2018-11-28 12:12:39,291 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 661 states to 661 states and 972 transitions. [2018-11-28 12:12:39,291 INFO L78 Accepts]: Start accepts. Automaton has 661 states and 972 transitions. Word has length 102 [2018-11-28 12:12:39,292 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-28 12:12:39,292 INFO L480 AbstractCegarLoop]: Abstraction has 661 states and 972 transitions. [2018-11-28 12:12:39,292 INFO L481 AbstractCegarLoop]: Interpolant automaton has 7 states. [2018-11-28 12:12:39,292 INFO L276 IsEmpty]: Start isEmpty. Operand 661 states and 972 transitions. [2018-11-28 12:12:39,293 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 107 [2018-11-28 12:12:39,293 INFO L394 BasicCegarLoop]: Found error trace [2018-11-28 12:12:39,293 INFO L402 BasicCegarLoop]: trace histogram [9, 9, 8, 6, 6, 4, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-28 12:12:39,293 INFO L423 AbstractCegarLoop]: === Iteration 25 === [mainErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-28 12:12:39,293 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-28 12:12:39,293 INFO L82 PathProgramCache]: Analyzing trace with hash -669250513, now seen corresponding path program 1 times [2018-11-28 12:12:39,293 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-28 12:12:39,294 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-28 12:12:39,294 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 12:12:39,294 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-28 12:12:39,294 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 12:12:39,334 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-28 12:12:39,506 INFO L134 CoverageAnalysis]: Checked inductivity of 194 backedges. 24 proven. 170 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-28 12:12:39,506 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-28 12:12:39,506 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_907111b8-e5c3-4c9a-8b01-db5944a86240/bin-2019/uautomizer/z3 Starting monitored process 18 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 18 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-28 12:12:39,515 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-28 12:12:39,588 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-28 12:12:39,591 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-28 12:12:39,702 INFO L134 CoverageAnalysis]: Checked inductivity of 194 backedges. 24 proven. 160 refuted. 0 times theorem prover too weak. 10 trivial. 0 not checked. [2018-11-28 12:12:39,726 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-11-28 12:12:39,726 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [11, 9] total 16 [2018-11-28 12:12:39,727 INFO L459 AbstractCegarLoop]: Interpolant automaton has 16 states [2018-11-28 12:12:39,727 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 16 interpolants. [2018-11-28 12:12:39,727 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=38, Invalid=202, Unknown=0, NotChecked=0, Total=240 [2018-11-28 12:12:39,727 INFO L87 Difference]: Start difference. First operand 661 states and 972 transitions. Second operand 16 states. [2018-11-28 12:12:40,080 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-28 12:12:40,080 INFO L93 Difference]: Finished difference Result 697 states and 1006 transitions. [2018-11-28 12:12:40,081 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 20 states. [2018-11-28 12:12:40,081 INFO L78 Accepts]: Start accepts. Automaton has 16 states. Word has length 106 [2018-11-28 12:12:40,082 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-28 12:12:40,083 INFO L225 Difference]: With dead ends: 697 [2018-11-28 12:12:40,084 INFO L226 Difference]: Without dead ends: 695 [2018-11-28 12:12:40,084 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 125 GetRequests, 102 SyntacticMatches, 1 SemanticMatches, 22 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 64 ImplicationChecksByTransitivity, 0.3s TimeCoverageRelationStatistics Valid=78, Invalid=474, Unknown=0, NotChecked=0, Total=552 [2018-11-28 12:12:40,085 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 695 states. [2018-11-28 12:12:40,102 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 695 to 661. [2018-11-28 12:12:40,102 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 661 states. [2018-11-28 12:12:40,104 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 661 states to 661 states and 971 transitions. [2018-11-28 12:12:40,104 INFO L78 Accepts]: Start accepts. Automaton has 661 states and 971 transitions. Word has length 106 [2018-11-28 12:12:40,104 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-28 12:12:40,104 INFO L480 AbstractCegarLoop]: Abstraction has 661 states and 971 transitions. [2018-11-28 12:12:40,104 INFO L481 AbstractCegarLoop]: Interpolant automaton has 16 states. [2018-11-28 12:12:40,104 INFO L276 IsEmpty]: Start isEmpty. Operand 661 states and 971 transitions. [2018-11-28 12:12:40,105 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 114 [2018-11-28 12:12:40,105 INFO L394 BasicCegarLoop]: Found error trace [2018-11-28 12:12:40,105 INFO L402 BasicCegarLoop]: trace histogram [10, 10, 9, 6, 6, 4, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-28 12:12:40,105 INFO L423 AbstractCegarLoop]: === Iteration 26 === [mainErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-28 12:12:40,106 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-28 12:12:40,106 INFO L82 PathProgramCache]: Analyzing trace with hash -1267384093, now seen corresponding path program 2 times [2018-11-28 12:12:40,106 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-28 12:12:40,106 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-28 12:12:40,106 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 12:12:40,106 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-28 12:12:40,107 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 12:12:40,160 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-28 12:12:40,367 INFO L134 CoverageAnalysis]: Checked inductivity of 235 backedges. 27 proven. 208 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-28 12:12:40,368 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-28 12:12:40,368 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_907111b8-e5c3-4c9a-8b01-db5944a86240/bin-2019/uautomizer/z3 Starting monitored process 19 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 19 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-28 12:12:40,375 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-11-28 12:12:40,428 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2018-11-28 12:12:40,428 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-11-28 12:12:40,430 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-28 12:12:40,526 INFO L134 CoverageAnalysis]: Checked inductivity of 235 backedges. 27 proven. 198 refuted. 0 times theorem prover too weak. 10 trivial. 0 not checked. [2018-11-28 12:12:40,542 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-11-28 12:12:40,542 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [12, 11] total 18 [2018-11-28 12:12:40,542 INFO L459 AbstractCegarLoop]: Interpolant automaton has 18 states [2018-11-28 12:12:40,543 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 18 interpolants. [2018-11-28 12:12:40,543 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=43, Invalid=263, Unknown=0, NotChecked=0, Total=306 [2018-11-28 12:12:40,543 INFO L87 Difference]: Start difference. First operand 661 states and 971 transitions. Second operand 18 states. [2018-11-28 12:12:40,921 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-28 12:12:40,921 INFO L93 Difference]: Finished difference Result 698 states and 1007 transitions. [2018-11-28 12:12:40,922 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 23 states. [2018-11-28 12:12:40,922 INFO L78 Accepts]: Start accepts. Automaton has 18 states. Word has length 113 [2018-11-28 12:12:40,922 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-28 12:12:40,924 INFO L225 Difference]: With dead ends: 698 [2018-11-28 12:12:40,924 INFO L226 Difference]: Without dead ends: 696 [2018-11-28 12:12:40,924 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 134 GetRequests, 107 SyntacticMatches, 2 SemanticMatches, 25 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 89 ImplicationChecksByTransitivity, 0.3s TimeCoverageRelationStatistics Valid=85, Invalid=617, Unknown=0, NotChecked=0, Total=702 [2018-11-28 12:12:40,925 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 696 states. [2018-11-28 12:12:40,939 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 696 to 662. [2018-11-28 12:12:40,939 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 662 states. [2018-11-28 12:12:40,940 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 662 states to 662 states and 972 transitions. [2018-11-28 12:12:40,941 INFO L78 Accepts]: Start accepts. Automaton has 662 states and 972 transitions. Word has length 113 [2018-11-28 12:12:40,941 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-28 12:12:40,941 INFO L480 AbstractCegarLoop]: Abstraction has 662 states and 972 transitions. [2018-11-28 12:12:40,941 INFO L481 AbstractCegarLoop]: Interpolant automaton has 18 states. [2018-11-28 12:12:40,941 INFO L276 IsEmpty]: Start isEmpty. Operand 662 states and 972 transitions. [2018-11-28 12:12:40,942 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 124 [2018-11-28 12:12:40,942 INFO L394 BasicCegarLoop]: Found error trace [2018-11-28 12:12:40,942 INFO L402 BasicCegarLoop]: trace histogram [11, 10, 10, 7, 7, 4, 3, 3, 3, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-28 12:12:40,943 INFO L423 AbstractCegarLoop]: === Iteration 27 === [mainErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-28 12:12:40,943 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-28 12:12:40,943 INFO L82 PathProgramCache]: Analyzing trace with hash -1815351467, now seen corresponding path program 2 times [2018-11-28 12:12:40,943 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-28 12:12:40,943 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-28 12:12:40,944 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 12:12:40,944 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-28 12:12:40,944 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 12:12:40,957 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-28 12:12:41,023 INFO L134 CoverageAnalysis]: Checked inductivity of 294 backedges. 68 proven. 206 refuted. 0 times theorem prover too weak. 20 trivial. 0 not checked. [2018-11-28 12:12:41,024 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-28 12:12:41,024 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_907111b8-e5c3-4c9a-8b01-db5944a86240/bin-2019/uautomizer/z3 Starting monitored process 20 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 20 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-28 12:12:41,036 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-11-28 12:12:41,104 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2018-11-28 12:12:41,104 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-11-28 12:12:41,107 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-28 12:12:41,121 INFO L134 CoverageAnalysis]: Checked inductivity of 294 backedges. 68 proven. 206 refuted. 0 times theorem prover too weak. 20 trivial. 0 not checked. [2018-11-28 12:12:41,136 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-11-28 12:12:41,137 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [8, 8] total 8 [2018-11-28 12:12:41,137 INFO L459 AbstractCegarLoop]: Interpolant automaton has 8 states [2018-11-28 12:12:41,137 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 8 interpolants. [2018-11-28 12:12:41,137 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=28, Invalid=28, Unknown=0, NotChecked=0, Total=56 [2018-11-28 12:12:41,137 INFO L87 Difference]: Start difference. First operand 662 states and 972 transitions. Second operand 8 states. [2018-11-28 12:12:41,274 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-28 12:12:41,274 INFO L93 Difference]: Finished difference Result 1275 states and 1870 transitions. [2018-11-28 12:12:41,275 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 8 states. [2018-11-28 12:12:41,275 INFO L78 Accepts]: Start accepts. Automaton has 8 states. Word has length 123 [2018-11-28 12:12:41,275 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-28 12:12:41,276 INFO L225 Difference]: With dead ends: 1275 [2018-11-28 12:12:41,277 INFO L226 Difference]: Without dead ends: 799 [2018-11-28 12:12:41,277 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 134 GetRequests, 128 SyntacticMatches, 0 SemanticMatches, 6 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=28, Invalid=28, Unknown=0, NotChecked=0, Total=56 [2018-11-28 12:12:41,278 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 799 states. [2018-11-28 12:12:41,298 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 799 to 740. [2018-11-28 12:12:41,298 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 740 states. [2018-11-28 12:12:41,300 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 740 states to 740 states and 1091 transitions. [2018-11-28 12:12:41,300 INFO L78 Accepts]: Start accepts. Automaton has 740 states and 1091 transitions. Word has length 123 [2018-11-28 12:12:41,300 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-28 12:12:41,300 INFO L480 AbstractCegarLoop]: Abstraction has 740 states and 1091 transitions. [2018-11-28 12:12:41,301 INFO L481 AbstractCegarLoop]: Interpolant automaton has 8 states. [2018-11-28 12:12:41,301 INFO L276 IsEmpty]: Start isEmpty. Operand 740 states and 1091 transitions. [2018-11-28 12:12:41,304 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 124 [2018-11-28 12:12:41,304 INFO L394 BasicCegarLoop]: Found error trace [2018-11-28 12:12:41,304 INFO L402 BasicCegarLoop]: trace histogram [11, 11, 10, 7, 7, 4, 3, 3, 3, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-28 12:12:41,304 INFO L423 AbstractCegarLoop]: === Iteration 28 === [mainErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-28 12:12:41,304 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-28 12:12:41,304 INFO L82 PathProgramCache]: Analyzing trace with hash 2086588819, now seen corresponding path program 2 times [2018-11-28 12:12:41,305 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-28 12:12:41,305 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-28 12:12:41,305 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 12:12:41,305 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-28 12:12:41,305 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 12:12:41,323 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-28 12:12:41,547 INFO L134 CoverageAnalysis]: Checked inductivity of 294 backedges. 35 proven. 254 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2018-11-28 12:12:41,547 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-28 12:12:41,547 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_907111b8-e5c3-4c9a-8b01-db5944a86240/bin-2019/uautomizer/z3 Starting monitored process 21 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 21 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-28 12:12:41,554 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-11-28 12:12:41,610 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2018-11-28 12:12:41,610 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-11-28 12:12:41,613 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-28 12:12:41,687 INFO L134 CoverageAnalysis]: Checked inductivity of 294 backedges. 30 proven. 244 refuted. 0 times theorem prover too weak. 20 trivial. 0 not checked. [2018-11-28 12:12:41,702 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-11-28 12:12:41,702 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [13, 9] total 17 [2018-11-28 12:12:41,703 INFO L459 AbstractCegarLoop]: Interpolant automaton has 17 states [2018-11-28 12:12:41,703 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 17 interpolants. [2018-11-28 12:12:41,703 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=41, Invalid=231, Unknown=0, NotChecked=0, Total=272 [2018-11-28 12:12:41,703 INFO L87 Difference]: Start difference. First operand 740 states and 1091 transitions. Second operand 17 states. [2018-11-28 12:12:42,030 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-28 12:12:42,030 INFO L93 Difference]: Finished difference Result 801 states and 1160 transitions. [2018-11-28 12:12:42,030 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 20 states. [2018-11-28 12:12:42,030 INFO L78 Accepts]: Start accepts. Automaton has 17 states. Word has length 123 [2018-11-28 12:12:42,031 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-28 12:12:42,032 INFO L225 Difference]: With dead ends: 801 [2018-11-28 12:12:42,032 INFO L226 Difference]: Without dead ends: 797 [2018-11-28 12:12:42,033 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 147 GetRequests, 122 SyntacticMatches, 2 SemanticMatches, 23 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 81 ImplicationChecksByTransitivity, 0.3s TimeCoverageRelationStatistics Valid=80, Invalid=520, Unknown=0, NotChecked=0, Total=600 [2018-11-28 12:12:42,033 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 797 states. [2018-11-28 12:12:42,055 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 797 to 759. [2018-11-28 12:12:42,055 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 759 states. [2018-11-28 12:12:42,057 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 759 states to 759 states and 1117 transitions. [2018-11-28 12:12:42,057 INFO L78 Accepts]: Start accepts. Automaton has 759 states and 1117 transitions. Word has length 123 [2018-11-28 12:12:42,057 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-28 12:12:42,057 INFO L480 AbstractCegarLoop]: Abstraction has 759 states and 1117 transitions. [2018-11-28 12:12:42,057 INFO L481 AbstractCegarLoop]: Interpolant automaton has 17 states. [2018-11-28 12:12:42,057 INFO L276 IsEmpty]: Start isEmpty. Operand 759 states and 1117 transitions. [2018-11-28 12:12:42,058 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 134 [2018-11-28 12:12:42,059 INFO L394 BasicCegarLoop]: Found error trace [2018-11-28 12:12:42,059 INFO L402 BasicCegarLoop]: trace histogram [12, 12, 11, 8, 8, 5, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-28 12:12:42,059 INFO L423 AbstractCegarLoop]: === Iteration 29 === [mainErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-28 12:12:42,059 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-28 12:12:42,059 INFO L82 PathProgramCache]: Analyzing trace with hash -635604026, now seen corresponding path program 2 times [2018-11-28 12:12:42,059 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-28 12:12:42,059 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-28 12:12:42,060 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 12:12:42,060 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-28 12:12:42,060 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 12:12:42,077 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-28 12:12:42,234 INFO L134 CoverageAnalysis]: Checked inductivity of 357 backedges. 33 proven. 298 refuted. 0 times theorem prover too weak. 26 trivial. 0 not checked. [2018-11-28 12:12:42,234 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-28 12:12:42,234 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_907111b8-e5c3-4c9a-8b01-db5944a86240/bin-2019/uautomizer/z3 Starting monitored process 22 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 22 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-28 12:12:42,244 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-11-28 12:12:42,338 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2018-11-28 12:12:42,338 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-11-28 12:12:42,342 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-28 12:12:42,424 INFO L134 CoverageAnalysis]: Checked inductivity of 357 backedges. 33 proven. 298 refuted. 0 times theorem prover too weak. 26 trivial. 0 not checked. [2018-11-28 12:12:42,453 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-11-28 12:12:42,453 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [9, 9] total 10 [2018-11-28 12:12:42,454 INFO L459 AbstractCegarLoop]: Interpolant automaton has 10 states [2018-11-28 12:12:42,454 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 10 interpolants. [2018-11-28 12:12:42,454 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=20, Invalid=70, Unknown=0, NotChecked=0, Total=90 [2018-11-28 12:12:42,454 INFO L87 Difference]: Start difference. First operand 759 states and 1117 transitions. Second operand 10 states. [2018-11-28 12:12:42,675 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-28 12:12:42,675 INFO L93 Difference]: Finished difference Result 788 states and 1154 transitions. [2018-11-28 12:12:42,676 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 10 states. [2018-11-28 12:12:42,676 INFO L78 Accepts]: Start accepts. Automaton has 10 states. Word has length 133 [2018-11-28 12:12:42,677 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-28 12:12:42,678 INFO L225 Difference]: With dead ends: 788 [2018-11-28 12:12:42,678 INFO L226 Difference]: Without dead ends: 784 [2018-11-28 12:12:42,678 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 148 GetRequests, 137 SyntacticMatches, 3 SemanticMatches, 8 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=20, Invalid=70, Unknown=0, NotChecked=0, Total=90 [2018-11-28 12:12:42,679 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 784 states. [2018-11-28 12:12:42,692 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 784 to 778. [2018-11-28 12:12:42,692 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 778 states. [2018-11-28 12:12:42,693 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 778 states to 778 states and 1143 transitions. [2018-11-28 12:12:42,693 INFO L78 Accepts]: Start accepts. Automaton has 778 states and 1143 transitions. Word has length 133 [2018-11-28 12:12:42,693 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-28 12:12:42,693 INFO L480 AbstractCegarLoop]: Abstraction has 778 states and 1143 transitions. [2018-11-28 12:12:42,694 INFO L481 AbstractCegarLoop]: Interpolant automaton has 10 states. [2018-11-28 12:12:42,694 INFO L276 IsEmpty]: Start isEmpty. Operand 778 states and 1143 transitions. [2018-11-28 12:12:42,695 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 137 [2018-11-28 12:12:42,695 INFO L394 BasicCegarLoop]: Found error trace [2018-11-28 12:12:42,695 INFO L402 BasicCegarLoop]: trace histogram [12, 12, 11, 8, 8, 5, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-28 12:12:42,695 INFO L423 AbstractCegarLoop]: === Iteration 30 === [mainErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-28 12:12:42,695 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-28 12:12:42,695 INFO L82 PathProgramCache]: Analyzing trace with hash -287211762, now seen corresponding path program 2 times [2018-11-28 12:12:42,695 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-28 12:12:42,695 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-28 12:12:42,696 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 12:12:42,696 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-28 12:12:42,696 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 12:12:42,730 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-28 12:12:42,906 INFO L134 CoverageAnalysis]: Checked inductivity of 367 backedges. 33 proven. 334 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-28 12:12:42,906 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-28 12:12:42,906 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_907111b8-e5c3-4c9a-8b01-db5944a86240/bin-2019/uautomizer/z3 Starting monitored process 23 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 23 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-28 12:12:42,929 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-11-28 12:12:42,992 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2018-11-28 12:12:42,992 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-11-28 12:12:42,995 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-28 12:12:43,097 INFO L134 CoverageAnalysis]: Checked inductivity of 367 backedges. 33 proven. 314 refuted. 0 times theorem prover too weak. 20 trivial. 0 not checked. [2018-11-28 12:12:43,112 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-11-28 12:12:43,112 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [14, 10] total 21 [2018-11-28 12:12:43,112 INFO L459 AbstractCegarLoop]: Interpolant automaton has 21 states [2018-11-28 12:12:43,112 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 21 interpolants. [2018-11-28 12:12:43,113 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=51, Invalid=369, Unknown=0, NotChecked=0, Total=420 [2018-11-28 12:12:43,113 INFO L87 Difference]: Start difference. First operand 778 states and 1143 transitions. Second operand 21 states. [2018-11-28 12:12:43,484 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-28 12:12:43,484 INFO L93 Difference]: Finished difference Result 785 states and 1150 transitions. [2018-11-28 12:12:43,485 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 19 states. [2018-11-28 12:12:43,485 INFO L78 Accepts]: Start accepts. Automaton has 21 states. Word has length 136 [2018-11-28 12:12:43,485 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-28 12:12:43,487 INFO L225 Difference]: With dead ends: 785 [2018-11-28 12:12:43,487 INFO L226 Difference]: Without dead ends: 783 [2018-11-28 12:12:43,487 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 156 GetRequests, 131 SyntacticMatches, 1 SemanticMatches, 24 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 58 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=75, Invalid=575, Unknown=0, NotChecked=0, Total=650 [2018-11-28 12:12:43,488 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 783 states. [2018-11-28 12:12:43,500 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 783 to 779. [2018-11-28 12:12:43,501 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 779 states. [2018-11-28 12:12:43,502 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 779 states to 779 states and 1144 transitions. [2018-11-28 12:12:43,502 INFO L78 Accepts]: Start accepts. Automaton has 779 states and 1144 transitions. Word has length 136 [2018-11-28 12:12:43,502 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-28 12:12:43,502 INFO L480 AbstractCegarLoop]: Abstraction has 779 states and 1144 transitions. [2018-11-28 12:12:43,502 INFO L481 AbstractCegarLoop]: Interpolant automaton has 21 states. [2018-11-28 12:12:43,502 INFO L276 IsEmpty]: Start isEmpty. Operand 779 states and 1144 transitions. [2018-11-28 12:12:43,503 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 149 [2018-11-28 12:12:43,503 INFO L394 BasicCegarLoop]: Found error trace [2018-11-28 12:12:43,504 INFO L402 BasicCegarLoop]: trace histogram [13, 12, 12, 9, 9, 6, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-28 12:12:43,504 INFO L423 AbstractCegarLoop]: === Iteration 31 === [mainErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-28 12:12:43,504 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-28 12:12:43,504 INFO L82 PathProgramCache]: Analyzing trace with hash 2035567456, now seen corresponding path program 2 times [2018-11-28 12:12:43,504 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-28 12:12:43,504 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-28 12:12:43,505 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 12:12:43,505 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-28 12:12:43,505 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 12:12:43,516 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-28 12:12:43,570 INFO L134 CoverageAnalysis]: Checked inductivity of 441 backedges. 85 proven. 330 refuted. 0 times theorem prover too weak. 26 trivial. 0 not checked. [2018-11-28 12:12:43,570 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-28 12:12:43,570 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_907111b8-e5c3-4c9a-8b01-db5944a86240/bin-2019/uautomizer/z3 Starting monitored process 24 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 24 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-28 12:12:43,577 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-11-28 12:12:43,600 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) [2018-11-28 12:12:43,600 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-11-28 12:12:43,602 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-28 12:12:43,657 INFO L134 CoverageAnalysis]: Checked inductivity of 441 backedges. 50 proven. 0 refuted. 0 times theorem prover too weak. 391 trivial. 0 not checked. [2018-11-28 12:12:43,671 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 1 imperfect interpolant sequences. [2018-11-28 12:12:43,672 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [9] total 10 [2018-11-28 12:12:43,672 INFO L459 AbstractCegarLoop]: Interpolant automaton has 10 states [2018-11-28 12:12:43,672 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 10 interpolants. [2018-11-28 12:12:43,672 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=45, Invalid=45, Unknown=0, NotChecked=0, Total=90 [2018-11-28 12:12:43,672 INFO L87 Difference]: Start difference. First operand 779 states and 1144 transitions. Second operand 10 states. [2018-11-28 12:12:43,850 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-28 12:12:43,851 INFO L93 Difference]: Finished difference Result 1568 states and 2302 transitions. [2018-11-28 12:12:43,851 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 10 states. [2018-11-28 12:12:43,851 INFO L78 Accepts]: Start accepts. Automaton has 10 states. Word has length 148 [2018-11-28 12:12:43,852 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-28 12:12:43,853 INFO L225 Difference]: With dead ends: 1568 [2018-11-28 12:12:43,853 INFO L226 Difference]: Without dead ends: 1009 [2018-11-28 12:12:43,854 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 161 GetRequests, 153 SyntacticMatches, 0 SemanticMatches, 8 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 12 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=45, Invalid=45, Unknown=0, NotChecked=0, Total=90 [2018-11-28 12:12:43,855 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1009 states. [2018-11-28 12:12:43,870 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1009 to 935. [2018-11-28 12:12:43,870 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 935 states. [2018-11-28 12:12:43,871 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 935 states to 935 states and 1377 transitions. [2018-11-28 12:12:43,871 INFO L78 Accepts]: Start accepts. Automaton has 935 states and 1377 transitions. Word has length 148 [2018-11-28 12:12:43,871 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-28 12:12:43,872 INFO L480 AbstractCegarLoop]: Abstraction has 935 states and 1377 transitions. [2018-11-28 12:12:43,872 INFO L481 AbstractCegarLoop]: Interpolant automaton has 10 states. [2018-11-28 12:12:43,872 INFO L276 IsEmpty]: Start isEmpty. Operand 935 states and 1377 transitions. [2018-11-28 12:12:43,873 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 149 [2018-11-28 12:12:43,873 INFO L394 BasicCegarLoop]: Found error trace [2018-11-28 12:12:43,873 INFO L402 BasicCegarLoop]: trace histogram [13, 13, 12, 9, 9, 6, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-28 12:12:43,873 INFO L423 AbstractCegarLoop]: === Iteration 32 === [mainErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-28 12:12:43,873 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-28 12:12:43,873 INFO L82 PathProgramCache]: Analyzing trace with hash -2001234402, now seen corresponding path program 2 times [2018-11-28 12:12:43,874 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-28 12:12:43,874 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-28 12:12:43,874 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 12:12:43,874 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-28 12:12:43,874 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 12:12:43,885 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-28 12:12:43,981 INFO L134 CoverageAnalysis]: Checked inductivity of 441 backedges. 36 proven. 379 refuted. 0 times theorem prover too weak. 26 trivial. 0 not checked. [2018-11-28 12:12:43,981 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-28 12:12:43,981 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_907111b8-e5c3-4c9a-8b01-db5944a86240/bin-2019/uautomizer/z3 Starting monitored process 25 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 25 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-28 12:12:43,988 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-11-28 12:12:44,053 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2018-11-28 12:12:44,053 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-11-28 12:12:44,057 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-28 12:12:44,083 INFO L134 CoverageAnalysis]: Checked inductivity of 441 backedges. 36 proven. 379 refuted. 0 times theorem prover too weak. 26 trivial. 0 not checked. [2018-11-28 12:12:44,098 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-11-28 12:12:44,099 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [9, 9] total 9 [2018-11-28 12:12:44,099 INFO L459 AbstractCegarLoop]: Interpolant automaton has 9 states [2018-11-28 12:12:44,099 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 9 interpolants. [2018-11-28 12:12:44,099 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=15, Invalid=57, Unknown=0, NotChecked=0, Total=72 [2018-11-28 12:12:44,099 INFO L87 Difference]: Start difference. First operand 935 states and 1377 transitions. Second operand 9 states. [2018-11-28 12:12:44,229 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-28 12:12:44,230 INFO L93 Difference]: Finished difference Result 982 states and 1443 transitions. [2018-11-28 12:12:44,230 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2018-11-28 12:12:44,230 INFO L78 Accepts]: Start accepts. Automaton has 9 states. Word has length 148 [2018-11-28 12:12:44,230 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-28 12:12:44,232 INFO L225 Difference]: With dead ends: 982 [2018-11-28 12:12:44,233 INFO L226 Difference]: Without dead ends: 976 [2018-11-28 12:12:44,233 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 161 GetRequests, 153 SyntacticMatches, 1 SemanticMatches, 7 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=15, Invalid=57, Unknown=0, NotChecked=0, Total=72 [2018-11-28 12:12:44,234 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 976 states. [2018-11-28 12:12:44,261 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 976 to 973. [2018-11-28 12:12:44,261 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 973 states. [2018-11-28 12:12:44,263 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 973 states to 973 states and 1431 transitions. [2018-11-28 12:12:44,263 INFO L78 Accepts]: Start accepts. Automaton has 973 states and 1431 transitions. Word has length 148 [2018-11-28 12:12:44,263 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-28 12:12:44,264 INFO L480 AbstractCegarLoop]: Abstraction has 973 states and 1431 transitions. [2018-11-28 12:12:44,264 INFO L481 AbstractCegarLoop]: Interpolant automaton has 9 states. [2018-11-28 12:12:44,264 INFO L276 IsEmpty]: Start isEmpty. Operand 973 states and 1431 transitions. [2018-11-28 12:12:44,265 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 153 [2018-11-28 12:12:44,265 INFO L394 BasicCegarLoop]: Found error trace [2018-11-28 12:12:44,265 INFO L402 BasicCegarLoop]: trace histogram [13, 13, 12, 9, 9, 6, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-28 12:12:44,265 INFO L423 AbstractCegarLoop]: === Iteration 33 === [mainErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-28 12:12:44,265 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-28 12:12:44,266 INFO L82 PathProgramCache]: Analyzing trace with hash -1445028928, now seen corresponding path program 2 times [2018-11-28 12:12:44,266 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-28 12:12:44,266 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-28 12:12:44,266 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 12:12:44,266 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-28 12:12:44,266 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 12:12:44,309 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-28 12:12:44,522 INFO L134 CoverageAnalysis]: Checked inductivity of 453 backedges. 36 proven. 417 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-28 12:12:44,523 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-28 12:12:44,523 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_907111b8-e5c3-4c9a-8b01-db5944a86240/bin-2019/uautomizer/z3 Starting monitored process 26 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 26 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-28 12:12:44,529 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-11-28 12:12:44,588 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2018-11-28 12:12:44,588 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-11-28 12:12:44,591 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-28 12:12:44,737 INFO L134 CoverageAnalysis]: Checked inductivity of 453 backedges. 36 proven. 397 refuted. 0 times theorem prover too weak. 20 trivial. 0 not checked. [2018-11-28 12:12:44,752 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-11-28 12:12:44,752 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [15, 11] total 24 [2018-11-28 12:12:44,753 INFO L459 AbstractCegarLoop]: Interpolant automaton has 24 states [2018-11-28 12:12:44,753 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 24 interpolants. [2018-11-28 12:12:44,753 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=60, Invalid=492, Unknown=0, NotChecked=0, Total=552 [2018-11-28 12:12:44,753 INFO L87 Difference]: Start difference. First operand 973 states and 1431 transitions. Second operand 24 states. [2018-11-28 12:12:45,168 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-28 12:12:45,168 INFO L93 Difference]: Finished difference Result 1025 states and 1481 transitions. [2018-11-28 12:12:45,169 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 28 states. [2018-11-28 12:12:45,170 INFO L78 Accepts]: Start accepts. Automaton has 24 states. Word has length 152 [2018-11-28 12:12:45,170 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-28 12:12:45,172 INFO L225 Difference]: With dead ends: 1025 [2018-11-28 12:12:45,172 INFO L226 Difference]: Without dead ends: 1023 [2018-11-28 12:12:45,173 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 180 GetRequests, 146 SyntacticMatches, 0 SemanticMatches, 34 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 160 ImplicationChecksByTransitivity, 0.4s TimeCoverageRelationStatistics Valid=122, Invalid=1138, Unknown=0, NotChecked=0, Total=1260 [2018-11-28 12:12:45,173 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1023 states. [2018-11-28 12:12:45,203 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1023 to 973. [2018-11-28 12:12:45,203 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 973 states. [2018-11-28 12:12:45,205 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 973 states to 973 states and 1430 transitions. [2018-11-28 12:12:45,205 INFO L78 Accepts]: Start accepts. Automaton has 973 states and 1430 transitions. Word has length 152 [2018-11-28 12:12:45,205 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-28 12:12:45,205 INFO L480 AbstractCegarLoop]: Abstraction has 973 states and 1430 transitions. [2018-11-28 12:12:45,206 INFO L481 AbstractCegarLoop]: Interpolant automaton has 24 states. [2018-11-28 12:12:45,206 INFO L276 IsEmpty]: Start isEmpty. Operand 973 states and 1430 transitions. [2018-11-28 12:12:45,206 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 160 [2018-11-28 12:12:45,206 INFO L394 BasicCegarLoop]: Found error trace [2018-11-28 12:12:45,207 INFO L402 BasicCegarLoop]: trace histogram [14, 14, 13, 9, 9, 6, 4, 4, 4, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-28 12:12:45,207 INFO L423 AbstractCegarLoop]: === Iteration 34 === [mainErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-28 12:12:45,207 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-28 12:12:45,207 INFO L82 PathProgramCache]: Analyzing trace with hash 1661877298, now seen corresponding path program 3 times [2018-11-28 12:12:45,207 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-28 12:12:45,207 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-28 12:12:45,208 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 12:12:45,208 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-28 12:12:45,208 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 12:12:45,290 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-28 12:12:45,729 INFO L134 CoverageAnalysis]: Checked inductivity of 513 backedges. 39 proven. 474 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-28 12:12:45,729 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-28 12:12:45,729 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_907111b8-e5c3-4c9a-8b01-db5944a86240/bin-2019/uautomizer/z3 Starting monitored process 27 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 27 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-28 12:12:45,735 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-11-28 12:12:45,798 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 6 check-sat command(s) [2018-11-28 12:12:45,798 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-11-28 12:12:45,801 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-28 12:12:46,139 INFO L134 CoverageAnalysis]: Checked inductivity of 513 backedges. 249 proven. 31 refuted. 0 times theorem prover too weak. 233 trivial. 0 not checked. [2018-11-28 12:12:46,153 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-11-28 12:12:46,153 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [16, 8] total 22 [2018-11-28 12:12:46,154 INFO L459 AbstractCegarLoop]: Interpolant automaton has 22 states [2018-11-28 12:12:46,154 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 22 interpolants. [2018-11-28 12:12:46,154 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=57, Invalid=405, Unknown=0, NotChecked=0, Total=462 [2018-11-28 12:12:46,154 INFO L87 Difference]: Start difference. First operand 973 states and 1430 transitions. Second operand 22 states. [2018-11-28 12:12:46,860 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-28 12:12:46,860 INFO L93 Difference]: Finished difference Result 1504 states and 2196 transitions. [2018-11-28 12:12:46,860 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 40 states. [2018-11-28 12:12:46,861 INFO L78 Accepts]: Start accepts. Automaton has 22 states. Word has length 159 [2018-11-28 12:12:46,861 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-28 12:12:46,863 INFO L225 Difference]: With dead ends: 1504 [2018-11-28 12:12:46,863 INFO L226 Difference]: Without dead ends: 787 [2018-11-28 12:12:46,864 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 203 GetRequests, 162 SyntacticMatches, 1 SemanticMatches, 40 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 234 ImplicationChecksByTransitivity, 0.8s TimeCoverageRelationStatistics Valid=170, Invalid=1552, Unknown=0, NotChecked=0, Total=1722 [2018-11-28 12:12:46,865 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 787 states. [2018-11-28 12:12:46,895 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 787 to 738. [2018-11-28 12:12:46,895 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 738 states. [2018-11-28 12:12:46,896 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 738 states to 738 states and 1036 transitions. [2018-11-28 12:12:46,897 INFO L78 Accepts]: Start accepts. Automaton has 738 states and 1036 transitions. Word has length 159 [2018-11-28 12:12:46,897 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-28 12:12:46,897 INFO L480 AbstractCegarLoop]: Abstraction has 738 states and 1036 transitions. [2018-11-28 12:12:46,897 INFO L481 AbstractCegarLoop]: Interpolant automaton has 22 states. [2018-11-28 12:12:46,897 INFO L276 IsEmpty]: Start isEmpty. Operand 738 states and 1036 transitions. [2018-11-28 12:12:46,898 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 170 [2018-11-28 12:12:46,898 INFO L394 BasicCegarLoop]: Found error trace [2018-11-28 12:12:46,899 INFO L402 BasicCegarLoop]: trace histogram [15, 14, 14, 10, 10, 6, 4, 4, 4, 4, 4, 4, 4, 4, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-28 12:12:46,899 INFO L423 AbstractCegarLoop]: === Iteration 35 === [mainErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-28 12:12:46,899 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-28 12:12:46,899 INFO L82 PathProgramCache]: Analyzing trace with hash 305812452, now seen corresponding path program 3 times [2018-11-28 12:12:46,899 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-28 12:12:46,899 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-28 12:12:46,900 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 12:12:46,900 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-28 12:12:46,900 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 12:12:46,923 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-28 12:12:47,058 INFO L134 CoverageAnalysis]: Checked inductivity of 598 backedges. 98 proven. 470 refuted. 0 times theorem prover too weak. 30 trivial. 0 not checked. [2018-11-28 12:12:47,058 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-28 12:12:47,058 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_907111b8-e5c3-4c9a-8b01-db5944a86240/bin-2019/uautomizer/z3 Starting monitored process 28 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 28 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-28 12:12:47,068 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-11-28 12:12:47,204 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 12 check-sat command(s) [2018-11-28 12:12:47,204 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-11-28 12:12:47,209 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-28 12:12:47,232 INFO L134 CoverageAnalysis]: Checked inductivity of 598 backedges. 98 proven. 470 refuted. 0 times theorem prover too weak. 30 trivial. 0 not checked. [2018-11-28 12:12:47,257 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-11-28 12:12:47,257 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [10, 10] total 10 [2018-11-28 12:12:47,258 INFO L459 AbstractCegarLoop]: Interpolant automaton has 10 states [2018-11-28 12:12:47,258 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 10 interpolants. [2018-11-28 12:12:47,258 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=45, Invalid=45, Unknown=0, NotChecked=0, Total=90 [2018-11-28 12:12:47,258 INFO L87 Difference]: Start difference. First operand 738 states and 1036 transitions. Second operand 10 states. [2018-11-28 12:12:47,412 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-28 12:12:47,412 INFO L93 Difference]: Finished difference Result 886 states and 1229 transitions. [2018-11-28 12:12:47,413 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 10 states. [2018-11-28 12:12:47,413 INFO L78 Accepts]: Start accepts. Automaton has 10 states. Word has length 169 [2018-11-28 12:12:47,413 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-28 12:12:47,415 INFO L225 Difference]: With dead ends: 886 [2018-11-28 12:12:47,415 INFO L226 Difference]: Without dead ends: 802 [2018-11-28 12:12:47,415 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 184 GetRequests, 176 SyntacticMatches, 0 SemanticMatches, 8 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=45, Invalid=45, Unknown=0, NotChecked=0, Total=90 [2018-11-28 12:12:47,416 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 802 states. [2018-11-28 12:12:47,431 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 802 to 722. [2018-11-28 12:12:47,431 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 722 states. [2018-11-28 12:12:47,432 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 722 states to 722 states and 1013 transitions. [2018-11-28 12:12:47,432 INFO L78 Accepts]: Start accepts. Automaton has 722 states and 1013 transitions. Word has length 169 [2018-11-28 12:12:47,433 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-28 12:12:47,433 INFO L480 AbstractCegarLoop]: Abstraction has 722 states and 1013 transitions. [2018-11-28 12:12:47,433 INFO L481 AbstractCegarLoop]: Interpolant automaton has 10 states. [2018-11-28 12:12:47,433 INFO L276 IsEmpty]: Start isEmpty. Operand 722 states and 1013 transitions. [2018-11-28 12:12:47,434 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 182 [2018-11-28 12:12:47,434 INFO L394 BasicCegarLoop]: Found error trace [2018-11-28 12:12:47,434 INFO L402 BasicCegarLoop]: trace histogram [16, 16, 15, 11, 11, 7, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-28 12:12:47,434 INFO L423 AbstractCegarLoop]: === Iteration 36 === [mainErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-28 12:12:47,434 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-28 12:12:47,434 INFO L82 PathProgramCache]: Analyzing trace with hash -1852980602, now seen corresponding path program 1 times [2018-11-28 12:12:47,434 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-28 12:12:47,435 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-28 12:12:47,435 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 12:12:47,435 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-28 12:12:47,435 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 12:12:47,481 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-28 12:12:47,639 INFO L134 CoverageAnalysis]: Checked inductivity of 692 backedges. 45 proven. 622 refuted. 0 times theorem prover too weak. 25 trivial. 0 not checked. [2018-11-28 12:12:47,639 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-28 12:12:47,639 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_907111b8-e5c3-4c9a-8b01-db5944a86240/bin-2019/uautomizer/z3 Starting monitored process 29 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 29 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-28 12:12:47,649 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-28 12:12:47,725 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-28 12:12:47,728 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-28 12:12:47,820 INFO L134 CoverageAnalysis]: Checked inductivity of 692 backedges. 656 proven. 0 refuted. 0 times theorem prover too weak. 36 trivial. 0 not checked. [2018-11-28 12:12:47,835 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 1 imperfect interpolant sequences. [2018-11-28 12:12:47,835 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [10] imperfect sequences [12] total 20 [2018-11-28 12:12:47,836 INFO L459 AbstractCegarLoop]: Interpolant automaton has 20 states [2018-11-28 12:12:47,836 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 20 interpolants. [2018-11-28 12:12:47,836 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=111, Invalid=269, Unknown=0, NotChecked=0, Total=380 [2018-11-28 12:12:47,836 INFO L87 Difference]: Start difference. First operand 722 states and 1013 transitions. Second operand 20 states. [2018-11-28 12:12:48,216 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-28 12:12:48,216 INFO L93 Difference]: Finished difference Result 883 states and 1229 transitions. [2018-11-28 12:12:48,216 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 22 states. [2018-11-28 12:12:48,216 INFO L78 Accepts]: Start accepts. Automaton has 20 states. Word has length 181 [2018-11-28 12:12:48,217 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-28 12:12:48,218 INFO L225 Difference]: With dead ends: 883 [2018-11-28 12:12:48,218 INFO L226 Difference]: Without dead ends: 878 [2018-11-28 12:12:48,218 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 208 GetRequests, 180 SyntacticMatches, 1 SemanticMatches, 27 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 93 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=200, Invalid=612, Unknown=0, NotChecked=0, Total=812 [2018-11-28 12:12:48,219 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 878 states. [2018-11-28 12:12:48,236 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 878 to 855. [2018-11-28 12:12:48,237 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 855 states. [2018-11-28 12:12:48,238 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 855 states to 855 states and 1202 transitions. [2018-11-28 12:12:48,238 INFO L78 Accepts]: Start accepts. Automaton has 855 states and 1202 transitions. Word has length 181 [2018-11-28 12:12:48,238 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-28 12:12:48,238 INFO L480 AbstractCegarLoop]: Abstraction has 855 states and 1202 transitions. [2018-11-28 12:12:48,238 INFO L481 AbstractCegarLoop]: Interpolant automaton has 20 states. [2018-11-28 12:12:48,238 INFO L276 IsEmpty]: Start isEmpty. Operand 855 states and 1202 transitions. [2018-11-28 12:12:48,239 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 183 [2018-11-28 12:12:48,239 INFO L394 BasicCegarLoop]: Found error trace [2018-11-28 12:12:48,240 INFO L402 BasicCegarLoop]: trace histogram [16, 16, 15, 11, 11, 7, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-28 12:12:48,240 INFO L423 AbstractCegarLoop]: === Iteration 37 === [mainErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-28 12:12:48,240 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-28 12:12:48,240 INFO L82 PathProgramCache]: Analyzing trace with hash -1596376353, now seen corresponding path program 3 times [2018-11-28 12:12:48,240 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-28 12:12:48,240 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-28 12:12:48,241 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 12:12:48,241 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-28 12:12:48,241 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 12:12:48,305 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-28 12:12:48,734 INFO L134 CoverageAnalysis]: Checked inductivity of 701 backedges. 45 proven. 656 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-28 12:12:48,734 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-28 12:12:48,734 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_907111b8-e5c3-4c9a-8b01-db5944a86240/bin-2019/uautomizer/z3 Starting monitored process 30 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 30 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-28 12:12:48,740 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-11-28 12:12:48,855 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 13 check-sat command(s) [2018-11-28 12:12:48,855 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-11-28 12:12:48,859 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-28 12:12:49,068 INFO L134 CoverageAnalysis]: Checked inductivity of 701 backedges. 665 proven. 6 refuted. 0 times theorem prover too weak. 30 trivial. 0 not checked. [2018-11-28 12:12:49,083 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-11-28 12:12:49,083 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [17, 12] total 27 [2018-11-28 12:12:49,083 INFO L459 AbstractCegarLoop]: Interpolant automaton has 27 states [2018-11-28 12:12:49,083 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 27 interpolants. [2018-11-28 12:12:49,083 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=164, Invalid=538, Unknown=0, NotChecked=0, Total=702 [2018-11-28 12:12:49,084 INFO L87 Difference]: Start difference. First operand 855 states and 1202 transitions. Second operand 27 states. [2018-11-28 12:12:49,380 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-28 12:12:49,380 INFO L93 Difference]: Finished difference Result 864 states and 1210 transitions. [2018-11-28 12:12:49,381 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 27 states. [2018-11-28 12:12:49,381 INFO L78 Accepts]: Start accepts. Automaton has 27 states. Word has length 182 [2018-11-28 12:12:49,381 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-28 12:12:49,383 INFO L225 Difference]: With dead ends: 864 [2018-11-28 12:12:49,383 INFO L226 Difference]: Without dead ends: 862 [2018-11-28 12:12:49,383 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 205 GetRequests, 173 SyntacticMatches, 2 SemanticMatches, 30 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 53 ImplicationChecksByTransitivity, 0.5s TimeCoverageRelationStatistics Valid=223, Invalid=769, Unknown=0, NotChecked=0, Total=992 [2018-11-28 12:12:49,384 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 862 states. [2018-11-28 12:12:49,402 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 862 to 855. [2018-11-28 12:12:49,402 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 855 states. [2018-11-28 12:12:49,403 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 855 states to 855 states and 1201 transitions. [2018-11-28 12:12:49,403 INFO L78 Accepts]: Start accepts. Automaton has 855 states and 1201 transitions. Word has length 182 [2018-11-28 12:12:49,403 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-28 12:12:49,403 INFO L480 AbstractCegarLoop]: Abstraction has 855 states and 1201 transitions. [2018-11-28 12:12:49,403 INFO L481 AbstractCegarLoop]: Interpolant automaton has 27 states. [2018-11-28 12:12:49,403 INFO L276 IsEmpty]: Start isEmpty. Operand 855 states and 1201 transitions. [2018-11-28 12:12:49,404 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 198 [2018-11-28 12:12:49,404 INFO L394 BasicCegarLoop]: Found error trace [2018-11-28 12:12:49,404 INFO L402 BasicCegarLoop]: trace histogram [17, 16, 16, 12, 12, 8, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 3, 3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-28 12:12:49,405 INFO L423 AbstractCegarLoop]: === Iteration 38 === [mainErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-28 12:12:49,405 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-28 12:12:49,405 INFO L82 PathProgramCache]: Analyzing trace with hash -730696556, now seen corresponding path program 1 times [2018-11-28 12:12:49,405 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-28 12:12:49,405 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-28 12:12:49,405 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 12:12:49,405 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-28 12:12:49,406 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 12:12:49,425 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-28 12:12:49,545 INFO L134 CoverageAnalysis]: Checked inductivity of 811 backedges. 125 proven. 650 refuted. 0 times theorem prover too weak. 36 trivial. 0 not checked. [2018-11-28 12:12:49,545 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-28 12:12:49,545 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_907111b8-e5c3-4c9a-8b01-db5944a86240/bin-2019/uautomizer/z3 Starting monitored process 31 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 31 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-28 12:12:49,555 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-28 12:12:49,626 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-28 12:12:49,629 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-28 12:12:49,646 INFO L134 CoverageAnalysis]: Checked inductivity of 811 backedges. 125 proven. 650 refuted. 0 times theorem prover too weak. 36 trivial. 0 not checked. [2018-11-28 12:12:49,661 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-11-28 12:12:49,661 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [11, 11] total 11 [2018-11-28 12:12:49,661 INFO L459 AbstractCegarLoop]: Interpolant automaton has 11 states [2018-11-28 12:12:49,661 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 11 interpolants. [2018-11-28 12:12:49,661 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=55, Invalid=55, Unknown=0, NotChecked=0, Total=110 [2018-11-28 12:12:49,662 INFO L87 Difference]: Start difference. First operand 855 states and 1201 transitions. Second operand 11 states. [2018-11-28 12:12:49,756 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-28 12:12:49,756 INFO L93 Difference]: Finished difference Result 1437 states and 2015 transitions. [2018-11-28 12:12:49,756 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 11 states. [2018-11-28 12:12:49,757 INFO L78 Accepts]: Start accepts. Automaton has 11 states. Word has length 197 [2018-11-28 12:12:49,757 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-28 12:12:49,758 INFO L225 Difference]: With dead ends: 1437 [2018-11-28 12:12:49,758 INFO L226 Difference]: Without dead ends: 962 [2018-11-28 12:12:49,759 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 214 GetRequests, 205 SyntacticMatches, 0 SemanticMatches, 9 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=55, Invalid=55, Unknown=0, NotChecked=0, Total=110 [2018-11-28 12:12:49,759 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 962 states. [2018-11-28 12:12:49,782 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 962 to 933. [2018-11-28 12:12:49,782 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 933 states. [2018-11-28 12:12:49,783 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 933 states to 933 states and 1313 transitions. [2018-11-28 12:12:49,783 INFO L78 Accepts]: Start accepts. Automaton has 933 states and 1313 transitions. Word has length 197 [2018-11-28 12:12:49,783 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-28 12:12:49,783 INFO L480 AbstractCegarLoop]: Abstraction has 933 states and 1313 transitions. [2018-11-28 12:12:49,783 INFO L481 AbstractCegarLoop]: Interpolant automaton has 11 states. [2018-11-28 12:12:49,783 INFO L276 IsEmpty]: Start isEmpty. Operand 933 states and 1313 transitions. [2018-11-28 12:12:49,784 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 199 [2018-11-28 12:12:49,784 INFO L394 BasicCegarLoop]: Found error trace [2018-11-28 12:12:49,784 INFO L402 BasicCegarLoop]: trace histogram [17, 17, 16, 12, 12, 8, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-28 12:12:49,784 INFO L423 AbstractCegarLoop]: === Iteration 39 === [mainErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-28 12:12:49,784 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-28 12:12:49,785 INFO L82 PathProgramCache]: Analyzing trace with hash 2108593553, now seen corresponding path program 3 times [2018-11-28 12:12:49,785 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-28 12:12:49,785 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-28 12:12:49,785 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 12:12:49,785 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-28 12:12:49,785 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 12:12:49,857 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-28 12:12:50,243 INFO L134 CoverageAnalysis]: Checked inductivity of 820 backedges. 56 proven. 742 refuted. 0 times theorem prover too weak. 22 trivial. 0 not checked. [2018-11-28 12:12:50,243 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-28 12:12:50,244 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_907111b8-e5c3-4c9a-8b01-db5944a86240/bin-2019/uautomizer/z3 Starting monitored process 32 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 32 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-28 12:12:50,250 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-11-28 12:12:50,352 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 13 check-sat command(s) [2018-11-28 12:12:50,352 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-11-28 12:12:50,356 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-28 12:12:50,532 INFO L134 CoverageAnalysis]: Checked inductivity of 820 backedges. 771 proven. 19 refuted. 0 times theorem prover too weak. 30 trivial. 0 not checked. [2018-11-28 12:12:50,547 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-11-28 12:12:50,547 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [15, 13] total 26 [2018-11-28 12:12:50,547 INFO L459 AbstractCegarLoop]: Interpolant automaton has 26 states [2018-11-28 12:12:50,547 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 26 interpolants. [2018-11-28 12:12:50,547 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=160, Invalid=490, Unknown=0, NotChecked=0, Total=650 [2018-11-28 12:12:50,548 INFO L87 Difference]: Start difference. First operand 933 states and 1313 transitions. Second operand 26 states. [2018-11-28 12:12:51,291 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-28 12:12:51,291 INFO L93 Difference]: Finished difference Result 1033 states and 1410 transitions. [2018-11-28 12:12:51,291 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 51 states. [2018-11-28 12:12:51,292 INFO L78 Accepts]: Start accepts. Automaton has 26 states. Word has length 198 [2018-11-28 12:12:51,292 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-28 12:12:51,293 INFO L225 Difference]: With dead ends: 1033 [2018-11-28 12:12:51,293 INFO L226 Difference]: Without dead ends: 1031 [2018-11-28 12:12:51,294 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 258 GetRequests, 197 SyntacticMatches, 3 SemanticMatches, 58 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 786 ImplicationChecksByTransitivity, 0.8s TimeCoverageRelationStatistics Valid=551, Invalid=2989, Unknown=0, NotChecked=0, Total=3540 [2018-11-28 12:12:51,294 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1031 states. [2018-11-28 12:12:51,319 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1031 to 933. [2018-11-28 12:12:51,319 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 933 states. [2018-11-28 12:12:51,320 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 933 states to 933 states and 1311 transitions. [2018-11-28 12:12:51,320 INFO L78 Accepts]: Start accepts. Automaton has 933 states and 1311 transitions. Word has length 198 [2018-11-28 12:12:51,320 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-28 12:12:51,320 INFO L480 AbstractCegarLoop]: Abstraction has 933 states and 1311 transitions. [2018-11-28 12:12:51,320 INFO L481 AbstractCegarLoop]: Interpolant automaton has 26 states. [2018-11-28 12:12:51,320 INFO L276 IsEmpty]: Start isEmpty. Operand 933 states and 1311 transitions. [2018-11-28 12:12:51,321 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 216 [2018-11-28 12:12:51,321 INFO L394 BasicCegarLoop]: Found error trace [2018-11-28 12:12:51,321 INFO L402 BasicCegarLoop]: trace histogram [19, 18, 18, 13, 13, 8, 5, 5, 5, 5, 5, 5, 5, 5, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-28 12:12:51,321 INFO L423 AbstractCegarLoop]: === Iteration 40 === [mainErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-28 12:12:51,321 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-28 12:12:51,321 INFO L82 PathProgramCache]: Analyzing trace with hash -699066829, now seen corresponding path program 4 times [2018-11-28 12:12:51,322 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-28 12:12:51,322 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-28 12:12:51,322 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 12:12:51,322 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-28 12:12:51,322 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 12:12:51,344 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-28 12:12:51,477 INFO L134 CoverageAnalysis]: Checked inductivity of 1010 backedges. 128 proven. 842 refuted. 0 times theorem prover too weak. 40 trivial. 0 not checked. [2018-11-28 12:12:51,477 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-28 12:12:51,477 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_907111b8-e5c3-4c9a-8b01-db5944a86240/bin-2019/uautomizer/z3 Starting monitored process 33 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 33 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-28 12:12:51,487 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-11-28 12:12:51,619 INFO L249 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-11-28 12:12:51,620 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-11-28 12:12:51,623 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-28 12:12:51,647 INFO L134 CoverageAnalysis]: Checked inductivity of 1010 backedges. 128 proven. 842 refuted. 0 times theorem prover too weak. 40 trivial. 0 not checked. [2018-11-28 12:12:51,662 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-11-28 12:12:51,662 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [12, 12] total 12 [2018-11-28 12:12:51,663 INFO L459 AbstractCegarLoop]: Interpolant automaton has 12 states [2018-11-28 12:12:51,663 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 12 interpolants. [2018-11-28 12:12:51,663 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=66, Invalid=66, Unknown=0, NotChecked=0, Total=132 [2018-11-28 12:12:51,663 INFO L87 Difference]: Start difference. First operand 933 states and 1311 transitions. Second operand 12 states. [2018-11-28 12:12:51,782 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-28 12:12:51,782 INFO L93 Difference]: Finished difference Result 1127 states and 1564 transitions. [2018-11-28 12:12:51,785 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 12 states. [2018-11-28 12:12:51,785 INFO L78 Accepts]: Start accepts. Automaton has 12 states. Word has length 215 [2018-11-28 12:12:51,786 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-28 12:12:51,788 INFO L225 Difference]: With dead ends: 1127 [2018-11-28 12:12:51,788 INFO L226 Difference]: Without dead ends: 1043 [2018-11-28 12:12:51,788 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 234 GetRequests, 224 SyntacticMatches, 0 SemanticMatches, 10 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=66, Invalid=66, Unknown=0, NotChecked=0, Total=132 [2018-11-28 12:12:51,789 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1043 states. [2018-11-28 12:12:51,817 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1043 to 1011. [2018-11-28 12:12:51,817 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1011 states. [2018-11-28 12:12:51,819 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1011 states to 1011 states and 1418 transitions. [2018-11-28 12:12:51,819 INFO L78 Accepts]: Start accepts. Automaton has 1011 states and 1418 transitions. Word has length 215 [2018-11-28 12:12:51,819 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-28 12:12:51,819 INFO L480 AbstractCegarLoop]: Abstraction has 1011 states and 1418 transitions. [2018-11-28 12:12:51,819 INFO L481 AbstractCegarLoop]: Interpolant automaton has 12 states. [2018-11-28 12:12:51,819 INFO L276 IsEmpty]: Start isEmpty. Operand 1011 states and 1418 transitions. [2018-11-28 12:12:51,820 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 244 [2018-11-28 12:12:51,820 INFO L394 BasicCegarLoop]: Found error trace [2018-11-28 12:12:51,820 INFO L402 BasicCegarLoop]: trace histogram [21, 20, 20, 15, 15, 10, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 4, 4, 4, 4, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-28 12:12:51,820 INFO L423 AbstractCegarLoop]: === Iteration 41 === [mainErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-28 12:12:51,821 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-28 12:12:51,821 INFO L82 PathProgramCache]: Analyzing trace with hash 408795747, now seen corresponding path program 2 times [2018-11-28 12:12:51,821 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-28 12:12:51,821 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-28 12:12:51,821 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 12:12:51,821 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-28 12:12:51,822 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 12:12:51,837 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-28 12:12:51,934 INFO L134 CoverageAnalysis]: Checked inductivity of 1283 backedges. 159 proven. 1078 refuted. 0 times theorem prover too weak. 46 trivial. 0 not checked. [2018-11-28 12:12:51,935 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-28 12:12:51,935 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_907111b8-e5c3-4c9a-8b01-db5944a86240/bin-2019/uautomizer/z3 Starting monitored process 34 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 34 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-28 12:12:51,954 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-11-28 12:12:52,046 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2018-11-28 12:12:52,046 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-11-28 12:12:52,049 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-28 12:12:52,078 INFO L134 CoverageAnalysis]: Checked inductivity of 1283 backedges. 159 proven. 1078 refuted. 0 times theorem prover too weak. 46 trivial. 0 not checked. [2018-11-28 12:12:52,093 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-11-28 12:12:52,093 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [13, 13] total 13 [2018-11-28 12:12:52,093 INFO L459 AbstractCegarLoop]: Interpolant automaton has 13 states [2018-11-28 12:12:52,093 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 13 interpolants. [2018-11-28 12:12:52,093 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=78, Invalid=78, Unknown=0, NotChecked=0, Total=156 [2018-11-28 12:12:52,094 INFO L87 Difference]: Start difference. First operand 1011 states and 1418 transitions. Second operand 13 states. [2018-11-28 12:12:52,210 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-28 12:12:52,210 INFO L93 Difference]: Finished difference Result 1677 states and 2346 transitions. [2018-11-28 12:12:52,211 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 13 states. [2018-11-28 12:12:52,211 INFO L78 Accepts]: Start accepts. Automaton has 13 states. Word has length 243 [2018-11-28 12:12:52,211 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-28 12:12:52,212 INFO L225 Difference]: With dead ends: 1677 [2018-11-28 12:12:52,212 INFO L226 Difference]: Without dead ends: 1124 [2018-11-28 12:12:52,213 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 264 GetRequests, 253 SyntacticMatches, 0 SemanticMatches, 11 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=78, Invalid=78, Unknown=0, NotChecked=0, Total=156 [2018-11-28 12:12:52,213 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1124 states. [2018-11-28 12:12:52,255 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1124 to 1089. [2018-11-28 12:12:52,255 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1089 states. [2018-11-28 12:12:52,257 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1089 states to 1089 states and 1529 transitions. [2018-11-28 12:12:52,257 INFO L78 Accepts]: Start accepts. Automaton has 1089 states and 1529 transitions. Word has length 243 [2018-11-28 12:12:52,257 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-28 12:12:52,257 INFO L480 AbstractCegarLoop]: Abstraction has 1089 states and 1529 transitions. [2018-11-28 12:12:52,257 INFO L481 AbstractCegarLoop]: Interpolant automaton has 13 states. [2018-11-28 12:12:52,257 INFO L276 IsEmpty]: Start isEmpty. Operand 1089 states and 1529 transitions. [2018-11-28 12:12:52,259 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 262 [2018-11-28 12:12:52,259 INFO L394 BasicCegarLoop]: Found error trace [2018-11-28 12:12:52,259 INFO L402 BasicCegarLoop]: trace histogram [23, 22, 22, 16, 16, 10, 6, 6, 6, 6, 6, 6, 6, 6, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-28 12:12:52,259 INFO L423 AbstractCegarLoop]: === Iteration 42 === [mainErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-28 12:12:52,259 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-28 12:12:52,259 INFO L82 PathProgramCache]: Analyzing trace with hash 1318987330, now seen corresponding path program 5 times [2018-11-28 12:12:52,259 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-28 12:12:52,259 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-28 12:12:52,260 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 12:12:52,260 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-28 12:12:52,260 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 12:12:52,281 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-28 12:12:52,436 INFO L134 CoverageAnalysis]: Checked inductivity of 1530 backedges. 158 proven. 1322 refuted. 0 times theorem prover too weak. 50 trivial. 0 not checked. [2018-11-28 12:12:52,436 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-28 12:12:52,437 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_907111b8-e5c3-4c9a-8b01-db5944a86240/bin-2019/uautomizer/z3 Starting monitored process 35 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 35 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-28 12:12:52,443 INFO L103 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-11-28 12:12:52,610 INFO L249 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 14 check-sat command(s) [2018-11-28 12:12:52,610 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-11-28 12:12:52,615 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-28 12:12:52,669 INFO L134 CoverageAnalysis]: Checked inductivity of 1530 backedges. 158 proven. 1322 refuted. 0 times theorem prover too weak. 50 trivial. 0 not checked. [2018-11-28 12:12:52,684 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-11-28 12:12:52,684 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [14, 14] total 14 [2018-11-28 12:12:52,684 INFO L459 AbstractCegarLoop]: Interpolant automaton has 14 states [2018-11-28 12:12:52,684 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 14 interpolants. [2018-11-28 12:12:52,684 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=91, Invalid=91, Unknown=0, NotChecked=0, Total=182 [2018-11-28 12:12:52,685 INFO L87 Difference]: Start difference. First operand 1089 states and 1529 transitions. Second operand 14 states. [2018-11-28 12:12:52,817 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-28 12:12:52,817 INFO L93 Difference]: Finished difference Result 1289 states and 1786 transitions. [2018-11-28 12:12:52,817 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 14 states. [2018-11-28 12:12:52,817 INFO L78 Accepts]: Start accepts. Automaton has 14 states. Word has length 261 [2018-11-28 12:12:52,817 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-28 12:12:52,819 INFO L225 Difference]: With dead ends: 1289 [2018-11-28 12:12:52,819 INFO L226 Difference]: Without dead ends: 1205 [2018-11-28 12:12:52,820 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 284 GetRequests, 272 SyntacticMatches, 0 SemanticMatches, 12 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=91, Invalid=91, Unknown=0, NotChecked=0, Total=182 [2018-11-28 12:12:52,820 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1205 states. [2018-11-28 12:12:52,849 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1205 to 1167. [2018-11-28 12:12:52,850 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1167 states. [2018-11-28 12:12:52,850 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1167 states to 1167 states and 1636 transitions. [2018-11-28 12:12:52,850 INFO L78 Accepts]: Start accepts. Automaton has 1167 states and 1636 transitions. Word has length 261 [2018-11-28 12:12:52,851 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-28 12:12:52,851 INFO L480 AbstractCegarLoop]: Abstraction has 1167 states and 1636 transitions. [2018-11-28 12:12:52,851 INFO L481 AbstractCegarLoop]: Interpolant automaton has 14 states. [2018-11-28 12:12:52,851 INFO L276 IsEmpty]: Start isEmpty. Operand 1167 states and 1636 transitions. [2018-11-28 12:12:52,852 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 290 [2018-11-28 12:12:52,852 INFO L394 BasicCegarLoop]: Found error trace [2018-11-28 12:12:52,852 INFO L402 BasicCegarLoop]: trace histogram [25, 24, 24, 18, 18, 12, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 5, 5, 5, 5, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-28 12:12:52,852 INFO L423 AbstractCegarLoop]: === Iteration 43 === [mainErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-28 12:12:52,852 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-28 12:12:52,853 INFO L82 PathProgramCache]: Analyzing trace with hash 589114866, now seen corresponding path program 3 times [2018-11-28 12:12:52,853 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-28 12:12:52,853 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-28 12:12:52,853 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 12:12:52,853 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-28 12:12:52,853 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 12:12:52,876 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-28 12:12:53,064 INFO L134 CoverageAnalysis]: Checked inductivity of 1863 backedges. 193 proven. 1614 refuted. 0 times theorem prover too weak. 56 trivial. 0 not checked. [2018-11-28 12:12:53,064 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-28 12:12:53,064 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_907111b8-e5c3-4c9a-8b01-db5944a86240/bin-2019/uautomizer/z3 Starting monitored process 36 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 36 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-28 12:12:53,074 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-11-28 12:12:53,141 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 5 check-sat command(s) [2018-11-28 12:12:53,141 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-11-28 12:12:53,146 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-28 12:12:53,340 INFO L134 CoverageAnalysis]: Checked inductivity of 1863 backedges. 469 proven. 4 refuted. 0 times theorem prover too weak. 1390 trivial. 0 not checked. [2018-11-28 12:12:53,365 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-11-28 12:12:53,365 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [15, 6] total 19 [2018-11-28 12:12:53,365 INFO L459 AbstractCegarLoop]: Interpolant automaton has 19 states [2018-11-28 12:12:53,366 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 19 interpolants. [2018-11-28 12:12:53,366 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=114, Invalid=228, Unknown=0, NotChecked=0, Total=342 [2018-11-28 12:12:53,366 INFO L87 Difference]: Start difference. First operand 1167 states and 1636 transitions. Second operand 19 states. [2018-11-28 12:12:54,016 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-28 12:12:54,016 INFO L93 Difference]: Finished difference Result 1316 states and 1834 transitions. [2018-11-28 12:12:54,016 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 35 states. [2018-11-28 12:12:54,017 INFO L78 Accepts]: Start accepts. Automaton has 19 states. Word has length 289 [2018-11-28 12:12:54,017 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-28 12:12:54,017 INFO L225 Difference]: With dead ends: 1316 [2018-11-28 12:12:54,018 INFO L226 Difference]: Without dead ends: 685 [2018-11-28 12:12:54,018 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 359 GetRequests, 312 SyntacticMatches, 0 SemanticMatches, 47 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 512 ImplicationChecksByTransitivity, 0.6s TimeCoverageRelationStatistics Valid=576, Invalid=1776, Unknown=0, NotChecked=0, Total=2352 [2018-11-28 12:12:54,019 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 685 states. [2018-11-28 12:12:54,040 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 685 to 662. [2018-11-28 12:12:54,040 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 662 states. [2018-11-28 12:12:54,040 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 662 states to 662 states and 909 transitions. [2018-11-28 12:12:54,041 INFO L78 Accepts]: Start accepts. Automaton has 662 states and 909 transitions. Word has length 289 [2018-11-28 12:12:54,041 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-28 12:12:54,041 INFO L480 AbstractCegarLoop]: Abstraction has 662 states and 909 transitions. [2018-11-28 12:12:54,041 INFO L481 AbstractCegarLoop]: Interpolant automaton has 19 states. [2018-11-28 12:12:54,041 INFO L276 IsEmpty]: Start isEmpty. Operand 662 states and 909 transitions. [2018-11-28 12:12:54,042 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 354 [2018-11-28 12:12:54,042 INFO L394 BasicCegarLoop]: Found error trace [2018-11-28 12:12:54,042 INFO L402 BasicCegarLoop]: trace histogram [31, 30, 30, 22, 22, 14, 8, 8, 8, 8, 8, 8, 8, 8, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-28 12:12:54,042 INFO L423 AbstractCegarLoop]: === Iteration 44 === [mainErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-28 12:12:54,042 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-28 12:12:54,042 INFO L82 PathProgramCache]: Analyzing trace with hash 927920032, now seen corresponding path program 6 times [2018-11-28 12:12:54,042 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-28 12:12:54,042 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-28 12:12:54,043 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 12:12:54,043 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-28 12:12:54,043 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 12:12:54,069 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-28 12:12:54,381 INFO L134 CoverageAnalysis]: Checked inductivity of 2894 backedges. 218 proven. 2606 refuted. 0 times theorem prover too weak. 70 trivial. 0 not checked. [2018-11-28 12:12:54,381 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-28 12:12:54,381 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_907111b8-e5c3-4c9a-8b01-db5944a86240/bin-2019/uautomizer/z3 Starting monitored process 37 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 37 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-28 12:12:54,389 INFO L103 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-11-28 12:12:54,616 INFO L249 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 21 check-sat command(s) [2018-11-28 12:12:54,616 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-11-28 12:12:54,622 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-28 12:12:54,675 INFO L134 CoverageAnalysis]: Checked inductivity of 2894 backedges. 218 proven. 2606 refuted. 0 times theorem prover too weak. 70 trivial. 0 not checked. [2018-11-28 12:12:54,701 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-11-28 12:12:54,701 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [18, 18] total 18 [2018-11-28 12:12:54,701 INFO L459 AbstractCegarLoop]: Interpolant automaton has 18 states [2018-11-28 12:12:54,701 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 18 interpolants. [2018-11-28 12:12:54,701 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=153, Invalid=153, Unknown=0, NotChecked=0, Total=306 [2018-11-28 12:12:54,701 INFO L87 Difference]: Start difference. First operand 662 states and 909 transitions. Second operand 18 states. [2018-11-28 12:12:54,814 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-28 12:12:54,814 INFO L93 Difference]: Finished difference Result 867 states and 1192 transitions. [2018-11-28 12:12:54,814 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 18 states. [2018-11-28 12:12:54,814 INFO L78 Accepts]: Start accepts. Automaton has 18 states. Word has length 353 [2018-11-28 12:12:54,814 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-28 12:12:54,815 INFO L225 Difference]: With dead ends: 867 [2018-11-28 12:12:54,815 INFO L226 Difference]: Without dead ends: 783 [2018-11-28 12:12:54,815 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 384 GetRequests, 368 SyntacticMatches, 0 SemanticMatches, 16 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=153, Invalid=153, Unknown=0, NotChecked=0, Total=306 [2018-11-28 12:12:54,816 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 783 states. [2018-11-28 12:12:54,834 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 783 to 740. [2018-11-28 12:12:54,834 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 740 states. [2018-11-28 12:12:54,835 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 740 states to 740 states and 1016 transitions. [2018-11-28 12:12:54,835 INFO L78 Accepts]: Start accepts. Automaton has 740 states and 1016 transitions. Word has length 353 [2018-11-28 12:12:54,836 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-28 12:12:54,836 INFO L480 AbstractCegarLoop]: Abstraction has 740 states and 1016 transitions. [2018-11-28 12:12:54,836 INFO L481 AbstractCegarLoop]: Interpolant automaton has 18 states. [2018-11-28 12:12:54,836 INFO L276 IsEmpty]: Start isEmpty. Operand 740 states and 1016 transitions. [2018-11-28 12:12:54,837 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 400 [2018-11-28 12:12:54,837 INFO L394 BasicCegarLoop]: Found error trace [2018-11-28 12:12:54,838 INFO L402 BasicCegarLoop]: trace histogram [35, 34, 34, 25, 25, 16, 9, 9, 9, 9, 9, 9, 9, 9, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-28 12:12:54,838 INFO L423 AbstractCegarLoop]: === Iteration 45 === [mainErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-28 12:12:54,838 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-28 12:12:54,838 INFO L82 PathProgramCache]: Analyzing trace with hash 1934002415, now seen corresponding path program 7 times [2018-11-28 12:12:54,838 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-28 12:12:54,838 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-28 12:12:54,839 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 12:12:54,839 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-28 12:12:54,839 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 12:12:55,199 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-28 12:12:55,614 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-28 12:12:55,684 INFO L469 BasicCegarLoop]: Counterexample might be feasible [2018-11-28 12:12:55,799 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction CFG 28.11 12:12:55 BoogieIcfgContainer [2018-11-28 12:12:55,799 INFO L132 PluginConnector]: ------------------------ END TraceAbstraction---------------------------- [2018-11-28 12:12:55,799 INFO L113 PluginConnector]: ------------------------Witness Printer---------------------------- [2018-11-28 12:12:55,799 INFO L271 PluginConnector]: Initializing Witness Printer... [2018-11-28 12:12:55,799 INFO L276 PluginConnector]: Witness Printer initialized [2018-11-28 12:12:55,800 INFO L185 PluginConnector]: Executing the observer RCFGCatcher from plugin Witness Printer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 28.11 12:12:31" (3/4) ... [2018-11-28 12:12:55,802 INFO L138 WitnessPrinter]: Generating witness for reachability counterexample [2018-11-28 12:12:55,970 INFO L145 WitnessManager]: Wrote witness to /tmp/vcloud-vcloud-master/worker/working_dir_907111b8-e5c3-4c9a-8b01-db5944a86240/bin-2019/uautomizer/witness.graphml [2018-11-28 12:12:55,970 INFO L132 PluginConnector]: ------------------------ END Witness Printer---------------------------- [2018-11-28 12:12:55,970 INFO L168 Benchmark]: Toolchain (without parser) took 25436.88 ms. Allocated memory was 1.0 GB in the beginning and 1.8 GB in the end (delta: 731.4 MB). Free memory was 954.9 MB in the beginning and 1.0 GB in the end (delta: -80.0 MB). Peak memory consumption was 651.4 MB. Max. memory is 11.5 GB. [2018-11-28 12:12:55,972 INFO L168 Benchmark]: CDTParser took 0.11 ms. Allocated memory is still 1.0 GB. Free memory is still 976.9 MB. There was no memory consumed. Max. memory is 11.5 GB. [2018-11-28 12:12:55,972 INFO L168 Benchmark]: CACSL2BoogieTranslator took 308.02 ms. Allocated memory was 1.0 GB in the beginning and 1.2 GB in the end (delta: 130.0 MB). Free memory was 949.5 MB in the beginning and 1.1 GB in the end (delta: -176.8 MB). Peak memory consumption was 32.3 MB. Max. memory is 11.5 GB. [2018-11-28 12:12:55,972 INFO L168 Benchmark]: Boogie Procedure Inliner took 15.55 ms. Allocated memory is still 1.2 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 2.7 MB). Peak memory consumption was 2.7 MB. Max. memory is 11.5 GB. [2018-11-28 12:12:55,972 INFO L168 Benchmark]: Boogie Preprocessor took 34.96 ms. Allocated memory is still 1.2 GB. Free memory is still 1.1 GB. There was no memory consumed. Max. memory is 11.5 GB. [2018-11-28 12:12:55,972 INFO L168 Benchmark]: RCFGBuilder took 590.20 ms. Allocated memory is still 1.2 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 54.6 MB). Peak memory consumption was 54.6 MB. Max. memory is 11.5 GB. [2018-11-28 12:12:55,973 INFO L168 Benchmark]: TraceAbstraction took 24314.41 ms. Allocated memory was 1.2 GB in the beginning and 1.8 GB in the end (delta: 601.4 MB). Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: -475.9 kB). Peak memory consumption was 600.9 MB. Max. memory is 11.5 GB. [2018-11-28 12:12:55,973 INFO L168 Benchmark]: Witness Printer took 170.57 ms. Allocated memory is still 1.8 GB. Free memory was 1.1 GB in the beginning and 1.0 GB in the end (delta: 34.7 MB). Peak memory consumption was 34.7 MB. Max. memory is 11.5 GB. [2018-11-28 12:12:55,974 INFO L336 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.11 ms. Allocated memory is still 1.0 GB. Free memory is still 976.9 MB. There was no memory consumed. Max. memory is 11.5 GB. * CACSL2BoogieTranslator took 308.02 ms. Allocated memory was 1.0 GB in the beginning and 1.2 GB in the end (delta: 130.0 MB). Free memory was 949.5 MB in the beginning and 1.1 GB in the end (delta: -176.8 MB). Peak memory consumption was 32.3 MB. Max. memory is 11.5 GB. * Boogie Procedure Inliner took 15.55 ms. Allocated memory is still 1.2 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 2.7 MB). Peak memory consumption was 2.7 MB. Max. memory is 11.5 GB. * Boogie Preprocessor took 34.96 ms. Allocated memory is still 1.2 GB. Free memory is still 1.1 GB. There was no memory consumed. Max. memory is 11.5 GB. * RCFGBuilder took 590.20 ms. Allocated memory is still 1.2 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 54.6 MB). Peak memory consumption was 54.6 MB. Max. memory is 11.5 GB. * TraceAbstraction took 24314.41 ms. Allocated memory was 1.2 GB in the beginning and 1.8 GB in the end (delta: 601.4 MB). Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: -475.9 kB). Peak memory consumption was 600.9 MB. Max. memory is 11.5 GB. * Witness Printer took 170.57 ms. Allocated memory is still 1.8 GB. Free memory was 1.1 GB in the beginning and 1.0 GB in the end (delta: 34.7 MB). Peak memory consumption was 34.7 MB. Max. memory is 11.5 GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - CounterExampleResult [Line: 569]: a call of __VERIFIER_error() is reachable a call of __VERIFIER_error() is reachable We found a FailurePath: [L5] int m_Protocol = 1; [L6] int m_msg_2 = 2; [L7] int m_recv_ack_2 = 3; [L8] int m_msg_1_1 = 4; [L9] int m_msg_1_2 = 5; [L10] int m_recv_ack_1_1 = 6; [L11] int m_recv_ack_1_2 = 7; VAL [\old(m_msg_1_1)=21, \old(m_msg_1_2)=18, \old(m_msg_2)=19, \old(m_Protocol)=23, \old(m_recv_ack_1_1)=20, \old(m_recv_ack_1_2)=22, \old(m_recv_ack_2)=24, m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3] [L16] int q = 0; [L17] int method_id; [L20] int this_expect = 0; [L21] int this_buffer_empty = 0; VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, q=0, this_buffer_empty=0, this_expect=0] [L24] COND TRUE 1 [L27] int P1=__VERIFIER_nondet_int(); [L28] int P2=__VERIFIER_nondet_int(); [L29] int P3=__VERIFIER_nondet_int(); [L30] int P4=__VERIFIER_nondet_int(); [L31] int P5=__VERIFIER_nondet_int(); [L32] int P6=__VERIFIER_nondet_int(); [L33] int P7=__VERIFIER_nondet_int(); [L34] int P8=__VERIFIER_nondet_int(); [L35] int P9=__VERIFIER_nondet_int(); [L38] COND FALSE !(this_expect > 16) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, P1=0, P2=0, P3=0, P4=0, P5=0, P6=0, P7=0, P8=1, P9=0, q=0, this_buffer_empty=0, this_expect=0] [L43] COND TRUE q == 0 [L44] COND TRUE __VERIFIER_nondet_int() [L48] method_id = 1 VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=1, P1=0, P2=0, P3=0, P4=0, P5=0, P6=0, P7=0, P8=1, P9=0, q=0, this_buffer_empty=0, this_expect=0] [L50] COND FALSE !(0) [L54] q = 1 [L56] this_expect=0 [L56] this_buffer_empty=1 VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=1, P1=0, P2=0, P3=0, P4=0, P5=0, P6=0, P7=0, P8=1, P9=0, q=1, this_buffer_empty=1, this_expect=0] [L24] COND TRUE 1 [L27] int P1=__VERIFIER_nondet_int(); [L28] int P2=__VERIFIER_nondet_int(); [L29] int P3=__VERIFIER_nondet_int(); [L30] int P4=__VERIFIER_nondet_int(); [L31] int P5=__VERIFIER_nondet_int(); [L32] int P6=__VERIFIER_nondet_int(); [L33] int P7=__VERIFIER_nondet_int(); [L34] int P8=__VERIFIER_nondet_int(); [L35] int P9=__VERIFIER_nondet_int(); [L38] COND FALSE !(this_expect > 16) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=1, P1=0, P2=0, P3=0, P4=0, P5=0, P6=0, P7=0, P8=0, P9=0, q=1, this_buffer_empty=1, this_expect=0] [L43] COND FALSE !(q == 0) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=1, P1=0, P2=0, P3=0, P4=0, P5=0, P6=0, P7=0, P8=0, P9=0, q=1, this_buffer_empty=1, this_expect=0] [L63] COND TRUE q == 1 [L64] COND TRUE __VERIFIER_nondet_int() [L66] COND TRUE !((P1 % 2) != (0 % 2)) [L68] method_id = 2 VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=2, P1=0, P2=0, P3=0, P4=0, P5=0, P6=0, P7=0, P8=0, P9=0, q=1, this_buffer_empty=1, this_expect=0] [L70] COND FALSE !((((((P1 % 2) != (this_expect % 2)) && (this_buffer_empty == 1)) && !((P1 % 2) != (0 % 2))) || ((this_buffer_empty != 1) && !((P1 % 2) != (0 % 2))))) [L74] q = 3 [L76] this_expect=(this_expect + 1) [L76] this_buffer_empty=(1 - this_buffer_empty) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=2, P1=0, P2=0, P3=0, P4=0, P5=0, P6=0, P7=0, P8=0, P9=0, q=3, this_buffer_empty=0, this_expect=1] [L24] COND TRUE 1 [L27] int P1=__VERIFIER_nondet_int(); [L28] int P2=__VERIFIER_nondet_int(); [L29] int P3=__VERIFIER_nondet_int(); [L30] int P4=__VERIFIER_nondet_int(); [L31] int P5=__VERIFIER_nondet_int(); [L32] int P6=__VERIFIER_nondet_int(); [L33] int P7=__VERIFIER_nondet_int(); [L34] int P8=__VERIFIER_nondet_int(); [L35] int P9=__VERIFIER_nondet_int(); [L38] COND FALSE !(this_expect > 16) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=2, P1=0, P2=0, P3=0, P4=0, P5=0, P6=0, P7=0, P8=0, P9=0, q=3, this_buffer_empty=0, this_expect=1] [L43] COND FALSE !(q == 0) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=2, P1=0, P2=0, P3=0, P4=0, P5=0, P6=0, P7=0, P8=0, P9=0, q=3, this_buffer_empty=0, this_expect=1] [L63] COND FALSE !(q == 1) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=2, P1=0, P2=0, P3=0, P4=0, P5=0, P6=0, P7=0, P8=0, P9=0, q=3, this_buffer_empty=0, this_expect=1] [L163] COND FALSE !(q == 2) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=2, P1=0, P2=0, P3=0, P4=0, P5=0, P6=0, P7=0, P8=0, P9=0, q=3, this_buffer_empty=0, this_expect=1] [L263] COND TRUE q == 3 [L264] COND FALSE !(__VERIFIER_nondet_int()) [L280] COND TRUE __VERIFIER_nondet_int() [L282] COND TRUE !(P1 != (((0 + 1) - 1) % 2)) [L284] method_id = 3 VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=3, P1=0, P2=0, P3=0, P4=0, P5=0, P6=0, P7=0, P8=0, P9=0, q=3, this_buffer_empty=0, this_expect=1] [L286] COND FALSE !((((this_buffer_empty == 1) && !(P3 != (((0 + 1) - 1) % 2))) || (((P3 != ((this_expect - 1) % 2)) && (this_buffer_empty != 1)) && !(P3 != (((0 + 1) - 1) % 2))))) [L290] q = 4 [L292] this_expect=this_expect [L292] this_buffer_empty=(1 - this_buffer_empty) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=3, P1=0, P2=0, P3=0, P4=0, P5=0, P6=0, P7=0, P8=0, P9=0, q=4, this_buffer_empty=1, this_expect=1] [L24] COND TRUE 1 [L27] int P1=__VERIFIER_nondet_int(); [L28] int P2=__VERIFIER_nondet_int(); [L29] int P3=__VERIFIER_nondet_int(); [L30] int P4=__VERIFIER_nondet_int(); [L31] int P5=__VERIFIER_nondet_int(); [L32] int P6=__VERIFIER_nondet_int(); [L33] int P7=__VERIFIER_nondet_int(); [L34] int P8=__VERIFIER_nondet_int(); [L35] int P9=__VERIFIER_nondet_int(); [L38] COND FALSE !(this_expect > 16) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=3, P1=3, P2=0, P3=0, P4=0, P5=0, P6=-1, P7=0, P8=0, P9=0, q=4, this_buffer_empty=1, this_expect=1] [L43] COND FALSE !(q == 0) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=3, P1=3, P2=0, P3=0, P4=0, P5=0, P6=-1, P7=0, P8=0, P9=0, q=4, this_buffer_empty=1, this_expect=1] [L63] COND FALSE !(q == 1) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=3, P1=3, P2=0, P3=0, P4=0, P5=0, P6=-1, P7=0, P8=0, P9=0, q=4, this_buffer_empty=1, this_expect=1] [L163] COND FALSE !(q == 2) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=3, P1=3, P2=0, P3=0, P4=0, P5=0, P6=-1, P7=0, P8=0, P9=0, q=4, this_buffer_empty=1, this_expect=1] [L263] COND FALSE !(q == 3) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=3, P1=3, P2=0, P3=0, P4=0, P5=0, P6=-1, P7=0, P8=0, P9=0, q=4, this_buffer_empty=1, this_expect=1] [L363] COND TRUE q == 4 [L364] COND FALSE !(__VERIFIER_nondet_int()) [L380] COND FALSE !(__VERIFIER_nondet_int()) [L396] COND FALSE !(__VERIFIER_nondet_int()) [L412] COND TRUE __VERIFIER_nondet_int() [L414] COND TRUE (((P1 % 2) != (0 % 2)) && !(((P1 % 2) != ((0 + 1) % 2)) && ((P1 % 2) != (0 % 2)))) [L416] method_id = 5 VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=5, P1=3, P2=0, P3=0, P4=0, P5=0, P6=-1, P7=0, P8=0, P9=0, q=4, this_buffer_empty=1, this_expect=1] [L418] COND FALSE !(((((((P6 % 2) != (this_expect % 2)) && (this_buffer_empty == 1)) && ((P6 % 2) != (0 % 2))) && (((P6 % 2) != (0 % 2)) && !(((P6 % 2) != ((0 + 1) % 2)) && ((P6 % 2) != (0 % 2))))) || (((this_buffer_empty != 1) && ((P6 % 2) != (0 % 2))) && (((P6 % 2) != (0 % 2)) && !(((P6 % 2) != ((0 + 1) % 2)) && ((P6 % 2) != (0 % 2))))))) [L422] q = 5 [L424] this_expect=(this_expect + 1) [L424] this_buffer_empty=(1 - this_buffer_empty) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=5, P1=3, P2=0, P3=0, P4=0, P5=0, P6=-1, P7=0, P8=0, P9=0, q=5, this_buffer_empty=0, this_expect=2] [L24] COND TRUE 1 [L27] int P1=__VERIFIER_nondet_int(); [L28] int P2=__VERIFIER_nondet_int(); [L29] int P3=__VERIFIER_nondet_int(); [L30] int P4=__VERIFIER_nondet_int(); [L31] int P5=__VERIFIER_nondet_int(); [L32] int P6=__VERIFIER_nondet_int(); [L33] int P7=__VERIFIER_nondet_int(); [L34] int P8=__VERIFIER_nondet_int(); [L35] int P9=__VERIFIER_nondet_int(); [L38] COND FALSE !(this_expect > 16) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=5, P1=1, P2=0, P3=0, P4=0, P5=0, P6=0, P7=0, P8=0, P9=1, q=5, this_buffer_empty=0, this_expect=2] [L43] COND FALSE !(q == 0) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=5, P1=1, P2=0, P3=0, P4=0, P5=0, P6=0, P7=0, P8=0, P9=1, q=5, this_buffer_empty=0, this_expect=2] [L63] COND FALSE !(q == 1) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=5, P1=1, P2=0, P3=0, P4=0, P5=0, P6=0, P7=0, P8=0, P9=1, q=5, this_buffer_empty=0, this_expect=2] [L163] COND FALSE !(q == 2) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=5, P1=1, P2=0, P3=0, P4=0, P5=0, P6=0, P7=0, P8=0, P9=1, q=5, this_buffer_empty=0, this_expect=2] [L263] COND FALSE !(q == 3) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=5, P1=1, P2=0, P3=0, P4=0, P5=0, P6=0, P7=0, P8=0, P9=1, q=5, this_buffer_empty=0, this_expect=2] [L363] COND FALSE !(q == 4) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=5, P1=1, P2=0, P3=0, P4=0, P5=0, P6=0, P7=0, P8=0, P9=1, q=5, this_buffer_empty=0, this_expect=2] [L463] COND TRUE q == 5 [L464] COND FALSE !(__VERIFIER_nondet_int()) [L480] COND FALSE !(__VERIFIER_nondet_int()) [L496] COND FALSE !(__VERIFIER_nondet_int()) [L512] COND FALSE !(__VERIFIER_nondet_int()) [L528] COND FALSE !(__VERIFIER_nondet_int()) [L544] COND TRUE __VERIFIER_nondet_int() [L546] COND TRUE ((P1 != (((0 + 1) - 1) % 2)) && !((P1 != ((((0 + 1) + 1) - 1) % 2)) && (P1 != (((0 + 1) - 1) % 2)))) [L548] method_id = 7 VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=7, P1=1, P2=0, P3=0, P4=0, P5=0, P6=0, P7=0, P8=0, P9=1, q=5, this_buffer_empty=0, this_expect=2] [L550] COND FALSE !(((((this_buffer_empty == 1) && (P9 != (((0 + 1) - 1) % 2))) && ((P9 != (((0 + 1) - 1) % 2)) && !((P9 != ((((0 + 1) + 1) - 1) % 2)) && (P9 != (((0 + 1) - 1) % 2))))) || ((((P9 != ((this_expect - 1) % 2)) && (this_buffer_empty != 1)) && (P9 != (((0 + 1) - 1) % 2))) && ((P9 != (((0 + 1) - 1) % 2)) && !((P9 != ((((0 + 1) + 1) - 1) % 2)) && (P9 != (((0 + 1) - 1) % 2))))))) [L554] q = 1 [L556] this_expect=this_expect [L556] this_buffer_empty=(1 - this_buffer_empty) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=7, P1=1, P2=0, P3=0, P4=0, P5=0, P6=0, P7=0, P8=0, P9=1, q=1, this_buffer_empty=1, this_expect=2] [L24] COND TRUE 1 [L27] int P1=__VERIFIER_nondet_int(); [L28] int P2=__VERIFIER_nondet_int(); [L29] int P3=__VERIFIER_nondet_int(); [L30] int P4=__VERIFIER_nondet_int(); [L31] int P5=__VERIFIER_nondet_int(); [L32] int P6=__VERIFIER_nondet_int(); [L33] int P7=__VERIFIER_nondet_int(); [L34] int P8=__VERIFIER_nondet_int(); [L35] int P9=__VERIFIER_nondet_int(); [L38] COND FALSE !(this_expect > 16) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=7, P1=-10, P2=0, P3=0, P4=0, P5=0, P6=0, P7=0, P8=0, P9=0, q=1, this_buffer_empty=1, this_expect=2] [L43] COND FALSE !(q == 0) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=7, P1=-10, P2=0, P3=0, P4=0, P5=0, P6=0, P7=0, P8=0, P9=0, q=1, this_buffer_empty=1, this_expect=2] [L63] COND TRUE q == 1 [L64] COND TRUE __VERIFIER_nondet_int() [L66] COND TRUE !((P1 % 2) != (0 % 2)) [L68] method_id = 2 VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=2, P1=-10, P2=0, P3=0, P4=0, P5=0, P6=0, P7=0, P8=0, P9=0, q=1, this_buffer_empty=1, this_expect=2] [L70] COND FALSE !((((((P1 % 2) != (this_expect % 2)) && (this_buffer_empty == 1)) && !((P1 % 2) != (0 % 2))) || ((this_buffer_empty != 1) && !((P1 % 2) != (0 % 2))))) [L74] q = 3 [L76] this_expect=(this_expect + 1) [L76] this_buffer_empty=(1 - this_buffer_empty) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=2, P1=-10, P2=0, P3=0, P4=0, P5=0, P6=0, P7=0, P8=0, P9=0, q=3, this_buffer_empty=0, this_expect=3] [L24] COND TRUE 1 [L27] int P1=__VERIFIER_nondet_int(); [L28] int P2=__VERIFIER_nondet_int(); [L29] int P3=__VERIFIER_nondet_int(); [L30] int P4=__VERIFIER_nondet_int(); [L31] int P5=__VERIFIER_nondet_int(); [L32] int P6=__VERIFIER_nondet_int(); [L33] int P7=__VERIFIER_nondet_int(); [L34] int P8=__VERIFIER_nondet_int(); [L35] int P9=__VERIFIER_nondet_int(); [L38] COND FALSE !(this_expect > 16) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=2, P1=0, P2=0, P3=1, P4=0, P5=0, P6=0, P7=0, P8=0, P9=0, q=3, this_buffer_empty=0, this_expect=3] [L43] COND FALSE !(q == 0) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=2, P1=0, P2=0, P3=1, P4=0, P5=0, P6=0, P7=0, P8=0, P9=0, q=3, this_buffer_empty=0, this_expect=3] [L63] COND FALSE !(q == 1) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=2, P1=0, P2=0, P3=1, P4=0, P5=0, P6=0, P7=0, P8=0, P9=0, q=3, this_buffer_empty=0, this_expect=3] [L163] COND FALSE !(q == 2) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=2, P1=0, P2=0, P3=1, P4=0, P5=0, P6=0, P7=0, P8=0, P9=0, q=3, this_buffer_empty=0, this_expect=3] [L263] COND TRUE q == 3 [L264] COND FALSE !(__VERIFIER_nondet_int()) [L280] COND TRUE __VERIFIER_nondet_int() [L282] COND TRUE !(P1 != (((0 + 1) - 1) % 2)) [L284] method_id = 3 VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=3, P1=0, P2=0, P3=1, P4=0, P5=0, P6=0, P7=0, P8=0, P9=0, q=3, this_buffer_empty=0, this_expect=3] [L286] COND FALSE !((((this_buffer_empty == 1) && !(P3 != (((0 + 1) - 1) % 2))) || (((P3 != ((this_expect - 1) % 2)) && (this_buffer_empty != 1)) && !(P3 != (((0 + 1) - 1) % 2))))) [L290] q = 4 [L292] this_expect=this_expect [L292] this_buffer_empty=(1 - this_buffer_empty) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=3, P1=0, P2=0, P3=1, P4=0, P5=0, P6=0, P7=0, P8=0, P9=0, q=4, this_buffer_empty=1, this_expect=3] [L24] COND TRUE 1 [L27] int P1=__VERIFIER_nondet_int(); [L28] int P2=__VERIFIER_nondet_int(); [L29] int P3=__VERIFIER_nondet_int(); [L30] int P4=__VERIFIER_nondet_int(); [L31] int P5=__VERIFIER_nondet_int(); [L32] int P6=__VERIFIER_nondet_int(); [L33] int P7=__VERIFIER_nondet_int(); [L34] int P8=__VERIFIER_nondet_int(); [L35] int P9=__VERIFIER_nondet_int(); [L38] COND FALSE !(this_expect > 16) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=3, P1=5, P2=0, P3=0, P4=0, P5=0, P6=-2, P7=0, P8=0, P9=0, q=4, this_buffer_empty=1, this_expect=3] [L43] COND FALSE !(q == 0) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=3, P1=5, P2=0, P3=0, P4=0, P5=0, P6=-2, P7=0, P8=0, P9=0, q=4, this_buffer_empty=1, this_expect=3] [L63] COND FALSE !(q == 1) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=3, P1=5, P2=0, P3=0, P4=0, P5=0, P6=-2, P7=0, P8=0, P9=0, q=4, this_buffer_empty=1, this_expect=3] [L163] COND FALSE !(q == 2) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=3, P1=5, P2=0, P3=0, P4=0, P5=0, P6=-2, P7=0, P8=0, P9=0, q=4, this_buffer_empty=1, this_expect=3] [L263] COND FALSE !(q == 3) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=3, P1=5, P2=0, P3=0, P4=0, P5=0, P6=-2, P7=0, P8=0, P9=0, q=4, this_buffer_empty=1, this_expect=3] [L363] COND TRUE q == 4 [L364] COND FALSE !(__VERIFIER_nondet_int()) [L380] COND FALSE !(__VERIFIER_nondet_int()) [L396] COND FALSE !(__VERIFIER_nondet_int()) [L412] COND TRUE __VERIFIER_nondet_int() [L414] COND TRUE (((P1 % 2) != (0 % 2)) && !(((P1 % 2) != ((0 + 1) % 2)) && ((P1 % 2) != (0 % 2)))) [L416] method_id = 5 VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=5, P1=5, P2=0, P3=0, P4=0, P5=0, P6=-2, P7=0, P8=0, P9=0, q=4, this_buffer_empty=1, this_expect=3] [L418] COND FALSE !(((((((P6 % 2) != (this_expect % 2)) && (this_buffer_empty == 1)) && ((P6 % 2) != (0 % 2))) && (((P6 % 2) != (0 % 2)) && !(((P6 % 2) != ((0 + 1) % 2)) && ((P6 % 2) != (0 % 2))))) || (((this_buffer_empty != 1) && ((P6 % 2) != (0 % 2))) && (((P6 % 2) != (0 % 2)) && !(((P6 % 2) != ((0 + 1) % 2)) && ((P6 % 2) != (0 % 2))))))) [L422] q = 5 [L424] this_expect=(this_expect + 1) [L424] this_buffer_empty=(1 - this_buffer_empty) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=5, P1=5, P2=0, P3=0, P4=0, P5=0, P6=-2, P7=0, P8=0, P9=0, q=5, this_buffer_empty=0, this_expect=4] [L24] COND TRUE 1 [L27] int P1=__VERIFIER_nondet_int(); [L28] int P2=__VERIFIER_nondet_int(); [L29] int P3=__VERIFIER_nondet_int(); [L30] int P4=__VERIFIER_nondet_int(); [L31] int P5=__VERIFIER_nondet_int(); [L32] int P6=__VERIFIER_nondet_int(); [L33] int P7=__VERIFIER_nondet_int(); [L34] int P8=__VERIFIER_nondet_int(); [L35] int P9=__VERIFIER_nondet_int(); [L38] COND FALSE !(this_expect > 16) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=5, P1=1, P2=0, P3=0, P4=0, P5=0, P6=0, P7=0, P8=0, P9=1, q=5, this_buffer_empty=0, this_expect=4] [L43] COND FALSE !(q == 0) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=5, P1=1, P2=0, P3=0, P4=0, P5=0, P6=0, P7=0, P8=0, P9=1, q=5, this_buffer_empty=0, this_expect=4] [L63] COND FALSE !(q == 1) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=5, P1=1, P2=0, P3=0, P4=0, P5=0, P6=0, P7=0, P8=0, P9=1, q=5, this_buffer_empty=0, this_expect=4] [L163] COND FALSE !(q == 2) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=5, P1=1, P2=0, P3=0, P4=0, P5=0, P6=0, P7=0, P8=0, P9=1, q=5, this_buffer_empty=0, this_expect=4] [L263] COND FALSE !(q == 3) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=5, P1=1, P2=0, P3=0, P4=0, P5=0, P6=0, P7=0, P8=0, P9=1, q=5, this_buffer_empty=0, this_expect=4] [L363] COND FALSE !(q == 4) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=5, P1=1, P2=0, P3=0, P4=0, P5=0, P6=0, P7=0, P8=0, P9=1, q=5, this_buffer_empty=0, this_expect=4] [L463] COND TRUE q == 5 [L464] COND FALSE !(__VERIFIER_nondet_int()) [L480] COND FALSE !(__VERIFIER_nondet_int()) [L496] COND FALSE !(__VERIFIER_nondet_int()) [L512] COND FALSE !(__VERIFIER_nondet_int()) [L528] COND FALSE !(__VERIFIER_nondet_int()) [L544] COND TRUE __VERIFIER_nondet_int() [L546] COND TRUE ((P1 != (((0 + 1) - 1) % 2)) && !((P1 != ((((0 + 1) + 1) - 1) % 2)) && (P1 != (((0 + 1) - 1) % 2)))) [L548] method_id = 7 VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=7, P1=1, P2=0, P3=0, P4=0, P5=0, P6=0, P7=0, P8=0, P9=1, q=5, this_buffer_empty=0, this_expect=4] [L550] COND FALSE !(((((this_buffer_empty == 1) && (P9 != (((0 + 1) - 1) % 2))) && ((P9 != (((0 + 1) - 1) % 2)) && !((P9 != ((((0 + 1) + 1) - 1) % 2)) && (P9 != (((0 + 1) - 1) % 2))))) || ((((P9 != ((this_expect - 1) % 2)) && (this_buffer_empty != 1)) && (P9 != (((0 + 1) - 1) % 2))) && ((P9 != (((0 + 1) - 1) % 2)) && !((P9 != ((((0 + 1) + 1) - 1) % 2)) && (P9 != (((0 + 1) - 1) % 2))))))) [L554] q = 1 [L556] this_expect=this_expect [L556] this_buffer_empty=(1 - this_buffer_empty) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=7, P1=1, P2=0, P3=0, P4=0, P5=0, P6=0, P7=0, P8=0, P9=1, q=1, this_buffer_empty=1, this_expect=4] [L24] COND TRUE 1 [L27] int P1=__VERIFIER_nondet_int(); [L28] int P2=__VERIFIER_nondet_int(); [L29] int P3=__VERIFIER_nondet_int(); [L30] int P4=__VERIFIER_nondet_int(); [L31] int P5=__VERIFIER_nondet_int(); [L32] int P6=__VERIFIER_nondet_int(); [L33] int P7=__VERIFIER_nondet_int(); [L34] int P8=__VERIFIER_nondet_int(); [L35] int P9=__VERIFIER_nondet_int(); [L38] COND FALSE !(this_expect > 16) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=7, P1=0, P2=0, P3=0, P4=0, P5=0, P6=0, P7=0, P8=0, P9=0, q=1, this_buffer_empty=1, this_expect=4] [L43] COND FALSE !(q == 0) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=7, P1=0, P2=0, P3=0, P4=0, P5=0, P6=0, P7=0, P8=0, P9=0, q=1, this_buffer_empty=1, this_expect=4] [L63] COND TRUE q == 1 [L64] COND TRUE __VERIFIER_nondet_int() [L66] COND TRUE !((P1 % 2) != (0 % 2)) [L68] method_id = 2 VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=2, P1=0, P2=0, P3=0, P4=0, P5=0, P6=0, P7=0, P8=0, P9=0, q=1, this_buffer_empty=1, this_expect=4] [L70] COND FALSE !((((((P1 % 2) != (this_expect % 2)) && (this_buffer_empty == 1)) && !((P1 % 2) != (0 % 2))) || ((this_buffer_empty != 1) && !((P1 % 2) != (0 % 2))))) [L74] q = 3 [L76] this_expect=(this_expect + 1) [L76] this_buffer_empty=(1 - this_buffer_empty) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=2, P1=0, P2=0, P3=0, P4=0, P5=0, P6=0, P7=0, P8=0, P9=0, q=3, this_buffer_empty=0, this_expect=5] [L24] COND TRUE 1 [L27] int P1=__VERIFIER_nondet_int(); [L28] int P2=__VERIFIER_nondet_int(); [L29] int P3=__VERIFIER_nondet_int(); [L30] int P4=__VERIFIER_nondet_int(); [L31] int P5=__VERIFIER_nondet_int(); [L32] int P6=__VERIFIER_nondet_int(); [L33] int P7=__VERIFIER_nondet_int(); [L34] int P8=__VERIFIER_nondet_int(); [L35] int P9=__VERIFIER_nondet_int(); [L38] COND FALSE !(this_expect > 16) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=2, P1=0, P2=0, P3=1, P4=0, P5=0, P6=0, P7=0, P8=0, P9=0, q=3, this_buffer_empty=0, this_expect=5] [L43] COND FALSE !(q == 0) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=2, P1=0, P2=0, P3=1, P4=0, P5=0, P6=0, P7=0, P8=0, P9=0, q=3, this_buffer_empty=0, this_expect=5] [L63] COND FALSE !(q == 1) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=2, P1=0, P2=0, P3=1, P4=0, P5=0, P6=0, P7=0, P8=0, P9=0, q=3, this_buffer_empty=0, this_expect=5] [L163] COND FALSE !(q == 2) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=2, P1=0, P2=0, P3=1, P4=0, P5=0, P6=0, P7=0, P8=0, P9=0, q=3, this_buffer_empty=0, this_expect=5] [L263] COND TRUE q == 3 [L264] COND FALSE !(__VERIFIER_nondet_int()) [L280] COND TRUE __VERIFIER_nondet_int() [L282] COND TRUE !(P1 != (((0 + 1) - 1) % 2)) [L284] method_id = 3 VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=3, P1=0, P2=0, P3=1, P4=0, P5=0, P6=0, P7=0, P8=0, P9=0, q=3, this_buffer_empty=0, this_expect=5] [L286] COND FALSE !((((this_buffer_empty == 1) && !(P3 != (((0 + 1) - 1) % 2))) || (((P3 != ((this_expect - 1) % 2)) && (this_buffer_empty != 1)) && !(P3 != (((0 + 1) - 1) % 2))))) [L290] q = 4 [L292] this_expect=this_expect [L292] this_buffer_empty=(1 - this_buffer_empty) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=3, P1=0, P2=0, P3=1, P4=0, P5=0, P6=0, P7=0, P8=0, P9=0, q=4, this_buffer_empty=1, this_expect=5] [L24] COND TRUE 1 [L27] int P1=__VERIFIER_nondet_int(); [L28] int P2=__VERIFIER_nondet_int(); [L29] int P3=__VERIFIER_nondet_int(); [L30] int P4=__VERIFIER_nondet_int(); [L31] int P5=__VERIFIER_nondet_int(); [L32] int P6=__VERIFIER_nondet_int(); [L33] int P7=__VERIFIER_nondet_int(); [L34] int P8=__VERIFIER_nondet_int(); [L35] int P9=__VERIFIER_nondet_int(); [L38] COND FALSE !(this_expect > 16) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=3, P1=11, P2=0, P3=0, P4=0, P5=0, P6=1, P7=0, P8=0, P9=0, q=4, this_buffer_empty=1, this_expect=5] [L43] COND FALSE !(q == 0) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=3, P1=11, P2=0, P3=0, P4=0, P5=0, P6=1, P7=0, P8=0, P9=0, q=4, this_buffer_empty=1, this_expect=5] [L63] COND FALSE !(q == 1) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=3, P1=11, P2=0, P3=0, P4=0, P5=0, P6=1, P7=0, P8=0, P9=0, q=4, this_buffer_empty=1, this_expect=5] [L163] COND FALSE !(q == 2) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=3, P1=11, P2=0, P3=0, P4=0, P5=0, P6=1, P7=0, P8=0, P9=0, q=4, this_buffer_empty=1, this_expect=5] [L263] COND FALSE !(q == 3) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=3, P1=11, P2=0, P3=0, P4=0, P5=0, P6=1, P7=0, P8=0, P9=0, q=4, this_buffer_empty=1, this_expect=5] [L363] COND TRUE q == 4 [L364] COND FALSE !(__VERIFIER_nondet_int()) [L380] COND FALSE !(__VERIFIER_nondet_int()) [L396] COND FALSE !(__VERIFIER_nondet_int()) [L412] COND TRUE __VERIFIER_nondet_int() [L414] COND TRUE (((P1 % 2) != (0 % 2)) && !(((P1 % 2) != ((0 + 1) % 2)) && ((P1 % 2) != (0 % 2)))) [L416] method_id = 5 VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=5, P1=11, P2=0, P3=0, P4=0, P5=0, P6=1, P7=0, P8=0, P9=0, q=4, this_buffer_empty=1, this_expect=5] [L418] COND FALSE !(((((((P6 % 2) != (this_expect % 2)) && (this_buffer_empty == 1)) && ((P6 % 2) != (0 % 2))) && (((P6 % 2) != (0 % 2)) && !(((P6 % 2) != ((0 + 1) % 2)) && ((P6 % 2) != (0 % 2))))) || (((this_buffer_empty != 1) && ((P6 % 2) != (0 % 2))) && (((P6 % 2) != (0 % 2)) && !(((P6 % 2) != ((0 + 1) % 2)) && ((P6 % 2) != (0 % 2))))))) [L422] q = 5 [L424] this_expect=(this_expect + 1) [L424] this_buffer_empty=(1 - this_buffer_empty) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=5, P1=11, P2=0, P3=0, P4=0, P5=0, P6=1, P7=0, P8=0, P9=0, q=5, this_buffer_empty=0, this_expect=6] [L24] COND TRUE 1 [L27] int P1=__VERIFIER_nondet_int(); [L28] int P2=__VERIFIER_nondet_int(); [L29] int P3=__VERIFIER_nondet_int(); [L30] int P4=__VERIFIER_nondet_int(); [L31] int P5=__VERIFIER_nondet_int(); [L32] int P6=__VERIFIER_nondet_int(); [L33] int P7=__VERIFIER_nondet_int(); [L34] int P8=__VERIFIER_nondet_int(); [L35] int P9=__VERIFIER_nondet_int(); [L38] COND FALSE !(this_expect > 16) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=5, P1=1, P2=0, P3=0, P4=0, P5=0, P6=0, P7=0, P8=0, P9=0, q=5, this_buffer_empty=0, this_expect=6] [L43] COND FALSE !(q == 0) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=5, P1=1, P2=0, P3=0, P4=0, P5=0, P6=0, P7=0, P8=0, P9=0, q=5, this_buffer_empty=0, this_expect=6] [L63] COND FALSE !(q == 1) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=5, P1=1, P2=0, P3=0, P4=0, P5=0, P6=0, P7=0, P8=0, P9=0, q=5, this_buffer_empty=0, this_expect=6] [L163] COND FALSE !(q == 2) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=5, P1=1, P2=0, P3=0, P4=0, P5=0, P6=0, P7=0, P8=0, P9=0, q=5, this_buffer_empty=0, this_expect=6] [L263] COND FALSE !(q == 3) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=5, P1=1, P2=0, P3=0, P4=0, P5=0, P6=0, P7=0, P8=0, P9=0, q=5, this_buffer_empty=0, this_expect=6] [L363] COND FALSE !(q == 4) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=5, P1=1, P2=0, P3=0, P4=0, P5=0, P6=0, P7=0, P8=0, P9=0, q=5, this_buffer_empty=0, this_expect=6] [L463] COND TRUE q == 5 [L464] COND FALSE !(__VERIFIER_nondet_int()) [L480] COND FALSE !(__VERIFIER_nondet_int()) [L496] COND FALSE !(__VERIFIER_nondet_int()) [L512] COND FALSE !(__VERIFIER_nondet_int()) [L528] COND FALSE !(__VERIFIER_nondet_int()) [L544] COND TRUE __VERIFIER_nondet_int() [L546] COND TRUE ((P1 != (((0 + 1) - 1) % 2)) && !((P1 != ((((0 + 1) + 1) - 1) % 2)) && (P1 != (((0 + 1) - 1) % 2)))) [L548] method_id = 7 VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=7, P1=1, P2=0, P3=0, P4=0, P5=0, P6=0, P7=0, P8=0, P9=0, q=5, this_buffer_empty=0, this_expect=6] [L550] COND FALSE !(((((this_buffer_empty == 1) && (P9 != (((0 + 1) - 1) % 2))) && ((P9 != (((0 + 1) - 1) % 2)) && !((P9 != ((((0 + 1) + 1) - 1) % 2)) && (P9 != (((0 + 1) - 1) % 2))))) || ((((P9 != ((this_expect - 1) % 2)) && (this_buffer_empty != 1)) && (P9 != (((0 + 1) - 1) % 2))) && ((P9 != (((0 + 1) - 1) % 2)) && !((P9 != ((((0 + 1) + 1) - 1) % 2)) && (P9 != (((0 + 1) - 1) % 2))))))) [L554] q = 1 [L556] this_expect=this_expect [L556] this_buffer_empty=(1 - this_buffer_empty) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=7, P1=1, P2=0, P3=0, P4=0, P5=0, P6=0, P7=0, P8=0, P9=0, q=1, this_buffer_empty=1, this_expect=6] [L24] COND TRUE 1 [L27] int P1=__VERIFIER_nondet_int(); [L28] int P2=__VERIFIER_nondet_int(); [L29] int P3=__VERIFIER_nondet_int(); [L30] int P4=__VERIFIER_nondet_int(); [L31] int P5=__VERIFIER_nondet_int(); [L32] int P6=__VERIFIER_nondet_int(); [L33] int P7=__VERIFIER_nondet_int(); [L34] int P8=__VERIFIER_nondet_int(); [L35] int P9=__VERIFIER_nondet_int(); [L38] COND FALSE !(this_expect > 16) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=7, P1=-4, P2=0, P3=0, P4=0, P5=0, P6=0, P7=0, P8=0, P9=0, q=1, this_buffer_empty=1, this_expect=6] [L43] COND FALSE !(q == 0) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=7, P1=-4, P2=0, P3=0, P4=0, P5=0, P6=0, P7=0, P8=0, P9=0, q=1, this_buffer_empty=1, this_expect=6] [L63] COND TRUE q == 1 [L64] COND TRUE __VERIFIER_nondet_int() [L66] COND TRUE !((P1 % 2) != (0 % 2)) [L68] method_id = 2 VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=2, P1=-4, P2=0, P3=0, P4=0, P5=0, P6=0, P7=0, P8=0, P9=0, q=1, this_buffer_empty=1, this_expect=6] [L70] COND FALSE !((((((P1 % 2) != (this_expect % 2)) && (this_buffer_empty == 1)) && !((P1 % 2) != (0 % 2))) || ((this_buffer_empty != 1) && !((P1 % 2) != (0 % 2))))) [L74] q = 3 [L76] this_expect=(this_expect + 1) [L76] this_buffer_empty=(1 - this_buffer_empty) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=2, P1=-4, P2=0, P3=0, P4=0, P5=0, P6=0, P7=0, P8=0, P9=0, q=3, this_buffer_empty=0, this_expect=7] [L24] COND TRUE 1 [L27] int P1=__VERIFIER_nondet_int(); [L28] int P2=__VERIFIER_nondet_int(); [L29] int P3=__VERIFIER_nondet_int(); [L30] int P4=__VERIFIER_nondet_int(); [L31] int P5=__VERIFIER_nondet_int(); [L32] int P6=__VERIFIER_nondet_int(); [L33] int P7=__VERIFIER_nondet_int(); [L34] int P8=__VERIFIER_nondet_int(); [L35] int P9=__VERIFIER_nondet_int(); [L38] COND FALSE !(this_expect > 16) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=2, P1=0, P2=0, P3=1, P4=0, P5=0, P6=0, P7=0, P8=0, P9=0, q=3, this_buffer_empty=0, this_expect=7] [L43] COND FALSE !(q == 0) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=2, P1=0, P2=0, P3=1, P4=0, P5=0, P6=0, P7=0, P8=0, P9=0, q=3, this_buffer_empty=0, this_expect=7] [L63] COND FALSE !(q == 1) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=2, P1=0, P2=0, P3=1, P4=0, P5=0, P6=0, P7=0, P8=0, P9=0, q=3, this_buffer_empty=0, this_expect=7] [L163] COND FALSE !(q == 2) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=2, P1=0, P2=0, P3=1, P4=0, P5=0, P6=0, P7=0, P8=0, P9=0, q=3, this_buffer_empty=0, this_expect=7] [L263] COND TRUE q == 3 [L264] COND FALSE !(__VERIFIER_nondet_int()) [L280] COND TRUE __VERIFIER_nondet_int() [L282] COND TRUE !(P1 != (((0 + 1) - 1) % 2)) [L284] method_id = 3 VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=3, P1=0, P2=0, P3=1, P4=0, P5=0, P6=0, P7=0, P8=0, P9=0, q=3, this_buffer_empty=0, this_expect=7] [L286] COND FALSE !((((this_buffer_empty == 1) && !(P3 != (((0 + 1) - 1) % 2))) || (((P3 != ((this_expect - 1) % 2)) && (this_buffer_empty != 1)) && !(P3 != (((0 + 1) - 1) % 2))))) [L290] q = 4 [L292] this_expect=this_expect [L292] this_buffer_empty=(1 - this_buffer_empty) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=3, P1=0, P2=0, P3=1, P4=0, P5=0, P6=0, P7=0, P8=0, P9=0, q=4, this_buffer_empty=1, this_expect=7] [L24] COND TRUE 1 [L27] int P1=__VERIFIER_nondet_int(); [L28] int P2=__VERIFIER_nondet_int(); [L29] int P3=__VERIFIER_nondet_int(); [L30] int P4=__VERIFIER_nondet_int(); [L31] int P5=__VERIFIER_nondet_int(); [L32] int P6=__VERIFIER_nondet_int(); [L33] int P7=__VERIFIER_nondet_int(); [L34] int P8=__VERIFIER_nondet_int(); [L35] int P9=__VERIFIER_nondet_int(); [L38] COND FALSE !(this_expect > 16) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=3, P1=13, P2=0, P3=0, P4=0, P5=0, P6=-2, P7=0, P8=0, P9=0, q=4, this_buffer_empty=1, this_expect=7] [L43] COND FALSE !(q == 0) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=3, P1=13, P2=0, P3=0, P4=0, P5=0, P6=-2, P7=0, P8=0, P9=0, q=4, this_buffer_empty=1, this_expect=7] [L63] COND FALSE !(q == 1) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=3, P1=13, P2=0, P3=0, P4=0, P5=0, P6=-2, P7=0, P8=0, P9=0, q=4, this_buffer_empty=1, this_expect=7] [L163] COND FALSE !(q == 2) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=3, P1=13, P2=0, P3=0, P4=0, P5=0, P6=-2, P7=0, P8=0, P9=0, q=4, this_buffer_empty=1, this_expect=7] [L263] COND FALSE !(q == 3) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=3, P1=13, P2=0, P3=0, P4=0, P5=0, P6=-2, P7=0, P8=0, P9=0, q=4, this_buffer_empty=1, this_expect=7] [L363] COND TRUE q == 4 [L364] COND FALSE !(__VERIFIER_nondet_int()) [L380] COND FALSE !(__VERIFIER_nondet_int()) [L396] COND FALSE !(__VERIFIER_nondet_int()) [L412] COND TRUE __VERIFIER_nondet_int() [L414] COND TRUE (((P1 % 2) != (0 % 2)) && !(((P1 % 2) != ((0 + 1) % 2)) && ((P1 % 2) != (0 % 2)))) [L416] method_id = 5 VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=5, P1=13, P2=0, P3=0, P4=0, P5=0, P6=-2, P7=0, P8=0, P9=0, q=4, this_buffer_empty=1, this_expect=7] [L418] COND FALSE !(((((((P6 % 2) != (this_expect % 2)) && (this_buffer_empty == 1)) && ((P6 % 2) != (0 % 2))) && (((P6 % 2) != (0 % 2)) && !(((P6 % 2) != ((0 + 1) % 2)) && ((P6 % 2) != (0 % 2))))) || (((this_buffer_empty != 1) && ((P6 % 2) != (0 % 2))) && (((P6 % 2) != (0 % 2)) && !(((P6 % 2) != ((0 + 1) % 2)) && ((P6 % 2) != (0 % 2))))))) [L422] q = 5 [L424] this_expect=(this_expect + 1) [L424] this_buffer_empty=(1 - this_buffer_empty) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=5, P1=13, P2=0, P3=0, P4=0, P5=0, P6=-2, P7=0, P8=0, P9=0, q=5, this_buffer_empty=0, this_expect=8] [L24] COND TRUE 1 [L27] int P1=__VERIFIER_nondet_int(); [L28] int P2=__VERIFIER_nondet_int(); [L29] int P3=__VERIFIER_nondet_int(); [L30] int P4=__VERIFIER_nondet_int(); [L31] int P5=__VERIFIER_nondet_int(); [L32] int P6=__VERIFIER_nondet_int(); [L33] int P7=__VERIFIER_nondet_int(); [L34] int P8=__VERIFIER_nondet_int(); [L35] int P9=__VERIFIER_nondet_int(); [L38] COND FALSE !(this_expect > 16) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=5, P1=1, P2=0, P3=0, P4=0, P5=0, P6=0, P7=0, P8=0, P9=1, q=5, this_buffer_empty=0, this_expect=8] [L43] COND FALSE !(q == 0) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=5, P1=1, P2=0, P3=0, P4=0, P5=0, P6=0, P7=0, P8=0, P9=1, q=5, this_buffer_empty=0, this_expect=8] [L63] COND FALSE !(q == 1) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=5, P1=1, P2=0, P3=0, P4=0, P5=0, P6=0, P7=0, P8=0, P9=1, q=5, this_buffer_empty=0, this_expect=8] [L163] COND FALSE !(q == 2) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=5, P1=1, P2=0, P3=0, P4=0, P5=0, P6=0, P7=0, P8=0, P9=1, q=5, this_buffer_empty=0, this_expect=8] [L263] COND FALSE !(q == 3) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=5, P1=1, P2=0, P3=0, P4=0, P5=0, P6=0, P7=0, P8=0, P9=1, q=5, this_buffer_empty=0, this_expect=8] [L363] COND FALSE !(q == 4) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=5, P1=1, P2=0, P3=0, P4=0, P5=0, P6=0, P7=0, P8=0, P9=1, q=5, this_buffer_empty=0, this_expect=8] [L463] COND TRUE q == 5 [L464] COND FALSE !(__VERIFIER_nondet_int()) [L480] COND FALSE !(__VERIFIER_nondet_int()) [L496] COND FALSE !(__VERIFIER_nondet_int()) [L512] COND FALSE !(__VERIFIER_nondet_int()) [L528] COND FALSE !(__VERIFIER_nondet_int()) [L544] COND TRUE __VERIFIER_nondet_int() [L546] COND TRUE ((P1 != (((0 + 1) - 1) % 2)) && !((P1 != ((((0 + 1) + 1) - 1) % 2)) && (P1 != (((0 + 1) - 1) % 2)))) [L548] method_id = 7 VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=7, P1=1, P2=0, P3=0, P4=0, P5=0, P6=0, P7=0, P8=0, P9=1, q=5, this_buffer_empty=0, this_expect=8] [L550] COND FALSE !(((((this_buffer_empty == 1) && (P9 != (((0 + 1) - 1) % 2))) && ((P9 != (((0 + 1) - 1) % 2)) && !((P9 != ((((0 + 1) + 1) - 1) % 2)) && (P9 != (((0 + 1) - 1) % 2))))) || ((((P9 != ((this_expect - 1) % 2)) && (this_buffer_empty != 1)) && (P9 != (((0 + 1) - 1) % 2))) && ((P9 != (((0 + 1) - 1) % 2)) && !((P9 != ((((0 + 1) + 1) - 1) % 2)) && (P9 != (((0 + 1) - 1) % 2))))))) [L554] q = 1 [L556] this_expect=this_expect [L556] this_buffer_empty=(1 - this_buffer_empty) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=7, P1=1, P2=0, P3=0, P4=0, P5=0, P6=0, P7=0, P8=0, P9=1, q=1, this_buffer_empty=1, this_expect=8] [L24] COND TRUE 1 [L27] int P1=__VERIFIER_nondet_int(); [L28] int P2=__VERIFIER_nondet_int(); [L29] int P3=__VERIFIER_nondet_int(); [L30] int P4=__VERIFIER_nondet_int(); [L31] int P5=__VERIFIER_nondet_int(); [L32] int P6=__VERIFIER_nondet_int(); [L33] int P7=__VERIFIER_nondet_int(); [L34] int P8=__VERIFIER_nondet_int(); [L35] int P9=__VERIFIER_nondet_int(); [L38] COND FALSE !(this_expect > 16) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=7, P1=-14, P2=0, P3=0, P4=0, P5=0, P6=0, P7=0, P8=0, P9=0, q=1, this_buffer_empty=1, this_expect=8] [L43] COND FALSE !(q == 0) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=7, P1=-14, P2=0, P3=0, P4=0, P5=0, P6=0, P7=0, P8=0, P9=0, q=1, this_buffer_empty=1, this_expect=8] [L63] COND TRUE q == 1 [L64] COND TRUE __VERIFIER_nondet_int() [L66] COND TRUE !((P1 % 2) != (0 % 2)) [L68] method_id = 2 VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=2, P1=-14, P2=0, P3=0, P4=0, P5=0, P6=0, P7=0, P8=0, P9=0, q=1, this_buffer_empty=1, this_expect=8] [L70] COND FALSE !((((((P1 % 2) != (this_expect % 2)) && (this_buffer_empty == 1)) && !((P1 % 2) != (0 % 2))) || ((this_buffer_empty != 1) && !((P1 % 2) != (0 % 2))))) [L74] q = 3 [L76] this_expect=(this_expect + 1) [L76] this_buffer_empty=(1 - this_buffer_empty) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=2, P1=-14, P2=0, P3=0, P4=0, P5=0, P6=0, P7=0, P8=0, P9=0, q=3, this_buffer_empty=0, this_expect=9] [L24] COND TRUE 1 [L27] int P1=__VERIFIER_nondet_int(); [L28] int P2=__VERIFIER_nondet_int(); [L29] int P3=__VERIFIER_nondet_int(); [L30] int P4=__VERIFIER_nondet_int(); [L31] int P5=__VERIFIER_nondet_int(); [L32] int P6=__VERIFIER_nondet_int(); [L33] int P7=__VERIFIER_nondet_int(); [L34] int P8=__VERIFIER_nondet_int(); [L35] int P9=__VERIFIER_nondet_int(); [L38] COND FALSE !(this_expect > 16) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=2, P1=0, P2=0, P3=1, P4=0, P5=0, P6=0, P7=0, P8=0, P9=0, q=3, this_buffer_empty=0, this_expect=9] [L43] COND FALSE !(q == 0) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=2, P1=0, P2=0, P3=1, P4=0, P5=0, P6=0, P7=0, P8=0, P9=0, q=3, this_buffer_empty=0, this_expect=9] [L63] COND FALSE !(q == 1) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=2, P1=0, P2=0, P3=1, P4=0, P5=0, P6=0, P7=0, P8=0, P9=0, q=3, this_buffer_empty=0, this_expect=9] [L163] COND FALSE !(q == 2) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=2, P1=0, P2=0, P3=1, P4=0, P5=0, P6=0, P7=0, P8=0, P9=0, q=3, this_buffer_empty=0, this_expect=9] [L263] COND TRUE q == 3 [L264] COND FALSE !(__VERIFIER_nondet_int()) [L280] COND TRUE __VERIFIER_nondet_int() [L282] COND TRUE !(P1 != (((0 + 1) - 1) % 2)) [L284] method_id = 3 VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=3, P1=0, P2=0, P3=1, P4=0, P5=0, P6=0, P7=0, P8=0, P9=0, q=3, this_buffer_empty=0, this_expect=9] [L286] COND FALSE !((((this_buffer_empty == 1) && !(P3 != (((0 + 1) - 1) % 2))) || (((P3 != ((this_expect - 1) % 2)) && (this_buffer_empty != 1)) && !(P3 != (((0 + 1) - 1) % 2))))) [L290] q = 4 [L292] this_expect=this_expect [L292] this_buffer_empty=(1 - this_buffer_empty) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=3, P1=0, P2=0, P3=1, P4=0, P5=0, P6=0, P7=0, P8=0, P9=0, q=4, this_buffer_empty=1, this_expect=9] [L24] COND TRUE 1 [L27] int P1=__VERIFIER_nondet_int(); [L28] int P2=__VERIFIER_nondet_int(); [L29] int P3=__VERIFIER_nondet_int(); [L30] int P4=__VERIFIER_nondet_int(); [L31] int P5=__VERIFIER_nondet_int(); [L32] int P6=__VERIFIER_nondet_int(); [L33] int P7=__VERIFIER_nondet_int(); [L34] int P8=__VERIFIER_nondet_int(); [L35] int P9=__VERIFIER_nondet_int(); [L38] COND FALSE !(this_expect > 16) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=3, P1=15, P2=0, P3=0, P4=0, P5=0, P6=-1, P7=0, P8=0, P9=0, q=4, this_buffer_empty=1, this_expect=9] [L43] COND FALSE !(q == 0) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=3, P1=15, P2=0, P3=0, P4=0, P5=0, P6=-1, P7=0, P8=0, P9=0, q=4, this_buffer_empty=1, this_expect=9] [L63] COND FALSE !(q == 1) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=3, P1=15, P2=0, P3=0, P4=0, P5=0, P6=-1, P7=0, P8=0, P9=0, q=4, this_buffer_empty=1, this_expect=9] [L163] COND FALSE !(q == 2) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=3, P1=15, P2=0, P3=0, P4=0, P5=0, P6=-1, P7=0, P8=0, P9=0, q=4, this_buffer_empty=1, this_expect=9] [L263] COND FALSE !(q == 3) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=3, P1=15, P2=0, P3=0, P4=0, P5=0, P6=-1, P7=0, P8=0, P9=0, q=4, this_buffer_empty=1, this_expect=9] [L363] COND TRUE q == 4 [L364] COND FALSE !(__VERIFIER_nondet_int()) [L380] COND FALSE !(__VERIFIER_nondet_int()) [L396] COND FALSE !(__VERIFIER_nondet_int()) [L412] COND TRUE __VERIFIER_nondet_int() [L414] COND TRUE (((P1 % 2) != (0 % 2)) && !(((P1 % 2) != ((0 + 1) % 2)) && ((P1 % 2) != (0 % 2)))) [L416] method_id = 5 VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=5, P1=15, P2=0, P3=0, P4=0, P5=0, P6=-1, P7=0, P8=0, P9=0, q=4, this_buffer_empty=1, this_expect=9] [L418] COND FALSE !(((((((P6 % 2) != (this_expect % 2)) && (this_buffer_empty == 1)) && ((P6 % 2) != (0 % 2))) && (((P6 % 2) != (0 % 2)) && !(((P6 % 2) != ((0 + 1) % 2)) && ((P6 % 2) != (0 % 2))))) || (((this_buffer_empty != 1) && ((P6 % 2) != (0 % 2))) && (((P6 % 2) != (0 % 2)) && !(((P6 % 2) != ((0 + 1) % 2)) && ((P6 % 2) != (0 % 2))))))) [L422] q = 5 [L424] this_expect=(this_expect + 1) [L424] this_buffer_empty=(1 - this_buffer_empty) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=5, P1=15, P2=0, P3=0, P4=0, P5=0, P6=-1, P7=0, P8=0, P9=0, q=5, this_buffer_empty=0, this_expect=10] [L24] COND TRUE 1 [L27] int P1=__VERIFIER_nondet_int(); [L28] int P2=__VERIFIER_nondet_int(); [L29] int P3=__VERIFIER_nondet_int(); [L30] int P4=__VERIFIER_nondet_int(); [L31] int P5=__VERIFIER_nondet_int(); [L32] int P6=__VERIFIER_nondet_int(); [L33] int P7=__VERIFIER_nondet_int(); [L34] int P8=__VERIFIER_nondet_int(); [L35] int P9=__VERIFIER_nondet_int(); [L38] COND FALSE !(this_expect > 16) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=5, P1=1, P2=0, P3=0, P4=0, P5=0, P6=0, P7=0, P8=0, P9=0, q=5, this_buffer_empty=0, this_expect=10] [L43] COND FALSE !(q == 0) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=5, P1=1, P2=0, P3=0, P4=0, P5=0, P6=0, P7=0, P8=0, P9=0, q=5, this_buffer_empty=0, this_expect=10] [L63] COND FALSE !(q == 1) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=5, P1=1, P2=0, P3=0, P4=0, P5=0, P6=0, P7=0, P8=0, P9=0, q=5, this_buffer_empty=0, this_expect=10] [L163] COND FALSE !(q == 2) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=5, P1=1, P2=0, P3=0, P4=0, P5=0, P6=0, P7=0, P8=0, P9=0, q=5, this_buffer_empty=0, this_expect=10] [L263] COND FALSE !(q == 3) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=5, P1=1, P2=0, P3=0, P4=0, P5=0, P6=0, P7=0, P8=0, P9=0, q=5, this_buffer_empty=0, this_expect=10] [L363] COND FALSE !(q == 4) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=5, P1=1, P2=0, P3=0, P4=0, P5=0, P6=0, P7=0, P8=0, P9=0, q=5, this_buffer_empty=0, this_expect=10] [L463] COND TRUE q == 5 [L464] COND FALSE !(__VERIFIER_nondet_int()) [L480] COND FALSE !(__VERIFIER_nondet_int()) [L496] COND FALSE !(__VERIFIER_nondet_int()) [L512] COND FALSE !(__VERIFIER_nondet_int()) [L528] COND FALSE !(__VERIFIER_nondet_int()) [L544] COND TRUE __VERIFIER_nondet_int() [L546] COND TRUE ((P1 != (((0 + 1) - 1) % 2)) && !((P1 != ((((0 + 1) + 1) - 1) % 2)) && (P1 != (((0 + 1) - 1) % 2)))) [L548] method_id = 7 VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=7, P1=1, P2=0, P3=0, P4=0, P5=0, P6=0, P7=0, P8=0, P9=0, q=5, this_buffer_empty=0, this_expect=10] [L550] COND FALSE !(((((this_buffer_empty == 1) && (P9 != (((0 + 1) - 1) % 2))) && ((P9 != (((0 + 1) - 1) % 2)) && !((P9 != ((((0 + 1) + 1) - 1) % 2)) && (P9 != (((0 + 1) - 1) % 2))))) || ((((P9 != ((this_expect - 1) % 2)) && (this_buffer_empty != 1)) && (P9 != (((0 + 1) - 1) % 2))) && ((P9 != (((0 + 1) - 1) % 2)) && !((P9 != ((((0 + 1) + 1) - 1) % 2)) && (P9 != (((0 + 1) - 1) % 2))))))) [L554] q = 1 [L556] this_expect=this_expect [L556] this_buffer_empty=(1 - this_buffer_empty) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=7, P1=1, P2=0, P3=0, P4=0, P5=0, P6=0, P7=0, P8=0, P9=0, q=1, this_buffer_empty=1, this_expect=10] [L24] COND TRUE 1 [L27] int P1=__VERIFIER_nondet_int(); [L28] int P2=__VERIFIER_nondet_int(); [L29] int P3=__VERIFIER_nondet_int(); [L30] int P4=__VERIFIER_nondet_int(); [L31] int P5=__VERIFIER_nondet_int(); [L32] int P6=__VERIFIER_nondet_int(); [L33] int P7=__VERIFIER_nondet_int(); [L34] int P8=__VERIFIER_nondet_int(); [L35] int P9=__VERIFIER_nondet_int(); [L38] COND FALSE !(this_expect > 16) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=7, P1=0, P2=0, P3=0, P4=0, P5=0, P6=0, P7=0, P8=0, P9=0, q=1, this_buffer_empty=1, this_expect=10] [L43] COND FALSE !(q == 0) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=7, P1=0, P2=0, P3=0, P4=0, P5=0, P6=0, P7=0, P8=0, P9=0, q=1, this_buffer_empty=1, this_expect=10] [L63] COND TRUE q == 1 [L64] COND TRUE __VERIFIER_nondet_int() [L66] COND TRUE !((P1 % 2) != (0 % 2)) [L68] method_id = 2 VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=2, P1=0, P2=0, P3=0, P4=0, P5=0, P6=0, P7=0, P8=0, P9=0, q=1, this_buffer_empty=1, this_expect=10] [L70] COND FALSE !((((((P1 % 2) != (this_expect % 2)) && (this_buffer_empty == 1)) && !((P1 % 2) != (0 % 2))) || ((this_buffer_empty != 1) && !((P1 % 2) != (0 % 2))))) [L74] q = 3 [L76] this_expect=(this_expect + 1) [L76] this_buffer_empty=(1 - this_buffer_empty) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=2, P1=0, P2=0, P3=0, P4=0, P5=0, P6=0, P7=0, P8=0, P9=0, q=3, this_buffer_empty=0, this_expect=11] [L24] COND TRUE 1 [L27] int P1=__VERIFIER_nondet_int(); [L28] int P2=__VERIFIER_nondet_int(); [L29] int P3=__VERIFIER_nondet_int(); [L30] int P4=__VERIFIER_nondet_int(); [L31] int P5=__VERIFIER_nondet_int(); [L32] int P6=__VERIFIER_nondet_int(); [L33] int P7=__VERIFIER_nondet_int(); [L34] int P8=__VERIFIER_nondet_int(); [L35] int P9=__VERIFIER_nondet_int(); [L38] COND FALSE !(this_expect > 16) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=2, P1=0, P2=0, P3=1, P4=0, P5=0, P6=0, P7=0, P8=0, P9=0, q=3, this_buffer_empty=0, this_expect=11] [L43] COND FALSE !(q == 0) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=2, P1=0, P2=0, P3=1, P4=0, P5=0, P6=0, P7=0, P8=0, P9=0, q=3, this_buffer_empty=0, this_expect=11] [L63] COND FALSE !(q == 1) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=2, P1=0, P2=0, P3=1, P4=0, P5=0, P6=0, P7=0, P8=0, P9=0, q=3, this_buffer_empty=0, this_expect=11] [L163] COND FALSE !(q == 2) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=2, P1=0, P2=0, P3=1, P4=0, P5=0, P6=0, P7=0, P8=0, P9=0, q=3, this_buffer_empty=0, this_expect=11] [L263] COND TRUE q == 3 [L264] COND FALSE !(__VERIFIER_nondet_int()) [L280] COND TRUE __VERIFIER_nondet_int() [L282] COND TRUE !(P1 != (((0 + 1) - 1) % 2)) [L284] method_id = 3 VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=3, P1=0, P2=0, P3=1, P4=0, P5=0, P6=0, P7=0, P8=0, P9=0, q=3, this_buffer_empty=0, this_expect=11] [L286] COND FALSE !((((this_buffer_empty == 1) && !(P3 != (((0 + 1) - 1) % 2))) || (((P3 != ((this_expect - 1) % 2)) && (this_buffer_empty != 1)) && !(P3 != (((0 + 1) - 1) % 2))))) [L290] q = 4 [L292] this_expect=this_expect [L292] this_buffer_empty=(1 - this_buffer_empty) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=3, P1=0, P2=0, P3=1, P4=0, P5=0, P6=0, P7=0, P8=0, P9=0, q=4, this_buffer_empty=1, this_expect=11] [L24] COND TRUE 1 [L27] int P1=__VERIFIER_nondet_int(); [L28] int P2=__VERIFIER_nondet_int(); [L29] int P3=__VERIFIER_nondet_int(); [L30] int P4=__VERIFIER_nondet_int(); [L31] int P5=__VERIFIER_nondet_int(); [L32] int P6=__VERIFIER_nondet_int(); [L33] int P7=__VERIFIER_nondet_int(); [L34] int P8=__VERIFIER_nondet_int(); [L35] int P9=__VERIFIER_nondet_int(); [L38] COND FALSE !(this_expect > 16) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=3, P1=17, P2=0, P3=0, P4=0, P5=0, P6=-1, P7=0, P8=0, P9=0, q=4, this_buffer_empty=1, this_expect=11] [L43] COND FALSE !(q == 0) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=3, P1=17, P2=0, P3=0, P4=0, P5=0, P6=-1, P7=0, P8=0, P9=0, q=4, this_buffer_empty=1, this_expect=11] [L63] COND FALSE !(q == 1) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=3, P1=17, P2=0, P3=0, P4=0, P5=0, P6=-1, P7=0, P8=0, P9=0, q=4, this_buffer_empty=1, this_expect=11] [L163] COND FALSE !(q == 2) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=3, P1=17, P2=0, P3=0, P4=0, P5=0, P6=-1, P7=0, P8=0, P9=0, q=4, this_buffer_empty=1, this_expect=11] [L263] COND FALSE !(q == 3) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=3, P1=17, P2=0, P3=0, P4=0, P5=0, P6=-1, P7=0, P8=0, P9=0, q=4, this_buffer_empty=1, this_expect=11] [L363] COND TRUE q == 4 [L364] COND FALSE !(__VERIFIER_nondet_int()) [L380] COND FALSE !(__VERIFIER_nondet_int()) [L396] COND FALSE !(__VERIFIER_nondet_int()) [L412] COND TRUE __VERIFIER_nondet_int() [L414] COND TRUE (((P1 % 2) != (0 % 2)) && !(((P1 % 2) != ((0 + 1) % 2)) && ((P1 % 2) != (0 % 2)))) [L416] method_id = 5 VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=5, P1=17, P2=0, P3=0, P4=0, P5=0, P6=-1, P7=0, P8=0, P9=0, q=4, this_buffer_empty=1, this_expect=11] [L418] COND FALSE !(((((((P6 % 2) != (this_expect % 2)) && (this_buffer_empty == 1)) && ((P6 % 2) != (0 % 2))) && (((P6 % 2) != (0 % 2)) && !(((P6 % 2) != ((0 + 1) % 2)) && ((P6 % 2) != (0 % 2))))) || (((this_buffer_empty != 1) && ((P6 % 2) != (0 % 2))) && (((P6 % 2) != (0 % 2)) && !(((P6 % 2) != ((0 + 1) % 2)) && ((P6 % 2) != (0 % 2))))))) [L422] q = 5 [L424] this_expect=(this_expect + 1) [L424] this_buffer_empty=(1 - this_buffer_empty) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=5, P1=17, P2=0, P3=0, P4=0, P5=0, P6=-1, P7=0, P8=0, P9=0, q=5, this_buffer_empty=0, this_expect=12] [L24] COND TRUE 1 [L27] int P1=__VERIFIER_nondet_int(); [L28] int P2=__VERIFIER_nondet_int(); [L29] int P3=__VERIFIER_nondet_int(); [L30] int P4=__VERIFIER_nondet_int(); [L31] int P5=__VERIFIER_nondet_int(); [L32] int P6=__VERIFIER_nondet_int(); [L33] int P7=__VERIFIER_nondet_int(); [L34] int P8=__VERIFIER_nondet_int(); [L35] int P9=__VERIFIER_nondet_int(); [L38] COND FALSE !(this_expect > 16) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=5, P1=1, P2=0, P3=0, P4=0, P5=0, P6=0, P7=0, P8=0, P9=2, q=5, this_buffer_empty=0, this_expect=12] [L43] COND FALSE !(q == 0) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=5, P1=1, P2=0, P3=0, P4=0, P5=0, P6=0, P7=0, P8=0, P9=2, q=5, this_buffer_empty=0, this_expect=12] [L63] COND FALSE !(q == 1) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=5, P1=1, P2=0, P3=0, P4=0, P5=0, P6=0, P7=0, P8=0, P9=2, q=5, this_buffer_empty=0, this_expect=12] [L163] COND FALSE !(q == 2) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=5, P1=1, P2=0, P3=0, P4=0, P5=0, P6=0, P7=0, P8=0, P9=2, q=5, this_buffer_empty=0, this_expect=12] [L263] COND FALSE !(q == 3) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=5, P1=1, P2=0, P3=0, P4=0, P5=0, P6=0, P7=0, P8=0, P9=2, q=5, this_buffer_empty=0, this_expect=12] [L363] COND FALSE !(q == 4) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=5, P1=1, P2=0, P3=0, P4=0, P5=0, P6=0, P7=0, P8=0, P9=2, q=5, this_buffer_empty=0, this_expect=12] [L463] COND TRUE q == 5 [L464] COND FALSE !(__VERIFIER_nondet_int()) [L480] COND FALSE !(__VERIFIER_nondet_int()) [L496] COND FALSE !(__VERIFIER_nondet_int()) [L512] COND FALSE !(__VERIFIER_nondet_int()) [L528] COND FALSE !(__VERIFIER_nondet_int()) [L544] COND TRUE __VERIFIER_nondet_int() [L546] COND TRUE ((P1 != (((0 + 1) - 1) % 2)) && !((P1 != ((((0 + 1) + 1) - 1) % 2)) && (P1 != (((0 + 1) - 1) % 2)))) [L548] method_id = 7 VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=7, P1=1, P2=0, P3=0, P4=0, P5=0, P6=0, P7=0, P8=0, P9=2, q=5, this_buffer_empty=0, this_expect=12] [L550] COND FALSE !(((((this_buffer_empty == 1) && (P9 != (((0 + 1) - 1) % 2))) && ((P9 != (((0 + 1) - 1) % 2)) && !((P9 != ((((0 + 1) + 1) - 1) % 2)) && (P9 != (((0 + 1) - 1) % 2))))) || ((((P9 != ((this_expect - 1) % 2)) && (this_buffer_empty != 1)) && (P9 != (((0 + 1) - 1) % 2))) && ((P9 != (((0 + 1) - 1) % 2)) && !((P9 != ((((0 + 1) + 1) - 1) % 2)) && (P9 != (((0 + 1) - 1) % 2))))))) [L554] q = 1 [L556] this_expect=this_expect [L556] this_buffer_empty=(1 - this_buffer_empty) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=7, P1=1, P2=0, P3=0, P4=0, P5=0, P6=0, P7=0, P8=0, P9=2, q=1, this_buffer_empty=1, this_expect=12] [L24] COND TRUE 1 [L27] int P1=__VERIFIER_nondet_int(); [L28] int P2=__VERIFIER_nondet_int(); [L29] int P3=__VERIFIER_nondet_int(); [L30] int P4=__VERIFIER_nondet_int(); [L31] int P5=__VERIFIER_nondet_int(); [L32] int P6=__VERIFIER_nondet_int(); [L33] int P7=__VERIFIER_nondet_int(); [L34] int P8=__VERIFIER_nondet_int(); [L35] int P9=__VERIFIER_nondet_int(); [L38] COND FALSE !(this_expect > 16) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=7, P1=-6, P2=0, P3=0, P4=0, P5=0, P6=0, P7=0, P8=0, P9=0, q=1, this_buffer_empty=1, this_expect=12] [L43] COND FALSE !(q == 0) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=7, P1=-6, P2=0, P3=0, P4=0, P5=0, P6=0, P7=0, P8=0, P9=0, q=1, this_buffer_empty=1, this_expect=12] [L63] COND TRUE q == 1 [L64] COND TRUE __VERIFIER_nondet_int() [L66] COND TRUE !((P1 % 2) != (0 % 2)) [L68] method_id = 2 VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=2, P1=-6, P2=0, P3=0, P4=0, P5=0, P6=0, P7=0, P8=0, P9=0, q=1, this_buffer_empty=1, this_expect=12] [L70] COND FALSE !((((((P1 % 2) != (this_expect % 2)) && (this_buffer_empty == 1)) && !((P1 % 2) != (0 % 2))) || ((this_buffer_empty != 1) && !((P1 % 2) != (0 % 2))))) [L74] q = 3 [L76] this_expect=(this_expect + 1) [L76] this_buffer_empty=(1 - this_buffer_empty) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=2, P1=-6, P2=0, P3=0, P4=0, P5=0, P6=0, P7=0, P8=0, P9=0, q=3, this_buffer_empty=0, this_expect=13] [L24] COND TRUE 1 [L27] int P1=__VERIFIER_nondet_int(); [L28] int P2=__VERIFIER_nondet_int(); [L29] int P3=__VERIFIER_nondet_int(); [L30] int P4=__VERIFIER_nondet_int(); [L31] int P5=__VERIFIER_nondet_int(); [L32] int P6=__VERIFIER_nondet_int(); [L33] int P7=__VERIFIER_nondet_int(); [L34] int P8=__VERIFIER_nondet_int(); [L35] int P9=__VERIFIER_nondet_int(); [L38] COND FALSE !(this_expect > 16) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=2, P1=0, P2=0, P3=1, P4=0, P5=0, P6=0, P7=0, P8=0, P9=0, q=3, this_buffer_empty=0, this_expect=13] [L43] COND FALSE !(q == 0) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=2, P1=0, P2=0, P3=1, P4=0, P5=0, P6=0, P7=0, P8=0, P9=0, q=3, this_buffer_empty=0, this_expect=13] [L63] COND FALSE !(q == 1) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=2, P1=0, P2=0, P3=1, P4=0, P5=0, P6=0, P7=0, P8=0, P9=0, q=3, this_buffer_empty=0, this_expect=13] [L163] COND FALSE !(q == 2) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=2, P1=0, P2=0, P3=1, P4=0, P5=0, P6=0, P7=0, P8=0, P9=0, q=3, this_buffer_empty=0, this_expect=13] [L263] COND TRUE q == 3 [L264] COND FALSE !(__VERIFIER_nondet_int()) [L280] COND TRUE __VERIFIER_nondet_int() [L282] COND TRUE !(P1 != (((0 + 1) - 1) % 2)) [L284] method_id = 3 VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=3, P1=0, P2=0, P3=1, P4=0, P5=0, P6=0, P7=0, P8=0, P9=0, q=3, this_buffer_empty=0, this_expect=13] [L286] COND FALSE !((((this_buffer_empty == 1) && !(P3 != (((0 + 1) - 1) % 2))) || (((P3 != ((this_expect - 1) % 2)) && (this_buffer_empty != 1)) && !(P3 != (((0 + 1) - 1) % 2))))) [L290] q = 4 [L292] this_expect=this_expect [L292] this_buffer_empty=(1 - this_buffer_empty) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=3, P1=0, P2=0, P3=1, P4=0, P5=0, P6=0, P7=0, P8=0, P9=0, q=4, this_buffer_empty=1, this_expect=13] [L24] COND TRUE 1 [L27] int P1=__VERIFIER_nondet_int(); [L28] int P2=__VERIFIER_nondet_int(); [L29] int P3=__VERIFIER_nondet_int(); [L30] int P4=__VERIFIER_nondet_int(); [L31] int P5=__VERIFIER_nondet_int(); [L32] int P6=__VERIFIER_nondet_int(); [L33] int P7=__VERIFIER_nondet_int(); [L34] int P8=__VERIFIER_nondet_int(); [L35] int P9=__VERIFIER_nondet_int(); [L38] COND FALSE !(this_expect > 16) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=3, P1=7, P2=0, P3=0, P4=0, P5=0, P6=-1, P7=0, P8=0, P9=0, q=4, this_buffer_empty=1, this_expect=13] [L43] COND FALSE !(q == 0) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=3, P1=7, P2=0, P3=0, P4=0, P5=0, P6=-1, P7=0, P8=0, P9=0, q=4, this_buffer_empty=1, this_expect=13] [L63] COND FALSE !(q == 1) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=3, P1=7, P2=0, P3=0, P4=0, P5=0, P6=-1, P7=0, P8=0, P9=0, q=4, this_buffer_empty=1, this_expect=13] [L163] COND FALSE !(q == 2) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=3, P1=7, P2=0, P3=0, P4=0, P5=0, P6=-1, P7=0, P8=0, P9=0, q=4, this_buffer_empty=1, this_expect=13] [L263] COND FALSE !(q == 3) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=3, P1=7, P2=0, P3=0, P4=0, P5=0, P6=-1, P7=0, P8=0, P9=0, q=4, this_buffer_empty=1, this_expect=13] [L363] COND TRUE q == 4 [L364] COND FALSE !(__VERIFIER_nondet_int()) [L380] COND FALSE !(__VERIFIER_nondet_int()) [L396] COND FALSE !(__VERIFIER_nondet_int()) [L412] COND TRUE __VERIFIER_nondet_int() [L414] COND TRUE (((P1 % 2) != (0 % 2)) && !(((P1 % 2) != ((0 + 1) % 2)) && ((P1 % 2) != (0 % 2)))) [L416] method_id = 5 VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=5, P1=7, P2=0, P3=0, P4=0, P5=0, P6=-1, P7=0, P8=0, P9=0, q=4, this_buffer_empty=1, this_expect=13] [L418] COND FALSE !(((((((P6 % 2) != (this_expect % 2)) && (this_buffer_empty == 1)) && ((P6 % 2) != (0 % 2))) && (((P6 % 2) != (0 % 2)) && !(((P6 % 2) != ((0 + 1) % 2)) && ((P6 % 2) != (0 % 2))))) || (((this_buffer_empty != 1) && ((P6 % 2) != (0 % 2))) && (((P6 % 2) != (0 % 2)) && !(((P6 % 2) != ((0 + 1) % 2)) && ((P6 % 2) != (0 % 2))))))) [L422] q = 5 [L424] this_expect=(this_expect + 1) [L424] this_buffer_empty=(1 - this_buffer_empty) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=5, P1=7, P2=0, P3=0, P4=0, P5=0, P6=-1, P7=0, P8=0, P9=0, q=5, this_buffer_empty=0, this_expect=14] [L24] COND TRUE 1 [L27] int P1=__VERIFIER_nondet_int(); [L28] int P2=__VERIFIER_nondet_int(); [L29] int P3=__VERIFIER_nondet_int(); [L30] int P4=__VERIFIER_nondet_int(); [L31] int P5=__VERIFIER_nondet_int(); [L32] int P6=__VERIFIER_nondet_int(); [L33] int P7=__VERIFIER_nondet_int(); [L34] int P8=__VERIFIER_nondet_int(); [L35] int P9=__VERIFIER_nondet_int(); [L38] COND FALSE !(this_expect > 16) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=5, P1=1, P2=0, P3=0, P4=0, P5=0, P6=0, P7=0, P8=0, P9=1, q=5, this_buffer_empty=0, this_expect=14] [L43] COND FALSE !(q == 0) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=5, P1=1, P2=0, P3=0, P4=0, P5=0, P6=0, P7=0, P8=0, P9=1, q=5, this_buffer_empty=0, this_expect=14] [L63] COND FALSE !(q == 1) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=5, P1=1, P2=0, P3=0, P4=0, P5=0, P6=0, P7=0, P8=0, P9=1, q=5, this_buffer_empty=0, this_expect=14] [L163] COND FALSE !(q == 2) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=5, P1=1, P2=0, P3=0, P4=0, P5=0, P6=0, P7=0, P8=0, P9=1, q=5, this_buffer_empty=0, this_expect=14] [L263] COND FALSE !(q == 3) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=5, P1=1, P2=0, P3=0, P4=0, P5=0, P6=0, P7=0, P8=0, P9=1, q=5, this_buffer_empty=0, this_expect=14] [L363] COND FALSE !(q == 4) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=5, P1=1, P2=0, P3=0, P4=0, P5=0, P6=0, P7=0, P8=0, P9=1, q=5, this_buffer_empty=0, this_expect=14] [L463] COND TRUE q == 5 [L464] COND FALSE !(__VERIFIER_nondet_int()) [L480] COND FALSE !(__VERIFIER_nondet_int()) [L496] COND FALSE !(__VERIFIER_nondet_int()) [L512] COND FALSE !(__VERIFIER_nondet_int()) [L528] COND FALSE !(__VERIFIER_nondet_int()) [L544] COND TRUE __VERIFIER_nondet_int() [L546] COND TRUE ((P1 != (((0 + 1) - 1) % 2)) && !((P1 != ((((0 + 1) + 1) - 1) % 2)) && (P1 != (((0 + 1) - 1) % 2)))) [L548] method_id = 7 VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=7, P1=1, P2=0, P3=0, P4=0, P5=0, P6=0, P7=0, P8=0, P9=1, q=5, this_buffer_empty=0, this_expect=14] [L550] COND FALSE !(((((this_buffer_empty == 1) && (P9 != (((0 + 1) - 1) % 2))) && ((P9 != (((0 + 1) - 1) % 2)) && !((P9 != ((((0 + 1) + 1) - 1) % 2)) && (P9 != (((0 + 1) - 1) % 2))))) || ((((P9 != ((this_expect - 1) % 2)) && (this_buffer_empty != 1)) && (P9 != (((0 + 1) - 1) % 2))) && ((P9 != (((0 + 1) - 1) % 2)) && !((P9 != ((((0 + 1) + 1) - 1) % 2)) && (P9 != (((0 + 1) - 1) % 2))))))) [L554] q = 1 [L556] this_expect=this_expect [L556] this_buffer_empty=(1 - this_buffer_empty) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=7, P1=1, P2=0, P3=0, P4=0, P5=0, P6=0, P7=0, P8=0, P9=1, q=1, this_buffer_empty=1, this_expect=14] [L24] COND TRUE 1 [L27] int P1=__VERIFIER_nondet_int(); [L28] int P2=__VERIFIER_nondet_int(); [L29] int P3=__VERIFIER_nondet_int(); [L30] int P4=__VERIFIER_nondet_int(); [L31] int P5=__VERIFIER_nondet_int(); [L32] int P6=__VERIFIER_nondet_int(); [L33] int P7=__VERIFIER_nondet_int(); [L34] int P8=__VERIFIER_nondet_int(); [L35] int P9=__VERIFIER_nondet_int(); [L38] COND FALSE !(this_expect > 16) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=7, P1=-12, P2=0, P3=0, P4=0, P5=0, P6=0, P7=0, P8=0, P9=0, q=1, this_buffer_empty=1, this_expect=14] [L43] COND FALSE !(q == 0) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=7, P1=-12, P2=0, P3=0, P4=0, P5=0, P6=0, P7=0, P8=0, P9=0, q=1, this_buffer_empty=1, this_expect=14] [L63] COND TRUE q == 1 [L64] COND TRUE __VERIFIER_nondet_int() [L66] COND TRUE !((P1 % 2) != (0 % 2)) [L68] method_id = 2 VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=2, P1=-12, P2=0, P3=0, P4=0, P5=0, P6=0, P7=0, P8=0, P9=0, q=1, this_buffer_empty=1, this_expect=14] [L70] COND FALSE !((((((P1 % 2) != (this_expect % 2)) && (this_buffer_empty == 1)) && !((P1 % 2) != (0 % 2))) || ((this_buffer_empty != 1) && !((P1 % 2) != (0 % 2))))) [L74] q = 3 [L76] this_expect=(this_expect + 1) [L76] this_buffer_empty=(1 - this_buffer_empty) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=2, P1=-12, P2=0, P3=0, P4=0, P5=0, P6=0, P7=0, P8=0, P9=0, q=3, this_buffer_empty=0, this_expect=15] [L24] COND TRUE 1 [L27] int P1=__VERIFIER_nondet_int(); [L28] int P2=__VERIFIER_nondet_int(); [L29] int P3=__VERIFIER_nondet_int(); [L30] int P4=__VERIFIER_nondet_int(); [L31] int P5=__VERIFIER_nondet_int(); [L32] int P6=__VERIFIER_nondet_int(); [L33] int P7=__VERIFIER_nondet_int(); [L34] int P8=__VERIFIER_nondet_int(); [L35] int P9=__VERIFIER_nondet_int(); [L38] COND FALSE !(this_expect > 16) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=2, P1=0, P2=0, P3=0, P4=0, P5=0, P6=0, P7=0, P8=0, P9=0, q=3, this_buffer_empty=0, this_expect=15] [L43] COND FALSE !(q == 0) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=2, P1=0, P2=0, P3=0, P4=0, P5=0, P6=0, P7=0, P8=0, P9=0, q=3, this_buffer_empty=0, this_expect=15] [L63] COND FALSE !(q == 1) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=2, P1=0, P2=0, P3=0, P4=0, P5=0, P6=0, P7=0, P8=0, P9=0, q=3, this_buffer_empty=0, this_expect=15] [L163] COND FALSE !(q == 2) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=2, P1=0, P2=0, P3=0, P4=0, P5=0, P6=0, P7=0, P8=0, P9=0, q=3, this_buffer_empty=0, this_expect=15] [L263] COND TRUE q == 3 [L264] COND FALSE !(__VERIFIER_nondet_int()) [L280] COND TRUE __VERIFIER_nondet_int() [L282] COND TRUE !(P1 != (((0 + 1) - 1) % 2)) [L284] method_id = 3 VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=3, P1=0, P2=0, P3=0, P4=0, P5=0, P6=0, P7=0, P8=0, P9=0, q=3, this_buffer_empty=0, this_expect=15] [L286] COND FALSE !((((this_buffer_empty == 1) && !(P3 != (((0 + 1) - 1) % 2))) || (((P3 != ((this_expect - 1) % 2)) && (this_buffer_empty != 1)) && !(P3 != (((0 + 1) - 1) % 2))))) [L290] q = 4 [L292] this_expect=this_expect [L292] this_buffer_empty=(1 - this_buffer_empty) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=3, P1=0, P2=0, P3=0, P4=0, P5=0, P6=0, P7=0, P8=0, P9=0, q=4, this_buffer_empty=1, this_expect=15] [L24] COND TRUE 1 [L27] int P1=__VERIFIER_nondet_int(); [L28] int P2=__VERIFIER_nondet_int(); [L29] int P3=__VERIFIER_nondet_int(); [L30] int P4=__VERIFIER_nondet_int(); [L31] int P5=__VERIFIER_nondet_int(); [L32] int P6=__VERIFIER_nondet_int(); [L33] int P7=__VERIFIER_nondet_int(); [L34] int P8=__VERIFIER_nondet_int(); [L35] int P9=__VERIFIER_nondet_int(); [L38] COND FALSE !(this_expect > 16) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=3, P1=9, P2=0, P3=0, P4=0, P5=0, P6=1, P7=0, P8=0, P9=0, q=4, this_buffer_empty=1, this_expect=15] [L43] COND FALSE !(q == 0) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=3, P1=9, P2=0, P3=0, P4=0, P5=0, P6=1, P7=0, P8=0, P9=0, q=4, this_buffer_empty=1, this_expect=15] [L63] COND FALSE !(q == 1) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=3, P1=9, P2=0, P3=0, P4=0, P5=0, P6=1, P7=0, P8=0, P9=0, q=4, this_buffer_empty=1, this_expect=15] [L163] COND FALSE !(q == 2) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=3, P1=9, P2=0, P3=0, P4=0, P5=0, P6=1, P7=0, P8=0, P9=0, q=4, this_buffer_empty=1, this_expect=15] [L263] COND FALSE !(q == 3) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=3, P1=9, P2=0, P3=0, P4=0, P5=0, P6=1, P7=0, P8=0, P9=0, q=4, this_buffer_empty=1, this_expect=15] [L363] COND TRUE q == 4 [L364] COND FALSE !(__VERIFIER_nondet_int()) [L380] COND FALSE !(__VERIFIER_nondet_int()) [L396] COND FALSE !(__VERIFIER_nondet_int()) [L412] COND TRUE __VERIFIER_nondet_int() [L414] COND TRUE (((P1 % 2) != (0 % 2)) && !(((P1 % 2) != ((0 + 1) % 2)) && ((P1 % 2) != (0 % 2)))) [L416] method_id = 5 VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=5, P1=9, P2=0, P3=0, P4=0, P5=0, P6=1, P7=0, P8=0, P9=0, q=4, this_buffer_empty=1, this_expect=15] [L418] COND FALSE !(((((((P6 % 2) != (this_expect % 2)) && (this_buffer_empty == 1)) && ((P6 % 2) != (0 % 2))) && (((P6 % 2) != (0 % 2)) && !(((P6 % 2) != ((0 + 1) % 2)) && ((P6 % 2) != (0 % 2))))) || (((this_buffer_empty != 1) && ((P6 % 2) != (0 % 2))) && (((P6 % 2) != (0 % 2)) && !(((P6 % 2) != ((0 + 1) % 2)) && ((P6 % 2) != (0 % 2))))))) [L422] q = 5 [L424] this_expect=(this_expect + 1) [L424] this_buffer_empty=(1 - this_buffer_empty) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=5, P1=9, P2=0, P3=0, P4=0, P5=0, P6=1, P7=0, P8=0, P9=0, q=5, this_buffer_empty=0, this_expect=16] [L24] COND TRUE 1 [L27] int P1=__VERIFIER_nondet_int(); [L28] int P2=__VERIFIER_nondet_int(); [L29] int P3=__VERIFIER_nondet_int(); [L30] int P4=__VERIFIER_nondet_int(); [L31] int P5=__VERIFIER_nondet_int(); [L32] int P6=__VERIFIER_nondet_int(); [L33] int P7=__VERIFIER_nondet_int(); [L34] int P8=__VERIFIER_nondet_int(); [L35] int P9=__VERIFIER_nondet_int(); [L38] COND FALSE !(this_expect > 16) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=5, P1=1, P2=0, P3=0, P4=0, P5=0, P6=0, P7=0, P8=0, P9=0, q=5, this_buffer_empty=0, this_expect=16] [L43] COND FALSE !(q == 0) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=5, P1=1, P2=0, P3=0, P4=0, P5=0, P6=0, P7=0, P8=0, P9=0, q=5, this_buffer_empty=0, this_expect=16] [L63] COND FALSE !(q == 1) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=5, P1=1, P2=0, P3=0, P4=0, P5=0, P6=0, P7=0, P8=0, P9=0, q=5, this_buffer_empty=0, this_expect=16] [L163] COND FALSE !(q == 2) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=5, P1=1, P2=0, P3=0, P4=0, P5=0, P6=0, P7=0, P8=0, P9=0, q=5, this_buffer_empty=0, this_expect=16] [L263] COND FALSE !(q == 3) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=5, P1=1, P2=0, P3=0, P4=0, P5=0, P6=0, P7=0, P8=0, P9=0, q=5, this_buffer_empty=0, this_expect=16] [L363] COND FALSE !(q == 4) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=5, P1=1, P2=0, P3=0, P4=0, P5=0, P6=0, P7=0, P8=0, P9=0, q=5, this_buffer_empty=0, this_expect=16] [L463] COND TRUE q == 5 [L464] COND FALSE !(__VERIFIER_nondet_int()) [L480] COND FALSE !(__VERIFIER_nondet_int()) [L496] COND FALSE !(__VERIFIER_nondet_int()) [L512] COND FALSE !(__VERIFIER_nondet_int()) [L528] COND FALSE !(__VERIFIER_nondet_int()) [L544] COND TRUE __VERIFIER_nondet_int() [L546] COND TRUE ((P1 != (((0 + 1) - 1) % 2)) && !((P1 != ((((0 + 1) + 1) - 1) % 2)) && (P1 != (((0 + 1) - 1) % 2)))) [L548] method_id = 7 VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=7, P1=1, P2=0, P3=0, P4=0, P5=0, P6=0, P7=0, P8=0, P9=0, q=5, this_buffer_empty=0, this_expect=16] [L550] COND FALSE !(((((this_buffer_empty == 1) && (P9 != (((0 + 1) - 1) % 2))) && ((P9 != (((0 + 1) - 1) % 2)) && !((P9 != ((((0 + 1) + 1) - 1) % 2)) && (P9 != (((0 + 1) - 1) % 2))))) || ((((P9 != ((this_expect - 1) % 2)) && (this_buffer_empty != 1)) && (P9 != (((0 + 1) - 1) % 2))) && ((P9 != (((0 + 1) - 1) % 2)) && !((P9 != ((((0 + 1) + 1) - 1) % 2)) && (P9 != (((0 + 1) - 1) % 2))))))) [L554] q = 1 [L556] this_expect=this_expect [L556] this_buffer_empty=(1 - this_buffer_empty) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=7, P1=1, P2=0, P3=0, P4=0, P5=0, P6=0, P7=0, P8=0, P9=0, q=1, this_buffer_empty=1, this_expect=16] [L24] COND TRUE 1 [L27] int P1=__VERIFIER_nondet_int(); [L28] int P2=__VERIFIER_nondet_int(); [L29] int P3=__VERIFIER_nondet_int(); [L30] int P4=__VERIFIER_nondet_int(); [L31] int P5=__VERIFIER_nondet_int(); [L32] int P6=__VERIFIER_nondet_int(); [L33] int P7=__VERIFIER_nondet_int(); [L34] int P8=__VERIFIER_nondet_int(); [L35] int P9=__VERIFIER_nondet_int(); [L38] COND FALSE !(this_expect > 16) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=7, P1=-8, P2=0, P3=0, P4=0, P5=0, P6=0, P7=0, P8=0, P9=0, q=1, this_buffer_empty=1, this_expect=16] [L43] COND FALSE !(q == 0) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=7, P1=-8, P2=0, P3=0, P4=0, P5=0, P6=0, P7=0, P8=0, P9=0, q=1, this_buffer_empty=1, this_expect=16] [L63] COND TRUE q == 1 [L64] COND TRUE __VERIFIER_nondet_int() [L66] COND TRUE !((P1 % 2) != (0 % 2)) [L68] method_id = 2 VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=2, P1=-8, P2=0, P3=0, P4=0, P5=0, P6=0, P7=0, P8=0, P9=0, q=1, this_buffer_empty=1, this_expect=16] [L70] COND FALSE !((((((P1 % 2) != (this_expect % 2)) && (this_buffer_empty == 1)) && !((P1 % 2) != (0 % 2))) || ((this_buffer_empty != 1) && !((P1 % 2) != (0 % 2))))) [L74] q = 3 [L76] this_expect=(this_expect + 1) [L76] this_buffer_empty=(1 - this_buffer_empty) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=2, P1=-8, P2=0, P3=0, P4=0, P5=0, P6=0, P7=0, P8=0, P9=0, q=3, this_buffer_empty=0, this_expect=17] [L24] COND TRUE 1 [L27] int P1=__VERIFIER_nondet_int(); [L28] int P2=__VERIFIER_nondet_int(); [L29] int P3=__VERIFIER_nondet_int(); [L30] int P4=__VERIFIER_nondet_int(); [L31] int P5=__VERIFIER_nondet_int(); [L32] int P6=__VERIFIER_nondet_int(); [L33] int P7=__VERIFIER_nondet_int(); [L34] int P8=__VERIFIER_nondet_int(); [L35] int P9=__VERIFIER_nondet_int(); [L38] COND TRUE this_expect > 16 [L39] this_expect = -16 VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=2, P1=0, P2=0, P3=0, P4=0, P5=0, P6=0, P7=0, P8=0, P9=0, q=3, this_buffer_empty=0, this_expect=-16] [L43] COND FALSE !(q == 0) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=2, P1=0, P2=0, P3=0, P4=0, P5=0, P6=0, P7=0, P8=0, P9=0, q=3, this_buffer_empty=0, this_expect=-16] [L63] COND FALSE !(q == 1) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=2, P1=0, P2=0, P3=0, P4=0, P5=0, P6=0, P7=0, P8=0, P9=0, q=3, this_buffer_empty=0, this_expect=-16] [L163] COND FALSE !(q == 2) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=2, P1=0, P2=0, P3=0, P4=0, P5=0, P6=0, P7=0, P8=0, P9=0, q=3, this_buffer_empty=0, this_expect=-16] [L263] COND TRUE q == 3 [L264] COND FALSE !(__VERIFIER_nondet_int()) [L280] COND TRUE __VERIFIER_nondet_int() [L282] COND TRUE !(P1 != (((0 + 1) - 1) % 2)) [L284] method_id = 3 VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=3, P1=0, P2=0, P3=0, P4=0, P5=0, P6=0, P7=0, P8=0, P9=0, q=3, this_buffer_empty=0, this_expect=-16] [L286] COND TRUE (((this_buffer_empty == 1) && !(P3 != (((0 + 1) - 1) % 2))) || (((P3 != ((this_expect - 1) % 2)) && (this_buffer_empty != 1)) && !(P3 != (((0 + 1) - 1) % 2)))) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=3, P1=0, P2=0, P3=0, P4=0, P5=0, P6=0, P7=0, P8=0, P9=0, q=3, this_buffer_empty=0, this_expect=-16] [L569] __VERIFIER_error() VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=3, P1=0, P2=0, P3=0, P4=0, P5=0, P6=0, P7=0, P8=0, P9=0, q=3, this_buffer_empty=0, this_expect=-16] - StatisticsResult: Ultimate Automizer benchmark data CFG has 3 procedures, 115 locations, 1 error locations. UNSAFE Result, 24.2s OverallTime, 45 OverallIterations, 35 TraceHistogramMax, 9.3s AutomataDifference, 0.0s DeadEndRemovalTime, 0.0s HoareAnnotationTime, HoareTripleCheckerStatistics: 9604 SDtfs, 18695 SDslu, 52007 SDs, 0 SdLazy, 9336 SolverSat, 1351 SolverUnsat, 0 SolverUnknown, 0 SolverNotchecked, 5.0s Time, PredicateUnifierStatistics: 0 DeclaredPredicates, 5286 GetRequests, 4706 SyntacticMatches, 40 SemanticMatches, 540 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2254 ImplicationChecksByTransitivity, 7.1s Time, 0.0s BasicInterpolantAutomatonTime, BiggestAbstraction: size=1167occurred in iteration=42, traceCheckStatistics: No data available, InterpolantConsolidationStatistics: No data available, PathInvariantsStatistics: No data available, 0/0 InterpolantCoveringCapability, TotalInterpolationStatistics: No data available, 0.0s AbstIntTime, 0 AbstIntIterations, 0 AbstIntStrong, NaN AbsIntWeakeningRatio, NaN AbsIntAvgWeakeningVarsNumRemoved, NaN AbsIntAvgWeakenedConjuncts, 0.0s DumpTime, AutomataMinimizationStatistics: 0.7s AutomataMinimizationTime, 44 MinimizatonAttempts, 1077 StatesRemovedByMinimization, 42 NontrivialMinimizations, HoareAnnotationStatistics: No data available, RefinementEngineStatistics: TraceCheckStatistics: 0.5s SsaConstructionTime, 3.2s SatisfiabilityAnalysisTime, 7.6s InterpolantComputationTime, 9881 NumberOfCodeBlocks, 9431 NumberOfCodeBlocksAsserted, 167 NumberOfCheckSat, 9402 ConstructedInterpolants, 94 QuantifiedInterpolants, 7117042 SizeOfPredicates, 75 NumberOfNonLiveVariables, 25255 ConjunctsInSsa, 652 ConjunctsInUnsatCore, 80 InterpolantComputations, 11 PerfectInterpolantSequences, 9546/33980 InterpolantCoveringCapability, InvariantSynthesisStatistics: No data available, InterpolantConsolidationStatistics: No data available, ReuseStatistics: No data available RESULT: Ultimate proved your program to be incorrect! Received shutdown request...